diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/Commando.qpf b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/Commando.qpf new file mode 100644 index 00000000..e7c6f85a --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/Commando.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition +# Date created = 04:04:47 October 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.0" +DATE = "04:04:47 October 16, 2017" + +# Revisions + +PROJECT_REVISION = "Commando" diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/Commando.qsf b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/Commando.qsf new file mode 100644 index 00000000..239885bd --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/Commando.qsf @@ -0,0 +1,174 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2014 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition +# Date created = 15:32:46 October 03, 2019 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Commando_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name SYSTEMVERILOG_FILE rtl/Commando_mist.sv +set_global_assignment -name VERILOG_FILE rtl/cmd_top.v +set_global_assignment -name VERILOG_FILE rtl/cmd_video.v +set_global_assignment -name VERILOG_FILE rtl/cmd_hvgen.v +set_global_assignment -name VERILOG_FILE rtl/cmd_sprite.v +set_global_assignment -name VHDL_FILE rtl/cmd_sound.vhd +set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd +set_global_assignment -name VERILOG_FILE rtl/rams.v +set_global_assignment -name VHDL_FILE rtl/dpram.vhd +set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd +set_global_assignment -name VHDL_FILE rtl/roms/cmd_prg_rom.vhd +set_global_assignment -name VHDL_FILE rtl/roms/cmd_dot_rom.vhd +set_global_assignment -name VHDL_FILE rtl/roms/cmd_chr_rom.vhd +set_global_assignment -name VHDL_FILE rtl/roms/cmd_pal_rom.vhd +set_global_assignment -name VHDL_FILE rtl/roms/cmd_col_rom.vhd +set_global_assignment -name VHDL_FILE rtl/roms/cmd_snd_rom.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80s.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd +set_global_assignment -name VHDL_FILE rtl/T65/T65_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/T65/T65_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/T65/T65_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/T65/T65.vhd +set_global_assignment -name VERILOG_FILE rtl/pll.v +set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP +set_global_assignment -name TOP_LEVEL_ENTITY Commando_mist + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# --------------------------- +# start ENTITY(Commando_mist) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(Commando_mist) +# ------------------------- +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/README.txt b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/README.txt new file mode 100644 index 00000000..a6f37ade --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/README.txt @@ -0,0 +1,18 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Commando (Sega) port to MiST +-- xx xxxx 20xx +-- From: https://github.com/MrX-8B/MiSTer-Arcade-RallyX +-- + +Todo: Sound ,GFX and some Controls + +--------------------------------------------------------------------------------- +-- FPGA New Rally-X for Spartan-3 Starter Board +------------------------------------------------ +-- Copyright (c) 2005 MiSTer-X +--------------------------------------------------------------------------------- +-- T80/T80s - Version : 0242 +----------------------------- +-- Z80 compatible microprocessor core +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) \ No newline at end of file diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/Snapshot/Commando.rbf b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/Snapshot/Commando.rbf new file mode 100644 index 00000000..ed87fcbc Binary files /dev/null and b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/Snapshot/Commando.rbf differ diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/clean.bat b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/Commando_mist.sv b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/Commando_mist.sv new file mode 100644 index 00000000..58a940e3 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/Commando_mist.sv @@ -0,0 +1,171 @@ +module Commando_mist ( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "Commando;;", +// "O2,Rotate,Off,On;", + "O34,Scanlines,None,CRT 25%,CRT 50%,CRT 75%;", +// "O5,Test,Off,On;", +// "O6,Service,Off,On;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + +assign LED = 1; +assign AUDIO_R = AUDIO_L; + +wire clock_24, clock_12; +pll pll( + .inclk0(CLOCK_27), + .c0(clock_24)//24.576MHz + ); + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoublerD; +wire ypbpr; +wire [10:0] audio; +wire hs, vs; +wire hb, vb; +wire blankn = ~(hb | vb); +wire [2:0] r, g; +wire [1:0] b; +wire key_strobe; +wire key_pressed; +wire [7:0] key_code; + + +wire [7:0] iDSW1 = ~{ m_down1,"0000000"}; +wire [7:0] iDSW2 = ~{ status[5], 1'b1, "000", "000"};//Test,Cab,CoinB,CoinA +wire [7:0] iCTR1 = ~{ btn_coin, 1'b0, m_right1, m_left1, m_fire1, status[6], 1'b0, m_up2}; +wire [7:0] iCTR2 = ~{ btn_one_player, btn_two_players, m_left2, m_right2, m_fire2, 1'b0, m_down2, m_up1}; + +cmd_top cmd_top( + .RESET(status[0] | status[6] | buttons[1]), + .CLK24M(clock_24), + .hsync(hs), + .vsync(vs), + .hblank(hb), + .vblank(vb), + .r(r), + .g(g), + .b(b), + .SND(audio), + .DSW1(iDSW1), + .DSW2(iDSW2), + .CTR1(iCTR1), + .CTR2(iCTR2), + .LAMP() + ); + +mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video( + .clk_sys ( clock_24 ), + .SPI_SCK ( SPI_SCK ), + .SPI_SS3 ( SPI_SS3 ), + .SPI_DI ( SPI_DI ), + .R ( blankn ? r : 0 ), + .G ( blankn ? g : 0 ), + .B ( blankn ? {b,1'b0} : 0 ), + .HSync ( hs ), + .VSync ( vs ), + .VGA_R ( VGA_R ), + .VGA_G ( VGA_G ), + .VGA_B ( VGA_B ), + .VGA_VS ( VGA_VS ), + .VGA_HS ( VGA_HS ), + .rotate ({1'b1,status[2]} ), + .scandoubler_disable( scandoublerD ), + .scanlines ( status[4:3] ), + .ypbpr ( ypbpr ) + ); + +user_io #(.STRLEN(($size(CONF_STR)>>3)))user_io( + .clk_sys (clock_24 ), + .conf_str (CONF_STR ), + .SPI_CLK (SPI_SCK ), + .SPI_SS_IO (CONF_DATA0 ), + .SPI_MISO (SPI_DO ), + .SPI_MOSI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable (scandoublerD ), + .ypbpr (ypbpr ), + .key_strobe (key_strobe ), + .key_pressed (key_pressed ), + .key_code (key_code ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) + ); + +dac #(.C_bits(16))dac( + .clk_i(clock_24), + .res_n_i(1), + .dac_i({audio,4'b0}), + .dac_o(AUDIO_L) + ); + +wire m_up1 = btn_up | joystick_0[3]; +wire m_down1 = btn_down | joystick_0[2]; +wire m_left1 = btn_left | joystick_0[1]; +wire m_right1 = btn_right | joystick_0[0]; +wire m_fire1 = btn_fire1 | joystick_0[4]; + +wire m_up2 = btn_up | joystick_1[3]; +wire m_down2 = btn_down | joystick_1[2]; +wire m_left2 = btn_left | joystick_1[1]; +wire m_right2 = btn_right | joystick_1[0]; +wire m_fire2 = btn_fire1 | joystick_1[4]; + + +reg btn_one_player = 0; +reg btn_two_players = 0; +reg btn_left = 0; +reg btn_right = 0; +reg btn_down = 0; +reg btn_up = 0; +reg btn_fire1 = 0; +//reg btn_fire2 = 0; +//reg btn_fire3 = 0; +reg btn_coin = 0; + +always @(posedge clock_24) begin + reg old_state; + old_state <= key_strobe; + if(old_state != key_strobe) begin + case(key_code) + 'h75: btn_up <= key_pressed; // up + 'h72: btn_down <= key_pressed; // down + 'h6B: btn_left <= key_pressed; // left + 'h74: btn_right <= key_pressed; // right + 'h76: btn_coin <= key_pressed; // ESC + 'h05: btn_one_player <= key_pressed; // F1 + 'h06: btn_two_players <= key_pressed; // F2 + // 'h14: btn_fire3 <= key_pressed; // ctrl + // 'h11: btn_fire2 <= key_pressed; // alt + 'h29: btn_fire1 <= key_pressed; // Space + endcase + end +end + +endmodule diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T65/T65.vhd b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T65/T65.vhd new file mode 100644 index 00000000..09253fe0 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T65/T65.vhd @@ -0,0 +1,564 @@ +-- **** +-- T65(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 more merging +-- Ver 300 Bugfixes by ehenciak added, started tidyup *bust* +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- 65xx compatible microprocessor core +-- +-- Version : 0246 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t65/ +-- +-- Limitations : +-- +-- 65C02 and 65C816 modes are incomplete +-- Undocumented instructions are not supported +-- Some interface signals behaves incorrect +-- +-- File history : +-- +-- 0246 : First release +-- + +library IEEE; + use IEEE.std_logic_1164.all; + use IEEE.numeric_std.all; + use work.T65_Pack.all; + +-- ehenciak 2-23-2005 : Added the enable signal so that one doesn't have to use +-- the ready signal to limit the CPU. +entity T65 is + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816 + Res_n : in std_logic; + Enable : in std_logic; + Clk : in std_logic; + Rdy : in std_logic; + Abort_n : in std_logic; + IRQ_n : in std_logic; + NMI_n : in std_logic; + SO_n : in std_logic; + R_W_n : out std_logic; + Sync : out std_logic; + EF : out std_logic; + MF : out std_logic; + XF : out std_logic; + ML_n : out std_logic; + VP_n : out std_logic; + VDA : out std_logic; + VPA : out std_logic; + A : out std_logic_vector(23 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T65; + +architecture rtl of T65 is + + -- Registers + signal ABC, X, Y, D : std_logic_vector(15 downto 0); + signal P, AD, DL : std_logic_vector(7 downto 0) := x"00"; + signal BAH : std_logic_vector(7 downto 0); + signal BAL : std_logic_vector(8 downto 0); + signal PBR : std_logic_vector(7 downto 0); + signal DBR : std_logic_vector(7 downto 0); + signal PC : unsigned(15 downto 0); + signal S : unsigned(15 downto 0); + signal EF_i : std_logic; + signal MF_i : std_logic; + signal XF_i : std_logic; + + signal IR : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + + signal Mode_r : std_logic_vector(1 downto 0); + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Write_Data_r : std_logic_vector(2 downto 0); + signal Set_Addr_To_r : std_logic_vector(1 downto 0); + signal PCAdder : unsigned(8 downto 0); + + signal RstCycle : std_logic; + signal IRQCycle : std_logic; + signal NMICycle : std_logic; + + signal B_o : std_logic; + signal SO_n_o : std_logic; + signal IRQ_n_o : std_logic; + signal NMI_n_o : std_logic; + signal NMIAct : std_logic; + + signal Break : std_logic; + + -- ALU signals + signal BusA : std_logic_vector(7 downto 0); + signal BusA_r : std_logic_vector(7 downto 0); + signal BusB : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal P_Out : std_logic_vector(7 downto 0); + + -- Micro code outputs + signal LCycle : std_logic_vector(2 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(2 downto 0); + signal Set_Addr_To : std_logic_vector(1 downto 0); + signal Write_Data : std_logic_vector(2 downto 0); + signal Jump : std_logic_vector(1 downto 0); + signal BAAdd : std_logic_vector(1 downto 0); + signal BreakAtNA : std_logic; + signal ADAdd : std_logic; + signal AddY : std_logic; + signal PCAdd : std_logic; + signal Inc_S : std_logic; + signal Dec_S : std_logic; + signal LDA : std_logic; + signal LDP : std_logic; + signal LDX : std_logic; + signal LDY : std_logic; + signal LDS : std_logic; + signal LDDI : std_logic; + signal LDALU : std_logic; + signal LDAD : std_logic; + signal LDBAL : std_logic; + signal LDBAH : std_logic; + signal SaveP : std_logic; + signal Write : std_logic; + + signal really_rdy : std_logic; + signal R_W_n_i : std_logic; + +begin + -- ehenciak : gate Rdy with read/write to make an "OK, it's + -- really OK to stop the processor now if Rdy is + -- deasserted" signal + really_rdy <= Rdy or not(R_W_n_i); + + -- ehenciak : Drive R_W_n_i off chip. + R_W_n <= R_W_n_i; + + Sync <= '1' when MCycle = "000" else '0'; + EF <= EF_i; + MF <= MF_i; + XF <= XF_i; + ML_n <= '0' when IR(7 downto 6) /= "10" and IR(2 downto 1) = "11" and MCycle(2 downto 1) /= "00" else '1'; + VP_n <= '0' when IRQCycle = '1' and (MCycle = "101" or MCycle = "110") else '1'; + VDA <= '1' when Set_Addr_To_r /= "00" else '0'; -- Incorrect !!!!!!!!!!!! + VPA <= '1' when Jump(1) = '0' else '0'; -- Incorrect !!!!!!!!!!!! + + mcode : T65_MCode + port map( + Mode => Mode_r, + IR => IR, + MCycle => MCycle, + P => P, + LCycle => LCycle, + ALU_Op => ALU_Op, + Set_BusA_To => Set_BusA_To, + Set_Addr_To => Set_Addr_To, + Write_Data => Write_Data, + Jump => Jump, + BAAdd => BAAdd, + BreakAtNA => BreakAtNA, + ADAdd => ADAdd, + AddY => AddY, + PCAdd => PCAdd, + Inc_S => Inc_S, + Dec_S => Dec_S, + LDA => LDA, + LDP => LDP, + LDX => LDX, + LDY => LDY, + LDS => LDS, + LDDI => LDDI, + LDALU => LDALU, + LDAD => LDAD, + LDBAL => LDBAL, + LDBAH => LDBAH, + SaveP => SaveP, + Write => Write + ); + + alu : T65_ALU + port map( + Mode => Mode_r, + Op => ALU_Op_r, + BusA => BusA_r, + BusB => BusB, + P_In => P, + P_Out => P_Out, + Q => ALU_Q + ); + + process (Res_n, Clk) + begin + if Res_n = '0' then + PC <= (others => '0'); -- Program Counter + IR <= "00000000"; + S <= (others => '0'); -- Dummy !!!!!!!!!!!!!!!!!!!!! + D <= (others => '0'); + PBR <= (others => '0'); + DBR <= (others => '0'); + + Mode_r <= (others => '0'); + ALU_Op_r <= "1100"; + Write_Data_r <= "000"; + Set_Addr_To_r <= "00"; + + R_W_n_i <= '1'; + EF_i <= '1'; + MF_i <= '1'; + XF_i <= '1'; + + elsif Clk'event and Clk = '1' then + if (Enable = '1') then + if (really_rdy = '1') then + R_W_n_i <= not Write or RstCycle; + + D <= (others => '1'); -- Dummy + PBR <= (others => '1'); -- Dummy + DBR <= (others => '1'); -- Dummy + EF_i <= '0'; -- Dummy + MF_i <= '0'; -- Dummy + XF_i <= '0'; -- Dummy + + if MCycle = "000" then + Mode_r <= Mode; + + if IRQCycle = '0' and NMICycle = '0' then + PC <= PC + 1; + end if; + + if IRQCycle = '1' or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DI; + end if; + end if; + + ALU_Op_r <= ALU_Op; + Write_Data_r <= Write_Data; + if Break = '1' then + Set_Addr_To_r <= "00"; + else + Set_Addr_To_r <= Set_Addr_To; + end if; + + if Inc_S = '1' then + S <= S + 1; + end if; + if Dec_S = '1' and RstCycle = '0' then + S <= S - 1; + end if; + if LDS = '1' then + S(7 downto 0) <= unsigned(ALU_Q); + end if; + + if IR = "00000000" and MCycle = "001" and IRQCycle = '0' and NMICycle = '0' then + PC <= PC + 1; + end if; + -- + -- jump control logic + -- + case Jump is + when "01" => + PC <= PC + 1; + + when "10" => + PC <= unsigned(DI & DL); + + when "11" => + if PCAdder(8) = '1' then + if DL(7) = '0' then + PC(15 downto 8) <= PC(15 downto 8) + 1; + else + PC(15 downto 8) <= PC(15 downto 8) - 1; + end if; + end if; + PC(7 downto 0) <= PCAdder(7 downto 0); + + when others => null; + end case; + end if; + end if; + end if; + end process; + + PCAdder <= resize(PC(7 downto 0),9) + resize(unsigned(DL(7) & DL),9) when PCAdd = '1' + else "0" & PC(7 downto 0); + + process (Clk) + begin + if Clk'event and Clk = '1' then + if (Enable = '1') then + if (really_rdy = '1') then + if MCycle = "000" then + if LDA = '1' then + ABC(7 downto 0) <= ALU_Q; + end if; + if LDX = '1' then + X(7 downto 0) <= ALU_Q; + end if; + if LDY = '1' then + Y(7 downto 0) <= ALU_Q; + end if; + if (LDA or LDX or LDY) = '1' then + P <= P_Out; + end if; + end if; + if SaveP = '1' then + P <= P_Out; + end if; + if LDP = '1' then + P <= ALU_Q; + end if; + if IR(4 downto 0) = "11000" then + case IR(7 downto 5) is + when "000" => + P(Flag_C) <= '0'; + when "001" => + P(Flag_C) <= '1'; + when "010" => + P(Flag_I) <= '0'; + when "011" => + P(Flag_I) <= '1'; + when "101" => + P(Flag_V) <= '0'; + when "110" => + P(Flag_D) <= '0'; + when "111" => + P(Flag_D) <= '1'; + when others => + end case; + end if; + + --if IR = "00000000" and MCycle = "011" and RstCycle = '0' and NMICycle = '0' and IRQCycle = '0' then + -- P(Flag_B) <= '1'; + --end if; + --if IR = "00000000" and MCycle = "100" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1') then + -- P(Flag_I) <= '1'; + -- P(Flag_B) <= B_o; + --end if; + + -- B=1 always on the 6502 + P(Flag_B) <= '1'; + if IR = "00000000" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1') then + if MCycle = "011" then + -- B=0 in *copy* of P pushed onto the stack + P(Flag_B) <= '0'; + elsif MCycle = "100" then + P(Flag_I) <= '1'; + end if; + end if; + + if SO_n_o = '1' and SO_n = '0' then + P(Flag_V) <= '1'; + end if; + if RstCycle = '1' and Mode_r /= "00" then + P(Flag_1) <= '1'; + P(Flag_D) <= '0'; + P(Flag_I) <= '1'; + end if; + P(Flag_1) <= '1'; + + B_o <= P(Flag_B); + SO_n_o <= SO_n; + IRQ_n_o <= IRQ_n; + NMI_n_o <= NMI_n; + end if; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + + process (Res_n, Clk) + begin + if Res_n = '0' then + BusA_r <= (others => '0'); + BusB <= (others => '0'); + AD <= (others => '0'); + BAL <= (others => '0'); + BAH <= (others => '0'); + DL <= (others => '0'); + elsif Clk'event and Clk = '1' then + if (Enable = '1') then + if (Rdy = '1') then + BusA_r <= BusA; + BusB <= DI; + + case BAAdd is + when "01" => + -- BA Inc + AD <= std_logic_vector(unsigned(AD) + 1); + BAL <= std_logic_vector(unsigned(BAL) + 1); + when "10" => + -- BA Add + BAL <= std_logic_vector(resize(unsigned(BAL(7 downto 0)),9) + resize(unsigned(BusA),9)); + when "11" => + -- BA Adj + if BAL(8) = '1' then + BAH <= std_logic_vector(unsigned(BAH) + 1); + end if; + when others => + end case; + + -- ehenciak : modified to use Y register as well (bugfix) + if ADAdd = '1' then + if (AddY = '1') then + AD <= std_logic_vector(unsigned(AD) + unsigned(Y(7 downto 0))); + else + AD <= std_logic_vector(unsigned(AD) + unsigned(X(7 downto 0))); + end if; + end if; + + if IR = "00000000" then + BAL <= (others => '1'); + BAH <= (others => '1'); + if RstCycle = '1' then + BAL(2 downto 0) <= "100"; + elsif NMICycle = '1' then + BAL(2 downto 0) <= "010"; + else + BAL(2 downto 0) <= "110"; + end if; + if Set_addr_To_r = "11" then + BAL(0) <= '1'; + end if; + end if; + + + if LDDI = '1' then + DL <= DI; + end if; + if LDALU = '1' then + DL <= ALU_Q; + end if; + if LDAD = '1' then + AD <= DI; + end if; + if LDBAL = '1' then + BAL(7 downto 0) <= DI; + end if; + if LDBAH = '1' then + BAH <= DI; + end if; + end if; + end if; + end if; + end process; + + Break <= (BreakAtNA and not BAL(8)) or (PCAdd and not PCAdder(8)); + + + with Set_BusA_To select + BusA <= DI when "000", + ABC(7 downto 0) when "001", + X(7 downto 0) when "010", + Y(7 downto 0) when "011", + std_logic_vector(S(7 downto 0)) when "100", + P when "101", + (others => '-') when others; + + with Set_Addr_To_r select + A <= "0000000000000001" & std_logic_vector(S(7 downto 0)) when "01", + DBR & "00000000" & AD when "10", + "00000000" & BAH & BAL(7 downto 0) when "11", + PBR & std_logic_vector(PC(15 downto 8)) & std_logic_vector(PCAdder(7 downto 0)) when others; + + with Write_Data_r select + DO <= DL when "000", + ABC(7 downto 0) when "001", + X(7 downto 0) when "010", + Y(7 downto 0) when "011", + std_logic_vector(S(7 downto 0)) when "100", + P when "101", + std_logic_vector(PC(7 downto 0)) when "110", + std_logic_vector(PC(15 downto 8)) when others; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + + process (Res_n, Clk) + begin + if Res_n = '0' then + MCycle <= "001"; + RstCycle <= '1'; + IRQCycle <= '0'; + NMICycle <= '0'; + NMIAct <= '0'; + elsif Clk'event and Clk = '1' then + if (Enable = '1') then + if (really_rdy = '1') then + if MCycle = LCycle or Break = '1' then + MCycle <= "000"; + RstCycle <= '0'; + IRQCycle <= '0'; + NMICycle <= '0'; + if NMIAct = '1' then + NMICycle <= '1'; + elsif IRQ_n_o = '0' and P(Flag_I) = '0' then + IRQCycle <= '1'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + + if NMICycle = '1' then + NMIAct <= '0'; + end if; + if NMI_n_o = '1' and NMI_n = '0' then + NMIAct <= '1'; + end if; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T65/T65_ALU.vhd b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T65/T65_ALU.vhd new file mode 100644 index 00000000..b1f6d632 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T65/T65_ALU.vhd @@ -0,0 +1,260 @@ +-- **** +-- T65(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 Bugfixes by ehenciak added +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- 6502 compatible microprocessor core +-- +-- Version : 0245 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t65/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0245 : First version +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T65_Pack.all; + +entity T65_ALU is + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816 + Op : in std_logic_vector(3 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + P_In : in std_logic_vector(7 downto 0); + P_Out : out std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0) + ); +end T65_ALU; + +architecture rtl of T65_ALU is + + -- AddSub variables (temporary signals) + signal ADC_Z : std_logic; + signal ADC_C : std_logic; + signal ADC_V : std_logic; + signal ADC_N : std_logic; + signal ADC_Q : std_logic_vector(7 downto 0); + signal SBC_Z : std_logic; + signal SBC_C : std_logic; + signal SBC_V : std_logic; + signal SBC_N : std_logic; + signal SBC_Q : std_logic_vector(7 downto 0); + +begin + + process (P_In, BusA, BusB) + variable AL : unsigned(6 downto 0); + variable AH : unsigned(6 downto 0); + variable C : std_logic; + begin + AL := resize(unsigned(BusA(3 downto 0) & P_In(Flag_C)), 7) + resize(unsigned(BusB(3 downto 0) & "1"), 7); + AH := resize(unsigned(BusA(7 downto 4) & AL(5)), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7); + +-- pragma translate_off + if is_x(std_logic_vector(AL)) then AL := "0000000"; end if; + if is_x(std_logic_vector(AH)) then AH := "0000000"; end if; +-- pragma translate_on + + if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then + ADC_Z <= '1'; + else + ADC_Z <= '0'; + end if; + + if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' then + AL(6 downto 1) := AL(6 downto 1) + 6; + end if; + + C := AL(6) or AL(5); + AH := resize(unsigned(BusA(7 downto 4) & C), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7); + + ADC_N <= AH(4); + ADC_V <= (AH(4) xor BusA(7)) and not (BusA(7) xor BusB(7)); + +-- pragma translate_off + if is_x(std_logic_vector(AH)) then AH := "0000000"; end if; +-- pragma translate_on + + if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' then + AH(6 downto 1) := AH(6 downto 1) + 6; + end if; + + ADC_C <= AH(6) or AH(5); + + ADC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1)); + end process; + + process (Op, P_In, BusA, BusB) + variable AL : unsigned(6 downto 0); + variable AH : unsigned(5 downto 0); + variable C : std_logic; + begin + C := P_In(Flag_C) or not Op(0); + AL := resize(unsigned(BusA(3 downto 0) & C), 7) - resize(unsigned(BusB(3 downto 0) & "1"), 6); + AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(5)), 6); + +-- pragma translate_off + if is_x(std_logic_vector(AL)) then AL := "0000000"; end if; + if is_x(std_logic_vector(AH)) then AH := "000000"; end if; +-- pragma translate_on + + if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then + SBC_Z <= '1'; + else + SBC_Z <= '0'; + end if; + + SBC_C <= not AH(5); + SBC_V <= (AH(4) xor BusA(7)) and (BusA(7) xor BusB(7)); + SBC_N <= AH(4); + + if P_In(Flag_D) = '1' then + if AL(5) = '1' then + AL(5 downto 1) := AL(5 downto 1) - 6; + end if; + AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(6)), 6); + if AH(5) = '1' then + AH(5 downto 1) := AH(5 downto 1) - 6; + end if; + end if; + + SBC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1)); + end process; + + process (Op, P_In, BusA, BusB, + ADC_Z, ADC_C, ADC_V, ADC_N, ADC_Q, + SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q) + variable Q_t : std_logic_vector(7 downto 0); + begin + -- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC + -- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC + P_Out <= P_In; + Q_t := BusA; + case Op(3 downto 0) is + when "0000" => + -- ORA + Q_t := BusA or BusB; + when "0001" => + -- AND + Q_t := BusA and BusB; + when "0010" => + -- EOR + Q_t := BusA xor BusB; + when "0011" => + -- ADC + P_Out(Flag_V) <= ADC_V; + P_Out(Flag_C) <= ADC_C; + Q_t := ADC_Q; + when "0101" | "1101" => + -- LDA + when "0110" => + -- CMP + P_Out(Flag_C) <= SBC_C; + when "0111" => + -- SBC + P_Out(Flag_V) <= SBC_V; + P_Out(Flag_C) <= SBC_C; + Q_t := SBC_Q; + when "1000" => + -- ASL + Q_t := BusA(6 downto 0) & "0"; + P_Out(Flag_C) <= BusA(7); + when "1001" => + -- ROL + Q_t := BusA(6 downto 0) & P_In(Flag_C); + P_Out(Flag_C) <= BusA(7); + when "1010" => + -- LSR + Q_t := "0" & BusA(7 downto 1); + P_Out(Flag_C) <= BusA(0); + when "1011" => + -- ROR + Q_t := P_In(Flag_C) & BusA(7 downto 1); + P_Out(Flag_C) <= BusA(0); + when "1100" => + -- BIT + P_Out(Flag_V) <= BusB(6); + when "1110" => + -- DEC + Q_t := std_logic_vector(unsigned(BusA) - 1); + when "1111" => + -- INC + Q_t := std_logic_vector(unsigned(BusA) + 1); + when others => + end case; + + case Op(3 downto 0) is + when "0011" => + P_Out(Flag_N) <= ADC_N; + P_Out(Flag_Z) <= ADC_Z; + when "0110" | "0111" => + P_Out(Flag_N) <= SBC_N; + P_Out(Flag_Z) <= SBC_Z; + when "0100" => + when "1100" => + P_Out(Flag_N) <= BusB(7); + if (BusA and BusB) = "00000000" then + P_Out(Flag_Z) <= '1'; + else + P_Out(Flag_Z) <= '0'; + end if; + when others => + P_Out(Flag_N) <= Q_t(7); + if Q_t = "00000000" then + P_Out(Flag_Z) <= '1'; + else + P_Out(Flag_Z) <= '0'; + end if; + end case; + + Q <= Q_t; + end process; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T65/T65_MCode.vhd b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T65/T65_MCode.vhd new file mode 100644 index 00000000..6c6c864a --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T65/T65_MCode.vhd @@ -0,0 +1,1052 @@ +-- **** +-- T65(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 302 minor timing fixes +-- Ver 301 Jump timing fixed +-- Ver 300 Bugfixes by ehenciak added +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- 65xx compatible microprocessor core +-- +-- Version : 0246 + fix +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t65/ +-- +-- Limitations : +-- +-- 65C02 +-- supported : inc, dec, phx, plx, phy, ply +-- missing : bra, ora, lda, cmp, sbc, tsb*2, trb*2, stz*2, bit*2, wai, stp, jmp, bbr*8, bbs*8 +-- +-- File history : +-- +-- 0246 : First release +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T65_Pack.all; + +entity T65_MCode is + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816 + IR : in std_logic_vector(7 downto 0); + MCycle : in std_logic_vector(2 downto 0); + P : in std_logic_vector(7 downto 0); + LCycle : out std_logic_vector(2 downto 0); + ALU_Op : out std_logic_vector(3 downto 0); + Set_BusA_To : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P + Set_Addr_To : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA + Write_Data : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH + Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel + BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj + BreakAtNA : out std_logic; + ADAdd : out std_logic; + AddY : out std_logic; + PCAdd : out std_logic; + Inc_S : out std_logic; + Dec_S : out std_logic; + LDA : out std_logic; + LDP : out std_logic; + LDX : out std_logic; + LDY : out std_logic; + LDS : out std_logic; + LDDI : out std_logic; + LDALU : out std_logic; + LDAD : out std_logic; + LDBAL : out std_logic; + LDBAH : out std_logic; + SaveP : out std_logic; + Write : out std_logic + ); +end T65_MCode; + +architecture rtl of T65_MCode is + + signal Branch : std_logic; + +begin + + with IR(7 downto 5) select + Branch <= not P(Flag_N) when "000", + P(Flag_N) when "001", + not P(Flag_V) when "010", + P(Flag_V) when "011", + not P(Flag_C) when "100", + P(Flag_C) when "101", + not P(Flag_Z) when "110", + P(Flag_Z) when others; + + process (IR, MCycle, P, Branch, Mode) + begin + LCycle <= "001"; + Set_BusA_To <= "001"; -- A + Set_Addr_To <= (others => '0'); + Write_Data <= (others => '0'); + Jump <= (others => '0'); + BAAdd <= "00"; + BreakAtNA <= '0'; + ADAdd <= '0'; + PCAdd <= '0'; + Inc_S <= '0'; + Dec_S <= '0'; + LDA <= '0'; + LDP <= '0'; + LDX <= '0'; + LDY <= '0'; + LDS <= '0'; + LDDI <= '0'; + LDALU <= '0'; + LDAD <= '0'; + LDBAL <= '0'; + LDBAH <= '0'; + SaveP <= '0'; + Write <= '0'; + AddY <= '0'; + + case IR(7 downto 5) is + when "100" => + --{{{ + case IR(1 downto 0) is + when "00" => + Set_BusA_To <= "011"; -- Y + Write_Data <= "011"; -- Y + when "10" => + Set_BusA_To <= "010"; -- X + Write_Data <= "010"; -- X + when others => + Write_Data <= "001"; -- A + end case; + --}}} + when "101" => + --{{{ + case IR(1 downto 0) is + when "00" => + if IR(4) /= '1' or IR(2) /= '0' then + LDY <= '1'; + end if; + when "10" => + LDX <= '1'; + when others => + LDA <= '1'; + end case; + Set_BusA_To <= "000"; -- DI + --}}} + when "110" => + --{{{ + case IR(1 downto 0) is + when "00" => + if IR(4) = '0' then + LDY <= '1'; + end if; + Set_BusA_To <= "011"; -- Y + when others => + Set_BusA_To <= "001"; -- A + end case; + --}}} + when "111" => + --{{{ + case IR(1 downto 0) is + when "00" => + if IR(4) = '0' then + LDX <= '1'; + end if; + Set_BusA_To <= "010"; -- X + when others => + Set_BusA_To <= "001"; -- A + end case; + --}}} + when others => + end case; + + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + Set_BusA_To <= "000"; -- DI + end if; + + case IR(4 downto 0) is + when "00000" | "01000" | "01010" | "11000" | "11010" => + --{{{ + -- Implied + case IR is + when "00000000" => + -- BRK + LCycle <= "110"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= "01"; -- S + Write_Data <= "111"; -- PCH + Write <= '1'; + when 2 => + Dec_S <= '1'; + Set_Addr_To <= "01"; -- S + Write_Data <= "110"; -- PCL + Write <= '1'; + when 3 => + Dec_S <= '1'; + Set_Addr_To <= "01"; -- S + Write_Data <= "101"; -- P + Write <= '1'; + when 4 => + Dec_S <= '1'; + Set_Addr_To <= "11"; -- BA + when 5 => + LDDI <= '1'; + Set_Addr_To <= "11"; -- BA + when 6 => + Jump <= "10"; -- DIDL + when others => + end case; + when "00100000" => + -- JSR + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDDI <= '1'; + Set_Addr_To <= "01"; -- S + when 2 => + Set_Addr_To <= "01"; -- S + Write_Data <= "111"; -- PCH + Write <= '1'; + when 3 => + Dec_S <= '1'; + Set_Addr_To <= "01"; -- S + Write_Data <= "110"; -- PCL + Write <= '1'; + when 4 => + Dec_S <= '1'; + when 5 => + Jump <= "10"; -- DIDL + when others => + end case; + when "01000000" => + -- RTI + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= "01"; -- S + when 2 => + Inc_S <= '1'; + Set_Addr_To <= "01"; -- S + when 3 => + Inc_S <= '1'; + Set_Addr_To <= "01"; -- S + Set_BusA_To <= "000"; -- DI + when 4 => + LDP <= '1'; + Inc_S <= '1'; + LDDI <= '1'; + Set_Addr_To <= "01"; -- S + when 5 => + Jump <= "10"; -- DIDL + when others => + end case; + when "01100000" => + -- RTS + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= "01"; -- S + when 2 => + Inc_S <= '1'; + Set_Addr_To <= "01"; -- S + when 3 => + Inc_S <= '1'; + LDDI <= '1'; + Set_Addr_To <= "01"; -- S + when 4 => + Jump <= "10"; -- DIDL + when 5 => + Jump <= "01"; + when others => + end case; + when "00001000" | "01001000" | "01011010" | "11011010" => + -- PHP, PHA, PHY*, PHX* + LCycle <= "010"; + if Mode = "00" and IR(1) = '1' then + LCycle <= "001"; + end if; + case to_integer(unsigned(MCycle)) is + when 1 => + case IR(7 downto 4) is + when "0000" => + Write_Data <= "101"; -- P + when "0100" => + Write_Data <= "001"; -- A + when "0101" => + Write_Data <= "011"; -- Y + when "1101" => + Write_Data <= "010"; -- X + when others => + end case; + Write <= '1'; + Set_Addr_To <= "01"; -- S + when 2 => + Dec_S <= '1'; + when others => + end case; + when "00101000" | "01101000" | "01111010" | "11111010" => + -- PLP, PLA, PLY*, PLX* + LCycle <= "011"; + if Mode = "00" and IR(1) = '1' then + LCycle <= "001"; + end if; + case IR(7 downto 4) is + when "0010" => + LDP <= '1'; + when "0110" => + LDA <= '1'; + when "0111" => + if Mode /= "00" then + LDY <= '1'; + end if; + when "1111" => + if Mode /= "00" then + LDX <= '1'; + end if; + when others => + end case; + case to_integer(unsigned(MCycle)) is + when 0 => + SaveP <= '1'; + when 1 => + Set_Addr_To <= "01"; -- S + when 2 => + Inc_S <= '1'; + Set_Addr_To <= "01"; -- S + when 3 => + Set_BusA_To <= "000"; -- DI + when others => + end case; + when "10100000" | "11000000" | "11100000" => + -- LDY, CPY, CPX + -- Immediate + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + when others => + end case; + when "10001000" => + -- DEY + LDY <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "011"; -- Y + when others => + end case; + when "11001010" => + -- DEX + LDX <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "010"; -- X + when others => + end case; + when "00011010" | "00111010" => + -- INC*, DEC* + if Mode /= "00" then + LDA <= '1'; -- A + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "100"; -- S + when others => + end case; + when "00001010" | "00101010" | "01001010" | "01101010" => + -- ASL, ROL, LSR, ROR + LDA <= '1'; -- A + Set_BusA_To <= "001"; -- A + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + when others => + end case; + when "10001010" | "10011000" => + -- TYA, TXA + LDA <= '1'; -- A + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + when others => + end case; + when "10101010" | "10101000" => + -- TAX, TAY + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "001"; -- A + when others => + end case; + when "10011010" => + -- TXS + case to_integer(unsigned(MCycle)) is + when 0 => + LDS <= '1'; + when 1 => + when others => + end case; + when "10111010" => + -- TSX + LDX <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "100"; -- S + when others => + end case; + + -- when "00011000" | "00111000" | "01011000" | "01111000" | "10111000" | "11011000" | "11111000" | "11001000" | "11101000" => + -- -- CLC, SEC, CLI, SEI, CLV, CLD, SED, INY, INX + -- case to_integer(unsigned(MCycle)) is + -- when 1 => + -- when others => + -- end case; + when others => + case to_integer(unsigned(MCycle)) is + when 0 => + when others => + end case; + end case; + --}}} + + when "00001" | "00011" => + --{{{ + -- Zero Page Indexed Indirect (d,x) + LCycle <= "101"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + ADAdd <= '1'; + Set_Addr_To <= "10"; -- AD + when 3 => + BAAdd <= "01"; -- DB Inc + LDBAL <= '1'; + Set_Addr_To <= "10"; -- AD + when 4 => + LDBAH <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 5 => + when others => + end case; + --}}} + + when "01001" | "01011" => + --{{{ + -- Immediate + LDA <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + when others => + end case; + + --}}} + + when "00010" | "10010" => + --{{{ + -- Immediate, KIL + LDX <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + if IR = "10100010" then + -- LDX + Jump <= "01"; + else + -- KIL !!!!!!!!!!!!!!!!!!!!!!!!!!!!! + end if; + when others => + end case; + --}}} + + when "00100" => + --{{{ + -- Zero Page + LCycle <= "010"; + case to_integer(unsigned(MCycle)) is + when 0 => + if IR(7 downto 5) = "001" then + SaveP <= '1'; + end if; + when 1 => + Jump <= "01"; + LDAD <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "10"; -- AD + when 2 => + when others => + end case; + --}}} + + when "00101" | "00110" | "00111" => + --{{{ + -- Zero Page + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + -- Read-Modify-Write + LCycle <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + LDDI <= '1'; + Write <= '1'; + Set_Addr_To <= "10"; -- AD + when 3 => + LDALU <= '1'; + SaveP <= '1'; + Write <= '1'; + Set_Addr_To <= "10"; -- AD + when 4 => + when others => + end case; + else + LCycle <= "010"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDAD <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "10"; -- AD + when 2 => + when others => + end case; + end if; + --}}} + + when "01100" => + --{{{ + -- Absolute + if IR(7 downto 6) = "01" and IR(4 downto 0) = "01100" then + -- JMP + if IR(5) = '0' then + --LCycle <= "011"; + LCycle <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDDI <= '1'; + when 2 => + Jump <= "10"; -- DIDL + when others => + end case; + else + --LCycle <= "101"; + LCycle <= "100"; -- mikej + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDDI <= '1'; + LDBAL <= '1'; + when 2 => + LDBAH <= '1'; + if Mode /= "00" then + Jump <= "10"; -- DIDL + end if; + if Mode = "00" then + Set_Addr_To <= "11"; -- BA + end if; + when 3 => + LDDI <= '1'; + if Mode = "00" then + Set_Addr_To <= "11"; -- BA + BAAdd <= "01"; -- DB Inc + else + Jump <= "01"; + end if; + when 4 => + Jump <= "10"; -- DIDL + when others => + end case; + end if; + else + LCycle <= "011"; + case to_integer(unsigned(MCycle)) is + when 0 => + if IR(7 downto 5) = "001" then + SaveP <= '1'; + end if; + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + LDBAH <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 3 => + when others => + end case; + end if; + --}}} + + when "01101" | "01110" | "01111" => + --{{{ + -- Absolute + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + -- Read-Modify-Write + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 3 => + LDDI <= '1'; + Write <= '1'; + Set_Addr_To <= "11"; -- BA + when 4 => + Write <= '1'; + LDALU <= '1'; + SaveP <= '1'; + Set_Addr_To <= "11"; -- BA + when 5 => + SaveP <= '0'; -- MIKEJ was 1 + when others => + end case; + else + LCycle <= "011"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + LDBAH <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 3 => + when others => + end case; + end if; + --}}} + + when "10000" => + --{{{ + -- Relative + + -- This circuit dictates when the last + -- microcycle occurs for the branch depending on + -- whether or not the branch is taken and if a page + -- is crossed... + if (Branch = '1') then + + LCycle <= "011"; -- We're done @ T3 if branching...upper + -- level logic will stop at T2 if no page cross + -- (See the Break signal) + else + + LCycle <= "001"; + + end if; + + -- This decodes the current microcycle and takes the + -- proper course of action... + case to_integer(unsigned(MCycle)) is + + -- On the T1 microcycle, increment the program counter + -- and instruct the upper level logic to fetch the offset + -- from the Din bus and store it in the data latches. This + -- will be the last microcycle if the branch isn't taken. + when 1 => + + Jump <= "01"; -- Increments the PC by one (PC will now be PC+2) + -- from microcycle T0. + + LDDI <= '1'; -- Tells logic in top level (T65.vhd) to route + -- the Din bus to the memory data latch (DL) + -- so that the branch offset is fetched. + + -- In microcycle T2, tell the logic in the top level to + -- add the offset. If the most significant byte of the + -- program counter (i.e. the current "page") does not need + -- updating, we are done here...the Break signal at the + -- T65.vhd level takes care of that... + when 2 => + + Jump <= "11"; -- Tell the PC Jump logic to use relative mode. + + PCAdd <= '1'; -- This tells the PC adder to update itself with + -- the current offset recently fetched from + -- memory. + + -- The following is microcycle T3 : + -- The program counter should be completely updated + -- on this cycle after the page cross is detected. + -- We don't need to do anything here... + when 3 => + + + when others => null; -- Do nothing. + + end case; + --}}} + + when "10001" | "10011" => + --{{{ + -- Zero Page Indirect Indexed (d),y + LCycle <= "101"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + LDBAL <= '1'; + BAAdd <= "01"; -- DB Inc + Set_Addr_To <= "10"; -- AD + when 3 => + Set_BusA_To <= "011"; -- Y + BAAdd <= "10"; -- BA Add + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 4 => + BAAdd <= "11"; -- BA Adj + if IR(7 downto 5) = "100" then + Write <= '1'; + else + BreakAtNA <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 5 => + when others => + end case; + --}}} + + when "10100" | "10101" | "10110" | "10111" => + --{{{ + -- Zero Page, X + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + -- Read-Modify-Write + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + ADAdd <= '1'; + Set_Addr_To <= "10"; -- AD + when 3 => + LDDI <= '1'; + Write <= '1'; + Set_Addr_To <= "10"; -- AD + when 4 => + LDALU <= '1'; + SaveP <= '1'; + Write <= '1'; + Set_Addr_To <= "10"; -- AD + when 5 => + when others => + end case; + else + LCycle <= "011"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + ADAdd <= '1'; + -- Added this check for Y reg. use... + if (IR(3 downto 0) = "0110") then + AddY <= '1'; + end if; + + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "10"; -- AD + when 3 => null; + when others => + end case; + end if; + --}}} + + when "11001" | "11011" => + --{{{ + -- Absolute Y + LCycle <= "100"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + Set_BusA_To <= "011"; -- Y + BAAdd <= "10"; -- BA Add + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 3 => + BAAdd <= "11"; -- BA adj + if IR(7 downto 5) = "100" then + Write <= '1'; + else + BreakAtNA <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 4 => + when others => + end case; + --}}} + + when "11100" | "11101" | "11110" | "11111" => + --{{{ + -- Absolute X + + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + -- Read-Modify-Write + LCycle <= "110"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + Set_BusA_To <= "010"; -- X + BAAdd <= "10"; -- BA Add + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 3 => + BAAdd <= "11"; -- BA adj + Set_Addr_To <= "11"; -- BA + when 4 => + LDDI <= '1'; + Write <= '1'; + Set_Addr_To <= "11"; -- BA + when 5 => + LDALU <= '1'; + SaveP <= '1'; + Write <= '1'; + Set_Addr_To <= "11"; -- BA + when 6 => + when others => + end case; + else + LCycle <= "100"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + -- mikej + -- special case 0xBE which uses Y reg as index!! + if (IR = "10111110") then + Set_BusA_To <= "011"; -- Y + else + Set_BusA_To <= "010"; -- X + end if; + BAAdd <= "10"; -- BA Add + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 3 => + BAAdd <= "11"; -- BA adj + if IR(7 downto 5) = "100" then + Write <= '1'; + else + BreakAtNA <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 4 => + when others => + end case; + end if; + --}}} + when others => + end case; + end process; + + process (IR, MCycle) + begin + -- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC + -- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC + case IR(1 downto 0) is + when "00" => + --{{{ + case IR(4 downto 2) is + when "000" | "001" | "011" => + case IR(7 downto 5) is + when "110" | "111" => + -- CP + ALU_Op <= "0110"; + when "101" => + -- LD + ALU_Op <= "0101"; + when "001" => + -- BIT + ALU_Op <= "1100"; + when others => + -- NOP/ST + ALU_Op <= "0100"; + end case; + when "010" => + case IR(7 downto 5) is + when "111" | "110" => + -- IN + ALU_Op <= "1111"; + when "100" => + -- DEY + ALU_Op <= "1110"; + when others => + -- LD + ALU_Op <= "1101"; + end case; + when "110" => + case IR(7 downto 5) is + when "100" => + -- TYA + ALU_Op <= "1101"; + when others => + ALU_Op <= "----"; + end case; + when others => + case IR(7 downto 5) is + when "101" => + -- LD + ALU_Op <= "1101"; + when others => + ALU_Op <= "0100"; + end case; + end case; + --}}} + when "01" => -- OR + --{{{ + ALU_Op(3) <= '0'; + ALU_Op(2 downto 0) <= IR(7 downto 5); + --}}} + when "10" => + --{{{ + ALU_Op(3) <= '1'; + ALU_Op(2 downto 0) <= IR(7 downto 5); + case IR(7 downto 5) is + when "000" => + if IR(4 downto 2) = "110" then + -- INC + ALU_Op <= "1111"; + end if; + when "001" => + if IR(4 downto 2) = "110" then + -- DEC + ALU_Op <= "1110"; + end if; + when "100" => + if IR(4 downto 2) = "010" then + -- TXA + ALU_Op <= "0101"; + else + ALU_Op <= "0100"; + end if; + when others => + end case; + --}}} + when others => + --{{{ + case IR(7 downto 5) is + when "100" => + ALU_Op <= "0100"; + when others => + if MCycle = "000" then + ALU_Op(3) <= '0'; + ALU_Op(2 downto 0) <= IR(7 downto 5); + else + ALU_Op(3) <= '1'; + ALU_Op(2 downto 0) <= IR(7 downto 5); + end if; + end case; + --}}} + end case; + end process; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T65/T65_Pack.vhd b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T65/T65_Pack.vhd new file mode 100644 index 00000000..e025e1bf --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T65/T65_Pack.vhd @@ -0,0 +1,117 @@ +-- **** +-- T65(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 Bugfixes by ehenciak added +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- 65xx compatible microprocessor core +-- +-- Version : 0246 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t65/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T65_Pack is + + constant Flag_C : integer := 0; + constant Flag_Z : integer := 1; + constant Flag_I : integer := 2; + constant Flag_D : integer := 3; + constant Flag_B : integer := 4; + constant Flag_1 : integer := 5; + constant Flag_V : integer := 6; + constant Flag_N : integer := 7; + + component T65_MCode + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816 + IR : in std_logic_vector(7 downto 0); + MCycle : in std_logic_vector(2 downto 0); + P : in std_logic_vector(7 downto 0); + LCycle : out std_logic_vector(2 downto 0); + ALU_Op : out std_logic_vector(3 downto 0); + Set_BusA_To : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P + Set_Addr_To : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA + Write_Data : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH + Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel + BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj + BreakAtNA : out std_logic; + ADAdd : out std_logic; + AddY : out std_logic; + PCAdd : out std_logic; + Inc_S : out std_logic; + Dec_S : out std_logic; + LDA : out std_logic; + LDP : out std_logic; + LDX : out std_logic; + LDY : out std_logic; + LDS : out std_logic; + LDDI : out std_logic; + LDALU : out std_logic; + LDAD : out std_logic; + LDBAL : out std_logic; + LDBAH : out std_logic; + SaveP : out std_logic; + Write : out std_logic + ); + end component; + + component T65_ALU + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816 + Op : in std_logic_vector(3 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + P_In : in std_logic_vector(7 downto 0); + P_Out : out std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T80/T80.vhd new file mode 100644 index 00000000..398fa0df --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T80/T80.vhd @@ -0,0 +1,1073 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 and Auto_Wait_t1 = '0' then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if T_Res = '1' then + Auto_Wait_t1 <= '0'; + else + Auto_Wait_t1 <= Auto_Wait or IORQ_i; + end if; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if (Auto_Wait = '1' and Auto_Wait_t2 = '0') nor + (IOWait = 1 and IORQ_i = '1' and Auto_Wait_t1 = '0') then + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T80/T80_ALU.vhd new file mode 100644 index 00000000..86fddce7 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T80/T80_ALU.vhd @@ -0,0 +1,351 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + OverFlow_v <= Carry_v xor Carry7_v; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T80/T80_MCode.vhd new file mode 100644 index 00000000..4cc30f35 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T80/T80_MCode.vhd @@ -0,0 +1,1934 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; +-- constant aNone : std_logic_vector(2 downto 0) := "000"; +-- constant aXY : std_logic_vector(2 downto 0) := "001"; +-- constant aIOA : std_logic_vector(2 downto 0) := "010"; +-- constant aSP : std_logic_vector(2 downto 0) := "011"; +-- constant aBC : std_logic_vector(2 downto 0) := "100"; +-- constant aDE : std_logic_vector(2 downto 0) := "101"; +-- constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0010"; + else + IncDec_16 <= "1010"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0010"; + else + IncDec_16 <= "1010"; + end if; + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T80/T80_Pack.vhd new file mode 100644 index 00000000..ac7d34da --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T80/T80_Pack.vhd @@ -0,0 +1,208 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T80/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T80/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T80/T80s.vhd b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T80/T80s.vhd new file mode 100644 index 00000000..5b612110 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T80/T80s.vhd @@ -0,0 +1,190 @@ +-- +-- Z80 compatible microprocessor core, synchronous top level +-- Different timing than the original z80 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed read with wait +-- +-- 0211 : Fixed interrupt cycle +-- +-- 0235 : Updated for T80 interface change +-- +-- 0236 : Added T2Write generic +-- +-- 0237 : Fixed T2Write with wait state +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80s is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2 + IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80s; + +architecture rtl of T80s is + + signal CEN : std_logic; + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + CEN <= '1'; + + u0 : T80 + generic map( + Mode => Mode, + IOWait => IOWait) + port map( + CEN => CEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if T2Write = 0 then + if TState = "010" and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + else + if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end process; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/YM2149_linmix_sep.vhd b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/YM2149_linmix_sep.vhd new file mode 100644 index 00000000..6ed2498a --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/YM2149_linmix_sep.vhd @@ -0,0 +1,574 @@ +-- changes for seperate audio outputs and enable now enables cpu access as well +-- +-- A simulation model of YM2149 (AY-3-8910 with bells on) + +-- Copyright (c) MikeJ - Jan 2005 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- +-- Clues from MAME sound driver and Kazuhiro TSUJIKAWA +-- +-- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V) +-- vol 15 .. 0 +-- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132 +-- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order +-- to produced all the required values. +-- (The first part of the curve is a bit steeper and the last bit is more linear than expected) +-- +-- NOTE, this component uses LINEAR mixing of the three analogue channels, and is only +-- accurate for designs where the outputs are buffered and not simply wired together. +-- The ouput level is more complex in that case and requires a larger table. + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity YM2149 is + port ( + -- data bus + I_DA : in std_logic_vector(7 downto 0); + O_DA : out std_logic_vector(7 downto 0); + O_DA_OE_L : out std_logic; + -- control + I_A9_L : in std_logic; + I_A8 : in std_logic; + I_BDIR : in std_logic; + I_BC2 : in std_logic; + I_BC1 : in std_logic; + I_SEL_L : in std_logic; + + O_AUDIO : out std_logic_vector(7 downto 0); + O_CHAN : out std_logic_vector(1 downto 0); + -- port a + I_IOA : in std_logic_vector(7 downto 0); + O_IOA : out std_logic_vector(7 downto 0); + O_IOA_OE_L : out std_logic; + -- port b + I_IOB : in std_logic_vector(7 downto 0); + O_IOB : out std_logic_vector(7 downto 0); + O_IOB_OE_L : out std_logic; + + ENA : in std_logic; -- clock enable for higher speed operation + RESET_L : in std_logic; + CLK : in std_logic -- note 6 Mhz + ); +end; + +architecture RTL of YM2149 is + type array_16x8 is array (0 to 15) of std_logic_vector( 7 downto 0); + type array_3x12 is array (1 to 3) of std_logic_vector(11 downto 0); + + signal cnt_div : std_logic_vector(3 downto 0) := (others => '0'); + signal cnt_div_t1 : std_logic_vector(3 downto 0); + signal noise_div : std_logic := '0'; + signal ena_div : std_logic; + signal ena_div_noise : std_logic; + signal poly17 : std_logic_vector(16 downto 0) := (others => '0'); + + -- registers + signal addr : std_logic_vector(7 downto 0); + signal busctrl_addr : std_logic; + signal busctrl_we : std_logic; + signal busctrl_re : std_logic; + + signal reg : array_16x8; + signal env_reset : std_logic; + signal ioa_inreg : std_logic_vector(7 downto 0); + signal iob_inreg : std_logic_vector(7 downto 0); + + signal noise_gen_cnt : std_logic_vector(4 downto 0); + signal noise_gen_op : std_logic; + signal tone_gen_cnt : array_3x12 := (others => (others => '0')); + signal tone_gen_op : std_logic_vector(3 downto 1) := "000"; + + signal env_gen_cnt : std_logic_vector(15 downto 0); + signal env_ena : std_logic; + signal env_hold : std_logic; + signal env_inc : std_logic; + signal env_vol : std_logic_vector(4 downto 0); + + signal tone_ena_l : std_logic; + signal tone_src : std_logic; + signal noise_ena_l : std_logic; + signal chan_vol : std_logic_vector(4 downto 0); + + signal dac_amp : std_logic_vector(7 downto 0); +begin + -- cpu i/f + p_busdecode : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8) + variable cs : std_logic; + variable sel : std_logic_vector(2 downto 0); + begin + -- BDIR BC2 BC1 MODE + -- 0 0 0 inactive + -- 0 0 1 address + -- 0 1 0 inactive + -- 0 1 1 read + -- 1 0 0 address + -- 1 0 1 inactive + -- 1 1 0 write + -- 1 1 1 read + busctrl_addr <= '0'; + busctrl_we <= '0'; + busctrl_re <= '0'; + + cs := '0'; + if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then + cs := '1'; + end if; + + sel := (I_BDIR & I_BC2 & I_BC1); + case sel is + when "000" => null; + when "001" => busctrl_addr <= '1'; + when "010" => null; + when "011" => busctrl_re <= cs; + when "100" => busctrl_addr <= '1'; + when "101" => null; + when "110" => busctrl_we <= cs; + when "111" => busctrl_addr <= '1'; + when others => null; + end case; + end process; + + p_oe : process(busctrl_re) + begin + -- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns + O_DA_OE_L <= not (busctrl_re); + end process; + + -- + -- CLOCKED + -- + p_waddr : process(RESET_L, CLK) + begin + -- looks like registers are latches in real chip, but the address is caught at the end of the address state. + if (RESET_L = '0') then + addr <= (others => '0'); + elsif rising_edge(CLK) then + if (ENA = '1') then + if (busctrl_addr = '1') then + addr <= I_DA; + end if; + end if; + end if; + end process; + + p_wdata : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + reg <= (others => (others => '0')); + env_reset <= '1'; + elsif rising_edge(CLK) then + if (ENA = '1') then + env_reset <= '0'; + if (busctrl_we = '1') then + case addr(3 downto 0) is + when x"0" => reg(0) <= I_DA; + when x"1" => reg(1) <= I_DA; + when x"2" => reg(2) <= I_DA; + when x"3" => reg(3) <= I_DA; + when x"4" => reg(4) <= I_DA; + when x"5" => reg(5) <= I_DA; + when x"6" => reg(6) <= I_DA; + when x"7" => reg(7) <= I_DA; + when x"8" => reg(8) <= I_DA; + when x"9" => reg(9) <= I_DA; + when x"A" => reg(10) <= I_DA; + when x"B" => reg(11) <= I_DA; + when x"C" => reg(12) <= I_DA; + when x"D" => reg(13) <= I_DA; env_reset <= '1'; + when x"E" => reg(14) <= I_DA; + when x"F" => reg(15) <= I_DA; + when others => null; + end case; + end if; + end if; + end if; + end process; + + p_rdata : process(busctrl_re, addr, reg, ioa_inreg, iob_inreg) + begin + O_DA <= (others => '0'); -- 'X' + if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator + case addr(3 downto 0) is + when x"0" => O_DA <= reg(0) ; + when x"1" => O_DA <= "0000" & reg(1)(3 downto 0) ; + when x"2" => O_DA <= reg(2) ; + when x"3" => O_DA <= "0000" & reg(3)(3 downto 0) ; + when x"4" => O_DA <= reg(4) ; + when x"5" => O_DA <= "0000" & reg(5)(3 downto 0) ; + when x"6" => O_DA <= "000" & reg(6)(4 downto 0) ; + when x"7" => O_DA <= reg(7) ; + when x"8" => O_DA <= "000" & reg(8)(4 downto 0) ; + when x"9" => O_DA <= "000" & reg(9)(4 downto 0) ; + when x"A" => O_DA <= "000" & reg(10)(4 downto 0) ; + when x"B" => O_DA <= reg(11); + when x"C" => O_DA <= reg(12); + when x"D" => O_DA <= "0000" & reg(13)(3 downto 0); + when x"E" => if (reg(7)(6) = '0') then -- input + O_DA <= ioa_inreg; + else + O_DA <= reg(14); -- read output reg + end if; + when x"F" => if (Reg(7)(7) = '0') then + O_DA <= iob_inreg; + else + O_DA <= reg(15); + end if; + when others => null; + end case; + end if; + end process; + -- + p_divider : process + begin + wait until rising_edge(CLK); + -- / 8 when SEL is high and /16 when SEL is low + if (ENA = '1') then + ena_div <= '0'; + ena_div_noise <= '0'; + if (cnt_div = "0000") then + cnt_div <= (not I_SEL_L) & "111"; + ena_div <= '1'; + + noise_div <= not noise_div; + if (noise_div = '1') then + ena_div_noise <= '1'; + end if; + else + cnt_div <= cnt_div - "1"; + end if; + end if; + end process; + + p_noise_gen : process + variable noise_gen_comp : std_logic_vector(4 downto 0); + variable poly17_zero : std_logic; + begin + wait until rising_edge(CLK); + if (reg(6)(4 downto 0) = "00000") then + noise_gen_comp := "00000"; + else + noise_gen_comp := (reg(6)(4 downto 0) - "1"); + end if; + + poly17_zero := '0'; + if (poly17 = "00000000000000000") then poly17_zero := '1'; end if; + + if (ENA = '1') then + if (ena_div_noise = '1') then -- divider ena + + if (noise_gen_cnt >= noise_gen_comp) then + noise_gen_cnt <= "00000"; + poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1); + else + noise_gen_cnt <= (noise_gen_cnt + "1"); + end if; + end if; + end if; + end process; + noise_gen_op <= poly17(0); + + p_tone_gens : process + variable tone_gen_freq : array_3x12; + variable tone_gen_comp : array_3x12; + begin + wait until rising_edge(CLK); + -- looks like real chips count up - we need to get the Exact behaviour .. + tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0); + tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2); + tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4); + -- period 0 = period 1 + for i in 1 to 3 loop + if (tone_gen_freq(i) = x"000") then + tone_gen_comp(i) := x"000"; + else + tone_gen_comp(i) := (tone_gen_freq(i) - "1"); + end if; + end loop; + + if (ENA = '1') then + for i in 1 to 3 loop + if (ena_div = '1') then -- divider ena + + if (tone_gen_cnt(i) >= tone_gen_comp(i)) then + tone_gen_cnt(i) <= x"000"; + tone_gen_op(i) <= not tone_gen_op(i); + else + tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1"); + end if; + end if; + end loop; + end if; + end process; + + p_envelope_freq : process + variable env_gen_freq : std_logic_vector(15 downto 0); + variable env_gen_comp : std_logic_vector(15 downto 0); + begin + wait until rising_edge(CLK); + env_gen_freq := reg(12) & reg(11); + -- envelope freqs 1 and 0 are the same. + if (env_gen_freq = x"0000") then + env_gen_comp := x"0000"; + else + env_gen_comp := (env_gen_freq - "1"); + end if; + + if (ENA = '1') then + env_ena <= '0'; + if (ena_div = '1') then -- divider ena + if (env_gen_cnt >= env_gen_comp) then + env_gen_cnt <= x"0000"; + env_ena <= '1'; + else + env_gen_cnt <= (env_gen_cnt + "1"); + end if; + end if; + end if; + end process; + + p_envelope_shape : process(env_reset, reg, CLK) + variable is_bot : boolean; + variable is_bot_p1 : boolean; + variable is_top_m1 : boolean; + variable is_top : boolean; + begin + -- envelope shapes + -- C AtAlH + -- 0 0 x x \___ + -- + -- 0 1 x x /___ + -- + -- 1 0 0 0 \\\\ + -- + -- 1 0 0 1 \___ + -- + -- 1 0 1 0 \/\/ + -- ___ + -- 1 0 1 1 \ + -- + -- 1 1 0 0 //// + -- ___ + -- 1 1 0 1 / + -- + -- 1 1 1 0 /\/\ + -- + -- 1 1 1 1 /___ + if (env_reset = '1') then + -- load initial state + if (reg(13)(2) = '0') then -- attack + env_vol <= "11111"; + env_inc <= '0'; -- -1 + else + env_vol <= "00000"; + env_inc <= '1'; -- +1 + end if; + env_hold <= '0'; + + elsif rising_edge(CLK) then + is_bot := (env_vol = "00000"); + is_bot_p1 := (env_vol = "00001"); + is_top_m1 := (env_vol = "11110"); + is_top := (env_vol = "11111"); + + if (ENA = '1') then + if (env_ena = '1') then + if (env_hold = '0') then + if (env_inc = '1') then + env_vol <= (env_vol + "00001"); + else + env_vol <= (env_vol + "11111"); + end if; + end if; + + -- envelope shape control. + if (reg(13)(3) = '0') then + if (env_inc = '0') then -- down + if is_bot_p1 then env_hold <= '1'; end if; + else + if is_top then env_hold <= '1'; end if; + end if; + else + if (reg(13)(0) = '1') then -- hold = 1 + if (env_inc = '0') then -- down + if (reg(13)(1) = '1') then -- alt + if is_bot then env_hold <= '1'; end if; + else + if is_bot_p1 then env_hold <= '1'; end if; + end if; + else + if (reg(13)(1) = '1') then -- alt + if is_top then env_hold <= '1'; end if; + else + if is_top_m1 then env_hold <= '1'; end if; + end if; + end if; + + elsif (reg(13)(1) = '1') then -- alternate + if (env_inc = '0') then -- down + if is_bot_p1 then env_hold <= '1'; end if; + if is_bot then env_hold <= '0'; env_inc <= '1'; end if; + else + if is_top_m1 then env_hold <= '1'; end if; + if is_top then env_hold <= '0'; env_inc <= '0'; end if; + end if; + end if; + + end if; + end if; + end if; + end if; + end process; + + p_chan_mixer : process(cnt_div, reg, tone_gen_op) + begin + tone_ena_l <= '1'; tone_src <= '1'; + noise_ena_l <= '1'; chan_vol <= "00000"; + case cnt_div(1 downto 0) is + when "00" => + tone_ena_l <= reg(7)(0); tone_src <= tone_gen_op(1); chan_vol <= reg(8)(4 downto 0); + noise_ena_l <= reg(7)(3); + when "01" => + tone_ena_l <= reg(7)(1); tone_src <= tone_gen_op(2); chan_vol <= reg(9)(4 downto 0); + noise_ena_l <= reg(7)(4); + when "10" => + tone_ena_l <= reg(7)(2); tone_src <= tone_gen_op(3); chan_vol <= reg(10)(4 downto 0); + noise_ena_l <= reg(7)(5); + when "11" => null; -- tone gen outputs become valid on this clock + when others => null; + end case; + end process; + + p_op_mixer : process + variable chan_mixed : std_logic; + variable chan_amp : std_logic_vector(4 downto 0); + begin + wait until rising_edge(CLK); + if (ENA = '1') then + + chan_mixed := (tone_ena_l or tone_src) and (noise_ena_l or noise_gen_op); + + chan_amp := (others => '0'); + if (chan_mixed = '1') then + if (chan_vol(4) = '0') then + if (chan_vol(3 downto 0) = "0000") then -- nothing is easy ! make sure quiet is quiet + chan_amp := "00000"; + else + chan_amp := chan_vol(3 downto 0) & '1'; -- make sure level 31 (env) = level 15 (tone) + end if; + else + chan_amp := env_vol(4 downto 0); + end if; + end if; + + dac_amp <= x"00"; + case chan_amp is + when "11111" => dac_amp <= x"FF"; + when "11110" => dac_amp <= x"D9"; + when "11101" => dac_amp <= x"BA"; + when "11100" => dac_amp <= x"9F"; + when "11011" => dac_amp <= x"88"; + when "11010" => dac_amp <= x"74"; + when "11001" => dac_amp <= x"63"; + when "11000" => dac_amp <= x"54"; + when "10111" => dac_amp <= x"48"; + when "10110" => dac_amp <= x"3D"; + when "10101" => dac_amp <= x"34"; + when "10100" => dac_amp <= x"2C"; + when "10011" => dac_amp <= x"25"; + when "10010" => dac_amp <= x"1F"; + when "10001" => dac_amp <= x"1A"; + when "10000" => dac_amp <= x"16"; + when "01111" => dac_amp <= x"13"; + when "01110" => dac_amp <= x"10"; + when "01101" => dac_amp <= x"0D"; + when "01100" => dac_amp <= x"0B"; + when "01011" => dac_amp <= x"09"; + when "01010" => dac_amp <= x"08"; + when "01001" => dac_amp <= x"07"; + when "01000" => dac_amp <= x"06"; + when "00111" => dac_amp <= x"05"; + when "00110" => dac_amp <= x"04"; + when "00101" => dac_amp <= x"03"; + when "00100" => dac_amp <= x"03"; + when "00011" => dac_amp <= x"02"; + when "00010" => dac_amp <= x"02"; + when "00001" => dac_amp <= x"01"; + when "00000" => dac_amp <= x"00"; + when others => null; + end case; + + cnt_div_t1 <= cnt_div; + end if; + end process; + + p_audio_output : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + O_AUDIO <= (others => '0'); + O_CHAN <= (others => '0'); + elsif rising_edge(CLK) then + + if (ENA = '1') then + O_AUDIO <= dac_amp(7 downto 0); + O_CHAN <= cnt_div_t1(1 downto 0); + end if; + end if; + end process; + + p_io_ports : process(reg) + begin + O_IOA <= reg(14); + O_IOA_OE_L <= not reg(7)(6); + O_IOB <= reg(15); + O_IOB_OE_L <= not reg(7)(7); + end process; + + p_io_ports_inreg : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then -- resync + ioa_inreg <= I_IOA; + iob_inreg <= I_IOB; + end if; + end process; +end architecture RTL; diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/build_id.tcl b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/cmd_hvgen.v b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/cmd_hvgen.v new file mode 100644 index 00000000..f4812295 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/cmd_hvgen.v @@ -0,0 +1,36 @@ +module cmd_hvgen +( + output [8:0] HPOS, + output [8:0] VPOS, + input PCLK, + output reg HBLK = 1, + output reg VBLK = 1, + output reg HSYN = 1, + output reg VSYN = 1 +); + +reg [8:0] hcnt = 0; +reg [8:0] vcnt = 0; + +assign HPOS = hcnt; +assign VPOS = vcnt; + +always @(posedge PCLK) begin + case (hcnt) + 287: begin HBLK <= 1; HSYN <= 0; hcnt <= hcnt+1; end + 311: begin HSYN <= 1; hcnt <= hcnt+1; end + 383: begin + HBLK <= 0; HSYN <= 1; hcnt <= 0; + case (vcnt) + 223: begin VBLK <= 1; vcnt <= vcnt+1; end + 226: begin VSYN <= 0; vcnt <= vcnt+1; end + 233: begin VSYN <= 1; vcnt <= vcnt+1; end + 242: begin VBLK <= 0; vcnt <= 0; end + default: vcnt <= vcnt+1; + endcase + end + default: hcnt <= hcnt+1; + endcase +end + +endmodule \ No newline at end of file diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/cmd_sound.vhd b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/cmd_sound.vhd new file mode 100644 index 00000000..2207d673 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/cmd_sound.vhd @@ -0,0 +1,425 @@ +--------------------------------------------------------------------------------- +-- burnin rubber sound by Dar (darfpga@aol.fr) (05/12/2017) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- +-- gen_ram.vhd & io_ps2_keyboard +-------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +--------------------------------------------------------------------------------- +-- T65(b) core.Ver 301 by MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +--------------------------------------------------------------------------------- +-- YM2149 (AY-3-8910) +-- Copyright (c) MikeJ - Jan 2005 +--------------------------------------------------------------------------------- +-- Use burnin_rubber_de10_lite.sdc to compile (Timequest constraints) +-- /!\ +-- Don't forget to set device configuration mode with memory initialization +-- (Assignments/Device/Pin options/Configuration mode) +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity cmd_sound is +port +( + clock_12 : in std_logic; + reset : in std_logic; + + sound_req : in std_logic; + sound_code_in : in std_logic_vector(7 downto 0); + sound_timing : in std_logic; + + audio_out : out std_logic_vector(10 downto 0); + + dbg_cpu_addr: out std_logic_vector(15 downto 0) + ); +end cmd_sound; + +architecture syn of cmd_sound is + + -- clocks, reset + signal clock_12n : std_logic; + signal clock_div1 : std_logic_vector(8 downto 0) := (others =>'0'); + signal clock_div2 : std_logic_vector(4 downto 0) := (others =>'0'); + signal clock_500K : std_logic; + signal ayx_clock : std_logic; + signal reset_n : std_logic; + + -- cpu signals + signal cpu_addr : std_logic_vector(23 downto 0); + signal cpu_di : std_logic_vector( 7 downto 0); + signal cpu_di_dec : std_logic_vector( 7 downto 0); + signal cpu_do : std_logic_vector( 7 downto 0); + signal cpu_rw_n : std_logic; + signal cpu_nmi_n : std_logic; + signal cpu_irq_n : std_logic; + signal cpu_sync : std_logic; + + -- program rom signals + signal prog_rom_cs : std_logic; + signal prog_rom_do : std_logic_vector(7 downto 0); + + -- working ram signals + signal wram_cs : std_logic; + signal wram_we : std_logic; + signal wram_do : std_logic_vector(7 downto 0); + + -- sound req management + signal nmi_reg : std_logic; + signal nmi_reg_cs : std_logic; + signal nmi_reg_we : std_logic; + signal sound_code : std_logic_vector(7 downto 0); + signal sound_code_cs : std_logic; + + -- ay-3-8910 signal + signal ay1_bc1 : std_logic; + signal ay1_bdir : std_logic; + signal ay1_audio_chan : std_logic_vector(1 downto 0); + signal ay1_audio_muxed: std_logic_vector(7 downto 0); + signal ay1_chan_a: std_logic_vector(7 downto 0); + signal ay1_chan_b: std_logic_vector(7 downto 0); + signal ay1_chan_c: std_logic_vector(7 downto 0); + + signal ay2_bc1 : std_logic; + signal ay2_bdir : std_logic; + signal ay2_audio_chan : std_logic_vector(1 downto 0); + signal ay2_audio_muxed: std_logic_vector(7 downto 0); + signal ay2_chan_a: std_logic_vector(7 downto 0); + signal ay2_chan_b: std_logic_vector(7 downto 0); + signal ay2_chan_c: std_logic_vector(7 downto 0); + + -- digital filtering AY2 channel A + signal uin : integer range -256 to 255; + signal u3 : integer range -32768 to 32767; + signal u4 : integer range -32768 to 32767; + signal du3 : integer range -32768*4096 to 32767*4096; + signal du4 : integer range -32768*4096 to 32767*4096; + signal uout : integer range -32768 to 32767; + signal uout_lim : integer range -128 to 127; + +begin + +process (clock_12, cpu_sync) +begin + if rising_edge(clock_12) then + if cpu_sync = '1' then + dbg_cpu_addr <= cpu_addr(15 downto 0); + end if; + end if; +end process; + +reset_n <= not reset; +clock_12n <= not clock_12; + +process (clock_12, reset) + begin + if reset='1' then + clock_div1 <= (others => '0'); + clock_div2 <= (others => '0'); + else + if rising_edge(clock_12) then + if clock_div1 = "111111111" then -- divide by 512 (23.437kHz) + clock_div1 <= "000000000"; + else + clock_div1 <= clock_div1 + '1'; + end if; + if clock_div2 = "10111" then -- divide by 24 + clock_div2 <= "00000"; + else + clock_div2 <= clock_div2 + '1'; + end if; + end if; + end if; +end process; + +clock_500K <= clock_div2(4); --12MHz/24 = 500kHz +ayx_clock <= clock_div1(2); --12MHz/8 = 1.5MHz + +--static ADDRESS_MAP_START( audio_map, AS_PROGRAM, 8, btime_state ) +-- AM_RANGE(0x0000, 0x03ff) AM_MIRROR(0x1c00) AM_RAM AM_SHARE("audio_rambase") +-- AM_RANGE(0x2000, 0x3fff) AM_DEVWRITE("ay1", ay8910_device, data_w) +-- AM_RANGE(0x4000, 0x5fff) AM_DEVWRITE("ay1", ay8910_device, address_w) +-- AM_RANGE(0x6000, 0x7fff) AM_DEVWRITE("ay2", ay8910_device, data_w) +-- AM_RANGE(0x8000, 0x9fff) AM_DEVWRITE("ay2", ay8910_device, address_w) +-- AM_RANGE(0xa000, 0xbfff) AM_READ(audio_command_r) +-- AM_RANGE(0xc000, 0xdfff) AM_WRITE(audio_nmi_enable_w) +-- AM_RANGE(0xe000, 0xefff) AM_MIRROR(0x1000) AM_ROM +--ADDRESS_MAP_END + +-- chip select +wram_cs <= '1' when cpu_addr(15 downto 13) = "000" else '0'; -- working ram 0000-07ff .. 1fff +ay1_bc1 <= '1' when cpu_addr(15 downto 13) = "010" else '0'; +ay1_bdir <= '1' when cpu_addr(15 downto 13) = "001" or ay1_bc1 = '1' else '0'; +ay2_bc1 <= '1' when cpu_addr(15 downto 13) = "100" else '0'; +ay2_bdir <= '1' when cpu_addr(15 downto 13) = "011" or ay2_bc1 = '1' else '0'; +sound_code_cs <= '1' when cpu_addr(15 downto 13) = "101" else '0'; +nmi_reg_cs <= '1' when cpu_addr(15 downto 13) = "110" else '0'; +prog_rom_cs <= '1' when cpu_addr(15 downto 13) = "111" else '0'; + +-- write enable +wram_we <= '1' when wram_cs = '1' and cpu_rw_n = '0' else '0'; +nmi_reg_we <= '1' when nmi_reg_cs = '1' and cpu_rw_n = '0' else '0'; + +-- cpu di mux +cpu_di <= wram_do when wram_cs = '1' else + prog_rom_do when prog_rom_cs = '1' else + sound_code when sound_code_cs = '1' else + X"FF"; + +-- regsiter sound code and irq management +process (clock_12) +begin + if rising_edge(clock_12) then + if sound_req = '1' then + sound_code <= sound_code_in; + cpu_irq_n <= '0'; + end if; + if sound_code_cs = '1' then + cpu_irq_n <= '1'; + end if; + end if; +end process; + +-- nmi autorisation management +process (reset, clock_12) +begin + if reset = '1' then + nmi_reg <= '0'; + else + if rising_edge(clock_12) then + if nmi_reg_we = '1' then + nmi_reg <= cpu_do(0); + end if; + end if; + end if; +end process; + +-- nmi +cpu_nmi_n <= '0' when nmi_reg = '1' and sound_timing = '1' else '1'; + +-- demux AY chips output +process (ayx_clock) +begin + if rising_edge(ayx_clock) then + if ay1_audio_chan = "00" then ay1_chan_a <= ay1_audio_muxed; end if; + if ay1_audio_chan = "01" then ay1_chan_b <= ay1_audio_muxed; end if; + if ay1_audio_chan = "10" then ay1_chan_c <= ay1_audio_muxed; end if; + if ay2_audio_chan = "00" then ay2_chan_a <= ay2_audio_muxed; end if; + if ay2_audio_chan = "01" then ay2_chan_b <= ay2_audio_muxed; end if; + if ay2_audio_chan = "10" then ay2_chan_c <= ay2_audio_muxed; end if; + end if; +end process; + +-- AOP Rauch passe bande filter +-- +-- ----------o------------ +-- u4^ | | | +-- | --- C4 | | R5 | +-- | --- | | | +-- | | C3 | | +-- --| R1 |----o----||---o------|\ | +-- ^ | ------> u3 | \__o--- +-- | | | / ^ +-- |uin | | R2 --|/ | +-- | | | | | uout +-- | | | | +-- ------------o--------------o---------- +-- +-- +-- i1 = (sin+u3)/R1 +-- i2 = -u3/R2 +-- i3 = (u4-u3)/R5 +-- i4 = i2-i1-i3 +-- +-- u3(t+dt) = u3(t) + i3(t)*dt/C3; +-- u4(t+dt) = u4(t) + i4(t)*dt/C4; + +-- uout = u4-u3 + +-- R1 = 5000; +-- R2 = 10000; +-- C3 = 0.068e-6; +-- C4 = 0.068e-6; +-- R5 = 47000; +-- +-- dt = 1/f_ech = 1/23437 +-- dt/C3 = dt/C4 = 627 +-- +-- (i3(t)*dt/C3)*8192 = du3*8192 = ((u4-u3)/47000*627)*8192 +-- = (u4-u3)*109 +-- +-- (i4(t)*dt/C4)*8192 = du4*8192 = (-u3/10000 -(uin+u3)/5000 -(u4-u3)/47000)*627*8192 +-- = -u3(514+1027-109) - uin*1027 - u4*109 +-- = -(u4*109 + u3*1432 + uin*1027) +-- + +-- down sample to 23.437kHz and filter AY2 channel A +uin <= to_integer(unsigned(ay2_chan_a)); + +process (clock_12) +begin + if rising_edge(clock_12) then + + if clock_div1 = "000000000" then + du3 <= u4*109 - u3*109; + du4 <= u4*109 + u3*1432 + uin*1027*16; -- add gain(16) to uin + end if; + + if clock_div1 = "000000001" then + u3 <= u3 + du3/8192; + u4 <= u4 - du4/8192; + end if; + + if clock_div1 = "000000010" then + uout <= (u4 - u3) / 8; -- adjust output gain + end if; + + -- limit signed dynamique before return to unsigned + if clock_div1 = "000000011" then + if uout > 127 then + uout_lim <= 127; + elsif uout < -127 then + uout_lim <= -127; + else + uout_lim <= uout; + end if; + end if; + + if clock_div1 = "000000100" then + + audio_out <= ("000"&ay1_chan_a(7 downto 0)) + + ("000"&ay1_chan_b(7 downto 0)) + + ("000"&ay1_chan_c(7 downto 0)) + + ("000"&std_logic_vector(to_unsigned(uout_lim+128,8)))+ + ("000"&ay2_chan_b(7 downto 0)) + + ("000"&ay2_chan_c(7 downto 0)); + end if; + + end if; +end process; + +--------------------------- +-- components +--------------------------- + +cpu_inst : entity work.T65 +port map +( + Mode => "00", -- 6502 + Res_n => reset_n, + Enable => '1', + Clk => clock_500K, + Rdy => '1', + Abort_n => '1', + IRQ_n => cpu_irq_n, + NMI_n => cpu_nmi_n, + SO_n => '1',--cpu_so_n, + R_W_n => cpu_rw_n, + Sync => cpu_sync, -- open + EF => open, + MF => open, + XF => open, + ML_n => open, + VP_n => open, + VDA => open, + VPA => open, + A => cpu_addr, + DI => cpu_di, + DO => cpu_do +); + +-- working ram +wram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 11) +port map( + clk => clock_12n, + we => wram_we, + addr => cpu_addr(10 downto 0), + d => cpu_do, + q => wram_do +); + +-- program rom +program_rom: entity work.cmd_snd_rom +port map( + clk => clock_12n, + addr => cpu_addr(11 downto 0), + data => prog_rom_do +); + +-- AY-3-8910 #1 +ay_3_8910_1 : entity work.YM2149 +port map( + -- data bus + I_DA => cpu_do, -- in std_logic_vector(7 downto 0); + O_DA => open, -- out std_logic_vector(7 downto 0); + O_DA_OE_L => open, -- out std_logic; + -- control + I_A9_L => '0', -- in std_logic; + I_A8 => '1', -- in std_logic; + I_BDIR => ay1_bdir, -- in std_logic; + I_BC2 => '1', -- in std_logic; + I_BC1 => ay1_bc1, -- in std_logic; + I_SEL_L => '1', -- in std_logic; + + O_AUDIO => ay1_audio_muxed, -- out std_logic_vector(7 downto 0); + O_CHAN => ay1_audio_chan, -- out std_logic_vector(1 downto 0); + + -- port a + I_IOA => X"00", -- in std_logic_vector(7 downto 0); + O_IOA => open, -- out std_logic_vector(7 downto 0); + O_IOA_OE_L => open, -- out std_logic; + -- port b + I_IOB => X"00", -- in std_logic_vector(7 downto 0); + O_IOB => open, -- out std_logic_vector(7 downto 0); + O_IOB_OE_L => open, -- out std_logic; + + ENA => '1', -- in std_logic; -- clock enable for higher speed operation + RESET_L => reset_n, -- in std_logic; + CLK => ayx_clock -- in std_logic -- note 6 Mhz +); + +-- AY-3-8910 #2 +ay_3_8910_2 : entity work.YM2149 +port map( + -- data bus + I_DA => cpu_do, -- in std_logic_vector(7 downto 0); + O_DA => open, -- out std_logic_vector(7 downto 0); + O_DA_OE_L => open, -- out std_logic; + -- control + I_A9_L => '0', -- in std_logic; + I_A8 => '1', -- in std_logic; + I_BDIR => ay2_bdir, -- in std_logic; + I_BC2 => '1', -- in std_logic; + I_BC1 => ay2_bc1, -- in std_logic; + I_SEL_L => '1', -- in std_logic; + + O_AUDIO => ay2_audio_muxed, -- out std_logic_vector(7 downto 0); + O_CHAN => ay2_audio_chan, -- out std_logic_vector(1 downto 0); + + -- port a + I_IOA => (others => '0'), -- in std_logic_vector(7 downto 0); + O_IOA => open, -- out std_logic_vector(7 downto 0); + O_IOA_OE_L => open, -- out std_logic; + -- port b + I_IOB => (others => '0'), -- in std_logic_vector(7 downto 0); + O_IOB => open, -- out std_logic_vector(7 downto 0); + O_IOB_OE_L => open, -- out std_logic; + + ENA => '1', --cpu_ena, -- in std_logic; -- clock enable for higher speed operation + RESET_L => reset_n, -- in std_logic; + CLK => ayx_clock -- in std_logic -- note 6 Mhz +); + + +end SYN; diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/cmd_sprite.v b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/cmd_sprite.v new file mode 100644 index 00000000..4e2052c7 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/cmd_sprite.v @@ -0,0 +1,154 @@ + +module cmd_sprite +( + input VCLKx4, + input HBLK, + + input [8:0] HPOS, + input [8:0] VPOS, + + output reg [10:0] SPRAADRS, + input [15:0] SPRADATA, + + output [3:0] ARAMADRS, + input [7:0] ARAMDATA, + + output [11:0] SPCHRADR, + input [7:0] SPCHRDAT, + + output [7:0] DROMAD, + input [7:0] DROMDT, + + output reg [8:0] SPCOL +); + +reg [1:0] clkcnt; +always @( posedge VCLKx4 ) clkcnt<=clkcnt+1; +wire VCLKx2 = clkcnt[0]; +wire VCLK = clkcnt[1]; + +wire SIDE = VPOS[0]; + + +reg [19:0] SPATR0; +reg [36:0] SPATRS[0:31]; +reg [3:0] WWADR; +reg bHit; + +assign ARAMADRS = SPRAADRS[3:0]; + + +reg [7:0] WRADR; +reg [8:0] HPOSW; +reg [8:0] SPWCL; + +wire [36:0] SPA = SPATRS[{~SIDE,WRADR[7:4]}]; + +wire [3:0] SH = WRADR[3:0]+4'h4; +wire [3:0] SV = SPA[35:32]; + +wire [2:0] SPFY = { 3{SPA[1]} }; +wire [1:0] SPFX = { 1'b0, SPA[0] }; +wire [5:0] SPPL = SPA[29:24]; + +assign SPCHRADR = { SPA[7:2], ( SV[3] ^ SPA[1] ), ( SH[3:2] ^ SPFX ), ( SV[2:0] ^ SPFY ) }; +wire [7:0] CHRO = SPCHRDAT; + + +wire [8:0] YM = ( SPRADATA[15:8] + 8'h10 ) + VPOS[7:0]; + +assign DROMAD = { 1'b0, (~SPA[19:17]), SPA[33:32], WRADR[3:2] }; + +always @ ( posedge VCLKx2 ) begin + + // in H-BLANK + if ( HBLK ) begin + + // Sprite V-hit check & list-up + if ( SPRAADRS < 10'h20 ) begin + if ( SPRAADRS[0] ) begin + if ( bHit ) begin + SPATRS[{SIDE,WWADR}] <= { 1'b1, SPATR0[3:0], SPRADATA, SPATR0[19:4] }; + WWADR <= WWADR+1; + end + end + else begin + if ( YM[7:4] == 4'b1111 ) begin + bHit <= 1; + SPATR0 <= { SPRADATA, YM[3:0] }; + end + else bHit <= 0; + end + SPRAADRS <= ( SPRAADRS == 10'h1F ) ? 10'h34 : (SPRAADRS+1); + end + // Rader-dot V-hit check & list-up + else begin + if ( SPRAADRS < 10'h40 ) begin + if ( YM[7:2] == 6'b111111 ) begin + SPATRS[{SIDE,WWADR}] <= { 1'b0, 2'b00, YM[1:0], 8'h0, ARAMDATA, SPRADATA }; + WWADR <= WWADR+1; + end + SPRAADRS <= SPRAADRS+1; + end + else SPATRS[{SIDE,WWADR}] <= 0; + end + + if ( SPA ) begin + // Rend Sprite + if ( SPA[36] ) begin + HPOSW <= ( WRADR[3:0] ) ? (HPOSW+1) : { SPA[31], SPA[23:16] }; + case ( SH[1:0] ^ {2{SPFX[0]}} ) + 2'b00: SPWCL <= { 1'b0, SPPL, CHRO[7], CHRO[3] }; + 2'b01: SPWCL <= { 1'b0, SPPL, CHRO[6], CHRO[2] }; + 2'b10: SPWCL <= { 1'b0, SPPL, CHRO[5], CHRO[1] }; + 2'b11: SPWCL <= { 1'b0, SPPL, CHRO[4], CHRO[0] }; + endcase + WRADR <= WRADR+1; + end + // Rend Rader-dot + else begin + HPOSW <= ( WRADR[3:0] ) ? (HPOSW+1) : ({ (~SPA[16]), SPA[7:0] }); + SPWCL <= ( DROMDT[1:0] != 2'b11 ) ? { 1'b1, 6'b000100, DROMDT[1:0] } : 0; + WRADR <= WRADR+4; + end + end + else SPWCL <= 0; + + end + + // in H-DISP + else begin + SPRAADRS <= 10'h14; + WWADR <= 0; + WRADR <= 0; + SPWCL <= 0; + end + +end + + +reg [9:0] radr0=0,radr1=1; +wire [8:0] SPCOLi; +dpram #( + .widthad_a(10), + .width_a(9)) +linebuffer( + .address_a({SIDE,HPOS}), + .address_b({~SIDE,HPOSW}), + .clock_a(VCLKx2), + .clock_b(VCLKx2), + .data_a(9'h0), + .data_b(SPWCL), + .wren_a(radr0==radr1), + .wren_b((SPWCL[0]|SPWCL[1])), + .q_a(SPCOLi), + .q_b() + ); + +always @(posedge VCLK) radr0 <= {SIDE,HPOS}; +always @(negedge VCLK) begin + if (radr0!=radr1) SPCOL <= SPCOLi; + radr1 <= radr0; +end + +endmodule diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/cmd_top.v b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/cmd_top.v new file mode 100644 index 00000000..8890be13 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/cmd_top.v @@ -0,0 +1,195 @@ +/************************************************************** + FPGA Commando (Main part) +***************************************************************/ +module cmd_top +( + input RESET, // RESET + input CLK24M, // Clock 24.576MHz + output hsync, + output vsync, + output hblank, + output vblank, + output [2:0] r, + output [2:0] g, + output [1:0] b, + output [10:0] SND, // Sound (unsigned PCM) + input [7:0] DSW1, // DipSW + input [7:0] DSW2, // DipSW + input [7:0] CTR1, // Controler (Negative logic) + input [7:0] CTR2 +); + + +//-------------------------------------------------- +// Clock Generators +//-------------------------------------------------- +reg [2:0] _CCLK; +always @( posedge CLK24M ) _CCLK <= _CCLK+1; + +wire CLK = CLK24M; // 24MHz +wire CCLKx4 = _CCLK[0]; // CPU CLOCKx4 : 12.0MHz +wire CCLK = _CCLK[2]; // CPU CLOCK : 3.0MHz + + +//-------------------------------------------------- +// CPU +//-------------------------------------------------- +// memory access signals +wire rd, wr, me, ie, rf, m1; +wire [15:0] ad; +wire [7:0] odt, viddata; + +wire mx = rf & (~me); +wire mr = mx & (~rd); +wire mw = mx & (~wr); + +// interrupt signal/vector generator & other latches +reg inte = 1'b0; +reg intl = 1'b0; +reg [7:0] intv = 8'h0; + + +reg out1r = 1'b0; +reg out2r = 1'b0; +reg out3r = 1'b0; +reg sonr = 1'b0;//sound On + +wire vblk = (VP==224)&(HP<=8); + +wire lat_Wce = ( ad[15:4] == 12'hA18 ) & mw; + +wire sndw = ( lat_Wce & ( ad[3:0] == 4'h0 ) ); +wire iewr = ( lat_Wce & ( ad[3:0] == 4'h1 ) ); +wire mute = ( lat_Wce & ( ad[3:0] == 4'h1 ) );//mute +wire flip = ( lat_Wce & ( ad[3:0] == 4'h3 ) );//flip +wire out1w = ( lat_Wce & ( ad[3:0] == 4'h4 ) ); +//wire out2w = ( lat_Wce & ( ad[3:0] == 4'h5 ) );//NOP +wire out3w = ( lat_Wce & ( ad[3:0] == 4'h6 ) ); +//wire starw = ( lat_Wce & ( ad[3:0] == 4'h7 ) );//not used +wire iowr = ( (~wr) & (~ie) & m1 ); + + +always @( posedge CCLK ) begin + if ( iowr ) intv <= odt; + if ( vblk ) intl <= 1'b1; + if ( iewr ) begin + inte <= odt[0]; + intl <= 1'b0; + end + if ( sndw ) sonr <= odt[0]; + if ( out1w ) out1r <= odt[0]; +// if ( out2w ) out2r <= odt[0]; + if ( out3w ) out3r <= odt[0]; +end + +wire irq_n = ~( intl & inte ); + + +// address decoders +wire rom_Rce = ( ( ad[15] == 1'b0 ) & mr ); // $0000-$7FFF(R) +wire ram_Rce = ( ( ad[15:11] == 5'b1001_1 ) & mr ); // $9800-$9FFF(R) +wire ram_Wce = ( ( ad[15:11] == 5'b1001_1 ) & mw ); // $9800-$9FFF(W) +wire inp_Rce = ( ( ad[15:12] == 4'b1010 ) & mr ); // $A000-$AFFF(R) +wire snd_Wce = ( ( ad[15:8] == 8'b1010_0001 ) & mw ); // $A100-$A1FF(W) +wire vid_Rce; + + +wire [7:0] romdata; +cmd_prg_rom cmd_prg_rom ( + .clk(CCLK), + .addr(ad[14:0]), + .data(romdata) + ); + +// Work RAM (2KB) +wire [7:0] ramdata; +GSPRAM #(11,8) workram( + .CL(CCLK), + .AD(ad[10:0]), + .WE(ram_Wce), + .DI(odt), + .DO(ramdata) + ); + + +// Controler/DipSW input +wire [7:0] in0data = CTR1; +wire [7:0] in1data = CTR2; +wire [7:0] in2data = DSW1; +wire [7:0] in3data = DSW2; +wire [7:0] inpdata = (ad[8:7] == 2'b11) ? in3data : (ad[8:7] == 2'b10) ? in2data : (ad[8:7] == 2'b01) ? in1data : in0data; +// databus selector +wire [7:0] romd = rom_Rce ? romdata : 8'h00; +wire [7:0] ramd = ram_Rce ? ramdata : 8'h00; +wire [7:0] vidd = vid_Rce ? viddata : 8'h00; +wire [7:0] inpd = inp_Rce ? inpdata : 8'h00; +wire [7:0] irqv = ( (~m1) & (~ie) ) ? intv : 8'h00; + +wire [7:0] idt = romd | ramd | irqv | vidd | inpd; + + +T80s z80( + .RESET_n(~RESET), + .CLK_n(CCLK), + .WAIT_n(1'b1), + .INT_n(1'b1), + .NMI_n(irq_n), + .BUSRQ_n(1'b1), + .DI(idt), + .M1_n(m1), + .MREQ_n(me), + .IORQ_n(ie), + .RD_n(rd), + .WR_n(wr), + .RFSH_n(rf), + .HALT_n(), + .BUSAK_n(), + .A(ad), + .DO(odt) + ); + +//-------------------------------------------------- +// VIDEO +//-------------------------------------------------- +wire [8:0] HP; +wire [8:0] VP; +wire PCLK; + +cmd_video video( + .VCLKx4(CLK), + .HPOS(HP+3), + .VPOS(VP+1), + .PCLK(PCLK), + .POUT({b,g,r}), + .CPUCLK(CCLK), + .CPUADDR(ad), + .CPUDI(odt), + .CPUDO(viddata), + .CPUME(mx), + .CPUWE(mw), + .CPUDT(vid_Rce) + ); + +cmd_hvgen hvgen( + .HPOS(HP), + .VPOS(VP), + .PCLK(PCLK), + .HBLK(hblank), + .VBLK(vblank), + .HSYN(hsync), + .VSYN(vsync) + ); + +//-------------------------------------------------- +// SOUND //Todo +//-------------------------------------------------- +cmd_sound cmd_sound( + .clock_12(CCLKx4), + .reset(RESET), + .sound_req(sonr), + .sound_code_in(odt), + .sound_timing(snd_Wce), + .audio_out(SND) + ); + +endmodule diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/cmd_video.v b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/cmd_video.v new file mode 100644 index 00000000..63e691a4 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/cmd_video.v @@ -0,0 +1,194 @@ +module cmd_video +( + input VCLKx4, // 24.976MHz + + input [8:0] HPOS, + input [8:0] VPOS, + output PCLK, + output reg [7:0] POUT, + + input CPUCLK, + input [15:0] CPUADDR, + input [7:0] CPUDI, + output [7:0] CPUDO, + input CPUME, + input CPUWE, + output CPUDT +); + +//----------------------------------------- +// Clock generators +//----------------------------------------- +reg VCLKx2; +always @( posedge VCLKx4 ) begin + VCLKx2 <= ~VCLKx2; +end + +reg VCLK; +always @( posedge VCLKx2 ) begin + VCLK <= ~VCLK; +end + +//----------------------------------------- +// BG scroll registers +//----------------------------------------- +reg [7:0] BGHSCR; +reg [7:0] BGVSCR; + +always @ ( posedge CPUCLK ) begin + if ( ( CPUADDR == 16'hA130 ) & CPUME & CPUWE ) begin + BGHSCR <= CPUDI-3; + end + if ( ( CPUADDR == 16'hA140 ) & CPUME & CPUWE ) begin + BGVSCR <= CPUDI; + end +end + + +//----------------------------------------- +// HV +//----------------------------------------- +wire [8:0] BGHPOS = HPOS + { 1'b0, BGHSCR }; +wire [8:0] BGVPOS = VPOS + { 1'b0, BGVSCR }; + +wire oHB = ( HPOS > 288 ) ? 1 : 0; +wire oVB = ( VPOS > 224 ) ? 1 : 0; + + +//---------------------------------------- +// VideoRAM Scanner +//---------------------------------------- +wire BF = ( HPOS >= 224 ); +wire [8:0] HP = BF ? HPOS : BGHPOS; +wire [8:0] VP = ( BF ? VPOS : BGVPOS ) + 9'h0F; + +wire [10:0] SPRAADRS; +wire [3:0] ARAMADRS; + +reg [10:0] VRAMADRS; +always @ ( HPOS ) begin + VRAMADRS <= oHB ? + SPRAADRS : + BF ? { 1'b0, VP[7:3], 2'b00, HP[5:3] } : { 1'b1, VP[7:3], HP[7:3] }; +end + +wire [7:0] CHRC; +wire [7:0] ATTR; +wire [7:0] ARDT; + +wire [7:0] V0DO, V1DO; + +wire CEV0 = ( ( CPUADDR[15:12] == 4'b1000 ) & (~CPUADDR[11]) ) & CPUME; +wire CEV1 = ( ( CPUADDR[15:12] == 4'b1000 ) & CPUADDR[11] ) & CPUME; +wire CEAT = ( CPUADDR[15:4] == 12'b1010_0000_0000 ) & CPUME; + +wire [7:0] DTV0 = CEV0 ? V0DO : 8'h00; +wire [7:0] DTV1 = CEV1 ? V1DO : 8'h00; + +assign CPUDO = DTV0 | DTV1; +assign CPUDT = ( ~CPUWE ) & ( CEV0 | CEV1 ); + +GDPRAM #(11,8) vram0( VCLKx4, VRAMADRS, CHRC, CPUCLK, CPUADDR[10:0], ( CPUWE & CEV0 ), CPUDI, V0DO ); + +GDPRAM #(11,8) vram1( VCLKx4, VRAMADRS, ATTR, CPUCLK, CPUADDR[10:0], ( CPUWE & CEV1 ), CPUDI, V1DO ); + +GDPRAM #(4,8) aram0( VCLKx4, ARAMADRS, ARDT, CPUCLK, CPUADDR[3:0], ( CPUWE & CEAT ), CPUDI ); + +wire BGF = ATTR[5]; + + +//---------------------------------------- +// BG/Sprite chip data reader +//---------------------------------------- +wire BGFX = ATTR[6]; +wire [2:0] BGFY = { ATTR[7], ATTR[7], ATTR[7] }; + +wire [12:0] SPCHRADR;//Todo +wire [12:0] CHRA = oHB ? SPCHRADR : {CHRC, ( HP[2] ^ BGFX ), ( VP[2:0] ^ BGFY ) };//Todo + +wire [7:0] CHRO; +cmd_chr_rom chrrom( + .clk(VCLKx4), + .addr(CHRA), + .data(CHRO) +); + +//---------------------------------------- +// Rader-dot chip ROM +//---------------------------------------- +wire [7:0] DROMAD; +wire [7:0] DROMDT; +cmd_dot_rom dotrom( + .clk(VCLKx4), + .addr(DROMAD), + .data(DROMDT) + ); + +//---------------------------------------- +// BG/FG scanline generator +//---------------------------------------- +wire [5:0] BGPL = ATTR[5:0]; +reg [7:0] BGCOL; + +always @ ( posedge VCLK ) begin + case ( HP[1:0]^{2{BGFX}} ) + 2'b00: BGCOL <= { BGPL, CHRO[4], CHRO[0] }; + 2'b01: BGCOL <= { BGPL, CHRO[5], CHRO[1] }; + 2'b10: BGCOL <= { BGPL, CHRO[6], CHRO[2] }; + 2'b11: BGCOL <= { BGPL, CHRO[7], CHRO[3] }; + endcase +end + + +//---------------------------------------- +// Sprite Engine +//---------------------------------------- +wire [8:0] SPCOL; +cmd_sprite speng( + .VCLKx4(VCLKx4), + .HBLK(oHB), + .HPOS(HPOS), + .VPOS(VPOS), + .SPRAADRS(SPRAADRS), + .SPRADATA({ ATTR, CHRC }), + .ARAMADRS(ARAMADRS), + .ARAMDATA(ARDT), + .SPCHRADR(SPCHRADR), + .SPCHRDAT(CHRO), + .DROMAD(DROMAD), + .DROMDT(DROMDT), + .SPCOL(SPCOL) + ); + + +//---------------------------------------- +// Color mixer +//---------------------------------------- +wire bBGOPAQUE = ( ( BF | BGF ) & (~SPCOL[8]) ); +wire bSPTRANSP = ( SPCOL[1:0] == 2'b00 ); + +wire [7:0] OUTCOL = ( bBGOPAQUE | bSPTRANSP ) ? BGCOL : SPCOL[7:0]; +wire [3:0] CLUT; +cmd_col_rom colrom( + .clk(~VCLKx4), + .addr(OUTCOL), + .data(CLUT) + ); + +wire [4:0] PALA = SPCOL[8] ? SPCOL[4:0] : { 1'b0, CLUT }; +wire [7:0] PALO; + +cmd_pal_rom palrom( + .clk(VCLKx4), + .addr(PALA), + .data(PALO) + ); + +//---------------------------------------- +// Color output +//---------------------------------------- +always @ ( posedge PCLK ) POUT <= (oHB|oVB) ? 8'h0 : PALO; +assign PCLK = VCLK; + + +endmodule \ No newline at end of file diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/dpram.vhd b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..cda0f3cd --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/dpram.vhd @@ -0,0 +1,123 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY dpram IS + GENERIC + ( + init_file : string := ""; + numwords_a : natural := 0; -- not used any more + widthad_a : natural; + width_a : natural := 8; + outdata_reg_a : string := "UNREGISTERED"; + outdata_reg_b : string := "UNREGISTERED" + ); + PORT + ( + address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + clock_a : IN STD_LOGIC ; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + wren_a : IN STD_LOGIC := '1'; + wren_b : IN STD_LOGIC := '1'; + q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); +END dpram; + + +ARCHITECTURE SYN OF dpram IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + + COMPONENT altsyncram + GENERIC ( + address_reg_b : STRING; + clock_enable_input_a : STRING; + clock_enable_input_b : STRING; + clock_enable_output_a : STRING; + clock_enable_output_b : STRING; + indata_reg_b : STRING; + init_file : STRING; + intended_device_family : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + numwords_b : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_aclr_b : STRING; + outdata_reg_a : STRING; + outdata_reg_b : STRING; + power_up_uninitialized : STRING; + widthad_a : NATURAL; + widthad_b : NATURAL; + width_a : NATURAL; + width_b : NATURAL; + width_byteena_a : NATURAL; + width_byteena_b : NATURAL; + wrcontrol_wraddress_reg_b : STRING + ); + PORT ( + wren_a : IN STD_LOGIC ; + clock0 : IN STD_LOGIC ; + wren_b : IN STD_LOGIC ; + clock1 : IN STD_LOGIC ; + address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q_a <= sub_wire0(width_a-1 DOWNTO 0); + q_b <= sub_wire1(width_a-1 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + address_reg_b => "CLOCK1", + clock_enable_input_a => "BYPASS", + clock_enable_input_b => "BYPASS", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", + init_file => init_file, + intended_device_family => "Cyclone III", + lpm_type => "altsyncram", + numwords_a => 2**widthad_a, + numwords_b => 2**widthad_a, + operation_mode => "BIDIR_DUAL_PORT", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => outdata_reg_a, + outdata_reg_b => outdata_reg_b, + power_up_uninitialized => "FALSE", + widthad_a => widthad_a, + widthad_b => widthad_a, + width_a => width_a, + width_b => width_a, + width_byteena_a => 1, + width_byteena_b => 1, + wrcontrol_wraddress_reg_b => "CLOCK1" + ) + PORT MAP ( + wren_a => wren_a, + clock0 => clock_a, + wren_b => wren_b, + clock1 => clock_b, + address_a => address_a, + address_b => address_b, + data_a => data_a, + data_b => data_b, + q_a => sub_wire0, + q_b => sub_wire1 + ); + +END SYN; diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/gen_ram.vhd b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/gen_ram.vhd new file mode 100644 index 00000000..f1a95608 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/gen_ram.vhd @@ -0,0 +1,84 @@ +-- ----------------------------------------------------------------------- +-- +-- Syntiac's generic VHDL support files. +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- +-- Modified April 2016 by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +-- Remove address register when writing +-- +-- ----------------------------------------------------------------------- +-- +-- gen_rwram.vhd +-- +-- ----------------------------------------------------------------------- +-- +-- generic ram. +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +entity gen_ram is + generic ( + dWidth : integer := 8; + aWidth : integer := 10 + ); + port ( + clk : in std_logic; + we : in std_logic; + addr : in std_logic_vector((aWidth-1) downto 0); + d : in std_logic_vector((dWidth-1) downto 0); + q : out std_logic_vector((dWidth-1) downto 0) + ); +end entity; + +-- ----------------------------------------------------------------------- + +architecture rtl of gen_ram is + subtype addressRange is integer range 0 to ((2**aWidth)-1); + type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0); + signal ram: ramDef; + + signal rAddrReg : std_logic_vector((aWidth-1) downto 0); + signal qReg : std_logic_vector((dWidth-1) downto 0); +begin +-- ----------------------------------------------------------------------- +-- Signals to entity interface +-- ----------------------------------------------------------------------- +-- q <= qReg; + +-- ----------------------------------------------------------------------- +-- Memory write +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if we = '1' then + ram(to_integer(unsigned(addr))) <= d; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Memory read +-- ----------------------------------------------------------------------- +process(clk) + begin + if rising_edge(clk) then +-- qReg <= ram(to_integer(unsigned(rAddrReg))); +-- rAddrReg <= addr; +---- qReg <= ram(to_integer(unsigned(addr))); + q <= ram(to_integer(unsigned(addr))); + end if; + end process; +--q <= ram(to_integer(unsigned(addr))); +end architecture; + diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/pll.qip b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/pll.qip new file mode 100644 index 00000000..afd958be --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/pll.v b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/pll.v new file mode 100644 index 00000000..70025276 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/pll.v @@ -0,0 +1,309 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.4 Build 182 03/12/2014 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2014 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + inclk0, + c0, + locked); + + input inclk0; + output c0; + output locked; + + wire [4:0] sub_wire0; + wire sub_wire2; + wire [0:0] sub_wire5 = 1'h0; + wire [0:0] sub_wire1 = sub_wire0[0:0]; + wire c0 = sub_wire1; + wire locked = sub_wire2; + wire sub_wire3 = inclk0; + wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; + + altpll altpll_component ( + .inclk (sub_wire4), + .clk (sub_wire0), + .locked (sub_wire2), + .activeclock (), + .areset (1'b0), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 78, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 71, + altpll_component.clk0_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_UNUSED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "78" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.576923" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "71" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.57600000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "78" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "71" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/rams.v b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/rams.v new file mode 100644 index 00000000..4d579578 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/rams.v @@ -0,0 +1,64 @@ + + + +module GSPRAM #(parameter AW,parameter DW) +( + input CL, + input [(AW-1):0] AD, + input WE, + input [(DW-1):0] DI, + output reg [(DW-1):0] DO +); + +reg [(DW-1):0] core[0:((2**AW)-1)]; + +always @(posedge CL) begin + DO <= core[AD]; + if (WE) core[AD] <= DI; +end + +endmodule + + +module GDPRAM #(parameter AW,parameter DW) +( + input CL0, + input [(AW-1):0] AD0, + output reg [(DW-1):0] DO0, + + input CL1, + input [(AW-1):0] AD1, + input WE1, + input [(DW-1):0] DI1, + output reg [(DW-1):0] DO1 +); + +reg [(DW-1):0] core[0:((2**AW)-1)]; + +always @(posedge CL0) DO0 <= core[AD0]; +always @(posedge CL1) begin DO1 <= core[AD1]; if (WE1) core[AD1] <= DI1; end + +endmodule + +/* +module GLINEBUF #(parameter AW,parameter DW) +( + input CL0, + input [(AW-1):0] AD0, + input WE0, + output reg [(DW-1):0] DO0, + + input CL1, + input [(AW-1):0] AD1, + input WE1, + input [(DW-1):0] DI1 +); + +reg [(DW-1):0] core[0:((2**AW)-1)]; + +always @(posedge CL0) begin DO0 <= core[AD0]; if (WE0) core[AD0] <= 0; end +always @(posedge CL1) if (WE1) core[AD1] <= DI1; + +endmodule*/ + + diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/cmd_chr_rom.vhd b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/cmd_chr_rom.vhd new file mode 100644 index 00000000..eb8bbb01 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/cmd_chr_rom.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity cmd_chr_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of cmd_chr_rom is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"CC",X"EE",X"22",X"22",X"22",X"EE",X"CC",X"00",X"77",X"FF",X"88",X"88",X"88",X"FF",X"77", + X"00",X"00",X"00",X"44",X"EE",X"EE",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"00",X"00", + X"00",X"44",X"66",X"22",X"22",X"AA",X"EE",X"CC",X"00",X"CC",X"EE",X"FF",X"FF",X"BB",X"99",X"88", + X"00",X"22",X"22",X"22",X"AA",X"EE",X"66",X"22",X"00",X"44",X"CC",X"99",X"99",X"99",X"FF",X"66", + X"00",X"00",X"88",X"CC",X"66",X"EE",X"EE",X"00",X"00",X"33",X"33",X"22",X"22",X"FF",X"FF",X"22", + X"00",X"EE",X"EE",X"AA",X"AA",X"AA",X"AA",X"00",X"00",X"44",X"CC",X"88",X"88",X"88",X"FF",X"77", + X"00",X"88",X"CC",X"66",X"22",X"22",X"22",X"00",X"00",X"77",X"FF",X"99",X"99",X"99",X"FF",X"66", + X"00",X"66",X"66",X"22",X"22",X"AA",X"EE",X"66",X"00",X"00",X"00",X"EE",X"FF",X"11",X"00",X"00", + X"00",X"CC",X"EE",X"22",X"22",X"22",X"EE",X"CC",X"00",X"66",X"FF",X"99",X"99",X"99",X"FF",X"66", + X"00",X"CC",X"EE",X"22",X"22",X"22",X"EE",X"CC",X"00",X"00",X"99",X"99",X"99",X"DD",X"77",X"33", + X"00",X"88",X"CC",X"66",X"22",X"66",X"CC",X"88",X"00",X"FF",X"FF",X"22",X"22",X"22",X"FF",X"FF", + X"00",X"EE",X"EE",X"22",X"22",X"22",X"EE",X"CC",X"00",X"FF",X"FF",X"99",X"99",X"99",X"FF",X"66", + X"00",X"88",X"CC",X"66",X"22",X"22",X"66",X"44",X"00",X"33",X"77",X"CC",X"88",X"88",X"CC",X"44", + X"00",X"EE",X"EE",X"22",X"22",X"66",X"CC",X"88",X"00",X"FF",X"FF",X"88",X"88",X"CC",X"77",X"33", + X"00",X"EE",X"EE",X"22",X"22",X"22",X"22",X"22",X"00",X"FF",X"FF",X"99",X"99",X"99",X"99",X"88", + X"00",X"EE",X"EE",X"22",X"22",X"22",X"22",X"22",X"00",X"FF",X"FF",X"11",X"11",X"11",X"11",X"00", + X"00",X"88",X"CC",X"66",X"22",X"22",X"22",X"22",X"00",X"33",X"77",X"CC",X"88",X"99",X"FF",X"FF", + X"00",X"EE",X"EE",X"00",X"00",X"00",X"EE",X"EE",X"00",X"FF",X"FF",X"11",X"11",X"11",X"FF",X"FF", + X"00",X"00",X"00",X"22",X"EE",X"EE",X"22",X"00",X"00",X"00",X"00",X"88",X"FF",X"FF",X"88",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"EE",X"EE",X"00",X"44",X"CC",X"88",X"88",X"88",X"FF",X"77", + X"00",X"EE",X"EE",X"00",X"88",X"CC",X"66",X"22",X"00",X"FF",X"FF",X"33",X"77",X"EE",X"CC",X"88", + X"00",X"EE",X"EE",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"88",X"88",X"88",X"88",X"88", + X"00",X"EE",X"EE",X"CC",X"88",X"CC",X"EE",X"EE",X"00",X"FF",X"FF",X"11",X"33",X"11",X"FF",X"FF", + X"00",X"EE",X"EE",X"CC",X"88",X"00",X"EE",X"EE",X"00",X"FF",X"FF",X"11",X"33",X"77",X"FF",X"FF", + X"00",X"CC",X"EE",X"22",X"22",X"22",X"EE",X"CC",X"00",X"77",X"FF",X"88",X"88",X"88",X"FF",X"77", + X"00",X"EE",X"EE",X"22",X"22",X"22",X"EE",X"CC",X"00",X"FF",X"FF",X"22",X"22",X"22",X"33",X"11", + X"00",X"CC",X"EE",X"22",X"22",X"22",X"EE",X"CC",X"00",X"77",X"FF",X"88",X"AA",X"EE",X"77",X"BB", + X"00",X"EE",X"EE",X"22",X"22",X"22",X"EE",X"CC",X"00",X"FF",X"FF",X"22",X"66",X"FF",X"DD",X"99", + X"00",X"CC",X"EE",X"22",X"22",X"22",X"66",X"44",X"00",X"44",X"DD",X"99",X"99",X"99",X"FF",X"66", + X"00",X"22",X"22",X"EE",X"EE",X"22",X"22",X"00",X"00",X"00",X"00",X"FF",X"FF",X"00",X"00",X"00", + X"00",X"EE",X"EE",X"00",X"00",X"00",X"EE",X"EE",X"00",X"77",X"FF",X"88",X"88",X"88",X"FF",X"77", + X"00",X"EE",X"EE",X"00",X"00",X"00",X"EE",X"EE",X"00",X"11",X"33",X"77",X"EE",X"77",X"33",X"11", + X"00",X"EE",X"EE",X"00",X"88",X"00",X"EE",X"EE",X"00",X"33",X"FF",X"77",X"33",X"77",X"FF",X"33", + X"00",X"66",X"EE",X"CC",X"88",X"CC",X"EE",X"66",X"00",X"CC",X"EE",X"77",X"33",X"77",X"EE",X"CC", + X"00",X"66",X"EE",X"00",X"00",X"EE",X"66",X"00",X"00",X"00",X"11",X"FF",X"FF",X"11",X"00",X"00", + X"00",X"22",X"22",X"22",X"AA",X"EE",X"EE",X"66",X"00",X"CC",X"EE",X"FF",X"BB",X"99",X"88",X"88", + X"CC",X"22",X"99",X"55",X"55",X"11",X"22",X"CC",X"33",X"44",X"99",X"AA",X"AA",X"88",X"44",X"33", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"FF",X"33",X"FF",X"CC",X"00",X"00",X"00",X"00",X"CC",X"CC",X"FF",X"FF",X"EE",X"00",X"00",X"00", + X"BB",X"BB",X"BB",X"00",X"00",X"00",X"CC",X"FF",X"00",X"FF",X"FF",X"00",X"CC",X"FF",X"FF",X"33", + X"BB",X"33",X"00",X"00",X"EE",X"FF",X"33",X"33",X"DD",X"CC",X"00",X"00",X"77",X"FF",X"CC",X"CC", + X"33",X"00",X"00",X"EE",X"FF",X"FF",X"BB",X"BB",X"77",X"00",X"00",X"77",X"FF",X"FF",X"DD",X"DD", + X"00",X"00",X"EE",X"FF",X"FF",X"BB",X"BB",X"BB",X"00",X"00",X"CC",X"DD",X"DD",X"DD",X"FF",X"FF", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"D0",X"A0",X"50",X"A0",X"40",X"C0",X"E0",X"E0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"B0",X"70",X"B0",X"10",X"80",X"10",X"80",X"10",X"80",X"50",X"A0", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"C0",X"C0",X"A0",X"C0",X"A0",X"40",X"80", + X"70",X"B0",X"F0",X"70",X"F0",X"F0",X"D0",X"E0",X"F0",X"F0",X"E0",X"F0",X"D0",X"F0",X"F0",X"F0", + X"00",X"00",X"80",X"80",X"40",X"80",X"40",X"A0",X"C0",X"F0",X"F0",X"E0",X"F0",X"F0",X"F0",X"F0", + X"00",X"40",X"80",X"60",X"E0",X"D0",X"E0",X"D0",X"A0",X"50",X"A0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10", + X"10",X"30",X"10",X"20",X"10",X"30",X"10",X"30",X"10",X"00",X"10",X"00",X"10",X"10",X"10",X"10", + X"10",X"20",X"10",X"30",X"10",X"30",X"10",X"20",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"10",X"00",X"10",X"00",X"30",X"20",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"D0",X"E0",X"50",X"A0",X"40",X"80",X"80",X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"E0", + X"70",X"F0",X"50",X"A0",X"00",X"00",X"00",X"00",X"10",X"00",X"10",X"00",X"00",X"00",X"00",X"00", + X"E0",X"D0",X"A0",X"D0",X"A0",X"40",X"80",X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"A0",X"C0", + X"48",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"4B",X"4B",X"5A",X"78",X"84",X"0C",X"00",X"00", + X"78",X"78",X"D2",X"D2",X"96",X"96",X"E1",X"E1",X"C3",X"78",X"78",X"5A",X"4B",X"4B",X"D2",X"E1", + X"B4",X"B4",X"96",X"96",X"D2",X"F0",X"5A",X"5A",X"96",X"96",X"C3",X"78",X"3C",X"69",X"69",X"4B", + X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"48",X"00",X"00",X"C0",X"C0",X"B4",X"96",X"78",X"B4", + X"0F",X"FF",X"FF",X"EE",X"EE",X"EE",X"CC",X"44",X"0F",X"77",X"33",X"33",X"11",X"11",X"00",X"00", + X"7B",X"F3",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"4B",X"4B",X"5A",X"78",X"B7",X"3F",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"F3",X"7B",X"FF",X"FF",X"F3",X"F3",X"B4",X"96",X"78",X"B4", + X"0F",X"FF",X"FF",X"FE",X"FE",X"FE",X"FC",X"F4",X"0F",X"F7",X"F3",X"F3",X"F1",X"F0",X"F0",X"F0", + X"00",X"22",X"44",X"88",X"00",X"88",X"44",X"22",X"00",X"88",X"44",X"22",X"11",X"22",X"44",X"88", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"01",X"01",X"01",X"00", + X"0C",X"0E",X"0F",X"87",X"87",X"0F",X"0E",X"0C",X"61",X"41",X"C2",X"87",X"87",X"C2",X"41",X"A1", + X"0F",X"0F",X"0F",X"0E",X"0E",X"0C",X"08",X"00",X"1E",X"0D",X"0B",X"07",X"0F",X"0F",X"0F",X"0E", + X"0F",X"0F",X"0F",X"0F",X"0E",X"87",X"C3",X"61",X"C3",X"C3",X"C3",X"61",X"70",X"70",X"D0",X"80", + X"00",X"08",X"0C",X"0E",X"0E",X"0F",X"0F",X"87",X"0E",X"0F",X"0F",X"07",X"0B",X"0D",X"1E",X"10", + X"43",X"C3",X"86",X"0F",X"0F",X"0F",X"0F",X"00",X"80",X"D0",X"70",X"70",X"61",X"C3",X"C3",X"C2", + X"0C",X"0E",X"0F",X"87",X"87",X"0F",X"0E",X"0C",X"A1",X"41",X"C2",X"87",X"87",X"C2",X"41",X"61", + X"86",X"86",X"0C",X"0A",X"84",X"C0",X"84",X"80",X"42",X"86",X"94",X"96",X"1E",X"3C",X"48",X"18", + X"08",X"0C",X"00",X"E0",X"80",X"48",X"2C",X"00",X"E0",X"30",X"12",X"21",X"21",X"21",X"52",X"52", + X"08",X"2C",X"78",X"A4",X"0C",X"48",X"A4",X"B4",X"52",X"43",X"21",X"29",X"A5",X"90",X"30",X"E0", + X"00",X"08",X"08",X"00",X"08",X"86",X"E0",X"87",X"09",X"1C",X"3C",X"29",X"A5",X"94",X"86",X"42", + X"3F",X"1F",X"0F",X"87",X"87",X"0F",X"1F",X"3F",X"E9",X"EB",X"D3",X"87",X"87",X"D3",X"EB",X"E5", + X"0F",X"0F",X"0F",X"1F",X"1F",X"3F",X"7F",X"FF",X"1E",X"2F",X"4F",X"8F",X"0F",X"0F",X"0F",X"1F", + X"0F",X"0F",X"0F",X"0F",X"1F",X"87",X"C3",X"E9",X"C3",X"C3",X"C3",X"E9",X"F8",X"F8",X"F2",X"F7", + X"FF",X"7F",X"3F",X"1F",X"1F",X"0F",X"0F",X"87",X"1F",X"0F",X"0F",X"8F",X"4F",X"2F",X"1E",X"FE", + X"CB",X"C3",X"97",X"0F",X"0F",X"0F",X"0F",X"FF",X"F7",X"F2",X"F8",X"F8",X"E9",X"C3",X"C3",X"D3", + X"3F",X"1F",X"0F",X"87",X"87",X"0F",X"1F",X"3F",X"E5",X"EB",X"D3",X"87",X"87",X"D3",X"EB",X"E9", + X"97",X"97",X"3F",X"5F",X"B7",X"F3",X"B7",X"F7",X"DB",X"97",X"B6",X"96",X"1E",X"3C",X"7B",X"79", + X"7F",X"3F",X"FF",X"F1",X"F7",X"7B",X"3D",X"FF",X"F1",X"FC",X"DE",X"ED",X"ED",X"ED",X"DA",X"DA", + X"7F",X"3D",X"78",X"B5",X"3F",X"7B",X"B5",X"B4",X"DA",X"CB",X"ED",X"6D",X"A5",X"F6",X"FC",X"F1", + X"FF",X"7F",X"7F",X"FF",X"7F",X"97",X"F1",X"87",X"6F",X"3E",X"3C",X"6D",X"A5",X"B6",X"97",X"DB", + X"CC",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"99",X"FF",X"CC",X"88",X"00",X"00",X"00",X"00", + X"8F",X"8F",X"0F",X"8E",X"0E",X"0C",X"08",X"00",X"FF",X"8F",X"0F",X"FF",X"8F",X"8F",X"0F",X"0E", + X"6F",X"CF",X"6F",X"EF",X"6F",X"CF",X"6F",X"67",X"0F",X"0F",X"0F",X"07",X"07",X"03",X"01",X"00", + X"00",X"08",X"0C",X"8E",X"8E",X"0F",X"0F",X"8F",X"0E",X"0F",X"7F",X"FF",X"8F",X"7F",X"0F",X"8F", + X"67",X"CF",X"6F",X"EF",X"6F",X"CF",X"6F",X"EF",X"00",X"01",X"03",X"07",X"07",X"0F",X"0F",X"0F", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"CC",X"00",X"00",X"00",X"00",X"88",X"CC",X"FF",X"99", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0E",X"2E",X"26",X"00",X"00",X"00",X"00",X"00", + X"CE",X"6F",X"7F",X"7F",X"7F",X"2E",X"2E",X"0F",X"1F",X"2F",X"2F",X"0F",X"07",X"07",X"4F",X"0C", + X"0E",X"0C",X"88",X"CC",X"6E",X"2E",X"4C",X"8C",X"0D",X"4D",X"07",X"27",X"1F",X"0F",X"0F",X"0F", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"00",X"00",X"00",X"08",X"0C",X"8F",X"AE",X"8E", + X"FC",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F9",X"FF",X"FC",X"F8",X"F0",X"F0",X"F0",X"F0", + X"8F",X"8F",X"0F",X"9E",X"1E",X"3C",X"78",X"F0",X"FF",X"8F",X"0F",X"FF",X"8F",X"8F",X"0F",X"1E", + X"6F",X"CF",X"6F",X"EF",X"6F",X"CF",X"6F",X"E7",X"0F",X"0F",X"0F",X"87",X"87",X"C3",X"E1",X"F0", + X"F0",X"78",X"3C",X"9E",X"9E",X"0F",X"0F",X"8F",X"1E",X"0F",X"7F",X"FF",X"8F",X"7F",X"0F",X"8F", + X"E7",X"CF",X"6F",X"EF",X"6F",X"CF",X"6F",X"EF",X"F0",X"E1",X"C3",X"87",X"87",X"0F",X"0F",X"0F", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"FC",X"F0",X"F0",X"F0",X"F0",X"F8",X"FC",X"FF",X"F9", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"1E",X"3E",X"B6",X"F0",X"F0",X"F0",X"F0",X"F0", + X"DE",X"6F",X"7F",X"7F",X"7F",X"3E",X"3E",X"0F",X"1F",X"2F",X"2F",X"0F",X"87",X"87",X"4F",X"3C", + X"1E",X"3C",X"F8",X"FC",X"7E",X"3E",X"7C",X"BC",X"2D",X"6D",X"87",X"A7",X"1F",X"0F",X"0F",X"0F", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"B4",X"F0",X"F0",X"F0",X"78",X"3C",X"8F",X"BE",X"9E", + X"F0",X"B4",X"1E",X"1E",X"5A",X"5A",X"F0",X"F0",X"F0",X"D2",X"96",X"B4",X"A5",X"87",X"C3",X"F0", + X"F0",X"1E",X"F0",X"1E",X"1E",X"F0",X"1E",X"1E",X"87",X"87",X"F0",X"C3",X"87",X"B4",X"87",X"C3", + X"1E",X"D2",X"1E",X"3C",X"F0",X"1E",X"1E",X"3C",X"87",X"B4",X"87",X"C3",X"F0",X"87",X"87",X"E1", + X"F0",X"1E",X"1E",X"5A",X"1E",X"96",X"F0",X"3C",X"F0",X"87",X"87",X"B4",X"87",X"87",X"F0",X"C3", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"FF",X"33",X"3D",X"A5",X"42",X"86",X"16",X"92",X"FF",X"FC",X"8B",X"9A",X"A4",X"96",X"06",X"14", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FB",X"F3",X"FF",X"FF",X"FF",X"3F",X"1F",X"69",X"2D",X"0F", + X"82",X"06",X"96",X"52",X"85",X"1D",X"F3",X"FF",X"94",X"86",X"16",X"24",X"DA",X"CB",X"CC",X"FF", + X"F3",X"FB",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"0F",X"0F",X"0F",X"1F",X"3F",X"FF",X"FF",X"FF", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"F0",X"0F",X"0F",X"0F",X"0F",X"0F",X"50",X"0F",X"20",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + X"00",X"00",X"00",X"0C",X"0C",X"0E",X"0E",X"0E",X"00",X"0C",X"0F",X"0F",X"0F",X"03",X"01",X"01", + X"1E",X"0F",X"0F",X"87",X"E0",X"C0",X"C0",X"C0",X"0F",X"0F",X"0F",X"1E",X"1E",X"1E",X"1E",X"1E", + X"0F",X"0F",X"F0",X"50",X"F0",X"F0",X"F0",X"F0",X"0F",X"00",X"00",X"10",X"20",X"10",X"20",X"50", + X"00",X"0C",X"0E",X"0E",X"0E",X"00",X"00",X"00",X"0F",X"0F",X"0F",X"0F",X"0F",X"80",X"00",X"80", + X"87",X"0F",X"0F",X"0F",X"0F",X"E0",X"D0",X"E0",X"F0",X"0F",X"0F",X"0F",X"0F",X"F0",X"F0",X"0F", + X"0F",X"0F",X"0F",X"0F",X"F0",X"70",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"18",X"0F",X"0F",X"0F", + X"0E",X"0E",X"0E",X"00",X"00",X"00",X"00",X"00",X"0F",X"0F",X"0F",X"00",X"80",X"80",X"80",X"0C", + X"0F",X"0F",X"0F",X"F0",X"F0",X"3C",X"0F",X"0F",X"0F",X"0F",X"0F",X"3C",X"0F",X"0F",X"87",X"E1", + X"E1",X"0F",X"0F",X"0F",X"87",X"61",X"F0",X"F0",X"10",X"01",X"01",X"01",X"00",X"00",X"10",X"18", + X"0E",X"00",X"00",X"00",X"00",X"00",X"08",X"0E",X"0F",X"00",X"00",X"00",X"00",X"0E",X"0F",X"0F", + X"0F",X"00",X"00",X"00",X"0F",X"0F",X"0F",X"0F",X"0F",X"00",X"00",X"0F",X"0F",X"0F",X"0F",X"F0", + X"00",X"00",X"0F",X"0F",X"0F",X"0F",X"70",X"F0",X"08",X"0F",X"0F",X"0F",X"0F",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"0C",X"0E",X"0E",X"80",X"00",X"00",X"0C",X"0F",X"0F",X"0F",X"0F", + X"F0",X"2C",X"0F",X"0F",X"07",X"0F",X"0F",X"0F",X"0F",X"0F",X"07",X"01",X"00",X"0F",X"0F",X"0F", + X"07",X"01",X"00",X"00",X"0F",X"0F",X"0F",X"0F",X"00",X"00",X"00",X"08",X"0F",X"0F",X"0F",X"0F", + X"00",X"00",X"08",X"0E",X"0E",X"0E",X"0E",X"00",X"C0",X"0E",X"0F",X"0F",X"0F",X"0F",X"0F",X"C0", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"F0",X"0F",X"0F",X"0F",X"F0",X"0F",X"0F",X"0F",X"3C", + X"0F",X"0F",X"10",X"00",X"01",X"0F",X"0F",X"0F",X"0F",X"00",X"00",X"00",X"00",X"01",X"01",X"01", + X"0E",X"0C",X"0C",X"08",X"80",X"00",X"00",X"00",X"C3",X"0F",X"0F",X"0F",X"0F",X"78",X"00",X"80", + X"F0",X"F0",X"0F",X"0F",X"0F",X"0F",X"E0",X"F0",X"70",X"3C",X"0F",X"0F",X"0F",X"87",X"F0",X"0F", + X"1E",X"0F",X"0F",X"0F",X"03",X"10",X"0F",X"0F",X"07",X"03",X"03",X"00",X"08",X"0F",X"0F",X"0F", + X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0F",X"C3",X"C3",X"E1",X"E1",X"E1",X"E1",X"E1", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"70",X"F0",X"30",X"B0",X"50",X"B0",X"70",X"B0", + X"18",X"08",X"00",X"00",X"10",X"00",X"18",X"28",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"07", + X"0C",X"00",X"00",X"00",X"80",X"80",X"80",X"08",X"0F",X"0F",X"0C",X"F0",X"78",X"1E",X"0F",X"0F", + X"C3",X"C3",X"C3",X"3C",X"0F",X"0F",X"0F",X"87",X"B0",X"50",X"F0",X"0F",X"0F",X"0F",X"0F",X"F0", + X"0F",X"03",X"00",X"03",X"0F",X"0F",X"0F",X"1E",X"00",X"00",X"00",X"00",X"01",X"03",X"07",X"07", + X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0C",X"03",X"01",X"01",X"C1",X"C1",X"C3",X"0F",X"0F", + X"00",X"00",X"70",X"F0",X"F0",X"70",X"F0",X"43",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"50", + X"00",X"00",X"08",X"08",X"0C",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"07",X"07",X"07",X"03",X"01", + X"00",X"00",X"00",X"00",X"08",X"0C",X"0C",X"0E",X"00",X"08",X"0E",X"0F",X"0F",X"0F",X"07",X"03", + X"0E",X"0F",X"0F",X"0F",X"07",X"01",X"00",X"00",X"0F",X"0F",X"0F",X"0F",X"00",X"00",X"00",X"00", + X"07",X"0F",X"0F",X"0F",X"0E",X"08",X"08",X"00",X"00",X"01",X"03",X"07",X"07",X"0F",X"0F",X"0F", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"00",X"00",X"00",X"13",X"13",X"1F",X"1F",X"1F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"07", + X"00",X"80",X"84",X"0C",X"0C",X"0C",X"0C",X"C0",X"30",X"BC",X"9E",X"8F",X"BC",X"BC",X"AD",X"8F", + X"1F",X"0F",X"0F",X"07",X"07",X"01",X"00",X"00",X"07",X"01",X"00",X"00",X"00",X"00",X"00",X"00", + X"C0",X"80",X"00",X"00",X"CC",X"EE",X"EE",X"00",X"8F",X"AD",X"2D",X"0C",X"0F",X"0F",X"07",X"00", + X"00",X"00",X"00",X"13",X"13",X"1F",X"1F",X"1F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"07", + X"00",X"80",X"84",X"0C",X"0C",X"0C",X"0C",X"C0",X"30",X"BC",X"9E",X"8F",X"BC",X"BC",X"AD",X"8F", + X"1F",X"0F",X"4F",X"EF",X"EF",X"6F",X"0F",X"06",X"07",X"03",X"00",X"00",X"00",X"00",X"00",X"00", + X"C0",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"8F",X"AD",X"2D",X"08",X"08",X"00",X"00",X"00", + X"00",X"00",X"01",X"07",X"07",X"0F",X"0F",X"1F",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"07", + X"00",X"EE",X"EE",X"CC",X"00",X"00",X"80",X"84",X"00",X"07",X"0F",X"0F",X"0C",X"3C",X"BC",X"9E", + X"1F",X"1F",X"1F",X"13",X"13",X"00",X"00",X"00",X"07",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"0C",X"0C",X"0C",X"0C",X"C0",X"C0",X"80",X"00",X"8F",X"BC",X"BC",X"AD",X"8F",X"8F",X"AD",X"21", + X"06",X"0F",X"6F",X"EF",X"EF",X"4F",X"0F",X"1F",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"07", + X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"84",X"00",X"00",X"00",X"08",X"08",X"3C",X"BC",X"9E", + X"1F",X"1F",X"1F",X"13",X"13",X"00",X"00",X"00",X"07",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"0C",X"0C",X"0C",X"0C",X"C0",X"C0",X"80",X"00",X"8F",X"BC",X"BC",X"AD",X"8F",X"8F",X"AD",X"21", + X"00",X"00",X"0F",X"8F",X"8F",X"87",X"87",X"0F",X"00",X"00",X"00",X"11",X"10",X"30",X"30",X"10", + X"00",X"00",X"00",X"C0",X"E0",X"69",X"0F",X"C3",X"00",X"00",X"00",X"0B",X"2F",X"6F",X"6F",X"6F", + X"0F",X"0F",X"0F",X"97",X"B7",X"37",X"03",X"00",X"01",X"34",X"34",X"34",X"34",X"00",X"00",X"00", + X"C3",X"87",X"3C",X"3C",X"A4",X"84",X"00",X"00",X"6F",X"6F",X"6F",X"6F",X"2F",X"0F",X"08",X"00", + X"CF",X"CF",X"4F",X"87",X"87",X"87",X"87",X"87",X"00",X"07",X"03",X"21",X"30",X"30",X"10",X"00", + X"00",X"00",X"00",X"00",X"00",X"84",X"A4",X"3C",X"00",X"08",X"0C",X"0E",X"0E",X"0F",X"0F",X"2F", + X"87",X"C3",X"C3",X"83",X"67",X"66",X"00",X"00",X"07",X"34",X"34",X"10",X"00",X"00",X"00",X"00", + X"3C",X"87",X"C3",X"C3",X"0F",X"69",X"E0",X"C0",X"6F",X"0F",X"EF",X"EF",X"EF",X"EF",X"67",X"01", + X"E1",X"69",X"C3",X"87",X"87",X"0F",X"EF",X"CF",X"03",X"01",X"07",X"34",X"30",X"30",X"30",X"31", + X"00",X"00",X"00",X"00",X"00",X"84",X"A4",X"3C",X"00",X"00",X"08",X"0C",X"0E",X"0F",X"0F",X"2F", + X"87",X"07",X"07",X"03",X"00",X"00",X"00",X"00",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"3C",X"87",X"C3",X"C3",X"07",X"69",X"E0",X"C0",X"6F",X"0F",X"EF",X"EF",X"EF",X"EF",X"67",X"01", + X"0C",X"86",X"F0",X"E1",X"E1",X"C3",X"C3",X"87",X"01",X"10",X"10",X"00",X"00",X"07",X"34",X"30", + X"00",X"00",X"00",X"00",X"00",X"84",X"A4",X"3C",X"00",X"00",X"08",X"0C",X"0E",X"0F",X"0F",X"2F", + X"87",X"C3",X"87",X"0E",X"0C",X"CC",X"88",X"00",X"30",X"10",X"10",X"00",X"11",X"11",X"00",X"00", + X"3C",X"87",X"C3",X"C3",X"0F",X"69",X"E0",X"C0",X"6F",X"0F",X"EF",X"EF",X"EF",X"EF",X"67",X"01", + X"00",X"88",X"CC",X"0C",X"0E",X"87",X"C3",X"87",X"00",X"00",X"11",X"11",X"00",X"10",X"10",X"30", + X"C0",X"E0",X"69",X"0F",X"C3",X"C3",X"87",X"3C",X"01",X"67",X"EF",X"EF",X"EF",X"EF",X"0F",X"6F", + X"87",X"C3",X"C3",X"E1",X"E1",X"F0",X"86",X"0C",X"30",X"34",X"07",X"00",X"00",X"10",X"10",X"01", + X"3C",X"A4",X"84",X"00",X"00",X"00",X"00",X"00",X"2F",X"0F",X"0F",X"0E",X"0C",X"08",X"00",X"00", + X"00",X"00",X"00",X"00",X"03",X"0F",X"0F",X"87",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10", + X"C0",X"E0",X"69",X"0F",X"C3",X"C3",X"87",X"3C",X"01",X"67",X"EF",X"EF",X"EF",X"EF",X"0F",X"6F", + X"CF",X"EF",X"0F",X"87",X"87",X"C3",X"69",X"E0",X"31",X"30",X"30",X"30",X"34",X"07",X"01",X"03", + X"3C",X"A4",X"84",X"00",X"00",X"00",X"00",X"00",X"2F",X"0F",X"0F",X"0E",X"0C",X"08",X"00",X"00", + X"00",X"00",X"66",X"67",X"83",X"C3",X"C3",X"87",X"00",X"00",X"00",X"00",X"10",X"30",X"34",X"07", + X"C0",X"E0",X"69",X"0F",X"C3",X"C3",X"87",X"3C",X"01",X"67",X"EF",X"EF",X"EF",X"EF",X"0F",X"6F", + X"87",X"87",X"87",X"87",X"C3",X"4F",X"CF",X"CF",X"00",X"10",X"30",X"30",X"21",X"03",X"07",X"00", + X"3C",X"A4",X"84",X"00",X"00",X"00",X"00",X"00",X"2F",X"0F",X"0F",X"0E",X"0E",X"0C",X"08",X"00", + X"66",X"EF",X"47",X"83",X"87",X"0F",X"0F",X"0F",X"00",X"07",X"07",X"03",X"43",X"70",X"70",X"61", + X"00",X"00",X"84",X"A4",X"3C",X"3C",X"87",X"C3",X"00",X"00",X"01",X"2B",X"6F",X"6F",X"0F",X"EF", + X"0F",X"0F",X"0F",X"0F",X"86",X"C0",X"0C",X"0E",X"21",X"21",X"21",X"10",X"10",X"10",X"01",X"01", + X"C3",X"0F",X"69",X"E0",X"C0",X"00",X"00",X"00",X"EF",X"EF",X"EF",X"67",X"01",X"00",X"00",X"00", + X"0E",X"0C",X"C0",X"86",X"0F",X"0F",X"0F",X"0F",X"01",X"01",X"10",X"10",X"10",X"21",X"21",X"21", + X"00",X"00",X"00",X"C0",X"E0",X"69",X"0F",X"C3",X"00",X"00",X"00",X"01",X"67",X"EF",X"EF",X"EF", + X"0F",X"0F",X"0F",X"87",X"87",X"47",X"EF",X"66",X"61",X"70",X"70",X"43",X"03",X"07",X"07",X"00", + X"C3",X"87",X"3C",X"3C",X"A4",X"84",X"00",X"00",X"EF",X"0F",X"6F",X"6F",X"2B",X"01",X"00",X"00", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"01",X"33",X"33",X"F7",X"A7",X"87",X"0F",X"0F",X"00",X"00",X"04",X"34",X"16",X"34",X"30",X"10", + X"00",X"00",X"00",X"C0",X"E0",X"69",X"0F",X"C3",X"08",X"0C",X"0C",X"0F",X"2F",X"6F",X"6F",X"6F", + X"0F",X"0F",X"87",X"87",X"87",X"83",X"00",X"00",X"10",X"10",X"10",X"30",X"34",X"16",X"34",X"04", + X"C3",X"87",X"3C",X"3C",X"A4",X"B7",X"FF",X"44",X"6F",X"6F",X"6F",X"6F",X"2F",X"0F",X"0F",X"00", + X"08",X"0E",X"E0",X"78",X"F0",X"C3",X"87",X"0F",X"03",X"34",X"07",X"43",X"70",X"70",X"70",X"30", + X"00",X"00",X"00",X"00",X"84",X"A4",X"3C",X"3C",X"00",X"00",X"00",X"00",X"01",X"2B",X"6F",X"0F", + X"0F",X"0F",X"0F",X"0F",X"03",X"01",X"00",X"00",X"30",X"01",X"01",X"00",X"00",X"00",X"00",X"00", + X"87",X"C3",X"C3",X"0F",X"69",X"E0",X"C0",X"00",X"6F",X"6F",X"6F",X"6F",X"2F",X"2F",X"0D",X"EE", + X"00",X"08",X"C0",X"C2",X"4B",X"0F",X"2F",X"6F",X"07",X"21",X"70",X"70",X"61",X"43",X"07",X"07", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"84",X"A4",X"3C",X"3C", + X"0F",X"6F",X"6F",X"6F",X"EF",X"67",X"01",X"00",X"07",X"07",X"07",X"07",X"47",X"67",X"22",X"66", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"87",X"C3",X"C3",X"0F",X"69",X"E0",X"C0",X"00", + X"00",X"08",X"C0",X"C2",X"4B",X"0F",X"2F",X"6F",X"07",X"21",X"70",X"70",X"61",X"43",X"07",X"07", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"84",X"A4",X"3C",X"3C", + X"0F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"07",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"4B",X"61",X"61",X"01",X"01",X"00",X"00",X"00", + X"00",X"00",X"01",X"03",X"0F",X"0F",X"0F",X"0F",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"30", + X"00",X"C0",X"E0",X"69",X"0F",X"C3",X"C3",X"87",X"EE",X"0D",X"2F",X"2F",X"6F",X"6F",X"6F",X"6F", + X"0F",X"87",X"C3",X"F0",X"78",X"E0",X"0E",X"08",X"30",X"70",X"70",X"70",X"43",X"07",X"34",X"03", + X"3C",X"3C",X"A4",X"84",X"00",X"00",X"00",X"00",X"0F",X"6F",X"2B",X"01",X"00",X"00",X"00",X"00", + X"00",X"01",X"67",X"EF",X"6F",X"6F",X"6F",X"0F",X"66",X"22",X"67",X"47",X"07",X"07",X"07",X"07", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"E0",X"69",X"0F",X"C3",X"C3",X"87", + X"6F",X"2F",X"0F",X"4B",X"C3",X"C0",X"08",X"00",X"07",X"07",X"43",X"61",X"70",X"70",X"21",X"07", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"3C",X"3C",X"A4",X"84",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"07", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"43",X"43",X"0F", + X"6F",X"2F",X"0F",X"4B",X"C2",X"C0",X"08",X"00",X"07",X"07",X"43",X"61",X"70",X"70",X"21",X"07", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"3C",X"3C",X"A4",X"84",X"00",X"00",X"00",X"00", + X"88",X"88",X"00",X"00",X"00",X"00",X"00",X"88",X"7F",X"7F",X"3F",X"0E",X"68",X"C0",X"00",X"BB", + X"69",X"69",X"4B",X"0F",X"B4",X"F0",X"30",X"22",X"01",X"01",X"01",X"01",X"10",X"00",X"00",X"33", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0E",X"0E",X"0C",X"08",X"08",X"6E",X"7F", + X"10",X"10",X"12",X"1E",X"0F",X"2D",X"69",X"69",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"01", + X"00",X"88",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"EE",X"00",X"00",X"00",X"00",X"00",X"00", + X"30",X"66",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"11",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"88",X"88",X"00",X"00",X"00",X"00",X"6E",X"7F",X"7F",X"7F",X"3F",X"0E",X"68",X"C0", + X"69",X"69",X"69",X"69",X"4B",X"0F",X"B4",X"F0",X"01",X"01",X"01",X"01",X"01",X"01",X"10",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0E",X"0E",X"0C",X"08",X"08", + X"00",X"00",X"10",X"10",X"12",X"1E",X"0F",X"2D",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01", + X"00",X"00",X"00",X"88",X"00",X"00",X"00",X"00",X"68",X"C0",X"00",X"CC",X"00",X"00",X"00",X"00", + X"B4",X"F0",X"30",X"DD",X"00",X"00",X"00",X"00",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"88",X"88",X"00",X"00",X"80",X"80",X"6E",X"7F",X"7F",X"7F",X"3F",X"0E", + X"0F",X"2D",X"69",X"69",X"69",X"69",X"4B",X"0F",X"00",X"01",X"01",X"01",X"01",X"01",X"01",X"01", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0E",X"0E",X"0C", + X"00",X"00",X"00",X"00",X"10",X"10",X"12",X"1E",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"88",X"00",X"00",X"3F",X"0E",X"68",X"C0",X"00",X"DD",X"00",X"00", + X"4B",X"0F",X"B4",X"F0",X"30",X"AA",X"00",X"00",X"01",X"01",X"10",X"00",X"00",X"11",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"88",X"88",X"0E",X"0C",X"08",X"08",X"6E",X"7F",X"7F",X"7F", + X"12",X"1E",X"0F",X"2D",X"69",X"69",X"69",X"69",X"00",X"00",X"00",X"01",X"01",X"01",X"01",X"01", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0E", + X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"8C",X"A8",X"88",X"20",X"20",X"20",X"00",X"00",X"1F",X"FF",X"F0",X"D0",X"D0",X"A0",X"C0",X"80", + X"CF",X"CF",X"DF",X"FE",X"FE",X"FC",X"FC",X"FC",X"3B",X"3B",X"3F",X"3B",X"3B",X"1D",X"11",X"00", + X"00",X"80",X"80",X"20",X"20",X"20",X"88",X"A8",X"EE",X"EF",X"88",X"88",X"EE",X"FF",X"FF",X"3F", + X"11",X"77",X"FF",X"FF",X"FF",X"FF",X"FF",X"EF",X"00",X"00",X"00",X"11",X"11",X"3B",X"3F",X"3B", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"80",X"00",X"00",X"00",X"00",X"00",X"00", + X"FC",X"FC",X"00",X"00",X"00",X"00",X"00",X"00",X"11",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"A8",X"A8",X"8C",X"A8",X"A8",X"00",X"20",X"20",X"FF",X"3F",X"1F",X"FF",X"F0",X"D0",X"D0",X"A0", + X"FF",X"EF",X"CF",X"CF",X"DF",X"FE",X"FE",X"FC",X"3F",X"3B",X"3B",X"3B",X"3F",X"3B",X"3B",X"1D", + X"00",X"00",X"80",X"80",X"00",X"20",X"20",X"00",X"00",X"00",X"EE",X"EF",X"88",X"88",X"EE",X"FF", + X"00",X"00",X"11",X"77",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"11",X"11",X"3B", + X"00",X"20",X"00",X"00",X"00",X"00",X"00",X"00",X"D0",X"A0",X"C0",X"80",X"00",X"00",X"00",X"00", + X"FE",X"FC",X"FC",X"FC",X"00",X"00",X"00",X"00",X"3B",X"1D",X"11",X"00",X"00",X"00",X"00",X"00", + X"00",X"20",X"A8",X"A8",X"8C",X"A8",X"A8",X"20",X"EE",X"FF",X"FF",X"3F",X"1F",X"FF",X"F0",X"D0", + X"FF",X"FF",X"FF",X"EF",X"CF",X"CF",X"DF",X"FE",X"11",X"3B",X"3F",X"3B",X"3B",X"3B",X"3F",X"3B", + X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"20",X"00",X"00",X"00",X"00",X"EE",X"EF",X"88",X"88", + X"00",X"00",X"00",X"00",X"11",X"77",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"11", + X"A8",X"00",X"20",X"20",X"00",X"00",X"00",X"00",X"F0",X"D0",X"D0",X"A0",X"C0",X"80",X"00",X"00", + X"DF",X"FE",X"FE",X"FC",X"FC",X"FC",X"00",X"00",X"3F",X"3B",X"3B",X"1D",X"11",X"00",X"00",X"00", + X"00",X"20",X"20",X"00",X"A8",X"A8",X"8C",X"A8",X"88",X"88",X"EE",X"FF",X"FF",X"3F",X"1F",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"EF",X"CF",X"CF",X"00",X"11",X"11",X"3B",X"3F",X"3B",X"3B",X"3B", + X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"EE",X"EF", + X"00",X"00",X"00",X"00",X"00",X"00",X"11",X"77",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"66",X"44",X"CC",X"88",X"00",X"00",X"00",X"00",X"F7",X"E6",X"4C",X"7F",X"E6",X"08",X"08",X"00", + X"5A",X"1E",X"C3",X"C3",X"96",X"0F",X"0F",X"07",X"61",X"43",X"03",X"30",X"10",X"01",X"00",X"00", + X"08",X"C0",X"C0",X"CA",X"CE",X"EE",X"AA",X"AA",X"E1",X"4B",X"3C",X"3F",X"7F",X"7F",X"F7",X"FF", + X"EF",X"EF",X"EF",X"EF",X"EF",X"EF",X"4F",X"FB",X"16",X"34",X"34",X"34",X"16",X"07",X"34",X"75", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"80",X"08",X"08",X"0C",X"A4",X"F0", + X"B4",X"A5",X"0F",X"6F",X"6F",X"6F",X"EF",X"EF",X"12",X"30",X"30",X"21",X"61",X"61",X"61",X"07", + X"00",X"00",X"08",X"0C",X"C0",X"80",X"00",X"00",X"00",X"E1",X"C3",X"1E",X"1E",X"3C",X"3C",X"84", + X"22",X"27",X"2F",X"2F",X"A7",X"A7",X"87",X"1E",X"00",X"00",X"00",X"00",X"10",X"10",X"10",X"03", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"08",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"0F",X"07",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"AA",X"AA",X"66",X"44",X"CC",X"88",X"00",X"00",X"F7",X"F7",X"F7",X"E6",X"4C",X"7F",X"E6",X"08", + X"4F",X"F7",X"5A",X"1E",X"C3",X"C3",X"96",X"0F",X"34",X"73",X"61",X"43",X"03",X"30",X"10",X"01", + X"00",X"00",X"08",X"C0",X"C0",X"CA",X"CE",X"EE",X"A4",X"F0",X"E1",X"4B",X"3C",X"3F",X"7F",X"7F", + X"EF",X"EF",X"EF",X"EF",X"EF",X"EF",X"EF",X"EF",X"61",X"07",X"16",X"34",X"34",X"34",X"16",X"07", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"3C",X"84",X"80",X"80",X"80",X"08",X"08",X"0C", + X"87",X"1E",X"B4",X"A5",X"0F",X"6F",X"6F",X"6F",X"10",X"03",X"12",X"30",X"30",X"21",X"61",X"61", + X"00",X"00",X"00",X"00",X"08",X"0C",X"C0",X"80",X"00",X"00",X"00",X"E1",X"C3",X"1E",X"1E",X"3C", + X"00",X"00",X"22",X"27",X"2F",X"2F",X"A7",X"A7",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"10", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"E6",X"08",X"08",X"00",X"00",X"00",X"00",X"00", + X"96",X"0F",X"0F",X"07",X"00",X"00",X"00",X"00",X"10",X"01",X"00",X"00",X"00",X"00",X"00",X"00", + X"CE",X"EE",X"AA",X"AA",X"66",X"44",X"CC",X"88",X"7F",X"7F",X"F7",X"FF",X"F7",X"E6",X"4C",X"7F", + X"EF",X"EF",X"4F",X"FE",X"5A",X"1E",X"C3",X"C3",X"16",X"07",X"34",X"76",X"61",X"43",X"03",X"30", + X"00",X"00",X"00",X"00",X"08",X"C0",X"C0",X"CA",X"08",X"0C",X"A4",X"F0",X"E1",X"4B",X"3C",X"3F", + X"6F",X"EF",X"EF",X"EF",X"EF",X"EF",X"EF",X"EF",X"61",X"61",X"61",X"07",X"16",X"34",X"34",X"34", + X"C0",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"1E",X"3C",X"3C",X"84",X"80",X"80",X"80",X"08", + X"A7",X"A7",X"87",X"1E",X"B4",X"A5",X"0F",X"6F",X"10",X"10",X"10",X"03",X"12",X"30",X"30",X"21", + X"00",X"00",X"00",X"00",X"00",X"00",X"08",X"0C",X"00",X"00",X"00",X"00",X"00",X"E1",X"C3",X"1E", + X"00",X"00",X"00",X"00",X"22",X"27",X"2F",X"2F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"CC",X"88",X"00",X"00",X"00",X"00",X"00",X"00",X"4C",X"7F",X"E6",X"08",X"08",X"00",X"00",X"00", + X"C3",X"C3",X"96",X"0F",X"0F",X"07",X"00",X"00",X"03",X"30",X"10",X"01",X"00",X"00",X"00",X"00", + X"C0",X"CA",X"CE",X"EE",X"AA",X"AA",X"66",X"44",X"3C",X"3F",X"7F",X"7F",X"F7",X"F7",X"F7",X"E6", + X"EF",X"EF",X"EF",X"EF",X"4F",X"FB",X"5A",X"1E",X"34",X"34",X"16",X"07",X"34",X"73",X"61",X"43", + X"00",X"00",X"00",X"00",X"00",X"00",X"08",X"C0",X"80",X"08",X"08",X"0C",X"A4",X"F0",X"E1",X"4B", + X"0F",X"6F",X"6F",X"EF",X"EF",X"EF",X"EF",X"EF",X"30",X"21",X"61",X"61",X"61",X"07",X"16",X"34", + X"08",X"0C",X"C0",X"80",X"00",X"00",X"00",X"00",X"C3",X"1E",X"1E",X"3C",X"3C",X"84",X"80",X"80", + X"2F",X"2F",X"A7",X"A7",X"87",X"1E",X"B4",X"A5",X"00",X"00",X"10",X"10",X"10",X"03",X"12",X"30", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"E1", + X"00",X"00",X"00",X"00",X"00",X"00",X"22",X"27",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"CC",X"02",X"08",X"6E",X"7B",X"F3",X"EE",X"88",X"97",X"F1",X"F3",X"E7",X"CF",X"16",X"32",X"11", + X"CF",X"7E",X"3D",X"F1",X"E4",X"CD",X"00",X"04",X"03",X"23",X"74",X"FC",X"FE",X"FF",X"77",X"00", + X"00",X"CC",X"EE",X"F8",X"7B",X"6A",X"4C",X"E6",X"02",X"00",X"DD",X"FC",X"E1",X"79",X"2F",X"4B", + X"00",X"9B",X"8F",X"2F",X"7C",X"EF",X"4B",X"F7",X"33",X"77",X"FE",X"ED",X"65",X"23",X"09",X"03", + X"8C",X"C0",X"C0",X"60",X"60",X"30",X"30",X"10",X"7E",X"F3",X"E6",X"C0",X"C1",X"80",X"80",X"80", + X"CB",X"FD",X"FE",X"FE",X"FF",X"66",X"00",X"00",X"FC",X"30",X"31",X"60",X"40",X"C0",X"81",X"80", + X"78",X"E6",X"EC",X"80",X"C4",X"EE",X"F7",X"E6",X"1E",X"A5",X"4B",X"0F",X"3D",X"E3",X"C3",X"9F", + X"6D",X"C3",X"69",X"BC",X"4B",X"CB",X"6D",X"9E",X"E1",X"63",X"31",X"32",X"77",X"FE",X"77",X"FE", + X"C4",X"EA",X"7F",X"7F",X"EA",X"C4",X"C8",X"68",X"4F",X"A5",X"F5",X"5A",X"69",X"C3",X"F9",X"B4", + X"D6",X"BD",X"E5",X"0F",X"5A",X"0F",X"DA",X"4B",X"77",X"FE",X"77",X"77",X"36",X"31",X"71",X"F0", + X"10",X"10",X"30",X"60",X"60",X"C0",X"C9",X"C0",X"00",X"00",X"80",X"A2",X"F7",X"FF",X"FA",X"FD", + X"10",X"10",X"54",X"FE",X"FC",X"FC",X"F5",X"CB",X"80",X"40",X"60",X"20",X"30",X"14",X"19",X"77", + X"60",X"30",X"30",X"10",X"00",X"00",X"00",X"00",X"C1",X"80",X"80",X"80",X"00",X"00",X"00",X"00", + X"FF",X"66",X"00",X"00",X"00",X"00",X"00",X"00",X"40",X"C0",X"81",X"80",X"00",X"00",X"00",X"00", + X"C4",X"EE",X"F7",X"E6",X"8C",X"C0",X"C0",X"60",X"3D",X"E3",X"C3",X"9F",X"7E",X"F3",X"E6",X"C0", + X"4F",X"CB",X"6D",X"9E",X"CB",X"FD",X"FE",X"FE",X"77",X"FE",X"77",X"FE",X"FC",X"30",X"31",X"60", + X"EA",X"C4",X"C8",X"68",X"78",X"E8",X"E2",X"80",X"69",X"C3",X"F9",X"B4",X"1E",X"A5",X"4B",X"0F", + X"5A",X"0F",X"DA",X"4B",X"6D",X"C3",X"69",X"BC",X"36",X"31",X"71",X"F0",X"E1",X"63",X"31",X"32", + X"60",X"C0",X"C9",X"C0",X"C4",X"EA",X"7F",X"7F",X"F7",X"FF",X"FA",X"FD",X"4F",X"A5",X"F5",X"5A", + X"FC",X"FC",X"F5",X"CB",X"D6",X"BD",X"E5",X"0F",X"30",X"14",X"19",X"77",X"77",X"FE",X"77",X"77", + X"00",X"00",X"00",X"00",X"10",X"10",X"30",X"60",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"A2", + X"00",X"00",X"00",X"00",X"10",X"10",X"54",X"FE",X"00",X"00",X"00",X"00",X"80",X"40",X"60",X"20", + X"0E",X"0E",X"0E",X"0C",X"0C",X"08",X"00",X"00",X"81",X"81",X"03",X"0F",X"0F",X"0F",X"0F",X"08", + X"F0",X"F0",X"E0",X"00",X"0F",X"0F",X"0F",X"0F",X"F0",X"70",X"30",X"0C",X"0F",X"0F",X"0F",X"07", + X"08",X"08",X"0E",X"0F",X"0F",X"0F",X"03",X"00",X"0F",X"07",X"07",X"03",X"03",X"00",X"00",X"00", + X"80",X"08",X"0C",X"0E",X"0E",X"0E",X"0E",X"0E",X"0F",X"0F",X"0F",X"C3",X"C3",X"C1",X"C1",X"C1", + X"0F",X"C3",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"0F",X"70",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"0F",X"0E",X"08",X"18",X"10",X"10",X"10",X"00",X"07",X"07",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + X"0C",X"08",X"00",X"80",X"80",X"80",X"C0",X"80",X"0F",X"0F",X"0F",X"0E",X"78",X"F0",X"78",X"1E", + X"F0",X"0F",X"0F",X"0F",X"0F",X"3C",X"0F",X"0F",X"78",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + X"0F",X"0F",X"0F",X"87",X"E1",X"C3",X"0F",X"0F",X"03",X"01",X"10",X"30",X"30",X"10",X"01",X"03", + X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0C",X"0F",X"01",X"81",X"01",X"01",X"01",X"83",X"43", + X"E0",X"D0",X"E0",X"D0",X"A0",X"D0",X"A0",X"D0",X"F0",X"F0",X"F0",X"F0",X"E0",X"F0",X"F0",X"F0", + X"30",X"10",X"30",X"70",X"78",X"78",X"3C",X"1E",X"0F",X"0F",X"0F",X"0F",X"07",X"07",X"07",X"03", + X"0E",X"0E",X"0E",X"0E",X"00",X"08",X"0E",X"0E",X"0F",X"0F",X"0F",X"01",X"08",X"0F",X"0F",X"0F", + X"0F",X"07",X"80",X"08",X"0F",X"0F",X"0F",X"0F",X"43",X"D0",X"68",X"0F",X"0F",X"0F",X"0F",X"F0", + X"10",X"70",X"0F",X"0F",X"0F",X"0F",X"07",X"07",X"08",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"00",X"00",X"00",X"00",X"00",X"08",X"0F", + X"0F",X"0F",X"00",X"00",X"00",X"0C",X"0F",X"0F",X"0F",X"0F",X"0F",X"00",X"0E",X"0F",X"0F",X"0F", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"01",X"00",X"0F",X"0F",X"0F",X"0F",X"0F",X"01",X"00", + X"00",X"00",X"08",X"0E",X"0E",X"0E",X"0E",X"0E",X"00",X"08",X"0F",X"0F",X"0F",X"07",X"0F",X"0F", + X"08",X"0F",X"0F",X"0F",X"07",X"00",X"0F",X"0F",X"0F",X"0F",X"0F",X"07",X"80",X"00",X"00",X"0F", + X"0F",X"0F",X"0F",X"50",X"20",X"00",X"00",X"00",X"0F",X"0F",X"20",X"10",X"00",X"00",X"00",X"00", + X"0E",X"0E",X"0E",X"0E",X"0C",X"00",X"00",X"00",X"81",X"81",X"0F",X"0F",X"0F",X"0E",X"80",X"80", + X"F0",X"F0",X"0F",X"0F",X"0F",X"0F",X"F0",X"F0",X"1E",X"1E",X"0F",X"0F",X"0F",X"0F",X"F0",X"78", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"66",X"EF",X"C7",X"C3",X"87",X"87",X"0F",X"00",X"00",X"00",X"14",X"34",X"16",X"34",X"10", + X"00",X"00",X"00",X"C0",X"E0",X"69",X"0F",X"C3",X"00",X"00",X"00",X"DB",X"2F",X"6F",X"6F",X"6F", + X"0F",X"0F",X"87",X"87",X"C3",X"C7",X"EF",X"66",X"10",X"10",X"34",X"16",X"34",X"14",X"00",X"00", + X"C3",X"87",X"3C",X"3C",X"A4",X"84",X"00",X"00",X"6F",X"6F",X"6F",X"6F",X"2F",X"0B",X"00",X"00", + X"00",X"00",X"80",X"C3",X"C3",X"C3",X"87",X"87",X"00",X"04",X"16",X"16",X"34",X"30",X"10",X"10", + X"00",X"44",X"FF",X"F3",X"E0",X"69",X"0F",X"C3",X"00",X"00",X"0F",X"0F",X"2B",X"6F",X"6F",X"6F", + X"87",X"87",X"87",X"C3",X"C3",X"C1",X"80",X"00",X"10",X"10",X"10",X"30",X"34",X"16",X"16",X"04", + X"C3",X"87",X"3C",X"3C",X"A4",X"B7",X"FF",X"44",X"6F",X"6F",X"6F",X"6F",X"2B",X"0F",X"0F",X"00", + X"61",X"E1",X"E1",X"E1",X"0F",X"0F",X"87",X"87",X"00",X"00",X"00",X"00",X"00",X"01",X"10",X"30", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"0E",X"0E",X"0E",X"08",X"0C",X"0C",X"1E",X"DE", + X"87",X"87",X"87",X"0F",X"D2",X"F0",X"30",X"CC",X"70",X"70",X"70",X"01",X"10",X"00",X"00",X"44", + X"80",X"80",X"00",X"00",X"00",X"00",X"00",X"88",X"EF",X"EF",X"EF",X"0E",X"E0",X"C0",X"00",X"44", + X"30",X"30",X"30",X"B4",X"B4",X"0F",X"B7",X"B7",X"00",X"00",X"00",X"44",X"10",X"10",X"74",X"30", + X"00",X"00",X"00",X"C0",X"E0",X"E0",X"2C",X"E0",X"00",X"00",X"80",X"80",X"C0",X"0F",X"8F",X"CF", + X"B7",X"B7",X"0F",X"B4",X"B4",X"30",X"30",X"30",X"74",X"30",X"10",X"54",X"00",X"00",X"00",X"00", + X"E0",X"2C",X"E0",X"E0",X"C0",X"00",X"00",X"00",X"CF",X"8F",X"0F",X"C0",X"80",X"80",X"00",X"00", + X"88",X"30",X"F0",X"D2",X"0F",X"87",X"87",X"87",X"22",X"00",X"00",X"10",X"01",X"70",X"70",X"70", + X"88",X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"99",X"00",X"C0",X"E0",X"0E",X"EF",X"EF",X"EF", + X"87",X"87",X"0F",X"0F",X"E1",X"E1",X"E1",X"61",X"30",X"10",X"01",X"00",X"00",X"00",X"00",X"00", + X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"DE",X"1E",X"0C",X"0C",X"08",X"0C",X"0E",X"0E", + X"40",X"68",X"2C",X"0F",X"0F",X"1F",X"1F",X"0F",X"00",X"01",X"03",X"43",X"43",X"61",X"61",X"01", + X"00",X"00",X"80",X"C0",X"C0",X"08",X"0C",X"48",X"00",X"00",X"10",X"3C",X"CF",X"EF",X"EF",X"CF", + X"87",X"C3",X"E1",X"E1",X"C0",X"00",X"00",X"00",X"00",X"10",X"30",X"70",X"30",X"10",X"00",X"00", + X"C0",X"91",X"80",X"44",X"00",X"00",X"00",X"00",X"0F",X"1E",X"3C",X"78",X"C0",X"11",X"22",X"00", + X"00",X"00",X"00",X"C0",X"E1",X"E1",X"C3",X"87",X"00",X"00",X"10",X"30",X"70",X"30",X"10",X"00", + X"00",X"00",X"00",X"88",X"44",X"80",X"91",X"C0",X"44",X"00",X"00",X"C0",X"78",X"3C",X"1E",X"0F", + X"0F",X"1F",X"1F",X"0F",X"0F",X"2C",X"68",X"40",X"01",X"61",X"61",X"43",X"43",X"03",X"01",X"00", + X"48",X"0C",X"08",X"C0",X"C0",X"80",X"00",X"00",X"CF",X"EF",X"EF",X"CF",X"3C",X"10",X"00",X"00", + X"C0",X"E0",X"F0",X"F0",X"E1",X"0F",X"0F",X"0F",X"00",X"00",X"10",X"10",X"00",X"00",X"01",X"01", + X"80",X"C0",X"86",X"0F",X"0F",X"0F",X"3C",X"28",X"10",X"30",X"30",X"83",X"0F",X"0F",X"0F",X"6F", + X"1F",X"97",X"C3",X"E1",X"30",X"00",X"44",X"22",X"10",X"10",X"44",X"00",X"11",X"00",X"00",X"00", + X"08",X"C0",X"E0",X"E0",X"C0",X"80",X"00",X"00",X"EF",X"EF",X"CF",X"1E",X"1C",X"00",X"00",X"00", + X"22",X"00",X"88",X"30",X"E1",X"C3",X"97",X"1F",X"00",X"00",X"00",X"11",X"00",X"44",X"10",X"10", + X"00",X"00",X"80",X"C0",X"E0",X"E0",X"C0",X"08",X"00",X"00",X"00",X"1C",X"1E",X"CF",X"EF",X"EF", + X"0F",X"0F",X"0F",X"E1",X"F0",X"F0",X"E0",X"C0",X"01",X"01",X"00",X"00",X"10",X"10",X"00",X"00", + X"28",X"3C",X"0F",X"0F",X"0F",X"86",X"C0",X"80",X"6F",X"0F",X"0F",X"0F",X"83",X"30",X"30",X"10", + X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"08",X"08",X"0E", + X"01",X"02",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0E",X"08",X"08",X"00",X"00",X"00",X"00",X"00", + X"F0",X"F1",X"F7",X"FF",X"FF",X"FF",X"FF",X"80",X"00",X"10",X"30",X"22",X"22",X"22",X"22",X"22", + X"00",X"00",X"C0",X"C0",X"E2",X"E2",X"E2",X"F3",X"80",X"FF",X"FF",X"FE",X"FC",X"FC",X"F8",X"70", + X"80",X"0C",X"0E",X"1F",X"08",X"34",X"00",X"00",X"22",X"22",X"02",X"01",X"07",X"01",X"01",X"00", + X"F3",X"F7",X"F7",X"77",X"66",X"C4",X"00",X"00",X"70",X"70",X"70",X"88",X"00",X"F0",X"00",X"00", + X"00",X"11",X"22",X"44",X"88",X"10",X"60",X"0C",X"00",X"00",X"00",X"00",X"00",X"01",X"05",X"03", + X"00",X"80",X"C0",X"E0",X"E8",X"FE",X"FF",X"FF",X"E0",X"70",X"30",X"30",X"77",X"FF",X"77",X"33", + X"0C",X"66",X"11",X"80",X"40",X"20",X"10",X"00",X"03",X"05",X"01",X"00",X"00",X"00",X"00",X"00", + X"F0",X"F0",X"F1",X"E6",X"EE",X"CC",X"88",X"00",X"30",X"70",X"F0",X"70",X"33",X"33",X"77",X"EE", + X"00",X"00",X"37",X"08",X"1E",X"0E",X"0C",X"88",X"00",X"01",X"01",X"07",X"01",X"02",X"20",X"20", + X"00",X"00",X"C8",X"60",X"70",X"F8",X"F8",X"FC",X"00",X"00",X"FF",X"00",X"80",X"77",X"77",X"77", + X"88",X"F0",X"F0",X"F0",X"F0",X"F8",X"FE",X"FF",X"20",X"20",X"20",X"20",X"20",X"33",X"11",X"00", + X"FC",X"EC",X"EC",X"EC",X"CC",X"CC",X"00",X"00",X"77",X"F7",X"F3",X"F3",X"F1",X"F0",X"F0",X"88", + X"00",X"33",X"77",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"15",X"17",X"15", + X"00",X"48",X"40",X"10",X"10",X"88",X"DC",X"DC",X"FF",X"FF",X"CC",X"CC",X"FF",X"FF",X"FF",X"1F", + X"EF",X"EF",X"EF",X"FF",X"FF",X"FE",X"FE",X"76",X"15",X"15",X"17",X"15",X"15",X"06",X"00",X"00", + X"DE",X"DC",X"D4",X"80",X"90",X"10",X"00",X"00",X"0F",X"7F",X"F8",X"E0",X"E0",X"D0",X"E0",X"C0", + X"00",X"33",X"77",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"15",X"17",X"15", + X"40",X"48",X"00",X"10",X"00",X"98",X"DC",X"CC",X"FF",X"FF",X"CC",X"CC",X"FF",X"FF",X"FF",X"1F", + X"EF",X"EF",X"EF",X"FF",X"FF",X"FE",X"FE",X"76",X"15",X"15",X"17",X"15",X"15",X"06",X"00",X"00", + X"DE",X"CC",X"D4",X"90",X"80",X"10",X"00",X"00",X"0F",X"7F",X"F8",X"E0",X"E0",X"D0",X"E0",X"C0", + X"00",X"23",X"47",X"7F",X"FF",X"FE",X"FE",X"FE",X"00",X"00",X"00",X"01",X"07",X"00",X"11",X"11", + X"00",X"00",X"00",X"98",X"98",X"C4",X"D0",X"D2",X"00",X"2E",X"FF",X"F3",X"F0",X"F0",X"F0",X"F0", + X"FE",X"FE",X"FE",X"FF",X"7F",X"47",X"23",X"00",X"11",X"11",X"00",X"07",X"01",X"00",X"00",X"00", + X"52",X"50",X"C4",X"98",X"98",X"00",X"00",X"00",X"F0",X"F0",X"E0",X"F0",X"F3",X"FF",X"2E",X"00", + X"76",X"FE",X"FE",X"FF",X"FF",X"EF",X"EF",X"EF",X"00",X"00",X"06",X"15",X"15",X"17",X"15",X"15", + X"00",X"00",X"10",X"80",X"90",X"D4",X"CC",X"DE",X"C0",X"E0",X"D0",X"E0",X"E0",X"F8",X"7F",X"0F", + X"FF",X"FF",X"FF",X"FF",X"FF",X"77",X"33",X"00",X"15",X"17",X"15",X"00",X"00",X"00",X"00",X"00", + X"CC",X"DC",X"98",X"00",X"10",X"40",X"48",X"00",X"1F",X"FF",X"FF",X"FF",X"CC",X"CC",X"FF",X"FF", + X"76",X"FE",X"FE",X"FF",X"FF",X"EF",X"EF",X"EF",X"00",X"00",X"06",X"15",X"15",X"17",X"15",X"15", + X"00",X"00",X"10",X"90",X"80",X"D4",X"DC",X"CE",X"C0",X"E0",X"D0",X"E0",X"E0",X"F8",X"7F",X"0F", + X"FF",X"FF",X"FF",X"FF",X"FF",X"77",X"33",X"00",X"15",X"17",X"15",X"00",X"00",X"00",X"00",X"00", + X"DC",X"DC",X"88",X"10",X"10",X"00",X"48",X"40",X"1F",X"FF",X"FF",X"FF",X"CC",X"CC",X"FF",X"FF", + X"00",X"00",X"11",X"77",X"7F",X"FF",X"EF",X"CF",X"00",X"00",X"00",X"01",X"03",X"02",X"06",X"15", + X"10",X"CE",X"DC",X"88",X"00",X"10",X"98",X"DC",X"00",X"77",X"FF",X"FF",X"FF",X"7F",X"3F",X"1F", + X"BF",X"FE",X"FC",X"F8",X"F0",X"F0",X"F0",X"30",X"17",X"33",X"37",X"33",X"33",X"11",X"00",X"00", + X"CC",X"DC",X"CE",X"DC",X"98",X"98",X"00",X"10",X"CF",X"F7",X"F3",X"F1",X"F1",X"B1",X"73",X"C4", + X"30",X"F0",X"F0",X"F0",X"F8",X"FC",X"FE",X"BF",X"00",X"00",X"11",X"33",X"33",X"37",X"33",X"17", + X"10",X"10",X"88",X"98",X"DC",X"CE",X"DC",X"DC",X"C4",X"73",X"B1",X"F1",X"F1",X"F3",X"F7",X"CF", + X"CF",X"EF",X"FF",X"7F",X"77",X"11",X"00",X"00",X"15",X"06",X"02",X"03",X"01",X"00",X"00",X"00", + X"DC",X"88",X"10",X"00",X"88",X"DC",X"CE",X"10",X"1F",X"3F",X"7F",X"FF",X"FF",X"FF",X"77",X"00", + X"E8",X"1F",X"DF",X"E3",X"E3",X"CF",X"C3",X"ED",X"11",X"21",X"21",X"57",X"57",X"43",X"43",X"12", + X"00",X"00",X"00",X"08",X"08",X"8C",X"8D",X"3F",X"00",X"00",X"0E",X"87",X"B7",X"9F",X"8F",X"87", + X"ED",X"C3",X"CF",X"E3",X"E3",X"DF",X"1F",X"E8",X"56",X"43",X"43",X"57",X"57",X"21",X"21",X"11", + X"3F",X"1D",X"0C",X"08",X"08",X"00",X"00",X"00",X"87",X"8F",X"8F",X"87",X"87",X"0E",X"00",X"00", + X"E6",X"1E",X"DE",X"E3",X"E3",X"CF",X"C3",X"ED",X"10",X"23",X"23",X"53",X"53",X"47",X"47",X"52", + X"00",X"00",X"00",X"08",X"08",X"8C",X"9D",X"3F",X"00",X"00",X"0E",X"8F",X"BF",X"97",X"87",X"8F", + X"ED",X"C3",X"CF",X"E3",X"E3",X"DE",X"1E",X"E6",X"52",X"47",X"47",X"53",X"53",X"23",X"23",X"10", + X"3F",X"1D",X"0C",X"08",X"08",X"00",X"00",X"00",X"8F",X"87",X"87",X"8F",X"8F",X"0E",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"CC",X"EE",X"FF",X"00",X"00",X"00",X"00",X"00",X"11",X"33",X"77", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"86",X"00",X"00",X"00",X"00",X"00",X"00",X"25",X"1E", + X"FF",X"FF",X"EE",X"CC",X"00",X"00",X"00",X"00",X"77",X"77",X"33",X"11",X"00",X"00",X"00",X"00", + X"78",X"80",X"20",X"00",X"00",X"00",X"00",X"00",X"0F",X"34",X"52",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"CC",X"EE",X"FF",X"00",X"00",X"00",X"00",X"00",X"11",X"33",X"77", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"68",X"00",X"00",X"00",X"00",X"00",X"00",X"52",X"E1", + X"FF",X"FF",X"EE",X"CC",X"00",X"00",X"00",X"00",X"77",X"77",X"33",X"11",X"00",X"00",X"00",X"00", + X"87",X"08",X"02",X"00",X"00",X"00",X"00",X"00",X"F0",X"43",X"25",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"10",X"00",X"14",X"5B",X"3E",X"78",X"00",X"00",X"00",X"02",X"01",X"00",X"00",X"50", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"18",X"84",X"CA", + X"16",X"29",X"10",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"B4",X"84",X"02",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"01",X"13",X"36",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"0C",X"84", + X"12",X"01",X"11",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"08",X"80",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"64",X"70",X"F5",X"E1",X"DA",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"00",X"00",X"00",X"84",X"C0",X"58",X"F4",X"3D", + X"C3",X"A5",X"72",X"21",X"22",X"00",X"00",X"00",X"00",X"00",X"10",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"B4",X"E8",X"20",X"80",X"00",X"00",X"00",X"00", + X"80",X"C0",X"42",X"60",X"B4",X"DA",X"87",X"D3",X"00",X"44",X"00",X"01",X"64",X"41",X"30",X"10", + X"80",X"22",X"00",X"08",X"74",X"C0",X"80",X"00",X"00",X"18",X"30",X"F0",X"7C",X"5A",X"78",X"2C", + X"0F",X"1E",X"A7",X"C3",X"5A",X"65",X"61",X"90",X"31",X"61",X"10",X"30",X"60",X"50",X"44",X"00", + X"A4",X"01",X"80",X"E0",X"30",X"08",X"22",X"80",X"87",X"9E",X"3C",X"5A",X"78",X"E0",X"30",X"11", + X"EE",X"FF",X"99",X"88",X"00",X"77",X"FF",X"88",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"66",X"11",X"FF",X"EE",X"00",X"EE",X"FF",X"11", + X"FF",X"77",X"00",X"77",X"FF",X"88",X"FF",X"77",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"EE",X"00",X"EE",X"FF",X"11",X"FF",X"EE", + X"44",X"88",X"FF",X"77",X"00",X"77",X"FF",X"88",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"22",X"99",X"FF",X"66",X"00",X"EE",X"FF",X"11", + X"FF",X"77",X"00",X"77",X"FF",X"88",X"FF",X"77",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"EE",X"00",X"EE",X"FF",X"11",X"FF",X"EE", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/cmd_col_rom.vhd b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/cmd_col_rom.vhd new file mode 100644 index 00000000..1eef2d60 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/cmd_col_rom.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity cmd_col_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of cmd_col_rom is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"01",X"02",X"04",X"0F",X"01",X"0F",X"0D",X"08",X"01",X"06",X"0C",X"0B",X"01",X"09",X"06",X"03", + X"01",X"03",X"04",X"05",X"01",X"05",X"0F",X"02",X"01",X"05",X"0F",X"02",X"01",X"02",X"05",X"08", + X"01",X"02",X"0F",X"04",X"01",X"04",X"03",X"0F",X"01",X"0D",X"09",X"0F",X"01",X"0F",X"08",X"00", + X"01",X"0F",X"09",X"02",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"02",X"04",X"0F",X"00",X"0F",X"0D",X"08",X"00",X"06",X"0C",X"0B",X"00",X"09",X"06",X"03", + X"00",X"03",X"04",X"05",X"00",X"05",X"0F",X"02",X"00",X"05",X"0F",X"02",X"00",X"02",X"05",X"08", + X"00",X"02",X"0F",X"04",X"00",X"04",X"03",X"0F",X"00",X"0D",X"09",X"0F",X"00",X"0F",X"08",X"00", + X"00",X"0F",X"09",X"02",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"01",X"02",X"04",X"0F",X"01",X"0F",X"0D",X"08",X"01",X"06",X"0C",X"0B",X"01",X"09",X"06",X"03", + X"01",X"03",X"04",X"05",X"01",X"05",X"0F",X"02",X"01",X"05",X"0F",X"02",X"01",X"02",X"05",X"08", + X"01",X"02",X"0F",X"04",X"01",X"04",X"03",X"0F",X"01",X"0D",X"09",X"0F",X"01",X"0F",X"08",X"00", + X"01",X"0F",X"09",X"02",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"02",X"04",X"0F",X"00",X"0F",X"0D",X"08",X"00",X"06",X"0C",X"0B",X"00",X"09",X"06",X"03", + X"00",X"03",X"04",X"05",X"00",X"05",X"0F",X"02",X"00",X"05",X"0F",X"02",X"00",X"02",X"05",X"08", + X"00",X"02",X"0F",X"04",X"00",X"04",X"03",X"0F",X"00",X"0D",X"09",X"0F",X"00",X"0F",X"08",X"00", + X"00",X"0F",X"09",X"02",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/cmd_dot_rom.vhd b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/cmd_dot_rom.vhd new file mode 100644 index 00000000..38ad297c --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/cmd_dot_rom.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity cmd_dot_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of cmd_dot_rom is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"03",X"03",X"03",X"01",X"03",X"03",X"01",X"03",X"03",X"01",X"03",X"03",X"01",X"03",X"03",X"03", + X"01",X"03",X"03",X"03",X"03",X"01",X"03",X"03",X"03",X"03",X"01",X"03",X"03",X"03",X"03",X"01", + X"02",X"03",X"03",X"02",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"02",X"03",X"03",X"02", + X"03",X"02",X"02",X"03",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"03",X"02",X"02",X"03", + X"03",X"03",X"03",X"03",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"03",X"03",X"03",X"03", + X"01",X"03",X"02",X"01",X"03",X"02",X"01",X"02",X"02",X"01",X"02",X"03",X"01",X"02",X"03",X"01", + X"03",X"03",X"03",X"02",X"03",X"02",X"02",X"03",X"03",X"02",X"02",X"03",X"02",X"03",X"03",X"03", + X"03",X"01",X"01",X"03",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"03",X"01",X"01",X"01", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/cmd_pal_rom.vhd b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/cmd_pal_rom.vhd new file mode 100644 index 00000000..76133e93 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/cmd_pal_rom.vhd @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity cmd_pal_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of cmd_pal_rom is + type rom is array(0 to 31) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"A0",X"25",X"3F",X"07",X"A4",X"2D",X"5D",X"27",X"A7",X"E0",X"B7",X"20",X"84",X"7A",X"FF", + X"00",X"3F",X"07",X"00",X"00",X"3F",X"07",X"00",X"00",X"3F",X"07",X"00",X"00",X"3F",X"07",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/cmd_prg_rom.vhd b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/cmd_prg_rom.vhd new file mode 100644 index 00000000..3b2b211f --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/cmd_prg_rom.vhd @@ -0,0 +1,1302 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity cmd_prg_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(14 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of cmd_prg_rom is + type rom is array(0 to 20479) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"C3",X"A0",X"00",X"2A",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20", + X"20",X"20",X"31",X"39",X"38",X"33",X"2E",X"30",X"39",X"20",X"20",X"20",X"20",X"42",X"59",X"20", + X"20",X"45",X"4C",X"53",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20", + X"20",X"20",X"20",X"20",X"2A",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"3A",X"00",X"A1",X"CB",X"5F",X"C0",X"3E",X"03",X"32",X"E4",X"9B",X"C9",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"F5",X"AF",X"32",X"81",X"A1",X"C5",X"D5",X"E5",X"DD",X"E5", + X"FD",X"E5",X"00",X"00",X"00",X"CD",X"5F",X"11",X"CD",X"C2",X"11",X"CD",X"88",X"0B",X"CD",X"56", + X"0F",X"CD",X"BD",X"0F",X"CD",X"EC",X"0A",X"3E",X"00",X"32",X"80",X"A0",X"FD",X"E1",X"DD",X"E1", + X"E1",X"D1",X"C1",X"3E",X"01",X"32",X"81",X"A1",X"F1",X"ED",X"45",X"00",X"00",X"00",X"00",X"00", + X"AF",X"32",X"81",X"A1",X"3E",X"01",X"32",X"83",X"A1",X"ED",X"47",X"AF",X"21",X"00",X"98",X"11", + X"01",X"98",X"01",X"FF",X"07",X"77",X"ED",X"B0",X"31",X"FF",X"9F",X"CD",X"01",X"07",X"CD",X"DB", + X"0A",X"21",X"FF",X"FF",X"22",X"F0",X"9B",X"AF",X"32",X"E6",X"9B",X"AF",X"32",X"F2",X"9B",X"32", + X"F3",X"9B",X"CD",X"02",X"06",X"3A",X"F4",X"9B",X"2F",X"47",X"3A",X"F5",X"9B",X"2F",X"A0",X"CA", + X"C6",X"01",X"3A",X"F6",X"9B",X"A7",X"C2",X"0D",X"01",X"3A",X"F7",X"9B",X"47",X"3A",X"F8",X"9B", + X"B0",X"CA",X"CB",X"00",X"2A",X"F0",X"9B",X"7C",X"B5",X"CA",X"3F",X"01",X"2B",X"22",X"F0",X"9B", + X"CD",X"CE",X"01",X"CD",X"33",X"01",X"AF",X"32",X"F9",X"9B",X"C3",X"E2",X"00",X"CD",X"B5",X"10", + X"CD",X"F2",X"12",X"CD",X"3F",X"02",X"AF",X"32",X"F9",X"9B",X"3A",X"F2",X"9B",X"A7",X"C2",X"6A", + X"01",X"3A",X"F6",X"9B",X"FE",X"02",X"DA",X"13",X"01",X"3A",X"F3",X"9B",X"A7",X"C2",X"78",X"01", + X"C3",X"13",X"01",X"3A",X"F9",X"9B",X"A7",X"C8",X"CD",X"B5",X"10",X"CD",X"F2",X"12",X"C9",X"3A", + X"FA",X"9B",X"A7",X"C2",X"56",X"01",X"3E",X"FF",X"32",X"FA",X"9B",X"3A",X"F7",X"9B",X"47",X"3A", + X"F8",X"9B",X"80",X"C3",X"C7",X"00",X"3A",X"F7",X"9B",X"47",X"3A",X"F8",X"9B",X"80",X"47",X"B8", + X"CA",X"CB",X"00",X"AF",X"32",X"FA",X"9B",X"C3",X"C1",X"00",X"AF",X"32",X"E3",X"9B",X"3A",X"F6", + X"9B",X"3D",X"32",X"F6",X"9B",X"C3",X"85",X"01",X"3E",X"FF",X"32",X"E3",X"9B",X"3A",X"F6",X"9B", + X"D6",X"02",X"32",X"F6",X"9B",X"AF",X"32",X"F2",X"9B",X"32",X"F3",X"9B",X"CD",X"16",X"07",X"CD", + X"3E",X"04",X"CD",X"3D",X"0C",X"3A",X"EE",X"9B",X"47",X"3A",X"EF",X"9B",X"A0",X"CA",X"8F",X"01", + X"AF",X"32",X"FC",X"9B",X"32",X"6C",X"9C",X"32",X"83",X"A1",X"32",X"54",X"9A",X"3E",X"FF",X"32", + X"FB",X"9B",X"CD",X"F2",X"12",X"AF",X"32",X"5D",X"9A",X"CD",X"2B",X"37",X"3A",X"6C",X"9C",X"A7", + X"CA",X"B9",X"01",X"C3",X"C1",X"00",X"3E",X"FF",X"32",X"F6",X"9B",X"C3",X"1A",X"01",X"3A",X"F6", + X"9B",X"A7",X"C0",X"CD",X"36",X"04",X"21",X"C2",X"3B",X"CD",X"84",X"10",X"3A",X"F7",X"9B",X"A7", + X"C2",X"EB",X"01",X"3A",X"F8",X"9B",X"A7",X"C2",X"28",X"02",X"C9",X"3A",X"F4",X"9B",X"4F",X"06", + X"00",X"CB",X"21",X"DD",X"21",X"77",X"3C",X"DD",X"09",X"DD",X"6E",X"00",X"DD",X"66",X"01",X"11", + X"E3",X"01",X"D5",X"ED",X"5B",X"59",X"9A",X"01",X"FF",X"03",X"7B",X"A1",X"4F",X"7A",X"A0",X"B1", + X"CC",X"84",X"10",X"E5",X"EB",X"11",X"00",X"02",X"19",X"EB",X"E1",X"01",X"FF",X"03",X"7B",X"A1", + X"4F",X"7A",X"A0",X"B1",X"CA",X"DD",X"0F",X"C9",X"3A",X"F5",X"9B",X"4F",X"06",X"00",X"CB",X"21", + X"DD",X"21",X"26",X"3D",X"DD",X"09",X"DD",X"6E",X"00",X"DD",X"66",X"01",X"C3",X"03",X"02",X"CD", + X"36",X"04",X"21",X"85",X"3C",X"CD",X"DD",X"0F",X"21",X"D6",X"3B",X"CD",X"DD",X"0F",X"21",X"C2", + X"3B",X"CD",X"DD",X"0F",X"3A",X"F6",X"9B",X"FE",X"02",X"DA",X"65",X"02",X"21",X"B0",X"3B",X"22", + X"85",X"9C",X"C3",X"6B",X"02",X"21",X"9F",X"3B",X"22",X"85",X"9C",X"2A",X"59",X"9A",X"01",X"FF", + X"03",X"79",X"A5",X"4F",X"78",X"A4",X"B1",X"CA",X"8B",X"02",X"01",X"00",X"02",X"09",X"01",X"FF", + X"03",X"79",X"A5",X"4F",X"78",X"A4",X"B1",X"CA",X"98",X"02",X"C9",X"21",X"8A",X"3B",X"CD",X"84", + X"10",X"2A",X"85",X"9C",X"CD",X"84",X"10",X"C9",X"2A",X"85",X"9C",X"CD",X"DD",X"0F",X"C9",X"3A", + X"F4",X"9B",X"FE",X"00",X"CA",X"E7",X"02",X"FE",X"01",X"CA",X"2F",X"03",X"FE",X"02",X"CA",X"5F", + X"03",X"FE",X"03",X"CA",X"77",X"03",X"FE",X"04",X"CA",X"FF",X"02",X"FE",X"05",X"CA",X"17",X"03", + X"C3",X"47",X"03",X"3A",X"F5",X"9B",X"FE",X"00",X"CA",X"8F",X"03",X"FE",X"01",X"CA",X"D6",X"03", + X"FE",X"02",X"CA",X"06",X"04",X"FE",X"03",X"CA",X"1E",X"04",X"FE",X"04",X"CA",X"A6",X"03",X"FE", + X"05",X"CA",X"BE",X"03",X"C3",X"EE",X"03",X"3A",X"F7",X"9B",X"C6",X"01",X"32",X"F7",X"9B",X"FE", + X"01",X"C0",X"3A",X"F6",X"9B",X"C6",X"01",X"32",X"F6",X"9B",X"AF",X"32",X"F7",X"9B",X"C9",X"3A", + X"F7",X"9B",X"C6",X"01",X"32",X"F7",X"9B",X"FE",X"01",X"C0",X"3A",X"F6",X"9B",X"C6",X"02",X"32", + X"F6",X"9B",X"AF",X"32",X"F7",X"9B",X"C9",X"3A",X"F7",X"9B",X"C6",X"01",X"32",X"F7",X"9B",X"FE", + X"01",X"C0",X"3A",X"F6",X"9B",X"C6",X"03",X"32",X"F6",X"9B",X"AF",X"32",X"F7",X"9B",X"C9",X"3A", + X"F7",X"9B",X"C6",X"01",X"32",X"F7",X"9B",X"FE",X"02",X"C0",X"3A",X"F6",X"9B",X"C6",X"01",X"32", + X"F6",X"9B",X"AF",X"32",X"F7",X"9B",X"C9",X"3A",X"F7",X"9B",X"C6",X"01",X"32",X"F7",X"9B",X"FE", + X"02",X"C0",X"3A",X"F6",X"9B",X"C6",X"03",X"32",X"F6",X"9B",X"AF",X"32",X"F7",X"9B",X"C9",X"3A", + X"F7",X"9B",X"C6",X"01",X"32",X"F7",X"9B",X"FE",X"03",X"C0",X"3A",X"F6",X"9B",X"C6",X"01",X"32", + X"F6",X"9B",X"AF",X"32",X"F7",X"9B",X"C9",X"3A",X"F7",X"9B",X"C6",X"01",X"32",X"F7",X"9B",X"FE", + X"04",X"C0",X"3A",X"F6",X"9B",X"C6",X"01",X"32",X"F6",X"9B",X"AF",X"32",X"F7",X"9B",X"C9",X"3A", + X"F8",X"9B",X"C6",X"01",X"32",X"F8",X"9B",X"FE",X"01",X"C0",X"3A",X"F6",X"9B",X"3C",X"32",X"F6", + X"9B",X"AF",X"32",X"F8",X"9B",X"C9",X"3A",X"F8",X"9B",X"C6",X"01",X"32",X"F8",X"9B",X"FE",X"01", + X"C0",X"3A",X"F6",X"9B",X"C6",X"02",X"32",X"F6",X"9B",X"AF",X"32",X"F8",X"9B",X"C9",X"3A",X"F8", + X"9B",X"C6",X"01",X"32",X"F8",X"9B",X"FE",X"01",X"C0",X"3A",X"F6",X"9B",X"C6",X"03",X"32",X"F6", + X"9B",X"AF",X"32",X"F8",X"9B",X"C9",X"3A",X"F8",X"9B",X"C6",X"01",X"32",X"F8",X"9B",X"FE",X"02", + X"C0",X"3A",X"F6",X"9B",X"C6",X"01",X"32",X"F6",X"9B",X"AF",X"32",X"F8",X"9B",X"C9",X"3A",X"F8", + X"9B",X"C6",X"01",X"32",X"F8",X"9B",X"FE",X"02",X"C0",X"3A",X"F6",X"9B",X"C6",X"03",X"32",X"F6", + X"9B",X"AF",X"32",X"F8",X"9B",X"C9",X"3A",X"F8",X"9B",X"C6",X"01",X"32",X"F8",X"9B",X"FE",X"03", + X"C0",X"3A",X"F6",X"9B",X"C6",X"01",X"32",X"F6",X"9B",X"AF",X"32",X"F8",X"9B",X"C9",X"3A",X"F8", + X"9B",X"C6",X"01",X"32",X"F8",X"9B",X"FE",X"04",X"C0",X"3A",X"F6",X"9B",X"C6",X"01",X"32",X"F6", + X"9B",X"AF",X"32",X"F8",X"9B",X"C9",X"2A",X"59",X"9A",X"23",X"22",X"59",X"9A",X"C9",X"3A",X"66", + X"9A",X"FE",X"0F",X"CA",X"55",X"04",X"FE",X"1F",X"CA",X"EE",X"04",X"CD",X"DB",X"0A",X"CD",X"8F", + X"07",X"CD",X"DB",X"0A",X"C9",X"CD",X"F2",X"12",X"3A",X"5D",X"9A",X"A7",X"C2",X"7E",X"04",X"3A", + X"8F",X"9C",X"A7",X"3E",X"00",X"32",X"8F",X"9C",X"C2",X"E1",X"04",X"3A",X"90",X"9C",X"A7",X"3E", + X"00",X"32",X"90",X"9C",X"C2",X"BB",X"04",X"DD",X"21",X"67",X"9A",X"C3",X"9A",X"04",X"3A",X"91", + X"9C",X"A7",X"3E",X"00",X"32",X"91",X"9C",X"C2",X"E7",X"04",X"3A",X"92",X"9C",X"A7",X"3E",X"00", + X"32",X"92",X"9C",X"C2",X"BB",X"04",X"DD",X"21",X"25",X"9B",X"DD",X"7E",X"00",X"32",X"8B",X"9C", + X"DD",X"7E",X"01",X"32",X"53",X"9A",X"DD",X"E5",X"E1",X"23",X"23",X"11",X"40",X"9A",X"01",X"11", + X"00",X"ED",X"B0",X"11",X"50",X"99",X"01",X"A0",X"00",X"ED",X"B0",X"CD",X"1E",X"14",X"CD",X"D1", + X"12",X"CD",X"09",X"14",X"CD",X"B3",X"12",X"CD",X"F7",X"0F",X"CD",X"2B",X"11",X"CD",X"5C",X"0E", + X"CD",X"E1",X"0A",X"3E",X"1F",X"32",X"66",X"9A",X"3E",X"03",X"CD",X"09",X"11",X"CD",X"E1",X"0A", + X"C9",X"CD",X"A3",X"12",X"C3",X"BB",X"04",X"AF",X"32",X"8B",X"9C",X"C3",X"E1",X"04",X"CD",X"6E", + X"15",X"CD",X"D0",X"20",X"CD",X"B7",X"21",X"CD",X"3B",X"24",X"CD",X"CF",X"25",X"CD",X"0B",X"28", + X"CD",X"AD",X"19",X"CD",X"0A",X"05",X"CD",X"12",X"05",X"C9",X"3A",X"59",X"9A",X"3C",X"32",X"59", + X"9A",X"C9",X"3A",X"51",X"9A",X"A7",X"CA",X"2D",X"05",X"3E",X"00",X"32",X"66",X"9A",X"32",X"51", + X"9A",X"32",X"8C",X"9C",X"CD",X"DB",X"0A",X"3E",X"08",X"CD",X"09",X"11",X"C9",X"3A",X"8B",X"9C", + X"FE",X"10",X"D8",X"DD",X"21",X"50",X"99",X"01",X"20",X"00",X"16",X"05",X"3E",X"00",X"DD",X"B6", + X"00",X"DD",X"09",X"15",X"C2",X"3E",X"05",X"A7",X"C0",X"AF",X"32",X"8B",X"9C",X"3E",X"06",X"CD", + X"09",X"11",X"CD",X"AA",X"05",X"CD",X"98",X"05",X"3A",X"40",X"9A",X"3C",X"32",X"40",X"9A",X"FE", + X"04",X"D2",X"8E",X"05",X"CD",X"0D",X"13",X"21",X"41",X"9A",X"11",X"42",X"9A",X"01",X"10",X"00", + X"36",X"00",X"ED",X"B0",X"3E",X"0F",X"32",X"66",X"9A",X"3A",X"5D",X"9A",X"A7",X"C2",X"86",X"05", + X"3E",X"FF",X"32",X"90",X"9C",X"C9",X"3E",X"FF",X"32",X"92",X"9C",X"C9",X"04",X"C9",X"AF",X"32", + X"40",X"9A",X"CD",X"D6",X"10",X"C3",X"64",X"05",X"3A",X"53",X"9A",X"3C",X"FE",X"04",X"D2",X"A5", + X"05",X"32",X"53",X"9A",X"C9",X"AF",X"32",X"53",X"9A",X"C9",X"CD",X"B5",X"10",X"CD",X"F2",X"12", + X"21",X"B0",X"44",X"CD",X"84",X"10",X"21",X"B9",X"44",X"CD",X"84",X"10",X"16",X"03",X"CD",X"51", + X"36",X"21",X"41",X"9A",X"0E",X"08",X"06",X"00",X"7E",X"A7",X"CC",X"8C",X"05",X"23",X"23",X"0D", + X"C2",X"C8",X"05",X"78",X"32",X"2B",X"86",X"4F",X"06",X"00",X"DD",X"21",X"C3",X"44",X"CB",X"21", + X"CB",X"10",X"DD",X"09",X"DD",X"6E",X"00",X"DD",X"66",X"01",X"22",X"5B",X"9A",X"DD",X"21",X"11", + X"45",X"DD",X"09",X"DD",X"6E",X"00",X"DD",X"66",X"01",X"CD",X"84",X"10",X"3E",X"08",X"CD",X"09", + X"11",X"C9",X"3A",X"E6",X"9B",X"A7",X"CA",X"5D",X"06",X"FE",X"0F",X"CA",X"92",X"06",X"CD",X"3E", + X"04",X"CD",X"21",X"06",X"3A",X"EE",X"9B",X"A7",X"C8",X"CD",X"CA",X"06",X"AF",X"32",X"E6",X"9B", + X"C9",X"3A",X"59",X"9A",X"E6",X"1F",X"C0",X"2A",X"E7",X"9B",X"23",X"22",X"E7",X"9B",X"E5",X"01", + X"A0",X"00",X"A7",X"ED",X"42",X"E1",X"D2",X"56",X"06",X"CB",X"3C",X"CB",X"1D",X"CB",X"3C",X"CB", + X"1D",X"01",X"D9",X"44",X"09",X"7E",X"32",X"54",X"9A",X"CB",X"45",X"C8",X"AF",X"32",X"55",X"9A", + X"3E",X"FF",X"32",X"56",X"9A",X"C9",X"21",X"00",X"00",X"22",X"E7",X"9B",X"C9",X"CD",X"B5",X"10", + X"CD",X"F2",X"12",X"CD",X"5C",X"0B",X"CD",X"DB",X"0A",X"AF",X"32",X"5D",X"9A",X"32",X"E3",X"9B", + X"32",X"EE",X"9B",X"3E",X"00",X"32",X"E4",X"9B",X"3E",X"0F",X"32",X"E6",X"9B",X"21",X"00",X"00", + X"22",X"E7",X"9B",X"22",X"87",X"9C",X"3E",X"01",X"32",X"EA",X"9B",X"32",X"52",X"9A",X"CD",X"A3", + X"12",X"C9",X"CD",X"E4",X"06",X"CD",X"0A",X"05",X"2A",X"E7",X"9B",X"01",X"FA",X"00",X"A7",X"ED", + X"42",X"D8",X"3E",X"08",X"CD",X"09",X"11",X"3E",X"FF",X"32",X"E6",X"9B",X"3E",X"0F",X"32",X"66", + X"9A",X"3E",X"FF",X"32",X"8F",X"9C",X"AF",X"32",X"90",X"9C",X"32",X"EE",X"9B",X"2F",X"32",X"EF", + X"9B",X"3E",X"01",X"32",X"52",X"9A",X"CD",X"F2",X"12",X"C9",X"3A",X"E9",X"9B",X"FE",X"03",X"D2", + X"D7",X"06",X"3C",X"32",X"E9",X"9B",X"C9",X"AF",X"32",X"E9",X"9B",X"CD",X"A5",X"3A",X"3E",X"08", + X"CD",X"09",X"11",X"C9",X"3A",X"59",X"9A",X"E6",X"7F",X"C0",X"CD",X"63",X"08",X"CD",X"9D",X"08", + X"CD",X"16",X"09",X"CD",X"83",X"0A",X"CD",X"B1",X"0A",X"2A",X"E7",X"9B",X"23",X"22",X"E7",X"9B", + X"C9",X"CD",X"B5",X"10",X"CD",X"F2",X"12",X"CD",X"0D",X"13",X"CD",X"6B",X"12",X"CD",X"D9",X"11", + X"3E",X"01",X"32",X"81",X"A1",X"C9",X"CD",X"B5",X"10",X"CD",X"FB",X"10",X"CD",X"07",X"0F",X"CD", + X"F2",X"12",X"CD",X"0D",X"13",X"CD",X"F7",X"0F",X"CD",X"A3",X"12",X"21",X"00",X"00",X"22",X"5B", + X"9A",X"3E",X"0F",X"32",X"66",X"9A",X"3E",X"01",X"32",X"EA",X"9B",X"32",X"EB",X"9B",X"32",X"52", + X"9A",X"CD",X"D5",X"0C",X"AF",X"32",X"EC",X"9B",X"32",X"ED",X"9B",X"32",X"51",X"9A",X"32",X"53", + X"9A",X"32",X"E6",X"9B",X"32",X"8B",X"9C",X"32",X"8C",X"9C",X"CD",X"B3",X"12",X"3A",X"E3",X"9B", + X"A7",X"C2",X"77",X"07",X"AF",X"3A",X"5D",X"9A",X"32",X"90",X"9C",X"2F",X"32",X"EF",X"9B",X"32", + X"8F",X"9C",X"AF",X"32",X"EE",X"9B",X"C9",X"AF",X"32",X"5D",X"9A",X"32",X"EF",X"9B",X"32",X"90", + X"9C",X"32",X"92",X"9C",X"3E",X"FF",X"32",X"91",X"9C",X"32",X"8F",X"9C",X"C3",X"72",X"07",X"CD", + X"37",X"08",X"CD",X"0D",X"13",X"CD",X"F2",X"12",X"3A",X"E3",X"9B",X"A7",X"C2",X"BE",X"07",X"3A", + X"E4",X"9B",X"A7",X"CA",X"B0",X"07",X"3D",X"32",X"E4",X"9B",X"3E",X"0F",X"32",X"66",X"9A",X"C9", + X"CD",X"51",X"11",X"3E",X"08",X"CD",X"09",X"11",X"3E",X"FF",X"32",X"EE",X"9B",X"C9",X"3A",X"5D", + X"9A",X"A7",X"C2",X"FE",X"07",X"3A",X"E4",X"9B",X"A7",X"CA",X"E1",X"07",X"3D",X"32",X"E4",X"9B", + X"3A",X"EF",X"9B",X"A7",X"CA",X"F3",X"07",X"AF",X"32",X"5D",X"9A",X"3E",X"0F",X"32",X"66",X"9A", + X"C9",X"CD",X"43",X"11",X"3E",X"08",X"CD",X"09",X"11",X"3E",X"FF",X"32",X"EE",X"9B",X"3A",X"EF", + X"9B",X"A7",X"C0",X"3E",X"FF",X"32",X"5D",X"9A",X"3E",X"0F",X"32",X"66",X"9A",X"C9",X"3A",X"E5", + X"9B",X"A7",X"CA",X"1B",X"08",X"3D",X"32",X"E5",X"9B",X"3A",X"EE",X"9B",X"A7",X"CA",X"2D",X"08", + X"3E",X"FF",X"32",X"5D",X"9A",X"3E",X"0F",X"32",X"66",X"9A",X"C9",X"CD",X"4A",X"11",X"3E",X"08", + X"CD",X"09",X"11",X"3E",X"FF",X"32",X"EF",X"9B",X"3A",X"EE",X"9B",X"A7",X"C0",X"AF",X"32",X"5D", + X"9A",X"3E",X"0F",X"32",X"66",X"9A",X"C9",X"3A",X"5D",X"9A",X"A7",X"C2",X"44",X"08",X"11",X"67", + X"9A",X"C3",X"47",X"08",X"11",X"25",X"9B",X"3A",X"8B",X"9C",X"12",X"21",X"53",X"9A",X"13",X"7E", + X"12",X"13",X"21",X"40",X"9A",X"01",X"11",X"00",X"ED",X"B0",X"21",X"50",X"99",X"01",X"A0",X"00", + X"ED",X"B0",X"C9",X"3A",X"87",X"9C",X"A7",X"C0",X"DD",X"21",X"B3",X"40",X"ED",X"4B",X"E7",X"9B", + X"CB",X"21",X"CB",X"10",X"DD",X"09",X"DD",X"7E",X"00",X"FE",X"FF",X"CA",X"97",X"08",X"FE",X"F0", + X"CA",X"8D",X"08",X"DD",X"56",X"00",X"DD",X"5E",X"01",X"CD",X"9C",X"33",X"C9",X"DD",X"56",X"00", + X"DD",X"5E",X"01",X"CD",X"B0",X"33",X"C9",X"3E",X"FF",X"32",X"87",X"9C",X"C9",X"2A",X"E7",X"9B", + X"01",X"28",X"00",X"A7",X"ED",X"42",X"D8",X"DD",X"21",X"E7",X"42",X"0E",X"07",X"DD",X"5E",X"00", + X"DD",X"56",X"01",X"A7",X"ED",X"52",X"CA",X"C4",X"08",X"DD",X"23",X"DD",X"23",X"DD",X"23",X"0D", + X"C2",X"AD",X"08",X"C9",X"DD",X"4E",X"02",X"06",X"00",X"CB",X"21",X"CB",X"10",X"DD",X"21",X"FC", + X"42",X"DD",X"09",X"DD",X"6E",X"00",X"DD",X"66",X"01",X"E5",X"E5",X"E5",X"E5",X"FD",X"E1",X"DD", + X"E1",X"0E",X"0C",X"DD",X"6E",X"00",X"DD",X"66",X"01",X"FD",X"7E",X"18",X"77",X"DD",X"23",X"DD", + X"23",X"FD",X"23",X"0D",X"C2",X"E3",X"08",X"DD",X"E1",X"FD",X"E1",X"11",X"00",X"08",X"0E",X"0C", + X"DD",X"6E",X"00",X"DD",X"66",X"01",X"19",X"FD",X"7E",X"24",X"77",X"DD",X"23",X"DD",X"23",X"FD", + X"23",X"0D",X"C2",X"00",X"09",X"C9",X"3A",X"88",X"9C",X"A7",X"C0",X"2A",X"E7",X"9B",X"01",X"64", + X"00",X"A7",X"ED",X"42",X"D8",X"01",X"24",X"43",X"CB",X"25",X"CB",X"14",X"09",X"E5",X"DD",X"E1", + X"DD",X"7E",X"00",X"FE",X"FF",X"CA",X"7D",X"0A",X"57",X"DD",X"5E",X"01",X"F5",X"CD",X"82",X"34", + X"F1",X"32",X"63",X"9A",X"47",X"3A",X"62",X"9A",X"4F",X"3E",X"01",X"32",X"62",X"9A",X"78",X"FE", + X"40",X"CA",X"84",X"09",X"FE",X"60",X"CA",X"A3",X"09",X"FE",X"70",X"CA",X"C2",X"09",X"FE",X"90", + X"CA",X"E1",X"09",X"FE",X"A0",X"CA",X"39",X"0A",X"FE",X"B0",X"CA",X"45",X"0A",X"FE",X"C0",X"CA", + X"51",X"0A",X"FE",X"F0",X"D2",X"7C",X"09",X"79",X"32",X"62",X"9A",X"C9",X"DD",X"5E",X"01",X"57", + X"CD",X"B0",X"33",X"C9",X"21",X"6B",X"45",X"CD",X"84",X"10",X"16",X"28",X"1E",X"88",X"26",X"8B", + X"2E",X"10",X"3E",X"00",X"CD",X"62",X"32",X"DD",X"21",X"97",X"41",X"FD",X"21",X"BB",X"41",X"CD", + X"5D",X"0A",X"C9",X"21",X"82",X"45",X"CD",X"84",X"10",X"16",X"28",X"1E",X"A0",X"26",X"AF",X"2E", + X"13",X"3E",X"01",X"CD",X"62",X"32",X"DD",X"21",X"C7",X"41",X"FD",X"21",X"EB",X"41",X"CD",X"5D", + X"0A",X"C9",X"21",X"93",X"45",X"CD",X"84",X"10",X"16",X"28",X"1E",X"B8",X"26",X"67",X"2E",X"12", + X"3E",X"02",X"CD",X"62",X"32",X"DD",X"21",X"F7",X"41",X"FD",X"21",X"1B",X"42",X"CD",X"5D",X"0A", + X"C9",X"21",X"A4",X"45",X"CD",X"84",X"10",X"CD",X"F6",X"09",X"DD",X"21",X"27",X"42",X"FD",X"21", + X"4B",X"42",X"CD",X"5D",X"0A",X"C9",X"FD",X"21",X"67",X"84",X"DD",X"21",X"BC",X"4C",X"DD",X"E5", + X"11",X"04",X"00",X"3E",X"06",X"DD",X"4E",X"00",X"FD",X"71",X"00",X"DD",X"4E",X"01",X"FD",X"71", + X"20",X"DD",X"4E",X"02",X"FD",X"71",X"40",X"DD",X"4E",X"03",X"FD",X"71",X"60",X"DD",X"19",X"FD", + X"2B",X"3D",X"C8",X"FE",X"03",X"C2",X"05",X"0A",X"DD",X"E1",X"11",X"0C",X"00",X"DD",X"19",X"11", + X"04",X"00",X"FD",X"21",X"67",X"8C",X"C3",X"05",X"0A",X"DD",X"21",X"B7",X"42",X"FD",X"21",X"DB", + X"42",X"CD",X"5D",X"0A",X"C9",X"DD",X"21",X"57",X"42",X"FD",X"21",X"7B",X"42",X"CD",X"5D",X"0A", + X"C9",X"DD",X"21",X"87",X"42",X"FD",X"21",X"AB",X"42",X"CD",X"5D",X"0A",X"C9",X"11",X"00",X"08", + X"06",X"04",X"0E",X"0C",X"DD",X"6E",X"00",X"DD",X"66",X"01",X"FD",X"7E",X"00",X"E6",X"F0",X"80", + X"19",X"77",X"DD",X"23",X"DD",X"23",X"FD",X"23",X"0D",X"C2",X"64",X"0A",X"C9",X"3E",X"FF",X"32", + X"88",X"9C",X"C9",X"2A",X"E7",X"9B",X"01",X"64",X"00",X"A7",X"ED",X"42",X"C0",X"21",X"23",X"85", + X"FD",X"21",X"23",X"8D",X"DD",X"21",X"0A",X"43",X"0E",X"0D",X"11",X"20",X"00",X"DD",X"7E",X"00", + X"77",X"DD",X"7E",X"0D",X"FD",X"77",X"00",X"DD",X"23",X"FD",X"19",X"19",X"0D",X"C2",X"9D",X"0A", + X"C9",X"3A",X"62",X"9A",X"A7",X"C8",X"4F",X"3C",X"32",X"62",X"9A",X"06",X"00",X"21",X"B5",X"45", + X"09",X"7E",X"FE",X"50",X"D2",X"D6",X"0A",X"5F",X"3A",X"63",X"9A",X"57",X"26",X"08",X"2E",X"00", + X"3E",X"00",X"CD",X"0E",X"32",X"C9",X"AF",X"32",X"62",X"9A",X"C9",X"21",X"17",X"9C",X"CB",X"C6", + X"C9",X"3A",X"E6",X"9B",X"A7",X"C0",X"21",X"17",X"9C",X"CB",X"CE",X"C9",X"3A",X"E6",X"9B",X"A7", + X"C4",X"36",X"0B",X"3A",X"17",X"9C",X"47",X"3E",X"00",X"32",X"17",X"9C",X"CB",X"40",X"C2",X"4E", + X"0B",X"CB",X"48",X"C2",X"49",X"0B",X"3A",X"16",X"9C",X"CB",X"47",X"C2",X"53",X"0B",X"3A",X"16", + X"9C",X"47",X"CB",X"F8",X"CB",X"80",X"CD",X"3C",X"0B",X"AF",X"32",X"16",X"9C",X"78",X"32",X"00", + X"A1",X"3E",X"01",X"32",X"80",X"A1",X"00",X"00",X"00",X"AF",X"32",X"80",X"A1",X"00",X"00",X"00", + X"3E",X"01",X"32",X"80",X"A1",X"C9",X"3E",X"00",X"32",X"16",X"9C",X"C9",X"3A",X"15",X"9C",X"A7", + X"3E",X"00",X"32",X"15",X"9C",X"C8",X"CB",X"C0",X"C9",X"3E",X"02",X"C3",X"1E",X"0B",X"3E",X"01", + X"C3",X"1E",X"0B",X"AF",X"32",X"16",X"9C",X"3E",X"04",X"C3",X"1E",X"0B",X"DD",X"21",X"CD",X"45", + X"FD",X"21",X"00",X"00",X"0E",X"30",X"3E",X"00",X"DD",X"86",X"00",X"FD",X"86",X"00",X"DD",X"23", + X"FD",X"23",X"0D",X"C2",X"68",X"0B",X"FE",X"F3",X"C8",X"21",X"CD",X"45",X"CD",X"84",X"10",X"21", + X"DD",X"45",X"CD",X"84",X"10",X"C3",X"79",X"0B",X"3A",X"E6",X"9B",X"A7",X"C0",X"3A",X"56",X"9A", + X"32",X"55",X"9A",X"3A",X"58",X"9A",X"32",X"57",X"9A",X"AF",X"32",X"56",X"9A",X"32",X"58",X"9A", + X"32",X"54",X"9A",X"3A",X"E3",X"9B",X"A7",X"CA",X"DE",X"0B",X"3A",X"00",X"9C",X"A7",X"C2",X"DE", + X"0B",X"3A",X"5D",X"9A",X"A7",X"CA",X"DE",X"0B",X"3A",X"80",X"A0",X"CB",X"5F",X"CC",X"37",X"0C", + X"CD",X"13",X"0C",X"3A",X"00",X"A0",X"CB",X"47",X"CA",X"1F",X"0C",X"3A",X"80",X"A0",X"CB",X"4F", + X"CA",X"25",X"0C",X"CB",X"6F",X"CA",X"2B",X"0C",X"CB",X"67",X"CA",X"31",X"0C",X"C9",X"3A",X"00", + X"A0",X"CB",X"5F",X"CC",X"37",X"0C",X"CD",X"07",X"0C",X"3A",X"80",X"A0",X"CB",X"47",X"CA",X"1F", + X"0C",X"3A",X"00",X"A0",X"CB",X"6F",X"CA",X"31",X"0C",X"CB",X"67",X"CA",X"2B",X"0C",X"3A",X"00", + X"A1",X"CB",X"7F",X"CA",X"25",X"0C",X"C9",X"3A",X"00",X"A1",X"CB",X"77",X"C0",X"3E",X"FF",X"32", + X"58",X"9A",X"C9",X"3A",X"80",X"A0",X"CB",X"57",X"C0",X"3E",X"FF",X"32",X"58",X"9A",X"C9",X"3E", + X"10",X"32",X"54",X"9A",X"C9",X"3E",X"20",X"32",X"54",X"9A",X"C9",X"3E",X"02",X"32",X"54",X"9A", + X"C9",X"3E",X"01",X"32",X"54",X"9A",X"C9",X"3E",X"FF",X"32",X"56",X"9A",X"C9",X"CD",X"5B",X"0C", + X"CD",X"32",X"0D",X"CD",X"BE",X"0D",X"3A",X"5D",X"9A",X"A7",X"C2",X"54",X"0C",X"3A",X"EA",X"9B", + X"32",X"52",X"9A",X"C9",X"3A",X"EB",X"9B",X"32",X"52",X"9A",X"C9",X"3A",X"5D",X"9A",X"A7",X"C2", + X"6D",X"0C",X"DD",X"21",X"0D",X"9C",X"FD",X"21",X"01",X"9C",X"C3",X"78",X"0C",X"DD",X"21",X"10", + X"9C",X"FD",X"21",X"07",X"9C",X"C3",X"78",X"0C",X"3A",X"FD",X"9B",X"A7",X"C2",X"D5",X"0C",X"2A", + X"5B",X"9A",X"7C",X"B5",X"C8",X"DD",X"7E",X"02",X"85",X"27",X"DD",X"77",X"02",X"DD",X"7E",X"01", + X"8C",X"27",X"DD",X"77",X"01",X"06",X"00",X"DD",X"7E",X"00",X"88",X"27",X"DD",X"77",X"00",X"21", + X"00",X"00",X"22",X"5B",X"9A",X"DD",X"E5",X"E1",X"AF",X"ED",X"6F",X"FD",X"77",X"00",X"ED",X"67", + X"7E",X"E6",X"0F",X"FD",X"77",X"01",X"23",X"ED",X"6F",X"FD",X"77",X"02",X"ED",X"67",X"7E",X"E6", + X"0F",X"FD",X"77",X"03",X"23",X"ED",X"6F",X"FD",X"77",X"04",X"ED",X"67",X"7E",X"E6",X"0F",X"FD", + X"77",X"05",X"CD",X"D1",X"0E",X"3A",X"5D",X"9A",X"A7",X"C2",X"E6",X"0C",X"21",X"66",X"80",X"FD", + X"21",X"01",X"9C",X"C3",X"ED",X"0C",X"21",X"E6",X"82",X"FD",X"21",X"07",X"9C",X"11",X"20",X"00", + X"06",X"06",X"FD",X"7E",X"00",X"77",X"19",X"FD",X"23",X"05",X"C2",X"F2",X"0C",X"3A",X"52",X"9A", + X"CB",X"47",X"CA",X"1C",X"0D",X"11",X"00",X"08",X"19",X"11",X"E0",X"FF",X"19",X"06",X"06",X"36", + X"00",X"19",X"05",X"C2",X"0F",X"0D",X"19",X"AF",X"32",X"FD",X"9B",X"C9",X"11",X"00",X"08",X"19", + X"11",X"E0",X"FF",X"19",X"06",X"06",X"36",X"10",X"19",X"05",X"C2",X"26",X"0D",X"AF",X"32",X"FD", + X"9B",X"C9",X"3A",X"E3",X"9B",X"A7",X"C8",X"3A",X"5D",X"9A",X"A7",X"C2",X"81",X"0D",X"DD",X"21", + X"67",X"80",X"FD",X"21",X"E7",X"82",X"01",X"01",X"02",X"3A",X"59",X"9A",X"5F",X"E6",X"3F",X"CA", + X"8F",X"0D",X"7B",X"C6",X"20",X"E6",X"3F",X"C0",X"DD",X"71",X"00",X"DD",X"36",X"20",X"1E",X"DD", + X"36",X"40",X"19",X"01",X"00",X"08",X"DD",X"09",X"06",X"03",X"3A",X"52",X"9A",X"CB",X"47",X"CC", + X"7C",X"0D",X"DD",X"70",X"00",X"DD",X"70",X"20",X"DD",X"70",X"40",X"C9",X"3E",X"FF",X"CB",X"E0", + X"C9",X"DD",X"21",X"E7",X"82",X"FD",X"21",X"67",X"80",X"01",X"02",X"01",X"C3",X"49",X"0D",X"3E", + X"7F",X"DD",X"77",X"00",X"DD",X"77",X"20",X"DD",X"77",X"40",X"FD",X"70",X"00",X"FD",X"36",X"20", + X"1E",X"FD",X"36",X"40",X"19",X"01",X"00",X"08",X"FD",X"09",X"06",X"03",X"3A",X"52",X"9A",X"CB", + X"47",X"CC",X"7C",X"0D",X"FD",X"70",X"00",X"FD",X"70",X"20",X"FD",X"70",X"40",X"C9",X"DD",X"21", + X"0D",X"9C",X"FD",X"21",X"10",X"9C",X"DD",X"7E",X"00",X"FD",X"BE",X"00",X"DA",X"0E",X"0E",X"C2", + X"E7",X"0D",X"DD",X"7E",X"01",X"FD",X"BE",X"01",X"DA",X"0E",X"0E",X"C2",X"E7",X"0D",X"DD",X"7E", + X"02",X"FD",X"BE",X"02",X"DA",X"0E",X"0E",X"DD",X"21",X"0D",X"9C",X"FD",X"21",X"73",X"9C",X"DD", + X"7E",X"00",X"FD",X"BE",X"00",X"D8",X"C2",X"19",X"0E",X"DD",X"7E",X"01",X"FD",X"BE",X"01",X"D8", + X"C2",X"19",X"0E",X"DD",X"7E",X"02",X"FD",X"BE",X"02",X"D8",X"C8",X"C3",X"19",X"0E",X"DD",X"21", + X"10",X"9C",X"FD",X"21",X"73",X"9C",X"C3",X"EF",X"0D",X"DD",X"7E",X"00",X"DD",X"46",X"01",X"DD", + X"4E",X"02",X"FD",X"77",X"00",X"FD",X"70",X"01",X"FD",X"71",X"02",X"FD",X"E5",X"E1",X"DD",X"21", + X"6D",X"9C",X"AF",X"ED",X"6F",X"DD",X"77",X"00",X"ED",X"67",X"7E",X"E6",X"0F",X"DD",X"77",X"01", + X"23",X"ED",X"6F",X"DD",X"77",X"02",X"ED",X"67",X"7E",X"E6",X"0F",X"DD",X"77",X"03",X"23",X"ED", + X"6F",X"DD",X"77",X"04",X"ED",X"67",X"7E",X"E6",X"0F",X"DD",X"77",X"05",X"3A",X"E3",X"9B",X"A7", + X"C2",X"6D",X"0E",X"21",X"87",X"81",X"DD",X"21",X"6D",X"9C",X"C3",X"77",X"0E",X"21",X"87",X"81", + X"DD",X"21",X"6D",X"9C",X"C3",X"77",X"0E",X"11",X"20",X"00",X"E5",X"36",X"11",X"19",X"36",X"12", + X"19",X"36",X"4D",X"19",X"36",X"1C",X"19",X"36",X"0C",X"19",X"36",X"18",X"19",X"36",X"1B",X"19", + X"36",X"0E",X"19",X"E1",X"E5",X"2B",X"19",X"0E",X"06",X"DD",X"7E",X"00",X"77",X"19",X"DD",X"23", + X"0D",X"C2",X"99",X"0E",X"E1",X"01",X"00",X"08",X"09",X"E5",X"0E",X"08",X"06",X"08",X"3A",X"52", + X"9A",X"CB",X"47",X"CC",X"7C",X"0D",X"70",X"19",X"0D",X"C2",X"B6",X"0E",X"0E",X"07",X"E1",X"2B", + X"06",X"00",X"3A",X"52",X"9A",X"CB",X"47",X"CC",X"7C",X"0D",X"70",X"19",X"0D",X"C2",X"CA",X"0E", + X"C9",X"3A",X"5D",X"9A",X"A7",X"C2",X"E1",X"0E",X"11",X"EC",X"9B",X"21",X"E4",X"9B",X"C3",X"EA", + X"0E",X"11",X"ED",X"9B",X"21",X"E5",X"9B",X"C3",X"EA",X"0E",X"1A",X"A7",X"C0",X"FD",X"7E",X"00", + X"A7",X"C2",X"FD",X"0E",X"3A",X"FE",X"9B",X"47",X"FD",X"7E",X"01",X"B8",X"D8",X"7E",X"3C",X"77", + X"3E",X"FF",X"12",X"CD",X"F7",X"0F",X"C9",X"3A",X"FF",X"9B",X"E6",X"03",X"47",X"3A",X"E3",X"9B", + X"A7",X"C2",X"19",X"0F",X"0E",X"00",X"C3",X"1B",X"0F",X"0E",X"FF",X"78",X"FE",X"00",X"CA",X"2E", + X"0F",X"FE",X"01",X"CA",X"38",X"0F",X"FE",X"02",X"CA",X"42",X"0F",X"C3",X"4C",X"0F",X"3E",X"02", + X"32",X"E4",X"9B",X"A1",X"32",X"E5",X"9B",X"C9",X"3E",X"03",X"32",X"E4",X"9B",X"A1",X"32",X"E5", + X"9B",X"C9",X"3E",X"04",X"32",X"E4",X"9B",X"A1",X"32",X"E5",X"9B",X"C9",X"3E",X"05",X"32",X"E4", + X"9B",X"A1",X"32",X"E5",X"9B",X"C9",X"21",X"80",X"86",X"11",X"20",X"00",X"0E",X"08",X"FD",X"21", + X"4B",X"3D",X"FD",X"7E",X"00",X"77",X"19",X"FD",X"23",X"0D",X"C2",X"62",X"0F",X"21",X"80",X"8E", + X"3E",X"00",X"0E",X"0A",X"77",X"19",X"0D",X"C2",X"74",X"0F",X"3A",X"F6",X"9B",X"FE",X"64",X"D2", + X"A7",X"0F",X"A7",X"CA",X"B4",X"0F",X"47",X"0E",X"01",X"AF",X"81",X"27",X"05",X"C2",X"8A",X"0F", + X"FD",X"21",X"60",X"87",X"47",X"E6",X"0F",X"FD",X"77",X"20",X"78",X"CB",X"3F",X"CB",X"3F",X"CB", + X"3F",X"CB",X"3F",X"FD",X"77",X"00",X"C9",X"FD",X"21",X"60",X"87",X"3E",X"28",X"FD",X"77",X"00", + X"FD",X"77",X"20",X"C9",X"FD",X"21",X"60",X"87",X"AF",X"FD",X"77",X"20",X"C9",X"3A",X"E3",X"9B", + X"A7",X"CA",X"D7",X"0F",X"3A",X"00",X"9C",X"A7",X"C2",X"D7",X"0F",X"3A",X"5D",X"9A",X"A7",X"CA", + X"D7",X"0F",X"AF",X"32",X"83",X"A1",X"C9",X"3E",X"01",X"32",X"83",X"A1",X"C9",X"E5",X"DD",X"E1", + X"D9",X"DD",X"6E",X"02",X"DD",X"66",X"03",X"DD",X"4E",X"00",X"11",X"20",X"00",X"3E",X"FF",X"77", + X"19",X"0D",X"C2",X"EF",X"0F",X"D9",X"C9",X"3A",X"5D",X"9A",X"A7",X"C2",X"04",X"10",X"21",X"E4", + X"9B",X"C3",X"07",X"10",X"21",X"E5",X"9B",X"7E",X"A7",X"CA",X"4E",X"10",X"F5",X"CD",X"4E",X"10", + X"DD",X"21",X"41",X"84",X"11",X"40",X"00",X"F1",X"FE",X"08",X"D0",X"4F",X"DD",X"36",X"00",X"7C", + X"DD",X"36",X"FF",X"7B",X"DD",X"36",X"20",X"7E",X"DD",X"36",X"1F",X"7D",X"DD",X"E5",X"D5",X"11", + X"00",X"08",X"DD",X"19",X"DD",X"36",X"00",X"1C",X"DD",X"36",X"FF",X"1C",X"DD",X"36",X"20",X"1C", + X"DD",X"36",X"1F",X"1C",X"D1",X"DD",X"E1",X"DD",X"19",X"0D",X"C2",X"1C",X"10",X"C9",X"21",X"41", + X"84",X"11",X"20",X"00",X"3E",X"7A",X"0E",X"10",X"77",X"19",X"0D",X"C2",X"58",X"10",X"21",X"40", + X"84",X"0E",X"10",X"77",X"19",X"0D",X"C2",X"63",X"10",X"21",X"41",X"8C",X"3E",X"00",X"0E",X"10", + X"77",X"19",X"0D",X"C2",X"70",X"10",X"21",X"40",X"8C",X"0E",X"10",X"3E",X"00",X"77",X"19",X"0D", + X"C2",X"7D",X"10",X"C9",X"E5",X"DD",X"E1",X"D9",X"DD",X"46",X"00",X"DD",X"4E",X"01",X"DD",X"6E", + X"02",X"DD",X"66",X"03",X"E5",X"C5",X"11",X"20",X"00",X"DD",X"7E",X"04",X"77",X"19",X"DD",X"23", + X"05",X"C2",X"99",X"10",X"C1",X"E1",X"11",X"00",X"08",X"19",X"11",X"20",X"00",X"71",X"19",X"05", + X"C2",X"AD",X"10",X"D9",X"C9",X"21",X"40",X"80",X"0E",X"FF",X"11",X"80",X"07",X"71",X"23",X"1B", + X"7A",X"B3",X"C2",X"BD",X"10",X"21",X"40",X"88",X"0E",X"00",X"11",X"80",X"07",X"71",X"23",X"1B", + X"7A",X"B3",X"C2",X"CD",X"10",X"C9",X"CD",X"E0",X"10",X"21",X"00",X"50",X"22",X"5B",X"9A",X"C9", + X"3A",X"5D",X"9A",X"A7",X"C2",X"F1",X"10",X"3A",X"EA",X"9B",X"C6",X"01",X"27",X"32",X"EA",X"9B", + X"C9",X"3A",X"EB",X"9B",X"C6",X"01",X"27",X"32",X"EB",X"9B",X"C9",X"21",X"01",X"9C",X"11",X"02", + X"9C",X"01",X"12",X"00",X"AF",X"77",X"ED",X"B0",X"C9",X"06",X"FF",X"0E",X"FF",X"0D",X"C2",X"0D", + X"11",X"05",X"C2",X"0B",X"11",X"3D",X"C2",X"09",X"11",X"C9",X"21",X"00",X"80",X"01",X"FF",X"07", + X"16",X"FF",X"72",X"23",X"0B",X"78",X"B1",X"C2",X"22",X"11",X"C9",X"3A",X"5D",X"9A",X"F5",X"AF", + X"32",X"5D",X"9A",X"CD",X"D5",X"0C",X"3E",X"FF",X"32",X"5D",X"9A",X"CD",X"D5",X"0C",X"F1",X"32", + X"5D",X"9A",X"C9",X"21",X"6A",X"3D",X"CD",X"84",X"10",X"C9",X"21",X"7E",X"3D",X"CD",X"84",X"10", + X"C9",X"21",X"92",X"3D",X"CD",X"84",X"10",X"C9",X"21",X"9F",X"3D",X"CD",X"84",X"10",X"C9",X"3A", + X"00",X"A0",X"CB",X"7F",X"3E",X"00",X"28",X"14",X"3A",X"13",X"9C",X"A7",X"CA",X"80",X"11",X"32", + X"15",X"9C",X"2F",X"32",X"13",X"9C",X"CD",X"9F",X"02",X"C3",X"80",X"11",X"2F",X"32",X"13",X"9C", + X"3A",X"00",X"A0",X"CB",X"77",X"3E",X"00",X"28",X"14",X"3A",X"14",X"9C",X"A7",X"CA",X"A1",X"11", + X"32",X"15",X"9C",X"2F",X"32",X"14",X"9C",X"CD",X"C3",X"02",X"C3",X"A1",X"11",X"2F",X"32",X"14", + X"9C",X"3A",X"00",X"A0",X"CB",X"67",X"C3",X"BD",X"11",X"3A",X"19",X"9C",X"A7",X"C0",X"2F",X"32", + X"19",X"9C",X"32",X"15",X"9C",X"3A",X"F6",X"9B",X"3C",X"32",X"F6",X"9B",X"C9",X"AF",X"32",X"19", + X"9C",X"C9",X"3A",X"80",X"A0",X"CB",X"7F",X"CA",X"D3",X"11",X"CB",X"77",X"C0",X"3E",X"FF",X"32", + X"F3",X"9B",X"C9",X"3E",X"FF",X"32",X"F2",X"9B",X"C9",X"3A",X"80",X"A1",X"2F",X"32",X"FF",X"9B", + X"5F",X"3A",X"00",X"A1",X"2F",X"57",X"CD",X"F3",X"11",X"CD",X"23",X"12",X"CD",X"48",X"12",X"CD", + X"59",X"12",X"C9",X"7B",X"CB",X"3F",X"CB",X"3F",X"E6",X"07",X"21",X"F4",X"9B",X"FE",X"00",X"CA", + X"2C",X"12",X"FE",X"01",X"CA",X"30",X"12",X"FE",X"02",X"CA",X"34",X"12",X"FE",X"03",X"CA",X"38", + X"12",X"FE",X"04",X"CA",X"3C",X"12",X"FE",X"05",X"CA",X"40",X"12",X"FE",X"06",X"CA",X"44",X"12", + X"36",X"FF",X"C9",X"21",X"F5",X"9B",X"7A",X"E6",X"07",X"C3",X"FD",X"11",X"3E",X"00",X"77",X"C9", + X"3E",X"01",X"77",X"C9",X"3E",X"02",X"77",X"C9",X"3E",X"03",X"77",X"C9",X"3E",X"04",X"77",X"C9", + X"3E",X"05",X"77",X"C9",X"3E",X"06",X"77",X"C9",X"7B",X"CB",X"7F",X"C2",X"53",X"12",X"AF",X"32", + X"00",X"9C",X"C9",X"3E",X"FF",X"32",X"00",X"9C",X"C9",X"7B",X"CB",X"5F",X"C2",X"65",X"12",X"3E", + X"03",X"32",X"FE",X"9B",X"C9",X"3E",X"05",X"32",X"FE",X"9B",X"C9",X"21",X"BC",X"3D",X"11",X"1A", + X"9C",X"01",X"10",X"00",X"ED",X"B0",X"21",X"CC",X"3D",X"11",X"2A",X"9C",X"01",X"10",X"00",X"ED", + X"B0",X"21",X"DC",X"3D",X"11",X"3A",X"9C",X"01",X"10",X"00",X"ED",X"B0",X"21",X"EC",X"3D",X"11", + X"4A",X"9C",X"01",X"10",X"00",X"ED",X"B0",X"21",X"FC",X"3D",X"11",X"5A",X"9C",X"01",X"10",X"00", + X"ED",X"B0",X"C9",X"21",X"37",X"3F",X"11",X"40",X"9A",X"01",X"11",X"00",X"ED",X"B0",X"AF",X"32", + X"53",X"9A",X"C9",X"DD",X"21",X"20",X"9A",X"DD",X"36",X"03",X"80",X"DD",X"36",X"04",X"80",X"DD", + X"36",X"00",X"FF",X"16",X"80",X"1E",X"E8",X"26",X"D3",X"2E",X"1A",X"3E",X"00",X"CD",X"62",X"32", + X"C9",X"DD",X"21",X"40",X"9A",X"0E",X"08",X"06",X"01",X"50",X"C5",X"DD",X"7E",X"01",X"A7",X"F5", + X"CC",X"51",X"36",X"F1",X"C4",X"A6",X"36",X"C1",X"DD",X"23",X"DD",X"23",X"04",X"0D",X"C2",X"D9", + X"12",X"C9",X"21",X"00",X"80",X"0E",X"40",X"06",X"FF",X"70",X"23",X"0D",X"C2",X"F9",X"12",X"21", + X"00",X"88",X"0E",X"40",X"06",X"FF",X"70",X"23",X"0D",X"C2",X"06",X"13",X"C9",X"21",X"00",X"98", + X"11",X"01",X"98",X"01",X"3F",X"02",X"36",X"00",X"ED",X"B0",X"DD",X"21",X"00",X"98",X"FD",X"21", + X"3B",X"3E",X"0E",X"09",X"11",X"10",X"00",X"CD",X"C3",X"13",X"DD",X"19",X"FD",X"23",X"FD",X"23", + X"FD",X"23",X"0D",X"C2",X"27",X"13",X"DD",X"21",X"90",X"98",X"FD",X"21",X"56",X"3E",X"0E",X"02", + X"11",X"10",X"00",X"CD",X"C3",X"13",X"DD",X"19",X"FD",X"23",X"FD",X"23",X"FD",X"23",X"0D",X"C2", + X"43",X"13",X"DD",X"21",X"B0",X"98",X"FD",X"21",X"68",X"3E",X"0E",X"05",X"11",X"20",X"00",X"CD", + X"E9",X"13",X"DD",X"19",X"FD",X"23",X"FD",X"23",X"FD",X"23",X"0D",X"C2",X"5F",X"13",X"DD",X"21", + X"50",X"99",X"FD",X"21",X"86",X"3E",X"0E",X"05",X"11",X"20",X"00",X"CD",X"F6",X"13",X"DD",X"19", + X"FD",X"23",X"FD",X"23",X"FD",X"23",X"0D",X"C2",X"7B",X"13",X"DD",X"21",X"F0",X"99",X"FD",X"21", + X"5C",X"3E",X"0E",X"03",X"11",X"10",X"00",X"CD",X"E9",X"13",X"DD",X"19",X"FD",X"23",X"FD",X"23", + X"FD",X"23",X"0D",X"C2",X"97",X"13",X"DD",X"21",X"20",X"9A",X"FD",X"21",X"65",X"3E",X"0E",X"01", + X"11",X"20",X"00",X"CD",X"E9",X"13",X"DD",X"19",X"FD",X"23",X"FD",X"23",X"FD",X"23",X"0D",X"C2", + X"B3",X"13",X"C9",X"FD",X"7E",X"00",X"DD",X"77",X"01",X"FD",X"7E",X"01",X"DD",X"77",X"02",X"FD", + X"7E",X"02",X"DD",X"77",X"0E",X"C9",X"FD",X"7E",X"00",X"DD",X"77",X"01",X"FD",X"7E",X"01",X"DD", + X"77",X"02",X"FD",X"7E",X"02",X"DD",X"77",X"03",X"C9",X"FD",X"7E",X"00",X"DD",X"77",X"01",X"FD", + X"7E",X"01",X"DD",X"77",X"02",X"C9",X"FD",X"7E",X"00",X"DD",X"77",X"01",X"FD",X"7E",X"01",X"DD", + X"77",X"02",X"FD",X"7E",X"02",X"DD",X"77",X"1F",X"C9",X"DD",X"21",X"50",X"99",X"01",X"20",X"00", + X"16",X"05",X"1E",X"00",X"DD",X"73",X"07",X"DD",X"09",X"15",X"C2",X"14",X"14",X"C9",X"3A",X"52", + X"9A",X"CB",X"47",X"CA",X"14",X"15",X"21",X"44",X"80",X"06",X"7F",X"0E",X"00",X"11",X"64",X"03", + X"70",X"23",X"1B",X"7B",X"B2",X"C2",X"30",X"14",X"21",X"44",X"88",X"11",X"64",X"03",X"71",X"23", + X"1B",X"7B",X"B2",X"C2",X"3E",X"14",X"DD",X"21",X"40",X"84",X"06",X"7A",X"0E",X"00",X"26",X"0B", + X"11",X"20",X"00",X"CD",X"B9",X"14",X"DD",X"21",X"40",X"8C",X"41",X"26",X"0B",X"11",X"20",X"00", + X"CD",X"B9",X"14",X"DD",X"21",X"4B",X"84",X"06",X"7F",X"26",X"11",X"11",X"20",X"00",X"CD",X"B9", + X"14",X"DD",X"21",X"4B",X"8C",X"26",X"11",X"06",X"00",X"CD",X"B9",X"14",X"DD",X"21",X"95",X"3E", + X"FD",X"21",X"CB",X"3E",X"0E",X"36",X"FD",X"6E",X"00",X"FD",X"66",X"01",X"DD",X"7E",X"00",X"77", + X"FD",X"23",X"FD",X"23",X"DD",X"23",X"0D",X"C2",X"86",X"14",X"DD",X"21",X"CB",X"3E",X"0E",X"36", + X"11",X"00",X"08",X"06",X"01",X"DD",X"6E",X"00",X"DD",X"66",X"01",X"19",X"70",X"DD",X"23",X"DD", + X"23",X"0D",X"C2",X"A5",X"14",X"CD",X"CF",X"14",X"C9",X"DD",X"E5",X"FD",X"E1",X"2E",X"1C",X"FD", + X"70",X"00",X"FD",X"19",X"2D",X"C2",X"BF",X"14",X"DD",X"23",X"25",X"C2",X"B9",X"14",X"C9",X"DD", + X"21",X"67",X"80",X"DD",X"36",X"00",X"01",X"DD",X"36",X"20",X"1E",X"DD",X"36",X"40",X"19",X"DD", + X"21",X"E7",X"82",X"DD",X"36",X"00",X"02",X"DD",X"36",X"20",X"1E",X"DD",X"36",X"40",X"19",X"06", + X"03",X"3A",X"52",X"9A",X"CB",X"47",X"CC",X"7C",X"0D",X"DD",X"21",X"67",X"88",X"FD",X"21",X"E7", + X"8A",X"DD",X"70",X"00",X"DD",X"70",X"20",X"DD",X"70",X"40",X"FD",X"70",X"00",X"FD",X"70",X"20", + X"FD",X"70",X"40",X"C9",X"21",X"44",X"80",X"06",X"7F",X"0E",X"10",X"11",X"64",X"03",X"70",X"23", + X"1B",X"7B",X"B2",X"C2",X"1E",X"15",X"21",X"44",X"88",X"11",X"64",X"03",X"71",X"23",X"1B",X"7B", + X"B2",X"C2",X"2C",X"15",X"DD",X"21",X"40",X"84",X"06",X"7A",X"0E",X"00",X"26",X"0B",X"11",X"20", + X"00",X"CD",X"B9",X"14",X"DD",X"21",X"40",X"8C",X"41",X"26",X"0B",X"11",X"20",X"00",X"CD",X"B9", + X"14",X"DD",X"21",X"4B",X"84",X"06",X"7F",X"26",X"11",X"11",X"20",X"00",X"CD",X"B9",X"14",X"DD", + X"21",X"4B",X"8C",X"26",X"11",X"06",X"10",X"CD",X"B9",X"14",X"CD",X"CF",X"14",X"C9",X"DD",X"21", + X"20",X"9A",X"CD",X"A1",X"15",X"CD",X"65",X"16",X"CD",X"D7",X"16",X"DD",X"7E",X"00",X"A7",X"C8", + X"DD",X"7E",X"05",X"A7",X"C0",X"CD",X"7F",X"17",X"DD",X"7E",X"06",X"A7",X"C0",X"CD",X"4B",X"18", + X"CD",X"8A",X"18",X"3A",X"59",X"9A",X"DD",X"86",X"02",X"DD",X"A6",X"01",X"C0",X"CD",X"D5",X"18", + X"C9",X"DD",X"7E",X"05",X"A7",X"C2",X"F4",X"15",X"0E",X"0B",X"FD",X"21",X"00",X"98",X"CD",X"C4", + X"15",X"11",X"10",X"00",X"FD",X"19",X"0D",X"C2",X"AE",X"15",X"DD",X"7E",X"05",X"A7",X"C8",X"DD", + X"36",X"06",X"3F",X"C9",X"FD",X"7E",X"00",X"A7",X"C8",X"21",X"E4",X"45",X"FD",X"46",X"04",X"3E", + X"E8",X"96",X"B8",X"D0",X"23",X"3E",X"E8",X"86",X"B8",X"D8",X"23",X"FD",X"46",X"03",X"DD",X"7E", + X"03",X"57",X"96",X"B8",X"D0",X"23",X"7A",X"86",X"B8",X"D8",X"DD",X"36",X"05",X"FF",X"21",X"16", + X"9C",X"CB",X"C6",X"C9",X"3A",X"59",X"9A",X"DD",X"86",X"02",X"DD",X"A6",X"01",X"C0",X"21",X"16", + X"9C",X"CB",X"C6",X"DD",X"7E",X"06",X"FE",X"30",X"CA",X"50",X"16",X"D2",X"1B",X"16",X"FE",X"20", + X"CA",X"57",X"16",X"FE",X"10",X"CA",X"5E",X"16",X"C3",X"1F",X"16",X"DD",X"36",X"0F",X"E3",X"DD", + X"56",X"03",X"1E",X"E8",X"DD",X"66",X"0F",X"2E",X"19",X"3E",X"00",X"CD",X"62",X"32",X"DD",X"35", + X"06",X"C0",X"3E",X"FF",X"32",X"51",X"9A",X"DD",X"36",X"05",X"00",X"DD",X"36",X"00",X"00",X"DD", + X"36",X"07",X"00",X"DD",X"36",X"09",X"00",X"DD",X"36",X"0F",X"D3",X"DD",X"36",X"12",X"00",X"C9", + X"DD",X"36",X"0F",X"E7",X"C3",X"1F",X"16",X"DD",X"36",X"0F",X"EB",X"C3",X"1F",X"16",X"DD",X"36", + X"0F",X"EF",X"C3",X"1F",X"16",X"DD",X"7E",X"07",X"A7",X"C8",X"3A",X"59",X"9A",X"E6",X"01",X"C0", + X"DD",X"7E",X"08",X"D6",X"02",X"DD",X"77",X"08",X"06",X"05",X"CD",X"8A",X"16",X"DD",X"7E",X"08", + X"C6",X"08",X"06",X"06",X"CD",X"8A",X"16",X"C3",X"97",X"16",X"DD",X"56",X"1E",X"5F",X"26",X"0B", + X"2E",X"00",X"78",X"CD",X"0E",X"32",X"C9",X"FD",X"21",X"25",X"46",X"06",X"00",X"0E",X"06",X"DD", + X"66",X"1E",X"DD",X"6E",X"08",X"CD",X"B7",X"16",X"78",X"A7",X"C2",X"C8",X"16",X"0D",X"C8",X"11", + X"03",X"00",X"FD",X"19",X"C3",X"A5",X"16",X"7D",X"FD",X"BE",X"00",X"D0",X"7C",X"FD",X"BE",X"01", + X"D8",X"FD",X"BE",X"02",X"D0",X"06",X"FF",X"C9",X"DD",X"36",X"07",X"00",X"3E",X"05",X"CD",X"5D", + X"18",X"3E",X"06",X"CD",X"5D",X"18",X"C9",X"DD",X"7E",X"09",X"A7",X"C8",X"3A",X"59",X"9A",X"E6", + X"01",X"C0",X"DD",X"7E",X"1D",X"A7",X"C2",X"5F",X"17",X"DD",X"7E",X"0C",X"A7",X"C2",X"01",X"17", + X"DD",X"7E",X"0B",X"DD",X"BE",X"11",X"DA",X"01",X"17",X"D6",X"02",X"DD",X"77",X"0B",X"C3",X"37", + X"17",X"DD",X"66",X"0E",X"DD",X"6E",X"0D",X"E5",X"FD",X"E1",X"DD",X"7E",X"0C",X"A7",X"CA",X"22", + X"17",X"11",X"02",X"00",X"FD",X"19",X"3D",X"C2",X"11",X"17",X"FD",X"7E",X"00",X"FE",X"80",X"CA", + X"47",X"17",X"DD",X"7E",X"0B",X"FD",X"86",X"00",X"DD",X"77",X"0B",X"FD",X"7E",X"01",X"DD",X"86", + X"0A",X"DD",X"77",X"0A",X"DD",X"34",X"0C",X"DD",X"56",X"0A",X"DD",X"5E",X"0B",X"26",X"0C",X"2E", + X"00",X"3E",X"04",X"CD",X"0E",X"32",X"C9",X"DD",X"36",X"1D",X"FF",X"DD",X"36",X"0C",X"03",X"DD", + X"56",X"0A",X"DD",X"5E",X"0B",X"26",X"0A",X"2E",X"00",X"3E",X"04",X"CD",X"0E",X"32",X"C9",X"DD", + X"35",X"0C",X"C0",X"DD",X"36",X"09",X"00",X"DD",X"36",X"1D",X"00",X"16",X"08",X"DD",X"72",X"0A", + X"1E",X"10",X"DD",X"73",X"0B",X"26",X"0F",X"2E",X"00",X"3E",X"04",X"CD",X"0E",X"32",X"C9",X"DD", + X"7E",X"06",X"FE",X"FF",X"C0",X"3A",X"59",X"9A",X"DD",X"86",X"02",X"DD",X"A6",X"01",X"C0",X"FD", + X"21",X"CE",X"4F",X"06",X"00",X"DD",X"7E",X"12",X"D6",X"03",X"A7",X"CA",X"A6",X"17",X"FD",X"23", + X"FD",X"23",X"3D",X"C2",X"9E",X"17",X"FD",X"6E",X"00",X"FD",X"66",X"01",X"E5",X"FD",X"E1",X"FD", + X"6E",X"0D",X"FD",X"66",X"0E",X"FD",X"7E",X"0C",X"A7",X"CA",X"C4",X"17",X"11",X"04",X"00",X"19", + X"3D",X"C2",X"BC",X"17",X"7E",X"FE",X"80",X"CA",X"1B",X"18",X"FD",X"86",X"04",X"FD",X"77",X"04", + X"5F",X"23",X"7E",X"FD",X"86",X"03",X"FD",X"77",X"03",X"57",X"23",X"46",X"23",X"4E",X"C5",X"E1", + X"FD",X"74",X"0F",X"DD",X"7E",X"12",X"CD",X"62",X"32",X"FD",X"34",X"0C",X"FD",X"7E",X"0B",X"FE", + X"10",X"C2",X"00",X"18",X"DD",X"7E",X"03",X"D6",X"03",X"FD",X"BE",X"03",X"D0",X"C3",X"09",X"18", + X"DD",X"7E",X"03",X"C6",X"03",X"FD",X"BE",X"03",X"D8",X"DD",X"7E",X"03",X"D6",X"02",X"57",X"1E", + X"DE",X"26",X"09",X"2E",X"00",X"3E",X"06",X"CD",X"0E",X"32",X"C9",X"DD",X"36",X"06",X"3F",X"DD", + X"36",X"05",X"FF",X"21",X"16",X"9C",X"CB",X"C6",X"16",X"F8",X"1E",X"F0",X"26",X"FF",X"FD",X"74", + X"0F",X"2E",X"0F",X"DD",X"7E",X"12",X"CD",X"62",X"32",X"3E",X"06",X"CD",X"5D",X"18",X"FD",X"36", + X"05",X"FF",X"FD",X"36",X"06",X"1E",X"FD",X"36",X"1E",X"00",X"C9",X"DD",X"7E",X"07",X"A7",X"C0", + X"3E",X"05",X"CD",X"5D",X"18",X"3E",X"06",X"CD",X"5D",X"18",X"C3",X"6C",X"18",X"16",X"08",X"1E", + X"10",X"DD",X"73",X"08",X"26",X"0F",X"2E",X"00",X"CD",X"0E",X"32",X"C9",X"3A",X"57",X"9A",X"A7", + X"C0",X"3A",X"58",X"9A",X"A7",X"C8",X"DD",X"36",X"07",X"FF",X"DD",X"36",X"08",X"DA",X"DD",X"7E", + X"03",X"DD",X"77",X"1E",X"21",X"16",X"9C",X"CB",X"D6",X"C9",X"DD",X"7E",X"09",X"A7",X"C0",X"16", + X"08",X"1E",X"10",X"DD",X"73",X"0B",X"26",X"0F",X"2E",X"00",X"3E",X"04",X"CD",X"0E",X"32",X"3A", + X"55",X"9A",X"A7",X"C0",X"3A",X"56",X"9A",X"A7",X"C8",X"DD",X"36",X"09",X"FF",X"DD",X"7E",X"03", + X"DD",X"77",X"0A",X"C6",X"10",X"DD",X"77",X"10",X"DD",X"7E",X"04",X"DD",X"77",X"11",X"DD",X"36", + X"0B",X"DA",X"DD",X"36",X"0C",X"00",X"21",X"FC",X"45",X"DD",X"75",X"0D",X"DD",X"74",X"0E",X"21", + X"16",X"9C",X"CB",X"CE",X"C9",X"3A",X"54",X"9A",X"CB",X"47",X"C2",X"E9",X"18",X"CB",X"4F",X"C2", + X"03",X"19",X"DD",X"36",X"0F",X"D3",X"C3",X"2F",X"19",X"DD",X"7E",X"03",X"C6",X"01",X"FE",X"DE", + X"D2",X"FC",X"18",X"DD",X"77",X"03",X"CD",X"1D",X"19",X"C3",X"2F",X"19",X"DD",X"36",X"03",X"DE", + X"C3",X"2F",X"19",X"DD",X"7E",X"03",X"D6",X"01",X"FE",X"1C",X"DA",X"16",X"19",X"DD",X"77",X"03", + X"CD",X"1D",X"19",X"C3",X"2F",X"19",X"DD",X"36",X"03",X"1C",X"C3",X"2F",X"19",X"DD",X"7E",X"0F", + X"FE",X"D3",X"CA",X"2A",X"19",X"DD",X"36",X"0F",X"D3",X"C9",X"DD",X"36",X"0F",X"D7",X"C9",X"DD", + X"56",X"03",X"1E",X"E8",X"DD",X"66",X"0F",X"2E",X"1A",X"3E",X"00",X"CD",X"62",X"32",X"3A",X"54", + X"9A",X"CB",X"67",X"C2",X"4E",X"19",X"CB",X"6F",X"C2",X"65",X"19",X"C3",X"7C",X"19",X"DD",X"7E", + X"04",X"D6",X"01",X"FE",X"22",X"DA",X"5E",X"19",X"DD",X"77",X"04",X"C3",X"7C",X"19",X"DD",X"36", + X"04",X"22",X"C3",X"7C",X"19",X"DD",X"7E",X"04",X"C6",X"01",X"FE",X"96",X"D2",X"75",X"19",X"DD", + X"77",X"04",X"C3",X"7C",X"19",X"DD",X"36",X"04",X"96",X"C3",X"7C",X"19",X"DD",X"7E",X"03",X"C6", + X"10",X"57",X"DD",X"5E",X"04",X"CD",X"B5",X"31",X"C9",X"DD",X"21",X"B0",X"98",X"CD",X"B4",X"19", + X"DD",X"21",X"D0",X"98",X"CD",X"B4",X"19",X"DD",X"21",X"F0",X"98",X"CD",X"B4",X"19",X"DD",X"21", + X"10",X"99",X"CD",X"B4",X"19",X"DD",X"21",X"30",X"99",X"CD",X"B4",X"19",X"C9",X"CD",X"89",X"19", + X"CD",X"77",X"1F",X"C9",X"CD",X"CD",X"19",X"DD",X"7E",X"00",X"A7",X"C8",X"CD",X"43",X"1A",X"3A", + X"59",X"9A",X"DD",X"86",X"02",X"DD",X"A6",X"01",X"C0",X"CD",X"25",X"1B",X"C9",X"DD",X"7E",X"07", + X"A7",X"C8",X"DD",X"6E",X"08",X"DD",X"66",X"09",X"E5",X"FD",X"E1",X"FD",X"7E",X"00",X"A7",X"C8", + X"3A",X"59",X"9A",X"FD",X"86",X"02",X"FD",X"A6",X"01",X"C0",X"FD",X"7E",X"04",X"C6",X"08",X"FD", + X"77",X"04",X"FE",X"F0",X"D2",X"04",X"1A",X"DD",X"7E",X"12",X"A7",X"C2",X"15",X"1A",X"3E",X"FF", + X"CD",X"21",X"1A",X"C9",X"AF",X"CD",X"21",X"1A",X"FD",X"E5",X"E1",X"3E",X"0D",X"CD",X"70",X"20", + X"DD",X"36",X"07",X"00",X"C9",X"FD",X"7E",X"03",X"FD",X"86",X"08",X"FD",X"77",X"03",X"C3",X"FE", + X"19",X"A7",X"CA",X"36",X"1A",X"FD",X"7E",X"0E",X"FD",X"56",X"03",X"FD",X"5E",X"04",X"26",X"0D", + X"2E",X"00",X"CD",X"0E",X"32",X"C9",X"FD",X"7E",X"0E",X"11",X"F0",X"08",X"21",X"FF",X"FF",X"CD", + X"0E",X"32",X"C9",X"DD",X"7E",X"05",X"A7",X"C2",X"96",X"1A",X"CD",X"6E",X"31",X"A7",X"C8",X"FD", + X"21",X"20",X"9A",X"DD",X"7E",X"03",X"C6",X"06",X"FD",X"96",X"0A",X"DA",X"64",X"1A",X"FE",X"10", + X"D0",X"C3",X"67",X"1A",X"FE",X"10",X"D0",X"DD",X"7E",X"04",X"C6",X"00",X"FD",X"96",X"0B",X"DA", + X"78",X"1A",X"FE",X"10",X"D0",X"C3",X"7D",X"1A",X"ED",X"44",X"FE",X"10",X"D0",X"DD",X"36",X"05", + X"FF",X"DD",X"36",X"06",X"30",X"21",X"16",X"9C",X"CB",X"DE",X"3E",X"00",X"32",X"29",X"9A",X"CD", + X"60",X"20",X"CD",X"80",X"20",X"C9",X"DD",X"7E",X"06",X"A7",X"CA",X"E3",X"1A",X"FE",X"10",X"CA", + X"A7",X"1A",X"3D",X"DD",X"77",X"06",X"C9",X"DD",X"7E",X"11",X"A7",X"C2",X"C5",X"1A",X"DD",X"56", + X"03",X"DD",X"5E",X"04",X"CD",X"A6",X"33",X"DD",X"7E",X"06",X"3D",X"DD",X"77",X"06",X"21",X"50", + X"00",X"22",X"5B",X"9A",X"C9",X"DD",X"56",X"03",X"DD",X"5E",X"04",X"26",X"EF",X"2E",X"19",X"DD", + X"7E",X"1F",X"CD",X"62",X"32",X"DD",X"35",X"06",X"DD",X"36",X"0C",X"40",X"21",X"00",X"02",X"22", + X"5B",X"9A",X"C9",X"DD",X"7E",X"11",X"A7",X"C2",X"00",X"1B",X"C3",X"91",X"1B",X"DD",X"56",X"03", + X"DD",X"5E",X"04",X"21",X"F0",X"08",X"DD",X"7E",X"1F",X"CD",X"62",X"32",X"CD",X"09",X"1F",X"C9", + X"DD",X"7E",X"0C",X"A7",X"CA",X"ED",X"1A",X"FE",X"20",X"CA",X"11",X"1B",X"3D",X"DD",X"77",X"0C", + X"C9",X"DD",X"56",X"03",X"DD",X"5E",X"04",X"26",X"F3",X"2E",X"10",X"DD",X"7E",X"1F",X"CD",X"62", + X"32",X"DD",X"35",X"0C",X"C9",X"DD",X"7E",X"05",X"A7",X"C0",X"CD",X"3E",X"1B",X"DD",X"7E",X"11", + X"A7",X"C2",X"48",X"1B",X"CD",X"66",X"1B",X"CD",X"9E",X"1B",X"CD",X"14",X"1C",X"C9",X"3A",X"8B", + X"9C",X"FE",X"0E",X"D8",X"CD",X"80",X"20",X"C9",X"DD",X"7E",X"12",X"A7",X"C2",X"59",X"1B",X"CD", + X"53",X"1D",X"CD",X"14",X"1C",X"CD",X"70",X"1C",X"C9",X"CD",X"E7",X"1D",X"CD",X"47",X"1F",X"CD", + X"14",X"1C",X"CD",X"62",X"1E",X"C9",X"DD",X"7E",X"03",X"C6",X"02",X"DD",X"77",X"03",X"FE",X"F0", + X"D2",X"8E",X"1B",X"DD",X"7E",X"12",X"A7",X"C2",X"84",X"1B",X"DD",X"56",X"03",X"DD",X"5E",X"04", + X"CD",X"BC",X"33",X"C9",X"DD",X"56",X"03",X"DD",X"5E",X"04",X"CD",X"82",X"34",X"C9",X"CD",X"57", + X"20",X"DD",X"56",X"03",X"DD",X"5E",X"04",X"CD",X"B0",X"33",X"CD",X"09",X"1F",X"C9",X"FD",X"21", + X"B0",X"98",X"0E",X"05",X"11",X"20",X"00",X"3A",X"53",X"9A",X"06",X"06",X"FE",X"02",X"DA",X"B3", + X"1B",X"06",X"08",X"FD",X"7E",X"00",X"A7",X"C4",X"FE",X"1B",X"FD",X"19",X"0D",X"C2",X"B3",X"1B", + X"78",X"A7",X"C8",X"3A",X"23",X"9A",X"DD",X"96",X"03",X"D8",X"FE",X"10",X"D0",X"DD",X"36",X"0B", + X"00",X"DD",X"36",X"14",X"01",X"DD",X"56",X"03",X"DD",X"5E",X"04",X"C5",X"CD",X"B0",X"33",X"C1", + X"DD",X"36",X"11",X"FF",X"CB",X"48",X"C2",X"F4",X"1B",X"CB",X"50",X"C2",X"F9",X"1B",X"3E",X"03", + X"DD",X"77",X"1F",X"C9",X"DD",X"36",X"1F",X"01",X"C9",X"DD",X"36",X"1F",X"02",X"C9",X"FD",X"7E", + X"1F",X"FE",X"01",X"CA",X"0E",X"1C",X"FE",X"02",X"CA",X"11",X"1C",X"CB",X"98",X"C9",X"CB",X"88", + X"C9",X"CB",X"90",X"C9",X"3A",X"59",X"9A",X"DD",X"86",X"02",X"DD",X"46",X"01",X"CB",X"20",X"CB", + X"C0",X"A0",X"C0",X"DD",X"7E",X"13",X"3C",X"DD",X"77",X"13",X"FE",X"60",X"D8",X"DD",X"36",X"13", + X"00",X"16",X"09",X"FD",X"21",X"00",X"98",X"01",X"10",X"00",X"FD",X"7E",X"00",X"A7",X"CA",X"48", + X"1C",X"FD",X"09",X"15",X"C2",X"3A",X"1C",X"C9",X"FD",X"36",X"00",X"FF",X"DD",X"7E",X"03",X"DD", + X"46",X"04",X"FD",X"77",X"03",X"FD",X"70",X"04",X"FD",X"36",X"06",X"00",X"FD",X"36",X"05",X"00", + X"FD",X"77",X"08",X"FD",X"36",X"09",X"E8",X"FD",X"36",X"0A",X"00",X"FD",X"36",X"07",X"02",X"C9", + X"DD",X"4E",X"0D",X"DD",X"46",X"0E",X"CB",X"21",X"CB",X"10",X"CB",X"21",X"CB",X"10",X"DD",X"5E", + X"14",X"FD",X"21",X"A3",X"40",X"16",X"00",X"CB",X"23",X"CB",X"12",X"FD",X"19",X"FD",X"5E",X"00", + X"FD",X"56",X"01",X"D5",X"FD",X"E1",X"FD",X"09",X"FD",X"7E",X"00",X"FE",X"80",X"CA",X"E5",X"1C", + X"DD",X"86",X"03",X"DD",X"77",X"03",X"57",X"FD",X"7E",X"01",X"DD",X"86",X"04",X"DD",X"77",X"04", + X"5F",X"FD",X"66",X"02",X"FD",X"6E",X"03",X"DD",X"7E",X"1F",X"CD",X"62",X"32",X"DD",X"7E",X"03", + X"FE",X"F0",X"D2",X"F4",X"1E",X"FE",X"10",X"DA",X"F4",X"1E",X"DD",X"7E",X"04",X"FE",X"10",X"DA", + X"F4",X"1E",X"FE",X"F0",X"D2",X"F4",X"1E",X"DD",X"6E",X"0D",X"DD",X"66",X"0E",X"23",X"DD",X"75", + X"0D",X"DD",X"74",X"0E",X"C9",X"3E",X"01",X"DD",X"46",X"0A",X"DD",X"34",X"0A",X"B8",X"DA",X"10", + X"1D",X"FD",X"46",X"01",X"ED",X"5F",X"CB",X"47",X"CA",X"44",X"1D",X"78",X"CB",X"3F",X"CB",X"3F", + X"CB",X"3F",X"CB",X"3F",X"DD",X"77",X"14",X"DD",X"36",X"0D",X"00",X"DD",X"36",X"0E",X"00",X"C9", + X"DD",X"7E",X"14",X"FE",X"00",X"CA",X"2A",X"1D",X"FE",X"04",X"CA",X"37",X"1D",X"FE",X"06",X"CA", + X"2A",X"1D",X"FE",X"07",X"CA",X"37",X"1D",X"C3",X"F1",X"1C",X"DD",X"36",X"14",X"06",X"DD",X"36", + X"0D",X"00",X"DD",X"36",X"0E",X"00",X"C9",X"DD",X"36",X"14",X"07",X"DD",X"36",X"0D",X"00",X"DD", + X"36",X"0E",X"00",X"C9",X"78",X"E6",X"0F",X"DD",X"77",X"14",X"DD",X"36",X"0D",X"00",X"DD",X"36", + X"0E",X"00",X"C9",X"DD",X"7E",X"14",X"FE",X"03",X"CA",X"61",X"1D",X"FE",X"01",X"CA",X"61",X"1D", + X"C9",X"DD",X"7E",X"0D",X"FE",X"05",X"C0",X"3A",X"23",X"9A",X"DD",X"96",X"03",X"DA",X"76",X"1D", + X"FE",X"20",X"D0",X"C3",X"31",X"1C",X"ED",X"44",X"FE",X"20",X"D0",X"C3",X"31",X"1C",X"FD",X"21", + X"00",X"98",X"01",X"10",X"00",X"2E",X"09",X"FD",X"7E",X"00",X"A7",X"CA",X"95",X"1D",X"FD",X"09", + X"2D",X"C2",X"87",X"1D",X"C9",X"FD",X"36",X"00",X"FF",X"DD",X"36",X"07",X"FF",X"DD",X"7E",X"03", + X"FD",X"77",X"03",X"DD",X"7E",X"04",X"FD",X"77",X"04",X"FD",X"36",X"05",X"00",X"FD",X"36",X"06", + X"00",X"FD",X"36",X"07",X"01",X"FD",X"E5",X"E1",X"DD",X"75",X"08",X"DD",X"74",X"09",X"3E",X"E8", + X"FD",X"77",X"09",X"3A",X"23",X"9A",X"DD",X"96",X"03",X"DA",X"D8",X"1D",X"CB",X"3F",X"CB",X"3F", + X"CB",X"3F",X"CB",X"3F",X"FD",X"77",X"08",X"C9",X"ED",X"44",X"CB",X"3F",X"CB",X"3F",X"CB",X"3F", + X"CB",X"3F",X"2F",X"FD",X"77",X"08",X"C9",X"DD",X"7E",X"0B",X"E6",X"F0",X"C2",X"32",X"1E",X"3A", + X"52",X"9A",X"DD",X"BE",X"0A",X"D8",X"3A",X"23",X"9A",X"47",X"DD",X"7E",X"0B",X"E6",X"0F",X"C2", + X"1A",X"1E",X"DD",X"7E",X"03",X"90",X"D8",X"FE",X"20",X"D8",X"DD",X"36",X"0B",X"F0",X"DD",X"36", + X"0C",X"08",X"DD",X"34",X"0A",X"DD",X"36",X"16",X"00",X"C9",X"78",X"DD",X"96",X"03",X"D8",X"FE", + X"20",X"D8",X"DD",X"36",X"0B",X"FF",X"DD",X"36",X"0C",X"08",X"DD",X"34",X"0A",X"DD",X"36",X"16", + X"00",X"C9",X"CD",X"57",X"1E",X"DD",X"56",X"03",X"DD",X"5E",X"04",X"26",X"BF",X"2E",X"11",X"DD", + X"7E",X"1F",X"CD",X"62",X"32",X"DD",X"7E",X"0C",X"3D",X"DD",X"77",X"0C",X"C0",X"DD",X"7E",X"0B", + X"2F",X"E6",X"0F",X"DD",X"77",X"0B",X"C9",X"DD",X"7E",X"04",X"3C",X"FE",X"90",X"D0",X"DD",X"77", + X"04",X"C9",X"DD",X"7E",X"0B",X"E6",X"F0",X"C0",X"DD",X"7E",X"07",X"A7",X"C2",X"CF",X"1E",X"DD", + X"34",X"0C",X"DD",X"7E",X"0B",X"E6",X"0F",X"C2",X"8D",X"1E",X"CD",X"B0",X"1E",X"DD",X"7E",X"03", + X"C6",X"02",X"DD",X"77",X"03",X"FE",X"F0",X"D2",X"F4",X"1E",X"C3",X"A0",X"1E",X"CD",X"C2",X"1E", + X"DD",X"7E",X"03",X"D6",X"02",X"DD",X"77",X"03",X"FE",X"10",X"DA",X"F4",X"1E",X"C3",X"A0",X"1E", + X"DD",X"56",X"03",X"DD",X"5E",X"04",X"DD",X"7E",X"1F",X"CD",X"62",X"32",X"DD",X"34",X"0C",X"C9", + X"DD",X"7E",X"0C",X"CB",X"47",X"CA",X"BD",X"1E",X"26",X"BB",X"2E",X"11",X"C9",X"26",X"B7",X"2E", + X"11",X"C9",X"DD",X"7E",X"0C",X"CB",X"47",X"CA",X"EF",X"1E",X"26",X"C7",X"2E",X"11",X"C9",X"DD", + X"7E",X"0B",X"E6",X"0F",X"C2",X"E8",X"1E",X"26",X"CB",X"2E",X"11",X"DD",X"56",X"03",X"DD",X"5E", + X"04",X"DD",X"7E",X"1F",X"CD",X"62",X"32",X"C9",X"26",X"CF",X"2E",X"11",X"C3",X"DB",X"1E",X"26", + X"C3",X"2E",X"11",X"C9",X"16",X"08",X"1E",X"FF",X"26",X"FF",X"2E",X"FF",X"DD",X"7E",X"1F",X"CD", + X"62",X"32",X"CD",X"09",X"1F",X"CD",X"57",X"20",X"C9",X"DD",X"46",X"07",X"DD",X"4E",X"08",X"DD", + X"56",X"09",X"DD",X"5E",X"12",X"DD",X"E5",X"E1",X"23",X"23",X"23",X"3E",X"1D",X"36",X"00",X"23", + X"3D",X"C2",X"1D",X"1F",X"DD",X"36",X"00",X"00",X"DD",X"70",X"07",X"DD",X"71",X"08",X"DD",X"72", + X"09",X"DD",X"73",X"12",X"C9",X"DD",X"7E",X"07",X"A7",X"C8",X"DD",X"6E",X"08",X"DD",X"66",X"09", + X"E5",X"FD",X"E1",X"CD",X"04",X"1A",X"C9",X"DD",X"7E",X"07",X"A7",X"C0",X"DD",X"7E",X"16",X"3C", + X"DD",X"77",X"16",X"FE",X"04",X"D0",X"DD",X"7E",X"0B",X"47",X"E6",X"F0",X"C0",X"78",X"E6",X"0F", + X"CA",X"6D",X"1F",X"3A",X"23",X"9A",X"DD",X"BE",X"03",X"D0",X"C3",X"7E",X"1D",X"3A",X"23",X"9A", + X"DD",X"BE",X"03",X"D8",X"C3",X"7E",X"1D",X"3A",X"59",X"9A",X"E6",X"3F",X"C0",X"3A",X"89",X"9C", + X"FE",X"08",X"D2",X"8A",X"1F",X"3C",X"32",X"89",X"9C",X"C9",X"AF",X"32",X"89",X"9C",X"3A",X"8B", + X"9C",X"47",X"3A",X"8C",X"9C",X"4F",X"CD",X"C5",X"1F",X"90",X"D8",X"C8",X"91",X"C8",X"D8",X"3A", + X"8A",X"9C",X"FE",X"09",X"D2",X"B8",X"1F",X"4F",X"3C",X"32",X"8A",X"9C",X"06",X"00",X"21",X"4F", + X"3F",X"09",X"5E",X"16",X"10",X"C3",X"D0",X"1F",X"AF",X"32",X"8A",X"9C",X"3A",X"4F",X"3F",X"5F", + X"16",X"10",X"C3",X"D0",X"1F",X"3A",X"FF",X"9B",X"CB",X"77",X"3E",X"10",X"C8",X"3E",X"18",X"C9", + X"3A",X"53",X"9A",X"FE",X"00",X"CA",X"E5",X"1F",X"FE",X"01",X"CA",X"0F",X"20",X"FE",X"02",X"CA", + X"14",X"20",X"C3",X"39",X"20",X"26",X"00",X"DD",X"21",X"B0",X"98",X"01",X"20",X"00",X"2E",X"05", + X"DD",X"7E",X"00",X"A7",X"CA",X"FE",X"1F",X"DD",X"09",X"2D",X"C2",X"F0",X"1F",X"C9",X"DD",X"36", + X"00",X"FF",X"DD",X"72",X"03",X"DD",X"73",X"04",X"DD",X"74",X"12",X"CD",X"4F",X"20",X"C9",X"26", + X"FF",X"C3",X"E7",X"1F",X"DD",X"21",X"F0",X"99",X"01",X"10",X"00",X"2E",X"03",X"DD",X"7E",X"00", + X"A7",X"CA",X"2B",X"20",X"DD",X"09",X"2D",X"C2",X"1D",X"20",X"C9",X"DD",X"36",X"00",X"FF",X"DD", + X"72",X"03",X"DD",X"73",X"04",X"CD",X"4F",X"20",X"C9",X"ED",X"5F",X"E6",X"03",X"FE",X"00",X"CA", + X"E5",X"1F",X"FE",X"01",X"CA",X"0F",X"20",X"FE",X"02",X"CA",X"14",X"20",X"C3",X"14",X"20",X"3A", + X"8C",X"9C",X"3C",X"32",X"8C",X"9C",X"C9",X"3A",X"8C",X"9C",X"3D",X"F8",X"32",X"8C",X"9C",X"C9", + X"3A",X"8B",X"9C",X"3C",X"32",X"8B",X"9C",X"3A",X"8C",X"9C",X"3D",X"F8",X"32",X"8C",X"9C",X"C9", + X"36",X"00",X"23",X"23",X"23",X"0E",X"00",X"D6",X"03",X"71",X"23",X"3D",X"C2",X"79",X"20",X"C9", + X"3A",X"53",X"9A",X"FE",X"02",X"D2",X"9F",X"20",X"FD",X"21",X"50",X"99",X"01",X"20",X"00",X"1E", + X"05",X"FD",X"7E",X"00",X"A7",X"CA",X"AB",X"20",X"FD",X"09",X"1D",X"C2",X"91",X"20",X"C9",X"FD", + X"21",X"70",X"99",X"01",X"20",X"00",X"1E",X"04",X"C3",X"91",X"20",X"FD",X"36",X"00",X"FF",X"DD", + X"7E",X"03",X"FD",X"77",X"03",X"DD",X"7E",X"04",X"FD",X"77",X"04",X"AF",X"FD",X"77",X"05",X"FD", + X"77",X"06",X"FD",X"77",X"0C",X"FD",X"77",X"17",X"FD",X"77",X"18",X"FD",X"36",X"1E",X"00",X"C9", + X"DD",X"21",X"F0",X"97",X"11",X"10",X"00",X"DD",X"19",X"DD",X"E5",X"E1",X"01",X"90",X"98",X"ED", + X"42",X"C8",X"CD",X"E8",X"20",X"C3",X"D4",X"20",X"DD",X"7E",X"00",X"A7",X"C8",X"DD",X"7E",X"07", + X"FE",X"02",X"C0",X"CD",X"11",X"21",X"DD",X"7E",X"05",X"A7",X"C0",X"DD",X"7E",X"00",X"A7",X"C8", + X"3A",X"59",X"9A",X"DD",X"86",X"02",X"DD",X"A6",X"01",X"C0",X"CD",X"1D",X"21",X"CD",X"58",X"21", + X"C9",X"DD",X"E5",X"FD",X"E1",X"DD",X"7E",X"05",X"A7",X"C2",X"3F",X"31",X"C9",X"DD",X"7E",X"04", + X"FE",X"D4",X"D0",X"C6",X"02",X"DD",X"77",X"04",X"5F",X"DD",X"56",X"03",X"26",X"0D",X"2E",X"00", + X"DD",X"7E",X"0E",X"CD",X"0E",X"32",X"DD",X"7E",X"04",X"FE",X"D4",X"D8",X"DD",X"7E",X"03",X"FE", + X"80",X"D2",X"4A",X"21",X"21",X"4D",X"46",X"C3",X"4D",X"21",X"21",X"37",X"46",X"DD",X"75",X"0B", + X"DD",X"74",X"0C",X"DD",X"36",X"0A",X"00",X"C9",X"DD",X"7E",X"04",X"FE",X"D4",X"D8",X"FE",X"E9", + X"DA",X"7C",X"21",X"DD",X"36",X"05",X"FF",X"DD",X"56",X"03",X"DD",X"5E",X"04",X"26",X"0A",X"2E", + X"00",X"DD",X"7E",X"0E",X"CD",X"0E",X"32",X"DD",X"36",X"06",X"08",X"C9",X"DD",X"66",X"0C",X"DD", + X"6E",X"0B",X"E5",X"FD",X"E1",X"DD",X"7E",X"0A",X"A7",X"CA",X"95",X"21",X"11",X"02",X"00",X"FD", + X"19",X"3D",X"C2",X"8C",X"21",X"FD",X"7E",X"01",X"DD",X"86",X"03",X"DD",X"77",X"03",X"57",X"FD", + X"7E",X"00",X"DD",X"86",X"04",X"DD",X"77",X"04",X"5F",X"26",X"0D",X"2E",X"00",X"DD",X"7E",X"0E", + X"CD",X"0E",X"32",X"DD",X"34",X"0A",X"C9",X"DD",X"21",X"E0",X"99",X"11",X"10",X"00",X"DD",X"19", + X"DD",X"E5",X"E1",X"01",X"20",X"9A",X"ED",X"42",X"C8",X"CD",X"CF",X"21",X"C3",X"BB",X"21",X"DD", + X"7E",X"00",X"A7",X"C8",X"CD",X"F1",X"21",X"3A",X"59",X"9A",X"DD",X"86",X"02",X"DD",X"A6",X"01", + X"C0",X"CD",X"69",X"22",X"CD",X"99",X"22",X"CD",X"22",X"23",X"CD",X"91",X"23",X"CD",X"18",X"24", + X"C9",X"DD",X"7E",X"05",X"A7",X"C2",X"49",X"22",X"CD",X"6E",X"31",X"A7",X"C8",X"21",X"EC",X"45", + X"FD",X"21",X"20",X"9A",X"DD",X"7E",X"04",X"47",X"96",X"FD",X"BE",X"11",X"D0",X"23",X"78",X"86", + X"FD",X"BE",X"11",X"D8",X"23",X"DD",X"7E",X"03",X"47",X"96",X"FD",X"BE",X"10",X"D0",X"23",X"78", + X"86",X"FD",X"BE",X"10",X"D8",X"DD",X"36",X"05",X"FF",X"DD",X"36",X"06",X"07",X"FD",X"36",X"09", + X"00",X"21",X"50",X"00",X"22",X"5B",X"9A",X"CD",X"60",X"20",X"DD",X"56",X"03",X"DD",X"5E",X"04", + X"CD",X"A6",X"33",X"21",X"16",X"9C",X"CB",X"DE",X"C9",X"3A",X"59",X"9A",X"DD",X"86",X"02",X"DD", + X"A6",X"01",X"C0",X"DD",X"35",X"06",X"C0",X"DD",X"36",X"00",X"00",X"DD",X"36",X"05",X"00",X"DD", + X"56",X"03",X"DD",X"5E",X"04",X"CD",X"B0",X"33",X"C9",X"DD",X"7E",X"05",X"A7",X"C0",X"DD",X"7E", + X"00",X"A7",X"C8",X"DD",X"7E",X"03",X"C6",X"02",X"FE",X"FC",X"D2",X"88",X"22",X"DD",X"77",X"03", + X"57",X"DD",X"5E",X"04",X"CD",X"9C",X"33",X"C9",X"DD",X"36",X"00",X"00",X"DD",X"56",X"03",X"DD", + X"5E",X"04",X"CD",X"B0",X"33",X"CD",X"57",X"20",X"C9",X"DD",X"7E",X"08",X"A7",X"C2",X"E7",X"22", + X"DD",X"7E",X"05",X"A7",X"C0",X"FD",X"21",X"F0",X"97",X"11",X"10",X"00",X"0E",X"08",X"FD",X"19", + X"FD",X"7E",X"00",X"A7",X"CA",X"BC",X"22",X"0D",X"C2",X"AE",X"22",X"C9",X"FD",X"36",X"00",X"FF", + X"FD",X"36",X"07",X"08",X"FD",X"36",X"05",X"00",X"FD",X"36",X"06",X"00",X"DD",X"7E",X"03",X"FD", + X"77",X"03",X"DD",X"7E",X"04",X"C6",X"0A",X"FD",X"77",X"04",X"DD",X"34",X"08",X"FD",X"E5",X"E1", + X"DD",X"74",X"0A",X"DD",X"75",X"09",X"C9",X"DD",X"34",X"08",X"DD",X"7E",X"08",X"FE",X"1E",X"CA", + X"18",X"23",X"FE",X"06",X"CA",X"1D",X"23",X"D0",X"DD",X"66",X"0A",X"DD",X"6E",X"09",X"E5",X"FD", + X"E1",X"FD",X"7E",X"04",X"C6",X"02",X"FD",X"77",X"04",X"5F",X"FD",X"56",X"03",X"26",X"0B",X"2E", + X"00",X"FD",X"7E",X"0E",X"CD",X"0E",X"32",X"C9",X"DD",X"36",X"08",X"00",X"C9",X"DD",X"36",X"07", + X"FF",X"C9",X"DD",X"7E",X"07",X"A7",X"C8",X"FD",X"21",X"80",X"98",X"11",X"10",X"00",X"0E",X"02", + X"FD",X"19",X"FD",X"7E",X"00",X"A7",X"CA",X"3E",X"23",X"0D",X"C2",X"30",X"23",X"C9",X"FD",X"E5", + X"D1",X"DD",X"66",X"0A",X"DD",X"6E",X"09",X"E5",X"FD",X"E1",X"FD",X"46",X"03",X"FD",X"4E",X"04", + X"FD",X"36",X"00",X"00",X"FD",X"36",X"07",X"00",X"D5",X"FD",X"E1",X"FD",X"36",X"00",X"FF",X"FD", + X"70",X"03",X"FD",X"71",X"04",X"FD",X"36",X"05",X"00",X"FD",X"21",X"20",X"9A",X"FD",X"7E",X"03", + X"D5",X"FD",X"E1",X"FD",X"77",X"08",X"DD",X"36",X"07",X"00",X"E5",X"FD",X"E1",X"16",X"08",X"1E", + X"08",X"26",X"00",X"2E",X"00",X"FD",X"7E",X"0E",X"CD",X"0E",X"32",X"21",X"16",X"9C",X"CB",X"E6", + X"C9",X"DD",X"7E",X"07",X"A7",X"C8",X"3A",X"53",X"9A",X"FE",X"03",X"C2",X"A7",X"23",X"FD",X"21", + X"50",X"99",X"0E",X"04",X"C3",X"AD",X"23",X"FD",X"21",X"30",X"99",X"0E",X"05",X"11",X"20",X"00", + X"3A",X"52",X"9A",X"FE",X"03",X"D2",X"B9",X"23",X"0D",X"FD",X"19",X"FD",X"7E",X"00",X"A7",X"CA", + X"C7",X"23",X"0D",X"C2",X"B9",X"23",X"C9",X"FD",X"E5",X"D1",X"DD",X"66",X"0A",X"DD",X"6E",X"09", + X"E5",X"FD",X"E1",X"FD",X"46",X"03",X"FD",X"4E",X"04",X"FD",X"36",X"00",X"00",X"D5",X"FD",X"E1", + X"FD",X"36",X"00",X"FF",X"FD",X"70",X"03",X"FD",X"71",X"04",X"FD",X"36",X"05",X"00",X"FD",X"36", + X"06",X"00",X"FD",X"36",X"0C",X"00",X"FD",X"36",X"17",X"00",X"FD",X"36",X"18",X"00",X"FD",X"36", + X"1E",X"00",X"DD",X"36",X"07",X"00",X"E5",X"FD",X"E1",X"16",X"08",X"1E",X"08",X"26",X"00",X"2E", + X"00",X"FD",X"7E",X"0E",X"CD",X"0E",X"32",X"C9",X"DD",X"7E",X"07",X"A7",X"C8",X"DD",X"66",X"0A", + X"DD",X"6E",X"09",X"E5",X"FD",X"E1",X"FD",X"36",X"05",X"00",X"FD",X"36",X"06",X"00",X"FD",X"36", + X"0A",X"00",X"FD",X"36",X"07",X"02",X"DD",X"36",X"07",X"00",X"C9",X"DD",X"21",X"80",X"98",X"11", + X"10",X"00",X"DD",X"19",X"DD",X"E5",X"E1",X"01",X"B0",X"98",X"ED",X"42",X"C8",X"CD",X"53",X"24", + X"C3",X"3F",X"24",X"DD",X"7E",X"00",X"A7",X"C8",X"CD",X"76",X"24",X"DD",X"7E",X"05",X"A7",X"C0", + X"3A",X"59",X"9A",X"DD",X"86",X"02",X"DD",X"A6",X"01",X"C0",X"DD",X"7E",X"00",X"A7",X"C8",X"CD", + X"2D",X"25",X"CD",X"41",X"25",X"C9",X"DD",X"7E",X"05",X"A7",X"C2",X"E6",X"24",X"FD",X"21",X"20", + X"9A",X"CD",X"6E",X"31",X"A7",X"CA",X"A2",X"24",X"21",X"E8",X"45",X"FD",X"56",X"10",X"FD",X"5E", + X"11",X"CD",X"BA",X"24",X"DD",X"7E",X"05",X"A7",X"CA",X"A2",X"24",X"FD",X"36",X"09",X"00",X"C3", + X"D7",X"24",X"21",X"E8",X"45",X"FD",X"56",X"1E",X"FD",X"5E",X"08",X"CD",X"BA",X"24",X"DD",X"7E", + X"05",X"A7",X"C8",X"FD",X"36",X"07",X"00",X"C3",X"D7",X"24",X"DD",X"7E",X"04",X"96",X"BB",X"D0", + X"23",X"DD",X"7E",X"04",X"86",X"BB",X"D8",X"23",X"DD",X"7E",X"03",X"96",X"BA",X"D0",X"23",X"86", + X"BA",X"D8",X"DD",X"36",X"05",X"FF",X"C9",X"DD",X"36",X"06",X"04",X"DD",X"36",X"07",X"05",X"21", + X"00",X"02",X"22",X"5B",X"9A",X"C9",X"3A",X"59",X"9A",X"DD",X"86",X"02",X"DD",X"A6",X"01",X"C0", + X"DD",X"7E",X"06",X"A7",X"CA",X"02",X"25",X"26",X"EB",X"2E",X"19",X"CD",X"20",X"25",X"DD",X"35", + X"06",X"C9",X"26",X"F3",X"2E",X"12",X"CD",X"20",X"25",X"DD",X"35",X"07",X"C0",X"DD",X"36",X"00", + X"00",X"26",X"FF",X"2E",X"0F",X"16",X"08",X"1E",X"10",X"DD",X"7E",X"0E",X"CD",X"62",X"32",X"C9", + X"DD",X"56",X"03",X"DD",X"5E",X"04",X"DD",X"7E",X"0E",X"CD",X"62",X"32",X"C9",X"DD",X"7E",X"04", + X"FE",X"70",X"D8",X"FE",X"A8",X"D0",X"FD",X"21",X"20",X"9A",X"FD",X"7E",X"03",X"DD",X"77",X"08", + X"C9",X"DD",X"7E",X"03",X"FE",X"10",X"DA",X"58",X"25",X"FE",X"F0",X"D2",X"58",X"25",X"DD",X"7E", + X"04",X"C6",X"02",X"FE",X"E8",X"DA",X"75",X"25",X"DD",X"36",X"00",X"00",X"DD",X"36",X"05",X"00", + X"26",X"FF",X"2E",X"0F",X"16",X"08",X"DD",X"72",X"03",X"1E",X"10",X"DD",X"73",X"04",X"DD",X"7E", + X"0E",X"CD",X"62",X"32",X"C9",X"DD",X"77",X"04",X"3E",X"E8",X"DD",X"96",X"04",X"47",X"CB",X"28", + X"DD",X"7E",X"08",X"DD",X"BE",X"03",X"CA",X"AA",X"25",X"DD",X"96",X"03",X"CB",X"7F",X"C2",X"9E", + X"25",X"B8",X"DA",X"98",X"25",X"DD",X"34",X"03",X"DD",X"34",X"03",X"C3",X"AA",X"25",X"ED",X"44", + X"B8",X"DA",X"A7",X"25",X"DD",X"35",X"03",X"DD",X"35",X"03",X"DD",X"7E",X"0F",X"FE",X"DB",X"CA", + X"B9",X"25",X"DD",X"36",X"0F",X"DB",X"C3",X"BD",X"25",X"DD",X"36",X"0F",X"DF",X"DD",X"56",X"03", + X"DD",X"5E",X"04",X"DD",X"66",X"0F",X"2E",X"14",X"DD",X"7E",X"0E",X"CD",X"62",X"32",X"C9",X"DD", + X"21",X"30",X"99",X"11",X"20",X"00",X"DD",X"19",X"DD",X"E5",X"E1",X"01",X"F0",X"99",X"ED",X"42", + X"C8",X"CD",X"E7",X"25",X"C3",X"D3",X"25",X"DD",X"7E",X"1E",X"FE",X"00",X"C0",X"DD",X"7E",X"00", + X"A7",X"C8",X"DD",X"36",X"01",X"0F",X"CD",X"1A",X"26",X"CD",X"4B",X"26",X"DD",X"7E",X"05",X"A7", + X"C0",X"3A",X"59",X"9A",X"DD",X"86",X"02",X"DD",X"A6",X"01",X"C0",X"DD",X"7E",X"00",X"A7",X"C8", + X"DD",X"34",X"06",X"CD",X"C7",X"26",X"CD",X"9F",X"27",X"C9",X"DD",X"7E",X"04",X"FE",X"60",X"D8", + X"DD",X"7E",X"17",X"A7",X"C0",X"FD",X"21",X"30",X"99",X"11",X"20",X"00",X"0E",X"05",X"FD",X"19", + X"0D",X"CA",X"42",X"26",X"FD",X"7E",X"00",X"A7",X"CA",X"2E",X"26",X"FD",X"36",X"0A",X"FF",X"C3", + X"2E",X"26",X"DD",X"36",X"0A",X"00",X"DD",X"36",X"17",X"FF",X"C9",X"DD",X"7E",X"05",X"A7",X"C2", + X"98",X"26",X"CD",X"6E",X"31",X"A7",X"C8",X"FD",X"21",X"20",X"9A",X"21",X"F0",X"45",X"DD",X"7E", + X"04",X"96",X"FD",X"BE",X"11",X"D0",X"23",X"DD",X"7E",X"04",X"86",X"FD",X"BE",X"11",X"D8",X"23", + X"DD",X"7E",X"03",X"96",X"FD",X"BE",X"10",X"D0",X"23",X"DD",X"7E",X"03",X"86",X"FD",X"BE",X"10", + X"D8",X"DD",X"36",X"05",X"FF",X"FD",X"36",X"09",X"00",X"21",X"00",X"03",X"22",X"5B",X"9A",X"DD", + X"36",X"06",X"04",X"DD",X"36",X"0F",X"F7",X"C9",X"3A",X"59",X"9A",X"DD",X"86",X"02",X"DD",X"A6", + X"01",X"C0",X"DD",X"56",X"03",X"DD",X"5E",X"04",X"DD",X"66",X"0F",X"2E",X"12",X"DD",X"7E",X"1F", + X"CD",X"62",X"32",X"DD",X"35",X"06",X"C0",X"DD",X"36",X"00",X"00",X"CD",X"F6",X"2F",X"DD",X"36", + X"17",X"00",X"DD",X"36",X"18",X"00",X"C9",X"DD",X"66",X"0E",X"DD",X"6E",X"0D",X"E5",X"FD",X"E1", + X"DD",X"7E",X"0C",X"A7",X"CA",X"0C",X"27",X"11",X"04",X"00",X"FD",X"19",X"3D",X"C2",X"DA",X"26", + X"FD",X"7E",X"00",X"FE",X"80",X"CA",X"0C",X"27",X"DD",X"7E",X"03",X"FD",X"86",X"01",X"DD",X"77", + X"03",X"57",X"DD",X"7E",X"04",X"FD",X"86",X"00",X"DD",X"77",X"04",X"5F",X"FD",X"66",X"02",X"FD", + X"6E",X"03",X"DD",X"7E",X"1F",X"CD",X"62",X"32",X"DD",X"34",X"0C",X"C9",X"DD",X"7E",X"18",X"A7", + X"CA",X"3A",X"27",X"21",X"63",X"46",X"C3",X"94",X"27",X"ED",X"5F",X"E6",X"7F",X"47",X"3A",X"59", + X"9A",X"80",X"47",X"3A",X"52",X"9A",X"17",X"17",X"4F",X"3E",X"3F",X"91",X"B8",X"DA",X"3A",X"27", + X"21",X"63",X"46",X"DD",X"36",X"18",X"FF",X"C3",X"94",X"27",X"21",X"E9",X"46",X"DD",X"7E",X"03", + X"BE",X"DA",X"58",X"27",X"23",X"BE",X"DA",X"6C",X"27",X"23",X"BE",X"DA",X"80",X"27",X"23",X"3E", + X"FF",X"BE",X"CA",X"58",X"27",X"C3",X"3D",X"27",X"DD",X"7E",X"06",X"FE",X"08",X"D2",X"66",X"27", + X"21",X"63",X"46",X"C3",X"94",X"27",X"21",X"8E",X"46",X"C3",X"94",X"27",X"DD",X"7E",X"06",X"FE", + X"08",X"D2",X"7A",X"27",X"21",X"7C",X"46",X"C3",X"94",X"27",X"21",X"AF",X"46",X"C3",X"94",X"27", + X"DD",X"7E",X"06",X"FE",X"08",X"D2",X"8E",X"27",X"21",X"85",X"46",X"C3",X"94",X"27",X"21",X"CC", + X"46",X"C3",X"94",X"27",X"DD",X"74",X"0E",X"DD",X"75",X"0D",X"DD",X"36",X"0C",X"01",X"C9",X"DD", + X"7E",X"04",X"FE",X"A0",X"D8",X"DD",X"7E",X"18",X"A7",X"C2",X"E6",X"27",X"DD",X"36",X"01",X"0F", + X"DD",X"56",X"03",X"1E",X"A0",X"DD",X"73",X"04",X"DD",X"36",X"06",X"00",X"DD",X"36",X"09",X"00", + X"DD",X"36",X"0B",X"00",X"DD",X"36",X"0C",X"00",X"26",X"83",X"DD",X"74",X"0F",X"DD",X"36",X"15", + X"00",X"DD",X"36",X"17",X"00",X"DD",X"36",X"18",X"00",X"DD",X"36",X"1E",X"FF",X"2E",X"12",X"DD", + X"7E",X"1F",X"CD",X"62",X"32",X"C9",X"16",X"08",X"DD",X"72",X"03",X"1E",X"10",X"DD",X"73",X"04", + X"26",X"FF",X"2E",X"0F",X"DD",X"7E",X"1F",X"CD",X"62",X"32",X"DD",X"36",X"00",X"00",X"DD",X"36", + X"17",X"00",X"DD",X"36",X"18",X"00",X"DD",X"36",X"06",X"00",X"C9",X"3A",X"59",X"9A",X"E6",X"0F", + X"C2",X"1F",X"28",X"3A",X"6D",X"99",X"3D",X"C2",X"1C",X"28",X"3E",X"8F",X"32",X"6D",X"99",X"DD", + X"21",X"30",X"99",X"11",X"20",X"00",X"DD",X"19",X"DD",X"E5",X"E1",X"01",X"F0",X"99",X"ED",X"42", + X"C8",X"CD",X"37",X"28",X"C3",X"23",X"28",X"CD",X"91",X"28",X"DD",X"7E",X"00",X"A7",X"C8",X"DD", + X"7E",X"1E",X"FE",X"FF",X"C0",X"3A",X"26",X"9A",X"A7",X"C0",X"3A",X"25",X"9A",X"A7",X"C0",X"CD", + X"AB",X"29",X"DD",X"7E",X"05",X"A7",X"C0",X"3A",X"6D",X"99",X"FE",X"8F",X"C2",X"63",X"28",X"DD", + X"36",X"0A",X"FF",X"3A",X"59",X"9A",X"DD",X"86",X"02",X"DD",X"A6",X"01",X"C0",X"DD",X"7E",X"00", + X"A7",X"C8",X"DD",X"7E",X"09",X"FE",X"00",X"CA",X"89",X"28",X"FE",X"20",X"CA",X"8D",X"28",X"CD", + X"0A",X"2B",X"CD",X"65",X"2C",X"CD",X"FB",X"2C",X"C9",X"CD",X"78",X"2A",X"C9",X"CD",X"40",X"2E", + X"C9",X"DD",X"7E",X"11",X"A7",X"C2",X"6F",X"29",X"DD",X"7E",X"07",X"A7",X"C8",X"DD",X"66",X"14", + X"DD",X"6E",X"13",X"E5",X"FD",X"E1",X"FD",X"7E",X"05",X"A7",X"CA",X"BA",X"28",X"CD",X"3F",X"31", + X"FD",X"7E",X"00",X"A7",X"C0",X"DD",X"36",X"07",X"00",X"C9",X"3A",X"59",X"9A",X"DD",X"86",X"02", + X"E6",X"07",X"C0",X"FD",X"66",X"0C",X"FD",X"6E",X"0B",X"FD",X"7E",X"0A",X"A7",X"CA",X"DC",X"28", + X"23",X"23",X"3D",X"C2",X"D0",X"28",X"7E",X"FE",X"80",X"CA",X"FD",X"28",X"FD",X"7E",X"04",X"86", + X"FD",X"77",X"04",X"5F",X"23",X"FD",X"7E",X"03",X"86",X"FD",X"77",X"03",X"57",X"26",X"0B",X"2E", + X"00",X"FD",X"7E",X"0E",X"CD",X"0E",X"32",X"FD",X"34",X"0A",X"C3",X"13",X"29",X"FD",X"7E",X"04", + X"C6",X"03",X"FD",X"77",X"04",X"5F",X"FD",X"56",X"03",X"26",X"0B",X"2E",X"00",X"FD",X"7E",X"0E", + X"CD",X"0E",X"32",X"FD",X"7E",X"04",X"FD",X"BE",X"09",X"D8",X"FD",X"7E",X"09",X"FE",X"E8",X"D2", + X"56",X"29",X"21",X"40",X"9A",X"DD",X"5E",X"10",X"16",X"00",X"CB",X"23",X"1D",X"19",X"36",X"FF", + X"DD",X"36",X"11",X"FF",X"DD",X"36",X"12",X"02",X"DD",X"56",X"10",X"CD",X"FB",X"36",X"FD",X"36", + X"00",X"00",X"16",X"08",X"1E",X"10",X"26",X"00",X"2E",X"00",X"FD",X"7E",X"0E",X"CD",X"0E",X"32", + X"21",X"16",X"9C",X"CB",X"DE",X"C9",X"FD",X"36",X"05",X"FF",X"FD",X"36",X"06",X"03",X"FD",X"56", + X"03",X"FD",X"5E",X"04",X"26",X"0A",X"2E",X"00",X"FD",X"7E",X"0E",X"CD",X"0E",X"32",X"C9",X"DD", + X"7E",X"11",X"FE",X"0F",X"CA",X"8A",X"29",X"DD",X"35",X"12",X"C0",X"DD",X"36",X"11",X"0F",X"DD", + X"36",X"12",X"02",X"DD",X"56",X"10",X"CD",X"13",X"37",X"C9",X"DD",X"35",X"12",X"C0",X"DD",X"36", + X"11",X"00",X"DD",X"56",X"10",X"CD",X"A6",X"36",X"21",X"40",X"9A",X"DD",X"5E",X"10",X"16",X"00", + X"CB",X"23",X"1D",X"19",X"36",X"FF",X"DD",X"36",X"07",X"00",X"C9",X"DD",X"7E",X"05",X"A7",X"C2", + X"0F",X"2A",X"DD",X"7E",X"09",X"FE",X"20",X"C2",X"2F",X"2A",X"3A",X"54",X"9A",X"A7",X"C8",X"DD", + X"7E",X"04",X"FE",X"E6",X"D8",X"FD",X"21",X"20",X"9A",X"FD",X"7E",X"03",X"D6",X"10",X"DD",X"BE", + X"03",X"D0",X"FD",X"7E",X"03",X"C6",X"10",X"DD",X"BE",X"03",X"D8",X"DD",X"36",X"05",X"FF",X"DD", + X"36",X"06",X"50",X"21",X"00",X"03",X"22",X"5B",X"9A",X"DD",X"56",X"03",X"DD",X"5E",X"04",X"DD", + X"7E",X"0B",X"FE",X"10",X"CA",X"FC",X"29",X"26",X"77",X"C3",X"FE",X"29",X"26",X"6B",X"2E",X"12", + X"DD",X"75",X"0F",X"DD",X"7E",X"1F",X"CD",X"62",X"32",X"21",X"16",X"9C",X"CB",X"EE",X"C9",X"DD", + X"35",X"06",X"C0",X"DD",X"36",X"00",X"00",X"DD",X"36",X"1E",X"00",X"DD",X"36",X"05",X"00",X"DD", + X"36",X"09",X"00",X"DD",X"36",X"0C",X"00",X"DD",X"36",X"15",X"00",X"CD",X"F6",X"2F",X"C9",X"21", + X"F4",X"45",X"FD",X"21",X"20",X"9A",X"FD",X"7E",X"07",X"A7",X"C8",X"DD",X"7E",X"04",X"96",X"FD", + X"BE",X"08",X"D0",X"23",X"DD",X"7E",X"04",X"86",X"FD",X"BE",X"08",X"D8",X"23",X"DD",X"7E",X"03", + X"96",X"FD",X"BE",X"1E",X"D0",X"23",X"DD",X"7E",X"03",X"86",X"FD",X"BE",X"1E",X"D8",X"FD",X"36", + X"07",X"00",X"DD",X"7E",X"09",X"FE",X"12",X"C2",X"DB",X"29",X"21",X"00",X"03",X"22",X"5B",X"9A", + X"21",X"16",X"9C",X"CB",X"EE",X"C3",X"13",X"2A",X"DD",X"7E",X"07",X"A7",X"C0",X"FD",X"21",X"87", + X"47",X"11",X"03",X"00",X"0E",X"00",X"DD",X"7E",X"03",X"FD",X"BE",X"01",X"D2",X"9B",X"2A",X"FD", + X"19",X"0C",X"79",X"FE",X"03",X"CA",X"9B",X"2A",X"C3",X"86",X"2A",X"79",X"A7",X"CA",X"DE",X"2A", + X"DD",X"71",X"10",X"21",X"40",X"9A",X"5F",X"16",X"00",X"CB",X"23",X"1D",X"19",X"7E",X"A7",X"C2", + X"DE",X"2A",X"DD",X"36",X"0B",X"10",X"3A",X"40",X"9A",X"FE",X"00",X"C2",X"DA",X"2A",X"CD",X"0B", + X"30",X"A7",X"CA",X"C8",X"2A",X"CD",X"2A",X"30",X"DD",X"36",X"09",X"10",X"21",X"E8",X"47",X"DD", + X"74",X"0E",X"DD",X"75",X"0D",X"DD",X"36",X"0C",X"00",X"C9",X"CD",X"2A",X"30",X"C9",X"0C",X"DD", + X"71",X"10",X"DD",X"36",X"09",X"10",X"DD",X"36",X"0B",X"20",X"DD",X"7E",X"10",X"FE",X"04",X"CA", + X"F8",X"2A",X"21",X"C7",X"47",X"C3",X"FF",X"2A",X"21",X"09",X"48",X"DD",X"36",X"0B",X"10",X"DD", + X"74",X"0E",X"DD",X"75",X"0D",X"DD",X"36",X"0C",X"00",X"C9",X"DD",X"7E",X"09",X"FE",X"10",X"C0", + X"DD",X"7E",X"07",X"A7",X"C0",X"FD",X"21",X"6F",X"47",X"11",X"03",X"00",X"0E",X"08",X"DD",X"7E", + X"04",X"FD",X"BE",X"00",X"D2",X"36",X"2B",X"DD",X"7E",X"03",X"FD",X"BE",X"01",X"D2",X"36",X"2B", + X"FD",X"BE",X"02",X"D2",X"3F",X"2B",X"FD",X"19",X"0D",X"C2",X"1E",X"2B",X"C3",X"6A",X"2B",X"21", + X"40",X"9A",X"7E",X"FE",X"00",X"CA",X"56",X"2B",X"DD",X"5E",X"10",X"16",X"00",X"CB",X"23",X"1D", + X"19",X"7E",X"A7",X"CA",X"5D",X"2B",X"CD",X"0B",X"30",X"A7",X"CA",X"6A",X"2B",X"DD",X"7E",X"15", + X"FE",X"03",X"D2",X"6A",X"2B",X"CD",X"2A",X"30",X"A7",X"C8",X"DD",X"66",X"0E",X"DD",X"6E",X"0D", + X"E5",X"FD",X"E1",X"11",X"04",X"00",X"DD",X"7E",X"0C",X"A7",X"CA",X"92",X"2B",X"FD",X"19",X"3D", + X"C2",X"7D",X"2B",X"FD",X"7E",X"00",X"FE",X"80",X"C2",X"92",X"2B",X"DD",X"36",X"0C",X"00",X"C3", + X"6A",X"2B",X"DD",X"7E",X"03",X"FD",X"86",X"01",X"57",X"DD",X"77",X"03",X"DD",X"7E",X"04",X"FD", + X"86",X"00",X"5F",X"DD",X"77",X"04",X"FD",X"66",X"02",X"DD",X"74",X"0F",X"FD",X"6E",X"03",X"DD", + X"7E",X"1F",X"CD",X"62",X"32",X"21",X"16",X"9C",X"CB",X"F6",X"DD",X"34",X"0C",X"FD",X"21",X"87", + X"47",X"11",X"03",X"00",X"DD",X"4E",X"10",X"0D",X"CA",X"D0",X"2B",X"FD",X"19",X"C3",X"C7",X"2B", + X"DD",X"7E",X"03",X"FD",X"BE",X"01",X"D0",X"FD",X"BE",X"02",X"D8",X"3A",X"40",X"9A",X"FE",X"00", + X"C2",X"16",X"2C",X"21",X"40",X"9A",X"DD",X"5E",X"10",X"16",X"00",X"CB",X"23",X"1D",X"19",X"7E", + X"A7",X"C2",X"16",X"2C",X"DD",X"7E",X"10",X"FE",X"06",X"CA",X"10",X"2C",X"DD",X"7E",X"0B",X"FE", + X"10",X"CA",X"0A",X"2C",X"21",X"E3",X"48",X"C3",X"56",X"2C",X"21",X"9A",X"48",X"C3",X"56",X"2C", + X"21",X"2C",X"49",X"C3",X"56",X"2C",X"DD",X"7E",X"10",X"FE",X"06",X"CA",X"53",X"2C",X"ED",X"5F", + X"47",X"3A",X"59",X"9A",X"80",X"DD",X"86",X"02",X"EA",X"3F",X"2C",X"DD",X"7E",X"0B",X"FE",X"10", + X"CA",X"39",X"2C",X"21",X"87",X"49",X"C3",X"56",X"2C",X"21",X"72",X"49",X"C3",X"56",X"2C",X"DD", + X"7E",X"0B",X"FE",X"10",X"CA",X"4D",X"2C",X"21",X"9C",X"49",X"C3",X"56",X"2C",X"21",X"AD",X"49", + X"C3",X"56",X"2C",X"21",X"5D",X"49",X"DD",X"74",X"0E",X"DD",X"75",X"0D",X"DD",X"36",X"0C",X"00", + X"DD",X"36",X"09",X"11",X"C9",X"DD",X"7E",X"09",X"FE",X"11",X"C0",X"DD",X"36",X"15",X"00",X"21", + X"40",X"9A",X"DD",X"5E",X"10",X"16",X"00",X"CB",X"23",X"19",X"7E",X"A7",X"CA",X"83",X"2C",X"DD", + X"36",X"0A",X"FF",X"DD",X"66",X"0E",X"DD",X"6E",X"0D",X"11",X"04",X"00",X"DD",X"7E",X"0C",X"A7", + X"CA",X"98",X"2C",X"19",X"3D",X"C2",X"93",X"2C",X"DD",X"7E",X"04",X"86",X"DD",X"77",X"04",X"5F", + X"23",X"DD",X"7E",X"03",X"86",X"DD",X"77",X"03",X"57",X"23",X"46",X"23",X"4E",X"DD",X"70",X"0F", + X"23",X"7E",X"FE",X"80",X"CA",X"C3",X"2C",X"C5",X"E1",X"DD",X"7E",X"1F",X"CD",X"62",X"32",X"DD", + X"34",X"0C",X"C9",X"CD",X"F6",X"2F",X"21",X"40",X"9A",X"7E",X"FE",X"00",X"C2",X"E5",X"2C",X"DD", + X"5E",X"10",X"16",X"00",X"CB",X"23",X"1D",X"19",X"7E",X"A7",X"C2",X"E5",X"2C",X"36",X"FF",X"DD", + X"56",X"10",X"CD",X"A6",X"36",X"DD",X"36",X"09",X"12",X"21",X"40",X"9A",X"DD",X"5E",X"10",X"16", + X"00",X"CB",X"23",X"19",X"36",X"FF",X"DD",X"36",X"06",X"10",X"C9",X"DD",X"7E",X"09",X"FE",X"12", + X"C0",X"DD",X"7E",X"0A",X"A7",X"C2",X"65",X"2D",X"DD",X"35",X"06",X"C0",X"DD",X"7E",X"07",X"A7", + X"C0",X"CD",X"0B",X"30",X"A7",X"CA",X"2C",X"2D",X"DD",X"7E",X"15",X"FE",X"03",X"D2",X"2C",X"2D", + X"CD",X"2A",X"30",X"A7",X"CA",X"2C",X"2D",X"DD",X"36",X"06",X"10",X"C9",X"DD",X"7E",X"0F",X"FE", + X"FF",X"CA",X"3A",X"2D",X"CD",X"F6",X"2F",X"C3",X"60",X"2D",X"DD",X"7E",X"10",X"21",X"A3",X"47", + X"11",X"04",X"00",X"19",X"3D",X"C2",X"43",X"2D",X"5E",X"DD",X"73",X"04",X"23",X"56",X"DD",X"72", + X"03",X"23",X"46",X"DD",X"70",X"0F",X"23",X"4E",X"C5",X"E1",X"DD",X"7E",X"1F",X"CD",X"62",X"32", + X"DD",X"36",X"06",X"10",X"C9",X"DD",X"36",X"15",X"00",X"DD",X"7E",X"10",X"FE",X"06",X"DA",X"8E", + X"2D",X"5F",X"FE",X"08",X"CA",X"00",X"2E",X"ED",X"5F",X"E6",X"7F",X"EA",X"8E",X"2D",X"21",X"40", + X"9A",X"16",X"00",X"CB",X"23",X"19",X"36",X"00",X"23",X"7E",X"A7",X"C2",X"00",X"2E",X"21",X"68", + X"4A",X"DD",X"7E",X"10",X"3D",X"CA",X"9D",X"2D",X"23",X"23",X"C3",X"94",X"2D",X"7E",X"DD",X"77", + X"04",X"23",X"7E",X"DD",X"77",X"03",X"DD",X"7E",X"10",X"FE",X"03",X"CA",X"C2",X"2D",X"FE",X"04", + X"CA",X"CC",X"2D",X"FE",X"05",X"CA",X"D6",X"2D",X"21",X"C7",X"47",X"DD",X"36",X"0B",X"20",X"C3", + X"DD",X"2D",X"21",X"09",X"48",X"DD",X"36",X"0B",X"10",X"C3",X"DD",X"2D",X"21",X"E8",X"47",X"DD", + X"36",X"0B",X"10",X"C3",X"DD",X"2D",X"21",X"E8",X"47",X"DD",X"36",X"0B",X"10",X"DD",X"74",X"0E", + X"DD",X"75",X"0D",X"DD",X"36",X"0C",X"00",X"DD",X"36",X"09",X"10",X"21",X"40",X"9A",X"16",X"00", + X"DD",X"5E",X"10",X"CB",X"23",X"19",X"36",X"00",X"DD",X"34",X"10",X"DD",X"36",X"0A",X"00",X"C9", + X"DD",X"7E",X"10",X"FE",X"08",X"CA",X"12",X"2E",X"21",X"BE",X"49",X"DD",X"36",X"0B",X"20",X"C3", + X"19",X"2E",X"21",X"E2",X"49",X"DD",X"36",X"0B",X"10",X"DD",X"74",X"0E",X"DD",X"75",X"0D",X"21", + X"68",X"4A",X"DD",X"7E",X"10",X"3D",X"CA",X"2E",X"2E",X"23",X"23",X"C3",X"25",X"2E",X"7E",X"DD", + X"77",X"04",X"23",X"7E",X"DD",X"77",X"03",X"DD",X"36",X"0C",X"00",X"DD",X"36",X"09",X"20",X"C9", + X"DD",X"7E",X"04",X"FE",X"E8",X"DA",X"7F",X"2F",X"DD",X"66",X"0E",X"DD",X"6E",X"0D",X"11",X"04", + X"00",X"DD",X"7E",X"0C",X"A7",X"CA",X"5D",X"2E",X"19",X"3D",X"C2",X"58",X"2E",X"DD",X"7E",X"04", + X"86",X"DD",X"77",X"04",X"5F",X"23",X"DD",X"7E",X"03",X"86",X"DD",X"77",X"03",X"57",X"23",X"46", + X"DD",X"70",X"0F",X"23",X"4E",X"C5",X"E1",X"DD",X"7E",X"1F",X"CD",X"62",X"32",X"21",X"16",X"9C", + X"CB",X"F6",X"DD",X"34",X"0C",X"DD",X"7E",X"0B",X"FE",X"10",X"CA",X"98",X"2E",X"3A",X"54",X"9A", + X"CB",X"47",X"C2",X"FA",X"2E",X"C3",X"A3",X"2E",X"3A",X"54",X"9A",X"CB",X"4F",X"C2",X"FA",X"2E", + X"C3",X"BB",X"2E",X"DD",X"7E",X"03",X"FD",X"21",X"20",X"9A",X"FD",X"BE",X"03",X"DA",X"31",X"2F", + X"D6",X"14",X"FD",X"BE",X"03",X"D2",X"31",X"2F",X"C3",X"D0",X"2E",X"DD",X"7E",X"03",X"FD",X"21", + X"20",X"9A",X"FD",X"BE",X"03",X"D2",X"31",X"2F",X"C6",X"14",X"FD",X"BE",X"03",X"DA",X"31",X"2F", + X"DD",X"36",X"01",X"0F",X"FD",X"36",X"06",X"FF",X"DD",X"7E",X"0B",X"FE",X"10",X"CA",X"E6",X"2E", + X"21",X"06",X"4A",X"C3",X"E9",X"2E",X"21",X"37",X"4A",X"DD",X"74",X"0E",X"DD",X"75",X"0D",X"DD", + X"36",X"0C",X"00",X"DD",X"7E",X"1F",X"FD",X"77",X"12",X"C9",X"DD",X"7E",X"0B",X"FE",X"10",X"CA", + X"0C",X"2F",X"DD",X"36",X"0B",X"10",X"21",X"E8",X"47",X"C3",X"13",X"2F",X"DD",X"36",X"0B",X"20", + X"21",X"C7",X"47",X"DD",X"74",X"0E",X"DD",X"75",X"0D",X"DD",X"7E",X"01",X"FE",X"0F",X"CA",X"28", + X"2F",X"DD",X"36",X"01",X"0F",X"C3",X"2C",X"2F",X"DD",X"36",X"01",X"03",X"DD",X"36",X"0C",X"00", + X"C9",X"DD",X"7E",X"03",X"FE",X"E6",X"D2",X"6A",X"2F",X"FE",X"1B",X"DA",X"6A",X"2F",X"DD",X"66", + X"0E",X"DD",X"6E",X"0D",X"11",X"04",X"00",X"DD",X"7E",X"0C",X"A7",X"C8",X"19",X"3D",X"C2",X"4C", + X"2F",X"19",X"7E",X"FE",X"80",X"C0",X"DD",X"7E",X"0B",X"FE",X"10",X"CA",X"64",X"2F",X"21",X"C7", + X"47",X"C3",X"74",X"2F",X"21",X"E8",X"47",X"C3",X"74",X"2F",X"3A",X"54",X"9A",X"A7",X"CA",X"FA", + X"2E",X"21",X"91",X"48",X"DD",X"74",X"0E",X"DD",X"75",X"0D",X"DD",X"36",X"0C",X"00",X"C9",X"DD", + X"66",X"0E",X"DD",X"6E",X"0D",X"E5",X"FD",X"E1",X"11",X"04",X"00",X"DD",X"7E",X"0C",X"A7",X"CA", + X"98",X"2F",X"FD",X"19",X"3D",X"C2",X"92",X"2F",X"DD",X"7E",X"03",X"FD",X"86",X"01",X"57",X"DD", + X"77",X"03",X"DD",X"7E",X"04",X"FD",X"86",X"00",X"5F",X"DD",X"77",X"04",X"FD",X"66",X"02",X"DD", + X"74",X"0F",X"FD",X"6E",X"03",X"DD",X"7E",X"1F",X"CD",X"62",X"32",X"21",X"16",X"9C",X"CB",X"F6", + X"DD",X"34",X"0C",X"DD",X"7E",X"04",X"FE",X"E8",X"D8",X"DD",X"7E",X"03",X"FD",X"21",X"20",X"9A", + X"FD",X"BE",X"03",X"DA",X"E0",X"2F",X"DD",X"36",X"0B",X"20",X"21",X"C7",X"47",X"C3",X"E7",X"2F", + X"DD",X"36",X"0B",X"10",X"21",X"E8",X"47",X"DD",X"74",X"0E",X"DD",X"75",X"0D",X"DD",X"36",X"0C", + X"00",X"DD",X"36",X"01",X"03",X"C9",X"16",X"08",X"1E",X"10",X"DD",X"73",X"04",X"26",X"FF",X"DD", + X"74",X"0F",X"2E",X"0F",X"DD",X"7E",X"1F",X"CD",X"62",X"32",X"C9",X"FD",X"21",X"20",X"9A",X"DD", + X"7E",X"03",X"C6",X"20",X"FD",X"BE",X"03",X"DA",X"28",X"30",X"DD",X"7E",X"03",X"D6",X"20",X"FD", + X"BE",X"03",X"D2",X"28",X"30",X"3E",X"FF",X"C9",X"AF",X"C9",X"FD",X"21",X"00",X"98",X"11",X"10", + X"00",X"FD",X"7E",X"00",X"A7",X"CA",X"4A",X"30",X"FD",X"19",X"FD",X"E5",X"E1",X"01",X"90",X"98", + X"ED",X"42",X"CA",X"48",X"30",X"C3",X"31",X"30",X"AF",X"C9",X"DD",X"34",X"15",X"FD",X"36",X"00", + X"FF",X"FD",X"36",X"05",X"00",X"FD",X"36",X"06",X"00",X"FD",X"36",X"07",X"04",X"FD",X"36",X"0A", + X"00",X"DD",X"36",X"07",X"FF",X"FD",X"E5",X"E1",X"DD",X"74",X"14",X"DD",X"75",X"13",X"DD",X"7E", + X"09",X"FE",X"12",X"CA",X"E8",X"30",X"DD",X"56",X"03",X"DD",X"5E",X"04",X"26",X"67",X"2E",X"12", + X"DD",X"7E",X"1F",X"CD",X"62",X"32",X"DD",X"7E",X"03",X"D6",X"04",X"FD",X"77",X"03",X"DD",X"7E", + X"04",X"D6",X"06",X"FD",X"77",X"04",X"21",X"40",X"9A",X"7E",X"FE",X"00",X"CA",X"C2",X"30",X"DD", + X"5E",X"10",X"16",X"00",X"CB",X"23",X"1D",X"19",X"7E",X"A7",X"C2",X"C2",X"30",X"DD",X"7E",X"10", + X"21",X"9F",X"47",X"3D",X"CA",X"BB",X"30",X"23",X"C3",X"B3",X"30",X"7E",X"FD",X"77",X"09",X"C3", + X"C6",X"30",X"FD",X"36",X"09",X"EB",X"DD",X"7E",X"10",X"FE",X"06",X"CA",X"DC",X"30",X"DD",X"7E", + X"0B",X"FE",X"10",X"C2",X"E2",X"30",X"21",X"31",X"47",X"C3",X"36",X"31",X"21",X"58",X"47",X"C3", + X"36",X"31",X"21",X"F3",X"46",X"C3",X"36",X"31",X"DD",X"7E",X"10",X"21",X"A3",X"47",X"11",X"04", + X"00",X"19",X"3D",X"C2",X"F1",X"30",X"7E",X"DD",X"77",X"04",X"5F",X"D6",X"08",X"FD",X"77",X"04", + X"23",X"56",X"DD",X"72",X"03",X"FD",X"72",X"03",X"FD",X"36",X"09",X"EB",X"2E",X"12",X"DD",X"7E", + X"10",X"3D",X"CB",X"4F",X"CA",X"28",X"31",X"26",X"2B",X"DD",X"74",X"0F",X"DD",X"7E",X"1F",X"CD", + X"62",X"32",X"21",X"58",X"47",X"C3",X"36",X"31",X"26",X"33",X"DD",X"74",X"0F",X"DD",X"7E",X"1F", + X"CD",X"62",X"32",X"21",X"1A",X"47",X"FD",X"74",X"0C",X"FD",X"75",X"0B",X"3E",X"FF",X"C9",X"3A", + X"59",X"9A",X"DD",X"86",X"02",X"DD",X"A6",X"01",X"C0",X"FD",X"35",X"06",X"C0",X"FD",X"36",X"00", + X"00",X"FD",X"36",X"05",X"00",X"FD",X"36",X"06",X"00",X"FD",X"36",X"07",X"00",X"FD",X"36",X"0A", + X"00",X"11",X"F0",X"08",X"21",X"FF",X"FF",X"FD",X"7E",X"0E",X"CD",X"0E",X"32",X"C9",X"3A",X"29", + X"9A",X"A7",X"C8",X"3A",X"3D",X"9A",X"A7",X"C0",X"FD",X"E5",X"FD",X"21",X"20",X"9A",X"21",X"F8", + X"45",X"FD",X"7E",X"11",X"96",X"FD",X"BE",X"0B",X"D2",X"B1",X"31",X"23",X"FD",X"7E",X"11",X"86", + X"FD",X"BE",X"0B",X"DA",X"B1",X"31",X"23",X"FD",X"7E",X"10",X"96",X"FD",X"BE",X"0A",X"D2",X"B1", + X"31",X"23",X"FD",X"7E",X"10",X"86",X"FD",X"BE",X"0A",X"DA",X"B1",X"31",X"3E",X"FF",X"FD",X"E1", + X"C9",X"AF",X"FD",X"E1",X"C9",X"DD",X"E5",X"FD",X"E5",X"DD",X"21",X"3C",X"4C",X"FD",X"21",X"0C", + X"4F",X"3A",X"5D",X"9A",X"47",X"3A",X"00",X"9C",X"90",X"FE",X"01",X"C2",X"D6",X"31",X"3E",X"00", + X"92",X"57",X"3E",X"00",X"93",X"5F",X"0E",X"04",X"DD",X"6E",X"04",X"DD",X"66",X"05",X"FD",X"7E", + X"00",X"CB",X"DF",X"77",X"DD",X"6E",X"00",X"DD",X"66",X"01",X"FD",X"7E",X"01",X"82",X"77",X"DD", + X"6E",X"02",X"DD",X"66",X"03",X"FD",X"7E",X"02",X"83",X"77",X"C5",X"01",X"04",X"00",X"DD",X"09", + X"DD",X"09",X"FD",X"09",X"C1",X"0D",X"C2",X"D8",X"31",X"FD",X"E1",X"DD",X"E1",X"C9",X"DD",X"E5", + X"FD",X"E5",X"DD",X"21",X"3C",X"4C",X"4F",X"06",X"00",X"CB",X"21",X"CB",X"10",X"CB",X"21",X"CB", + X"10",X"CB",X"21",X"CB",X"10",X"DD",X"09",X"3A",X"5D",X"9A",X"47",X"3A",X"00",X"9C",X"90",X"FE", + X"01",X"CA",X"37",X"32",X"C3",X"3F",X"32",X"3E",X"00",X"92",X"57",X"3E",X"00",X"93",X"5F",X"DD", + X"4E",X"00",X"DD",X"46",X"01",X"7A",X"D6",X"02",X"02",X"DD",X"4E",X"02",X"DD",X"46",X"03",X"7B", + X"D6",X"02",X"02",X"DD",X"4E",X"04",X"DD",X"46",X"05",X"CB",X"DC",X"7C",X"02",X"FD",X"E1",X"DD", + X"E1",X"C9",X"DD",X"E5",X"FD",X"E5",X"DD",X"21",X"FC",X"4B",X"4F",X"06",X"00",X"CB",X"21",X"CB", + X"10",X"CB",X"21",X"CB",X"10",X"CB",X"21",X"CB",X"10",X"DD",X"09",X"3A",X"5D",X"9A",X"47",X"3A", + X"00",X"9C",X"90",X"FE",X"01",X"CA",X"8B",X"32",X"C3",X"97",X"32",X"3E",X"00",X"92",X"57",X"3E", + X"00",X"93",X"5F",X"7C",X"EE",X"02",X"67",X"DD",X"4E",X"00",X"DD",X"46",X"01",X"7A",X"D6",X"08", + X"02",X"DD",X"4E",X"02",X"DD",X"46",X"03",X"7B",X"D6",X"08",X"02",X"DD",X"4E",X"04",X"DD",X"46", + X"05",X"7C",X"02",X"DD",X"4E",X"06",X"DD",X"46",X"07",X"7D",X"02",X"FD",X"E1",X"DD",X"E1",X"C9", + X"DD",X"E5",X"FD",X"E5",X"DD",X"2A",X"60",X"9A",X"7A",X"CB",X"3F",X"CB",X"3F",X"CB",X"3F",X"FE", + X"1C",X"D4",X"94",X"33",X"06",X"00",X"D6",X"02",X"DC",X"99",X"33",X"4F",X"FD",X"21",X"1B",X"84", + X"CB",X"21",X"CB",X"10",X"CB",X"21",X"CB",X"10",X"CB",X"21",X"CB",X"10",X"CB",X"21",X"CB",X"10", + X"CB",X"21",X"CB",X"10",X"FD",X"09",X"7B",X"CB",X"3F",X"CB",X"3F",X"CB",X"3F",X"D6",X"04",X"4F", + X"06",X"00",X"A7",X"FD",X"E5",X"E1",X"ED",X"42",X"E5",X"FD",X"E1",X"7A",X"E6",X"07",X"CB",X"3F", + X"4F",X"06",X"00",X"21",X"00",X"00",X"C5",X"E1",X"CB",X"21",X"CB",X"10",X"CB",X"21",X"CB",X"10", + X"CB",X"21",X"CB",X"10",X"CB",X"25",X"CB",X"14",X"09",X"E5",X"C1",X"DD",X"56",X"00",X"DD",X"5E", + X"01",X"DD",X"09",X"01",X"20",X"00",X"2E",X"05",X"FD",X"E5",X"DD",X"7E",X"02",X"FD",X"77",X"00", + X"FD",X"09",X"DD",X"23",X"2D",X"C2",X"3A",X"33",X"FD",X"E1",X"FD",X"E5",X"FD",X"2B",X"2E",X"05", + X"DD",X"7E",X"02",X"FD",X"77",X"00",X"FD",X"09",X"DD",X"23",X"2D",X"C2",X"50",X"33",X"3A",X"52", + X"9A",X"CB",X"47",X"CC",X"92",X"33",X"7A",X"FD",X"E1",X"01",X"00",X"08",X"FD",X"09",X"01",X"20", + X"00",X"FD",X"E5",X"2E",X"05",X"FD",X"77",X"00",X"FD",X"09",X"2D",X"C2",X"75",X"33",X"2E",X"05", + X"FD",X"E1",X"FD",X"2B",X"FD",X"77",X"00",X"FD",X"09",X"2D",X"C2",X"84",X"33",X"FD",X"E1",X"DD", + X"E1",X"C9",X"53",X"C9",X"3E",X"1C",X"16",X"E0",X"C9",X"3E",X"00",X"C9",X"21",X"1C",X"4F",X"22", + X"60",X"9A",X"CD",X"C0",X"32",X"C9",X"21",X"7A",X"4F",X"22",X"60",X"9A",X"CD",X"C0",X"32",X"C9", + X"21",X"A4",X"4F",X"22",X"60",X"9A",X"CD",X"C0",X"32",X"C9",X"53",X"C9",X"DD",X"E5",X"FD",X"E5", + X"DD",X"21",X"46",X"4F",X"7A",X"CB",X"3F",X"CB",X"3F",X"CB",X"3F",X"06",X"00",X"D6",X"02",X"DC", + X"99",X"33",X"4F",X"CB",X"21",X"CB",X"10",X"CB",X"21",X"CB",X"10",X"CB",X"21",X"CB",X"10",X"CB", + X"21",X"CB",X"10",X"CB",X"21",X"CB",X"10",X"FD",X"21",X"1B",X"84",X"FD",X"09",X"7B",X"CB",X"3F", + X"CB",X"3F",X"CB",X"3F",X"D6",X"04",X"06",X"00",X"4F",X"A7",X"FD",X"E5",X"E1",X"ED",X"42",X"E5", + X"FD",X"E1",X"7A",X"E6",X"07",X"CB",X"3F",X"4F",X"06",X"00",X"C5",X"E1",X"CB",X"21",X"CB",X"10", + X"CB",X"21",X"CB",X"10",X"CB",X"25",X"CB",X"14",X"09",X"E5",X"C1",X"DD",X"56",X"00",X"DD",X"5E", + X"01",X"DD",X"09",X"01",X"20",X"00",X"2E",X"03",X"FD",X"E5",X"DD",X"7E",X"02",X"FD",X"77",X"00", + X"FD",X"09",X"DD",X"23",X"2D",X"C2",X"2A",X"34",X"FD",X"E1",X"FD",X"E5",X"FD",X"2B",X"2E",X"03", + X"DD",X"7E",X"02",X"FD",X"77",X"00",X"FD",X"09",X"DD",X"23",X"2D",X"C2",X"40",X"34",X"3A",X"52", + X"9A",X"CB",X"47",X"CC",X"BA",X"33",X"7A",X"FD",X"E1",X"01",X"00",X"08",X"FD",X"09",X"01",X"20", + X"00",X"FD",X"E5",X"2E",X"03",X"FD",X"77",X"00",X"FD",X"09",X"2D",X"C2",X"65",X"34",X"FD",X"E1", + X"FD",X"2B",X"2E",X"03",X"FD",X"77",X"00",X"FD",X"09",X"2D",X"C2",X"74",X"34",X"FD",X"E1",X"DD", + X"E1",X"C9",X"DD",X"E5",X"FD",X"E5",X"DD",X"21",X"60",X"4F",X"7A",X"CB",X"3F",X"CB",X"3F",X"CB", + X"3F",X"06",X"00",X"D6",X"02",X"DC",X"99",X"33",X"4F",X"CB",X"21",X"CB",X"10",X"CB",X"21",X"CB", + X"10",X"CB",X"21",X"CB",X"10",X"CB",X"21",X"CB",X"10",X"CB",X"21",X"CB",X"10",X"FD",X"21",X"1B", + X"84",X"FD",X"09",X"7B",X"CB",X"3F",X"CB",X"3F",X"CB",X"3F",X"D6",X"04",X"06",X"00",X"4F",X"A7", + X"FD",X"E5",X"E1",X"ED",X"42",X"E5",X"FD",X"E1",X"7A",X"E6",X"07",X"CB",X"3F",X"4F",X"06",X"00", + X"C5",X"E1",X"CB",X"21",X"CB",X"10",X"CB",X"21",X"CB",X"10",X"CB",X"25",X"CB",X"14",X"09",X"E5", + X"C1",X"DD",X"56",X"00",X"DD",X"5E",X"01",X"DD",X"09",X"01",X"20",X"00",X"2E",X"03",X"FD",X"E5", + X"DD",X"7E",X"02",X"FD",X"77",X"00",X"FD",X"09",X"DD",X"23",X"2D",X"C2",X"F0",X"34",X"FD",X"E1", + X"FD",X"E5",X"FD",X"2B",X"2E",X"03",X"DD",X"7E",X"02",X"FD",X"77",X"00",X"FD",X"09",X"DD",X"23", + X"2D",X"C2",X"06",X"35",X"3A",X"52",X"9A",X"CB",X"47",X"CC",X"BA",X"33",X"7A",X"FD",X"E1",X"01", + X"00",X"08",X"FD",X"09",X"01",X"20",X"00",X"FD",X"E5",X"2E",X"03",X"FD",X"77",X"00",X"FD",X"09", + X"2D",X"C2",X"2B",X"35",X"FD",X"E1",X"FD",X"2B",X"2E",X"03",X"FD",X"77",X"00",X"FD",X"09",X"2D", + X"C2",X"3A",X"35",X"FD",X"E1",X"DD",X"E1",X"C9",X"DD",X"E5",X"FD",X"E5",X"15",X"5A",X"CB",X"23", + X"16",X"00",X"DD",X"21",X"FC",X"4E",X"DD",X"19",X"DD",X"5E",X"00",X"DD",X"56",X"01",X"3A",X"5E", + X"9A",X"4F",X"06",X"00",X"C5",X"E1",X"CB",X"21",X"CB",X"10",X"CB",X"21",X"CB",X"10",X"CB",X"21", + X"CB",X"10",X"CB",X"21",X"CB",X"10",X"CB",X"21",X"CB",X"10",X"CB",X"25",X"CB",X"14",X"CB",X"25", + X"CB",X"14",X"09",X"E5",X"C1",X"DD",X"21",X"BC",X"4C",X"DD",X"09",X"01",X"20",X"00",X"D5",X"FD", + X"E1",X"2E",X"04",X"DD",X"7E",X"00",X"FD",X"77",X"00",X"FD",X"09",X"DD",X"23",X"2D",X"C2",X"93", + X"35",X"D5",X"FD",X"E1",X"FD",X"2B",X"2E",X"04",X"DD",X"7E",X"00",X"FD",X"77",X"00",X"FD",X"09", + X"DD",X"23",X"2D",X"C2",X"A8",X"35",X"D5",X"FD",X"E1",X"FD",X"2B",X"FD",X"2B",X"2E",X"04",X"DD", + X"7E",X"00",X"FD",X"77",X"00",X"FD",X"09",X"DD",X"23",X"2D",X"C2",X"BF",X"35",X"D5",X"FD",X"E1", + X"FD",X"2B",X"FD",X"2B",X"FD",X"2B",X"3A",X"52",X"9A",X"CB",X"47",X"CC",X"4B",X"36",X"D5",X"FD", + X"E1",X"01",X"00",X"08",X"FD",X"09",X"01",X"20",X"00",X"2E",X"04",X"DD",X"7E",X"00",X"FD",X"77", + X"00",X"FD",X"09",X"DD",X"23",X"2D",X"C2",X"EB",X"35",X"D5",X"FD",X"E1",X"01",X"00",X"08",X"FD", + X"2B",X"FD",X"09",X"01",X"20",X"00",X"2E",X"04",X"DD",X"7E",X"00",X"FD",X"77",X"00",X"FD",X"09", + X"DD",X"23",X"2D",X"C2",X"08",X"36",X"D5",X"FD",X"E1",X"01",X"00",X"08",X"FD",X"2B",X"FD",X"2B", + X"FD",X"09",X"01",X"20",X"00",X"2E",X"04",X"DD",X"7E",X"00",X"FD",X"77",X"00",X"FD",X"09",X"DD", + X"23",X"2D",X"C2",X"27",X"36",X"D5",X"FD",X"E1",X"01",X"00",X"08",X"FD",X"2B",X"FD",X"2B",X"FD", + X"2B",X"FD",X"09",X"01",X"20",X"00",X"FD",X"E1",X"DD",X"E1",X"C9",X"01",X"0C",X"00",X"DD",X"09", + X"C9",X"3A",X"40",X"9A",X"FE",X"00",X"CA",X"76",X"36",X"FE",X"01",X"CA",X"8E",X"36",X"7A",X"FE", + X"04",X"DA",X"6D",X"36",X"3E",X"05",X"32",X"5E",X"9A",X"CD",X"48",X"35",X"C9",X"3E",X"04",X"32", + X"5E",X"9A",X"CD",X"48",X"35",X"C9",X"7A",X"FE",X"04",X"DA",X"85",X"36",X"3E",X"01",X"32",X"5E", + X"9A",X"CD",X"48",X"35",X"C9",X"3E",X"00",X"32",X"5E",X"9A",X"CD",X"48",X"35",X"C9",X"7A",X"FE", + X"04",X"DA",X"9D",X"36",X"3E",X"09",X"32",X"5E",X"9A",X"CD",X"48",X"35",X"C9",X"3E",X"08",X"32", + X"5E",X"9A",X"CD",X"48",X"35",X"C9",X"3A",X"40",X"9A",X"FE",X"00",X"CA",X"CB",X"36",X"FE",X"01", + X"CA",X"E3",X"36",X"7A",X"FE",X"04",X"DA",X"C2",X"36",X"3E",X"07",X"32",X"5E",X"9A",X"CD",X"48", + X"35",X"C9",X"3E",X"06",X"32",X"5E",X"9A",X"CD",X"48",X"35",X"C9",X"7A",X"FE",X"04",X"DA",X"DA", + X"36",X"3E",X"03",X"32",X"5E",X"9A",X"CD",X"48",X"35",X"C9",X"3E",X"02",X"32",X"5E",X"9A",X"CD", + X"48",X"35",X"C9",X"7A",X"FE",X"04",X"DA",X"F2",X"36",X"3E",X"0B",X"32",X"5E",X"9A",X"CD",X"48", + X"35",X"C9",X"3E",X"0A",X"32",X"5E",X"9A",X"CD",X"48",X"35",X"C9",X"7A",X"FE",X"04",X"DA",X"0A", + X"37",X"3E",X"0D",X"32",X"5E",X"9A",X"CD",X"48",X"35",X"C9",X"3E",X"0C",X"32",X"5E",X"9A",X"CD", + X"48",X"35",X"C9",X"7A",X"FE",X"04",X"DA",X"22",X"37",X"3E",X"0F",X"32",X"5E",X"9A",X"CD",X"48", + X"35",X"C9",X"3E",X"0E",X"32",X"5E",X"9A",X"CD",X"48",X"35",X"C9",X"CD",X"55",X"37",X"3A",X"6A", + X"9C",X"47",X"3A",X"6B",X"9C",X"B0",X"C0",X"3E",X"FF",X"32",X"6C",X"9C",X"AF",X"CD",X"B5",X"10", + X"C9",X"3A",X"76",X"9C",X"3C",X"32",X"76",X"9C",X"06",X"0F",X"0E",X"26",X"0D",X"C2",X"4C",X"37", + X"05",X"C2",X"4A",X"37",X"C9",X"CD",X"41",X"37",X"3A",X"FB",X"9B",X"A7",X"CA",X"5D",X"39",X"AF", + X"32",X"FB",X"9B",X"32",X"6A",X"9C",X"32",X"6B",X"9C",X"32",X"84",X"9C",X"32",X"80",X"9C",X"32", + X"7E",X"9C",X"21",X"70",X"00",X"22",X"82",X"9C",X"DD",X"21",X"01",X"9C",X"21",X"78",X"9C",X"11", + X"6A",X"9C",X"CD",X"9F",X"37",X"DD",X"21",X"07",X"9C",X"21",X"7A",X"9C",X"11",X"6B",X"9C",X"CD", + X"9F",X"37",X"3A",X"6A",X"9C",X"47",X"3A",X"6B",X"9C",X"B0",X"C8",X"CD",X"A5",X"3A",X"C9",X"FD", + X"21",X"64",X"3B",X"CD",X"16",X"39",X"A7",X"C8",X"FD",X"21",X"5A",X"9C",X"CD",X"16",X"39",X"A7", + X"C8",X"3E",X"FF",X"12",X"FD",X"21",X"4A",X"9C",X"CD",X"16",X"39",X"A7",X"CA",X"2F",X"38",X"FD", + X"21",X"3A",X"9C",X"CD",X"16",X"39",X"A7",X"CA",X"65",X"38",X"FD",X"21",X"2A",X"9C",X"CD",X"16", + X"39",X"A7",X"CA",X"9C",X"38",X"FD",X"21",X"1A",X"9C",X"CD",X"16",X"39",X"A7",X"CA",X"D9",X"38", + X"FD",X"22",X"7C",X"9C",X"ED",X"4B",X"7C",X"9C",X"71",X"23",X"70",X"21",X"5A",X"9C",X"11",X"0F", + X"00",X"19",X"EB",X"21",X"5A",X"9C",X"2B",X"01",X"3F",X"00",X"ED",X"B8",X"21",X"1A",X"9C",X"23", + X"54",X"5D",X"2B",X"3E",X"FF",X"77",X"01",X"0F",X"00",X"ED",X"B0",X"11",X"1A",X"9C",X"DD",X"22", + X"7C",X"9C",X"2A",X"7C",X"9C",X"01",X"06",X"00",X"ED",X"B0",X"2A",X"7C",X"9C",X"11",X"01",X"9C", + X"A7",X"ED",X"52",X"C8",X"2A",X"78",X"9C",X"11",X"10",X"00",X"19",X"22",X"78",X"9C",X"C9",X"01", + X"5A",X"9C",X"71",X"23",X"70",X"21",X"5A",X"9C",X"23",X"54",X"5D",X"2B",X"3E",X"FF",X"77",X"01", + X"0F",X"00",X"ED",X"B0",X"DD",X"22",X"7C",X"9C",X"2A",X"7C",X"9C",X"11",X"5A",X"9C",X"01",X"06", + X"00",X"ED",X"B0",X"3A",X"84",X"9C",X"A7",X"C2",X"60",X"38",X"3E",X"FF",X"32",X"84",X"9C",X"C9", + X"AF",X"32",X"6A",X"9C",X"C9",X"01",X"4A",X"9C",X"71",X"23",X"70",X"21",X"4A",X"9C",X"11",X"5A", + X"9C",X"01",X"0F",X"00",X"ED",X"B0",X"21",X"4A",X"9C",X"23",X"54",X"5D",X"2B",X"3E",X"FF",X"77", + X"01",X"0F",X"00",X"ED",X"B0",X"DD",X"22",X"7C",X"9C",X"2A",X"7C",X"9C",X"11",X"4A",X"9C",X"01", + X"06",X"00",X"ED",X"B0",X"DD",X"21",X"4A",X"9C",X"CD",X"40",X"3B",X"C9",X"01",X"3A",X"9C",X"71", + X"23",X"70",X"21",X"5A",X"9C",X"11",X"0F",X"00",X"19",X"EB",X"21",X"5A",X"9C",X"2B",X"01",X"1F", + X"00",X"ED",X"B8",X"21",X"3A",X"9C",X"23",X"54",X"5D",X"2B",X"01",X"0F",X"00",X"3E",X"FF",X"77", + X"ED",X"B0",X"DD",X"22",X"7C",X"9C",X"2A",X"7C",X"9C",X"11",X"3A",X"9C",X"01",X"06",X"00",X"ED", + X"B0",X"DD",X"21",X"3A",X"9C",X"CD",X"40",X"3B",X"C9",X"01",X"2A",X"9C",X"71",X"23",X"70",X"21", + X"5A",X"9C",X"11",X"0F",X"00",X"19",X"EB",X"21",X"5A",X"9C",X"2B",X"01",X"2F",X"00",X"ED",X"B8", + X"21",X"2A",X"9C",X"23",X"54",X"5D",X"2B",X"3E",X"FF",X"77",X"01",X"0F",X"00",X"ED",X"B0",X"DD", + X"22",X"7C",X"9C",X"2A",X"7C",X"9C",X"11",X"2A",X"9C",X"01",X"06",X"00",X"ED",X"B0",X"DD",X"21", + X"2A",X"9C",X"CD",X"40",X"3B",X"C9",X"DD",X"7E",X"00",X"FD",X"46",X"00",X"B8",X"DA",X"57",X"39", + X"C2",X"5A",X"39",X"DD",X"7E",X"01",X"FD",X"46",X"01",X"B8",X"DA",X"57",X"39",X"C2",X"5A",X"39", + X"DD",X"7E",X"02",X"FD",X"46",X"02",X"B8",X"DA",X"57",X"39",X"C2",X"5A",X"39",X"DD",X"7E",X"03", + X"FD",X"46",X"03",X"B8",X"DA",X"57",X"39",X"C2",X"5A",X"39",X"DD",X"7E",X"04",X"FD",X"46",X"04", + X"B8",X"DA",X"57",X"39",X"C2",X"5A",X"39",X"3E",X"00",X"C9",X"3E",X"FF",X"C9",X"DD",X"21",X"78", + X"9C",X"CD",X"8D",X"0B",X"FD",X"21",X"6A",X"9C",X"3A",X"6A",X"9C",X"A7",X"C2",X"87",X"39",X"DD", + X"21",X"7A",X"9C",X"3E",X"FF",X"32",X"5D",X"9A",X"CD",X"8D",X"0B",X"FD",X"21",X"6B",X"9C",X"3A", + X"6B",X"9C",X"A7",X"C2",X"87",X"39",X"C9",X"3A",X"76",X"9C",X"E6",X"3F",X"C0",X"2A",X"82",X"9C", + X"2B",X"22",X"82",X"9C",X"7D",X"44",X"B0",X"CA",X"29",X"3A",X"3A",X"54",X"9A",X"57",X"FE",X"01", + X"CC",X"03",X"3A",X"7A",X"FE",X"02",X"CC",X"16",X"3A",X"CD",X"64",X"3A",X"3A",X"56",X"9A",X"A7", + X"CA",X"FE",X"39",X"3A",X"93",X"9C",X"A7",X"C0",X"3E",X"FF",X"32",X"93",X"9C",X"3A",X"7E",X"9C", + X"FE",X"1C",X"CA",X"29",X"3A",X"3A",X"7E",X"9C",X"FE",X"1B",X"CA",X"3D",X"3A",X"3A",X"80",X"9C", + X"FE",X"03",X"C8",X"D0",X"6F",X"26",X"00",X"DD",X"4E",X"00",X"DD",X"46",X"01",X"09",X"22",X"7C", + X"9C",X"DD",X"2A",X"7C",X"9C",X"3A",X"7E",X"9C",X"4F",X"06",X"00",X"21",X"6A",X"3B",X"09",X"7E", + X"DD",X"77",X"06",X"3A",X"80",X"9C",X"3C",X"32",X"80",X"9C",X"CD",X"A5",X"3A",X"C9",X"AF",X"32", + X"93",X"9C",X"C9",X"3A",X"7E",X"9C",X"FE",X"1C",X"CA",X"10",X"3A",X"3C",X"32",X"7E",X"9C",X"C9", + X"3E",X"00",X"32",X"7E",X"9C",X"C9",X"3A",X"7E",X"9C",X"FE",X"00",X"CA",X"23",X"3A",X"3D",X"32", + X"7E",X"9C",X"C9",X"3E",X"1C",X"32",X"7E",X"9C",X"C9",X"AF",X"FD",X"77",X"00",X"32",X"7E",X"9C", + X"32",X"80",X"9C",X"21",X"70",X"00",X"22",X"82",X"9C",X"CD",X"A5",X"3A",X"C9",X"3A",X"80",X"9C", + X"FE",X"00",X"CA",X"FA",X"39",X"4F",X"06",X"00",X"3D",X"32",X"80",X"9C",X"DD",X"6E",X"00",X"DD", + X"66",X"01",X"09",X"22",X"7C",X"9C",X"DD",X"2A",X"7C",X"9C",X"DD",X"2B",X"3E",X"FF",X"DD",X"77", + X"06",X"C3",X"FA",X"39",X"21",X"6A",X"3B",X"06",X"00",X"3A",X"7E",X"9C",X"FE",X"1B",X"CA",X"85", + X"3A",X"FE",X"1C",X"CA",X"95",X"3A",X"4F",X"09",X"7E",X"32",X"F8",X"85",X"3E",X"FF",X"32",X"18", + X"86",X"32",X"D8",X"85",X"C9",X"3E",X"1B",X"32",X"D8",X"85",X"3E",X"1E",X"32",X"F8",X"85",X"3E", + X"0B",X"32",X"18",X"86",X"C9",X"3E",X"0E",X"32",X"D8",X"85",X"3E",X"17",X"32",X"F8",X"85",X"3E", + X"0D",X"32",X"18",X"86",X"C9",X"00",X"CD",X"B5",X"10",X"3E",X"01",X"32",X"D5",X"84",X"3E",X"02", + X"32",X"D3",X"84",X"3E",X"03",X"32",X"D1",X"84",X"3E",X"04",X"32",X"CF",X"84",X"3E",X"05",X"32", + X"CD",X"84",X"DD",X"21",X"1A",X"9C",X"21",X"15",X"85",X"CD",X"F5",X"3A",X"DD",X"21",X"2A",X"9C", + X"21",X"13",X"85",X"CD",X"F5",X"3A",X"DD",X"21",X"3A",X"9C",X"21",X"11",X"85",X"CD",X"F5",X"3A", + X"DD",X"21",X"4A",X"9C",X"21",X"0F",X"85",X"CD",X"F5",X"3A",X"DD",X"21",X"5A",X"9C",X"21",X"0D", + X"85",X"CD",X"F5",X"3A",X"C9",X"E5",X"06",X"06",X"11",X"20",X"00",X"DD",X"7E",X"00",X"77",X"DD", + X"23",X"19",X"05",X"C2",X"FB",X"3A",X"06",X"06",X"11",X"00",X"08",X"19",X"11",X"E0",X"FF",X"19", + X"3E",X"00",X"77",X"19",X"05",X"C2",X"12",X"3B",X"E1",X"11",X"20",X"01",X"19",X"06",X"0A",X"11", + X"20",X"00",X"DD",X"7E",X"00",X"77",X"DD",X"23",X"19",X"05",X"C2",X"22",X"3B",X"06",X"0A",X"11", + X"00",X"08",X"19",X"11",X"E0",X"FF",X"19",X"3E",X"01",X"77",X"19",X"05",X"C2",X"39",X"3B",X"C9", + X"2A",X"7C",X"9C",X"11",X"01",X"9C",X"A7",X"ED",X"52",X"C8",X"2A",X"78",X"9C",X"DD",X"22",X"7C", + X"9C",X"ED",X"5B",X"7C",X"9C",X"A7",X"ED",X"52",X"D8",X"2A",X"78",X"9C",X"11",X"10",X"00",X"19", + X"22",X"78",X"9C",X"C9",X"00",X"00",X"03",X"00",X"00",X"00",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F", + X"10",X"11",X"12",X"13",X"14",X"15",X"16",X"17",X"18",X"19",X"1A",X"1B",X"1C",X"1D",X"1E",X"1F", + X"20",X"21",X"22",X"23",X"4D",X"4D",X"FF",X"FF",X"FF",X"FF",X"11",X"02",X"13",X"85",X"19",X"1E", + X"1C",X"11",X"FF",X"1C",X"1D",X"0A",X"1B",X"1D",X"FF",X"0B",X"1E",X"1D",X"1D",X"18",X"17",X"0D", + X"02",X"50",X"85",X"01",X"FF",X"19",X"15",X"0A",X"22",X"0E",X"1B",X"FF",X"18",X"17",X"15",X"22", + X"0E",X"02",X"50",X"85",X"01",X"FF",X"18",X"1B",X"FF",X"02",X"FF",X"19",X"15",X"0A",X"22",X"0E", + X"1B",X"1C",X"10",X"01",X"51",X"85",X"19",X"15",X"0E",X"0A",X"1C",X"0E",X"FF",X"16",X"18",X"1B", + X"0E",X"FF",X"0C",X"18",X"12",X"17",X"13",X"01",X"4C",X"85",X"0C",X"18",X"12",X"17",X"FF",X"0A", + X"FF",X"FF",X"01",X"0C",X"18",X"12",X"17",X"FF",X"01",X"19",X"15",X"0A",X"22",X"13",X"01",X"4C", + X"85",X"0C",X"18",X"12",X"17",X"FF",X"0A",X"FF",X"02",X"0C",X"18",X"12",X"17",X"1C",X"FF",X"01", + X"19",X"15",X"0A",X"22",X"13",X"01",X"4C",X"85",X"0C",X"18",X"12",X"17",X"FF",X"0A",X"FF",X"03", + X"0C",X"18",X"12",X"17",X"1C",X"FF",X"01",X"19",X"15",X"0A",X"22",X"13",X"01",X"4C",X"85",X"0C", + X"18",X"12",X"17",X"FF",X"0A",X"FF",X"04",X"0C",X"18",X"12",X"17",X"1C",X"FF",X"01",X"19",X"15", + X"0A",X"22",X"13",X"01",X"4C",X"85",X"0C",X"18",X"12",X"17",X"FF",X"0A",X"FF",X"FF",X"01",X"0C", + X"18",X"12",X"17",X"FF",X"02",X"19",X"15",X"0A",X"22",X"13",X"01",X"4C",X"85",X"0C",X"18",X"12", + X"17",X"FF",X"0A",X"FF",X"FF",X"01",X"0C",X"18",X"12",X"17",X"FF",X"03",X"19",X"15",X"0A",X"22", + X"13",X"01",X"4C",X"85",X"0C",X"18",X"12",X"17",X"FF",X"0A",X"FF",X"02",X"0C",X"18",X"12",X"17", + X"1C",X"FF",X"03",X"19",X"15",X"0A",X"22",X"D6",X"3B",X"ED",X"3B",X"04",X"3C",X"1B",X"3C",X"32", + X"3C",X"49",X"3C",X"60",X"3C",X"13",X"01",X"4D",X"85",X"0C",X"18",X"12",X"17",X"FF",X"0B",X"FF", + X"FF",X"01",X"0C",X"18",X"12",X"17",X"FF",X"01",X"19",X"15",X"0A",X"22",X"13",X"01",X"4D",X"85", + X"0C",X"18",X"12",X"17",X"FF",X"0B",X"FF",X"02",X"0C",X"18",X"12",X"17",X"1C",X"FF",X"01",X"19", + X"15",X"0A",X"22",X"13",X"01",X"4D",X"85",X"0C",X"18",X"12",X"17",X"FF",X"0B",X"FF",X"03",X"0C", + X"18",X"12",X"17",X"1C",X"FF",X"01",X"19",X"15",X"0A",X"22",X"13",X"01",X"4D",X"85",X"0C",X"18", + X"12",X"17",X"FF",X"0B",X"FF",X"04",X"0C",X"18",X"12",X"17",X"1C",X"FF",X"01",X"19",X"15",X"0A", + X"22",X"13",X"01",X"4D",X"85",X"0C",X"18",X"12",X"17",X"FF",X"0B",X"FF",X"FF",X"01",X"0C",X"18", + X"12",X"17",X"FF",X"02",X"19",X"15",X"0A",X"22",X"13",X"01",X"4D",X"85",X"0C",X"18",X"12",X"17", + X"FF",X"0B",X"FF",X"FF",X"01",X"0C",X"18",X"12",X"17",X"FF",X"03",X"19",X"15",X"0A",X"22",X"13", + X"01",X"4D",X"85",X"0C",X"18",X"12",X"17",X"FF",X"0B",X"FF",X"02",X"0C",X"18",X"12",X"17",X"1C", + X"FF",X"03",X"19",X"15",X"0A",X"22",X"85",X"3C",X"9C",X"3C",X"B3",X"3C",X"CA",X"3C",X"E1",X"3C", + X"F8",X"3C",X"0F",X"3D",X"09",X"01",X"50",X"85",X"10",X"0A",X"16",X"0E",X"FF",X"18",X"1F",X"0E", + X"1B",X"0A",X"0A",X"0A",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"0C",X"1B",X"0E",X"0D",X"12", + X"1D",X"FF",X"00",X"0B",X"01",X"B5",X"85",X"12",X"17",X"1C",X"0E",X"1B",X"1D",X"FF",X"0C",X"18", + X"12",X"17",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"00",X"34",X"85",X"FF",X"01", + X"1E",X"19",X"FF",X"10",X"0A",X"16",X"0E",X"FF",X"18",X"1F",X"0E",X"1B",X"FF",X"FF",X"10",X"00", + X"34",X"85",X"FF",X"02",X"1E",X"19",X"FF",X"10",X"0A",X"16",X"0E",X"FF",X"18",X"1F",X"0E",X"1B", + X"FF",X"FF",X"09",X"00",X"74",X"85",X"10",X"0A",X"16",X"0E",X"FF",X"18",X"1F",X"0E",X"1B",X"05", + X"00",X"B4",X"85",X"1C",X"1D",X"0A",X"1B",X"1D",X"10",X"00",X"4E",X"85",X"24",X"FF",X"01",X"09", + X"08",X"03",X"FF",X"0F",X"0A",X"15",X"0C",X"18",X"17",X"FF",X"FF",X"FF",X"00",X"00",X"07",X"05", + X"00",X"00",X"0F",X"0A",X"15",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"06",X"08", + X"00",X"00",X"0E",X"15",X"1C",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"05",X"05", + X"00",X"00",X"14",X"FF",X"22",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"03",X"09", + X"00",X"00",X"1D",X"14",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"03",X"08", + X"00",X"00",X"1D",X"1C",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"0E",X"00",X"C9",X"96", + X"0D",X"18",X"FF",X"17",X"18",X"1D",X"FF",X"1B",X"0E",X"20",X"1B",X"12",X"1D",X"0E",X"FF",X"FF", + X"0B",X"00",X"6B",X"96",X"16",X"0E",X"16",X"18",X"1B",X"22",X"FF",X"0D",X"0A",X"1D",X"0A",X"FF", + X"FF",X"FF",X"FF",X"FF",X"03",X"00",X"30",X"96",X"0E",X"15",X"1C",X"0F",X"00",X"07",X"0F",X"01", + X"08",X"0F",X"02",X"09",X"0F",X"03",X"0A",X"0F",X"04",X"0B",X"0F",X"05",X"0C",X"0F",X"06",X"0D", + X"0F",X"07",X"0E",X"0F",X"08",X"0F",X"0F",X"09",X"01",X"0F",X"0A",X"02",X"0F",X"1A",X"00",X"0F", + X"1B",X"00",X"0F",X"1E",X"00",X"03",X"1D",X"00",X"0F",X"0B",X"00",X"0F",X"0C",X"00",X"0F",X"0D", + X"00",X"0F",X"0E",X"00",X"0F",X"0F",X"00",X"0F",X"10",X"03",X"0F",X"11",X"04",X"0F",X"12",X"05", + X"0F",X"13",X"06",X"0F",X"14",X"07",X"0F",X"15",X"03",X"0F",X"16",X"04",X"0F",X"17",X"05",X"0F", + X"18",X"06",X"0F",X"19",X"07",X"3D",X"3D",X"3D",X"3D",X"3D",X"3D",X"3D",X"3D",X"42",X"7A",X"7A", + X"7A",X"7A",X"7A",X"7A",X"3A",X"43",X"7A",X"3A",X"37",X"41",X"3C",X"43",X"39",X"41",X"39",X"40", + X"3F",X"3F",X"3E",X"3D",X"3D",X"38",X"3C",X"7A",X"7A",X"7A",X"7A",X"7A",X"7A",X"3B",X"37",X"7A", + X"7A",X"7A",X"7A",X"3C",X"7A",X"7A",X"7A",X"3B",X"3A",X"37",X"39",X"4F",X"84",X"6F",X"84",X"8F", + X"84",X"AF",X"84",X"CF",X"84",X"EF",X"84",X"0F",X"85",X"2F",X"85",X"4F",X"85",X"50",X"84",X"70", + X"84",X"90",X"84",X"B0",X"84",X"D0",X"84",X"F0",X"84",X"10",X"85",X"30",X"85",X"51",X"84",X"71", + X"84",X"91",X"84",X"B1",X"84",X"D1",X"84",X"F1",X"84",X"11",X"85",X"52",X"84",X"72",X"84",X"EF", + X"86",X"0F",X"87",X"2F",X"87",X"4F",X"87",X"6F",X"87",X"8F",X"87",X"AF",X"87",X"F0",X"86",X"10", + X"87",X"30",X"87",X"50",X"87",X"70",X"87",X"90",X"87",X"B0",X"87",X"11",X"87",X"31",X"87",X"51", + X"87",X"71",X"87",X"91",X"87",X"B1",X"87",X"52",X"87",X"72",X"87",X"92",X"87",X"B2",X"87",X"73", + X"87",X"93",X"87",X"B3",X"87",X"94",X"87",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"30", + X"40",X"20",X"40",X"20",X"30",X"40",X"20",X"30",X"40",X"20",X"40",X"20",X"30",X"20",X"30",X"FE", + X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE",X"10",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE", + X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE", + X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE", + X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE", + X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE", + X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE", + X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE", + X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE", + X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE", + X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE", + X"00",X"93",X"10",X"80",X"62",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B", + X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B", + X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B", + X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B", + X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B", + X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B", + X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B", + X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B", + X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B", + X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B", + X"10",X"80",X"73",X"98",X"4B",X"78",X"4A",X"DC",X"4A",X"AA",X"4A",X"CA",X"4B",X"3A",X"4B",X"05", + X"40",X"5F",X"3F",X"10",X"58",X"12",X"58",X"14",X"58",X"16",X"58",X"18",X"58",X"1A",X"58",X"1C", + X"58",X"1E",X"58",X"20",X"58",X"22",X"58",X"24",X"58",X"26",X"58",X"28",X"58",X"2A",X"58",X"2C", + X"58",X"2E",X"58",X"30",X"58",X"32",X"58",X"34",X"58",X"36",X"58",X"38",X"58",X"3A",X"58",X"3C", + X"58",X"3E",X"58",X"40",X"58",X"42",X"58",X"44",X"58",X"46",X"58",X"48",X"58",X"4A",X"58",X"4C", + X"58",X"4E",X"58",X"50",X"58",X"52",X"58",X"54",X"58",X"56",X"58",X"58",X"58",X"5A",X"58",X"5C", + X"58",X"5E",X"58",X"60",X"58",X"62",X"58",X"64",X"58",X"66",X"58",X"68",X"58",X"6A",X"58",X"6C", + X"58",X"6E",X"58",X"70",X"58",X"72",X"58",X"74",X"58",X"76",X"58",X"78",X"58",X"7A",X"58",X"7C", + X"58",X"7E",X"58",X"80",X"58",X"82",X"58",X"84",X"58",X"86",X"58",X"88",X"58",X"8A",X"58",X"8C", + X"58",X"8E",X"58",X"90",X"58",X"92",X"58",X"94",X"58",X"96",X"58",X"98",X"58",X"9A",X"58",X"9C", + X"58",X"9E",X"58",X"A0",X"58",X"A2",X"58",X"A4",X"58",X"A6",X"58",X"A8",X"58",X"AA",X"58",X"AC", + X"58",X"AE",X"58",X"B0",X"58",X"B2",X"58",X"B4",X"58",X"B6",X"58",X"B8",X"58",X"BA",X"58",X"BC", + X"58",X"BE",X"58",X"C0",X"58",X"C2",X"58",X"C4",X"58",X"C6",X"58",X"C8",X"58",X"CA",X"58",X"CC", + X"58",X"CE",X"58",X"D0",X"58",X"D2",X"58",X"D4",X"58",X"D6",X"58",X"D8",X"58",X"DA",X"58",X"DC", + X"58",X"DE",X"58",X"E0",X"58",X"E2",X"58",X"E4",X"58",X"E6",X"58",X"E8",X"58",X"EA",X"58",X"EC", + X"58",X"EE",X"58",X"F0",X"58",X"FF",X"FF",X"F5",X"84",X"F4",X"84",X"F3",X"84",X"F5",X"84",X"F4", + X"84",X"F3",X"84",X"15",X"85",X"14",X"85",X"13",X"85",X"35",X"85",X"34",X"85",X"33",X"85",X"1F", + X"20",X"21",X"1F",X"20",X"21",X"1C",X"1D",X"1E",X"19",X"1A",X"1B",X"4B",X"4B",X"4B",X"4B",X"4B", + X"4B",X"4B",X"4B",X"4B",X"4B",X"4B",X"4B",X"55",X"85",X"54",X"85",X"53",X"85",X"55",X"85",X"54", + X"85",X"53",X"85",X"55",X"85",X"54",X"85",X"53",X"85",X"75",X"85",X"74",X"85",X"73",X"85",X"16", + X"17",X"18",X"16",X"17",X"18",X"16",X"17",X"18",X"13",X"14",X"15",X"4B",X"4B",X"4B",X"4B",X"4B", + X"4B",X"4B",X"4B",X"4B",X"4B",X"4B",X"4B",X"95",X"85",X"94",X"85",X"93",X"85",X"95",X"85",X"94", + X"85",X"93",X"85",X"B5",X"85",X"B4",X"85",X"B3",X"85",X"D5",X"85",X"D4",X"85",X"D3",X"85",X"10", + X"11",X"12",X"10",X"11",X"12",X"0D",X"0E",X"0F",X"0A",X"0B",X"0C",X"4B",X"4B",X"4B",X"4B",X"4B", + X"4B",X"4B",X"4B",X"4B",X"4B",X"4B",X"4B",X"F5",X"85",X"F4",X"85",X"F3",X"85",X"F5",X"85",X"F4", + X"85",X"F3",X"85",X"F5",X"85",X"F4",X"85",X"F3",X"85",X"15",X"86",X"14",X"86",X"13",X"86",X"07", + X"08",X"09",X"07",X"08",X"09",X"07",X"08",X"09",X"04",X"05",X"06",X"4B",X"4B",X"4B",X"4B",X"4B", + X"4B",X"4B",X"4B",X"4B",X"4B",X"4B",X"4B",X"75",X"86",X"74",X"86",X"73",X"86",X"75",X"86",X"74", + X"86",X"73",X"86",X"95",X"86",X"94",X"86",X"93",X"86",X"B5",X"86",X"B4",X"86",X"B3",X"86",X"FA", + X"FB",X"FC",X"FA",X"FB",X"FC",X"F7",X"F8",X"F9",X"F4",X"F5",X"F6",X"0B",X"0B",X"0B",X"0B",X"0B", + X"0B",X"0B",X"0B",X"0B",X"0B",X"0B",X"0B",X"D5",X"86",X"D4",X"86",X"D3",X"86",X"F5",X"86",X"F4", + X"86",X"F3",X"86",X"15",X"87",X"14",X"87",X"13",X"87",X"35",X"87",X"34",X"87",X"33",X"87",X"F1", + X"F2",X"F3",X"EE",X"EF",X"F0",X"EB",X"EC",X"ED",X"E8",X"E9",X"EA",X"0B",X"0B",X"0B",X"0B",X"0B", + X"0B",X"0B",X"0B",X"0B",X"0B",X"0B",X"0B",X"35",X"86",X"34",X"86",X"33",X"86",X"35",X"86",X"34", + X"86",X"33",X"86",X"35",X"86",X"34",X"86",X"33",X"86",X"55",X"86",X"54",X"86",X"53",X"86",X"01", + X"02",X"03",X"01",X"02",X"03",X"01",X"02",X"03",X"FD",X"FE",X"00",X"4B",X"4B",X"4B",X"4B",X"4B", + X"4B",X"4B",X"4B",X"4B",X"0B",X"0B",X"4B",X"08",X"00",X"00",X"0A",X"00",X"01",X"0C",X"00",X"02", + X"0E",X"00",X"03",X"10",X"00",X"04",X"12",X"00",X"05",X"14",X"00",X"06",X"97",X"41",X"C7",X"41", + X"F7",X"41",X"27",X"42",X"B7",X"42",X"57",X"42",X"87",X"42",X"24",X"FF",X"01",X"09",X"08",X"03", + X"FF",X"2A",X"29",X"28",X"27",X"26",X"25",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02", + X"02",X"02",X"02",X"02",X"10",X"30",X"12",X"30",X"14",X"30",X"16",X"30",X"18",X"30",X"1A",X"30", + X"1C",X"30",X"1E",X"30",X"20",X"30",X"22",X"30",X"24",X"30",X"26",X"30",X"28",X"30",X"2A",X"30", + X"2C",X"30",X"2E",X"30",X"30",X"30",X"32",X"30",X"34",X"30",X"36",X"30",X"38",X"30",X"3A",X"30", + X"3C",X"30",X"3E",X"30",X"40",X"30",X"42",X"30",X"44",X"30",X"46",X"30",X"48",X"30",X"4A",X"30", + X"4C",X"30",X"4E",X"30",X"50",X"30",X"52",X"30",X"54",X"30",X"56",X"30",X"58",X"30",X"5A",X"30", + X"5C",X"30",X"5E",X"30",X"60",X"30",X"62",X"30",X"64",X"30",X"66",X"30",X"68",X"30",X"6A",X"30", + X"6C",X"30",X"6E",X"30",X"70",X"30",X"72",X"30",X"74",X"30",X"76",X"30",X"78",X"30",X"7A",X"30", + X"7C",X"30",X"7E",X"30",X"80",X"30",X"82",X"30",X"84",X"30",X"86",X"30",X"88",X"30",X"8A",X"30", + X"8C",X"30",X"8E",X"30",X"90",X"30",X"92",X"30",X"94",X"30",X"96",X"30",X"98",X"30",X"9A",X"30", + X"9C",X"30",X"9E",X"30",X"A0",X"30",X"A2",X"30",X"A4",X"30",X"A6",X"30",X"A8",X"30",X"AA",X"30", + X"AC",X"30",X"AE",X"30",X"B0",X"30",X"B2",X"30",X"B4",X"30",X"B6",X"30",X"B8",X"30",X"BA",X"30", + X"BC",X"30",X"BE",X"30",X"C0",X"30",X"C2",X"30",X"C4",X"30",X"C6",X"30",X"C8",X"30",X"CA",X"30", + X"CC",X"30",X"CE",X"30",X"D0",X"30",X"D2",X"30",X"D4",X"30",X"D6",X"30",X"D8",X"30",X"DA",X"30", + X"DC",X"30",X"DE",X"30",X"E0",X"30",X"E2",X"30",X"E4",X"30",X"E6",X"30",X"E8",X"30",X"EA",X"30", + X"EC",X"30",X"EE",X"30",X"F0",X"30",X"F8",X"30",X"FF",X"FF",X"FF",X"FF",X"01",X"01",X"34",X"31", + X"2E",X"2B",X"7F",X"35",X"32",X"2F",X"2C",X"7F",X"34",X"31",X"2E",X"2B",X"7F",X"35",X"32",X"2F", + X"2C",X"7F",X"34",X"31",X"2E",X"2B",X"7F",X"35",X"32",X"2F",X"2C",X"7F",X"34",X"31",X"2E",X"2B", + X"7F",X"35",X"32",X"2F",X"2C",X"7F",X"01",X"01",X"36",X"33",X"30",X"2D",X"7F",X"7F",X"7F",X"7F", + X"7F",X"7F",X"36",X"33",X"30",X"2D",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"36",X"33",X"30",X"2D", + X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"36",X"33",X"30",X"2D",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F", + X"A0",X"E0",X"A0",X"D8",X"A0",X"D0",X"A0",X"C8",X"A0",X"C0",X"A0",X"B8",X"A0",X"B0",X"A0",X"A8", + X"A0",X"A0",X"A0",X"98",X"A0",X"90",X"A0",X"88",X"A0",X"80",X"A0",X"80",X"A0",X"80",X"A0",X"80", + X"A0",X"80",X"A0",X"80",X"A0",X"80",X"A0",X"80",X"A0",X"80",X"A0",X"80",X"A0",X"80",X"A0",X"80", + X"A0",X"80",X"A0",X"80",X"A0",X"80",X"A0",X"80",X"A0",X"80",X"A0",X"80",X"A0",X"80",X"A0",X"80", + X"A0",X"80",X"A0",X"80",X"A0",X"80",X"A0",X"80",X"A0",X"80",X"A0",X"80",X"A0",X"80",X"A0",X"80", + X"05",X"00",X"91",X"85",X"0B",X"18",X"17",X"1E",X"1C",X"06",X"00",X"6B",X"85",X"05",X"00",X"00", + X"FF",X"4C",X"FF",X"00",X"00",X"00",X"05",X"00",X"10",X"00",X"15",X"00",X"20",X"00",X"25",X"00", + X"30",X"00",X"35",X"00",X"40",X"00",X"45",X"00",X"50",X"10",X"10",X"20",X"01",X"02",X"02",X"02", + X"00",X"10",X"01",X"01",X"01",X"02",X"02",X"10",X"20",X"00",X"00",X"20",X"20",X"10",X"10",X"10", + X"01",X"01",X"01",X"02",X"02",X"02",X"10",X"10",X"10",X"20",X"20",X"01",X"01",X"20",X"10",X"20", + X"20",X"10",X"01",X"01",X"02",X"02",X"02",X"10",X"10",X"10",X"10",X"10",X"01",X"01",X"02",X"02", + X"00",X"23",X"45",X"2B",X"45",X"33",X"45",X"3B",X"45",X"43",X"45",X"4B",X"45",X"53",X"45",X"5B", + X"45",X"63",X"45",X"04",X"01",X"51",X"86",X"00",X"00",X"00",X"00",X"04",X"01",X"51",X"86",X"FF", + X"05",X"00",X"00",X"04",X"01",X"51",X"86",X"01",X"00",X"00",X"00",X"04",X"01",X"51",X"86",X"01", + X"05",X"00",X"00",X"04",X"01",X"51",X"86",X"02",X"00",X"00",X"00",X"04",X"01",X"51",X"86",X"02", + X"05",X"00",X"00",X"04",X"01",X"51",X"86",X"03",X"00",X"00",X"00",X"04",X"01",X"51",X"86",X"03", + X"05",X"00",X"00",X"04",X"01",X"51",X"86",X"04",X"00",X"00",X"00",X"13",X"02",X"0F",X"85",X"4D", + X"4D",X"4D",X"FF",X"05",X"00",X"FF",X"18",X"1B",X"FF",X"02",X"00",X"00",X"FF",X"19",X"18",X"12", + X"17",X"1D",X"0D",X"02",X"0C",X"85",X"4D",X"4D",X"4D",X"FF",X"02",X"00",X"00",X"FF",X"19",X"18", + X"12",X"17",X"1D",X"0D",X"02",X"09",X"85",X"4D",X"4D",X"4D",X"FF",X"03",X"00",X"00",X"FF",X"19", + X"18",X"12",X"17",X"1D",X"0D",X"02",X"06",X"85",X"4D",X"4D",X"4D",X"FF",X"05",X"00",X"00",X"FF", + X"19",X"18",X"12",X"17",X"1D",X"30",X"32",X"34",X"36",X"38",X"3A",X"3C",X"3E",X"40",X"42",X"44", + X"46",X"48",X"4A",X"4C",X"4E",X"50",X"52",X"54",X"56",X"58",X"5A",X"5C",X"5E",X"0C",X"03",X"54", + X"85",X"0D",X"18",X"17",X"1D",X"FF",X"1B",X"0E",X"20",X"1B",X"12",X"1D",X"0E",X"03",X"03",X"0D", + X"86",X"0E",X"15",X"1C",X"07",X"08",X"09",X"09",X"0A",X"08",X"0A",X"0B",X"09",X"0A",X"11",X"13", + X"06",X"07",X"07",X"07",X"06",X"04",X"08",X"08",X"03",X"05",X"04",X"04",X"FE",X"01",X"FE",X"00", + X"FE",X"01",X"FE",X"00",X"FE",X"01",X"FE",X"01",X"FE",X"01",X"FF",X"02",X"00",X"02",X"01",X"02", + X"02",X"01",X"02",X"01",X"02",X"01",X"02",X"00",X"02",X"01",X"02",X"00",X"02",X"01",X"02",X"01", + X"01",X"00",X"00",X"00",X"80",X"9C",X"10",X"F0",X"B4",X"4E",X"62",X"B4",X"9E",X"B2",X"CC",X"20", + X"32",X"CC",X"76",X"8B",X"CC",X"CE",X"E0",X"01",X"FD",X"03",X"FF",X"02",X"03",X"01",X"FD",X"03", + X"FF",X"02",X"03",X"01",X"FD",X"03",X"FF",X"02",X"03",X"01",X"FD",X"03",X"FF",X"01",X"03",X"03", + X"01",X"02",X"FD",X"01",X"03",X"03",X"01",X"02",X"FD",X"01",X"03",X"03",X"01",X"02",X"FD",X"01", + X"03",X"03",X"01",X"02",X"FF",X"A7",X"13",X"02",X"00",X"A7",X"13",X"02",X"01",X"A7",X"13",X"02", + X"01",X"A7",X"13",X"02",X"00",X"A7",X"13",X"02",X"FF",X"A7",X"13",X"80",X"02",X"FE",X"A7",X"13", + X"02",X"00",X"A7",X"13",X"80",X"02",X"02",X"A7",X"13",X"02",X"00",X"A7",X"13",X"80",X"02",X"00", + X"AF",X"13",X"02",X"00",X"AF",X"13",X"02",X"00",X"B3",X"13",X"02",X"00",X"B3",X"13",X"02",X"00", + X"AF",X"13",X"02",X"00",X"AF",X"13",X"02",X"00",X"AB",X"13",X"02",X"00",X"AB",X"13",X"80",X"02", + X"FE",X"B3",X"13",X"02",X"FE",X"B3",X"13",X"02",X"FF",X"B3",X"13",X"02",X"FF",X"AF",X"13",X"02", + X"FF",X"B3",X"13",X"02",X"FE",X"B3",X"13",X"02",X"FE",X"B3",X"13",X"80",X"02",X"02",X"AB",X"13", + X"02",X"02",X"AB",X"13",X"02",X"01",X"AB",X"13",X"02",X"01",X"AF",X"13",X"02",X"01",X"AB",X"13", + X"02",X"02",X"AB",X"13",X"02",X"02",X"AB",X"13",X"80",X"18",X"30",X"50",X"60",X"80",X"A0",X"B0", + X"D0",X"E9",X"FF",X"FD",X"00",X"FD",X"FF",X"FE",X"FE",X"FE",X"FD",X"FD",X"FE",X"FE",X"FD",X"FF", + X"FD",X"00",X"FD",X"01",X"FD",X"01",X"FD",X"02",X"FD",X"02",X"FD",X"03",X"FE",X"02",X"FE",X"03", + X"FE",X"03",X"FF",X"03",X"FF",X"03",X"FF",X"03",X"00",X"80",X"FE",X"00",X"FE",X"FF",X"FD",X"FF", + X"FD",X"FF",X"FD",X"FE",X"FD",X"FE",X"00",X"FE",X"03",X"FE",X"03",X"FE",X"03",X"FF",X"03",X"FF", + X"80",X"FD",X"00",X"FD",X"01",X"FE",X"02",X"FE",X"03",X"FD",X"02",X"FE",X"03",X"FF",X"03",X"00", + X"03",X"01",X"03",X"01",X"03",X"02",X"03",X"02",X"03",X"03",X"02",X"02",X"02",X"03",X"02",X"03", + X"01",X"03",X"01",X"03",X"01",X"03",X"00",X"80",X"FE",X"00",X"FE",X"01",X"FD",X"01",X"FD",X"01", + X"FD",X"02",X"FD",X"02",X"00",X"02",X"03",X"02",X"03",X"02",X"03",X"01",X"03",X"01",X"80",X"A2", + X"F0",X"E8",X"A2",X"B2",X"9E",X"A2",X"62",X"4E",X"BA",X"34",X"2C",X"BA",X"84",X"7C",X"BA",X"D2", + X"CE",X"D2",X"A8",X"A4",X"D2",X"48",X"44",X"A2",X"E7",X"B9",X"A2",X"97",X"69",X"A2",X"47",X"19", + X"BA",X"60",X"41",X"BA",X"B0",X"91",X"BA",X"E0",X"D0",X"D2",X"97",X"78",X"D2",X"3F",X"20",X"A4", + X"A4",X"A4",X"BC",X"BC",X"D4",X"D4",X"D4",X"9C",X"C0",X"37",X"12",X"9C",X"70",X"37",X"12",X"9C", + X"42",X"2F",X"12",X"B4",X"6A",X"2F",X"12",X"B4",X"98",X"37",X"12",X"CC",X"C8",X"37",X"12",X"CC", + X"92",X"2F",X"12",X"CC",X"3A",X"2F",X"12",X"00",X"FE",X"4B",X"12",X"00",X"FE",X"4B",X"12",X"00", + X"FE",X"4F",X"12",X"00",X"FE",X"4F",X"12",X"00",X"FE",X"53",X"12",X"00",X"FE",X"53",X"12",X"00", + X"FE",X"4F",X"12",X"00",X"FE",X"4F",X"12",X"80",X"00",X"02",X"3F",X"12",X"00",X"02",X"3F",X"12", + X"00",X"02",X"43",X"12",X"00",X"02",X"43",X"12",X"00",X"02",X"47",X"12",X"00",X"02",X"47",X"12", + X"00",X"02",X"43",X"12",X"00",X"02",X"43",X"12",X"80",X"03",X"00",X"83",X"12",X"03",X"00",X"83", + X"12",X"03",X"00",X"83",X"12",X"03",X"00",X"83",X"12",X"03",X"00",X"3F",X"12",X"02",X"02",X"3F", + X"12",X"02",X"02",X"43",X"12",X"02",X"02",X"43",X"12",X"02",X"02",X"47",X"12",X"01",X"02",X"47", + X"12",X"00",X"02",X"43",X"12",X"00",X"02",X"43",X"12",X"00",X"02",X"3F",X"12",X"00",X"02",X"3F", + X"12",X"00",X"02",X"43",X"12",X"00",X"02",X"43",X"12",X"00",X"02",X"47",X"12",X"00",X"02",X"47", + X"12",X"00",X"02",X"43",X"12",X"00",X"02",X"43",X"12",X"00",X"02",X"3F",X"12",X"00",X"02",X"3F", + X"12",X"00",X"02",X"43",X"12",X"00",X"02",X"43",X"12",X"00",X"02",X"47",X"12",X"00",X"02",X"47", + X"12",X"00",X"02",X"43",X"12",X"00",X"02",X"43",X"12",X"00",X"02",X"3F",X"12",X"00",X"02",X"3F", + X"12",X"00",X"02",X"43",X"12",X"00",X"02",X"43",X"12",X"00",X"02",X"47",X"12",X"00",X"02",X"47", + X"12",X"00",X"00",X"87",X"12",X"00",X"00",X"87",X"12",X"80",X"FD",X"01",X"57",X"12",X"FD",X"01", + X"57",X"12",X"FD",X"01",X"57",X"12",X"FD",X"01",X"57",X"12",X"FE",X"02",X"57",X"12",X"FD",X"02", + X"57",X"12",X"FE",X"03",X"57",X"12",X"FF",X"03",X"57",X"12",X"00",X"03",X"57",X"12",X"01",X"03", + X"57",X"12",X"02",X"03",X"57",X"12",X"01",X"01",X"83",X"12",X"00",X"00",X"87",X"12",X"00",X"00", + X"87",X"12",X"00",X"00",X"83",X"12",X"00",X"00",X"83",X"12",X"00",X"00",X"87",X"12",X"00",X"00", + X"87",X"12",X"80",X"FD",X"FF",X"5B",X"12",X"FD",X"FF",X"5B",X"12",X"FD",X"FF",X"5B",X"12",X"FD", + X"FF",X"5B",X"12",X"FE",X"FE",X"5B",X"12",X"FD",X"FE",X"5B",X"12",X"FE",X"FD",X"5B",X"12",X"FF", + X"FD",X"5B",X"12",X"00",X"FD",X"5B",X"12",X"01",X"FD",X"5B",X"12",X"02",X"FD",X"5B",X"12",X"01", + X"FF",X"83",X"12",X"00",X"00",X"87",X"12",X"00",X"00",X"87",X"12",X"00",X"00",X"83",X"12",X"00", + X"00",X"83",X"12",X"00",X"00",X"87",X"12",X"00",X"00",X"87",X"12",X"80",X"00",X"02",X"57",X"12", + X"01",X"03",X"57",X"12",X"03",X"02",X"57",X"12",X"03",X"01",X"57",X"12",X"01",X"00",X"83",X"12", + X"00",X"00",X"87",X"12",X"00",X"00",X"87",X"12",X"00",X"00",X"87",X"12",X"00",X"00",X"83",X"12", + X"00",X"00",X"83",X"12",X"00",X"00",X"87",X"12",X"00",X"00",X"87",X"12",X"80",X"00",X"02",X"57", + X"12",X"01",X"03",X"57",X"12",X"03",X"02",X"57",X"12",X"03",X"02",X"57",X"12",X"00",X"00",X"87", + X"12",X"80",X"00",X"00",X"6F",X"12",X"00",X"00",X"6F",X"12",X"00",X"06",X"73",X"12",X"00",X"00", + X"73",X"12",X"00",X"00",X"73",X"12",X"80",X"00",X"00",X"7B",X"12",X"00",X"00",X"7B",X"12",X"00", + X"FA",X"7F",X"12",X"00",X"00",X"7F",X"12",X"00",X"00",X"7F",X"12",X"80",X"00",X"00",X"77",X"12", + X"00",X"00",X"7B",X"12",X"00",X"FA",X"7F",X"12",X"00",X"00",X"7F",X"12",X"80",X"00",X"00",X"6B", + X"12",X"00",X"00",X"6F",X"12",X"00",X"06",X"73",X"12",X"00",X"00",X"73",X"12",X"80",X"03",X"FF", + X"4B",X"12",X"03",X"FF",X"4B",X"12",X"03",X"FF",X"4F",X"12",X"03",X"FF",X"4F",X"12",X"03",X"FF", + X"53",X"12",X"03",X"FF",X"53",X"12",X"03",X"FF",X"4F",X"12",X"03",X"FF",X"4F",X"12",X"01",X"FF", + X"4B",X"12",X"03",X"01",X"3F",X"12",X"03",X"01",X"3F",X"12",X"03",X"01",X"43",X"12",X"03",X"01", + X"43",X"12",X"03",X"01",X"47",X"12",X"03",X"01",X"47",X"12",X"03",X"01",X"43",X"12",X"03",X"01", + X"43",X"12",X"01",X"01",X"3F",X"12",X"FD",X"FF",X"5B",X"12",X"FD",X"FF",X"5B",X"12",X"FD",X"FE", + X"5B",X"12",X"FD",X"FE",X"5B",X"12",X"FD",X"FE",X"5B",X"12",X"FE",X"FD",X"5B",X"12",X"FE",X"FD", + X"5B",X"12",X"FF",X"FD",X"5B",X"12",X"00",X"FD",X"5B",X"12",X"01",X"FD",X"5B",X"12",X"01",X"FD", + X"5B",X"12",X"02",X"FE",X"5B",X"12",X"80",X"FD",X"01",X"57",X"12",X"FD",X"01",X"57",X"12",X"FD", + X"02",X"57",X"12",X"FD",X"02",X"57",X"12",X"FD",X"02",X"57",X"12",X"FE",X"03",X"57",X"12",X"FE", + X"03",X"57",X"12",X"FE",X"03",X"57",X"12",X"00",X"03",X"57",X"12",X"01",X"03",X"57",X"12",X"01", + X"03",X"57",X"12",X"02",X"02",X"57",X"12",X"80",X"A0",X"B8",X"A0",X"68",X"A0",X"18",X"B8",X"70", + X"B8",X"C0",X"D0",X"C0",X"D0",X"68",X"D0",X"40",X"03",X"10",X"8B",X"10",X"03",X"01",X"8B",X"10", + X"03",X"01",X"8B",X"10",X"03",X"01",X"9F",X"10",X"03",X"02",X"9F",X"10",X"03",X"03",X"9F",X"10", + X"02",X"03",X"9F",X"10",X"02",X"03",X"9F",X"10",X"01",X"03",X"8F",X"10",X"00",X"03",X"8F",X"10", + X"01",X"02",X"8F",X"10",X"00",X"03",X"8F",X"10",X"80",X"22",X"FD",X"00",X"93",X"10",X"FD",X"01", + X"93",X"10",X"FD",X"01",X"93",X"10",X"FD",X"01",X"A3",X"10",X"FD",X"02",X"A3",X"10",X"FE",X"03", + X"A3",X"10",X"FE",X"03",X"A3",X"10",X"FE",X"03",X"A3",X"10",X"FF",X"03",X"8F",X"10",X"00",X"03", + X"8F",X"10",X"FF",X"02",X"8F",X"10",X"00",X"02",X"8F",X"10",X"80",X"55",X"00",X"03",X"8F",X"10", + X"FF",X"03",X"8F",X"10",X"FF",X"03",X"8F",X"10",X"FF",X"03",X"A3",X"10",X"FE",X"03",X"A3",X"10", + X"FE",X"02",X"A3",X"10",X"FD",X"02",X"A3",X"10",X"FD",X"02",X"A3",X"10",X"FD",X"02",X"93",X"10", + X"FD",X"00",X"93",X"10",X"FD",X"01",X"93",X"10",X"FD",X"00",X"93",X"10",X"FD",X"00",X"93",X"10", + X"FD",X"FF",X"93",X"10",X"FD",X"FF",X"9B",X"10",X"FD",X"FE",X"9B",X"10",X"FD",X"FE",X"9B",X"10", + X"FE",X"FD",X"9B",X"10",X"FE",X"FD",X"9B",X"10",X"FE",X"FD",X"8D",X"10",X"FF",X"FD",X"8D",X"10", + X"FF",X"FD",X"8D",X"10",X"00",X"FD",X"8D",X"10",X"80",X"00",X"00",X"03",X"8F",X"10",X"01",X"03", + X"8F",X"10",X"01",X"03",X"8F",X"10",X"01",X"03",X"9F",X"10",X"02",X"03",X"9F",X"10",X"02",X"02", + X"9F",X"10",X"03",X"02",X"9F",X"10",X"03",X"02",X"9F",X"10",X"03",X"02",X"8B",X"10",X"03",X"00", + X"8B",X"10",X"03",X"01",X"8B",X"10",X"03",X"00",X"8B",X"10",X"03",X"00",X"8B",X"10",X"03",X"FF", + X"8B",X"10",X"03",X"FF",X"97",X"10",X"03",X"FE",X"97",X"10",X"03",X"FE",X"97",X"10",X"02",X"FD", + X"97",X"10",X"02",X"FD",X"97",X"10",X"02",X"FD",X"8D",X"10",X"01",X"FD",X"8D",X"10",X"01",X"FD", + X"8D",X"10",X"00",X"FD",X"8D",X"10",X"80",X"44",X"00",X"FD",X"8D",X"10",X"01",X"FD",X"8D",X"10", + X"01",X"FD",X"8D",X"10",X"01",X"FD",X"97",X"10",X"02",X"FD",X"97",X"10",X"02",X"FE",X"97",X"10", + X"02",X"FE",X"97",X"10",X"03",X"FE",X"97",X"10",X"03",X"FF",X"8B",X"10",X"03",X"FF",X"8B",X"10", + X"03",X"FF",X"8B",X"10",X"03",X"00",X"8B",X"10",X"80",X"61",X"00",X"FD",X"8D",X"10",X"FF",X"FD", + X"8D",X"10",X"FF",X"FD",X"8D",X"10",X"FF",X"FD",X"9B",X"10",X"FE",X"FD",X"9B",X"10",X"FE",X"FE", + X"9B",X"10",X"FE",X"FE",X"9B",X"10",X"FD",X"FE",X"9B",X"10",X"FD",X"FF",X"93",X"10",X"FD",X"FF", + X"93",X"10",X"FD",X"FF",X"93",X"10",X"FD",X"00",X"93",X"10",X"80",X"73",X"00",X"88",X"01",X"80", + X"00",X"80",X"01",X"88",X"02",X"88",X"03",X"80",X"02",X"80",X"03",X"88",X"14",X"88",X"15",X"80", + X"14",X"80",X"15",X"88",X"16",X"88",X"17",X"80",X"16",X"80",X"17",X"88",X"18",X"88",X"19",X"80", + X"18",X"80",X"19",X"88",X"1A",X"88",X"1B",X"80",X"1A",X"80",X"1B",X"88",X"1C",X"88",X"1D",X"80", + X"1C",X"80",X"1D",X"88",X"1E",X"88",X"1F",X"80",X"1E",X"80",X"1F",X"88",X"20",X"88",X"20",X"80", + X"00",X"A0",X"62",X"9A",X"21",X"88",X"21",X"80",X"01",X"A0",X"62",X"9A",X"22",X"88",X"22",X"80", + X"02",X"A0",X"62",X"9A",X"23",X"88",X"23",X"80",X"03",X"A0",X"62",X"9A",X"34",X"88",X"34",X"80", + X"04",X"A0",X"62",X"9A",X"35",X"88",X"35",X"80",X"05",X"A0",X"62",X"9A",X"36",X"88",X"36",X"80", + X"06",X"A0",X"62",X"9A",X"37",X"88",X"37",X"80",X"07",X"A0",X"62",X"9A",X"38",X"88",X"38",X"80", + X"08",X"A0",X"62",X"9A",X"39",X"88",X"39",X"80",X"09",X"A0",X"62",X"9A",X"3A",X"88",X"3A",X"80", + X"0A",X"A0",X"62",X"9A",X"3B",X"88",X"3B",X"80",X"0B",X"A0",X"62",X"9A",X"3C",X"88",X"3C",X"80", + X"0C",X"A0",X"62",X"9A",X"3D",X"88",X"3D",X"80",X"0D",X"A0",X"62",X"9A",X"3E",X"88",X"3E",X"80", + X"0E",X"A0",X"62",X"9A",X"3F",X"88",X"3F",X"80",X"0F",X"A0",X"62",X"9A",X"7F",X"7F",X"7F",X"7F", + X"47",X"46",X"45",X"44",X"79",X"78",X"77",X"76",X"00",X"00",X"00",X"00",X"05",X"05",X"05",X"05", + X"05",X"05",X"05",X"05",X"10",X"10",X"10",X"10",X"15",X"15",X"15",X"15",X"05",X"05",X"05",X"05", + X"7A",X"7A",X"7A",X"7A",X"4A",X"46",X"45",X"49",X"79",X"78",X"77",X"76",X"00",X"00",X"00",X"00", + X"05",X"05",X"05",X"05",X"05",X"05",X"05",X"05",X"00",X"00",X"00",X"00",X"05",X"05",X"05",X"05", + X"05",X"05",X"05",X"05",X"7F",X"7F",X"48",X"7F",X"47",X"46",X"45",X"44",X"7A",X"7A",X"7A",X"7A", + X"00",X"00",X"01",X"00",X"05",X"05",X"05",X"05",X"05",X"05",X"05",X"05",X"10",X"10",X"11",X"10", + X"15",X"05",X"05",X"15",X"05",X"05",X"05",X"05",X"7A",X"7A",X"4B",X"7A",X"4A",X"46",X"45",X"49", + X"7A",X"7A",X"7A",X"7A",X"00",X"00",X"07",X"00",X"05",X"05",X"05",X"05",X"05",X"05",X"05",X"05", + X"00",X"00",X"07",X"00",X"05",X"05",X"05",X"05",X"05",X"05",X"05",X"05",X"7F",X"51",X"4F",X"7F", + X"53",X"52",X"50",X"4E",X"79",X"78",X"77",X"76",X"00",X"06",X"06",X"00",X"06",X"06",X"06",X"06", + X"04",X"04",X"04",X"04",X"10",X"16",X"16",X"10",X"16",X"16",X"16",X"16",X"04",X"04",X"04",X"04", + X"7A",X"5B",X"59",X"7A",X"5D",X"5C",X"5A",X"58",X"79",X"78",X"77",X"76",X"00",X"06",X"06",X"00", + X"06",X"06",X"06",X"06",X"04",X"04",X"04",X"04",X"00",X"06",X"06",X"00",X"06",X"06",X"06",X"06", + X"04",X"04",X"04",X"04",X"7F",X"7F",X"7F",X"7F",X"57",X"56",X"55",X"54",X"7A",X"7A",X"7A",X"7A", + X"00",X"00",X"00",X"00",X"06",X"06",X"06",X"06",X"04",X"04",X"04",X"04",X"10",X"10",X"10",X"10", + X"16",X"16",X"16",X"16",X"04",X"04",X"04",X"04",X"7A",X"7A",X"7A",X"7A",X"61",X"60",X"5F",X"5E", + X"7A",X"7A",X"7A",X"7A",X"00",X"00",X"00",X"00",X"06",X"06",X"06",X"06",X"04",X"04",X"04",X"04", + X"00",X"00",X"00",X"00",X"06",X"06",X"06",X"06",X"04",X"04",X"04",X"04",X"7F",X"65",X"63",X"7F", + X"67",X"66",X"64",X"62",X"79",X"78",X"77",X"76",X"00",X"08",X"08",X"00",X"08",X"08",X"08",X"08", + X"01",X"01",X"01",X"01",X"10",X"18",X"18",X"10",X"18",X"18",X"18",X"18",X"01",X"01",X"01",X"01", + X"7A",X"6F",X"6D",X"7A",X"71",X"70",X"6E",X"6C",X"79",X"78",X"77",X"76",X"00",X"08",X"08",X"00", + X"08",X"08",X"08",X"08",X"01",X"01",X"01",X"01",X"00",X"08",X"08",X"00",X"08",X"08",X"08",X"08", + X"01",X"01",X"01",X"01",X"7F",X"7F",X"7F",X"7F",X"6B",X"6A",X"69",X"68",X"7A",X"7A",X"7A",X"7A", + X"00",X"00",X"00",X"00",X"08",X"08",X"08",X"08",X"01",X"01",X"01",X"01",X"10",X"10",X"10",X"10", + X"18",X"18",X"18",X"18",X"01",X"01",X"01",X"01",X"7A",X"7A",X"7A",X"7A",X"75",X"74",X"73",X"72", + X"7A",X"7A",X"7A",X"7A",X"00",X"00",X"00",X"00",X"08",X"08",X"08",X"08",X"01",X"01",X"01",X"01", + X"10",X"10",X"10",X"10",X"08",X"08",X"08",X"08",X"01",X"01",X"01",X"01",X"7F",X"D4",X"D2",X"7F", + X"7F",X"D5",X"D3",X"7F",X"7A",X"7A",X"7A",X"7A",X"00",X"09",X"09",X"00",X"00",X"09",X"09",X"00", + X"01",X"01",X"01",X"01",X"10",X"19",X"19",X"10",X"10",X"19",X"19",X"10",X"01",X"01",X"01",X"01", + X"7A",X"D4",X"D2",X"7A",X"7A",X"D5",X"D3",X"7A",X"7A",X"7A",X"7A",X"7A",X"00",X"09",X"09",X"00", + X"00",X"09",X"09",X"00",X"01",X"01",X"01",X"01",X"00",X"09",X"09",X"00",X"00",X"09",X"09",X"00", + X"01",X"01",X"01",X"01",X"DC",X"DA",X"D8",X"D6",X"DD",X"DB",X"D9",X"D7",X"7A",X"7A",X"7A",X"7A", + X"09",X"09",X"09",X"09",X"09",X"09",X"09",X"09",X"04",X"04",X"04",X"04",X"19",X"19",X"19",X"19", + X"19",X"19",X"19",X"19",X"04",X"04",X"04",X"04",X"DC",X"DA",X"D8",X"D6",X"DD",X"DB",X"D9",X"D7", + X"7A",X"7A",X"7A",X"7A",X"09",X"09",X"09",X"09",X"09",X"09",X"09",X"09",X"04",X"04",X"04",X"04", + X"09",X"09",X"09",X"09",X"09",X"09",X"09",X"09",X"04",X"04",X"04",X"04",X"0D",X"87",X"CD",X"85", + X"8D",X"84",X"2A",X"85",X"6A",X"86",X"27",X"87",X"C7",X"85",X"67",X"84",X"0F",X"FC",X"FC",X"00", + X"0E",X"FC",X"00",X"00",X"0E",X"00",X"FC",X"00",X"0F",X"00",X"00",X"00",X"02",X"12",X"BC",X"BA", + X"B8",X"B6",X"B4",X"BD",X"BB",X"B9",X"B7",X"B5",X"C6",X"C4",X"C2",X"C0",X"BE",X"C7",X"C5",X"C3", + X"C1",X"BF",X"D0",X"CE",X"CC",X"CA",X"C8",X"D1",X"CF",X"CD",X"CB",X"C9",X"7F",X"B2",X"B0",X"AE", + X"AC",X"7F",X"B3",X"B1",X"AF",X"AD",X"00",X"10",X"88",X"86",X"84",X"89",X"87",X"85",X"8E",X"8C", + X"8A",X"8F",X"8D",X"8B",X"94",X"92",X"90",X"95",X"93",X"91",X"7F",X"82",X"80",X"7F",X"83",X"81", + X"01",X"11",X"9E",X"9C",X"9A",X"9F",X"9D",X"9B",X"A4",X"A2",X"A0",X"A5",X"A3",X"A1",X"AA",X"A8", + X"A6",X"AB",X"A9",X"A7",X"7F",X"98",X"96",X"7F",X"99",X"97",X"09",X"19",X"E6",X"E4",X"E2",X"E0", + X"DE",X"E7",X"E5",X"E3",X"E1",X"DF",X"E6",X"E4",X"E2",X"E0",X"DE",X"E7",X"E5",X"E3",X"E1",X"DF", + X"7F",X"DC",X"DA",X"D8",X"D6",X"7F",X"DD",X"DB",X"D9",X"D7",X"7F",X"DC",X"DA",X"D8",X"D6",X"7F", + X"DD",X"DB",X"D9",X"D7",X"05",X"15",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F", + X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F", + X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"50",X"99", + X"70",X"99",X"90",X"99",X"B0",X"99",X"D0",X"99",X"21",X"8A",X"48",X"C3",X"6D",X"2F",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/cmd_snd_rom.vhd b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/cmd_snd_rom.vhd new file mode 100644 index 00000000..75a9efbe --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/cmd_snd_rom.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity cmd_snd_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of cmd_snd_rom is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"F3",X"C3",X"00",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"F5",X"DD",X"E5",X"E5",X"C5",X"D5",X"FD",X"E5", + X"00",X"00",X"00",X"CD",X"46",X"01",X"CD",X"32",X"03",X"CD",X"F9",X"05",X"FD",X"E1",X"D1",X"C1", + X"E1",X"DD",X"E1",X"F1",X"FB",X"ED",X"4D",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"21",X"00",X"20",X"11",X"01",X"20",X"01",X"FF",X"03",X"36",X"00",X"ED",X"B0",X"31",X"FF",X"23", + X"DD",X"21",X"67",X"06",X"0E",X"10",X"16",X"00",X"7A",X"DD",X"46",X"00",X"CD",X"57",X"06",X"DD", + X"23",X"14",X"0D",X"C2",X"18",X"01",X"DD",X"21",X"67",X"06",X"16",X"00",X"0E",X"10",X"7A",X"DD", + X"46",X"00",X"CD",X"5F",X"06",X"DD",X"23",X"14",X"0D",X"C2",X"2E",X"01",X"FB",X"00",X"CD",X"86", + X"01",X"00",X"00",X"C3",X"3D",X"01",X"3E",X"0E",X"CD",X"49",X"06",X"CB",X"7F",X"C2",X"59",X"01", + X"26",X"00",X"6F",X"22",X"00",X"20",X"C3",X"75",X"01",X"CB",X"BF",X"67",X"2E",X"00",X"CB",X"3C", + X"CB",X"1D",X"CB",X"3C",X"CB",X"1D",X"CB",X"3C",X"CB",X"1D",X"CB",X"3C",X"CB",X"1D",X"CB",X"3C", + X"CB",X"1D",X"22",X"00",X"20",X"DD",X"21",X"02",X"20",X"DD",X"34",X"07",X"DD",X"34",X"0F",X"DD", + X"34",X"17",X"DD",X"34",X"2F",X"C9",X"ED",X"5B",X"00",X"20",X"21",X"00",X"00",X"22",X"00",X"20", + X"CB",X"43",X"C2",X"F7",X"01",X"CB",X"3A",X"CB",X"1B",X"CB",X"43",X"C2",X"86",X"02",X"CB",X"3A", + X"CB",X"1B",X"CB",X"43",X"C2",X"3C",X"02",X"3A",X"33",X"20",X"A7",X"C0",X"CB",X"3A",X"CB",X"1B", + X"0E",X"07",X"DD",X"21",X"87",X"06",X"CB",X"43",X"C4",X"C8",X"02",X"CB",X"3A",X"CB",X"1B",X"DD", + X"23",X"DD",X"23",X"DD",X"23",X"DD",X"23",X"0D",X"C2",X"B6",X"01",X"DD",X"21",X"02",X"20",X"CD", + X"E8",X"01",X"DD",X"21",X"0A",X"20",X"CD",X"E8",X"01",X"DD",X"21",X"12",X"20",X"CD",X"E8",X"01", + X"DD",X"21",X"2A",X"20",X"CD",X"E8",X"01",X"C9",X"DD",X"7E",X"07",X"FE",X"20",X"D8",X"DD",X"36", + X"07",X"00",X"DD",X"36",X"00",X"0F",X"C9",X"3E",X"0F",X"32",X"02",X"20",X"32",X"0A",X"20",X"32", + X"12",X"20",X"32",X"1A",X"20",X"32",X"22",X"20",X"32",X"2A",X"20",X"DD",X"21",X"67",X"06",X"0E", + X"10",X"16",X"00",X"7A",X"DD",X"46",X"00",X"CD",X"57",X"06",X"DD",X"23",X"14",X"0D",X"C2",X"13", + X"02",X"DD",X"21",X"67",X"06",X"16",X"00",X"0E",X"10",X"7A",X"DD",X"46",X"00",X"CD",X"5F",X"06", + X"DD",X"23",X"14",X"0D",X"C2",X"29",X"02",X"AF",X"32",X"33",X"20",X"C9",X"AF",X"32",X"02",X"20", + X"32",X"0A",X"20",X"32",X"12",X"20",X"32",X"1A",X"20",X"32",X"22",X"20",X"32",X"2A",X"20",X"3A", + X"33",X"20",X"A7",X"C0",X"3E",X"FF",X"32",X"33",X"20",X"DD",X"21",X"77",X"06",X"16",X"00",X"0E", + X"10",X"7A",X"DD",X"46",X"00",X"CD",X"57",X"06",X"DD",X"23",X"14",X"0D",X"C2",X"61",X"02",X"DD", + X"21",X"67",X"06",X"16",X"00",X"0E",X"10",X"7A",X"DD",X"46",X"00",X"CD",X"5F",X"06",X"DD",X"23", + X"14",X"0D",X"C2",X"77",X"02",X"C9",X"3A",X"1A",X"20",X"A7",X"C0",X"DD",X"21",X"1A",X"20",X"DD", + X"36",X"00",X"FF",X"DD",X"36",X"01",X"01",X"DD",X"36",X"02",X"00",X"21",X"7A",X"08",X"DD",X"75", + X"03",X"DD",X"74",X"04",X"DD",X"36",X"05",X"00",X"DD",X"21",X"22",X"20",X"DD",X"36",X"00",X"FF", + X"DD",X"36",X"01",X"01",X"DD",X"36",X"02",X"00",X"21",X"C6",X"09",X"DD",X"75",X"03",X"DD",X"74", + X"04",X"DD",X"36",X"05",X"01",X"C3",X"AC",X"01",X"DD",X"7E",X"02",X"FE",X"03",X"CA",X"E1",X"02", + X"FE",X"00",X"CA",X"E8",X"02",X"FE",X"01",X"CA",X"EF",X"02",X"FD",X"21",X"12",X"20",X"C3",X"F3", + X"02",X"FD",X"21",X"2A",X"20",X"C3",X"F3",X"02",X"FD",X"21",X"02",X"20",X"C3",X"F3",X"02",X"FD", + X"21",X"0A",X"20",X"FD",X"7E",X"00",X"A7",X"CA",X"04",X"03",X"DD",X"7E",X"03",X"FD",X"BE",X"05", + X"CA",X"2D",X"03",X"D0",X"FD",X"36",X"00",X"FF",X"FD",X"36",X"01",X"01",X"FD",X"36",X"02",X"00", + X"FD",X"36",X"07",X"00",X"DD",X"6E",X"00",X"DD",X"66",X"01",X"FD",X"75",X"03",X"FD",X"74",X"04", + X"DD",X"7E",X"03",X"FD",X"77",X"05",X"DD",X"7E",X"02",X"FD",X"77",X"06",X"C9",X"FD",X"36",X"07", + X"00",X"C9",X"CD",X"52",X"03",X"DD",X"21",X"2A",X"20",X"CD",X"32",X"04",X"DD",X"21",X"02",X"20", + X"CD",X"32",X"04",X"DD",X"21",X"0A",X"20",X"CD",X"32",X"04",X"DD",X"21",X"12",X"20",X"CD",X"32", + X"04",X"C9",X"3A",X"32",X"20",X"3C",X"32",X"32",X"20",X"FE",X"01",X"C0",X"AF",X"32",X"32",X"20", + X"DD",X"21",X"1A",X"20",X"CD",X"6F",X"03",X"DD",X"21",X"22",X"20",X"CD",X"6F",X"03",X"C9",X"DD", + X"7E",X"00",X"A7",X"C8",X"FE",X"0F",X"CA",X"08",X"04",X"DD",X"7E",X"01",X"3D",X"DD",X"77",X"01", + X"C0",X"DD",X"6E",X"03",X"DD",X"66",X"04",X"DD",X"4E",X"02",X"DD",X"34",X"02",X"06",X"00",X"CB", + X"21",X"CB",X"10",X"CB",X"21",X"CB",X"10",X"09",X"E5",X"FD",X"E1",X"FD",X"7E",X"00",X"FE",X"FF", + X"CA",X"C2",X"03",X"DD",X"77",X"01",X"DD",X"7E",X"05",X"FE",X"00",X"CA",X"CB",X"03",X"FE",X"01", + X"CA",X"DA",X"03",X"16",X"04",X"3E",X"07",X"CD",X"49",X"06",X"CB",X"97",X"CB",X"EF",X"4F",X"C3", + X"E6",X"03",X"DD",X"36",X"02",X"00",X"DD",X"36",X"01",X"01",X"C9",X"16",X"00",X"3E",X"07",X"CD", + X"49",X"06",X"CB",X"87",X"CB",X"DF",X"4F",X"C3",X"E6",X"03",X"16",X"02",X"3E",X"07",X"CD",X"49", + X"06",X"CB",X"8F",X"CB",X"E7",X"4F",X"7A",X"FD",X"46",X"01",X"CD",X"57",X"06",X"7A",X"C6",X"01", + X"FD",X"46",X"02",X"CD",X"57",X"06",X"7A",X"CB",X"3F",X"C6",X"08",X"FD",X"46",X"03",X"CD",X"57", + X"06",X"3E",X"07",X"41",X"CD",X"57",X"06",X"C9",X"3E",X"07",X"CD",X"49",X"06",X"4F",X"DD",X"7E", + X"05",X"FE",X"00",X"CA",X"20",X"04",X"FE",X"01",X"CA",X"25",X"04",X"CB",X"D1",X"C3",X"27",X"04", + X"CB",X"C1",X"C3",X"27",X"04",X"CB",X"C9",X"3E",X"07",X"41",X"CD",X"57",X"06",X"DD",X"36",X"00", + X"00",X"C9",X"DD",X"7E",X"00",X"A7",X"C8",X"FE",X"0F",X"CA",X"42",X"05",X"DD",X"7E",X"01",X"3D", + X"DD",X"77",X"01",X"C0",X"DD",X"4E",X"02",X"DD",X"34",X"02",X"06",X"00",X"21",X"00",X"00",X"09", + X"09",X"09",X"09",X"09",X"09",X"DD",X"4E",X"03",X"DD",X"46",X"04",X"09",X"E5",X"FD",X"E1",X"FD", + X"7E",X"00",X"FE",X"FF",X"CA",X"9A",X"04",X"FE",X"FE",X"CA",X"9F",X"04",X"DD",X"77",X"01",X"FD", + X"5E",X"01",X"3E",X"07",X"CD",X"50",X"06",X"47",X"DD",X"7E",X"06",X"FE",X"03",X"CA",X"8A",X"05", + X"FE",X"00",X"CA",X"A8",X"04",X"FE",X"01",X"CA",X"B8",X"04",X"16",X"04",X"CB",X"4B",X"C4",X"DC", + X"04",X"CB",X"53",X"C4",X"E1",X"04",X"48",X"C3",X"E6",X"04",X"DD",X"36",X"00",X"0F",X"C9",X"DD", + X"36",X"02",X"00",X"DD",X"36",X"01",X"01",X"C9",X"16",X"00",X"CB",X"4B",X"C4",X"C8",X"04",X"CB", + X"53",X"C4",X"CD",X"04",X"48",X"C3",X"E6",X"04",X"16",X"02",X"CB",X"4B",X"C4",X"D2",X"04",X"CB", + X"53",X"C4",X"D7",X"04",X"48",X"C3",X"E6",X"04",X"CB",X"80",X"CB",X"D8",X"C9",X"CB",X"98",X"CB", + X"C0",X"C9",X"CB",X"88",X"CB",X"E0",X"C9",X"CB",X"A0",X"CB",X"C8",X"C9",X"CB",X"90",X"CB",X"E8", + X"C9",X"CB",X"A8",X"CB",X"D0",X"C9",X"CB",X"43",X"C2",X"15",X"05",X"7A",X"FD",X"46",X"02",X"CD", + X"5F",X"06",X"7A",X"C6",X"01",X"FD",X"46",X"03",X"CD",X"5F",X"06",X"3E",X"06",X"FD",X"46",X"04", + X"CD",X"5F",X"06",X"7A",X"CB",X"3F",X"C6",X"08",X"FD",X"46",X"05",X"CD",X"5F",X"06",X"3E",X"07", + X"41",X"CD",X"5F",X"06",X"C9",X"3E",X"0B",X"FD",X"46",X"02",X"CD",X"5F",X"06",X"3E",X"0C",X"FD", + X"46",X"03",X"CD",X"5F",X"06",X"3E",X"06",X"FD",X"46",X"04",X"CD",X"5F",X"06",X"7A",X"CB",X"3F", + X"C6",X"08",X"06",X"10",X"CD",X"5F",X"06",X"3E",X"0D",X"FD",X"46",X"05",X"CD",X"5F",X"06",X"C3", + X"0E",X"05",X"3E",X"07",X"CD",X"50",X"06",X"47",X"DD",X"7E",X"06",X"FE",X"03",X"CA",X"76",X"05", + X"FE",X"00",X"CA",X"61",X"05",X"FE",X"01",X"CA",X"68",X"05",X"CB",X"D0",X"CB",X"E8",X"C3",X"6C", + X"05",X"CB",X"C0",X"CB",X"D8",X"C3",X"6C",X"05",X"CB",X"C8",X"CB",X"D0",X"3E",X"07",X"CD",X"5F", + X"06",X"AF",X"DD",X"77",X"00",X"C9",X"3E",X"07",X"CD",X"49",X"06",X"CB",X"D7",X"CB",X"EF",X"47", + X"3E",X"07",X"CD",X"57",X"06",X"DD",X"36",X"00",X"00",X"C9",X"3E",X"07",X"CD",X"49",X"06",X"47", + X"16",X"04",X"CB",X"4B",X"C4",X"DC",X"04",X"CB",X"53",X"C4",X"E1",X"04",X"48",X"CB",X"43",X"C2", + X"CC",X"05",X"7A",X"FD",X"46",X"02",X"CD",X"57",X"06",X"7A",X"C6",X"01",X"FD",X"46",X"03",X"CD", + X"57",X"06",X"3E",X"06",X"FD",X"46",X"04",X"CD",X"57",X"06",X"7A",X"CB",X"3F",X"C6",X"08",X"FD", + X"46",X"05",X"CD",X"57",X"06",X"3E",X"07",X"41",X"CD",X"57",X"06",X"C9",X"3E",X"0B",X"FD",X"46", + X"02",X"CD",X"57",X"06",X"3E",X"0C",X"FD",X"46",X"03",X"CD",X"57",X"06",X"3E",X"06",X"FD",X"46", + X"04",X"CD",X"57",X"06",X"7A",X"CB",X"3F",X"C6",X"08",X"06",X"10",X"CD",X"57",X"06",X"3E",X"0D", + X"FD",X"46",X"05",X"CD",X"57",X"06",X"C3",X"C5",X"05",X"3A",X"33",X"20",X"A7",X"C8",X"3D",X"32", + X"33",X"20",X"FE",X"04",X"D0",X"AF",X"32",X"33",X"20",X"3A",X"1A",X"20",X"A7",X"C0",X"DD",X"21", + X"1A",X"20",X"DD",X"36",X"00",X"FF",X"DD",X"36",X"01",X"01",X"DD",X"36",X"02",X"00",X"21",X"7A", + X"08",X"DD",X"75",X"03",X"DD",X"74",X"04",X"DD",X"36",X"05",X"00",X"DD",X"21",X"22",X"20",X"DD", + X"36",X"00",X"FF",X"DD",X"36",X"01",X"01",X"DD",X"36",X"02",X"00",X"21",X"C6",X"09",X"DD",X"75", + X"03",X"DD",X"74",X"04",X"DD",X"36",X"05",X"01",X"C9",X"32",X"00",X"50",X"3A",X"00",X"40",X"C9", + X"32",X"00",X"70",X"3A",X"00",X"60",X"C9",X"32",X"00",X"50",X"78",X"32",X"00",X"40",X"C9",X"32", + X"00",X"70",X"78",X"32",X"00",X"60",X"C9",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"3F",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"1F",X"37",X"10", + X"00",X"00",X"00",X"60",X"09",X"00",X"00",X"A7",X"06",X"02",X"04",X"03",X"07",X"00",X"05",X"CB", + X"06",X"03",X"06",X"FB",X"06",X"00",X"07",X"7C",X"07",X"01",X"08",X"0B",X"07",X"01",X"09",X"49", + X"07",X"00",X"0A",X"49",X"07",X"00",X"0A",X"04",X"02",X"F0",X"00",X"00",X"0E",X"02",X"02",X"A0", + X"00",X"00",X"0E",X"02",X"02",X"90",X"00",X"00",X"0E",X"02",X"02",X"80",X"00",X"00",X"0E",X"02", + X"02",X"70",X"00",X"00",X"0E",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"02",X"02",X"F0",X"00",X"00", + X"0E",X"02",X"02",X"00",X"00",X"00",X"00",X"02",X"02",X"F0",X"00",X"00",X"0E",X"02",X"02",X"00", + X"00",X"00",X"0E",X"02",X"02",X"F0",X"00",X"00",X"0E",X"02",X"02",X"00",X"00",X"00",X"00",X"02", + X"02",X"F0",X"00",X"00",X"0E",X"02",X"02",X"00",X"00",X"00",X"00",X"20",X"05",X"00",X"10",X"07", + X"09",X"FF",X"FF",X"20",X"05",X"00",X"20",X"0F",X"09",X"0F",X"0F",X"02",X"02",X"00",X"02",X"00", + X"0F",X"02",X"02",X"00",X"00",X"00",X"00",X"02",X"02",X"80",X"01",X"00",X"0F",X"02",X"02",X"40", + X"01",X"00",X"0F",X"02",X"02",X"00",X"00",X"00",X"00",X"02",X"02",X"20",X"01",X"00",X"0F",X"02", + X"02",X"00",X"00",X"00",X"00",X"02",X"00",X"10",X"00",X"00",X"0F",X"05",X"02",X"E0",X"00",X"00", + X"0F",X"05",X"02",X"20",X"01",X"00",X"0F",X"FF",X"FF",X"05",X"02",X"00",X"02",X"00",X"0C",X"02", + X"00",X"00",X"00",X"00",X"00",X"05",X"02",X"00",X"01",X"00",X"0C",X"02",X"00",X"00",X"00",X"00", + X"00",X"05",X"02",X"00",X"02",X"00",X"0C",X"02",X"00",X"00",X"00",X"00",X"00",X"05",X"02",X"00", + X"01",X"00",X"0C",X"02",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"08",X"02",X"00",X"01", + X"00",X"0E",X"08",X"02",X"08",X"01",X"00",X"0E",X"08",X"02",X"10",X"01",X"00",X"0E",X"08",X"02", + X"18",X"01",X"00",X"0E",X"08",X"02",X"20",X"01",X"00",X"0E",X"08",X"02",X"28",X"01",X"00",X"0E", + X"08",X"02",X"30",X"01",X"00",X"0E",X"08",X"02",X"38",X"01",X"00",X"0E",X"08",X"02",X"40",X"01", + X"00",X"0E",X"08",X"02",X"48",X"01",X"00",X"0E",X"08",X"02",X"50",X"01",X"00",X"0E",X"08",X"02", + X"58",X"01",X"00",X"0E",X"08",X"02",X"60",X"01",X"00",X"0E",X"08",X"02",X"68",X"01",X"00",X"0E", + X"08",X"02",X"70",X"01",X"00",X"0E",X"08",X"02",X"78",X"01",X"00",X"0E",X"08",X"02",X"80",X"01", + X"00",X"0E",X"08",X"02",X"88",X"01",X"00",X"0E",X"08",X"02",X"90",X"01",X"00",X"0E",X"08",X"02", + X"98",X"01",X"00",X"0E",X"08",X"02",X"A0",X"01",X"00",X"0E",X"08",X"02",X"A8",X"01",X"00",X"0E", + X"08",X"02",X"B0",X"01",X"00",X"0E",X"08",X"02",X"B8",X"01",X"00",X"0E",X"08",X"02",X"C0",X"01", + X"00",X"0E",X"08",X"02",X"C8",X"01",X"00",X"0E",X"08",X"02",X"D0",X"01",X"00",X"0E",X"08",X"02", + X"D8",X"01",X"00",X"0E",X"08",X"02",X"E0",X"01",X"00",X"0E",X"08",X"02",X"E8",X"01",X"00",X"0E", + X"08",X"02",X"F0",X"01",X"00",X"0E",X"08",X"02",X"F8",X"01",X"00",X"0E",X"08",X"02",X"00",X"02", + X"00",X"0E",X"08",X"02",X"08",X"02",X"00",X"0E",X"08",X"02",X"10",X"02",X"00",X"0E",X"08",X"02", + X"18",X"02",X"00",X"0E",X"08",X"02",X"20",X"02",X"00",X"0E",X"08",X"02",X"28",X"02",X"00",X"0E", + X"08",X"02",X"30",X"02",X"00",X"0E",X"08",X"02",X"38",X"02",X"00",X"0E",X"08",X"02",X"40",X"02", + X"00",X"0E",X"08",X"02",X"48",X"02",X"00",X"0E",X"FF",X"FF",X"0A",X"8F",X"00",X"09",X"02",X"01", + X"00",X"00",X"0A",X"AA",X"00",X"09",X"26",X"01",X"00",X"00",X"0B",X"AA",X"00",X"09",X"01",X"01", + X"00",X"00",X"0B",X"A0",X"00",X"09",X"01",X"01",X"00",X"00",X"0B",X"8F",X"00",X"09",X"01",X"01", + X"00",X"00",X"0A",X"55",X"00",X"09",X"0E",X"01",X"00",X"00",X"0A",X"55",X"00",X"09",X"0E",X"01", + X"00",X"00",X"23",X"6B",X"00",X"09",X"0D",X"01",X"00",X"00",X"0A",X"8F",X"00",X"09",X"02",X"01", + X"00",X"00",X"0A",X"AA",X"00",X"09",X"26",X"01",X"00",X"00",X"0B",X"AA",X"00",X"09",X"01",X"01", + X"00",X"00",X"0B",X"A0",X"00",X"09",X"01",X"01",X"00",X"00",X"0B",X"AA",X"00",X"09",X"01",X"01", + X"00",X"00",X"0A",X"8F",X"00",X"09",X"0E",X"01",X"00",X"00",X"0A",X"8F",X"00",X"09",X"0E",X"01", + X"00",X"00",X"23",X"A0",X"00",X"09",X"0D",X"01",X"00",X"00",X"0A",X"A0",X"00",X"09",X"02",X"01", + X"00",X"00",X"0A",X"BE",X"00",X"09",X"26",X"01",X"00",X"00",X"0B",X"BE",X"00",X"09",X"01",X"01", + X"00",X"00",X"0B",X"AA",X"00",X"09",X"01",X"01",X"00",X"00",X"0B",X"A0",X"00",X"09",X"01",X"01", + X"00",X"00",X"0A",X"8F",X"00",X"09",X"02",X"01",X"00",X"00",X"0A",X"AA",X"00",X"09",X"26",X"01", + X"00",X"00",X"0B",X"AA",X"00",X"09",X"01",X"01",X"00",X"00",X"0B",X"97",X"00",X"09",X"01",X"01", + X"00",X"00",X"0B",X"AA",X"00",X"09",X"01",X"01",X"00",X"00",X"0B",X"BE",X"00",X"09",X"01",X"01", + X"00",X"00",X"17",X"8F",X"00",X"09",X"01",X"01",X"00",X"00",X"0B",X"AA",X"00",X"09",X"01",X"01", + X"00",X"00",X"0B",X"97",X"00",X"09",X"01",X"01",X"00",X"00",X"0A",X"BE",X"00",X"09",X"0E",X"01", + X"00",X"00",X"0B",X"7F",X"00",X"09",X"01",X"01",X"00",X"00",X"11",X"8F",X"00",X"09",X"01",X"01", + X"00",X"00",X"05",X"97",X"00",X"09",X"01",X"01",X"00",X"00",X"0B",X"8F",X"00",X"09",X"01",X"01", + X"00",X"00",X"0B",X"7F",X"00",X"09",X"01",X"01",X"00",X"00",X"0B",X"8F",X"00",X"09",X"01",X"01", + X"00",X"00",X"0B",X"A0",X"00",X"09",X"01",X"01",X"00",X"00",X"0B",X"AA",X"00",X"09",X"01",X"01", + X"00",X"00",X"0B",X"BE",X"00",X"09",X"01",X"01",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"23",X"53",X"01",X"08",X"01",X"01",X"00",X"00",X"0B",X"AC", + X"01",X"08",X"01",X"01",X"00",X"00",X"23",X"53",X"01",X"08",X"01",X"01",X"00",X"00",X"0B",X"AC", + X"01",X"08",X"01",X"01",X"00",X"00",X"17",X"1D",X"01",X"08",X"01",X"01",X"00",X"00",X"17",X"53", + X"01",X"08",X"01",X"01",X"00",X"00",X"17",X"AC",X"01",X"08",X"19",X"01",X"00",X"00",X"23",X"53", + X"01",X"08",X"01",X"01",X"00",X"00",X"0B",X"7D",X"01",X"08",X"01",X"01",X"00",X"00",X"23",X"53", + X"01",X"08",X"01",X"01",X"00",X"00",X"0B",X"7D",X"01",X"08",X"01",X"01",X"00",X"00",X"17",X"FE", + X"00",X"08",X"01",X"01",X"00",X"00",X"17",X"40",X"01",X"08",X"01",X"01",X"00",X"00",X"17",X"AC", + X"01",X"08",X"19",X"01",X"00",X"00",X"0B",X"40",X"01",X"08",X"07",X"01",X"00",X"00",X"05",X"AC", + X"01",X"08",X"01",X"01",X"00",X"00",X"17",X"AC",X"01",X"08",X"01",X"01",X"00",X"00",X"0B",X"40", + X"01",X"08",X"07",X"01",X"00",X"00",X"05",X"AC",X"01",X"08",X"01",X"01",X"00",X"00",X"17",X"AC", + X"01",X"08",X"01",X"01",X"00",X"00",X"0B",X"1D",X"01",X"08",X"07",X"01",X"00",X"00",X"05",X"AC", + X"01",X"08",X"01",X"01",X"00",X"00",X"17",X"AC",X"01",X"08",X"01",X"01",X"00",X"00",X"0B",X"1D", + X"01",X"08",X"07",X"01",X"00",X"00",X"05",X"AC",X"01",X"08",X"01",X"01",X"00",X"00",X"17",X"AC", + X"01",X"08",X"01",X"01",X"00",X"00",X"17",X"1D",X"01",X"08",X"01",X"01",X"00",X"00",X"11",X"1D", + X"01",X"08",X"01",X"01",X"00",X"00",X"05",X"FE",X"00",X"08",X"01",X"01",X"00",X"00",X"0B",X"1D", + X"01",X"08",X"01",X"01",X"00",X"00",X"0B",X"53",X"01",X"08",X"01",X"01",X"00",X"00",X"0B",X"AC", + X"01",X"08",X"01",X"01",X"00",X"00",X"0B",X"53",X"01",X"08",X"01",X"01",X"00",X"00",X"05",X"1D", + X"01",X"08",X"07",X"01",X"00",X"00",X"05",X"1D",X"01",X"08",X"01",X"01",X"00",X"00",X"05",X"FE", + X"00",X"08",X"01",X"01",X"00",X"00",X"05",X"1D",X"01",X"08",X"07",X"01",X"00",X"00",X"05",X"1D", + X"01",X"08",X"01",X"01",X"00",X"00",X"05",X"FE",X"00",X"08",X"01",X"01",X"00",X"00",X"23",X"1D", + X"01",X"08",X"0D",X"01",X"00",X"00",X"FF",X"53",X"01",X"08",X"01",X"01",X"00",X"00",X"0B",X"1D", + X"01",X"07",X"0D",X"01",X"00",X"00",X"11",X"1D",X"01",X"07",X"01",X"01",X"00",X"00",X"05",X"FE", + X"00",X"0A",X"01",X"01",X"00",X"00",X"0B",X"1D",X"01",X"07",X"01",X"01",X"00",X"00",X"0B",X"53", + X"01",X"07",X"01",X"01",X"00",X"00",X"0B",X"AC",X"01",X"07",X"01",X"01",X"00",X"00",X"0B",X"53", + X"01",X"07",X"01",X"01",X"00",X"00",X"05",X"1D",X"01",X"07",X"07",X"01",X"00",X"00",X"05",X"1D", + X"01",X"07",X"01",X"01",X"00",X"00",X"05",X"FE",X"00",X"0A",X"01",X"01",X"00",X"00",X"05",X"1D", + X"01",X"07",X"07",X"01",X"00",X"00",X"05",X"1D",X"01",X"07",X"01",X"01",X"00",X"00",X"05",X"FE", + X"00",X"0A",X"01",X"01",X"00",X"00",X"23",X"1D",X"01",X"07",X"0D",X"01",X"00",X"00",X"FF",X"FF", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/commsega.zip b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/commsega.zip new file mode 100644 index 00000000..0d92c530 Binary files /dev/null and b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/commsega.zip differ diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/make_commando_proms.bat b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/make_commando_proms.bat new file mode 100644 index 00000000..c38ac8c3 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/make_commando_proms.bat @@ -0,0 +1,15 @@ +copy /B csega1 + csega2 + csega3 + csega4 + csega5 JUNGLER.ROM +make_vhdl_prom COMMANDO.ROM cmd_prg_rom.vhd + +copy /B csega7 + csega6 gfx1.bin +make_vhdl_prom gfx1.bin cmd_chr_rom.vhd + +make_vhdl_prom gg3.bpr cmd_dot_rom.vhd + +make_vhdl_prom csega8 cmd_snd_rom.vhd + + + +make_vhdl_prom gg1.bpr cmd_pal_rom.vhd +make_vhdl_prom gg2.bpr cmd_col_rom.vhd + diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/make_vhdl_prom.exe b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/make_vhdl_prom.exe new file mode 100644 index 00000000..1e5618bf Binary files /dev/null and b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/make_vhdl_prom.exe differ diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/Jungler.qpf b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/Jungler.qpf new file mode 100644 index 00000000..998d8489 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/Jungler.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition +# Date created = 04:04:47 October 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.0" +DATE = "04:04:47 October 16, 2017" + +# Revisions + +PROJECT_REVISION = "Jungler" diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/Jungler.qsf b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/Jungler.qsf new file mode 100644 index 00000000..e60b18a7 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/Jungler.qsf @@ -0,0 +1,174 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2014 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition +# Date created = 16:37:48 September 22, 2019 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# RallyX_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP +set_global_assignment -name TOP_LEVEL_ENTITY jungler_mist + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# ------------------------- +# start ENTITY(rallyX_mist) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(rallyX_mist) +# ----------------------- +set_global_assignment -name SYSTEMVERILOG_FILE rtl/jungler_mist.sv +set_global_assignment -name VERILOG_FILE rtl/jng_top.v +set_global_assignment -name VERILOG_FILE rtl/jng_video.v +set_global_assignment -name VERILOG_FILE rtl/jng_hvgen.v +set_global_assignment -name VERILOG_FILE rtl/jng_sprite.v +set_global_assignment -name VHDL_FILE "rtl/jng_sound.vhd" +set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd +set_global_assignment -name VERILOG_FILE rtl/rams.v +set_global_assignment -name VHDL_FILE rtl/dpram.vhd +set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd +set_global_assignment -name VHDL_FILE rtl/roms/jng_prg_rom.vhd +set_global_assignment -name VHDL_FILE rtl/roms/jng_dot_rom.vhd +set_global_assignment -name VHDL_FILE rtl/roms/jng_chr_rom.vhd +set_global_assignment -name VHDL_FILE rtl/roms/jng_pal_rom.vhd +set_global_assignment -name VHDL_FILE rtl/roms/jng_col_rom.vhd +set_global_assignment -name VHDL_FILE rtl/roms/jng_snd_rom.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80s.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd +set_global_assignment -name VHDL_FILE rtl/T65/T65_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/T65/T65_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/T65/T65_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/T65/T65.vhd +set_global_assignment -name VERILOG_FILE rtl/pll.v +set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/README.txt b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/README.txt new file mode 100644 index 00000000..bcc9c29c --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/README.txt @@ -0,0 +1,18 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Jungler port to MiST +-- xx xxxx 20xx +-- From: https://github.com/MrX-8B/MiSTer-Arcade-RallyX +-- + +Todo: Sound ,GFX and some Controls + +--------------------------------------------------------------------------------- +-- FPGA New Rally-X for Spartan-3 Starter Board +------------------------------------------------ +-- Copyright (c) 2005 MiSTer-X +--------------------------------------------------------------------------------- +-- T80/T80s - Version : 0242 +----------------------------- +-- Z80 compatible microprocessor core +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) \ No newline at end of file diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/Snapshot/Jungler.rbf b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/Snapshot/Jungler.rbf new file mode 100644 index 00000000..548adfdc Binary files /dev/null and b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/Snapshot/Jungler.rbf differ diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/clean.bat b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T65/T65.vhd b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T65/T65.vhd new file mode 100644 index 00000000..09253fe0 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T65/T65.vhd @@ -0,0 +1,564 @@ +-- **** +-- T65(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 more merging +-- Ver 300 Bugfixes by ehenciak added, started tidyup *bust* +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- 65xx compatible microprocessor core +-- +-- Version : 0246 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t65/ +-- +-- Limitations : +-- +-- 65C02 and 65C816 modes are incomplete +-- Undocumented instructions are not supported +-- Some interface signals behaves incorrect +-- +-- File history : +-- +-- 0246 : First release +-- + +library IEEE; + use IEEE.std_logic_1164.all; + use IEEE.numeric_std.all; + use work.T65_Pack.all; + +-- ehenciak 2-23-2005 : Added the enable signal so that one doesn't have to use +-- the ready signal to limit the CPU. +entity T65 is + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816 + Res_n : in std_logic; + Enable : in std_logic; + Clk : in std_logic; + Rdy : in std_logic; + Abort_n : in std_logic; + IRQ_n : in std_logic; + NMI_n : in std_logic; + SO_n : in std_logic; + R_W_n : out std_logic; + Sync : out std_logic; + EF : out std_logic; + MF : out std_logic; + XF : out std_logic; + ML_n : out std_logic; + VP_n : out std_logic; + VDA : out std_logic; + VPA : out std_logic; + A : out std_logic_vector(23 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T65; + +architecture rtl of T65 is + + -- Registers + signal ABC, X, Y, D : std_logic_vector(15 downto 0); + signal P, AD, DL : std_logic_vector(7 downto 0) := x"00"; + signal BAH : std_logic_vector(7 downto 0); + signal BAL : std_logic_vector(8 downto 0); + signal PBR : std_logic_vector(7 downto 0); + signal DBR : std_logic_vector(7 downto 0); + signal PC : unsigned(15 downto 0); + signal S : unsigned(15 downto 0); + signal EF_i : std_logic; + signal MF_i : std_logic; + signal XF_i : std_logic; + + signal IR : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + + signal Mode_r : std_logic_vector(1 downto 0); + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Write_Data_r : std_logic_vector(2 downto 0); + signal Set_Addr_To_r : std_logic_vector(1 downto 0); + signal PCAdder : unsigned(8 downto 0); + + signal RstCycle : std_logic; + signal IRQCycle : std_logic; + signal NMICycle : std_logic; + + signal B_o : std_logic; + signal SO_n_o : std_logic; + signal IRQ_n_o : std_logic; + signal NMI_n_o : std_logic; + signal NMIAct : std_logic; + + signal Break : std_logic; + + -- ALU signals + signal BusA : std_logic_vector(7 downto 0); + signal BusA_r : std_logic_vector(7 downto 0); + signal BusB : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal P_Out : std_logic_vector(7 downto 0); + + -- Micro code outputs + signal LCycle : std_logic_vector(2 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(2 downto 0); + signal Set_Addr_To : std_logic_vector(1 downto 0); + signal Write_Data : std_logic_vector(2 downto 0); + signal Jump : std_logic_vector(1 downto 0); + signal BAAdd : std_logic_vector(1 downto 0); + signal BreakAtNA : std_logic; + signal ADAdd : std_logic; + signal AddY : std_logic; + signal PCAdd : std_logic; + signal Inc_S : std_logic; + signal Dec_S : std_logic; + signal LDA : std_logic; + signal LDP : std_logic; + signal LDX : std_logic; + signal LDY : std_logic; + signal LDS : std_logic; + signal LDDI : std_logic; + signal LDALU : std_logic; + signal LDAD : std_logic; + signal LDBAL : std_logic; + signal LDBAH : std_logic; + signal SaveP : std_logic; + signal Write : std_logic; + + signal really_rdy : std_logic; + signal R_W_n_i : std_logic; + +begin + -- ehenciak : gate Rdy with read/write to make an "OK, it's + -- really OK to stop the processor now if Rdy is + -- deasserted" signal + really_rdy <= Rdy or not(R_W_n_i); + + -- ehenciak : Drive R_W_n_i off chip. + R_W_n <= R_W_n_i; + + Sync <= '1' when MCycle = "000" else '0'; + EF <= EF_i; + MF <= MF_i; + XF <= XF_i; + ML_n <= '0' when IR(7 downto 6) /= "10" and IR(2 downto 1) = "11" and MCycle(2 downto 1) /= "00" else '1'; + VP_n <= '0' when IRQCycle = '1' and (MCycle = "101" or MCycle = "110") else '1'; + VDA <= '1' when Set_Addr_To_r /= "00" else '0'; -- Incorrect !!!!!!!!!!!! + VPA <= '1' when Jump(1) = '0' else '0'; -- Incorrect !!!!!!!!!!!! + + mcode : T65_MCode + port map( + Mode => Mode_r, + IR => IR, + MCycle => MCycle, + P => P, + LCycle => LCycle, + ALU_Op => ALU_Op, + Set_BusA_To => Set_BusA_To, + Set_Addr_To => Set_Addr_To, + Write_Data => Write_Data, + Jump => Jump, + BAAdd => BAAdd, + BreakAtNA => BreakAtNA, + ADAdd => ADAdd, + AddY => AddY, + PCAdd => PCAdd, + Inc_S => Inc_S, + Dec_S => Dec_S, + LDA => LDA, + LDP => LDP, + LDX => LDX, + LDY => LDY, + LDS => LDS, + LDDI => LDDI, + LDALU => LDALU, + LDAD => LDAD, + LDBAL => LDBAL, + LDBAH => LDBAH, + SaveP => SaveP, + Write => Write + ); + + alu : T65_ALU + port map( + Mode => Mode_r, + Op => ALU_Op_r, + BusA => BusA_r, + BusB => BusB, + P_In => P, + P_Out => P_Out, + Q => ALU_Q + ); + + process (Res_n, Clk) + begin + if Res_n = '0' then + PC <= (others => '0'); -- Program Counter + IR <= "00000000"; + S <= (others => '0'); -- Dummy !!!!!!!!!!!!!!!!!!!!! + D <= (others => '0'); + PBR <= (others => '0'); + DBR <= (others => '0'); + + Mode_r <= (others => '0'); + ALU_Op_r <= "1100"; + Write_Data_r <= "000"; + Set_Addr_To_r <= "00"; + + R_W_n_i <= '1'; + EF_i <= '1'; + MF_i <= '1'; + XF_i <= '1'; + + elsif Clk'event and Clk = '1' then + if (Enable = '1') then + if (really_rdy = '1') then + R_W_n_i <= not Write or RstCycle; + + D <= (others => '1'); -- Dummy + PBR <= (others => '1'); -- Dummy + DBR <= (others => '1'); -- Dummy + EF_i <= '0'; -- Dummy + MF_i <= '0'; -- Dummy + XF_i <= '0'; -- Dummy + + if MCycle = "000" then + Mode_r <= Mode; + + if IRQCycle = '0' and NMICycle = '0' then + PC <= PC + 1; + end if; + + if IRQCycle = '1' or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DI; + end if; + end if; + + ALU_Op_r <= ALU_Op; + Write_Data_r <= Write_Data; + if Break = '1' then + Set_Addr_To_r <= "00"; + else + Set_Addr_To_r <= Set_Addr_To; + end if; + + if Inc_S = '1' then + S <= S + 1; + end if; + if Dec_S = '1' and RstCycle = '0' then + S <= S - 1; + end if; + if LDS = '1' then + S(7 downto 0) <= unsigned(ALU_Q); + end if; + + if IR = "00000000" and MCycle = "001" and IRQCycle = '0' and NMICycle = '0' then + PC <= PC + 1; + end if; + -- + -- jump control logic + -- + case Jump is + when "01" => + PC <= PC + 1; + + when "10" => + PC <= unsigned(DI & DL); + + when "11" => + if PCAdder(8) = '1' then + if DL(7) = '0' then + PC(15 downto 8) <= PC(15 downto 8) + 1; + else + PC(15 downto 8) <= PC(15 downto 8) - 1; + end if; + end if; + PC(7 downto 0) <= PCAdder(7 downto 0); + + when others => null; + end case; + end if; + end if; + end if; + end process; + + PCAdder <= resize(PC(7 downto 0),9) + resize(unsigned(DL(7) & DL),9) when PCAdd = '1' + else "0" & PC(7 downto 0); + + process (Clk) + begin + if Clk'event and Clk = '1' then + if (Enable = '1') then + if (really_rdy = '1') then + if MCycle = "000" then + if LDA = '1' then + ABC(7 downto 0) <= ALU_Q; + end if; + if LDX = '1' then + X(7 downto 0) <= ALU_Q; + end if; + if LDY = '1' then + Y(7 downto 0) <= ALU_Q; + end if; + if (LDA or LDX or LDY) = '1' then + P <= P_Out; + end if; + end if; + if SaveP = '1' then + P <= P_Out; + end if; + if LDP = '1' then + P <= ALU_Q; + end if; + if IR(4 downto 0) = "11000" then + case IR(7 downto 5) is + when "000" => + P(Flag_C) <= '0'; + when "001" => + P(Flag_C) <= '1'; + when "010" => + P(Flag_I) <= '0'; + when "011" => + P(Flag_I) <= '1'; + when "101" => + P(Flag_V) <= '0'; + when "110" => + P(Flag_D) <= '0'; + when "111" => + P(Flag_D) <= '1'; + when others => + end case; + end if; + + --if IR = "00000000" and MCycle = "011" and RstCycle = '0' and NMICycle = '0' and IRQCycle = '0' then + -- P(Flag_B) <= '1'; + --end if; + --if IR = "00000000" and MCycle = "100" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1') then + -- P(Flag_I) <= '1'; + -- P(Flag_B) <= B_o; + --end if; + + -- B=1 always on the 6502 + P(Flag_B) <= '1'; + if IR = "00000000" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1') then + if MCycle = "011" then + -- B=0 in *copy* of P pushed onto the stack + P(Flag_B) <= '0'; + elsif MCycle = "100" then + P(Flag_I) <= '1'; + end if; + end if; + + if SO_n_o = '1' and SO_n = '0' then + P(Flag_V) <= '1'; + end if; + if RstCycle = '1' and Mode_r /= "00" then + P(Flag_1) <= '1'; + P(Flag_D) <= '0'; + P(Flag_I) <= '1'; + end if; + P(Flag_1) <= '1'; + + B_o <= P(Flag_B); + SO_n_o <= SO_n; + IRQ_n_o <= IRQ_n; + NMI_n_o <= NMI_n; + end if; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + + process (Res_n, Clk) + begin + if Res_n = '0' then + BusA_r <= (others => '0'); + BusB <= (others => '0'); + AD <= (others => '0'); + BAL <= (others => '0'); + BAH <= (others => '0'); + DL <= (others => '0'); + elsif Clk'event and Clk = '1' then + if (Enable = '1') then + if (Rdy = '1') then + BusA_r <= BusA; + BusB <= DI; + + case BAAdd is + when "01" => + -- BA Inc + AD <= std_logic_vector(unsigned(AD) + 1); + BAL <= std_logic_vector(unsigned(BAL) + 1); + when "10" => + -- BA Add + BAL <= std_logic_vector(resize(unsigned(BAL(7 downto 0)),9) + resize(unsigned(BusA),9)); + when "11" => + -- BA Adj + if BAL(8) = '1' then + BAH <= std_logic_vector(unsigned(BAH) + 1); + end if; + when others => + end case; + + -- ehenciak : modified to use Y register as well (bugfix) + if ADAdd = '1' then + if (AddY = '1') then + AD <= std_logic_vector(unsigned(AD) + unsigned(Y(7 downto 0))); + else + AD <= std_logic_vector(unsigned(AD) + unsigned(X(7 downto 0))); + end if; + end if; + + if IR = "00000000" then + BAL <= (others => '1'); + BAH <= (others => '1'); + if RstCycle = '1' then + BAL(2 downto 0) <= "100"; + elsif NMICycle = '1' then + BAL(2 downto 0) <= "010"; + else + BAL(2 downto 0) <= "110"; + end if; + if Set_addr_To_r = "11" then + BAL(0) <= '1'; + end if; + end if; + + + if LDDI = '1' then + DL <= DI; + end if; + if LDALU = '1' then + DL <= ALU_Q; + end if; + if LDAD = '1' then + AD <= DI; + end if; + if LDBAL = '1' then + BAL(7 downto 0) <= DI; + end if; + if LDBAH = '1' then + BAH <= DI; + end if; + end if; + end if; + end if; + end process; + + Break <= (BreakAtNA and not BAL(8)) or (PCAdd and not PCAdder(8)); + + + with Set_BusA_To select + BusA <= DI when "000", + ABC(7 downto 0) when "001", + X(7 downto 0) when "010", + Y(7 downto 0) when "011", + std_logic_vector(S(7 downto 0)) when "100", + P when "101", + (others => '-') when others; + + with Set_Addr_To_r select + A <= "0000000000000001" & std_logic_vector(S(7 downto 0)) when "01", + DBR & "00000000" & AD when "10", + "00000000" & BAH & BAL(7 downto 0) when "11", + PBR & std_logic_vector(PC(15 downto 8)) & std_logic_vector(PCAdder(7 downto 0)) when others; + + with Write_Data_r select + DO <= DL when "000", + ABC(7 downto 0) when "001", + X(7 downto 0) when "010", + Y(7 downto 0) when "011", + std_logic_vector(S(7 downto 0)) when "100", + P when "101", + std_logic_vector(PC(7 downto 0)) when "110", + std_logic_vector(PC(15 downto 8)) when others; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + + process (Res_n, Clk) + begin + if Res_n = '0' then + MCycle <= "001"; + RstCycle <= '1'; + IRQCycle <= '0'; + NMICycle <= '0'; + NMIAct <= '0'; + elsif Clk'event and Clk = '1' then + if (Enable = '1') then + if (really_rdy = '1') then + if MCycle = LCycle or Break = '1' then + MCycle <= "000"; + RstCycle <= '0'; + IRQCycle <= '0'; + NMICycle <= '0'; + if NMIAct = '1' then + NMICycle <= '1'; + elsif IRQ_n_o = '0' and P(Flag_I) = '0' then + IRQCycle <= '1'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + + if NMICycle = '1' then + NMIAct <= '0'; + end if; + if NMI_n_o = '1' and NMI_n = '0' then + NMIAct <= '1'; + end if; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T65/T65_ALU.vhd b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T65/T65_ALU.vhd new file mode 100644 index 00000000..b1f6d632 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T65/T65_ALU.vhd @@ -0,0 +1,260 @@ +-- **** +-- T65(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 Bugfixes by ehenciak added +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- 6502 compatible microprocessor core +-- +-- Version : 0245 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t65/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0245 : First version +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T65_Pack.all; + +entity T65_ALU is + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816 + Op : in std_logic_vector(3 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + P_In : in std_logic_vector(7 downto 0); + P_Out : out std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0) + ); +end T65_ALU; + +architecture rtl of T65_ALU is + + -- AddSub variables (temporary signals) + signal ADC_Z : std_logic; + signal ADC_C : std_logic; + signal ADC_V : std_logic; + signal ADC_N : std_logic; + signal ADC_Q : std_logic_vector(7 downto 0); + signal SBC_Z : std_logic; + signal SBC_C : std_logic; + signal SBC_V : std_logic; + signal SBC_N : std_logic; + signal SBC_Q : std_logic_vector(7 downto 0); + +begin + + process (P_In, BusA, BusB) + variable AL : unsigned(6 downto 0); + variable AH : unsigned(6 downto 0); + variable C : std_logic; + begin + AL := resize(unsigned(BusA(3 downto 0) & P_In(Flag_C)), 7) + resize(unsigned(BusB(3 downto 0) & "1"), 7); + AH := resize(unsigned(BusA(7 downto 4) & AL(5)), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7); + +-- pragma translate_off + if is_x(std_logic_vector(AL)) then AL := "0000000"; end if; + if is_x(std_logic_vector(AH)) then AH := "0000000"; end if; +-- pragma translate_on + + if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then + ADC_Z <= '1'; + else + ADC_Z <= '0'; + end if; + + if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' then + AL(6 downto 1) := AL(6 downto 1) + 6; + end if; + + C := AL(6) or AL(5); + AH := resize(unsigned(BusA(7 downto 4) & C), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7); + + ADC_N <= AH(4); + ADC_V <= (AH(4) xor BusA(7)) and not (BusA(7) xor BusB(7)); + +-- pragma translate_off + if is_x(std_logic_vector(AH)) then AH := "0000000"; end if; +-- pragma translate_on + + if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' then + AH(6 downto 1) := AH(6 downto 1) + 6; + end if; + + ADC_C <= AH(6) or AH(5); + + ADC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1)); + end process; + + process (Op, P_In, BusA, BusB) + variable AL : unsigned(6 downto 0); + variable AH : unsigned(5 downto 0); + variable C : std_logic; + begin + C := P_In(Flag_C) or not Op(0); + AL := resize(unsigned(BusA(3 downto 0) & C), 7) - resize(unsigned(BusB(3 downto 0) & "1"), 6); + AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(5)), 6); + +-- pragma translate_off + if is_x(std_logic_vector(AL)) then AL := "0000000"; end if; + if is_x(std_logic_vector(AH)) then AH := "000000"; end if; +-- pragma translate_on + + if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then + SBC_Z <= '1'; + else + SBC_Z <= '0'; + end if; + + SBC_C <= not AH(5); + SBC_V <= (AH(4) xor BusA(7)) and (BusA(7) xor BusB(7)); + SBC_N <= AH(4); + + if P_In(Flag_D) = '1' then + if AL(5) = '1' then + AL(5 downto 1) := AL(5 downto 1) - 6; + end if; + AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(6)), 6); + if AH(5) = '1' then + AH(5 downto 1) := AH(5 downto 1) - 6; + end if; + end if; + + SBC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1)); + end process; + + process (Op, P_In, BusA, BusB, + ADC_Z, ADC_C, ADC_V, ADC_N, ADC_Q, + SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q) + variable Q_t : std_logic_vector(7 downto 0); + begin + -- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC + -- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC + P_Out <= P_In; + Q_t := BusA; + case Op(3 downto 0) is + when "0000" => + -- ORA + Q_t := BusA or BusB; + when "0001" => + -- AND + Q_t := BusA and BusB; + when "0010" => + -- EOR + Q_t := BusA xor BusB; + when "0011" => + -- ADC + P_Out(Flag_V) <= ADC_V; + P_Out(Flag_C) <= ADC_C; + Q_t := ADC_Q; + when "0101" | "1101" => + -- LDA + when "0110" => + -- CMP + P_Out(Flag_C) <= SBC_C; + when "0111" => + -- SBC + P_Out(Flag_V) <= SBC_V; + P_Out(Flag_C) <= SBC_C; + Q_t := SBC_Q; + when "1000" => + -- ASL + Q_t := BusA(6 downto 0) & "0"; + P_Out(Flag_C) <= BusA(7); + when "1001" => + -- ROL + Q_t := BusA(6 downto 0) & P_In(Flag_C); + P_Out(Flag_C) <= BusA(7); + when "1010" => + -- LSR + Q_t := "0" & BusA(7 downto 1); + P_Out(Flag_C) <= BusA(0); + when "1011" => + -- ROR + Q_t := P_In(Flag_C) & BusA(7 downto 1); + P_Out(Flag_C) <= BusA(0); + when "1100" => + -- BIT + P_Out(Flag_V) <= BusB(6); + when "1110" => + -- DEC + Q_t := std_logic_vector(unsigned(BusA) - 1); + when "1111" => + -- INC + Q_t := std_logic_vector(unsigned(BusA) + 1); + when others => + end case; + + case Op(3 downto 0) is + when "0011" => + P_Out(Flag_N) <= ADC_N; + P_Out(Flag_Z) <= ADC_Z; + when "0110" | "0111" => + P_Out(Flag_N) <= SBC_N; + P_Out(Flag_Z) <= SBC_Z; + when "0100" => + when "1100" => + P_Out(Flag_N) <= BusB(7); + if (BusA and BusB) = "00000000" then + P_Out(Flag_Z) <= '1'; + else + P_Out(Flag_Z) <= '0'; + end if; + when others => + P_Out(Flag_N) <= Q_t(7); + if Q_t = "00000000" then + P_Out(Flag_Z) <= '1'; + else + P_Out(Flag_Z) <= '0'; + end if; + end case; + + Q <= Q_t; + end process; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T65/T65_MCode.vhd b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T65/T65_MCode.vhd new file mode 100644 index 00000000..6c6c864a --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T65/T65_MCode.vhd @@ -0,0 +1,1052 @@ +-- **** +-- T65(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 302 minor timing fixes +-- Ver 301 Jump timing fixed +-- Ver 300 Bugfixes by ehenciak added +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- 65xx compatible microprocessor core +-- +-- Version : 0246 + fix +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t65/ +-- +-- Limitations : +-- +-- 65C02 +-- supported : inc, dec, phx, plx, phy, ply +-- missing : bra, ora, lda, cmp, sbc, tsb*2, trb*2, stz*2, bit*2, wai, stp, jmp, bbr*8, bbs*8 +-- +-- File history : +-- +-- 0246 : First release +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T65_Pack.all; + +entity T65_MCode is + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816 + IR : in std_logic_vector(7 downto 0); + MCycle : in std_logic_vector(2 downto 0); + P : in std_logic_vector(7 downto 0); + LCycle : out std_logic_vector(2 downto 0); + ALU_Op : out std_logic_vector(3 downto 0); + Set_BusA_To : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P + Set_Addr_To : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA + Write_Data : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH + Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel + BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj + BreakAtNA : out std_logic; + ADAdd : out std_logic; + AddY : out std_logic; + PCAdd : out std_logic; + Inc_S : out std_logic; + Dec_S : out std_logic; + LDA : out std_logic; + LDP : out std_logic; + LDX : out std_logic; + LDY : out std_logic; + LDS : out std_logic; + LDDI : out std_logic; + LDALU : out std_logic; + LDAD : out std_logic; + LDBAL : out std_logic; + LDBAH : out std_logic; + SaveP : out std_logic; + Write : out std_logic + ); +end T65_MCode; + +architecture rtl of T65_MCode is + + signal Branch : std_logic; + +begin + + with IR(7 downto 5) select + Branch <= not P(Flag_N) when "000", + P(Flag_N) when "001", + not P(Flag_V) when "010", + P(Flag_V) when "011", + not P(Flag_C) when "100", + P(Flag_C) when "101", + not P(Flag_Z) when "110", + P(Flag_Z) when others; + + process (IR, MCycle, P, Branch, Mode) + begin + LCycle <= "001"; + Set_BusA_To <= "001"; -- A + Set_Addr_To <= (others => '0'); + Write_Data <= (others => '0'); + Jump <= (others => '0'); + BAAdd <= "00"; + BreakAtNA <= '0'; + ADAdd <= '0'; + PCAdd <= '0'; + Inc_S <= '0'; + Dec_S <= '0'; + LDA <= '0'; + LDP <= '0'; + LDX <= '0'; + LDY <= '0'; + LDS <= '0'; + LDDI <= '0'; + LDALU <= '0'; + LDAD <= '0'; + LDBAL <= '0'; + LDBAH <= '0'; + SaveP <= '0'; + Write <= '0'; + AddY <= '0'; + + case IR(7 downto 5) is + when "100" => + --{{{ + case IR(1 downto 0) is + when "00" => + Set_BusA_To <= "011"; -- Y + Write_Data <= "011"; -- Y + when "10" => + Set_BusA_To <= "010"; -- X + Write_Data <= "010"; -- X + when others => + Write_Data <= "001"; -- A + end case; + --}}} + when "101" => + --{{{ + case IR(1 downto 0) is + when "00" => + if IR(4) /= '1' or IR(2) /= '0' then + LDY <= '1'; + end if; + when "10" => + LDX <= '1'; + when others => + LDA <= '1'; + end case; + Set_BusA_To <= "000"; -- DI + --}}} + when "110" => + --{{{ + case IR(1 downto 0) is + when "00" => + if IR(4) = '0' then + LDY <= '1'; + end if; + Set_BusA_To <= "011"; -- Y + when others => + Set_BusA_To <= "001"; -- A + end case; + --}}} + when "111" => + --{{{ + case IR(1 downto 0) is + when "00" => + if IR(4) = '0' then + LDX <= '1'; + end if; + Set_BusA_To <= "010"; -- X + when others => + Set_BusA_To <= "001"; -- A + end case; + --}}} + when others => + end case; + + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + Set_BusA_To <= "000"; -- DI + end if; + + case IR(4 downto 0) is + when "00000" | "01000" | "01010" | "11000" | "11010" => + --{{{ + -- Implied + case IR is + when "00000000" => + -- BRK + LCycle <= "110"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= "01"; -- S + Write_Data <= "111"; -- PCH + Write <= '1'; + when 2 => + Dec_S <= '1'; + Set_Addr_To <= "01"; -- S + Write_Data <= "110"; -- PCL + Write <= '1'; + when 3 => + Dec_S <= '1'; + Set_Addr_To <= "01"; -- S + Write_Data <= "101"; -- P + Write <= '1'; + when 4 => + Dec_S <= '1'; + Set_Addr_To <= "11"; -- BA + when 5 => + LDDI <= '1'; + Set_Addr_To <= "11"; -- BA + when 6 => + Jump <= "10"; -- DIDL + when others => + end case; + when "00100000" => + -- JSR + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDDI <= '1'; + Set_Addr_To <= "01"; -- S + when 2 => + Set_Addr_To <= "01"; -- S + Write_Data <= "111"; -- PCH + Write <= '1'; + when 3 => + Dec_S <= '1'; + Set_Addr_To <= "01"; -- S + Write_Data <= "110"; -- PCL + Write <= '1'; + when 4 => + Dec_S <= '1'; + when 5 => + Jump <= "10"; -- DIDL + when others => + end case; + when "01000000" => + -- RTI + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= "01"; -- S + when 2 => + Inc_S <= '1'; + Set_Addr_To <= "01"; -- S + when 3 => + Inc_S <= '1'; + Set_Addr_To <= "01"; -- S + Set_BusA_To <= "000"; -- DI + when 4 => + LDP <= '1'; + Inc_S <= '1'; + LDDI <= '1'; + Set_Addr_To <= "01"; -- S + when 5 => + Jump <= "10"; -- DIDL + when others => + end case; + when "01100000" => + -- RTS + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= "01"; -- S + when 2 => + Inc_S <= '1'; + Set_Addr_To <= "01"; -- S + when 3 => + Inc_S <= '1'; + LDDI <= '1'; + Set_Addr_To <= "01"; -- S + when 4 => + Jump <= "10"; -- DIDL + when 5 => + Jump <= "01"; + when others => + end case; + when "00001000" | "01001000" | "01011010" | "11011010" => + -- PHP, PHA, PHY*, PHX* + LCycle <= "010"; + if Mode = "00" and IR(1) = '1' then + LCycle <= "001"; + end if; + case to_integer(unsigned(MCycle)) is + when 1 => + case IR(7 downto 4) is + when "0000" => + Write_Data <= "101"; -- P + when "0100" => + Write_Data <= "001"; -- A + when "0101" => + Write_Data <= "011"; -- Y + when "1101" => + Write_Data <= "010"; -- X + when others => + end case; + Write <= '1'; + Set_Addr_To <= "01"; -- S + when 2 => + Dec_S <= '1'; + when others => + end case; + when "00101000" | "01101000" | "01111010" | "11111010" => + -- PLP, PLA, PLY*, PLX* + LCycle <= "011"; + if Mode = "00" and IR(1) = '1' then + LCycle <= "001"; + end if; + case IR(7 downto 4) is + when "0010" => + LDP <= '1'; + when "0110" => + LDA <= '1'; + when "0111" => + if Mode /= "00" then + LDY <= '1'; + end if; + when "1111" => + if Mode /= "00" then + LDX <= '1'; + end if; + when others => + end case; + case to_integer(unsigned(MCycle)) is + when 0 => + SaveP <= '1'; + when 1 => + Set_Addr_To <= "01"; -- S + when 2 => + Inc_S <= '1'; + Set_Addr_To <= "01"; -- S + when 3 => + Set_BusA_To <= "000"; -- DI + when others => + end case; + when "10100000" | "11000000" | "11100000" => + -- LDY, CPY, CPX + -- Immediate + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + when others => + end case; + when "10001000" => + -- DEY + LDY <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "011"; -- Y + when others => + end case; + when "11001010" => + -- DEX + LDX <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "010"; -- X + when others => + end case; + when "00011010" | "00111010" => + -- INC*, DEC* + if Mode /= "00" then + LDA <= '1'; -- A + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "100"; -- S + when others => + end case; + when "00001010" | "00101010" | "01001010" | "01101010" => + -- ASL, ROL, LSR, ROR + LDA <= '1'; -- A + Set_BusA_To <= "001"; -- A + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + when others => + end case; + when "10001010" | "10011000" => + -- TYA, TXA + LDA <= '1'; -- A + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + when others => + end case; + when "10101010" | "10101000" => + -- TAX, TAY + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "001"; -- A + when others => + end case; + when "10011010" => + -- TXS + case to_integer(unsigned(MCycle)) is + when 0 => + LDS <= '1'; + when 1 => + when others => + end case; + when "10111010" => + -- TSX + LDX <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "100"; -- S + when others => + end case; + + -- when "00011000" | "00111000" | "01011000" | "01111000" | "10111000" | "11011000" | "11111000" | "11001000" | "11101000" => + -- -- CLC, SEC, CLI, SEI, CLV, CLD, SED, INY, INX + -- case to_integer(unsigned(MCycle)) is + -- when 1 => + -- when others => + -- end case; + when others => + case to_integer(unsigned(MCycle)) is + when 0 => + when others => + end case; + end case; + --}}} + + when "00001" | "00011" => + --{{{ + -- Zero Page Indexed Indirect (d,x) + LCycle <= "101"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + ADAdd <= '1'; + Set_Addr_To <= "10"; -- AD + when 3 => + BAAdd <= "01"; -- DB Inc + LDBAL <= '1'; + Set_Addr_To <= "10"; -- AD + when 4 => + LDBAH <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 5 => + when others => + end case; + --}}} + + when "01001" | "01011" => + --{{{ + -- Immediate + LDA <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + when others => + end case; + + --}}} + + when "00010" | "10010" => + --{{{ + -- Immediate, KIL + LDX <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + if IR = "10100010" then + -- LDX + Jump <= "01"; + else + -- KIL !!!!!!!!!!!!!!!!!!!!!!!!!!!!! + end if; + when others => + end case; + --}}} + + when "00100" => + --{{{ + -- Zero Page + LCycle <= "010"; + case to_integer(unsigned(MCycle)) is + when 0 => + if IR(7 downto 5) = "001" then + SaveP <= '1'; + end if; + when 1 => + Jump <= "01"; + LDAD <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "10"; -- AD + when 2 => + when others => + end case; + --}}} + + when "00101" | "00110" | "00111" => + --{{{ + -- Zero Page + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + -- Read-Modify-Write + LCycle <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + LDDI <= '1'; + Write <= '1'; + Set_Addr_To <= "10"; -- AD + when 3 => + LDALU <= '1'; + SaveP <= '1'; + Write <= '1'; + Set_Addr_To <= "10"; -- AD + when 4 => + when others => + end case; + else + LCycle <= "010"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDAD <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "10"; -- AD + when 2 => + when others => + end case; + end if; + --}}} + + when "01100" => + --{{{ + -- Absolute + if IR(7 downto 6) = "01" and IR(4 downto 0) = "01100" then + -- JMP + if IR(5) = '0' then + --LCycle <= "011"; + LCycle <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDDI <= '1'; + when 2 => + Jump <= "10"; -- DIDL + when others => + end case; + else + --LCycle <= "101"; + LCycle <= "100"; -- mikej + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDDI <= '1'; + LDBAL <= '1'; + when 2 => + LDBAH <= '1'; + if Mode /= "00" then + Jump <= "10"; -- DIDL + end if; + if Mode = "00" then + Set_Addr_To <= "11"; -- BA + end if; + when 3 => + LDDI <= '1'; + if Mode = "00" then + Set_Addr_To <= "11"; -- BA + BAAdd <= "01"; -- DB Inc + else + Jump <= "01"; + end if; + when 4 => + Jump <= "10"; -- DIDL + when others => + end case; + end if; + else + LCycle <= "011"; + case to_integer(unsigned(MCycle)) is + when 0 => + if IR(7 downto 5) = "001" then + SaveP <= '1'; + end if; + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + LDBAH <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 3 => + when others => + end case; + end if; + --}}} + + when "01101" | "01110" | "01111" => + --{{{ + -- Absolute + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + -- Read-Modify-Write + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 3 => + LDDI <= '1'; + Write <= '1'; + Set_Addr_To <= "11"; -- BA + when 4 => + Write <= '1'; + LDALU <= '1'; + SaveP <= '1'; + Set_Addr_To <= "11"; -- BA + when 5 => + SaveP <= '0'; -- MIKEJ was 1 + when others => + end case; + else + LCycle <= "011"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + LDBAH <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 3 => + when others => + end case; + end if; + --}}} + + when "10000" => + --{{{ + -- Relative + + -- This circuit dictates when the last + -- microcycle occurs for the branch depending on + -- whether or not the branch is taken and if a page + -- is crossed... + if (Branch = '1') then + + LCycle <= "011"; -- We're done @ T3 if branching...upper + -- level logic will stop at T2 if no page cross + -- (See the Break signal) + else + + LCycle <= "001"; + + end if; + + -- This decodes the current microcycle and takes the + -- proper course of action... + case to_integer(unsigned(MCycle)) is + + -- On the T1 microcycle, increment the program counter + -- and instruct the upper level logic to fetch the offset + -- from the Din bus and store it in the data latches. This + -- will be the last microcycle if the branch isn't taken. + when 1 => + + Jump <= "01"; -- Increments the PC by one (PC will now be PC+2) + -- from microcycle T0. + + LDDI <= '1'; -- Tells logic in top level (T65.vhd) to route + -- the Din bus to the memory data latch (DL) + -- so that the branch offset is fetched. + + -- In microcycle T2, tell the logic in the top level to + -- add the offset. If the most significant byte of the + -- program counter (i.e. the current "page") does not need + -- updating, we are done here...the Break signal at the + -- T65.vhd level takes care of that... + when 2 => + + Jump <= "11"; -- Tell the PC Jump logic to use relative mode. + + PCAdd <= '1'; -- This tells the PC adder to update itself with + -- the current offset recently fetched from + -- memory. + + -- The following is microcycle T3 : + -- The program counter should be completely updated + -- on this cycle after the page cross is detected. + -- We don't need to do anything here... + when 3 => + + + when others => null; -- Do nothing. + + end case; + --}}} + + when "10001" | "10011" => + --{{{ + -- Zero Page Indirect Indexed (d),y + LCycle <= "101"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + LDBAL <= '1'; + BAAdd <= "01"; -- DB Inc + Set_Addr_To <= "10"; -- AD + when 3 => + Set_BusA_To <= "011"; -- Y + BAAdd <= "10"; -- BA Add + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 4 => + BAAdd <= "11"; -- BA Adj + if IR(7 downto 5) = "100" then + Write <= '1'; + else + BreakAtNA <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 5 => + when others => + end case; + --}}} + + when "10100" | "10101" | "10110" | "10111" => + --{{{ + -- Zero Page, X + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + -- Read-Modify-Write + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + ADAdd <= '1'; + Set_Addr_To <= "10"; -- AD + when 3 => + LDDI <= '1'; + Write <= '1'; + Set_Addr_To <= "10"; -- AD + when 4 => + LDALU <= '1'; + SaveP <= '1'; + Write <= '1'; + Set_Addr_To <= "10"; -- AD + when 5 => + when others => + end case; + else + LCycle <= "011"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + ADAdd <= '1'; + -- Added this check for Y reg. use... + if (IR(3 downto 0) = "0110") then + AddY <= '1'; + end if; + + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "10"; -- AD + when 3 => null; + when others => + end case; + end if; + --}}} + + when "11001" | "11011" => + --{{{ + -- Absolute Y + LCycle <= "100"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + Set_BusA_To <= "011"; -- Y + BAAdd <= "10"; -- BA Add + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 3 => + BAAdd <= "11"; -- BA adj + if IR(7 downto 5) = "100" then + Write <= '1'; + else + BreakAtNA <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 4 => + when others => + end case; + --}}} + + when "11100" | "11101" | "11110" | "11111" => + --{{{ + -- Absolute X + + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + -- Read-Modify-Write + LCycle <= "110"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + Set_BusA_To <= "010"; -- X + BAAdd <= "10"; -- BA Add + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 3 => + BAAdd <= "11"; -- BA adj + Set_Addr_To <= "11"; -- BA + when 4 => + LDDI <= '1'; + Write <= '1'; + Set_Addr_To <= "11"; -- BA + when 5 => + LDALU <= '1'; + SaveP <= '1'; + Write <= '1'; + Set_Addr_To <= "11"; -- BA + when 6 => + when others => + end case; + else + LCycle <= "100"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + -- mikej + -- special case 0xBE which uses Y reg as index!! + if (IR = "10111110") then + Set_BusA_To <= "011"; -- Y + else + Set_BusA_To <= "010"; -- X + end if; + BAAdd <= "10"; -- BA Add + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 3 => + BAAdd <= "11"; -- BA adj + if IR(7 downto 5) = "100" then + Write <= '1'; + else + BreakAtNA <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 4 => + when others => + end case; + end if; + --}}} + when others => + end case; + end process; + + process (IR, MCycle) + begin + -- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC + -- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC + case IR(1 downto 0) is + when "00" => + --{{{ + case IR(4 downto 2) is + when "000" | "001" | "011" => + case IR(7 downto 5) is + when "110" | "111" => + -- CP + ALU_Op <= "0110"; + when "101" => + -- LD + ALU_Op <= "0101"; + when "001" => + -- BIT + ALU_Op <= "1100"; + when others => + -- NOP/ST + ALU_Op <= "0100"; + end case; + when "010" => + case IR(7 downto 5) is + when "111" | "110" => + -- IN + ALU_Op <= "1111"; + when "100" => + -- DEY + ALU_Op <= "1110"; + when others => + -- LD + ALU_Op <= "1101"; + end case; + when "110" => + case IR(7 downto 5) is + when "100" => + -- TYA + ALU_Op <= "1101"; + when others => + ALU_Op <= "----"; + end case; + when others => + case IR(7 downto 5) is + when "101" => + -- LD + ALU_Op <= "1101"; + when others => + ALU_Op <= "0100"; + end case; + end case; + --}}} + when "01" => -- OR + --{{{ + ALU_Op(3) <= '0'; + ALU_Op(2 downto 0) <= IR(7 downto 5); + --}}} + when "10" => + --{{{ + ALU_Op(3) <= '1'; + ALU_Op(2 downto 0) <= IR(7 downto 5); + case IR(7 downto 5) is + when "000" => + if IR(4 downto 2) = "110" then + -- INC + ALU_Op <= "1111"; + end if; + when "001" => + if IR(4 downto 2) = "110" then + -- DEC + ALU_Op <= "1110"; + end if; + when "100" => + if IR(4 downto 2) = "010" then + -- TXA + ALU_Op <= "0101"; + else + ALU_Op <= "0100"; + end if; + when others => + end case; + --}}} + when others => + --{{{ + case IR(7 downto 5) is + when "100" => + ALU_Op <= "0100"; + when others => + if MCycle = "000" then + ALU_Op(3) <= '0'; + ALU_Op(2 downto 0) <= IR(7 downto 5); + else + ALU_Op(3) <= '1'; + ALU_Op(2 downto 0) <= IR(7 downto 5); + end if; + end case; + --}}} + end case; + end process; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T65/T65_Pack.vhd b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T65/T65_Pack.vhd new file mode 100644 index 00000000..e025e1bf --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T65/T65_Pack.vhd @@ -0,0 +1,117 @@ +-- **** +-- T65(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 Bugfixes by ehenciak added +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- 65xx compatible microprocessor core +-- +-- Version : 0246 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t65/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T65_Pack is + + constant Flag_C : integer := 0; + constant Flag_Z : integer := 1; + constant Flag_I : integer := 2; + constant Flag_D : integer := 3; + constant Flag_B : integer := 4; + constant Flag_1 : integer := 5; + constant Flag_V : integer := 6; + constant Flag_N : integer := 7; + + component T65_MCode + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816 + IR : in std_logic_vector(7 downto 0); + MCycle : in std_logic_vector(2 downto 0); + P : in std_logic_vector(7 downto 0); + LCycle : out std_logic_vector(2 downto 0); + ALU_Op : out std_logic_vector(3 downto 0); + Set_BusA_To : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P + Set_Addr_To : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA + Write_Data : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH + Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel + BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj + BreakAtNA : out std_logic; + ADAdd : out std_logic; + AddY : out std_logic; + PCAdd : out std_logic; + Inc_S : out std_logic; + Dec_S : out std_logic; + LDA : out std_logic; + LDP : out std_logic; + LDX : out std_logic; + LDY : out std_logic; + LDS : out std_logic; + LDDI : out std_logic; + LDALU : out std_logic; + LDAD : out std_logic; + LDBAL : out std_logic; + LDBAH : out std_logic; + SaveP : out std_logic; + Write : out std_logic + ); + end component; + + component T65_ALU + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816 + Op : in std_logic_vector(3 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + P_In : in std_logic_vector(7 downto 0); + P_Out : out std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T80/T80.vhd new file mode 100644 index 00000000..398fa0df --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T80/T80.vhd @@ -0,0 +1,1073 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 and Auto_Wait_t1 = '0' then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if T_Res = '1' then + Auto_Wait_t1 <= '0'; + else + Auto_Wait_t1 <= Auto_Wait or IORQ_i; + end if; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if (Auto_Wait = '1' and Auto_Wait_t2 = '0') nor + (IOWait = 1 and IORQ_i = '1' and Auto_Wait_t1 = '0') then + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T80/T80_ALU.vhd new file mode 100644 index 00000000..86fddce7 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T80/T80_ALU.vhd @@ -0,0 +1,351 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + OverFlow_v <= Carry_v xor Carry7_v; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T80/T80_MCode.vhd new file mode 100644 index 00000000..4cc30f35 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T80/T80_MCode.vhd @@ -0,0 +1,1934 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; +-- constant aNone : std_logic_vector(2 downto 0) := "000"; +-- constant aXY : std_logic_vector(2 downto 0) := "001"; +-- constant aIOA : std_logic_vector(2 downto 0) := "010"; +-- constant aSP : std_logic_vector(2 downto 0) := "011"; +-- constant aBC : std_logic_vector(2 downto 0) := "100"; +-- constant aDE : std_logic_vector(2 downto 0) := "101"; +-- constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0010"; + else + IncDec_16 <= "1010"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0010"; + else + IncDec_16 <= "1010"; + end if; + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T80/T80_Pack.vhd new file mode 100644 index 00000000..ac7d34da --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T80/T80_Pack.vhd @@ -0,0 +1,208 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T80/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T80/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T80/T80s.vhd b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T80/T80s.vhd new file mode 100644 index 00000000..5b612110 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T80/T80s.vhd @@ -0,0 +1,190 @@ +-- +-- Z80 compatible microprocessor core, synchronous top level +-- Different timing than the original z80 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed read with wait +-- +-- 0211 : Fixed interrupt cycle +-- +-- 0235 : Updated for T80 interface change +-- +-- 0236 : Added T2Write generic +-- +-- 0237 : Fixed T2Write with wait state +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80s is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2 + IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80s; + +architecture rtl of T80s is + + signal CEN : std_logic; + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + CEN <= '1'; + + u0 : T80 + generic map( + Mode => Mode, + IOWait => IOWait) + port map( + CEN => CEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if T2Write = 0 then + if TState = "010" and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + else + if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end process; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/YM2149_linmix_sep.vhd b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/YM2149_linmix_sep.vhd new file mode 100644 index 00000000..6ed2498a --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/YM2149_linmix_sep.vhd @@ -0,0 +1,574 @@ +-- changes for seperate audio outputs and enable now enables cpu access as well +-- +-- A simulation model of YM2149 (AY-3-8910 with bells on) + +-- Copyright (c) MikeJ - Jan 2005 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- +-- Clues from MAME sound driver and Kazuhiro TSUJIKAWA +-- +-- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V) +-- vol 15 .. 0 +-- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132 +-- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order +-- to produced all the required values. +-- (The first part of the curve is a bit steeper and the last bit is more linear than expected) +-- +-- NOTE, this component uses LINEAR mixing of the three analogue channels, and is only +-- accurate for designs where the outputs are buffered and not simply wired together. +-- The ouput level is more complex in that case and requires a larger table. + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity YM2149 is + port ( + -- data bus + I_DA : in std_logic_vector(7 downto 0); + O_DA : out std_logic_vector(7 downto 0); + O_DA_OE_L : out std_logic; + -- control + I_A9_L : in std_logic; + I_A8 : in std_logic; + I_BDIR : in std_logic; + I_BC2 : in std_logic; + I_BC1 : in std_logic; + I_SEL_L : in std_logic; + + O_AUDIO : out std_logic_vector(7 downto 0); + O_CHAN : out std_logic_vector(1 downto 0); + -- port a + I_IOA : in std_logic_vector(7 downto 0); + O_IOA : out std_logic_vector(7 downto 0); + O_IOA_OE_L : out std_logic; + -- port b + I_IOB : in std_logic_vector(7 downto 0); + O_IOB : out std_logic_vector(7 downto 0); + O_IOB_OE_L : out std_logic; + + ENA : in std_logic; -- clock enable for higher speed operation + RESET_L : in std_logic; + CLK : in std_logic -- note 6 Mhz + ); +end; + +architecture RTL of YM2149 is + type array_16x8 is array (0 to 15) of std_logic_vector( 7 downto 0); + type array_3x12 is array (1 to 3) of std_logic_vector(11 downto 0); + + signal cnt_div : std_logic_vector(3 downto 0) := (others => '0'); + signal cnt_div_t1 : std_logic_vector(3 downto 0); + signal noise_div : std_logic := '0'; + signal ena_div : std_logic; + signal ena_div_noise : std_logic; + signal poly17 : std_logic_vector(16 downto 0) := (others => '0'); + + -- registers + signal addr : std_logic_vector(7 downto 0); + signal busctrl_addr : std_logic; + signal busctrl_we : std_logic; + signal busctrl_re : std_logic; + + signal reg : array_16x8; + signal env_reset : std_logic; + signal ioa_inreg : std_logic_vector(7 downto 0); + signal iob_inreg : std_logic_vector(7 downto 0); + + signal noise_gen_cnt : std_logic_vector(4 downto 0); + signal noise_gen_op : std_logic; + signal tone_gen_cnt : array_3x12 := (others => (others => '0')); + signal tone_gen_op : std_logic_vector(3 downto 1) := "000"; + + signal env_gen_cnt : std_logic_vector(15 downto 0); + signal env_ena : std_logic; + signal env_hold : std_logic; + signal env_inc : std_logic; + signal env_vol : std_logic_vector(4 downto 0); + + signal tone_ena_l : std_logic; + signal tone_src : std_logic; + signal noise_ena_l : std_logic; + signal chan_vol : std_logic_vector(4 downto 0); + + signal dac_amp : std_logic_vector(7 downto 0); +begin + -- cpu i/f + p_busdecode : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8) + variable cs : std_logic; + variable sel : std_logic_vector(2 downto 0); + begin + -- BDIR BC2 BC1 MODE + -- 0 0 0 inactive + -- 0 0 1 address + -- 0 1 0 inactive + -- 0 1 1 read + -- 1 0 0 address + -- 1 0 1 inactive + -- 1 1 0 write + -- 1 1 1 read + busctrl_addr <= '0'; + busctrl_we <= '0'; + busctrl_re <= '0'; + + cs := '0'; + if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then + cs := '1'; + end if; + + sel := (I_BDIR & I_BC2 & I_BC1); + case sel is + when "000" => null; + when "001" => busctrl_addr <= '1'; + when "010" => null; + when "011" => busctrl_re <= cs; + when "100" => busctrl_addr <= '1'; + when "101" => null; + when "110" => busctrl_we <= cs; + when "111" => busctrl_addr <= '1'; + when others => null; + end case; + end process; + + p_oe : process(busctrl_re) + begin + -- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns + O_DA_OE_L <= not (busctrl_re); + end process; + + -- + -- CLOCKED + -- + p_waddr : process(RESET_L, CLK) + begin + -- looks like registers are latches in real chip, but the address is caught at the end of the address state. + if (RESET_L = '0') then + addr <= (others => '0'); + elsif rising_edge(CLK) then + if (ENA = '1') then + if (busctrl_addr = '1') then + addr <= I_DA; + end if; + end if; + end if; + end process; + + p_wdata : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + reg <= (others => (others => '0')); + env_reset <= '1'; + elsif rising_edge(CLK) then + if (ENA = '1') then + env_reset <= '0'; + if (busctrl_we = '1') then + case addr(3 downto 0) is + when x"0" => reg(0) <= I_DA; + when x"1" => reg(1) <= I_DA; + when x"2" => reg(2) <= I_DA; + when x"3" => reg(3) <= I_DA; + when x"4" => reg(4) <= I_DA; + when x"5" => reg(5) <= I_DA; + when x"6" => reg(6) <= I_DA; + when x"7" => reg(7) <= I_DA; + when x"8" => reg(8) <= I_DA; + when x"9" => reg(9) <= I_DA; + when x"A" => reg(10) <= I_DA; + when x"B" => reg(11) <= I_DA; + when x"C" => reg(12) <= I_DA; + when x"D" => reg(13) <= I_DA; env_reset <= '1'; + when x"E" => reg(14) <= I_DA; + when x"F" => reg(15) <= I_DA; + when others => null; + end case; + end if; + end if; + end if; + end process; + + p_rdata : process(busctrl_re, addr, reg, ioa_inreg, iob_inreg) + begin + O_DA <= (others => '0'); -- 'X' + if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator + case addr(3 downto 0) is + when x"0" => O_DA <= reg(0) ; + when x"1" => O_DA <= "0000" & reg(1)(3 downto 0) ; + when x"2" => O_DA <= reg(2) ; + when x"3" => O_DA <= "0000" & reg(3)(3 downto 0) ; + when x"4" => O_DA <= reg(4) ; + when x"5" => O_DA <= "0000" & reg(5)(3 downto 0) ; + when x"6" => O_DA <= "000" & reg(6)(4 downto 0) ; + when x"7" => O_DA <= reg(7) ; + when x"8" => O_DA <= "000" & reg(8)(4 downto 0) ; + when x"9" => O_DA <= "000" & reg(9)(4 downto 0) ; + when x"A" => O_DA <= "000" & reg(10)(4 downto 0) ; + when x"B" => O_DA <= reg(11); + when x"C" => O_DA <= reg(12); + when x"D" => O_DA <= "0000" & reg(13)(3 downto 0); + when x"E" => if (reg(7)(6) = '0') then -- input + O_DA <= ioa_inreg; + else + O_DA <= reg(14); -- read output reg + end if; + when x"F" => if (Reg(7)(7) = '0') then + O_DA <= iob_inreg; + else + O_DA <= reg(15); + end if; + when others => null; + end case; + end if; + end process; + -- + p_divider : process + begin + wait until rising_edge(CLK); + -- / 8 when SEL is high and /16 when SEL is low + if (ENA = '1') then + ena_div <= '0'; + ena_div_noise <= '0'; + if (cnt_div = "0000") then + cnt_div <= (not I_SEL_L) & "111"; + ena_div <= '1'; + + noise_div <= not noise_div; + if (noise_div = '1') then + ena_div_noise <= '1'; + end if; + else + cnt_div <= cnt_div - "1"; + end if; + end if; + end process; + + p_noise_gen : process + variable noise_gen_comp : std_logic_vector(4 downto 0); + variable poly17_zero : std_logic; + begin + wait until rising_edge(CLK); + if (reg(6)(4 downto 0) = "00000") then + noise_gen_comp := "00000"; + else + noise_gen_comp := (reg(6)(4 downto 0) - "1"); + end if; + + poly17_zero := '0'; + if (poly17 = "00000000000000000") then poly17_zero := '1'; end if; + + if (ENA = '1') then + if (ena_div_noise = '1') then -- divider ena + + if (noise_gen_cnt >= noise_gen_comp) then + noise_gen_cnt <= "00000"; + poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1); + else + noise_gen_cnt <= (noise_gen_cnt + "1"); + end if; + end if; + end if; + end process; + noise_gen_op <= poly17(0); + + p_tone_gens : process + variable tone_gen_freq : array_3x12; + variable tone_gen_comp : array_3x12; + begin + wait until rising_edge(CLK); + -- looks like real chips count up - we need to get the Exact behaviour .. + tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0); + tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2); + tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4); + -- period 0 = period 1 + for i in 1 to 3 loop + if (tone_gen_freq(i) = x"000") then + tone_gen_comp(i) := x"000"; + else + tone_gen_comp(i) := (tone_gen_freq(i) - "1"); + end if; + end loop; + + if (ENA = '1') then + for i in 1 to 3 loop + if (ena_div = '1') then -- divider ena + + if (tone_gen_cnt(i) >= tone_gen_comp(i)) then + tone_gen_cnt(i) <= x"000"; + tone_gen_op(i) <= not tone_gen_op(i); + else + tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1"); + end if; + end if; + end loop; + end if; + end process; + + p_envelope_freq : process + variable env_gen_freq : std_logic_vector(15 downto 0); + variable env_gen_comp : std_logic_vector(15 downto 0); + begin + wait until rising_edge(CLK); + env_gen_freq := reg(12) & reg(11); + -- envelope freqs 1 and 0 are the same. + if (env_gen_freq = x"0000") then + env_gen_comp := x"0000"; + else + env_gen_comp := (env_gen_freq - "1"); + end if; + + if (ENA = '1') then + env_ena <= '0'; + if (ena_div = '1') then -- divider ena + if (env_gen_cnt >= env_gen_comp) then + env_gen_cnt <= x"0000"; + env_ena <= '1'; + else + env_gen_cnt <= (env_gen_cnt + "1"); + end if; + end if; + end if; + end process; + + p_envelope_shape : process(env_reset, reg, CLK) + variable is_bot : boolean; + variable is_bot_p1 : boolean; + variable is_top_m1 : boolean; + variable is_top : boolean; + begin + -- envelope shapes + -- C AtAlH + -- 0 0 x x \___ + -- + -- 0 1 x x /___ + -- + -- 1 0 0 0 \\\\ + -- + -- 1 0 0 1 \___ + -- + -- 1 0 1 0 \/\/ + -- ___ + -- 1 0 1 1 \ + -- + -- 1 1 0 0 //// + -- ___ + -- 1 1 0 1 / + -- + -- 1 1 1 0 /\/\ + -- + -- 1 1 1 1 /___ + if (env_reset = '1') then + -- load initial state + if (reg(13)(2) = '0') then -- attack + env_vol <= "11111"; + env_inc <= '0'; -- -1 + else + env_vol <= "00000"; + env_inc <= '1'; -- +1 + end if; + env_hold <= '0'; + + elsif rising_edge(CLK) then + is_bot := (env_vol = "00000"); + is_bot_p1 := (env_vol = "00001"); + is_top_m1 := (env_vol = "11110"); + is_top := (env_vol = "11111"); + + if (ENA = '1') then + if (env_ena = '1') then + if (env_hold = '0') then + if (env_inc = '1') then + env_vol <= (env_vol + "00001"); + else + env_vol <= (env_vol + "11111"); + end if; + end if; + + -- envelope shape control. + if (reg(13)(3) = '0') then + if (env_inc = '0') then -- down + if is_bot_p1 then env_hold <= '1'; end if; + else + if is_top then env_hold <= '1'; end if; + end if; + else + if (reg(13)(0) = '1') then -- hold = 1 + if (env_inc = '0') then -- down + if (reg(13)(1) = '1') then -- alt + if is_bot then env_hold <= '1'; end if; + else + if is_bot_p1 then env_hold <= '1'; end if; + end if; + else + if (reg(13)(1) = '1') then -- alt + if is_top then env_hold <= '1'; end if; + else + if is_top_m1 then env_hold <= '1'; end if; + end if; + end if; + + elsif (reg(13)(1) = '1') then -- alternate + if (env_inc = '0') then -- down + if is_bot_p1 then env_hold <= '1'; end if; + if is_bot then env_hold <= '0'; env_inc <= '1'; end if; + else + if is_top_m1 then env_hold <= '1'; end if; + if is_top then env_hold <= '0'; env_inc <= '0'; end if; + end if; + end if; + + end if; + end if; + end if; + end if; + end process; + + p_chan_mixer : process(cnt_div, reg, tone_gen_op) + begin + tone_ena_l <= '1'; tone_src <= '1'; + noise_ena_l <= '1'; chan_vol <= "00000"; + case cnt_div(1 downto 0) is + when "00" => + tone_ena_l <= reg(7)(0); tone_src <= tone_gen_op(1); chan_vol <= reg(8)(4 downto 0); + noise_ena_l <= reg(7)(3); + when "01" => + tone_ena_l <= reg(7)(1); tone_src <= tone_gen_op(2); chan_vol <= reg(9)(4 downto 0); + noise_ena_l <= reg(7)(4); + when "10" => + tone_ena_l <= reg(7)(2); tone_src <= tone_gen_op(3); chan_vol <= reg(10)(4 downto 0); + noise_ena_l <= reg(7)(5); + when "11" => null; -- tone gen outputs become valid on this clock + when others => null; + end case; + end process; + + p_op_mixer : process + variable chan_mixed : std_logic; + variable chan_amp : std_logic_vector(4 downto 0); + begin + wait until rising_edge(CLK); + if (ENA = '1') then + + chan_mixed := (tone_ena_l or tone_src) and (noise_ena_l or noise_gen_op); + + chan_amp := (others => '0'); + if (chan_mixed = '1') then + if (chan_vol(4) = '0') then + if (chan_vol(3 downto 0) = "0000") then -- nothing is easy ! make sure quiet is quiet + chan_amp := "00000"; + else + chan_amp := chan_vol(3 downto 0) & '1'; -- make sure level 31 (env) = level 15 (tone) + end if; + else + chan_amp := env_vol(4 downto 0); + end if; + end if; + + dac_amp <= x"00"; + case chan_amp is + when "11111" => dac_amp <= x"FF"; + when "11110" => dac_amp <= x"D9"; + when "11101" => dac_amp <= x"BA"; + when "11100" => dac_amp <= x"9F"; + when "11011" => dac_amp <= x"88"; + when "11010" => dac_amp <= x"74"; + when "11001" => dac_amp <= x"63"; + when "11000" => dac_amp <= x"54"; + when "10111" => dac_amp <= x"48"; + when "10110" => dac_amp <= x"3D"; + when "10101" => dac_amp <= x"34"; + when "10100" => dac_amp <= x"2C"; + when "10011" => dac_amp <= x"25"; + when "10010" => dac_amp <= x"1F"; + when "10001" => dac_amp <= x"1A"; + when "10000" => dac_amp <= x"16"; + when "01111" => dac_amp <= x"13"; + when "01110" => dac_amp <= x"10"; + when "01101" => dac_amp <= x"0D"; + when "01100" => dac_amp <= x"0B"; + when "01011" => dac_amp <= x"09"; + when "01010" => dac_amp <= x"08"; + when "01001" => dac_amp <= x"07"; + when "01000" => dac_amp <= x"06"; + when "00111" => dac_amp <= x"05"; + when "00110" => dac_amp <= x"04"; + when "00101" => dac_amp <= x"03"; + when "00100" => dac_amp <= x"03"; + when "00011" => dac_amp <= x"02"; + when "00010" => dac_amp <= x"02"; + when "00001" => dac_amp <= x"01"; + when "00000" => dac_amp <= x"00"; + when others => null; + end case; + + cnt_div_t1 <= cnt_div; + end if; + end process; + + p_audio_output : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + O_AUDIO <= (others => '0'); + O_CHAN <= (others => '0'); + elsif rising_edge(CLK) then + + if (ENA = '1') then + O_AUDIO <= dac_amp(7 downto 0); + O_CHAN <= cnt_div_t1(1 downto 0); + end if; + end if; + end process; + + p_io_ports : process(reg) + begin + O_IOA <= reg(14); + O_IOA_OE_L <= not reg(7)(6); + O_IOB <= reg(15); + O_IOB_OE_L <= not reg(7)(7); + end process; + + p_io_ports_inreg : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then -- resync + ioa_inreg <= I_IOA; + iob_inreg <= I_IOB; + end if; + end process; +end architecture RTL; diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/build_id.tcl b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/dpram.vhd b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..cda0f3cd --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/dpram.vhd @@ -0,0 +1,123 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY dpram IS + GENERIC + ( + init_file : string := ""; + numwords_a : natural := 0; -- not used any more + widthad_a : natural; + width_a : natural := 8; + outdata_reg_a : string := "UNREGISTERED"; + outdata_reg_b : string := "UNREGISTERED" + ); + PORT + ( + address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + clock_a : IN STD_LOGIC ; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + wren_a : IN STD_LOGIC := '1'; + wren_b : IN STD_LOGIC := '1'; + q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); +END dpram; + + +ARCHITECTURE SYN OF dpram IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + + COMPONENT altsyncram + GENERIC ( + address_reg_b : STRING; + clock_enable_input_a : STRING; + clock_enable_input_b : STRING; + clock_enable_output_a : STRING; + clock_enable_output_b : STRING; + indata_reg_b : STRING; + init_file : STRING; + intended_device_family : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + numwords_b : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_aclr_b : STRING; + outdata_reg_a : STRING; + outdata_reg_b : STRING; + power_up_uninitialized : STRING; + widthad_a : NATURAL; + widthad_b : NATURAL; + width_a : NATURAL; + width_b : NATURAL; + width_byteena_a : NATURAL; + width_byteena_b : NATURAL; + wrcontrol_wraddress_reg_b : STRING + ); + PORT ( + wren_a : IN STD_LOGIC ; + clock0 : IN STD_LOGIC ; + wren_b : IN STD_LOGIC ; + clock1 : IN STD_LOGIC ; + address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q_a <= sub_wire0(width_a-1 DOWNTO 0); + q_b <= sub_wire1(width_a-1 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + address_reg_b => "CLOCK1", + clock_enable_input_a => "BYPASS", + clock_enable_input_b => "BYPASS", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", + init_file => init_file, + intended_device_family => "Cyclone III", + lpm_type => "altsyncram", + numwords_a => 2**widthad_a, + numwords_b => 2**widthad_a, + operation_mode => "BIDIR_DUAL_PORT", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => outdata_reg_a, + outdata_reg_b => outdata_reg_b, + power_up_uninitialized => "FALSE", + widthad_a => widthad_a, + widthad_b => widthad_a, + width_a => width_a, + width_b => width_a, + width_byteena_a => 1, + width_byteena_b => 1, + wrcontrol_wraddress_reg_b => "CLOCK1" + ) + PORT MAP ( + wren_a => wren_a, + clock0 => clock_a, + wren_b => wren_b, + clock1 => clock_b, + address_a => address_a, + address_b => address_b, + data_a => data_a, + data_b => data_b, + q_a => sub_wire0, + q_b => sub_wire1 + ); + +END SYN; diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/gen_ram.vhd b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/gen_ram.vhd new file mode 100644 index 00000000..f1a95608 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/gen_ram.vhd @@ -0,0 +1,84 @@ +-- ----------------------------------------------------------------------- +-- +-- Syntiac's generic VHDL support files. +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- +-- Modified April 2016 by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +-- Remove address register when writing +-- +-- ----------------------------------------------------------------------- +-- +-- gen_rwram.vhd +-- +-- ----------------------------------------------------------------------- +-- +-- generic ram. +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +entity gen_ram is + generic ( + dWidth : integer := 8; + aWidth : integer := 10 + ); + port ( + clk : in std_logic; + we : in std_logic; + addr : in std_logic_vector((aWidth-1) downto 0); + d : in std_logic_vector((dWidth-1) downto 0); + q : out std_logic_vector((dWidth-1) downto 0) + ); +end entity; + +-- ----------------------------------------------------------------------- + +architecture rtl of gen_ram is + subtype addressRange is integer range 0 to ((2**aWidth)-1); + type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0); + signal ram: ramDef; + + signal rAddrReg : std_logic_vector((aWidth-1) downto 0); + signal qReg : std_logic_vector((dWidth-1) downto 0); +begin +-- ----------------------------------------------------------------------- +-- Signals to entity interface +-- ----------------------------------------------------------------------- +-- q <= qReg; + +-- ----------------------------------------------------------------------- +-- Memory write +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if we = '1' then + ram(to_integer(unsigned(addr))) <= d; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Memory read +-- ----------------------------------------------------------------------- +process(clk) + begin + if rising_edge(clk) then +-- qReg <= ram(to_integer(unsigned(rAddrReg))); +-- rAddrReg <= addr; +---- qReg <= ram(to_integer(unsigned(addr))); + q <= ram(to_integer(unsigned(addr))); + end if; + end process; +--q <= ram(to_integer(unsigned(addr))); +end architecture; + diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jng_hvgen.v b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jng_hvgen.v new file mode 100644 index 00000000..56e6ec98 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jng_hvgen.v @@ -0,0 +1,36 @@ +module jng_hvgen +( + output [8:0] HPOS, + output [8:0] VPOS, + input PCLK, + output reg HBLK = 1, + output reg VBLK = 1, + output reg HSYN = 1, + output reg VSYN = 1 +); + +reg [8:0] hcnt = 0; +reg [8:0] vcnt = 0; + +assign HPOS = hcnt; +assign VPOS = vcnt; + +always @(posedge PCLK) begin + case (hcnt) + 287: begin HBLK <= 1; HSYN <= 0; hcnt <= hcnt+1; end + 311: begin HSYN <= 1; hcnt <= hcnt+1; end + 383: begin + HBLK <= 0; HSYN <= 1; hcnt <= 0; + case (vcnt) + 223: begin VBLK <= 1; vcnt <= vcnt+1; end + 226: begin VSYN <= 0; vcnt <= vcnt+1; end + 233: begin VSYN <= 1; vcnt <= vcnt+1; end + 242: begin VBLK <= 0; vcnt <= 0; end + default: vcnt <= vcnt+1; + endcase + end + default: hcnt <= hcnt+1; + endcase +end + +endmodule \ No newline at end of file diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jng_sound.vhd b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jng_sound.vhd new file mode 100644 index 00000000..12f35807 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jng_sound.vhd @@ -0,0 +1,425 @@ +--------------------------------------------------------------------------------- +-- burnin rubber sound by Dar (darfpga@aol.fr) (05/12/2017) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- +-- gen_ram.vhd & io_ps2_keyboard +-------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +--------------------------------------------------------------------------------- +-- T65(b) core.Ver 301 by MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +--------------------------------------------------------------------------------- +-- YM2149 (AY-3-8910) +-- Copyright (c) MikeJ - Jan 2005 +--------------------------------------------------------------------------------- +-- Use burnin_rubber_de10_lite.sdc to compile (Timequest constraints) +-- /!\ +-- Don't forget to set device configuration mode with memory initialization +-- (Assignments/Device/Pin options/Configuration mode) +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity jng_sound is +port +( + clock_12 : in std_logic; + reset : in std_logic; + + sound_req : in std_logic; + sound_code_in : in std_logic_vector(7 downto 0); + sound_timing : in std_logic; + + audio_out : out std_logic_vector(10 downto 0); + + dbg_cpu_addr: out std_logic_vector(15 downto 0) + ); +end jng_sound; + +architecture syn of jng_sound is + + -- clocks, reset + signal clock_12n : std_logic; + signal clock_div1 : std_logic_vector(8 downto 0) := (others =>'0'); + signal clock_div2 : std_logic_vector(4 downto 0) := (others =>'0'); + signal clock_500K : std_logic; + signal ayx_clock : std_logic; + signal reset_n : std_logic; + + -- cpu signals + signal cpu_addr : std_logic_vector(23 downto 0); + signal cpu_di : std_logic_vector( 7 downto 0); + signal cpu_di_dec : std_logic_vector( 7 downto 0); + signal cpu_do : std_logic_vector( 7 downto 0); + signal cpu_rw_n : std_logic; + signal cpu_nmi_n : std_logic; + signal cpu_irq_n : std_logic; + signal cpu_sync : std_logic; + + -- program rom signals + signal prog_rom_cs : std_logic; + signal prog_rom_do : std_logic_vector(7 downto 0); + + -- working ram signals + signal wram_cs : std_logic; + signal wram_we : std_logic; + signal wram_do : std_logic_vector(7 downto 0); + + -- sound req management + signal nmi_reg : std_logic; + signal nmi_reg_cs : std_logic; + signal nmi_reg_we : std_logic; + signal sound_code : std_logic_vector(7 downto 0); + signal sound_code_cs : std_logic; + + -- ay-3-8910 signal + signal ay1_bc1 : std_logic; + signal ay1_bdir : std_logic; + signal ay1_audio_chan : std_logic_vector(1 downto 0); + signal ay1_audio_muxed: std_logic_vector(7 downto 0); + signal ay1_chan_a: std_logic_vector(7 downto 0); + signal ay1_chan_b: std_logic_vector(7 downto 0); + signal ay1_chan_c: std_logic_vector(7 downto 0); + + signal ay2_bc1 : std_logic; + signal ay2_bdir : std_logic; + signal ay2_audio_chan : std_logic_vector(1 downto 0); + signal ay2_audio_muxed: std_logic_vector(7 downto 0); + signal ay2_chan_a: std_logic_vector(7 downto 0); + signal ay2_chan_b: std_logic_vector(7 downto 0); + signal ay2_chan_c: std_logic_vector(7 downto 0); + + -- digital filtering AY2 channel A + signal uin : integer range -256 to 255; + signal u3 : integer range -32768 to 32767; + signal u4 : integer range -32768 to 32767; + signal du3 : integer range -32768*4096 to 32767*4096; + signal du4 : integer range -32768*4096 to 32767*4096; + signal uout : integer range -32768 to 32767; + signal uout_lim : integer range -128 to 127; + +begin + +process (clock_12, cpu_sync) +begin + if rising_edge(clock_12) then + if cpu_sync = '1' then + dbg_cpu_addr <= cpu_addr(15 downto 0); + end if; + end if; +end process; + +reset_n <= not reset; +clock_12n <= not clock_12; + +process (clock_12, reset) + begin + if reset='1' then + clock_div1 <= (others => '0'); + clock_div2 <= (others => '0'); + else + if rising_edge(clock_12) then + if clock_div1 = "111111111" then -- divide by 512 (23.437kHz) + clock_div1 <= "000000000"; + else + clock_div1 <= clock_div1 + '1'; + end if; + if clock_div2 = "10111" then -- divide by 24 + clock_div2 <= "00000"; + else + clock_div2 <= clock_div2 + '1'; + end if; + end if; + end if; +end process; + +clock_500K <= clock_div2(4); --12MHz/24 = 500kHz +ayx_clock <= clock_div1(2); --12MHz/8 = 1.5MHz + +--static ADDRESS_MAP_START( audio_map, AS_PROGRAM, 8, btime_state ) +-- AM_RANGE(0x0000, 0x03ff) AM_MIRROR(0x1c00) AM_RAM AM_SHARE("audio_rambase") +-- AM_RANGE(0x2000, 0x3fff) AM_DEVWRITE("ay1", ay8910_device, data_w) +-- AM_RANGE(0x4000, 0x5fff) AM_DEVWRITE("ay1", ay8910_device, address_w) +-- AM_RANGE(0x6000, 0x7fff) AM_DEVWRITE("ay2", ay8910_device, data_w) +-- AM_RANGE(0x8000, 0x9fff) AM_DEVWRITE("ay2", ay8910_device, address_w) +-- AM_RANGE(0xa000, 0xbfff) AM_READ(audio_command_r) +-- AM_RANGE(0xc000, 0xdfff) AM_WRITE(audio_nmi_enable_w) +-- AM_RANGE(0xe000, 0xefff) AM_MIRROR(0x1000) AM_ROM +--ADDRESS_MAP_END + +-- chip select +wram_cs <= '1' when cpu_addr(15 downto 13) = "000" else '0'; -- working ram 0000-07ff .. 1fff +ay1_bc1 <= '1' when cpu_addr(15 downto 13) = "010" else '0'; +ay1_bdir <= '1' when cpu_addr(15 downto 13) = "001" or ay1_bc1 = '1' else '0'; +ay2_bc1 <= '1' when cpu_addr(15 downto 13) = "100" else '0'; +ay2_bdir <= '1' when cpu_addr(15 downto 13) = "011" or ay2_bc1 = '1' else '0'; +sound_code_cs <= '1' when cpu_addr(15 downto 13) = "101" else '0'; +nmi_reg_cs <= '1' when cpu_addr(15 downto 13) = "110" else '0'; +prog_rom_cs <= '1' when cpu_addr(15 downto 13) = "111" else '0'; + +-- write enable +wram_we <= '1' when wram_cs = '1' and cpu_rw_n = '0' else '0'; +nmi_reg_we <= '1' when nmi_reg_cs = '1' and cpu_rw_n = '0' else '0'; + +-- cpu di mux +cpu_di <= wram_do when wram_cs = '1' else + prog_rom_do when prog_rom_cs = '1' else + sound_code when sound_code_cs = '1' else + X"FF"; + +-- regsiter sound code and irq management +process (clock_12) +begin + if rising_edge(clock_12) then + if sound_req = '1' then + sound_code <= sound_code_in; + cpu_irq_n <= '0'; + end if; + if sound_code_cs = '1' then + cpu_irq_n <= '1'; + end if; + end if; +end process; + +-- nmi autorisation management +process (reset, clock_12) +begin + if reset = '1' then + nmi_reg <= '0'; + else + if rising_edge(clock_12) then + if nmi_reg_we = '1' then + nmi_reg <= cpu_do(0); + end if; + end if; + end if; +end process; + +-- nmi +cpu_nmi_n <= '0' when nmi_reg = '1' and sound_timing = '1' else '1'; + +-- demux AY chips output +process (ayx_clock) +begin + if rising_edge(ayx_clock) then + if ay1_audio_chan = "00" then ay1_chan_a <= ay1_audio_muxed; end if; + if ay1_audio_chan = "01" then ay1_chan_b <= ay1_audio_muxed; end if; + if ay1_audio_chan = "10" then ay1_chan_c <= ay1_audio_muxed; end if; + if ay2_audio_chan = "00" then ay2_chan_a <= ay2_audio_muxed; end if; + if ay2_audio_chan = "01" then ay2_chan_b <= ay2_audio_muxed; end if; + if ay2_audio_chan = "10" then ay2_chan_c <= ay2_audio_muxed; end if; + end if; +end process; + +-- AOP Rauch passe bande filter +-- +-- ----------o------------ +-- u4^ | | | +-- | --- C4 | | R5 | +-- | --- | | | +-- | | C3 | | +-- --| R1 |----o----||---o------|\ | +-- ^ | ------> u3 | \__o--- +-- | | | / ^ +-- |uin | | R2 --|/ | +-- | | | | | uout +-- | | | | +-- ------------o--------------o---------- +-- +-- +-- i1 = (sin+u3)/R1 +-- i2 = -u3/R2 +-- i3 = (u4-u3)/R5 +-- i4 = i2-i1-i3 +-- +-- u3(t+dt) = u3(t) + i3(t)*dt/C3; +-- u4(t+dt) = u4(t) + i4(t)*dt/C4; + +-- uout = u4-u3 + +-- R1 = 5000; +-- R2 = 10000; +-- C3 = 0.068e-6; +-- C4 = 0.068e-6; +-- R5 = 47000; +-- +-- dt = 1/f_ech = 1/23437 +-- dt/C3 = dt/C4 = 627 +-- +-- (i3(t)*dt/C3)*8192 = du3*8192 = ((u4-u3)/47000*627)*8192 +-- = (u4-u3)*109 +-- +-- (i4(t)*dt/C4)*8192 = du4*8192 = (-u3/10000 -(uin+u3)/5000 -(u4-u3)/47000)*627*8192 +-- = -u3(514+1027-109) - uin*1027 - u4*109 +-- = -(u4*109 + u3*1432 + uin*1027) +-- + +-- down sample to 23.437kHz and filter AY2 channel A +uin <= to_integer(unsigned(ay2_chan_a)); + +process (clock_12) +begin + if rising_edge(clock_12) then + + if clock_div1 = "000000000" then + du3 <= u4*109 - u3*109; + du4 <= u4*109 + u3*1432 + uin*1027*16; -- add gain(16) to uin + end if; + + if clock_div1 = "000000001" then + u3 <= u3 + du3/8192; + u4 <= u4 - du4/8192; + end if; + + if clock_div1 = "000000010" then + uout <= (u4 - u3) / 8; -- adjust output gain + end if; + + -- limit signed dynamique before return to unsigned + if clock_div1 = "000000011" then + if uout > 127 then + uout_lim <= 127; + elsif uout < -127 then + uout_lim <= -127; + else + uout_lim <= uout; + end if; + end if; + + if clock_div1 = "000000100" then + + audio_out <= ("000"&ay1_chan_a(7 downto 0)) + + ("000"&ay1_chan_b(7 downto 0)) + + ("000"&ay1_chan_c(7 downto 0)) + + ("000"&std_logic_vector(to_unsigned(uout_lim+128,8)))+ + ("000"&ay2_chan_b(7 downto 0)) + + ("000"&ay2_chan_c(7 downto 0)); + end if; + + end if; +end process; + +--------------------------- +-- components +--------------------------- + +cpu_inst : entity work.T65 +port map +( + Mode => "00", -- 6502 + Res_n => reset_n, + Enable => '1', + Clk => clock_500K, + Rdy => '1', + Abort_n => '1', + IRQ_n => cpu_irq_n, + NMI_n => cpu_nmi_n, + SO_n => '1',--cpu_so_n, + R_W_n => cpu_rw_n, + Sync => cpu_sync, -- open + EF => open, + MF => open, + XF => open, + ML_n => open, + VP_n => open, + VDA => open, + VPA => open, + A => cpu_addr, + DI => cpu_di, + DO => cpu_do +); + +-- working ram +wram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 11) +port map( + clk => clock_12n, + we => wram_we, + addr => cpu_addr(10 downto 0), + d => cpu_do, + q => wram_do +); + +-- program rom +program_rom: entity work.jng_snd_rom +port map( + clk => clock_12n, + addr => cpu_addr(11 downto 0), + data => prog_rom_do +); + +-- AY-3-8910 #1 +ay_3_8910_1 : entity work.YM2149 +port map( + -- data bus + I_DA => cpu_do, -- in std_logic_vector(7 downto 0); + O_DA => open, -- out std_logic_vector(7 downto 0); + O_DA_OE_L => open, -- out std_logic; + -- control + I_A9_L => '0', -- in std_logic; + I_A8 => '1', -- in std_logic; + I_BDIR => ay1_bdir, -- in std_logic; + I_BC2 => '1', -- in std_logic; + I_BC1 => ay1_bc1, -- in std_logic; + I_SEL_L => '1', -- in std_logic; + + O_AUDIO => ay1_audio_muxed, -- out std_logic_vector(7 downto 0); + O_CHAN => ay1_audio_chan, -- out std_logic_vector(1 downto 0); + + -- port a + I_IOA => X"00", -- in std_logic_vector(7 downto 0); + O_IOA => open, -- out std_logic_vector(7 downto 0); + O_IOA_OE_L => open, -- out std_logic; + -- port b + I_IOB => X"00", -- in std_logic_vector(7 downto 0); + O_IOB => open, -- out std_logic_vector(7 downto 0); + O_IOB_OE_L => open, -- out std_logic; + + ENA => '1', -- in std_logic; -- clock enable for higher speed operation + RESET_L => reset_n, -- in std_logic; + CLK => ayx_clock -- in std_logic -- note 6 Mhz +); + +-- AY-3-8910 #2 +ay_3_8910_2 : entity work.YM2149 +port map( + -- data bus + I_DA => cpu_do, -- in std_logic_vector(7 downto 0); + O_DA => open, -- out std_logic_vector(7 downto 0); + O_DA_OE_L => open, -- out std_logic; + -- control + I_A9_L => '0', -- in std_logic; + I_A8 => '1', -- in std_logic; + I_BDIR => ay2_bdir, -- in std_logic; + I_BC2 => '1', -- in std_logic; + I_BC1 => ay2_bc1, -- in std_logic; + I_SEL_L => '1', -- in std_logic; + + O_AUDIO => ay2_audio_muxed, -- out std_logic_vector(7 downto 0); + O_CHAN => ay2_audio_chan, -- out std_logic_vector(1 downto 0); + + -- port a + I_IOA => (others => '0'), -- in std_logic_vector(7 downto 0); + O_IOA => open, -- out std_logic_vector(7 downto 0); + O_IOA_OE_L => open, -- out std_logic; + -- port b + I_IOB => (others => '0'), -- in std_logic_vector(7 downto 0); + O_IOB => open, -- out std_logic_vector(7 downto 0); + O_IOB_OE_L => open, -- out std_logic; + + ENA => '1', --cpu_ena, -- in std_logic; -- clock enable for higher speed operation + RESET_L => reset_n, -- in std_logic; + CLK => ayx_clock -- in std_logic -- note 6 Mhz +); + + +end SYN; diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jng_sprite.v b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jng_sprite.v new file mode 100644 index 00000000..c84bdd88 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jng_sprite.v @@ -0,0 +1,154 @@ + +module jng_sprite +( + input VCLKx4, + input HBLK, + + input [8:0] HPOS, + input [8:0] VPOS, + + output reg [10:0] SPRAADRS, + input [15:0] SPRADATA, + + output [3:0] ARAMADRS, + input [7:0] ARAMDATA, + + output [11:0] SPCHRADR, + input [7:0] SPCHRDAT, + + output [7:0] DROMAD, + input [7:0] DROMDT, + + output reg [8:0] SPCOL +); + +reg [1:0] clkcnt; +always @( posedge VCLKx4 ) clkcnt<=clkcnt+1; +wire VCLKx2 = clkcnt[0]; +wire VCLK = clkcnt[1]; + +wire SIDE = VPOS[0]; + + +reg [19:0] SPATR0; +reg [36:0] SPATRS[0:31]; +reg [3:0] WWADR; +reg bHit; + +assign ARAMADRS = SPRAADRS[3:0]; + + +reg [7:0] WRADR; +reg [8:0] HPOSW; +reg [8:0] SPWCL; + +wire [36:0] SPA = SPATRS[{~SIDE,WRADR[7:4]}]; + +wire [3:0] SH = WRADR[3:0]+4'h4; +wire [3:0] SV = SPA[35:32]; + +wire [2:0] SPFY = { 3{SPA[1]} }; +wire [1:0] SPFX = { 1'b0, SPA[0] }; +wire [5:0] SPPL = SPA[29:24]; + +assign SPCHRADR = { SPA[7:2], ( SV[3] ^ SPA[1] ), ( SH[3:2] ^ SPFX ), ( SV[2:0] ^ SPFY ) }; +wire [7:0] CHRO = SPCHRDAT; + + +wire [8:0] YM = ( SPRADATA[15:8] + 8'h10 ) + VPOS[7:0]; + +assign DROMAD = { 1'b0, (~SPA[19:17]), SPA[33:32], WRADR[3:2] }; + +always @ ( posedge VCLKx2 ) begin + + // in H-BLANK + if ( HBLK ) begin + + // Sprite V-hit check & list-up + if ( SPRAADRS < 10'h20 ) begin + if ( SPRAADRS[0] ) begin + if ( bHit ) begin + SPATRS[{SIDE,WWADR}] <= { 1'b1, SPATR0[3:0], SPRADATA, SPATR0[19:4] }; + WWADR <= WWADR+1; + end + end + else begin + if ( YM[7:4] == 4'b1111 ) begin + bHit <= 1; + SPATR0 <= { SPRADATA, YM[3:0] }; + end + else bHit <= 0; + end + SPRAADRS <= ( SPRAADRS == 10'h1F ) ? 10'h34 : (SPRAADRS+1); + end + // Rader-dot V-hit check & list-up + else begin + if ( SPRAADRS < 10'h40 ) begin + if ( YM[7:2] == 6'b111111 ) begin + SPATRS[{SIDE,WWADR}] <= { 1'b0, 2'b00, YM[1:0], 8'h0, ARAMDATA, SPRADATA }; + WWADR <= WWADR+1; + end + SPRAADRS <= SPRAADRS+1; + end + else SPATRS[{SIDE,WWADR}] <= 0; + end + + if ( SPA ) begin + // Rend Sprite + if ( SPA[36] ) begin + HPOSW <= ( WRADR[3:0] ) ? (HPOSW+1) : { SPA[31], SPA[23:16] }; + case ( SH[1:0] ^ {2{SPFX[0]}} ) + 2'b00: SPWCL <= { 1'b0, SPPL, CHRO[7], CHRO[3] }; + 2'b01: SPWCL <= { 1'b0, SPPL, CHRO[6], CHRO[2] }; + 2'b10: SPWCL <= { 1'b0, SPPL, CHRO[5], CHRO[1] }; + 2'b11: SPWCL <= { 1'b0, SPPL, CHRO[4], CHRO[0] }; + endcase + WRADR <= WRADR+1; + end + // Rend Rader-dot + else begin + HPOSW <= ( WRADR[3:0] ) ? (HPOSW+1) : ({ (~SPA[16]), SPA[7:0] }); + SPWCL <= ( DROMDT[1:0] != 2'b11 ) ? { 1'b1, 6'b000100, DROMDT[1:0] } : 0; + WRADR <= WRADR+4; + end + end + else SPWCL <= 0; + + end + + // in H-DISP + else begin + SPRAADRS <= 10'h14; + WWADR <= 0; + WRADR <= 0; + SPWCL <= 0; + end + +end + + +reg [9:0] radr0=0,radr1=1; +wire [8:0] SPCOLi; +dpram #( + .widthad_a(10), + .width_a(9)) +linebuffer( + .address_a({SIDE,HPOS}), + .address_b({~SIDE,HPOSW}), + .clock_a(VCLKx2), + .clock_b(VCLKx2), + .data_a(9'h0), + .data_b(SPWCL), + .wren_a(radr0==radr1), + .wren_b((SPWCL[0]|SPWCL[1])), + .q_a(SPCOLi), + .q_b() + ); + +always @(posedge VCLK) radr0 <= {SIDE,HPOS}; +always @(negedge VCLK) begin + if (radr0!=radr1) SPCOL <= SPCOLi; + radr1 <= radr0; +end + +endmodule diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jng_top.v b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jng_top.v new file mode 100644 index 00000000..aa6b9dca --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jng_top.v @@ -0,0 +1,195 @@ +/************************************************************** + FPGA Jungler (Main part) +***************************************************************/ +module jng_top +( + input RESET, // RESET + input CLK24M, // Clock 24.576MHz + output hsync, + output vsync, + output hblank, + output vblank, + output [2:0] r, + output [2:0] g, + output [1:0] b, + output [10:0] SND, // Sound (unsigned PCM) + input [7:0] DSW1, // DipSW + input [7:0] DSW2, // DipSW + input [7:0] CTR1, // Controler (Negative logic) + input [7:0] CTR2 +); + + +//-------------------------------------------------- +// Clock Generators +//-------------------------------------------------- +reg [2:0] _CCLK; +always @( posedge CLK24M ) _CCLK <= _CCLK+1; + +wire CLK = CLK24M; // 24MHz +wire CCLKx4 = _CCLK[0]; // CPU CLOCKx4 : 12.0MHz +wire CCLK = _CCLK[2]; // CPU CLOCK : 3.0MHz + + +//-------------------------------------------------- +// CPU +//-------------------------------------------------- +// memory access signals +wire rd, wr, me, ie, rf, m1; +wire [15:0] ad; +wire [7:0] odt, viddata; + +wire mx = rf & (~me); +wire mr = mx & (~rd); +wire mw = mx & (~wr); + +// interrupt signal/vector generator & other latches +reg inte = 1'b0; +reg intl = 1'b0; +reg [7:0] intv = 8'h0; + + +reg out1r = 1'b0; +reg out2r = 1'b0; +reg out3r = 1'b0; +reg sonr = 1'b0;//sound On + +wire vblk = (VP==224)&(HP<=8); + +wire lat_Wce = ( ad[15:4] == 12'hA18 ) & mw; + +wire sndw = ( lat_Wce & ( ad[3:0] == 4'h0 ) ); +wire iewr = ( lat_Wce & ( ad[3:0] == 4'h1 ) ); +wire mute = ( lat_Wce & ( ad[3:0] == 4'h1 ) );//mute +wire flip = ( lat_Wce & ( ad[3:0] == 4'h3 ) );//flip +wire out1w = ( lat_Wce & ( ad[3:0] == 4'h4 ) ); +//wire out2w = ( lat_Wce & ( ad[3:0] == 4'h5 ) );//NOP +wire out3w = ( lat_Wce & ( ad[3:0] == 4'h6 ) ); +//wire starw = ( lat_Wce & ( ad[3:0] == 4'h7 ) );//not used +wire iowr = ( (~wr) & (~ie) & m1 ); + + +always @( posedge CCLK ) begin + if ( iowr ) intv <= odt; + if ( vblk ) intl <= 1'b1; + if ( iewr ) begin + inte <= odt[0]; + intl <= 1'b0; + end + if ( sndw ) sonr <= odt[0]; + if ( out1w ) out1r <= odt[0]; +// if ( out2w ) out2r <= odt[0]; + if ( out3w ) out3r <= odt[0]; +end + +wire irq_n = ~( intl & inte ); + + +// address decoders +wire rom_Rce = ( ( ad[15] == 1'b0 ) & mr ); // $0000-$7FFF(R) +wire ram_Rce = ( ( ad[15:11] == 5'b1001_1 ) & mr ); // $9800-$9FFF(R) +wire ram_Wce = ( ( ad[15:11] == 5'b1001_1 ) & mw ); // $9800-$9FFF(W) +wire inp_Rce = ( ( ad[15:12] == 4'b1010 ) & mr ); // $A000-$AFFF(R) +wire snd_Wce = ( ( ad[15:8] == 8'b1010_0001 ) & mw ); // $A100-$A1FF(W) +wire vid_Rce; + + +wire [7:0] romdata; +jng_prg_rom jng_prg_rom ( + .clk(CCLK), + .addr(ad[13:0]), + .data(romdata) + ); + +// Work RAM (2KB) +wire [7:0] ramdata; +GSPRAM #(11,8) workram( + .CL(CCLK), + .AD(ad[10:0]), + .WE(ram_Wce), + .DI(odt), + .DO(ramdata) + ); + + +// Controler/DipSW input +wire [7:0] in0data = CTR1; +wire [7:0] in1data = CTR2; +wire [7:0] in2data = DSW1; +wire [7:0] in3data = DSW2; +wire [7:0] inpdata = (ad[8:7] == 2'b11) ? in3data : (ad[8:7] == 2'b10) ? in2data : (ad[8:7] == 2'b01) ? in1data : in0data; +// databus selector +wire [7:0] romd = rom_Rce ? romdata : 8'h00; +wire [7:0] ramd = ram_Rce ? ramdata : 8'h00; +wire [7:0] vidd = vid_Rce ? viddata : 8'h00; +wire [7:0] inpd = inp_Rce ? inpdata : 8'h00; +wire [7:0] irqv = ( (~m1) & (~ie) ) ? intv : 8'h00; + +wire [7:0] idt = romd | ramd | irqv | vidd | inpd; + + +T80s z80( + .RESET_n(~RESET), + .CLK_n(CCLK), + .WAIT_n(1'b1), + .INT_n(1'b1), + .NMI_n(irq_n), + .BUSRQ_n(1'b1), + .DI(idt), + .M1_n(m1), + .MREQ_n(me), + .IORQ_n(ie), + .RD_n(rd), + .WR_n(wr), + .RFSH_n(rf), + .HALT_n(), + .BUSAK_n(), + .A(ad), + .DO(odt) + ); + +//-------------------------------------------------- +// VIDEO +//-------------------------------------------------- +wire [8:0] HP; +wire [8:0] VP; +wire PCLK; + +jng_video video( + .VCLKx4(CLK), + .HPOS(HP+3), + .VPOS(VP+1), + .PCLK(PCLK), + .POUT({b,g,r}), + .CPUCLK(CCLK), + .CPUADDR(ad), + .CPUDI(odt), + .CPUDO(viddata), + .CPUME(mx), + .CPUWE(mw), + .CPUDT(vid_Rce) + ); + +jng_hvgen hvgen( + .HPOS(HP), + .VPOS(VP), + .PCLK(PCLK), + .HBLK(hblank), + .VBLK(vblank), + .HSYN(hsync), + .VSYN(vsync) + ); + +//-------------------------------------------------- +// SOUND //ToDo +//-------------------------------------------------- +jng_sound jng_sound( + .clock_12(CCLKx4), + .reset(RESET), + .sound_req(sonr), + .sound_code_in(odt), + .sound_timing(snd_Wce), + .audio_out(SND) + ); + +endmodule diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jng_video.v b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jng_video.v new file mode 100644 index 00000000..e455df1d --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jng_video.v @@ -0,0 +1,194 @@ +module jng_video +( + input VCLKx4, // 24.976MHz + + input [8:0] HPOS, + input [8:0] VPOS, + output PCLK, + output reg [7:0] POUT, + + input CPUCLK, + input [15:0] CPUADDR, + input [7:0] CPUDI, + output [7:0] CPUDO, + input CPUME, + input CPUWE, + output CPUDT +); + +//----------------------------------------- +// Clock generators +//----------------------------------------- +reg VCLKx2; +always @( posedge VCLKx4 ) begin + VCLKx2 <= ~VCLKx2; +end + +reg VCLK; +always @( posedge VCLKx2 ) begin + VCLK <= ~VCLK; +end + +//----------------------------------------- +// BG scroll registers +//----------------------------------------- +reg [7:0] BGHSCR; +reg [7:0] BGVSCR; + +always @ ( posedge CPUCLK ) begin + if ( ( CPUADDR == 16'hA130 ) & CPUME & CPUWE ) begin + BGHSCR <= CPUDI-3; + end + if ( ( CPUADDR == 16'hA140 ) & CPUME & CPUWE ) begin + BGVSCR <= CPUDI; + end +end + + +//----------------------------------------- +// HV +//----------------------------------------- +wire [8:0] BGHPOS = HPOS + { 1'b0, BGHSCR }; +wire [8:0] BGVPOS = VPOS + { 1'b0, BGVSCR }; + +wire oHB = ( HPOS > 288 ) ? 1 : 0; +wire oVB = ( VPOS > 224 ) ? 1 : 0; + + +//---------------------------------------- +// VideoRAM Scanner +//---------------------------------------- +wire BF = ( HPOS >= 224 ); +wire [8:0] HP = BF ? HPOS : BGHPOS; +wire [8:0] VP = ( BF ? VPOS : BGVPOS ) + 9'h0F; + +wire [10:0] SPRAADRS; +wire [3:0] ARAMADRS; + +reg [10:0] VRAMADRS; +always @ ( HPOS ) begin + VRAMADRS <= oHB ? + SPRAADRS : + BF ? { 1'b0, VP[7:3], 2'b00, HP[5:3] } : { 1'b1, VP[7:3], HP[7:3] }; +end + +wire [7:0] CHRC; +wire [7:0] ATTR; +wire [7:0] ARDT; + +wire [7:0] V0DO, V1DO; + +wire CEV0 = ( ( CPUADDR[15:12] == 4'b1000 ) & (~CPUADDR[11]) ) & CPUME; +wire CEV1 = ( ( CPUADDR[15:12] == 4'b1000 ) & CPUADDR[11] ) & CPUME; +wire CEAT = ( CPUADDR[15:4] == 12'b1010_0000_0000 ) & CPUME; + +wire [7:0] DTV0 = CEV0 ? V0DO : 8'h00; +wire [7:0] DTV1 = CEV1 ? V1DO : 8'h00; + +assign CPUDO = DTV0 | DTV1; +assign CPUDT = ( ~CPUWE ) & ( CEV0 | CEV1 ); + +GDPRAM #(11,8) vram0( VCLKx4, VRAMADRS, CHRC, CPUCLK, CPUADDR[10:0], ( CPUWE & CEV0 ), CPUDI, V0DO ); + +GDPRAM #(11,8) vram1( VCLKx4, VRAMADRS, ATTR, CPUCLK, CPUADDR[10:0], ( CPUWE & CEV1 ), CPUDI, V1DO ); + +GDPRAM #(4,8) aram0( VCLKx4, ARAMADRS, ARDT, CPUCLK, CPUADDR[3:0], ( CPUWE & CEAT ), CPUDI ); + +wire BGF = ATTR[5]; + + +//---------------------------------------- +// BG/Sprite chip data reader +//---------------------------------------- +wire BGFX = ATTR[6]; +wire [2:0] BGFY = { ATTR[7], ATTR[7], ATTR[7] }; + +wire [11:0] SPCHRADR; +wire [11:0] CHRA = oHB ? SPCHRADR : { CHRC, ( HP[2] ^ BGFX ), ( VP[2:0] ^ BGFY ) }; + +wire [7:0] CHRO; +jng_chr_rom chrrom( + .clk(VCLKx4), + .addr(CHRA), + .data(CHRO) +); + +//---------------------------------------- +// Rader-dot chip ROM +//---------------------------------------- +wire [7:0] DROMAD; +wire [7:0] DROMDT; +jng_dot_rom dotrom( + .clk(VCLKx4), + .addr(DROMAD), + .data(DROMDT) + ); + +//---------------------------------------- +// BG/FG scanline generator +//---------------------------------------- +wire [5:0] BGPL = ATTR[5:0]; +reg [7:0] BGCOL; + +always @ ( posedge VCLK ) begin + case ( HP[1:0]^{2{BGFX}} ) + 2'b00: BGCOL <= { BGPL, CHRO[4], CHRO[0] }; + 2'b01: BGCOL <= { BGPL, CHRO[5], CHRO[1] }; + 2'b10: BGCOL <= { BGPL, CHRO[6], CHRO[2] }; + 2'b11: BGCOL <= { BGPL, CHRO[7], CHRO[3] }; + endcase +end + + +//---------------------------------------- +// Sprite Engine +//---------------------------------------- +wire [8:0] SPCOL; +jng_sprite speng( + .VCLKx4(VCLKx4), + .HBLK(oHB), + .HPOS(HPOS), + .VPOS(VPOS), + .SPRAADRS(SPRAADRS), + .SPRADATA({ ATTR, CHRC }), + .ARAMADRS(ARAMADRS), + .ARAMDATA(ARDT), + .SPCHRADR(SPCHRADR), + .SPCHRDAT(CHRO), + .DROMAD(DROMAD), + .DROMDT(DROMDT), + .SPCOL(SPCOL) + ); + + +//---------------------------------------- +// Color mixer +//---------------------------------------- +wire bBGOPAQUE = ( ( BF | BGF ) & (~SPCOL[8]) ); +wire bSPTRANSP = ( SPCOL[1:0] == 2'b00 ); + +wire [7:0] OUTCOL = ( bBGOPAQUE | bSPTRANSP ) ? BGCOL : SPCOL[7:0]; +wire [3:0] CLUT; +jng_col_rom colrom( + .clk(~VCLKx4), + .addr(OUTCOL), + .data(CLUT) + ); + +wire [4:0] PALA = SPCOL[8] ? SPCOL[4:0] : { 1'b0, CLUT }; +wire [7:0] PALO; + +jng_pal_rom palrom( + .clk(VCLKx4), + .addr(PALA), + .data(PALO) + ); + +//---------------------------------------- +// Color output +//---------------------------------------- +always @ ( posedge PCLK ) POUT <= (oHB|oVB) ? 8'h0 : PALO; +assign PCLK = VCLK; + + +endmodule diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jungler_mist.sv b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jungler_mist.sv new file mode 100644 index 00000000..ef65a4ba --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jungler_mist.sv @@ -0,0 +1,175 @@ +module jungler_mist ( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "Jungler;;", + "O2,Rotate,Off,On;", + "O34,Scanlines,None,CRT 25%,CRT 50%,CRT 75%;", + "O5,Test,Off,On;", + "O6,Service,Off,On;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + +assign LED = 1; +assign AUDIO_R = AUDIO_L; + +wire clock_24, clock_12; +pll pll( + .inclk0(CLOCK_27), + .c0(clock_24)//24.576MHz + ); + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoublerD; +wire ypbpr; +wire [10:0] audio; +wire hs, vs; +wire hb, vb; +wire blankn = ~(hb | vb); +wire [2:0] r, g; +wire [1:0] b; +wire key_strobe; +wire key_pressed; +wire [7:0] key_code; + + +wire [7:0] iDSW1 = ~{ m_down1,"0000000"}; +wire [7:0] iDSW2 = ~{ status[5], 1'b1, "000", "000"};//Test,Cab,CoinB,CoinA +wire [7:0] iCTR1 = ~{ btn_coin, 1'b0, m_right1, m_left1, m_fire1, status[6], 1'b0, m_up2}; +wire [7:0] iCTR2 = ~{ btn_one_player, btn_two_players, m_left2, m_right2, m_fire2, 1'b0, m_down2, m_up1}; + + + +jng_top jng_top( + .RESET(status[0] | status[6] | buttons[1]), + .CLK24M(clock_24), + .hsync(hs), + .vsync(vs), + .hblank(hb), + .vblank(vb), + .r(r), + .g(g), + .b(b), + .SND(audio), + .DSW1(iDSW1), + .DSW2(iDSW2), + .CTR1(iCTR1), + .CTR2(iCTR2), + .LAMP() + ); + + +mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video( + .clk_sys ( clock_24 ), + .SPI_SCK ( SPI_SCK ), + .SPI_SS3 ( SPI_SS3 ), + .SPI_DI ( SPI_DI ), + .R ( blankn ? r : 0 ), + .G ( blankn ? g : 0 ), + .B ( blankn ? {b,1'b0} : 0 ), + .HSync ( hs ), + .VSync ( vs ), + .VGA_R ( VGA_R ), + .VGA_G ( VGA_G ), + .VGA_B ( VGA_B ), + .VGA_VS ( VGA_VS ), + .VGA_HS ( VGA_HS ), + .rotate ({1'b1,status[2]} ), + .scandoubler_disable( scandoublerD ), + .scanlines ( status[4:3] ), + .ypbpr ( ypbpr ) + ); + +user_io #(.STRLEN(($size(CONF_STR)>>3)))user_io( + .clk_sys (clock_24 ), + .conf_str (CONF_STR ), + .SPI_CLK (SPI_SCK ), + .SPI_SS_IO (CONF_DATA0 ), + .SPI_MISO (SPI_DO ), + .SPI_MOSI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable (scandoublerD ), + .ypbpr (ypbpr ), + .key_strobe (key_strobe ), + .key_pressed (key_pressed ), + .key_code (key_code ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) + ); + +dac #(.C_bits(16))dac( + .clk_i(clock_24), + .res_n_i(1), + .dac_i({audio,audio[4:0]}), + .dac_o(AUDIO_L) + ); + +wire m_up1 = btn_up | joystick_0[3]; +wire m_down1 = btn_down | joystick_0[2]; +wire m_left1 = btn_left | joystick_0[1]; +wire m_right1 = btn_right | joystick_0[0]; +wire m_fire1 = btn_fire1 | joystick_0[4]; + +wire m_up2 = btn_up | joystick_1[3]; +wire m_down2 = btn_down | joystick_1[2]; +wire m_left2 = btn_left | joystick_1[1]; +wire m_right2 = btn_right | joystick_1[0]; +wire m_fire2 = btn_fire1 | joystick_1[4]; + + +reg btn_one_player = 0; +reg btn_two_players = 0; +reg btn_left = 0; +reg btn_right = 0; +reg btn_down = 0; +reg btn_up = 0; +reg btn_fire1 = 0; +//reg btn_fire2 = 0; +//reg btn_fire3 = 0; +reg btn_coin = 0; + +always @(posedge clock_24) begin + reg old_state; + old_state <= key_strobe; + if(old_state != key_strobe) begin + case(key_code) + 'h75: btn_up <= key_pressed; // up + 'h72: btn_down <= key_pressed; // down + 'h6B: btn_left <= key_pressed; // left + 'h74: btn_right <= key_pressed; // right + 'h76: btn_coin <= key_pressed; // ESC + 'h05: btn_one_player <= key_pressed; // F1 + 'h06: btn_two_players <= key_pressed; // F2 + // 'h14: btn_fire3 <= key_pressed; // ctrl + // 'h11: btn_fire2 <= key_pressed; // alt + 'h29: btn_fire1 <= key_pressed; // Space + endcase + end +end + + +endmodule diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/pll.qip b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/pll.qip new file mode 100644 index 00000000..afd958be --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/pll.v b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/pll.v new file mode 100644 index 00000000..70025276 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/pll.v @@ -0,0 +1,309 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.4 Build 182 03/12/2014 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2014 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + inclk0, + c0, + locked); + + input inclk0; + output c0; + output locked; + + wire [4:0] sub_wire0; + wire sub_wire2; + wire [0:0] sub_wire5 = 1'h0; + wire [0:0] sub_wire1 = sub_wire0[0:0]; + wire c0 = sub_wire1; + wire locked = sub_wire2; + wire sub_wire3 = inclk0; + wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; + + altpll altpll_component ( + .inclk (sub_wire4), + .clk (sub_wire0), + .locked (sub_wire2), + .activeclock (), + .areset (1'b0), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 78, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 71, + altpll_component.clk0_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_UNUSED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "78" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.576923" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "71" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.57600000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "78" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "71" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/rams.v b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/rams.v new file mode 100644 index 00000000..4d579578 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/rams.v @@ -0,0 +1,64 @@ + + + +module GSPRAM #(parameter AW,parameter DW) +( + input CL, + input [(AW-1):0] AD, + input WE, + input [(DW-1):0] DI, + output reg [(DW-1):0] DO +); + +reg [(DW-1):0] core[0:((2**AW)-1)]; + +always @(posedge CL) begin + DO <= core[AD]; + if (WE) core[AD] <= DI; +end + +endmodule + + +module GDPRAM #(parameter AW,parameter DW) +( + input CL0, + input [(AW-1):0] AD0, + output reg [(DW-1):0] DO0, + + input CL1, + input [(AW-1):0] AD1, + input WE1, + input [(DW-1):0] DI1, + output reg [(DW-1):0] DO1 +); + +reg [(DW-1):0] core[0:((2**AW)-1)]; + +always @(posedge CL0) DO0 <= core[AD0]; +always @(posedge CL1) begin DO1 <= core[AD1]; if (WE1) core[AD1] <= DI1; end + +endmodule + +/* +module GLINEBUF #(parameter AW,parameter DW) +( + input CL0, + input [(AW-1):0] AD0, + input WE0, + output reg [(DW-1):0] DO0, + + input CL1, + input [(AW-1):0] AD1, + input WE1, + input [(DW-1):0] DI1 +); + +reg [(DW-1):0] core[0:((2**AW)-1)]; + +always @(posedge CL0) begin DO0 <= core[AD0]; if (WE0) core[AD0] <= 0; end +always @(posedge CL1) if (WE1) core[AD1] <= DI1; + +endmodule*/ + + diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_chr_rom.vhd b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_chr_rom.vhd new file mode 100644 index 00000000..7936c894 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_chr_rom.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity jng_chr_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of jng_chr_rom is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"80",X"C0",X"20",X"20",X"60",X"C0",X"80",X"00",X"30",X"70",X"C0",X"80",X"80",X"70",X"30",X"00", + X"20",X"20",X"E0",X"E0",X"20",X"20",X"00",X"00",X"00",X"00",X"F0",X"F0",X"40",X"00",X"00",X"00", + X"20",X"20",X"A0",X"A0",X"E0",X"E0",X"60",X"00",X"60",X"F0",X"B0",X"90",X"90",X"C0",X"40",X"00", + X"C0",X"E0",X"20",X"20",X"20",X"60",X"40",X"00",X"80",X"D0",X"F0",X"B0",X"90",X"80",X"00",X"00", + X"80",X"E0",X"E0",X"80",X"80",X"80",X"80",X"00",X"00",X"F0",X"F0",X"C0",X"60",X"30",X"10",X"00", + X"C0",X"E0",X"20",X"20",X"20",X"60",X"40",X"00",X"10",X"B0",X"A0",X"A0",X"A0",X"E0",X"E0",X"00", + X"C0",X"E0",X"20",X"20",X"20",X"E0",X"C0",X"00",X"00",X"90",X"90",X"90",X"D0",X"70",X"30",X"00", + X"00",X"00",X"00",X"E0",X"E0",X"00",X"00",X"00",X"C0",X"E0",X"B0",X"90",X"80",X"C0",X"C0",X"00", + X"C0",X"E0",X"A0",X"A0",X"20",X"20",X"C0",X"00",X"00",X"60",X"90",X"90",X"B0",X"F0",X"60",X"00", + X"80",X"C0",X"60",X"20",X"20",X"20",X"00",X"00",X"70",X"F0",X"90",X"90",X"90",X"F0",X"60",X"00", + X"40",X"40",X"20",X"00",X"00",X"00",X"00",X"00",X"40",X"40",X"80",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"00",X"00",X"00",X"00",X"00",X"10",X"20",X"20", + X"40",X"40",X"40",X"00",X"00",X"00",X"00",X"00",X"40",X"40",X"40",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"40",X"40",X"40",X"00",X"00",X"00",X"00",X"00",X"40",X"40",X"40", + X"80",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"20",X"20",X"10",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"20",X"40",X"40",X"00",X"00",X"00",X"00",X"00",X"80",X"40",X"40", + X"00",X"00",X"00",X"00",X"90",X"F0",X"52",X"61",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"90",X"F0",X"A4",X"68", + X"30",X"20",X"28",X"28",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"40",X"41",X"41",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"0C",X"00",X"F0",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"30",X"E0",X"A4",X"78", + X"10",X"F0",X"00",X"0C",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"78",X"A4",X"E0",X"30",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"28",X"28",X"20",X"30",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"41",X"41",X"40",X"E0", + X"61",X"52",X"F0",X"90",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"68",X"A4",X"F0",X"90",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"C0",X"70",X"52",X"E1",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"00",X"F0",X"80", + X"E1",X"52",X"70",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"F0",X"00",X"03",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"81",X"F0",X"D2",X"61",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"18",X"F0",X"B4",X"68", + X"30",X"10",X"18",X"18",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"80",X"81",X"81",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"0C",X"00",X"10",X"F0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"70",X"E0",X"A4",X"69", + X"F0",X"10",X"00",X"0C",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"69",X"A4",X"E0",X"70",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"18",X"18",X"10",X"30",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"81",X"81",X"80",X"C0", + X"61",X"D2",X"F0",X"81",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"68",X"B4",X"F0",X"18",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"E0",X"70",X"52",X"69",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"00",X"80",X"F0", + X"69",X"52",X"70",X"E0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"F0",X"80",X"00",X"03",X"00",X"00",X"00",X"00", + X"00",X"77",X"44",X"44",X"77",X"00",X"77",X"44",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"EE",X"22",X"22",X"EE",X"00",X"EE",X"22", + X"44",X"77",X"00",X"55",X"55",X"55",X"77",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"22",X"EE",X"00",X"EE",X"22",X"22",X"22",X"00", + X"00",X"E0",X"C0",X"C2",X"C2",X"C0",X"E0",X"00",X"00",X"04",X"10",X"61",X"61",X"10",X"04",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"E0",X"E0",X"80",X"80",X"80",X"E0",X"E0",X"00",X"30",X"70",X"C0",X"80",X"C0",X"70",X"30",X"00", + X"C0",X"E0",X"20",X"20",X"20",X"E0",X"E0",X"00",X"60",X"F0",X"90",X"90",X"90",X"F0",X"F0",X"00", + X"40",X"60",X"20",X"20",X"60",X"C0",X"80",X"00",X"40",X"C0",X"80",X"80",X"C0",X"70",X"30",X"00", + X"80",X"C0",X"60",X"20",X"20",X"E0",X"E0",X"00",X"30",X"70",X"C0",X"80",X"80",X"F0",X"F0",X"00", + X"20",X"20",X"20",X"20",X"E0",X"E0",X"00",X"00",X"80",X"90",X"90",X"90",X"F0",X"F0",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"E0",X"E0",X"00",X"80",X"90",X"90",X"90",X"90",X"F0",X"F0",X"00", + X"E0",X"E0",X"20",X"20",X"60",X"C0",X"80",X"00",X"90",X"90",X"90",X"80",X"C0",X"70",X"30",X"00", + X"E0",X"E0",X"00",X"00",X"00",X"E0",X"E0",X"00",X"F0",X"F0",X"10",X"10",X"10",X"F0",X"F0",X"00", + X"20",X"20",X"E0",X"E0",X"20",X"20",X"00",X"00",X"80",X"80",X"F0",X"F0",X"80",X"80",X"00",X"00", + X"C0",X"E0",X"20",X"20",X"20",X"60",X"40",X"00",X"F0",X"F0",X"00",X"00",X"00",X"00",X"00",X"00", + X"20",X"60",X"E0",X"C0",X"80",X"E0",X"E0",X"00",X"80",X"C0",X"60",X"30",X"10",X"F0",X"F0",X"00", + X"20",X"20",X"20",X"20",X"E0",X"E0",X"00",X"00",X"00",X"00",X"00",X"00",X"F0",X"F0",X"00",X"00", + X"E0",X"E0",X"00",X"80",X"00",X"E0",X"E0",X"00",X"F0",X"F0",X"70",X"30",X"70",X"F0",X"F0",X"00", + X"E0",X"E0",X"C0",X"80",X"00",X"E0",X"E0",X"00",X"F0",X"F0",X"10",X"30",X"70",X"F0",X"F0",X"00", + X"C0",X"E0",X"20",X"20",X"20",X"E0",X"C0",X"00",X"70",X"F0",X"80",X"80",X"80",X"F0",X"70",X"00", + X"00",X"80",X"80",X"80",X"80",X"E0",X"E0",X"00",X"70",X"F0",X"80",X"80",X"80",X"F0",X"F0",X"00", + X"A0",X"C0",X"E0",X"A0",X"20",X"E0",X"C0",X"00",X"70",X"F0",X"80",X"80",X"80",X"F0",X"70",X"00", + X"20",X"60",X"E0",X"C0",X"80",X"E0",X"E0",X"00",X"70",X"F0",X"90",X"80",X"80",X"F0",X"F0",X"00", + X"C0",X"E0",X"20",X"20",X"20",X"60",X"40",X"00",X"00",X"50",X"D0",X"90",X"90",X"F0",X"60",X"00", + X"00",X"00",X"E0",X"E0",X"00",X"00",X"00",X"00",X"80",X"80",X"F0",X"F0",X"80",X"80",X"00",X"00", + X"C0",X"E0",X"20",X"20",X"20",X"E0",X"C0",X"00",X"F0",X"F0",X"00",X"00",X"00",X"F0",X"F0",X"00", + X"00",X"80",X"C0",X"E0",X"C0",X"80",X"00",X"00",X"F0",X"F0",X"10",X"00",X"10",X"F0",X"F0",X"00", + X"E0",X"E0",X"C0",X"80",X"C0",X"E0",X"E0",X"00",X"F0",X"F0",X"10",X"30",X"10",X"F0",X"F0",X"00", + X"60",X"E0",X"C0",X"80",X"C0",X"E0",X"60",X"00",X"C0",X"E0",X"70",X"30",X"70",X"E0",X"C0",X"00", + X"00",X"00",X"E0",X"E0",X"00",X"00",X"00",X"00",X"E0",X"F0",X"10",X"10",X"F0",X"E0",X"00",X"00", + X"20",X"20",X"20",X"A0",X"E0",X"E0",X"60",X"00",X"C0",X"E0",X"F0",X"B0",X"90",X"80",X"80",X"00", + X"00",X"00",X"00",X"60",X"60",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"C0",X"20",X"10",X"50",X"50",X"90",X"20",X"C0",X"30",X"40",X"80",X"A0",X"A0",X"90",X"40",X"30", + X"C0",X"E8",X"E4",X"E0",X"E0",X"E0",X"C0",X"00",X"30",X"79",X"78",X"FC",X"78",X"78",X"30",X"00", + X"E0",X"C0",X"68",X"E0",X"68",X"C0",X"E0",X"00",X"00",X"10",X"F0",X"21",X"F0",X"10",X"00",X"00", + X"C0",X"20",X"80",X"C0",X"80",X"20",X"C0",X"00",X"10",X"30",X"70",X"F0",X"70",X"30",X"10",X"00", + X"00",X"00",X"00",X"00",X"10",X"00",X"3F",X"56",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"11", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"08",X"08",X"4F",X"A6", + X"25",X"2A",X"8B",X"26",X"15",X"00",X"00",X"00",X"11",X"11",X"01",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"A2",X"4C",X"84",X"82",X"88",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"3B",X"AC",X"8A",X"98",X"00",X"00",X"00",X"00",X"01",X"00",X"00",X"00", + X"00",X"00",X"00",X"04",X"08",X"88",X"88",X"00",X"00",X"00",X"00",X"04",X"15",X"8B",X"14",X"18", + X"51",X"46",X"0D",X"A9",X"66",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"00",X"00",X"00",X"00", + X"04",X"08",X"00",X"00",X"00",X"00",X"00",X"00",X"8B",X"E2",X"26",X"C6",X"09",X"08",X"00",X"00", + X"00",X"00",X"11",X"2A",X"49",X"21",X"95",X"45",X"00",X"02",X"01",X"00",X"00",X"11",X"23",X"22", + X"00",X"00",X"00",X"00",X"02",X"0C",X"88",X"88",X"00",X"02",X"8A",X"45",X"C6",X"11",X"AD",X"C4", + X"5C",X"26",X"90",X"04",X"8A",X"01",X"01",X"00",X"11",X"01",X"02",X"13",X"04",X"00",X"00",X"00", + X"00",X"06",X"08",X"00",X"00",X"08",X"08",X"00",X"A8",X"0A",X"91",X"66",X"81",X"00",X"00",X"00", + X"00",X"18",X"AC",X"84",X"13",X"38",X"91",X"23",X"01",X"00",X"11",X"2E",X"47",X"54",X"40",X"06", + X"09",X"0A",X"02",X"05",X"08",X"00",X"0C",X"03",X"04",X"04",X"05",X"CE",X"3E",X"31",X"39",X"89", + X"2F",X"59",X"42",X"A8",X"6F",X"10",X"01",X"01",X"3A",X"32",X"11",X"05",X"08",X"01",X"01",X"01", + X"88",X"C4",X"4C",X"8E",X"01",X"00",X"00",X"00",X"BA",X"32",X"4D",X"06",X"B3",X"4A",X"01",X"01", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"02",X"04",X"00",X"64",X"00",X"40",X"02",X"00",X"18",X"40",X"01",X"D5",X"01",X"04",X"18", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"18",X"F0",X"B4",X"68",X"C0",X"80",X"81",X"81",X"81",X"F0",X"D2",X"61",X"30",X"10",X"18",X"18", + X"90",X"F0",X"A4",X"68",X"C0",X"40",X"41",X"41",X"90",X"F0",X"52",X"61",X"30",X"20",X"28",X"28", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"21",X"43",X"53",X"E1",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"88",X"0C",X"0E",X"4F", + X"D3",X"61",X"43",X"21",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"2E",X"8C",X"08",X"00",X"00",X"00",X"00", + X"00",X"80",X"C0",X"E0",X"E0",X"C0",X"80",X"00",X"00",X"10",X"30",X"70",X"70",X"30",X"10",X"00", + X"80",X"C0",X"E0",X"E0",X"C0",X"80",X"00",X"00",X"10",X"30",X"70",X"70",X"30",X"10",X"00",X"00", + X"C0",X"E0",X"E0",X"E0",X"C0",X"00",X"00",X"08",X"70",X"70",X"70",X"30",X"10",X"00",X"00",X"03", + X"E0",X"E0",X"E0",X"C0",X"00",X"00",X"08",X"0C",X"70",X"70",X"30",X"10",X"00",X"00",X"03",X"07", + X"E0",X"C0",X"80",X"00",X"00",X"08",X"0C",X"0E",X"70",X"30",X"10",X"00",X"00",X"01",X"03",X"07", + X"C0",X"80",X"00",X"00",X"08",X"0C",X"0E",X"0E",X"30",X"10",X"00",X"00",X"01",X"03",X"07",X"07", + X"80",X"00",X"00",X"0C",X"0E",X"0E",X"0E",X"0C",X"30",X"00",X"00",X"01",X"03",X"07",X"07",X"07", + X"00",X"00",X"0C",X"0E",X"0E",X"0E",X"0C",X"08",X"00",X"00",X"01",X"03",X"07",X"07",X"07",X"03", + X"00",X"80",X"C0",X"E0",X"E0",X"C0",X"80",X"00",X"00",X"10",X"30",X"70",X"70",X"30",X"10",X"00", + X"00",X"00",X"80",X"C0",X"C0",X"80",X"00",X"00",X"00",X"30",X"70",X"F0",X"F0",X"70",X"30",X"00", + X"00",X"00",X"80",X"81",X"81",X"01",X"00",X"00",X"00",X"70",X"F0",X"F0",X"F0",X"F0",X"E0",X"00", + X"00",X"00",X"01",X"03",X"03",X"03",X"01",X"00",X"00",X"E0",X"F0",X"F0",X"F0",X"E0",X"C0",X"00", + X"00",X"01",X"03",X"07",X"07",X"03",X"01",X"00",X"00",X"80",X"C0",X"E0",X"E0",X"C0",X"80",X"00", + X"00",X"03",X"07",X"0F",X"0F",X"07",X"03",X"00",X"00",X"00",X"80",X"C0",X"C0",X"80",X"00",X"00", + X"00",X"0E",X"0F",X"0F",X"0F",X"0F",X"07",X"00",X"00",X"00",X"01",X"81",X"81",X"80",X"00",X"00", + X"00",X"0C",X"0E",X"0F",X"0F",X"0F",X"0E",X"00",X"00",X"01",X"03",X"03",X"03",X"01",X"00",X"00", + X"C0",X"E0",X"F0",X"F0",X"E0",X"C0",X"00",X"00",X"00",X"10",X"30",X"30",X"10",X"00",X"00",X"00", + X"80",X"C0",X"E0",X"E0",X"C0",X"80",X"00",X"00",X"10",X"30",X"70",X"70",X"30",X"10",X"00",X"00", + X"C0",X"E0",X"E0",X"C1",X"81",X"00",X"00",X"00",X"30",X"70",X"70",X"30",X"10",X"00",X"00",X"00", + X"E0",X"E0",X"C1",X"83",X"03",X"01",X"00",X"00",X"70",X"70",X"30",X"10",X"00",X"00",X"00",X"00", + X"E0",X"C1",X"83",X"07",X"07",X"03",X"01",X"00",X"70",X"30",X"10",X"00",X"00",X"00",X"00",X"00", + X"C0",X"83",X"07",X"0F",X"0F",X"07",X"03",X"00",X"30",X"10",X"00",X"00",X"00",X"00",X"00",X"00", + X"80",X"06",X"0F",X"0F",X"0F",X"0F",X"06",X"00",X"10",X"00",X"00",X"01",X"01",X"00",X"00",X"00", + X"00",X"0C",X"0E",X"0F",X"0F",X"0E",X"0C",X"00",X"00",X"00",X"01",X"03",X"03",X"01",X"00",X"00", + X"C0",X"E0",X"F0",X"F0",X"E0",X"C0",X"00",X"00",X"00",X"10",X"30",X"30",X"10",X"00",X"00",X"00", + X"00",X"C0",X"E0",X"F0",X"F0",X"E0",X"C0",X"00",X"00",X"00",X"10",X"30",X"30",X"10",X"00",X"00", + X"08",X"60",X"F0",X"F0",X"F0",X"F0",X"60",X"00",X"01",X"00",X"00",X"10",X"10",X"00",X"00",X"00", + X"0C",X"38",X"70",X"F0",X"F0",X"70",X"30",X"00",X"03",X"01",X"00",X"00",X"00",X"00",X"00",X"00", + X"0E",X"1C",X"38",X"70",X"70",X"30",X"10",X"00",X"07",X"03",X"01",X"00",X"00",X"00",X"00",X"00", + X"0E",X"0E",X"1C",X"38",X"30",X"10",X"00",X"00",X"07",X"07",X"03",X"01",X"00",X"00",X"00",X"00", + X"0C",X"0E",X"0E",X"1C",X"18",X"00",X"00",X"00",X"03",X"07",X"07",X"03",X"01",X"00",X"00",X"00", + X"08",X"0C",X"0E",X"0E",X"0C",X"08",X"00",X"00",X"01",X"03",X"07",X"07",X"03",X"01",X"00",X"00", + X"00",X"80",X"C0",X"E0",X"E0",X"C0",X"80",X"00",X"00",X"10",X"30",X"70",X"70",X"30",X"10",X"00", + X"80",X"C0",X"E0",X"E0",X"C0",X"80",X"00",X"00",X"10",X"30",X"70",X"70",X"30",X"10",X"00",X"00", + X"C0",X"E0",X"E0",X"E0",X"C0",X"00",X"00",X"08",X"70",X"70",X"70",X"30",X"10",X"00",X"00",X"01", + X"E0",X"E0",X"E0",X"C0",X"00",X"00",X"08",X"0C",X"70",X"70",X"30",X"10",X"00",X"00",X"01",X"03", + X"E0",X"C0",X"80",X"00",X"00",X"08",X"0C",X"0E",X"70",X"30",X"10",X"00",X"00",X"01",X"03",X"07", + X"C0",X"80",X"00",X"00",X"08",X"0C",X"0E",X"0F",X"30",X"10",X"00",X"00",X"01",X"03",X"07",X"0F", + X"80",X"00",X"00",X"08",X"0C",X"0E",X"0F",X"0D",X"30",X"00",X"00",X"01",X"03",X"07",X"0F",X"0B", + X"00",X"00",X"08",X"0C",X"0E",X"0F",X"0D",X"09",X"00",X"00",X"01",X"03",X"07",X"0F",X"0B",X"09", + X"00",X"80",X"C0",X"E0",X"E0",X"C0",X"80",X"00",X"00",X"10",X"30",X"70",X"70",X"30",X"10",X"00", + X"00",X"00",X"80",X"C0",X"C0",X"80",X"00",X"00",X"00",X"30",X"70",X"F0",X"F0",X"70",X"30",X"00", + X"00",X"00",X"80",X"81",X"81",X"00",X"00",X"00",X"00",X"70",X"F0",X"F0",X"F0",X"F0",X"E0",X"00", + X"00",X"00",X"01",X"03",X"03",X"01",X"00",X"00",X"00",X"E0",X"F0",X"F0",X"F0",X"E0",X"C0",X"00", + X"00",X"01",X"03",X"07",X"07",X"03",X"01",X"00",X"00",X"80",X"C0",X"E0",X"E0",X"C0",X"80",X"00", + X"01",X"03",X"07",X"0F",X"0F",X"07",X"03",X"01",X"00",X"00",X"80",X"C0",X"C0",X"80",X"00",X"00", + X"03",X"06",X"0F",X"0F",X"0F",X"0F",X"06",X"03",X"00",X"00",X"00",X"81",X"81",X"80",X"00",X"00", + X"07",X"0C",X"0E",X"0F",X"0F",X"0E",X"0C",X"07",X"00",X"00",X"01",X"03",X"03",X"01",X"00",X"00", + X"C0",X"E0",X"F0",X"F0",X"E0",X"C0",X"00",X"00",X"00",X"10",X"30",X"30",X"10",X"00",X"00",X"00", + X"80",X"C0",X"E0",X"E0",X"C0",X"80",X"00",X"00",X"10",X"30",X"70",X"70",X"30",X"10",X"00",X"00", + X"C0",X"E0",X"E0",X"C1",X"81",X"00",X"00",X"00",X"30",X"70",X"70",X"30",X"10",X"00",X"00",X"00", + X"E0",X"E0",X"C1",X"83",X"03",X"01",X"00",X"00",X"70",X"70",X"30",X"10",X"00",X"00",X"00",X"00", + X"E0",X"C1",X"83",X"07",X"07",X"03",X"01",X"00",X"70",X"30",X"10",X"00",X"00",X"00",X"00",X"00", + X"C1",X"83",X"07",X"0F",X"0F",X"07",X"03",X"01",X"30",X"10",X"00",X"00",X"00",X"00",X"00",X"00", + X"83",X"06",X"0F",X"0F",X"0F",X"0F",X"06",X"03",X"10",X"00",X"00",X"01",X"01",X"00",X"00",X"00", + X"07",X"0C",X"0E",X"0F",X"0F",X"0E",X"0C",X"07",X"00",X"00",X"01",X"03",X"03",X"01",X"00",X"00", + X"C0",X"E0",X"F0",X"F0",X"E0",X"C0",X"00",X"00",X"00",X"10",X"30",X"30",X"10",X"00",X"00",X"00", + X"00",X"C0",X"E0",X"F0",X"F0",X"E0",X"C0",X"00",X"00",X"00",X"10",X"30",X"30",X"10",X"00",X"00", + X"08",X"60",X"F0",X"F0",X"F0",X"F0",X"60",X"00",X"01",X"00",X"00",X"10",X"10",X"00",X"00",X"00", + X"0C",X"38",X"70",X"F0",X"F0",X"70",X"30",X"00",X"03",X"01",X"00",X"00",X"00",X"00",X"00",X"00", + X"0E",X"1C",X"38",X"70",X"70",X"30",X"10",X"00",X"07",X"03",X"01",X"00",X"00",X"00",X"00",X"00", + X"0F",X"0E",X"1C",X"38",X"30",X"10",X"00",X"00",X"0F",X"07",X"03",X"01",X"00",X"00",X"00",X"00", + X"0D",X"0F",X"0E",X"1C",X"18",X"00",X"00",X"00",X"0B",X"0F",X"07",X"03",X"01",X"00",X"00",X"00", + X"09",X"0D",X"0F",X"0E",X"0C",X"08",X"00",X"00",X"09",X"0B",X"0F",X"07",X"03",X"01",X"00",X"00", + X"00",X"80",X"C0",X"E0",X"F0",X"D0",X"90",X"20",X"00",X"10",X"30",X"70",X"F0",X"B0",X"90",X"40", + X"80",X"C0",X"E0",X"F0",X"D0",X"90",X"20",X"00",X"10",X"30",X"70",X"F0",X"B0",X"90",X"40",X"00", + X"C0",X"E0",X"F0",X"D0",X"90",X"20",X"00",X"00",X"30",X"70",X"F0",X"B0",X"90",X"40",X"00",X"00", + X"E0",X"F0",X"D0",X"90",X"20",X"00",X"00",X"00",X"70",X"F0",X"B0",X"90",X"40",X"00",X"00",X"00", + X"F0",X"D0",X"90",X"20",X"00",X"00",X"00",X"00",X"F0",X"B0",X"90",X"40",X"00",X"00",X"00",X"00", + X"D0",X"90",X"20",X"00",X"00",X"00",X"00",X"00",X"B0",X"90",X"40",X"00",X"00",X"00",X"00",X"00", + X"90",X"20",X"00",X"00",X"00",X"00",X"00",X"00",X"90",X"40",X"00",X"00",X"00",X"00",X"00",X"00", + X"20",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"E0",X"90",X"C0",X"E0",X"E0",X"C0",X"90",X"E0",X"00",X"10",X"30",X"70",X"70",X"30",X"10",X"00", + X"C0",X"20",X"80",X"C0",X"C0",X"80",X"20",X"C0",X"10",X"30",X"70",X"F0",X"F0",X"70",X"30",X"10", + X"80",X"40",X"00",X"80",X"80",X"00",X"40",X"80",X"30",X"60",X"F0",X"F0",X"F0",X"F0",X"60",X"30", + X"00",X"80",X"00",X"00",X"00",X"00",X"80",X"00",X"70",X"C0",X"E0",X"F0",X"F0",X"E0",X"C0",X"70", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"E0",X"90",X"C0",X"E0",X"E0",X"C0",X"90",X"E0", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"20",X"80",X"C0",X"C0",X"80",X"20",X"C0", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"40",X"00",X"80",X"80",X"00",X"40",X"80", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"00",X"00",X"00",X"00",X"80",X"00", + X"80",X"C0",X"E0",X"F0",X"D0",X"90",X"20",X"00",X"10",X"30",X"70",X"F0",X"B0",X"90",X"40",X"00", + X"80",X"C0",X"E0",X"F0",X"D0",X"90",X"20",X"00",X"10",X"30",X"70",X"F0",X"B0",X"90",X"40",X"00", + X"C0",X"E0",X"F0",X"D0",X"90",X"20",X"00",X"00",X"30",X"70",X"F0",X"B0",X"90",X"40",X"00",X"00", + X"E0",X"F0",X"D0",X"90",X"20",X"00",X"00",X"00",X"70",X"F0",X"B0",X"90",X"40",X"00",X"00",X"00", + X"F0",X"D0",X"90",X"20",X"00",X"00",X"00",X"00",X"F0",X"B0",X"90",X"40",X"00",X"00",X"00",X"00", + X"D0",X"90",X"20",X"00",X"00",X"00",X"00",X"00",X"B0",X"90",X"40",X"00",X"00",X"00",X"00",X"00", + X"90",X"20",X"00",X"00",X"00",X"00",X"00",X"00",X"90",X"40",X"00",X"00",X"00",X"00",X"00",X"00", + X"20",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"80",X"C0",X"E0",X"F0",X"F0",X"E0",X"C0",X"80",X"30",X"40",X"10",X"30",X"30",X"10",X"40",X"30", + X"80",X"C0",X"E0",X"F0",X"F0",X"E0",X"C0",X"80",X"30",X"40",X"10",X"30",X"30",X"10",X"40",X"30", + X"C0",X"60",X"F0",X"F0",X"F0",X"F0",X"60",X"C0",X"10",X"20",X"00",X"10",X"10",X"00",X"20",X"10", + X"E0",X"30",X"70",X"F0",X"F0",X"70",X"30",X"E0",X"00",X"10",X"00",X"00",X"00",X"00",X"10",X"00", + X"70",X"90",X"30",X"70",X"70",X"30",X"90",X"70",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"30",X"40",X"10",X"30",X"30",X"10",X"40",X"30",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"10",X"20",X"00",X"10",X"10",X"00",X"20",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"10",X"00",X"00",X"00",X"00",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"50",X"A0",X"50",X"A0",X"50",X"A0",X"F0",X"00",X"50",X"60",X"50",X"60",X"50",X"20",X"10",X"00", + X"00",X"F0",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"00",X"10",X"20",X"50",X"60",X"50",X"60",X"50", + X"A0",X"60",X"A0",X"60",X"A0",X"40",X"80",X"00",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"F0",X"00", + X"00",X"80",X"40",X"A0",X"60",X"A0",X"60",X"A0",X"00",X"F0",X"50",X"A0",X"50",X"A0",X"50",X"A0", + X"A0",X"50",X"A0",X"50",X"A0",X"50",X"F0",X"00",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"F0",X"00", + X"00",X"F0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"00",X"F0",X"50",X"A0",X"50",X"A0",X"50",X"A0", + X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"60",X"50",X"60",X"50",X"60",X"50",X"60",X"50", + X"60",X"A0",X"60",X"A0",X"60",X"A0",X"60",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0", + X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"20", + X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"20",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50", + X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"40",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50", + X"40",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0", + X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50", + X"C0",X"20",X"50",X"90",X"90",X"50",X"20",X"C0",X"30",X"40",X"A0",X"90",X"90",X"A0",X"40",X"30", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"20",X"40",X"20",X"90",X"20",X"40",X"20",X"90",X"50",X"A0",X"50",X"20",X"50",X"A0",X"50",X"20", + X"20",X"50",X"A0",X"50",X"80",X"20",X"50",X"80",X"20",X"50",X"A0",X"50",X"80",X"20",X"50",X"80", + X"20",X"50",X"A0",X"50",X"00",X"20",X"10",X"A0",X"20",X"90",X"40",X"20",X"50",X"A0",X"50",X"20", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_col_rom.vhd b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_col_rom.vhd new file mode 100644 index 00000000..49e9603b --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_col_rom.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity jng_col_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of jng_col_rom is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"0F",X"00",X"00",X"01",X"0F",X"00",X"00",X"02",X"0F",X"00",X"00",X"04",X"0F", + X"00",X"00",X"0C",X"0F",X"00",X"00",X"0E",X"0F",X"00",X"00",X"0F",X"0F",X"00",X"01",X"00",X"0F", + X"00",X"01",X"01",X"0F",X"00",X"01",X"02",X"0F",X"00",X"01",X"04",X"0F",X"00",X"01",X"0C",X"0F", + X"00",X"01",X"0E",X"0F",X"00",X"01",X"0F",X"0F",X"00",X"02",X"00",X"0F",X"00",X"02",X"01",X"0F", + X"00",X"02",X"02",X"0F",X"00",X"02",X"04",X"0F",X"00",X"02",X"0C",X"0F",X"00",X"02",X"0E",X"0F", + X"00",X"02",X"0F",X"0F",X"00",X"04",X"00",X"0F",X"00",X"04",X"01",X"0F",X"00",X"04",X"02",X"0F", + X"00",X"04",X"04",X"0F",X"00",X"04",X"0C",X"0F",X"00",X"04",X"0E",X"0F",X"00",X"04",X"0F",X"0F", + X"00",X"0C",X"00",X"0F",X"00",X"0C",X"01",X"0F",X"00",X"0C",X"02",X"0F",X"00",X"0C",X"04",X"0F", + X"00",X"0C",X"0C",X"0F",X"00",X"0C",X"0E",X"0F",X"00",X"0C",X"0F",X"0F",X"00",X"0E",X"00",X"0F", + X"00",X"0E",X"01",X"0F",X"00",X"0E",X"02",X"0F",X"00",X"0E",X"04",X"0F",X"00",X"0E",X"0C",X"0F", + X"00",X"0E",X"0E",X"0F",X"00",X"0E",X"0F",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"01",X"0F", + X"00",X"0F",X"02",X"0F",X"00",X"0F",X"04",X"0F",X"00",X"0F",X"0C",X"0F",X"00",X"0F",X"0E",X"0F", + X"00",X"0F",X"0F",X"0F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"01",X"02",X"09",X"00",X"0F",X"09",X"02",X"00",X"02",X"01",X"04", + X"00",X"0C",X"0F",X"0A",X"00",X"07",X"05",X"08",X"00",X"0D",X"04",X"06",X"00",X"02",X"04",X"0B"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_dot_rom.vhd b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_dot_rom.vhd new file mode 100644 index 00000000..74c632c5 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_dot_rom.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity jng_dot_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of jng_dot_rom is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"02",X"02",X"00",X"00",X"02",X"02",X"00",X"00",X"00",X"00",X"00", + X"00",X"02",X"02",X"00",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"00",X"02",X"02",X"00", + X"00",X"02",X"02",X"00",X"02",X"01",X"01",X"02",X"02",X"01",X"01",X"02",X"00",X"02",X"02",X"00", + X"00",X"00",X"00",X"00",X"00",X"02",X"00",X"00",X"02",X"02",X"02",X"00",X"00",X"02",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"00",X"00",X"01",X"01",X"00",X"00",X"00",X"00",X"00", + X"00",X"01",X"01",X"00",X"01",X"01",X"01",X"01",X"01",X"00",X"01",X"01",X"00",X"01",X"01",X"00", + X"00",X"01",X"01",X"00",X"01",X"02",X"02",X"01",X"01",X"02",X"02",X"01",X"00",X"01",X"01",X"00", + X"00",X"00",X"00",X"00",X"00",X"01",X"00",X"00",X"01",X"01",X"01",X"00",X"00",X"01",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"02",X"02",X"00",X"00",X"02",X"02",X"00",X"00",X"00",X"00",X"00", + X"00",X"02",X"02",X"00",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"00",X"02",X"02",X"00", + X"00",X"02",X"02",X"00",X"02",X"01",X"01",X"02",X"02",X"01",X"01",X"02",X"00",X"02",X"02",X"00", + X"00",X"00",X"00",X"00",X"00",X"02",X"00",X"00",X"02",X"02",X"02",X"00",X"00",X"02",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"00",X"00",X"01",X"01",X"00",X"00",X"00",X"00",X"00", + X"00",X"01",X"01",X"00",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"00",X"01",X"01",X"00", + X"00",X"01",X"01",X"00",X"01",X"02",X"02",X"01",X"01",X"02",X"02",X"01",X"00",X"01",X"01",X"00", + X"00",X"00",X"00",X"00",X"00",X"01",X"00",X"00",X"01",X"01",X"01",X"00",X"00",X"01",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_pal_rom.vhd b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_pal_rom.vhd new file mode 100644 index 00000000..78dca849 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_pal_rom.vhd @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity jng_pal_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of jng_pal_rom is + type rom is array(0 to 31) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"07",X"38",X"3C",X"3F",X"8C",X"E0",X"27",X"AA",X"8C",X"1F",X"B6",X"C0",X"C7",X"F8",X"FE", + X"00",X"3F",X"FE",X"67",X"00",X"3F",X"FE",X"67",X"00",X"3F",X"FE",X"67",X"00",X"3F",X"FE",X"67"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_prg_rom.vhd b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_prg_rom.vhd new file mode 100644 index 00000000..7b2b0c96 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_prg_rom.vhd @@ -0,0 +1,1046 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity jng_prg_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of jng_prg_rom is + type rom is array(0 to 16383) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"AF",X"32",X"81",X"A1",X"C3",X"24",X"14",X"FF",X"85",X"6F",X"D0",X"24",X"C9",X"FF",X"FF",X"FF", + X"7B",X"C6",X"20",X"5F",X"D0",X"14",X"C9",X"FF",X"87",X"CF",X"5E",X"23",X"56",X"C9",X"FF",X"FF", + X"7D",X"D6",X"20",X"6F",X"D0",X"25",X"C9",X"FF",X"7B",X"D6",X"20",X"5F",X"D0",X"15",X"C9",X"FF", + X"E1",X"DF",X"EB",X"E9",X"FF",X"FF",X"FF",X"FF",X"7E",X"FE",X"40",X"C8",X"12",X"23",X"D7",X"18", + X"F7",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"AF",X"32",X"81",X"A1",X"32",X"80",X"A0",X"3A",X"2C",X"99", + X"32",X"30",X"A1",X"3A",X"2D",X"99",X"32",X"40",X"A1",X"21",X"00",X"9C",X"11",X"14",X"80",X"01", + X"0C",X"00",X"ED",X"B0",X"21",X"10",X"9C",X"11",X"14",X"88",X"01",X"0C",X"00",X"ED",X"B0",X"21", + X"24",X"9C",X"11",X"34",X"80",X"01",X"08",X"00",X"ED",X"B0",X"21",X"34",X"9C",X"11",X"34",X"88", + X"01",X"08",X"00",X"ED",X"B0",X"21",X"44",X"9C",X"11",X"34",X"A0",X"01",X"08",X"00",X"ED",X"B0", + X"CD",X"5E",X"2D",X"CD",X"84",X"2D",X"3A",X"00",X"A0",X"2F",X"32",X"03",X"98",X"3A",X"80",X"A0", + X"2F",X"32",X"04",X"98",X"3A",X"00",X"A1",X"2F",X"32",X"05",X"98",X"CD",X"C2",X"2F",X"CD",X"0E", + X"30",X"CD",X"DB",X"2F",X"21",X"E8",X"00",X"E5",X"3A",X"20",X"99",X"F7",X"D4",X"01",X"01",X"04", + X"D0",X"07",X"35",X"0A",X"D0",X"0C",X"6B",X"0E",X"CD",X"69",X"30",X"CD",X"8D",X"30",X"CD",X"5F", + X"33",X"21",X"02",X"98",X"34",X"21",X"00",X"98",X"7E",X"A7",X"28",X"01",X"35",X"2A",X"06",X"98", + X"7C",X"B5",X"28",X"04",X"2B",X"22",X"06",X"98",X"3E",X"01",X"32",X"81",X"A1",X"C9",X"4A",X"55", + X"4E",X"47",X"4C",X"45",X"52",X"40",X"43",X"52",X"45",X"44",X"49",X"54",X"40",X"4C",X"4F",X"4F", + X"50",X"20",X"40",X"42",X"4F",X"4D",X"42",X"20",X"54",X"49",X"4D",X"45",X"52",X"20",X"40",X"48", + X"49",X"20",X"53",X"43",X"4F",X"52",X"45",X"40",X"50",X"55",X"53",X"48",X"20",X"53",X"54",X"41", + X"52",X"54",X"20",X"42",X"55",X"54",X"54",X"4F",X"4E",X"40",X"4F",X"4E",X"45",X"20",X"50",X"4C", + X"41",X"59",X"45",X"52",X"20",X"4F",X"4E",X"4C",X"59",X"20",X"20",X"20",X"40",X"4F",X"4E",X"45", + X"20",X"4F",X"52",X"20",X"54",X"57",X"4F",X"20",X"50",X"4C",X"41",X"59",X"45",X"52",X"53",X"40", + X"4F",X"4E",X"45",X"40",X"54",X"57",X"4F",X"40",X"01",X"55",X"50",X"40",X"02",X"55",X"50",X"40", + X"47",X"41",X"4D",X"45",X"20",X"4F",X"56",X"45",X"52",X"40",X"53",X"43",X"4F",X"52",X"45",X"20", + X"52",X"41",X"4E",X"4B",X"49",X"4E",X"47",X"40",X"50",X"4C",X"41",X"59",X"45",X"52",X"40",X"45", + X"4E",X"44",X"40",X"45",X"4E",X"45",X"4D",X"59",X"40",X"50",X"4F",X"49",X"4E",X"54",X"53",X"40", + X"5C",X"20",X"4B",X"4F",X"4E",X"41",X"4D",X"49",X"20",X"01",X"09",X"08",X"01",X"40",X"50",X"4C", + X"41",X"59",X"45",X"52",X"20",X"4F",X"4E",X"45",X"40",X"50",X"4C",X"41",X"59",X"45",X"52",X"20", + X"54",X"57",X"4F",X"40",X"21",X"F0",X"01",X"E5",X"3A",X"21",X"99",X"F7",X"F1",X"01",X"1B",X"02", + X"27",X"02",X"34",X"02",X"44",X"02",X"56",X"02",X"67",X"02",X"6E",X"02",X"97",X"02",X"F8",X"02", + X"C9",X"3E",X"01",X"32",X"83",X"A1",X"32",X"2F",X"99",X"CD",X"0A",X"02",X"CD",X"05",X"1B",X"3E", + X"1E",X"32",X"00",X"98",X"CD",X"1B",X"03",X"C3",X"FC",X"03",X"CD",X"84",X"1A",X"21",X"0E",X"01", + X"11",X"85",X"81",X"0E",X"BA",X"CD",X"DA",X"16",X"C3",X"48",X"30",X"3A",X"00",X"98",X"A7",X"C0", + X"CD",X"D1",X"1A",X"C0",X"C3",X"FC",X"03",X"3A",X"23",X"99",X"A7",X"CA",X"FC",X"03",X"3E",X"07", + X"32",X"21",X"99",X"C9",X"3A",X"23",X"99",X"A7",X"20",X"F4",X"AF",X"32",X"21",X"99",X"3E",X"05", + X"32",X"20",X"99",X"C9",X"3A",X"23",X"99",X"A7",X"20",X"E4",X"CD",X"B9",X"19",X"D8",X"3E",X"FF", + X"32",X"00",X"98",X"C3",X"FC",X"03",X"3A",X"23",X"99",X"A7",X"20",X"05",X"3A",X"00",X"98",X"A7", + X"C0",X"CD",X"1B",X"03",X"C3",X"FC",X"03",X"CD",X"D1",X"1A",X"C0",X"C3",X"FC",X"03",X"3A",X"23", + X"99",X"A7",X"20",X"0A",X"AF",X"32",X"21",X"99",X"3E",X"04",X"32",X"20",X"99",X"C9",X"3E",X"01", + X"32",X"83",X"A1",X"32",X"2F",X"99",X"21",X"38",X"01",X"11",X"16",X"85",X"0E",X"A3",X"CD",X"DA", + X"16",X"CD",X"17",X"0F",X"C3",X"FC",X"03",X"CD",X"75",X"03",X"11",X"15",X"85",X"3A",X"23",X"99", + X"FE",X"01",X"20",X"05",X"21",X"4A",X"01",X"18",X"03",X"21",X"5D",X"01",X"0E",X"A3",X"CD",X"DA", + X"16",X"3A",X"04",X"98",X"E6",X"C0",X"C8",X"21",X"23",X"99",X"E6",X"80",X"28",X"0C",X"7E",X"D6", + X"01",X"27",X"77",X"3E",X"00",X"32",X"10",X"99",X"18",X"13",X"7E",X"FE",X"02",X"D8",X"D6",X"01", + X"27",X"D6",X"01",X"27",X"77",X"CD",X"4E",X"03",X"3E",X"01",X"32",X"10",X"99",X"AF",X"32",X"11", + X"99",X"CD",X"27",X"03",X"CD",X"48",X"30",X"CD",X"AD",X"1A",X"CD",X"FB",X"33",X"3E",X"1E",X"32", + X"00",X"98",X"CD",X"1B",X"03",X"C3",X"FC",X"03",X"3A",X"00",X"98",X"A7",X"C0",X"CD",X"D1",X"1A", + X"C0",X"21",X"A2",X"88",X"11",X"20",X"00",X"06",X"03",X"36",X"8E",X"19",X"10",X"FB",X"21",X"62", + X"8B",X"06",X"03",X"36",X"8E",X"19",X"10",X"FB",X"C3",X"F4",X"03",X"3E",X"20",X"32",X"01",X"98", + X"21",X"00",X"84",X"22",X"52",X"98",X"C9",X"3E",X"03",X"32",X"00",X"9F",X"AF",X"32",X"01",X"9F", + X"32",X"02",X"9F",X"32",X"0A",X"9F",X"3A",X"34",X"99",X"A7",X"28",X"05",X"3E",X"FF",X"32",X"00", + X"9F",X"21",X"01",X"9F",X"34",X"CD",X"94",X"03",X"3E",X"0A",X"32",X"03",X"9F",X"C9",X"3E",X"03", + X"32",X"40",X"9F",X"AF",X"32",X"41",X"9F",X"32",X"42",X"9F",X"32",X"4A",X"9F",X"3A",X"34",X"99", + X"A7",X"28",X"05",X"3E",X"FF",X"32",X"40",X"9F",X"21",X"41",X"9F",X"34",X"CD",X"AB",X"03",X"3E", + X"0A",X"32",X"43",X"9F",X"C9",X"21",X"00",X"99",X"06",X"10",X"36",X"00",X"23",X"10",X"FB",X"21", + X"00",X"9F",X"06",X"10",X"36",X"00",X"23",X"10",X"FB",X"21",X"40",X"9F",X"06",X"10",X"36",X"00", + X"23",X"10",X"FB",X"C9",X"7E",X"FE",X"19",X"38",X"02",X"3E",X"17",X"21",X"C2",X"03",X"CF",X"7E", + X"32",X"08",X"9F",X"3E",X"19",X"CF",X"7E",X"32",X"09",X"9F",X"C9",X"7E",X"FE",X"19",X"38",X"02", + X"3E",X"17",X"21",X"C2",X"03",X"CF",X"7E",X"32",X"48",X"9F",X"3E",X"19",X"CF",X"7E",X"32",X"49", + X"9F",X"C9",X"00",X"03",X"04",X"05",X"04",X"05",X"06",X"07",X"04",X"07",X"07",X"07",X"05",X"07", + X"07",X"07",X"05",X"08",X"08",X"08",X"06",X"08",X"08",X"08",X"07",X"00",X"02",X"03",X"04",X"03", + X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"05",X"05",X"05",X"04",X"06",X"06",X"06",X"04", + X"07",X"07",X"07",X"04",X"21",X"20",X"99",X"34",X"23",X"36",X"00",X"C9",X"21",X"21",X"99",X"34", + X"C9",X"21",X"1F",X"04",X"E5",X"3A",X"21",X"99",X"F7",X"20",X"04",X"42",X"04",X"52",X"04",X"8F", + X"04",X"F3",X"04",X"3F",X"05",X"16",X"06",X"8B",X"06",X"A6",X"06",X"B6",X"06",X"D2",X"06",X"C9", + X"AF",X"32",X"08",X"98",X"3C",X"32",X"83",X"A1",X"32",X"2F",X"99",X"21",X"00",X"9F",X"7E",X"A7", + X"28",X"04",X"35",X"C3",X"FC",X"03",X"21",X"0A",X"9F",X"7E",X"36",X"00",X"32",X"04",X"9F",X"C3", + X"FC",X"03",X"3A",X"01",X"9F",X"32",X"01",X"99",X"CD",X"84",X"32",X"C0",X"CD",X"C3",X"1A",X"C3", + X"FC",X"03",X"CD",X"B8",X"1A",X"CD",X"0A",X"02",X"CD",X"8F",X"31",X"3A",X"10",X"99",X"A7",X"20", + X"29",X"21",X"2F",X"01",X"11",X"C2",X"82",X"CD",X"E7",X"30",X"21",X"2F",X"01",X"11",X"C1",X"82", + X"CD",X"E7",X"30",X"CD",X"DD",X"04",X"21",X"00",X"9F",X"11",X"00",X"99",X"01",X"10",X"00",X"ED", + X"B0",X"CD",X"06",X"19",X"CD",X"57",X"19",X"C3",X"FC",X"03",X"CD",X"B3",X"31",X"18",X"E4",X"CD", + X"1D",X"17",X"CD",X"72",X"17",X"CD",X"FB",X"17",X"CD",X"84",X"18",X"3A",X"03",X"99",X"32",X"0F", + X"99",X"CD",X"B8",X"3F",X"3E",X"78",X"32",X"00",X"98",X"21",X"20",X"1C",X"22",X"06",X"98",X"CD", + X"65",X"2E",X"CD",X"25",X"2E",X"CD",X"E5",X"2D",X"CD",X"A0",X"2D",X"CD",X"63",X"1F",X"CD",X"BA", + X"1F",X"CD",X"09",X"20",X"CD",X"58",X"20",X"CD",X"AD",X"23",X"06",X"0A",X"11",X"71",X"85",X"CD", + X"18",X"05",X"06",X"09",X"11",X"8E",X"85",X"CD",X"13",X"05",X"C3",X"FC",X"03",X"21",X"98",X"01", + X"11",X"46",X"80",X"0E",X"A3",X"CD",X"DA",X"16",X"21",X"70",X"01",X"11",X"A5",X"80",X"0E",X"A3", + X"C3",X"DA",X"16",X"3A",X"00",X"98",X"A7",X"20",X"0E",X"06",X"0A",X"11",X"71",X"85",X"CD",X"2E", + X"05",X"CD",X"BB",X"33",X"C3",X"FC",X"03",X"21",X"BE",X"01",X"11",X"71",X"85",X"01",X"20",X"00", + X"C3",X"5B",X"06",X"21",X"EC",X"98",X"18",X"03",X"21",X"D4",X"98",X"1A",X"77",X"CB",X"DA",X"23", + X"1A",X"77",X"23",X"CB",X"9A",X"D7",X"10",X"F3",X"C9",X"21",X"EC",X"98",X"18",X"03",X"21",X"D4", + X"98",X"7E",X"12",X"CB",X"DA",X"23",X"7E",X"12",X"CB",X"9A",X"23",X"D7",X"10",X"F3",X"C9",X"2A", + X"06",X"98",X"7D",X"A7",X"CC",X"12",X"07",X"CD",X"47",X"2A",X"CD",X"65",X"2E",X"CD",X"A8",X"28", + X"CD",X"25",X"2E",X"CD",X"F5",X"26",X"CD",X"E5",X"2D",X"CD",X"DE",X"25",X"CD",X"A0",X"2D",X"CD", + X"63",X"1F",X"CD",X"BA",X"1F",X"CD",X"09",X"20",X"CD",X"58",X"20",X"CD",X"AD",X"23",X"CD",X"A7", + X"20",X"CD",X"59",X"1B",X"CD",X"C6",X"1B",X"CD",X"E5",X"1C",X"CD",X"54",X"1E",X"CD",X"3A",X"25", + X"CD",X"7C",X"21",X"CD",X"E5",X"21",X"CD",X"7D",X"22",X"CD",X"15",X"23",X"CD",X"3C",X"3F",X"CD", + X"3C",X"3E",X"CD",X"33",X"39",X"CD",X"D4",X"31",X"3A",X"04",X"99",X"A7",X"CA",X"05",X"06",X"FD", + X"21",X"80",X"98",X"DD",X"21",X"04",X"99",X"DD",X"7E",X"01",X"FD",X"B6",X"01",X"CC",X"6B",X"17", + X"DD",X"7E",X"02",X"FD",X"B6",X"02",X"CC",X"F4",X"17",X"DD",X"7E",X"03",X"FD",X"B6",X"03",X"CC", + X"7D",X"18",X"DD",X"7E",X"01",X"DD",X"B6",X"02",X"DD",X"B6",X"03",X"C0",X"FD",X"7E",X"01",X"FD", + X"B6",X"02",X"FD",X"B6",X"03",X"C0",X"CD",X"C0",X"33",X"CD",X"0A",X"34",X"3E",X"78",X"32",X"00", + X"98",X"CD",X"1B",X"03",X"3E",X"0A",X"32",X"21",X"99",X"C9",X"CD",X"C0",X"33",X"3E",X"78",X"32", + X"00",X"98",X"CD",X"1B",X"03",X"3A",X"00",X"99",X"21",X"0A",X"99",X"B6",X"C2",X"FC",X"03",X"CD", + X"20",X"34",X"C3",X"FC",X"03",X"CD",X"0B",X"06",X"C0",X"18",X"DF",X"21",X"80",X"98",X"7E",X"23", + X"B6",X"23",X"B6",X"23",X"B6",X"C9",X"3A",X"00",X"98",X"FE",X"01",X"38",X"08",X"28",X"59",X"CD", + X"4A",X"06",X"C3",X"E2",X"1E",X"CD",X"D1",X"1A",X"C0",X"3A",X"00",X"99",X"21",X"0A",X"99",X"B6", + X"28",X"15",X"3A",X"10",X"99",X"A7",X"28",X"0C",X"3A",X"40",X"9F",X"21",X"4A",X"9F",X"B6",X"28", + X"03",X"CD",X"FC",X"03",X"CD",X"FC",X"03",X"C3",X"FC",X"03",X"3A",X"00",X"99",X"21",X"0A",X"99", + X"B6",X"C0",X"21",X"80",X"01",X"11",X"8E",X"85",X"01",X"20",X"00",X"7E",X"FE",X"40",X"C8",X"D5", + X"E5",X"CD",X"72",X"2D",X"3A",X"02",X"98",X"0F",X"0F",X"E6",X"07",X"21",X"83",X"06",X"CF",X"7E", + X"12",X"D1",X"E1",X"13",X"09",X"EB",X"18",X"E3",X"CD",X"05",X"1B",X"11",X"8E",X"85",X"06",X"09", + X"C3",X"29",X"05",X"87",X"8E",X"95",X"A3",X"87",X"9C",X"95",X"BE",X"3A",X"10",X"99",X"A7",X"20", + X"0A",X"3E",X"03",X"32",X"20",X"99",X"AF",X"32",X"21",X"99",X"C9",X"3A",X"40",X"9F",X"21",X"4A", + X"9F",X"B6",X"28",X"ED",X"18",X"10",X"AF",X"32",X"21",X"99",X"21",X"00",X"99",X"11",X"00",X"9F", + X"01",X"10",X"00",X"ED",X"B0",X"C9",X"3A",X"2E",X"99",X"32",X"83",X"A1",X"32",X"2F",X"99",X"3E", + X"01",X"32",X"11",X"99",X"21",X"00",X"99",X"11",X"00",X"9F",X"01",X"10",X"00",X"ED",X"B0",X"C3", + X"F4",X"03",X"3A",X"00",X"98",X"FE",X"01",X"38",X"06",X"CA",X"05",X"1B",X"C3",X"E2",X"1E",X"CD", + X"D1",X"1A",X"C0",X"3A",X"04",X"99",X"FE",X"09",X"38",X"14",X"3E",X"08",X"32",X"04",X"99",X"21", + X"0A",X"99",X"34",X"7E",X"FE",X"08",X"38",X"06",X"36",X"00",X"21",X"00",X"99",X"34",X"3E",X"01", + X"32",X"21",X"99",X"21",X"00",X"99",X"11",X"00",X"9F",X"01",X"10",X"00",X"ED",X"B0",X"CD",X"41", + X"03",X"C9",X"7C",X"FE",X"10",X"30",X"28",X"E6",X"03",X"20",X"24",X"3A",X"65",X"98",X"FE",X"38", + X"30",X"05",X"C6",X"08",X"32",X"65",X"98",X"3A",X"68",X"98",X"FE",X"38",X"30",X"05",X"C6",X"08", + X"32",X"68",X"98",X"3A",X"6B",X"98",X"FE",X"38",X"D0",X"C6",X"08",X"32",X"6B",X"98",X"C9",X"7C", + X"FE",X"17",X"28",X"10",X"FE",X"13",X"28",X"41",X"FE",X"0B",X"28",X"38",X"FE",X"11",X"C0",X"AF", + X"32",X"18",X"9C",X"C9",X"CD",X"A5",X"2F",X"E6",X"03",X"32",X"1A",X"98",X"4F",X"3A",X"2F",X"99", + X"A7",X"28",X"05",X"21",X"BC",X"07",X"18",X"03",X"21",X"C6",X"07",X"7E",X"32",X"08",X"9C",X"23", + X"7E",X"32",X"19",X"9C",X"23",X"79",X"87",X"CF",X"7E",X"32",X"18",X"9C",X"23",X"7E",X"32",X"09", + X"9C",X"C3",X"2F",X"34",X"AF",X"32",X"1A",X"9C",X"C9",X"CD",X"A5",X"2F",X"E6",X"03",X"21",X"1A", + X"98",X"BE",X"28",X"F5",X"4F",X"3A",X"2F",X"99",X"A7",X"28",X"05",X"21",X"BC",X"07",X"18",X"03", + X"21",X"C6",X"07",X"7E",X"32",X"0A",X"9C",X"23",X"7E",X"32",X"1B",X"9C",X"23",X"79",X"87",X"CF", + X"7E",X"32",X"1A",X"9C",X"23",X"7E",X"32",X"0B",X"9C",X"C3",X"2F",X"34",X"7C",X"0F",X"94",X"8C", + X"94",X"BC",X"5C",X"BC",X"5C",X"8C",X"7F",X"0F",X"5C",X"84",X"5C",X"54",X"94",X"54",X"94",X"84", + X"21",X"EE",X"07",X"E5",X"3A",X"21",X"99",X"F7",X"EF",X"07",X"06",X"08",X"16",X"08",X"39",X"08", + X"96",X"08",X"B6",X"08",X"82",X"09",X"B1",X"09",X"C4",X"09",X"D4",X"09",X"F5",X"09",X"C9",X"21", + X"40",X"9F",X"7E",X"A7",X"28",X"04",X"35",X"C3",X"FC",X"03",X"21",X"4A",X"9F",X"7E",X"36",X"00", + X"32",X"44",X"9F",X"C3",X"FC",X"03",X"3A",X"41",X"9F",X"32",X"01",X"99",X"CD",X"84",X"32",X"C0", + X"CD",X"C3",X"1A",X"C3",X"FC",X"03",X"CD",X"B8",X"1A",X"CD",X"0A",X"02",X"CD",X"8F",X"31",X"CD", + X"B3",X"31",X"CD",X"87",X"08",X"21",X"40",X"9F",X"11",X"00",X"99",X"01",X"10",X"00",X"ED",X"B0", + X"CD",X"06",X"19",X"CD",X"57",X"19",X"C3",X"FC",X"03",X"CD",X"1D",X"17",X"CD",X"72",X"17",X"CD", + X"FB",X"17",X"CD",X"84",X"18",X"3A",X"03",X"99",X"32",X"0F",X"99",X"CD",X"B8",X"3F",X"3E",X"78", + X"32",X"00",X"98",X"21",X"20",X"1C",X"22",X"06",X"98",X"CD",X"65",X"2E",X"CD",X"25",X"2E",X"CD", + X"E5",X"2D",X"CD",X"A0",X"2D",X"CD",X"63",X"1F",X"CD",X"BA",X"1F",X"CD",X"09",X"20",X"CD",X"58", + X"20",X"CD",X"AD",X"23",X"06",X"0A",X"11",X"71",X"85",X"CD",X"18",X"05",X"06",X"09",X"11",X"8E", + X"85",X"CD",X"13",X"05",X"C3",X"FC",X"03",X"21",X"98",X"01",X"11",X"46",X"80",X"FF",X"21",X"74", + X"01",X"11",X"A5",X"80",X"FF",X"C9",X"3A",X"00",X"98",X"A7",X"20",X"0E",X"06",X"0A",X"11",X"71", + X"85",X"CD",X"2E",X"05",X"CD",X"BB",X"33",X"C3",X"FC",X"03",X"21",X"C9",X"01",X"11",X"71",X"85", + X"01",X"20",X"00",X"C3",X"5B",X"06",X"2A",X"06",X"98",X"7D",X"A7",X"CC",X"12",X"07",X"CD",X"47", + X"2A",X"CD",X"65",X"2E",X"CD",X"A8",X"28",X"CD",X"25",X"2E",X"CD",X"F5",X"26",X"CD",X"E5",X"2D", + X"CD",X"DE",X"25",X"CD",X"A0",X"2D",X"CD",X"63",X"1F",X"CD",X"BA",X"1F",X"CD",X"09",X"20",X"CD", + X"58",X"20",X"CD",X"AD",X"23",X"CD",X"A7",X"20",X"CD",X"59",X"1B",X"CD",X"C6",X"1B",X"CD",X"E5", + X"1C",X"CD",X"54",X"1E",X"CD",X"3A",X"25",X"CD",X"7C",X"21",X"CD",X"E5",X"21",X"CD",X"7D",X"22", + X"CD",X"15",X"23",X"CD",X"3C",X"3F",X"CD",X"3C",X"3E",X"CD",X"33",X"39",X"CD",X"D4",X"31",X"3A", + X"04",X"99",X"A7",X"CA",X"7C",X"09",X"FD",X"21",X"80",X"98",X"DD",X"21",X"04",X"99",X"DD",X"7E", + X"01",X"FD",X"B6",X"01",X"CC",X"6B",X"17",X"DD",X"7E",X"02",X"FD",X"B6",X"02",X"CC",X"F4",X"17", + X"DD",X"7E",X"03",X"FD",X"B6",X"03",X"CC",X"7D",X"18",X"DD",X"7E",X"01",X"DD",X"B6",X"02",X"DD", + X"B6",X"03",X"C0",X"FD",X"7E",X"01",X"FD",X"B6",X"02",X"FD",X"B6",X"03",X"C0",X"CD",X"C0",X"33", + X"CD",X"0A",X"34",X"3E",X"78",X"32",X"00",X"98",X"CD",X"1B",X"03",X"3E",X"0A",X"32",X"21",X"99", + X"C9",X"CD",X"C0",X"33",X"3E",X"78",X"32",X"00",X"98",X"CD",X"1B",X"03",X"3A",X"00",X"99",X"21", + X"0A",X"99",X"B6",X"C2",X"FC",X"03",X"CD",X"20",X"34",X"C3",X"FC",X"03",X"CD",X"0B",X"06",X"C0", + X"18",X"DF",X"3A",X"00",X"98",X"FE",X"01",X"38",X"09",X"CA",X"78",X"06",X"CD",X"4A",X"06",X"C3", + X"E2",X"1E",X"CD",X"D1",X"1A",X"C0",X"3A",X"00",X"99",X"21",X"0A",X"99",X"B6",X"28",X"0F",X"3A", + X"00",X"9F",X"21",X"0A",X"9F",X"B6",X"28",X"03",X"CD",X"FC",X"03",X"CD",X"FC",X"03",X"C3",X"FC", + X"03",X"3A",X"00",X"9F",X"21",X"0A",X"9F",X"B6",X"20",X"1A",X"3E",X"03",X"32",X"20",X"99",X"AF", + X"32",X"21",X"99",X"C9",X"AF",X"32",X"21",X"99",X"21",X"00",X"99",X"11",X"40",X"9F",X"01",X"10", + X"00",X"ED",X"B0",X"C9",X"3E",X"01",X"32",X"83",X"A1",X"32",X"2F",X"99",X"3E",X"00",X"32",X"11", + X"99",X"21",X"00",X"99",X"11",X"40",X"9F",X"01",X"10",X"00",X"ED",X"B0",X"AF",X"32",X"21",X"99", + X"3C",X"32",X"20",X"99",X"C9",X"3A",X"00",X"98",X"FE",X"01",X"38",X"06",X"CA",X"05",X"1B",X"C3", + X"E2",X"1E",X"CD",X"D1",X"1A",X"C0",X"3A",X"04",X"99",X"FE",X"09",X"38",X"14",X"3E",X"08",X"32", + X"04",X"99",X"21",X"0A",X"99",X"34",X"7E",X"FE",X"08",X"38",X"06",X"36",X"00",X"21",X"00",X"99", + X"34",X"3E",X"01",X"32",X"21",X"99",X"21",X"00",X"99",X"11",X"40",X"9F",X"01",X"10",X"00",X"ED", + X"B0",X"CD",X"68",X"03",X"C9",X"21",X"57",X"0A",X"E5",X"3A",X"21",X"99",X"F7",X"77",X"0A",X"29", + X"0B",X"2F",X"0B",X"79",X"0B",X"45",X"0C",X"70",X"0C",X"91",X"0C",X"AA",X"0C",X"AD",X"0C",X"B0", + X"0C",X"B3",X"0C",X"B6",X"0C",X"BF",X"0C",X"3A",X"23",X"99",X"A7",X"C8",X"4F",X"3A",X"04",X"98", + X"E6",X"C0",X"C8",X"E6",X"80",X"28",X"0A",X"AF",X"32",X"20",X"99",X"3E",X"05",X"32",X"21",X"99", + X"C9",X"79",X"FE",X"02",X"D8",X"18",X"F0",X"AF",X"32",X"11",X"99",X"FD",X"21",X"12",X"99",X"DD", + X"21",X"40",X"98",X"DD",X"36",X"00",X"00",X"21",X"42",X"99",X"06",X"0A",X"E5",X"22",X"52",X"98", + X"FD",X"7E",X"02",X"BE",X"38",X"48",X"28",X"02",X"18",X"12",X"FD",X"7E",X"01",X"2B",X"BE",X"38", + X"3D",X"28",X"02",X"18",X"07",X"FD",X"7E",X"00",X"2B",X"BE",X"38",X"32",X"E1",X"2B",X"2B",X"E5", + X"05",X"78",X"32",X"47",X"98",X"28",X"0F",X"87",X"87",X"87",X"87",X"4F",X"06",X"00",X"21",X"CF", + X"99",X"11",X"DF",X"99",X"ED",X"B8",X"E1",X"FD",X"7E",X"00",X"77",X"23",X"FD",X"7E",X"01",X"77", + X"23",X"FD",X"7E",X"02",X"77",X"06",X"0C",X"23",X"36",X"5B",X"10",X"FB",X"18",X"1C",X"DD",X"34", + X"00",X"E1",X"11",X"10",X"00",X"19",X"10",X"A4",X"CD",X"FC",X"03",X"CD",X"FC",X"03",X"CD",X"FC", + X"03",X"CD",X"FC",X"03",X"CD",X"FC",X"03",X"C3",X"FC",X"03",X"AF",X"32",X"41",X"98",X"32",X"42", + X"98",X"21",X"E0",X"99",X"06",X"0C",X"36",X"5B",X"23",X"10",X"FB",X"3A",X"21",X"99",X"FE",X"06", + X"30",X"0B",X"3E",X"01",X"32",X"83",X"A1",X"32",X"2F",X"99",X"C3",X"FC",X"03",X"3A",X"2E",X"99", + X"32",X"83",X"A1",X"32",X"2F",X"99",X"C3",X"FC",X"03",X"CD",X"88",X"19",X"C3",X"FC",X"03",X"CD", + X"B9",X"19",X"D8",X"CD",X"23",X"0C",X"CD",X"5B",X"1A",X"3A",X"47",X"98",X"87",X"21",X"98",X"01", + X"11",X"06",X"8D",X"83",X"5F",X"0E",X"87",X"CD",X"F2",X"30",X"3A",X"42",X"98",X"06",X"95",X"CD", + X"5F",X"0C",X"3A",X"41",X"98",X"0E",X"95",X"CD",X"54",X"0C",X"3A",X"21",X"99",X"FE",X"06",X"30", + X"0C",X"CD",X"DD",X"04",X"21",X"08",X"07",X"22",X"06",X"98",X"C3",X"FC",X"03",X"CD",X"DD",X"04", + X"21",X"08",X"07",X"22",X"06",X"98",X"C3",X"FC",X"03",X"3A",X"02",X"98",X"E6",X"07",X"C0",X"2A", + X"06",X"98",X"7C",X"B5",X"CA",X"32",X"0C",X"CD",X"06",X"2D",X"28",X"5F",X"3A",X"16",X"98",X"CB", + X"47",X"28",X"2E",X"21",X"42",X"98",X"CB",X"4F",X"7E",X"32",X"43",X"98",X"28",X"0A",X"34",X"7E", + X"FE",X"1B",X"38",X"0B",X"36",X"00",X"18",X"07",X"7E",X"A7",X"20",X"02",X"36",X"1B",X"35",X"3A", + X"43",X"98",X"06",X"8E",X"CD",X"5F",X"0C",X"3A",X"42",X"98",X"06",X"95",X"CD",X"5F",X"0C",X"18", + X"2A",X"21",X"41",X"98",X"CB",X"4F",X"7E",X"32",X"44",X"98",X"28",X"0A",X"34",X"7E",X"FE",X"0C", + X"38",X"09",X"36",X"0B",X"18",X"05",X"7E",X"A7",X"28",X"01",X"35",X"3A",X"44",X"98",X"0E",X"8E", + X"CD",X"54",X"0C",X"3A",X"41",X"98",X"0E",X"95",X"CD",X"54",X"0C",X"CD",X"AB",X"1B",X"20",X"33", + X"3A",X"42",X"98",X"FE",X"1A",X"28",X"3B",X"21",X"E0",X"99",X"3A",X"41",X"98",X"CF",X"3A",X"42", + X"98",X"C6",X"41",X"77",X"21",X"41",X"98",X"7E",X"32",X"44",X"98",X"34",X"7E",X"FE",X"0C",X"38", + X"02",X"36",X"0B",X"3A",X"44",X"98",X"0E",X"8E",X"CD",X"54",X"0C",X"3A",X"41",X"98",X"0E",X"95", + X"CD",X"54",X"0C",X"21",X"E0",X"99",X"11",X"E4",X"85",X"06",X"0C",X"7E",X"12",X"23",X"D7",X"10", + X"FA",X"C9",X"ED",X"5B",X"52",X"98",X"13",X"21",X"E0",X"99",X"01",X"0C",X"00",X"ED",X"B0",X"CD", + X"88",X"19",X"C3",X"FC",X"03",X"CD",X"B9",X"19",X"D8",X"3E",X"1E",X"32",X"00",X"98",X"CD",X"1B", + X"03",X"C3",X"FC",X"03",X"11",X"C4",X"8D",X"3C",X"47",X"D7",X"10",X"FD",X"79",X"12",X"C9",X"21", + X"61",X"8F",X"4F",X"3E",X"1A",X"91",X"CF",X"70",X"EB",X"D7",X"78",X"12",X"D7",X"78",X"12",X"C9", + X"3A",X"00",X"98",X"A7",X"C0",X"CD",X"D1",X"1A",X"C0",X"3A",X"10",X"99",X"A7",X"C2",X"FC",X"03", + X"AF",X"32",X"20",X"99",X"3C",X"32",X"83",X"A1",X"32",X"2F",X"99",X"3E",X"03",X"32",X"21",X"99", + X"C9",X"3E",X"01",X"32",X"11",X"99",X"FD",X"21",X"17",X"99",X"DD",X"21",X"40",X"98",X"DD",X"36", + X"00",X"00",X"21",X"42",X"99",X"06",X"0A",X"C3",X"8C",X"0A",X"C3",X"29",X"0B",X"C3",X"2F",X"0B", + X"C3",X"79",X"0B",X"C3",X"45",X"0C",X"3A",X"00",X"98",X"A7",X"C0",X"CD",X"D1",X"1A",X"C0",X"AF", + X"32",X"20",X"99",X"3C",X"32",X"83",X"A1",X"32",X"2F",X"99",X"3E",X"03",X"32",X"21",X"99",X"C9", + X"21",X"EA",X"0C",X"E5",X"3A",X"21",X"99",X"F7",X"F7",X"0C",X"07",X"0D",X"17",X"0D",X"31",X"0D", + X"6F",X"0D",X"77",X"0D",X"21",X"0E",X"2C",X"0E",X"50",X"0E",X"3A",X"23",X"99",X"A7",X"C8",X"AF", + X"32",X"20",X"99",X"32",X"21",X"99",X"C9",X"AF",X"32",X"10",X"99",X"32",X"11",X"99",X"CD",X"75", + X"03",X"CD",X"27",X"03",X"C3",X"FC",X"03",X"3A",X"01",X"9F",X"32",X"01",X"99",X"CD",X"84",X"32", + X"C0",X"CD",X"C3",X"1A",X"C3",X"FC",X"03",X"CD",X"B8",X"1A",X"CD",X"0A",X"02",X"CD",X"DD",X"04", + X"21",X"00",X"9F",X"11",X"00",X"99",X"01",X"10",X"00",X"ED",X"B0",X"CD",X"06",X"19",X"C3",X"FC", + X"03",X"CD",X"1D",X"17",X"CD",X"72",X"17",X"CD",X"FB",X"17",X"CD",X"84",X"18",X"3A",X"03",X"99", + X"32",X"0F",X"99",X"CD",X"B8",X"3F",X"3E",X"3C",X"32",X"00",X"98",X"21",X"20",X"1C",X"22",X"06", + X"98",X"CD",X"65",X"2E",X"CD",X"25",X"2E",X"CD",X"E5",X"2D",X"CD",X"A0",X"2D",X"CD",X"63",X"1F", + X"CD",X"BA",X"1F",X"CD",X"09",X"20",X"CD",X"58",X"20",X"CD",X"AD",X"23",X"C3",X"FC",X"03",X"3A", + X"00",X"98",X"A7",X"C0",X"C3",X"FC",X"03",X"2A",X"06",X"98",X"7D",X"A7",X"CC",X"12",X"07",X"CD", + X"B0",X"3E",X"CD",X"47",X"2A",X"CD",X"65",X"2E",X"CD",X"A8",X"28",X"CD",X"25",X"2E",X"CD",X"F5", + X"26",X"CD",X"E5",X"2D",X"CD",X"E6",X"2B",X"CD",X"A0",X"2D",X"CD",X"63",X"1F",X"CD",X"BA",X"1F", + X"CD",X"09",X"20",X"CD",X"58",X"20",X"CD",X"AD",X"23",X"CD",X"A7",X"20",X"CD",X"A3",X"1C",X"CD", + X"C6",X"1B",X"CD",X"E5",X"1C",X"CD",X"54",X"1E",X"CD",X"3A",X"25",X"CD",X"7C",X"21",X"CD",X"E5", + X"21",X"CD",X"7D",X"22",X"CD",X"15",X"23",X"CD",X"3C",X"3F",X"CD",X"3C",X"3E",X"CD",X"D4",X"31", + X"3A",X"04",X"99",X"A7",X"28",X"3A",X"FD",X"21",X"80",X"98",X"DD",X"21",X"04",X"99",X"DD",X"7E", + X"01",X"FD",X"B6",X"01",X"CC",X"6B",X"17",X"DD",X"7E",X"02",X"FD",X"B6",X"02",X"CC",X"F4",X"17", + X"DD",X"7E",X"03",X"FD",X"B6",X"03",X"CC",X"7D",X"18",X"DD",X"7E",X"01",X"DD",X"B6",X"02",X"DD", + X"B6",X"03",X"C0",X"FD",X"7E",X"01",X"FD",X"B6",X"02",X"FD",X"B6",X"03",X"C0",X"C3",X"FC",X"03", + X"CD",X"0B",X"06",X"C0",X"3E",X"08",X"32",X"21",X"99",X"3E",X"78",X"32",X"00",X"98",X"C3",X"1B", + X"03",X"3E",X"78",X"32",X"00",X"98",X"CD",X"1B",X"03",X"C3",X"FC",X"03",X"3A",X"00",X"98",X"FE", + X"01",X"38",X"06",X"CA",X"05",X"1B",X"C3",X"E2",X"1E",X"CD",X"D1",X"1A",X"C0",X"21",X"00",X"99", + X"11",X"00",X"9F",X"01",X"10",X"00",X"ED",X"B0",X"3E",X"01",X"32",X"21",X"99",X"C3",X"41",X"03", + X"3A",X"00",X"98",X"FE",X"01",X"38",X"06",X"CA",X"05",X"1B",X"C3",X"E2",X"1E",X"CD",X"D1",X"1A", + X"C0",X"AF",X"32",X"20",X"99",X"3E",X"03",X"32",X"21",X"99",X"C9",X"21",X"95",X"0E",X"E5",X"3A", + X"21",X"99",X"F7",X"A2",X"0E",X"A5",X"0E",X"22",X"0F",X"84",X"0F",X"AE",X"0F",X"E1",X"0F",X"44", + X"10",X"60",X"10",X"6E",X"10",X"B4",X"10",X"D8",X"10",X"E0",X"10",X"36",X"11",X"52",X"11",X"66", + X"11",X"F3",X"11",X"FE",X"11",X"3A",X"23",X"99",X"A7",X"C8",X"AF",X"32",X"20",X"99",X"32",X"21", + X"99",X"C9",X"C3",X"FC",X"03",X"21",X"23",X"01",X"11",X"B0",X"84",X"0E",X"A3",X"CD",X"F2",X"30", + X"21",X"23",X"01",X"11",X"AA",X"84",X"0E",X"A3",X"CD",X"F2",X"30",X"21",X"98",X"01",X"11",X"7A", + X"86",X"0E",X"BA",X"CD",X"DA",X"16",X"21",X"A3",X"01",X"11",X"1A",X"85",X"0E",X"8E",X"CD",X"DA", + X"16",X"21",X"A9",X"01",X"11",X"B0",X"84",X"FF",X"21",X"A9",X"01",X"11",X"AA",X"84",X"FF",X"CD", + X"17",X"0F",X"DD",X"21",X"A0",X"13",X"21",X"78",X"86",X"CD",X"13",X"12",X"DD",X"21",X"A0",X"13", + X"21",X"76",X"86",X"CD",X"13",X"12",X"DD",X"21",X"A0",X"13",X"21",X"74",X"86",X"CD",X"13",X"12", + X"DD",X"21",X"8F",X"13",X"21",X"6E",X"86",X"CD",X"13",X"12",X"DD",X"21",X"A0",X"13",X"21",X"68", + X"86",X"CD",X"13",X"12",X"C3",X"FC",X"03",X"21",X"B0",X"01",X"11",X"42",X"85",X"0E",X"BA",X"C3", + X"DA",X"16",X"DD",X"21",X"CB",X"13",X"21",X"98",X"85",X"CD",X"18",X"12",X"DD",X"21",X"BE",X"13", + X"21",X"96",X"85",X"CD",X"18",X"12",X"DD",X"21",X"AD",X"13",X"21",X"94",X"85",X"CD",X"18",X"12", + X"DD",X"21",X"D4",X"13",X"21",X"8E",X"85",X"CD",X"18",X"12",X"DD",X"21",X"AD",X"13",X"21",X"88", + X"85",X"CD",X"18",X"12",X"3E",X"0A",X"32",X"F4",X"85",X"3C",X"32",X"14",X"86",X"3C",X"32",X"F6", + X"85",X"3C",X"32",X"16",X"86",X"3C",X"32",X"F8",X"85",X"3C",X"32",X"18",X"86",X"3E",X"BA",X"32", + X"F4",X"8D",X"32",X"14",X"8E",X"32",X"F6",X"8D",X"32",X"16",X"8E",X"32",X"F8",X"8D",X"32",X"18", + X"8E",X"C3",X"FC",X"03",X"AF",X"32",X"10",X"99",X"32",X"11",X"99",X"CD",X"75",X"03",X"CD",X"27", + X"03",X"CD",X"B8",X"1A",X"CD",X"C3",X"1A",X"21",X"00",X"9F",X"11",X"00",X"99",X"01",X"10",X"00", + X"ED",X"B0",X"AF",X"32",X"45",X"98",X"3E",X"3C",X"32",X"00",X"98",X"C3",X"FC",X"03",X"3A",X"00", + X"98",X"A7",X"C0",X"3A",X"45",X"98",X"21",X"57",X"12",X"87",X"4F",X"87",X"81",X"CF",X"7E",X"23", + X"5E",X"23",X"56",X"23",X"E5",X"EB",X"CD",X"E3",X"16",X"E1",X"7E",X"32",X"46",X"98",X"23",X"5E", + X"23",X"56",X"EB",X"CD",X"00",X"17",X"3E",X"20",X"32",X"62",X"98",X"32",X"65",X"98",X"C3",X"FC", + X"03",X"CD",X"89",X"3F",X"CD",X"E5",X"2D",X"CD",X"C9",X"3E",X"CD",X"A0",X"2D",X"CD",X"63",X"1F", + X"CD",X"BA",X"1F",X"CD",X"AD",X"23",X"CD",X"A7",X"20",X"CD",X"E5",X"1C",X"CD",X"3A",X"25",X"CD", + X"7C",X"21",X"CD",X"E5",X"21",X"FD",X"21",X"80",X"98",X"DD",X"21",X"04",X"99",X"DD",X"7E",X"00", + X"A7",X"28",X"16",X"DD",X"7E",X"01",X"FD",X"B6",X"01",X"C0",X"ED",X"5B",X"02",X"9B",X"3E",X"77", + X"CD",X"72",X"2D",X"3E",X"AB",X"12",X"C3",X"FC",X"03",X"FD",X"7E",X"00",X"A7",X"C0",X"3E",X"4A", + X"ED",X"5B",X"42",X"9B",X"CB",X"DA",X"12",X"CB",X"9A",X"3E",X"76",X"CD",X"72",X"2D",X"3E",X"4A", + X"12",X"C3",X"FC",X"03",X"21",X"45",X"98",X"34",X"7E",X"FE",X"03",X"30",X"0B",X"3E",X"04",X"32", + X"21",X"99",X"3E",X"3C",X"32",X"00",X"98",X"C9",X"3E",X"3C",X"32",X"00",X"98",X"C3",X"FC",X"03", + X"3A",X"00",X"98",X"A7",X"C0",X"CD",X"FC",X"03",X"AF",X"32",X"12",X"9C",X"18",X"18",X"3A",X"00", + X"98",X"A7",X"C0",X"AF",X"32",X"10",X"9C",X"32",X"12",X"9C",X"21",X"00",X"9B",X"CD",X"47",X"1B", + X"21",X"40",X"9B",X"CD",X"47",X"1B",X"3A",X"45",X"98",X"21",X"57",X"12",X"87",X"4F",X"87",X"81", + X"CF",X"7E",X"23",X"5E",X"23",X"56",X"23",X"E5",X"EB",X"CD",X"E3",X"16",X"E1",X"7E",X"32",X"46", + X"98",X"23",X"5E",X"23",X"56",X"EB",X"CD",X"00",X"17",X"3E",X"20",X"32",X"62",X"98",X"32",X"65", + X"98",X"C3",X"FC",X"03",X"21",X"70",X"85",X"11",X"20",X"00",X"06",X"04",X"36",X"20",X"19",X"10", + X"FB",X"CD",X"E5",X"2D",X"CD",X"A0",X"2D",X"CD",X"BA",X"1F",X"CD",X"63",X"1F",X"CD",X"AD",X"23", + X"3E",X"3C",X"32",X"00",X"98",X"C3",X"FC",X"03",X"3A",X"00",X"98",X"A7",X"C0",X"C3",X"FC",X"03", + X"CD",X"89",X"3F",X"CD",X"E5",X"2D",X"CD",X"C9",X"3E",X"CD",X"A0",X"2D",X"CD",X"63",X"1F",X"CD", + X"BA",X"1F",X"CD",X"AD",X"23",X"CD",X"A7",X"20",X"CD",X"E5",X"1C",X"CD",X"3A",X"25",X"CD",X"7C", + X"21",X"CD",X"E5",X"21",X"FD",X"21",X"80",X"98",X"DD",X"21",X"04",X"99",X"DD",X"7E",X"00",X"FD", + X"B6",X"00",X"CA",X"FC",X"03",X"DD",X"7E",X"01",X"FD",X"B6",X"01",X"CA",X"FC",X"03",X"3A",X"46", + X"98",X"21",X"68",X"21",X"DF",X"7B",X"32",X"42",X"98",X"7A",X"11",X"70",X"85",X"CD",X"B1",X"30", + X"3A",X"42",X"98",X"C3",X"B6",X"30",X"21",X"45",X"98",X"34",X"7E",X"FE",X"0B",X"30",X"0B",X"3E", + X"08",X"32",X"21",X"99",X"3E",X"3C",X"32",X"00",X"98",X"C9",X"3E",X"3C",X"32",X"00",X"98",X"C3", + X"FC",X"03",X"3A",X"00",X"98",X"A7",X"C0",X"ED",X"5B",X"02",X"9B",X"3E",X"77",X"CD",X"72",X"2D", + X"3E",X"AB",X"12",X"C3",X"AE",X"0F",X"AF",X"32",X"62",X"98",X"32",X"65",X"98",X"CD",X"C1",X"11", + X"3A",X"05",X"99",X"A7",X"28",X"0F",X"3A",X"02",X"98",X"E6",X"3F",X"20",X"08",X"3E",X"FF",X"32", + X"70",X"98",X"CD",X"E5",X"11",X"CD",X"E5",X"2D",X"CD",X"A0",X"2D",X"CD",X"63",X"1F",X"CD",X"BA", + X"1F",X"CD",X"AD",X"23",X"CD",X"A3",X"1C",X"CD",X"E5",X"1C",X"CD",X"3A",X"25",X"CD",X"7C",X"21", + X"CD",X"E5",X"21",X"FD",X"21",X"80",X"98",X"DD",X"21",X"04",X"99",X"DD",X"7E",X"01",X"FD",X"B6", + X"01",X"C0",X"ED",X"5B",X"02",X"9B",X"3E",X"77",X"CD",X"72",X"2D",X"3E",X"AB",X"12",X"C3",X"FC", + X"03",X"3A",X"47",X"98",X"A7",X"C8",X"AF",X"32",X"47",X"98",X"3A",X"05",X"99",X"A7",X"28",X"08", + X"11",X"AA",X"85",X"3E",X"60",X"C3",X"B6",X"30",X"3E",X"05",X"11",X"6A",X"85",X"CD",X"B1",X"30", + X"3E",X"00",X"C3",X"B6",X"30",X"21",X"6A",X"85",X"11",X"20",X"00",X"06",X"04",X"36",X"20",X"19", + X"10",X"FB",X"C9",X"3E",X"3C",X"32",X"00",X"98",X"CD",X"1B",X"03",X"C3",X"FC",X"03",X"3A",X"00", + X"98",X"A7",X"C0",X"CD",X"D1",X"1A",X"C0",X"CD",X"88",X"19",X"32",X"20",X"99",X"3E",X"04",X"32", + X"21",X"99",X"C9",X"11",X"20",X"00",X"18",X"03",X"11",X"E0",X"FF",X"DD",X"46",X"00",X"DD",X"23", + X"DD",X"7E",X"00",X"77",X"DD",X"23",X"DD",X"7E",X"00",X"CB",X"DC",X"77",X"CB",X"9C",X"19",X"10", + X"01",X"C9",X"05",X"28",X"13",X"DD",X"23",X"DD",X"7E",X"00",X"77",X"DD",X"23",X"DD",X"7E",X"00", + X"CB",X"DC",X"77",X"CB",X"9C",X"19",X"10",X"ED",X"DD",X"23",X"DD",X"7E",X"00",X"77",X"DD",X"23", + X"DD",X"7E",X"00",X"CB",X"DC",X"77",X"C9",X"06",X"9F",X"12",X"04",X"17",X"13",X"06",X"B7",X"12", + X"06",X"2F",X"13",X"06",X"CF",X"12",X"08",X"47",X"13",X"08",X"E7",X"12",X"08",X"5F",X"13",X"08", + X"E7",X"12",X"07",X"5F",X"13",X"08",X"E7",X"12",X"06",X"5F",X"13",X"08",X"E7",X"12",X"05",X"5F", + X"13",X"08",X"E7",X"12",X"04",X"5F",X"13",X"08",X"E7",X"12",X"03",X"5F",X"13",X"08",X"E7",X"12", + X"02",X"5F",X"13",X"08",X"E7",X"12",X"01",X"5F",X"13",X"06",X"FF",X"12",X"08",X"77",X"13",X"58", + X"86",X"78",X"86",X"98",X"86",X"B8",X"86",X"D8",X"86",X"F8",X"86",X"18",X"87",X"38",X"87",X"58", + X"87",X"78",X"87",X"98",X"87",X"B8",X"87",X"56",X"86",X"76",X"86",X"96",X"86",X"B6",X"86",X"D6", + X"86",X"F6",X"86",X"16",X"87",X"36",X"87",X"56",X"87",X"76",X"87",X"96",X"87",X"B6",X"87",X"54", + X"86",X"74",X"86",X"94",X"86",X"B4",X"86",X"D4",X"86",X"F4",X"86",X"14",X"87",X"34",X"87",X"54", + X"87",X"74",X"87",X"94",X"87",X"B4",X"87",X"4E",X"86",X"6E",X"86",X"8E",X"86",X"AE",X"86",X"CE", + X"86",X"EE",X"86",X"0E",X"87",X"2E",X"87",X"4E",X"87",X"6E",X"87",X"8E",X"87",X"AE",X"87",X"48", + X"86",X"68",X"86",X"88",X"86",X"A8",X"86",X"C8",X"86",X"E8",X"86",X"08",X"87",X"28",X"87",X"48", + X"87",X"68",X"87",X"88",X"87",X"A8",X"87",X"B8",X"85",X"98",X"85",X"78",X"85",X"58",X"85",X"38", + X"85",X"18",X"85",X"F8",X"84",X"D8",X"84",X"B8",X"84",X"98",X"84",X"78",X"84",X"58",X"84",X"B6", + X"85",X"96",X"85",X"76",X"85",X"56",X"85",X"36",X"85",X"16",X"85",X"F6",X"84",X"D6",X"84",X"B6", + X"84",X"96",X"84",X"76",X"84",X"56",X"84",X"B4",X"85",X"94",X"85",X"74",X"85",X"54",X"85",X"34", + X"85",X"14",X"85",X"F4",X"84",X"D4",X"84",X"B4",X"84",X"94",X"84",X"74",X"84",X"54",X"84",X"AE", + X"85",X"8E",X"85",X"6E",X"85",X"4E",X"85",X"2E",X"85",X"0E",X"85",X"EE",X"84",X"CE",X"84",X"AE", + X"84",X"8E",X"84",X"6E",X"84",X"5E",X"84",X"A8",X"85",X"88",X"85",X"68",X"85",X"48",X"85",X"28", + X"85",X"08",X"85",X"E8",X"84",X"C8",X"84",X"A8",X"84",X"88",X"84",X"68",X"84",X"58",X"84",X"08", + X"77",X"AB",X"80",X"B0",X"80",X"B0",X"80",X"B0",X"80",X"B0",X"80",X"B0",X"A0",X"B0",X"C0",X"6A", + X"06",X"77",X"AB",X"80",X"B0",X"80",X"B0",X"80",X"B0",X"80",X"B0",X"C0",X"6A",X"08",X"76",X"4A", + X"80",X"88",X"80",X"88",X"80",X"88",X"80",X"88",X"80",X"88",X"A0",X"88",X"C0",X"88",X"06",X"76", + X"56",X"80",X"98",X"80",X"98",X"80",X"98",X"80",X"98",X"C0",X"98",X"04",X"76",X"4F",X"80",X"90", + X"80",X"90",X"C0",X"90",X"08",X"76",X"56",X"80",X"98",X"80",X"98",X"80",X"98",X"80",X"98",X"80", + X"98",X"A0",X"98",X"C0",X"98",X"07",X"76",X"4F",X"80",X"90",X"80",X"90",X"80",X"90",X"80",X"90", + X"A0",X"90",X"C0",X"90",X"06",X"76",X"4F",X"80",X"90",X"80",X"90",X"80",X"90",X"A0",X"90",X"C0", + X"90",X"05",X"76",X"4F",X"80",X"90",X"80",X"90",X"A0",X"90",X"C0",X"90",X"04",X"76",X"4F",X"80", + X"90",X"A0",X"90",X"C0",X"90",X"03",X"76",X"4F",X"A0",X"90",X"C0",X"90",X"02",X"76",X"4F",X"C0", + X"90",X"01",X"76",X"4F",X"3A",X"00",X"40",X"FE",X"55",X"CA",X"00",X"40",X"31",X"00",X"A0",X"ED", + X"46",X"F3",X"32",X"80",X"A0",X"21",X"00",X"98",X"11",X"01",X"98",X"01",X"00",X"08",X"36",X"00", + X"ED",X"B0",X"21",X"00",X"80",X"06",X"40",X"36",X"00",X"23",X"10",X"FB",X"01",X"C0",X"07",X"11", + X"41",X"80",X"36",X"20",X"ED",X"B0",X"32",X"80",X"A0",X"21",X"00",X"88",X"06",X"08",X"36",X"BA", + X"23",X"10",X"FB",X"06",X"18",X"36",X"20",X"23",X"10",X"FB",X"21",X"00",X"88",X"11",X"20",X"88", + X"01",X"E0",X"03",X"ED",X"B0",X"21",X"00",X"88",X"06",X"40",X"36",X"00",X"23",X"10",X"FB",X"21", + X"42",X"88",X"11",X"20",X"00",X"06",X"1C",X"36",X"8E",X"19",X"10",X"FB",X"21",X"00",X"8C",X"11", + X"01",X"8C",X"01",X"00",X"04",X"36",X"48",X"ED",X"B0",X"21",X"3F",X"A0",X"06",X"10",X"36",X"00", + X"23",X"10",X"FB",X"21",X"80",X"A1",X"06",X"08",X"36",X"00",X"23",X"10",X"FB",X"21",X"21",X"15", + X"11",X"00",X"9E",X"01",X"11",X"00",X"ED",X"B0",X"21",X"32",X"15",X"11",X"40",X"99",X"01",X"A0", + X"00",X"ED",X"B0",X"3E",X"02",X"32",X"1E",X"99",X"3A",X"80",X"A1",X"2F",X"4F",X"07",X"E6",X"01", + X"32",X"34",X"99",X"79",X"07",X"07",X"E6",X"01",X"32",X"2E",X"99",X"79",X"E6",X"07",X"21",X"19", + X"15",X"CF",X"7E",X"32",X"26",X"99",X"79",X"0F",X"0F",X"0F",X"E6",X"07",X"21",X"19",X"15",X"CF", + X"7E",X"32",X"29",X"99",X"AF",X"CD",X"78",X"33",X"3E",X"00",X"32",X"2D",X"99",X"3E",X"01",X"32", + X"83",X"A1",X"32",X"2F",X"99",X"3A",X"34",X"99",X"A7",X"C2",X"DF",X"15",X"C3",X"D2",X"15",X"3E", + X"01",X"32",X"81",X"A1",X"32",X"80",X"A0",X"18",X"FE",X"01",X"02",X"03",X"04",X"11",X"21",X"31", + X"33",X"FF",X"05",X"F6",X"80",X"32",X"17",X"9C",X"C9",X"DD",X"21",X"74",X"98",X"FD",X"BF",X"24", + X"AE",X"46",X"00",X"00",X"02",X"48",X"49",X"52",X"4F",X"53",X"48",X"49",X"54",X"41",X"5B",X"5B", + X"5B",X"5B",X"80",X"99",X"01",X"49",X"4E",X"4F",X"55",X"45",X"5B",X"5B",X"5B",X"5B",X"5B",X"5B", + X"5B",X"5B",X"50",X"88",X"01",X"4E",X"55",X"4D",X"41",X"5B",X"5B",X"5B",X"5B",X"5B",X"5B",X"5B", + X"5B",X"5B",X"00",X"64",X"01",X"46",X"55",X"4A",X"49",X"4E",X"41",X"4B",X"41",X"5B",X"5B",X"5B", + X"5B",X"5B",X"10",X"13",X"01",X"46",X"55",X"4B",X"55",X"54",X"41",X"4B",X"45",X"5B",X"5B",X"5B", + X"5B",X"5B",X"60",X"05",X"01",X"54",X"41",X"4D",X"4F",X"54",X"53",X"55",X"5B",X"5B",X"5B",X"5B", + X"5B",X"5B",X"90",X"90",X"00",X"4F",X"53",X"48",X"49",X"54",X"41",X"5B",X"5B",X"5B",X"5B",X"5B", + X"5B",X"5B",X"30",X"90",X"00",X"54",X"53",X"55",X"44",X"41",X"5B",X"5B",X"5B",X"5B",X"5B",X"5B", + X"5B",X"5B",X"90",X"86",X"00",X"4D",X"49",X"59",X"4F",X"53",X"48",X"49",X"5B",X"5B",X"5B",X"5B", + X"5B",X"5B",X"10",X"82",X"00",X"48",X"41",X"52",X"41",X"5B",X"54",X"5B",X"5B",X"5B",X"5B",X"5B", + X"5B",X"5B",X"11",X"BA",X"84",X"21",X"D3",X"16",X"0E",X"8E",X"CD",X"DA",X"16",X"18",X"16",X"11", + X"44",X"80",X"21",X"BF",X"16",X"0E",X"87",X"CD",X"DA",X"16",X"11",X"BA",X"84",X"21",X"BF",X"16", + X"0E",X"87",X"CD",X"DA",X"16",X"11",X"B8",X"84",X"21",X"A3",X"16",X"0E",X"BA",X"CD",X"DA",X"16", + X"11",X"F8",X"85",X"21",X"B3",X"16",X"0E",X"BA",X"CD",X"DA",X"16",X"11",X"D8",X"86",X"21",X"B9", + X"16",X"0E",X"BA",X"CD",X"DA",X"16",X"11",X"98",X"85",X"3A",X"26",X"99",X"0F",X"0F",X"0F",X"0F", + X"E6",X"07",X"3C",X"CD",X"B1",X"30",X"11",X"78",X"86",X"3A",X"26",X"99",X"E6",X"07",X"CD",X"B1", + X"30",X"11",X"B6",X"84",X"21",X"AB",X"16",X"0E",X"BA",X"CD",X"DA",X"16",X"11",X"F6",X"85",X"21", + X"B3",X"16",X"0E",X"BA",X"CD",X"DA",X"16",X"11",X"D6",X"86",X"21",X"B9",X"16",X"0E",X"BA",X"CD", + X"DA",X"16",X"11",X"96",X"85",X"3A",X"29",X"99",X"0F",X"0F",X"0F",X"0F",X"E6",X"07",X"3C",X"CD", + X"B1",X"30",X"11",X"76",X"86",X"3A",X"29",X"99",X"E6",X"07",X"CD",X"B1",X"30",X"11",X"B4",X"84", + X"0E",X"BA",X"21",X"CD",X"16",X"3A",X"2E",X"99",X"A7",X"28",X"03",X"21",X"C4",X"16",X"CD",X"DA", + X"16",X"06",X"06",X"C5",X"06",X"00",X"C5",X"32",X"80",X"A0",X"3E",X"87",X"32",X"B8",X"8D",X"32", + X"98",X"8E",X"32",X"B6",X"8D",X"32",X"96",X"8E",X"10",X"F0",X"C1",X"10",X"E9",X"C1",X"10",X"E3", + X"C3",X"0F",X"15",X"43",X"4F",X"49",X"4E",X"01",X"20",X"20",X"40",X"43",X"4F",X"49",X"4E",X"02", + X"20",X"20",X"40",X"43",X"4F",X"49",X"4E",X"20",X"40",X"50",X"4C",X"41",X"59",X"20",X"40",X"54", + X"45",X"53",X"54",X"40",X"55",X"50",X"20",X"52",X"49",X"47",X"48",X"54",X"40",X"54",X"41",X"42", + X"4C",X"45",X"40",X"4E",X"4F",X"52",X"4D",X"41",X"4C",X"40",X"E5",X"D5",X"CD",X"F2",X"30",X"D1", + X"E1",X"FF",X"C9",X"11",X"00",X"9B",X"01",X"18",X"00",X"ED",X"B0",X"32",X"04",X"99",X"21",X"80", + X"9A",X"11",X"81",X"9A",X"01",X"0C",X"00",X"36",X"00",X"ED",X"B0",X"AF",X"32",X"60",X"98",X"C9", + X"11",X"40",X"9B",X"01",X"18",X"00",X"ED",X"B0",X"32",X"05",X"99",X"21",X"A0",X"9A",X"11",X"A1", + X"9A",X"01",X"0C",X"00",X"36",X"02",X"ED",X"B0",X"AF",X"32",X"63",X"98",X"C9",X"21",X"04",X"99", + X"7E",X"A7",X"20",X"03",X"3E",X"08",X"77",X"CD",X"4F",X"1E",X"32",X"62",X"98",X"21",X"48",X"17", + X"11",X"80",X"9A",X"01",X"0C",X"00",X"ED",X"B0",X"21",X"53",X"17",X"11",X"00",X"9B",X"01",X"18", + X"00",X"ED",X"B0",X"AF",X"32",X"60",X"98",X"C9",X"01",X"01",X"05",X"10",X"0F",X"0A",X"05",X"00", + X"02",X"10",X"07",X"EF",X"85",X"EE",X"85",X"ED",X"85",X"0D",X"86",X"0E",X"86",X"EE",X"85",X"ED", + X"85",X"0D",X"86",X"ED",X"85",X"0D",X"86",X"0E",X"86",X"EE",X"85",X"3A",X"03",X"99",X"E6",X"03", + X"28",X"44",X"21",X"79",X"84",X"22",X"40",X"9B",X"21",X"7A",X"84",X"22",X"42",X"9B",X"21",X"42", + X"9B",X"11",X"44",X"9B",X"01",X"16",X"00",X"ED",X"B0",X"3A",X"05",X"99",X"A7",X"20",X"0F",X"21", + X"03",X"99",X"7E",X"A7",X"C8",X"35",X"CD",X"B8",X"3F",X"3E",X"09",X"32",X"05",X"99",X"CD",X"40", + X"1E",X"32",X"65",X"98",X"21",X"A0",X"9A",X"11",X"A1",X"9A",X"01",X"0C",X"00",X"36",X"03",X"ED", + X"B0",X"AF",X"32",X"63",X"98",X"C9",X"21",X"7A",X"87",X"22",X"40",X"9B",X"21",X"9A",X"87",X"22", + X"42",X"9B",X"21",X"42",X"9B",X"11",X"44",X"9B",X"01",X"16",X"00",X"ED",X"B0",X"21",X"03",X"99", + X"7E",X"A7",X"C8",X"35",X"CD",X"B8",X"3F",X"3E",X"09",X"32",X"05",X"99",X"CD",X"40",X"1E",X"32", + X"65",X"98",X"21",X"A0",X"9A",X"11",X"A1",X"9A",X"01",X"0C",X"00",X"36",X"00",X"ED",X"B0",X"AF", + X"32",X"63",X"98",X"C9",X"3A",X"03",X"99",X"E6",X"03",X"28",X"44",X"21",X"82",X"84",X"22",X"80", + X"9B",X"21",X"62",X"84",X"22",X"82",X"9B",X"21",X"82",X"9B",X"11",X"84",X"9B",X"01",X"16",X"00", + X"ED",X"B0",X"3A",X"06",X"99",X"A7",X"20",X"0F",X"21",X"03",X"99",X"7E",X"A7",X"C8",X"35",X"CD", + X"B8",X"3F",X"3E",X"09",X"32",X"06",X"99",X"CD",X"40",X"1E",X"32",X"68",X"98",X"21",X"C0",X"9A", + X"11",X"C1",X"9A",X"01",X"0C",X"00",X"36",X"02",X"ED",X"B0",X"AF",X"32",X"66",X"98",X"C9",X"21", + X"7A",X"87",X"22",X"80",X"9B",X"21",X"9A",X"87",X"22",X"82",X"9B",X"21",X"82",X"9B",X"11",X"84", + X"9B",X"01",X"16",X"00",X"ED",X"B0",X"21",X"03",X"99",X"7E",X"A7",X"C8",X"35",X"CD",X"B8",X"3F", + X"3E",X"09",X"32",X"06",X"99",X"CD",X"40",X"1E",X"32",X"68",X"98",X"21",X"C0",X"9A",X"11",X"C1", + X"9A",X"01",X"0C",X"00",X"36",X"00",X"ED",X"B0",X"AF",X"32",X"66",X"98",X"C9",X"3A",X"03",X"99", + X"E6",X"03",X"28",X"44",X"21",X"83",X"87",X"22",X"C0",X"9B",X"21",X"82",X"87",X"22",X"C2",X"9B", + X"21",X"C2",X"9B",X"11",X"C4",X"9B",X"01",X"16",X"00",X"ED",X"B0",X"3A",X"07",X"99",X"A7",X"20", + X"0F",X"21",X"03",X"99",X"7E",X"A7",X"C8",X"35",X"CD",X"B8",X"3F",X"3E",X"09",X"32",X"07",X"99", + X"CD",X"40",X"1E",X"32",X"6B",X"98",X"21",X"E0",X"9A",X"11",X"E1",X"9A",X"01",X"0C",X"00",X"36", + X"01",X"ED",X"B0",X"AF",X"32",X"69",X"98",X"C9",X"21",X"7A",X"87",X"22",X"C0",X"9B",X"21",X"9A", + X"87",X"22",X"C2",X"9B",X"21",X"C2",X"9B",X"11",X"C4",X"9B",X"01",X"16",X"00",X"ED",X"B0",X"21", + X"03",X"99",X"7E",X"A7",X"C8",X"35",X"CD",X"B8",X"3F",X"3E",X"09",X"32",X"07",X"99",X"CD",X"40", + X"1E",X"32",X"6B",X"98",X"21",X"E0",X"9A",X"11",X"E1",X"9A",X"01",X"0C",X"00",X"36",X"00",X"ED", + X"B0",X"AF",X"32",X"69",X"98",X"C9",X"21",X"A7",X"80",X"11",X"E0",X"FF",X"3A",X"00",X"99",X"FE", + X"05",X"30",X"1C",X"4F",X"3E",X"04",X"91",X"28",X"06",X"47",X"36",X"20",X"19",X"10",X"FB",X"79", + X"A7",X"28",X"0C",X"47",X"36",X"5E",X"CB",X"DC",X"36",X"AB",X"CB",X"9C",X"19",X"10",X"F5",X"21", + X"24",X"81",X"11",X"E0",X"FF",X"3A",X"0A",X"99",X"FE",X"09",X"D0",X"4F",X"3E",X"08",X"91",X"28", + X"06",X"47",X"36",X"20",X"19",X"10",X"FB",X"79",X"A7",X"C8",X"47",X"36",X"5F",X"CB",X"DC",X"36", + X"AB",X"CB",X"9C",X"19",X"10",X"F5",X"C9",X"3A",X"01",X"99",X"FE",X"19",X"D0",X"4F",X"21",X"A7", + X"8B",X"11",X"E0",X"FF",X"06",X"06",X"36",X"89",X"19",X"36",X"89",X"19",X"36",X"89",X"19",X"36", + X"95",X"19",X"10",X"F2",X"21",X"A7",X"83",X"41",X"36",X"5D",X"19",X"10",X"FB",X"3E",X"18",X"91", + X"C8",X"47",X"36",X"20",X"19",X"10",X"FB",X"C9",X"11",X"78",X"8C",X"01",X"18",X"04",X"3E",X"8E", + X"CD",X"6D",X"1A",X"11",X"18",X"8D",X"01",X"18",X"06",X"3E",X"BA",X"CD",X"6D",X"1A",X"11",X"F8", + X"8D",X"01",X"13",X"0C",X"3E",X"95",X"CD",X"6D",X"1A",X"21",X"8A",X"01",X"11",X"3A",X"85",X"0E", + X"BE",X"CD",X"DA",X"16",X"AF",X"32",X"40",X"98",X"C9",X"3A",X"02",X"98",X"E6",X"01",X"FE",X"01", + X"D8",X"11",X"D8",X"84",X"21",X"47",X"1A",X"3A",X"40",X"98",X"47",X"A7",X"28",X"05",X"23",X"1B", + X"1B",X"10",X"FB",X"7E",X"12",X"11",X"B8",X"84",X"21",X"51",X"1A",X"3A",X"40",X"98",X"47",X"A7", + X"28",X"05",X"23",X"1B",X"1B",X"10",X"FB",X"7E",X"12",X"11",X"78",X"84",X"3A",X"40",X"98",X"47", + X"A7",X"28",X"04",X"1B",X"1B",X"10",X"FC",X"C6",X"01",X"27",X"CD",X"B1",X"30",X"11",X"18",X"85", + X"21",X"42",X"99",X"01",X"10",X"00",X"3A",X"40",X"98",X"A7",X"28",X"06",X"1B",X"1B",X"09",X"3D", + X"20",X"FA",X"06",X"00",X"7E",X"CD",X"C9",X"30",X"2B",X"7E",X"CD",X"C9",X"30",X"2B",X"7E",X"CD", + X"B6",X"30",X"11",X"F8",X"85",X"21",X"43",X"99",X"01",X"10",X"00",X"3A",X"40",X"98",X"A7",X"28", + X"06",X"1B",X"1B",X"09",X"3D",X"20",X"FA",X"06",X"0C",X"7E",X"12",X"23",X"D7",X"10",X"FA",X"21", + X"40",X"98",X"34",X"7E",X"FE",X"0A",X"C9",X"54",X"44",X"44",X"48",X"48",X"48",X"48",X"48",X"48", + X"48",X"53",X"4E",X"52",X"54",X"54",X"54",X"54",X"54",X"54",X"54",X"11",X"9B",X"87",X"06",X"1A", + X"3E",X"41",X"12",X"1B",X"3C",X"10",X"FB",X"EF",X"21",X"9F",X"01",X"FF",X"C9",X"C5",X"41",X"D5", + X"12",X"1B",X"10",X"FC",X"D1",X"F5",X"D7",X"F1",X"C1",X"10",X"F2",X"C9",X"21",X"40",X"98",X"7E", + X"C6",X"01",X"27",X"77",X"21",X"2F",X"01",X"11",X"82",X"81",X"D5",X"E5",X"FF",X"21",X"1F",X"FF", + X"19",X"EB",X"3A",X"1E",X"99",X"06",X"00",X"CD",X"C9",X"30",X"3A",X"1D",X"99",X"CD",X"C9",X"30", + X"3A",X"1C",X"99",X"CD",X"B6",X"30",X"E1",X"D1",X"0E",X"87",X"C3",X"F2",X"30",X"21",X"12",X"99", + X"06",X"0A",X"36",X"00",X"23",X"10",X"FB",X"C9",X"21",X"00",X"98",X"06",X"00",X"36",X"00",X"23", + X"10",X"FB",X"C9",X"21",X"00",X"9A",X"11",X"01",X"9A",X"01",X"FF",X"03",X"36",X"00",X"ED",X"B0", + X"C9",X"AF",X"21",X"34",X"9C",X"06",X"08",X"77",X"23",X"10",X"FC",X"32",X"10",X"9C",X"32",X"12", + X"9C",X"32",X"14",X"9C",X"32",X"16",X"9C",X"32",X"18",X"9C",X"32",X"1A",X"9C",X"2A",X"52",X"98", + X"06",X"20",X"36",X"20",X"CB",X"DC",X"36",X"BF",X"CB",X"9C",X"23",X"10",X"F5",X"22",X"52",X"98", + X"21",X"01",X"98",X"35",X"C9",X"21",X"A4",X"83",X"11",X"E0",X"FF",X"06",X"08",X"36",X"20",X"19", + X"10",X"FB",X"AF",X"21",X"34",X"9C",X"06",X"08",X"77",X"23",X"10",X"FC",X"32",X"00",X"9D",X"21", + X"00",X"9B",X"CD",X"47",X"1B",X"21",X"40",X"9B",X"CD",X"47",X"1B",X"21",X"80",X"9B",X"CD",X"47", + X"1B",X"21",X"C0",X"9B",X"AF",X"32",X"10",X"9C",X"32",X"12",X"9C",X"32",X"14",X"9C",X"32",X"16", + X"9C",X"32",X"18",X"9C",X"32",X"1A",X"9C",X"06",X"0A",X"3E",X"20",X"5E",X"23",X"56",X"23",X"7B", + X"B2",X"28",X"03",X"3E",X"20",X"12",X"10",X"F3",X"C9",X"CD",X"AB",X"1B",X"C0",X"3A",X"04",X"99", + X"A7",X"C8",X"DD",X"21",X"74",X"98",X"DD",X"7E",X"00",X"A7",X"28",X"07",X"DD",X"23",X"DD",X"7E", + X"00",X"A7",X"C0",X"CD",X"A5",X"33",X"3A",X"61",X"98",X"DD",X"77",X"10",X"3A",X"6C",X"98",X"DD", + X"77",X"20",X"3A",X"80",X"9A",X"E6",X"03",X"87",X"21",X"A3",X"1B",X"CF",X"7E",X"DD",X"77",X"30", + X"23",X"7E",X"DD",X"77",X"40",X"3E",X"FF",X"DD",X"77",X"00",X"C9",X"02",X"00",X"00",X"02",X"FE", + X"00",X"00",X"FE",X"03",X"00",X"00",X"03",X"FD",X"00",X"00",X"FD",X"21",X"15",X"98",X"3A",X"2F", + X"99",X"A7",X"3A",X"04",X"98",X"28",X"03",X"3A",X"03",X"98",X"0F",X"0F",X"0F",X"0F",X"CB",X"16", + X"7E",X"E6",X"07",X"FE",X"01",X"C9",X"3A",X"71",X"98",X"A7",X"28",X"07",X"DD",X"21",X"76",X"98", + X"CD",X"27",X"1C",X"3A",X"72",X"98",X"A7",X"28",X"07",X"DD",X"21",X"78",X"98",X"CD",X"65",X"1C", + X"3A",X"73",X"98",X"A7",X"C8",X"DD",X"21",X"7A",X"98",X"DD",X"7E",X"00",X"A7",X"28",X"07",X"DD", + X"23",X"DD",X"7E",X"00",X"A7",X"C0",X"3A",X"02",X"98",X"E6",X"0F",X"C0",X"32",X"73",X"98",X"CD", + X"A9",X"33",X"3A",X"6A",X"98",X"DD",X"77",X"10",X"3A",X"6F",X"98",X"DD",X"77",X"20",X"3A",X"E0", + X"9A",X"E6",X"03",X"87",X"21",X"9B",X"1B",X"CF",X"7E",X"DD",X"77",X"30",X"23",X"7E",X"DD",X"77", + X"40",X"3E",X"FF",X"DD",X"77",X"00",X"C9",X"DD",X"7E",X"00",X"A7",X"28",X"07",X"DD",X"23",X"DD", + X"7E",X"00",X"A7",X"C0",X"3A",X"02",X"98",X"E6",X"0F",X"C0",X"32",X"71",X"98",X"CD",X"A9",X"33", + X"3A",X"64",X"98",X"DD",X"77",X"10",X"3A",X"6D",X"98",X"DD",X"77",X"20",X"3A",X"A0",X"9A",X"E6", + X"03",X"87",X"21",X"9B",X"1B",X"CF",X"7E",X"DD",X"77",X"30",X"23",X"7E",X"DD",X"77",X"40",X"3E", + X"FF",X"DD",X"77",X"00",X"C9",X"DD",X"7E",X"00",X"A7",X"28",X"07",X"DD",X"23",X"DD",X"7E",X"00", + X"A7",X"C0",X"3A",X"02",X"98",X"E6",X"0F",X"C0",X"32",X"72",X"98",X"CD",X"A9",X"33",X"3A",X"67", + X"98",X"DD",X"77",X"10",X"3A",X"6E",X"98",X"DD",X"77",X"20",X"3A",X"C0",X"9A",X"E6",X"03",X"87", + X"21",X"9B",X"1B",X"CF",X"7E",X"DD",X"77",X"30",X"23",X"7E",X"DD",X"77",X"40",X"3E",X"FF",X"DD", + X"77",X"00",X"C9",X"3A",X"70",X"98",X"A7",X"C8",X"AF",X"32",X"70",X"98",X"DD",X"21",X"74",X"98", + X"DD",X"7E",X"00",X"A7",X"28",X"07",X"DD",X"23",X"DD",X"7E",X"00",X"A7",X"C0",X"CD",X"A5",X"33", + X"3A",X"61",X"98",X"DD",X"77",X"10",X"3A",X"6C",X"98",X"DD",X"77",X"20",X"3A",X"80",X"9A",X"E6", + X"03",X"87",X"21",X"A3",X"1B",X"CF",X"7E",X"DD",X"77",X"30",X"23",X"7E",X"DD",X"77",X"40",X"3E", + X"FF",X"DD",X"77",X"00",X"C9",X"FD",X"21",X"74",X"98",X"CD",X"EE",X"1C",X"FD",X"23",X"FD",X"7E", + X"00",X"A7",X"C8",X"FD",X"7E",X"20",X"FD",X"86",X"40",X"FD",X"77",X"20",X"4F",X"FD",X"7E",X"10", + X"FD",X"86",X"30",X"FD",X"77",X"10",X"2F",X"E6",X"F8",X"26",X"00",X"6F",X"29",X"29",X"79",X"E6", + X"F8",X"0F",X"0F",X"0F",X"CF",X"11",X"00",X"84",X"19",X"7E",X"FE",X"E8",X"D2",X"DF",X"1D",X"EB", + X"3A",X"05",X"99",X"A7",X"28",X"3B",X"DD",X"21",X"C4",X"98",X"CD",X"E4",X"1D",X"20",X"32",X"21", + X"05",X"99",X"35",X"20",X"1E",X"AF",X"32",X"71",X"98",X"3E",X"40",X"32",X"81",X"98",X"CD",X"BF", + X"31",X"28",X"03",X"32",X"B1",X"98",X"3E",X"01",X"32",X"91",X"98",X"32",X"A1",X"98",X"CD",X"11", + X"1E",X"18",X"03",X"CD",X"F8",X"1D",X"3A",X"05",X"99",X"CD",X"40",X"1E",X"32",X"65",X"98",X"18", + X"7E",X"3A",X"06",X"99",X"A7",X"28",X"3B",X"DD",X"21",X"C8",X"98",X"CD",X"E4",X"1D",X"20",X"32", + X"21",X"06",X"99",X"35",X"20",X"1E",X"AF",X"32",X"72",X"98",X"3E",X"40",X"32",X"82",X"98",X"CD", + X"BF",X"31",X"28",X"03",X"32",X"B2",X"98",X"3E",X"01",X"32",X"92",X"98",X"32",X"A2",X"98",X"CD", + X"11",X"1E",X"18",X"03",X"CD",X"F8",X"1D",X"3A",X"06",X"99",X"CD",X"40",X"1E",X"32",X"68",X"98", + X"18",X"3D",X"3A",X"07",X"99",X"A7",X"C8",X"DD",X"21",X"CC",X"98",X"CD",X"E4",X"1D",X"C0",X"21", + X"07",X"99",X"35",X"20",X"1E",X"AF",X"32",X"73",X"98",X"3E",X"40",X"32",X"83",X"98",X"CD",X"BF", + X"31",X"28",X"03",X"32",X"B3",X"98",X"3E",X"01",X"32",X"93",X"98",X"32",X"A3",X"98",X"CD",X"11", + X"1E",X"18",X"03",X"CD",X"F8",X"1D",X"3A",X"07",X"99",X"CD",X"40",X"1E",X"32",X"6B",X"98",X"AF", + X"FD",X"77",X"00",X"C9",X"DD",X"6E",X"00",X"DD",X"66",X"01",X"AF",X"ED",X"52",X"C8",X"DD",X"6E", + X"02",X"DD",X"66",X"03",X"AF",X"ED",X"52",X"C9",X"FD",X"E5",X"21",X"60",X"00",X"3E",X"FF",X"32", + X"47",X"98",X"22",X"15",X"99",X"22",X"1A",X"99",X"CD",X"FE",X"30",X"CD",X"EB",X"33",X"FD",X"E1", + X"C9",X"FD",X"E5",X"21",X"00",X"05",X"3E",X"FF",X"32",X"47",X"98",X"22",X"15",X"99",X"22",X"1A", + X"99",X"CD",X"FE",X"30",X"CD",X"EF",X"33",X"FD",X"E1",X"C9",X"00",X"2A",X"28",X"26",X"24",X"22", + X"20",X"1E",X"1C",X"1A",X"16",X"00",X"2C",X"2A",X"28",X"26",X"24",X"22",X"20",X"1E",X"1C",X"1A", + X"21",X"2A",X"1E",X"CF",X"3A",X"01",X"99",X"3D",X"86",X"FE",X"39",X"D8",X"3E",X"38",X"C9",X"21", + X"35",X"1E",X"18",X"EF",X"DD",X"21",X"76",X"98",X"CD",X"71",X"1E",X"DD",X"23",X"CD",X"71",X"1E", + X"DD",X"23",X"CD",X"71",X"1E",X"DD",X"23",X"CD",X"71",X"1E",X"DD",X"23",X"CD",X"71",X"1E",X"DD", + X"23",X"DD",X"7E",X"00",X"A7",X"C8",X"DD",X"7E",X"20",X"DD",X"86",X"40",X"DD",X"77",X"20",X"4F", + X"DD",X"7E",X"10",X"DD",X"86",X"30",X"DD",X"77",X"10",X"2F",X"E6",X"F8",X"26",X"00",X"6F",X"29", + X"29",X"79",X"E6",X"F8",X"0F",X"0F",X"0F",X"CF",X"11",X"00",X"84",X"19",X"7E",X"FE",X"E8",X"30", + X"3C",X"3A",X"04",X"99",X"A7",X"C8",X"EB",X"2A",X"C0",X"98",X"A7",X"ED",X"52",X"20",X"07",X"3A", + X"60",X"98",X"FE",X"A0",X"38",X"0D",X"2A",X"C2",X"98",X"A7",X"ED",X"52",X"C0",X"3A",X"60",X"98", + X"FE",X"80",X"D8",X"CD",X"E7",X"33",X"21",X"04",X"99",X"35",X"20",X"0A",X"3E",X"40",X"32",X"80", + X"98",X"3E",X"01",X"32",X"90",X"98",X"7E",X"CD",X"4F",X"1E",X"32",X"62",X"98",X"AF",X"DD",X"77", + X"00",X"C9",X"FD",X"21",X"74",X"98",X"06",X"08",X"CD",X"2B",X"1F",X"FD",X"23",X"10",X"F9",X"CD", + X"3A",X"25",X"3A",X"D3",X"98",X"A7",X"20",X"03",X"CD",X"47",X"2A",X"CD",X"65",X"2E",X"3A",X"D2", + X"98",X"A7",X"20",X"03",X"CD",X"A8",X"28",X"CD",X"25",X"2E",X"3A",X"D1",X"98",X"A7",X"20",X"03", + X"CD",X"F5",X"26",X"CD",X"E5",X"2D",X"CD",X"DE",X"25",X"CD",X"A0",X"2D",X"CD",X"63",X"1F",X"CD", + X"BA",X"1F",X"CD",X"09",X"20",X"CD",X"58",X"20",X"C3",X"AD",X"23",X"FD",X"7E",X"00",X"A7",X"C8", + X"FD",X"7E",X"20",X"FD",X"86",X"40",X"FD",X"77",X"20",X"4F",X"FD",X"7E",X"10",X"FD",X"86",X"30", + X"FD",X"77",X"10",X"2F",X"E6",X"F8",X"26",X"00",X"6F",X"29",X"29",X"79",X"E6",X"F8",X"0F",X"0F", + X"0F",X"CF",X"11",X"00",X"84",X"19",X"7E",X"FE",X"E8",X"D8",X"FD",X"36",X"00",X"00",X"FD",X"36", + X"10",X"00",X"C9",X"2A",X"02",X"9B",X"11",X"00",X"84",X"A7",X"ED",X"52",X"7D",X"E6",X"1F",X"87", + X"87",X"87",X"C6",X"04",X"32",X"6C",X"98",X"CB",X"3C",X"CB",X"1D",X"CB",X"3C",X"CB",X"1D",X"7D", + X"E6",X"F8",X"C6",X"04",X"2F",X"32",X"61",X"98",X"3A",X"60",X"98",X"07",X"07",X"07",X"E6",X"07", + X"C8",X"47",X"4F",X"3A",X"80",X"9A",X"E6",X"03",X"21",X"B2",X"1F",X"87",X"CF",X"3A",X"61",X"98", + X"86",X"10",X"FD",X"32",X"61",X"98",X"23",X"3A",X"6C",X"98",X"41",X"86",X"10",X"FD",X"32",X"6C", + X"98",X"C9",X"01",X"00",X"00",X"01",X"FF",X"00",X"00",X"FF",X"2A",X"42",X"9B",X"11",X"00",X"84", + X"A7",X"ED",X"52",X"7D",X"E6",X"1F",X"87",X"87",X"87",X"C6",X"04",X"32",X"6D",X"98",X"CB",X"3C", + X"CB",X"1D",X"CB",X"3C",X"CB",X"1D",X"7D",X"E6",X"F8",X"C6",X"04",X"2F",X"32",X"64",X"98",X"3A", + X"63",X"98",X"07",X"07",X"07",X"E6",X"07",X"C8",X"47",X"4F",X"3A",X"A1",X"9A",X"E6",X"03",X"21", + X"B2",X"1F",X"87",X"CF",X"3A",X"64",X"98",X"86",X"10",X"FD",X"32",X"64",X"98",X"23",X"3A",X"6D", + X"98",X"41",X"86",X"10",X"FD",X"32",X"6D",X"98",X"C9",X"2A",X"82",X"9B",X"11",X"00",X"84",X"A7", + X"ED",X"52",X"7D",X"E6",X"1F",X"87",X"87",X"87",X"C6",X"04",X"32",X"6E",X"98",X"CB",X"3C",X"CB", + X"1D",X"CB",X"3C",X"CB",X"1D",X"7D",X"E6",X"F8",X"C6",X"04",X"2F",X"32",X"67",X"98",X"3A",X"66", + X"98",X"07",X"07",X"07",X"E6",X"07",X"C8",X"47",X"4F",X"3A",X"C1",X"9A",X"E6",X"03",X"21",X"B2", + X"1F",X"87",X"CF",X"3A",X"67",X"98",X"86",X"10",X"FD",X"32",X"67",X"98",X"23",X"3A",X"6E",X"98", + X"41",X"86",X"10",X"FD",X"32",X"6E",X"98",X"C9",X"2A",X"C2",X"9B",X"11",X"00",X"84",X"A7",X"ED", + X"52",X"7D",X"E6",X"1F",X"87",X"87",X"87",X"C6",X"04",X"32",X"6F",X"98",X"CB",X"3C",X"CB",X"1D", + X"CB",X"3C",X"CB",X"1D",X"7D",X"E6",X"F8",X"C6",X"04",X"2F",X"32",X"6A",X"98",X"3A",X"69",X"98", + X"07",X"07",X"07",X"E6",X"07",X"C8",X"47",X"4F",X"3A",X"E1",X"9A",X"E6",X"03",X"21",X"B2",X"1F", + X"87",X"CF",X"3A",X"6A",X"98",X"86",X"10",X"FD",X"32",X"6A",X"98",X"23",X"3A",X"6F",X"98",X"41", + X"86",X"10",X"FD",X"32",X"6F",X"98",X"C9",X"3A",X"05",X"99",X"32",X"40",X"98",X"21",X"64",X"98", + X"11",X"6D",X"98",X"DD",X"21",X"81",X"98",X"CD",X"04",X"21",X"3A",X"40",X"98",X"32",X"05",X"99", + X"A7",X"20",X"03",X"32",X"71",X"98",X"3A",X"06",X"99",X"32",X"40",X"98",X"21",X"67",X"98",X"11", + X"6E",X"98",X"DD",X"21",X"82",X"98",X"CD",X"04",X"21",X"3A",X"40",X"98",X"32",X"06",X"99",X"A7", + X"20",X"03",X"32",X"72",X"98",X"3A",X"07",X"99",X"32",X"40",X"98",X"21",X"6A",X"98",X"11",X"6F", + X"98",X"DD",X"21",X"83",X"98",X"CD",X"04",X"21",X"3A",X"40",X"98",X"32",X"07",X"99",X"A7",X"C0", + X"32",X"73",X"98",X"C9",X"3A",X"04",X"99",X"A7",X"C8",X"3A",X"40",X"98",X"A7",X"C8",X"3A",X"61", + X"98",X"96",X"30",X"02",X"ED",X"44",X"FE",X"08",X"D0",X"47",X"EB",X"3A",X"6C",X"98",X"96",X"30", + X"02",X"ED",X"44",X"FE",X"08",X"D0",X"A7",X"28",X"03",X"78",X"A7",X"C0",X"21",X"40",X"98",X"3A", + X"04",X"99",X"BE",X"38",X"24",X"3E",X"40",X"DD",X"77",X"00",X"CD",X"BF",X"31",X"28",X"03",X"DD", + X"77",X"30",X"21",X"40",X"98",X"7E",X"36",X"00",X"DD",X"77",X"10",X"21",X"68",X"21",X"DF",X"EB", + X"22",X"15",X"99",X"22",X"1A",X"99",X"C3",X"FE",X"30",X"3E",X"40",X"32",X"80",X"98",X"21",X"04", + X"99",X"7E",X"36",X"00",X"32",X"90",X"98",X"C9",X"00",X"00",X"80",X"00",X"60",X"01",X"40",X"02", + X"20",X"03",X"00",X"04",X"80",X"04",X"60",X"05",X"40",X"06",X"00",X"08",X"21",X"80",X"98",X"7E", + X"A7",X"C8",X"35",X"28",X"2F",X"7E",X"FE",X"2A",X"28",X"4F",X"FE",X"15",X"28",X"51",X"FE",X"3E", + X"C0",X"CD",X"AD",X"33",X"21",X"02",X"9B",X"3A",X"90",X"98",X"3D",X"28",X"0B",X"47",X"04",X"3E", + X"74",X"5E",X"2C",X"56",X"2C",X"12",X"10",X"F9",X"5E",X"2C",X"56",X"3E",X"20",X"12",X"3E",X"64", + X"32",X"00",X"9C",X"C9",X"3A",X"90",X"98",X"3D",X"28",X"19",X"4F",X"0C",X"11",X"02",X"9B",X"21", + X"50",X"9C",X"7E",X"3C",X"87",X"47",X"7E",X"81",X"77",X"78",X"85",X"6F",X"EB",X"CB",X"21",X"06", + X"00",X"ED",X"B0",X"3E",X"20",X"32",X"00",X"9C",X"C9",X"3E",X"68",X"32",X"00",X"9C",X"C9",X"3E", + X"6C",X"32",X"00",X"9C",X"C9",X"21",X"81",X"98",X"7E",X"A7",X"C8",X"35",X"28",X"35",X"3A",X"A1", + X"98",X"A7",X"20",X"67",X"7E",X"FE",X"2A",X"28",X"56",X"FE",X"15",X"28",X"58",X"FE",X"3E",X"C0", + X"CD",X"C5",X"33",X"21",X"42",X"9B",X"3A",X"91",X"98",X"3D",X"28",X"0B",X"47",X"04",X"3E",X"74", + X"5E",X"2C",X"56",X"2C",X"12",X"10",X"F9",X"5E",X"2C",X"56",X"3E",X"20",X"12",X"3E",X"64",X"32", + X"02",X"9C",X"C9",X"3A",X"91",X"98",X"3D",X"28",X"19",X"4F",X"0C",X"11",X"42",X"9B",X"21",X"50", + X"9C",X"7E",X"3C",X"87",X"47",X"7E",X"81",X"77",X"78",X"85",X"6F",X"EB",X"CB",X"21",X"06",X"00", + X"ED",X"B0",X"3E",X"20",X"32",X"02",X"9C",X"AF",X"32",X"A1",X"98",X"32",X"D1",X"98",X"C9",X"3E", + X"68",X"32",X"02",X"9C",X"C9",X"3E",X"6C",X"32",X"02",X"9C",X"C9",X"7E",X"FE",X"3E",X"C0",X"3A", + X"2F",X"99",X"A7",X"28",X"04",X"3E",X"34",X"18",X"02",X"3E",X"37",X"32",X"02",X"9C",X"21",X"42", + X"9B",X"5E",X"2C",X"56",X"3E",X"20",X"12",X"2C",X"5E",X"2C",X"56",X"12",X"C9",X"21",X"82",X"98", + X"7E",X"A7",X"C8",X"35",X"28",X"35",X"3A",X"A2",X"98",X"A7",X"20",X"67",X"7E",X"FE",X"2A",X"28", + X"56",X"FE",X"15",X"28",X"58",X"FE",X"3E",X"C0",X"CD",X"C5",X"33",X"21",X"82",X"9B",X"3A",X"92", + X"98",X"3D",X"28",X"0B",X"47",X"04",X"3E",X"74",X"5E",X"2C",X"56",X"2C",X"12",X"10",X"F9",X"5E", + X"2C",X"56",X"3E",X"20",X"12",X"3E",X"64",X"32",X"04",X"9C",X"C9",X"3A",X"92",X"98",X"3D",X"28", + X"19",X"4F",X"0C",X"11",X"82",X"9B",X"21",X"50",X"9C",X"7E",X"3C",X"87",X"47",X"7E",X"81",X"77", + X"78",X"85",X"6F",X"EB",X"CB",X"21",X"06",X"00",X"ED",X"B0",X"3E",X"20",X"32",X"04",X"9C",X"AF", + X"32",X"A2",X"98",X"32",X"D2",X"98",X"C9",X"3E",X"68",X"32",X"04",X"9C",X"C9",X"3E",X"6C",X"32", + X"04",X"9C",X"C9",X"7E",X"FE",X"3E",X"C0",X"3A",X"2F",X"99",X"A7",X"28",X"04",X"3E",X"34",X"18", + X"02",X"3E",X"37",X"32",X"04",X"9C",X"21",X"82",X"9B",X"5E",X"2C",X"56",X"3E",X"20",X"12",X"2C", + X"5E",X"2C",X"56",X"12",X"C9",X"21",X"83",X"98",X"7E",X"A7",X"C8",X"35",X"28",X"35",X"3A",X"A3", + X"98",X"A7",X"20",X"67",X"7E",X"FE",X"2A",X"28",X"56",X"FE",X"15",X"28",X"58",X"FE",X"3E",X"C0", + X"CD",X"C5",X"33",X"21",X"C2",X"9B",X"3A",X"93",X"98",X"3D",X"28",X"0B",X"47",X"04",X"3E",X"74", + X"5E",X"2C",X"56",X"2C",X"12",X"10",X"F9",X"5E",X"2C",X"56",X"3E",X"20",X"12",X"3E",X"64",X"32", + X"06",X"9C",X"C9",X"3A",X"93",X"98",X"3D",X"28",X"19",X"4F",X"0C",X"11",X"C2",X"9B",X"21",X"50", + X"9C",X"7E",X"3C",X"87",X"47",X"7E",X"81",X"77",X"78",X"85",X"6F",X"EB",X"CB",X"21",X"06",X"00", + X"ED",X"B0",X"3E",X"20",X"32",X"06",X"9C",X"AF",X"32",X"A3",X"98",X"32",X"D3",X"98",X"C9",X"3E", + X"68",X"32",X"06",X"9C",X"C9",X"3E",X"6C",X"32",X"06",X"9C",X"C9",X"7E",X"FE",X"3E",X"C0",X"3A", + X"2F",X"99",X"A7",X"28",X"04",X"3E",X"34",X"18",X"02",X"3E",X"37",X"32",X"06",X"9C",X"21",X"C2", + X"9B",X"5E",X"2C",X"56",X"3E",X"20",X"12",X"2C",X"5E",X"2C",X"56",X"12",X"C9",X"3A",X"2F",X"99", + X"A7",X"C2",X"65",X"24",X"3A",X"04",X"99",X"A7",X"28",X"0E",X"3A",X"80",X"9A",X"C6",X"02",X"E6", + X"03",X"87",X"87",X"C6",X"10",X"32",X"00",X"9C",X"3A",X"05",X"99",X"A7",X"28",X"0E",X"3A",X"A1", + X"9A",X"C6",X"02",X"E6",X"03",X"87",X"87",X"C6",X"24",X"32",X"02",X"9C",X"3A",X"06",X"99",X"A7", + X"28",X"0E",X"3A",X"C1",X"9A",X"C6",X"02",X"E6",X"03",X"87",X"87",X"C6",X"24",X"32",X"04",X"9C", + X"3A",X"07",X"99",X"A7",X"28",X"0E",X"3A",X"E1",X"9A",X"C6",X"02",X"E6",X"03",X"87",X"87",X"C6", + X"24",X"32",X"06",X"9C",X"3A",X"61",X"98",X"C6",X"FA",X"32",X"10",X"9C",X"3A",X"6C",X"98",X"C6", + X"F8",X"32",X"01",X"9C",X"3A",X"11",X"9C",X"E6",X"7F",X"32",X"11",X"9C",X"3A",X"64",X"98",X"C6", + X"FA",X"32",X"12",X"9C",X"3A",X"6D",X"98",X"C6",X"F8",X"32",X"03",X"9C",X"3A",X"13",X"9C",X"E6", + X"7F",X"32",X"13",X"9C",X"3A",X"67",X"98",X"C6",X"FA",X"32",X"14",X"9C",X"3A",X"6E",X"98",X"C6", + X"F8",X"32",X"05",X"9C",X"3A",X"15",X"9C",X"E6",X"7F",X"32",X"15",X"9C",X"3A",X"6A",X"98",X"C6", + X"FA",X"32",X"16",X"9C",X"3A",X"6F",X"98",X"C6",X"F8",X"32",X"07",X"9C",X"3A",X"17",X"9C",X"E6", + X"7F",X"32",X"17",X"9C",X"C9",X"3A",X"04",X"99",X"A7",X"28",X"0C",X"3A",X"80",X"9A",X"E6",X"03", + X"87",X"87",X"C6",X"10",X"32",X"00",X"9C",X"3A",X"05",X"99",X"A7",X"28",X"0C",X"3A",X"A1",X"9A", + X"E6",X"03",X"87",X"87",X"C6",X"24",X"32",X"02",X"9C",X"3A",X"06",X"99",X"A7",X"28",X"0C",X"3A", + X"C1",X"9A",X"E6",X"03",X"87",X"87",X"C6",X"24",X"32",X"04",X"9C",X"3A",X"07",X"99",X"A7",X"28", + X"0C",X"3A",X"E1",X"9A",X"E6",X"03",X"87",X"87",X"C6",X"24",X"32",X"06",X"9C",X"3A",X"61",X"98", + X"2F",X"C6",X"F9",X"32",X"10",X"9C",X"3A",X"6C",X"98",X"2F",X"C6",X"19",X"32",X"01",X"9C",X"3A", + X"11",X"9C",X"38",X"07",X"E6",X"7F",X"32",X"11",X"9C",X"18",X"05",X"F6",X"80",X"32",X"11",X"9C", + X"3A",X"64",X"98",X"2F",X"C6",X"F9",X"32",X"12",X"9C",X"3A",X"6D",X"98",X"2F",X"C6",X"19",X"32", + X"03",X"9C",X"3A",X"13",X"9C",X"38",X"07",X"E6",X"7F",X"32",X"13",X"9C",X"18",X"05",X"F6",X"80", + X"32",X"13",X"9C",X"3A",X"67",X"98",X"2F",X"C6",X"F9",X"32",X"14",X"9C",X"3A",X"6E",X"98",X"2F", + X"C6",X"19",X"32",X"05",X"9C",X"3A",X"15",X"9C",X"38",X"07",X"E6",X"7F",X"32",X"15",X"9C",X"18", + X"05",X"F6",X"80",X"32",X"15",X"9C",X"3A",X"6A",X"98",X"2F",X"C6",X"F9",X"32",X"16",X"9C",X"3A", + X"6F",X"98",X"2F",X"C6",X"19",X"32",X"07",X"9C",X"3A",X"17",X"9C",X"38",X"07",X"E6",X"7F",X"32", + X"17",X"9C",X"18",X"05",X"F6",X"80",X"32",X"17",X"9C",X"C9",X"DD",X"21",X"74",X"98",X"FD",X"21", + X"24",X"9C",X"06",X"06",X"CD",X"5C",X"25",X"FD",X"23",X"DD",X"23",X"CD",X"5C",X"25",X"FD",X"23", + X"DD",X"23",X"CD",X"9D",X"25",X"FD",X"23",X"DD",X"23",X"10",X"F7",X"C9",X"DD",X"7E",X"00",X"A7", + X"28",X"37",X"3A",X"2F",X"99",X"A7",X"28",X"19",X"DD",X"7E",X"10",X"2F",X"C6",X"FF",X"FD",X"77", + X"10",X"DD",X"7E",X"20",X"2F",X"C6",X"1F",X"FD",X"77",X"00",X"38",X"18",X"FD",X"36",X"20",X"0C", + X"C9",X"DD",X"7E",X"10",X"FD",X"77",X"10",X"DD",X"7E",X"20",X"C6",X"FE",X"FD",X"77",X"00",X"FD", + X"36",X"20",X"0C",X"C9",X"FD",X"36",X"20",X"04",X"C9",X"FD",X"77",X"10",X"C9",X"DD",X"7E",X"00", + X"A7",X"28",X"37",X"3A",X"2F",X"99",X"A7",X"28",X"19",X"DD",X"7E",X"10",X"2F",X"C6",X"FF",X"FD", + X"77",X"10",X"DD",X"7E",X"20",X"2F",X"C6",X"1F",X"FD",X"77",X"00",X"38",X"18",X"FD",X"36",X"20", + X"08",X"C9",X"DD",X"7E",X"10",X"FD",X"77",X"10",X"DD",X"7E",X"20",X"C6",X"FE",X"FD",X"77",X"00", + X"FD",X"36",X"20",X"08",X"C9",X"FD",X"36",X"20",X"00",X"C9",X"FD",X"77",X"10",X"C9",X"3A",X"04", + X"99",X"A7",X"C8",X"CD",X"06",X"2D",X"3A",X"17",X"98",X"A7",X"C2",X"6D",X"26",X"3A",X"62",X"98", + X"21",X"60",X"98",X"86",X"77",X"D0",X"21",X"8A",X"9A",X"11",X"8B",X"9A",X"01",X"0B",X"00",X"ED", + X"B8",X"21",X"15",X"9B",X"11",X"17",X"9B",X"01",X"16",X"00",X"ED",X"B8",X"3A",X"16",X"98",X"4F", + X"21",X"80",X"9A",X"96",X"E6",X"03",X"28",X"06",X"FE",X"02",X"28",X"73",X"18",X"29",X"79",X"21", + X"DD",X"26",X"DF",X"2A",X"00",X"9B",X"19",X"7E",X"FE",X"EC",X"30",X"10",X"FE",X"E8",X"30",X"7A", + X"22",X"00",X"9B",X"3A",X"80",X"9A",X"E6",X"03",X"32",X"80",X"9A",X"C9",X"3E",X"00",X"32",X"60", + X"98",X"3E",X"FF",X"32",X"17",X"98",X"C9",X"79",X"21",X"DD",X"26",X"DF",X"2A",X"00",X"9B",X"19", + X"7E",X"FE",X"E8",X"3A",X"80",X"9A",X"30",X"C7",X"22",X"00",X"9B",X"3A",X"80",X"9A",X"E6",X"03", + X"87",X"87",X"81",X"C6",X"04",X"32",X"81",X"9A",X"79",X"32",X"80",X"9A",X"C9",X"3A",X"16",X"98", + X"4F",X"21",X"80",X"9A",X"96",X"E6",X"03",X"C8",X"E6",X"01",X"28",X"13",X"79",X"21",X"DD",X"26", + X"DF",X"2A",X"00",X"9B",X"19",X"7E",X"FE",X"E8",X"D0",X"AF",X"32",X"17",X"98",X"18",X"C9",X"AF", + X"32",X"60",X"98",X"32",X"17",X"98",X"2A",X"04",X"9B",X"22",X"00",X"9B",X"3A",X"80",X"9A",X"C6", + X"02",X"E6",X"03",X"32",X"80",X"9A",X"32",X"81",X"9A",X"C9",X"D6",X"EC",X"E6",X"03",X"4F",X"3A", + X"80",X"9A",X"E6",X"03",X"87",X"87",X"81",X"21",X"E5",X"26",X"CF",X"7E",X"4F",X"21",X"DD",X"26", + X"DF",X"2A",X"00",X"9B",X"19",X"7E",X"FE",X"E8",X"30",X"02",X"18",X"8C",X"79",X"C6",X"02",X"E6", + X"03",X"4F",X"21",X"DD",X"26",X"DF",X"2A",X"00",X"9B",X"19",X"C3",X"58",X"26",X"E0",X"FF",X"01", + X"00",X"20",X"00",X"FF",X"FF",X"01",X"01",X"03",X"03",X"00",X"02",X"00",X"02",X"01",X"01",X"03", + X"03",X"00",X"02",X"00",X"02",X"3A",X"05",X"99",X"A7",X"C8",X"3A",X"D1",X"98",X"A7",X"C2",X"77", + X"28",X"3A",X"65",X"98",X"21",X"63",X"98",X"86",X"77",X"D0",X"21",X"AA",X"9A",X"11",X"AB",X"9A", + X"01",X"0B",X"00",X"ED",X"B8",X"21",X"55",X"9B",X"11",X"57",X"9B",X"01",X"16",X"00",X"ED",X"B8", + X"3A",X"C0",X"98",X"E6",X"1F",X"47",X"3A",X"40",X"9B",X"E6",X"1F",X"90",X"32",X"41",X"98",X"3E", + X"03",X"30",X"02",X"3E",X"01",X"32",X"42",X"98",X"2A",X"C0",X"98",X"29",X"29",X"29",X"7C",X"E6", + X"1F",X"47",X"2A",X"40",X"9B",X"29",X"29",X"29",X"7C",X"E6",X"1F",X"90",X"32",X"43",X"98",X"3E", + X"00",X"30",X"02",X"3E",X"02",X"32",X"44",X"98",X"3A",X"A0",X"9A",X"E6",X"03",X"4F",X"21",X"DD", + X"26",X"DF",X"2A",X"40",X"9B",X"19",X"22",X"50",X"98",X"7E",X"FE",X"E8",X"30",X"3C",X"CD",X"A5", + X"2F",X"E6",X"07",X"28",X"4A",X"21",X"08",X"99",X"BE",X"D2",X"13",X"28",X"3A",X"41",X"98",X"A7", + X"20",X"05",X"3A",X"44",X"98",X"18",X"0A",X"3A",X"43",X"98",X"A7",X"C2",X"42",X"28",X"3A",X"42", + X"98",X"47",X"CD",X"A5",X"2F",X"E6",X"0F",X"FE",X"02",X"38",X"78",X"79",X"90",X"E6",X"03",X"28", + X"7B",X"E6",X"01",X"28",X"1A",X"48",X"79",X"C3",X"4E",X"28",X"CD",X"A5",X"2F",X"E6",X"01",X"28", + X"0E",X"79",X"E6",X"01",X"3A",X"42",X"98",X"28",X"03",X"3A",X"44",X"98",X"4F",X"18",X"09",X"CD", + X"A5",X"2F",X"F6",X"01",X"81",X"E6",X"03",X"4F",X"21",X"DD",X"26",X"DF",X"2A",X"40",X"9B",X"19", + X"7E",X"FE",X"E8",X"30",X"18",X"79",X"32",X"A0",X"9A",X"22",X"40",X"9B",X"21",X"A1",X"9A",X"7E", + X"E6",X"03",X"87",X"87",X"81",X"C6",X"04",X"77",X"AF",X"32",X"71",X"98",X"C9",X"79",X"C6",X"02", + X"E6",X"03",X"4F",X"21",X"DD",X"26",X"DF",X"2A",X"40",X"9B",X"19",X"7E",X"FE",X"E8",X"38",X"D5", + X"3A",X"A0",X"9A",X"E6",X"03",X"4F",X"21",X"DD",X"26",X"DF",X"2A",X"40",X"9B",X"19",X"7E",X"FE", + X"E8",X"30",X"4B",X"CD",X"A5",X"2F",X"E6",X"1F",X"28",X"10",X"18",X"13",X"CD",X"39",X"34",X"CD", + X"A5",X"2F",X"E6",X"07",X"21",X"09",X"99",X"BE",X"30",X"05",X"3E",X"FF",X"32",X"71",X"98",X"2A", + X"50",X"98",X"22",X"40",X"9B",X"C9",X"79",X"E6",X"01",X"78",X"20",X"03",X"3A",X"41",X"98",X"4F", + X"18",X"86",X"79",X"E6",X"01",X"3A",X"42",X"98",X"28",X"03",X"3A",X"44",X"98",X"4F",X"21",X"DD", + X"26",X"DF",X"2A",X"40",X"9B",X"19",X"7E",X"FE",X"E8",X"DA",X"D5",X"27",X"18",X"B5",X"3E",X"80", + X"32",X"63",X"98",X"3E",X"F0",X"32",X"D1",X"98",X"21",X"00",X"03",X"22",X"15",X"99",X"22",X"1A", + X"99",X"CD",X"F3",X"33",X"C3",X"FE",X"30",X"21",X"D1",X"98",X"35",X"20",X"16",X"21",X"05",X"99", + X"7E",X"32",X"91",X"98",X"36",X"00",X"3E",X"40",X"32",X"81",X"98",X"CD",X"BF",X"31",X"C8",X"32", + X"B1",X"98",X"C9",X"7E",X"0F",X"E6",X"07",X"21",X"A0",X"28",X"CF",X"7E",X"32",X"63",X"98",X"C9", + X"C0",X"C0",X"A0",X"A0",X"80",X"80",X"60",X"60",X"3A",X"06",X"99",X"A7",X"C8",X"3A",X"D2",X"98", + X"A7",X"C2",X"1E",X"2A",X"3A",X"68",X"98",X"21",X"66",X"98",X"86",X"77",X"D0",X"21",X"CA",X"9A", + X"11",X"CB",X"9A",X"01",X"0B",X"00",X"ED",X"B8",X"21",X"95",X"9B",X"11",X"97",X"9B",X"01",X"16", + X"00",X"ED",X"B8",X"3A",X"C0",X"98",X"E6",X"1F",X"47",X"3A",X"80",X"9B",X"E6",X"1F",X"90",X"32", + X"41",X"98",X"3E",X"03",X"30",X"02",X"3E",X"01",X"32",X"42",X"98",X"2A",X"C0",X"98",X"29",X"29", + X"29",X"7C",X"E6",X"1F",X"47",X"2A",X"80",X"9B",X"29",X"29",X"29",X"7C",X"E6",X"1F",X"90",X"32", + X"43",X"98",X"3E",X"00",X"30",X"02",X"3E",X"02",X"32",X"44",X"98",X"3A",X"C0",X"9A",X"E6",X"03", + X"4F",X"21",X"DD",X"26",X"DF",X"2A",X"80",X"9B",X"19",X"22",X"50",X"98",X"7E",X"FE",X"E8",X"30", + X"3C",X"CD",X"A5",X"2F",X"E6",X"07",X"28",X"4A",X"21",X"08",X"99",X"BE",X"D2",X"C6",X"29",X"3A", + X"41",X"98",X"A7",X"20",X"05",X"3A",X"44",X"98",X"18",X"0A",X"3A",X"43",X"98",X"A7",X"C2",X"F5", + X"29",X"3A",X"42",X"98",X"47",X"CD",X"A5",X"2F",X"E6",X"0F",X"FE",X"08",X"38",X"78",X"79",X"90", + X"E6",X"03",X"28",X"7B",X"E6",X"01",X"28",X"1A",X"48",X"79",X"C3",X"01",X"2A",X"CD",X"A5",X"2F", + X"E6",X"01",X"28",X"0E",X"79",X"E6",X"01",X"3A",X"42",X"98",X"28",X"03",X"3A",X"44",X"98",X"4F", + X"18",X"09",X"CD",X"A5",X"2F",X"F6",X"01",X"81",X"E6",X"03",X"4F",X"21",X"DD",X"26",X"DF",X"2A", + X"80",X"9B",X"19",X"7E",X"FE",X"E8",X"30",X"18",X"79",X"32",X"C0",X"9A",X"22",X"80",X"9B",X"21", + X"C1",X"9A",X"7E",X"E6",X"03",X"87",X"87",X"81",X"C6",X"04",X"77",X"AF",X"32",X"72",X"98",X"C9", + X"79",X"C6",X"02",X"E6",X"03",X"4F",X"21",X"DD",X"26",X"DF",X"2A",X"80",X"9B",X"19",X"7E",X"FE", + X"E8",X"38",X"D5",X"3A",X"C0",X"9A",X"E6",X"03",X"4F",X"21",X"DD",X"26",X"DF",X"2A",X"80",X"9B", + X"19",X"7E",X"FE",X"E8",X"30",X"4B",X"CD",X"A5",X"2F",X"E6",X"1F",X"28",X"10",X"18",X"13",X"CD", + X"39",X"34",X"CD",X"A5",X"2F",X"E6",X"07",X"21",X"09",X"99",X"BE",X"30",X"05",X"3E",X"FF",X"32", + X"72",X"98",X"2A",X"50",X"98",X"22",X"80",X"9B",X"C9",X"79",X"E6",X"01",X"78",X"20",X"03",X"3A", + X"41",X"98",X"4F",X"18",X"86",X"79",X"E6",X"01",X"3A",X"42",X"98",X"28",X"03",X"3A",X"44",X"98", + X"4F",X"21",X"DD",X"26",X"DF",X"2A",X"80",X"9B",X"19",X"7E",X"FE",X"E8",X"DA",X"88",X"29",X"18", + X"B5",X"3E",X"80",X"32",X"66",X"98",X"3E",X"F0",X"32",X"D2",X"98",X"C3",X"68",X"28",X"21",X"D2", + X"98",X"35",X"20",X"16",X"21",X"06",X"99",X"7E",X"32",X"92",X"98",X"36",X"00",X"3E",X"40",X"32", + X"82",X"98",X"CD",X"BF",X"31",X"C8",X"32",X"B2",X"98",X"C9",X"7E",X"0F",X"E6",X"07",X"21",X"A0", + X"28",X"CF",X"7E",X"32",X"66",X"98",X"C9",X"3A",X"07",X"99",X"A7",X"C8",X"3A",X"D3",X"98",X"A7", + X"C2",X"BD",X"2B",X"3A",X"6B",X"98",X"21",X"69",X"98",X"86",X"77",X"D0",X"21",X"EA",X"9A",X"11", + X"EB",X"9A",X"01",X"0B",X"00",X"ED",X"B8",X"21",X"D5",X"9B",X"11",X"D7",X"9B",X"01",X"16",X"00", + X"ED",X"B8",X"3A",X"C0",X"98",X"E6",X"1F",X"47",X"3A",X"C0",X"9B",X"E6",X"1F",X"90",X"32",X"41", + X"98",X"3E",X"03",X"30",X"02",X"3E",X"01",X"32",X"42",X"98",X"2A",X"C0",X"98",X"29",X"29",X"29", + X"7C",X"E6",X"1F",X"47",X"2A",X"C0",X"9B",X"29",X"29",X"29",X"7C",X"E6",X"1F",X"90",X"32",X"43", + X"98",X"3E",X"00",X"30",X"02",X"3E",X"02",X"32",X"44",X"98",X"3A",X"E0",X"9A",X"E6",X"03",X"4F", + X"21",X"DD",X"26",X"DF",X"2A",X"C0",X"9B",X"19",X"22",X"50",X"98",X"7E",X"FE",X"E8",X"30",X"3C", + X"CD",X"A5",X"2F",X"E6",X"07",X"28",X"4A",X"21",X"08",X"99",X"BE",X"D2",X"65",X"2B",X"3A",X"41", + X"98",X"A7",X"20",X"05",X"3A",X"44",X"98",X"18",X"0A",X"3A",X"43",X"98",X"A7",X"C2",X"94",X"2B", + X"3A",X"42",X"98",X"47",X"CD",X"A5",X"2F",X"E6",X"0F",X"FE",X"0C",X"38",X"78",X"79",X"90",X"E6", + X"03",X"28",X"7B",X"E6",X"01",X"28",X"1A",X"48",X"79",X"C3",X"A0",X"2B",X"CD",X"A5",X"2F",X"E6", + X"01",X"28",X"0E",X"79",X"E6",X"01",X"3A",X"42",X"98",X"28",X"03",X"3A",X"44",X"98",X"4F",X"18", + X"09",X"CD",X"A5",X"2F",X"F6",X"01",X"81",X"E6",X"03",X"4F",X"21",X"DD",X"26",X"DF",X"2A",X"C0", + X"9B",X"19",X"7E",X"FE",X"E8",X"30",X"18",X"79",X"32",X"E0",X"9A",X"22",X"C0",X"9B",X"21",X"E1", + X"9A",X"7E",X"E6",X"03",X"87",X"87",X"81",X"C6",X"04",X"77",X"AF",X"32",X"73",X"98",X"C9",X"79", + X"C6",X"02",X"E6",X"03",X"4F",X"21",X"DD",X"26",X"DF",X"2A",X"C0",X"9B",X"19",X"7E",X"FE",X"E8", + X"38",X"D5",X"3A",X"E0",X"9A",X"E6",X"03",X"4F",X"21",X"DD",X"26",X"DF",X"2A",X"C0",X"9B",X"19", + X"7E",X"FE",X"E8",X"30",X"4B",X"CD",X"A5",X"2F",X"E6",X"1F",X"28",X"10",X"18",X"13",X"CD",X"39", + X"34",X"CD",X"A5",X"2F",X"E6",X"07",X"21",X"09",X"99",X"BE",X"30",X"05",X"3E",X"FF",X"32",X"73", + X"98",X"2A",X"50",X"98",X"22",X"C0",X"9B",X"C9",X"79",X"E6",X"01",X"78",X"20",X"03",X"3A",X"41", + X"98",X"4F",X"18",X"86",X"79",X"E6",X"01",X"3A",X"42",X"98",X"28",X"03",X"3A",X"44",X"98",X"4F", + X"21",X"DD",X"26",X"DF",X"2A",X"C0",X"9B",X"19",X"7E",X"FE",X"E8",X"DA",X"27",X"2B",X"18",X"B5", + X"3E",X"80",X"32",X"69",X"98",X"3E",X"F0",X"32",X"D3",X"98",X"C3",X"68",X"28",X"21",X"D3",X"98", + X"35",X"20",X"16",X"21",X"07",X"99",X"7E",X"32",X"93",X"98",X"36",X"00",X"3E",X"40",X"32",X"83", + X"98",X"CD",X"BF",X"31",X"C8",X"32",X"B3",X"98",X"C9",X"7E",X"0F",X"E6",X"07",X"21",X"A0",X"28", + X"CF",X"7E",X"32",X"69",X"98",X"C9",X"3A",X"04",X"99",X"A7",X"C8",X"3A",X"62",X"98",X"21",X"60", + X"98",X"86",X"77",X"D0",X"21",X"8A",X"9A",X"11",X"8B",X"9A",X"01",X"0B",X"00",X"ED",X"B8",X"21", + X"15",X"9B",X"11",X"17",X"9B",X"01",X"16",X"00",X"ED",X"B8",X"3A",X"80",X"9A",X"E6",X"03",X"4F", + X"21",X"DD",X"26",X"DF",X"2A",X"00",X"9B",X"19",X"22",X"50",X"98",X"7E",X"FE",X"E8",X"30",X"79", + X"CD",X"A5",X"2F",X"E6",X"07",X"FE",X"01",X"38",X"70",X"3A",X"05",X"99",X"A7",X"28",X"05",X"2A", + X"C6",X"98",X"18",X"0E",X"3A",X"06",X"99",X"A7",X"28",X"05",X"2A",X"CA",X"98",X"18",X"03",X"2A", + X"CE",X"98",X"22",X"58",X"98",X"3A",X"58",X"98",X"E6",X"1F",X"47",X"3A",X"00",X"9B",X"E6",X"1F", + X"90",X"28",X"1C",X"06",X"03",X"30",X"02",X"06",X"01",X"2A",X"58",X"98",X"7D",X"E6",X"E0",X"6F", + X"ED",X"5B",X"00",X"9B",X"7B",X"E6",X"E0",X"5F",X"ED",X"52",X"C2",X"EE",X"2C",X"18",X"17",X"2A", + X"58",X"98",X"7D",X"E6",X"E0",X"6F",X"ED",X"5B",X"00",X"9B",X"7B",X"E6",X"E0",X"5F",X"ED",X"52", + X"06",X"02",X"30",X"02",X"06",X"00",X"3E",X"FF",X"32",X"70",X"98",X"79",X"90",X"E6",X"03",X"28", + X"5D",X"E6",X"01",X"28",X"04",X"48",X"79",X"18",X"0D",X"AF",X"32",X"70",X"98",X"CD",X"A5",X"2F", + X"F6",X"01",X"81",X"E6",X"03",X"4F",X"21",X"DD",X"26",X"DF",X"2A",X"00",X"9B",X"19",X"7E",X"FE", + X"E8",X"30",X"14",X"79",X"32",X"80",X"9A",X"22",X"00",X"9B",X"21",X"81",X"9A",X"7E",X"E6",X"03", + X"87",X"87",X"81",X"C6",X"04",X"77",X"C9",X"79",X"C6",X"02",X"E6",X"03",X"4F",X"21",X"DD",X"26", + X"DF",X"2A",X"00",X"9B",X"19",X"7E",X"FE",X"E8",X"38",X"D9",X"3A",X"80",X"9A",X"E6",X"03",X"4F", + X"21",X"DD",X"26",X"DF",X"2A",X"00",X"9B",X"19",X"7E",X"FE",X"E8",X"D2",X"8F",X"26",X"2A",X"50", + X"98",X"22",X"00",X"9B",X"C9",X"CD",X"A5",X"2F",X"E6",X"0F",X"20",X"08",X"CD",X"A5",X"2F",X"E6", + X"03",X"3C",X"4F",X"C9",X"AF",X"C9",X"3A",X"2F",X"99",X"A7",X"28",X"29",X"0E",X"04",X"3A",X"05", + X"98",X"CB",X"7F",X"20",X"17",X"0D",X"3A",X"03",X"98",X"CB",X"6F",X"20",X"0F",X"0D",X"3A",X"04", + X"98",X"CB",X"47",X"20",X"07",X"0D",X"3A",X"03",X"98",X"CB",X"67",X"C8",X"79",X"3D",X"32",X"16", + X"98",X"3E",X"FF",X"A7",X"C9",X"0E",X"04",X"3A",X"04",X"98",X"CB",X"4F",X"20",X"17",X"0D",X"3A", + X"04",X"98",X"CB",X"67",X"20",X"0F",X"0D",X"3A",X"03",X"98",X"CB",X"47",X"20",X"07",X"0D",X"3A", + X"04",X"98",X"CB",X"6F",X"C8",X"79",X"3D",X"32",X"16",X"98",X"3E",X"FF",X"A7",X"C9",X"21",X"50", + X"9C",X"7E",X"A7",X"C8",X"47",X"36",X"00",X"3E",X"20",X"2C",X"2C",X"5E",X"2C",X"56",X"12",X"10", + X"F9",X"C9",X"21",X"00",X"9D",X"34",X"08",X"7E",X"87",X"87",X"6F",X"73",X"2C",X"72",X"2C",X"08", + X"77",X"2C",X"EB",X"C9",X"3A",X"00",X"9D",X"A7",X"C8",X"47",X"21",X"04",X"9D",X"AF",X"32",X"00", + X"9D",X"5E",X"2C",X"56",X"2C",X"7E",X"12",X"2C",X"CB",X"DA",X"7E",X"12",X"2C",X"10",X"F2",X"C9", + X"3A",X"04",X"99",X"A7",X"C8",X"32",X"40",X"98",X"21",X"99",X"2F",X"11",X"48",X"98",X"01",X"03", + X"00",X"ED",X"B0",X"21",X"05",X"9B",X"87",X"CF",X"E5",X"DD",X"E1",X"3A",X"40",X"98",X"21",X"80", + X"9A",X"CF",X"E5",X"FD",X"E1",X"3A",X"60",X"98",X"07",X"07",X"07",X"E6",X"07",X"32",X"41",X"98", + X"21",X"11",X"9C",X"22",X"54",X"98",X"CD",X"A5",X"2E",X"21",X"56",X"98",X"11",X"C0",X"98",X"01", + X"04",X"00",X"ED",X"B0",X"C9",X"3A",X"05",X"99",X"A7",X"C8",X"32",X"40",X"98",X"CD",X"7B",X"2F", + X"3A",X"40",X"98",X"21",X"45",X"9B",X"87",X"CF",X"E5",X"DD",X"E1",X"3A",X"40",X"98",X"21",X"A0", + X"9A",X"CF",X"E5",X"FD",X"E1",X"3A",X"63",X"98",X"07",X"07",X"07",X"E6",X"07",X"32",X"41",X"98", + X"21",X"13",X"9C",X"22",X"54",X"98",X"CD",X"A5",X"2E",X"21",X"56",X"98",X"11",X"C4",X"98",X"01", + X"04",X"00",X"ED",X"B0",X"C9",X"3A",X"06",X"99",X"A7",X"C8",X"32",X"40",X"98",X"CD",X"7B",X"2F", + X"3A",X"40",X"98",X"21",X"85",X"9B",X"87",X"CF",X"E5",X"DD",X"E1",X"3A",X"40",X"98",X"21",X"C0", + X"9A",X"CF",X"E5",X"FD",X"E1",X"3A",X"66",X"98",X"07",X"07",X"07",X"E6",X"07",X"32",X"41",X"98", + X"21",X"15",X"9C",X"22",X"54",X"98",X"CD",X"A5",X"2E",X"21",X"56",X"98",X"11",X"C8",X"98",X"01", + X"04",X"00",X"ED",X"B0",X"C9",X"3A",X"07",X"99",X"A7",X"C8",X"32",X"40",X"98",X"CD",X"7B",X"2F", + X"3A",X"40",X"98",X"21",X"C5",X"9B",X"87",X"CF",X"E5",X"DD",X"E1",X"3A",X"40",X"98",X"21",X"E0", + X"9A",X"CF",X"E5",X"FD",X"E1",X"3A",X"69",X"98",X"07",X"07",X"07",X"E6",X"07",X"32",X"41",X"98", + X"21",X"17",X"9C",X"22",X"54",X"98",X"CD",X"A5",X"2E",X"21",X"56",X"98",X"11",X"CC",X"98",X"01", + X"04",X"00",X"ED",X"B0",X"C9",X"3A",X"48",X"98",X"2A",X"54",X"98",X"CB",X"7E",X"77",X"28",X"02", + X"CB",X"FE",X"DD",X"56",X"00",X"DD",X"2B",X"DD",X"5E",X"00",X"DD",X"2B",X"21",X"50",X"9C",X"34", + X"7E",X"87",X"85",X"6F",X"73",X"2C",X"72",X"DD",X"56",X"00",X"DD",X"2B",X"DD",X"5E",X"00",X"DD", + X"2B",X"21",X"50",X"9C",X"34",X"7E",X"87",X"85",X"6F",X"73",X"2C",X"72",X"21",X"40",X"98",X"35", + X"20",X"13",X"DD",X"66",X"00",X"DD",X"6E",X"FF",X"22",X"56",X"98",X"DD",X"66",X"FE",X"DD",X"6E", + X"FD",X"22",X"58",X"98",X"C9",X"DD",X"56",X"00",X"DD",X"2B",X"DD",X"5E",X"00",X"DD",X"2B",X"FD", + X"7E",X"00",X"FD",X"2B",X"ED",X"53",X"56",X"98",X"21",X"28",X"3F",X"85",X"6F",X"46",X"25",X"3A", + X"41",X"98",X"86",X"CD",X"72",X"2D",X"3A",X"4A",X"98",X"B0",X"12",X"DD",X"66",X"00",X"DD",X"6E", + X"FF",X"22",X"58",X"98",X"DD",X"56",X"00",X"DD",X"2B",X"DD",X"5E",X"00",X"DD",X"2B",X"FD",X"7E", + X"00",X"FD",X"2B",X"21",X"14",X"3F",X"85",X"6F",X"46",X"25",X"3A",X"41",X"98",X"86",X"CD",X"72", + X"2D",X"3A",X"4A",X"98",X"B0",X"12",X"3A",X"40",X"98",X"3D",X"28",X"29",X"47",X"C5",X"DD",X"56", + X"00",X"DD",X"2B",X"DD",X"5E",X"00",X"DD",X"2B",X"FD",X"7E",X"00",X"FD",X"2B",X"21",X"00",X"3F", + X"85",X"6F",X"46",X"25",X"3A",X"41",X"98",X"86",X"CD",X"72",X"2D",X"3A",X"4A",X"98",X"B0",X"12", + X"78",X"C1",X"10",X"D9",X"47",X"3A",X"49",X"98",X"B0",X"12",X"C9",X"21",X"04",X"99",X"BE",X"28", + X"07",X"30",X"0A",X"21",X"9C",X"2F",X"18",X"08",X"21",X"9F",X"2F",X"18",X"03",X"21",X"A2",X"2F", + X"11",X"48",X"98",X"01",X"03",X"00",X"ED",X"B0",X"C9",X"2B",X"06",X"30",X"0F",X"02",X"10",X"16", + X"03",X"18",X"0A",X"01",X"08",X"D9",X"21",X"0F",X"9E",X"11",X"10",X"9E",X"01",X"10",X"00",X"ED", + X"B8",X"21",X"10",X"9E",X"3A",X"07",X"9E",X"AE",X"32",X"00",X"9E",X"21",X"02",X"98",X"86",X"D9", + X"C9",X"D9",X"3A",X"03",X"98",X"0F",X"0F",X"0F",X"21",X"22",X"99",X"CB",X"16",X"7E",X"E6",X"07", + X"FE",X"01",X"C0",X"CD",X"A1",X"33",X"3E",X"01",X"C3",X"3E",X"30",X"3A",X"03",X"98",X"21",X"27", + X"99",X"07",X"07",X"CB",X"16",X"7E",X"E6",X"07",X"FE",X"01",X"C0",X"EB",X"CD",X"A1",X"33",X"21", + X"30",X"99",X"34",X"EB",X"23",X"7E",X"C6",X"10",X"77",X"47",X"23",X"7E",X"90",X"D0",X"7E",X"4F", + X"E6",X"F0",X"C6",X"10",X"2B",X"ED",X"44",X"86",X"77",X"79",X"E6",X"0F",X"18",X"30",X"3A",X"03", + X"98",X"21",X"24",X"99",X"07",X"CB",X"16",X"7E",X"E6",X"07",X"FE",X"01",X"C0",X"EB",X"CD",X"A1", + X"33",X"21",X"2A",X"99",X"34",X"EB",X"23",X"7E",X"C6",X"10",X"77",X"47",X"23",X"7E",X"90",X"D0", + X"7E",X"4F",X"E6",X"F0",X"C6",X"10",X"2B",X"ED",X"44",X"86",X"77",X"79",X"E6",X"0F",X"21",X"23", + X"99",X"86",X"27",X"77",X"30",X"02",X"36",X"99",X"11",X"06",X"83",X"21",X"16",X"01",X"FF",X"21", + X"BF",X"FF",X"19",X"EB",X"3A",X"23",X"99",X"CD",X"B1",X"30",X"21",X"06",X"8B",X"11",X"20",X"00", + X"3E",X"A3",X"06",X"06",X"77",X"19",X"10",X"FC",X"C9",X"3A",X"2A",X"99",X"A7",X"C8",X"21",X"2B", + X"99",X"7E",X"A7",X"20",X"07",X"36",X"30",X"3C",X"32",X"84",X"A1",X"C9",X"35",X"28",X"09",X"7E", + X"FE",X"18",X"C0",X"AF",X"32",X"84",X"A1",X"C9",X"21",X"2A",X"99",X"35",X"C9",X"3A",X"30",X"99", + X"A7",X"C8",X"21",X"31",X"99",X"7E",X"A7",X"20",X"07",X"36",X"30",X"3C",X"32",X"86",X"A1",X"C9", + X"35",X"28",X"09",X"7E",X"FE",X"18",X"C0",X"AF",X"32",X"86",X"A1",X"C9",X"21",X"30",X"99",X"35", + X"C9",X"FE",X"0A",X"4F",X"38",X"0F",X"4F",X"0F",X"0F",X"0F",X"0F",X"E6",X"0F",X"12",X"D7",X"79", + X"E6",X"0F",X"12",X"D7",X"C9",X"3E",X"20",X"18",X"F4",X"4F",X"0F",X"0F",X"0F",X"0F",X"E6",X"0F", + X"CD",X"D6",X"30",X"79",X"E6",X"0F",X"28",X"04",X"04",X"12",X"D7",X"C9",X"78",X"A7",X"28",X"03", + X"AF",X"18",X"F6",X"3E",X"20",X"18",X"F2",X"7E",X"FE",X"40",X"C8",X"3E",X"20",X"12",X"23",X"D7", + X"18",X"F5",X"CB",X"DA",X"7E",X"FE",X"40",X"C8",X"79",X"12",X"23",X"D7",X"18",X"F6",X"3A",X"20", + X"99",X"FE",X"04",X"D0",X"3A",X"11",X"99",X"A7",X"20",X"79",X"FD",X"21",X"12",X"99",X"11",X"A2", + X"80",X"21",X"78",X"01",X"FD",X"7E",X"03",X"FD",X"86",X"00",X"27",X"FD",X"77",X"00",X"FD",X"7E", + X"04",X"FD",X"8E",X"01",X"27",X"FD",X"77",X"01",X"3E",X"00",X"FD",X"8E",X"02",X"27",X"FD",X"77", + X"02",X"E6",X"0F",X"FE",X"02",X"28",X"0A",X"FE",X"07",X"28",X"06",X"AF",X"32",X"02",X"99",X"18", + X"03",X"CD",X"9A",X"3E",X"DD",X"21",X"1C",X"99",X"FD",X"7E",X"02",X"DD",X"BE",X"02",X"38",X"49", + X"28",X"02",X"18",X"14",X"FD",X"7E",X"01",X"DD",X"BE",X"01",X"38",X"3D",X"28",X"02",X"18",X"08", + X"DD",X"7E",X"00",X"FD",X"BE",X"00",X"30",X"31",X"FD",X"7E",X"00",X"DD",X"77",X"00",X"FD",X"7E", + X"01",X"DD",X"77",X"01",X"FD",X"7E",X"02",X"DD",X"77",X"02",X"D5",X"E5",X"CD",X"84",X"1A",X"E1", + X"D1",X"18",X"16",X"FD",X"21",X"17",X"99",X"11",X"62",X"83",X"21",X"7C",X"01",X"18",X"85",X"FD", + X"21",X"12",X"99",X"11",X"A2",X"80",X"21",X"78",X"01",X"FF",X"21",X"3F",X"FF",X"19",X"EB",X"FD", + X"7E",X"02",X"06",X"00",X"CD",X"C9",X"30",X"FD",X"7E",X"01",X"CD",X"C9",X"30",X"FD",X"7E",X"00", + X"C3",X"B6",X"30",X"FD",X"21",X"17",X"99",X"11",X"62",X"83",X"21",X"7C",X"01",X"18",X"DA",X"21", + X"0F",X"99",X"7E",X"A7",X"C8",X"35",X"7E",X"FE",X"03",X"28",X"03",X"3E",X"40",X"C9",X"3E",X"40", + X"32",X"B0",X"98",X"C9",X"3A",X"01",X"99",X"E6",X"03",X"06",X"9C",X"20",X"02",X"06",X"8E",X"21", + X"B0",X"98",X"11",X"BB",X"8F",X"CD",X"FA",X"31",X"23",X"11",X"5B",X"8C",X"CD",X"FA",X"31",X"23", + X"11",X"41",X"8C",X"CD",X"FA",X"31",X"23",X"11",X"A1",X"8F",X"7E",X"A7",X"C8",X"35",X"28",X"11", + X"CB",X"56",X"3E",X"00",X"28",X"02",X"3E",X"87",X"E6",X"3F",X"4F",X"1A",X"E6",X"C0",X"B1",X"12", + X"C9",X"78",X"18",X"F4",X"3A",X"04",X"99",X"A7",X"C8",X"3A",X"02",X"98",X"E6",X"3F",X"C0",X"CD", + X"A5",X"2F",X"E6",X"07",X"FE",X"03",X"D0",X"FE",X"01",X"38",X"3C",X"28",X"1D",X"3A",X"07",X"99", + X"A7",X"28",X"04",X"32",X"73",X"98",X"C9",X"3A",X"05",X"99",X"A7",X"28",X"04",X"32",X"71",X"98", + X"C9",X"3A",X"06",X"99",X"A7",X"C8",X"32",X"72",X"98",X"C9",X"3A",X"06",X"99",X"A7",X"28",X"04", + X"32",X"72",X"98",X"C9",X"3A",X"07",X"99",X"A7",X"28",X"04",X"32",X"73",X"98",X"C9",X"3A",X"05", + X"99",X"A7",X"C8",X"32",X"71",X"98",X"C9",X"3A",X"05",X"99",X"A7",X"28",X"04",X"32",X"71",X"98", + X"C9",X"3A",X"06",X"99",X"A7",X"28",X"04",X"32",X"72",X"98",X"C9",X"3A",X"07",X"99",X"A7",X"C8", + X"32",X"73",X"98",X"C9",X"3A",X"01",X"99",X"E6",X"03",X"0E",X"1D",X"20",X"02",X"0E",X"0F",X"21", + X"08",X"98",X"7E",X"47",X"34",X"87",X"87",X"87",X"6F",X"26",X"00",X"29",X"29",X"11",X"41",X"84", + X"19",X"78",X"A7",X"CA",X"1D",X"33",X"FE",X"1B",X"CA",X"3E",X"33",X"E5",X"3A",X"01",X"99",X"3D", + X"E6",X"07",X"21",X"43",X"34",X"DF",X"EB",X"11",X"0C",X"00",X"05",X"28",X"03",X"19",X"10",X"FD", + X"EB",X"E1",X"36",X"F8",X"CB",X"DC",X"CB",X"F1",X"71",X"CB",X"9C",X"23",X"36",X"20",X"23",X"06", + X"0C",X"CB",X"F9",X"CB",X"B1",X"1A",X"0F",X"0F",X"0F",X"0F",X"E6",X"0F",X"FE",X"0F",X"28",X"2D", + X"C6",X"E8",X"77",X"CB",X"DC",X"FE",X"F5",X"28",X"2C",X"71",X"CB",X"9C",X"23",X"1A",X"E6",X"0F", + X"FE",X"0F",X"28",X"1D",X"C6",X"E8",X"77",X"CB",X"DC",X"FE",X"F5",X"28",X"1C",X"71",X"CB",X"9C", + X"23",X"13",X"10",X"D1",X"36",X"F8",X"CB",X"DC",X"71",X"3E",X"FF",X"A7",X"C9",X"3E",X"20",X"18", + X"D1",X"3E",X"20",X"18",X"E1",X"36",X"BE",X"18",X"D1",X"36",X"BE",X"18",X"E1",X"CB",X"F1",X"36", + X"FA",X"CB",X"DC",X"71",X"CB",X"9C",X"23",X"CB",X"B1",X"06",X"19",X"36",X"F9",X"CB",X"DC",X"71", + X"CB",X"9C",X"23",X"10",X"F6",X"36",X"FA",X"CB",X"DC",X"71",X"3E",X"FF",X"A7",X"C9",X"36",X"FA", + X"CB",X"DC",X"CB",X"F9",X"CB",X"F1",X"71",X"CB",X"9C",X"23",X"06",X"19",X"36",X"F9",X"CB",X"DC", + X"71",X"CB",X"9C",X"23",X"10",X"F6",X"36",X"FA",X"CB",X"DC",X"CB",X"B1",X"71",X"AF",X"C9",X"21", + X"F0",X"99",X"7E",X"A7",X"C8",X"35",X"F5",X"23",X"7E",X"CD",X"78",X"33",X"F1",X"C8",X"3D",X"06", + X"00",X"4F",X"5D",X"54",X"23",X"ED",X"B0",X"C9",X"32",X"00",X"A1",X"3E",X"00",X"32",X"80",X"A1", + X"00",X"00",X"00",X"00",X"3E",X"01",X"32",X"80",X"A1",X"C9",X"F5",X"FE",X"05",X"28",X"07",X"3A", + X"20",X"99",X"FE",X"04",X"30",X"09",X"21",X"F0",X"99",X"34",X"7E",X"CF",X"F1",X"77",X"C9",X"F1", + X"C9",X"3E",X"05",X"18",X"E5",X"3E",X"07",X"18",X"E1",X"3E",X"06",X"18",X"DD",X"AF",X"CD",X"8A", + X"33",X"3E",X"02",X"CD",X"8A",X"33",X"3E",X"0F",X"C3",X"8A",X"33",X"3E",X"01",X"C3",X"8A",X"33", + X"3E",X"81",X"C3",X"8A",X"33",X"3E",X"03",X"CD",X"8A",X"33",X"3E",X"08",X"CD",X"8A",X"33",X"3A", + X"01",X"99",X"E6",X"03",X"C0",X"21",X"04",X"99",X"7E",X"A7",X"C8",X"FE",X"09",X"D0",X"34",X"7E", + X"CD",X"4F",X"1E",X"32",X"62",X"98",X"C9",X"3E",X"09",X"18",X"9F",X"3E",X"0B",X"18",X"9B",X"3E", + X"04",X"18",X"D9",X"3E",X"19",X"18",X"93",X"3E",X"0A",X"18",X"8F",X"3E",X"10",X"CD",X"8A",X"33", + X"3E",X"11",X"CD",X"8A",X"33",X"3E",X"12",X"C3",X"8A",X"33",X"AF",X"32",X"18",X"9C",X"CD",X"8A", + X"33",X"3E",X"13",X"CD",X"8A",X"33",X"3E",X"14",X"CD",X"8A",X"33",X"3E",X"15",X"C3",X"8A",X"33", + X"3E",X"16",X"CD",X"8A",X"33",X"3E",X"17",X"CD",X"8A",X"33",X"3E",X"18",X"C3",X"8A",X"33",X"3E", + X"0D",X"C3",X"8A",X"33",X"3E",X"0C",X"C3",X"8A",X"33",X"3A",X"04",X"99",X"A7",X"C8",X"3E",X"0E", + X"C3",X"8A",X"33",X"53",X"34",X"53",X"34",X"8B",X"35",X"8B",X"35",X"C3",X"36",X"C3",X"36",X"FB", + X"37",X"FB",X"37",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"24", + X"44",X"0F",X"24",X"44",X"0F",X"20",X"F2",X"0F",X"24",X"44",X"0F",X"35",X"55",X"1F",X"35",X"55", + X"1F",X"76",X"F3",X"1F",X"35",X"5B",X"6F",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"76",X"FF",X"FF", + X"FF",X"F7",X"6F",X"24",X"44",X"44",X"40",X"F2",X"44",X"A6",X"F2",X"0F",X"20",X"F7",X"6F",X"35", + X"55",X"55",X"51",X"F3",X"55",X"51",X"F3",X"1F",X"31",X"F7",X"6F",X"DF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"F7",X"6F",X"24",X"44",X"44",X"44",X"44",X"0F",X"24",X"44",X"44", + X"40",X"F7",X"6F",X"35",X"55",X"55",X"55",X"5B",X"6F",X"35",X"55",X"55",X"B6",X"F3",X"1F",X"FF", + X"FF",X"FF",X"FF",X"F7",X"6F",X"FF",X"FF",X"FF",X"76",X"FF",X"FF",X"24",X"44",X"0F",X"20",X"F7", + X"6F",X"24",X"44",X"0F",X"76",X"F2",X"0F",X"35",X"55",X"1F",X"31",X"F3",X"1F",X"35",X"55",X"1F", + X"31",X"F3",X"1F",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"24",X"44",X"44",X"40",X"F2", + X"0F",X"24",X"44",X"44",X"40",X"F2",X"0F",X"35",X"55",X"55",X"51",X"F7",X"6F",X"35",X"55",X"55", + X"51",X"F7",X"6F",X"FF",X"FF",X"FF",X"FF",X"F7",X"6F",X"FF",X"FF",X"FF",X"FF",X"F7",X"6F",X"20", + X"F2",X"0F",X"20",X"F7",X"6F",X"20",X"F2",X"0F",X"24",X"4A",X"6F",X"31",X"F3",X"1F",X"76",X"F3", + X"1F",X"31",X"F7",X"6F",X"35",X"5B",X"6F",X"FF",X"FF",X"FF",X"76",X"FF",X"FF",X"FF",X"F7",X"6F", + X"FF",X"F7",X"6F",X"24",X"44",X"0F",X"76",X"F2",X"44",X"40",X"F7",X"84",X"40",X"F7",X"6F",X"35", + X"55",X"1F",X"76",X"F3",X"55",X"B6",X"F3",X"55",X"51",X"F3",X"1F",X"FF",X"FF",X"FF",X"76",X"FF", + X"FF",X"76",X"FF",X"FF",X"FF",X"FF",X"FF",X"20",X"F2",X"44",X"A6",X"F2",X"0F",X"78",X"44",X"44", + X"44",X"44",X"0F",X"31",X"F3",X"55",X"51",X"F3",X"1F",X"35",X"55",X"55",X"55",X"55",X"1F",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"20",X"F2",X"44",X"44",X"44",X"0F",X"20",X"F2",X"44", + X"40",X"F2",X"0F",X"76",X"F7",X"95",X"55",X"5B",X"6F",X"76",X"F3",X"55",X"51",X"F7",X"6F",X"76", + X"F7",X"6F",X"FF",X"F7",X"6F",X"76",X"FF",X"FF",X"FF",X"F7",X"6F",X"76",X"F7",X"6F",X"20",X"F7", + X"6F",X"76",X"F2",X"44",X"44",X"4A",X"6F",X"76",X"F7",X"6F",X"76",X"F7",X"6F",X"76",X"F7",X"95", + X"55",X"55",X"1F",X"76",X"F7",X"6F",X"76",X"F7",X"6F",X"76",X"F7",X"6F",X"FF",X"FF",X"FF",X"76", + X"F7",X"6F",X"76",X"F7",X"6F",X"76",X"F7",X"6F",X"24",X"44",X"0F",X"76",X"F3",X"1F",X"76",X"F7", + X"6F",X"31",X"F7",X"6F",X"35",X"55",X"1F",X"76",X"FF",X"FF",X"76",X"F7",X"6F",X"FF",X"F7",X"6F", + X"DF",X"FF",X"FF",X"78",X"44",X"44",X"A6",X"F7",X"6F",X"24",X"4A",X"6F",X"24",X"44",X"0F",X"35", + X"55",X"55",X"51",X"F3",X"1F",X"35",X"55",X"1F",X"35",X"55",X"1F",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"20",X"F2",X"0F",X"20",X"F2",X"0F",X"24",X"44",X"44",X"40",X"F2",X"0F",X"76", + X"F7",X"6F",X"76",X"F7",X"6F",X"79",X"55",X"55",X"B6",X"F7",X"6F",X"76",X"F7",X"6F",X"76",X"F7", + X"6F",X"76",X"FF",X"FF",X"76",X"F7",X"6F",X"76",X"F7",X"6F",X"76",X"F7",X"6F",X"76",X"F2",X"0F", + X"76",X"F7",X"6F",X"76",X"F7",X"6F",X"76",X"F7",X"6F",X"31",X"F7",X"6F",X"31",X"F3",X"1F",X"76", + X"F7",X"6F",X"76",X"F7",X"6F",X"FF",X"F7",X"6F",X"FF",X"FF",X"FF",X"76",X"F7",X"6F",X"76",X"F7", + X"6F",X"24",X"4A",X"84",X"44",X"44",X"0F",X"31",X"F7",X"6F",X"31",X"F7",X"6F",X"35",X"55",X"55", + X"55",X"55",X"1F",X"FF",X"F7",X"6F",X"FF",X"F7",X"6F",X"FF",X"FF",X"DF",X"FF",X"FF",X"FF",X"20", + X"F7",X"84",X"44",X"4A",X"6F",X"24",X"44",X"0F",X"24",X"44",X"0F",X"31",X"F3",X"55",X"55",X"55", + X"1F",X"35",X"55",X"1F",X"35",X"55",X"1F",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"24", + X"44",X"44",X"40",X"F2",X"0F",X"24",X"44",X"0F",X"20",X"F2",X"0F",X"79",X"55",X"55",X"51",X"F7", + X"6F",X"35",X"55",X"1F",X"76",X"F3",X"1F",X"76",X"DF",X"FF",X"FF",X"F7",X"6F",X"FF",X"FF",X"FF", + X"76",X"FF",X"FF",X"76",X"F2",X"0F",X"20",X"F7",X"6F",X"20",X"F2",X"44",X"A6",X"F2",X"0F",X"76", + X"F3",X"1F",X"76",X"F7",X"6F",X"76",X"F3",X"55",X"51",X"F7",X"6F",X"76",X"FF",X"FF",X"76",X"F7", + X"6F",X"76",X"FF",X"FF",X"FF",X"F7",X"6F",X"76",X"F2",X"44",X"A6",X"F7",X"6F",X"78",X"44",X"0F", + X"20",X"F7",X"6F",X"76",X"F3",X"55",X"51",X"F7",X"6F",X"79",X"55",X"1F",X"76",X"F7",X"6F",X"76", + X"FF",X"FF",X"FF",X"F7",X"6F",X"76",X"FF",X"FF",X"76",X"F7",X"6F",X"76",X"F2",X"44",X"44",X"4A", + X"6F",X"76",X"F2",X"44",X"A6",X"F7",X"6F",X"31",X"F3",X"55",X"55",X"55",X"1F",X"31",X"F3",X"55", + X"51",X"F3",X"1F",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"20",X"F2",X"44",X"40",X"F2", + X"0F",X"24",X"44",X"0F",X"24",X"44",X"0F",X"76",X"F3",X"55",X"B6",X"F7",X"6F",X"35",X"55",X"1F", + X"35",X"5B",X"6F",X"76",X"FF",X"FF",X"76",X"F7",X"6F",X"FF",X"FF",X"FF",X"FF",X"F7",X"6F",X"76", + X"F2",X"0F",X"76",X"F7",X"6F",X"20",X"F2",X"44",X"40",X"F7",X"6F",X"31",X"F7",X"6F",X"31",X"F3", + X"1F",X"76",X"F3",X"55",X"51",X"F7",X"6F",X"FF",X"F7",X"6F",X"FF",X"FF",X"FF",X"76",X"FF",X"FF", + X"FF",X"F7",X"6F",X"20",X"F7",X"84",X"44",X"44",X"0F",X"76",X"F2",X"44",X"40",X"F7",X"6F",X"31", + X"F3",X"55",X"55",X"5B",X"6F",X"76",X"F3",X"55",X"51",X"F3",X"1F",X"FF",X"FF",X"FF",X"FF",X"F7", + X"6F",X"76",X"FF",X"FF",X"FF",X"FF",X"FF",X"24",X"44",X"44",X"40",X"F7",X"6F",X"78",X"44",X"0F", + X"24",X"44",X"0F",X"35",X"55",X"55",X"51",X"F3",X"1F",X"35",X"55",X"1F",X"35",X"55",X"1F",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"20",X"F2",X"0F",X"20",X"F2",X"0F",X"20",X"F2",X"0F", + X"20",X"F2",X"0F",X"31",X"F3",X"1F",X"31",X"F3",X"1F",X"31",X"F3",X"1F",X"31",X"F3",X"1F",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"20",X"F2",X"0F",X"20",X"F2", + X"0F",X"20",X"F2",X"0F",X"20",X"F2",X"0F",X"31",X"F3",X"1F",X"31",X"F3",X"1F",X"31",X"F3",X"1F", + X"31",X"F3",X"1F",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"20", + X"F2",X"0F",X"20",X"F2",X"0F",X"20",X"F2",X"0F",X"20",X"F2",X"0F",X"31",X"F3",X"1F",X"31",X"F3", + X"1F",X"31",X"F3",X"1F",X"31",X"F3",X"1F",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"20",X"F2",X"0F",X"20",X"F2",X"0F",X"20",X"F2",X"0F",X"20",X"F2",X"0F",X"31", + X"F3",X"1F",X"31",X"F3",X"1F",X"31",X"F3",X"1F",X"31",X"F3",X"1F",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"20",X"F2",X"0F",X"20",X"F2",X"0F",X"20",X"F2",X"0F",X"20",X"F2",X"0F",X"31", + X"F3",X"1F",X"31",X"F3",X"1F",X"31",X"F3",X"1F",X"31",X"F3",X"1F",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"20",X"F2",X"0F",X"20",X"F2",X"0F",X"20",X"F2",X"0F", + X"20",X"F2",X"0F",X"31",X"F3",X"1F",X"31",X"F3",X"1F",X"31",X"F3",X"1F",X"31",X"F3",X"1F",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FD",X"FF",X"FF",X"FF",X"20",X"F2",X"0F",X"20",X"F2", + X"0F",X"20",X"F2",X"0F",X"20",X"F2",X"0F",X"31",X"F3",X"1F",X"31",X"F3",X"1F",X"31",X"F3",X"1F", + X"31",X"F3",X"1F",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"20", + X"F2",X"0F",X"20",X"F2",X"0F",X"20",X"F2",X"0F",X"20",X"F2",X"0F",X"31",X"F3",X"1F",X"31",X"F3", + X"1F",X"31",X"F3",X"1F",X"31",X"F3",X"1F",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"3A",X"1A",X"9C",X"A7",X"C8",X"3A",X"04",X"99",X"A7",X"C8",X"3A",X"19",X"98", + X"A7",X"20",X"44",X"21",X"1A",X"9C",X"11",X"0B",X"9C",X"3A",X"10",X"9C",X"96",X"30",X"02",X"ED", + X"44",X"FE",X"08",X"D0",X"47",X"EB",X"3A",X"01",X"9C",X"96",X"30",X"02",X"ED",X"44",X"FE",X"08", + X"D0",X"CD",X"34",X"34",X"CD",X"D5",X"33",X"3E",X"40",X"32",X"19",X"98",X"3A",X"2F",X"99",X"A7", + X"28",X"04",X"3E",X"34",X"18",X"02",X"3E",X"37",X"32",X"0A",X"9C",X"21",X"00",X"05",X"22",X"15", + X"99",X"22",X"1A",X"99",X"C3",X"FE",X"30",X"3D",X"32",X"19",X"98",X"C0",X"AF",X"32",X"1A",X"9C", + X"C9",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"80",X"88",X"80",X"88",X"FF",X"98",X"FF",X"98",X"90",X"FF",X"90",X"FF",X"FF",X"98",X"FF",X"98", + X"90",X"FF",X"90",X"FF",X"A0",X"A8",X"A0",X"A8",X"FF",X"B8",X"FF",X"B8",X"B0",X"FF",X"B0",X"FF", + X"FF",X"B8",X"FF",X"B8",X"B0",X"FF",X"B0",X"FF",X"C0",X"C8",X"C0",X"C8",X"FF",X"D8",X"FF",X"D8", + X"D0",X"FF",X"D0",X"FF",X"FF",X"D8",X"FF",X"D8",X"D0",X"FF",X"D0",X"FF",X"3A",X"18",X"9C",X"A7", + X"C8",X"3A",X"04",X"99",X"A7",X"C8",X"3A",X"18",X"98",X"A7",X"20",X"44",X"21",X"18",X"9C",X"11", + X"09",X"9C",X"3A",X"10",X"9C",X"96",X"30",X"02",X"ED",X"44",X"FE",X"08",X"D0",X"47",X"EB",X"3A", + X"01",X"9C",X"96",X"30",X"02",X"ED",X"44",X"FE",X"08",X"D0",X"CD",X"34",X"34",X"CD",X"D5",X"33", + X"3E",X"40",X"32",X"18",X"98",X"3A",X"2F",X"99",X"A7",X"28",X"04",X"3E",X"34",X"18",X"02",X"3E", + X"37",X"32",X"08",X"9C",X"21",X"00",X"05",X"22",X"15",X"99",X"22",X"1A",X"99",X"C3",X"FE",X"30", + X"3D",X"32",X"18",X"98",X"C0",X"AF",X"32",X"18",X"9C",X"C9",X"3A",X"02",X"99",X"A7",X"C0",X"2F", + X"32",X"02",X"99",X"D9",X"21",X"00",X"99",X"34",X"CD",X"06",X"19",X"CD",X"F7",X"33",X"D9",X"C9", + X"3A",X"04",X"99",X"A7",X"C8",X"3A",X"02",X"98",X"E6",X"1F",X"C0",X"CD",X"A5",X"2F",X"E6",X"07", + X"FE",X"03",X"D0",X"3E",X"FF",X"32",X"70",X"98",X"C9",X"3A",X"04",X"99",X"A7",X"C8",X"3A",X"62", + X"98",X"21",X"60",X"98",X"86",X"77",X"D0",X"21",X"8A",X"9A",X"11",X"8B",X"9A",X"01",X"0B",X"00", + X"ED",X"B8",X"21",X"15",X"9B",X"11",X"17",X"9B",X"01",X"16",X"00",X"ED",X"B8",X"2A",X"00",X"9B", + X"11",X"E0",X"FF",X"19",X"22",X"00",X"9B",X"C9",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"40",X"80",X"80",X"40",X"FF",X"C0",X"FF",X"80",X"00",X"FF",X"80",X"FF",X"FF",X"40",X"FF",X"00", + X"40",X"FF",X"C0",X"FF",X"40",X"80",X"80",X"40",X"FF",X"C0",X"FF",X"80",X"00",X"FF",X"80",X"FF", + X"FF",X"40",X"FF",X"00",X"40",X"FF",X"C0",X"FF",X"40",X"80",X"80",X"40",X"FF",X"C0",X"FF",X"80", + X"00",X"FF",X"80",X"FF",X"FF",X"40",X"FF",X"00",X"40",X"FF",X"C0",X"FF",X"DD",X"21",X"74",X"98", + X"DD",X"7E",X"00",X"A7",X"C4",X"4E",X"3F",X"DD",X"23",X"DD",X"7E",X"00",X"A7",X"C8",X"FD",X"21", + X"86",X"98",X"06",X"06",X"FD",X"7E",X"F0",X"A7",X"28",X"2A",X"FD",X"7E",X"00",X"DD",X"96",X"10", + X"30",X"02",X"ED",X"44",X"FE",X"04",X"30",X"1C",X"FD",X"7E",X"10",X"DD",X"96",X"20",X"30",X"02", + X"ED",X"44",X"FE",X"04",X"30",X"0E",X"AF",X"DD",X"77",X"00",X"DD",X"77",X"10",X"FD",X"77",X"F0", + X"FD",X"77",X"00",X"C9",X"FD",X"23",X"10",X"CC",X"C9",X"3A",X"05",X"99",X"A7",X"C8",X"3A",X"65", + X"98",X"21",X"63",X"98",X"86",X"77",X"D0",X"21",X"AA",X"9A",X"11",X"AB",X"9A",X"01",X"0B",X"00", + X"ED",X"B8",X"21",X"55",X"9B",X"11",X"57",X"9B",X"01",X"16",X"00",X"ED",X"B8",X"2A",X"40",X"9B", + X"11",X"20",X"00",X"19",X"22",X"40",X"9B",X"C9",X"3A",X"03",X"99",X"A7",X"28",X"2A",X"FE",X"08", + X"D0",X"21",X"A4",X"8B",X"11",X"E0",X"FF",X"47",X"4F",X"36",X"96",X"19",X"10",X"FB",X"21",X"44", + X"8B",X"36",X"A4",X"21",X"A4",X"83",X"47",X"36",X"38",X"19",X"10",X"FB",X"3E",X"07",X"91",X"D8", + X"C8",X"47",X"36",X"20",X"19",X"10",X"FB",X"C9",X"21",X"A4",X"83",X"11",X"E0",X"FF",X"06",X"08", + X"36",X"20",X"19",X"10",X"FB",X"C9",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_snd_rom.vhd b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_snd_rom.vhd new file mode 100644 index 00000000..daa71a58 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_snd_rom.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity jng_snd_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of jng_snd_rom is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"21",X"00",X"20",X"06",X"00",X"C3",X"B2",X"01",X"32",X"00",X"50",X"3A",X"00",X"40",X"C9",X"FF", + X"32",X"00",X"70",X"3A",X"00",X"60",X"C9",X"FF",X"78",X"CF",X"79",X"32",X"00",X"40",X"C9",X"FF", + X"78",X"D7",X"79",X"32",X"00",X"60",X"C9",X"FF",X"87",X"85",X"6F",X"7C",X"CE",X"00",X"67",X"7E", + X"23",X"66",X"6F",X"E9",X"FF",X"FF",X"FF",X"FF",X"D9",X"08",X"CD",X"40",X"00",X"08",X"D9",X"C9", + X"3E",X"0E",X"CF",X"B7",X"28",X"09",X"F2",X"79",X"00",X"CB",X"BF",X"CD",X"6C",X"00",X"C9",X"21", + X"00",X"20",X"06",X"0C",X"AF",X"77",X"23",X"10",X"FC",X"C9",X"21",X"00",X"20",X"06",X"06",X"0E", + X"07",X"BE",X"28",X"05",X"23",X"23",X"10",X"F9",X"41",X"79",X"90",X"C9",X"CD",X"5A",X"00",X"C8", + X"AF",X"77",X"23",X"77",X"C9",X"13",X"23",X"22",X"28",X"32",X"1A",X"20",X"CD",X"5A",X"00",X"28", + X"04",X"23",X"36",X"00",X"C9",X"3A",X"1A",X"20",X"21",X"75",X"00",X"06",X"02",X"BE",X"28",X"19", + X"23",X"10",X"FA",X"06",X"02",X"BE",X"28",X"21",X"23",X"10",X"FA",X"AF",X"CD",X"5A",X"00",X"28", + X"3A",X"3A",X"1A",X"20",X"77",X"23",X"36",X"00",X"C9",X"AF",X"CD",X"5A",X"00",X"28",X"05",X"FE", + X"04",X"FA",X"C9",X"00",X"CD",X"37",X"01",X"18",X"58",X"AF",X"CD",X"5A",X"00",X"28",X"05",X"FE", + X"04",X"F2",X"C9",X"00",X"CD",X"62",X"01",X"18",X"40",X"21",X"1A",X"20",X"46",X"0E",X"00",X"21", + X"00",X"20",X"3D",X"87",X"5F",X"51",X"19",X"70",X"23",X"71",X"C9",X"CD",X"37",X"01",X"CD",X"62", + X"01",X"B7",X"28",X"2D",X"3A",X"17",X"20",X"B7",X"28",X"1F",X"3A",X"18",X"20",X"21",X"06",X"20", + X"CD",X"26",X"01",X"CD",X"2E",X"01",X"57",X"3A",X"17",X"20",X"21",X"00",X"20",X"CD",X"26",X"01", + X"CD",X"2E",X"01",X"BA",X"F2",X"09",X"01",X"18",X"08",X"3A",X"18",X"20",X"21",X"06",X"20",X"18", + X"06",X"3A",X"17",X"20",X"21",X"00",X"20",X"B7",X"C8",X"3D",X"87",X"4F",X"06",X"00",X"09",X"3A", + X"1A",X"20",X"77",X"23",X"70",X"C9",X"3D",X"87",X"4F",X"06",X"00",X"09",X"7E",X"C9",X"21",X"87", + X"07",X"06",X"00",X"4F",X"09",X"7E",X"C9",X"3A",X"00",X"20",X"CD",X"2E",X"01",X"32",X"12",X"20", + X"3A",X"02",X"20",X"CD",X"2E",X"01",X"32",X"13",X"20",X"3A",X"04",X"20",X"CD",X"2E",X"01",X"32", + X"14",X"20",X"3A",X"1A",X"20",X"CD",X"2E",X"01",X"32",X"15",X"20",X"CD",X"8D",X"01",X"32",X"17", + X"20",X"C9",X"3A",X"06",X"20",X"CD",X"2E",X"01",X"32",X"12",X"20",X"3A",X"08",X"20",X"CD",X"2E", + X"01",X"32",X"13",X"20",X"3A",X"0A",X"20",X"CD",X"2E",X"01",X"32",X"14",X"20",X"3A",X"1A",X"20", + X"CD",X"2E",X"01",X"32",X"15",X"20",X"CD",X"8D",X"01",X"32",X"18",X"20",X"C9",X"21",X"12",X"20", + X"3A",X"15",X"20",X"06",X"03",X"4F",X"7E",X"B9",X"F2",X"9C",X"01",X"4F",X"23",X"10",X"F7",X"79", + X"06",X"03",X"0E",X"01",X"21",X"12",X"20",X"BE",X"28",X"06",X"0C",X"23",X"10",X"F9",X"0E",X"00", + X"79",X"C9",X"70",X"23",X"7C",X"FE",X"24",X"20",X"F9",X"F9",X"ED",X"56",X"21",X"00",X"30",X"22", + X"0C",X"20",X"77",X"01",X"3F",X"07",X"DF",X"E7",X"32",X"0E",X"20",X"32",X"0F",X"20",X"CD",X"C8", + X"02",X"CD",X"CC",X"02",X"CD",X"D0",X"02",X"CD",X"D6",X"02",X"CD",X"DA",X"02",X"CD",X"DE",X"02", + X"FB",X"3E",X"0F",X"CF",X"E6",X"80",X"20",X"F9",X"3E",X"0F",X"CF",X"E6",X"80",X"28",X"F9",X"F3", + X"3E",X"01",X"32",X"10",X"20",X"3A",X"01",X"20",X"B7",X"3A",X"00",X"20",X"CA",X"04",X"02",X"CD", + X"AC",X"02",X"18",X"03",X"CD",X"92",X"02",X"FB",X"00",X"00",X"F3",X"3E",X"02",X"32",X"10",X"20", + X"3A",X"03",X"20",X"B7",X"3A",X"02",X"20",X"CA",X"1F",X"02",X"CD",X"AC",X"02",X"18",X"03",X"CD", + X"92",X"02",X"FB",X"00",X"00",X"F3",X"3E",X"03",X"32",X"10",X"20",X"3A",X"05",X"20",X"B7",X"3A", + X"04",X"20",X"CA",X"3A",X"02",X"CD",X"AC",X"02",X"18",X"03",X"CD",X"92",X"02",X"FB",X"00",X"00", + X"F3",X"3E",X"04",X"32",X"10",X"20",X"3A",X"07",X"20",X"B7",X"3A",X"06",X"20",X"CA",X"55",X"02", + X"CD",X"AC",X"02",X"18",X"03",X"CD",X"92",X"02",X"FB",X"00",X"00",X"F3",X"3E",X"05",X"32",X"10", + X"20",X"3A",X"09",X"20",X"B7",X"3A",X"08",X"20",X"CA",X"70",X"02",X"CD",X"AC",X"02",X"18",X"03", + X"CD",X"92",X"02",X"FB",X"00",X"00",X"F3",X"3E",X"06",X"32",X"10",X"20",X"3A",X"0B",X"20",X"B7", + X"3A",X"0A",X"20",X"CA",X"8C",X"02",X"CD",X"AC",X"02",X"C3",X"E0",X"01",X"CD",X"92",X"02",X"C3", + X"E0",X"01",X"21",X"A1",X"07",X"EF",X"B7",X"20",X"1B",X"E5",X"21",X"01",X"20",X"3A",X"10",X"20", + X"3D",X"87",X"D5",X"5F",X"16",X"00",X"19",X"D1",X"36",X"01",X"E1",X"C9",X"B7",X"C8",X"21",X"D5", + X"07",X"EF",X"B7",X"C8",X"57",X"21",X"00",X"20",X"3A",X"10",X"20",X"3D",X"4F",X"06",X"00",X"09", + X"09",X"15",X"28",X"01",X"70",X"23",X"70",X"C9",X"06",X"08",X"18",X"06",X"06",X"09",X"18",X"02", + X"06",X"0A",X"0E",X"00",X"DF",X"C9",X"06",X"08",X"18",X"06",X"06",X"09",X"18",X"02",X"06",X"0A", + X"0E",X"00",X"E7",X"C9",X"3A",X"10",X"20",X"3D",X"21",X"ED",X"02",X"EF",X"C9",X"F9",X"02",X"02", + X"03",X"0B",X"03",X"14",X"03",X"1D",X"03",X"26",X"03",X"CD",X"C8",X"02",X"0E",X"09",X"CD",X"2F", + X"03",X"C9",X"CD",X"CC",X"02",X"0E",X"12",X"CD",X"2F",X"03",X"C9",X"CD",X"D0",X"02",X"0E",X"24", + X"CD",X"2F",X"03",X"C9",X"CD",X"D6",X"02",X"0E",X"09",X"CD",X"3B",X"03",X"C9",X"CD",X"DA",X"02", + X"0E",X"12",X"CD",X"3B",X"03",X"C9",X"CD",X"DE",X"02",X"0E",X"24",X"CD",X"3B",X"03",X"C9",X"3A", + X"0E",X"20",X"B1",X"32",X"0E",X"20",X"06",X"07",X"4F",X"DF",X"C9",X"3A",X"0F",X"20",X"B1",X"32", + X"0F",X"20",X"06",X"07",X"4F",X"E7",X"C9",X"06",X"06",X"3A",X"10",X"20",X"FE",X"04",X"FA",X"53", + X"03",X"E7",X"C9",X"DF",X"C9",X"06",X"06",X"3A",X"10",X"20",X"FE",X"04",X"FA",X"63",X"03",X"78", + X"D7",X"4F",X"C9",X"78",X"CF",X"4F",X"C9",X"3A",X"0E",X"20",X"A0",X"B1",X"32",X"0E",X"20",X"4F", + X"06",X"07",X"DF",X"C9",X"3A",X"0F",X"20",X"A0",X"B1",X"32",X"0F",X"20",X"4F",X"06",X"07",X"E7", + X"C9",X"3A",X"10",X"20",X"3D",X"21",X"8A",X"03",X"EF",X"C9",X"96",X"03",X"9D",X"03",X"A4",X"03", + X"AB",X"03",X"B2",X"03",X"B9",X"03",X"01",X"08",X"FE",X"CD",X"67",X"03",X"C9",X"01",X"10",X"FD", + X"CD",X"67",X"03",X"C9",X"01",X"20",X"FB",X"CD",X"67",X"03",X"C9",X"01",X"08",X"FE",X"CD",X"74", + X"03",X"C9",X"01",X"10",X"FD",X"CD",X"74",X"03",X"C9",X"01",X"20",X"FB",X"CD",X"74",X"03",X"C9", + X"3A",X"10",X"20",X"3D",X"21",X"C9",X"03",X"EF",X"C9",X"D5",X"03",X"DC",X"03",X"E3",X"03",X"EA", + X"03",X"F1",X"03",X"F8",X"03",X"01",X"01",X"F7",X"CD",X"67",X"03",X"C9",X"01",X"02",X"EF",X"CD", + X"67",X"03",X"C9",X"01",X"04",X"DF",X"CD",X"67",X"03",X"C9",X"01",X"01",X"F7",X"CD",X"74",X"03", + X"C9",X"01",X"02",X"EF",X"CD",X"74",X"03",X"C9",X"01",X"04",X"DF",X"CD",X"74",X"03",X"C9",X"3A", + X"10",X"20",X"3D",X"21",X"08",X"04",X"EF",X"C9",X"14",X"04",X"1B",X"04",X"22",X"04",X"29",X"04", + X"30",X"04",X"37",X"04",X"01",X"00",X"F6",X"CD",X"67",X"03",X"C9",X"01",X"00",X"ED",X"CD",X"67", + X"03",X"C9",X"01",X"00",X"DB",X"CD",X"67",X"03",X"C9",X"01",X"00",X"F6",X"CD",X"74",X"03",X"C9", + X"01",X"00",X"ED",X"CD",X"74",X"03",X"C9",X"01",X"00",X"DB",X"CD",X"74",X"03",X"C9",X"3A",X"10", + X"20",X"FE",X"04",X"30",X"05",X"C6",X"07",X"47",X"DF",X"C9",X"C6",X"04",X"47",X"E7",X"C9",X"3A", + X"10",X"20",X"FE",X"04",X"30",X"04",X"C6",X"07",X"CF",X"C9",X"C6",X"04",X"D7",X"C9",X"3A",X"10", + X"20",X"FE",X"04",X"30",X"09",X"3D",X"87",X"47",X"4D",X"DF",X"4C",X"04",X"DF",X"C9",X"D6",X"04", + X"87",X"47",X"4D",X"E7",X"4C",X"04",X"E7",X"C9",X"3A",X"10",X"20",X"FE",X"04",X"30",X"0A",X"3D", + X"87",X"67",X"24",X"CF",X"6F",X"7C",X"CF",X"67",X"C9",X"D6",X"04",X"87",X"67",X"24",X"D7",X"6F", + X"7C",X"D7",X"67",X"C9",X"FE",X"04",X"D0",X"F5",X"CD",X"E4",X"04",X"F1",X"B7",X"20",X"02",X"77", + X"C9",X"21",X"B4",X"04",X"87",X"87",X"4F",X"87",X"81",X"4F",X"06",X"00",X"09",X"3A",X"10",X"20", + X"3D",X"EF",X"77",X"C9",X"07",X"05",X"0C",X"05",X"11",X"05",X"16",X"05",X"1B",X"05",X"20",X"05", + X"25",X"05",X"2A",X"05",X"2F",X"05",X"34",X"05",X"39",X"05",X"3E",X"05",X"43",X"05",X"48",X"05", + X"4D",X"05",X"52",X"05",X"57",X"05",X"5C",X"05",X"61",X"05",X"66",X"05",X"6B",X"05",X"70",X"05", + X"75",X"05",X"7A",X"05",X"21",X"B4",X"04",X"3A",X"10",X"20",X"3D",X"EF",X"C9",X"2A",X"0C",X"20", + X"7B",X"A5",X"6F",X"7A",X"A4",X"67",X"22",X"0C",X"20",X"C9",X"2A",X"0C",X"20",X"7B",X"B5",X"6F", + X"7A",X"B4",X"67",X"22",X"0C",X"20",X"C9",X"11",X"3F",X"FF",X"18",X"E1",X"11",X"FF",X"FC",X"18", + X"DC",X"11",X"FF",X"F3",X"18",X"D7",X"11",X"FC",X"FF",X"18",X"D2",X"11",X"F3",X"FF",X"18",X"CD", + X"11",X"CF",X"FF",X"18",X"C8",X"11",X"80",X"00",X"18",X"D0",X"11",X"00",X"02",X"18",X"CB",X"11", + X"00",X"08",X"18",X"C6",X"11",X"02",X"00",X"18",X"C1",X"11",X"08",X"00",X"18",X"BC",X"11",X"20", + X"00",X"18",X"B7",X"11",X"40",X"00",X"18",X"B2",X"11",X"00",X"01",X"18",X"AD",X"11",X"00",X"04", + X"18",X"A8",X"11",X"01",X"00",X"18",X"A3",X"11",X"04",X"00",X"18",X"9E",X"11",X"10",X"00",X"18", + X"99",X"11",X"C0",X"00",X"18",X"94",X"11",X"00",X"03",X"18",X"8F",X"11",X"00",X"0C",X"18",X"8A", + X"11",X"03",X"00",X"18",X"85",X"11",X"0C",X"00",X"18",X"80",X"11",X"30",X"00",X"C3",X"FA",X"04", + X"DD",X"7E",X"00",X"FE",X"FF",X"C8",X"CD",X"8B",X"05",X"AF",X"C9",X"DD",X"35",X"01",X"C0",X"3A", + X"42",X"20",X"DD",X"77",X"01",X"DD",X"CB",X"00",X"46",X"C2",X"AB",X"05",X"DD",X"7E",X"07",X"D6", + X"01",X"FA",X"AB",X"05",X"DD",X"77",X"07",X"4F",X"CD",X"3E",X"04",X"DD",X"35",X"00",X"C0",X"DD", + X"6E",X"02",X"DD",X"66",X"03",X"7E",X"47",X"E6",X"1F",X"CA",X"46",X"06",X"FE",X"1F",X"C2",X"62", + X"06",X"23",X"DD",X"75",X"02",X"DD",X"74",X"03",X"78",X"E6",X"E0",X"0F",X"0F",X"0F",X"0F",X"4F", + X"06",X"00",X"21",X"DB",X"05",X"09",X"5E",X"23",X"56",X"EB",X"E9",X"EB",X"05",X"09",X"06",X"1F", + X"06",X"3C",X"06",X"3C",X"06",X"3C",X"06",X"3C",X"06",X"3C",X"06",X"DD",X"6E",X"02",X"DD",X"66", + X"03",X"4E",X"CB",X"21",X"06",X"00",X"21",X"95",X"06",X"09",X"5E",X"23",X"56",X"ED",X"53",X"40", + X"20",X"DD",X"73",X"04",X"DD",X"72",X"05",X"18",X"23",X"DD",X"6E",X"02",X"DD",X"66",X"03",X"4E", + X"06",X"00",X"21",X"2D",X"07",X"09",X"7E",X"32",X"42",X"20",X"DD",X"77",X"01",X"18",X"0D",X"DD", + X"6E",X"02",X"DD",X"66",X"03",X"7E",X"DD",X"77",X"06",X"DD",X"77",X"07",X"DD",X"6E",X"02",X"DD", + X"66",X"03",X"23",X"DD",X"75",X"02",X"DD",X"74",X"03",X"C3",X"AF",X"05",X"0E",X"00",X"CD",X"3E", + X"04",X"DD",X"36",X"00",X"FF",X"C9",X"CD",X"50",X"06",X"0E",X"00",X"CD",X"3E",X"04",X"18",X"37", + X"78",X"E6",X"E0",X"07",X"07",X"07",X"47",X"3E",X"01",X"18",X"01",X"07",X"10",X"FD",X"DD",X"77", + X"00",X"C9",X"C5",X"CD",X"50",X"06",X"C1",X"78",X"E6",X"1F",X"3D",X"07",X"4F",X"06",X"00",X"DD", + X"6E",X"04",X"DD",X"66",X"05",X"09",X"5E",X"23",X"56",X"EB",X"CD",X"5E",X"04",X"DD",X"4E",X"06", + X"79",X"DD",X"77",X"07",X"CD",X"3E",X"04",X"DD",X"6E",X"02",X"DD",X"66",X"03",X"23",X"DD",X"75", + X"02",X"DD",X"74",X"03",X"C9",X"B5",X"06",X"B9",X"06",X"BD",X"06",X"C1",X"06",X"C5",X"06",X"C9", + X"06",X"CD",X"06",X"D1",X"06",X"D5",X"06",X"D9",X"06",X"DD",X"06",X"E1",X"06",X"E5",X"06",X"E9", + X"06",X"ED",X"06",X"F1",X"06",X"6B",X"08",X"F2",X"07",X"80",X"07",X"14",X"07",X"AE",X"06",X"4E", + X"06",X"F3",X"05",X"9E",X"05",X"4E",X"05",X"01",X"05",X"B9",X"04",X"76",X"04",X"36",X"04",X"F9", + X"03",X"C0",X"03",X"8A",X"03",X"57",X"03",X"27",X"03",X"FA",X"02",X"CF",X"02",X"A7",X"02",X"81", + X"02",X"5D",X"02",X"3B",X"02",X"1B",X"02",X"FD",X"01",X"E0",X"01",X"C5",X"01",X"AC",X"01",X"94", + X"01",X"7D",X"01",X"68",X"01",X"53",X"01",X"40",X"01",X"2E",X"01",X"1D",X"01",X"0D",X"01",X"FE", + X"00",X"F0",X"00",X"E3",X"00",X"D6",X"00",X"CA",X"00",X"BE",X"00",X"B4",X"00",X"AA",X"00",X"A0", + X"00",X"97",X"00",X"8F",X"00",X"87",X"00",X"7F",X"00",X"78",X"00",X"71",X"00",X"6B",X"00",X"65", + X"00",X"5F",X"00",X"5A",X"00",X"55",X"00",X"50",X"00",X"4C",X"00",X"47",X"00",X"57",X"42",X"34", + X"2C",X"25",X"21",X"1D",X"1A",X"0C",X"0B",X"0A",X"09",X"08",X"07",X"06",X"05",X"21",X"6F",X"07", + X"11",X"20",X"20",X"01",X"18",X"00",X"ED",X"B0",X"3A",X"43",X"20",X"07",X"4F",X"07",X"81",X"4F", + X"06",X"00",X"21",X"01",X"0D",X"09",X"11",X"22",X"20",X"CD",X"65",X"07",X"11",X"2A",X"20",X"CD", + X"65",X"07",X"11",X"32",X"20",X"7E",X"12",X"CD",X"6C",X"07",X"7E",X"12",X"23",X"13",X"C9",X"01", + X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"01", + X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"0E",X"07",X"06",X"01",X"04",X"03",X"05", + X"0C",X"02",X"0A",X"09",X"08",X"0D",X"0F",X"11",X"12",X"13",X"14",X"15",X"16",X"17",X"18",X"19", + X"0B",X"E4",X"02",X"09",X"08",X"43",X"08",X"71",X"08",X"D3",X"08",X"1A",X"09",X"AB",X"09",X"F5", + X"09",X"57",X"0A",X"BC",X"0A",X"FD",X"0A",X"60",X"0B",X"B0",X"0B",X"F7",X"0B",X"2E",X"0C",X"74", + X"0C",X"13",X"0D",X"17",X"0D",X"19",X"0D",X"21",X"0D",X"25",X"0D",X"27",X"0D",X"2F",X"0D",X"33", + X"0D",X"35",X"0D",X"C5",X"0C",X"00",X"00",X"24",X"08",X"64",X"08",X"92",X"08",X"EB",X"08",X"40", + X"09",X"C3",X"09",X"12",X"0A",X"77",X"0A",X"D5",X"0A",X"1F",X"0B",X"7A",X"0B",X"CA",X"0B",X"11", + X"0C",X"4B",X"0C",X"8F",X"0C",X"1B",X"0D",X"1D",X"0D",X"1F",X"0D",X"29",X"0D",X"2B",X"0D",X"2D", + X"0D",X"37",X"0D",X"39",X"0D",X"3B",X"0D",X"E2",X"0C",X"3E",X"03",X"CD",X"94",X"04",X"CD",X"81", + X"03",X"21",X"00",X"01",X"CD",X"5E",X"04",X"0E",X"0C",X"CD",X"3E",X"04",X"AF",X"32",X"51",X"20", + X"32",X"50",X"20",X"C9",X"3A",X"50",X"20",X"3D",X"32",X"50",X"20",X"E6",X"03",X"20",X"12",X"CD", + X"78",X"04",X"3A",X"51",X"20",X"C6",X"DB",X"32",X"51",X"20",X"AD",X"E6",X"7F",X"6F",X"CD",X"5E", + X"04",X"AF",X"C9",X"3E",X"01",X"CD",X"94",X"04",X"CD",X"81",X"03",X"0E",X"10",X"CD",X"3E",X"04", + X"21",X"40",X"0D",X"CD",X"5E",X"04",X"CD",X"4F",X"04",X"3D",X"FE",X"04",X"28",X"11",X"4F",X"CD", + X"3E",X"04",X"AF",X"C9",X"CD",X"78",X"04",X"2D",X"28",X"E6",X"CD",X"5E",X"04",X"AF",X"C9",X"3D", + X"C9",X"3E",X"01",X"CD",X"94",X"04",X"CD",X"FF",X"03",X"01",X"1F",X"06",X"CD",X"49",X"03",X"21", + X"00",X"04",X"CD",X"5E",X"04",X"0E",X"0F",X"CD",X"3E",X"04",X"AF",X"32",X"53",X"20",X"32",X"52", + X"20",X"C9",X"21",X"52",X"20",X"35",X"56",X"CD",X"78",X"04",X"3A",X"53",X"20",X"C6",X"B5",X"32", + X"53",X"20",X"AD",X"6F",X"7A",X"E6",X"0F",X"20",X"05",X"25",X"20",X"02",X"26",X"01",X"CD",X"5E", + X"04",X"7A",X"E6",X"3F",X"20",X"19",X"7C",X"FE",X"01",X"20",X"14",X"06",X"06",X"CD",X"57",X"03", + X"0D",X"0D",X"CD",X"49",X"03",X"CD",X"4F",X"04",X"3D",X"28",X"06",X"4F",X"CD",X"3E",X"04",X"AF", + X"C9",X"3D",X"C9",X"3E",X"00",X"CD",X"94",X"04",X"CD",X"81",X"03",X"21",X"40",X"00",X"CD",X"5E", + X"04",X"3E",X"20",X"32",X"55",X"20",X"AF",X"32",X"54",X"20",X"C9",X"3A",X"55",X"20",X"3D",X"32", + X"55",X"20",X"20",X"02",X"3D",X"C9",X"CB",X"47",X"28",X"07",X"0E",X"0C",X"CD",X"3E",X"04",X"AF", + X"C9",X"CD",X"78",X"04",X"3A",X"54",X"20",X"3C",X"32",X"54",X"20",X"85",X"6F",X"30",X"01",X"24", + X"CD",X"5E",X"04",X"0E",X"00",X"CD",X"3E",X"04",X"AF",X"C9",X"AF",X"CD",X"94",X"04",X"CD",X"81", + X"03",X"21",X"40",X"00",X"CD",X"5E",X"04",X"0E",X"00",X"CD",X"3E",X"04",X"3E",X"08",X"32",X"59", + X"20",X"32",X"58",X"20",X"3E",X"DB",X"32",X"56",X"20",X"3E",X"AA",X"32",X"57",X"20",X"AF",X"C9", + X"3A",X"56",X"20",X"3D",X"32",X"56",X"20",X"20",X"02",X"3D",X"C9",X"FE",X"C3",X"38",X"24",X"28", + X"15",X"FE",X"CF",X"38",X"0A",X"CD",X"4F",X"04",X"3C",X"4F",X"CD",X"3E",X"04",X"AF",X"C9",X"0E", + X"00",X"CD",X"3E",X"04",X"AF",X"C9",X"0E",X"0C",X"CD",X"3E",X"04",X"21",X"1F",X"00",X"CD",X"5E", + X"04",X"AF",X"C9",X"3A",X"58",X"20",X"3D",X"32",X"58",X"20",X"28",X"02",X"AF",X"C9",X"3A",X"59", + X"20",X"32",X"58",X"20",X"21",X"57",X"20",X"CB",X"0E",X"38",X"0C",X"CD",X"78",X"04",X"3E",X"20", + X"85",X"6F",X"CD",X"5E",X"04",X"AF",X"C9",X"CD",X"78",X"04",X"3E",X"E0",X"85",X"6F",X"CD",X"5E", + X"04",X"CD",X"4F",X"04",X"3D",X"4F",X"CD",X"3E",X"04",X"AF",X"C9",X"3E",X"00",X"CD",X"94",X"04", + X"CD",X"81",X"03",X"21",X"30",X"00",X"CD",X"5E",X"04",X"0E",X"08",X"CD",X"3E",X"04",X"AF",X"32", + X"5A",X"20",X"C9",X"21",X"5A",X"20",X"35",X"7E",X"28",X"29",X"57",X"FE",X"E8",X"28",X"0C",X"38", + X"11",X"CD",X"4F",X"04",X"3D",X"4F",X"CD",X"3E",X"04",X"AF",X"C9",X"0E",X"0F",X"CD",X"3E",X"04", + X"AF",X"C9",X"CD",X"78",X"04",X"01",X"02",X"00",X"09",X"CD",X"5E",X"04",X"7A",X"E6",X"0F",X"28", + X"E0",X"AF",X"C9",X"3D",X"C9",X"AF",X"CD",X"94",X"04",X"CD",X"81",X"03",X"0E",X"0C",X"CD",X"3E", + X"04",X"21",X"90",X"00",X"CD",X"5E",X"04",X"AF",X"32",X"5B",X"20",X"3E",X"AA",X"32",X"5C",X"20", + X"AF",X"C9",X"21",X"5C",X"20",X"CB",X"0E",X"30",X"02",X"AF",X"C9",X"3A",X"5B",X"20",X"3D",X"32", + X"5B",X"20",X"FE",X"EC",X"38",X"18",X"FE",X"F6",X"28",X"0C",X"CD",X"78",X"04",X"3E",X"F0",X"85", + X"6F",X"CD",X"5E",X"04",X"AF",X"C9",X"21",X"90",X"00",X"CD",X"5E",X"04",X"AF",X"C9",X"CD",X"78", + X"04",X"3E",X"10",X"85",X"6F",X"CD",X"5E",X"04",X"CD",X"4F",X"04",X"D6",X"02",X"20",X"02",X"3D", + X"C9",X"4F",X"CD",X"3E",X"04",X"AF",X"C9",X"3E",X"01",X"CD",X"94",X"04",X"CD",X"81",X"03",X"21", + X"00",X"05",X"CD",X"5E",X"04",X"0E",X"0E",X"CD",X"3E",X"04",X"3E",X"02",X"32",X"5E",X"20",X"AF", + X"32",X"5F",X"20",X"32",X"5D",X"20",X"C9",X"3A",X"5E",X"20",X"3D",X"32",X"5E",X"20",X"20",X"28", + X"3E",X"02",X"32",X"5E",X"20",X"21",X"5D",X"20",X"35",X"28",X"1F",X"7E",X"57",X"CD",X"78",X"04", + X"7A",X"FE",X"E0",X"38",X"18",X"E6",X"07",X"20",X"01",X"25",X"3A",X"5F",X"20",X"C6",X"C3",X"32", + X"5F",X"20",X"AA",X"AD",X"6F",X"CD",X"5E",X"04",X"AF",X"C9",X"3E",X"FF",X"C9",X"E6",X"0F",X"20", + X"E9",X"CD",X"4F",X"04",X"3D",X"4F",X"CD",X"3E",X"04",X"C3",X"9A",X"0A",X"AF",X"CD",X"94",X"04", + X"CD",X"81",X"03",X"21",X"C0",X"01",X"CD",X"5E",X"04",X"0E",X"0F",X"CD",X"3E",X"04",X"3E",X"48", + X"32",X"60",X"20",X"AF",X"C9",X"3A",X"60",X"20",X"3D",X"32",X"60",X"20",X"20",X"02",X"3D",X"C9", + X"FE",X"02",X"38",X"12",X"E6",X"07",X"28",X"02",X"AF",X"C9",X"CD",X"78",X"04",X"01",X"D4",X"FF", + X"09",X"CD",X"5E",X"04",X"AF",X"C9",X"0E",X"0F",X"CD",X"3E",X"04",X"AF",X"C9",X"3E",X"01",X"CD", + X"94",X"04",X"CD",X"81",X"03",X"21",X"40",X"00",X"CD",X"5E",X"04",X"0E",X"03",X"CD",X"3E",X"04", + X"3E",X"20",X"32",X"61",X"20",X"32",X"62",X"20",X"3E",X"08",X"32",X"63",X"20",X"AF",X"C9",X"3A", + X"62",X"20",X"3D",X"32",X"62",X"20",X"28",X"25",X"FE",X"1A",X"28",X"0C",X"38",X"11",X"CD",X"4F", + X"04",X"C6",X"02",X"CD",X"3E",X"04",X"AF",X"C9",X"0E",X"0F",X"CD",X"3E",X"04",X"AF",X"C9",X"E6", + X"01",X"28",X"08",X"CD",X"4F",X"04",X"3D",X"4F",X"CD",X"3E",X"04",X"AF",X"C9",X"3A",X"63",X"20", + X"3D",X"32",X"63",X"20",X"20",X"02",X"3D",X"C9",X"3A",X"61",X"20",X"32",X"62",X"20",X"AF",X"C9", + X"3E",X"01",X"CD",X"94",X"04",X"CD",X"81",X"03",X"0E",X"0E",X"CD",X"3E",X"04",X"21",X"FF",X"00", + X"CD",X"5E",X"04",X"3E",X"40",X"32",X"64",X"20",X"AF",X"C9",X"3A",X"64",X"20",X"3D",X"32",X"64", + X"20",X"20",X"02",X"3D",X"C9",X"E6",X"07",X"20",X"08",X"CD",X"4F",X"04",X"3D",X"4F",X"CD",X"3E", + X"04",X"3A",X"64",X"20",X"E6",X"08",X"28",X"0C",X"CD",X"78",X"04",X"3E",X"F0",X"85",X"6F",X"CD", + X"5E",X"04",X"AF",X"C9",X"CD",X"78",X"04",X"3E",X"10",X"85",X"6F",X"CD",X"5E",X"04",X"AF",X"C9", + X"3E",X"00",X"CD",X"94",X"04",X"CD",X"81",X"03",X"21",X"7C",X"00",X"CD",X"5E",X"04",X"0E",X"0F", + X"CD",X"3E",X"04",X"3E",X"3F",X"32",X"65",X"20",X"AF",X"C9",X"21",X"65",X"20",X"35",X"7E",X"28", + X"24",X"FE",X"11",X"38",X"15",X"FE",X"30",X"38",X"08",X"CD",X"4F",X"04",X"3D",X"4F",X"CD",X"3E", + X"04",X"CD",X"78",X"04",X"2D",X"CD",X"5E",X"04",X"AF",X"C9",X"E6",X"02",X"0E",X"07",X"28",X"EE", + X"0E",X"0F",X"C3",X"DE",X"0B",X"3D",X"C9",X"3E",X"00",X"CD",X"94",X"04",X"CD",X"81",X"03",X"0E", + X"0D",X"CD",X"3E",X"04",X"21",X"FF",X"00",X"CD",X"5E",X"04",X"3E",X"0F",X"32",X"66",X"20",X"AF", + X"C9",X"3A",X"66",X"20",X"3D",X"32",X"66",X"20",X"28",X"02",X"AF",X"C9",X"3E",X"0F",X"32",X"66", + X"20",X"CD",X"78",X"04",X"3E",X"F0",X"85",X"D0",X"6F",X"CD",X"5E",X"04",X"AF",X"C9",X"3E",X"00", + X"CD",X"94",X"04",X"CD",X"81",X"03",X"21",X"90",X"00",X"CD",X"5E",X"04",X"0E",X"09",X"CD",X"3E", + X"04",X"3E",X"F4",X"32",X"68",X"20",X"AF",X"32",X"67",X"20",X"C9",X"21",X"67",X"20",X"35",X"7E", + X"E6",X"07",X"20",X"11",X"CD",X"78",X"04",X"3A",X"68",X"20",X"3C",X"28",X"15",X"32",X"68",X"20", + X"85",X"6F",X"CD",X"5E",X"04",X"7E",X"E6",X"08",X"0E",X"09",X"20",X"01",X"4F",X"CD",X"3E",X"04", + X"AF",X"C9",X"3D",X"C9",X"3E",X"01",X"CD",X"94",X"04",X"CD",X"81",X"03",X"21",X"D0",X"00",X"CD", + X"5E",X"04",X"3E",X"08",X"32",X"69",X"20",X"32",X"6A",X"20",X"AF",X"32",X"6B",X"20",X"C9",X"3A", + X"6A",X"20",X"3D",X"57",X"32",X"6A",X"20",X"20",X"1E",X"3A",X"69",X"20",X"32",X"6A",X"20",X"CD", + X"78",X"04",X"3A",X"6B",X"20",X"3C",X"32",X"6B",X"20",X"FE",X"4E",X"20",X"03",X"3E",X"FF",X"C9", + X"4F",X"06",X"00",X"09",X"CD",X"5E",X"04",X"7A",X"E6",X"02",X"0E",X"03",X"28",X"02",X"0E",X"0C", + X"CD",X"3E",X"04",X"AF",X"C9",X"3E",X"01",X"CD",X"94",X"04",X"CD",X"81",X"03",X"0E",X"0E",X"CD", + X"3E",X"04",X"3E",X"05",X"32",X"6D",X"20",X"21",X"04",X"00",X"CD",X"5E",X"04",X"AF",X"32",X"6C", + X"20",X"C9",X"21",X"6C",X"20",X"35",X"7E",X"28",X"16",X"FE",X"DA",X"20",X"06",X"21",X"6D",X"20", + X"35",X"20",X"E4",X"CD",X"78",X"04",X"01",X"0C",X"00",X"09",X"CD",X"5E",X"04",X"AF",X"C9",X"3D", + X"C9",X"6A",X"0D",X"91",X"0D",X"B6",X"0D",X"D7",X"0D",X"17",X"0E",X"37",X"0E",X"49",X"0E",X"5E", + X"0E",X"71",X"0E",X"3E",X"00",X"18",X"26",X"18",X"33",X"18",X"31",X"18",X"38",X"18",X"3D",X"18", + X"42",X"3E",X"01",X"18",X"18",X"18",X"25",X"18",X"23",X"18",X"2A",X"18",X"2F",X"18",X"34",X"3E", + X"02",X"18",X"0A",X"18",X"17",X"18",X"15",X"18",X"1C",X"18",X"21",X"18",X"26",X"32",X"43",X"20", + X"CD",X"3D",X"07",X"AF",X"CD",X"94",X"04",X"CD",X"81",X"03",X"AF",X"C9",X"AF",X"CD",X"94",X"04", + X"CD",X"81",X"03",X"AF",X"C9",X"DD",X"21",X"20",X"20",X"C3",X"80",X"05",X"DD",X"21",X"28",X"20", + X"C3",X"80",X"05",X"DD",X"21",X"30",X"20",X"C3",X"80",X"05",X"1F",X"0E",X"3F",X"0B",X"5F",X"09", + X"6D",X"6F",X"72",X"6D",X"6F",X"72",X"6D",X"6F",X"6F",X"71",X"74",X"6F",X"71",X"74",X"6F",X"74", + X"72",X"72",X"72",X"74",X"74",X"74",X"36",X"36",X"36",X"36",X"36",X"36",X"36",X"36",X"B6",X"A0", + X"FF",X"1F",X"0E",X"5F",X"09",X"6A",X"6B",X"6F",X"6A",X"6B",X"6F",X"6A",X"6B",X"6C",X"6D",X"71", + X"6C",X"6D",X"71",X"6C",X"6D",X"6F",X"6F",X"6F",X"70",X"70",X"70",X"32",X"32",X"32",X"32",X"32", + X"32",X"32",X"32",X"B2",X"A0",X"FF",X"1F",X"05",X"5F",X"09",X"8C",X"60",X"8C",X"60",X"6C",X"6C", + X"8E",X"60",X"8E",X"60",X"6E",X"6E",X"69",X"69",X"69",X"6A",X"6A",X"6A",X"2C",X"2C",X"2C",X"2C", + X"2C",X"2C",X"2C",X"2C",X"AC",X"A0",X"FF",X"1F",X"0E",X"3F",X"0C",X"5F",X"09",X"70",X"70",X"60", + X"70",X"90",X"71",X"71",X"60",X"71",X"91",X"93",X"91",X"70",X"71",X"70",X"71",X"90",X"71",X"73", + X"71",X"73",X"91",X"93",X"91",X"2E",X"2F",X"30",X"31",X"2F",X"30",X"31",X"32",X"30",X"31",X"32", + X"33",X"31",X"32",X"33",X"34",X"32",X"33",X"34",X"35",X"33",X"34",X"35",X"36",X"34",X"35",X"36", + X"37",X"35",X"36",X"37",X"38",X"A0",X"FF",X"1F",X"0E",X"5F",X"09",X"6C",X"6C",X"60",X"6C",X"8C", + X"6E",X"6E",X"60",X"6E",X"8E",X"90",X"8E",X"6C",X"6E",X"6C",X"6E",X"8C",X"6E",X"70",X"6E",X"70", + X"8E",X"90",X"8E",X"A0",X"A0",X"A0",X"FF",X"1F",X"08",X"5F",X"09",X"AC",X"A0",X"A0",X"80",X"87", + X"AC",X"A0",X"A0",X"80",X"87",X"A0",X"A0",X"A0",X"FF",X"1F",X"0E",X"3F",X"0B",X"5F",X"09",X"69", + X"69",X"60",X"6C",X"60",X"69",X"60",X"67",X"89",X"8C",X"6E",X"70",X"73",X"B5",X"FF",X"1F",X"08", + X"5F",X"09",X"69",X"69",X"60",X"6C",X"60",X"69",X"60",X"67",X"89",X"8C",X"6E",X"70",X"73",X"B5", + X"FF",X"1F",X"02",X"5F",X"08",X"69",X"69",X"60",X"6C",X"60",X"69",X"60",X"67",X"89",X"8C",X"6E", + X"70",X"73",X"B5",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jungler.zip b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jungler.zip new file mode 100644 index 00000000..8cfd2780 Binary files /dev/null and b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jungler.zip differ diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/make_jungler_proms.bat b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/make_jungler_proms.bat new file mode 100644 index 00000000..b93d9228 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/make_jungler_proms.bat @@ -0,0 +1,15 @@ +copy /B jungr1 + jungr2 + jungr3 + jungr4 JUNGLER.ROM +make_vhdl_prom JUNGLER.ROM jng_prg_rom.vhd + +copy /B 5k + 5m gfx1.bin +make_vhdl_prom gfx1.bin jng_chr_rom.vhd + +make_vhdl_prom 82s129.10g jng_dot_rom.vhd + +make_vhdl_prom 1b jng_snd_rom.vhd + + + +make_vhdl_prom 18s030.8b jng_pal_rom.vhd +make_vhdl_prom tbp24s10.9d jng_col_rom.vhd + diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/make_vhdl_prom.exe b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/make_vhdl_prom.exe new file mode 100644 index 00000000..1e5618bf Binary files /dev/null and b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/make_vhdl_prom.exe differ diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/Locomotion.qpf b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/Locomotion.qpf new file mode 100644 index 00000000..10b38fc5 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/Locomotion.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition +# Date created = 04:04:47 October 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.0" +DATE = "04:04:47 October 16, 2017" + +# Revisions + +PROJECT_REVISION = "Locomotion" diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/Locomotion.qsf b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/Locomotion.qsf new file mode 100644 index 00000000..04174989 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/Locomotion.qsf @@ -0,0 +1,174 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2014 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition +# Date created = 16:08:40 October 03, 2019 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Locomotion_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name SYSTEMVERILOG_FILE rtl/Locomotion_mist.sv +set_global_assignment -name VERILOG_FILE rtl/loc_top.v +set_global_assignment -name VERILOG_FILE rtl/loc_video.v +set_global_assignment -name VERILOG_FILE rtl/loc_hvgen.v +set_global_assignment -name VERILOG_FILE rtl/loc_sprite.v +set_global_assignment -name VHDL_FILE rtl/loc_sound.vhd +set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd +set_global_assignment -name VERILOG_FILE rtl/rams.v +set_global_assignment -name VHDL_FILE rtl/dpram.vhd +set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd +set_global_assignment -name VHDL_FILE rtl/roms/loc_prg_rom.vhd +set_global_assignment -name VHDL_FILE rtl/roms/loc_dot_rom.vhd +set_global_assignment -name VHDL_FILE rtl/roms/loc_chr_rom.vhd +set_global_assignment -name VHDL_FILE rtl/roms/loc_pal_rom.vhd +set_global_assignment -name VHDL_FILE rtl/roms/loc_col_rom.vhd +set_global_assignment -name VHDL_FILE rtl/roms/loc_snd_rom.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80s.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd +set_global_assignment -name VHDL_FILE rtl/T65/T65_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/T65/T65_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/T65/T65_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/T65/T65.vhd +set_global_assignment -name VERILOG_FILE rtl/pll.v +set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP +set_global_assignment -name TOP_LEVEL_ENTITY Locomotion_mist + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# ----------------------------- +# start ENTITY(Locomotion_mist) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(Locomotion_mist) +# --------------------------- \ No newline at end of file diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/README.txt b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/README.txt new file mode 100644 index 00000000..412e9142 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/README.txt @@ -0,0 +1,18 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Locomotion port to MiST +-- xx xxxx 20xx +-- From: https://github.com/MrX-8B/MiSTer-Arcade-RallyX +-- + +Todo: Sound ,GFX and some Controls + +--------------------------------------------------------------------------------- +-- FPGA New Rally-X for Spartan-3 Starter Board +------------------------------------------------ +-- Copyright (c) 2005 MiSTer-X +--------------------------------------------------------------------------------- +-- T80/T80s - Version : 0242 +----------------------------- +-- Z80 compatible microprocessor core +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) \ No newline at end of file diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/Snapshot/Locomotion.rbf b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/Snapshot/Locomotion.rbf new file mode 100644 index 00000000..3450dddf Binary files /dev/null and b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/Snapshot/Locomotion.rbf differ diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/clean.bat b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/Locomotion_mist.sv b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/Locomotion_mist.sv new file mode 100644 index 00000000..80d05b57 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/Locomotion_mist.sv @@ -0,0 +1,176 @@ +module Locomotion_mist ( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "Locomotion;;", + "O2,Rotate,Off,On;", + "O34,Scanlines,None,CRT 25%,CRT 50%,CRT 75%;", + "O5,Test,Off,On;", + "O6,Service,Off,On;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + +assign LED = 1; +assign AUDIO_R = AUDIO_L; + +wire clock_24, clock_12; +pll pll( + .inclk0(CLOCK_27), + .c0(clock_24)//24.576MHz + ); + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoublerD; +wire ypbpr; +wire [10:0] audio; +wire hs, vs; +wire hb, vb; +wire blankn = ~(hb | vb); +wire [2:0] r, g; +wire [1:0] b; +wire key_strobe; +wire key_pressed; +wire [7:0] key_code; + + +wire [7:0] iDSW2 = ~{ m_down1, 1'b0, "00", 1'b0, 1'b0, 1'b0};//Down1,Unused,Lives,Cabinet ,Intermissions,demo sound +wire [7:0] iDSW1 = ~{ "0000","0000"};//Coin A, No Coin B = coins produce sound, but no effect on coin counter + +wire [7:0] iCTR1 = ~{ btn_coin, 1'b0, m_right1, m_left1, m_fire1, status[6], 1'b0, m_up2}; +wire [7:0] iCTR2 = ~{ btn_one_player, btn_two_players, m_left2, m_right2, m_fire2, 1'b0, m_down2, m_up1}; + + + +loc_top loc_top( + .RESET(status[0] | status[6] | buttons[1]), + .CLK24M(clock_24), + .hsync(hs), + .vsync(vs), + .hblank(hb), + .vblank(vb), + .r(r), + .g(g), + .b(b), + .SND(audio), + .DSW1(iDSW1), + .DSW2(iDSW2), + .CTR1(iCTR1), + .CTR2(iCTR2), + .LAMP() + ); + + +mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video( + .clk_sys ( clock_24 ), + .SPI_SCK ( SPI_SCK ), + .SPI_SS3 ( SPI_SS3 ), + .SPI_DI ( SPI_DI ), + .R ( blankn ? r : 0 ), + .G ( blankn ? g : 0 ), + .B ( blankn ? {b,1'b0} : 0 ), + .HSync ( hs ), + .VSync ( vs ), + .VGA_R ( VGA_R ), + .VGA_G ( VGA_G ), + .VGA_B ( VGA_B ), + .VGA_VS ( VGA_VS ), + .VGA_HS ( VGA_HS ), + .rotate ({1'b1,status[2]} ), + .scandoubler_disable( scandoublerD ), + .scanlines ( status[4:3] ), + .ypbpr ( ypbpr ) + ); + +user_io #(.STRLEN(($size(CONF_STR)>>3)))user_io( + .clk_sys (clock_24 ), + .conf_str (CONF_STR ), + .SPI_CLK (SPI_SCK ), + .SPI_SS_IO (CONF_DATA0 ), + .SPI_MISO (SPI_DO ), + .SPI_MOSI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable (scandoublerD ), + .ypbpr (ypbpr ), + .key_strobe (key_strobe ), + .key_pressed (key_pressed ), + .key_code (key_code ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) + ); + +dac #(.C_bits(16))dac( + .clk_i(clock_24), + .res_n_i(1), + .dac_i({audio,audio[4:0]}), + .dac_o(AUDIO_L) + ); + +wire m_up1 = btn_up | joystick_0[3]; +wire m_down1 = btn_down | joystick_0[2]; +wire m_left1 = btn_left | joystick_0[1]; +wire m_right1 = btn_right | joystick_0[0]; +wire m_fire1 = btn_fire1 | joystick_0[4]; + +wire m_up2 = btn_up | joystick_1[3]; +wire m_down2 = btn_down | joystick_1[2]; +wire m_left2 = btn_left | joystick_1[1]; +wire m_right2 = btn_right | joystick_1[0]; +wire m_fire2 = btn_fire1 | joystick_1[4]; + + +reg btn_one_player = 0; +reg btn_two_players = 0; +reg btn_left = 0; +reg btn_right = 0; +reg btn_down = 0; +reg btn_up = 0; +reg btn_fire1 = 0; +//reg btn_fire2 = 0; +//reg btn_fire3 = 0; +reg btn_coin = 0; + +always @(posedge clock_24) begin + reg old_state; + old_state <= key_strobe; + if(old_state != key_strobe) begin + case(key_code) + 'h75: btn_up <= key_pressed; // up + 'h72: btn_down <= key_pressed; // down + 'h6B: btn_left <= key_pressed; // left + 'h74: btn_right <= key_pressed; // right + 'h76: btn_coin <= key_pressed; // ESC + 'h05: btn_one_player <= key_pressed; // F1 + 'h06: btn_two_players <= key_pressed; // F2 + // 'h14: btn_fire3 <= key_pressed; // ctrl + // 'h11: btn_fire2 <= key_pressed; // alt + 'h29: btn_fire1 <= key_pressed; // Space + endcase + end +end + + +endmodule diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T65/T65.vhd b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T65/T65.vhd new file mode 100644 index 00000000..09253fe0 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T65/T65.vhd @@ -0,0 +1,564 @@ +-- **** +-- T65(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 more merging +-- Ver 300 Bugfixes by ehenciak added, started tidyup *bust* +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- 65xx compatible microprocessor core +-- +-- Version : 0246 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t65/ +-- +-- Limitations : +-- +-- 65C02 and 65C816 modes are incomplete +-- Undocumented instructions are not supported +-- Some interface signals behaves incorrect +-- +-- File history : +-- +-- 0246 : First release +-- + +library IEEE; + use IEEE.std_logic_1164.all; + use IEEE.numeric_std.all; + use work.T65_Pack.all; + +-- ehenciak 2-23-2005 : Added the enable signal so that one doesn't have to use +-- the ready signal to limit the CPU. +entity T65 is + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816 + Res_n : in std_logic; + Enable : in std_logic; + Clk : in std_logic; + Rdy : in std_logic; + Abort_n : in std_logic; + IRQ_n : in std_logic; + NMI_n : in std_logic; + SO_n : in std_logic; + R_W_n : out std_logic; + Sync : out std_logic; + EF : out std_logic; + MF : out std_logic; + XF : out std_logic; + ML_n : out std_logic; + VP_n : out std_logic; + VDA : out std_logic; + VPA : out std_logic; + A : out std_logic_vector(23 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T65; + +architecture rtl of T65 is + + -- Registers + signal ABC, X, Y, D : std_logic_vector(15 downto 0); + signal P, AD, DL : std_logic_vector(7 downto 0) := x"00"; + signal BAH : std_logic_vector(7 downto 0); + signal BAL : std_logic_vector(8 downto 0); + signal PBR : std_logic_vector(7 downto 0); + signal DBR : std_logic_vector(7 downto 0); + signal PC : unsigned(15 downto 0); + signal S : unsigned(15 downto 0); + signal EF_i : std_logic; + signal MF_i : std_logic; + signal XF_i : std_logic; + + signal IR : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + + signal Mode_r : std_logic_vector(1 downto 0); + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Write_Data_r : std_logic_vector(2 downto 0); + signal Set_Addr_To_r : std_logic_vector(1 downto 0); + signal PCAdder : unsigned(8 downto 0); + + signal RstCycle : std_logic; + signal IRQCycle : std_logic; + signal NMICycle : std_logic; + + signal B_o : std_logic; + signal SO_n_o : std_logic; + signal IRQ_n_o : std_logic; + signal NMI_n_o : std_logic; + signal NMIAct : std_logic; + + signal Break : std_logic; + + -- ALU signals + signal BusA : std_logic_vector(7 downto 0); + signal BusA_r : std_logic_vector(7 downto 0); + signal BusB : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal P_Out : std_logic_vector(7 downto 0); + + -- Micro code outputs + signal LCycle : std_logic_vector(2 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(2 downto 0); + signal Set_Addr_To : std_logic_vector(1 downto 0); + signal Write_Data : std_logic_vector(2 downto 0); + signal Jump : std_logic_vector(1 downto 0); + signal BAAdd : std_logic_vector(1 downto 0); + signal BreakAtNA : std_logic; + signal ADAdd : std_logic; + signal AddY : std_logic; + signal PCAdd : std_logic; + signal Inc_S : std_logic; + signal Dec_S : std_logic; + signal LDA : std_logic; + signal LDP : std_logic; + signal LDX : std_logic; + signal LDY : std_logic; + signal LDS : std_logic; + signal LDDI : std_logic; + signal LDALU : std_logic; + signal LDAD : std_logic; + signal LDBAL : std_logic; + signal LDBAH : std_logic; + signal SaveP : std_logic; + signal Write : std_logic; + + signal really_rdy : std_logic; + signal R_W_n_i : std_logic; + +begin + -- ehenciak : gate Rdy with read/write to make an "OK, it's + -- really OK to stop the processor now if Rdy is + -- deasserted" signal + really_rdy <= Rdy or not(R_W_n_i); + + -- ehenciak : Drive R_W_n_i off chip. + R_W_n <= R_W_n_i; + + Sync <= '1' when MCycle = "000" else '0'; + EF <= EF_i; + MF <= MF_i; + XF <= XF_i; + ML_n <= '0' when IR(7 downto 6) /= "10" and IR(2 downto 1) = "11" and MCycle(2 downto 1) /= "00" else '1'; + VP_n <= '0' when IRQCycle = '1' and (MCycle = "101" or MCycle = "110") else '1'; + VDA <= '1' when Set_Addr_To_r /= "00" else '0'; -- Incorrect !!!!!!!!!!!! + VPA <= '1' when Jump(1) = '0' else '0'; -- Incorrect !!!!!!!!!!!! + + mcode : T65_MCode + port map( + Mode => Mode_r, + IR => IR, + MCycle => MCycle, + P => P, + LCycle => LCycle, + ALU_Op => ALU_Op, + Set_BusA_To => Set_BusA_To, + Set_Addr_To => Set_Addr_To, + Write_Data => Write_Data, + Jump => Jump, + BAAdd => BAAdd, + BreakAtNA => BreakAtNA, + ADAdd => ADAdd, + AddY => AddY, + PCAdd => PCAdd, + Inc_S => Inc_S, + Dec_S => Dec_S, + LDA => LDA, + LDP => LDP, + LDX => LDX, + LDY => LDY, + LDS => LDS, + LDDI => LDDI, + LDALU => LDALU, + LDAD => LDAD, + LDBAL => LDBAL, + LDBAH => LDBAH, + SaveP => SaveP, + Write => Write + ); + + alu : T65_ALU + port map( + Mode => Mode_r, + Op => ALU_Op_r, + BusA => BusA_r, + BusB => BusB, + P_In => P, + P_Out => P_Out, + Q => ALU_Q + ); + + process (Res_n, Clk) + begin + if Res_n = '0' then + PC <= (others => '0'); -- Program Counter + IR <= "00000000"; + S <= (others => '0'); -- Dummy !!!!!!!!!!!!!!!!!!!!! + D <= (others => '0'); + PBR <= (others => '0'); + DBR <= (others => '0'); + + Mode_r <= (others => '0'); + ALU_Op_r <= "1100"; + Write_Data_r <= "000"; + Set_Addr_To_r <= "00"; + + R_W_n_i <= '1'; + EF_i <= '1'; + MF_i <= '1'; + XF_i <= '1'; + + elsif Clk'event and Clk = '1' then + if (Enable = '1') then + if (really_rdy = '1') then + R_W_n_i <= not Write or RstCycle; + + D <= (others => '1'); -- Dummy + PBR <= (others => '1'); -- Dummy + DBR <= (others => '1'); -- Dummy + EF_i <= '0'; -- Dummy + MF_i <= '0'; -- Dummy + XF_i <= '0'; -- Dummy + + if MCycle = "000" then + Mode_r <= Mode; + + if IRQCycle = '0' and NMICycle = '0' then + PC <= PC + 1; + end if; + + if IRQCycle = '1' or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DI; + end if; + end if; + + ALU_Op_r <= ALU_Op; + Write_Data_r <= Write_Data; + if Break = '1' then + Set_Addr_To_r <= "00"; + else + Set_Addr_To_r <= Set_Addr_To; + end if; + + if Inc_S = '1' then + S <= S + 1; + end if; + if Dec_S = '1' and RstCycle = '0' then + S <= S - 1; + end if; + if LDS = '1' then + S(7 downto 0) <= unsigned(ALU_Q); + end if; + + if IR = "00000000" and MCycle = "001" and IRQCycle = '0' and NMICycle = '0' then + PC <= PC + 1; + end if; + -- + -- jump control logic + -- + case Jump is + when "01" => + PC <= PC + 1; + + when "10" => + PC <= unsigned(DI & DL); + + when "11" => + if PCAdder(8) = '1' then + if DL(7) = '0' then + PC(15 downto 8) <= PC(15 downto 8) + 1; + else + PC(15 downto 8) <= PC(15 downto 8) - 1; + end if; + end if; + PC(7 downto 0) <= PCAdder(7 downto 0); + + when others => null; + end case; + end if; + end if; + end if; + end process; + + PCAdder <= resize(PC(7 downto 0),9) + resize(unsigned(DL(7) & DL),9) when PCAdd = '1' + else "0" & PC(7 downto 0); + + process (Clk) + begin + if Clk'event and Clk = '1' then + if (Enable = '1') then + if (really_rdy = '1') then + if MCycle = "000" then + if LDA = '1' then + ABC(7 downto 0) <= ALU_Q; + end if; + if LDX = '1' then + X(7 downto 0) <= ALU_Q; + end if; + if LDY = '1' then + Y(7 downto 0) <= ALU_Q; + end if; + if (LDA or LDX or LDY) = '1' then + P <= P_Out; + end if; + end if; + if SaveP = '1' then + P <= P_Out; + end if; + if LDP = '1' then + P <= ALU_Q; + end if; + if IR(4 downto 0) = "11000" then + case IR(7 downto 5) is + when "000" => + P(Flag_C) <= '0'; + when "001" => + P(Flag_C) <= '1'; + when "010" => + P(Flag_I) <= '0'; + when "011" => + P(Flag_I) <= '1'; + when "101" => + P(Flag_V) <= '0'; + when "110" => + P(Flag_D) <= '0'; + when "111" => + P(Flag_D) <= '1'; + when others => + end case; + end if; + + --if IR = "00000000" and MCycle = "011" and RstCycle = '0' and NMICycle = '0' and IRQCycle = '0' then + -- P(Flag_B) <= '1'; + --end if; + --if IR = "00000000" and MCycle = "100" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1') then + -- P(Flag_I) <= '1'; + -- P(Flag_B) <= B_o; + --end if; + + -- B=1 always on the 6502 + P(Flag_B) <= '1'; + if IR = "00000000" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1') then + if MCycle = "011" then + -- B=0 in *copy* of P pushed onto the stack + P(Flag_B) <= '0'; + elsif MCycle = "100" then + P(Flag_I) <= '1'; + end if; + end if; + + if SO_n_o = '1' and SO_n = '0' then + P(Flag_V) <= '1'; + end if; + if RstCycle = '1' and Mode_r /= "00" then + P(Flag_1) <= '1'; + P(Flag_D) <= '0'; + P(Flag_I) <= '1'; + end if; + P(Flag_1) <= '1'; + + B_o <= P(Flag_B); + SO_n_o <= SO_n; + IRQ_n_o <= IRQ_n; + NMI_n_o <= NMI_n; + end if; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + + process (Res_n, Clk) + begin + if Res_n = '0' then + BusA_r <= (others => '0'); + BusB <= (others => '0'); + AD <= (others => '0'); + BAL <= (others => '0'); + BAH <= (others => '0'); + DL <= (others => '0'); + elsif Clk'event and Clk = '1' then + if (Enable = '1') then + if (Rdy = '1') then + BusA_r <= BusA; + BusB <= DI; + + case BAAdd is + when "01" => + -- BA Inc + AD <= std_logic_vector(unsigned(AD) + 1); + BAL <= std_logic_vector(unsigned(BAL) + 1); + when "10" => + -- BA Add + BAL <= std_logic_vector(resize(unsigned(BAL(7 downto 0)),9) + resize(unsigned(BusA),9)); + when "11" => + -- BA Adj + if BAL(8) = '1' then + BAH <= std_logic_vector(unsigned(BAH) + 1); + end if; + when others => + end case; + + -- ehenciak : modified to use Y register as well (bugfix) + if ADAdd = '1' then + if (AddY = '1') then + AD <= std_logic_vector(unsigned(AD) + unsigned(Y(7 downto 0))); + else + AD <= std_logic_vector(unsigned(AD) + unsigned(X(7 downto 0))); + end if; + end if; + + if IR = "00000000" then + BAL <= (others => '1'); + BAH <= (others => '1'); + if RstCycle = '1' then + BAL(2 downto 0) <= "100"; + elsif NMICycle = '1' then + BAL(2 downto 0) <= "010"; + else + BAL(2 downto 0) <= "110"; + end if; + if Set_addr_To_r = "11" then + BAL(0) <= '1'; + end if; + end if; + + + if LDDI = '1' then + DL <= DI; + end if; + if LDALU = '1' then + DL <= ALU_Q; + end if; + if LDAD = '1' then + AD <= DI; + end if; + if LDBAL = '1' then + BAL(7 downto 0) <= DI; + end if; + if LDBAH = '1' then + BAH <= DI; + end if; + end if; + end if; + end if; + end process; + + Break <= (BreakAtNA and not BAL(8)) or (PCAdd and not PCAdder(8)); + + + with Set_BusA_To select + BusA <= DI when "000", + ABC(7 downto 0) when "001", + X(7 downto 0) when "010", + Y(7 downto 0) when "011", + std_logic_vector(S(7 downto 0)) when "100", + P when "101", + (others => '-') when others; + + with Set_Addr_To_r select + A <= "0000000000000001" & std_logic_vector(S(7 downto 0)) when "01", + DBR & "00000000" & AD when "10", + "00000000" & BAH & BAL(7 downto 0) when "11", + PBR & std_logic_vector(PC(15 downto 8)) & std_logic_vector(PCAdder(7 downto 0)) when others; + + with Write_Data_r select + DO <= DL when "000", + ABC(7 downto 0) when "001", + X(7 downto 0) when "010", + Y(7 downto 0) when "011", + std_logic_vector(S(7 downto 0)) when "100", + P when "101", + std_logic_vector(PC(7 downto 0)) when "110", + std_logic_vector(PC(15 downto 8)) when others; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + + process (Res_n, Clk) + begin + if Res_n = '0' then + MCycle <= "001"; + RstCycle <= '1'; + IRQCycle <= '0'; + NMICycle <= '0'; + NMIAct <= '0'; + elsif Clk'event and Clk = '1' then + if (Enable = '1') then + if (really_rdy = '1') then + if MCycle = LCycle or Break = '1' then + MCycle <= "000"; + RstCycle <= '0'; + IRQCycle <= '0'; + NMICycle <= '0'; + if NMIAct = '1' then + NMICycle <= '1'; + elsif IRQ_n_o = '0' and P(Flag_I) = '0' then + IRQCycle <= '1'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + + if NMICycle = '1' then + NMIAct <= '0'; + end if; + if NMI_n_o = '1' and NMI_n = '0' then + NMIAct <= '1'; + end if; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T65/T65_ALU.vhd b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T65/T65_ALU.vhd new file mode 100644 index 00000000..b1f6d632 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T65/T65_ALU.vhd @@ -0,0 +1,260 @@ +-- **** +-- T65(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 Bugfixes by ehenciak added +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- 6502 compatible microprocessor core +-- +-- Version : 0245 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t65/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0245 : First version +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T65_Pack.all; + +entity T65_ALU is + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816 + Op : in std_logic_vector(3 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + P_In : in std_logic_vector(7 downto 0); + P_Out : out std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0) + ); +end T65_ALU; + +architecture rtl of T65_ALU is + + -- AddSub variables (temporary signals) + signal ADC_Z : std_logic; + signal ADC_C : std_logic; + signal ADC_V : std_logic; + signal ADC_N : std_logic; + signal ADC_Q : std_logic_vector(7 downto 0); + signal SBC_Z : std_logic; + signal SBC_C : std_logic; + signal SBC_V : std_logic; + signal SBC_N : std_logic; + signal SBC_Q : std_logic_vector(7 downto 0); + +begin + + process (P_In, BusA, BusB) + variable AL : unsigned(6 downto 0); + variable AH : unsigned(6 downto 0); + variable C : std_logic; + begin + AL := resize(unsigned(BusA(3 downto 0) & P_In(Flag_C)), 7) + resize(unsigned(BusB(3 downto 0) & "1"), 7); + AH := resize(unsigned(BusA(7 downto 4) & AL(5)), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7); + +-- pragma translate_off + if is_x(std_logic_vector(AL)) then AL := "0000000"; end if; + if is_x(std_logic_vector(AH)) then AH := "0000000"; end if; +-- pragma translate_on + + if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then + ADC_Z <= '1'; + else + ADC_Z <= '0'; + end if; + + if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' then + AL(6 downto 1) := AL(6 downto 1) + 6; + end if; + + C := AL(6) or AL(5); + AH := resize(unsigned(BusA(7 downto 4) & C), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7); + + ADC_N <= AH(4); + ADC_V <= (AH(4) xor BusA(7)) and not (BusA(7) xor BusB(7)); + +-- pragma translate_off + if is_x(std_logic_vector(AH)) then AH := "0000000"; end if; +-- pragma translate_on + + if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' then + AH(6 downto 1) := AH(6 downto 1) + 6; + end if; + + ADC_C <= AH(6) or AH(5); + + ADC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1)); + end process; + + process (Op, P_In, BusA, BusB) + variable AL : unsigned(6 downto 0); + variable AH : unsigned(5 downto 0); + variable C : std_logic; + begin + C := P_In(Flag_C) or not Op(0); + AL := resize(unsigned(BusA(3 downto 0) & C), 7) - resize(unsigned(BusB(3 downto 0) & "1"), 6); + AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(5)), 6); + +-- pragma translate_off + if is_x(std_logic_vector(AL)) then AL := "0000000"; end if; + if is_x(std_logic_vector(AH)) then AH := "000000"; end if; +-- pragma translate_on + + if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then + SBC_Z <= '1'; + else + SBC_Z <= '0'; + end if; + + SBC_C <= not AH(5); + SBC_V <= (AH(4) xor BusA(7)) and (BusA(7) xor BusB(7)); + SBC_N <= AH(4); + + if P_In(Flag_D) = '1' then + if AL(5) = '1' then + AL(5 downto 1) := AL(5 downto 1) - 6; + end if; + AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(6)), 6); + if AH(5) = '1' then + AH(5 downto 1) := AH(5 downto 1) - 6; + end if; + end if; + + SBC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1)); + end process; + + process (Op, P_In, BusA, BusB, + ADC_Z, ADC_C, ADC_V, ADC_N, ADC_Q, + SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q) + variable Q_t : std_logic_vector(7 downto 0); + begin + -- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC + -- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC + P_Out <= P_In; + Q_t := BusA; + case Op(3 downto 0) is + when "0000" => + -- ORA + Q_t := BusA or BusB; + when "0001" => + -- AND + Q_t := BusA and BusB; + when "0010" => + -- EOR + Q_t := BusA xor BusB; + when "0011" => + -- ADC + P_Out(Flag_V) <= ADC_V; + P_Out(Flag_C) <= ADC_C; + Q_t := ADC_Q; + when "0101" | "1101" => + -- LDA + when "0110" => + -- CMP + P_Out(Flag_C) <= SBC_C; + when "0111" => + -- SBC + P_Out(Flag_V) <= SBC_V; + P_Out(Flag_C) <= SBC_C; + Q_t := SBC_Q; + when "1000" => + -- ASL + Q_t := BusA(6 downto 0) & "0"; + P_Out(Flag_C) <= BusA(7); + when "1001" => + -- ROL + Q_t := BusA(6 downto 0) & P_In(Flag_C); + P_Out(Flag_C) <= BusA(7); + when "1010" => + -- LSR + Q_t := "0" & BusA(7 downto 1); + P_Out(Flag_C) <= BusA(0); + when "1011" => + -- ROR + Q_t := P_In(Flag_C) & BusA(7 downto 1); + P_Out(Flag_C) <= BusA(0); + when "1100" => + -- BIT + P_Out(Flag_V) <= BusB(6); + when "1110" => + -- DEC + Q_t := std_logic_vector(unsigned(BusA) - 1); + when "1111" => + -- INC + Q_t := std_logic_vector(unsigned(BusA) + 1); + when others => + end case; + + case Op(3 downto 0) is + when "0011" => + P_Out(Flag_N) <= ADC_N; + P_Out(Flag_Z) <= ADC_Z; + when "0110" | "0111" => + P_Out(Flag_N) <= SBC_N; + P_Out(Flag_Z) <= SBC_Z; + when "0100" => + when "1100" => + P_Out(Flag_N) <= BusB(7); + if (BusA and BusB) = "00000000" then + P_Out(Flag_Z) <= '1'; + else + P_Out(Flag_Z) <= '0'; + end if; + when others => + P_Out(Flag_N) <= Q_t(7); + if Q_t = "00000000" then + P_Out(Flag_Z) <= '1'; + else + P_Out(Flag_Z) <= '0'; + end if; + end case; + + Q <= Q_t; + end process; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T65/T65_MCode.vhd b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T65/T65_MCode.vhd new file mode 100644 index 00000000..6c6c864a --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T65/T65_MCode.vhd @@ -0,0 +1,1052 @@ +-- **** +-- T65(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 302 minor timing fixes +-- Ver 301 Jump timing fixed +-- Ver 300 Bugfixes by ehenciak added +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- 65xx compatible microprocessor core +-- +-- Version : 0246 + fix +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t65/ +-- +-- Limitations : +-- +-- 65C02 +-- supported : inc, dec, phx, plx, phy, ply +-- missing : bra, ora, lda, cmp, sbc, tsb*2, trb*2, stz*2, bit*2, wai, stp, jmp, bbr*8, bbs*8 +-- +-- File history : +-- +-- 0246 : First release +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T65_Pack.all; + +entity T65_MCode is + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816 + IR : in std_logic_vector(7 downto 0); + MCycle : in std_logic_vector(2 downto 0); + P : in std_logic_vector(7 downto 0); + LCycle : out std_logic_vector(2 downto 0); + ALU_Op : out std_logic_vector(3 downto 0); + Set_BusA_To : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P + Set_Addr_To : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA + Write_Data : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH + Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel + BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj + BreakAtNA : out std_logic; + ADAdd : out std_logic; + AddY : out std_logic; + PCAdd : out std_logic; + Inc_S : out std_logic; + Dec_S : out std_logic; + LDA : out std_logic; + LDP : out std_logic; + LDX : out std_logic; + LDY : out std_logic; + LDS : out std_logic; + LDDI : out std_logic; + LDALU : out std_logic; + LDAD : out std_logic; + LDBAL : out std_logic; + LDBAH : out std_logic; + SaveP : out std_logic; + Write : out std_logic + ); +end T65_MCode; + +architecture rtl of T65_MCode is + + signal Branch : std_logic; + +begin + + with IR(7 downto 5) select + Branch <= not P(Flag_N) when "000", + P(Flag_N) when "001", + not P(Flag_V) when "010", + P(Flag_V) when "011", + not P(Flag_C) when "100", + P(Flag_C) when "101", + not P(Flag_Z) when "110", + P(Flag_Z) when others; + + process (IR, MCycle, P, Branch, Mode) + begin + LCycle <= "001"; + Set_BusA_To <= "001"; -- A + Set_Addr_To <= (others => '0'); + Write_Data <= (others => '0'); + Jump <= (others => '0'); + BAAdd <= "00"; + BreakAtNA <= '0'; + ADAdd <= '0'; + PCAdd <= '0'; + Inc_S <= '0'; + Dec_S <= '0'; + LDA <= '0'; + LDP <= '0'; + LDX <= '0'; + LDY <= '0'; + LDS <= '0'; + LDDI <= '0'; + LDALU <= '0'; + LDAD <= '0'; + LDBAL <= '0'; + LDBAH <= '0'; + SaveP <= '0'; + Write <= '0'; + AddY <= '0'; + + case IR(7 downto 5) is + when "100" => + --{{{ + case IR(1 downto 0) is + when "00" => + Set_BusA_To <= "011"; -- Y + Write_Data <= "011"; -- Y + when "10" => + Set_BusA_To <= "010"; -- X + Write_Data <= "010"; -- X + when others => + Write_Data <= "001"; -- A + end case; + --}}} + when "101" => + --{{{ + case IR(1 downto 0) is + when "00" => + if IR(4) /= '1' or IR(2) /= '0' then + LDY <= '1'; + end if; + when "10" => + LDX <= '1'; + when others => + LDA <= '1'; + end case; + Set_BusA_To <= "000"; -- DI + --}}} + when "110" => + --{{{ + case IR(1 downto 0) is + when "00" => + if IR(4) = '0' then + LDY <= '1'; + end if; + Set_BusA_To <= "011"; -- Y + when others => + Set_BusA_To <= "001"; -- A + end case; + --}}} + when "111" => + --{{{ + case IR(1 downto 0) is + when "00" => + if IR(4) = '0' then + LDX <= '1'; + end if; + Set_BusA_To <= "010"; -- X + when others => + Set_BusA_To <= "001"; -- A + end case; + --}}} + when others => + end case; + + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + Set_BusA_To <= "000"; -- DI + end if; + + case IR(4 downto 0) is + when "00000" | "01000" | "01010" | "11000" | "11010" => + --{{{ + -- Implied + case IR is + when "00000000" => + -- BRK + LCycle <= "110"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= "01"; -- S + Write_Data <= "111"; -- PCH + Write <= '1'; + when 2 => + Dec_S <= '1'; + Set_Addr_To <= "01"; -- S + Write_Data <= "110"; -- PCL + Write <= '1'; + when 3 => + Dec_S <= '1'; + Set_Addr_To <= "01"; -- S + Write_Data <= "101"; -- P + Write <= '1'; + when 4 => + Dec_S <= '1'; + Set_Addr_To <= "11"; -- BA + when 5 => + LDDI <= '1'; + Set_Addr_To <= "11"; -- BA + when 6 => + Jump <= "10"; -- DIDL + when others => + end case; + when "00100000" => + -- JSR + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDDI <= '1'; + Set_Addr_To <= "01"; -- S + when 2 => + Set_Addr_To <= "01"; -- S + Write_Data <= "111"; -- PCH + Write <= '1'; + when 3 => + Dec_S <= '1'; + Set_Addr_To <= "01"; -- S + Write_Data <= "110"; -- PCL + Write <= '1'; + when 4 => + Dec_S <= '1'; + when 5 => + Jump <= "10"; -- DIDL + when others => + end case; + when "01000000" => + -- RTI + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= "01"; -- S + when 2 => + Inc_S <= '1'; + Set_Addr_To <= "01"; -- S + when 3 => + Inc_S <= '1'; + Set_Addr_To <= "01"; -- S + Set_BusA_To <= "000"; -- DI + when 4 => + LDP <= '1'; + Inc_S <= '1'; + LDDI <= '1'; + Set_Addr_To <= "01"; -- S + when 5 => + Jump <= "10"; -- DIDL + when others => + end case; + when "01100000" => + -- RTS + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= "01"; -- S + when 2 => + Inc_S <= '1'; + Set_Addr_To <= "01"; -- S + when 3 => + Inc_S <= '1'; + LDDI <= '1'; + Set_Addr_To <= "01"; -- S + when 4 => + Jump <= "10"; -- DIDL + when 5 => + Jump <= "01"; + when others => + end case; + when "00001000" | "01001000" | "01011010" | "11011010" => + -- PHP, PHA, PHY*, PHX* + LCycle <= "010"; + if Mode = "00" and IR(1) = '1' then + LCycle <= "001"; + end if; + case to_integer(unsigned(MCycle)) is + when 1 => + case IR(7 downto 4) is + when "0000" => + Write_Data <= "101"; -- P + when "0100" => + Write_Data <= "001"; -- A + when "0101" => + Write_Data <= "011"; -- Y + when "1101" => + Write_Data <= "010"; -- X + when others => + end case; + Write <= '1'; + Set_Addr_To <= "01"; -- S + when 2 => + Dec_S <= '1'; + when others => + end case; + when "00101000" | "01101000" | "01111010" | "11111010" => + -- PLP, PLA, PLY*, PLX* + LCycle <= "011"; + if Mode = "00" and IR(1) = '1' then + LCycle <= "001"; + end if; + case IR(7 downto 4) is + when "0010" => + LDP <= '1'; + when "0110" => + LDA <= '1'; + when "0111" => + if Mode /= "00" then + LDY <= '1'; + end if; + when "1111" => + if Mode /= "00" then + LDX <= '1'; + end if; + when others => + end case; + case to_integer(unsigned(MCycle)) is + when 0 => + SaveP <= '1'; + when 1 => + Set_Addr_To <= "01"; -- S + when 2 => + Inc_S <= '1'; + Set_Addr_To <= "01"; -- S + when 3 => + Set_BusA_To <= "000"; -- DI + when others => + end case; + when "10100000" | "11000000" | "11100000" => + -- LDY, CPY, CPX + -- Immediate + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + when others => + end case; + when "10001000" => + -- DEY + LDY <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "011"; -- Y + when others => + end case; + when "11001010" => + -- DEX + LDX <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "010"; -- X + when others => + end case; + when "00011010" | "00111010" => + -- INC*, DEC* + if Mode /= "00" then + LDA <= '1'; -- A + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "100"; -- S + when others => + end case; + when "00001010" | "00101010" | "01001010" | "01101010" => + -- ASL, ROL, LSR, ROR + LDA <= '1'; -- A + Set_BusA_To <= "001"; -- A + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + when others => + end case; + when "10001010" | "10011000" => + -- TYA, TXA + LDA <= '1'; -- A + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + when others => + end case; + when "10101010" | "10101000" => + -- TAX, TAY + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "001"; -- A + when others => + end case; + when "10011010" => + -- TXS + case to_integer(unsigned(MCycle)) is + when 0 => + LDS <= '1'; + when 1 => + when others => + end case; + when "10111010" => + -- TSX + LDX <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "100"; -- S + when others => + end case; + + -- when "00011000" | "00111000" | "01011000" | "01111000" | "10111000" | "11011000" | "11111000" | "11001000" | "11101000" => + -- -- CLC, SEC, CLI, SEI, CLV, CLD, SED, INY, INX + -- case to_integer(unsigned(MCycle)) is + -- when 1 => + -- when others => + -- end case; + when others => + case to_integer(unsigned(MCycle)) is + when 0 => + when others => + end case; + end case; + --}}} + + when "00001" | "00011" => + --{{{ + -- Zero Page Indexed Indirect (d,x) + LCycle <= "101"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + ADAdd <= '1'; + Set_Addr_To <= "10"; -- AD + when 3 => + BAAdd <= "01"; -- DB Inc + LDBAL <= '1'; + Set_Addr_To <= "10"; -- AD + when 4 => + LDBAH <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 5 => + when others => + end case; + --}}} + + when "01001" | "01011" => + --{{{ + -- Immediate + LDA <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + when others => + end case; + + --}}} + + when "00010" | "10010" => + --{{{ + -- Immediate, KIL + LDX <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + if IR = "10100010" then + -- LDX + Jump <= "01"; + else + -- KIL !!!!!!!!!!!!!!!!!!!!!!!!!!!!! + end if; + when others => + end case; + --}}} + + when "00100" => + --{{{ + -- Zero Page + LCycle <= "010"; + case to_integer(unsigned(MCycle)) is + when 0 => + if IR(7 downto 5) = "001" then + SaveP <= '1'; + end if; + when 1 => + Jump <= "01"; + LDAD <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "10"; -- AD + when 2 => + when others => + end case; + --}}} + + when "00101" | "00110" | "00111" => + --{{{ + -- Zero Page + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + -- Read-Modify-Write + LCycle <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + LDDI <= '1'; + Write <= '1'; + Set_Addr_To <= "10"; -- AD + when 3 => + LDALU <= '1'; + SaveP <= '1'; + Write <= '1'; + Set_Addr_To <= "10"; -- AD + when 4 => + when others => + end case; + else + LCycle <= "010"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDAD <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "10"; -- AD + when 2 => + when others => + end case; + end if; + --}}} + + when "01100" => + --{{{ + -- Absolute + if IR(7 downto 6) = "01" and IR(4 downto 0) = "01100" then + -- JMP + if IR(5) = '0' then + --LCycle <= "011"; + LCycle <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDDI <= '1'; + when 2 => + Jump <= "10"; -- DIDL + when others => + end case; + else + --LCycle <= "101"; + LCycle <= "100"; -- mikej + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDDI <= '1'; + LDBAL <= '1'; + when 2 => + LDBAH <= '1'; + if Mode /= "00" then + Jump <= "10"; -- DIDL + end if; + if Mode = "00" then + Set_Addr_To <= "11"; -- BA + end if; + when 3 => + LDDI <= '1'; + if Mode = "00" then + Set_Addr_To <= "11"; -- BA + BAAdd <= "01"; -- DB Inc + else + Jump <= "01"; + end if; + when 4 => + Jump <= "10"; -- DIDL + when others => + end case; + end if; + else + LCycle <= "011"; + case to_integer(unsigned(MCycle)) is + when 0 => + if IR(7 downto 5) = "001" then + SaveP <= '1'; + end if; + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + LDBAH <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 3 => + when others => + end case; + end if; + --}}} + + when "01101" | "01110" | "01111" => + --{{{ + -- Absolute + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + -- Read-Modify-Write + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 3 => + LDDI <= '1'; + Write <= '1'; + Set_Addr_To <= "11"; -- BA + when 4 => + Write <= '1'; + LDALU <= '1'; + SaveP <= '1'; + Set_Addr_To <= "11"; -- BA + when 5 => + SaveP <= '0'; -- MIKEJ was 1 + when others => + end case; + else + LCycle <= "011"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + LDBAH <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 3 => + when others => + end case; + end if; + --}}} + + when "10000" => + --{{{ + -- Relative + + -- This circuit dictates when the last + -- microcycle occurs for the branch depending on + -- whether or not the branch is taken and if a page + -- is crossed... + if (Branch = '1') then + + LCycle <= "011"; -- We're done @ T3 if branching...upper + -- level logic will stop at T2 if no page cross + -- (See the Break signal) + else + + LCycle <= "001"; + + end if; + + -- This decodes the current microcycle and takes the + -- proper course of action... + case to_integer(unsigned(MCycle)) is + + -- On the T1 microcycle, increment the program counter + -- and instruct the upper level logic to fetch the offset + -- from the Din bus and store it in the data latches. This + -- will be the last microcycle if the branch isn't taken. + when 1 => + + Jump <= "01"; -- Increments the PC by one (PC will now be PC+2) + -- from microcycle T0. + + LDDI <= '1'; -- Tells logic in top level (T65.vhd) to route + -- the Din bus to the memory data latch (DL) + -- so that the branch offset is fetched. + + -- In microcycle T2, tell the logic in the top level to + -- add the offset. If the most significant byte of the + -- program counter (i.e. the current "page") does not need + -- updating, we are done here...the Break signal at the + -- T65.vhd level takes care of that... + when 2 => + + Jump <= "11"; -- Tell the PC Jump logic to use relative mode. + + PCAdd <= '1'; -- This tells the PC adder to update itself with + -- the current offset recently fetched from + -- memory. + + -- The following is microcycle T3 : + -- The program counter should be completely updated + -- on this cycle after the page cross is detected. + -- We don't need to do anything here... + when 3 => + + + when others => null; -- Do nothing. + + end case; + --}}} + + when "10001" | "10011" => + --{{{ + -- Zero Page Indirect Indexed (d),y + LCycle <= "101"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + LDBAL <= '1'; + BAAdd <= "01"; -- DB Inc + Set_Addr_To <= "10"; -- AD + when 3 => + Set_BusA_To <= "011"; -- Y + BAAdd <= "10"; -- BA Add + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 4 => + BAAdd <= "11"; -- BA Adj + if IR(7 downto 5) = "100" then + Write <= '1'; + else + BreakAtNA <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 5 => + when others => + end case; + --}}} + + when "10100" | "10101" | "10110" | "10111" => + --{{{ + -- Zero Page, X + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + -- Read-Modify-Write + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + ADAdd <= '1'; + Set_Addr_To <= "10"; -- AD + when 3 => + LDDI <= '1'; + Write <= '1'; + Set_Addr_To <= "10"; -- AD + when 4 => + LDALU <= '1'; + SaveP <= '1'; + Write <= '1'; + Set_Addr_To <= "10"; -- AD + when 5 => + when others => + end case; + else + LCycle <= "011"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + ADAdd <= '1'; + -- Added this check for Y reg. use... + if (IR(3 downto 0) = "0110") then + AddY <= '1'; + end if; + + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "10"; -- AD + when 3 => null; + when others => + end case; + end if; + --}}} + + when "11001" | "11011" => + --{{{ + -- Absolute Y + LCycle <= "100"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + Set_BusA_To <= "011"; -- Y + BAAdd <= "10"; -- BA Add + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 3 => + BAAdd <= "11"; -- BA adj + if IR(7 downto 5) = "100" then + Write <= '1'; + else + BreakAtNA <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 4 => + when others => + end case; + --}}} + + when "11100" | "11101" | "11110" | "11111" => + --{{{ + -- Absolute X + + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + -- Read-Modify-Write + LCycle <= "110"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + Set_BusA_To <= "010"; -- X + BAAdd <= "10"; -- BA Add + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 3 => + BAAdd <= "11"; -- BA adj + Set_Addr_To <= "11"; -- BA + when 4 => + LDDI <= '1'; + Write <= '1'; + Set_Addr_To <= "11"; -- BA + when 5 => + LDALU <= '1'; + SaveP <= '1'; + Write <= '1'; + Set_Addr_To <= "11"; -- BA + when 6 => + when others => + end case; + else + LCycle <= "100"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + -- mikej + -- special case 0xBE which uses Y reg as index!! + if (IR = "10111110") then + Set_BusA_To <= "011"; -- Y + else + Set_BusA_To <= "010"; -- X + end if; + BAAdd <= "10"; -- BA Add + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 3 => + BAAdd <= "11"; -- BA adj + if IR(7 downto 5) = "100" then + Write <= '1'; + else + BreakAtNA <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 4 => + when others => + end case; + end if; + --}}} + when others => + end case; + end process; + + process (IR, MCycle) + begin + -- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC + -- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC + case IR(1 downto 0) is + when "00" => + --{{{ + case IR(4 downto 2) is + when "000" | "001" | "011" => + case IR(7 downto 5) is + when "110" | "111" => + -- CP + ALU_Op <= "0110"; + when "101" => + -- LD + ALU_Op <= "0101"; + when "001" => + -- BIT + ALU_Op <= "1100"; + when others => + -- NOP/ST + ALU_Op <= "0100"; + end case; + when "010" => + case IR(7 downto 5) is + when "111" | "110" => + -- IN + ALU_Op <= "1111"; + when "100" => + -- DEY + ALU_Op <= "1110"; + when others => + -- LD + ALU_Op <= "1101"; + end case; + when "110" => + case IR(7 downto 5) is + when "100" => + -- TYA + ALU_Op <= "1101"; + when others => + ALU_Op <= "----"; + end case; + when others => + case IR(7 downto 5) is + when "101" => + -- LD + ALU_Op <= "1101"; + when others => + ALU_Op <= "0100"; + end case; + end case; + --}}} + when "01" => -- OR + --{{{ + ALU_Op(3) <= '0'; + ALU_Op(2 downto 0) <= IR(7 downto 5); + --}}} + when "10" => + --{{{ + ALU_Op(3) <= '1'; + ALU_Op(2 downto 0) <= IR(7 downto 5); + case IR(7 downto 5) is + when "000" => + if IR(4 downto 2) = "110" then + -- INC + ALU_Op <= "1111"; + end if; + when "001" => + if IR(4 downto 2) = "110" then + -- DEC + ALU_Op <= "1110"; + end if; + when "100" => + if IR(4 downto 2) = "010" then + -- TXA + ALU_Op <= "0101"; + else + ALU_Op <= "0100"; + end if; + when others => + end case; + --}}} + when others => + --{{{ + case IR(7 downto 5) is + when "100" => + ALU_Op <= "0100"; + when others => + if MCycle = "000" then + ALU_Op(3) <= '0'; + ALU_Op(2 downto 0) <= IR(7 downto 5); + else + ALU_Op(3) <= '1'; + ALU_Op(2 downto 0) <= IR(7 downto 5); + end if; + end case; + --}}} + end case; + end process; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T65/T65_Pack.vhd b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T65/T65_Pack.vhd new file mode 100644 index 00000000..e025e1bf --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T65/T65_Pack.vhd @@ -0,0 +1,117 @@ +-- **** +-- T65(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 Bugfixes by ehenciak added +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- 65xx compatible microprocessor core +-- +-- Version : 0246 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t65/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T65_Pack is + + constant Flag_C : integer := 0; + constant Flag_Z : integer := 1; + constant Flag_I : integer := 2; + constant Flag_D : integer := 3; + constant Flag_B : integer := 4; + constant Flag_1 : integer := 5; + constant Flag_V : integer := 6; + constant Flag_N : integer := 7; + + component T65_MCode + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816 + IR : in std_logic_vector(7 downto 0); + MCycle : in std_logic_vector(2 downto 0); + P : in std_logic_vector(7 downto 0); + LCycle : out std_logic_vector(2 downto 0); + ALU_Op : out std_logic_vector(3 downto 0); + Set_BusA_To : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P + Set_Addr_To : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA + Write_Data : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH + Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel + BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj + BreakAtNA : out std_logic; + ADAdd : out std_logic; + AddY : out std_logic; + PCAdd : out std_logic; + Inc_S : out std_logic; + Dec_S : out std_logic; + LDA : out std_logic; + LDP : out std_logic; + LDX : out std_logic; + LDY : out std_logic; + LDS : out std_logic; + LDDI : out std_logic; + LDALU : out std_logic; + LDAD : out std_logic; + LDBAL : out std_logic; + LDBAH : out std_logic; + SaveP : out std_logic; + Write : out std_logic + ); + end component; + + component T65_ALU + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816 + Op : in std_logic_vector(3 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + P_In : in std_logic_vector(7 downto 0); + P_Out : out std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T80/T80.vhd new file mode 100644 index 00000000..398fa0df --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T80/T80.vhd @@ -0,0 +1,1073 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 and Auto_Wait_t1 = '0' then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if T_Res = '1' then + Auto_Wait_t1 <= '0'; + else + Auto_Wait_t1 <= Auto_Wait or IORQ_i; + end if; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if (Auto_Wait = '1' and Auto_Wait_t2 = '0') nor + (IOWait = 1 and IORQ_i = '1' and Auto_Wait_t1 = '0') then + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T80/T80_ALU.vhd new file mode 100644 index 00000000..86fddce7 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T80/T80_ALU.vhd @@ -0,0 +1,351 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + OverFlow_v <= Carry_v xor Carry7_v; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T80/T80_MCode.vhd new file mode 100644 index 00000000..4cc30f35 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T80/T80_MCode.vhd @@ -0,0 +1,1934 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; +-- constant aNone : std_logic_vector(2 downto 0) := "000"; +-- constant aXY : std_logic_vector(2 downto 0) := "001"; +-- constant aIOA : std_logic_vector(2 downto 0) := "010"; +-- constant aSP : std_logic_vector(2 downto 0) := "011"; +-- constant aBC : std_logic_vector(2 downto 0) := "100"; +-- constant aDE : std_logic_vector(2 downto 0) := "101"; +-- constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0010"; + else + IncDec_16 <= "1010"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0010"; + else + IncDec_16 <= "1010"; + end if; + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T80/T80_Pack.vhd new file mode 100644 index 00000000..ac7d34da --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T80/T80_Pack.vhd @@ -0,0 +1,208 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T80/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T80/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T80/T80s.vhd b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T80/T80s.vhd new file mode 100644 index 00000000..5b612110 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T80/T80s.vhd @@ -0,0 +1,190 @@ +-- +-- Z80 compatible microprocessor core, synchronous top level +-- Different timing than the original z80 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed read with wait +-- +-- 0211 : Fixed interrupt cycle +-- +-- 0235 : Updated for T80 interface change +-- +-- 0236 : Added T2Write generic +-- +-- 0237 : Fixed T2Write with wait state +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80s is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2 + IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80s; + +architecture rtl of T80s is + + signal CEN : std_logic; + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + CEN <= '1'; + + u0 : T80 + generic map( + Mode => Mode, + IOWait => IOWait) + port map( + CEN => CEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if T2Write = 0 then + if TState = "010" and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + else + if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end process; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/YM2149_linmix_sep.vhd b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/YM2149_linmix_sep.vhd new file mode 100644 index 00000000..6ed2498a --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/YM2149_linmix_sep.vhd @@ -0,0 +1,574 @@ +-- changes for seperate audio outputs and enable now enables cpu access as well +-- +-- A simulation model of YM2149 (AY-3-8910 with bells on) + +-- Copyright (c) MikeJ - Jan 2005 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- +-- Clues from MAME sound driver and Kazuhiro TSUJIKAWA +-- +-- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V) +-- vol 15 .. 0 +-- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132 +-- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order +-- to produced all the required values. +-- (The first part of the curve is a bit steeper and the last bit is more linear than expected) +-- +-- NOTE, this component uses LINEAR mixing of the three analogue channels, and is only +-- accurate for designs where the outputs are buffered and not simply wired together. +-- The ouput level is more complex in that case and requires a larger table. + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity YM2149 is + port ( + -- data bus + I_DA : in std_logic_vector(7 downto 0); + O_DA : out std_logic_vector(7 downto 0); + O_DA_OE_L : out std_logic; + -- control + I_A9_L : in std_logic; + I_A8 : in std_logic; + I_BDIR : in std_logic; + I_BC2 : in std_logic; + I_BC1 : in std_logic; + I_SEL_L : in std_logic; + + O_AUDIO : out std_logic_vector(7 downto 0); + O_CHAN : out std_logic_vector(1 downto 0); + -- port a + I_IOA : in std_logic_vector(7 downto 0); + O_IOA : out std_logic_vector(7 downto 0); + O_IOA_OE_L : out std_logic; + -- port b + I_IOB : in std_logic_vector(7 downto 0); + O_IOB : out std_logic_vector(7 downto 0); + O_IOB_OE_L : out std_logic; + + ENA : in std_logic; -- clock enable for higher speed operation + RESET_L : in std_logic; + CLK : in std_logic -- note 6 Mhz + ); +end; + +architecture RTL of YM2149 is + type array_16x8 is array (0 to 15) of std_logic_vector( 7 downto 0); + type array_3x12 is array (1 to 3) of std_logic_vector(11 downto 0); + + signal cnt_div : std_logic_vector(3 downto 0) := (others => '0'); + signal cnt_div_t1 : std_logic_vector(3 downto 0); + signal noise_div : std_logic := '0'; + signal ena_div : std_logic; + signal ena_div_noise : std_logic; + signal poly17 : std_logic_vector(16 downto 0) := (others => '0'); + + -- registers + signal addr : std_logic_vector(7 downto 0); + signal busctrl_addr : std_logic; + signal busctrl_we : std_logic; + signal busctrl_re : std_logic; + + signal reg : array_16x8; + signal env_reset : std_logic; + signal ioa_inreg : std_logic_vector(7 downto 0); + signal iob_inreg : std_logic_vector(7 downto 0); + + signal noise_gen_cnt : std_logic_vector(4 downto 0); + signal noise_gen_op : std_logic; + signal tone_gen_cnt : array_3x12 := (others => (others => '0')); + signal tone_gen_op : std_logic_vector(3 downto 1) := "000"; + + signal env_gen_cnt : std_logic_vector(15 downto 0); + signal env_ena : std_logic; + signal env_hold : std_logic; + signal env_inc : std_logic; + signal env_vol : std_logic_vector(4 downto 0); + + signal tone_ena_l : std_logic; + signal tone_src : std_logic; + signal noise_ena_l : std_logic; + signal chan_vol : std_logic_vector(4 downto 0); + + signal dac_amp : std_logic_vector(7 downto 0); +begin + -- cpu i/f + p_busdecode : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8) + variable cs : std_logic; + variable sel : std_logic_vector(2 downto 0); + begin + -- BDIR BC2 BC1 MODE + -- 0 0 0 inactive + -- 0 0 1 address + -- 0 1 0 inactive + -- 0 1 1 read + -- 1 0 0 address + -- 1 0 1 inactive + -- 1 1 0 write + -- 1 1 1 read + busctrl_addr <= '0'; + busctrl_we <= '0'; + busctrl_re <= '0'; + + cs := '0'; + if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then + cs := '1'; + end if; + + sel := (I_BDIR & I_BC2 & I_BC1); + case sel is + when "000" => null; + when "001" => busctrl_addr <= '1'; + when "010" => null; + when "011" => busctrl_re <= cs; + when "100" => busctrl_addr <= '1'; + when "101" => null; + when "110" => busctrl_we <= cs; + when "111" => busctrl_addr <= '1'; + when others => null; + end case; + end process; + + p_oe : process(busctrl_re) + begin + -- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns + O_DA_OE_L <= not (busctrl_re); + end process; + + -- + -- CLOCKED + -- + p_waddr : process(RESET_L, CLK) + begin + -- looks like registers are latches in real chip, but the address is caught at the end of the address state. + if (RESET_L = '0') then + addr <= (others => '0'); + elsif rising_edge(CLK) then + if (ENA = '1') then + if (busctrl_addr = '1') then + addr <= I_DA; + end if; + end if; + end if; + end process; + + p_wdata : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + reg <= (others => (others => '0')); + env_reset <= '1'; + elsif rising_edge(CLK) then + if (ENA = '1') then + env_reset <= '0'; + if (busctrl_we = '1') then + case addr(3 downto 0) is + when x"0" => reg(0) <= I_DA; + when x"1" => reg(1) <= I_DA; + when x"2" => reg(2) <= I_DA; + when x"3" => reg(3) <= I_DA; + when x"4" => reg(4) <= I_DA; + when x"5" => reg(5) <= I_DA; + when x"6" => reg(6) <= I_DA; + when x"7" => reg(7) <= I_DA; + when x"8" => reg(8) <= I_DA; + when x"9" => reg(9) <= I_DA; + when x"A" => reg(10) <= I_DA; + when x"B" => reg(11) <= I_DA; + when x"C" => reg(12) <= I_DA; + when x"D" => reg(13) <= I_DA; env_reset <= '1'; + when x"E" => reg(14) <= I_DA; + when x"F" => reg(15) <= I_DA; + when others => null; + end case; + end if; + end if; + end if; + end process; + + p_rdata : process(busctrl_re, addr, reg, ioa_inreg, iob_inreg) + begin + O_DA <= (others => '0'); -- 'X' + if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator + case addr(3 downto 0) is + when x"0" => O_DA <= reg(0) ; + when x"1" => O_DA <= "0000" & reg(1)(3 downto 0) ; + when x"2" => O_DA <= reg(2) ; + when x"3" => O_DA <= "0000" & reg(3)(3 downto 0) ; + when x"4" => O_DA <= reg(4) ; + when x"5" => O_DA <= "0000" & reg(5)(3 downto 0) ; + when x"6" => O_DA <= "000" & reg(6)(4 downto 0) ; + when x"7" => O_DA <= reg(7) ; + when x"8" => O_DA <= "000" & reg(8)(4 downto 0) ; + when x"9" => O_DA <= "000" & reg(9)(4 downto 0) ; + when x"A" => O_DA <= "000" & reg(10)(4 downto 0) ; + when x"B" => O_DA <= reg(11); + when x"C" => O_DA <= reg(12); + when x"D" => O_DA <= "0000" & reg(13)(3 downto 0); + when x"E" => if (reg(7)(6) = '0') then -- input + O_DA <= ioa_inreg; + else + O_DA <= reg(14); -- read output reg + end if; + when x"F" => if (Reg(7)(7) = '0') then + O_DA <= iob_inreg; + else + O_DA <= reg(15); + end if; + when others => null; + end case; + end if; + end process; + -- + p_divider : process + begin + wait until rising_edge(CLK); + -- / 8 when SEL is high and /16 when SEL is low + if (ENA = '1') then + ena_div <= '0'; + ena_div_noise <= '0'; + if (cnt_div = "0000") then + cnt_div <= (not I_SEL_L) & "111"; + ena_div <= '1'; + + noise_div <= not noise_div; + if (noise_div = '1') then + ena_div_noise <= '1'; + end if; + else + cnt_div <= cnt_div - "1"; + end if; + end if; + end process; + + p_noise_gen : process + variable noise_gen_comp : std_logic_vector(4 downto 0); + variable poly17_zero : std_logic; + begin + wait until rising_edge(CLK); + if (reg(6)(4 downto 0) = "00000") then + noise_gen_comp := "00000"; + else + noise_gen_comp := (reg(6)(4 downto 0) - "1"); + end if; + + poly17_zero := '0'; + if (poly17 = "00000000000000000") then poly17_zero := '1'; end if; + + if (ENA = '1') then + if (ena_div_noise = '1') then -- divider ena + + if (noise_gen_cnt >= noise_gen_comp) then + noise_gen_cnt <= "00000"; + poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1); + else + noise_gen_cnt <= (noise_gen_cnt + "1"); + end if; + end if; + end if; + end process; + noise_gen_op <= poly17(0); + + p_tone_gens : process + variable tone_gen_freq : array_3x12; + variable tone_gen_comp : array_3x12; + begin + wait until rising_edge(CLK); + -- looks like real chips count up - we need to get the Exact behaviour .. + tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0); + tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2); + tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4); + -- period 0 = period 1 + for i in 1 to 3 loop + if (tone_gen_freq(i) = x"000") then + tone_gen_comp(i) := x"000"; + else + tone_gen_comp(i) := (tone_gen_freq(i) - "1"); + end if; + end loop; + + if (ENA = '1') then + for i in 1 to 3 loop + if (ena_div = '1') then -- divider ena + + if (tone_gen_cnt(i) >= tone_gen_comp(i)) then + tone_gen_cnt(i) <= x"000"; + tone_gen_op(i) <= not tone_gen_op(i); + else + tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1"); + end if; + end if; + end loop; + end if; + end process; + + p_envelope_freq : process + variable env_gen_freq : std_logic_vector(15 downto 0); + variable env_gen_comp : std_logic_vector(15 downto 0); + begin + wait until rising_edge(CLK); + env_gen_freq := reg(12) & reg(11); + -- envelope freqs 1 and 0 are the same. + if (env_gen_freq = x"0000") then + env_gen_comp := x"0000"; + else + env_gen_comp := (env_gen_freq - "1"); + end if; + + if (ENA = '1') then + env_ena <= '0'; + if (ena_div = '1') then -- divider ena + if (env_gen_cnt >= env_gen_comp) then + env_gen_cnt <= x"0000"; + env_ena <= '1'; + else + env_gen_cnt <= (env_gen_cnt + "1"); + end if; + end if; + end if; + end process; + + p_envelope_shape : process(env_reset, reg, CLK) + variable is_bot : boolean; + variable is_bot_p1 : boolean; + variable is_top_m1 : boolean; + variable is_top : boolean; + begin + -- envelope shapes + -- C AtAlH + -- 0 0 x x \___ + -- + -- 0 1 x x /___ + -- + -- 1 0 0 0 \\\\ + -- + -- 1 0 0 1 \___ + -- + -- 1 0 1 0 \/\/ + -- ___ + -- 1 0 1 1 \ + -- + -- 1 1 0 0 //// + -- ___ + -- 1 1 0 1 / + -- + -- 1 1 1 0 /\/\ + -- + -- 1 1 1 1 /___ + if (env_reset = '1') then + -- load initial state + if (reg(13)(2) = '0') then -- attack + env_vol <= "11111"; + env_inc <= '0'; -- -1 + else + env_vol <= "00000"; + env_inc <= '1'; -- +1 + end if; + env_hold <= '0'; + + elsif rising_edge(CLK) then + is_bot := (env_vol = "00000"); + is_bot_p1 := (env_vol = "00001"); + is_top_m1 := (env_vol = "11110"); + is_top := (env_vol = "11111"); + + if (ENA = '1') then + if (env_ena = '1') then + if (env_hold = '0') then + if (env_inc = '1') then + env_vol <= (env_vol + "00001"); + else + env_vol <= (env_vol + "11111"); + end if; + end if; + + -- envelope shape control. + if (reg(13)(3) = '0') then + if (env_inc = '0') then -- down + if is_bot_p1 then env_hold <= '1'; end if; + else + if is_top then env_hold <= '1'; end if; + end if; + else + if (reg(13)(0) = '1') then -- hold = 1 + if (env_inc = '0') then -- down + if (reg(13)(1) = '1') then -- alt + if is_bot then env_hold <= '1'; end if; + else + if is_bot_p1 then env_hold <= '1'; end if; + end if; + else + if (reg(13)(1) = '1') then -- alt + if is_top then env_hold <= '1'; end if; + else + if is_top_m1 then env_hold <= '1'; end if; + end if; + end if; + + elsif (reg(13)(1) = '1') then -- alternate + if (env_inc = '0') then -- down + if is_bot_p1 then env_hold <= '1'; end if; + if is_bot then env_hold <= '0'; env_inc <= '1'; end if; + else + if is_top_m1 then env_hold <= '1'; end if; + if is_top then env_hold <= '0'; env_inc <= '0'; end if; + end if; + end if; + + end if; + end if; + end if; + end if; + end process; + + p_chan_mixer : process(cnt_div, reg, tone_gen_op) + begin + tone_ena_l <= '1'; tone_src <= '1'; + noise_ena_l <= '1'; chan_vol <= "00000"; + case cnt_div(1 downto 0) is + when "00" => + tone_ena_l <= reg(7)(0); tone_src <= tone_gen_op(1); chan_vol <= reg(8)(4 downto 0); + noise_ena_l <= reg(7)(3); + when "01" => + tone_ena_l <= reg(7)(1); tone_src <= tone_gen_op(2); chan_vol <= reg(9)(4 downto 0); + noise_ena_l <= reg(7)(4); + when "10" => + tone_ena_l <= reg(7)(2); tone_src <= tone_gen_op(3); chan_vol <= reg(10)(4 downto 0); + noise_ena_l <= reg(7)(5); + when "11" => null; -- tone gen outputs become valid on this clock + when others => null; + end case; + end process; + + p_op_mixer : process + variable chan_mixed : std_logic; + variable chan_amp : std_logic_vector(4 downto 0); + begin + wait until rising_edge(CLK); + if (ENA = '1') then + + chan_mixed := (tone_ena_l or tone_src) and (noise_ena_l or noise_gen_op); + + chan_amp := (others => '0'); + if (chan_mixed = '1') then + if (chan_vol(4) = '0') then + if (chan_vol(3 downto 0) = "0000") then -- nothing is easy ! make sure quiet is quiet + chan_amp := "00000"; + else + chan_amp := chan_vol(3 downto 0) & '1'; -- make sure level 31 (env) = level 15 (tone) + end if; + else + chan_amp := env_vol(4 downto 0); + end if; + end if; + + dac_amp <= x"00"; + case chan_amp is + when "11111" => dac_amp <= x"FF"; + when "11110" => dac_amp <= x"D9"; + when "11101" => dac_amp <= x"BA"; + when "11100" => dac_amp <= x"9F"; + when "11011" => dac_amp <= x"88"; + when "11010" => dac_amp <= x"74"; + when "11001" => dac_amp <= x"63"; + when "11000" => dac_amp <= x"54"; + when "10111" => dac_amp <= x"48"; + when "10110" => dac_amp <= x"3D"; + when "10101" => dac_amp <= x"34"; + when "10100" => dac_amp <= x"2C"; + when "10011" => dac_amp <= x"25"; + when "10010" => dac_amp <= x"1F"; + when "10001" => dac_amp <= x"1A"; + when "10000" => dac_amp <= x"16"; + when "01111" => dac_amp <= x"13"; + when "01110" => dac_amp <= x"10"; + when "01101" => dac_amp <= x"0D"; + when "01100" => dac_amp <= x"0B"; + when "01011" => dac_amp <= x"09"; + when "01010" => dac_amp <= x"08"; + when "01001" => dac_amp <= x"07"; + when "01000" => dac_amp <= x"06"; + when "00111" => dac_amp <= x"05"; + when "00110" => dac_amp <= x"04"; + when "00101" => dac_amp <= x"03"; + when "00100" => dac_amp <= x"03"; + when "00011" => dac_amp <= x"02"; + when "00010" => dac_amp <= x"02"; + when "00001" => dac_amp <= x"01"; + when "00000" => dac_amp <= x"00"; + when others => null; + end case; + + cnt_div_t1 <= cnt_div; + end if; + end process; + + p_audio_output : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + O_AUDIO <= (others => '0'); + O_CHAN <= (others => '0'); + elsif rising_edge(CLK) then + + if (ENA = '1') then + O_AUDIO <= dac_amp(7 downto 0); + O_CHAN <= cnt_div_t1(1 downto 0); + end if; + end if; + end process; + + p_io_ports : process(reg) + begin + O_IOA <= reg(14); + O_IOA_OE_L <= not reg(7)(6); + O_IOB <= reg(15); + O_IOB_OE_L <= not reg(7)(7); + end process; + + p_io_ports_inreg : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then -- resync + ioa_inreg <= I_IOA; + iob_inreg <= I_IOB; + end if; + end process; +end architecture RTL; diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/build_id.tcl b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/dpram.vhd b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..cda0f3cd --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/dpram.vhd @@ -0,0 +1,123 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY dpram IS + GENERIC + ( + init_file : string := ""; + numwords_a : natural := 0; -- not used any more + widthad_a : natural; + width_a : natural := 8; + outdata_reg_a : string := "UNREGISTERED"; + outdata_reg_b : string := "UNREGISTERED" + ); + PORT + ( + address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + clock_a : IN STD_LOGIC ; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + wren_a : IN STD_LOGIC := '1'; + wren_b : IN STD_LOGIC := '1'; + q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); +END dpram; + + +ARCHITECTURE SYN OF dpram IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + + COMPONENT altsyncram + GENERIC ( + address_reg_b : STRING; + clock_enable_input_a : STRING; + clock_enable_input_b : STRING; + clock_enable_output_a : STRING; + clock_enable_output_b : STRING; + indata_reg_b : STRING; + init_file : STRING; + intended_device_family : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + numwords_b : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_aclr_b : STRING; + outdata_reg_a : STRING; + outdata_reg_b : STRING; + power_up_uninitialized : STRING; + widthad_a : NATURAL; + widthad_b : NATURAL; + width_a : NATURAL; + width_b : NATURAL; + width_byteena_a : NATURAL; + width_byteena_b : NATURAL; + wrcontrol_wraddress_reg_b : STRING + ); + PORT ( + wren_a : IN STD_LOGIC ; + clock0 : IN STD_LOGIC ; + wren_b : IN STD_LOGIC ; + clock1 : IN STD_LOGIC ; + address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q_a <= sub_wire0(width_a-1 DOWNTO 0); + q_b <= sub_wire1(width_a-1 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + address_reg_b => "CLOCK1", + clock_enable_input_a => "BYPASS", + clock_enable_input_b => "BYPASS", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", + init_file => init_file, + intended_device_family => "Cyclone III", + lpm_type => "altsyncram", + numwords_a => 2**widthad_a, + numwords_b => 2**widthad_a, + operation_mode => "BIDIR_DUAL_PORT", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => outdata_reg_a, + outdata_reg_b => outdata_reg_b, + power_up_uninitialized => "FALSE", + widthad_a => widthad_a, + widthad_b => widthad_a, + width_a => width_a, + width_b => width_a, + width_byteena_a => 1, + width_byteena_b => 1, + wrcontrol_wraddress_reg_b => "CLOCK1" + ) + PORT MAP ( + wren_a => wren_a, + clock0 => clock_a, + wren_b => wren_b, + clock1 => clock_b, + address_a => address_a, + address_b => address_b, + data_a => data_a, + data_b => data_b, + q_a => sub_wire0, + q_b => sub_wire1 + ); + +END SYN; diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/gen_ram.vhd b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/gen_ram.vhd new file mode 100644 index 00000000..f1a95608 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/gen_ram.vhd @@ -0,0 +1,84 @@ +-- ----------------------------------------------------------------------- +-- +-- Syntiac's generic VHDL support files. +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- +-- Modified April 2016 by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +-- Remove address register when writing +-- +-- ----------------------------------------------------------------------- +-- +-- gen_rwram.vhd +-- +-- ----------------------------------------------------------------------- +-- +-- generic ram. +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +entity gen_ram is + generic ( + dWidth : integer := 8; + aWidth : integer := 10 + ); + port ( + clk : in std_logic; + we : in std_logic; + addr : in std_logic_vector((aWidth-1) downto 0); + d : in std_logic_vector((dWidth-1) downto 0); + q : out std_logic_vector((dWidth-1) downto 0) + ); +end entity; + +-- ----------------------------------------------------------------------- + +architecture rtl of gen_ram is + subtype addressRange is integer range 0 to ((2**aWidth)-1); + type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0); + signal ram: ramDef; + + signal rAddrReg : std_logic_vector((aWidth-1) downto 0); + signal qReg : std_logic_vector((dWidth-1) downto 0); +begin +-- ----------------------------------------------------------------------- +-- Signals to entity interface +-- ----------------------------------------------------------------------- +-- q <= qReg; + +-- ----------------------------------------------------------------------- +-- Memory write +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if we = '1' then + ram(to_integer(unsigned(addr))) <= d; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Memory read +-- ----------------------------------------------------------------------- +process(clk) + begin + if rising_edge(clk) then +-- qReg <= ram(to_integer(unsigned(rAddrReg))); +-- rAddrReg <= addr; +---- qReg <= ram(to_integer(unsigned(addr))); + q <= ram(to_integer(unsigned(addr))); + end if; + end process; +--q <= ram(to_integer(unsigned(addr))); +end architecture; + diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/loc_hvgen.v b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/loc_hvgen.v new file mode 100644 index 00000000..348647b8 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/loc_hvgen.v @@ -0,0 +1,36 @@ +module loc_hvgen +( + output [8:0] HPOS, + output [8:0] VPOS, + input PCLK, + output reg HBLK = 1, + output reg VBLK = 1, + output reg HSYN = 1, + output reg VSYN = 1 +); + +reg [8:0] hcnt = 0; +reg [8:0] vcnt = 0; + +assign HPOS = hcnt; +assign VPOS = vcnt; + +always @(posedge PCLK) begin + case (hcnt) + 287: begin HBLK <= 1; HSYN <= 0; hcnt <= hcnt+1; end + 311: begin HSYN <= 1; hcnt <= hcnt+1; end + 383: begin + HBLK <= 0; HSYN <= 1; hcnt <= 0; + case (vcnt) + 223: begin VBLK <= 1; vcnt <= vcnt+1; end + 226: begin VSYN <= 0; vcnt <= vcnt+1; end + 233: begin VSYN <= 1; vcnt <= vcnt+1; end + 242: begin VBLK <= 0; vcnt <= 0; end + default: vcnt <= vcnt+1; + endcase + end + default: hcnt <= hcnt+1; + endcase +end + +endmodule \ No newline at end of file diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/loc_sound.vhd b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/loc_sound.vhd new file mode 100644 index 00000000..bdcf3db4 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/loc_sound.vhd @@ -0,0 +1,425 @@ +--------------------------------------------------------------------------------- +-- burnin rubber sound by Dar (darfpga@aol.fr) (05/12/2017) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- +-- gen_ram.vhd & io_ps2_keyboard +-------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +--------------------------------------------------------------------------------- +-- T65(b) core.Ver 301 by MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +--------------------------------------------------------------------------------- +-- YM2149 (AY-3-8910) +-- Copyright (c) MikeJ - Jan 2005 +--------------------------------------------------------------------------------- +-- Use burnin_rubber_de10_lite.sdc to compile (Timequest constraints) +-- /!\ +-- Don't forget to set device configuration mode with memory initialization +-- (Assignments/Device/Pin options/Configuration mode) +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity loc_sound is +port +( + clock_12 : in std_logic; + reset : in std_logic; + + sound_req : in std_logic; + sound_code_in : in std_logic_vector(7 downto 0); + sound_timing : in std_logic; + + audio_out : out std_logic_vector(10 downto 0); + + dbg_cpu_addr: out std_logic_vector(15 downto 0) + ); +end loc_sound; + +architecture syn of loc_sound is + + -- clocks, reset + signal clock_12n : std_logic; + signal clock_div1 : std_logic_vector(8 downto 0) := (others =>'0'); + signal clock_div2 : std_logic_vector(4 downto 0) := (others =>'0'); + signal clock_500K : std_logic; + signal ayx_clock : std_logic; + signal reset_n : std_logic; + + -- cpu signals + signal cpu_addr : std_logic_vector(23 downto 0); + signal cpu_di : std_logic_vector( 7 downto 0); + signal cpu_di_dec : std_logic_vector( 7 downto 0); + signal cpu_do : std_logic_vector( 7 downto 0); + signal cpu_rw_n : std_logic; + signal cpu_nmi_n : std_logic; + signal cpu_irq_n : std_logic; + signal cpu_sync : std_logic; + + -- program rom signals + signal prog_rom_cs : std_logic; + signal prog_rom_do : std_logic_vector(7 downto 0); + + -- working ram signals + signal wram_cs : std_logic; + signal wram_we : std_logic; + signal wram_do : std_logic_vector(7 downto 0); + + -- sound req management + signal nmi_reg : std_logic; + signal nmi_reg_cs : std_logic; + signal nmi_reg_we : std_logic; + signal sound_code : std_logic_vector(7 downto 0); + signal sound_code_cs : std_logic; + + -- ay-3-8910 signal + signal ay1_bc1 : std_logic; + signal ay1_bdir : std_logic; + signal ay1_audio_chan : std_logic_vector(1 downto 0); + signal ay1_audio_muxed: std_logic_vector(7 downto 0); + signal ay1_chan_a: std_logic_vector(7 downto 0); + signal ay1_chan_b: std_logic_vector(7 downto 0); + signal ay1_chan_c: std_logic_vector(7 downto 0); + + signal ay2_bc1 : std_logic; + signal ay2_bdir : std_logic; + signal ay2_audio_chan : std_logic_vector(1 downto 0); + signal ay2_audio_muxed: std_logic_vector(7 downto 0); + signal ay2_chan_a: std_logic_vector(7 downto 0); + signal ay2_chan_b: std_logic_vector(7 downto 0); + signal ay2_chan_c: std_logic_vector(7 downto 0); + + -- digital filtering AY2 channel A + signal uin : integer range -256 to 255; + signal u3 : integer range -32768 to 32767; + signal u4 : integer range -32768 to 32767; + signal du3 : integer range -32768*4096 to 32767*4096; + signal du4 : integer range -32768*4096 to 32767*4096; + signal uout : integer range -32768 to 32767; + signal uout_lim : integer range -128 to 127; + +begin + +process (clock_12, cpu_sync) +begin + if rising_edge(clock_12) then + if cpu_sync = '1' then + dbg_cpu_addr <= cpu_addr(15 downto 0); + end if; + end if; +end process; + +reset_n <= not reset; +clock_12n <= not clock_12; + +process (clock_12, reset) + begin + if reset='1' then + clock_div1 <= (others => '0'); + clock_div2 <= (others => '0'); + else + if rising_edge(clock_12) then + if clock_div1 = "111111111" then -- divide by 512 (23.437kHz) + clock_div1 <= "000000000"; + else + clock_div1 <= clock_div1 + '1'; + end if; + if clock_div2 = "10111" then -- divide by 24 + clock_div2 <= "00000"; + else + clock_div2 <= clock_div2 + '1'; + end if; + end if; + end if; +end process; + +clock_500K <= clock_div2(4); --12MHz/24 = 500kHz +ayx_clock <= clock_div1(2); --12MHz/8 = 1.5MHz + +--static ADDRESS_MAP_START( audio_map, AS_PROGRAM, 8, btime_state ) +-- AM_RANGE(0x0000, 0x03ff) AM_MIRROR(0x1c00) AM_RAM AM_SHARE("audio_rambase") +-- AM_RANGE(0x2000, 0x3fff) AM_DEVWRITE("ay1", ay8910_device, data_w) +-- AM_RANGE(0x4000, 0x5fff) AM_DEVWRITE("ay1", ay8910_device, address_w) +-- AM_RANGE(0x6000, 0x7fff) AM_DEVWRITE("ay2", ay8910_device, data_w) +-- AM_RANGE(0x8000, 0x9fff) AM_DEVWRITE("ay2", ay8910_device, address_w) +-- AM_RANGE(0xa000, 0xbfff) AM_READ(audio_command_r) +-- AM_RANGE(0xc000, 0xdfff) AM_WRITE(audio_nmi_enable_w) +-- AM_RANGE(0xe000, 0xefff) AM_MIRROR(0x1000) AM_ROM +--ADDRESS_MAP_END + +-- chip select +wram_cs <= '1' when cpu_addr(15 downto 13) = "000" else '0'; -- working ram 0000-07ff .. 1fff +ay1_bc1 <= '1' when cpu_addr(15 downto 13) = "010" else '0'; +ay1_bdir <= '1' when cpu_addr(15 downto 13) = "001" or ay1_bc1 = '1' else '0'; +ay2_bc1 <= '1' when cpu_addr(15 downto 13) = "100" else '0'; +ay2_bdir <= '1' when cpu_addr(15 downto 13) = "011" or ay2_bc1 = '1' else '0'; +sound_code_cs <= '1' when cpu_addr(15 downto 13) = "101" else '0'; +nmi_reg_cs <= '1' when cpu_addr(15 downto 13) = "110" else '0'; +prog_rom_cs <= '1' when cpu_addr(15 downto 13) = "111" else '0'; + +-- write enable +wram_we <= '1' when wram_cs = '1' and cpu_rw_n = '0' else '0'; +nmi_reg_we <= '1' when nmi_reg_cs = '1' and cpu_rw_n = '0' else '0'; + +-- cpu di mux +cpu_di <= wram_do when wram_cs = '1' else + prog_rom_do when prog_rom_cs = '1' else + sound_code when sound_code_cs = '1' else + X"FF"; + +-- regsiter sound code and irq management +process (clock_12) +begin + if rising_edge(clock_12) then + if sound_req = '1' then + sound_code <= sound_code_in; + cpu_irq_n <= '0'; + end if; + if sound_code_cs = '1' then + cpu_irq_n <= '1'; + end if; + end if; +end process; + +-- nmi autorisation management +process (reset, clock_12) +begin + if reset = '1' then + nmi_reg <= '0'; + else + if rising_edge(clock_12) then + if nmi_reg_we = '1' then + nmi_reg <= cpu_do(0); + end if; + end if; + end if; +end process; + +-- nmi +cpu_nmi_n <= '0' when nmi_reg = '1' and sound_timing = '1' else '1'; + +-- demux AY chips output +process (ayx_clock) +begin + if rising_edge(ayx_clock) then + if ay1_audio_chan = "00" then ay1_chan_a <= ay1_audio_muxed; end if; + if ay1_audio_chan = "01" then ay1_chan_b <= ay1_audio_muxed; end if; + if ay1_audio_chan = "10" then ay1_chan_c <= ay1_audio_muxed; end if; + if ay2_audio_chan = "00" then ay2_chan_a <= ay2_audio_muxed; end if; + if ay2_audio_chan = "01" then ay2_chan_b <= ay2_audio_muxed; end if; + if ay2_audio_chan = "10" then ay2_chan_c <= ay2_audio_muxed; end if; + end if; +end process; + +-- AOP Rauch passe bande filter +-- +-- ----------o------------ +-- u4^ | | | +-- | --- C4 | | R5 | +-- | --- | | | +-- | | C3 | | +-- --| R1 |----o----||---o------|\ | +-- ^ | ------> u3 | \__o--- +-- | | | / ^ +-- |uin | | R2 --|/ | +-- | | | | | uout +-- | | | | +-- ------------o--------------o---------- +-- +-- +-- i1 = (sin+u3)/R1 +-- i2 = -u3/R2 +-- i3 = (u4-u3)/R5 +-- i4 = i2-i1-i3 +-- +-- u3(t+dt) = u3(t) + i3(t)*dt/C3; +-- u4(t+dt) = u4(t) + i4(t)*dt/C4; + +-- uout = u4-u3 + +-- R1 = 5000; +-- R2 = 10000; +-- C3 = 0.068e-6; +-- C4 = 0.068e-6; +-- R5 = 47000; +-- +-- dt = 1/f_ech = 1/23437 +-- dt/C3 = dt/C4 = 627 +-- +-- (i3(t)*dt/C3)*8192 = du3*8192 = ((u4-u3)/47000*627)*8192 +-- = (u4-u3)*109 +-- +-- (i4(t)*dt/C4)*8192 = du4*8192 = (-u3/10000 -(uin+u3)/5000 -(u4-u3)/47000)*627*8192 +-- = -u3(514+1027-109) - uin*1027 - u4*109 +-- = -(u4*109 + u3*1432 + uin*1027) +-- + +-- down sample to 23.437kHz and filter AY2 channel A +uin <= to_integer(unsigned(ay2_chan_a)); + +process (clock_12) +begin + if rising_edge(clock_12) then + + if clock_div1 = "000000000" then + du3 <= u4*109 - u3*109; + du4 <= u4*109 + u3*1432 + uin*1027*16; -- add gain(16) to uin + end if; + + if clock_div1 = "000000001" then + u3 <= u3 + du3/8192; + u4 <= u4 - du4/8192; + end if; + + if clock_div1 = "000000010" then + uout <= (u4 - u3) / 8; -- adjust output gain + end if; + + -- limit signed dynamique before return to unsigned + if clock_div1 = "000000011" then + if uout > 127 then + uout_lim <= 127; + elsif uout < -127 then + uout_lim <= -127; + else + uout_lim <= uout; + end if; + end if; + + if clock_div1 = "000000100" then + + audio_out <= ("000"&ay1_chan_a(7 downto 0)) + + ("000"&ay1_chan_b(7 downto 0)) + + ("000"&ay1_chan_c(7 downto 0)) + + ("000"&std_logic_vector(to_unsigned(uout_lim+128,8)))+ + ("000"&ay2_chan_b(7 downto 0)) + + ("000"&ay2_chan_c(7 downto 0)); + end if; + + end if; +end process; + +--------------------------- +-- components +--------------------------- + +cpu_inst : entity work.T65 +port map +( + Mode => "00", -- 6502 + Res_n => reset_n, + Enable => '1', + Clk => clock_500K, + Rdy => '1', + Abort_n => '1', + IRQ_n => cpu_irq_n, + NMI_n => cpu_nmi_n, + SO_n => '1',--cpu_so_n, + R_W_n => cpu_rw_n, + Sync => cpu_sync, -- open + EF => open, + MF => open, + XF => open, + ML_n => open, + VP_n => open, + VDA => open, + VPA => open, + A => cpu_addr, + DI => cpu_di, + DO => cpu_do +); + +-- working ram +wram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 11) +port map( + clk => clock_12n, + we => wram_we, + addr => cpu_addr(10 downto 0), + d => cpu_do, + q => wram_do +); + +-- program rom +program_rom: entity work.loc_snd_rom +port map( + clk => clock_12n, + addr => cpu_addr(11 downto 0), + data => prog_rom_do +); + +-- AY-3-8910 #1 +ay_3_8910_1 : entity work.YM2149 +port map( + -- data bus + I_DA => cpu_do, -- in std_logic_vector(7 downto 0); + O_DA => open, -- out std_logic_vector(7 downto 0); + O_DA_OE_L => open, -- out std_logic; + -- control + I_A9_L => '0', -- in std_logic; + I_A8 => '1', -- in std_logic; + I_BDIR => ay1_bdir, -- in std_logic; + I_BC2 => '1', -- in std_logic; + I_BC1 => ay1_bc1, -- in std_logic; + I_SEL_L => '1', -- in std_logic; + + O_AUDIO => ay1_audio_muxed, -- out std_logic_vector(7 downto 0); + O_CHAN => ay1_audio_chan, -- out std_logic_vector(1 downto 0); + + -- port a + I_IOA => X"00", -- in std_logic_vector(7 downto 0); + O_IOA => open, -- out std_logic_vector(7 downto 0); + O_IOA_OE_L => open, -- out std_logic; + -- port b + I_IOB => X"00", -- in std_logic_vector(7 downto 0); + O_IOB => open, -- out std_logic_vector(7 downto 0); + O_IOB_OE_L => open, -- out std_logic; + + ENA => '1', -- in std_logic; -- clock enable for higher speed operation + RESET_L => reset_n, -- in std_logic; + CLK => ayx_clock -- in std_logic -- note 6 Mhz +); + +-- AY-3-8910 #2 +ay_3_8910_2 : entity work.YM2149 +port map( + -- data bus + I_DA => cpu_do, -- in std_logic_vector(7 downto 0); + O_DA => open, -- out std_logic_vector(7 downto 0); + O_DA_OE_L => open, -- out std_logic; + -- control + I_A9_L => '0', -- in std_logic; + I_A8 => '1', -- in std_logic; + I_BDIR => ay2_bdir, -- in std_logic; + I_BC2 => '1', -- in std_logic; + I_BC1 => ay2_bc1, -- in std_logic; + I_SEL_L => '1', -- in std_logic; + + O_AUDIO => ay2_audio_muxed, -- out std_logic_vector(7 downto 0); + O_CHAN => ay2_audio_chan, -- out std_logic_vector(1 downto 0); + + -- port a + I_IOA => (others => '0'), -- in std_logic_vector(7 downto 0); + O_IOA => open, -- out std_logic_vector(7 downto 0); + O_IOA_OE_L => open, -- out std_logic; + -- port b + I_IOB => (others => '0'), -- in std_logic_vector(7 downto 0); + O_IOB => open, -- out std_logic_vector(7 downto 0); + O_IOB_OE_L => open, -- out std_logic; + + ENA => '1', --cpu_ena, -- in std_logic; -- clock enable for higher speed operation + RESET_L => reset_n, -- in std_logic; + CLK => ayx_clock -- in std_logic -- note 6 Mhz +); + + +end SYN; diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/loc_sprite.v b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/loc_sprite.v new file mode 100644 index 00000000..3a880175 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/loc_sprite.v @@ -0,0 +1,154 @@ + +module loc_sprite +( + input VCLKx4, + input HBLK, + + input [8:0] HPOS, + input [8:0] VPOS, + + output reg [10:0] SPRAADRS, + input [15:0] SPRADATA, + + output [3:0] ARAMADRS, + input [7:0] ARAMDATA, + + output [12:0] SPCHRADR, + input [7:0] SPCHRDAT, + + output [7:0] DROMAD, + input [7:0] DROMDT, + + output reg [8:0] SPCOL +); + +reg [1:0] clkcnt; +always @( posedge VCLKx4 ) clkcnt<=clkcnt+1; +wire VCLKx2 = clkcnt[0]; +wire VCLK = clkcnt[1]; + +wire SIDE = VPOS[0]; + + +reg [19:0] SPATR0; +reg [36:0] SPATRS[0:31]; +reg [3:0] WWADR; +reg bHit; + +assign ARAMADRS = SPRAADRS[3:0]; + + +reg [7:0] WRADR; +reg [8:0] HPOSW; +reg [8:0] SPWCL; + +wire [36:0] SPA = SPATRS[{~SIDE,WRADR[7:4]}]; + +wire [3:0] SH = WRADR[3:0]+4'h4; +wire [3:0] SV = SPA[35:32]; + +wire [2:0] SPFY = { 3{SPA[1]} }; +wire [1:0] SPFX = { 1'b0, SPA[0] }; +wire [5:0] SPPL = SPA[29:24]; + +assign SPCHRADR = { SPA[7:2], ( SV[3] ^ SPA[1] ), ( SH[3:2] ^ SPFX ), ( SV[2:0] ^ SPFY ) };//Todo +wire [7:0] CHRO = SPCHRDAT; + + +wire [8:0] YM = ( SPRADATA[15:8] + 8'h10 ) + VPOS[7:0]; + +assign DROMAD = { 1'b0, (~SPA[19:17]), SPA[33:32], WRADR[3:2] }; + +always @ ( posedge VCLKx2 ) begin + + // in H-BLANK + if ( HBLK ) begin + + // Sprite V-hit check & list-up + if ( SPRAADRS < 10'h20 ) begin + if ( SPRAADRS[0] ) begin + if ( bHit ) begin + SPATRS[{SIDE,WWADR}] <= { 1'b1, SPATR0[3:0], SPRADATA, SPATR0[19:4] }; + WWADR <= WWADR+1; + end + end + else begin + if ( YM[7:4] == 4'b1111 ) begin + bHit <= 1; + SPATR0 <= { SPRADATA, YM[3:0] }; + end + else bHit <= 0; + end + SPRAADRS <= ( SPRAADRS == 10'h1F ) ? 10'h34 : (SPRAADRS+1); + end + // Rader-dot V-hit check & list-up + else begin + if ( SPRAADRS < 10'h40 ) begin + if ( YM[7:2] == 6'b111111 ) begin + SPATRS[{SIDE,WWADR}] <= { 1'b0, 2'b00, YM[1:0], 8'h0, ARAMDATA, SPRADATA }; + WWADR <= WWADR+1; + end + SPRAADRS <= SPRAADRS+1; + end + else SPATRS[{SIDE,WWADR}] <= 0; + end + + if ( SPA ) begin + // Rend Sprite + if ( SPA[36] ) begin + HPOSW <= ( WRADR[3:0] ) ? (HPOSW+1) : { SPA[31], SPA[23:16] }; + case ( SH[1:0] ^ {2{SPFX[0]}} ) + 2'b00: SPWCL <= { 1'b0, SPPL, CHRO[7], CHRO[3] }; + 2'b01: SPWCL <= { 1'b0, SPPL, CHRO[6], CHRO[2] }; + 2'b10: SPWCL <= { 1'b0, SPPL, CHRO[5], CHRO[1] }; + 2'b11: SPWCL <= { 1'b0, SPPL, CHRO[4], CHRO[0] }; + endcase + WRADR <= WRADR+1; + end + // Rend Rader-dot + else begin + HPOSW <= ( WRADR[3:0] ) ? (HPOSW+1) : ({ (~SPA[16]), SPA[7:0] }); + SPWCL <= ( DROMDT[1:0] != 2'b11 ) ? { 1'b1, 6'b000100, DROMDT[1:0] } : 0; + WRADR <= WRADR+4; + end + end + else SPWCL <= 0; + + end + + // in H-DISP + else begin + SPRAADRS <= 10'h14; + WWADR <= 0; + WRADR <= 0; + SPWCL <= 0; + end + +end + + +reg [9:0] radr0=0,radr1=1; +wire [8:0] SPCOLi; +dpram #( + .widthad_a(10), + .width_a(9)) +linebuffer( + .address_a({SIDE,HPOS}), + .address_b({~SIDE,HPOSW}), + .clock_a(VCLKx2), + .clock_b(VCLKx2), + .data_a(9'h0), + .data_b(SPWCL), + .wren_a(radr0==radr1), + .wren_b((SPWCL[0]|SPWCL[1])), + .q_a(SPCOLi), + .q_b() + ); + +always @(posedge VCLK) radr0 <= {SIDE,HPOS}; +always @(negedge VCLK) begin + if (radr0!=radr1) SPCOL <= SPCOLi; + radr1 <= radr0; +end + +endmodule diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/loc_top.v b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/loc_top.v new file mode 100644 index 00000000..6dffa672 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/loc_top.v @@ -0,0 +1,195 @@ +/************************************************************** + FPGA Locomotion (Main part) +***************************************************************/ +module loc_top +( + input RESET, // RESET + input CLK24M, // Clock 24.576MHz + output hsync, + output vsync, + output hblank, + output vblank, + output [2:0] r, + output [2:0] g, + output [1:0] b, + output [10:0] SND, // Sound (unsigned PCM) + input [7:0] DSW1, // DipSW + input [7:0] DSW2, // DipSW + input [7:0] CTR1, // Controler (Negative logic) + input [7:0] CTR2 +); + + +//-------------------------------------------------- +// Clock Generators +//-------------------------------------------------- +reg [2:0] _CCLK; +always @( posedge CLK24M ) _CCLK <= _CCLK+1; + +wire CLK = CLK24M; // 24MHz +wire CCLKx4 = _CCLK[0]; // CPU CLOCKx4 : 12.0MHz +wire CCLK = _CCLK[2]; // CPU CLOCK : 3.0MHz + + +//-------------------------------------------------- +// CPU +//-------------------------------------------------- +// memory access signals +wire rd, wr, me, ie, rf, m1; +wire [15:0] ad; +wire [7:0] odt, viddata; + +wire mx = rf & (~me); +wire mr = mx & (~rd); +wire mw = mx & (~wr); + +// interrupt signal/vector generator & other latches +reg inte = 1'b0; +reg intl = 1'b0; +reg [7:0] intv = 8'h0; + + +reg out1r = 1'b0; +reg out2r = 1'b0; +reg out3r = 1'b0; +reg sonr = 1'b0;//sound On + +wire vblk = (VP==224)&(HP<=8); + +wire lat_Wce = ( ad[15:4] == 12'hA18 ) & mw; + +wire sndw = ( lat_Wce & ( ad[3:0] == 4'h0 ) ); +wire iewr = ( lat_Wce & ( ad[3:0] == 4'h1 ) ); +wire mute = ( lat_Wce & ( ad[3:0] == 4'h1 ) );//mute +wire flip = ( lat_Wce & ( ad[3:0] == 4'h3 ) );//flip +wire out1w = ( lat_Wce & ( ad[3:0] == 4'h4 ) ); +//wire out2w = ( lat_Wce & ( ad[3:0] == 4'h5 ) );//NOP +wire out3w = ( lat_Wce & ( ad[3:0] == 4'h6 ) ); +//wire starw = ( lat_Wce & ( ad[3:0] == 4'h7 ) );//not used +wire iowr = ( (~wr) & (~ie) & m1 ); + + +always @( posedge CCLK ) begin + if ( iowr ) intv <= odt; + if ( vblk ) intl <= 1'b1; + if ( iewr ) begin + inte <= odt[0]; + intl <= 1'b0; + end + if ( sndw ) sonr <= odt[0]; + if ( out1w ) out1r <= odt[0]; +// if ( out2w ) out2r <= odt[0]; + if ( out3w ) out3r <= odt[0]; +end + +wire irq_n = ~( intl & inte ); + + +// address decoders +wire rom_Rce = ( ( ad[15] == 1'b0 ) & mr ); // $0000-$7FFF(R) +wire ram_Rce = ( ( ad[15:11] == 5'b1001_1 ) & mr ); // $9800-$9FFF(R) +wire ram_Wce = ( ( ad[15:11] == 5'b1001_1 ) & mw ); // $9800-$9FFF(W) +wire inp_Rce = ( ( ad[15:12] == 4'b1010 ) & mr ); // $A000-$AFFF(R) +wire snd_Wce = ( ( ad[15:8] == 8'b1010_0001 ) & mw ); // $A100-$A1FF(W) +wire vid_Rce; + + +wire [7:0] romdata; +loc_prg_rom loc_prg_rom ( + .clk(CCLK), + .addr(ad[14:0]), + .data(romdata) + ); + +// Work RAM (2KB) +wire [7:0] ramdata; +GSPRAM #(11,8) workram( + .CL(CCLK), + .AD(ad[10:0]), + .WE(ram_Wce), + .DI(odt), + .DO(ramdata) + ); + + +// Controler/DipSW input +wire [7:0] in0data = CTR1; +wire [7:0] in1data = CTR2; +wire [7:0] in2data = DSW1; +wire [7:0] in3data = DSW2; +wire [7:0] inpdata = (ad[8:7] == 2'b11) ? in3data : (ad[8:7] == 2'b10) ? in2data : (ad[8:7] == 2'b01) ? in1data : in0data; +// databus selector +wire [7:0] romd = rom_Rce ? romdata : 8'h00; +wire [7:0] ramd = ram_Rce ? ramdata : 8'h00; +wire [7:0] vidd = vid_Rce ? viddata : 8'h00; +wire [7:0] inpd = inp_Rce ? inpdata : 8'h00; +wire [7:0] irqv = ( (~m1) & (~ie) ) ? intv : 8'h00; + +wire [7:0] idt = romd | ramd | irqv | vidd | inpd; + + +T80s z80( + .RESET_n(~RESET), + .CLK_n(CCLK), + .WAIT_n(1'b1), + .INT_n(1'b1), + .NMI_n(irq_n), + .BUSRQ_n(1'b1), + .DI(idt), + .M1_n(m1), + .MREQ_n(me), + .IORQ_n(ie), + .RD_n(rd), + .WR_n(wr), + .RFSH_n(rf), + .HALT_n(), + .BUSAK_n(), + .A(ad), + .DO(odt) + ); + +//-------------------------------------------------- +// VIDEO +//-------------------------------------------------- +wire [8:0] HP; +wire [8:0] VP; +wire PCLK; + +loc_video video( + .VCLKx4(CLK), + .HPOS(HP+3), + .VPOS(VP+1), + .PCLK(PCLK), + .POUT({b,g,r}), + .CPUCLK(CCLK), + .CPUADDR(ad), + .CPUDI(odt), + .CPUDO(viddata), + .CPUME(mx), + .CPUWE(mw), + .CPUDT(vid_Rce) + ); + +loc_hvgen hvgen( + .HPOS(HP), + .VPOS(VP), + .PCLK(PCLK), + .HBLK(hblank), + .VBLK(vblank), + .HSYN(hsync), + .VSYN(vsync) + ); + +//-------------------------------------------------- +// SOUND //ToDo +//-------------------------------------------------- +loc_sound sound( + .clock_12(CCLKx4), + .reset(RESET), + .sound_req(sonr), + .sound_code_in(odt), + .sound_timing(snd_Wce), + .audio_out(SND) + ); + +endmodule diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/loc_video.v b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/loc_video.v new file mode 100644 index 00000000..807719dd --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/loc_video.v @@ -0,0 +1,194 @@ +module loc_video +( + input VCLKx4, // 24.976MHz + + input [8:0] HPOS, + input [8:0] VPOS, + output PCLK, + output reg [7:0] POUT, + + input CPUCLK, + input [15:0] CPUADDR, + input [7:0] CPUDI, + output [7:0] CPUDO, + input CPUME, + input CPUWE, + output CPUDT +); + +//----------------------------------------- +// Clock generators +//----------------------------------------- +reg VCLKx2; +always @( posedge VCLKx4 ) begin + VCLKx2 <= ~VCLKx2; +end + +reg VCLK; +always @( posedge VCLKx2 ) begin + VCLK <= ~VCLK; +end + +//----------------------------------------- +// BG scroll registers +//----------------------------------------- +reg [7:0] BGHSCR; +reg [7:0] BGVSCR; + +always @ ( posedge CPUCLK ) begin + if ( ( CPUADDR == 16'hA130 ) & CPUME & CPUWE ) begin + BGHSCR <= CPUDI-3; + end + if ( ( CPUADDR == 16'hA140 ) & CPUME & CPUWE ) begin + BGVSCR <= CPUDI; + end +end + + +//----------------------------------------- +// HV +//----------------------------------------- +wire [8:0] BGHPOS = HPOS + { 1'b0, BGHSCR }; +wire [8:0] BGVPOS = VPOS + { 1'b0, BGVSCR }; + +wire oHB = ( HPOS > 288 ) ? 1 : 0; +wire oVB = ( VPOS > 224 ) ? 1 : 0; + + +//---------------------------------------- +// VideoRAM Scanner +//---------------------------------------- +wire BF = ( HPOS >= 224 ); +wire [8:0] HP = BF ? HPOS : BGHPOS; +wire [8:0] VP = ( BF ? VPOS : BGVPOS ) + 9'h0F; + +wire [10:0] SPRAADRS; +wire [3:0] ARAMADRS; + +reg [10:0] VRAMADRS; +always @ ( HPOS ) begin + VRAMADRS <= oHB ? + SPRAADRS : + BF ? { 1'b0, VP[7:3], 2'b00, HP[5:3] } : { 1'b1, VP[7:3], HP[7:3] }; +end + +wire [7:0] CHRC; +wire [7:0] ATTR; +wire [7:0] ARDT; + +wire [7:0] V0DO, V1DO; + +wire CEV0 = ( ( CPUADDR[15:12] == 4'b1000 ) & (~CPUADDR[11]) ) & CPUME; +wire CEV1 = ( ( CPUADDR[15:12] == 4'b1000 ) & CPUADDR[11] ) & CPUME; +wire CEAT = ( CPUADDR[15:4] == 12'b1010_0000_0000 ) & CPUME; + +wire [7:0] DTV0 = CEV0 ? V0DO : 8'h00; +wire [7:0] DTV1 = CEV1 ? V1DO : 8'h00; + +assign CPUDO = DTV0 | DTV1; +assign CPUDT = ( ~CPUWE ) & ( CEV0 | CEV1 ); + +GDPRAM #(11,8) vram0( VCLKx4, VRAMADRS, CHRC, CPUCLK, CPUADDR[10:0], ( CPUWE & CEV0 ), CPUDI, V0DO ); + +GDPRAM #(11,8) vram1( VCLKx4, VRAMADRS, ATTR, CPUCLK, CPUADDR[10:0], ( CPUWE & CEV1 ), CPUDI, V1DO ); + +GDPRAM #(4,8) aram0( VCLKx4, ARAMADRS, ARDT, CPUCLK, CPUADDR[3:0], ( CPUWE & CEAT ), CPUDI ); + +wire BGF = ATTR[5]; + + +//---------------------------------------- +// BG/Sprite chip data reader +//---------------------------------------- +wire BGFX = ATTR[6]; +wire [2:0] BGFY = { ATTR[7], ATTR[7], ATTR[7] }; + +wire [12:0] SPCHRADR;//Todo +wire [12:0] CHRA = oHB ? SPCHRADR : { CHRC, ( HP[2] ^ BGFX ), ( VP[2:0] ^ BGFY ) }; + +wire [7:0] CHRO; +loc_chr_rom chrrom( + .clk(VCLKx4), + .addr(CHRA), + .data(CHRO) +); + +//---------------------------------------- +// Rader-dot chip ROM +//---------------------------------------- +wire [7:0] DROMAD; +wire [7:0] DROMDT; +loc_dot_rom dotrom( + .clk(VCLKx4), + .addr(DROMAD), + .data(DROMDT) + ); + +//---------------------------------------- +// BG/FG scanline generator +//---------------------------------------- +wire [5:0] BGPL = ATTR[5:0]; +reg [7:0] BGCOL; + +always @ ( posedge VCLK ) begin + case ( HP[1:0]^{2{BGFX}} ) + 2'b00: BGCOL <= { BGPL, CHRO[4], CHRO[0] }; + 2'b01: BGCOL <= { BGPL, CHRO[5], CHRO[1] }; + 2'b10: BGCOL <= { BGPL, CHRO[6], CHRO[2] }; + 2'b11: BGCOL <= { BGPL, CHRO[7], CHRO[3] }; + endcase +end + + +//---------------------------------------- +// Sprite Engine +//---------------------------------------- +wire [8:0] SPCOL; +loc_sprite speng( + .VCLKx4(VCLKx4), + .HBLK(oHB), + .HPOS(HPOS), + .VPOS(VPOS), + .SPRAADRS(SPRAADRS), + .SPRADATA({ ATTR, CHRC }), + .ARAMADRS(ARAMADRS), + .ARAMDATA(ARDT), + .SPCHRADR(SPCHRADR), + .SPCHRDAT(CHRO), + .DROMAD(DROMAD), + .DROMDT(DROMDT), + .SPCOL(SPCOL) + ); + + +//---------------------------------------- +// Color mixer +//---------------------------------------- +wire bBGOPAQUE = ( ( BF | BGF ) & (~SPCOL[8]) ); +wire bSPTRANSP = ( SPCOL[1:0] == 2'b00 ); + +wire [7:0] OUTCOL = ( bBGOPAQUE | bSPTRANSP ) ? BGCOL : SPCOL[7:0]; +wire [3:0] CLUT; +loc_col_rom colrom( + .clk(~VCLKx4), + .addr(OUTCOL), + .data(CLUT) + ); + +wire [4:0] PALA = SPCOL[8] ? SPCOL[4:0] : { 1'b0, CLUT }; +wire [7:0] PALO; + +loc_pal_rom palrom( + .clk(VCLKx4), + .addr(PALA), + .data(PALO) + ); + +//---------------------------------------- +// Color output +//---------------------------------------- +always @ ( posedge PCLK ) POUT <= (oHB|oVB) ? 8'h0 : PALO; +assign PCLK = VCLK; + + +endmodule \ No newline at end of file diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/pll.qip b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/pll.qip new file mode 100644 index 00000000..afd958be --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/pll.v b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/pll.v new file mode 100644 index 00000000..70025276 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/pll.v @@ -0,0 +1,309 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.4 Build 182 03/12/2014 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2014 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + inclk0, + c0, + locked); + + input inclk0; + output c0; + output locked; + + wire [4:0] sub_wire0; + wire sub_wire2; + wire [0:0] sub_wire5 = 1'h0; + wire [0:0] sub_wire1 = sub_wire0[0:0]; + wire c0 = sub_wire1; + wire locked = sub_wire2; + wire sub_wire3 = inclk0; + wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; + + altpll altpll_component ( + .inclk (sub_wire4), + .clk (sub_wire0), + .locked (sub_wire2), + .activeclock (), + .areset (1'b0), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 78, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 71, + altpll_component.clk0_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_UNUSED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "78" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.576923" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "71" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.57600000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "78" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "71" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/rams.v b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/rams.v new file mode 100644 index 00000000..4d579578 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/rams.v @@ -0,0 +1,64 @@ + + + +module GSPRAM #(parameter AW,parameter DW) +( + input CL, + input [(AW-1):0] AD, + input WE, + input [(DW-1):0] DI, + output reg [(DW-1):0] DO +); + +reg [(DW-1):0] core[0:((2**AW)-1)]; + +always @(posedge CL) begin + DO <= core[AD]; + if (WE) core[AD] <= DI; +end + +endmodule + + +module GDPRAM #(parameter AW,parameter DW) +( + input CL0, + input [(AW-1):0] AD0, + output reg [(DW-1):0] DO0, + + input CL1, + input [(AW-1):0] AD1, + input WE1, + input [(DW-1):0] DI1, + output reg [(DW-1):0] DO1 +); + +reg [(DW-1):0] core[0:((2**AW)-1)]; + +always @(posedge CL0) DO0 <= core[AD0]; +always @(posedge CL1) begin DO1 <= core[AD1]; if (WE1) core[AD1] <= DI1; end + +endmodule + +/* +module GLINEBUF #(parameter AW,parameter DW) +( + input CL0, + input [(AW-1):0] AD0, + input WE0, + output reg [(DW-1):0] DO0, + + input CL1, + input [(AW-1):0] AD1, + input WE1, + input [(DW-1):0] DI1 +); + +reg [(DW-1):0] core[0:((2**AW)-1)]; + +always @(posedge CL0) begin DO0 <= core[AD0]; if (WE0) core[AD0] <= 0; end +always @(posedge CL1) if (WE1) core[AD1] <= DI1; + +endmodule*/ + + diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/gutangtn.zip b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/gutangtn.zip new file mode 100644 index 00000000..2afbe5d9 Binary files /dev/null and b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/gutangtn.zip differ diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/loc_chr_rom.vhd b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/loc_chr_rom.vhd new file mode 100644 index 00000000..c2d9ac92 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/loc_chr_rom.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity loc_chr_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of loc_chr_rom is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"0E",X"01",X"01",X"01",X"0F",X"0F",X"0E",X"00",X"07",X"08",X"08",X"08",X"0F",X"0F",X"07", + X"00",X"00",X"00",X"0F",X"0F",X"0F",X"00",X"00",X"00",X"00",X"00",X"0F",X"0F",X"07",X"04",X"00", + X"00",X"01",X"09",X"0D",X"0F",X"07",X"03",X"01",X"00",X"07",X"0F",X"0F",X"08",X"08",X"08",X"06", + X"00",X"0E",X"0F",X"0F",X"01",X"01",X"01",X"06",X"00",X"06",X"0F",X"0F",X"09",X"08",X"08",X"04", + X"00",X"04",X"0F",X"0F",X"0F",X"04",X"04",X"0C",X"00",X"00",X"0F",X"0F",X"07",X"02",X"01",X"00", + X"00",X"0E",X"0F",X"0F",X"01",X"01",X"02",X"02",X"00",X"08",X"09",X"09",X"09",X"09",X"09",X"0F", + X"00",X"0E",X"01",X"01",X"01",X"0F",X"0F",X"0E",X"00",X"04",X"09",X"09",X"09",X"0F",X"0F",X"07", + X"00",X"00",X"00",X"08",X"0F",X"0F",X"03",X"01",X"00",X"0C",X"0E",X"0F",X"0B",X"08",X"08",X"08", + X"00",X"0E",X"0F",X"0D",X"09",X"01",X"01",X"0E",X"00",X"00",X"06",X"09",X"0B",X"0F",X"07",X"00", + X"00",X"0E",X"0F",X"0F",X"09",X"09",X"09",X"02",X"00",X"07",X"0F",X"0F",X"08",X"08",X"08",X"07", + X"0C",X"02",X"01",X"05",X"05",X"09",X"02",X"0C",X"03",X"04",X"08",X"0A",X"0A",X"09",X"04",X"03", + X"0F",X"01",X"01",X"01",X"01",X"01",X"01",X"0F",X"0F",X"08",X"08",X"08",X"08",X"08",X"08",X"0F", + X"00",X"00",X"00",X"0A",X"0A",X"00",X"00",X"00",X"00",X"00",X"00",X"07",X"07",X"00",X"00",X"00", + X"00",X"00",X"00",X"04",X"04",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"02",X"00",X"00",X"00", + X"00",X"00",X"06",X"06",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"08",X"0C",X"0E",X"0C",X"08",X"00",X"00",X"03",X"07",X"07",X"03",X"07",X"07",X"03", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"07",X"0F",X"0E",X"0A",X"02",X"0E",X"03",X"00",X"00",X"01",X"07",X"0F",X"03",X"00",X"00", + X"00",X"0E",X"01",X"01",X"01",X"0F",X"0F",X"0F",X"00",X"06",X"09",X"09",X"09",X"0F",X"0F",X"0F", + X"00",X"06",X"01",X"01",X"01",X"0F",X"0F",X"0E",X"00",X"04",X"08",X"08",X"08",X"0F",X"0F",X"07", + X"00",X"0C",X"02",X"01",X"01",X"0F",X"0F",X"0F",X"00",X"03",X"04",X"08",X"08",X"0F",X"0F",X"0F", + X"00",X"01",X"01",X"01",X"01",X"0F",X"0F",X"0F",X"00",X"09",X"09",X"09",X"09",X"0F",X"0F",X"0F", + X"00",X"00",X"00",X"00",X"00",X"0F",X"0F",X"0F",X"00",X"09",X"09",X"09",X"09",X"0F",X"0F",X"0F", + X"00",X"0E",X"01",X"01",X"01",X"0F",X"0F",X"0E",X"00",X"05",X"09",X"09",X"08",X"0F",X"0F",X"07", + X"00",X"0F",X"00",X"00",X"00",X"0F",X"0F",X"0F",X"00",X"0F",X"01",X"01",X"01",X"0F",X"0F",X"0F", + X"00",X"00",X"00",X"0F",X"0F",X"0F",X"00",X"00",X"00",X"00",X"00",X"0F",X"0F",X"0F",X"00",X"00", + X"00",X"0E",X"0F",X"0F",X"01",X"01",X"01",X"02",X"00",X"0F",X"0F",X"0F",X"00",X"00",X"00",X"00", + X"00",X"03",X"0C",X"00",X"00",X"0F",X"0F",X"0F",X"00",X"08",X"04",X"03",X"02",X"0F",X"0F",X"0F", + X"00",X"01",X"01",X"01",X"01",X"0F",X"0F",X"0F",X"00",X"00",X"00",X"00",X"00",X"0F",X"0F",X"0F", + X"00",X"0F",X"08",X"0C",X"0E",X"0C",X"08",X"0F",X"00",X"0F",X"07",X"03",X"01",X"03",X"07",X"0F", + X"00",X"0F",X"0F",X"0E",X"0C",X"08",X"00",X"0F",X"00",X"0F",X"00",X"01",X"03",X"07",X"0F",X"0F", + X"00",X"0E",X"01",X"01",X"01",X"0F",X"0F",X"0E",X"00",X"07",X"08",X"08",X"08",X"0F",X"0F",X"07", + X"00",X"08",X"04",X"04",X"04",X"0F",X"0F",X"0F",X"00",X"07",X"08",X"08",X"08",X"0F",X"0F",X"0F", + X"00",X"0F",X"03",X"0D",X"01",X"0F",X"0F",X"0E",X"00",X"07",X"08",X"08",X"08",X"0F",X"0F",X"07", + X"00",X"09",X"05",X"06",X"04",X"0F",X"0F",X"0F",X"00",X"07",X"08",X"08",X"08",X"0F",X"0F",X"0F", + X"00",X"06",X"0F",X"0F",X"0F",X"09",X"01",X"02",X"00",X"04",X"08",X"09",X"0F",X"0F",X"0F",X"06", + X"00",X"00",X"00",X"0F",X"0F",X"0F",X"00",X"00",X"00",X"08",X"08",X"0F",X"0F",X"0F",X"08",X"08", + X"00",X"0E",X"01",X"01",X"01",X"0F",X"0F",X"0E",X"00",X"0F",X"00",X"00",X"00",X"0F",X"0F",X"0F", + X"00",X"00",X"00",X"0C",X"0F",X"0E",X"08",X"00",X"00",X"0C",X"03",X"00",X"00",X"03",X"0F",X"0E", + X"00",X"0F",X"0E",X"0C",X"08",X"0C",X"0E",X"0F",X"00",X"0F",X"01",X"03",X"07",X"03",X"01",X"0F", + X"00",X"07",X"0E",X"0C",X"08",X"04",X"02",X"01",X"00",X"08",X"04",X"03",X"03",X"07",X"0E",X"0C", + X"00",X"00",X"00",X"00",X"08",X"0C",X"02",X"01",X"00",X"0C",X"02",X"01",X"03",X"07",X"0F",X"0E", + X"00",X"01",X"01",X"09",X"0F",X"0F",X"0F",X"03",X"00",X"08",X"0E",X"0F",X"0F",X"0B",X"08",X"08", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"03",X"03",X"03",X"03",X"00", + X"0C",X"06",X"02",X"02",X"02",X"02",X"06",X"0C",X"07",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"07", + X"08",X"08",X"08",X"08",X"08",X"08",X"08",X"08",X"01",X"07",X"03",X"03",X"03",X"03",X"03",X"03", + X"0C",X"0E",X"0E",X"0E",X"0C",X"08",X"00",X"0E",X"07",X"08",X"08",X"00",X"01",X"03",X"07",X"0F", + X"0C",X"0E",X"0E",X"0C",X"0E",X"0E",X"0E",X"0C",X"07",X"08",X"00",X"01",X"00",X"08",X"08",X"07", + X"0C",X"0C",X"0C",X"0C",X"0C",X"0E",X"0C",X"0C",X"00",X"01",X"03",X"05",X"09",X"0F",X"01",X"01", + X"0C",X"00",X"00",X"0C",X"0E",X"0E",X"0E",X"0C",X"0F",X"08",X"08",X"0F",X"00",X"00",X"0C",X"03", + X"0C",X"02",X"00",X"0C",X"02",X"02",X"02",X"0C",X"07",X"0E",X"0E",X"0F",X"0E",X"0E",X"0E",X"07", + X"0E",X"0E",X"0C",X"08",X"08",X"00",X"00",X"00",X"0F",X"00",X"01",X"01",X"03",X"03",X"07",X"0F", + X"08",X"04",X"04",X"08",X"0E",X"0E",X"06",X"0C",X"03",X"06",X"07",X"07",X"09",X"08",X"08",X"07", + X"0C",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0C",X"07",X"08",X"08",X"08",X"07",X"00",X"08",X"07", + X"08",X"0E",X"00",X"02",X"0A",X"0A",X"0E",X"00",X"00",X"01",X"00",X"02",X"02",X"02",X"03",X"00", + X"00",X"0C",X"02",X"02",X"0E",X"00",X"0E",X"04",X"00",X"00",X"01",X"01",X"01",X"00",X"01",X"00", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"74",X"BA",X"DD",X"EE",X"FF",X"33",X"CC",X"F3",X"BB",X"BB",X"D5",X"D5",X"E2",X"F1",X"F0",X"F0", + X"F0",X"F0",X"F8",X"74",X"BA",X"BA",X"DD",X"DD",X"FC",X"33",X"CC",X"FF",X"77",X"BB",X"D5",X"E2", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"34",X"1A",X"0D",X"0E",X"0F",X"03",X"0C",X"C3",X"0B",X"0B",X"85",X"85",X"C2",X"E1",X"F0",X"F0", + X"F0",X"F0",X"78",X"34",X"1A",X"1A",X"0D",X"0D",X"3C",X"03",X"0C",X"0F",X"07",X"0B",X"85",X"C2", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"00",X"D5",X"D5",X"D5",X"E2",X"E2",X"E2",X"F1",X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F8",X"F8",X"00",X"BA",X"BA",X"BA",X"DD",X"DD",X"EE",X"66", + X"66",X"77",X"BB",X"BB",X"D5",X"D5",X"D5",X"D5",X"F1",X"F1",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F8",X"74",X"74",X"74",X"BA",X"BA",X"BA",X"BA", + X"00",X"85",X"85",X"85",X"C2",X"C2",X"C2",X"E1",X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"78",X"78",X"00",X"1A",X"1A",X"1A",X"0D",X"0D",X"0E",X"06", + X"06",X"07",X"0B",X"0B",X"85",X"85",X"85",X"85",X"E1",X"E1",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"78",X"34",X"34",X"34",X"1A",X"1A",X"1A",X"1A", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"FE",X"11",X"F0",X"F0",X"F0",X"F0",X"F0",X"FF",X"00",X"FF", + X"E0",X"E0",X"E0",X"E0",X"E0",X"EE",X"00",X"EE",X"F0",X"F0",X"F0",X"FC",X"33",X"CC",X"FF",X"77", + X"EE",X"FF",X"33",X"CC",X"F3",X"F0",X"F0",X"F0",X"FF",X"00",X"FF",X"F0",X"F0",X"F0",X"F0",X"F0", + X"EE",X"00",X"EE",X"E0",X"E0",X"E0",X"E0",X"E0",X"88",X"F7",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"1E",X"01",X"F0",X"F0",X"F0",X"F0",X"F0",X"0F",X"00",X"0F", + X"E0",X"E0",X"E0",X"E0",X"E0",X"0E",X"00",X"0E",X"F0",X"F0",X"F0",X"3C",X"03",X"0C",X"0F",X"07", + X"0E",X"0F",X"03",X"0C",X"C3",X"F0",X"F0",X"F0",X"0F",X"00",X"0F",X"F0",X"F0",X"F0",X"F0",X"F0", + X"0E",X"00",X"0E",X"E0",X"E0",X"E0",X"E0",X"E0",X"08",X"87",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"DD",X"DD",X"BA",X"BA",X"74",X"F8",X"F0",X"F0",X"E2",X"D5",X"BB",X"77",X"FF",X"CC",X"33",X"FC", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F3",X"CC",X"33",X"FF",X"EE",X"DD",X"BA",X"74",X"F0",X"F0",X"F1",X"E2",X"D5",X"D5",X"BB",X"BB", + X"0D",X"0D",X"1A",X"1A",X"34",X"78",X"F0",X"F0",X"C2",X"85",X"0B",X"07",X"0F",X"0C",X"03",X"3C", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"C3",X"0C",X"03",X"0F",X"0E",X"0D",X"1A",X"34",X"F0",X"F0",X"E1",X"C2",X"85",X"85",X"0B",X"0B", + X"00",X"D5",X"D5",X"D5",X"BB",X"BB",X"77",X"66",X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F1",X"F1", + X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"00",X"BA",X"BA",X"BA",X"74",X"74",X"74",X"F8", + X"F1",X"E2",X"E2",X"E2",X"D5",X"D5",X"D5",X"D5",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F8",X"F8",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"66",X"EE",X"DD",X"DD",X"BA",X"BA",X"BA",X"BA", + X"00",X"85",X"85",X"85",X"0B",X"0B",X"07",X"06",X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"E1",X"E1", + X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"00",X"1A",X"1A",X"1A",X"34",X"34",X"34",X"78", + X"E1",X"C2",X"C2",X"C2",X"85",X"85",X"85",X"85",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"78",X"78",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"06",X"0E",X"0D",X"0D",X"1A",X"1A",X"1A",X"1A", + X"F0",X"F0",X"F0",X"F3",X"CC",X"33",X"FF",X"EE",X"F0",X"F0",X"F0",X"F0",X"F0",X"FF",X"00",X"FF", + X"E0",X"E0",X"E0",X"E0",X"E0",X"EE",X"00",X"EE",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F7",X"88", + X"11",X"FE",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"FF",X"00",X"FF",X"F0",X"F0",X"F0",X"F0",X"F0", + X"EE",X"00",X"EE",X"E0",X"E0",X"E0",X"E0",X"E0",X"77",X"FF",X"CC",X"33",X"FC",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"C3",X"0C",X"03",X"0F",X"0E",X"F0",X"F0",X"F0",X"F0",X"F0",X"0F",X"00",X"0F", + X"E0",X"E0",X"E0",X"E0",X"E0",X"0E",X"00",X"0E",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"87",X"08", + X"01",X"1E",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"0F",X"00",X"0F",X"F0",X"F0",X"F0",X"F0",X"F0", + X"0E",X"00",X"0E",X"E0",X"E0",X"E0",X"E0",X"E0",X"07",X"0F",X"0C",X"03",X"3C",X"F0",X"F0",X"F0", + X"D5",X"D5",X"D5",X"D5",X"D5",X"DD",X"00",X"DD",X"F0",X"F0",X"F0",X"F0",X"F0",X"FF",X"00",X"FF", + X"F0",X"F0",X"F0",X"F0",X"F0",X"FF",X"00",X"FF",X"BA",X"BA",X"BA",X"BA",X"BA",X"BB",X"00",X"BB", + X"DD",X"00",X"DD",X"D5",X"D5",X"D5",X"D5",X"D5",X"FF",X"00",X"FF",X"F0",X"F0",X"F0",X"F0",X"F0", + X"FF",X"00",X"FF",X"F0",X"F0",X"F0",X"F0",X"F0",X"BB",X"00",X"BB",X"BA",X"BA",X"BA",X"BA",X"BA", + X"85",X"85",X"85",X"85",X"85",X"8D",X"00",X"8D",X"F0",X"F0",X"F0",X"F0",X"F0",X"FF",X"00",X"FF", + X"F0",X"F0",X"F0",X"F0",X"F0",X"FF",X"00",X"FF",X"1A",X"1A",X"1A",X"1A",X"1A",X"1B",X"00",X"1B", + X"8D",X"00",X"8D",X"85",X"85",X"85",X"85",X"85",X"FF",X"00",X"FF",X"F0",X"F0",X"F0",X"F0",X"F0", + X"FF",X"00",X"FF",X"F0",X"F0",X"F0",X"F0",X"F0",X"1B",X"00",X"1B",X"1A",X"1A",X"1A",X"1A",X"1A", + X"D5",X"D5",X"D5",X"D5",X"D5",X"0D",X"00",X"0D",X"F0",X"F0",X"F0",X"F0",X"F0",X"0F",X"00",X"0F", + X"F0",X"F0",X"F0",X"F0",X"F0",X"0F",X"00",X"0F",X"BA",X"BA",X"BA",X"BA",X"BA",X"0B",X"00",X"0B", + X"0D",X"00",X"0D",X"D5",X"D5",X"D5",X"D5",X"D5",X"0F",X"00",X"0F",X"F0",X"F0",X"F0",X"F0",X"F0", + X"0F",X"00",X"0F",X"F0",X"F0",X"F0",X"F0",X"F0",X"0B",X"00",X"0B",X"BA",X"BA",X"BA",X"BA",X"BA", + X"85",X"85",X"85",X"85",X"85",X"0D",X"00",X"0D",X"F0",X"F0",X"F0",X"F0",X"F0",X"0F",X"00",X"0F", + X"F0",X"F0",X"F0",X"F0",X"F0",X"0F",X"00",X"0F",X"1A",X"1A",X"1A",X"1A",X"1A",X"0B",X"00",X"0B", + X"0D",X"00",X"0D",X"85",X"85",X"85",X"85",X"85",X"0F",X"00",X"0F",X"F0",X"F0",X"F0",X"F0",X"F0", + X"0F",X"00",X"0F",X"F0",X"F0",X"F0",X"F0",X"F0",X"0B",X"00",X"0B",X"1A",X"1A",X"1A",X"1A",X"1A", + X"F0",X"F0",X"F0",X"F0",X"F0",X"FF",X"00",X"FF",X"F0",X"F0",X"F0",X"F0",X"F0",X"FF",X"00",X"FF", + X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"00",X"BA",X"BA",X"BA",X"BA",X"BA",X"BA",X"BA", + X"FF",X"00",X"FF",X"F0",X"F0",X"F0",X"F0",X"F0",X"FF",X"00",X"FF",X"F0",X"F0",X"F0",X"F0",X"F0", + X"00",X"D5",X"D5",X"D5",X"D5",X"D5",X"D5",X"D5",X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"0F",X"00",X"0F",X"F0",X"F0",X"F0",X"F0",X"F0",X"0F",X"00",X"0F", + X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"00",X"1A",X"1A",X"1A",X"1A",X"1A",X"1A",X"1A", + X"0F",X"00",X"0F",X"F0",X"F0",X"F0",X"F0",X"F0",X"0F",X"00",X"0F",X"F0",X"F0",X"F0",X"F0",X"F0", + X"00",X"85",X"85",X"85",X"85",X"85",X"85",X"85",X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"95",X"4A",X"2D",X"1E",X"0F",X"C3",X"3C",X"8B",X"4B",X"4B",X"A5",X"A5",X"D6",X"A3",X"D5",X"A2", + X"10",X"BA",X"54",X"BA",X"54",X"1E",X"F0",X"1E",X"00",X"AA",X"55",X"2E",X"C3",X"3C",X"0F",X"87", + X"55",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"AA",X"D5",X"A2",X"D5",X"A2",X"D5",X"A2",X"D5",X"A2", + X"1E",X"F0",X"1E",X"BA",X"54",X"BA",X"54",X"BA",X"78",X"8F",X"55",X"AA",X"55",X"AA",X"55",X"AA", + X"55",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"AA",X"D5",X"A2",X"D5",X"A2",X"D5",X"A2",X"D5",X"A2", + X"54",X"BA",X"54",X"BA",X"54",X"1E",X"F0",X"1E",X"55",X"AA",X"55",X"AA",X"55",X"AA",X"07",X"78", + X"47",X"3C",X"C3",X"0F",X"1E",X"2D",X"5B",X"A6",X"D5",X"A2",X"C5",X"92",X"A5",X"A5",X"4B",X"4B", + X"1E",X"F0",X"1E",X"BA",X"54",X"BA",X"54",X"1C",X"87",X"0F",X"3C",X"C3",X"1D",X"AA",X"55",X"8B", + X"11",X"AA",X"55",X"8B",X"3C",X"C3",X"0F",X"1E",X"80",X"A2",X"D5",X"A2",X"D5",X"0F",X"F0",X"0F", + X"2D",X"2D",X"5A",X"5A",X"94",X"3A",X"54",X"BA",X"56",X"AD",X"4B",X"87",X"0F",X"3C",X"C3",X"2E", + X"E1",X"0E",X"55",X"AA",X"55",X"AA",X"55",X"AA",X"0F",X"F0",X"0F",X"A2",X"D5",X"A2",X"D5",X"A2", + X"54",X"BA",X"54",X"BA",X"54",X"BA",X"54",X"BA",X"55",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"AA", + X"55",X"AA",X"55",X"AA",X"55",X"AA",X"0F",X"E1",X"D5",X"A2",X"D5",X"A2",X"D5",X"0F",X"F0",X"0F", + X"54",X"BA",X"54",X"BA",X"54",X"BA",X"54",X"BA",X"55",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"AA", + X"1E",X"0F",X"C3",X"3C",X"47",X"AA",X"55",X"0C",X"0F",X"F0",X"0F",X"A2",X"D5",X"A2",X"D5",X"83", + X"54",X"BA",X"5C",X"B6",X"5A",X"5A",X"2D",X"2D",X"1D",X"C3",X"3C",X"0F",X"87",X"4B",X"25",X"9A", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"F0",X"AA",X"45",X"AB",X"45",X"AB",X"4C",X"2A",X"5A",X"4A",X"5B",X"4A",X"2D",X"2D",X"1E",X"96", + X"55",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"F0",X"55",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"F0", + X"95",X"4A",X"2D",X"1E",X"0F",X"C3",X"3C",X"C3",X"4B",X"4B",X"25",X"AD",X"56",X"AB",X"55",X"F0", + X"F0",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"AA",X"F0",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"AA", + X"C3",X"3C",X"C3",X"0F",X"1E",X"2D",X"5B",X"A6",X"F0",X"AA",X"45",X"9A",X"25",X"AD",X"4B",X"4B", + X"45",X"9A",X"56",X"9A",X"25",X"AD",X"25",X"A5",X"55",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"F0", + X"5D",X"2A",X"45",X"AB",X"45",X"AB",X"44",X"F0",X"96",X"1E",X"2D",X"2D",X"5B",X"4A",X"5B",X"5A", + X"F0",X"AD",X"25",X"AD",X"4B",X"4B",X"87",X"96",X"F0",X"22",X"55",X"22",X"55",X"22",X"45",X"AB", + X"F0",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"AA",X"F0",X"4A",X"5B",X"4A",X"95",X"A6",X"95",X"2A", + X"2D",X"2D",X"5B",X"4A",X"95",X"2A",X"55",X"F0",X"56",X"AD",X"4B",X"87",X"0F",X"3C",X"C3",X"3C", + X"55",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"F0",X"55",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"F0", + X"F0",X"AA",X"5D",X"A6",X"5B",X"4A",X"2D",X"2D",X"3C",X"C3",X"3C",X"0F",X"87",X"4B",X"25",X"9A", + X"F0",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"AA",X"F0",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"AA", + X"96",X"87",X"4B",X"4B",X"25",X"AD",X"25",X"A5",X"45",X"23",X"55",X"22",X"55",X"22",X"55",X"F0", + X"55",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"F0",X"5D",X"A6",X"95",X"A6",X"5B",X"4A",X"5B",X"5A", + X"C4",X"EA",X"FD",X"FE",X"FF",X"F3",X"FC",X"33",X"FB",X"FB",X"F5",X"F5",X"B2",X"91",X"80",X"80", + X"10",X"10",X"10",X"10",X"10",X"FE",X"F0",X"FE",X"00",X"00",X"00",X"CC",X"F3",X"FC",X"FF",X"F7", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80", + X"FE",X"F0",X"FE",X"10",X"10",X"10",X"10",X"10",X"F8",X"77",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80", + X"10",X"10",X"10",X"10",X"10",X"FE",X"F0",X"FE",X"00",X"00",X"00",X"00",X"00",X"00",X"77",X"F8", + X"33",X"FC",X"F3",X"FF",X"FE",X"FD",X"EA",X"C4",X"80",X"80",X"91",X"B2",X"F5",X"F5",X"FB",X"FB", + X"FE",X"F0",X"FE",X"10",X"10",X"10",X"10",X"DC",X"F7",X"FF",X"FC",X"F3",X"CC",X"00",X"00",X"33", + X"00",X"00",X"00",X"33",X"FC",X"F3",X"FF",X"FE",X"80",X"80",X"80",X"80",X"80",X"FF",X"F0",X"FF", + X"FD",X"FD",X"FA",X"FA",X"D4",X"98",X"10",X"10",X"32",X"75",X"FB",X"F7",X"FF",X"FC",X"F3",X"CC", + X"F1",X"EE",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"F0",X"FF",X"80",X"80",X"80",X"80",X"80", + X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"F1",X"80",X"80",X"80",X"80",X"80",X"FF",X"F0",X"FF", + X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80", + X"FE",X"FF",X"F3",X"FC",X"33",X"00",X"00",X"CC",X"FF",X"F0",X"FF",X"80",X"80",X"80",X"80",X"B3", + X"10",X"10",X"98",X"D4",X"FA",X"FA",X"FD",X"FD",X"CC",X"F3",X"FC",X"FF",X"F7",X"FB",X"75",X"32", + X"F0",X"75",X"75",X"75",X"32",X"32",X"32",X"11",X"F0",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"F0",X"00",X"11",X"11",X"11",X"11",X"88",X"88",X"F0",X"EA",X"EA",X"EA",X"FD",X"FD",X"FE",X"F6", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"F0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"F0", + X"C4",X"EA",X"FD",X"FE",X"FF",X"F3",X"FC",X"F3",X"FB",X"FB",X"75",X"75",X"32",X"11",X"00",X"F0", + X"F0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"F0",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"F3",X"FC",X"F3",X"FF",X"FE",X"FD",X"EA",X"C4",X"F0",X"00",X"11",X"32",X"75",X"75",X"FB",X"FB", + X"11",X"32",X"32",X"32",X"75",X"75",X"75",X"F5",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"F0", + X"88",X"88",X"11",X"11",X"11",X"11",X"00",X"F0",X"F6",X"FE",X"FD",X"FD",X"EA",X"EA",X"EA",X"FA", + X"F0",X"75",X"75",X"75",X"FB",X"FB",X"F7",X"F6",X"F0",X"00",X"00",X"00",X"00",X"00",X"11",X"11", + X"F0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"F0",X"EA",X"EA",X"EA",X"C4",X"C4",X"C4",X"88", + X"FD",X"FD",X"EA",X"EA",X"C4",X"88",X"00",X"F0",X"32",X"75",X"FB",X"F7",X"FF",X"FC",X"F3",X"FC", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"F0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"F0", + X"F0",X"00",X"88",X"C4",X"EA",X"EA",X"FD",X"FD",X"FC",X"F3",X"FC",X"FF",X"F7",X"FB",X"75",X"32", + X"F0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"F0",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"F6",X"F7",X"FB",X"FB",X"75",X"75",X"75",X"F5",X"11",X"11",X"00",X"00",X"00",X"00",X"00",X"F0", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"F0",X"88",X"C4",X"C4",X"C4",X"EA",X"EA",X"EA",X"FA", + X"81",X"40",X"20",X"10",X"00",X"C0",X"30",X"08",X"40",X"40",X"A0",X"A0",X"94",X"82",X"85",X"82", + X"14",X"1A",X"14",X"1A",X"14",X"10",X"F0",X"10",X"05",X"0A",X"05",X"02",X"C0",X"30",X"00",X"80", + X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"85",X"82",X"85",X"82",X"85",X"82",X"85",X"82", + X"10",X"F0",X"10",X"1A",X"14",X"1A",X"14",X"1A",X"70",X"08",X"05",X"0A",X"05",X"0A",X"05",X"0A", + X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"85",X"82",X"85",X"82",X"85",X"82",X"85",X"82", + X"14",X"1A",X"14",X"1A",X"14",X"10",X"F0",X"10",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"00",X"70", + X"04",X"30",X"C0",X"00",X"10",X"20",X"41",X"82",X"85",X"82",X"84",X"90",X"A0",X"A0",X"40",X"40", + X"10",X"F0",X"10",X"1A",X"14",X"1A",X"14",X"1A",X"80",X"00",X"30",X"C0",X"01",X"0A",X"05",X"0A", + X"05",X"0A",X"05",X"08",X"30",X"C0",X"00",X"10",X"85",X"82",X"85",X"82",X"85",X"00",X"F0",X"00", + X"20",X"20",X"50",X"50",X"90",X"12",X"14",X"1A",X"20",X"40",X"80",X"00",X"00",X"30",X"C0",X"02", + X"E0",X"00",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"00",X"F0",X"00",X"82",X"85",X"82",X"85",X"82", + X"14",X"1A",X"14",X"1A",X"14",X"1A",X"14",X"1A",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A", + X"05",X"0A",X"05",X"0A",X"05",X"0A",X"00",X"E0",X"85",X"82",X"85",X"82",X"85",X"00",X"F0",X"00", + X"14",X"1A",X"14",X"1A",X"14",X"1A",X"14",X"1A",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A", + X"10",X"00",X"C0",X"30",X"04",X"0A",X"05",X"0A",X"00",X"F0",X"00",X"82",X"85",X"82",X"85",X"82", + X"14",X"1A",X"14",X"92",X"50",X"50",X"20",X"20",X"01",X"C0",X"30",X"00",X"80",X"40",X"20",X"18", + X"F0",X"28",X"20",X"28",X"14",X"18",X"14",X"0A",X"F0",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A", + X"F0",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"02",X"F0",X"40",X"41",X"40",X"20",X"20",X"10",X"90", + X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"F0",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"F0", + X"81",X"40",X"20",X"10",X"00",X"C0",X"30",X"C0",X"40",X"40",X"20",X"28",X"14",X"0A",X"05",X"F0", + X"F0",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"F0",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A", + X"C0",X"30",X"C0",X"00",X"10",X"20",X"41",X"82",X"F0",X"0A",X"04",X"18",X"20",X"28",X"40",X"40", + X"04",X"18",X"14",X"18",X"20",X"28",X"20",X"A0",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"F0", + X"05",X"02",X"05",X"0A",X"05",X"0A",X"05",X"F0",X"90",X"10",X"20",X"20",X"41",X"40",X"41",X"50", + X"F0",X"28",X"20",X"28",X"40",X"40",X"80",X"90",X"F0",X"0A",X"05",X"0A",X"05",X"0A",X"04",X"0A", + X"F0",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"F0",X"40",X"41",X"40",X"81",X"82",X"81",X"02", + X"20",X"20",X"41",X"40",X"81",X"02",X"05",X"F0",X"14",X"28",X"40",X"80",X"00",X"30",X"C0",X"30", + X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"F0",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"F0", + X"F0",X"0A",X"05",X"82",X"41",X"40",X"20",X"20",X"30",X"C0",X"30",X"00",X"80",X"40",X"20",X"18", + X"F0",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"F0",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A", + X"90",X"80",X"40",X"40",X"20",X"28",X"20",X"A0",X"04",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"F0", + X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"F0",X"05",X"82",X"81",X"82",X"41",X"40",X"41",X"50", + X"84",X"A6",X"84",X"A6",X"84",X"A6",X"84",X"A6",X"4B",X"4B",X"4B",X"4B",X"4B",X"4B",X"4B",X"4B", + X"00",X"AA",X"0F",X"F0",X"0F",X"0F",X"F0",X"0F",X"00",X"AA",X"0F",X"F0",X"0F",X"0F",X"F0",X"0F", + X"81",X"82",X"81",X"82",X"81",X"82",X"81",X"82",X"40",X"40",X"40",X"40",X"40",X"40",X"40",X"40", + X"05",X"0A",X"00",X"F0",X"00",X"00",X"F0",X"00",X"05",X"0A",X"00",X"F0",X"00",X"00",X"F0",X"00", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A", + X"C4",X"C4",X"C4",X"C4",X"C4",X"C4",X"C4",X"C4",X"FB",X"FB",X"FB",X"FB",X"FB",X"FB",X"FB",X"FB", + X"00",X"00",X"FF",X"F0",X"FF",X"FF",X"F0",X"FF",X"00",X"00",X"FF",X"F0",X"FF",X"FF",X"F0",X"FF", + X"08",X"0C",X"86",X"C2",X"C2",X"86",X"0C",X"08",X"07",X"1E",X"4B",X"0F",X"0F",X"4B",X"1E",X"07", + X"0C",X"86",X"4B",X"69",X"69",X"4B",X"86",X"0C",X"03",X"07",X"2D",X"0F",X"0F",X"2D",X"07",X"03", + X"88",X"CC",X"AE",X"2E",X"2E",X"AE",X"CC",X"88",X"77",X"FF",X"9F",X"FF",X"FF",X"9F",X"FF",X"77", + X"CC",X"EE",X"DF",X"9F",X"9F",X"DF",X"EE",X"CC",X"33",X"77",X"CF",X"FF",X"FF",X"CF",X"77",X"33", + X"2D",X"2D",X"2D",X"2D",X"2D",X"2D",X"2D",X"2D",X"56",X"12",X"56",X"12",X"56",X"12",X"56",X"12", + X"0F",X"F0",X"0F",X"0F",X"F0",X"0F",X"55",X"00",X"0F",X"F0",X"0F",X"0F",X"F0",X"0F",X"55",X"00", + X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"14",X"18",X"14",X"18",X"14",X"18",X"14",X"18", + X"00",X"F0",X"00",X"00",X"F0",X"00",X"05",X"0A",X"00",X"F0",X"00",X"00",X"F0",X"00",X"05",X"0A", + X"F0",X"AD",X"25",X"AD",X"16",X"9A",X"56",X"AB",X"F0",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"AA", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FD",X"FD",X"FD",X"FD",X"FD",X"FD",X"FD",X"FD",X"32",X"32",X"32",X"32",X"32",X"32",X"32",X"32", + X"FF",X"F0",X"FF",X"FF",X"F0",X"FF",X"00",X"00",X"FF",X"F0",X"FF",X"FF",X"F0",X"FF",X"00",X"00", + X"EE",X"DF",X"9F",X"9F",X"DF",X"EE",X"CC",X"00",X"77",X"CF",X"FF",X"FF",X"CF",X"77",X"33",X"00", + X"86",X"4B",X"69",X"69",X"4B",X"86",X"0C",X"00",X"07",X"2D",X"0F",X"0F",X"2D",X"07",X"03",X"00", + X"CC",X"EE",X"DF",X"9F",X"9F",X"DF",X"EE",X"CC",X"33",X"77",X"CF",X"FF",X"FF",X"CF",X"77",X"33", + X"0C",X"86",X"4B",X"69",X"69",X"4B",X"86",X"0C",X"03",X"07",X"2D",X"0F",X"0F",X"2D",X"07",X"03", + X"F0",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"F0",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"F0",X"FE",X"FE",X"FE",X"FE",X"FE",X"FE",X"FE",X"F0",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FE",X"FE",X"FE",X"FE",X"FE",X"FE",X"FE",X"FE",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + X"55",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"AA", + X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"F0",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"F0", + X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"00",X"E0",X"E0",X"E0",X"E0",X"E0",X"E0",X"E0",X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"E0",X"E0",X"E0",X"E0",X"E0",X"E0",X"E0",X"E0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"0F",X"00",X"00",X"00",X"00",X"01",X"03",X"07",X"0F", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"08",X"0C",X"0E",X"0F",X"0C",X"0C",X"0C",X"0C", + X"0F",X"0F",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"07",X"03",X"01",X"00",X"00",X"00",X"00", + X"01",X"03",X"07",X"0F",X"03",X"03",X"03",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"DD",X"DD",X"99",X"99",X"55",X"DD",X"00",X"DD",X"E2",X"D5",X"BB",X"77",X"FF",X"CC",X"00",X"FF", + X"74",X"BA",X"DD",X"EE",X"FF",X"33",X"00",X"FF",X"BB",X"BB",X"99",X"99",X"AA",X"BB",X"00",X"BB", + X"DD",X"00",X"DD",X"55",X"99",X"99",X"DD",X"DD",X"FF",X"00",X"CC",X"FF",X"77",X"BB",X"D5",X"E2", + X"FF",X"00",X"33",X"FF",X"EE",X"DD",X"BA",X"74",X"BB",X"00",X"BB",X"AA",X"99",X"99",X"BB",X"BB", + X"F0",X"F1",X"F1",X"F3",X"F3",X"F3",X"F7",X"F7",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F1",X"F7",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"F0",X"F0",X"F0",X"F1",X"F1",X"F3",X"F7",X"FF", + X"F7",X"F7",X"F3",X"F3",X"F3",X"F1",X"F1",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"F7",X"F1",X"FF",X"F7",X"F3",X"F1",X"F1",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F7",X"FF",X"FF",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F3",X"F7", + X"F0",X"F0",X"F0",X"F7",X"FF",X"FF",X"FF",X"FF",X"F0",X"F0",X"F0",X"F0",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"F7",X"F0",X"F0",X"F0",X"F0",X"F0",X"F7",X"F3",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"FF",X"FF",X"FF",X"FF",X"F7",X"F0",X"F0",X"F0",X"FF",X"FF",X"FF",X"FF",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"0F",X"0D",X"0B",X"07",X"F0",X"F0",X"F0",X"F0",X"0F",X"0B",X"0D",X"0E", + X"E0",X"E0",X"E0",X"E0",X"0E",X"0C",X"0A",X"06",X"F0",X"F0",X"F0",X"F0",X"0F",X"0B",X"0D",X"0E", + X"07",X"0B",X"0D",X"0F",X"F0",X"F0",X"F0",X"F0",X"0E",X"0D",X"0B",X"0F",X"F0",X"F0",X"F0",X"F0", + X"06",X"0A",X"0C",X"0E",X"E0",X"E0",X"E0",X"E0",X"0E",X"0D",X"0B",X"0F",X"F0",X"F0",X"F0",X"F0", + X"00",X"0B",X"0D",X"0E",X"0E",X"0D",X"0B",X"0F",X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"00",X"0D",X"0B",X"07",X"07",X"0B",X"0D",X"0F", + X"0F",X"0B",X"0D",X"0E",X"0E",X"0D",X"0B",X"0F",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"0F",X"0D",X"0B",X"07",X"07",X"0B",X"0D",X"0F", + X"00",X"01",X"03",X"0E",X"0C",X"00",X"00",X"00",X"00",X"08",X"0C",X"07",X"03",X"00",X"00",X"00", + X"00",X"00",X"00",X"0C",X"0E",X"03",X"01",X"00",X"00",X"00",X"00",X"03",X"07",X"0C",X"08",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"01",X"0F",X"0F",X"F0",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"0F", + X"00",X"00",X"07",X"0F",X"0F",X"0F",X"0F",X"F0",X"00",X"00",X"00",X"03",X"0F",X"0F",X"0F",X"F0", + X"0F",X"0F",X"01",X"00",X"00",X"00",X"00",X"00",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"0F",X"0F",X"0F",X"0F",X"07",X"00",X"00",X"00",X"0F",X"0F",X"0F",X"03",X"00",X"00",X"00",X"00", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"F0",X"F0",X"01",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"F0", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"F0",X"F0",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"03",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"01",X"00", + X"F0",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"F0",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"E0",X"E0",X"E0",X"E0",X"E0",X"EE",X"00",X"EE",X"F0",X"F0",X"F0",X"F0",X"F0",X"FF",X"00",X"FF", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"BA",X"BA",X"BA",X"BA",X"BA",X"BA",X"BA",X"BA", + X"EE",X"00",X"EE",X"E0",X"E0",X"E0",X"E0",X"E0",X"FF",X"00",X"FF",X"F0",X"F0",X"F0",X"F0",X"F0", + X"D5",X"D5",X"D5",X"D5",X"D5",X"D5",X"D5",X"D5",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"E0",X"E0",X"E0",X"E0",X"E0",X"0E",X"00",X"0E",X"F0",X"F0",X"F0",X"F0",X"F0",X"0F",X"00",X"0F", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"1A",X"1A",X"1A",X"1A",X"1A",X"1A",X"1A",X"1A", + X"0E",X"00",X"0E",X"E0",X"E0",X"E0",X"E0",X"E0",X"0F",X"00",X"0F",X"F0",X"F0",X"F0",X"F0",X"F0", + X"85",X"85",X"85",X"85",X"85",X"85",X"85",X"85",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F3",X"CC",X"33",X"00",X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"FF",X"00",X"FF", + X"E0",X"E0",X"E0",X"E0",X"E0",X"EE",X"00",X"EE",X"F0",X"F0",X"F0",X"FC",X"33",X"CC",X"00",X"00", + X"00",X"00",X"33",X"CC",X"F3",X"F0",X"F0",X"F0",X"FF",X"00",X"FF",X"F0",X"F0",X"F0",X"F0",X"F0", + X"EE",X"00",X"EE",X"E0",X"E0",X"E0",X"E0",X"E0",X"00",X"00",X"CC",X"33",X"FC",X"F0",X"F0",X"F0", + X"00",X"D5",X"D5",X"D5",X"88",X"88",X"44",X"44",X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F1",X"F1", + X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F8",X"F8",X"00",X"BA",X"BA",X"BA",X"11",X"11",X"22",X"22", + X"44",X"44",X"88",X"88",X"D5",X"D5",X"D5",X"D5",X"F1",X"F1",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F8",X"F8",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"22",X"22",X"11",X"11",X"BA",X"BA",X"BA",X"BA", + X"00",X"04",X"E2",X"F3",X"FF",X"BB",X"EE",X"00",X"00",X"02",X"70",X"78",X"78",X"70",X"04",X"04", + X"88",X"89",X"C1",X"E1",X"E1",X"E1",X"E1",X"C1",X"33",X"22",X"70",X"70",X"70",X"70",X"70",X"70", + X"0F",X"0F",X"0F",X"0F",X"0F",X"F0",X"F0",X"F0",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"F0",X"F0", + X"0F",X"0F",X"0F",X"0F",X"0F",X"F0",X"F0",X"F0",X"0F",X"0F",X"0F",X"0F",X"0F",X"F0",X"F0",X"F0", + X"0F",X"0F",X"0F",X"0F",X"78",X"F0",X"F0",X"F0",X"0F",X"0F",X"0F",X"0F",X"0F",X"F0",X"F0",X"F0", + X"0F",X"0F",X"0F",X"0F",X"F0",X"F0",X"F0",X"F0",X"0F",X"0F",X"0F",X"0F",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"78",X"0F",X"0F",X"0F",X"0F",X"0F",X"F0",X"F0",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + X"F0",X"F0",X"F0",X"0F",X"0F",X"0F",X"0F",X"0F",X"F0",X"F0",X"F0",X"0F",X"0F",X"0F",X"0F",X"0F", + X"00",X"00",X"11",X"11",X"30",X"70",X"F0",X"E1",X"00",X"00",X"00",X"00",X"00",X"00",X"CC",X"FF", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"CC",X"CC",X"CC",X"88",X"88",X"C0",X"E0",X"F0",X"78", + X"E1",X"F0",X"70",X"30",X"11",X"11",X"33",X"33",X"33",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"FF",X"33",X"00",X"00",X"00",X"00",X"00",X"00",X"78",X"F0",X"E0",X"C0",X"88",X"88",X"00",X"00", + X"22",X"66",X"66",X"66",X"74",X"70",X"F0",X"E1",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"EE",X"FF",X"00",X"00",X"00",X"00",X"00",X"C0",X"F1",X"F0",X"78", + X"E1",X"F0",X"F8",X"30",X"00",X"00",X"00",X"00",X"00",X"FF",X"77",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"78",X"F0",X"E0",X"E2",X"66",X"66",X"66",X"44", + X"00",X"00",X"00",X"00",X"30",X"70",X"F0",X"E1",X"00",X"00",X"00",X"66",X"66",X"33",X"33",X"00", + X"00",X"88",X"88",X"00",X"00",X"00",X"00",X"00",X"00",X"11",X"77",X"66",X"C0",X"E0",X"F0",X"78", + X"E1",X"F0",X"70",X"30",X"66",X"EE",X"88",X"00",X"00",X"00",X"00",X"00",X"00",X"11",X"11",X"00", + X"00",X"CC",X"CC",X"66",X"66",X"00",X"00",X"00",X"78",X"F0",X"E0",X"C0",X"00",X"00",X"00",X"00", + X"F0",X"F0",X"F0",X"C3",X"0C",X"03",X"00",X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"0F",X"00",X"0F", + X"E0",X"E0",X"E0",X"E0",X"E0",X"0E",X"00",X"0E",X"F0",X"F0",X"F0",X"3C",X"03",X"0C",X"00",X"00", + X"00",X"00",X"03",X"0C",X"C3",X"F0",X"F0",X"F0",X"0F",X"00",X"0F",X"F0",X"F0",X"F0",X"F0",X"F0", + X"0E",X"00",X"0E",X"E0",X"E0",X"E0",X"E0",X"E0",X"00",X"00",X"0C",X"03",X"3C",X"F0",X"F0",X"F0", + X"00",X"85",X"85",X"85",X"08",X"08",X"04",X"04",X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"E1",X"E1", + X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"78",X"78",X"00",X"1A",X"1A",X"1A",X"01",X"01",X"02",X"02", + X"04",X"04",X"08",X"08",X"85",X"85",X"85",X"85",X"E1",X"E1",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"78",X"78",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"02",X"02",X"01",X"01",X"1A",X"1A",X"1A",X"1A", + X"00",X"EE",X"EE",X"EE",X"EE",X"EE",X"EE",X"EE",X"00",X"11",X"33",X"77",X"77",X"77",X"77",X"77", + X"00",X"EE",X"EE",X"EE",X"EE",X"EE",X"EE",X"EE",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"33", + X"EE",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"77",X"77",X"77",X"77",X"77",X"33",X"11",X"00", + X"EE",X"EE",X"EE",X"EE",X"EE",X"CC",X"88",X"00",X"77",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00", + X"33",X"33",X"33",X"33",X"33",X"33",X"00",X"33",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"EE",X"EE",X"EE",X"00",X"00",X"00",X"00",X"CC",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"FF", + X"33",X"33",X"00",X"33",X"33",X"33",X"33",X"33",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"EE",X"EE",X"EE",X"EE",X"EE",X"EE",X"EE",X"CC",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"33",X"11",X"00",X"33",X"33",X"33",X"33",X"33",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"EE",X"EE",X"00",X"00",X"00",X"EE",X"EE",X"EE",X"FF",X"FF",X"00",X"FF",X"FF",X"FF",X"FF",X"FF", + X"33",X"33",X"33",X"33",X"00",X"33",X"33",X"33",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"EE",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"00",X"FF",X"FF",X"FF", + X"33",X"33",X"00",X"11",X"33",X"33",X"33",X"33",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"EE",X"EE",X"EE",X"CC",X"88",X"EE",X"EE",X"EE",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"00",X"11",X"33",X"33",X"33",X"33",X"33",X"33",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"EE",X"EE",X"EE",X"EE",X"CC",X"EE",X"EE",X"00",X"FF",X"FF",X"FF",X"FF",X"99",X"FF",X"FF", + X"00",X"00",X"00",X"00",X"00",X"11",X"33",X"33",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"CC",X"EE",X"EE",X"00",X"00",X"00",X"00",X"00",X"BB",X"BB",X"BB", + X"33",X"33",X"33",X"33",X"33",X"11",X"00",X"33",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"EE",X"EE",X"EE",X"EE",X"EE",X"CC",X"00",X"EE",X"BB",X"88",X"FF",X"FF",X"FF",X"FF",X"00",X"FF", + X"33",X"33",X"33",X"33",X"33",X"33",X"00",X"11",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"EE",X"EE",X"EE",X"00",X"00",X"00",X"00",X"CC",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"FF", + X"33",X"33",X"33",X"33",X"33",X"33",X"33",X"11",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"EE",X"EE",X"EE",X"EE",X"EE",X"EE",X"EE",X"CC",X"FF",X"FF",X"99",X"FF",X"FF",X"FF",X"FF",X"FF", + X"00",X"11",X"33",X"33",X"33",X"33",X"33",X"33",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"CC",X"EE",X"EE",X"EE",X"EE",X"EE",X"EE",X"00",X"FF",X"FF",X"FF",X"99",X"FF",X"FF",X"FF", + X"33",X"11",X"00",X"33",X"33",X"33",X"33",X"33",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"EE",X"CC",X"00",X"00",X"00",X"00",X"EE",X"EE",X"FF",X"FF",X"00",X"FF",X"FF",X"FF",X"FF",X"FF", + X"F0",X"F0",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"F0",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + X"F0",X"F0",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"F0",X"F0",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"44",X"CF",X"C4",X"C6",X"CC",X"DD",X"FF",X"00",X"00",X"11",X"32",X"76",X"76",X"FF",X"FF", + X"00",X"00",X"00",X"00",X"C0",X"C0",X"00",X"00",X"00",X"00",X"06",X"22",X"6E",X"66",X"EE",X"EE", + X"FF",X"FF",X"DD",X"CC",X"C6",X"C4",X"CF",X"44",X"FF",X"FF",X"FF",X"76",X"76",X"32",X"11",X"00", + X"00",X"00",X"00",X"C0",X"C0",X"00",X"00",X"00",X"EE",X"EE",X"EE",X"66",X"6E",X"22",X"06",X"00", + X"00",X"01",X"02",X"19",X"13",X"19",X"BB",X"BB",X"00",X"00",X"00",X"23",X"77",X"75",X"FD",X"FD", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"30",X"B8",X"88",X"CC",X"CC",X"EE", + X"FF",X"FF",X"EE",X"EE",X"FF",X"F9",X"F8",X"77",X"FF",X"FF",X"FF",X"77",X"77",X"33",X"11",X"00", + X"60",X"60",X"00",X"88",X"0C",X"00",X"00",X"00",X"EE",X"FF",X"FF",X"02",X"08",X"02",X"8C",X"88", + X"00",X"00",X"0C",X"22",X"33",X"15",X"19",X"33",X"00",X"00",X"00",X"00",X"01",X"46",X"EE",X"F9", + X"00",X"00",X"00",X"00",X"00",X"00",X"60",X"60",X"00",X"00",X"C0",X"C0",X"00",X"88",X"CC",X"EE", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FC",X"FE",X"77",X"F9",X"FD",X"FF",X"77",X"77",X"33",X"11",X"00", + X"00",X"88",X"04",X"04",X"00",X"00",X"00",X"00",X"FF",X"FF",X"89",X"00",X"8C",X"C5",X"E6",X"CC", + X"00",X"30",X"30",X"CC",X"77",X"7F",X"33",X"33",X"00",X"00",X"00",X"01",X"00",X"02",X"04",X"CD", + X"00",X"00",X"00",X"00",X"C0",X"C0",X"00",X"CC",X"00",X"00",X"00",X"00",X"00",X"CC",X"FF",X"FF", + X"33",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"77",X"FF",X"F9",X"F8",X"77",X"77",X"33",X"11",X"00", + X"02",X"04",X"00",X"08",X"88",X"88",X"00",X"00",X"FF",X"CD",X"00",X"CE",X"FF",X"F1",X"FF",X"CC", + X"00",X"00",X"80",X"80",X"00",X"FF",X"FF",X"77",X"00",X"00",X"10",X"10",X"00",X"37",X"15",X"01", + X"00",X"00",X"00",X"00",X"00",X"8C",X"04",X"00",X"00",X"00",X"30",X"30",X"00",X"FF",X"FF",X"CD", + X"77",X"33",X"FF",X"FF",X"F7",X"FF",X"FF",X"77",X"04",X"05",X"FF",X"74",X"74",X"33",X"11",X"00", + X"04",X"04",X"EE",X"C4",X"C4",X"88",X"00",X"00",X"CC",X"89",X"FF",X"FE",X"FC",X"FF",X"FF",X"CC", + X"00",X"77",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"11",X"33",X"77",X"77",X"F9",X"F9", + X"00",X"00",X"00",X"88",X"08",X"08",X"00",X"04",X"00",X"CC",X"FF",X"F1",X"FF",X"CE",X"00",X"CD", + X"33",X"77",X"77",X"7F",X"66",X"88",X"30",X"30",X"FB",X"CD",X"04",X"02",X"00",X"01",X"01",X"00", + X"8A",X"88",X"00",X"C0",X"C0",X"00",X"00",X"00",X"FF",X"FF",X"EE",X"88",X"00",X"00",X"00",X"00", + X"00",X"77",X"FE",X"FC",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"11",X"33",X"77",X"77",X"FF",X"FD", + X"00",X"00",X"00",X"00",X"00",X"04",X"04",X"88",X"00",X"CC",X"E6",X"C6",X"89",X"04",X"02",X"99", + X"FF",X"77",X"33",X"33",X"37",X"22",X"0C",X"00",X"F9",X"F9",X"EF",X"44",X"02",X"00",X"00",X"00", + X"00",X"60",X"60",X"00",X"00",X"00",X"00",X"00",X"FF",X"EE",X"CC",X"88",X"00",X"00",X"C0",X"C0", + X"00",X"77",X"F9",X"F9",X"FB",X"EE",X"EE",X"FF",X"00",X"00",X"11",X"33",X"77",X"77",X"FF",X"FF", + X"00",X"00",X"00",X"00",X"08",X"88",X"88",X"60",X"00",X"88",X"8C",X"02",X"08",X"02",X"33",X"FF", + X"FF",X"BB",X"BB",X"19",X"13",X"08",X"02",X"01",X"FF",X"FD",X"FD",X"75",X"77",X"33",X"00",X"00", + X"60",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"EE",X"EE",X"CC",X"CC",X"B8",X"B8",X"00", + X"00",X"00",X"00",X"00",X"01",X"0F",X"0F",X"0F",X"00",X"00",X"00",X"00",X"00",X"00",X"07",X"0F", + X"00",X"00",X"07",X"0F",X"0F",X"0F",X"0F",X"0F",X"00",X"00",X"00",X"03",X"0F",X"0F",X"0F",X"0F", + X"0F",X"0F",X"01",X"00",X"00",X"00",X"00",X"00",X"07",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"0F",X"0F",X"0F",X"0F",X"07",X"00",X"00",X"00",X"0F",X"0F",X"0F",X"03",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"EE",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"03",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"01",X"00", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"01",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + X"FF",X"FF",X"CC",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"EE",X"CC",X"CC",X"CC", + X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"CC",X"FF",X"FF",X"FF",X"CC",X"CC",X"EE",X"FF",X"FF",X"FF",X"FF",X"FF", + X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"FF", + X"EE",X"CC",X"88",X"88",X"88",X"88",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"EE",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"EE",X"88",X"00",X"00", + X"00",X"88",X"88",X"88",X"88",X"CC",X"EE",X"EE",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"00",X"00",X"00",X"00",X"EE",X"FF",X"FF",X"FF",X"00",X"88",X"EE",X"FF",X"FF",X"FF",X"FF",X"FF", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"CC",X"88",X"88",X"88",X"88",X"00",X"00",X"00", + X"88",X"88",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"EE",X"EE",X"CC",X"CC", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"88",X"88",X"88",X"88",X"CC", + X"00",X"00",X"00",X"00",X"00",X"00",X"88",X"88",X"CC",X"CC",X"EE",X"EE",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"EE",X"CC",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"EE",X"88",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"EE",X"CC",X"00",X"00",X"00", + X"CC",X"EE",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"00",X"00",X"00",X"00",X"00",X"88",X"EE",X"FF",X"00",X"00",X"00",X"CC",X"EE",X"FF",X"FF",X"FF", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"EE",X"EE",X"EE",X"EE",X"EE",X"EE", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"EE",X"EE",X"EE",X"EE",X"EE",X"EE",X"FF",X"FF", + X"EE",X"CC",X"CC",X"88",X"88",X"88",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"88",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"EE",X"CC",X"88",X"88",X"00",X"00", + X"00",X"00",X"88",X"88",X"88",X"CC",X"CC",X"EE",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"88",X"00",X"00",X"88",X"88",X"CC",X"EE",X"FF",X"FF", + X"00",X"03",X"78",X"78",X"70",X"70",X"70",X"FF",X"00",X"00",X"03",X"03",X"00",X"00",X"00",X"33", + X"00",X"00",X"00",X"00",X"0C",X"0C",X"00",X"00",X"00",X"0E",X"F0",X"F0",X"F0",X"F0",X"F0",X"F8", + X"11",X"11",X"11",X"11",X"FF",X"FF",X"FF",X"00",X"33",X"33",X"33",X"33",X"33",X"11",X"00",X"00", + X"0C",X"0C",X"00",X"00",X"04",X"00",X"00",X"00",X"F8",X"F8",X"F8",X"FF",X"FF",X"EE",X"CC",X"00", + X"00",X"34",X"78",X"F0",X"F0",X"F0",X"F0",X"F1",X"00",X"00",X"00",X"01",X"12",X"1E",X"0C",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"0C",X"0C",X"00",X"80",X"C3",X"C3",X"E0",X"E0",X"F0",X"F8", + X"77",X"88",X"88",X"88",X"CC",X"FF",X"FF",X"33",X"00",X"11",X"11",X"11",X"11",X"00",X"00",X"00", + X"80",X"8A",X"CC",X"88",X"88",X"88",X"00",X"00",X"F8",X"FC",X"FF",X"77",X"FF",X"FF",X"EE",X"CC", + X"00",X"24",X"78",X"F0",X"F0",X"F0",X"F0",X"F1",X"00",X"00",X"00",X"01",X"12",X"30",X"34",X"1E", + X"00",X"00",X"00",X"00",X"08",X"08",X"08",X"82",X"00",X"04",X"0C",X"84",X"C0",X"E1",X"F0",X"F8", + X"F3",X"E6",X"CC",X"CC",X"EE",X"77",X"33",X"11",X"1C",X"00",X"00",X"11",X"00",X"00",X"00",X"00", + X"CC",X"CC",X"CC",X"CC",X"88",X"00",X"00",X"00",X"FC",X"FF",X"77",X"33",X"77",X"FF",X"EE",X"CC", + X"00",X"03",X"C3",X"F0",X"F0",X"F0",X"F0",X"F1",X"00",X"00",X"01",X"12",X"12",X"34",X"70",X"70", + X"00",X"00",X"00",X"00",X"02",X"00",X"CC",X"CC",X"00",X"00",X"00",X"03",X"C3",X"F0",X"F0",X"F9", + X"F3",X"E2",X"44",X"44",X"FF",X"77",X"11",X"00",X"34",X"0E",X"0C",X"00",X"00",X"00",X"00",X"00", + X"CC",X"EE",X"CC",X"CC",X"88",X"88",X"00",X"00",X"FF",X"FF",X"33",X"33",X"33",X"FF",X"FF",X"00", + X"00",X"00",X"00",X"33",X"33",X"22",X"E2",X"E2",X"00",X"00",X"00",X"06",X"06",X"06",X"70",X"78", + X"00",X"00",X"00",X"00",X"88",X"CC",X"CC",X"CC",X"00",X"00",X"00",X"FF",X"FF",X"11",X"11",X"11", + X"F3",X"F3",X"F0",X"F0",X"F0",X"09",X"09",X"00",X"78",X"78",X"78",X"78",X"70",X"01",X"01",X"00", + X"CC",X"CC",X"CC",X"88",X"00",X"00",X"00",X"00",X"FF",X"FF",X"F3",X"F3",X"F3",X"08",X"09",X"00", + X"00",X"00",X"11",X"77",X"FF",X"44",X"44",X"E2",X"00",X"00",X"00",X"00",X"00",X"00",X"0C",X"0E", + X"00",X"00",X"00",X"88",X"88",X"CC",X"CC",X"EE",X"00",X"00",X"FF",X"FF",X"33",X"33",X"33",X"FF", + X"F3",X"F1",X"F0",X"F0",X"F0",X"F0",X"4B",X"03",X"34",X"70",X"70",X"70",X"12",X"03",X"01",X"00", + X"CC",X"CC",X"CC",X"00",X"02",X"00",X"00",X"00",X"FF",X"F9",X"F0",X"F0",X"C3",X"03",X"00",X"00", + X"00",X"11",X"33",X"77",X"EE",X"CC",X"CC",X"66",X"00",X"00",X"00",X"00",X"00",X"11",X"00",X"00", + X"00",X"00",X"00",X"00",X"88",X"CC",X"CC",X"CC",X"00",X"CC",X"EE",X"FF",X"77",X"33",X"77",X"FF", + X"F3",X"F1",X"F0",X"F0",X"F0",X"F0",X"78",X"24",X"0C",X"1E",X"34",X"30",X"12",X"01",X"00",X"00", + X"CC",X"82",X"08",X"08",X"08",X"00",X"00",X"00",X"FC",X"F8",X"F0",X"E1",X"C0",X"84",X"0C",X"04", + X"00",X"33",X"FF",X"FF",X"CC",X"88",X"88",X"88",X"00",X"00",X"00",X"00",X"11",X"11",X"11",X"11", + X"00",X"00",X"00",X"88",X"88",X"88",X"CC",X"8A",X"00",X"CC",X"EE",X"FF",X"FF",X"77",X"FF",X"FC", + X"77",X"F1",X"F0",X"F0",X"F0",X"F0",X"78",X"07",X"00",X"00",X"0C",X"1E",X"12",X"10",X"00",X"00", + X"80",X"0C",X"0C",X"00",X"00",X"00",X"00",X"00",X"F8",X"F8",X"F0",X"E0",X"E0",X"C3",X"C3",X"80", + X"00",X"00",X"FF",X"FF",X"FF",X"11",X"11",X"11",X"00",X"00",X"00",X"11",X"33",X"33",X"33",X"33", + X"00",X"00",X"00",X"00",X"04",X"00",X"00",X"0C",X"00",X"00",X"CC",X"EE",X"FF",X"FF",X"F8",X"F8", + X"11",X"FF",X"70",X"70",X"70",X"78",X"78",X"03",X"33",X"33",X"00",X"00",X"00",X"03",X"03",X"00", + X"0C",X"00",X"00",X"0C",X"0C",X"00",X"00",X"00",X"F8",X"F8",X"F0",X"F0",X"F0",X"F0",X"F0",X"0E", + X"00",X"22",X"FF",X"FF",X"FF",X"FF",X"33",X"33",X"00",X"00",X"00",X"33",X"77",X"77",X"66",X"66", + X"00",X"00",X"00",X"00",X"08",X"08",X"00",X"00",X"00",X"01",X"CC",X"CC",X"E9",X"E1",X"F0",X"F8", + X"11",X"33",X"FC",X"30",X"10",X"12",X"07",X"06",X"77",X"33",X"33",X"11",X"00",X"00",X"00",X"00", + X"86",X"86",X"C0",X"C0",X"84",X"08",X"00",X"00",X"F8",X"F0",X"F0",X"F0",X"F0",X"E1",X"C2",X"00", + X"00",X"00",X"FF",X"FF",X"FE",X"FE",X"77",X"33",X"00",X"00",X"00",X"11",X"33",X"77",X"FF",X"EE", + X"00",X"00",X"00",X"00",X"00",X"00",X"0E",X"84",X"00",X"08",X"00",X"87",X"C2",X"E0",X"F0",X"F8", + X"11",X"33",X"FE",X"DC",X"88",X"00",X"01",X"01",X"EE",X"77",X"33",X"11",X"00",X"00",X"00",X"00", + X"C0",X"E0",X"C2",X"84",X"08",X"00",X"00",X"00",X"F8",X"F0",X"F0",X"F0",X"F0",X"69",X"0C",X"08", + X"00",X"02",X"44",X"FE",X"FC",X"FC",X"FE",X"77",X"00",X"00",X"00",X"33",X"33",X"77",X"FF",X"FF", + X"00",X"00",X"00",X"00",X"0C",X"0C",X"C0",X"C2",X"00",X"00",X"0C",X"0C",X"C0",X"F0",X"F0",X"F8", + X"11",X"11",X"11",X"EE",X"EE",X"00",X"00",X"00",X"EE",X"EE",X"77",X"77",X"11",X"00",X"00",X"00", + X"C2",X"C2",X"C2",X"84",X"80",X"00",X"00",X"00",X"F8",X"F0",X"F0",X"F0",X"34",X"07",X"0E",X"0C", + X"00",X"00",X"00",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"11",X"33",X"77",X"77",X"77", + X"00",X"00",X"00",X"0C",X"0C",X"0C",X"C0",X"C2",X"00",X"00",X"00",X"88",X"88",X"88",X"F8",X"F8", + X"FF",X"FF",X"F8",X"F8",X"F8",X"03",X"03",X"00",X"77",X"77",X"77",X"33",X"11",X"00",X"01",X"00", + X"C2",X"C2",X"C2",X"C2",X"C0",X"00",X"00",X"00",X"F8",X"F8",X"F0",X"F0",X"F0",X"03",X"03",X"00", + X"00",X"00",X"00",X"00",X"EE",X"EE",X"11",X"11",X"00",X"00",X"00",X"00",X"11",X"77",X"77",X"EE", + X"00",X"00",X"00",X"00",X"08",X"84",X"C2",X"E0",X"00",X"06",X"06",X"03",X"30",X"F0",X"F0",X"F0", + X"11",X"77",X"FE",X"FC",X"FC",X"FE",X"44",X"04",X"EE",X"FF",X"FF",X"77",X"33",X"33",X"00",X"00", + X"E0",X"E0",X"C0",X"0C",X"0C",X"00",X"00",X"00",X"F8",X"F8",X"F0",X"F0",X"C0",X"0C",X"0C",X"00", + X"00",X"01",X"01",X"00",X"88",X"DC",X"FE",X"33",X"00",X"00",X"00",X"00",X"00",X"11",X"33",X"77", + X"00",X"00",X"00",X"00",X"08",X"84",X"C2",X"E0",X"00",X"08",X"0C",X"69",X"F0",X"F0",X"F0",X"F0", + X"11",X"33",X"77",X"FE",X"FE",X"FF",X"FF",X"00",X"EE",X"EE",X"FF",X"77",X"33",X"11",X"00",X"00", + X"C0",X"84",X"0E",X"00",X"00",X"00",X"00",X"00",X"F8",X"F8",X"F0",X"E0",X"C2",X"87",X"00",X"08", + X"00",X"06",X"07",X"12",X"10",X"30",X"FC",X"33",X"00",X"00",X"00",X"00",X"00",X"11",X"33",X"33", + X"00",X"00",X"00",X"08",X"84",X"C0",X"C0",X"86",X"00",X"00",X"C2",X"E1",X"F0",X"F0",X"F0",X"F0", + X"11",X"33",X"33",X"FF",X"FF",X"FF",X"FF",X"22",X"77",X"66",X"66",X"77",X"77",X"33",X"00",X"00", + X"86",X"00",X"00",X"08",X"08",X"00",X"00",X"00",X"F8",X"F8",X"F0",X"E1",X"E9",X"CC",X"CC",X"01"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/loc_col_rom.vhd b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/loc_col_rom.vhd new file mode 100644 index 00000000..e5727bd6 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/loc_col_rom.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity loc_col_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of loc_col_rom is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"09",X"05",X"0C",X"00",X"01",X"08",X"06",X"00",X"06",X"0F",X"01",X"00",X"01",X"02",X"03", + X"00",X"04",X"05",X"07",X"00",X"07",X"08",X"09",X"00",X"0A",X"0B",X"0C",X"00",X"08",X"05",X"0F", + X"00",X"08",X"0F",X"01",X"00",X"05",X"04",X"0E",X"00",X"01",X"07",X"08",X"00",X"0B",X"0C",X"0D", + X"00",X"01",X"01",X"01",X"00",X"02",X"02",X"02",X"00",X"03",X"03",X"03",X"00",X"04",X"04",X"04", + X"00",X"05",X"05",X"05",X"00",X"06",X"06",X"06",X"00",X"07",X"07",X"07",X"00",X"08",X"08",X"08", + X"00",X"09",X"09",X"09",X"00",X"0A",X"0A",X"0A",X"00",X"0B",X"0B",X"0B",X"00",X"0C",X"0C",X"0C", + X"00",X"0D",X"0D",X"0D",X"00",X"0E",X"0E",X"0E",X"00",X"0F",X"0F",X"0F",X"00",X"00",X"00",X"00", + X"00",X"02",X"05",X"0C",X"00",X"09",X"05",X"0C",X"00",X"0B",X"05",X"0C",X"00",X"0E",X"05",X"0C", + X"00",X"09",X"05",X"0C",X"00",X"01",X"08",X"06",X"00",X"06",X"0F",X"01",X"00",X"01",X"02",X"03", + X"00",X"04",X"05",X"07",X"00",X"07",X"08",X"09",X"00",X"0A",X"0B",X"0C",X"00",X"08",X"05",X"0F", + X"00",X"08",X"00",X"01",X"00",X"05",X"04",X"0E",X"00",X"01",X"07",X"08",X"00",X"0B",X"0C",X"0D", + X"00",X"01",X"01",X"01",X"00",X"02",X"02",X"02",X"00",X"03",X"03",X"03",X"00",X"04",X"04",X"04", + X"00",X"05",X"05",X"05",X"00",X"06",X"06",X"06",X"00",X"07",X"07",X"07",X"00",X"08",X"08",X"08", + X"00",X"09",X"09",X"09",X"00",X"0A",X"0A",X"0A",X"00",X"0B",X"0B",X"0B",X"00",X"0C",X"0C",X"0C", + X"00",X"0D",X"0D",X"0D",X"00",X"0E",X"0E",X"0E",X"00",X"0F",X"0F",X"0F",X"00",X"03",X"06",X"0D", + X"00",X"04",X"05",X"0C",X"00",X"03",X"05",X"0C",X"00",X"0B",X"08",X"09",X"00",X"09",X"04",X"0D"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/loc_dot_rom.vhd b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/loc_dot_rom.vhd new file mode 100644 index 00000000..2a1b624f --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/loc_dot_rom.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity loc_dot_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of loc_dot_rom is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"02",X"02",X"02",X"02",X"01",X"02",X"03", + X"03",X"03",X"02",X"01",X"03",X"01",X"02",X"01",X"03",X"01",X"01",X"01",X"03",X"01",X"01",X"01", + X"01",X"01",X"01",X"01",X"01",X"01",X"02",X"01",X"01",X"02",X"01",X"01",X"01",X"01",X"01",X"01", + X"01",X"01",X"01",X"01",X"01",X"02",X"02",X"02",X"02",X"02",X"03",X"03",X"03",X"03",X"03",X"03", + X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"02",X"02",X"01",X"01",X"02",X"03",X"03", + X"02",X"02",X"03",X"03",X"01",X"01",X"01",X"03",X"01",X"01",X"01",X"02",X"02",X"01",X"01",X"02", + X"02",X"01",X"01",X"01",X"02",X"01",X"01",X"01",X"03",X"02",X"01",X"01",X"03",X"03",X"01",X"01", + X"01",X"01",X"01",X"02",X"01",X"01",X"01",X"02",X"01",X"01",X"02",X"03",X"01",X"01",X"03",X"03", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"08",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"08",X"00",X"00",X"00",X"08",X"00", + X"00",X"00",X"08",X"00",X"00",X"00",X"08",X"00",X"00",X"00",X"08",X"00",X"00",X"00",X"08",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/loc_pal_rom.vhd b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/loc_pal_rom.vhd new file mode 100644 index 00000000..62d63c29 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/loc_pal_rom.vhd @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity loc_pal_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of loc_pal_rom is + type rom is array(0 to 31) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"07",X"A0",X"97",X"67",X"3F",X"7D",X"38",X"F0",X"A8",X"C0",X"18",X"5E",X"A8",X"1B",X"FF", + X"00",X"FF",X"B7",X"00",X"00",X"FF",X"B7",X"00",X"00",X"FF",X"B7",X"00",X"00",X"FF",X"B7",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/loc_prg_rom.vhd b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/loc_prg_rom.vhd new file mode 100644 index 00000000..48d5172a --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/loc_prg_rom.vhd @@ -0,0 +1,1302 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity loc_prg_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(14 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of loc_prg_rom is + type rom is array(0 to 20479) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"3E",X"00",X"32",X"81",X"A1",X"C3",X"A5",X"02",X"E1",X"87",X"E7",X"5E",X"23",X"56",X"EB",X"E9", + X"77",X"23",X"10",X"FC",X"0D",X"20",X"F9",X"C9",X"35",X"34",X"C8",X"35",X"C9",X"FF",X"FF",X"FF", + X"85",X"6F",X"D0",X"24",X"C9",X"FF",X"FF",X"FF",X"19",X"7C",X"E6",X"03",X"F6",X"80",X"67",X"C9", + X"EB",X"4E",X"23",X"46",X"EB",X"09",X"C9",X"FF",X"3A",X"C0",X"98",X"26",X"98",X"6F",X"7E",X"B7", + X"C0",X"72",X"2C",X"73",X"2C",X"7D",X"20",X"02",X"3E",X"C2",X"32",X"C0",X"98",X"C9",X"FF",X"FF", + X"FF",X"FF",X"FD",X"E1",X"DD",X"E1",X"E1",X"D1",X"C1",X"F1",X"D9",X"08",X"E1",X"D1",X"C1",X"3E", + X"01",X"32",X"81",X"A1",X"F1",X"C9",X"F5",X"AF",X"32",X"81",X"A1",X"C5",X"D5",X"E5",X"08",X"D9", + X"F5",X"C5",X"D5",X"E5",X"DD",X"E5",X"FD",X"E5",X"CD",X"58",X"01",X"CD",X"2E",X"01",X"21",X"1E", + X"98",X"11",X"1F",X"98",X"ED",X"A8",X"3A",X"00",X"A1",X"2F",X"12",X"1D",X"2D",X"ED",X"A8",X"3A", + X"80",X"A0",X"2F",X"12",X"1D",X"2D",X"ED",X"A8",X"ED",X"A8",X"ED",X"A8",X"3A",X"00",X"A0",X"2F", + X"12",X"32",X"80",X"A0",X"21",X"07",X"98",X"35",X"CD",X"C0",X"1F",X"CD",X"BE",X"00",X"21",X"52", + X"00",X"E5",X"3A",X"00",X"98",X"CF",X"18",X"02",X"4F",X"09",X"04",X"21",X"92",X"15",X"21",X"10", + X"98",X"7E",X"B7",X"28",X"05",X"35",X"07",X"32",X"84",X"A1",X"2E",X"14",X"7E",X"B7",X"28",X"05", + X"35",X"07",X"32",X"86",X"A1",X"21",X"18",X"98",X"7E",X"2C",X"B6",X"2C",X"2F",X"A6",X"E6",X"C4", + X"C8",X"47",X"E6",X"84",X"28",X"30",X"B8",X"28",X"04",X"01",X"16",X"01",X"C5",X"07",X"30",X"08", + X"3E",X"82",X"32",X"10",X"98",X"CD",X"8C",X"20",X"3A",X"15",X"98",X"47",X"21",X"11",X"98",X"7E", + X"C6",X"10",X"B8",X"77",X"D8",X"36",X"00",X"78",X"E6",X"0F",X"21",X"12",X"98",X"86",X"FE",X"63", + X"38",X"02",X"3E",X"63",X"77",X"C9",X"CD",X"8C",X"20",X"3E",X"86",X"32",X"14",X"98",X"3A",X"16", + X"98",X"47",X"21",X"13",X"98",X"7E",X"C6",X"10",X"B8",X"77",X"D8",X"C3",X"05",X"01",X"21",X"40", + X"98",X"11",X"14",X"80",X"AF",X"CD",X"3E",X"01",X"21",X"42",X"98",X"11",X"14",X"88",X"01",X"0C", + X"00",X"ED",X"A0",X"ED",X"A0",X"2C",X"2C",X"B9",X"38",X"F7",X"0E",X"04",X"1E",X"00",X"ED",X"A0", + X"ED",X"A0",X"2C",X"2C",X"B9",X"38",X"F7",X"C9",X"AF",X"21",X"20",X"88",X"01",X"01",X"04",X"D7", + X"21",X"60",X"98",X"11",X"34",X"80",X"CD",X"72",X"01",X"11",X"04",X"A0",X"CD",X"72",X"01",X"11", + X"34",X"88",X"ED",X"A0",X"ED",X"A0",X"ED",X"A0",X"ED",X"A0",X"ED",X"A0",X"ED",X"A0",X"ED",X"A0", + X"ED",X"A0",X"ED",X"A0",X"ED",X"A0",X"ED",X"A0",X"ED",X"A0",X"11",X"04",X"00",X"19",X"C9",X"21", + X"0E",X"99",X"34",X"5E",X"16",X"4E",X"1A",X"2C",X"86",X"77",X"C9",X"26",X"98",X"3A",X"C1",X"98", + X"6F",X"7E",X"87",X"20",X"0F",X"26",X"9C",X"3A",X"21",X"9C",X"6F",X"7E",X"87",X"20",X"22",X"CD", + X"C0",X"03",X"18",X"E7",X"4F",X"06",X"00",X"70",X"23",X"5E",X"2C",X"7D",X"20",X"02",X"3E",X"C2", + X"32",X"C1",X"98",X"7B",X"21",X"EF",X"01",X"09",X"5E",X"23",X"56",X"21",X"9B",X"01",X"E5",X"EB", + X"E9",X"4F",X"06",X"00",X"70",X"23",X"5E",X"2C",X"7D",X"FE",X"20",X"38",X"01",X"AF",X"32",X"21", + X"9C",X"7B",X"21",X"EF",X"01",X"09",X"5E",X"23",X"56",X"21",X"9B",X"01",X"E5",X"EB",X"E9",X"FF", + X"03",X"2C",X"03",X"84",X"04",X"DB",X"04",X"A6",X"08",X"E9",X"08",X"03",X"09",X"1E",X"09",X"00", + X"04",X"3A",X"20",X"9C",X"6F",X"26",X"9C",X"7E",X"B7",X"C0",X"72",X"2C",X"73",X"2C",X"7D",X"FE", + X"20",X"38",X"01",X"AF",X"32",X"20",X"9C",X"C9",X"3A",X"80",X"A1",X"47",X"E6",X"0F",X"20",X"01", + X"47",X"4F",X"A8",X"0F",X"0F",X"0F",X"0F",X"21",X"21",X"09",X"E7",X"46",X"79",X"21",X"21",X"09", + X"E7",X"4E",X"ED",X"43",X"15",X"98",X"3A",X"00",X"A1",X"EE",X"33",X"47",X"0F",X"0F",X"0F",X"0F", + X"E6",X"03",X"C6",X"03",X"FE",X"06",X"20",X"02",X"3E",X"FF",X"32",X"0C",X"98",X"78",X"21",X"00", + X"00",X"54",X"5C",X"44",X"4C",X"0F",X"CB",X"14",X"0F",X"CB",X"11",X"0F",X"CB",X"12",X"0F",X"CB", + X"10",X"3A",X"80",X"A1",X"E6",X"0F",X"20",X"01",X"2C",X"ED",X"53",X"BC",X"98",X"22",X"BE",X"98", + X"21",X"0B",X"98",X"70",X"2E",X"0F",X"71",X"3E",X"0A",X"06",X"00",X"21",X"31",X"09",X"11",X"00", + X"9F",X"0E",X"03",X"ED",X"B0",X"EB",X"01",X"3E",X"09",X"71",X"2C",X"10",X"FC",X"EB",X"3D",X"20", + X"F0",X"21",X"31",X"09",X"11",X"C6",X"99",X"0E",X"03",X"ED",X"B0",X"3E",X"01",X"32",X"0D",X"98", + X"21",X"00",X"98",X"34",X"C9",X"3A",X"00",X"50",X"FE",X"55",X"CA",X"01",X"50",X"21",X"00",X"98", + X"11",X"01",X"98",X"01",X"FF",X"07",X"36",X"00",X"ED",X"B0",X"32",X"80",X"A0",X"31",X"00",X"A0", + X"21",X"C2",X"C2",X"22",X"C0",X"98",X"21",X"D0",X"99",X"01",X"01",X"30",X"3E",X"FF",X"D7",X"21", + X"D0",X"D0",X"22",X"CD",X"99",X"32",X"80",X"A0",X"AF",X"32",X"84",X"A1",X"32",X"86",X"A1",X"32", + X"87",X"A1",X"3C",X"32",X"83",X"A1",X"CD",X"E5",X"1F",X"3E",X"0B",X"21",X"00",X"80",X"01",X"04", + X"00",X"D7",X"32",X"80",X"A0",X"01",X"04",X"00",X"D7",X"3E",X"80",X"32",X"80",X"A0",X"01",X"04", + X"00",X"D7",X"3E",X"80",X"32",X"80",X"A0",X"01",X"04",X"00",X"D7",X"CD",X"D1",X"1C",X"32",X"80", + X"A0",X"CD",X"22",X"03",X"CD",X"EB",X"1F",X"CD",X"22",X"03",X"3E",X"01",X"32",X"81",X"A1",X"C3", + X"9B",X"01",X"0B",X"32",X"80",X"A0",X"78",X"B1",X"20",X"F8",X"37",X"C9",X"47",X"3A",X"08",X"98", + X"B7",X"C8",X"3A",X"09",X"98",X"B7",X"20",X"63",X"11",X"00",X"02",X"CD",X"01",X"02",X"11",X"C0", + X"99",X"78",X"87",X"20",X"06",X"21",X"C9",X"99",X"C3",X"50",X"03",X"80",X"21",X"48",X"04",X"E7", + X"B7",X"06",X"03",X"1A",X"8E",X"27",X"12",X"1C",X"23",X"10",X"F8",X"47",X"30",X"04",X"AF",X"32", + X"3F",X"99",X"3A",X"01",X"99",X"B8",X"DC",X"A7",X"03",X"3A",X"3F",X"99",X"B7",X"20",X"1A",X"06", + X"03",X"21",X"C8",X"99",X"1D",X"1A",X"BE",X"D8",X"20",X"04",X"2D",X"10",X"F7",X"C9",X"3E",X"01", + X"32",X"3F",X"99",X"3E",X"04",X"90",X"EB",X"E7",X"EB",X"EB",X"2D",X"11",X"C8",X"99",X"ED",X"A8", + X"ED",X"A8",X"ED",X"A8",X"11",X"02",X"02",X"CD",X"01",X"02",X"C9",X"11",X"01",X"02",X"CD",X"01", + X"02",X"11",X"C3",X"99",X"C3",X"41",X"03",X"D5",X"C6",X"07",X"27",X"30",X"02",X"3E",X"99",X"21", + X"01",X"99",X"77",X"2D",X"34",X"11",X"00",X"05",X"CD",X"01",X"02",X"CD",X"73",X"20",X"D1",X"C9", + X"CD",X"59",X"2A",X"CD",X"87",X"2C",X"CD",X"2F",X"2E",X"CD",X"33",X"2B",X"21",X"19",X"98",X"CB", + X"46",X"C8",X"C9",X"0E",X"30",X"1A",X"91",X"77",X"13",X"3E",X"20",X"E7",X"10",X"F7",X"C9",X"81", + X"8C",X"9A",X"81",X"8C",X"8E",X"8E",X"8E",X"8E",X"90",X"90",X"90",X"90",X"90",X"90",X"91",X"91", + X"91",X"91",X"91",X"91",X"92",X"92",X"92",X"92",X"92",X"92",X"92",X"92",X"93",X"93",X"93",X"C9", + X"3C",X"28",X"06",X"21",X"DF",X"03",X"CD",X"C4",X"11",X"01",X"10",X"0B",X"79",X"C5",X"CD",X"DB", + X"04",X"C1",X"0C",X"10",X"F7",X"21",X"98",X"85",X"DD",X"21",X"02",X"9F",X"06",X"0A",X"C5",X"11", + X"20",X"00",X"CD",X"A2",X"04",X"11",X"60",X"00",X"19",X"DD",X"E5",X"D1",X"13",X"13",X"13",X"13", + X"06",X"03",X"CD",X"D3",X"03",X"11",X"0F",X"00",X"DD",X"19",X"11",X"7E",X"FE",X"19",X"C1",X"10", + X"DD",X"11",X"0F",X"03",X"CD",X"01",X"02",X"C9",X"00",X"00",X"00",X"10",X"00",X"00",X"20",X"00", + X"00",X"30",X"00",X"00",X"40",X"00",X"00",X"50",X"00",X"00",X"60",X"00",X"00",X"70",X"00",X"00", + X"80",X"00",X"00",X"90",X"00",X"00",X"00",X"01",X"00",X"10",X"01",X"00",X"20",X"01",X"00",X"30", + X"01",X"00",X"40",X"01",X"00",X"50",X"01",X"00",X"00",X"02",X"00",X"00",X"04",X"00",X"00",X"10", + X"00",X"00",X"50",X"00",X"DD",X"21",X"C2",X"99",X"21",X"85",X"80",X"A7",X"28",X"11",X"DD",X"21", + X"C5",X"99",X"21",X"C5",X"82",X"3D",X"28",X"07",X"DD",X"21",X"C8",X"99",X"21",X"A5",X"81",X"11", + X"20",X"00",X"06",X"03",X"DD",X"7E",X"00",X"4F",X"0F",X"0F",X"0F",X"0F",X"E6",X"0F",X"20",X"1F", + X"36",X"10",X"19",X"79",X"E6",X"0F",X"20",X"1C",X"36",X"10",X"19",X"DD",X"2B",X"10",X"E5",X"AF", + X"ED",X"52",X"77",X"19",X"C9",X"DD",X"7E",X"00",X"4F",X"0F",X"0F",X"0F",X"0F",X"E6",X"0F",X"77", + X"19",X"79",X"E6",X"0F",X"77",X"19",X"DD",X"2B",X"10",X"EB",X"C9",X"47",X"E6",X"3F",X"FE",X"03", + X"20",X"0A",X"78",X"E6",X"C0",X"F6",X"31",X"C5",X"CD",X"ED",X"04",X"C1",X"78",X"87",X"F5",X"21", + X"2B",X"05",X"E6",X"7F",X"85",X"6F",X"30",X"01",X"24",X"F1",X"5E",X"23",X"56",X"EB",X"5E",X"23", + X"56",X"23",X"EB",X"01",X"20",X"00",X"38",X"15",X"1A",X"FE",X"2E",X"28",X"0B",X"FE",X"2F",X"C8", + X"D6",X"30",X"77",X"13",X"09",X"18",X"F1",X"37",X"EB",X"23",X"C3",X"FE",X"04",X"1A",X"FE",X"2E", + X"28",X"F5",X"FE",X"2F",X"C8",X"36",X"10",X"13",X"09",X"18",X"F2",X"9B",X"05",X"A2",X"05",X"A9", + X"05",X"B0",X"05",X"DC",X"05",X"F3",X"05",X"09",X"06",X"12",X"06",X"2A",X"06",X"3C",X"06",X"51", + X"06",X"5B",X"06",X"68",X"06",X"75",X"06",X"81",X"06",X"92",X"06",X"A3",X"06",X"B9",X"06",X"BF", + X"06",X"C5",X"06",X"CB",X"06",X"D1",X"06",X"D7",X"06",X"DD",X"06",X"E3",X"06",X"E9",X"06",X"EF", + X"06",X"F6",X"06",X"00",X"07",X"07",X"07",X"07",X"07",X"37",X"07",X"37",X"07",X"66",X"07",X"73", + X"07",X"81",X"07",X"90",X"07",X"98",X"07",X"A8",X"07",X"B4",X"07",X"CC",X"07",X"E6",X"07",X"F7", + X"07",X"FD",X"07",X"0F",X"08",X"19",X"08",X"26",X"08",X"33",X"08",X"43",X"08",X"51",X"08",X"66", + X"08",X"A3",X"08",X"A3",X"08",X"A3",X"08",X"A3",X"08",X"A3",X"08",X"C6",X"81",X"48",X"49",X"47", + X"48",X"2F",X"A6",X"80",X"31",X"5B",X"55",X"50",X"2F",X"E6",X"82",X"32",X"5B",X"55",X"50",X"2F", + X"D9",X"84",X"3F",X"3F",X"40",X"40",X"4C",X"4F",X"43",X"4F",X"5B",X"4D",X"4F",X"54",X"49",X"4F", + X"4E",X"40",X"40",X"3F",X"3F",X"2F",X"D9",X"84",X"5B",X"40",X"47",X"55",X"54",X"54",X"41",X"4E", + X"47",X"40",X"47",X"4F",X"54",X"54",X"4F",X"4E",X"47",X"40",X"5B",X"2F",X"B2",X"84",X"50",X"4C", + X"45",X"41",X"53",X"45",X"40",X"44",X"45",X"50",X"4F",X"53",X"49",X"54",X"40",X"43",X"4F",X"49", + X"4E",X"53",X"2F",X"CC",X"84",X"48",X"41",X"56",X"45",X"40",X"41",X"40",X"4E",X"49",X"43",X"45", + X"40",X"54",X"52",X"49",X"50",X"40",X"3C",X"3C",X"2F",X"95",X"85",X"50",X"4C",X"45",X"41",X"53", + X"45",X"2F",X"A4",X"84",X"50",X"55",X"53",X"48",X"40",X"53",X"54",X"41",X"52",X"54",X"40",X"42", + X"55",X"54",X"54",X"4F",X"4E",X"40",X"46",X"4F",X"52",X"2F",X"02",X"85",X"4F",X"4E",X"45",X"40", + X"50",X"4C",X"41",X"59",X"45",X"52",X"40",X"4F",X"4E",X"4C",X"59",X"2F",X"C2",X"84",X"4F",X"4E", + X"45",X"40",X"4F",X"52",X"40",X"54",X"57",X"4F",X"40",X"50",X"4C",X"41",X"59",X"45",X"52",X"53", + X"2F",X"84",X"82",X"43",X"52",X"45",X"44",X"49",X"54",X"40",X"2F",X"75",X"85",X"50",X"4C",X"41", + X"59",X"45",X"52",X"40",X"4F",X"4E",X"45",X"2F",X"75",X"85",X"50",X"4C",X"41",X"59",X"45",X"52", + X"40",X"54",X"57",X"4F",X"2F",X"71",X"85",X"47",X"41",X"4D",X"45",X"40",X"4F",X"56",X"45",X"52", + X"2F",X"22",X"85",X"3A",X"40",X"43",X"45",X"4E",X"54",X"55",X"52",X"49",X"40",X"31",X"39",X"38", + X"32",X"2F",X"20",X"85",X"3A",X"40",X"43",X"45",X"4E",X"54",X"55",X"52",X"49",X"40",X"31",X"39", + X"38",X"32",X"2F",X"DA",X"84",X"5B",X"40",X"40",X"53",X"43",X"4F",X"52",X"45",X"40",X"52",X"41", + X"4E",X"4B",X"49",X"4E",X"47",X"40",X"40",X"5B",X"2F",X"B8",X"84",X"31",X"53",X"54",X"2F",X"B6", + X"84",X"32",X"4E",X"44",X"2F",X"B4",X"84",X"33",X"52",X"44",X"2F",X"B2",X"84",X"34",X"54",X"48", + X"2F",X"B0",X"84",X"35",X"54",X"48",X"2F",X"AE",X"84",X"36",X"54",X"48",X"2F",X"AC",X"84",X"37", + X"54",X"48",X"2F",X"AA",X"84",X"38",X"54",X"48",X"2F",X"A8",X"84",X"39",X"54",X"48",X"2F",X"86", + X"84",X"31",X"30",X"54",X"48",X"2F",X"A7",X"85",X"53",X"54",X"41",X"54",X"49",X"4F",X"4E",X"2F", + X"A8",X"84",X"31",X"35",X"30",X"30",X"2F",X"D7",X"84",X"3F",X"3F",X"40",X"40",X"4C",X"4F",X"43", + X"4F",X"5B",X"4D",X"4F",X"54",X"49",X"4F",X"4E",X"40",X"40",X"3F",X"3F",X"2F",X"78",X"85",X"12", + X"10",X"16",X"14",X"1A",X"18",X"1E",X"1C",X"22",X"20",X"2F",X"77",X"85",X"13",X"11",X"17",X"15", + X"1B",X"19",X"1F",X"1D",X"23",X"21",X"2F",X"00",X"85",X"4C",X"49",X"43",X"45",X"4E",X"53",X"45", + X"44",X"40",X"42",X"59",X"40",X"4B",X"4F",X"4E",X"41",X"4D",X"49",X"2F",X"B6",X"85",X"12",X"10", + X"26",X"24",X"1A",X"2A",X"28",X"1C",X"22",X"20",X"2F",X"B5",X"85",X"13",X"11",X"27",X"25",X"1B", + X"2B",X"29",X"1D",X"23",X"21",X"2F",X"67",X"85",X"42",X"4F",X"4E",X"55",X"53",X"40",X"4C",X"49", + X"4E",X"45",X"2F",X"67",X"85",X"43",X"52",X"41",X"5A",X"59",X"40",X"54",X"52",X"41",X"49",X"4E", + X"2F",X"47",X"85",X"4C",X"4F",X"4F",X"50",X"40",X"53",X"57",X"45",X"45",X"50",X"45",X"52",X"2F", + X"74",X"85",X"42",X"4F",X"4E",X"55",X"53",X"2F",X"47",X"85",X"42",X"4F",X"4E",X"55",X"53",X"40", + X"53",X"54",X"41",X"54",X"49",X"4F",X"4E",X"2F",X"84",X"82",X"46",X"52",X"45",X"45",X"40",X"50", + X"4C",X"41",X"59",X"2F",X"D9",X"84",X"41",X"44",X"4A",X"55",X"53",X"54",X"40",X"52",X"41",X"49", + X"4C",X"40",X"57",X"41",X"59",X"40",X"4C",X"49",X"4E",X"45",X"53",X"2F",X"B7",X"84",X"53",X"4F", + X"40",X"41",X"53",X"40",X"54",X"4F",X"40",X"4C",X"45",X"54",X"40",X"59",X"4F",X"55",X"52",X"40", + X"54",X"52",X"41",X"49",X"4E",X"2F",X"B5",X"84",X"41",X"44",X"56",X"41",X"4E",X"43",X"45",X"40", + X"53",X"41",X"46",X"45",X"4C",X"59",X"2F",X"CF",X"85",X"41",X"4E",X"44",X"2F",X"11",X"85",X"40", + X"50",X"45",X"52",X"46",X"45",X"43",X"54",X"40",X"43",X"4C",X"45",X"41",X"52",X"40",X"2F",X"91", + X"85",X"40",X"43",X"4C",X"45",X"41",X"52",X"40",X"2F",X"6E",X"85",X"40",X"35",X"30",X"30",X"30", + X"40",X"50",X"54",X"53",X"40",X"2F",X"6E",X"85",X"40",X"31",X"30",X"30",X"30",X"40",X"50",X"54", + X"53",X"40",X"2F",X"31",X"8D",X"C3",X"C3",X"C3",X"C3",X"C3",X"C3",X"C3",X"C3",X"C3",X"C3",X"C3", + X"C3",X"C3",X"2F",X"8E",X"8D",X"C3",X"C3",X"C3",X"C3",X"C3",X"C3",X"C3",X"C3",X"2F",X"00",X"84", + X"2F",X"00",X"85",X"4C",X"49",X"43",X"45",X"4E",X"53",X"45",X"44",X"40",X"42",X"59",X"40",X"4B", + X"4F",X"4E",X"41",X"4D",X"49",X"2F",X"44",X"84",X"4D",X"4F",X"56",X"45",X"40",X"54",X"48",X"45", + X"40",X"4A",X"4F",X"59",X"53",X"54",X"49",X"43",X"4B",X"40",X"54",X"4F",X"40",X"53",X"45",X"4C", + X"45",X"43",X"54",X"2E",X"42",X"84",X"49",X"4E",X"49",X"54",X"49",X"41",X"4C",X"40",X"41",X"4E", + X"44",X"40",X"50",X"52",X"45",X"53",X"53",X"40",X"46",X"49",X"52",X"45",X"42",X"55",X"54",X"54", + X"4F",X"4E",X"2F",X"00",X"80",X"2F",X"3A",X"BE",X"98",X"B7",X"28",X"05",X"3E",X"26",X"C3",X"DB", + X"04",X"3E",X"0A",X"CD",X"DB",X"04",X"3A",X"12",X"98",X"FE",X"63",X"38",X"02",X"3E",X"63",X"CD", + X"CD",X"08",X"21",X"64",X"83",X"11",X"20",X"00",X"06",X"01",X"C3",X"A7",X"04",X"4F",X"0F",X"0F", + X"0F",X"0F",X"E6",X"0F",X"47",X"04",X"AF",X"81",X"27",X"0E",X"00",X"C6",X"06",X"27",X"30",X"01", + X"0C",X"10",X"F8",X"D6",X"06",X"27",X"D0",X"0D",X"C9",X"3A",X"00",X"99",X"01",X"C4",X"06",X"11", + X"E0",X"FF",X"21",X"04",X"81",X"B8",X"38",X"05",X"71",X"19",X"10",X"F9",X"C9",X"36",X"10",X"19", + X"10",X"F3",X"C9",X"3A",X"02",X"99",X"3C",X"01",X"C5",X"10",X"11",X"20",X"00",X"21",X"A4",X"81", + X"B8",X"38",X"05",X"71",X"19",X"10",X"F9",X"C9",X"36",X"10",X"19",X"10",X"F3",X"C9",X"C3",X"CD", + X"30",X"00",X"11",X"22",X"04",X"31",X"06",X"15",X"02",X"33",X"07",X"21",X"03",X"24",X"05",X"13", + X"01",X"00",X"00",X"01",X"30",X"85",X"00",X"90",X"76",X"00",X"30",X"70",X"00",X"80",X"62",X"00", + X"00",X"54",X"00",X"90",X"39",X"00",X"00",X"36",X"00",X"50",X"28",X"00",X"10",X"24",X"00",X"3A", + X"BE",X"98",X"B7",X"28",X"08",X"21",X"C0",X"21",X"E5",X"11",X"26",X"03",X"FF",X"21",X"7B",X"09", + X"E5",X"3A",X"01",X"98",X"CF",X"AF",X"15",X"8A",X"09",X"FB",X"09",X"29",X"0C",X"38",X"0D",X"43", + X"0E",X"41",X"10",X"75",X"22",X"49",X"10",X"72",X"10",X"A6",X"10",X"3A",X"12",X"98",X"B7",X"C8", + X"AF",X"21",X"00",X"98",X"34",X"2C",X"77",X"2C",X"77",X"C9",X"3A",X"03",X"98",X"CF",X"94",X"09", + X"34",X"0B",X"9D",X"10",X"3A",X"07",X"98",X"0F",X"D8",X"CD",X"91",X"11",X"3A",X"2C",X"98",X"FE", + X"20",X"D8",X"AF",X"32",X"2C",X"98",X"21",X"DB",X"09",X"CD",X"C4",X"11",X"21",X"40",X"98",X"01", + X"01",X"50",X"D7",X"3C",X"CD",X"61",X"11",X"1E",X"2A",X"FF",X"1E",X"04",X"FF",X"1C",X"FF",X"1E", + X"1D",X"FF",X"1C",X"FF",X"1C",X"FF",X"1C",X"FF",X"1E",X"4E",X"FF",X"3E",X"04",X"32",X"3E",X"98", + X"CD",X"6F",X"11",X"21",X"02",X"98",X"36",X"00",X"2C",X"34",X"C9",X"81",X"8C",X"9A",X"81",X"8C", + X"8C",X"8C",X"8C",X"95",X"95",X"95",X"95",X"90",X"90",X"91",X"91",X"91",X"91",X"91",X"91",X"91", + X"8E",X"8E",X"8E",X"8E",X"90",X"90",X"90",X"90",X"90",X"90",X"90",X"3A",X"03",X"98",X"CF",X"15", + X"0A",X"A7",X"0A",X"D3",X"0A",X"11",X"0B",X"47",X"0B",X"50",X"0B",X"79",X"0B",X"A1",X"0B",X"0F", + X"0C",X"18",X"0C",X"9D",X"10",X"3A",X"07",X"98",X"0F",X"D8",X"CD",X"91",X"11",X"3A",X"2C",X"98", + X"FE",X"20",X"D8",X"AF",X"32",X"2C",X"98",X"CD",X"61",X"11",X"CD",X"6F",X"11",X"21",X"83",X"0A", + X"CD",X"C4",X"11",X"11",X"03",X"03",X"FF",X"1E",X"0E",X"FF",X"21",X"A3",X"0A",X"11",X"40",X"98", + X"01",X"04",X"00",X"ED",X"B0",X"CD",X"7D",X"11",X"11",X"6E",X"85",X"21",X"1B",X"42",X"CD",X"31", + X"11",X"21",X"BB",X"44",X"CD",X"31",X"11",X"21",X"BB",X"43",X"3E",X"02",X"CD",X"1F",X"11",X"11", + X"6A",X"85",X"21",X"BB",X"44",X"CD",X"31",X"11",X"21",X"BB",X"44",X"CD",X"31",X"11",X"21",X"DB", + X"43",X"3E",X"02",X"CD",X"1F",X"11",X"3E",X"80",X"32",X"21",X"98",X"21",X"02",X"98",X"36",X"02", + X"2C",X"34",X"C9",X"81",X"8C",X"9A",X"81",X"8C",X"8C",X"8C",X"8C",X"8C",X"8C",X"8C",X"9A",X"8C", + X"9A",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"9A",X"9A",X"9A",X"9A",X"93", + X"93",X"93",X"93",X"C1",X"98",X"58",X"01",X"3A",X"07",X"98",X"0F",X"D0",X"21",X"42",X"98",X"34", + X"7E",X"FE",X"70",X"21",X"00",X"FF",X"28",X"06",X"FE",X"90",X"C0",X"21",X"80",X"FF",X"11",X"6A", + X"86",X"19",X"EB",X"21",X"DB",X"3C",X"CD",X"31",X"11",X"21",X"02",X"98",X"35",X"C0",X"36",X"40", + X"2C",X"34",X"C9",X"3A",X"07",X"98",X"0F",X"D0",X"3A",X"02",X"98",X"DD",X"21",X"40",X"98",X"01", + X"90",X"88",X"FD",X"21",X"02",X"98",X"21",X"FD",X"10",X"22",X"1B",X"99",X"CD",X"AB",X"10",X"FD", + X"35",X"00",X"C0",X"FD",X"34",X"01",X"11",X"6E",X"86",X"21",X"BB",X"42",X"3E",X"02",X"CD",X"1F", + X"11",X"11",X"6A",X"86",X"21",X"DB",X"42",X"3E",X"02",X"CD",X"1F",X"11",X"11",X"1B",X"03",X"FF", + X"C9",X"3A",X"02",X"98",X"C6",X"1F",X"E6",X"20",X"20",X"14",X"3E",X"20",X"21",X"48",X"04",X"E7", + X"E5",X"DD",X"E1",X"21",X"F4",X"85",X"CD",X"9F",X"04",X"CD",X"01",X"0C",X"18",X"06",X"21",X"F4", + X"85",X"CD",X"3C",X"0B",X"21",X"02",X"98",X"35",X"C0",X"2C",X"34",X"C9",X"11",X"20",X"00",X"01", + X"10",X"0A",X"71",X"19",X"10",X"FC",X"C9",X"11",X"9B",X"03",X"FF",X"21",X"03",X"98",X"34",X"C9", + X"3A",X"07",X"98",X"0F",X"D0",X"3A",X"02",X"98",X"DD",X"21",X"40",X"98",X"01",X"90",X"88",X"FD", + X"21",X"02",X"98",X"21",X"FD",X"10",X"22",X"1B",X"99",X"CD",X"AB",X"10",X"FD",X"35",X"00",X"FD", + X"7E",X"00",X"E6",X"3F",X"C0",X"FD",X"34",X"01",X"C9",X"3A",X"07",X"98",X"0F",X"D0",X"21",X"42", + X"98",X"35",X"7E",X"FE",X"70",X"28",X"11",X"FE",X"6C",X"C0",X"3E",X"03",X"32",X"17",X"98",X"11", + X"21",X"03",X"FF",X"21",X"03",X"98",X"34",X"C9",X"11",X"EE",X"85",X"21",X"DB",X"3C",X"C3",X"31", + X"11",X"3A",X"02",X"98",X"C6",X"1F",X"E6",X"20",X"20",X"43",X"3E",X"2F",X"21",X"48",X"04",X"E7", + X"E5",X"DD",X"E1",X"21",X"14",X"85",X"CD",X"9F",X"04",X"CD",X"01",X"0C",X"CD",X"34",X"0B",X"3A", + X"07",X"98",X"E6",X"0F",X"C0",X"21",X"17",X"98",X"35",X"7E",X"20",X"02",X"36",X"03",X"87",X"F5", + X"21",X"F5",X"0B",X"E7",X"5E",X"23",X"56",X"EB",X"11",X"6E",X"85",X"CD",X"43",X"11",X"F1",X"21", + X"FB",X"0B",X"E7",X"5E",X"23",X"56",X"EB",X"11",X"6A",X"85",X"C3",X"43",X"11",X"21",X"14",X"85", + X"CD",X"3C",X"0B",X"18",X"C7",X"FB",X"41",X"3B",X"42",X"5B",X"42",X"DB",X"3C",X"DB",X"40",X"DB", + X"3C",X"01",X"20",X"00",X"11",X"0B",X"0C",X"09",X"C3",X"08",X"05",X"50",X"54",X"53",X"2F",X"11", + X"A1",X"03",X"FF",X"21",X"03",X"98",X"34",X"C9",X"21",X"40",X"98",X"01",X"01",X"40",X"AF",X"D7", + X"21",X"03",X"98",X"34",X"AF",X"32",X"17",X"98",X"C9",X"3A",X"03",X"98",X"CF",X"9A",X"0C",X"D2", + X"0C",X"08",X"0D",X"3F",X"0C",X"45",X"0C",X"8B",X"0C",X"34",X"0B",X"18",X"0C",X"9D",X"10",X"CD", + X"4B",X"0C",X"C3",X"A7",X"0A",X"CD",X"4B",X"0C",X"C3",X"D3",X"0A",X"3A",X"07",X"98",X"E6",X"1F", + X"C0",X"DD",X"21",X"1F",X"99",X"DD",X"7E",X"FE",X"D6",X"10",X"27",X"DD",X"77",X"FE",X"DD",X"7E", + X"FF",X"DE",X"00",X"27",X"DD",X"77",X"FF",X"21",X"F4",X"85",X"CD",X"9F",X"04",X"CD",X"01",X"0C", + X"21",X"1E",X"99",X"11",X"6F",X"86",X"7E",X"CD",X"7C",X"0C",X"2D",X"7E",X"0F",X"0F",X"0F",X"0F", + X"CD",X"84",X"0C",X"7E",X"E6",X"0F",X"C6",X"2C",X"12",X"1D",X"C9",X"CD",X"7D",X"11",X"11",X"25", + X"03",X"FF",X"1E",X"24",X"FF",X"21",X"03",X"98",X"34",X"C9",X"3A",X"07",X"98",X"0F",X"D8",X"CD", + X"91",X"11",X"3A",X"2C",X"98",X"FE",X"20",X"D8",X"AF",X"32",X"2C",X"98",X"CD",X"61",X"11",X"CD", + X"6F",X"11",X"21",X"83",X"0A",X"CD",X"C4",X"11",X"11",X"03",X"03",X"FF",X"1E",X"0E",X"FF",X"21", + X"A3",X"0A",X"11",X"40",X"98",X"01",X"04",X"00",X"ED",X"B0",X"CD",X"7D",X"11",X"21",X"03",X"98", + X"34",X"C9",X"11",X"6E",X"85",X"21",X"BB",X"3C",X"CD",X"31",X"11",X"21",X"FB",X"40",X"CD",X"31", + X"11",X"21",X"BB",X"43",X"3E",X"02",X"CD",X"1F",X"11",X"11",X"6A",X"85",X"21",X"BB",X"44",X"CD", + X"31",X"11",X"21",X"7B",X"41",X"CD",X"31",X"11",X"21",X"DB",X"43",X"3E",X"02",X"CD",X"1F",X"11", + X"21",X"02",X"98",X"36",X"02",X"2C",X"34",X"C9",X"11",X"30",X"0D",X"21",X"00",X"15",X"22",X"1D", + X"99",X"21",X"9A",X"9A",X"22",X"6C",X"8E",X"22",X"6E",X"8E",X"EB",X"11",X"6C",X"86",X"01",X"04", + X"00",X"ED",X"B0",X"21",X"03",X"98",X"34",X"C9",X"11",X"34",X"0D",X"21",X"40",X"00",X"18",X"DE", + X"2C",X"2C",X"31",X"2D",X"2C",X"30",X"2C",X"2C",X"3A",X"03",X"98",X"CF",X"9A",X"0C",X"4E",X"0D", + X"28",X"0D",X"94",X"0D",X"A6",X"0D",X"BD",X"0D",X"E1",X"0F",X"18",X"0C",X"9D",X"10",X"FD",X"21", + X"00",X"9D",X"FD",X"36",X"00",X"00",X"FD",X"36",X"01",X"00",X"FD",X"36",X"1F",X"01",X"11",X"6E", + X"85",X"21",X"9B",X"44",X"CD",X"31",X"11",X"21",X"FB",X"44",X"CD",X"31",X"11",X"21",X"BB",X"43", + X"3E",X"02",X"CD",X"1F",X"11",X"11",X"6A",X"85",X"21",X"9B",X"40",X"CD",X"31",X"11",X"21",X"1B", + X"45",X"CD",X"31",X"11",X"21",X"DB",X"43",X"3E",X"02",X"CD",X"1F",X"11",X"21",X"02",X"98",X"36", + X"02",X"2C",X"34",X"C9",X"CD",X"4B",X"0C",X"CD",X"C6",X"0D",X"21",X"1D",X"99",X"7E",X"2C",X"B6", + X"C0",X"21",X"03",X"98",X"34",X"C9",X"21",X"18",X"02",X"22",X"20",X"9D",X"7C",X"32",X"47",X"98", + X"0F",X"32",X"3F",X"9D",X"11",X"22",X"03",X"FF",X"21",X"03",X"98",X"34",X"C9",X"CD",X"09",X"0F", + X"CD",X"C6",X"0D",X"C3",X"7A",X"0F",X"21",X"ED",X"0D",X"E5",X"DD",X"21",X"40",X"98",X"FD",X"21", + X"00",X"9D",X"21",X"FD",X"10",X"22",X"1B",X"99",X"FD",X"7E",X"01",X"FD",X"77",X"1E",X"CF",X"B9", + X"0F",X"C3",X"0F",X"C3",X"0F",X"A0",X"0F",X"C3",X"0F",X"C3",X"0F",X"C3",X"0F",X"FD",X"7E",X"1E", + X"FD",X"BE",X"01",X"C8",X"FE",X"05",X"C8",X"B7",X"20",X"08",X"FD",X"36",X"1F",X"FF",X"FD",X"36", + X"00",X"C0",X"FE",X"04",X"20",X"07",X"CD",X"0D",X"0E",X"FD",X"7E",X"1E",X"3C",X"87",X"87",X"21", + X"27",X"0E",X"E7",X"5E",X"23",X"56",X"23",X"7E",X"23",X"66",X"6F",X"FD",X"7E",X"1E",X"FE",X"04", + X"C2",X"31",X"11",X"0F",X"C3",X"1F",X"11",X"EE",X"85",X"9B",X"44",X"6E",X"85",X"BB",X"3C",X"6A", + X"85",X"9B",X"3C",X"EA",X"85",X"DB",X"40",X"6A",X"86",X"DB",X"42",X"6E",X"86",X"BB",X"42",X"EE", + X"85",X"BB",X"3C",X"3A",X"03",X"98",X"CF",X"51",X"0E",X"CD",X"0E",X"E1",X"0F",X"18",X"0C",X"9D", + X"10",X"3A",X"07",X"98",X"0F",X"D8",X"CD",X"91",X"11",X"3A",X"2C",X"98",X"FE",X"20",X"D8",X"AF", + X"32",X"2C",X"98",X"CD",X"61",X"11",X"CD",X"6F",X"11",X"21",X"83",X"0A",X"CD",X"C4",X"11",X"11", + X"03",X"03",X"FF",X"1E",X"0E",X"FF",X"21",X"C5",X"0E",X"11",X"40",X"98",X"01",X"08",X"00",X"ED", + X"B0",X"3E",X"FF",X"32",X"1F",X"9D",X"32",X"3F",X"9D",X"ED",X"43",X"20",X"9D",X"21",X"C0",X"04", + X"22",X"00",X"9D",X"11",X"6E",X"85",X"21",X"9B",X"44",X"CD",X"31",X"11",X"21",X"BB",X"44",X"CD", + X"31",X"11",X"21",X"7B",X"44",X"CD",X"31",X"11",X"11",X"6A",X"85",X"21",X"FB",X"40",X"CD",X"31", + X"11",X"21",X"BB",X"44",X"CD",X"31",X"11",X"21",X"BB",X"40",X"CD",X"31",X"11",X"21",X"02",X"98", + X"36",X"40",X"2C",X"34",X"C9",X"E1",X"78",X"78",X"01",X"D4",X"98",X"8C",X"07",X"CD",X"1E",X"0F", + X"3A",X"1F",X"99",X"B7",X"28",X"06",X"CD",X"43",X"0F",X"C3",X"7A",X"0F",X"3A",X"07",X"98",X"E6", + X"04",X"21",X"00",X"00",X"28",X"03",X"2A",X"CA",X"0E",X"22",X"45",X"98",X"3A",X"42",X"98",X"FE", + X"7C",X"D8",X"3E",X"03",X"32",X"22",X"9D",X"32",X"1F",X"99",X"3C",X"32",X"47",X"98",X"2A",X"CA", + X"0E",X"22",X"45",X"98",X"11",X"23",X"03",X"FF",X"C9",X"3A",X"07",X"98",X"0F",X"D8",X"DD",X"21", + X"44",X"98",X"FD",X"21",X"20",X"9D",X"21",X"ED",X"10",X"22",X"1B",X"99",X"18",X"13",X"3A",X"07", + X"98",X"0F",X"D0",X"21",X"FD",X"10",X"22",X"1B",X"99",X"DD",X"21",X"40",X"98",X"FD",X"21",X"00", + X"9D",X"FD",X"7E",X"01",X"CF",X"A0",X"0F",X"BE",X"0F",X"BE",X"0F",X"A9",X"0F",X"C3",X"0F",X"C3", + X"0F",X"DC",X"0F",X"DD",X"21",X"44",X"98",X"FD",X"21",X"20",X"9D",X"3A",X"07",X"98",X"0F",X"30", + X"14",X"FD",X"35",X"02",X"FD",X"7E",X"02",X"20",X"04",X"FD",X"36",X"02",X"03",X"21",X"74",X"0F", + X"E7",X"7E",X"DD",X"77",X"00",X"FD",X"7E",X"01",X"B7",X"28",X"C6",X"FE",X"03",X"28",X"C2",X"FD", + X"35",X"00",X"18",X"BD",X"CC",X"D0",X"D4",X"05",X"06",X"07",X"DD",X"21",X"40",X"98",X"DD",X"7E", + X"01",X"DD",X"96",X"05",X"30",X"02",X"ED",X"44",X"FE",X"0C",X"D0",X"DD",X"7E",X"02",X"DD",X"96", + X"06",X"30",X"02",X"ED",X"44",X"FE",X"0C",X"D0",X"21",X"02",X"98",X"36",X"80",X"2C",X"34",X"C9", + X"11",X"01",X"90",X"FD",X"36",X"00",X"40",X"18",X"03",X"11",X"FF",X"70",X"DD",X"7E",X"02",X"83", + X"DD",X"77",X"02",X"BA",X"C0",X"FD",X"34",X"01",X"C9",X"01",X"70",X"68",X"18",X"08",X"01",X"90", + X"88",X"18",X"03",X"01",X"70",X"88",X"FD",X"7E",X"00",X"CD",X"AB",X"10",X"FD",X"7E",X"1F",X"FD", + X"86",X"00",X"FD",X"77",X"00",X"E6",X"3F",X"C0",X"FD",X"34",X"01",X"C9",X"FD",X"36",X"01",X"00", + X"C9",X"DD",X"21",X"40",X"98",X"CD",X"EF",X"0F",X"DD",X"21",X"44",X"98",X"C3",X"12",X"10",X"11", + X"31",X"10",X"21",X"02",X"98",X"35",X"7E",X"20",X"02",X"2C",X"34",X"0F",X"0F",X"E6",X"03",X"EB", + X"E7",X"7E",X"DD",X"77",X"00",X"3E",X"04",X"E7",X"7E",X"DD",X"77",X"03",X"C9",X"11",X"39",X"10", + X"18",X"E0",X"3A",X"3F",X"9D",X"07",X"30",X"F5",X"21",X"22",X"9D",X"35",X"7E",X"20",X"02",X"36", + X"03",X"21",X"74",X"0F",X"E7",X"7E",X"DD",X"77",X"00",X"3E",X"03",X"E7",X"7E",X"DD",X"77",X"03", + X"C9",X"F1",X"E1",X"D1",X"C1",X"10",X"0C",X"04",X"08",X"83",X"81",X"93",X"91",X"1A",X"09",X"08", + X"07",X"CD",X"6D",X"22",X"21",X"01",X"98",X"34",X"C9",X"CD",X"55",X"11",X"CD",X"92",X"15",X"CD", + X"55",X"11",X"FE",X"03",X"20",X"17",X"11",X"0E",X"03",X"FF",X"1E",X"03",X"FF",X"C9",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FE",X"05",X"C0", + X"34",X"C9",X"3A",X"03",X"98",X"CF",X"7C",X"10",X"34",X"0B",X"9D",X"10",X"3A",X"07",X"98",X"0F", + X"D8",X"CD",X"91",X"11",X"3A",X"2C",X"98",X"FE",X"20",X"D8",X"AF",X"32",X"2C",X"98",X"CD",X"61", + X"11",X"CD",X"6F",X"11",X"11",X"01",X"08",X"FF",X"21",X"03",X"98",X"34",X"C9",X"21",X"03",X"98", + X"36",X"00",X"2D",X"2D",X"34",X"C9",X"AF",X"32",X"01",X"98",X"C9",X"6F",X"CB",X"3F",X"AD",X"ED", + X"47",X"11",X"7A",X"4D",X"26",X"00",X"29",X"19",X"CD",X"0D",X"11",X"80",X"DD",X"77",X"01",X"EB", + X"23",X"CD",X"0D",X"11",X"81",X"DD",X"77",X"02",X"FD",X"7E",X"00",X"E6",X"0F",X"FE",X"08",X"C0", + X"FD",X"AE",X"00",X"0F",X"0F",X"0F",X"0F",X"FD",X"CB",X"1F",X"7E",X"20",X"04",X"C6",X"09",X"E6", + X"0F",X"4F",X"06",X"00",X"2A",X"1B",X"99",X"09",X"7E",X"DD",X"77",X"00",X"C9",X"91",X"8D",X"89", + X"85",X"81",X"9D",X"99",X"95",X"91",X"8D",X"89",X"85",X"81",X"9D",X"99",X"95",X"D1",X"CD",X"C9", + X"C5",X"C1",X"FD",X"F9",X"F5",X"F1",X"ED",X"E9",X"E5",X"E1",X"DD",X"D9",X"D5",X"5E",X"16",X"00", + X"EB",X"29",X"29",X"29",X"29",X"ED",X"57",X"07",X"ED",X"47",X"7C",X"D0",X"ED",X"44",X"C9",X"ED", + X"A0",X"ED",X"A0",X"ED",X"A0",X"ED",X"A0",X"01",X"1C",X"00",X"EB",X"09",X"EB",X"3D",X"20",X"EF", + X"C9",X"D5",X"3E",X"04",X"CD",X"1F",X"11",X"EB",X"E3",X"EB",X"CB",X"DA",X"3E",X"04",X"CD",X"1F", + X"11",X"D1",X"C9",X"D5",X"3E",X"04",X"CD",X"1F",X"11",X"EB",X"E3",X"EB",X"CB",X"DA",X"3E",X"04", + X"CD",X"1F",X"11",X"D1",X"C9",X"11",X"01",X"98",X"21",X"17",X"98",X"4E",X"1A",X"EB",X"71",X"12", + X"C9",X"11",X"00",X"03",X"FF",X"1C",X"FF",X"1C",X"3A",X"0A",X"98",X"B7",X"20",X"FF",X"C9",X"11", + X"00",X"02",X"FF",X"1C",X"3A",X"0A",X"98",X"B7",X"20",X"FF",X"1C",X"FF",X"C9",X"21",X"6A",X"8E", + X"11",X"18",X"00",X"0E",X"02",X"06",X"08",X"36",X"C0",X"23",X"10",X"FB",X"0D",X"19",X"20",X"F5", + X"C9",X"21",X"B7",X"11",X"E5",X"3A",X"2C",X"98",X"3C",X"32",X"2C",X"98",X"6F",X"26",X"00",X"E6", + X"1E",X"BD",X"20",X"03",X"25",X"ED",X"44",X"6F",X"29",X"29",X"29",X"29",X"11",X"00",X"86",X"19", + X"3E",X"10",X"01",X"01",X"1C",X"D7",X"C9",X"7D",X"E6",X"E0",X"6F",X"CB",X"94",X"01",X"01",X"08", + X"3E",X"10",X"D7",X"C9",X"22",X"30",X"98",X"11",X"04",X"88",X"01",X"04",X"00",X"CD",X"DC",X"11", + X"2A",X"30",X"98",X"3E",X"04",X"E7",X"11",X"00",X"8C",X"01",X"1C",X"00",X"D9",X"06",X"20",X"D9", + X"C5",X"ED",X"B0",X"C1",X"B7",X"ED",X"42",X"EB",X"ED",X"42",X"3E",X"20",X"E7",X"EB",X"D9",X"10", + X"EE",X"C9",X"21",X"10",X"39",X"10",X"1C",X"01",X"0A",X"01",X"2B",X"01",X"09",X"20",X"0C",X"20", + X"40",X"02",X"30",X"20",X"36",X"01",X"25",X"10",X"08",X"10",X"50",X"02",X"20",X"20",X"20",X"02", + X"50",X"10",X"40",X"02",X"40",X"20",X"40",X"20",X"40",X"20",X"40",X"00",X"40",X"00",X"40",X"00", + X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"01",X"40",X"20",X"40",X"00",X"40",X"00", + X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"02",X"40",X"20",X"40",X"00", + X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"01",X"40",X"01", + X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"10",X"40",X"00",X"40",X"00",X"40",X"00", + X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00", + X"40",X"00",X"40",X"00",X"40",X"10",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00", + X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"20",X"40",X"00",X"40",X"00", + X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00", + X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00", + X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"3A",X"09",X"99",X"B7",X"C8",X"FD", + X"E5",X"E1",X"4F",X"06",X"03",X"2C",X"AF",X"86",X"86",X"2C",X"10",X"FB",X"06",X"06",X"86",X"2C", + X"10",X"FC",X"FE",X"1E",X"D8",X"41",X"3E",X"F0",X"A5",X"6F",X"D9",X"CD",X"8F",X"01",X"E6",X"1E", + X"21",X"FE",X"12",X"E7",X"7E",X"B7",X"28",X"F3",X"23",X"08",X"7E",X"D9",X"B5",X"6F",X"7E",X"B7", + X"28",X"E4",X"35",X"3E",X"F0",X"A5",X"6F",X"08",X"B5",X"6F",X"34",X"10",X"D9",X"C9",X"00",X"00", + X"04",X"01",X"06",X"02",X"08",X"03",X"0B",X"04",X"0B",X"05",X"0B",X"06",X"0B",X"07",X"0B",X"08", + X"0B",X"09",X"00",X"00",X"00",X"00",X"00",X"00",X"05",X"01",X"07",X"02",X"09",X"03",X"06",X"40", + X"1A",X"E6",X"3F",X"FE",X"10",X"30",X"06",X"B5",X"6F",X"34",X"E6",X"F0",X"6F",X"13",X"10",X"F0", + X"3E",X"0F",X"B5",X"6F",X"06",X"03",X"7E",X"36",X"00",X"2D",X"86",X"36",X"00",X"10",X"FA",X"77", + X"C9",X"21",X"02",X"99",X"3E",X"03",X"BE",X"38",X"01",X"7E",X"87",X"87",X"87",X"ED",X"44",X"C6", + X"80",X"2C",X"77",X"2E",X"07",X"36",X"04",X"3A",X"02",X"99",X"FE",X"08",X"38",X"02",X"3E",X"07", + X"87",X"21",X"9F",X"13",X"E7",X"4E",X"23",X"46",X"ED",X"43",X"0C",X"99",X"3A",X"02",X"99",X"47", + X"E6",X"0F",X"4F",X"A8",X"0F",X"47",X"0F",X"0F",X"80",X"81",X"E6",X"07",X"21",X"96",X"13",X"E7", + X"7E",X"32",X"06",X"99",X"47",X"E6",X"0E",X"4F",X"A8",X"0F",X"0F",X"0F",X"0F",X"E6",X"0E",X"81", + X"6F",X"67",X"22",X"09",X"99",X"C9",X"44",X"54",X"64",X"45",X"56",X"55",X"65",X"66",X"46",X"18", + X"00",X"10",X"01",X"0C",X"02",X"0A",X"03",X"08",X"04",X"06",X"05",X"05",X"06",X"04",X"07",X"11", + X"A0",X"99",X"21",X"C2",X"13",X"01",X"10",X"00",X"ED",X"B0",X"21",X"C2",X"13",X"0E",X"10",X"ED", + X"B0",X"C9",X"01",X"08",X"08",X"08",X"01",X"02",X"02",X"01",X"02",X"02",X"00",X"00",X"01",X"00", + X"00",X"00",X"3A",X"02",X"99",X"87",X"87",X"87",X"6F",X"67",X"22",X"0E",X"99",X"01",X"01",X"40", + X"3E",X"FF",X"DD",X"E5",X"E1",X"D7",X"CD",X"C4",X"14",X"CD",X"65",X"14",X"CD",X"53",X"15",X"CD", + X"3C",X"14",X"C9",X"3A",X"08",X"99",X"D6",X"04",X"2E",X"00",X"67",X"22",X"06",X"9D",X"E6",X"F0", + X"6F",X"AC",X"87",X"87",X"87",X"87",X"67",X"11",X"10",X"10",X"19",X"22",X"04",X"9D",X"3A",X"07", + X"9D",X"6F",X"26",X"9A",X"6E",X"26",X"00",X"29",X"29",X"29",X"3E",X"04",X"E7",X"11",X"3B",X"45", + X"19",X"5E",X"23",X"56",X"ED",X"53",X"08",X"9D",X"11",X"82",X"99",X"3A",X"09",X"98",X"B7",X"28", + X"02",X"1E",X"92",X"01",X"08",X"00",X"21",X"02",X"9D",X"ED",X"B0",X"C9",X"DD",X"E5",X"E1",X"FD", + X"E5",X"D1",X"01",X"00",X"10",X"1A",X"B7",X"28",X"17",X"7D",X"E6",X"C0",X"6F",X"D9",X"CD",X"8F", + X"01",X"D9",X"E6",X"3F",X"B5",X"6F",X"7E",X"3C",X"20",X"EF",X"71",X"EB",X"35",X"EB",X"20",X"E9", + X"0C",X"13",X"10",X"E1",X"C9",X"3A",X"06",X"99",X"4F",X"E6",X"0F",X"47",X"A9",X"0F",X"0F",X"0F", + X"0F",X"4F",X"ED",X"43",X"24",X"98",X"0E",X"24",X"11",X"18",X"19",X"DD",X"E5",X"E1",X"CD",X"B1", + X"14",X"ED",X"4B",X"24",X"98",X"58",X"41",X"16",X"00",X"4A",X"1C",X"CB",X"38",X"30",X"01",X"0C", + X"36",X"1E",X"19",X"36",X"1C",X"2C",X"36",X"1F",X"19",X"36",X"1D",X"2C",X"10",X"F2",X"CB",X"41", + X"28",X"06",X"36",X"23",X"19",X"36",X"22",X"2C",X"3A",X"25",X"98",X"47",X"0E",X"21",X"11",X"1A", + X"1B",X"36",X"20",X"2C",X"CB",X"38",X"30",X"02",X"71",X"2C",X"72",X"2C",X"73",X"2C",X"10",X"FA", + X"36",X"20",X"2C",X"C9",X"3A",X"06",X"99",X"47",X"E6",X"03",X"4F",X"A8",X"0F",X"0F",X"E6",X"0C", + X"B1",X"87",X"21",X"3D",X"15",X"E7",X"7E",X"32",X"08",X"99",X"23",X"7E",X"5F",X"AF",X"57",X"DD", + X"E5",X"E1",X"19",X"77",X"FD",X"35",X"00",X"CD",X"13",X"15",X"23",X"D9",X"FD",X"E5",X"C1",X"CD", + X"8F",X"01",X"E6",X"07",X"28",X"F9",X"21",X"0B",X"15",X"E7",X"7E",X"57",X"60",X"69",X"E7",X"35", + X"F2",X"07",X"15",X"34",X"C3",X"EF",X"14",X"7A",X"D9",X"77",X"C9",X"00",X"01",X"02",X"03",X"05", + X"07",X"09",X"0C",X"2B",X"2B",X"FD",X"7E",X"03",X"B7",X"28",X"06",X"36",X"03",X"FD",X"35",X"03", + X"C9",X"FD",X"7E",X"09",X"B7",X"28",X"06",X"36",X"09",X"FD",X"35",X"09",X"C9",X"36",X"09",X"AF", + X"06",X"0F",X"FD",X"E5",X"D1",X"EB",X"23",X"B6",X"28",X"FC",X"35",X"EB",X"C9",X"8A",X"16",X"89", + X"19",X"8A",X"1D",X"00",X"00",X"7A",X"16",X"79",X"19",X"7A",X"1D",X"00",X"00",X"8A",X"1C",X"89", + X"20",X"8A",X"25",X"3A",X"06",X"99",X"C6",X"11",X"47",X"E6",X"0F",X"4F",X"A8",X"0F",X"0F",X"0F", + X"0F",X"81",X"87",X"ED",X"44",X"C6",X"1C",X"C8",X"47",X"36",X"20",X"2C",X"10",X"FB",X"7D",X"E6", + X"3F",X"2F",X"C6",X"40",X"47",X"04",X"FD",X"E5",X"D1",X"EB",X"7D",X"6F",X"D9",X"CD",X"8F",X"01", + X"D9",X"E6",X"0F",X"12",X"B5",X"6F",X"E6",X"F0",X"35",X"34",X"28",X"EF",X"35",X"6F",X"13",X"10", + X"EA",X"C9",X"CD",X"01",X"17",X"3A",X"01",X"98",X"CF",X"AF",X"15",X"E3",X"15",X"BE",X"16",X"7D", + X"17",X"6C",X"18",X"DC",X"18",X"30",X"19",X"A8",X"19",X"F1",X"19",X"D9",X"1A",X"54",X"1D",X"AF", + X"21",X"40",X"98",X"01",X"01",X"50",X"D7",X"21",X"00",X"9D",X"01",X"02",X"00",X"D7",X"21",X"00", + X"9A",X"01",X"02",X"00",X"D7",X"21",X"00",X"99",X"01",X"01",X"80",X"D7",X"21",X"01",X"98",X"34", + X"AF",X"32",X"2C",X"98",X"32",X"03",X"98",X"3A",X"08",X"98",X"47",X"3A",X"BE",X"98",X"A0",X"32", + X"20",X"98",X"C9",X"CD",X"1E",X"16",X"3A",X"0A",X"98",X"B7",X"C4",X"4E",X"16",X"3A",X"08",X"98", + X"B7",X"28",X"1A",X"11",X"0B",X"03",X"ED",X"53",X"24",X"98",X"21",X"01",X"98",X"34",X"2C",X"36", + X"00",X"3A",X"08",X"98",X"B7",X"C4",X"91",X"20",X"AF",X"32",X"2C",X"98",X"C9",X"21",X"01",X"98", + X"34",X"2C",X"36",X"01",X"AF",X"32",X"2C",X"98",X"3E",X"25",X"32",X"20",X"99",X"C9",X"11",X"80", + X"99",X"21",X"6D",X"17",X"01",X"10",X"00",X"ED",X"B0",X"3A",X"0C",X"98",X"32",X"00",X"99",X"CD", + X"AF",X"13",X"CD",X"41",X"13",X"DD",X"21",X"00",X"9B",X"FD",X"21",X"A0",X"99",X"CD",X"D2",X"13", + X"DD",X"21",X"00",X"99",X"21",X"00",X"9B",X"CD",X"0D",X"1C",X"CD",X"F3",X"13",X"C9",X"21",X"00", + X"99",X"11",X"60",X"99",X"01",X"20",X"00",X"ED",X"B0",X"21",X"80",X"99",X"11",X"90",X"99",X"0E", + X"10",X"ED",X"B0",X"11",X"40",X"9B",X"21",X"00",X"9B",X"0E",X"40",X"ED",X"B0",X"C9",X"81",X"8C", + X"9A",X"81",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80", + X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"3A",X"08", + X"98",X"B7",X"28",X"0B",X"ED",X"5B",X"24",X"98",X"FF",X"3A",X"0A",X"98",X"B7",X"28",X"08",X"11", + X"01",X"02",X"FF",X"11",X"02",X"03",X"FF",X"11",X"00",X"02",X"FF",X"1E",X"02",X"FF",X"11",X"01", + X"03",X"FF",X"1D",X"FF",X"21",X"2C",X"98",X"34",X"21",X"6E",X"16",X"C3",X"C4",X"11",X"3A",X"2C", + X"98",X"FE",X"21",X"30",X"16",X"3A",X"07",X"98",X"0F",X"D8",X"3E",X"10",X"CD",X"91",X"11",X"3A", + X"2C",X"98",X"FE",X"20",X"D8",X"11",X"0E",X"03",X"FF",X"18",X"B3",X"21",X"02",X"98",X"35",X"28", + X"11",X"3E",X"07",X"A6",X"C0",X"3E",X"18",X"A6",X"ED",X"5B",X"24",X"98",X"20",X"02",X"CB",X"FB", + X"FF",X"C9",X"36",X"40",X"2D",X"34",X"11",X"CB",X"03",X"FF",X"1E",X"8E",X"FF",X"CD",X"20",X"17", + X"C9",X"3A",X"08",X"98",X"0F",X"D0",X"3A",X"07",X"98",X"47",X"E6",X"07",X"C0",X"11",X"01",X"03", + X"3A",X"09",X"98",X"0F",X"30",X"01",X"1C",X"3E",X"18",X"A0",X"20",X"02",X"CB",X"FB",X"FF",X"C9", + X"3A",X"06",X"99",X"ED",X"44",X"C6",X"66",X"32",X"38",X"98",X"C9",X"3A",X"06",X"99",X"47",X"3A", + X"38",X"98",X"ED",X"44",X"C6",X"66",X"B8",X"3A",X"38",X"98",X"CD",X"CD",X"30",X"3A",X"38",X"98", + X"CD",X"47",X"17",X"32",X"38",X"98",X"C9",X"4F",X"E6",X"F0",X"47",X"A9",X"4F",X"3A",X"06",X"99", + X"C6",X"88",X"5F",X"E6",X"F0",X"57",X"AB",X"5F",X"B9",X"20",X"0A",X"78",X"BA",X"30",X"0B",X"7B", + X"2F",X"C6",X"2F",X"80",X"C9",X"3E",X"02",X"80",X"81",X"C9",X"3E",X"FF",X"C9",X"01",X"00",X"90", + X"50",X"A0",X"30",X"F0",X"84",X"00",X"02",X"00",X"00",X"D1",X"01",X"01",X"C1",X"3A",X"38",X"98", + X"3C",X"28",X"3A",X"CD",X"2B",X"17",X"3A",X"38",X"98",X"3C",X"C0",X"11",X"00",X"9D",X"21",X"80", + X"99",X"01",X"10",X"00",X"3A",X"09",X"98",X"B7",X"28",X"02",X"2E",X"90",X"ED",X"B0",X"21",X"00", + X"99",X"35",X"CD",X"15",X"18",X"CD",X"EF",X"24",X"CD",X"E9",X"17",X"11",X"00",X"06",X"FF",X"11", + X"00",X"05",X"FF",X"3A",X"0C",X"99",X"32",X"9B",X"9C",X"C3",X"D1",X"1C",X"C9",X"21",X"02",X"98", + X"35",X"C0",X"3A",X"0A",X"99",X"B7",X"28",X"16",X"21",X"01",X"98",X"34",X"2C",X"2C",X"36",X"00", + X"3E",X"10",X"32",X"98",X"9C",X"CD",X"82",X"20",X"CD",X"7B",X"2E",X"C3",X"13",X"20",X"21",X"08", + X"C0",X"22",X"01",X"98",X"AF",X"32",X"2C",X"98",X"C9",X"3A",X"08",X"9D",X"21",X"F5",X"17",X"E7", + X"7E",X"32",X"0C",X"9D",X"C9",X"D1",X"F1",X"C1",X"E1",X"F1",X"C1",X"F1",X"E1",X"C1",X"D1",X"D1", + X"E1",X"F1",X"C1",X"D1",X"E1",X"F1",X"F1",X"C1",X"C1",X"F1",X"F1",X"E1",X"E1",X"C1",X"C1",X"D1", + X"D1",X"D1",X"D1",X"E1",X"E1",X"11",X"30",X"9D",X"21",X"2C",X"18",X"3E",X"04",X"01",X"10",X"00", + X"EB",X"09",X"EB",X"ED",X"B0",X"3D",X"20",X"F5",X"CD",X"58",X"24",X"C9",X"00",X"00",X"10",X"70", + X"A0",X"30",X"F0",X"06",X"00",X"02",X"00",X"00",X"81",X"03",X"01",X"81",X"00",X"00",X"10",X"B0", + X"A0",X"30",X"F0",X"0A",X"00",X"02",X"00",X"00",X"81",X"02",X"01",X"81",X"00",X"00",X"F0",X"30", + X"A0",X"30",X"F0",X"E2",X"00",X"02",X"00",X"00",X"81",X"02",X"01",X"81",X"00",X"00",X"F0",X"70", + X"A0",X"30",X"F0",X"E6",X"00",X"02",X"00",X"00",X"81",X"02",X"01",X"81",X"CD",X"AE",X"33",X"CD", + X"C1",X"3B",X"CD",X"D1",X"1C",X"CD",X"CE",X"26",X"CD",X"7E",X"2A",X"3A",X"07",X"98",X"E6",X"0F", + X"CC",X"22",X"20",X"3A",X"00",X"9D",X"B7",X"C0",X"CD",X"EF",X"1F",X"DD",X"21",X"00",X"9D",X"DD", + X"36",X"06",X"F0",X"CD",X"3F",X"35",X"CD",X"B3",X"32",X"CD",X"98",X"35",X"3E",X"01",X"32",X"0D", + X"9D",X"11",X"80",X"99",X"21",X"00",X"9D",X"36",X"01",X"01",X"10",X"00",X"3A",X"09",X"98",X"B7", + X"28",X"02",X"1E",X"90",X"ED",X"B0",X"AF",X"32",X"2C",X"98",X"21",X"40",X"98",X"01",X"01",X"50", + X"D7",X"21",X"A0",X"99",X"01",X"01",X"12",X"D7",X"21",X"98",X"9C",X"01",X"01",X"68",X"D7",X"21", + X"80",X"9B",X"01",X"01",X"08",X"D7",X"21",X"01",X"98",X"36",X"05",X"C9",X"CD",X"95",X"11",X"3A", + X"2C",X"98",X"FE",X"20",X"D8",X"21",X"6E",X"16",X"CD",X"C4",X"11",X"AF",X"21",X"20",X"99",X"01", + X"01",X"20",X"D7",X"21",X"00",X"9D",X"01",X"02",X"00",X"D7",X"3E",X"08",X"32",X"89",X"9B",X"3A", + X"00",X"99",X"B7",X"20",X"0A",X"3E",X"0A",X"32",X"01",X"98",X"AF",X"32",X"03",X"98",X"C9",X"CD", + X"20",X"17",X"CD",X"FF",X"1B",X"28",X"06",X"3E",X"06",X"32",X"01",X"98",X"C9",X"21",X"03",X"40", + X"22",X"01",X"98",X"11",X"00",X"9B",X"CD",X"44",X"1C",X"21",X"00",X"9B",X"CD",X"0D",X"1C",X"C9", + X"3A",X"09",X"98",X"EE",X"01",X"32",X"09",X"98",X"20",X"47",X"21",X"00",X"99",X"11",X"60",X"99", + X"01",X"20",X"00",X"ED",X"B0",X"11",X"40",X"9B",X"CD",X"44",X"1C",X"21",X"40",X"99",X"11",X"00", + X"99",X"01",X"20",X"00",X"ED",X"B0",X"21",X"00",X"9B",X"CD",X"0D",X"1C",X"11",X"0B",X"03",X"ED", + X"53",X"24",X"98",X"11",X"01",X"03",X"FF",X"1C",X"FF",X"21",X"0B",X"98",X"3A",X"09",X"98",X"A6", + X"32",X"0E",X"98",X"EE",X"01",X"32",X"83",X"A1",X"21",X"01",X"98",X"36",X"02",X"2C",X"36",X"80", + X"C9",X"21",X"00",X"99",X"11",X"40",X"99",X"01",X"20",X"00",X"ED",X"B0",X"11",X"00",X"9B",X"CD", + X"44",X"1C",X"21",X"60",X"99",X"11",X"00",X"99",X"01",X"20",X"00",X"ED",X"B0",X"21",X"40",X"9B", + X"CD",X"0D",X"1C",X"11",X"0C",X"03",X"18",X"B7",X"3A",X"06",X"99",X"47",X"E6",X"0F",X"4F",X"A8", + X"47",X"87",X"81",X"ED",X"44",X"16",X"FF",X"87",X"5F",X"38",X"01",X"15",X"21",X"0E",X"86",X"19", + X"79",X"87",X"87",X"4F",X"2F",X"C6",X"21",X"5F",X"16",X"00",X"78",X"0F",X"0F",X"D9",X"47",X"3E", + X"10",X"D9",X"41",X"77",X"2C",X"10",X"FC",X"19",X"D9",X"10",X"F6",X"C9",X"3A",X"09",X"99",X"B7", + X"11",X"13",X"01",X"28",X"01",X"1D",X"FF",X"3A",X"09",X"99",X"B7",X"CA",X"CD",X"20",X"C3",X"AA", + X"20",X"3A",X"00",X"9D",X"0F",X"D2",X"88",X"18",X"3A",X"07",X"98",X"0F",X"D8",X"AF",X"21",X"44", + X"98",X"01",X"01",X"60",X"D7",X"3A",X"02",X"98",X"FE",X"BF",X"CC",X"A8",X"19",X"3A",X"02",X"98", + X"FE",X"B0",X"CC",X"DC",X"19",X"3A",X"02",X"98",X"47",X"E6",X"07",X"20",X"17",X"11",X"2B",X"03", + X"3A",X"09",X"99",X"B7",X"28",X"01",X"1C",X"3E",X"18",X"A0",X"20",X"02",X"CB",X"FB",X"FF",X"1E", + X"2F",X"FF",X"1C",X"FF",X"3A",X"09",X"99",X"B7",X"11",X"2D",X"03",X"28",X"01",X"1C",X"FF",X"21", + X"02",X"98",X"35",X"C0",X"34",X"11",X"AD",X"03",X"FF",X"AF",X"21",X"40",X"98",X"01",X"01",X"60", + X"D7",X"3E",X"10",X"CD",X"95",X"11",X"3A",X"2C",X"98",X"FE",X"20",X"D8",X"21",X"6E",X"16",X"CD", + X"C4",X"11",X"CD",X"B3",X"32",X"11",X"00",X"9B",X"3A",X"09",X"98",X"0F",X"30",X"02",X"1E",X"40", + X"CD",X"44",X"1C",X"3A",X"09",X"98",X"0F",X"38",X"57",X"11",X"00",X"9B",X"21",X"A0",X"99",X"D5", + X"DD",X"E1",X"E5",X"FD",X"E1",X"CD",X"1E",X"13",X"CD",X"BA",X"12",X"21",X"02",X"99",X"34",X"CD", + X"41",X"13",X"CD",X"D2",X"13",X"DD",X"E5",X"E1",X"CD",X"0D",X"1C",X"CD",X"F3",X"13",X"CD",X"20", + X"17",X"AF",X"21",X"20",X"99",X"01",X"01",X"20",X"D7",X"21",X"80",X"9B",X"01",X"01",X"10",X"D7", + X"21",X"98",X"9C",X"01",X"01",X"70",X"D7",X"21",X"20",X"9D",X"06",X"0B",X"11",X"20",X"00",X"77", + X"19",X"10",X"FC",X"21",X"00",X"99",X"34",X"21",X"01",X"98",X"34",X"AF",X"32",X"03",X"98",X"C9", + X"11",X"40",X"9B",X"21",X"A0",X"99",X"C3",X"7F",X"1A",X"3A",X"00",X"A1",X"CB",X"4F",X"28",X"15", + X"3A",X"02",X"99",X"C6",X"02",X"E6",X"03",X"20",X"0C",X"3A",X"03",X"98",X"CF",X"FC",X"1A",X"1D", + X"1B",X"4A",X"1B",X"69",X"1B",X"21",X"03",X"40",X"22",X"01",X"98",X"C9",X"21",X"03",X"98",X"34", + X"11",X"13",X"00",X"21",X"4F",X"84",X"3E",X"64",X"CD",X"10",X"1B",X"3E",X"C0",X"21",X"4F",X"8C", + X"0E",X"1C",X"06",X"0D",X"77",X"2C",X"10",X"FC",X"19",X"0D",X"20",X"F6",X"C9",X"21",X"40",X"02", + X"22",X"02",X"98",X"AF",X"21",X"30",X"98",X"06",X"04",X"77",X"2C",X"10",X"FC",X"11",X"67",X"85", + X"21",X"43",X"47",X"CD",X"39",X"1B",X"11",X"67",X"8D",X"3E",X"0A",X"01",X"0D",X"00",X"ED",X"B0", + X"EB",X"01",X"13",X"00",X"09",X"EB",X"3D",X"20",X"F2",X"C9",X"21",X"02",X"98",X"2C",X"34",X"21", + X"30",X"98",X"34",X"7E",X"EB",X"FE",X"06",X"30",X"9C",X"87",X"21",X"F5",X"1B",X"E7",X"4E",X"23", + X"46",X"ED",X"43",X"32",X"98",X"1C",X"AF",X"12",X"C9",X"3A",X"07",X"98",X"0F",X"D8",X"21",X"31", + X"98",X"7E",X"34",X"FE",X"15",X"38",X"06",X"3E",X"02",X"32",X"03",X"98",X"C9",X"11",X"20",X"00", + X"47",X"04",X"21",X"47",X"84",X"E7",X"3A",X"30",X"98",X"FE",X"05",X"28",X"47",X"3E",X"07",X"B8", + X"DC",X"DD",X"1B",X"E5",X"21",X"F0",X"1B",X"3A",X"30",X"98",X"E7",X"46",X"E1",X"7D",X"E6",X"1F", + X"21",X"60",X"85",X"B5",X"6F",X"3A",X"31",X"98",X"90",X"38",X"23",X"FE",X"0D",X"D0",X"D9",X"2A", + X"32",X"98",X"23",X"22",X"32",X"98",X"2B",X"11",X"0D",X"00",X"CD",X"C3",X"1B",X"D9",X"01",X"C0", + X"06",X"09",X"D9",X"06",X"0A",X"7E",X"19",X"D9",X"77",X"19",X"D9",X"10",X"F8",X"C9",X"06",X"0A", + X"3E",X"10",X"18",X"04",X"3E",X"10",X"06",X"1C",X"77",X"19",X"10",X"FC",X"C9",X"3E",X"71",X"CD", + X"D6",X"1B",X"01",X"80",X"04",X"09",X"3E",X"C0",X"C3",X"D6",X"1B",X"08",X"07",X"05",X"01",X"00", + X"00",X"01",X"03",X"07",X"08",X"43",X"47",X"47",X"48",X"4B",X"49",X"4F",X"4A",X"53",X"4B",X"21", + X"40",X"99",X"3A",X"09",X"98",X"B7",X"20",X"02",X"2E",X"60",X"7E",X"B7",X"C9",X"3A",X"06",X"99", + X"C6",X"22",X"47",X"4F",X"E6",X"0F",X"5F",X"A8",X"0F",X"0F",X"0F",X"0F",X"57",X"3E",X"88",X"91", + X"ED",X"53",X"2C",X"98",X"32",X"2E",X"98",X"16",X"9A",X"5F",X"D9",X"3A",X"2D",X"98",X"47",X"D9", + X"3A",X"2C",X"98",X"01",X"10",X"00",X"ED",X"A0",X"1C",X"3D",X"20",X"FA",X"EB",X"09",X"09",X"EB", + X"D9",X"10",X"EC",X"C9",X"3A",X"06",X"99",X"C6",X"22",X"47",X"4F",X"E6",X"0F",X"6F",X"A8",X"0F", + X"0F",X"0F",X"0F",X"67",X"3E",X"88",X"91",X"22",X"2C",X"98",X"32",X"2E",X"98",X"26",X"9A",X"6F", + X"D9",X"3A",X"2D",X"98",X"47",X"D9",X"3A",X"2C",X"98",X"01",X"10",X"00",X"08",X"7E",X"E6",X"3F", + X"12",X"23",X"13",X"08",X"0D",X"2C",X"3D",X"20",X"F3",X"09",X"09",X"D9",X"10",X"E7",X"21",X"00", + X"9A",X"AF",X"01",X"01",X"00",X"D7",X"C9",X"21",X"60",X"98",X"3A",X"00",X"9E",X"B7",X"28",X"38", + X"EB",X"3A",X"0E",X"98",X"0F",X"30",X"1B",X"01",X"06",X"00",X"21",X"14",X"9E",X"ED",X"B0",X"CD", + X"BE",X"1C",X"21",X"0E",X"9E",X"11",X"80",X"98",X"06",X"06",X"7E",X"2F",X"12",X"23",X"13",X"10", + X"F9",X"C9",X"21",X"14",X"9E",X"CD",X"A8",X"1C",X"CD",X"BE",X"1C",X"21",X"0E",X"9E",X"0E",X"0A", + X"EB",X"09",X"EB",X"0E",X"06",X"ED",X"B0",X"C9",X"21",X"80",X"98",X"01",X"01",X"10",X"AF",X"D7", + X"C9",X"CD",X"87",X"1C",X"06",X"08",X"11",X"20",X"00",X"21",X"40",X"98",X"DD",X"21",X"00",X"9D", + X"3A",X"0E",X"98",X"0F",X"38",X"35",X"0E",X"07",X"DD",X"7E",X"00",X"B7",X"28",X"22",X"DD",X"7E", + X"0C",X"77",X"2C",X"2C",X"DD",X"7E",X"02",X"D6",X"08",X"77",X"2D",X"DD",X"7E",X"03",X"C6",X"27", + X"2F",X"C6",X"20",X"77",X"DD",X"7E",X"0D",X"2C",X"2C",X"77",X"2C",X"DD",X"19",X"10",X"D9",X"C9", + X"2C",X"77",X"2C",X"77",X"2C",X"2C",X"DD",X"19",X"10",X"CE",X"C9",X"DD",X"7E",X"00",X"B7",X"28", + X"28",X"0E",X"00",X"DD",X"7E",X"0C",X"EE",X"02",X"77",X"2C",X"DD",X"7E",X"03",X"D6",X"08",X"30", + X"02",X"0E",X"80",X"77",X"2C",X"DD",X"7E",X"02",X"ED",X"44",X"D6",X"07",X"77",X"2C",X"DD",X"7E", + X"0D",X"B1",X"77",X"2C",X"DD",X"19",X"10",X"D3",X"C9",X"2C",X"77",X"2C",X"77",X"2C",X"2C",X"DD", + X"19",X"10",X"C8",X"C9",X"CD",X"FF",X"1B",X"20",X"04",X"21",X"C0",X"21",X"E5",X"3A",X"03",X"98", + X"CF",X"69",X"1D",X"7F",X"1D",X"95",X"1D",X"D2",X"1D",X"11",X"0D",X"03",X"FF",X"3A",X"09",X"98", + X"B7",X"1E",X"0B",X"28",X"01",X"1C",X"FF",X"21",X"03",X"98",X"34",X"2D",X"36",X"60",X"C9",X"21", + X"02",X"98",X"35",X"C0",X"2C",X"34",X"CD",X"22",X"1E",X"11",X"8C",X"03",X"FF",X"1C",X"FF",X"16", + X"08",X"FF",X"C3",X"F0",X"20",X"3A",X"28",X"98",X"B7",X"C4",X"8F",X"1E",X"21",X"02",X"98",X"35", + X"C0",X"11",X"A0",X"03",X"FF",X"21",X"29",X"98",X"36",X"0A",X"2D",X"7E",X"B7",X"20",X"01",X"34", + X"3A",X"28",X"98",X"B7",X"C4",X"38",X"1F",X"21",X"28",X"98",X"7E",X"B7",X"36",X"00",X"28",X"02", + X"3E",X"80",X"3C",X"21",X"03",X"98",X"34",X"2D",X"77",X"11",X"FF",X"08",X"FF",X"AF",X"32",X"2C", + X"98",X"C9",X"21",X"02",X"98",X"35",X"C0",X"34",X"3E",X"10",X"CD",X"95",X"11",X"3A",X"2C",X"98", + X"FE",X"20",X"D8",X"CD",X"FF",X"1B",X"28",X"1B",X"21",X"05",X"80",X"01",X"20",X"1A",X"11",X"06", + X"00",X"3E",X"10",X"2C",X"77",X"10",X"FC",X"19",X"06",X"1A",X"0D",X"20",X"F6",X"3E",X"06",X"32", + X"01",X"98",X"C9",X"21",X"17",X"1E",X"11",X"00",X"98",X"01",X"0A",X"00",X"ED",X"B0",X"AF",X"32", + X"0E",X"98",X"3C",X"32",X"83",X"A1",X"C9",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"AF",X"32",X"28",X"98",X"DD",X"21",X"C0",X"99",X"3A",X"09",X"98",X"B7",X"28",X"04", + X"DD",X"21",X"C3",X"99",X"06",X"0A",X"21",X"02",X"9F",X"11",X"0E",X"00",X"7E",X"DD",X"BE",X"02", + X"20",X"11",X"2B",X"7E",X"DD",X"BE",X"01",X"20",X"0B",X"2B",X"7E",X"DD",X"BE",X"00",X"20",X"05", + X"C3",X"57",X"1E",X"2B",X"2B",X"38",X"04",X"19",X"10",X"E2",X"C9",X"E5",X"21",X"28",X"98",X"70", + X"23",X"36",X"00",X"23",X"36",X"00",X"23",X"36",X"00",X"05",X"28",X"11",X"21",X"6B",X"9F",X"11", + X"77",X"9F",X"78",X"87",X"87",X"4F",X"87",X"81",X"4F",X"06",X"00",X"ED",X"B8",X"DD",X"E5",X"E1", + X"D1",X"ED",X"A0",X"ED",X"A0",X"ED",X"A0",X"EB",X"01",X"01",X"09",X"3E",X"40",X"D7",X"C9",X"21", + X"02",X"98",X"34",X"EB",X"21",X"04",X"99",X"DF",X"20",X"04",X"36",X"08",X"EB",X"35",X"3A",X"02", + X"98",X"47",X"E6",X"03",X"20",X"0A",X"11",X"32",X"03",X"CB",X"50",X"28",X"02",X"CB",X"FB",X"FF", + X"21",X"2B",X"98",X"DF",X"CD",X"0D",X"3B",X"B7",X"C4",X"D8",X"1E",X"C3",X"38",X"1F",X"21",X"2A", + X"98",X"34",X"28",X"06",X"2D",X"34",X"3E",X"04",X"BE",X"C0",X"21",X"29",X"98",X"36",X"10",X"21", + X"02",X"98",X"36",X"01",X"E1",X"C3",X"38",X"1F",X"21",X"2B",X"98",X"DF",X"C0",X"36",X"10",X"2D", + X"47",X"E6",X"33",X"28",X"D9",X"E6",X"30",X"28",X"19",X"34",X"28",X"DE",X"2D",X"CB",X"68",X"3E", + X"01",X"28",X"02",X"ED",X"44",X"86",X"FE",X"FF",X"20",X"02",X"3E",X"03",X"FE",X"04",X"28",X"CA", + X"77",X"2C",X"78",X"E6",X"03",X"C8",X"4F",X"2D",X"7E",X"FE",X"03",X"D0",X"2D",X"46",X"21",X"7B", + X"9F",X"11",X"F4",X"FF",X"19",X"10",X"FD",X"E7",X"CB",X"49",X"28",X"0E",X"34",X"3E",X"5B",X"BE", + X"D0",X"36",X"3B",X"21",X"2A",X"98",X"34",X"28",X"A1",X"C9",X"35",X"7E",X"FE",X"3B",X"D0",X"36", + X"5B",X"21",X"2A",X"98",X"34",X"28",X"93",X"C9",X"CD",X"8D",X"1F",X"DD",X"21",X"7B",X"9F",X"21", + X"A4",X"86",X"11",X"02",X"00",X"01",X"F4",X"FF",X"3A",X"28",X"98",X"DD",X"09",X"19",X"3D",X"20", + X"FA",X"DD",X"E5",X"D1",X"06",X"03",X"CD",X"D3",X"03",X"2B",X"3A",X"29",X"98",X"D6",X"03",X"5F", + X"3E",X"8E",X"16",X"2B",X"01",X"10",X"04",X"20",X"0B",X"36",X"37",X"CD",X"B5",X"1F",X"16",X"36", + X"05",X"CD",X"83",X"1F",X"1D",X"71",X"1C",X"20",X"01",X"72",X"CD",X"B5",X"1F",X"CD",X"83",X"1F", + X"10",X"F3",X"C9",X"08",X"7D",X"D6",X"20",X"6F",X"30",X"01",X"25",X"08",X"C9",X"3A",X"07",X"98", + X"47",X"E6",X"07",X"C0",X"3E",X"18",X"A0",X"28",X"22",X"FE",X"08",X"C0",X"21",X"84",X"84",X"3A", + X"28",X"98",X"87",X"85",X"6F",X"3E",X"8E",X"01",X"10",X"18",X"11",X"20",X"00",X"71",X"CD",X"B5", + X"1F",X"19",X"10",X"F9",X"C9",X"CB",X"DC",X"77",X"CB",X"9C",X"C9",X"11",X"FF",X"08",X"FF",X"C9", + X"21",X"CE",X"99",X"5E",X"16",X"99",X"1A",X"3C",X"C8",X"3D",X"47",X"3E",X"FF",X"12",X"1C",X"20", + X"02",X"1E",X"D0",X"73",X"3E",X"10",X"B8",X"28",X"17",X"3A",X"BF",X"98",X"21",X"08",X"98",X"B6", + X"C8",X"78",X"C3",X"F0",X"1F",X"3E",X"01",X"32",X"82",X"A1",X"C9",X"AF",X"32",X"82",X"A1",X"AF", + X"32",X"00",X"A1",X"3E",X"00",X"32",X"80",X"A1",X"00",X"00",X"00",X"00",X"3E",X"01",X"32",X"80", + X"A1",X"C9",X"47",X"11",X"CD",X"99",X"1A",X"6F",X"26",X"99",X"70",X"2C",X"20",X"02",X"2E",X"D0", + X"EB",X"73",X"C9",X"3E",X"1E",X"CD",X"02",X"20",X"3E",X"04",X"C3",X"02",X"20",X"3E",X"84",X"C3", + X"02",X"20",X"2A",X"30",X"99",X"29",X"29",X"7C",X"E6",X"0F",X"C8",X"C6",X"1D",X"C3",X"02",X"20", + X"3E",X"01",X"CD",X"02",X"20",X"3E",X"02",X"CD",X"02",X"20",X"3E",X"03",X"C3",X"02",X"20",X"3E", + X"05",X"C3",X"02",X"20",X"3E",X"85",X"C3",X"02",X"20",X"3E",X"85",X"CD",X"02",X"20",X"3E",X"06", + X"C3",X"02",X"20",X"3E",X"85",X"3E",X"86",X"C3",X"02",X"20",X"3E",X"07",X"C3",X"02",X"20",X"3E", + X"08",X"C3",X"02",X"20",X"3E",X"87",X"C3",X"02",X"20",X"3E",X"09",X"CD",X"02",X"20",X"3E",X"0A", + X"C3",X"02",X"20",X"3E",X"0B",X"C3",X"02",X"20",X"3E",X"0C",X"C3",X"02",X"20",X"3E",X"0D",X"C3", + X"02",X"20",X"3E",X"0E",X"C3",X"02",X"20",X"3E",X"0F",X"C3",X"02",X"20",X"3E",X"10",X"C3",X"02", + X"20",X"3E",X"00",X"CD",X"02",X"20",X"3E",X"11",X"CD",X"02",X"20",X"3E",X"12",X"CD",X"02",X"20", + X"3E",X"13",X"CD",X"02",X"20",X"3E",X"14",X"C3",X"02",X"20",X"3E",X"84",X"CD",X"02",X"20",X"3E", + X"85",X"CD",X"02",X"20",X"3E",X"86",X"CD",X"02",X"20",X"3E",X"87",X"CD",X"02",X"20",X"3E",X"15", + X"CD",X"02",X"20",X"3E",X"16",X"CD",X"02",X"20",X"3E",X"17",X"C3",X"02",X"20",X"3E",X"84",X"CD", + X"02",X"20",X"3E",X"85",X"CD",X"02",X"20",X"3E",X"86",X"CD",X"02",X"20",X"3E",X"87",X"CD",X"02", + X"20",X"3E",X"18",X"CD",X"02",X"20",X"3E",X"19",X"CD",X"02",X"20",X"3E",X"1A",X"C3",X"02",X"20", + X"3E",X"00",X"CD",X"02",X"20",X"3E",X"1B",X"CD",X"02",X"20",X"3E",X"1C",X"CD",X"02",X"20",X"3E", + X"1D",X"C3",X"02",X"20",X"3A",X"BE",X"98",X"B7",X"28",X"0B",X"AF",X"32",X"12",X"98",X"21",X"00", + X"00",X"22",X"00",X"98",X"C9",X"21",X"C0",X"21",X"E5",X"3A",X"01",X"98",X"CF",X"25",X"21",X"38", + X"21",X"8E",X"21",X"BB",X"21",X"21",X"40",X"98",X"01",X"01",X"50",X"AF",X"D7",X"32",X"2C",X"98", + X"21",X"02",X"98",X"36",X"10",X"2D",X"34",X"C9",X"3A",X"07",X"98",X"0F",X"D8",X"3E",X"10",X"CD", + X"91",X"11",X"3A",X"2C",X"98",X"FE",X"20",X"D8",X"11",X"01",X"02",X"FF",X"11",X"02",X"03",X"FF", + X"11",X"00",X"02",X"FF",X"1E",X"02",X"FF",X"11",X"01",X"03",X"FF",X"1D",X"FF",X"CD",X"EF",X"1F", + X"21",X"01",X"98",X"34",X"2C",X"36",X"FF",X"2C",X"AF",X"77",X"32",X"09",X"98",X"32",X"2C",X"98", + X"3C",X"32",X"83",X"A1",X"11",X"00",X"04",X"FF",X"11",X"07",X"03",X"FF",X"16",X"08",X"FF",X"3A", + X"0D",X"98",X"47",X"E6",X"0F",X"78",X"E6",X"F0",X"C8",X"0F",X"0F",X"0F",X"0F",X"C9",X"21",X"02", + X"98",X"DF",X"CC",X"75",X"22",X"3A",X"12",X"98",X"A7",X"C8",X"3D",X"11",X"08",X"03",X"28",X"01", + X"1C",X"0E",X"07",X"3A",X"07",X"98",X"47",X"E6",X"0F",X"C0",X"78",X"E6",X"30",X"20",X"04",X"CB", + X"FB",X"CB",X"F9",X"FF",X"59",X"FF",X"11",X"00",X"04",X"FF",X"C9",X"AF",X"32",X"01",X"98",X"C9", + X"3A",X"1C",X"98",X"E6",X"C0",X"C8",X"07",X"38",X"3B",X"3A",X"BE",X"98",X"B7",X"20",X"0B",X"3A", + X"12",X"98",X"FE",X"02",X"D8",X"D6",X"02",X"32",X"12",X"98",X"AF",X"21",X"C3",X"99",X"01",X"01", + X"03",X"D7",X"21",X"00",X"01",X"22",X"09",X"98",X"AF",X"21",X"C0",X"99",X"01",X"01",X"03",X"D7", + X"AF",X"32",X"01",X"98",X"32",X"0E",X"98",X"3C",X"32",X"83",X"A1",X"32",X"08",X"98",X"21",X"00", + X"98",X"36",X"03",X"C9",X"3A",X"BE",X"98",X"B7",X"20",X"09",X"3A",X"12",X"98",X"A7",X"C8",X"3D", + X"32",X"12",X"98",X"21",X"00",X"00",X"C3",X"E5",X"21",X"81",X"8C",X"9A",X"81",X"8C",X"8C",X"8E", + X"8E",X"8E",X"90",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80", + X"80",X"92",X"92",X"92",X"92",X"92",X"93",X"93",X"93",X"24",X"01",X"30",X"10",X"3C",X"02",X"30", + X"20",X"24",X"01",X"60",X"02",X"48",X"10",X"24",X"01",X"3C",X"20",X"24",X"02",X"30",X"20",X"21", + X"01",X"2A",X"01",X"21",X"10",X"1E",X"02",X"1E",X"02",X"3C",X"20",X"24",X"01",X"24",X"01",X"2A", + X"10",X"24",X"10",X"24",X"02",X"30",X"20",X"24",X"20",X"54",X"01",X"A8",X"FF",X"AF",X"32",X"2C", + X"98",X"32",X"03",X"98",X"C9",X"3A",X"03",X"98",X"CF",X"81",X"22",X"97",X"22",X"E7",X"22",X"5A", + X"23",X"3E",X"10",X"CD",X"95",X"11",X"3A",X"2C",X"98",X"FE",X"20",X"D8",X"21",X"19",X"22",X"CD", + X"C4",X"11",X"21",X"03",X"98",X"34",X"C9",X"21",X"03",X"98",X"34",X"11",X"27",X"03",X"FF",X"1C", + X"FF",X"1C",X"FF",X"1E",X"0F",X"FF",X"AF",X"21",X"00",X"9D",X"01",X"01",X"20",X"D7",X"21",X"00", + X"99",X"01",X"01",X"40",X"D7",X"21",X"90",X"9C",X"01",X"01",X"70",X"D7",X"21",X"2E",X"23",X"11", + X"00",X"9D",X"01",X"10",X"00",X"ED",X"B0",X"11",X"00",X"99",X"0E",X"10",X"ED",X"B0",X"11",X"54", + X"9A",X"CD",X"D7",X"22",X"CD",X"D7",X"22",X"3E",X"04",X"01",X"20",X"00",X"ED",X"A0",X"1C",X"0D", + X"3D",X"20",X"F9",X"EB",X"09",X"EB",X"C9",X"3E",X"C0",X"21",X"52",X"8D",X"11",X"20",X"00",X"06", + X"0C",X"77",X"19",X"10",X"FC",X"21",X"53",X"8D",X"06",X"0C",X"77",X"19",X"10",X"FC",X"01",X"03", + X"04",X"21",X"54",X"9A",X"E5",X"C5",X"7D",X"CD",X"CD",X"30",X"C1",X"E1",X"23",X"23",X"10",X"F4", + X"06",X"04",X"11",X"18",X"00",X"19",X"0D",X"20",X"EB",X"AF",X"32",X"08",X"98",X"21",X"01",X"00", + X"22",X"28",X"98",X"21",X"39",X"22",X"22",X"2A",X"98",X"21",X"03",X"98",X"34",X"C9",X"01",X"00", + X"80",X"38",X"80",X"30",X"18",X"74",X"00",X"02",X"00",X"00",X"D1",X"01",X"01",X"C1",X"00",X"00", + X"00",X"90",X"00",X"00",X"34",X"04",X"78",X"00",X"02",X"00",X"08",X"FF",X"00",X"00",X"02",X"03", + X"01",X"1C",X"03",X"0B",X"00",X"1D",X"01",X"02",X"08",X"22",X"CD",X"71",X"23",X"3A",X"07",X"98", + X"0F",X"DC",X"6E",X"32",X"CD",X"A7",X"34",X"CD",X"63",X"2E",X"CD",X"D1",X"1C",X"CD",X"7E",X"2A", + X"C9",X"21",X"28",X"98",X"35",X"28",X"57",X"7E",X"FE",X"12",X"C0",X"2C",X"7E",X"3D",X"F8",X"3A", + X"08",X"99",X"CD",X"27",X"24",X"3A",X"29",X"98",X"FE",X"10",X"38",X"1F",X"21",X"4E",X"24",X"CB", + X"67",X"28",X"03",X"21",X"53",X"24",X"46",X"23",X"4E",X"23",X"EB",X"09",X"EB",X"ED",X"A0",X"ED", + X"A0",X"CB",X"DA",X"3E",X"80",X"AE",X"1D",X"12",X"1D",X"12",X"C9",X"21",X"44",X"24",X"0F",X"38", + X"03",X"21",X"49",X"24",X"46",X"23",X"4E",X"23",X"EB",X"09",X"01",X"20",X"00",X"1A",X"77",X"09", + X"13",X"1A",X"77",X"13",X"CB",X"DC",X"1A",X"EE",X"80",X"77",X"ED",X"42",X"77",X"C9",X"3A",X"29", + X"98",X"FE",X"FF",X"28",X"40",X"EB",X"2A",X"2A",X"98",X"ED",X"A0",X"ED",X"A0",X"22",X"2A",X"98", + X"B7",X"C8",X"47",X"3A",X"2A",X"99",X"F6",X"28",X"6F",X"26",X"99",X"70",X"3E",X"01",X"AD",X"32", + X"2A",X"99",X"3A",X"08",X"99",X"CD",X"27",X"24",X"21",X"21",X"00",X"19",X"01",X"1F",X"00",X"3E", + X"FF",X"77",X"2C",X"77",X"09",X"77",X"2C",X"77",X"CB",X"DC",X"3E",X"80",X"77",X"2D",X"77",X"ED", + X"42",X"77",X"2D",X"77",X"C9",X"CD",X"F2",X"23",X"AF",X"32",X"00",X"9D",X"32",X"03",X"98",X"32", + X"2C",X"98",X"21",X"01",X"98",X"34",X"C9",X"3D",X"4F",X"E6",X"0F",X"47",X"A9",X"16",X"00",X"87", + X"CB",X"12",X"87",X"CB",X"12",X"80",X"80",X"5F",X"47",X"FE",X"0F",X"20",X"02",X"CB",X"EB",X"3E", + X"84",X"B2",X"57",X"C9",X"00",X"21",X"86",X"84",X"00",X"00",X"22",X"84",X"86",X"80",X"00",X"41", + X"87",X"85",X"80",X"00",X"21",X"85",X"87",X"00",X"3A",X"02",X"99",X"FE",X"0E",X"38",X"02",X"3E", + X"0A",X"C6",X"02",X"0F",X"0F",X"E6",X"03",X"C8",X"4F",X"06",X"0C",X"11",X"20",X"00",X"21",X"A2", + X"24",X"DD",X"21",X"40",X"9D",X"7E",X"32",X"80",X"9B",X"D9",X"CD",X"72",X"29",X"3A",X"80",X"9B", + X"B7",X"28",X"13",X"DD",X"E5",X"E1",X"CD",X"2A",X"28",X"CD",X"31",X"2C",X"38",X"08",X"D9",X"AF", + X"0D",X"28",X"0B",X"DD",X"19",X"D9",X"D9",X"23",X"10",X"DB",X"AF",X"DD",X"77",X"00",X"32",X"80", + X"9B",X"C9",X"01",X"0A",X"1B",X"11",X"03",X"19",X"09",X"13",X"02",X"0B",X"1A",X"12",X"3A",X"07", + X"9D",X"5F",X"16",X"9A",X"1A",X"E6",X"3F",X"C6",X"F0",X"FE",X"FC",X"D8",X"21",X"38",X"99",X"7E", + X"BB",X"28",X"07",X"73",X"2C",X"36",X"00",X"C3",X"44",X"20",X"2C",X"34",X"7E",X"FE",X"03",X"CA", + X"3F",X"20",X"FE",X"04",X"D8",X"36",X"00",X"C3",X"B6",X"2D",X"3A",X"08",X"9D",X"21",X"E3",X"24", + X"E7",X"6E",X"C9",X"03",X"03",X"03",X"03",X"02",X"02",X"01",X"01",X"01",X"01",X"02",X"02",X"AF", + X"32",X"01",X"9D",X"3A",X"07",X"9D",X"6F",X"26",X"9A",X"7E",X"EB",X"E6",X"3F",X"6F",X"C6",X"F0", + X"FE",X"FC",X"D4",X"DA",X"24",X"26",X"00",X"29",X"29",X"29",X"01",X"3C",X"45",X"09",X"3A",X"09", + X"9D",X"FE",X"04",X"20",X"07",X"3A",X"08",X"9D",X"E6",X"03",X"EE",X"02",X"47",X"EE",X"02",X"87", + X"E7",X"7E",X"FE",X"04",X"20",X"01",X"78",X"EE",X"02",X"87",X"21",X"E0",X"25",X"E7",X"4E",X"23", + X"46",X"7B",X"E6",X"F0",X"6F",X"AB",X"87",X"87",X"87",X"87",X"67",X"09",X"22",X"02",X"9D",X"22", + X"04",X"9D",X"3A",X"07",X"9D",X"2A",X"08",X"9D",X"22",X"28",X"98",X"32",X"2A",X"98",X"7D",X"C6", + X"F0",X"FE",X"FC",X"30",X"04",X"CD",X"24",X"26",X"D8",X"AF",X"32",X"2C",X"98",X"3A",X"07",X"9D", + X"6F",X"26",X"9A",X"7E",X"B7",X"28",X"5F",X"FE",X"0B",X"28",X"5B",X"CB",X"6F",X"20",X"57",X"C6", + X"F0",X"FE",X"FC",X"30",X"51",X"7D",X"32",X"07",X"9D",X"7E",X"E6",X"3F",X"EB",X"6F",X"26",X"00", + X"29",X"29",X"29",X"01",X"3B",X"45",X"09",X"06",X"00",X"7E",X"C6",X"F0",X"FE",X"FC",X"38",X"06", + X"04",X"23",X"23",X"C3",X"89",X"25",X"78",X"FE",X"04",X"30",X"25",X"4E",X"23",X"46",X"ED",X"43", + X"08",X"9D",X"87",X"21",X"E0",X"25",X"E7",X"4E",X"23",X"46",X"7B",X"E6",X"F0",X"6F",X"AB",X"87", + X"87",X"87",X"87",X"67",X"09",X"22",X"02",X"9D",X"22",X"04",X"9D",X"AF",X"32",X"06",X"9D",X"C9", + X"3A",X"07",X"9D",X"6F",X"26",X"9A",X"D9",X"21",X"2C",X"98",X"7E",X"34",X"E6",X"07",X"21",X"D8", + X"25",X"E7",X"7E",X"D9",X"85",X"C3",X"60",X"25",X"02",X"DE",X"1E",X"22",X"C2",X"FC",X"40",X"24", + X"10",X"10",X"20",X"00",X"10",X"F0",X"00",X"00",X"3A",X"07",X"9D",X"2A",X"08",X"9D",X"22",X"28", + X"98",X"32",X"2A",X"98",X"7D",X"FE",X"0C",X"30",X"09",X"CD",X"24",X"26",X"30",X"04",X"CD",X"24", + X"26",X"D8",X"3A",X"07",X"9D",X"6F",X"26",X"9A",X"4E",X"EB",X"21",X"00",X"9A",X"3E",X"03",X"06", + X"00",X"BE",X"28",X"07",X"2C",X"10",X"FA",X"3D",X"20",X"F5",X"C9",X"71",X"12",X"CD",X"0E",X"14", + X"C9",X"C3",X"E8",X"25",X"ED",X"4B",X"29",X"98",X"79",X"21",X"83",X"35",X"E7",X"7E",X"80",X"32", + X"2A",X"98",X"6F",X"26",X"9A",X"7E",X"E6",X"3F",X"6F",X"C6",X"F0",X"FE",X"FC",X"30",X"25",X"26", + X"00",X"29",X"29",X"29",X"11",X"3B",X"45",X"19",X"79",X"FE",X"04",X"20",X"07",X"3A",X"28",X"98", + X"E6",X"03",X"EE",X"02",X"57",X"87",X"E7",X"4E",X"23",X"46",X"ED",X"43",X"28",X"98",X"3E",X"F0", + X"81",X"FE",X"FC",X"C9",X"37",X"C9",X"21",X"00",X"00",X"54",X"06",X"08",X"0F",X"30",X"01",X"19", + X"CB",X"23",X"CB",X"12",X"10",X"F6",X"C9",X"87",X"5F",X"16",X"00",X"30",X"01",X"14",X"21",X"7A", + X"4D",X"19",X"7E",X"C9",X"87",X"3C",X"5F",X"16",X"00",X"30",X"01",X"14",X"21",X"7A",X"4D",X"19", + X"7E",X"C9",X"DD",X"66",X"06",X"3A",X"03",X"99",X"57",X"AF",X"06",X"80",X"5F",X"6F",X"ED",X"52", + X"D0",X"19",X"CB",X"3A",X"CB",X"1B",X"ED",X"52",X"30",X"02",X"B0",X"19",X"CB",X"38",X"30",X"F2", + X"2F",X"37",X"C9",X"87",X"5F",X"16",X"00",X"30",X"01",X"14",X"21",X"7A",X"4D",X"19",X"5E",X"23", + X"56",X"63",X"7C",X"AA",X"E6",X"01",X"4F",X"CD",X"99",X"26",X"E6",X"FE",X"B1",X"C9",X"21",X"80", + X"9B",X"7E",X"B7",X"28",X"09",X"2C",X"7E",X"CF",X"4A",X"29",X"1F",X"27",X"6A",X"27",X"3A",X"07", + X"98",X"E6",X"0F",X"C0",X"21",X"89",X"9B",X"DF",X"C0",X"CD",X"8F",X"01",X"E6",X"1B",X"6F",X"26", + X"00",X"22",X"80",X"9B",X"C9",X"1E",X"F3",X"3A",X"02",X"99",X"FE",X"08",X"38",X"04",X"87",X"2F", + X"83",X"5F",X"3A",X"82",X"9B",X"B7",X"C8",X"CD",X"66",X"26",X"7C",X"32",X"82",X"9B",X"B7",X"CA", + X"99",X"27",X"FE",X"0A",X"CA",X"5F",X"20",X"C6",X"D8",X"FE",X"FC",X"D8",X"C3",X"5A",X"20",X"CD", + X"9A",X"28",X"3A",X"07",X"98",X"E6",X"1F",X"CC",X"F5",X"26",X"ED",X"4B",X"85",X"9B",X"ED",X"5B", + X"02",X"9D",X"78",X"92",X"C6",X"05",X"FE",X"0B",X"D0",X"79",X"93",X"C6",X"05",X"FE",X"0B",X"D0", + X"3A",X"82",X"9B",X"CD",X"31",X"29",X"78",X"87",X"87",X"87",X"87",X"81",X"47",X"7A",X"87",X"87", + X"87",X"87",X"4F",X"ED",X"43",X"C9",X"99",X"AF",X"32",X"CB",X"99",X"11",X"00",X"01",X"FF",X"21", + X"81",X"9B",X"34",X"2D",X"36",X"40",X"CD",X"64",X"20",X"C9",X"21",X"80",X"9B",X"35",X"C2",X"9A", + X"28",X"21",X"0D",X"99",X"7E",X"34",X"FE",X"07",X"38",X"02",X"3E",X"07",X"21",X"91",X"27",X"E7", + X"7E",X"32",X"89",X"9B",X"CD",X"64",X"28",X"21",X"00",X"00",X"22",X"80",X"9B",X"CD",X"64",X"20", + X"C9",X"30",X"20",X"18",X"14",X"10",X"0C",X"0A",X"08",X"E1",X"21",X"71",X"27",X"E5",X"CD",X"8F", + X"01",X"E6",X"03",X"28",X"0F",X"06",X"04",X"11",X"20",X"00",X"21",X"40",X"9D",X"7E",X"B7",X"28", + X"79",X"19",X"10",X"F9",X"CD",X"69",X"20",X"3A",X"88",X"9B",X"6F",X"26",X"9A",X"3E",X"01",X"32", + X"94",X"9C",X"7E",X"08",X"7E",X"0F",X"E6",X"03",X"20",X"02",X"3E",X"04",X"C6",X"20",X"77",X"08", + X"EB",X"21",X"09",X"99",X"34",X"E6",X"1F",X"FE",X"18",X"38",X"13",X"2C",X"35",X"20",X"0F",X"F5", + X"D9",X"AF",X"32",X"2C",X"98",X"01",X"08",X"C0",X"ED",X"43",X"01",X"98",X"D9",X"F1",X"E6",X"07", + X"87",X"21",X"D3",X"36",X"E7",X"7E",X"83",X"4F",X"42",X"08",X"02",X"16",X"07",X"FF",X"43",X"59", + X"FF",X"60",X"69",X"DD",X"21",X"00",X"9D",X"06",X"06",X"11",X"20",X"00",X"DD",X"7E",X"00",X"0F", + X"30",X"0B",X"DD",X"7E",X"07",X"BC",X"CC",X"22",X"28",X"BD",X"CC",X"22",X"28",X"DD",X"19",X"10", + X"EB",X"C9",X"DD",X"34",X"00",X"DD",X"36",X"01",X"04",X"C9",X"3E",X"01",X"77",X"2C",X"77",X"2C", + X"ED",X"4B",X"85",X"9B",X"71",X"2C",X"70",X"2C",X"71",X"2C",X"70",X"2C",X"36",X"F0",X"2C",X"3A", + X"87",X"9B",X"57",X"78",X"0F",X"0F",X"0F",X"0F",X"B1",X"CB",X"4A",X"20",X"02",X"D6",X"11",X"77", + X"2C",X"36",X"00",X"2C",X"7A",X"FE",X"02",X"3E",X"01",X"30",X"01",X"3C",X"77",X"CB",X"D5",X"36", + X"02",X"C3",X"7D",X"20",X"3A",X"87",X"9B",X"CF",X"70",X"28",X"70",X"28",X"87",X"28",X"87",X"28", + X"2A",X"85",X"9B",X"11",X"F0",X"EF",X"19",X"7C",X"0F",X"0F",X"0F",X"0F",X"85",X"F5",X"C6",X"02", + X"CD",X"CD",X"30",X"F1",X"C3",X"CD",X"30",X"2A",X"85",X"9B",X"7C",X"0F",X"0F",X"0F",X"0F",X"85", + X"F5",X"D6",X"20",X"CD",X"CD",X"30",X"F1",X"C3",X"CD",X"30",X"3A",X"81",X"9B",X"B7",X"C8",X"01", + X"18",X"00",X"FE",X"02",X"28",X"18",X"3A",X"82",X"9B",X"FE",X"28",X"30",X"02",X"0E",X"0C",X"FE", + X"0A",X"30",X"02",X"0E",X"04",X"3A",X"07",X"98",X"2F",X"A1",X"20",X"02",X"06",X"04",X"3A",X"87", + X"9B",X"80",X"CF",X"F7",X"28",X"F7",X"28",X"15",X"29",X"15",X"29",X"D3",X"28",X"D3",X"28",X"D9", + X"28",X"D9",X"28",X"11",X"FF",X"FF",X"C3",X"DC",X"28",X"11",X"20",X"00",X"2A",X"83",X"9B",X"3E", + X"10",X"CD",X"F0",X"28",X"7A",X"2F",X"57",X"7B",X"2F",X"5F",X"13",X"19",X"3E",X"88",X"CB",X"DC", + X"06",X"04",X"77",X"19",X"10",X"FC",X"C9",X"3A",X"82",X"9B",X"CD",X"31",X"29",X"2A",X"83",X"9B", + X"1E",X"2C",X"78",X"83",X"77",X"2D",X"79",X"83",X"77",X"2D",X"7A",X"83",X"77",X"2D",X"73",X"11", + X"01",X"00",X"C3",X"EC",X"28",X"3A",X"82",X"9B",X"CD",X"31",X"29",X"2A",X"83",X"9B",X"1E",X"20", + X"7B",X"70",X"E7",X"71",X"7B",X"E7",X"72",X"7B",X"E7",X"36",X"00",X"11",X"E0",X"FF",X"C3",X"EC", + X"28",X"01",X"00",X"00",X"D6",X"64",X"38",X"04",X"04",X"C3",X"34",X"29",X"C6",X"64",X"D6",X"0A", + X"38",X"04",X"0C",X"C3",X"3E",X"29",X"C6",X"0A",X"57",X"C9",X"CD",X"72",X"29",X"11",X"FF",X"80", + X"E6",X"08",X"20",X"0C",X"D9",X"CD",X"8F",X"01",X"D9",X"E6",X"07",X"20",X"4B",X"11",X"3F",X"30", + X"D9",X"CD",X"8F",X"01",X"D9",X"A3",X"B2",X"32",X"82",X"9B",X"21",X"81",X"9B",X"34",X"CD",X"7D", + X"20",X"C9",X"CD",X"DA",X"29",X"38",X"31",X"22",X"83",X"9B",X"3A",X"80",X"9B",X"E6",X"18",X"0F", + X"0F",X"0F",X"32",X"87",X"9B",X"CD",X"AD",X"29",X"3A",X"87",X"9B",X"ED",X"4B",X"85",X"9B",X"57", + X"78",X"0F",X"0F",X"0F",X"0F",X"B1",X"CB",X"4A",X"20",X"02",X"D6",X"11",X"6F",X"26",X"9A",X"32", + X"88",X"9B",X"7E",X"E6",X"18",X"28",X"01",X"C9",X"AF",X"32",X"80",X"9B",X"C9",X"3A",X"87",X"9B", + X"87",X"21",X"D2",X"29",X"E7",X"5E",X"23",X"56",X"2A",X"83",X"9B",X"19",X"7D",X"87",X"87",X"87", + X"E6",X"F8",X"57",X"7D",X"CB",X"1C",X"1F",X"CB",X"1C",X"1F",X"E6",X"F8",X"5F",X"ED",X"53",X"85", + X"9B",X"C9",X"DF",X"FF",X"3F",X"00",X"3F",X"00",X"42",X"00",X"3A",X"80",X"9B",X"CB",X"67",X"20", + X"38",X"0E",X"00",X"61",X"CB",X"5F",X"20",X"01",X"0C",X"E6",X"07",X"28",X"2A",X"87",X"47",X"3A", + X"06",X"99",X"57",X"E6",X"F0",X"6F",X"AA",X"B8",X"D8",X"87",X"C6",X"13",X"CB",X"20",X"CB",X"20", + X"90",X"47",X"29",X"29",X"CB",X"E5",X"EB",X"21",X"F0",X"85",X"CB",X"41",X"28",X"05",X"ED",X"52", + X"78",X"E7",X"C9",X"19",X"78",X"E7",X"C9",X"37",X"C9",X"0E",X"00",X"61",X"CB",X"5F",X"20",X"01", + X"0C",X"E6",X"07",X"28",X"F2",X"47",X"3A",X"06",X"99",X"57",X"E6",X"F0",X"6F",X"AA",X"87",X"CB", + X"41",X"28",X"01",X"2F",X"C6",X"0E",X"4F",X"29",X"29",X"54",X"5D",X"29",X"7C",X"B8",X"D8",X"21", + X"40",X"85",X"ED",X"52",X"78",X"84",X"67",X"06",X"00",X"09",X"C9",X"3E",X"C0",X"06",X"04",X"11", + X"20",X"00",X"CB",X"DC",X"77",X"19",X"10",X"FC",X"C9",X"21",X"94",X"9C",X"7E",X"B7",X"C8",X"34", + X"3D",X"CA",X"4D",X"2E",X"3D",X"28",X"0A",X"D6",X"04",X"C0",X"77",X"3E",X"10",X"32",X"98",X"9C", + X"C9",X"AF",X"32",X"98",X"9C",X"32",X"93",X"9C",X"3E",X"10",X"32",X"9C",X"9C",X"C9",X"3A",X"07", + X"98",X"E6",X"03",X"C0",X"3A",X"9D",X"9C",X"B7",X"C0",X"21",X"98",X"9C",X"7E",X"B7",X"C0",X"21", + X"93",X"9C",X"7E",X"B7",X"FA",X"D5",X"2A",X"C8",X"3A",X"34",X"99",X"B7",X"C0",X"36",X"A1",X"CD", + X"4D",X"2E",X"3A",X"90",X"9C",X"47",X"3A",X"07",X"9D",X"B8",X"20",X"6F",X"3A",X"92",X"9C",X"32", + X"99",X"9C",X"3A",X"A0",X"9C",X"6F",X"26",X"9A",X"3A",X"91",X"9C",X"47",X"AE",X"E6",X"3F",X"28", + X"0F",X"78",X"E6",X"3F",X"C6",X"F0",X"FE",X"FC",X"38",X"50",X"78",X"AE",X"E6",X"3C",X"20",X"4A", + X"70",X"7D",X"C3",X"CD",X"30",X"34",X"6F",X"7E",X"B7",X"28",X"3A",X"5F",X"16",X"9A",X"1A",X"E6", + X"3F",X"6F",X"C6",X"F0",X"FE",X"FC",X"30",X"23",X"26",X"00",X"29",X"29",X"E5",X"29",X"01",X"3C", + X"45",X"09",X"3A",X"99",X"9C",X"4F",X"87",X"E7",X"7E",X"32",X"99",X"9C",X"E1",X"06",X"00",X"09", + X"01",X"63",X"46",X"09",X"1A",X"B6",X"12",X"7B",X"C3",X"CD",X"30",X"3A",X"99",X"9C",X"C6",X"4C", + X"12",X"7B",X"CD",X"CD",X"30",X"AF",X"32",X"93",X"9C",X"C9",X"00",X"AF",X"32",X"93",X"9C",X"3E", + X"10",X"32",X"98",X"9C",X"C9",X"3A",X"09",X"9D",X"EE",X"02",X"C6",X"4C",X"77",X"32",X"91",X"9C", + X"C3",X"78",X"20",X"21",X"98",X"9C",X"7E",X"B7",X"C8",X"FA",X"9B",X"2B",X"3A",X"00",X"9D",X"0F", + X"D0",X"3A",X"34",X"99",X"B7",X"C0",X"3E",X"10",X"32",X"93",X"9C",X"36",X"A0",X"2C",X"3A",X"09", + X"9D",X"77",X"32",X"92",X"9C",X"2C",X"36",X"00",X"EE",X"02",X"47",X"3A",X"07",X"9D",X"32",X"A0", + X"9C",X"32",X"90",X"9C",X"6F",X"26",X"9A",X"7E",X"E6",X"3F",X"C6",X"F0",X"FE",X"FC",X"30",X"B5", + X"7E",X"EB",X"87",X"87",X"21",X"63",X"46",X"80",X"E7",X"7E",X"EB",X"B6",X"77",X"32",X"91",X"9C", + X"7D",X"C9",X"6F",X"26",X"9A",X"7E",X"22",X"96",X"9C",X"32",X"95",X"9C",X"7D",X"CD",X"CD",X"30", + X"2A",X"96",X"9C",X"3A",X"95",X"9C",X"BE",X"C8",X"C3",X"85",X"2B",X"5E",X"34",X"3A",X"99",X"9C", + X"21",X"83",X"35",X"E7",X"16",X"9C",X"1A",X"86",X"13",X"12",X"5F",X"16",X"9A",X"1A",X"E6",X"3F", + X"6F",X"C6",X"F0",X"FE",X"FC",X"30",X"4C",X"26",X"00",X"29",X"29",X"E5",X"29",X"01",X"3B",X"45", + X"09",X"3A",X"99",X"9C",X"4F",X"87",X"E7",X"7E",X"C6",X"F0",X"FE",X"FC",X"30",X"2A",X"23",X"7E", + X"32",X"99",X"9C",X"E1",X"06",X"00",X"09",X"01",X"63",X"46",X"09",X"1A",X"B6",X"EB",X"BE",X"20", + X"14",X"3A",X"A0",X"9C",X"BD",X"20",X"0F",X"21",X"98",X"9C",X"5E",X"16",X"9C",X"AF",X"12",X"77", + X"2C",X"2C",X"36",X"01",X"C9",X"77",X"7D",X"C9",X"E1",X"21",X"98",X"9C",X"5E",X"16",X"9C",X"AF", + X"12",X"77",X"C9",X"1A",X"FE",X"40",X"38",X"1E",X"21",X"38",X"99",X"7B",X"BE",X"20",X"13",X"2C", + X"34",X"7E",X"D6",X"03",X"38",X"10",X"01",X"3F",X"20",X"28",X"03",X"01",X"B6",X"2D",X"C5",X"28", + X"05",X"2D",X"73",X"2C",X"36",X"00",X"3A",X"99",X"9C",X"C6",X"4C",X"12",X"AF",X"32",X"98",X"9C", + X"C9",X"3A",X"07",X"9D",X"47",X"DD",X"7E",X"07",X"B8",X"28",X"4A",X"DD",X"66",X"09",X"32",X"30", + X"98",X"22",X"31",X"98",X"CD",X"56",X"2C",X"D8",X"C6",X"F0",X"FE",X"FC",X"D0",X"CD",X"56",X"2C", + X"D8",X"C6",X"F0",X"FE",X"FC",X"D0",X"3A",X"32",X"98",X"21",X"83",X"35",X"E7",X"3A",X"30",X"98", + X"86",X"32",X"30",X"98",X"B8",X"28",X"1E",X"6F",X"26",X"9A",X"7E",X"E6",X"3F",X"6F",X"26",X"00", + X"29",X"29",X"29",X"11",X"3B",X"45",X"19",X"3A",X"32",X"98",X"87",X"E7",X"7E",X"23",X"4E",X"ED", + X"43",X"32",X"98",X"B7",X"C9",X"37",X"C9",X"21",X"9D",X"9C",X"7E",X"B7",X"C8",X"3A",X"9A",X"9C", + X"B7",X"20",X"51",X"21",X"A0",X"9C",X"7E",X"B7",X"28",X"45",X"5F",X"16",X"9A",X"1A",X"87",X"87", + X"47",X"3A",X"9E",X"9C",X"EE",X"02",X"80",X"21",X"63",X"46",X"E7",X"7E",X"2F",X"EB",X"A6",X"77", + X"7D",X"CD",X"82",X"2B",X"21",X"98",X"9C",X"DF",X"2E",X"9C",X"DF",X"2E",X"93",X"DF",X"21",X"A0", + X"9C",X"11",X"9F",X"9C",X"01",X"60",X"00",X"ED",X"B0",X"EB",X"70",X"3A",X"9B",X"9C",X"FE",X"04", + X"30",X"02",X"3E",X"04",X"32",X"9B",X"9C",X"3A",X"39",X"99",X"FE",X"03",X"C4",X"44",X"20",X"21", + X"9D",X"9C",X"35",X"C9",X"21",X"98",X"9C",X"DF",X"2E",X"9C",X"DF",X"2E",X"93",X"DF",X"21",X"A0", + X"9C",X"11",X"9F",X"9C",X"ED",X"A0",X"1A",X"08",X"ED",X"A0",X"7E",X"B7",X"20",X"FA",X"08",X"12", + X"21",X"9D",X"9C",X"35",X"21",X"9B",X"9C",X"DF",X"CA",X"98",X"2D",X"7E",X"FE",X"03",X"C0",X"CD", + X"3F",X"20",X"3A",X"20",X"9D",X"B7",X"C0",X"ED",X"4B",X"A3",X"9C",X"78",X"B7",X"20",X"04",X"3A", + X"A0",X"9C",X"47",X"91",X"38",X"17",X"D6",X"02",X"20",X"08",X"0E",X"02",X"11",X"10",X"F0",X"C3", + X"51",X"2D",X"D6",X"1E",X"C0",X"0E",X"03",X"11",X"00",X"00",X"C3",X"51",X"2D",X"C6",X"02",X"20", + X"08",X"0E",X"00",X"11",X"10",X"10",X"C3",X"51",X"2D",X"C6",X"1E",X"C0",X"0E",X"01",X"11",X"20", + X"00",X"78",X"E6",X"F0",X"6F",X"A8",X"87",X"87",X"87",X"87",X"67",X"19",X"22",X"22",X"9D",X"22", + X"24",X"9D",X"ED",X"43",X"26",X"9D",X"68",X"26",X"9A",X"7E",X"E6",X"3F",X"6F",X"26",X"00",X"29", + X"29",X"29",X"11",X"3B",X"45",X"19",X"79",X"87",X"E7",X"5E",X"23",X"56",X"ED",X"53",X"28",X"9D", + X"21",X"8F",X"34",X"22",X"2A",X"9D",X"21",X"02",X"01",X"22",X"20",X"9D",X"21",X"D4",X"07",X"22", + X"2C",X"9D",X"3E",X"01",X"32",X"2E",X"9D",X"C9",X"3A",X"20",X"9D",X"0F",X"30",X"12",X"21",X"A0", + X"9C",X"06",X"60",X"3A",X"27",X"9D",X"4F",X"7E",X"B7",X"28",X"05",X"B9",X"C8",X"2C",X"10",X"F7", + X"3A",X"0C",X"99",X"32",X"9B",X"9C",X"ED",X"4B",X"A0",X"9C",X"78",X"91",X"38",X"17",X"D6",X"02", + X"20",X"08",X"0E",X"02",X"11",X"10",X"F0",X"C3",X"E9",X"2D",X"D6",X"1E",X"C0",X"0E",X"03",X"11", + X"00",X"00",X"C3",X"E9",X"2D",X"C6",X"02",X"20",X"08",X"0E",X"00",X"11",X"10",X"10",X"C3",X"E9", + X"2D",X"C6",X"1E",X"C0",X"0E",X"01",X"11",X"20",X"00",X"78",X"E6",X"F0",X"6F",X"A8",X"87",X"87", + X"87",X"87",X"67",X"19",X"22",X"22",X"9D",X"22",X"24",X"9D",X"ED",X"43",X"26",X"9D",X"68",X"26", + X"9A",X"7E",X"E6",X"3F",X"6F",X"26",X"00",X"29",X"29",X"29",X"11",X"3B",X"45",X"19",X"79",X"87", + X"E7",X"5E",X"23",X"56",X"ED",X"53",X"28",X"9D",X"21",X"8F",X"34",X"22",X"2A",X"9D",X"21",X"01", + X"03",X"22",X"20",X"9D",X"3E",X"01",X"32",X"2E",X"9D",X"CD",X"44",X"20",X"C3",X"49",X"20",X"21", + X"9C",X"9C",X"7E",X"B7",X"C8",X"FA",X"3A",X"2E",X"36",X"9F",X"34",X"6E",X"7E",X"B7",X"C8",X"36", + X"00",X"5F",X"16",X"9A",X"1A",X"B7",X"C8",X"7B",X"C3",X"82",X"2B",X"77",X"C9",X"AF",X"32",X"98", + X"9C",X"06",X"3F",X"26",X"9A",X"11",X"A0",X"9C",X"1A",X"B7",X"C8",X"6F",X"7E",X"A0",X"77",X"1C", + X"20",X"F6",X"C9",X"DD",X"21",X"00",X"9E",X"3A",X"00",X"9E",X"B7",X"28",X"08",X"3A",X"01",X"9E", + X"CF",X"75",X"2E",X"C2",X"2E",X"21",X"1F",X"9E",X"DF",X"C0",X"C9",X"DD",X"21",X"00",X"9E",X"DD", + X"36",X"00",X"01",X"DD",X"36",X"01",X"01",X"3A",X"0C",X"9D",X"D6",X"C0",X"0F",X"0F",X"E6",X"0F", + X"21",X"B4",X"30",X"E7",X"11",X"74",X"30",X"3A",X"0E",X"98",X"B7",X"28",X"03",X"11",X"94",X"30", + X"7E",X"DD",X"77",X"04",X"EB",X"E7",X"11",X"1A",X"9E",X"01",X"06",X"00",X"ED",X"B0",X"56",X"23", + X"5E",X"2A",X"02",X"9D",X"19",X"22",X"02",X"9E",X"AF",X"DD",X"77",X"05",X"3C",X"DD",X"77",X"06", + X"C9",X"C9",X"DD",X"35",X"06",X"C0",X"06",X"06",X"DD",X"70",X"06",X"D9",X"DD",X"34",X"05",X"DD", + X"7E",X"05",X"21",X"11",X"2F",X"E7",X"7E",X"B7",X"FA",X"0D",X"2F",X"87",X"87",X"4F",X"87",X"81", + X"4F",X"06",X"00",X"DD",X"7E",X"04",X"0F",X"0F",X"21",X"1C",X"2F",X"E7",X"5E",X"23",X"56",X"EB", + X"09",X"ED",X"4B",X"02",X"9E",X"11",X"0E",X"9E",X"CD",X"FF",X"2E",X"3A",X"03",X"9E",X"4F",X"06", + X"06",X"7E",X"FE",X"FF",X"28",X"01",X"81",X"12",X"23",X"1C",X"10",X"F5",X"C9",X"DD",X"36",X"00", + X"00",X"C9",X"00",X"01",X"02",X"03",X"02",X"03",X"04",X"05",X"06",X"FF",X"24",X"2F",X"78",X"2F", + X"CC",X"2F",X"20",X"30",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"FF",X"FF",X"FF",X"FF",X"FF", + X"00",X"02",X"FF",X"FF",X"00",X"02",X"00",X"00",X"FF",X"FF",X"FD",X"FD",X"00",X"03",X"00",X"03", + X"00",X"03",X"00",X"00",X"FD",X"FD",X"FA",X"FA",X"00",X"04",X"00",X"04",X"00",X"04",X"00",X"00", + X"FC",X"FC",X"F8",X"F8",X"01",X"04",X"01",X"04",X"01",X"04",X"FE",X"FE",X"FB",X"FB",X"F8",X"F8", + X"02",X"04",X"FF",X"FF",X"02",X"04",X"FC",X"FC",X"FF",X"FF",X"F9",X"F9",X"03",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FA",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"FF", + X"FF",X"FF",X"FF",X"FF",X"00",X"02",X"FF",X"FF",X"00",X"02",X"00",X"00",X"FF",X"FF",X"03",X"03", + X"00",X"03",X"00",X"03",X"00",X"03",X"00",X"00",X"03",X"03",X"06",X"06",X"00",X"04",X"00",X"04", + X"00",X"04",X"00",X"00",X"04",X"04",X"08",X"08",X"01",X"04",X"01",X"04",X"01",X"04",X"02",X"02", + X"05",X"05",X"08",X"08",X"02",X"04",X"FF",X"FF",X"02",X"04",X"04",X"04",X"FF",X"FF",X"07",X"07", + X"03",X"FF",X"FF",X"FF",X"FF",X"FF",X"06",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"FF",X"FF",X"FF", + X"FF",X"FF",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"FF",X"FF",X"FD",X"FD",X"00",X"02", + X"FF",X"FF",X"00",X"02",X"00",X"00",X"FD",X"FD",X"FA",X"FA",X"00",X"03",X"00",X"03",X"00",X"03", + X"00",X"00",X"FC",X"FC",X"F8",X"F8",X"00",X"04",X"00",X"04",X"00",X"04",X"FE",X"FE",X"FB",X"FB", + X"F8",X"F8",X"01",X"04",X"01",X"04",X"01",X"04",X"FC",X"FC",X"FF",X"FF",X"F9",X"F9",X"02",X"04", + X"02",X"04",X"02",X"04",X"FA",X"FF",X"FF",X"FF",X"FF",X"FF",X"03",X"FF",X"FF",X"FF",X"FF",X"FF", + X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"FF",X"FF", + X"03",X"03",X"00",X"02",X"FF",X"FF",X"00",X"02",X"00",X"00",X"03",X"03",X"06",X"06",X"00",X"03", + X"00",X"03",X"00",X"03",X"00",X"00",X"04",X"04",X"08",X"08",X"00",X"04",X"00",X"04",X"00",X"04", + X"02",X"02",X"05",X"05",X"08",X"08",X"01",X"04",X"01",X"04",X"01",X"04",X"04",X"04",X"FF",X"FF", + X"07",X"07",X"02",X"04",X"02",X"04",X"02",X"04",X"06",X"FF",X"FF",X"FF",X"FF",X"FF",X"03",X"FF", + X"FF",X"FF",X"FF",X"FF",X"0B",X"0E",X"0C",X"0D",X"0C",X"0A",X"07",X"06",X"09",X"0A",X"0C",X"0D", + X"0C",X"0E",X"FE",X"08",X"0F",X"0E",X"0F",X"0D",X"0C",X"0B",X"0B",X"03",X"0A",X"09",X"0F",X"0D", + X"0A",X"0E",X"0B",X"FA",X"0E",X"0C",X"0A",X"0D",X"0E",X"09",X"06",X"08",X"0A",X"09",X"0E",X"0F", + X"0A",X"0C",X"FC",X"07",X"0E",X"08",X"0F",X"0A",X"0E",X"0A",X"07",X"05",X"09",X"0A",X"0E",X"0A", + X"09",X"0B",X"08",X"FA",X"10",X"10",X"10",X"10",X"00",X"00",X"00",X"00",X"18",X"18",X"18",X"18", + X"08",X"08",X"08",X"08",X"11",X"FE",X"83",X"3A",X"00",X"9A",X"C3",X"F0",X"30",X"B7",X"28",X"F4", + X"6F",X"26",X"9A",X"3D",X"4F",X"E6",X"0F",X"47",X"A9",X"16",X"00",X"87",X"CB",X"12",X"87",X"CB", + X"12",X"80",X"80",X"5F",X"78",X"FE",X"0F",X"20",X"02",X"CB",X"EB",X"3E",X"84",X"B2",X"57",X"7E", + X"6F",X"26",X"00",X"29",X"29",X"7C",X"E5",X"87",X"21",X"73",X"3C",X"E7",X"4E",X"23",X"46",X"E1", + X"29",X"29",X"3E",X"03",X"A4",X"20",X"21",X"29",X"09",X"3E",X"04",X"CD",X"16",X"31",X"EB",X"01", + X"80",X"07",X"09",X"EB",X"3E",X"04",X"ED",X"A0",X"ED",X"A0",X"ED",X"A0",X"ED",X"A0",X"EB",X"01", + X"1C",X"00",X"09",X"EB",X"3D",X"20",X"EF",X"C9",X"3D",X"28",X"3A",X"7D",X"B7",X"28",X"06",X"2E", + X"00",X"87",X"C3",X"66",X"31",X"29",X"09",X"13",X"13",X"23",X"23",X"CB",X"63",X"28",X"04",X"1B", + X"1B",X"2B",X"2B",X"CB",X"4A",X"20",X"0A",X"01",X"08",X"00",X"09",X"EB",X"01",X"40",X"00",X"09", + X"EB",X"3E",X"02",X"CD",X"A8",X"31",X"01",X"08",X"00",X"09",X"EB",X"01",X"C0",X"07",X"09",X"EB", + X"3E",X"02",X"C3",X"A8",X"31",X"7D",X"29",X"09",X"D9",X"07",X"07",X"07",X"E6",X"03",X"CF",X"77", + X"31",X"96",X"31",X"9A",X"31",X"B8",X"31",X"D9",X"01",X"08",X"00",X"09",X"01",X"40",X"00",X"EB", + X"09",X"EB",X"3E",X"02",X"CD",X"16",X"31",X"01",X"08",X"00",X"09",X"EB",X"01",X"C0",X"07",X"09", + X"EB",X"3E",X"02",X"C3",X"16",X"31",X"D9",X"C3",X"82",X"31",X"D9",X"3E",X"04",X"CD",X"A8",X"31", + X"EB",X"01",X"80",X"07",X"09",X"EB",X"3E",X"04",X"ED",X"A0",X"ED",X"A0",X"23",X"23",X"EB",X"01", + X"1E",X"00",X"09",X"EB",X"3D",X"20",X"F1",X"C9",X"D9",X"23",X"23",X"13",X"13",X"C3",X"9B",X"31", + X"3A",X"35",X"99",X"CB",X"4F",X"0E",X"05",X"20",X"01",X"0D",X"21",X"2C",X"99",X"06",X"04",X"D9", + X"21",X"07",X"9D",X"11",X"20",X"00",X"06",X"06",X"3A",X"36",X"99",X"4F",X"3A",X"08",X"99",X"BE", + X"20",X"0B",X"08",X"71",X"7D",X"D9",X"91",X"77",X"2C",X"05",X"C8",X"D9",X"08",X"19",X"10",X"EF", + X"D9",X"36",X"00",X"C9",X"3A",X"08",X"99",X"5F",X"D6",X"02",X"0E",X"01",X"C3",X"41",X"32",X"3A", + X"08",X"99",X"5F",X"D6",X"20",X"0E",X"02",X"C3",X"41",X"32",X"3A",X"08",X"99",X"5F",X"C6",X"20", + X"0E",X"03",X"C3",X"41",X"32",X"3A",X"2B",X"99",X"F6",X"28",X"6F",X"26",X"99",X"7E",X"B7",X"C8", + X"36",X"00",X"08",X"7D",X"EE",X"01",X"32",X"2B",X"99",X"08",X"0F",X"38",X"C7",X"0F",X"38",X"09", + X"0F",X"0F",X"0F",X"38",X"CA",X"0F",X"38",X"D2",X"C9",X"3A",X"08",X"99",X"5F",X"C6",X"02",X"0E", + X"00",X"6F",X"26",X"9A",X"54",X"7E",X"E6",X"3F",X"FE",X"10",X"D0",X"32",X"37",X"99",X"3E",X"01", + X"32",X"94",X"9C",X"D9",X"CD",X"4D",X"2E",X"D9",X"36",X"00",X"43",X"ED",X"43",X"35",X"99",X"7D", + X"32",X"08",X"99",X"CD",X"87",X"20",X"CD",X"C0",X"31",X"3E",X"04",X"C3",X"74",X"32",X"3A",X"34", + X"99",X"B7",X"28",X"A1",X"3D",X"32",X"34",X"99",X"47",X"D9",X"CC",X"B3",X"32",X"CD",X"90",X"32", + X"D9",X"CD",X"32",X"33",X"3A",X"35",X"99",X"CF",X"CF",X"32",X"EF",X"32",X"FB",X"32",X"1F",X"33", + X"21",X"AF",X"32",X"3A",X"35",X"99",X"E7",X"4E",X"11",X"2C",X"99",X"06",X"04",X"26",X"9D",X"1A", + X"B7",X"C8",X"6F",X"7E",X"81",X"77",X"2C",X"2C",X"7E",X"81",X"77",X"1C",X"10",X"F1",X"C9",X"F8", + X"08",X"08",X"F8",X"2A",X"36",X"99",X"7C",X"B7",X"C8",X"26",X"9A",X"77",X"ED",X"4B",X"38",X"99", + X"78",X"BD",X"C0",X"79",X"FE",X"03",X"C0",X"3D",X"32",X"39",X"99",X"C3",X"44",X"20",X"C9",X"D9", + X"68",X"26",X"00",X"19",X"E5",X"11",X"04",X"00",X"19",X"3E",X"FF",X"06",X"04",X"11",X"20",X"00", + X"CB",X"DC",X"36",X"80",X"CB",X"9C",X"77",X"19",X"10",X"F6",X"D1",X"79",X"C3",X"F0",X"30",X"D9", + X"78",X"ED",X"44",X"83",X"6F",X"62",X"E5",X"2B",X"C3",X"D9",X"32",X"D9",X"EB",X"11",X"E0",X"FF", + X"AF",X"B0",X"28",X"03",X"19",X"10",X"FD",X"E5",X"19",X"3E",X"FF",X"06",X"04",X"11",X"01",X"00", + X"CB",X"DC",X"36",X"80",X"CB",X"9C",X"77",X"19",X"10",X"F6",X"D1",X"79",X"C3",X"F0",X"30",X"D9", + X"EB",X"11",X"20",X"00",X"AF",X"B0",X"28",X"03",X"19",X"10",X"FD",X"E5",X"1E",X"80",X"19",X"C3", + X"09",X"33",X"2A",X"36",X"99",X"4C",X"7D",X"3D",X"57",X"E6",X"0F",X"67",X"AA",X"16",X"00",X"87", + X"CB",X"12",X"87",X"CB",X"12",X"84",X"84",X"5F",X"7C",X"FE",X"0F",X"20",X"02",X"CB",X"EB",X"3E", + X"84",X"B2",X"57",X"D9",X"C9",X"26",X"00",X"11",X"96",X"33",X"3A",X"0D",X"9D",X"DD",X"BE",X"0D", + X"28",X"03",X"11",X"7E",X"33",X"DD",X"7E",X"1F",X"C6",X"08",X"0F",X"0F",X"0F",X"0F",X"84",X"E6", + X"0F",X"DD",X"AE",X"11",X"EB",X"E7",X"7E",X"DD",X"86",X"0F",X"DD",X"77",X"0C",X"C9",X"00",X"1E", + X"1A",X"16",X"12",X"0E",X"0A",X"06",X"02",X"1C",X"18",X"14",X"10",X"0C",X"08",X"04",X"00",X"1E", + X"1A",X"16",X"12",X"0E",X"0A",X"06",X"00",X"3C",X"38",X"34",X"30",X"2C",X"28",X"24",X"20",X"1C", + X"18",X"14",X"10",X"0C",X"08",X"04",X"00",X"3C",X"38",X"34",X"30",X"2C",X"28",X"24",X"3A",X"00", + X"9D",X"0F",X"30",X"06",X"CD",X"A5",X"3A",X"CD",X"6E",X"32",X"CD",X"A7",X"34",X"CD",X"63",X"2E", + X"C9",X"DD",X"7E",X"06",X"C6",X"04",X"DD",X"77",X"06",X"C9",X"3A",X"0D",X"9D",X"DD",X"BE",X"0D", + X"20",X"EF",X"3A",X"06",X"9D",X"32",X"33",X"99",X"3A",X"3B",X"99",X"CB",X"5F",X"28",X"24",X"ED", + X"4B",X"30",X"99",X"3E",X"04",X"81",X"4F",X"30",X"09",X"04",X"3E",X"03",X"B8",X"30",X"03",X"01", + X"FF",X"03",X"ED",X"43",X"30",X"99",X"2A",X"32",X"99",X"04",X"09",X"22",X"32",X"99",X"7C",X"32", + X"06",X"9D",X"C9",X"ED",X"4B",X"30",X"99",X"3E",X"F8",X"81",X"4F",X"38",X"E5",X"05",X"78",X"3C", + X"20",X"E0",X"01",X"00",X"00",X"C3",X"F2",X"33",X"3A",X"20",X"9D",X"B7",X"C8",X"3A",X"21",X"9D", + X"CF",X"2D",X"34",X"2D",X"34",X"52",X"34",X"52",X"34",X"6D",X"34",X"81",X"34",X"3A",X"9B",X"9C", + X"FE",X"04",X"38",X"07",X"21",X"00",X"00",X"22",X"20",X"9D",X"C9",X"06",X"0C",X"3D",X"20",X"02", + X"06",X"04",X"2A",X"24",X"9D",X"3A",X"07",X"98",X"A0",X"28",X"03",X"21",X"00",X"00",X"22",X"22", + X"9D",X"C9",X"3A",X"26",X"9D",X"C6",X"09",X"32",X"26",X"9D",X"3A",X"2C",X"9D",X"32",X"3D",X"9D", + X"CD",X"36",X"35",X"3A",X"3D",X"9D",X"32",X"2C",X"9D",X"CD",X"C4",X"3A",X"C9",X"CD",X"53",X"20", + X"21",X"9B",X"34",X"22",X"2A",X"9D",X"DD",X"36",X"0E",X"01",X"DD",X"36",X"10",X"40",X"DD",X"34", + X"01",X"CD",X"C4",X"3A",X"DD",X"35",X"10",X"C0",X"21",X"00",X"00",X"22",X"20",X"9D",X"C9",X"D4", + X"04",X"02",X"D0",X"04",X"02",X"CC",X"04",X"02",X"FF",X"8F",X"34",X"D4",X"05",X"01",X"D0",X"06", + X"01",X"CC",X"07",X"01",X"FF",X"9B",X"34",X"DD",X"21",X"00",X"9D",X"CD",X"D6",X"34",X"DD",X"21", + X"20",X"9D",X"CD",X"18",X"34",X"11",X"20",X"00",X"DD",X"19",X"3A",X"07",X"98",X"0F",X"30",X"02", + X"DD",X"19",X"06",X"02",X"1E",X"40",X"DD",X"7E",X"00",X"B7",X"28",X"05",X"D9",X"CD",X"D6",X"34", + X"D9",X"DD",X"19",X"10",X"F1",X"C9",X"DD",X"7E",X"01",X"CF",X"33",X"35",X"33",X"35",X"33",X"35", + X"33",X"35",X"E6",X"34",X"06",X"35",X"3A",X"0D",X"9D",X"DD",X"BE",X"0D",X"21",X"15",X"35",X"28", + X"03",X"21",X"24",X"35",X"11",X"40",X"01",X"DD",X"75",X"0A",X"DD",X"74",X"0B",X"DD",X"72",X"0E", + X"DD",X"73",X"10",X"DD",X"34",X"01",X"CD",X"C4",X"3A",X"DD",X"35",X"10",X"C0",X"AF",X"DD",X"77", + X"00",X"DD",X"77",X"01",X"C9",X"C1",X"08",X"04",X"D1",X"04",X"04",X"E1",X"0C",X"04",X"F1",X"10", + X"04",X"FF",X"15",X"35",X"91",X"07",X"03",X"81",X"08",X"03",X"93",X"09",X"03",X"83",X"1A",X"03", + X"FF",X"24",X"35",X"CD",X"CA",X"33",X"3A",X"03",X"99",X"3D",X"DD",X"BE",X"06",X"38",X"59",X"DD", + X"7E",X"08",X"CF",X"E2",X"36",X"EC",X"36",X"F8",X"36",X"02",X"37",X"0E",X"37",X"2A",X"37",X"48", + X"37",X"66",X"37",X"82",X"37",X"9E",X"37",X"BC",X"37",X"D8",X"37",X"F6",X"37",X"F6",X"37",X"F6", + X"37",X"F6",X"37",X"0E",X"38",X"2D",X"38",X"4C",X"38",X"6D",X"38",X"8E",X"38",X"AF",X"38",X"D0", + X"38",X"EF",X"38",X"0E",X"39",X"2D",X"39",X"4C",X"39",X"6D",X"39",X"8E",X"39",X"AD",X"39",X"CC", + X"39",X"ED",X"39",X"FE",X"E0",X"02",X"20",X"00",X"3A",X"34",X"99",X"B7",X"C8",X"3A",X"36",X"99", + X"95",X"3E",X"00",X"C0",X"3A",X"37",X"99",X"C9",X"3A",X"34",X"99",X"B7",X"28",X"14",X"3A",X"36", + X"99",X"DD",X"BE",X"07",X"20",X"0C",X"DD",X"7E",X"02",X"DD",X"77",X"04",X"DD",X"7E",X"03",X"C3", + X"C3",X"35",X"DD",X"7E",X"02",X"C6",X"06",X"E6",X"F0",X"DD",X"77",X"04",X"DD",X"7E",X"03",X"C6", + X"06",X"E6",X"F0",X"DD",X"77",X"05",X"DD",X"7E",X"09",X"21",X"83",X"35",X"E7",X"7E",X"DD",X"4E", + X"07",X"81",X"DD",X"77",X"07",X"6F",X"26",X"9A",X"7E",X"E6",X"3F",X"CC",X"88",X"35",X"6F",X"C6", + X"F0",X"FE",X"FC",X"D4",X"B5",X"36",X"26",X"00",X"29",X"29",X"29",X"11",X"3B",X"45",X"19",X"DD", + X"7E",X"09",X"FE",X"04",X"20",X"05",X"DD",X"7E",X"08",X"E6",X"03",X"57",X"87",X"E7",X"46",X"23", + X"DD",X"7E",X"08",X"C6",X"F0",X"38",X"11",X"A0",X"C6",X"F0",X"FE",X"FC",X"38",X"0A",X"DD",X"34", + X"00",X"DD",X"36",X"01",X"04",X"C3",X"69",X"20",X"DD",X"70",X"08",X"7E",X"DD",X"77",X"09",X"DD", + X"36",X"06",X"00",X"FE",X"04",X"20",X"03",X"DD",X"71",X"07",X"3A",X"2D",X"9D",X"DD",X"BE",X"0D", + X"C8",X"3A",X"0D",X"9D",X"DD",X"BE",X"0D",X"20",X"75",X"D9",X"11",X"01",X"01",X"FF",X"D9",X"21", + X"9D",X"9C",X"34",X"7A",X"2C",X"77",X"DD",X"7E",X"08",X"C6",X"F0",X"30",X"55",X"DD",X"6E",X"07", + X"26",X"9A",X"7E",X"E6",X"3F",X"FE",X"18",X"D8",X"E6",X"07",X"87",X"EB",X"21",X"D2",X"36",X"E7", + X"3A",X"08",X"9D",X"BE",X"C0",X"1A",X"D6",X"08",X"12",X"23",X"6E",X"26",X"00",X"CB",X"7D",X"28", + X"01",X"25",X"19",X"7E",X"D6",X"08",X"77",X"16",X"07",X"45",X"FF",X"58",X"FF",X"CD",X"82",X"20", + X"CD",X"7B",X"2E",X"11",X"0A",X"01",X"FF",X"21",X"09",X"99",X"35",X"2C",X"35",X"C0",X"AF",X"32", + X"2C",X"98",X"01",X"08",X"C0",X"ED",X"43",X"01",X"98",X"21",X"80",X"9B",X"7E",X"B7",X"C8",X"36", + X"01",X"C9",X"FE",X"FC",X"D8",X"21",X"02",X"04",X"22",X"00",X"9D",X"C3",X"30",X"20",X"CD",X"31", + X"2C",X"D0",X"C3",X"7D",X"20",X"3A",X"0D",X"9D",X"DD",X"BE",X"0D",X"20",X"0C",X"11",X"0F",X"01", + X"FF",X"CD",X"78",X"20",X"3E",X"01",X"32",X"94",X"9C",X"CD",X"8F",X"01",X"E6",X"03",X"28",X"F9", + X"6F",X"C9",X"1D",X"FE",X"15",X"02",X"1B",X"FE",X"11",X"02",X"1E",X"20",X"18",X"E0",X"16",X"20", + X"12",X"E0",X"CD",X"20",X"3A",X"DD",X"86",X"05",X"DD",X"77",X"03",X"C9",X"CD",X"20",X"3A",X"ED", + X"44",X"DD",X"86",X"05",X"DD",X"77",X"03",X"C9",X"CD",X"20",X"3A",X"DD",X"86",X"04",X"DD",X"77", + X"02",X"C9",X"CD",X"20",X"3A",X"ED",X"44",X"DD",X"86",X"04",X"DD",X"77",X"02",X"C9",X"CD",X"92", + X"26",X"01",X"00",X"40",X"CD",X"37",X"3A",X"CD",X"6D",X"3A",X"7C",X"D6",X"10",X"DD",X"77",X"02", + X"CD",X"96",X"3A",X"DD",X"74",X"03",X"CD",X"55",X"33",X"C9",X"CD",X"92",X"26",X"01",X"01",X"40", + X"CD",X"37",X"3A",X"CD",X"6D",X"3A",X"DD",X"74",X"02",X"CD",X"96",X"3A",X"7C",X"C6",X"10",X"DD", + X"77",X"03",X"26",X"08",X"CD",X"57",X"33",X"C9",X"CD",X"92",X"26",X"01",X"01",X"80",X"CD",X"37", + X"3A",X"CD",X"7A",X"3A",X"7C",X"C6",X"10",X"DD",X"77",X"02",X"CD",X"96",X"3A",X"DD",X"74",X"03", + X"26",X"08",X"CD",X"57",X"33",X"C9",X"CD",X"92",X"26",X"01",X"00",X"80",X"CD",X"37",X"3A",X"CD", + X"7A",X"3A",X"DD",X"74",X"02",X"CD",X"96",X"3A",X"7C",X"C6",X"10",X"DD",X"77",X"03",X"CD",X"55", + X"33",X"C9",X"CD",X"92",X"26",X"01",X"00",X"00",X"CD",X"37",X"3A",X"CD",X"6D",X"3A",X"DD",X"74", + X"02",X"CD",X"89",X"3A",X"7C",X"D6",X"10",X"DD",X"77",X"03",X"CD",X"55",X"33",X"C9",X"CD",X"92", + X"26",X"01",X"01",X"00",X"CD",X"37",X"3A",X"CD",X"6D",X"3A",X"7C",X"D6",X"10",X"DD",X"77",X"02", + X"CD",X"89",X"3A",X"DD",X"74",X"03",X"26",X"08",X"CD",X"57",X"33",X"C9",X"CD",X"92",X"26",X"01", + X"00",X"C0",X"CD",X"37",X"3A",X"CD",X"7A",X"3A",X"7C",X"C6",X"10",X"DD",X"77",X"02",X"CD",X"89", + X"3A",X"DD",X"74",X"03",X"CD",X"55",X"33",X"C9",X"CD",X"92",X"26",X"01",X"01",X"C0",X"CD",X"37", + X"3A",X"CD",X"7A",X"3A",X"DD",X"74",X"02",X"CD",X"89",X"3A",X"7C",X"D6",X"10",X"DD",X"77",X"03", + X"26",X"08",X"CD",X"57",X"33",X"C9",X"DD",X"34",X"06",X"DD",X"34",X"06",X"3A",X"03",X"99",X"D6", + X"02",X"DD",X"BE",X"06",X"D0",X"3E",X"08",X"DD",X"AE",X"11",X"DD",X"77",X"11",X"C9",X"CD",X"92", + X"26",X"01",X"00",X"40",X"CD",X"37",X"3A",X"CD",X"0E",X"3A",X"CD",X"6D",X"3A",X"7C",X"D6",X"10", + X"DD",X"77",X"02",X"CD",X"96",X"3A",X"DD",X"74",X"03",X"CD",X"55",X"33",X"C9",X"CD",X"92",X"26", + X"01",X"00",X"40",X"CD",X"37",X"3A",X"CD",X"17",X"3A",X"CD",X"6D",X"3A",X"7C",X"D6",X"10",X"DD", + X"77",X"02",X"CD",X"96",X"3A",X"DD",X"74",X"03",X"CD",X"55",X"33",X"C9",X"CD",X"92",X"26",X"01", + X"01",X"40",X"CD",X"37",X"3A",X"CD",X"0E",X"3A",X"CD",X"6D",X"3A",X"DD",X"74",X"02",X"CD",X"96", + X"3A",X"7C",X"C6",X"10",X"DD",X"77",X"03",X"26",X"08",X"CD",X"57",X"33",X"C9",X"CD",X"92",X"26", + X"01",X"01",X"40",X"CD",X"37",X"3A",X"CD",X"17",X"3A",X"CD",X"6D",X"3A",X"DD",X"74",X"02",X"CD", + X"96",X"3A",X"7C",X"C6",X"10",X"DD",X"77",X"03",X"26",X"08",X"CD",X"57",X"33",X"C9",X"CD",X"92", + X"26",X"01",X"01",X"80",X"CD",X"37",X"3A",X"CD",X"0E",X"3A",X"CD",X"7A",X"3A",X"7C",X"C6",X"10", + X"DD",X"77",X"02",X"CD",X"96",X"3A",X"DD",X"74",X"03",X"26",X"08",X"CD",X"57",X"33",X"C9",X"CD", + X"92",X"26",X"01",X"01",X"80",X"CD",X"37",X"3A",X"CD",X"17",X"3A",X"CD",X"7A",X"3A",X"7C",X"C6", + X"10",X"DD",X"77",X"02",X"CD",X"96",X"3A",X"DD",X"74",X"03",X"26",X"08",X"CD",X"57",X"33",X"C9", + X"CD",X"92",X"26",X"01",X"00",X"80",X"CD",X"37",X"3A",X"CD",X"0E",X"3A",X"CD",X"7A",X"3A",X"DD", + X"74",X"02",X"CD",X"96",X"3A",X"7C",X"C6",X"10",X"DD",X"77",X"03",X"CD",X"55",X"33",X"C9",X"CD", + X"92",X"26",X"01",X"00",X"80",X"CD",X"37",X"3A",X"CD",X"17",X"3A",X"CD",X"7A",X"3A",X"DD",X"74", + X"02",X"CD",X"96",X"3A",X"7C",X"C6",X"10",X"DD",X"77",X"03",X"CD",X"55",X"33",X"C9",X"CD",X"92", + X"26",X"01",X"00",X"00",X"CD",X"37",X"3A",X"CD",X"0E",X"3A",X"CD",X"6D",X"3A",X"DD",X"74",X"02", + X"CD",X"89",X"3A",X"7C",X"D6",X"10",X"DD",X"77",X"03",X"CD",X"55",X"33",X"C9",X"CD",X"92",X"26", + X"01",X"00",X"00",X"CD",X"37",X"3A",X"CD",X"17",X"3A",X"CD",X"6D",X"3A",X"DD",X"74",X"02",X"CD", + X"89",X"3A",X"7C",X"D6",X"10",X"DD",X"77",X"03",X"CD",X"55",X"33",X"C9",X"CD",X"92",X"26",X"01", + X"01",X"00",X"CD",X"37",X"3A",X"CD",X"0E",X"3A",X"CD",X"6D",X"3A",X"7C",X"D6",X"10",X"DD",X"77", + X"02",X"CD",X"89",X"3A",X"DD",X"74",X"03",X"26",X"08",X"CD",X"57",X"33",X"C9",X"CD",X"92",X"26", + X"01",X"01",X"00",X"CD",X"37",X"3A",X"CD",X"17",X"3A",X"CD",X"6D",X"3A",X"7C",X"D6",X"10",X"DD", + X"77",X"02",X"CD",X"89",X"3A",X"DD",X"74",X"03",X"26",X"08",X"CD",X"57",X"33",X"C9",X"CD",X"92", + X"26",X"01",X"00",X"C0",X"CD",X"37",X"3A",X"CD",X"0E",X"3A",X"CD",X"7A",X"3A",X"7C",X"C6",X"10", + X"DD",X"77",X"02",X"CD",X"89",X"3A",X"DD",X"74",X"03",X"CD",X"55",X"33",X"C9",X"CD",X"92",X"26", + X"01",X"00",X"C0",X"CD",X"37",X"3A",X"CD",X"17",X"3A",X"CD",X"7A",X"3A",X"7C",X"C6",X"10",X"DD", + X"77",X"02",X"CD",X"89",X"3A",X"DD",X"74",X"03",X"CD",X"55",X"33",X"C9",X"CD",X"92",X"26",X"01", + X"01",X"C0",X"CD",X"37",X"3A",X"CD",X"0E",X"3A",X"CD",X"7A",X"3A",X"DD",X"74",X"02",X"CD",X"89", + X"3A",X"7C",X"D6",X"10",X"DD",X"77",X"03",X"26",X"08",X"CD",X"57",X"33",X"C9",X"CD",X"92",X"26", + X"01",X"01",X"C0",X"CD",X"37",X"3A",X"CD",X"17",X"3A",X"CD",X"7A",X"3A",X"DD",X"74",X"02",X"CD", + X"89",X"3A",X"7C",X"D6",X"10",X"DD",X"77",X"03",X"26",X"08",X"CD",X"57",X"33",X"C9",X"21",X"00", + X"FD",X"19",X"D0",X"11",X"00",X"03",X"C9",X"21",X"00",X"FD",X"09",X"D0",X"01",X"00",X"03",X"C9", + X"CD",X"92",X"26",X"DD",X"77",X"1F",X"5F",X"3A",X"07",X"99",X"87",X"87",X"87",X"CD",X"66",X"26", + X"7C",X"CB",X"15",X"30",X"01",X"3C",X"C9",X"C6",X"02",X"30",X"02",X"3E",X"FF",X"CB",X"41",X"28", + X"02",X"ED",X"44",X"E6",X"FC",X"0F",X"0F",X"80",X"DD",X"77",X"1F",X"87",X"21",X"7A",X"4D",X"5F", + X"16",X"00",X"30",X"01",X"14",X"19",X"4E",X"23",X"5E",X"16",X"00",X"42",X"CB",X"21",X"CB",X"10", + X"CB",X"21",X"CB",X"10",X"CB",X"23",X"CB",X"12",X"CB",X"23",X"CB",X"12",X"C9",X"3A",X"07",X"99", + X"DD",X"66",X"04",X"2E",X"80",X"09",X"3D",X"20",X"FC",X"C9",X"3A",X"07",X"99",X"DD",X"66",X"04", + X"2E",X"80",X"B7",X"ED",X"42",X"3D",X"20",X"FB",X"C9",X"3A",X"07",X"99",X"47",X"DD",X"66",X"05", + X"2E",X"80",X"19",X"10",X"FD",X"C9",X"3A",X"07",X"99",X"47",X"DD",X"66",X"05",X"2E",X"80",X"B7", + X"ED",X"52",X"10",X"FC",X"C9",X"CD",X"0D",X"3B",X"3A",X"3B",X"99",X"E6",X"33",X"C8",X"47",X"21", + X"3A",X"99",X"AE",X"A0",X"C8",X"47",X"11",X"2A",X"99",X"1A",X"F6",X"28",X"6F",X"26",X"99",X"70", + X"EE",X"01",X"12",X"C9",X"DD",X"35",X"0E",X"C0",X"DD",X"E5",X"E1",X"11",X"0A",X"00",X"19",X"5E", + X"2C",X"56",X"2C",X"EB",X"7E",X"3C",X"28",X"0D",X"ED",X"A0",X"ED",X"A0",X"ED",X"A0",X"DD",X"75", + X"0A",X"DD",X"74",X"0B",X"C9",X"23",X"4E",X"23",X"46",X"60",X"69",X"C3",X"D8",X"3A",X"21",X"20", + X"99",X"35",X"20",X"0F",X"23",X"7E",X"34",X"2B",X"EB",X"21",X"F2",X"11",X"87",X"E7",X"ED",X"A0", + X"7E",X"18",X"4F",X"3A",X"A8",X"9C",X"B7",X"28",X"49",X"3E",X"08",X"18",X"45",X"3A",X"3B",X"99", + X"32",X"3A",X"99",X"3A",X"08",X"98",X"0F",X"30",X"D5",X"3A",X"0E",X"98",X"B7",X"28",X"10",X"3A", + X"18",X"98",X"E6",X"01",X"47",X"3A",X"1C",X"98",X"E6",X"3E",X"B0",X"32",X"3B",X"99",X"C9",X"3A", + X"1C",X"98",X"E6",X"01",X"4F",X"3A",X"18",X"98",X"87",X"E6",X"74",X"47",X"0F",X"E6",X"08",X"ED", + X"44",X"80",X"CB",X"77",X"28",X"02",X"D6",X"30",X"B1",X"47",X"3A",X"1E",X"98",X"07",X"07",X"E6", + X"02",X"B0",X"32",X"3B",X"99",X"C9",X"DD",X"6E",X"07",X"26",X"9A",X"7E",X"E6",X"3F",X"BE",X"28", + X"05",X"3E",X"01",X"32",X"94",X"9C",X"7E",X"E6",X"3F",X"FE",X"04",X"30",X"15",X"EB",X"47",X"87", + X"87",X"4F",X"DD",X"7E",X"09",X"EE",X"02",X"81",X"21",X"B1",X"3B",X"E7",X"7E",X"12",X"16",X"07", + X"FF",X"C9",X"FE",X"0C",X"30",X"07",X"36",X"0B",X"EB",X"16",X"07",X"FF",X"C9",X"CB",X"67",X"C8", + X"3A",X"80",X"9B",X"B7",X"CA",X"BD",X"27",X"EB",X"1A",X"E6",X"07",X"87",X"21",X"D3",X"36",X"E7", + X"7E",X"83",X"4F",X"EB",X"3A",X"88",X"9B",X"B9",X"28",X"04",X"BD",X"C2",X"BD",X"27",X"11",X"71", + X"27",X"D5",X"C3",X"BD",X"27",X"05",X"05",X"04",X"04",X"07",X"06",X"06",X"07",X"08",X"09",X"08", + X"09",X"CD",X"C8",X"3B",X"CD",X"F4",X"3B",X"C9",X"3A",X"00",X"9D",X"0F",X"D0",X"ED",X"5B",X"02", + X"9D",X"2A",X"07",X"9D",X"D9",X"06",X"05",X"11",X"20",X"00",X"DD",X"21",X"20",X"9D",X"D9",X"CD", + X"3E",X"3C",X"38",X"06",X"D9",X"DD",X"19",X"10",X"F5",X"C9",X"CD",X"33",X"3C",X"21",X"02",X"04", + X"22",X"00",X"9D",X"C9",X"0E",X"04",X"11",X"20",X"00",X"FD",X"21",X"20",X"9D",X"FD",X"7E",X"00", + X"0F",X"30",X"20",X"FD",X"E5",X"DD",X"E1",X"DD",X"19",X"41",X"D9",X"FD",X"56",X"03",X"FD",X"5E", + X"02",X"FD",X"66",X"08",X"FD",X"6E",X"07",X"D9",X"D9",X"CD",X"3E",X"3C",X"38",X"0B",X"D9",X"DD", + X"19",X"10",X"F5",X"FD",X"19",X"0D",X"20",X"D5",X"C9",X"CD",X"56",X"3B",X"FD",X"34",X"00",X"FD", + X"36",X"01",X"04",X"CD",X"69",X"20",X"DD",X"34",X"00",X"DD",X"36",X"01",X"04",X"C9",X"DD",X"7E", + X"00",X"0F",X"D0",X"DD",X"7E",X"02",X"93",X"C6",X"08",X"FE",X"11",X"D0",X"DD",X"7E",X"03",X"92", + X"C6",X"08",X"FE",X"11",X"D0",X"DD",X"7E",X"07",X"BD",X"20",X"14",X"7C",X"D6",X"08",X"FE",X"08", + X"30",X"0D",X"C6",X"08",X"E6",X"FE",X"67",X"DD",X"7E",X"08",X"E6",X"FE",X"BC",X"20",X"02",X"37", + X"C9",X"B7",X"C9",X"7B",X"3C",X"7B",X"38",X"5B",X"34",X"BB",X"2C",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"80",X"80",X"80",X"80",X"80", + X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"83",X"5B",X"5A",X"82",X"63", + X"53",X"52",X"62",X"61",X"51",X"50",X"60",X"81",X"59",X"58",X"80",X"9C",X"9C",X"9C",X"9C",X"9C", + X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"83",X"43",X"42",X"82",X"4B", + X"3B",X"3A",X"4A",X"49",X"39",X"38",X"48",X"81",X"41",X"40",X"80",X"9D",X"9D",X"9D",X"9D",X"9D", + X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"83",X"AD",X"AF",X"82",X"AE", + X"6B",X"6A",X"7A",X"AC",X"69",X"68",X"78",X"81",X"79",X"7B",X"80",X"9E",X"9E",X"9E",X"9E",X"9E", + X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"83",X"9B",X"9A",X"82",X"97", + X"82",X"38",X"62",X"95",X"38",X"50",X"60",X"81",X"59",X"58",X"80",X"9C",X"9C",X"9C",X"9C",X"9C", + X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"83",X"5B",X"5A",X"82",X"63", + X"53",X"38",X"96",X"61",X"38",X"82",X"94",X"81",X"99",X"98",X"80",X"9C",X"9C",X"9C",X"9C",X"9C", + X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"83",X"43",X"42",X"82",X"97", + X"38",X"3A",X"4A",X"95",X"82",X"38",X"48",X"81",X"99",X"98",X"80",X"9D",X"9D",X"9D",X"9D",X"9D", + X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"83",X"9B",X"9A",X"82",X"4B", + X"38",X"82",X"96",X"49",X"39",X"38",X"94",X"81",X"41",X"40",X"80",X"9D",X"9D",X"9D",X"9D",X"9D", + X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"83",X"AD",X"AF",X"82",X"97", + X"AD",X"AF",X"96",X"95",X"AD",X"AF",X"94",X"81",X"79",X"7B",X"80",X"9E",X"9E",X"9E",X"9E",X"9E", + X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"83",X"9B",X"9A",X"82",X"AE", + X"7A",X"7A",X"7A",X"AC",X"78",X"78",X"78",X"81",X"99",X"98",X"80",X"9E",X"9E",X"9E",X"9E",X"9E", + X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"83",X"9B",X"9A",X"82",X"97", + X"8F",X"8E",X"7A",X"95",X"8D",X"8C",X"78",X"81",X"79",X"7B",X"80",X"9E",X"9E",X"9E",X"9E",X"9E", + X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"83",X"9B",X"9A",X"82",X"97", + X"82",X"82",X"96",X"95",X"82",X"82",X"94",X"81",X"99",X"98",X"80",X"9E",X"9E",X"9E",X"9E",X"9E", + X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"83",X"C3",X"C2",X"82",X"BF", + X"8B",X"8A",X"BE",X"BD",X"89",X"88",X"BC",X"81",X"C1",X"C0",X"80",X"9E",X"9E",X"9E",X"9E",X"9E", + X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"83",X"C3",X"C2",X"82",X"BF", + X"8B",X"8A",X"BE",X"BD",X"89",X"88",X"BC",X"81",X"C1",X"C0",X"80",X"9E",X"9E",X"9E",X"9E",X"9E", + X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"83",X"C3",X"C2",X"82",X"BF", + X"8B",X"8A",X"BE",X"BD",X"89",X"88",X"BC",X"81",X"C1",X"C0",X"80",X"9E",X"9E",X"9E",X"9E",X"9E", + X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"83",X"C3",X"C2",X"82",X"BF", + X"8B",X"8A",X"BE",X"BD",X"89",X"88",X"BC",X"81",X"C1",X"C0",X"80",X"9E",X"9E",X"9E",X"9E",X"9E", + X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"65",X"65",X"65",X"65",X"65", + X"65",X"65",X"65",X"63",X"53",X"5B",X"5B",X"5D",X"51",X"50",X"5D",X"10",X"10",X"10",X"10",X"10", + X"10",X"10",X"10",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"65",X"65",X"65",X"65",X"65", + X"65",X"65",X"65",X"5B",X"5B",X"5A",X"63",X"5D",X"59",X"58",X"5D",X"10",X"10",X"10",X"10",X"10", + X"10",X"10",X"10",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"52",X"57",X"56",X"52",X"6F", + X"55",X"54",X"54",X"65",X"65",X"65",X"65",X"65",X"65",X"65",X"65",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"52",X"5F",X"5E",X"52",X"54", + X"54",X"5C",X"6F",X"65",X"65",X"65",X"65",X"65",X"65",X"65",X"65",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"4B",X"42",X"65",X"65",X"43", + X"42",X"65",X"65",X"41",X"40",X"65",X"65",X"4B",X"62",X"65",X"65",X"C0",X"C0",X"10",X"10",X"C0", + X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"4B",X"62",X"65",X"65",X"47", + X"46",X"65",X"65",X"45",X"42",X"65",X"65",X"4B",X"42",X"65",X"65",X"C0",X"C0",X"10",X"10",X"C0", + X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"65",X"65",X"4B",X"44",X"65", + X"65",X"4B",X"4A",X"65",X"65",X"49",X"48",X"65",X"65",X"6E",X"44",X"10",X"10",X"C0",X"C0",X"10", + X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"65",X"65",X"6E",X"44",X"65", + X"65",X"4F",X"4E",X"65",X"65",X"4B",X"4C",X"65",X"65",X"4B",X"44",X"10",X"10",X"C0",X"C0",X"10", + X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"64",X"64",X"64",X"64",X"64", + X"64",X"64",X"64",X"67",X"33",X"3B",X"3B",X"6A",X"31",X"30",X"3D",X"10",X"10",X"10",X"10",X"10", + X"10",X"10",X"10",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"64",X"64",X"64",X"64",X"64", + X"64",X"64",X"64",X"3B",X"3B",X"3A",X"67",X"3D",X"39",X"38",X"6B",X"10",X"10",X"10",X"10",X"10", + X"10",X"10",X"10",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"6A",X"37",X"36",X"32",X"73", + X"35",X"34",X"34",X"64",X"64",X"64",X"64",X"64",X"64",X"64",X"64",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"32",X"3F",X"3E",X"6B",X"34", + X"34",X"3C",X"73",X"64",X"64",X"64",X"64",X"64",X"64",X"64",X"64",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"2B",X"22",X"64",X"64",X"23", + X"22",X"64",X"64",X"21",X"20",X"64",X"64",X"76",X"66",X"64",X"64",X"C0",X"C0",X"10",X"10",X"C0", + X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"74",X"66",X"64",X"64",X"27", + X"26",X"64",X"64",X"25",X"22",X"64",X"64",X"2B",X"22",X"64",X"64",X"C0",X"C0",X"10",X"10",X"C0", + X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"64",X"64",X"2B",X"24",X"64", + X"64",X"2B",X"2A",X"64",X"64",X"29",X"28",X"64",X"64",X"72",X"76",X"10",X"10",X"C0",X"C0",X"10", + X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"64",X"64",X"72",X"74",X"64", + X"64",X"2F",X"2E",X"64",X"64",X"2B",X"2C",X"64",X"64",X"2B",X"24",X"10",X"10",X"C0",X"C0",X"10", + X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"7B",X"7A",X"7A",X"7A",X"7B", + X"7A",X"7A",X"7A",X"7B",X"7A",X"7A",X"7A",X"79",X"78",X"78",X"78",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"83",X"5B",X"5A",X"82",X"63", + X"53",X"B6",X"66",X"61",X"B5",X"54",X"64",X"81",X"5D",X"5C",X"80",X"9C",X"9C",X"9C",X"9C",X"9C", + X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"83",X"47",X"46",X"82",X"4B", + X"BB",X"3E",X"4E",X"49",X"39",X"B8",X"4C",X"81",X"41",X"40",X"80",X"9D",X"9D",X"9D",X"9D",X"9D", + X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"83",X"AD",X"AF",X"82",X"B2", + X"73",X"72",X"7E",X"B0",X"71",X"70",X"7C",X"81",X"79",X"7B",X"80",X"9E",X"9E",X"9E",X"9E",X"9E", + X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"83",X"9B",X"9A",X"82",X"97", + X"82",X"38",X"66",X"95",X"38",X"54",X"64",X"81",X"5D",X"5C",X"80",X"9C",X"9C",X"9C",X"9C",X"9C", + X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"83",X"5F",X"5E",X"82",X"67", + X"57",X"38",X"96",X"65",X"38",X"82",X"94",X"81",X"99",X"98",X"80",X"9C",X"9C",X"9C",X"9C",X"9C", + X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"83",X"47",X"46",X"82",X"97", + X"38",X"3E",X"4E",X"95",X"82",X"38",X"4C",X"81",X"99",X"98",X"80",X"9D",X"9D",X"9D",X"9D",X"9D", + X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"83",X"9B",X"9A",X"82",X"4F", + X"38",X"82",X"96",X"4D",X"3D",X"38",X"94",X"81",X"45",X"44",X"80",X"9D",X"9D",X"9D",X"9D",X"9D", + X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"83",X"B1",X"B3",X"82",X"97", + X"B1",X"B3",X"96",X"95",X"B1",X"B3",X"94",X"81",X"7D",X"7F",X"80",X"9E",X"9E",X"9E",X"9E",X"9E", + X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"83",X"9B",X"9A",X"82",X"B2", + X"7E",X"7E",X"7E",X"B0",X"7C",X"7C",X"7C",X"81",X"99",X"98",X"80",X"9E",X"9E",X"9E",X"9E",X"9E", + X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"83",X"9B",X"9A",X"82",X"97", + X"8F",X"8E",X"93",X"95",X"8D",X"8C",X"91",X"81",X"7D",X"7F",X"80",X"9E",X"9E",X"9E",X"9E",X"9E", + X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"83",X"9B",X"9A",X"82",X"97", + X"82",X"82",X"96",X"95",X"82",X"82",X"94",X"81",X"99",X"98",X"80",X"9E",X"9E",X"9E",X"9E",X"9E", + X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"83",X"C3",X"C2",X"82",X"BF", + X"8B",X"8A",X"DA",X"BD",X"89",X"88",X"D8",X"81",X"C1",X"C0",X"80",X"9E",X"9E",X"9E",X"9E",X"9E", + X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"83",X"C3",X"C2",X"82",X"BF", + X"8B",X"8A",X"BE",X"BD",X"89",X"88",X"BC",X"81",X"DD",X"DC",X"80",X"9E",X"9E",X"9E",X"9E",X"9E", + X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"83",X"C3",X"C2",X"82",X"DB", + X"8B",X"8A",X"BE",X"D9",X"89",X"88",X"BC",X"81",X"C1",X"C0",X"80",X"9E",X"9E",X"9E",X"9E",X"9E", + X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"83",X"DF",X"DE",X"82",X"BF", + X"8B",X"8A",X"BE",X"BD",X"89",X"88",X"BC",X"81",X"C1",X"C0",X"80",X"9E",X"9E",X"9E",X"9E",X"9E", + X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"65",X"65",X"65",X"65",X"65", + X"65",X"65",X"65",X"63",X"53",X"5B",X"5B",X"54",X"51",X"50",X"54",X"10",X"10",X"10",X"10",X"10", + X"10",X"10",X"10",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"65",X"65",X"65",X"65",X"65", + X"65",X"65",X"65",X"5B",X"5B",X"5A",X"63",X"54",X"59",X"58",X"54",X"10",X"10",X"10",X"10",X"10", + X"10",X"10",X"10",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"52",X"57",X"56",X"52",X"6F", + X"55",X"54",X"54",X"65",X"65",X"65",X"65",X"65",X"65",X"65",X"65",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"52",X"5F",X"5E",X"52",X"54", + X"54",X"5C",X"6F",X"65",X"65",X"65",X"65",X"65",X"65",X"65",X"65",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"4B",X"42",X"65",X"65",X"43", + X"42",X"65",X"65",X"41",X"40",X"65",X"65",X"4B",X"62",X"65",X"65",X"C0",X"C0",X"10",X"10",X"C0", + X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"4B",X"62",X"65",X"65",X"47", + X"46",X"65",X"65",X"45",X"42",X"65",X"65",X"4B",X"42",X"65",X"65",X"C0",X"C0",X"10",X"10",X"C0", + X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"65",X"65",X"4B",X"44",X"65", + X"65",X"4B",X"4A",X"65",X"65",X"49",X"48",X"65",X"65",X"6E",X"42",X"10",X"10",X"C0",X"C0",X"10", + X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"65",X"65",X"6E",X"42",X"65", + X"65",X"4F",X"4E",X"65",X"65",X"4B",X"4C",X"65",X"65",X"4B",X"44",X"10",X"10",X"C0",X"C0",X"10", + X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"64",X"64",X"64",X"64",X"64", + X"64",X"64",X"64",X"61",X"13",X"1B",X"1B",X"68",X"11",X"70",X"1D",X"10",X"10",X"10",X"10",X"10", + X"10",X"10",X"10",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"64",X"64",X"64",X"64",X"64", + X"64",X"64",X"64",X"1B",X"1B",X"1A",X"61",X"1D",X"19",X"18",X"69",X"10",X"10",X"10",X"10",X"10", + X"10",X"10",X"10",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"68",X"17",X"16",X"12",X"6D", + X"15",X"14",X"14",X"64",X"64",X"64",X"64",X"64",X"64",X"64",X"64",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"12",X"1F",X"1E",X"69",X"14", + X"14",X"1C",X"6D",X"64",X"64",X"64",X"64",X"64",X"64",X"64",X"64",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"0B",X"02",X"64",X"64",X"03", + X"02",X"64",X"64",X"01",X"00",X"64",X"64",X"77",X"60",X"64",X"64",X"C0",X"C0",X"10",X"10",X"C0", + X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"75",X"60",X"64",X"64",X"07", + X"06",X"64",X"64",X"05",X"02",X"64",X"64",X"0B",X"02",X"64",X"64",X"C0",X"C0",X"10",X"10",X"C0", + X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"64",X"64",X"0B",X"04",X"64", + X"64",X"0B",X"0A",X"64",X"64",X"09",X"08",X"64",X"64",X"6C",X"77",X"10",X"10",X"C0",X"C0",X"10", + X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"64",X"64",X"6C",X"75",X"64", + X"64",X"0F",X"0E",X"64",X"64",X"0B",X"0C",X"64",X"64",X"0B",X"04",X"10",X"10",X"C0",X"C0",X"10", + X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"83",X"5F",X"5E",X"82",X"67", + X"57",X"BA",X"62",X"65",X"B9",X"50",X"60",X"81",X"59",X"58",X"80",X"9C",X"9C",X"9C",X"9C",X"9C", + X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"83",X"43",X"42",X"82",X"4F", + X"B7",X"3A",X"4A",X"4D",X"3D",X"B4",X"48",X"81",X"45",X"44",X"80",X"9D",X"9D",X"9D",X"9D",X"9D", + X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"83",X"B1",X"B3",X"82",X"AE", + X"6F",X"6E",X"7A",X"AC",X"6D",X"6C",X"78",X"81",X"7D",X"7F",X"80",X"9E",X"9E",X"9E",X"9E",X"9E", + X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"83",X"5F",X"5E",X"82",X"67", + X"57",X"56",X"66",X"65",X"55",X"54",X"64",X"81",X"5D",X"5C",X"80",X"9C",X"9C",X"9C",X"9C",X"9C", + X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"83",X"47",X"46",X"82",X"4F", + X"3F",X"3E",X"4E",X"4D",X"3D",X"3C",X"4C",X"81",X"45",X"44",X"80",X"9D",X"9D",X"9D",X"9D",X"9D", + X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"83",X"B1",X"B3",X"82",X"B2", + X"77",X"76",X"7E",X"B0",X"75",X"74",X"7C",X"81",X"7D",X"7F",X"80",X"9E",X"9E",X"9E",X"9E",X"9E", + X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"0E",X"04",X"0F",X"04",X"0C", + X"04",X"0D",X"04",X"06",X"03",X"07",X"02",X"09",X"01",X"08",X"00",X"04",X"01",X"0B",X"00",X"0A", + X"03",X"05",X"02",X"01",X"00",X"03",X"01",X"00",X"02",X"02",X"03",X"06",X"03",X"07",X"02",X"0C", + X"04",X"0D",X"04",X"0E",X"04",X"0F",X"04",X"09",X"01",X"08",X"00",X"04",X"01",X"0F",X"04",X"0C", + X"04",X"05",X"02",X"0E",X"04",X"0B",X"00",X"0A",X"03",X"0D",X"04",X"0E",X"04",X"03",X"01",X"0C", + X"04",X"02",X"03",X"01",X"00",X"0F",X"04",X"00",X"02",X"0D",X"04",X"06",X"03",X"07",X"02",X"0C", + X"04",X"0D",X"04",X"0E",X"04",X"0F",X"04",X"0C",X"04",X"0D",X"04",X"06",X"03",X"07",X"02",X"09", + X"01",X"08",X"00",X"04",X"01",X"0B",X"00",X"0A",X"03",X"05",X"02",X"01",X"00",X"03",X"01",X"00", + X"02",X"02",X"03",X"0E",X"04",X"0F",X"04",X"0C",X"04",X"0D",X"04",X"0E",X"04",X"1F",X"00",X"1D", + X"03",X"0D",X"04",X"15",X"03",X"17",X"02",X"0C",X"04",X"0D",X"04",X"0E",X"04",X"0F",X"04",X"1B", + X"01",X"19",X"00",X"11",X"01",X"0F",X"04",X"0C",X"04",X"13",X"02",X"0E",X"04",X"1E",X"00",X"1C", + X"03",X"0D",X"04",X"0E",X"04",X"0F",X"04",X"1A",X"01",X"18",X"00",X"14",X"03",X"16",X"02",X"0C", + X"04",X"0D",X"04",X"10",X"01",X"0F",X"04",X"0C",X"04",X"12",X"02",X"0E",X"04",X"1F",X"00",X"1D", + X"03",X"0D",X"04",X"15",X"03",X"17",X"02",X"0C",X"04",X"0D",X"04",X"0E",X"04",X"0F",X"04",X"1B", + X"01",X"19",X"00",X"11",X"01",X"0F",X"04",X"0C",X"04",X"13",X"02",X"0E",X"04",X"1E",X"00",X"1C", + X"03",X"0D",X"04",X"0E",X"04",X"0F",X"04",X"1A",X"01",X"18",X"00",X"14",X"03",X"16",X"02",X"0C", + X"04",X"0D",X"04",X"10",X"01",X"0F",X"04",X"0C",X"04",X"12",X"02",X"0E",X"04",X"0F",X"04",X"0C", + X"04",X"0D",X"04",X"0E",X"04",X"0F",X"04",X"0C",X"04",X"0D",X"04",X"0E",X"04",X"0F",X"04",X"0C", + X"04",X"0D",X"04",X"0E",X"04",X"0F",X"04",X"0C",X"04",X"0D",X"04",X"0E",X"04",X"0F",X"04",X"0C", + X"04",X"0D",X"04",X"00",X"00",X"00",X"00",X"40",X"40",X"80",X"80",X"40",X"80",X"80",X"40",X"40", + X"80",X"40",X"80",X"40",X"40",X"00",X"00",X"00",X"00",X"40",X"40",X"40",X"00",X"00",X"40",X"00", + X"40",X"40",X"00",X"00",X"40",X"00",X"40",X"40",X"00",X"40",X"00",X"40",X"40",X"00",X"00",X"00", + X"00",X"00",X"00",X"40",X"40",X"40",X"40",X"40",X"40",X"40",X"40",X"40",X"40",X"40",X"40",X"40", + X"40",X"40",X"40",X"00",X"40",X"40",X"00",X"40",X"40",X"00",X"00",X"00",X"00",X"40",X"40",X"40", + X"00",X"00",X"40",X"00",X"40",X"40",X"00",X"00",X"00",X"40",X"40",X"40",X"40",X"00",X"00",X"40", + X"00",X"00",X"40",X"00",X"40",X"40",X"00",X"40",X"40",X"00",X"00",X"00",X"00",X"40",X"40",X"40", + X"00",X"00",X"40",X"00",X"40",X"40",X"00",X"00",X"00",X"40",X"40",X"40",X"40",X"00",X"00",X"40", + X"00",X"00",X"40",X"C1",X"01",X"00",X"C1",X"00",X"00",X"FD",X"01",X"00",X"FD",X"00",X"00",X"F9", + X"01",X"00",X"F9",X"00",X"00",X"F5",X"01",X"00",X"F5",X"00",X"00",X"F1",X"00",X"00",X"F1",X"01", + X"00",X"ED",X"00",X"00",X"ED",X"00",X"00",X"E9",X"00",X"00",X"E9",X"00",X"00",X"E5",X"00",X"00", + X"E5",X"00",X"00",X"E1",X"00",X"00",X"E1",X"00",X"00",X"DD",X"00",X"00",X"DD",X"00",X"00",X"D9", + X"00",X"00",X"D9",X"00",X"00",X"D5",X"00",X"00",X"D5",X"00",X"00",X"D1",X"00",X"00",X"D1",X"01", + X"00",X"CD",X"00",X"00",X"CD",X"00",X"00",X"C9",X"00",X"00",X"C9",X"00",X"00",X"C5",X"00",X"00", + X"C5",X"00",X"00",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"64",X"64",X"64",X"64",X"64", + X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"64",X"64",X"64",X"64",X"64",X"A3",X"A2",X"10", + X"10",X"10",X"10",X"10",X"10",X"93",X"92",X"64",X"64",X"64",X"FE",X"FE",X"A6",X"A3",X"A2",X"10", + X"10",X"10",X"71",X"71",X"8F",X"64",X"64",X"CB",X"CA",X"FD",X"FC",X"A9",X"A8",X"A3",X"A2",X"71", + X"71",X"71",X"8E",X"64",X"C9",X"C8",X"C7",X"C6",X"A5",X"A4",X"A1",X"A0",X"A5",X"71",X"71",X"8C", + X"64",X"FE",X"FE",X"A7",X"A1",X"A0",X"A4",X"10",X"10",X"71",X"71",X"8D",X"64",X"64",X"A1",X"A0", + X"A4",X"10",X"10",X"10",X"10",X"10",X"91",X"90",X"64",X"64",X"64",X"10",X"10",X"10",X"10",X"10", + X"10",X"10",X"10",X"64",X"64",X"64",X"64",X"64",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10", + X"64",X"64",X"64",X"64",X"64",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"C0",X"C0",X"C0", + X"C0",X"C0",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"C0",X"C0",X"C0",X"80",X"80",X"C0",X"C0", + X"C0",X"80",X"80",X"80",X"C0",X"C0",X"80",X"C0",X"C0",X"80",X"80",X"80",X"80",X"80",X"80",X"80", + X"80",X"C0",X"C0",X"C0",X"80",X"C0",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"C0",X"C0", + X"C0",X"80",X"C0",X"80",X"80",X"C0",X"C0",X"C0",X"C0",X"80",X"80",X"C0",X"C0",X"80",X"C0",X"C0", + X"C0",X"C0",X"C0",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"C0",X"C0",X"C0",X"80",X"80",X"80", + X"80",X"80",X"80",X"80",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"80",X"80",X"80",X"80",X"80",X"80", + X"80",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"71",X"71", + X"71",X"71",X"71",X"71",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"71",X"71",X"71",X"71",X"71", + X"71",X"A3",X"A2",X"10",X"10",X"10",X"10",X"10",X"71",X"71",X"71",X"71",X"71",X"71",X"FE",X"FE", + X"A6",X"A3",X"A2",X"10",X"10",X"71",X"71",X"71",X"71",X"71",X"71",X"CB",X"CA",X"FD",X"FC",X"A9", + X"A8",X"A3",X"AB",X"AA",X"71",X"71",X"71",X"71",X"C9",X"C8",X"C7",X"C6",X"A5",X"A4",X"A1",X"A9", + X"A8",X"71",X"71",X"71",X"71",X"FE",X"FE",X"A7",X"A1",X"A0",X"A4",X"10",X"71",X"71",X"71",X"71", + X"71",X"71",X"A1",X"A0",X"A4",X"10",X"10",X"10",X"10",X"71",X"71",X"71",X"71",X"71",X"71",X"10", + X"10",X"10",X"10",X"10",X"10",X"10",X"71",X"71",X"71",X"71",X"71",X"71",X"10",X"10",X"10",X"10", + X"10",X"10",X"10",X"71",X"71",X"71",X"71",X"71",X"71",X"80",X"80",X"80",X"80",X"80",X"80",X"80", + X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"C0",X"C0",X"80",X"80",X"80",X"80",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0", + X"80",X"80",X"C0",X"C0",X"C0",X"80",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"80",X"80",X"80", + X"80",X"80",X"80",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"80",X"80",X"80",X"80",X"80",X"80", + X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"80",X"80",X"C0",X"C0",X"C0",X"C0",X"80",X"C0",X"C0", + X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"80",X"80",X"80",X"80",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"80",X"80", + X"80",X"80",X"80",X"80",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"10",X"10",X"10",X"10",X"10", + X"71",X"71",X"71",X"71",X"71",X"71",X"71",X"71",X"10",X"10",X"10",X"10",X"10",X"71",X"71",X"71", + X"71",X"71",X"71",X"71",X"71",X"A3",X"A2",X"10",X"10",X"10",X"71",X"71",X"71",X"71",X"71",X"71", + X"71",X"71",X"FE",X"FE",X"A6",X"A3",X"A2",X"AB",X"AB",X"AF",X"71",X"71",X"71",X"71",X"71",X"CB", + X"CA",X"FD",X"FC",X"A9",X"10",X"10",X"10",X"AE",X"71",X"71",X"71",X"71",X"C9",X"C8",X"C7",X"C6", + X"A5",X"10",X"10",X"10",X"AC",X"71",X"71",X"71",X"71",X"FE",X"FE",X"A7",X"A1",X"A0",X"A9",X"A9", + X"AD",X"71",X"71",X"71",X"71",X"71",X"A1",X"A0",X"A4",X"10",X"10",X"71",X"71",X"71",X"71",X"71", + X"71",X"71",X"71",X"10",X"10",X"10",X"10",X"10",X"71",X"71",X"71",X"71",X"71",X"71",X"71",X"71", + X"10",X"10",X"10",X"10",X"10",X"71",X"71",X"71",X"71",X"71",X"71",X"71",X"71",X"80",X"80",X"80", + X"80",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"80",X"80",X"80",X"80",X"80",X"C0", + X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"80",X"80",X"80",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"C0",X"80",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"80",X"80",X"80",X"80",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"80",X"80", + X"80",X"80",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"80",X"80",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"80",X"80",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"C0",X"C0",X"80",X"80",X"80",X"80",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"80",X"80",X"80",X"80",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"10", + X"71",X"71",X"71",X"71",X"71",X"71",X"71",X"71",X"71",X"71",X"71",X"71",X"10",X"71",X"71",X"71", + X"71",X"71",X"71",X"71",X"71",X"71",X"71",X"71",X"71",X"A3",X"10",X"10",X"10",X"10",X"B7",X"B6", + X"71",X"71",X"71",X"71",X"71",X"71",X"FE",X"10",X"10",X"10",X"10",X"10",X"B3",X"71",X"71",X"71", + X"71",X"71",X"71",X"CB",X"10",X"10",X"10",X"10",X"10",X"B2",X"71",X"71",X"71",X"71",X"71",X"71", + X"C9",X"10",X"10",X"10",X"10",X"10",X"B0",X"71",X"71",X"71",X"71",X"71",X"71",X"FE",X"10",X"10", + X"10",X"10",X"10",X"B1",X"71",X"71",X"71",X"71",X"71",X"71",X"A1",X"10",X"10",X"10",X"10",X"B5", + X"B4",X"71",X"71",X"71",X"71",X"71",X"71",X"10",X"71",X"71",X"71",X"71",X"71",X"71",X"71",X"71", + X"71",X"71",X"71",X"71",X"10",X"71",X"71",X"71",X"71",X"71",X"71",X"71",X"71",X"71",X"71",X"71", + X"71",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"80",X"C0", + X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"C0",X"C0",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"80", + X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"B7",X"B6",X"71",X"71", + X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"BF",X"71",X"10",X"10",X"10", + X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"BE",X"10",X"10",X"10",X"10",X"10",X"10", + X"10",X"10",X"10",X"10",X"10",X"10",X"BB",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10", + X"10",X"10",X"10",X"BA",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10", + X"B8",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"B9",X"10",X"10", + X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"BC",X"10",X"10",X"10",X"10",X"10", + X"10",X"10",X"10",X"10",X"10",X"10",X"BD",X"71",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10", + X"10",X"B5",X"B4",X"71",X"71",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"FF",X"06",X"FF",X"0D",X"FF", + X"13",X"FF",X"19",X"FF",X"1F",X"FE",X"26",X"FD",X"2C",X"FC",X"32",X"FB",X"38",X"FA",X"3E",X"F8", + X"44",X"F7",X"4A",X"F5",X"50",X"F3",X"56",X"F1",X"5C",X"EF",X"62",X"ED",X"68",X"EA",X"6D",X"E7", + X"73",X"E5",X"79",X"E2",X"7E",X"DF",X"84",X"DC",X"89",X"D8",X"8E",X"D5",X"93",X"D1",X"99",X"CE", + X"9E",X"CA",X"A2",X"C6",X"A7",X"C2",X"AC",X"BE",X"B1",X"B9",X"B5",X"B5",X"B9",X"B1",X"BE",X"AC", + X"C2",X"A7",X"C6",X"A2",X"CA",X"9E",X"CE",X"99",X"D1",X"93",X"D5",X"8E",X"D8",X"89",X"DC",X"84", + X"DF",X"7E",X"E2",X"79",X"E5",X"73",X"E7",X"6D",X"EA",X"68",X"ED",X"62",X"EF",X"5C",X"F1",X"56", + X"F3",X"50",X"F5",X"4A",X"F7",X"44",X"F8",X"3E",X"FA",X"38",X"FB",X"32",X"FC",X"2C",X"FD",X"26", + X"FE",X"1F",X"FF",X"19",X"FF",X"13",X"FF",X"0D",X"FF",X"06",X"FF",X"00",X"FF",X"06",X"FF",X"0D", + X"FF",X"13",X"FF",X"19",X"FE",X"1F",X"FD",X"26",X"FC",X"2C",X"FB",X"32",X"FA",X"38",X"F8",X"3E", + X"F7",X"44",X"F5",X"4A",X"F3",X"50",X"F1",X"56",X"EF",X"5C",X"ED",X"62",X"EA",X"68",X"E7",X"6D", + X"E5",X"73",X"E2",X"79",X"DF",X"7E",X"DC",X"84",X"D8",X"89",X"D5",X"8E",X"D1",X"93",X"CE",X"99", + X"CA",X"9E",X"C6",X"A2",X"C2",X"A7",X"BE",X"AC",X"B9",X"B1",X"B5",X"B5",X"B1",X"B9",X"AC",X"BE", + X"A7",X"C2",X"A2",X"C6",X"9E",X"CA",X"99",X"CE",X"93",X"D1",X"8E",X"D5",X"89",X"D8",X"84",X"DC", + X"7E",X"DF",X"79",X"E2",X"73",X"E5",X"6D",X"E7",X"68",X"EA",X"62",X"ED",X"5C",X"EF",X"56",X"F1", + X"50",X"F3",X"4A",X"F5",X"44",X"F7",X"3E",X"F8",X"38",X"FA",X"32",X"FB",X"2C",X"FC",X"26",X"FD", + X"1F",X"FE",X"19",X"FF",X"13",X"FF",X"0D",X"FF",X"06",X"FF",X"00",X"FF",X"06",X"FF",X"0D",X"FF", + X"13",X"FF",X"19",X"FF",X"1F",X"FE",X"26",X"FD",X"2C",X"FC",X"32",X"FB",X"38",X"FA",X"3E",X"F8", + X"44",X"F7",X"4A",X"F5",X"50",X"F3",X"56",X"F1",X"5C",X"EF",X"62",X"ED",X"68",X"EA",X"6D",X"E7", + X"73",X"E5",X"79",X"E2",X"7E",X"DF",X"84",X"DC",X"89",X"D8",X"8E",X"D5",X"93",X"D1",X"99",X"CE", + X"9E",X"CA",X"A2",X"C6",X"A7",X"C2",X"AC",X"BE",X"B1",X"B9",X"B5",X"B5",X"B9",X"B1",X"BE",X"AC", + X"C2",X"A7",X"C6",X"A2",X"CA",X"9E",X"CE",X"99",X"D1",X"93",X"D5",X"8E",X"D8",X"89",X"DC",X"84", + X"DF",X"7E",X"E2",X"79",X"E5",X"73",X"E7",X"6D",X"EA",X"68",X"ED",X"62",X"EF",X"5C",X"F1",X"56", + X"F3",X"50",X"F5",X"4A",X"F7",X"44",X"F8",X"3E",X"FA",X"38",X"FB",X"32",X"FC",X"2C",X"FD",X"26", + X"FE",X"1F",X"FF",X"19",X"FF",X"13",X"FF",X"0D",X"FF",X"06",X"FF",X"00",X"FF",X"06",X"FF",X"0D", + X"FF",X"13",X"FF",X"19",X"FE",X"1F",X"FD",X"26",X"FC",X"2C",X"FB",X"32",X"FA",X"38",X"F8",X"3E", + X"F7",X"44",X"F5",X"4A",X"F3",X"50",X"F1",X"56",X"EF",X"5C",X"ED",X"62",X"EA",X"68",X"E7",X"6D", + X"E5",X"73",X"E2",X"79",X"DF",X"7E",X"DC",X"84",X"D8",X"89",X"D5",X"8E",X"D1",X"93",X"CE",X"99", + X"CA",X"9E",X"C6",X"A2",X"C2",X"A7",X"BE",X"AC",X"B9",X"B1",X"B5",X"B5",X"B1",X"B9",X"AC",X"BE", + X"A7",X"C2",X"A2",X"C6",X"9E",X"CA",X"99",X"CE",X"93",X"D1",X"8E",X"D5",X"89",X"D8",X"84",X"DC", + X"7E",X"DF",X"79",X"E2",X"73",X"E5",X"6D",X"E7",X"68",X"EA",X"62",X"ED",X"5C",X"EF",X"56",X"F1", + X"50",X"F3",X"4A",X"F5",X"44",X"F7",X"3E",X"F8",X"38",X"FA",X"32",X"FB",X"2C",X"FC",X"26",X"FD", + X"1F",X"FE",X"19",X"FF",X"13",X"FF",X"0D",X"FF",X"06",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/loc_snd_rom.vhd b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/loc_snd_rom.vhd new file mode 100644 index 00000000..af226908 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/loc_snd_rom.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity loc_snd_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of loc_snd_rom is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"21",X"00",X"20",X"06",X"00",X"C3",X"6A",X"01",X"32",X"00",X"50",X"3A",X"00",X"40",X"C9",X"FF", + X"32",X"00",X"70",X"3A",X"00",X"60",X"C9",X"FF",X"78",X"CF",X"79",X"32",X"00",X"40",X"C9",X"FF", + X"78",X"D7",X"79",X"32",X"00",X"60",X"C9",X"FF",X"87",X"85",X"6F",X"7C",X"CE",X"00",X"67",X"7E", + X"23",X"66",X"6F",X"E9",X"FF",X"FF",X"FF",X"FF",X"D9",X"08",X"CD",X"40",X"00",X"08",X"D9",X"C9", + X"3E",X"0E",X"CF",X"B7",X"28",X"0D",X"57",X"CB",X"BF",X"FE",X"2D",X"D0",X"CB",X"7A",X"28",X"29", + X"C3",X"70",X"00",X"21",X"00",X"20",X"06",X"0C",X"AF",X"77",X"23",X"10",X"FC",X"C9",X"21",X"00", + X"20",X"06",X"06",X"0E",X"07",X"BE",X"28",X"05",X"23",X"23",X"10",X"F9",X"41",X"79",X"90",X"C9", + X"CD",X"5E",X"00",X"C8",X"AF",X"77",X"23",X"77",X"C9",X"32",X"17",X"20",X"CD",X"5E",X"00",X"28", + X"04",X"23",X"36",X"00",X"C9",X"AF",X"CD",X"5E",X"00",X"28",X"08",X"3A",X"17",X"20",X"77",X"23", + X"36",X"00",X"C9",X"CD",X"EF",X"00",X"CD",X"1A",X"01",X"B7",X"28",X"2D",X"3A",X"15",X"20",X"B7", + X"28",X"1F",X"3A",X"16",X"20",X"21",X"06",X"20",X"CD",X"DE",X"00",X"CD",X"E6",X"00",X"57",X"3A", + X"15",X"20",X"21",X"00",X"20",X"CD",X"DE",X"00",X"CD",X"E6",X"00",X"BA",X"F2",X"C1",X"00",X"18", + X"08",X"3A",X"16",X"20",X"21",X"06",X"20",X"18",X"06",X"3A",X"15",X"20",X"21",X"00",X"20",X"B7", + X"C8",X"3D",X"87",X"4F",X"06",X"00",X"09",X"3A",X"17",X"20",X"77",X"23",X"70",X"C9",X"3D",X"87", + X"4F",X"06",X"00",X"09",X"7E",X"C9",X"21",X"F6",X"0C",X"06",X"00",X"4F",X"09",X"7E",X"C9",X"3A", + X"00",X"20",X"CD",X"E6",X"00",X"32",X"11",X"20",X"3A",X"02",X"20",X"CD",X"E6",X"00",X"32",X"12", + X"20",X"3A",X"04",X"20",X"CD",X"E6",X"00",X"32",X"13",X"20",X"3A",X"17",X"20",X"CD",X"E6",X"00", + X"32",X"14",X"20",X"CD",X"45",X"01",X"32",X"15",X"20",X"C9",X"3A",X"06",X"20",X"CD",X"E6",X"00", + X"32",X"11",X"20",X"3A",X"08",X"20",X"CD",X"E6",X"00",X"32",X"12",X"20",X"3A",X"0A",X"20",X"CD", + X"E6",X"00",X"32",X"13",X"20",X"3A",X"17",X"20",X"CD",X"E6",X"00",X"32",X"14",X"20",X"CD",X"45", + X"01",X"32",X"16",X"20",X"C9",X"21",X"11",X"20",X"3A",X"14",X"20",X"06",X"03",X"4F",X"7E",X"B9", + X"F2",X"54",X"01",X"4F",X"23",X"10",X"F7",X"79",X"06",X"03",X"0E",X"01",X"21",X"11",X"20",X"BE", + X"28",X"06",X"0C",X"23",X"10",X"F9",X"0E",X"00",X"79",X"C9",X"70",X"23",X"7C",X"FE",X"24",X"20", + X"F9",X"F9",X"ED",X"56",X"21",X"00",X"30",X"22",X"0C",X"20",X"77",X"01",X"3F",X"07",X"DF",X"E7", + X"32",X"0E",X"20",X"32",X"0F",X"20",X"CD",X"7C",X"02",X"CD",X"80",X"02",X"CD",X"84",X"02",X"CD", + X"8A",X"02",X"CD",X"8E",X"02",X"CD",X"92",X"02",X"FB",X"3E",X"0F",X"CF",X"E6",X"40",X"20",X"F9", + X"3E",X"0F",X"CF",X"E6",X"40",X"28",X"F9",X"F3",X"3E",X"01",X"32",X"10",X"20",X"3A",X"01",X"20", + X"B7",X"3A",X"00",X"20",X"CA",X"BC",X"01",X"CD",X"64",X"02",X"18",X"03",X"CD",X"4A",X"02",X"FB", + X"00",X"00",X"F3",X"3E",X"02",X"32",X"10",X"20",X"3A",X"03",X"20",X"B7",X"3A",X"02",X"20",X"CA", + X"D7",X"01",X"CD",X"64",X"02",X"18",X"03",X"CD",X"4A",X"02",X"FB",X"00",X"00",X"F3",X"3E",X"03", + X"32",X"10",X"20",X"3A",X"05",X"20",X"B7",X"3A",X"04",X"20",X"CA",X"F2",X"01",X"CD",X"64",X"02", + X"18",X"03",X"CD",X"4A",X"02",X"FB",X"00",X"00",X"F3",X"3E",X"04",X"32",X"10",X"20",X"3A",X"07", + X"20",X"B7",X"3A",X"06",X"20",X"CA",X"0D",X"02",X"CD",X"64",X"02",X"18",X"03",X"CD",X"4A",X"02", + X"FB",X"00",X"00",X"F3",X"3E",X"05",X"32",X"10",X"20",X"3A",X"09",X"20",X"B7",X"3A",X"08",X"20", + X"CA",X"28",X"02",X"CD",X"64",X"02",X"18",X"03",X"CD",X"4A",X"02",X"FB",X"00",X"00",X"F3",X"3E", + X"06",X"32",X"10",X"20",X"3A",X"0B",X"20",X"B7",X"3A",X"0A",X"20",X"CA",X"44",X"02",X"CD",X"64", + X"02",X"C3",X"98",X"01",X"CD",X"4A",X"02",X"C3",X"98",X"01",X"21",X"23",X"0D",X"EF",X"B7",X"20", + X"1B",X"E5",X"21",X"01",X"20",X"3A",X"10",X"20",X"3D",X"87",X"D5",X"5F",X"16",X"00",X"19",X"D1", + X"36",X"01",X"E1",X"C9",X"B7",X"C8",X"21",X"7D",X"0D",X"EF",X"B7",X"C8",X"21",X"00",X"20",X"3A", + X"10",X"20",X"3D",X"4F",X"06",X"00",X"09",X"09",X"70",X"23",X"70",X"C9",X"06",X"08",X"18",X"06", + X"06",X"09",X"18",X"02",X"06",X"0A",X"0E",X"00",X"DF",X"C9",X"06",X"08",X"18",X"06",X"06",X"09", + X"18",X"02",X"06",X"0A",X"0E",X"00",X"E7",X"C9",X"3A",X"10",X"20",X"3D",X"21",X"A2",X"02",X"EF", + X"AF",X"C9",X"AE",X"02",X"B7",X"02",X"C0",X"02",X"C9",X"02",X"D2",X"02",X"DB",X"02",X"CD",X"7C", + X"02",X"0E",X"09",X"CD",X"E4",X"02",X"C9",X"CD",X"80",X"02",X"0E",X"12",X"CD",X"E4",X"02",X"C9", + X"CD",X"84",X"02",X"0E",X"24",X"CD",X"E4",X"02",X"C9",X"CD",X"8A",X"02",X"0E",X"09",X"CD",X"F0", + X"02",X"C9",X"CD",X"8E",X"02",X"0E",X"12",X"CD",X"F0",X"02",X"C9",X"CD",X"92",X"02",X"0E",X"24", + X"CD",X"F0",X"02",X"C9",X"3A",X"0E",X"20",X"B1",X"32",X"0E",X"20",X"06",X"07",X"4F",X"DF",X"C9", + X"3A",X"0F",X"20",X"B1",X"32",X"0F",X"20",X"06",X"07",X"4F",X"E7",X"C9",X"06",X"06",X"3A",X"10", + X"20",X"FE",X"04",X"FA",X"08",X"03",X"E7",X"C9",X"DF",X"C9",X"3A",X"0E",X"20",X"A0",X"B1",X"32", + X"0E",X"20",X"4F",X"06",X"07",X"DF",X"C9",X"3A",X"0F",X"20",X"A0",X"B1",X"32",X"0F",X"20",X"4F", + X"06",X"07",X"E7",X"C9",X"3A",X"10",X"20",X"3D",X"21",X"2D",X"03",X"EF",X"C9",X"39",X"03",X"40", + X"03",X"47",X"03",X"4E",X"03",X"55",X"03",X"5C",X"03",X"01",X"08",X"FE",X"CD",X"0A",X"03",X"C9", + X"01",X"10",X"FD",X"CD",X"0A",X"03",X"C9",X"01",X"20",X"FB",X"CD",X"0A",X"03",X"C9",X"01",X"08", + X"FE",X"CD",X"17",X"03",X"C9",X"01",X"10",X"FD",X"CD",X"17",X"03",X"C9",X"01",X"20",X"FB",X"CD", + X"17",X"03",X"C9",X"3A",X"10",X"20",X"3D",X"21",X"6C",X"03",X"EF",X"C9",X"78",X"03",X"7F",X"03", + X"86",X"03",X"8D",X"03",X"94",X"03",X"9B",X"03",X"01",X"01",X"F7",X"CD",X"0A",X"03",X"C9",X"01", + X"02",X"EF",X"CD",X"0A",X"03",X"C9",X"01",X"04",X"DF",X"CD",X"0A",X"03",X"C9",X"01",X"01",X"F7", + X"CD",X"17",X"03",X"C9",X"01",X"02",X"EF",X"CD",X"17",X"03",X"C9",X"01",X"04",X"DF",X"CD",X"17", + X"03",X"C9",X"3A",X"10",X"20",X"3D",X"21",X"AB",X"03",X"EF",X"C9",X"B7",X"03",X"BE",X"03",X"C5", + X"03",X"CC",X"03",X"D3",X"03",X"DA",X"03",X"01",X"00",X"F6",X"CD",X"0A",X"03",X"C9",X"01",X"00", + X"ED",X"CD",X"0A",X"03",X"C9",X"01",X"00",X"DB",X"CD",X"0A",X"03",X"C9",X"01",X"00",X"F6",X"CD", + X"17",X"03",X"C9",X"01",X"00",X"ED",X"CD",X"17",X"03",X"C9",X"01",X"00",X"DB",X"CD",X"17",X"03", + X"C9",X"3A",X"10",X"20",X"FE",X"04",X"30",X"05",X"C6",X"07",X"47",X"DF",X"C9",X"C6",X"04",X"47", + X"E7",X"C9",X"3A",X"10",X"20",X"FE",X"04",X"30",X"09",X"3D",X"87",X"47",X"4D",X"DF",X"4C",X"04", + X"DF",X"C9",X"D6",X"04",X"87",X"47",X"4D",X"E7",X"4C",X"04",X"E7",X"C9",X"FE",X"04",X"D0",X"F5", + X"CD",X"5C",X"04",X"F1",X"B7",X"20",X"02",X"77",X"C9",X"21",X"2C",X"04",X"87",X"87",X"4F",X"87", + X"81",X"4F",X"06",X"00",X"09",X"3A",X"10",X"20",X"3D",X"EF",X"77",X"C9",X"7F",X"04",X"84",X"04", + X"89",X"04",X"8E",X"04",X"93",X"04",X"98",X"04",X"9D",X"04",X"A2",X"04",X"A7",X"04",X"AC",X"04", + X"B1",X"04",X"B6",X"04",X"BB",X"04",X"C0",X"04",X"C5",X"04",X"CA",X"04",X"CF",X"04",X"D4",X"04", + X"D9",X"04",X"DE",X"04",X"E3",X"04",X"E8",X"04",X"ED",X"04",X"F2",X"04",X"21",X"2C",X"04",X"3A", + X"10",X"20",X"3D",X"EF",X"C9",X"2A",X"0C",X"20",X"7B",X"A5",X"6F",X"7A",X"A4",X"67",X"22",X"0C", + X"20",X"C9",X"2A",X"0C",X"20",X"7B",X"B5",X"6F",X"7A",X"B4",X"67",X"22",X"0C",X"20",X"C9",X"11", + X"3F",X"FF",X"18",X"E1",X"11",X"FF",X"FC",X"18",X"DC",X"11",X"FF",X"F3",X"18",X"D7",X"11",X"FC", + X"FF",X"18",X"D2",X"11",X"F3",X"FF",X"18",X"CD",X"11",X"CF",X"FF",X"18",X"C8",X"11",X"80",X"00", + X"18",X"D0",X"11",X"00",X"02",X"18",X"CB",X"11",X"00",X"08",X"18",X"C6",X"11",X"02",X"00",X"18", + X"C1",X"11",X"08",X"00",X"18",X"BC",X"11",X"20",X"00",X"18",X"B7",X"11",X"40",X"00",X"18",X"B2", + X"11",X"00",X"01",X"18",X"AD",X"11",X"00",X"04",X"18",X"A8",X"11",X"01",X"00",X"18",X"A3",X"11", + X"04",X"00",X"18",X"9E",X"11",X"10",X"00",X"18",X"99",X"11",X"C0",X"00",X"18",X"94",X"11",X"00", + X"03",X"18",X"8F",X"11",X"00",X"0C",X"18",X"8A",X"11",X"03",X"00",X"18",X"85",X"11",X"0C",X"00", + X"18",X"80",X"11",X"30",X"00",X"C3",X"72",X"04",X"DD",X"7E",X"00",X"32",X"37",X"20",X"FE",X"FF", + X"C8",X"CD",X"06",X"05",X"AF",X"C9",X"DD",X"35",X"01",X"C0",X"3A",X"32",X"20",X"DD",X"77",X"01", + X"DD",X"CB",X"00",X"46",X"C2",X"29",X"05",X"DD",X"7E",X"07",X"D6",X"01",X"FA",X"29",X"05",X"DD", + X"77",X"07",X"32",X"34",X"20",X"4F",X"CD",X"E1",X"03",X"DD",X"35",X"00",X"C0",X"DD",X"6E",X"02", + X"DD",X"66",X"03",X"7E",X"47",X"E6",X"1F",X"CA",X"C1",X"05",X"FE",X"1F",X"C2",X"D8",X"05",X"23", + X"DD",X"75",X"02",X"DD",X"74",X"03",X"78",X"E6",X"E0",X"0F",X"0F",X"0F",X"0F",X"4F",X"06",X"00", + X"21",X"59",X"05",X"09",X"5E",X"23",X"56",X"EB",X"E9",X"69",X"05",X"87",X"05",X"9D",X"05",X"B7", + X"05",X"B7",X"05",X"B7",X"05",X"B7",X"05",X"B7",X"05",X"DD",X"6E",X"02",X"DD",X"66",X"03",X"4E", + X"CB",X"21",X"06",X"00",X"21",X"11",X"06",X"09",X"5E",X"23",X"56",X"ED",X"53",X"30",X"20",X"DD", + X"73",X"04",X"DD",X"72",X"05",X"18",X"20",X"DD",X"6E",X"02",X"DD",X"66",X"03",X"4E",X"06",X"00", + X"21",X"A9",X"06",X"09",X"7E",X"32",X"32",X"20",X"DD",X"77",X"01",X"18",X"0A",X"DD",X"6E",X"02", + X"DD",X"66",X"03",X"7E",X"DD",X"77",X"06",X"DD",X"6E",X"02",X"DD",X"66",X"03",X"23",X"DD",X"75", + X"02",X"DD",X"74",X"03",X"C3",X"2D",X"05",X"0E",X"00",X"CD",X"E1",X"03",X"DD",X"36",X"00",X"FF", + X"C9",X"CD",X"C6",X"05",X"18",X"3D",X"78",X"E6",X"E0",X"07",X"07",X"07",X"47",X"3E",X"01",X"18", + X"01",X"07",X"10",X"FD",X"DD",X"77",X"00",X"C9",X"C5",X"CD",X"C6",X"05",X"C1",X"78",X"E6",X"1F", + X"3D",X"07",X"4F",X"06",X"00",X"DD",X"6E",X"04",X"DD",X"66",X"05",X"09",X"5E",X"23",X"56",X"EB", + X"22",X"35",X"20",X"CD",X"F2",X"03",X"DD",X"4E",X"06",X"79",X"DD",X"77",X"07",X"32",X"34",X"20", + X"CD",X"E1",X"03",X"DD",X"6E",X"02",X"DD",X"66",X"03",X"23",X"DD",X"75",X"02",X"DD",X"74",X"03", + X"C9",X"31",X"06",X"35",X"06",X"39",X"06",X"3D",X"06",X"41",X"06",X"45",X"06",X"49",X"06",X"4D", + X"06",X"51",X"06",X"55",X"06",X"59",X"06",X"5D",X"06",X"61",X"06",X"65",X"06",X"69",X"06",X"6D", + X"06",X"6B",X"08",X"F2",X"07",X"80",X"07",X"14",X"07",X"AE",X"06",X"4E",X"06",X"F3",X"05",X"9E", + X"05",X"4E",X"05",X"01",X"05",X"B9",X"04",X"76",X"04",X"36",X"04",X"F9",X"03",X"C0",X"03",X"8A", + X"03",X"57",X"03",X"27",X"03",X"FA",X"02",X"CF",X"02",X"A7",X"02",X"81",X"02",X"5D",X"02",X"3B", + X"02",X"1B",X"02",X"FD",X"01",X"E0",X"01",X"C5",X"01",X"AC",X"01",X"94",X"01",X"7D",X"01",X"68", + X"01",X"53",X"01",X"40",X"01",X"2E",X"01",X"1D",X"01",X"0D",X"01",X"FE",X"00",X"F0",X"00",X"E3", + X"00",X"D6",X"00",X"CA",X"00",X"BE",X"00",X"B4",X"00",X"AA",X"00",X"A0",X"00",X"97",X"00",X"8F", + X"00",X"87",X"00",X"7F",X"00",X"78",X"00",X"71",X"00",X"6B",X"00",X"65",X"00",X"5F",X"00",X"5A", + X"00",X"55",X"00",X"50",X"00",X"4C",X"00",X"47",X"00",X"46",X"3F",X"38",X"31",X"2B",X"26",X"21", + X"1C",X"18",X"15",X"12",X"0F",X"0D",X"0C",X"0B",X"0A",X"AF",X"32",X"37",X"20",X"21",X"EF",X"06", + X"11",X"18",X"20",X"01",X"18",X"00",X"ED",X"B0",X"3A",X"33",X"20",X"07",X"4F",X"07",X"81",X"4F", + X"06",X"00",X"21",X"07",X"0E",X"09",X"11",X"1A",X"20",X"CD",X"E5",X"06",X"11",X"22",X"20",X"CD", + X"E5",X"06",X"11",X"2A",X"20",X"7E",X"12",X"CD",X"EC",X"06",X"7E",X"12",X"23",X"13",X"C9",X"01", + X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"01", + X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"3E",X"1E",X"C3",X"4F",X"07",X"3E",X"1D",X"C3",X"4F", + X"07",X"3E",X"1C",X"C3",X"4F",X"07",X"3E",X"1B",X"C3",X"4F",X"07",X"3E",X"1A",X"C3",X"4F",X"07", + X"3E",X"19",X"C3",X"4F",X"07",X"3E",X"18",X"C3",X"4F",X"07",X"3E",X"17",X"C3",X"4F",X"07",X"3E", + X"16",X"C3",X"4F",X"07",X"3E",X"15",X"C3",X"4F",X"07",X"3E",X"14",X"C3",X"4F",X"07",X"3E",X"13", + X"C3",X"4F",X"07",X"3E",X"12",X"C3",X"4F",X"07",X"3E",X"11",X"C3",X"4F",X"07",X"3E",X"10",X"32", + X"49",X"20",X"3E",X"FF",X"C9",X"3E",X"01",X"CD",X"0C",X"04",X"CD",X"24",X"03",X"21",X"00",X"05", + X"22",X"3B",X"20",X"CD",X"F2",X"03",X"3E",X"0A",X"32",X"3A",X"20",X"4F",X"CD",X"E1",X"03",X"3E", + X"40",X"32",X"38",X"20",X"3E",X"F0",X"32",X"39",X"20",X"AF",X"32",X"3D",X"20",X"C9",X"21",X"3D", + X"20",X"35",X"7E",X"E6",X"01",X"20",X"36",X"21",X"38",X"20",X"35",X"7E",X"57",X"20",X"0A",X"36", + X"40",X"21",X"3A",X"20",X"35",X"4E",X"CD",X"E1",X"03",X"2A",X"3B",X"20",X"CB",X"62",X"3A",X"39", + X"20",X"06",X"FF",X"20",X"05",X"04",X"ED",X"44",X"CB",X"3F",X"4F",X"09",X"22",X"3B",X"20",X"CD", + X"F2",X"03",X"7A",X"E6",X"1F",X"20",X"06",X"21",X"39",X"20",X"34",X"28",X"02",X"AF",X"C9",X"3D", + X"C9",X"3E",X"01",X"CD",X"0C",X"04",X"CD",X"24",X"03",X"21",X"60",X"00",X"22",X"40",X"20",X"CD", + X"F2",X"03",X"3E",X"0C",X"32",X"3F",X"20",X"4F",X"CD",X"E1",X"03",X"3E",X"20",X"32",X"3E",X"20", + X"AF",X"C9",X"3A",X"3D",X"20",X"E6",X"01",X"C8",X"21",X"3E",X"20",X"35",X"28",X"17",X"7E",X"2A", + X"40",X"20",X"FE",X"18",X"01",X"E8",X"FF",X"38",X"03",X"01",X"08",X"00",X"09",X"22",X"40",X"20", + X"CD",X"F2",X"03",X"AF",X"C9",X"36",X"20",X"21",X"60",X"00",X"22",X"40",X"20",X"CD",X"F2",X"03", + X"21",X"3F",X"20",X"35",X"28",X"06",X"4E",X"CD",X"E1",X"03",X"AF",X"C9",X"3D",X"C9",X"3E",X"01", + X"CD",X"0C",X"04",X"CD",X"24",X"03",X"21",X"00",X"01",X"22",X"45",X"20",X"CD",X"F2",X"03",X"0E", + X"0C",X"CD",X"E1",X"03",X"AF",X"32",X"42",X"20",X"32",X"43",X"20",X"C9",X"3A",X"3D",X"20",X"E6", + X"01",X"C8",X"21",X"43",X"20",X"35",X"7E",X"28",X"21",X"57",X"FE",X"DC",X"28",X"2A",X"38",X"30", + X"FE",X"E8",X"28",X"18",X"2A",X"45",X"20",X"3A",X"42",X"20",X"C6",X"9D",X"32",X"42",X"20",X"AA", + X"AD",X"6F",X"22",X"45",X"20",X"CD",X"F2",X"03",X"AF",X"C9",X"3D",X"C9",X"3E",X"0F",X"32",X"44", + X"20",X"4F",X"CD",X"E1",X"03",X"C3",X"54",X"08",X"3E",X"02",X"CD",X"0C",X"04",X"C3",X"54",X"08", + X"E6",X"0F",X"20",X"D0",X"23",X"35",X"4E",X"CD",X"E1",X"03",X"C3",X"54",X"08",X"3E",X"02",X"CD", + X"0C",X"04",X"CD",X"63",X"03",X"3E",X"01",X"32",X"47",X"20",X"3E",X"0B",X"32",X"4A",X"20",X"4F", + X"CD",X"E1",X"03",X"AF",X"32",X"48",X"20",X"32",X"4B",X"20",X"C9",X"21",X"4B",X"20",X"35",X"7E", + X"E6",X"01",X"C8",X"21",X"47",X"20",X"35",X"20",X"2D",X"3A",X"49",X"20",X"CB",X"3F",X"CB",X"3F", + X"77",X"21",X"48",X"20",X"35",X"7E",X"E6",X"1F",X"16",X"0B",X"28",X"12",X"16",X"F2",X"FE",X"18", + X"28",X"0C",X"3A",X"4A",X"20",X"57",X"CB",X"56",X"3E",X"FF",X"28",X"02",X"ED",X"44",X"82",X"32", + X"4A",X"20",X"4F",X"CD",X"E1",X"03",X"3A",X"49",X"20",X"4F",X"CD",X"FC",X"02",X"AF",X"C9",X"3E", + X"01",X"CD",X"0C",X"04",X"CD",X"24",X"03",X"0E",X"0A",X"CD",X"E1",X"03",X"21",X"00",X"00",X"CD", + X"F2",X"03",X"3E",X"0F",X"32",X"4C",X"20",X"32",X"4D",X"20",X"AF",X"C9",X"21",X"4C",X"20",X"35", + X"7E",X"E6",X"0F",X"21",X"4D",X"20",X"20",X"03",X"35",X"28",X"E1",X"BE",X"21",X"F0",X"00",X"38", + X"02",X"2E",X"00",X"CD",X"F2",X"03",X"AF",X"C9",X"3E",X"03",X"CD",X"0C",X"04",X"CD",X"24",X"03", + X"0E",X"0B",X"CD",X"E1",X"03",X"21",X"FF",X"02",X"7D",X"32",X"4E",X"20",X"32",X"4F",X"20",X"CD", + X"F2",X"03",X"3E",X"08",X"32",X"50",X"20",X"AF",X"32",X"51",X"20",X"C9",X"21",X"51",X"20",X"35", + X"7E",X"E6",X"03",X"20",X"19",X"21",X"50",X"20",X"3A",X"4F",X"20",X"57",X"B7",X"3A",X"4E",X"20", + X"28",X"0E",X"96",X"38",X"0F",X"32",X"4E",X"20",X"6F",X"26",X"02",X"CD",X"F2",X"03",X"AF",X"C9", + X"86",X"C3",X"63",X"09",X"7A",X"2F",X"32",X"4F",X"20",X"7E",X"3C",X"FE",X"3E",X"30",X"EF",X"77", + X"AF",X"C9",X"3E",X"01",X"CD",X"0C",X"04",X"CD",X"24",X"03",X"0E",X"00",X"CD",X"E1",X"03",X"3E", + X"03",X"21",X"56",X"20",X"77",X"2C",X"77",X"21",X"A0",X"00",X"22",X"54",X"20",X"3E",X"0A",X"32", + X"53",X"20",X"3E",X"58",X"32",X"52",X"20",X"AF",X"C9",X"21",X"56",X"20",X"35",X"7E",X"2C",X"A6", + X"20",X"28",X"21",X"52",X"20",X"35",X"28",X"DF",X"7E",X"57",X"E6",X"0F",X"20",X"09",X"21",X"53", + X"20",X"35",X"35",X"4E",X"CD",X"E1",X"03",X"2A",X"54",X"20",X"CB",X"42",X"3E",X"0C",X"28",X"02", + X"ED",X"44",X"85",X"6F",X"22",X"54",X"20",X"CD",X"F2",X"03",X"AF",X"C9",X"3E",X"01",X"32",X"57", + X"20",X"3E",X"FF",X"C9",X"3E",X"01",X"CD",X"0C",X"04",X"CD",X"24",X"03",X"21",X"00",X"00",X"22", + X"5C",X"20",X"CD",X"F2",X"03",X"3E",X"0F",X"32",X"5A",X"20",X"4F",X"CD",X"E1",X"03",X"3E",X"02", + X"32",X"59",X"20",X"AF",X"32",X"58",X"20",X"32",X"5B",X"20",X"32",X"5E",X"20",X"C9",X"21",X"5E", + X"20",X"35",X"7E",X"E6",X"01",X"C8",X"21",X"58",X"20",X"35",X"7E",X"57",X"20",X"04",X"2C",X"35", + X"28",X"28",X"E6",X"1F",X"20",X"08",X"21",X"5A",X"20",X"35",X"4E",X"CD",X"E1",X"03",X"2A",X"5C", + X"20",X"3A",X"5B",X"20",X"C6",X"C5",X"32",X"5B",X"20",X"AA",X"AD",X"6F",X"67",X"1F",X"38",X"02", + X"26",X"01",X"22",X"5C",X"20",X"CD",X"F2",X"03",X"AF",X"C9",X"3D",X"C9",X"AF",X"CD",X"0C",X"04", + X"CD",X"24",X"03",X"21",X"20",X"00",X"22",X"61",X"20",X"CD",X"F2",X"03",X"0E",X"09",X"CD",X"E1", + X"03",X"3E",X"20",X"32",X"5F",X"20",X"3E",X"1E",X"32",X"60",X"20",X"AF",X"C9",X"3A",X"5E",X"20", + X"E6",X"01",X"20",X"1C",X"21",X"5F",X"20",X"35",X"7E",X"28",X"17",X"2C",X"BE",X"38",X"11",X"0E", + X"00",X"28",X"18",X"2A",X"61",X"20",X"01",X"0C",X"00",X"09",X"22",X"61",X"20",X"CD",X"F2",X"03", + X"AF",X"C9",X"36",X"20",X"2C",X"35",X"35",X"28",X"07",X"0E",X"09",X"CD",X"E1",X"03",X"AF",X"C9", + X"3D",X"C9",X"3E",X"01",X"CD",X"0C",X"04",X"CD",X"24",X"03",X"21",X"20",X"00",X"CD",X"F2",X"03", + X"3E",X"08",X"32",X"64",X"20",X"4F",X"CD",X"E1",X"03",X"3E",X"01",X"32",X"65",X"20",X"AF",X"32", + X"63",X"20",X"C9",X"21",X"63",X"20",X"35",X"7E",X"E6",X"3F",X"4F",X"28",X"19",X"FE",X"0C",X"20", + X"18",X"21",X"65",X"20",X"3A",X"64",X"20",X"86",X"28",X"11",X"32",X"64",X"20",X"FE",X"0F",X"4F", + X"20",X"04",X"7E",X"ED",X"44",X"77",X"CD",X"E1",X"03",X"AF",X"C9",X"3D",X"C9",X"3E",X"01",X"CD", + X"0C",X"04",X"CD",X"24",X"03",X"21",X"00",X"01",X"CD",X"F2",X"03",X"3E",X"E0",X"32",X"67",X"20", + X"32",X"69",X"20",X"32",X"66",X"20",X"3E",X"0C",X"32",X"68",X"20",X"4F",X"CD",X"E1",X"03",X"AF", + X"C9",X"21",X"69",X"20",X"35",X"7E",X"E6",X"01",X"C8",X"21",X"67",X"20",X"35",X"7E",X"28",X"2B", + X"57",X"E6",X"07",X"20",X"13",X"7A",X"FE",X"60",X"28",X"DC",X"FE",X"80",X"28",X"D8",X"FE",X"C0", + X"28",X"D4",X"2C",X"35",X"4E",X"CD",X"E1",X"03",X"3A",X"66",X"20",X"C6",X"9B",X"32",X"66",X"20", + X"AA",X"6F",X"17",X"9F",X"3C",X"67",X"CD",X"F2",X"03",X"AF",X"C9",X"3D",X"C9",X"3E",X"01",X"CD", + X"0C",X"04",X"CD",X"24",X"03",X"21",X"50",X"01",X"CD",X"F2",X"03",X"3E",X"07",X"32",X"6C",X"20", + X"4F",X"CD",X"E1",X"03",X"3E",X"80",X"32",X"6A",X"20",X"AF",X"32",X"6B",X"20",X"32",X"6D",X"20", + X"C9",X"21",X"6D",X"20",X"35",X"7E",X"E6",X"01",X"C8",X"21",X"6B",X"20",X"35",X"7E",X"28",X"2F", + X"FE",X"C0",X"38",X"17",X"E6",X"07",X"20",X"13",X"3A",X"6A",X"20",X"D6",X"0A",X"32",X"6A",X"20", + X"3A",X"6C",X"20",X"3C",X"32",X"6C",X"20",X"4F",X"CD",X"E1",X"03",X"7E",X"E6",X"03",X"07",X"07", + X"07",X"07",X"57",X"3A",X"6A",X"20",X"92",X"6F",X"26",X"01",X"CD",X"F2",X"03",X"AF",X"C9",X"3D", + X"C9",X"3E",X"01",X"CD",X"0C",X"04",X"CD",X"24",X"03",X"21",X"38",X"01",X"CD",X"F2",X"03",X"3E", + X"04",X"32",X"70",X"20",X"4F",X"CD",X"E1",X"03",X"3E",X"68",X"32",X"6E",X"20",X"AF",X"32",X"6F", + X"20",X"32",X"71",X"20",X"C9",X"21",X"71",X"20",X"35",X"7E",X"E6",X"01",X"C8",X"21",X"6F",X"20", + X"35",X"7E",X"28",X"2F",X"FE",X"C0",X"38",X"17",X"E6",X"07",X"20",X"13",X"3A",X"6E",X"20",X"D6", + X"0A",X"32",X"6E",X"20",X"3A",X"70",X"20",X"3C",X"32",X"70",X"20",X"4F",X"CD",X"E1",X"03",X"7E", + X"E6",X"03",X"07",X"07",X"07",X"07",X"57",X"3A",X"6E",X"20",X"92",X"6F",X"26",X"01",X"CD",X"F2", + X"03",X"AF",X"C9",X"3D",X"C9",X"3E",X"00",X"CD",X"0C",X"04",X"CD",X"24",X"03",X"21",X"00",X"00", + X"22",X"75",X"20",X"CD",X"F2",X"03",X"AF",X"32",X"74",X"20",X"4F",X"CD",X"E1",X"03",X"AF",X"32", + X"72",X"20",X"32",X"73",X"20",X"32",X"77",X"20",X"C9",X"21",X"77",X"20",X"35",X"7E",X"E6",X"01", + X"C8",X"21",X"73",X"20",X"35",X"7E",X"28",X"29",X"57",X"FE",X"D0",X"28",X"3A",X"38",X"51",X"FE", + X"E0",X"28",X"20",X"38",X"25",X"2C",X"34",X"4E",X"CD",X"E1",X"03",X"2A",X"75",X"20",X"3A",X"72", + X"20",X"C6",X"9D",X"32",X"72",X"20",X"AA",X"AD",X"6F",X"22",X"75",X"20",X"CD",X"F2",X"03",X"AF", + X"C9",X"3D",X"C9",X"21",X"10",X"00",X"CD",X"F2",X"03",X"7A",X"E6",X"02",X"0E",X"00",X"28",X"02", + X"0E",X"0F",X"CD",X"E1",X"03",X"AF",X"C9",X"3E",X"01",X"CD",X"0C",X"04",X"21",X"70",X"00",X"22", + X"75",X"20",X"CD",X"F2",X"03",X"3E",X"05",X"32",X"74",X"20",X"4F",X"CD",X"E1",X"03",X"AF",X"C9", + X"E6",X"3F",X"20",X"06",X"2C",X"35",X"4E",X"CD",X"E1",X"03",X"2A",X"75",X"20",X"CB",X"52",X"3E", + X"01",X"28",X"02",X"ED",X"44",X"85",X"6F",X"CD",X"F2",X"03",X"AF",X"C9",X"3E",X"01",X"CD",X"0C", + X"04",X"CD",X"24",X"03",X"21",X"00",X"01",X"CD",X"F2",X"03",X"3E",X"0F",X"32",X"79",X"20",X"4F", + X"CD",X"E1",X"03",X"AF",X"32",X"78",X"20",X"C9",X"21",X"78",X"20",X"35",X"7E",X"E6",X"3F",X"FE", + X"0C",X"0E",X"00",X"28",X"0A",X"B7",X"20",X"0A",X"21",X"79",X"20",X"35",X"28",X"06",X"4E",X"CD", + X"E1",X"03",X"AF",X"C9",X"3D",X"C9",X"00",X"10",X"0F",X"0E",X"0D",X"0C",X"0B",X"0A",X"09",X"08", + X"07",X"06",X"05",X"04",X"03",X"02",X"01",X"2C",X"2B",X"2A",X"29",X"28",X"27",X"26",X"25",X"24", + X"23",X"22",X"21",X"20",X"1F",X"1E",X"1D",X"1C",X"1B",X"1A",X"19",X"18",X"17",X"16",X"15",X"14", + X"13",X"12",X"11",X"98",X"02",X"55",X"07",X"C1",X"07",X"1E",X"08",X"8D",X"08",X"EF",X"08",X"28", + X"09",X"82",X"09",X"DC",X"09",X"E4",X"09",X"4C",X"0A",X"A2",X"0A",X"ED",X"0A",X"4D",X"0B",X"B1", + X"0B",X"15",X"0C",X"BC",X"0C",X"B9",X"0D",X"D0",X"0D",X"D0",X"0D",X"D0",X"0D",X"BE",X"0D",X"D0", + X"0D",X"D0",X"0D",X"C3",X"0D",X"D0",X"0D",X"D0",X"0D",X"C8",X"0D",X"D0",X"0D",X"D0",X"0D",X"07", + X"07",X"0C",X"07",X"11",X"07",X"16",X"07",X"1B",X"07",X"20",X"07",X"25",X"07",X"2A",X"07",X"2F", + X"07",X"34",X"07",X"39",X"07",X"3E",X"07",X"43",X"07",X"48",X"07",X"4D",X"07",X"00",X"00",X"7E", + X"07",X"E2",X"07",X"3C",X"08",X"AB",X"08",X"0C",X"09",X"4C",X"09",X"A9",X"09",X"00",X"00",X"0E", + X"0A",X"6D",X"0A",X"C3",X"0A",X"11",X"0B",X"71",X"0B",X"D5",X"0B",X"39",X"0C",X"D8",X"0C",X"D9", + X"0D",X"EE",X"0D",X"E0",X"0D",X"E7",X"0D",X"D9",X"0D",X"E0",X"0D",X"E7",X"0D",X"D9",X"0D",X"E0", + X"0D",X"E7",X"0D",X"D9",X"0D",X"E0",X"0D",X"E7",X"0D",X"3E",X"00",X"C3",X"CA",X"0D",X"3E",X"01", + X"C3",X"CA",X"0D",X"3E",X"02",X"C3",X"CA",X"0D",X"3E",X"03",X"32",X"33",X"20",X"CD",X"B9",X"06", + X"AF",X"CD",X"0C",X"04",X"CD",X"24",X"03",X"AF",X"C9",X"DD",X"21",X"18",X"20",X"C3",X"F8",X"04", + X"DD",X"21",X"20",X"20",X"C3",X"F8",X"04",X"DD",X"21",X"28",X"20",X"C3",X"F8",X"04",X"3A",X"37", + X"20",X"FE",X"FF",X"C8",X"3A",X"34",X"20",X"4F",X"CD",X"E1",X"03",X"2A",X"35",X"20",X"CB",X"3C", + X"CB",X"1D",X"CD",X"F2",X"03",X"AF",X"C9",X"1F",X"0E",X"3D",X"0E",X"72",X"0E",X"87",X"0E",X"B3", + X"0E",X"DD",X"0E",X"F2",X"0E",X"21",X"0F",X"4E",X"0F",X"62",X"0F",X"AC",X"0F",X"CF",X"0F",X"1F", + X"0F",X"5F",X"09",X"3F",X"0A",X"A6",X"80",X"81",X"86",X"60",X"61",X"86",X"60",X"68",X"3F",X"0B", + X"CA",X"C6",X"3F",X"0C",X"AB",X"80",X"8B",X"A6",X"A8",X"3F",X"0D",X"EA",X"FF",X"1F",X"03",X"5F", + X"07",X"80",X"76",X"76",X"80",X"76",X"76",X"80",X"76",X"76",X"80",X"76",X"76",X"80",X"76",X"76", + X"80",X"76",X"76",X"80",X"76",X"76",X"80",X"76",X"76",X"80",X"77",X"77",X"80",X"77",X"77",X"80", + X"77",X"77",X"80",X"77",X"77",X"80",X"76",X"76",X"80",X"76",X"76",X"80",X"76",X"76",X"80",X"76", + X"76",X"FF",X"1F",X"03",X"5F",X"08",X"A6",X"A1",X"A6",X"A1",X"A6",X"A1",X"A6",X"AA",X"AB",X"A6", + X"AB",X"AB",X"A6",X"A5",X"A3",X"A1",X"FF",X"1F",X"0E",X"3F",X"03",X"5F",X"09",X"38",X"38",X"38", + X"38",X"78",X"3A",X"5A",X"38",X"3A",X"5A",X"3D",X"38",X"38",X"38",X"38",X"78",X"36",X"56",X"35", + X"36",X"56",X"38",X"35",X"35",X"35",X"35",X"75",X"33",X"53",X"31",X"33",X"53",X"35",X"71",X"71", + X"71",X"60",X"FF",X"1F",X"0E",X"5F",X"09",X"35",X"35",X"35",X"35",X"75",X"36",X"56",X"35",X"36", + X"56",X"3A",X"35",X"35",X"35",X"35",X"75",X"33",X"53",X"31",X"33",X"53",X"35",X"31",X"31",X"31", + X"31",X"71",X"30",X"50",X"2E",X"30",X"50",X"31",X"6E",X"6E",X"6E",X"60",X"FF",X"1F",X"08",X"5F", + X"09",X"69",X"69",X"6A",X"6A",X"69",X"69",X"67",X"67",X"65",X"65",X"67",X"67",X"65",X"65",X"65", + X"60",X"FF",X"1F",X"0E",X"3F",X"0B",X"5F",X"09",X"8E",X"6E",X"6E",X"8E",X"6E",X"6E",X"90",X"70", + X"70",X"90",X"70",X"70",X"8E",X"6E",X"6E",X"8E",X"6E",X"6E",X"90",X"70",X"70",X"90",X"70",X"70", + X"92",X"72",X"72",X"93",X"73",X"73",X"B2",X"B0",X"8E",X"6E",X"6E",X"6E",X"72",X"6E",X"72",X"AE", + X"FF",X"1F",X"0E",X"5F",X"09",X"92",X"72",X"72",X"92",X"72",X"72",X"93",X"73",X"73",X"93",X"73", + X"73",X"92",X"72",X"72",X"92",X"72",X"72",X"93",X"73",X"73",X"93",X"73",X"73",X"95",X"75",X"75", + X"97",X"77",X"77",X"B5",X"B3",X"92",X"72",X"72",X"72",X"75",X"72",X"75",X"B2",X"FF",X"1F",X"02", + X"5F",X"08",X"AE",X"A0",X"B0",X"A0",X"AE",X"A0",X"B0",X"A0",X"B2",X"B3",X"B2",X"B0",X"B2",X"B2", + X"B2",X"FF",X"1F",X"0E",X"5F",X"09",X"3F",X"0B",X"69",X"66",X"82",X"82",X"62",X"64",X"66",X"67", + X"89",X"89",X"89",X"86",X"3F",X"0A",X"8B",X"8B",X"8B",X"60",X"69",X"8B",X"60",X"69",X"6B",X"6D", + X"6E",X"70",X"3F",X"09",X"92",X"1F",X"08",X"89",X"89",X"1F",X"0E",X"6E",X"69",X"3F",X"08",X"8E", + X"1F",X"08",X"89",X"89",X"1F",X"0E",X"69",X"66",X"3F",X"07",X"89",X"1F",X"08",X"89",X"89",X"1F", + X"0E",X"64",X"66",X"3F",X"06",X"82",X"1F",X"08",X"89",X"89",X"A0",X"FF",X"1F",X"08",X"5F",X"08", + X"80",X"82",X"89",X"89",X"89",X"82",X"89",X"89",X"89",X"82",X"8B",X"8B",X"8B",X"82",X"8B",X"8B", + X"8B",X"80",X"86",X"86",X"A0",X"86",X"86",X"A0",X"87",X"87",X"A0",X"86",X"86",X"A0",X"FF",X"1F", + X"08",X"5F",X"08",X"A0",X"86",X"86",X"86",X"80",X"86",X"86",X"86",X"80",X"87",X"87",X"87",X"80", + X"87",X"87",X"87",X"80",X"82",X"82",X"A0",X"82",X"82",X"A0",X"81",X"81",X"A0",X"82",X"82",X"A0", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/locomotn.zip b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/locomotn.zip new file mode 100644 index 00000000..89fa19e5 Binary files /dev/null and b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/locomotn.zip differ diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/make_GuttangGottong_proms.bat b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/make_GuttangGottong_proms.bat new file mode 100644 index 00000000..ebf3d7e9 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/make_GuttangGottong_proms.bat @@ -0,0 +1,15 @@ +copy /B 3d_1.bin + 3e_2.bin + 3f_3.bin + 3h_4.bin + 3j_5.bin JUNGLER.ROM +make_vhdl_prom JUNGLER.ROM jng_prg_rom.vhd + +copy /B 5l_c1.bin + 5m_c2.bin gfx1.bin +make_vhdl_prom gfx1.bin jng_chr_rom.vhd + +make_vhdl_prom 10g.bpr jng_dot_rom.vhd + +make_vhdl_prom 1b_s1.bin jng_snd_rom.vhd + + + +make_vhdl_prom 8b.bpr jng_pal_rom.vhd +make_vhdl_prom 9d.bpr jng_col_rom.vhd + diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/make_locomotion_proms.bat b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/make_locomotion_proms.bat new file mode 100644 index 00000000..ef4aebe2 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/make_locomotion_proms.bat @@ -0,0 +1,17 @@ +copy /B 1a.cpu + 2a.cpu + 3.cpu + 4.cpu + 5.cpu LOCOMOTION.ROM +make_vhdl_prom LOCOMOTION.ROM loc_prg_rom.vhd + +copy /B 5l_c1.bin + c2.cpu gfx1.bin +make_vhdl_prom gfx1.bin loc_chr_rom.vhd + +make_vhdl_prom 10g.bpr loc_dot_rom.vhd + +make_vhdl_prom 1b_s1.bin loc_snd_rom.vhd + + + +make_vhdl_prom 8b.bpr loc_pal_rom.vhd +make_vhdl_prom 9d.bpr loc_col_rom.vhd + +pause + diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/make_vhdl_prom.exe b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/make_vhdl_prom.exe new file mode 100644 index 00000000..1e5618bf Binary files /dev/null and b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/make_vhdl_prom.exe differ