From 465830203dc9f97acf6934e9614b5b4c6a9eacac Mon Sep 17 00:00:00 2001 From: Marcel Date: Thu, 3 Oct 2019 16:15:22 +0200 Subject: [PATCH] sync --- .../Comando_MiST/Commando.qpf | 31 + .../Comando_MiST/Commando.qsf | 174 ++ .../Comando_MiST/README.txt | 18 + .../Comando_MiST/Snapshot/Commando.rbf | Bin 0 -> 320352 bytes .../Comando_MiST/clean.bat | 37 + .../Comando_MiST/rtl/Commando_mist.sv | 171 ++ .../Comando_MiST/rtl/T65/T65.vhd | 564 +++++ .../Comando_MiST/rtl/T65/T65_ALU.vhd | 260 +++ .../Comando_MiST/rtl/T65/T65_MCode.vhd | 1052 +++++++++ .../Comando_MiST/rtl/T65/T65_Pack.vhd | 117 + .../Comando_MiST/rtl/T80/T80.vhd | 1073 +++++++++ .../Comando_MiST/rtl/T80/T80_ALU.vhd | 351 +++ .../Comando_MiST/rtl/T80/T80_MCode.vhd | 1934 +++++++++++++++++ .../Comando_MiST/rtl/T80/T80_Pack.vhd | 208 ++ .../Comando_MiST/rtl/T80/T80_Reg.vhd | 105 + .../Comando_MiST/rtl/T80/T80s.vhd | 190 ++ .../Comando_MiST/rtl/YM2149_linmix_sep.vhd | 574 +++++ .../Comando_MiST/rtl/build_id.tcl | 35 + .../Comando_MiST/rtl/cmd_hvgen.v | 36 + .../Comando_MiST/rtl/cmd_sound.vhd | 425 ++++ .../Comando_MiST/rtl/cmd_sprite.v | 154 ++ .../Comando_MiST/rtl/cmd_top.v | 195 ++ .../Comando_MiST/rtl/cmd_video.v | 194 ++ .../Comando_MiST/rtl/dpram.vhd | 123 ++ .../Comando_MiST/rtl/gen_ram.vhd | 84 + .../Comando_MiST/rtl/pll.qip | 4 + .../Comando_MiST/rtl/pll.v | 309 +++ .../Comando_MiST/rtl/rams.v | 64 + .../Comando_MiST/rtl/roms/cmd_chr_rom.vhd | 534 +++++ .../Comando_MiST/rtl/roms/cmd_col_rom.vhd | 38 + .../Comando_MiST/rtl/roms/cmd_dot_rom.vhd | 38 + .../Comando_MiST/rtl/roms/cmd_pal_rom.vhd | 24 + .../Comando_MiST/rtl/roms/cmd_prg_rom.vhd | 1302 +++++++++++ .../Comando_MiST/rtl/roms/cmd_snd_rom.vhd | 278 +++ .../Comando_MiST/rtl/roms/commsega.zip | Bin 0 -> 19296 bytes .../rtl/roms/make_commando_proms.bat | 15 + .../Comando_MiST/rtl/roms/make_vhdl_prom.exe | Bin 0 -> 119861 bytes .../Jungler_MiST/Jungler.qpf | 31 + .../Jungler_MiST/Jungler.qsf | 174 ++ .../Jungler_MiST/README.txt | 18 + .../Jungler_MiST/Snapshot/Jungler.rbf | Bin 0 -> 309605 bytes .../Jungler_MiST/clean.bat | 37 + .../Jungler_MiST/rtl/T65/T65.vhd | 564 +++++ .../Jungler_MiST/rtl/T65/T65_ALU.vhd | 260 +++ .../Jungler_MiST/rtl/T65/T65_MCode.vhd | 1052 +++++++++ .../Jungler_MiST/rtl/T65/T65_Pack.vhd | 117 + .../Jungler_MiST/rtl/T80/T80.vhd | 1073 +++++++++ .../Jungler_MiST/rtl/T80/T80_ALU.vhd | 351 +++ .../Jungler_MiST/rtl/T80/T80_MCode.vhd | 1934 +++++++++++++++++ .../Jungler_MiST/rtl/T80/T80_Pack.vhd | 208 ++ .../Jungler_MiST/rtl/T80/T80_Reg.vhd | 105 + .../Jungler_MiST/rtl/T80/T80s.vhd | 190 ++ .../Jungler_MiST/rtl/YM2149_linmix_sep.vhd | 574 +++++ .../Jungler_MiST/rtl/build_id.tcl | 35 + .../Jungler_MiST/rtl/dpram.vhd | 123 ++ .../Jungler_MiST/rtl/gen_ram.vhd | 84 + .../Jungler_MiST/rtl/jng_hvgen.v | 36 + .../Jungler_MiST/rtl/jng_sound.vhd | 425 ++++ .../Jungler_MiST/rtl/jng_sprite.v | 154 ++ .../Jungler_MiST/rtl/jng_top.v | 195 ++ .../Jungler_MiST/rtl/jng_video.v | 194 ++ .../Jungler_MiST/rtl/jungler_mist.sv | 175 ++ .../Jungler_MiST/rtl/pll.qip | 4 + .../Jungler_MiST/rtl/pll.v | 309 +++ .../Jungler_MiST/rtl/rams.v | 64 + .../Jungler_MiST/rtl/roms/jng_chr_rom.vhd | 278 +++ .../Jungler_MiST/rtl/roms/jng_col_rom.vhd | 38 + .../Jungler_MiST/rtl/roms/jng_dot_rom.vhd | 38 + .../Jungler_MiST/rtl/roms/jng_pal_rom.vhd | 24 + .../Jungler_MiST/rtl/roms/jng_prg_rom.vhd | 1046 +++++++++ .../Jungler_MiST/rtl/roms/jng_snd_rom.vhd | 278 +++ .../Jungler_MiST/rtl/roms/jungler.zip | Bin 0 -> 13766 bytes .../rtl/roms/make_jungler_proms.bat | 15 + .../Jungler_MiST/rtl/roms/make_vhdl_prom.exe | Bin 0 -> 119861 bytes .../Locomotion_MiST/Locomotion.qpf | 31 + .../Locomotion_MiST/Locomotion.qsf | 174 ++ .../Locomotion_MiST/README.txt | 18 + .../Locomotion_MiST/Snapshot/Locomotion.rbf | Bin 0 -> 322817 bytes .../Locomotion_MiST/clean.bat | 37 + .../Locomotion_MiST/rtl/Locomotion_mist.sv | 176 ++ .../Locomotion_MiST/rtl/T65/T65.vhd | 564 +++++ .../Locomotion_MiST/rtl/T65/T65_ALU.vhd | 260 +++ .../Locomotion_MiST/rtl/T65/T65_MCode.vhd | 1052 +++++++++ .../Locomotion_MiST/rtl/T65/T65_Pack.vhd | 117 + .../Locomotion_MiST/rtl/T80/T80.vhd | 1073 +++++++++ .../Locomotion_MiST/rtl/T80/T80_ALU.vhd | 351 +++ .../Locomotion_MiST/rtl/T80/T80_MCode.vhd | 1934 +++++++++++++++++ .../Locomotion_MiST/rtl/T80/T80_Pack.vhd | 208 ++ .../Locomotion_MiST/rtl/T80/T80_Reg.vhd | 105 + .../Locomotion_MiST/rtl/T80/T80s.vhd | 190 ++ .../Locomotion_MiST/rtl/YM2149_linmix_sep.vhd | 574 +++++ .../Locomotion_MiST/rtl/build_id.tcl | 35 + .../Locomotion_MiST/rtl/dpram.vhd | 123 ++ .../Locomotion_MiST/rtl/gen_ram.vhd | 84 + .../Locomotion_MiST/rtl/loc_hvgen.v | 36 + .../Locomotion_MiST/rtl/loc_sound.vhd | 425 ++++ .../Locomotion_MiST/rtl/loc_sprite.v | 154 ++ .../Locomotion_MiST/rtl/loc_top.v | 195 ++ .../Locomotion_MiST/rtl/loc_video.v | 194 ++ .../Locomotion_MiST/rtl/pll.qip | 4 + .../Locomotion_MiST/rtl/pll.v | 309 +++ .../Locomotion_MiST/rtl/rams.v | 64 + .../Locomotion_MiST/rtl/roms/gutangtn.zip | Bin 0 -> 20474 bytes .../Locomotion_MiST/rtl/roms/loc_chr_rom.vhd | 534 +++++ .../Locomotion_MiST/rtl/roms/loc_col_rom.vhd | 38 + .../Locomotion_MiST/rtl/roms/loc_dot_rom.vhd | 38 + .../Locomotion_MiST/rtl/roms/loc_pal_rom.vhd | 24 + .../Locomotion_MiST/rtl/roms/loc_prg_rom.vhd | 1302 +++++++++++ .../Locomotion_MiST/rtl/roms/loc_snd_rom.vhd | 278 +++ .../Locomotion_MiST/rtl/roms/locomotn.zip | Bin 0 -> 21193 bytes .../rtl/roms/make_GuttangGottong_proms.bat | 15 + .../rtl/roms/make_locomotion_proms.bat | 17 + .../rtl/roms/make_vhdl_prom.exe | Bin 0 -> 119861 bytes 113 files changed, 31647 insertions(+) create mode 100644 Arcade_MiST/Namco Rally X Hardware/Comando_MiST/Commando.qpf create mode 100644 Arcade_MiST/Namco Rally X Hardware/Comando_MiST/Commando.qsf create mode 100644 Arcade_MiST/Namco Rally X Hardware/Comando_MiST/README.txt create mode 100644 Arcade_MiST/Namco Rally X Hardware/Comando_MiST/Snapshot/Commando.rbf create mode 100644 Arcade_MiST/Namco Rally X Hardware/Comando_MiST/clean.bat create mode 100644 Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/Commando_mist.sv create mode 100644 Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T65/T65.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T65/T65_ALU.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T65/T65_MCode.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T65/T65_Pack.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T80/T80.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T80/T80_ALU.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T80/T80_MCode.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T80/T80_Pack.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T80/T80_Reg.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T80/T80s.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/YM2149_linmix_sep.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/build_id.tcl create mode 100644 Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/cmd_hvgen.v create mode 100644 Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/cmd_sound.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/cmd_sprite.v create mode 100644 Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/cmd_top.v create mode 100644 Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/cmd_video.v create mode 100644 Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/dpram.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/gen_ram.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/pll.qip create mode 100644 Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/pll.v create mode 100644 Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/rams.v create mode 100644 Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/cmd_chr_rom.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/cmd_col_rom.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/cmd_dot_rom.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/cmd_pal_rom.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/cmd_prg_rom.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/cmd_snd_rom.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/commsega.zip create mode 100644 Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/make_commando_proms.bat create mode 100644 Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/make_vhdl_prom.exe create mode 100644 Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/Jungler.qpf create mode 100644 Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/Jungler.qsf create mode 100644 Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/README.txt create mode 100644 Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/Snapshot/Jungler.rbf create mode 100644 Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/clean.bat create mode 100644 Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T65/T65.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T65/T65_ALU.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T65/T65_MCode.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T65/T65_Pack.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T80/T80.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T80/T80_ALU.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T80/T80_MCode.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T80/T80_Pack.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T80/T80_Reg.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T80/T80s.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/YM2149_linmix_sep.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/build_id.tcl create mode 100644 Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/dpram.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/gen_ram.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jng_hvgen.v create mode 100644 Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jng_sound.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jng_sprite.v create mode 100644 Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jng_top.v create mode 100644 Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jng_video.v create mode 100644 Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jungler_mist.sv create mode 100644 Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/pll.qip create mode 100644 Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/pll.v create mode 100644 Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/rams.v create mode 100644 Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_chr_rom.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_col_rom.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_dot_rom.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_pal_rom.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_prg_rom.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_snd_rom.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jungler.zip create mode 100644 Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/make_jungler_proms.bat create mode 100644 Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/make_vhdl_prom.exe create mode 100644 Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/Locomotion.qpf create mode 100644 Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/Locomotion.qsf create mode 100644 Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/README.txt create mode 100644 Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/Snapshot/Locomotion.rbf create mode 100644 Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/clean.bat create mode 100644 Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/Locomotion_mist.sv create mode 100644 Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T65/T65.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T65/T65_ALU.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T65/T65_MCode.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T65/T65_Pack.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T80/T80.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T80/T80_ALU.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T80/T80_MCode.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T80/T80_Pack.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T80/T80_Reg.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T80/T80s.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/YM2149_linmix_sep.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/build_id.tcl create mode 100644 Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/dpram.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/gen_ram.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/loc_hvgen.v create mode 100644 Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/loc_sound.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/loc_sprite.v create mode 100644 Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/loc_top.v create mode 100644 Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/loc_video.v create mode 100644 Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/pll.qip create mode 100644 Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/pll.v create mode 100644 Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/rams.v create mode 100644 Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/gutangtn.zip create mode 100644 Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/loc_chr_rom.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/loc_col_rom.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/loc_dot_rom.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/loc_pal_rom.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/loc_prg_rom.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/loc_snd_rom.vhd create mode 100644 Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/locomotn.zip create mode 100644 Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/make_GuttangGottong_proms.bat create mode 100644 Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/make_locomotion_proms.bat create mode 100644 Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/make_vhdl_prom.exe diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/Commando.qpf b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/Commando.qpf new file mode 100644 index 00000000..e7c6f85a --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/Commando.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition +# Date created = 04:04:47 October 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.0" +DATE = "04:04:47 October 16, 2017" + +# Revisions + +PROJECT_REVISION = "Commando" diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/Commando.qsf b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/Commando.qsf new file mode 100644 index 00000000..239885bd --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/Commando.qsf @@ -0,0 +1,174 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2014 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition +# Date created = 15:32:46 October 03, 2019 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Commando_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name SYSTEMVERILOG_FILE rtl/Commando_mist.sv +set_global_assignment -name VERILOG_FILE rtl/cmd_top.v +set_global_assignment -name VERILOG_FILE rtl/cmd_video.v +set_global_assignment -name VERILOG_FILE rtl/cmd_hvgen.v +set_global_assignment -name VERILOG_FILE rtl/cmd_sprite.v +set_global_assignment -name VHDL_FILE rtl/cmd_sound.vhd +set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd +set_global_assignment -name VERILOG_FILE rtl/rams.v +set_global_assignment -name VHDL_FILE rtl/dpram.vhd +set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd +set_global_assignment -name VHDL_FILE rtl/roms/cmd_prg_rom.vhd +set_global_assignment -name VHDL_FILE rtl/roms/cmd_dot_rom.vhd +set_global_assignment -name VHDL_FILE rtl/roms/cmd_chr_rom.vhd +set_global_assignment -name VHDL_FILE rtl/roms/cmd_pal_rom.vhd +set_global_assignment -name VHDL_FILE rtl/roms/cmd_col_rom.vhd +set_global_assignment -name VHDL_FILE rtl/roms/cmd_snd_rom.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80s.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd +set_global_assignment -name VHDL_FILE rtl/T65/T65_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/T65/T65_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/T65/T65_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/T65/T65.vhd +set_global_assignment -name VERILOG_FILE rtl/pll.v +set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP +set_global_assignment -name TOP_LEVEL_ENTITY Commando_mist + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# --------------------------- +# start ENTITY(Commando_mist) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(Commando_mist) +# ------------------------- +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/README.txt b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/README.txt new file mode 100644 index 00000000..a6f37ade --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/README.txt @@ -0,0 +1,18 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Commando (Sega) port to MiST +-- xx xxxx 20xx +-- From: https://github.com/MrX-8B/MiSTer-Arcade-RallyX +-- + +Todo: Sound ,GFX and some Controls + +--------------------------------------------------------------------------------- +-- FPGA New Rally-X for Spartan-3 Starter Board +------------------------------------------------ +-- Copyright (c) 2005 MiSTer-X +--------------------------------------------------------------------------------- +-- T80/T80s - Version : 0242 +----------------------------- +-- Z80 compatible microprocessor core +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) \ No newline at end of file diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/Snapshot/Commando.rbf b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/Snapshot/Commando.rbf new file mode 100644 index 0000000000000000000000000000000000000000..ed87fcbc8a0643ce921cfb3dc47694add1c5b58c GIT binary patch literal 320352 zcmeFa4}2Wgb>BO?T-$3Kj(106WDK*^?r6=9AXy?Q+C>;Q-dPN+r360$5}mM#Vv)3x zr@BogD(!o2(pEdbz+8l&Ny${g#%=`Bj4eBVBr9_3CQZbZz=p1wh_dCzuW_q?Y2&0# zw3OAFw*2RPe|L6(1&Du=;C|$Whv59V_s+TJo_p@O=bU?I_Iux39zO6517CmPxo^Gj z!r61*{LXj2{mt)v_dDPD*7sic-gnNOJNKP$fBW3I?|$oB-}>WsFOTT|_*@HU0NrO@ zUx1g!fm{c=pH9r3(A! zJdXjd26WB>DkGY77AS2YBsp`(h55Rl%T2BpE3=Rv3(H&#{5l{EHDEP3Uv3%kLXhGS zF9a!VN*68H07=gLqws$bAK>PJ1VwEqC8p9LoXrFDbSQb^NPHoZ>k(^)c*LP}TK2IY$;Ju7_T<23L~ zz$xI1Kw8gI=O=+QFRfqa-9V`Ws;3*2toz>trhqaa+Vsq6AWc`E?!VdrU8j(yEp{GR z0EYqbTp)Q!t_p>eCXES!(!~$auQ8`_rGC*E(!F@1vq0CoI*_C!Y5xiM3ZSe7WQ+)Z zcm2BmM}VFYExJ$PV;xYsXb?@3|FrKu1f=6(xv}zi2hy^_lhSn^p!!mp(sN3K&M6(b zc7a;~p%fj*0iA_gX=xp+Ijip50MVmlA*w1G?`Abp8Y&K6FDjZ$^ZogU-5N2^Q*;bgZQ3w7#XzX?~b3n4D`B!JjWD3uBK=-;# z)6=uY*f=13X`04uHz=0nwoXB42ovEc(Rz?)p|sQ%Xas=Ec|429f?uL3&jn z8%>~e-D|G;aiF&YzXs_3zW_S#1VoF@g7*SCr}T+t*^en5;;*jLv5_)E_tIZF%N~+W z6KJfz8IY~}WgxYyb(TH76fD&7{|!)DN=JHDech1KmeM7@{}!M!DX%pDhz|l?r=WZB zrTe__I+ZK&Aq9SvwZOs(*8;B-v}rslBTQQZUmGj(EO!) z=`7jN0$slkNbZtjxBgY%ss3(A>k~~Wq-i><9)Ye!liKhlKysCW?ia$D1@IWqozzW( zt|fbE{W_~Yfv%;)Bwy04(lr8&`~M6mEd|}L1maOQXv}JCrl9&3gKq;Gd);}mB?OD5 zDgB8K==#M#H@*wk7dUW%0~a{3S`JA6NuSOu-!RKb^OBaiaTeq~^f6=Ib)|+~*Dvz& z(L+5i@`cO^0)18&(rP87hWm%_BXw1r6Q}&Kfjf$e)Rl;YfqSK zStW73?)V%FMpPOcYZf^vRI^+K7DR@GK1o-qX)-m#(;25+m?`m?2SrgB+m^$F*DX~jLw zT{Yk9%QXC5-ZYPfLw2@5t7rfApM$8Bu^OVjH=#m z&TH1uxBkxGocWKrzlva3k_)RN7II`?PU1tq@kWrz6EQBbe7TM!zTCw2?|n;?#`gpD zrn9BTwmcXdv+cJHzNO;nxOL0$xewLe;%vF$-2S~ED7PkV^pEx0Z~Mcay1c(k*^|fY z4e>1ldS?FFdpbDxp;zwX-Wh239*%GEk5@dk@S4ueTfVVoGqTnGTfebtMX+K)G{u_f zO6xm)E7rH_0&A_pR$cK*1=or&Vnvqqb7o{tSez*%-fIbuZ52Wl~=OLUulNM(lp>l@g3tKpz}i zGlA8l)JQDf1+~1C+u~pS5|6E&ZM~E+ZawtpYe%#74<=qpTNi)kf-+g0FUzDR6T|nz ze#JCay)V;rU-WV8dHGh0=Dp0si{5C=ZDUUdo+k_Zl1H#i9}LQmOx*5&qSwCR+=Tam z@?*FCJIrm$VtYSjtn13cvzHj*uh7T6tZ1KSZYMVn>@&<=MrK|_))Svu(_r`7C`-*R zg|j!VjoEG1ThIK*HErgLVDJh>Uz**wIMVO8t+0f(xi~TNQm^>QdABd?=KIVs<8!BD;k@>iMteYQteNyQ??E)cc|Qscg-r1~KSd|6oqfHO1%Dyhz1UbX3yJ7eDiRcS^Oun(aEWems zu zIM>=Jnnx)6?H1g>h}$QAKKmj{FJDxxT(gmRA>O?_v(L{xU;584v)YvJv%s#FjPuK_ zHDPNeuWL4wm^Pc;ia%Ip_nN=gcfpH4U;LL#Nyh*8$%0kIi-y8qX5#lRlJ4C1$#oav z-P)4BHsIXy=GVS5wdD_dyjx?IakK)ofBgsTZNn8Bv}pDPD`ru)ERzVwE=-ln@Mn>% zSF(_;nU1{>@Lr_nS4g_>O63J7egzRZFT3NCzDz@S(Z|1k*71c`D%aqJ&i_MSsa%~o z$~buFO>6dw%IcyAqHK|GFr7Cft)Kp1=cm1>l#=!v8t|-(zxIaoW{GntV|N+w%bW7; zAN{XOV3|#J)y@=F!1m>To)%oTHD2FiJUaqHmi!<&GzInBK+*YDn0fNvSmA>eZ@OcB33#J&n$h5 z7yiA;#nYEcU5>Q&SAS-y$L6KmjcDaAux>rRlB7Y4n|8yz3KqF}*S~oEBB@IzEz_Ai z^H49JL0BbdbHuXH{;lhl%~uzK!}O!1E@|>I1U|8TrG3DlGnmv5;1%}esBGVP#|jjt z*(sLN5^dJXUHi*=2YR((aQE6bpNL&POL$Mwnl6I3Q7k`P>|57(s$9-pTFI>N0TeBw zJ^A4!s7a{?t1acn=N20oK8R@Ur;E#soc5`k(}$Nh8-z9_lRt-YnOLA6|mMGv%uKb>q&AqEmT7SN(wn-`FMTa!jZA`b$x{9;zr2zGX2?%dy^i(rHUF*7C>{158KaoEit+UENj9yvr+pH|6fUgkv+az)4y-?+(!?s7xyv5Ti^aeOVH3sHg>tW zUZ(LWio1&|g^JRWE1y@6#LtnoBDQK~$K5NFCP~y}i9BM@E*opR|I`YO?Q~I+(+L2Z9sWliwi-(6KD_AC!P#+Fs?%P|_oNq8bK_sUc6p7;4>K@WOA#kJ9p%pitYaf3VgW*K3;QlzVO#UO z=FYo0A6xsU7RC(11%;%+nLKPwO3axeZ3POgLszY!Ss0(xBGL?b(pNNpDY*aa(s||? zkR%K<7W4`&wx0OJ3Z^cdlEjEOsR+OCDAO)jI!@dtk7OjV}@!+pDZMJ z9<|QDS|J<+lC&=j-g!?iym_*3CE6NM#&(m|$+mYfb(Ujb_3Tq`Us%cfdpKv8B4Q&Y zqE?DxC+e8vGI-nHcw|17^X>>P8-q`xh|Z@Lh2drKb#Y_iQ^nh#krT4iOQGO7?*ry( zN57~Kn_E}Dc^RP-Rf#37Hq6r4bvc`sUbMGNrI*W`Wu&eKZh2vaDZr2-qqmEuuFHjW z@O>A5g-NROh%uuLS`#T>hTi)JR~VUH7`4yze>Y@zETi&d8G45G?Lh@w+V5B&GS-g|OHCd3$eq;TK zPppo5dpO@2PKFqd=B`M+^XTus?tkkx`0Ib_Z41BAnBI4NtMSqY`PAcGYx}9kB|oH$apk~D>cr5d`Ixzi=V#}X6vO%F8?RZ2vpO$27&77-nG!=O8Q0)m z-XgjG_g9)r6C$AUd}vXHkTW0*BW;mYt|?pV1@T4F`oe&U9-=u13z`OfWQzq$$} zu)o7NPU+>M&t3e{<)x%r&zsel*@x5VVm6`s!fF5aAMU=Z-MkuV&u;!n)k=zB!MXa_ z53k%2r9=gbdt4e#x&Y1GZTq)J=WZ6eiqga`64Rvf&V{r8{x>W%&!RScgl3YE%^C02 zeBb6HCt};$GD&&_%`BWu)9wGA*WZhzwCOd=3ab@r` zRV`ygTkUP1n1|!Mn;0~UAw93)TtfSwy>q3-Ll%S8XI&;VE}!DuOTw)`oLe$a8P$Bl z-~*+wCO6Bs{mJ9Y52$3)OKM$lJX!a(Rv1rmZH&9vA(3uT|8(w_YTWJr=5JKfTe9>AGUt(!I4Ep(gii);x{Mzo|ulR+dE8P9T&vD-P zLHF@@JQ%!x{Gj>l`kwKF=DX{?U)iM(ukVR|OFwtS$$WXeb?(DFA}e0!E8IiLr`R{1 zbIlJStpW)y0Z6XzAi4f6Z%vSpuqcvCKhY~n?lP48$(mBahvcE8c8z|$=~;dXDIuhG z&C{P;@vAZ=IR-kU{sB_9TzI4X$!C|6-4~zErsd}HPsv9>sj>M;Dy5<5MV_qYtSA3$QO78nD{Zt|_<~`5yAQ&pRvV6CspVIEu z+Xk6c;Iu2KPKJ*{(Weve!;u;}qiSr1GqEy^2X89G6ba>d+mAoa#w zx%4hMcUWD`n?@JRsbqsnKw8qJ$?d{pvNz|xv7F&UJm(|O?}@{sIz@0Q08rfNvut`L zaY@0*j;Xf&jbG^`R@F>gCu4AM1(*3^ z$bus24mbgIHIeLlzNg9>V|2D!)-X6btkq|BJ(16H4;U}!p zo#gMZ-;IvchKVO9l5F$`Ar`AW{$a8VwdUM8h&8?{!x+|(5PhX=1jeL3iit3RL1nH| zk}dc5emdoC=iE7!Ofya4!}MY^OF~rxImK4Wc-+V$?Gj!tsm!*1`_Igioq;jiT5Bqc z4rlzGCgY=3e!450EVRL9UR;PBt7&anOUw1bs}mED*j?UA1C6#6@+?}u;Rny zao^P(?v&8si8;6LyoMxM*d3U=O2%i zYoIAAkFGPNfU-a=g+dg_j%&GaVcnKth@YL%b&>Wr&>cdZ+@$_vBj@8 zA$nVl{5w2n%Fb7})eqOG@DH0OV$0++S$MAHcYfzJzO!aodflNPvv%^Hq5{vf&MkWD z@7Zj*=J#Hwi-WHnz86dPezzRtW3f6TM`vy@XaRbH-|wGFa#*17ls8#DtGZF|dD3vH@e8S*n4N zs4`@V`WZ!6_-IQcDFNsL?g$X*fJ%3W?D)+I}3-ahl#iq**?zscl)bVt;Z|Sc;JK<*~ z8p#87BSalFLNzoX?R&$i*_#eVNOcsngStTn;c#tMOJ|owV%^<%(;GC%U8?9T z55@GzL9OA%q#ODc{;|xoEgBr3A$`9WL-VjEkObRee%24~ zETOGBRZ&a`t6u?g!vi4`N2l3wbZHJEP6$(i&7Wh(Y-$O@qHKbt)Ka-#IrA64C)fM< zk3ASXJ+{wyaeK#%Q@8aUU#auEu5WSPf$zjm*Y1f9n%}PN{mL)sXS901vd#Q>?bNfK zAFtK<>9Mnk6SsFP@#=m6k>JG{-xMd#w1)c~_r76_Ny+@9J5~)iJE`8bl9fCy=A~e} z_kUvL;9FXHr8E0G8^(%=jOc5sXSR{2!HibTZ_ICG?wiU?X8ou%W;eYt`;^}pTNjaC z$`p?J5k`I?u^I=k`Y<7^WVxiP;zYZ&`>!$B88fp`&^)R;<55{mZOHW%Du39un9-T= zH*tpqCdFnS?7Dc@&$4nQsWi4mO23i}`T6*Sd&0+5@@PRen!Qb3zxI5R zYsN@IGCVXC6Xu!pY)z*CeuX%~)}`(>vQoxm&e3i9x|C`E$YUnMP-q+%U4a6Cg?=ZK zv^Z8n8%XYy1_;l0a3-h5Yz0Y2{;mI!K5Cc&)g7jQn{i?4izUvkXIzD}v=BEgfft}n zFe!%{{gsiF_FsM!kys93s77&j5f8%C2qcIA`8f@#3c;0ja^^BJ3CW=|l8r1W#q?fu z0=FoUDm(z&x;>j8Y&k4AB0tt)xU2QJ3DGtpm zuh3L_-=Ur+Ei-@kYtnkA@z(u5?E&yKJd%?{+9s_~!tWeuBB~8_>@<4(*p_bDlyuG- z7*uuk@4eZIWyISPUukAWns|S*a*w||e`#(4?{ETB)Oao|jy*m0#b##OD^?$CUe|2Y zexcrczrv55%T$xrm~3p~y2{NX%)oen#I_tgKK z?;j{mmk)RcU9124ru>?1>l(-4(YB8lr#<5pNTB9`dON$&toEnBn50AL{JQ0IBvl&< z`*E4Ef4uwMOh0CyTRKMFZB^ZPz|UI!>r`()4m#?`7?D}H-0HoGJV;p zHm0)9AIhxp^cdZ8NUE$+6VJ`z>1eb$eaQ&_!2{cOHK(tVwIN5+vr5OVf)`wtmTGG? zbMd!dOC^aLDK=~Pbk#eNZx9@ndkF~|NGxFWD~d%oJSmFszvVAaqi5xu&u+Lx{3MJV zI?#4^%DI?9k41>>|kcZX5X&g!+PK4RQV$q%8%u}Ed zs4a!LwtyX{&x3>0I^b-N*}IzfmWWzM6Nu0lO$~dcVp`P~-(w_coj5FAeTXxxA`VcpI z_+HPY)s3g3jtrNc^9Sh7tE!Qxl1qA=Su%Tqp3wS=3E8uRXqFP8g{4Hg|3nPq$!%or zKeSGo0yS2JlB#>OCN+XH2!V?HS(5=v7Enp4)L|_dFOgUofq92Gv29&eBa-i*h^gNq zIy{TdxRz#Lq1xO2PrtIenP%2V=pZzPfVg2fconnHG_umD5Gu+%6>ezll8#(h1G^e| zdUr%&=g@Dwdi8$i12=0G@y4kKd@UpDtcADPb;OT$R^G1tXtD(Oxz1wby$^0Ti;?#x zOMt6cjQrLow4iy;J$}nJgXFk=NP5rsq3h%XKNUUa8!vc+f1mj^=?#8oQS)1K#Jsdc z&83zSpZoKFRD!!HM6vk?XB$}rz~9J!A{te<>D4;__ePQ5zbA_5fG5X3<9f%+8;|;p zOV-7_#!mFq%esUPN*XtdK=tg;K9?j{b5bB(Ma+%gm9WI6-nE>C_P>2^V-|_A6_{kJ zs8lQ7J%*;(1VY+@zae9E+!&%;Vr$%x$B0tsR}=h}js}vAik*UKGE0B)N?FV)Ac{=p z3SDDV9#+_uaD5|78jFPt9J6J&kl#I~mJos^M&yl^IcsPca5^)2=l1?x+E1H+VZjiy z9znPcB*uiS9AF?#Ep_~1qdPi5GFHvf?DjkUIK5o*oFEp0lrZT?K!eJ_T>6jxYMQp% z^BgVai8+;LS&zPt0lqrW>~A0yiw;}nD8p{7Bs)?iPX^M4C3k8~jMk7^Y1Cp^6e|*r zLL|eWHB3(m>qt3^7pImBornrUiEya8M!;bfl(hh9`>8*l%{CW_s+*UVu&g1&ezpmX z*)Huaijm+wbcb;*Vk_v*QCn&8Y!{lmlrzkL^UJ1pr3_bhU%%*Tcv|K~ojYHdd{NIV zS$I`nKwI+Z`56}oo6nDx?_S{?(`cRl7KLOVIhU<4YeAUd_+pBl9sPe-X3c6#{LK;I zf)vSWA(~$>xiuQuYWUgP|5yP}DZ)8r#ucV0X{KyMuc}YYbS+%ENzaNk=(=R0W*iMP zvhBB@PA(Te8pLF!^VMA4X-=wn98DA!$is-GLtZzxsgPQh?FKhW9W5b zkq;!3cv`R3zU?oS+JQpP40^rFZW5x&h9|-vAmz;#v4=vQzr?DDQZC?Y*yBO|1UZe& zxZENpzS*7U;Ju~qH6f>DYl>N3Cu~}Gcg0j88;S~OJvX!*5?wAusXJwiBjK|Rci6aL zf@C%U4zpOTPBJCi8!v+7bSn@Sn2`iUR6~`}2qu$39%zSDCon`@#a2w8s*)KriHK91 zFq-@PkXIliU=BhF0=JjYvsDVrMh1}3GB*a#RwYlDyWNzeu|Y^>yRrcg2b2YqbWTBu0j zi4SPA>D=z1q-Cb%F3h4us-~2IG_~J|km(I&=q_QB5!YT*n&kHHOquNDAnGh*ui}uI zZtluVTbb0GW|*ovHwhP>_<0S+1aJ^Kk4Z!f0TM}B#ENg3v17zIGLkK1h=qD5$us8; z;q9kyt5#CF$-sbDpMgslIT`9^b?$ib%!j(8y5bOBWu%Eq0|_sZO4Z%fW~Q{+ z9Zy0J9dli@mc*Ro5sr87oM&|Eal_DrFJe=SZ_B9Lgw(3LHE2$-7d=7I!E1zJ4ymyJ z{$J~ug18B8gF5ZXG%u~NV|YU!iY0A1p~u;B?Ww0`uMvliAehHHG^=Hl2Zf2nl4>&M zP$bVMlp0pGPyWY}TG;`Ln`9VljM|hoGXQu@UOq)*@)^LLxGxDdFZ4!?L~Si452&7f z@5AOo2Qy-&+YEB`xa2G;m=tQ5kVtYp|42^qn38Y#({+Qh$rz zNkyuuFN!03cNC$fla(yH>Ykz>tz@F2DDLCr(y3I@?AiHT9>N<|_d)*lAgnETHQRXnhoF+95TP#WR4=L8&R>eU_|Vth7{Yx? zm)R&Za_|25aE*Z1ty6@E6^%2|#!j%Atw@hGYx(MJb)wBy-)D~Sam$21Nidpx_E}iH z%72x$iPtnF5V7KbZmDd(t(t8FdP{@XH{y6WPearqqS+4}$_7KZlr9s0bCd9!q?-Ll zX1|HHk0@SFyA=~QP#W!oL*YPQQ32^rh?WAX86Be7pDxMMx~CDJ%l@ES<4d>=V$)o0 z2|~fruU(KvUBz*txCXg7CgEV|0o4JBMg)QXZSU_^|8YFqEJBIMj3g8iI(0}$%~J|b z3TEp8UDQ=gf}Qa+TMHB_(i>0IGtWNtL*X3zU{?pd8jA%)l}VC1lmz!cE|#&m|RZj9bZxM!lQnr|g&meCE3Ohh4rKdGeD!LKyv zS1z3T>K8`3T7U$aF>408O3;vmPt!$~YoZKelRp#CO(MIL5r9**bZj6JI=hs_)%O3q zXJm#XT5lW^Hq@ZH(>bGSua8pI`gAuEI#e-Rt%Ik}fP>CaRlKqhX=z-@&PYJv7KipH zf3CWoq_i?^>#^8C1h+H+o**zgF}t^j8HN2!F(pig%(_iBZ=bWqmT*&Fws!iw47Zo& zn9KWAi4IV$yTIm=I>|f zAo=pV{Y;+?I+Tod_A`ApFqHiA;9FL`pJ|a@LtDMO|q=1Kz<%-h>&R1e)yb`m(Uui zt7|BhOj+D31EkiBbZ^0p*$NaNcF+M~9MalcD~Jb+^_=Byasxu(SUpaT(r&@e%s>zB zP!waoYh@iL48^55``w><_0QzPYP|=~R?Vb+FpZ`m1Gz$v6%FkoQKZZia-o{NJF<4S z)SY3$&4tzBe;7@KHwR+S=SL|PM4Q~ukhwi`tAnFSM^b44M&#W%YP4LJWsA%tx8s>d z-vot0HOJccSRe(D9TTWEp{U?4blqK-lLiGaF)Zwit=>AhVQ2?dVQ2lYI|Apb`7kVH zVkFg#LfZ-(QIP9ps?AyB5nQsZ$tY7eDYpkL(pP+x|K97AsY?nSxtZmF}nRP9Tcm)Nu>i ze>Zs#2B{VHYFO`qS=3~D!*DFFh8piU)$~ZH96@BmLg+%Ym6-rFh(gtZxPs;Hd;z+U z#I%4Rzwg1}r5|0A&09TtFo-)Hj$uTW6SvqWTV6o{<)z^>=!&7I+Pxly&fnuUm z92AfwhLidYppry%XiOz4XJVQ%u4$9bFq2|$j(ynd7E)o;CgA~fDN`7Lok|8unHzWX zj3M!eY}g9Iq55zxm?3Z!Iz3?=%WEdN;ED%vwMRn}`a>5V6WOlZv3~FlXYdYpq<(n) zV9Tvm_5@c)y+<6hXYW6DjygyimT}>=3ha0) zQ+5AIWv1A7UDyb23vUQ7{h4TD{qf>p{ZwpYS&V1mC)wg+Rc{FU_C#;;pDwn1{C)Y? z@0CMy#Kno;;KuA|vNkZM+jn2ngBK+#s=LC%u3;+ zaf=(c5a8=j&T2c(Q2tPKcD-XJvI#1_r#O`B%bX047Y`JJu#b&XQRA$;ej>-4E`@uG zRMB%7y>`Gnk85l_83lR$m-|E$+aLYSDm9%P#=d}eO)5Ou!={=X^cZDkjff6zaw121 zi~Ib@DLJ8sqR*@!H7$um?hsT=>>3W$;6o7x#iOla&wM%v4P*#8(3k`ApV4oSdDOKY z{ntMfj*T=6Z0;Ez$|Vyqg`h*aNE8~rFv{_I6ICHc&TM1qdnzjC;-Q}Et|_=1f_>La zkn~L64rWjv$xRQvMBN+MEJO?XG86gxU5JDRcKmL3o%^?;GidFIC

X20)IIzR9WH z0!N+}EieKX6NXN#&lS{oCx<$TPl~bX7>&&#n3_n)K8T{M}+}>;^xeM zu^Xv~sq5tM@!}zb%6(J^Z8M|)K^h|mLB8#ZPWpkO^)5GC=%MM9 zsk*xypQ6SQj&OwG08~f=JHD8F=G_o-=9HN}#iWD0BluV|x#Z&{hrNW=kpCTzRC_VdWcvNeRB?dcJX&#MgPS?W39I{xX4OdmL4J_fOx zonYralz)x4A>Aox)}IHZsLVg(geNAdYbpF*LaGyR?jC1j$(&)9rq7-k1FL|} z$hF?}_Dr+-x=3awwgrQ?o?|o*L6#{I$^ORxbI7$C#V|j4hwM3=GbnN+tY6GVv*_v~ zI90Agi?F;_lH(XBRrVVy!~|d^`%&TSkNgyV8OSl@L#nDe)HT6KH5FkCF@xuf+^QAQ zC6Iz!Z) zZvs?K&(t0UCM}A0tA(eW5Y(;~+gxjVCLv0FM?VDl-X?MRPz$Q8JQ&na@aSK?*78dJ zSl(({Y}bSww(0t+a0!qrfhn(ERI4Dgl;fWh=eVp{j5jMN)~sUSSk>o)e{Kc6?mquW zt$Os$Ugh1Vj#OJ-tsNJqvWIJf^*j7aU&UCz?~a++^L9tYL$#x|D0*|bwl^Mrt#i4T z+u;%(IhvHLNC#2$IIn0FhmY2-@C%a|g9fH81|!*kikHbG%o7xcHt* z6kU2#-SK}5Q?IX{`>XAIr{8YgK;f$ z*>!C2-BmyQZr*_Y*j{@wYQ=xYo{BFz7nCo5I*v{`>-UxiUwyU9Tb`eKd+bc95eMVK zW54ugqp$Th*2}FU<*Db7bl$RBq6=SCvNo(Rq5`b!Tu|*{WFef1*%C57u!rTHG9G3S z*j|T7P0U1bSg(kcif(Ru3oBo9EWJh|A)jb_&|`BXM=TW?{l4 zxx%h`5(tP2i2(0YC^+_Rw+1uij^0qL24Yd8G;WCd3gs!fF|Mq?Sx0;_Q)k#Ptda` z48%%%h7eGr=*D9$Hh)%U{A!+|Uiey+Wl+mwQyfvRzuo?yRTEH-#8bKGn(%?hIKW{c z#MQ#uA!P<64g|P$0#j%o{^dw-sWhAKt#B%gE*>s9hhqI;6G+#BV@}wGPln$6S zav$S+PJjrODcKG&eCu#iRTzDUaR6;0dFZQZUUl$L%pM!W%WCgCZoxJ9#!1mNoy?th zDXW1LItp>nGz2DEY9=HZ8klhw@1?dBEHF@lcvAy+h3BulL60hfZh)}ZlnI5DRMirS zezac`|8Xi)8YLE>58KQzPmoH4CV^0~TY0JtQtT7ll(LE-@c)({fBhzd*HCJTC**Sp z69_~gP=O+g3VD<=Bid2~V`-P6mqljY5@XQJZ47e2GlVB0?Oe$*H8YUa`& zh7QvovZ?TGmB9&q4JOqa!wRnQQH$w839SYdftYS=3ULl5Iis zk*#N=sD0T~GC?tDLaOWponR2b0W)zT!w~~&XPxq<7Cp!6VFR;ONl?m6rho)Bm)2P& z-hNUyci`@yc|FWFH^j@N5Rz-Ci(whUAdrHq9t5kUWZqH?Ox)QaKY^r-w9L z2~n{3D(9YwvyF^L2#fg`J%c`@zlD)Vc%yvwzxEk(K^z6(S|R}`)mZ@$4ca*lSMY5^ zl|+LD$xyNUz@9E2_OWJiGEHDrA8KZR7d!g0CAwdM#{*kSh|P1~z^lmyGs@yyV!I)AL_Ol)Ua!CA=I`K*tY}m5&;P)h8ELjk#iN9Aii5Q%8&rQ`nDA1l zc!55UIfPD%afU;CqM5P2e0eRhcZF3iJW|8kpDym;vl+v_c2*GcA)+y)G1s@xb<2B; zQ`dz`}}&pfE=?B(yd-gejVM>*gbn8{Csj!UcKcF!9l#*yOD`dGi~0H3ME2BU&=ruvb6jOpQy23C<+D~nUMCelNh?)8%#TwEWeZhKSC_6(sjTL5X63X?p z+zFx-Bh5yzYX-%@!_(eDzYrhWY#}$;MbJBu_b1$Yy(bmj;7!45<~yIJN(>a$3-f8% zMEwTC07Z_(6LJ(-A{$Z^9m+8Jn%1?&uzJpM7>FoGS{=aWp&YgmXEqPP6}}|nN`O4# zN1pbZOnb~^Fe>J=F?C{yFoZVd+mG~voWTu#!icJ9mm*eV5_~m1p<<9?VrO(>Y!PBa zswm~=Xg)fbRm%u6tS4I;F(~ZMo?L&ttQ{i_Y}0@?i!M_qazNDRProVto>ok$u@MbpUE^Yfwl)i)7le?SizwvOFi0P(omZL)?p&TL<$y?99pO8^rUVDUCj{I zjuoVy`-!79q(G9QR~k>njatrY1UY}mIqpqm(Gb%%AD4M`Os5g$aWxL6Js5EJU%nw$ zT{PJ7nG<+1GO{ef+_Ge1dX=|)>mf4-*5lhS&Vo()u>{`r)I!2wF}FJiY`1z(c`9%# zQE;?oPvV!Hh)bjOlDF9@?ZsUl+Z&X|vyRQH@0(roxg0M(ErqW}wmj$p>{>rCPq^Y25(>1F~Uh zg%=+|D0iQSu6*K+#HgMRDmyx#$+@kv>_<=cIoh1^bZyzMo_5|=R z<3Y4KU)xD{r+jwd?vy0b_07&Fd%nrrihQ!?t{X2+_Q@n$Tt3UmAQ|O+JpE+P@moIk z*(6-{%h#GME-$1=eq}G=vUC1jH-73^uU>il&Plylc;A)>PwEBCZ!PlW)8{r`Q<9+Y zhuwnO!Cf?~DC)I92LUX_0^@~5v!_C*>QRivQU+T_Mu*b-qpUG-TyFrg$Hm0zkN95N zG**CFe!&1}zwmbry7VBCG!`cKJ9Ra%Dw}EkQs+u1qy1;UdpO3h3B#)VEoW!F>V`Q? zt6j08N)rz43hQBgXN)e2<6wv{X7W`aL4K1vRdjETFmw^UC~UDi0fT~;1eg!lXm&il znWk-Nl%tkYb->837M6)igZatLu06RK=WvrhIf&Z>^>6yz2VRdMns^Ecbu=yrWV>jg z8i_3A_;?_<=!nU3s~H-5&sRhy7q47l3uoQupXLmC(G#hER4n$oxlz&p$7fx z-pDpikjIGSja-Jpj@JZXRsLES1~UcIc+5CCQ-yqs?j)i&#I{(tKr+m!59eD1AmR{P zhG8yiG{Wd29>Mln921REx*NYQ%VGn2No};#Cbj}aalu~)={)kjRyEwo#*WL2>z%sG zrQ&JSrlFV*1FT*~G!cy!m?GlH;nDRc9Q+0<@aUF8Pi*tyz{$X`-Hc0+Ke3+Rc5XN` zGd|wJ!+=3IjfL@v^^^8#9|s@xh;N=HiW<`yqj9N7p|MQ6e9*8Nv0iW7j8D&48u~FdR zCf}MwvByYlh?S9#BVKRKlrnI{@=&kVCb#{jy$IZJj-D9|hOwCo!^CeUazlK4?`GN# zQ8YdvxWInpTriHC6AYbl?5pAS6x({DFO+@1m)Uu%KghD^%t(FXKXb#azW3zV9RpML zO@Ujwt{!c4ouhtOxOqI_)!ROM#t(2y>_|B7bgQQjPLC)L!B#%5(f;U{tVY0mis!*V z#`{G?7?+J=U2%xeZPDdb_l9~jGal6Ir=56)&tn8LNcwoo=|vW1HsW8-M7=lE50t|Y zC*bCx7>POM9w_(LeIzgRTK0*`RPaGJ0*shU7Too#2VHY373I>Za>!ZVThISFD=*CQ1Lc@u@YL=Gn@JOki`(IyY@(xrBVJn(UuZ6M9ghsI^)O1tmDfmpw z3Qa*)yd68DLd+?!PE}fN{eay#aocQsK5x&rT5r2dl-P8>zd48K@o)asiZwQ8evDcxuFE zXasGI7{xxuIX#(=Tz8YdMKyxY3hnCin|)df6tF*xzHD*LAQR7|R8V)7Op67)oCyM8oW5hEn3{>-q^Qs*1Z`cq9EK zY`KY$MNTXQx!BCP1lD_CHqFpNyVy>aT%b~fl@K_U zGT+nU2|Ix*2KJdTfFoXryR6 zOJw97umgQYE5?uK+cMT+r?IDYt?l(EJLm%wq`^Zp-yJr)u&B&*So@RwaBHkfD$J<| zxD@YlTC>5YgskAi`iR&|-OormpjjClBd?^-U+SUH6FIWO1~C#zW^aCrWgSME6oH|~ z;`Y`T8X1_ZW>6hnCZ8J)(=dqv7_^xU|6bt=tK>-y(S7u**{lN#V2OzdY;wpb+c_|U z0l~zfjUskVanpYD2RR}tns(?W%wWay2rZbn9<`8&xU=U0jZHrjlAQ5*JDLHLA8Hm| zPSC|apO{r+olA=jJJIJe{@@m8z~ftPC$xtGpmvH4lrj%J^@axX6p+{g+(0RnCLtM0 zv!#&9rWE94SIl@;=#A8)P0ozPkj7aesBd{L;cGhBnep{u)kx?}H*gcXyT?jdc9j3u z=Oud*j4&XON_+yfz-AGP0Y!z1o7h!&Cc+5B-OM-~&oHC95o`^|$2_mdK(g(@+Sc`U zF9gB?ZB0al(uoLh z!`LmuOe#C$nVIS^n|yl1TsYHvLp=OgJQ_3gFcb>m$K1HD_SJarBL~U{9eX$%%!K|% z=I2dL^>gl>TQ{C|X8MkmAK4S#y7j2PKiFLxY&kRUIO6ukAkFdFi&S56g zeSTtRy_Xkfv}JUXNrurLY`EMW{GH0?t&_J6Y#o?l9^douMhvRc7`+vL@RIT!>-P^n z(sCZTf;he8yXK&c z9_|LGU$Qw5v%rc%J?1_--F^^8K2MnW(#NE{w3@ah_xG| zc$e?pT5nuDqidMx%BcUz)OCW%XZmBp&`WVJd>8 z)7}++Tsr%&o~ec~I*0!}T?_;5OHve~*cXI^71&F2Qo36^JK~dWr967Nl)-^V`~%+k zu!afR94pcysC_iZ^glh89g2@#1S%pG@x=4c`=#b+b4Tr%*@Dx@E+zs_A~ooLZeU;s zk7Or$w%v2pgo!QmdwiVs7#~Brs*mv5wr6m``F`xvW3_zS`5X!zrIdL3CwquV5O_FH ziVE>XM7}FTSb;`vW{XvczCGYY&XXU{$tOqO^^Mj; z?Mw>Tr4vFqJTrUGa;9U63=y4cjGkt7i-kQ5EfYs79V_o>!69{k-BZXb#&g=UCeBqV zE+1RkqR$HVA@*Ao`mqLRU@r{kOUC`#(lIo!7nzj^+q#=Af4LafDZe`+xWgZ6IJ6j3 z1ghviO~3X?h{Gg?pqLw@ry4DX{d362v=;{c7G^Qa#ezPz#hv(ICC4B?GYm6eoz?%v zkjX*wMZVwT3u;+$BldhgC=9OHde^^u~sB_B1 z+7KS>?|^KQ8`+_Xcb15mU?gPMTL=SaE&2Yhqlx-GoA;xb zhaRtKLOg9kZPxBUlsJlXv7bkj9Bh`ZJB`m7DUC7gRU^8e@qgJ~!iw25tV8kj>L~MM z#Ga}4kN#73{3V76`-K!JjENzQ3|sMOmYbO$nNNpu>{23}OZ+(wZ*|?T)ZiZLFDIs~ za3VJlME=ynE)Go)mV&Un*$;g;I#WAdt~SR;n+FMHVm<~rw}rhJ*zDmNXI|yUbNJN> zb|2{-UHPZ&yFZOEsI#pQLh9P?q(J=%OpHKA0^Sz3%bqA?^Aa}q-;Xm&A^~T<@iJi_s^+?6F!%IKJUeam1_f*V*tx&GnV%i_%2JC9ai_8|N##m;UKs~kr z6aU%I{?XE}Po*1%{O*rf{mG3}otKt6pTb(W18VmDsdNX_H6LB%Q_kNu0Ue@CU?VWJ z?XwCD#YCAp(IvitrF~TTD3;!Rdf}I~kLsL1aXY)0Hu!uL>#lxnsQQK9|MJtdr=l-z zO9M>*Gw_pN`1$C9ALseE4{j&cb>x<0Ti0E})2p8eO3=*zvh*S^Q9ZhUovdUAg)tEW zOhN5ojN*u%O2SSd100^pxYG_ezJx1#f$rr)Pve->d`-&pC-+3|leK%wyo!7WLz5Rk zC=tbzd&Y^t*k0c;qD=e~8cQF|$~q5y`VGmgNi&0zE17)Dg1%e|$lNn9CL3PR-gR#^ zF4oy95kxFhhP)|*hY}4D@d&D0^$t+bn+sS<8)0!xRxUdYhS)FevTnrVWcp~X!E6{z z#M#*G+lvbv^TQd9>_pD;Vjm@+3tI2-Co?S=Li}fDGGiJrwRg-qjD_PhGE>E~fA7&xH^(l`WM&!tx_85H)Ktfo`8=Rz3vE>hIT1{6E&5~Cc<#FGy@#6_@B_*7~ANM&M%W)<9{P8>(244ozR zZ-)2d*;`qIo+@YBfBnaW%SYofo;v$GT!fc5x{UaKrJji=wh{z!CgKcQE$nHbqh^A* zkqHV%ofd)6s5;}uTSD((1&3zx=~~gbd63g%acf|(RUt-n^BAwbOg+4Q{Fr^eU)<_T z{3Dn6Rh}NU`H>6lXld!Sm3WF(KxVrlE3&ocfAQ_r%II;07wbeA@#n1}T)y=LhT@6b zc(7G_NsE;X9$(Ok4^~2YaJYDLG@fa>(cpD;hLr8j*uz`g@u!1_D}4{FXWAYs2Lt|l z2Er3tXRaRWeQ>=!^Ug2WUbKHO8V^oy4X|_L{$T6n<98AY9ryOsVg>^ae#nblIACs` zcpfe(+k&>Yd|a^N5Wzb8`JKOXxEEJ1LQoI0gj{bHc~LxcFW25^k7j#%A_ANk1ofB>X61%<<9_SHq+p}+}=1Js)l`*bn~om-ttgU92| zl>>J5YhyEh?~Gf$Iq<^q+7!Bfs)n+#?P$|_Ho|RUpuQtd%xYsjH{cB)EAz(27T3G` zxt=ns=QAM=rMeawkWVg$ypgHq*#_u3^{>X+_qbO_dLz$yyj~lYN;_cVkwa7IVYX-$ zdRP&{i#=R%PgH#RC{vQb0)`wS3O3ebP=z>mB|AsC(rx?KZ8x?{Y^Jo3CG`@58Dni| zCS|Y&liKo(sBEVG(>h#%It2TN5_km>|sBuvXbrL7rWNfSkR23fC#r4 z&5?&MJXy;%qA|j3c;650e1lac5KAq%*)vpNC_^iwOwe4UGbnPCZ~?`1LNyb`2J1Sbwn@WjygJww$4Jzqq%Mtq}BU zp_N+!0bAaPb#sJgc{4L+FK5pnPSNQA@4jB)ZKX!b4SJ9Ao{e@dFydRGJ^b;qzddWQ z@h|qb=*OY7mtz36bf;U0$BHvI4jM3Y5gR!;6vEwek?U4sYmnP;M) z{d=FW3R$Q!P|d~YWY#c%6XGAtA7?0{)_Bnr0jAs}3J@wvce;(>rkVv2t{+ZRSly(< z3?knz+*{^(%UA4<|DjbX+w})ezGjmX!(&vnq(?JuOTxrcL=*L0CD=?$uHNBuqZ*B>d<#`0ah>$ZN6w%|`>UJ1eemG9l&REMiicv;=`E`BCcrZU)oY}9l68F&DBfg`u5$l|(h#3t= zFxwB;!*{M9%1`mKqRq$~WXVC}j}@BUa;6tme25+&8AEc}@J+C@#FSCW1axQ2GH{L+ zWBev`+F@6Fj$#v^wW_E1W-T8s4gBkPm)D-mYM$jY&DF{s6-ATi6N0m0Bg!)TZ(^5< z=`?E1fi$EmF^+ok_q{dq{`&hWyf4=?69kA(L@x7IYbxlGX!fqJ*IBkZ;qdAgZ-cq- zbcchRf?i@}v;tbUvboLT_8ZPf03pO6D4DStwiGNKzUbn;J z<-P}auWs_;%3%4av3ttnyrAUS16z9^ukQ(ZKj%E)c-i0!r}hMg9dAQr z(7ya51MhJCvFKqc3$|8zACH-cPLI~#Re#M}Z`yN`s5jeyZm0*rBbgzWAXjg`Mbt6G zyuB%Uq)cpLH(J4+IqZzonVBXkds+m{++nsgp~s7rfW@lb8E4Dshb!(Cj*VfycZ>;b zgTEtsdhDsO$Kt`t-m$^5?LJ<==%$+Y$UWsP{?vG_=jtfjzR%BHJvRK2%I;b?e24SM zofV>e-qe@s`zl|F_tZ92;{CzK=DKm-%NwXn+J0tmvop2XrD^+XS6=@5;awZ6A4Fej zW0Rs{yV=;J00;9haWeUq$BX-0EtK!h_)K%3yPmh`Cf2k6i38 zKVT~`*1ykX`^w%i_Da2foLHJdZrh275m4KrgNco4gOtA~Aoe!)^R5$jmv)aWDOWIc1wzVM$_9^CRt#c;N;?dof_PZ$3%VkgPRi!)x|9Yn^S`{Qfdj$JMv zbPu)6`%&R^v1OtGBG2756)2X)Yklmp(W^|O!;19uL?pq2)1zVEW6hvm`Hah(UhI$B z?6Sd1J6c$`8!HDed$XFvFOKm}ob6U%#0-JK^5~4;_lO&B_ntyhy$$P!lDJz)H0QbX zPC#5`=s3L=Ah|?zwmslxrZ3sASNgVjCa9;--qZTcQnB}V3Pp{_JAEPM$mt9C&4dXpyPeKu&`@}ROC%NuGlT6R}zVeu#tt$MnwLG zGlXfsP#lVhpU|tVfk^K*#_y^0!32Mk+w%K1yOG!b8D815roAZw9ef;qLVRIcn!&6t zV23nK9}S62=JnQDA0Mi}$_?8O|KdpHlKePtMj|CMe2S=t0NzXpPLVwlGA7vDL`V{v zY+fJcm3(6H3r2y4k_!@#pdWk-j)a+6)5$|yXw*VuCkI0uE z9@yZP6tQa~p(elSvG0#S-BpvL;nlUiJKSl{hwFsT2%X*UKgX_8jIC`Saffzc*fTTH zwGcjh{HhHUwf~Ty-LWEZz8yj4%nPp`vh5nL`bHL^$DJW&bWlYYiKPwYEELSC#$zE1 zMJ-}D1PooW2ywO=^tS}W+Qj$Yw`hN|?-8#ZyROL|v$#YAw5NYvj4Z}Ja!IFN&kP=5 z5pNqzLi^333frjqKVCfP9A{r1qW{=TkmslKg3>-#TwZt|;u)4*0@*R4O=y`4hUrFv zSp>OazP9m4h`i+T$yShK{UC=kN?cSQZ)YnQdj-)3r#yZvOkrvGP-Rh*Wr0S~eA|9x zxN)1yel%Mf@di$=*Eg-kud6eusZswwYi|P`$93I#Ru{_(Y|}Qn*g?t&B6mGhH;XNb zB$_-9g7Id$3a^0%*fc>H%i(Gmn`nbHqxeIDIX*gG&$_EoEjC7=`4OI3of*vp03k*v zJ8>BybdCfSnr^9eU9H zYKS3GC)E>y5C>U|KL_1B#ojRh=lM{oh)uLw#LX>|j&usN?pcZ)WY76=M#bgr%S3Fh zZ4;sGo1BB@t9Vs%`-*m;2#K*4>}phtCbTo5zkuW6Ez1eo_1O#s@(Y(Ufp>Y(CfMx7 zw=kLsp|P;-4gthrIpds$&cp&8%d({C0~;1}Xp|&SB8#I&u-P~>f+-xQTXa1rr~~r$ zsYEHY_?+`fXUSZ?WG71!+52@5j$^yicSoA>d&8Z z0{`pl*5ilsI1q%}!|qfeBL{@d*kfy z@Sy~z1R#9-#O;6o!G>75iK9@G9Z&pjqOk}M;)gjL?h0`-G5@iQ6W@cG$D1^8DKWU^ zCviXwB~3&iGWY(_AP&LZS7yJQhVV15_@_Qe8j;V$CHZ+TR{iadzENMxtduKV9UYes zHSm}urtCPrxOQ}(RbF!_+tW4drtG)}GfERSL122Cc>6XXW+e3oJ>bxF@Ctw zp@k@QrSE#>Y(@oD(}{lZ)&Cu^Y>6c^k557vlv6n##6c$jP>KUQgc9{)=~uhE7evX@ z#)6w#NbM6a6`!c#466aJXOB+;h7;87%{^S}>lG8_UT?D+vwkB|e zY@v{i6-A2l`C!odTO*}L03rpbFwzAw2r30#B`yRaRz9uVeunve}KRI|3?;ayM+_M?*v3dyjfujNz97h7a;x1yHlc-V) z0^_g0_5J`vVg5j)$Ld5cq$wPUGZ+zlRB<-jZJhqSI1sThhNnR27{+MKYc3Vx{Nblm zTdB6cBhy`tQvr|?wqj}XymD>dWVlZfiWJYE1*awS%VNJiPQkYkFkQ^;Ks4+^4LC_v zUxT_uqu)A1A&#Kil5{7kc@WlOL;(p;I*Hk@;50%W7w1l5{etTiwy%sp_`j6~Fin+k zXi?z{)U_JK)dl4Q6tkGxs7`kwEf0mS2W5@n=7UNc;9g{o zM_LO=$9mf5w5t%W^nAwN?z*Y!bTFd{b!ji0WwVUyuJjQh1&oW$4Olqfy|8KcK*f$u z28^91=~Ivm{d1&Dqd(ZM}?7NH#}fm|E23|L}4g#5LJ399UrjyJOB=pfN$mH2GN>FM;fNqxzt z=}w*Cd|*srBHnF%WX`q+7jOgJ8+{)nHtI+~N@ks{VRq@$7PXEo@GV?$!r+{G%8-am zi~s4UW^tjYaGY(>WV>CWPBb6HKJkP&)n|ypvW#6B+eZIDJHyW16-&UEEHEzgvu~_? zf@LAXt7$bQu@Z|4N1KRG$ssecX{XO(BM~T=F!c%{Tu-tK_~@QBPa8cJo_VaR zCKZhY(F!1b2{#_Ue#1Y{VhhVcB>fTdlx$}^Di#MJogJNi5LptJtN`PN{Q%fB3AK-S ztSQ?B!sR4yQZ!h@w+g?X_2`;KD6_$F@f9NY46e?mTfv&Jucgg_*19oDF)h!`QdL|a!fxN{n(6RZK0)hbyVGC4r2i~42{l9k0k7)M)! zgAg`P?4V%4NECv47@mZ%vYOdbAu=+XGCuPRXK5io=;(1lt0l!%S5u`pB{4{#LzK`c zSsiA+0GlABW<_WkHPR^j4x-_iKOiBL;229OyJ3=S|4XkhJ z%EaIN5F-FhA~$S;zE{Y~C(%?1)DaW?RchuS+fV=Venh zLC+WxWy)Cg5=z{|(`lKH1gVO6tnyqj0Bjb^;ei%5G>jjyD#RCL}L&zi`uml&v8PXK0i4~Y(JBYEA zh;1XOx?&YaBbd-GZD(tuqiC45hP@#y9MeR}lDXt(Zi4)7=tGHU=dXR3;4EemLzl03 zb~eE31@`Ch!t}CYSvKe&L$ik94+bGnoXVPWHf%0hqO~a)MH?ltZs7++6q^f4GzHx~(#U+j#%0`HqMs0+wO`7RL=3svW`J8+=tNgr zOnIrRnp`$aGbkWU{FU5vq_Jpo`S7N!tEL-9w9$~vkDP8wzIw7QK>FA?>w5h=?+;i= z!AayQc2j0grqlh2OpGQXzBS{ccaY4s-jx}fj)I=A5&m@;Z8MgddnE=IL!ZnOZp=QM zuwdk%km|vnzEM`szi*^Zc+Ls$I6Jd(ev0e*Y~rm6CmRLWAX+z*(Q6JhvbK{tHBkXG zJq!6_w1=c8qDN2=S@iIrdV&s@?p*qJyJEuRNsbJfUO+&(UG8dkvZ>+p6xrx7HK_s4 zuse{^?27fxrz?l!on+EF((_}4^{iNY1A)0uOl zWmnygj)^|=SHDmN@n-s_SWK7~_oCWt(70&~AE&3!n#YStz%mgQZU)W7d8c}qw=>{Q%n+IjYc+CE?U`qr$ zX#pXOcoi5Bjp4}Qb`GhIKu}T?&yUZ}gwQ zEMytvqp@mZfT;Alsy6!fm92;z=>T z!a>4TcbN(7HMMcp;?9tuJt?mS#+2>~xC!kf3}4<11jqfP+R`^LNRq2D#b zSbB^^VAo!bq#L$&0U?nTrJegp^E0(3dania#$U!xT-6!j0SOYMLKgZAbXTMRFc`>6 z7kSN&v4e2OH@-N@Tu3Y1R+jn`;-_4AYHN@OK1r=5YdGT#vHMa zHeTC=#G@Gix)a1Pnv1&&AymHNF^fFc)LAoYJ^?5g!E3MRv;}j+FAzQk^M*RyE2dg~ z4)|26eGPv^@>l0b@nzMWjG}T9IA?dC2d1P4@B=*oLbdAD>M}}_W;jv(O`0uRb-XyV z92l8;qDTyTlo^cAcm--@DFPCUc9lH?8B-vcoB?riL7f~<*+r9z-zeWI|DEQ~=g-zo2n~c0@@ts18E)BoUribe{CrzxuxSs5SQ9 zg}v{AU~l*vXc{QmI}e?F$2pIq#K=)D>>u7OGJZGG?%{_43ll7Dl*23k_ICEJUK@ID zHHowveDm!Hxw{zFaB}SAPZb-xckJX1LgdsFgxpCx1&*OC4Bsn#_RHQzq}@BZa~G7` z$SQsB@IkUllX$(2-uO>%6fK(^7l4o>FIT*s`+uRqx-kM-J@UeL#fHSD1sRdg#C?mf z6UB4Dpu`@-UlD`%T`#`b_)tKWMk*U&%y-4U@#*>GvaGbY(XRYJax_+^{KPBX`0qX6 zwHWw@+W1a>G`{~0>;5<(l{_d_yRaLp#6*MGRJv!{o%yp4Km++@^Gh}{5W3y&u3A-K zuXa!0s}*WZ^tF4|`i8OoVuwH@wj)2$$9|O2j+)+CpO7j&h~-xW*oxY|(|)1dcc!oE zrv2&0sSK<;Cb~%LzOMEeuN$0Yjg4^%1h>vQJ!=k7Mi8If)16Xto4W6m_t(=?!IIII zL9_MTMXU_IZp_9Z`|0F~9pE?WRBJIw2?k(6^t(8+q{}Rzry^87u3x2+*`7vlv#b;) zZ>s(#!|C8JNcpiOT5imopKf3!6XG|(sX}<Qu4M>tx!MPD0O(@$0pi=n8ICbLiKZdcDwRE(d4wpGEFoq8e8#|m z0Zt=iLR=I?P{iYGOW12BSV(D#q2Ot><2vCbxV*&cVcO$6=qR2`5l({fLEcG}?~33F z!X!#@D!}*aips|W!DXUSjEhQ;4h(8T*fYMsTn1hYg%p1Hi@Q8Hs6!9%-|+VXQla>O zhj|kFX3$CA#Iu*(IYQFRYi4#jlsOz;hNGMyQUL*(?9@KLJ!(W|3A3EZVq)>(&|pYX zSb-oH{A;M%HHS9pGQRIwO+25HrNLAsB#Q}-pi$W*8?Jlv_7wJTEXl_UDe>GF0PvhY zivt|tSjP(}`t$y-?dT*MOxRT5tU=a3?~x94C*u#(3lgv+eTI-x0A><{KqFXNymw>q z+dj64m&y|0gUh@B!4FZxp1H@H0+}H0z0wRac=fSDg!zh(My4lmxP`Sjmd_NR5Sx@aL*DZ2Ox1I!tsizh***~FaQJ$5J@KfEaI)6 z_Hfj{?`|^4_5~mViN}S7H?kzUQj#ZPp>Z9Hrc1{Hoq?ZcGWZil42*?)ES`4BI@4#s zfrM!4IKr*<@nmS6cyz(NkczRSgi{_63lAD(%`1bTsl{v&C*f@Us-9-D$J7End@ zEiCSyz#|4rF`9AO#~IeZTC#&VpSB1zk~BQ-;{|pACs<&GNC?53rN1#ADtLs=nF6gK z#n`*eDEi0$ja*NMWBH$#{Lh9KJjsu|*|BDk5RBW!+5!mCBy`!n8-mhU0KWM6*kocW zV7J<(nC&l--^A6_fi7)m%^Tr~cl!QSvan%r9uNqv>#m!^c%ip*lHoO+o0Kj6nSiROgLX_hTMfl*W}qNu9OY^r?(Qfr2q;+Z(zfUj2ud1nh#!}=(iyDg^ zM1o~k}>lJ@Q!-Gm?@0J6)@(L8`!(~=4* z8>>@>E*vk#zL2`qczzTS2i17VvyBpfn=mLgu?TuFC{RJTm>2Sv-59`Sb)?}CQV16@ zrNd+aWX(8|ikwIyF}m5)kjq&q+*c0>mSqI?`5*rcIVUawTjhJ9A56y;ZYtnLI!i!2 zyBKadPRYR&3*nPK>O*s#p?J&MEGrVjX_Y7RSOTF7@w2Io=48oxIrxirWHZ5OZRR?13D4#x5;Z^3 z_rgGCc%ZL`nC=%|siX+Pu9DF^+GzK5w!bv%pZB7k=lr0LLKg&GtFeANzM45X96aF` z(#ON$z@rY}*fjlPKaK)lZj@rWB8(x~xJ1O0T{_3#z;~x3+=BS)r#=W%ZMYRM7xO4l zpVG|~e~CUc79J&vCdMrh=VRjy%;7HNMUU}S+7dF-O5)7!1)E91`7vecF{LEI6BoRt zY5@)|QEc_;AOKuTxDz)edgs3@Bnn=^mE3Zv|Gx56hZ@)SVz8(l?}r$r6^h4`%@oIr z>CyR^z%s&~1*^K>d9l3_u_liEsr;>U^r;0tkQ!f7lnXz3u8YgRo5s~dmibQkRn-xxS+_|vKOV@^>k!{JAt!3YyS_9 zKn8-ERei$4TF*Mf$WSUCq4eSbqDTl3k+%ijlJqf_OdR7-(s`=)^-4{pm)p4f3GQ%U z4b%rjka!m01E34%68TK|2KQKxaZ0CDP^Euk>s#RNLpIbCIv-^o=v-edQmES=bt9GfCfP+qPE0_MR(sY+xGPl zbJ9W%CkP2(6VpM285kK6enaNjb5qU?YhGPih=X zm-~pW+88eH2>6Y}JAjYd&#`-eq#|~RI`}OEip6xPxdHF7_f=0B^F%R8@EhrraE;JP zfKHrpa0O^;6x0BrGDEY-)3SA>fp{;k@YI6DqcM3fS;!1=6$cSXGp1x?o4Yd>(t605|mwh!!J1i`_ zIxFEn#GS>9{k}{o6v@YpB%`?ZK&*zo4B|jww5Up!9Ev3c$puPb27u!>ilxCK3#n&6 z`GF(|?GSxpHHtVC;VVEY-~ae3b6AJlQ2Bd zy10k8k3S}l<~M*NKG{Z4ZCB~FmSk0;YZe%!tgT8kEJfYEpk*7mj+xb9JkDMo6t8v- zg0q!Vc09J6=KQu^m#{QNJ$nV!8Ip|t?ZyoQ_(dK_Y1hC0on&{44L6Xy$c&SU@J)+g zWzl!^g={=JOHD28%kDo5#cgXo*{Z(+q+1+20B5iwCtAY?^y_nBHCjq{!;E^{ifarj z^O_W;C}}E!X>>5CmXG(*IupVHl4Y3{-h>%m8$}xuQh<^th9@Enr~Ao}j|3z_y>DcQ z2#N%9CLFXamY`t)f3oQo5mkY|0Eb+~JRJr=A`GkHrYK&2-pitSupN3fi>RjosZmd$ z1)*nnuoCQ5mw*bQWdSa+vv={Sd~_O|5JAnsJDZ$?xuQ%<8S=)eJN&Spz8Qc`7qz-wMuod8rc=HQ9{&YygfkZ`vQvw9IxClXqeSEM-c% z5|ece^AdIv%P%!Q9i3tOt(78D2ELt+RQ5ph^2PVz4Lr@MR8+4LA27mF=ytH_p`A!0 zDvM#ZunAa+JHe?vS+j>?B{Pv377l<#liOo?9 z3l{$hVI{#n_>EmSY``Rrk_`kx9bWzt-U&OWL5YY6M6JwXB>U1q1ZImDD}-g8vu#Kn zj0{vD6pBJ*(UP5=YkZch#_qnDl30`s>dyEk&tjEfB-!29oJh{x+LfHRW?*wi;{UVa zjz{%WsYN2-?T7wD*2J504WFlC0>=?kVfWgJcMzE}=ek6!ErO%lQsUr5rA%Dx!}qAp z`m#ITrCu=SOv+oi$|uZ%1`Olc9yWI@gtjO99KsPWpj7e2#kNYDe_Z*18yl#>3_J*x zvnjcRmyla{jem#|Ts}>Gtdg0vam(jTO!Ti~)Y+Uca6V%#K1(-~h~rj20NorNx4lxPqrg<0 zd?(W#oAFEMyldu>(C91_J)f+I9c=$l!^Y8PDpi(}kqui>DzZc1k9rD10?{W3AE1I`y>I}TAIH}M-NBX~)+g8- zCrF(I;It+y3vGM=I>2dwwkEsuNhk5EEdebk3x<`)emK6ePyM%P<`v~`7cq~h$MC%m z8!nn$R%k38uwg&in0*T_fvXvqr zhrB==MO=`87VO{tKEYygz-BVF+`?77%PYxd({V&aJ5IqW`2;~m%s9>_wt3Iz1^NO% z3Sb8qwQCn}63g^1JHYyuL`*_pL>HW4OPF31{mozdfR>r0`MWYsIzJCTVv_KDZN&kh zQ2Iz9NC;il^(EwuW;WW8XEZ{H7=tB^fup)DnT(6~SSwfb?j^T2Eu*~g$ zaTL0+PIxM>yDjq{W<|2frc&XdBew?)bt~Z!~#|nxhPttS`Z2__cM7~JnM(q!qtbGLz5-6#fXCRgh zLUgqC(%C+FP6IDw<0Zt7jryJMJt_ac`z6p20Icv0Y{J^|+>OD)mC>1uJuJT^n2yW` zohezw{w3p(h7$V91;9*Smk)mCmCz2359HY}cRgeciTG3kP|{qT?ZbTnC?sqTGNj2j z69$zR8T3Nc+ZVnkzeVzvyyBnyD7``i*upbBM&~Uf$fIRw(dhQ!x=8$}b310&6F|6(Y&q^1gA802r)7q2R!=TJbf~tb^!KW!Cp%o|t z@MSZrJYh8H7-LH6c}dF*MyPXp=u=|)Cyh&2rJMXSWG%xPV8DS6sJB(ETAk8k84*lz z+yNfnwSAv|$|G%h(A(?g2fcheS!uVKmP3`!ON}rSzfysrsqoOn!;p%V!VyMNC)edMD~My#Y>(;OC&Dn6?r}oGjEr zDofrBiKM2+(jFp`_W5e;vX}lu=B0i!j@#XvaX;hWr300d5_c)4uVJ7xc`mXslPs*$ z|MvZ@822Zj_K%2>yFL-WFm-%EXe(@%Apm3zV1@i4oJ#T804_Rhe~!@#Msl|z)__XB zI`2V>F}0lL3pT8zVlQ&>Cl%0@bH9(rl)`MlF*fH$TczaF`%Eq8jpNhioNnrPvS zq}}AWc~1`EGmIBoS7d_3m8N$`!^~ilVw(?3fDrEaHNJ1Qy0jF`Df?uA1*9e6Ne|6U zM#Eubuc!(C#m)|I+r{+iAw4v^&{gf?Ih=17OOYx{-8T=-OCBCMN<+iS+9qX_?2W?b zl)5R{oV|8BVxQ?NhnOAiglTZ?#FeH${71hDSVe;{X92lEgtZ6~B7qBnI^Z(nJeOiq zXZz3f1w(F#`wJ4e8aEme>$64ji~?yAKtj}Bq(D11`9qrwPz9WD{8&j;GVw!C!9`yx ze9+(w_ymg)7jvTv34vr$@}le!#jzzCNs_*xTDgy89T69#2sslSB!MzkTMbFHkrWG1 z2g6vEXdE13Idu)UA1_*>I;3hiU;_(F{O4zPeke<+hI=HCX9?%L{f=;Dz5%jQTmxkQ zXGji{2gltjE@%bPLgH%@Ea-``YAGpQB~ectx+wIH%aW*krx5A?>!Hh6W!c|Hr63K}R>M1SdxHsBbOw$-4EHD+T=1c$R!&qjr z(ejR`;nMRMj6GUK?vx|NE+F~1aViLm7IXpzw|4kZfP+*AlrTCHkF+zqZ(=QQBFb06 zy%<)O^8#UjT^XN}0aC&WS0u(f<;e*(|JCVt4il__{v{9I7<@@bX4B$67HymihDD(h zkb#&<(#0Yw9c=SdDr@p>A2^9svaUb{Mhc~p`|gpgbZ6`T^z*Af-E-vMRsBhVK>m}J z#osHId>J;C=_YMQ*%WN>!#t+ zA|Mps+bUL(hI8Z_T$Os#17^@NjtD@0_f^^WpC^WqJdPhCPTZl>_U*LdCyriNQCHIow{Z)9eIgt&4Csl6fV*cj$&xg(1N<@0*# zh#T^hdmn525Bom^RHuRBjBa-_t&Eb=%QJGt-WE+JAye5D_wt=>c%e6rfV=l)7wx{| zzRRIy?24a_#jd6^^4&zFev$5Q-)HaL$2w<)W-op3gUNtlANr04O;{vhhvaivELj8( z-$WaYg$cl&hmOQJ=s15AjoARt}Ddjr1?sn7yT%_kbppWmmkv z;@GCk1+>E+SKR%myQJW%5$U`!{8s!p?2CC`viO?b$k)W3B=?*0eN0CWt;yY6h&+|n zAxm<%FRgcl;w9n1-d5k1jtjTTgg^p*xkq<~QMdWDJCuptMVmi!t$ydHep+#jH1YPw zxBu!-Wu4X`NJg9pPgeXDX-WRUOeGmt>6|?F9VY0;#lBp8T>#W~wehUbptA2?Bd2FS z#BL#t;YgHTNiWmhb@d$AcvobkJc%povh&$|=eI^Rp_1${ZhV{h6<2!rVEBNRF24KL ziqD%8$KC- z{F1rmsoYFAX46akj-7rW{IwJA8@1r0DqPoV zkB_|3iRoATpSa~&bw12ruEiTS{P>@Kq+}kcK{Oo>3M5D|1a_DKl+`Xc$ushK%LqKy zS9emc@@Kv(C3lUz>n`Jnl355@!CCdznv|Z)T6tyt&Pd7|Ia`B(!{dxt!33@2CZ}H;v2V53=IPrs;1qxWMn{&F!9KfwKFuH$8SKGr+#i z+>(lVm$m?@C?D*N(3|~XND8NB6HkLoRVhlnFGFmDz1W{!9^ks66c-tVNnHr1VD+q* zvAFJjxhhIIxBut+g>88jR~2rk&|X&CC+XgUYEk7Tl{cYerHQz4dR@jrTXc!^9N%zD z$*SS2-lc(JK}FJSfSPQ>-s9!vDa3G1>7cB6Fu@gc#xAHOg)``9O+WA5&>)}M5==sR zpWzy(_fEWxw||B$ybGQQ$HeDPSlHnLaiQrxKqGW+_vKAUmKL+ZWr>c_Fh zCR$e{;yQan6_v5QsN9{3igA;*oHdi{2~FBh=9O_Tx{JHjVBYi~;0|wxm;Z`)aAqbq za&X04Jyh*953e~3AgWJLFRkZC(FHf|rJQZO-}He(kAyqCQii9O6FxMmujq}*?(L73 zx71UG{)^tjYQ-C0sf{&OLLG*c@#lz>q{HPyx;=J@6F$L0fBf=h{1T^YUf3wxxS?w5 z3~X3GC!A>8)=@iS!|7B3VLF&MwOphwbkTpHKWF+om3;%54zC1dvXe&azP`SvGB2H# z!$fyE^Tk0mzdTT+G#8v=RA)VU%aWnPC9Pl8ujq(m-fRSO`a}J&!o?u;EA)3as9KZbJ?kHbGmQw8J%zK>O|I6dlc(*OhJNOj&eBHeo_$-zhBh4=uZP zv5q2LR-<9TCdz>wa=J+hz{X`uZXxP-FStW1<#DEFWu!2r$FAz}J$mFh9d~rd?vdV; zk%#`_H$MOba;Vjfq%5#dWub3dSIj7^P?%IM>x_@+fh>C=W??S6uzQzXI;RRuyhv5V zE7GzgS0xJ&HE+Y6NS)n7n;5!q>Rwfyly$;}5CTW*eVIfKCeqRvx`4PGVAhXS#+PTt zkLkrQ)YTbX89$+|AYj7~G0p4WCGx2W_T%#^6jlBPv)xZ`YgEvJpdRCQu|zbtvqWZtA8VzQh@3{;vVMHQ9ApnvQ=1ch;9IuC& z=e(lV%~PQ%Nb(r*I1Jl`Nt8(4rDEZIkW~A%hhNnVmfcuK^D9gMqd-vBvSEDZ7n0eJ zPx*CppPFPU{r*`9YRaO5Qf|&h+`c{igY{@`X-naf{aJ>?8uI!t!(cTCi@K7oio8x% zNL^Im7PwBF6C}DZ`@ih7mSo8nn0{j?B)F`2wDe*t&*qPCpg@=~X(Qq!40qk#VqaA|A-lF64` zWvj*X5L5rVL708Ku`)B9@s@Q^*$Y7{p=>cE{F!oIKfP&V+M8^B!|^*<_N?Ov`IA$! zKv+j&&_l`Or3MSp(!gNvr<9*-2vb~9c{IJpB^ZrNByv+YbN7(Di7gqCoUfOu)>DMzBazb{oVZoF4=UevJvt~|lmb{Bnz^WYFKmH4 zc9un{w7&y=%p}vrvRF(LdNh#h`hAYNxiB!~&MoU2i(RQoII6=>>R@a}i_uiJw1g6DgRj&nuT+$o*haD`@F4T?jR~WGg%{g2`geughFH%=9ZP15d&ht`1#AC ziN-L+YF;k9uX*T?JCTG{-|rBeeoCo>uU)*5!9P!$FhYwC5@2AUpG zdR6Iudon*0cpgrH$mc5MHDOX@Q*>dVaH%-0>gzB^|9Y(!vf?IH?qJwi$@Nw$hdZbG zINCb%-Eob ztiHW^cqSf>_2FtKp1;%=UCOY{-)uelzp{G-Zizu{!ljLMR8M#ni&^K6)yiSU3_OFG zJfBHKP`|8yg@(GS^5Hr>9nOTg$zx?0CU>Z@)NW6-4E=g^$+?4NHSqDupg*L{gfEm| zwQq%L5`#S;CR5>W4He_+K6tG2 zbXalv4p$-YQu^iSQKqpgKFxY7V%A{JD>}R$(p?FXqZp2knFq02QxM88qzZF+tEPPT zcb`|OKF5GMdgOR#R8tr^F2ChuFao8{ffN7u;`=G7#q>2v9-vu&yE1oR+b5c92RiX+ z7)~84iw^)>Ad_4ZyQ+8YJHFBf!bm3;> zDreT)BFp+W@e~eC(!*4BhNE#q=)JW!Jq)eMoG}Lz7FsHgH&#ZDkB`jgeR@=n-_r4U zJx9smOtnhM;7(te-|P`9H(A5*v>ZvF z;^>pY91-D#oBh)WTr4hF!{1+<&2to3_)vjx5vyFaVwQ@t=0D=M8W+;6vZC-vp%w;X zwNOiVi$o{#7sfTgr=1$bs z!F=i9AGO`MdH7lzZy~e4eW}kSAL6yvcl@jV9MeSi-8sC!s~)mW1-c{)vb%#Wmi35= z8N@%MLUQlYmy6>U_2NiDdCz$t_r|eq_En>W6P3ej?anFZ<=~ahB`0``7?$UqJH!9d z2v&t>L@U#PC=q1aR{mgK%d%6WA|}d{$0ih#=gNleucvx9siEk?mckvoxK(Xa4SQCt zhv6-yLi?c3eR7;OqvkacD$afu6gBJ^i8)6HMS=@^z8;3!3t6NR77_$wH-n`#d>^F- z{l$KVt9qA4$5&?RIBb8Qi(WZ?Q!^Fu_=!qob5mcFj@-lzmr*=@lh_`C3%by*YF&l* zjLHYSLNU((G6=?;8Hn^v@Br?sH#YGQdH=1mLq!8MMf!g#mnEK zZIO#m9{wK<%Fku6rm#BeV#TL>`!CEqyfUN4FXo5O&+O2Z5${&#)z+JpYV&XfhqnAo z`ZgKZu>E7NZ4SzPbpCp)p~T<7HbAeehV>^xP6zfE4>!Nld23k{aw? zQajx*;~x3jW|4tA^7#>4WYf4ltlL4H;5w(N96uL*#|a00QRf$SE07PRbpc*Tj6AFo zM$!9<7IoxcU7MWMCPvH>F8+vLxQMVBIp?8}_Udu{R;6+>9yz?WT6ry|KD7iTwdT{0 zoucrTh#i7vSj7G=l?z#!g{xvsHb5QJL^$Ju_$L4hp-+ejMbeG)z!n$zx{gr@L2u+| z^OGZb;_=)=#JR}~pKv;vp68vjxc&2p{AY?oLfkFvA@PvCMC2rjNemZ;k{GFpBH?US z8S0jyr-S2R?cv9NIPwSHq<&az>MPZ8=HO(!S~=WWxa7PNv#2C3<%O=&VT4>)B+8_2 zZdKc{HAI~IpBJ7l_w-C+(um2iVZ=m@C7Vp0!nzxZ^Tk51L>2}n7 zRVZ`~)jAhE<~Yv}s>}ZJ03yg0XWbOfiC|a>TF1JF{c-9sv6uUOzt;r;K)+rb5#z9^ z_lF&%{>TaarmoK4VyNvV$2dm&ocSm^OUa)vUHs4leTVTm?#VWH(e2!2WuNnA`a^pv z%%Nu`Z=GEgtb+Q|?!;+iJpjfe2*=nPUVgMz21S}!_6V7aG4Fz4?m+7_vH|ADK5;?w zC~b{oBNib6)U==%h#VuppoQU=Wn_zP!GrNHj;Q0G)FbgREl|LC=0}}9l`>s!PE|F~ zDd^DB;nGyhJ_1b7dV*ADXn z?{yjDQIzb#W7B2l;9qni<5cE!K$WY#WIt9~H~1qa7!J6*iHU_7Z)mJ?lPDumv~*wK z%KakwQ*{7&C*iNrN+IuEJa&BivUlHJEhhQ()~$|*Dc1eX^gaYJ`D$pcZ~dAaQ$Eq6 z)RXv4k0|p2-jLsz(;r8w%m8x9V-PsKco2R;HRhIgtNV)>Hh8sSA?#4uVtyK@(RaHY zP7<-7NR!_i(6Rc;}ZzwomtD-~hw#yy@GM70x zauisYc`avd1#L_ylvIjffuZPf@lz^Cr`>Me3SmuoGr91P!V-x~a*P4-d@@6#ob2BI zIb<2$iY5RSPGRK)oLnhV@t7xRUWYxOM3X+`T(_->;hOBA)euBpD?>P_A6eD3cM z*d|I9E~i_{zoK$QrhbQV)wU4Tl=l#gBFeNSSk$78sE!1702e#QA{B7S%O4DLQ!4jR zVWm?(yhgpJcuPzuG!cIgb5KB^iy?n_hUOb!X{n_f&_8?NVYs(-&`BV_k)f_0Zmf zD#Zaj2qI?c2_P&D%@f3{PG#F=+j9lEvrRReKqnKmV0H31k*gJdAoF5G8o0eMF!)6A z32bJx5e$weQvh-x@(A&Ybp(bt6O0D*TCkoAxOH6WEqM>G=;PTH@A&W!K}gi$0F5${s@jc>rA8x%+VFS9G;gJykiW!_~ua(D`n<`#i@gA8391zm@ny zI1VbqrQlB3>*7D}K+2+`CpFd-6k+LOVPjuoeqdrRs{XL3`j^!<)4*g$_vR)^rH$KI z7wi@iN4n5hRvb`)u9qE=!c{L&9K`^O!Oqf_MMNp%sDp=R=zYLmw#nSdLT8H_L5hKu z-l^96?+}b5JbYC>2&|857aTn}lKb>CZq#0NHkb8bag^ImevLIH_bhG!gk;{Xdet`o zu(8fjcxVA}?ds7c79V;S%cu8g#9m>=+cmRq=2&Kr9@XUqKz&M29@bDeh>#o4PkpFt zp=Idz6Do=XK5>sIR7Y-B{e5qrnkj?oX|OO0=XO7qGj1gYB+ux*Q?$4C_q)4Q4p+Z% z<5;L|Q|HD%S*14b|CPzy--m~LmXd03`F_myk959>hD0FYX~D>BDT(Id{ExfM)|bI% zdguC=W_p)p^CT=Z_Gmzz4obk858nFr2~eBZ$9=i%1Kr{Z z;f1<6p7FWxsEyvsgr;nHIGmh|bM7v|po)a}9jX_Hq6epclKIgfXh$c#+(XN`5m3FU z>H3Zn$wu_MpSs;xD6 z=HN(>yARV5^GCF>JSutG@)m9iC)M^lMON;*T30tTM#|P2VAkY%^U&{+sgQY!mCHCT z@no5EUFRF*#^w7*<=ytt^}_GN+uNAXq;jarw2e^t-hWTs*HwHmLn%ni;`DB#0~_l~gi0PsJ#}n)rX1eK;)*Y2 zWXh9)q>EyRx)%`QHltwd{c=m*1O1!`kA8Z^jhduj{)zJ^;7oWJ5vT4v=KQE}$yrVp zi$qow7|0cY5iLW+m2pP)0D!E4!Ha`MX1u?EjqYPAs&IHjc3qg3N*qq;c=gZ3wvle! zjFzZgaQfq$nO0W4h}#DK5atltKX)U%>S3$c?6#r#Ed%kuWeO=H%F5WmGG{x<4rfA* z_MG@((CKhyO|uUxk+Tz8k$mIF*@QWyBb0nqydM(Rf9oUKFi`Cq4|P4*ymVQa>;u{`0*{^%&V&kpttRjnI?>xE za54T;qgETO&6IoaI-3XA2>Avz!~Kk-(~VhQHoqAN%R>t4t~e zH@1k@7Fxkdwlw6qyVQ1i2_Ia|m*32j7(D46HOW|%@zW6wdFVRQIL&MWSJkl*vP{Z; zTufxOC@S8>T7{@c1g56G9F8js2lLpQGv3%&ys5-Y9e%ZysT@uqt#-iZqxh2%0#rHy z+X}nRD!UPeH5Q-l$Jv_E-n2I(co~$1uJU|=LVdKQ!k?@b)i7`&@LP@$YdBRp5H*o` zJ7n`8=(G-xV()rbj50Tv9pcY3ZrrB^tI?{c@%%CE`(tRz(YP|Nox^cECKi+gz2Eu% zhatbvQvBW{;XYW82j|hL{G1WvOkC!YTPBFG)MOUff~zU)_XiY7OH*TxW^rEn7C7c!XCh7n&DmJs%&)8Z<^5*KC9 zdYP@j_zh22_G>o#^-CuznsbB>w^o^BLeswgryohihI#B8#89~2wq@0SLt&}Rgos+> z=wyvq+K}%+xOf1&RR5&vm(k=*q)aWG(MKm&Rwtj)o#tjlQ>QFT{FKkRtP$QND;!%; z?91WM0`rr#o@jjeie=QW#`71C6&lAzMrJ}mS#R+tv!=riWje31ZU~Y5_P_2*dI^(@ zDDAf!iJsctD2gjr);*K?AZH6ZaXo}@V8Rs4Jfcci!}s{f!-S~mTR%9o++IDj)|^^v zmmMaHva?6#@1Ta#|tYn#Dx@rY4$C*P5 zorzA+%uFp{G(_M2jU?rh?=jTK8SNI3sRq>N1y&2a<&x5wpM-~|CD^v}H0o=P` zv+q=4$TB||x?cC;1$28mX7N;>6n&`RWoRav5vvGENlQXW{>Xw5U!kt@@yanj3;ZQ+ z1j#z}pYC%7^Gf6rkps6=dezIj$A*L;W&atkO4llGP~F0@jc< z7i;4l7+2xq$cT4CPs%1Rb}pXh2$hCGrfCp=?e^Cs!iUkKB#tnJU@Ewri0r-UOX1{9 z`Jg^J<#iKTA#)Bfmm#Gx&m<_YxIWv~6(&3?AY`dCvTpWS0upw*=Iv)-$SiEE{71Z7 zAz?L$G7HDvqOY>X`DU?ZRAl8;|9}qS8IOVE>StLvRlzx`RyQJ}`POewiiAm4AkW^4 zA1}MVp}7Mi(Q}W6Q|$K1jy8?(<1z@i6_iP~SuJrtJ@UE?uSh=CXjAcb^^y>;pqbpxsN}-;?>Hx!j+Lx*>fAtv`!#D+s(eim2yTRD_%djS!UN~dXaa& zyHx=49rVPmvHPc3D4sW+8?o4!7?!vxT-FONQ66}I>HaSl*WKMk54SnbYLIi@?99|R zpSDSe4ccws+7`&&$%e=@c!Ah1J$x006`$H-*2?-kKn5Gw*h`E3y=uuF%DYdGVgg=7 z^2-i(^%k7lIT?p|5xVd2HPN=M2u=5AuSj^iEO6g=1eO3P@ph=suLF^UM}Zx5X$0BQ z$w=Co93aOw<+8m)IrtdZB}`FG&uk5mXI}2pji(RO`qUaGcqfkHIBu@_b8vedN@q#; zoe9wqBK6VuC27=<3{r_NquqLZ-|@<^H?=o5smDF^$79tsHZ_CQsf98QPdh3(Z>@g4 zJFz)LWcu3??nt0>Y8$J(Hd!m1?$Jr0%%Id^oBVA9mF*?sjUE{2eFd_>%i{ZDX@9OZ z?cpwbGxzCgJ4SZ5DRqK=T|)^fNWuFR4+M7DG!U-52ol)vbj09X?k|Ayvqy1Za_H%S zuQpa{58oPjRo~E;X9T_6ug~ij5)_t7X5~Yj=2T~uq{;YWpZP#p`Y*~*8F^?8kRaMI zZ{{+YjOns$Hi95F;_iw9z(z0FIkq=p4e(UPcd$mc!>14ZF(t;Dn^zra8@#J z97ry3H_PR3ehr}`emUj_{K5Vv3)4nN{T9S5Pu08<&Qc)2x9rLY*$3(on^)$8MQ5A2 z9er_I?>JqzfBB<{(m;@zEJ61=LKaxBkmzCWsJ<^} zmaNwUmsZ86Bp$4v4Y4=aqH-TdKhVDuxx=!>IcJBzHa(5SyYlp*1**BNb~Sb8a7z@^ z8DFR^K(|t}9#tR$2?s;)mAvT$*|7;b5zNZ{-E!|mV%=)PBYV6``Gh{92leUr1P3rd ziM3U$43VSwW&iyfGCi3^7uWF|Hn%xuf5n>|nVBHm0pUVW9)AXh7>{4L(4SM$f3RVH z5qIaj&(-oQ!YOb12Y8R{?@YDY?T*+C(ZXaaN`k(`I^aCM(Gb)Y4TCHyQ(`BZLLZY1 zP?-&VBC^J7;PEpsF$mON?8We8hoLt$rBRUij`LRE?~4W!g~zn9^Sa&KE`H29=HO>1 z^Da?W`58Kki1CQMkyw!a!m^v6RRHqtvf7S~enZdZzoNi2?eOr*)1Ss9LDIF$hZb1n zYkqSOBNKfOG%Vs7x?(*fki&4wu#tYf7&!SRz`I%7;rV0vnjV`%>z%3yU8kz?>XfWG ztnkWP?bif!6J2SlEG8qKOd|H?g13Frq$A_2o_{Et* zQ3n`0`*i88YGvdTnhm82$`Ah#QT)fxh`A*k#T_^)vPaW@4teZ9m_KS;Zn=j&dCp+D zyT>H^lEuN^n*`VHbX_sVcfyKlGJjN$9K4#F{EJm4Y$8TS;Mtv`WR99cE5ftLVpDSf zscnhN1=rEpeMBoK;VZb_U_As&UD$%8lQ6xNW8?Nr`0y=lg+}FM+|--37>`DDy7pmV zqq=Zo-DJg>+p%IE;151kUSm__#II#YVjUT_8XT&*_V(SytY~x=*(ma3q-;hj8ltji z7{CC?oHe|L{PRAo!eL@6u7^dhdN=+NKZg+s_xZ|ZArSoNKC}Yb@$gC>=lld*8+3oI za-w>u({4`10hl4G^Y-lb#6c1%g9h!FeJ{5lP|brFi1x^2?I@<#K_$Tzggl6-OfT9) zNS?Wy{g>=Jw(UKDqodX_W~brtqx#@_^N@fPQeQn_Eb;nJ=IQ`;t?33eS$~66@0s! zeI)8>EMR5{XRIsMkysXaneb)x1(+3Ot&U2(8B-}BqUk$z_N+yUfJ>od#zZkrls|mQ&;Z(f{5A6vhN3ZttZy8-gpWy~kd19?XJ!X$mg<@r02oCiwAA2~)0V;b9 z3Dc;~#L@T+lBNn#XfFumNYg3J<{m+yFN;7*1!WedI#VTKVW z0k0Pb*m8&Z&$3;eTSodaKj9AV^VseB=t13CS(0s65fGa5E&!08;i!(QRPnSG!8{lc zbX*1dJUljpFmfUwI%qG4zz|?kPhqbt*+T>~_AUiqT@FT9tlTc!}r2&hd2r0_9LN$ zngB0d*VBX94!)D~xd~J%2;xnWuv__vqA2Cl~hO z_y*16L3uC}+da>?z32QP7Yv-~;vGjI3xojopuHu^XHTY#=3+_-;?dSQ~ z4ZNJV>L9`hSVE)-yFfqg#t(3NYyIx8s{#w=0rmMC`o_qt${bW~`Ju;`#Ek4apLsdB z*%rhW%obsCXV8x%qS>A6C$61!FrnEbkyT(MX$^Z5%wJe@U}#w!4M9}@>xWj#{^E?@ z3yE}P3?_<)C2WK3ure0cQd$CW0J#a8d+c|+t5XZ&?8%IvmSsicLhM$F3GfWj_3Ss| zS~{FkjQy9Ge?!DuNqohhy9iEM2yOvqvnG1f4%y`!nQAndcXm5D%@TZDo@U?gM=~W4 zTN=UtY=q+5AdC>)TF!Km1PzjH?lykmz*nChc<5qS*O^!K58lNE?X}K z>;N2(dVKfJum3XxoWAM2)|&Mn^Bo+2@qHW2#C8S(p%I**9eBYK)_&LdqYM2arRmL| z_xJygNL)8(;uJA6N5KoHK;^!%(&VYDoEPy(U)RY9a@FP(h&lnX^iqPC{3{p^!dC1` zF$`!ccDRs;t&E5OAo+3kEZBBfsbO`2GX~>K2OGq`H&q4WZD#b>GL^?1Y8-#&Uw3Iu zUc3Q!W2J;94p?p-b~nmBCVdB8p$=1)y=MZVmywBfP9^?3Kd*=3n<_s%Im2qmO)caO zRshwiL6pwsO_N<1JhG10@>?B zMVTxQ!9isAvP^VO2BY9$zIhNE4tKG$nwbJtqK+rBD@!yuqc^K&d5oQn#sEX_!r~GG z)jxy$5U+h%xeDxisumz7t^bF$_YaQaJnuYvnqwNa6&q-ckqN@0r{C!r4u=#)3>gQ9 z+wx8~8o&SqB@$+IJf30^BZy&mv18KQoa0TMrw0uQ45^jG0}`EF!ex%_VD6R_*zct>ix6cR)$b)$U(607;PS>3REkpC8}n z=R1?3-kiKk*F%mfRv~R~&zds)Ftbj^ICz2>@uBaGAE{F67ZP}x4AD(bB`O-&I&!vH zC4*BOD$3i(b>&HS1>-$^BO=Gl56ok2S{Pxn*oVPJ$4MBc^Yk5z9f}{C2~`Mr=#@1@ zZ0)s#LNo8o8^8Jy2t`>Tn)Az*=PO`4C0@yt8(abpsjgm1QZnwr_`*;m7xYb5>7pt7EZAm9EMeJmX< z3F&KKy#<(9N~KI415pKcTU4GPtQc($h)d@Q6R5sq1nLyKwe9a1Z+jG7VSl!n7x27h z@r<5$^htOnMeV}XoFw>V)eZPhEpY3LMYM{_HGIm)f^a+lj)tTRQ1xSEkH&y{s@GWH z*JW=yaHq>|RDA?FJQT-&Na1Y$@T=DkFI}IfP&Gq6!keG`NF9b(`Ds*v;8oWTaDGq^ zZ$;?qvPT%=5G$%LpW{22O?8CdZ7{9~goGj^HNrE&%uS+Fxkyt1?HmVU(y zf@3^Id*QU9Fo4C$`BUgZSEGM_jW*7R$dSz5n;w4p~iG`$4%4;9tsqJ3#mei@i?A|3HQ9R zHhz-=>pTV4B;vy#{n`j9j0WScn*>u+DFO)5bS_?V&@tQ0{G4=(yt)~V9H1|xQ>1ZV zwYD>(nhtzcpwzqNGBH6iM-!i8{g2L|!j~BCwr?Ow)07lOr9xSkOMrbQx)4y@ft;gF zD66M?1hE0nfo9strQEdJs2sb1T|k|rn8xuf-)bnNHnTX>hyzt8C;1<|=#Iw>sOzIi z@T|lFyfsVNAN9uT2E;fk2uU~QX1GHL0zOhVX2JLhfg@t2^FV>MGNGPu4zaxSxmU+= zM<0zR!g< zoNbKwvGm9OB6|&MkJ)*XLrDb+3vjh%lAY@&LeD*5gMGkUkB!OZU&v9r0a$I*z#{&B z%Rgv}%SI(C>+twCgL^bldgw@3shL-w-r^0itxr+-1(}i;N6zP^!Qpe?Pe1@iql##c z(Uf@Jq#JiDZA5?xlgCZXj|^Ql(eYy|!JR;1dh$vs-`DevnRoMY3azf1OY;AAm@ErB zqRJWT1UuEJMoa)1?Se=otRzJA2r=bRcGz@b*)xcxTWr5%JjDVcvLeVQ^v72oSAvNY z;LQeQCtIkiun7I^0K@#{Ky0ABA|J!MY@@i%fI^_c$y}f&HFmdEH0?`K3omS%z7tKU0ZVK3tGH(yBxZgSjH#UF-p zXV|ylAu2bhmnpQtJ*NY#l8xubl>FbT1j2$P3!6qNhdU9oZmR1O9+Eq8n&&u_zTP05 zFBKoZ77phU3dDdJ$$$4({WI_F2Cfq}$_S0AQ|*fe)Qtw0=NFMIp9^5#kalL2Ppj)w z*yGlY`a>_(D9)d463sbHcCa*f=*jDcPb|iV8>ukN*4%46w|cA34h+&_Fe2xV3UHzV zK3WJ$tFS|%JL?l)<1C3*lDOzUGi3aWPmBhaV{_tiF!grCRYzX0#Pj?7^pzMg&jF7(CGxWn+ zZTl^sQ6*eTUgLByf&9;Q4}6~-)4B1(jjg%CcV%nO4#?h~8lm`-rIA9qKR*hB0w)}e zq}<~=vO#rb?q%E7wP{2#e{bj#Tfb6{C`a7~{(L>2kHd#i|Bd6c8oY9S=0{s{gTKQ7 z1oiK1%|E=>m&8`c4=?c`K;8<0Cl`@z>S1;$a5g@eoqu9*(5>fE8LuSq{dSRvWc5pw zrfz@7GeryOC`mpxJMn~Dn(Z!^BySkXnXx$@LvpSoQ$`kkcZ7;?I187^_w*<{2IYZS zf@kAd?3f}U2`UWmx~aOboSQCv?bz|^1YvhdSYC#)co0xpc98}(I#+I~#BAXf@ZtIV zj^hU!{U`R8`L?a zPw5m32^z7IpDqXKlWh`T8)FyL-5VcY8$0w$n7n#2|86e#yW%bS9`F9vU+I)TbT5Hv zjH`UR7G|5$cW$RK=t_SjrFPcFeW{-{rJ-$sV1;^E;An4$l{JXn0gyrkk+-;gJ!YlEY|%0zn1q0XT@dVqYYfcmka9B56Y0_G0(o zk@9j-4c?we&lBoV4WMd>pIRHs0XpL6b5p{0l&~dt-~D+`CBCj`&+`>k41uk22LM2; zkd{bKbCNm|L-I)YqlC_)wE`;jq9lpANOeNBc-MFYm}?$xTTmp$XBq@|&Z!yM!$d==GRpnoQnR@60YxTAK;spvVu{&ol56}Pe1C0X~c4+ZW6MWb74Ye>< z-Qp=@D9NBP?pTSAKmD9JDH(L-c`5A|9|m$~PFOu2uHFi@liG$OwZEkR^105qDe3Q8Wt2Mo5pr6w9?v zvyhfex)MA*u{z&WxM3d-Ph&CvC{MVbT3c+u7HiD7`FD4InB2aNH(a5)5EO}loi)1+ z{p})pgwmX&Jj0iw4#&tb^7%9YqhFfT8F&#c6uxGepn2#AD{0bC4eWc%zNjw5BI1S^ z(^}Dt7NQXGXSoDFsTAmts4m+h996Ew017R4L3#p(K~PEC!=kEYO+wW!t#&q`}7Y+_$3wV?Qp=at(o z>EZGPvF5C~l%G9!Ed@P#DB&L3rkorwr06d89j+Y)Z=3R3fSM0cVs&vUCpKvW0);pg zhUXxF!(R!O=c|{a>9?a(blOshm!^l(KOm|XFM@5hJQY5C4FykI3JHYoov^`bByAT7 z5ZI0fCZI=EJaB%s%s3HN#yuJHkpHB)wX zFd3oAK4ifxs|vltq|fE^N82bDS9Q1O^-3I@Iw+8oF3Kxr6f6NXeH3M)OgzfA24BXU z6UxAr$Bo98I6HH2W-4<=Iz0X9AJ&yvPtUCrDB*5L`Dm~02G#SyFQQ|gAWr9(T&z$} zU2MqnFbz3mF9wEg6>lkjF@%O|Q(f^my($#*AE;jP4mZe#Ey92ju2(8)>mmUV9Jq=D zFN9@mj`$X`UO;FzbeqO^kxzhk1R%?zV>WkhjqZZqy!JR!| z<<521W*{;=K}pn$SbaK3=?BvafnUvti3p-3{sXp+IrkU}&Jn>!+=S*hG`-Djpp&uj zF&P(FofWUeq@~Uc+>CY0=g3F>&Of2W3RACdAdzx-j?!7L<2$TFNmc?pD37}(O=IF+ zB-@Gfu;#8QYP>*TH8XWXa{t0Po-aU1F<7#0LvsrwquM7(2=3&Ku8rv0G_|UV<0;U! zg^8>jzfk2j%kfZm4uATg*z7aJ117R`ntnYdTbW&)4>{8B8Ia=E{C5}bs~_%l=|@ED zob7H&1r0T-#0@de1LTL8%hSjR3q(yQHl?kPhas~tYHaHiBEV^j2u@^50M7> z!wsyb6%TtDiD7trA@N;k-7-u=ppO9dQ(dSGn?~*+gW;(oD{~!~`-{Q5af~%?Or}vx zugL`xyt_DVKM)-fn#^^|wB#(BksZaI zw``)6|126UnSMz0oyQpY3tRp`w^!c`Itj{*&_i4V|CplhC#Kzu#$!@ixMm?vMmF{a zW#2l!rq0pUG%$L}JF@(E0UdolsJ<*DU#ss9hSW=_P(k$yeF1WM9hRnA6@>rQ`6-qyUhqMC*4am90dY73dG~a zpRO%)c4VG{i974RhW1UbDzjU46=`|EuC)jmDf$KbLP^%WSx%GMQq%=s4h}S!16T~GJ zB0!Om7O`beKBnab@9`pPGk~`M$@g-ko=s}8i|t2N=$Wg$zQ5OO2y9v~Et-yry5Su|efp@HojvckZuIyK`}D zgiDT>55;_suaR~JDih(x{PJhPr=~%wXbcf%U&wDUVkL_e8&A>S2h(#v#NU|uIAfFhT5ZFk zZvc!DN*3Y!5Ydq|Y9|g(EEk>JXriQR{XdP3zeF-dZDfbqcBoPz!8+Xl}!T|5EehrVoT?(R0=jzVdzC@Spp*BZP>L_9AP>W;z%_j zy_-9V+vTv+Z`}iiQDZ`vuUJJz6~QYcaBCIPpcUDkyc$HP&1UU3iVnGnLy~9loDt?# z_?tTZSLi-At5k`sPuxZ(-$IS7aryX6{^i`kHSUNTMLz#inepr*S&P=}l6bC2R+dFa zBz?})5vU4qX+MV2YuPNEAce|Y_9z~O-qU;l^$8)Fme`AtOYezi#d5$)Ds+gmQ$=MY ziW*uYg}`R#1gHrEQ|?4U7%h@Vb2Cnie$8soE(gb`{k%aDMLf2b{O2=ib}bFB-wui3 z6R5wi2iK1pW6^hKlPJPyxtQ zj*I5R;VLy|HSCR(RH?i`AkX^w4j^e5I+B7U;Iu0sOar6zV{$I!;*CKDE+_r8y3PF1 z*T&%Jt3h*yB4*SG!E#!AC(t@X;ui^jqW1F8`m2ANQGr0qfaFX&g0E#IT}79nAS2LV z6V`0IG~Y7~&>OWTYqR729W)n25df@W=6$~&9YGpV*$Kz4VY%?Ci1Stet7Re%q}s9T zf`00^m3rj6y@CA(C|dCfE5SqaX8$~pgg(Le0%^FtjRQ-IGr9Ot1m-usPkg0M2uk@C zkY5Liq4Q4hK}rx|c4{(?Za>@sv*E;5E5F2cx!Wwv7P%qRN8B>tTtA6b#k1%8ebG*+?eOh`w ze2TaoAhqurW+}n1{`TpQCgVN((#r_tzmDR1z|@;8SD6yyoeDrAO=ygbDfq*3i7^)) ztD1i3)gB}SMi9&(h!yt4A9sVbVA)BjBOkctVQ+@^5FuwPz^cPM0pV^IUA`G(BC=u+ z0YKbXPfv#)Van^MK>Wd><$rXFQjqAxjre?AzM#0w#PO7TEd_JGuh|c;3Fg3h#EO44 zbA7|rG%B*J8Q<1N@CfI{tW`FQGA z=7TjkVc|0|YH#t;SD1iAc$=9QJnfyI_72P_j;ilBmzd&%t9%LoxXT!_aR3Z}v?|cV zFX$2xNHhXTbp|L;|8%Xk6*UOhs;b|H>!}8~RNoKp29wT&CkxMP&(u)BEaS~540_A+k6M6H#mnv!gxuZynTwYV}5LlJxp zsp46xH{LWKyH2{w5|}`B+qJ3MavNiAIpcLC1HM-92<8A1Q$>zpriOqA*lLO|qH5Ry z_m`SYa3f4{A0T+EjZDLK#fyLyD+L1AZH2ux<~Ia-h^u4j$8mTKdjrQ0F(R$Yq(TPL z9g8M{lp@4N{FFe_;+ruX^zb#Xfi~>!C+{AJi6{~Ifmo_mssk3#aS9Fzd(^Qma0BFo z3`SURJJwHO1k_8{lrZ~*aJ`4zwKysGbBW~Y>~Mv_iwn$=Kmh@2uqgA9B3z2hq4QWY zx6?W+hHkWGwcKq^qaA~kQtYJ(lJ@tZkq7wxR$fB)ssH*D2U3*Y24yKdt|4PBs0oDV znlaCv7tcBv2Q}$~N*Riy|8asHMWP5QG*~5C?nM(HUvzaM`qXn<^7(Vgz>;-oM=dDz zU;&&~wqFhaA<#HGNUQ^-h|6ox+6DJSw^{g3Ky0@;F&{_i_$%>5He7tOAyh<}7$>*9 z_TneRJpEs;;L;{Md=tK`5SLM@dr$$~p&IxmMnR4)K)8q+pcSYGC}P%GCU&NXRhM+3 z9Gw0w*?5gpAo^(ct$3qw091!*CZiBiTD%{IQ~pVva*w7Yl!Q$AzFX)TAqyZ81+=kd znaFNXseq5dQJMelQ+C^Jl(zhR*a;ayfGS1eF;`G%inln{r$Q5e^|krj5(l?L^t^lp zMHlc?CaAlp0JVm;EEm2}xT zK>-q_?MD?BsLcr z)z>NTv57}_8Jf;5Pq<|j53IzE@g5>>EadLHZY=^OWI1vSOhEcn@^NC3h(Dcc8~NN zQCjT=kcf#k3|Jdi+@cO($O0{;v#hE@rXpskR@;ngIyONR0efuXPnuOVD$lfSt{feNil?x7LxniTvcfbs!}LTpskE@-N^>93Dqm? zMdZ2Z;v?rcy~sj17j0#M*K?G-fY6zr87F2A0R0c6=xz zL(9w@xB#EG3;7@P{|qgA!!W*Yx8ej!@Gnxim?loj;Y$_#&zeVDi=RO=kuFx7IJ!rk zC~n=H`V2h4yuQtemC{$J9G+e!Vot-B`cj#wA7n|dhcn@!bQ~ftWX|qDjvdmh==qv4 zxHAGZQ(`(C-8&nsF;B9vZ^1R|XIkUh?si4D0BG&VTtO4~Hh@AJY=+HOWa6wvEW_SN zl^{x+K#9;|iwchl3Jb}=5D;&mp3g3oC#_VDn@+iT;_|VMp<+mL9QMT#r3BaFqoKy& zptbC6?>@hathH5LgnfB-Xo2JCnYO1e+N6q{Yu9i%xN@VEnzy2O*$k7em7GiRPbzD*GgoP-2EL`Z9uxxsD47X<6S3NQ% z_@T0HAOQs)N=HsG)ImIe{DWGM0ZJ^j7MO;cw^iuL$OJScGQ)2Qv&mv=wfsNP1cqr( zOsD+ZjrL89r2*l!>{y(?4=npedW)cjm8{2heaK3dbi%o4iG3q`RC1rC1_*%(iXazw zRxnV?Muc$G8Zua`VZ#95ikJj}j{)f}ZoMzHP9>WMDTs#nn&mIB<>hf)4YEaoD@GGa zfuUfuTQKiRIO~zgjb=!j-i}E>(|;FkBOs}wEvs~xUxpR>7Y0Cve zx9)N%pcOMU0nxhJLd=T@4J=S@pORNwcT0rNaZ<^G!Gg7Ff*5auUDPF17M%6V;_v9l zwB_7P&zoV@#fzpUF18pEyKpp`X-0roaz*xFH@}rd~hhq z>IWo3YmP?J_%{X42EMX+x*Jq^fD7?MF!cD#aduLzGq1 zAXLqADt=kDOt35g+$y9cKLPFVKw$tdsEc^}W%o12?+Bp78z?QLOGrSxs^V7~b2zSI zBWx}hGla?|%n`9xfF|@+`WAkILalZh1efE6voB~g!gy*8r8Tj)w^V|wiPc!w@@Fy+ ze&*wjqK=DH`h49`%?txXH}sp_Kg_uy=olPmN)ZSjW@ve#oKsCN(7zO6cde-5?gXX7 z|0-m?g*iL(aADb}>K|{$r`wV=G73r!JvK@pW8e_LjU3B^-<`C{nwXYZVRMP_=aq$ei%2AFAo61 znG}$TJ)|S<;;@I;vb9EVX1Pc#huDVWI|tf}6M_orV8;9c%lJauwGmQ7;zxK3-L>(% zRig~n&@H{ro?bNllSeMifpTY7csgQ@np`t+fdW@J4Uc^dgp=?4=U)NO@mf?bGtP!l z6rg>@G$m(6w-Pu2M9DBP!E7QDQTE7I^t;&f{Fc!j6h|ClB}*Nq=uFGFF2Qjp=EmT($;`N<-gAtvm zg3L42H>VtXzU1|RwRtocb(M||N*~ek3RfXkjC)sFLYM&I<1CUZ-k;$r?lSNQ1qoPW zo~jPyvP8Y-B1jvcxt5K=U)#jN87>IxU6I<;1zHls?cs)r(_IE^k&& zG^2-talwOhKAz6fpM5<$9^WR2h@e@xarYPg5$7**+*-n_9f~v84S0a84so#Z#3NB$ znxKt_Pr_f!SS$m`DS;7pNC3aXptWX+CjRx(;qQ;rpFs`+bIYwc7>enlo-^vUNXRa@ zNEkr_HW|vI4tlF*%diY6m{vD}2bxXnZ4e)g8_~JjDfO7@5t#W_?qI6^nje8;mIppH z=7u3nl6~ler`m|assj430`{xfH4oEequDCs-UQv__C--$pQVXf~g~T45qsCNK1n5Rct~U>lw*d@d|mnq9ht*1`>z zDYNEm*qnQ*l5kKH^;0PGN{pL}J0JySL*n8H*g@S9$D6I-$!;`}GOR?#3|n@3hVinR zy1>MmP@d|Ls{UvzbDi;&_zE^e7rw+7RPJi@KW@9Yu9NzC0-1Qr>W=R=?|l4d%mrT1kM;l z8wi6h7*yAr7|&Bi!zWoyF9mGPEM}2{j6M9p6cTXN4?QqXrPz#K2vE&942|drTyPJ3 zTPNDT#_1Ur%>coRJ`% z0nC!soPQy}#Apim3i_ewl41^J;Y?@Mpnk)0G zSYy~llEH)pOsMtNS+f1~+WQChWZvgFq)2Th9b8uJ&=q6eG36?zj)*l! zT>QN~8c}gMv+I01Glu4fVfgjUI0pC%Ll}&EPjipuc$z%IW50C$3fx|1>(s+^*C;EjCG!k2RtmhYkL9PC~|8Q@6Y(n>` z_8GL?ta;0}XU`IB6x+=bX~7g=SvM#rs`-?J*uSbii&0vEovynNj^*TP#OT-2h41Z< z)dv@gyC_&6l9212Iz%)^E!F}hq^X(^6r-?EWqrLHBSrGw(ax7RUu>=u9B;Y%5H*fF z8euMD{;)lKrpGY$Y5vI#i^VW3xMHxFswS#%7TT4HttPU7Nkjb-vZGF$lXu!EKh-?# zJa0;SgTM$nR!TihMmB8WWPSwqcvmH~Hj4%*zRXrP`$3Wc*e_=y)v%==e z2_O`ma51Toc*|eLr(?J%9KRicB>a=i)S5mm|C|Gu@kcZiVH*Z))ohQv^=P(S%H^<8 zWEeF73_C!{~^Yk)oUj|ETkMM0UafiRYD65NFALOv4=kwlMXef&6Ir3gfgqZe> z*rIWDP$JJ%d4%f8-ef#*5dxYtGOABgofJZU;FB2<~}7j zy2(>*teK+k*w-$ql9Srtit$6X-w;&ZvuC|JIfNShd&P5iAr@or1Qv}S`G$DG(Sf9# z;a20c(IN&74nXO!KQw^h)AU$?KSWOm>fo41(R3QHPBhcrU@~sa$LZPlsWgpoF>~3Y zN%D6;{Si4fsqhx2RFNSf2&@i>`a+=d7!~K(*l~QX)}GqVIUm4_-&+}nQx9}Yp74N; z8Hk6NJH9J_rsoNBA_d@ZH5k93CUN*v9BKg!1HX6?tD$DLwYXAhGS%bB`8bq!IJGvj zFJ3(S$~96ZoP9>Q>@^vy(T_n-p3C6GYXWSAbT$huM>hj3udj&A#yTrCdX`%dTN&Dp zu-0y+atU@G?p_i+02U06im5x^PX%3+O zw&QhbqlwN6Tdh^Nusqu=ub3kFv6aQyugl^j$y~x=H_zvXTtt6hWE6)M?yRs>%EBV4 zWN6AS2sNp)AL0;*5@J!Qel4EfMs}%uxmjI}%XhLwE^@pOB<+=-egl#m9p1fFA{3z>5Q)D>AH)Df1Onm(YIqI zh;l$)d>A_F&{<^XTq3j=0;_pLYgS+fkUz;PAIH)!ZZcKof?qb%mzyV6=f8je($Twi zVP=LBaTFXK*c?y1aI36rm}S{=pB~jOwO8SQUFP+8c7l~?t2boI7+@j?N6b;Vv`)oX zFlQeorDNfqL@l`{QO!wygnBi4D#D%zQ@5x@q!rYLjYc}P&Rp~O@g`lA?UjkJ!|<7x z8#f!wc;mya=9ACwmGVqlMtV$Bf9>wmR1yETX51sG$-=~;m}z@S5kW_9Az?^bc@8_) zph>C6o?G))b$UZIV)`CV4!hoBzsYCAl-l!b4_&Lq!z#||lPdvUfSI`*l!GgAR-jKK z{tnO7Nws@KW)|j>Pzq5EUa;TQay(u$=NvxXCN4 z%CQ|0#o-Mg?$SM*n}l{2!W#s0K|};M(MyEE+CXiT=46B%DL#O*=dV-Tk+=i>9<`z1 zVo+(E5T-r8EAC&3C*C~AGm&e(nrjU#h0kB?zmI0r=PPGUF^R|}nsLg?RB@GRqX=if z^vfIB;7UdR2)?YE;sR?`UE@`N5$CIUvrEfh1L;nZyk@RVeZX?DW|b#24RIR~bG&LM zGg(VS6^No3%-iTj)8z>UvBk$?S$MxiG096PpRVVQ=^ z;zf@m(%9s3R*2t$ly!-@%x{PIc_tqn$N4{Qj-8&*juU*J$^KsY(9HEM4EQH;E787| z|J2`p{F)kjVR3K}A_Hxx9n-)$9SZTdyeixkwp}rnj*rq_))Wq-{1=vp?WE*PDaQ8V z5sA1osOAIM{?3t+^ejq?3Jz4dBL`|S8qX4Q#=dLG)Vw3z%lvP{n(P2&gzwLpR?M9Q zT9L6qhf;@2^~~Upe)f|bJf{?sq^LM+<0XQ+O|aB?)(ur7C?+h0scqSiwgP0Rsq?1X zzQUTlz0_%=@w2JxADm! z+h`CQnz#|aJ#iXUIvszx!89y^6~1GKk)Hq8BmFw71z&v^K9R(d9EyT`d_KA3XjkyW z>GGiDh`2h6$xrmvUS@=$BB&lU@5bzG!X(5qN?G`%#EE9s;D>J#8-1E8qV@K2k@iJD z;WQTGA_^hX=CbvyL#^9*3a4gT3&I1-QQ>l2sotK5R?L3(or9ter7)|S+_hl%lget& z8~TM`?PmxXH88T?&KKd)lET4iA85O{WH#3=h}TlMl`kqCU~9Htu>uxM7NH`B;L^Hy z+P5!AiB$UZltBO1EcwhVhTcvl(eamxCQ*xl&}WZNo6E#!PR~>Pa2i!R(F+uLV*>$! zv1fkgBjj^{1waNuIc4@!TC`GX138p&p;m!UMbCHq3K3J6R7|O@A~=?Y`m&J%to*)25fR#mWF~h!R4D3czQKNc*u;CE$BEMkoZt#7nhp4Bd4VgKvK=W=3xFM6@?B z#QkAP#3`gFTH%+lkn!&P455D;?NjhSaqydnsJkS7iCWhq#7A_5k{utN)hTjzP_bsV zno)aBhzSY`I`kbk)e zvAq@34C%ayBw>(T0?zBVpXsOOKx4PAR3HmVjU9Uc*n<_CMZ5FC+Gr^v?2f)TRL+O7 zC}cDVk#sa?+Xhke7@{%+<2BSR+B6luU$N*D2mzX};0v%qTYkkR#@SYeuHG6NzBav5 zVp?llWwvazcfPSZj;0}=JQFf-A)@u*^2Y!}^(C0vHHv;h6l@R#kEW5rx2*8r3U^*+KxCQA8nI zWBOkP>g9bX{$jimI}^m$b&9Ixz042(+Jz1K`_8Ply*^S>@D#uY%IU~=eY7M&+bpx& zxu5Fy?w&h9o^>b~@e3ZcYt$7;GJZ3OzRc(XSx5h(;XO?AfUnp*Y$KUTSW%t@6)oNS z&FCctIaRym=vkcqFT`WF<1`yh$lmi7$GNkzNKp+6Qe21`Cv#V1ImIgmWiBhJ#cga~ z0npB_Fo?i^$3rrLPp@-Pi7i*RB-csRfY=jgNa|E4npsKoArngs%UP%g?`PTJd1Y=S zrpYFbfx5WIRJ((RhssZ`G#?7a)}x>nYjR+Ag15wZ_)(XhT*^X6@#OI~=Wo#DddokF z5Mp%vx7b;hz&Dgs1t^-4ZrwdqbCDf389@5FI9F;^F??&7HW<!g@O<0Irik{vH7?F%0!;!q}iLjHSlqmQTvF` z6+)etI#$&#R)Rmyb+e@+;F%#;51!qh0Y7a5sDlM%4uE3!Fg4?SB4{oST-*ge9BszNwvF_L zHL^YR*Ckm8r%(+I@DgBT>HL2{FX#vPtwIQ>;L@nQ8tg}GZR`i#4A<@NsXj^@CDy!`p`^!iU;Qr}QSGdGw&Gl+P-axN*Oa=3os+Egcuw|% z953luGkTKk{Sp@uf5*2L-$_ARWG*)FT~Q-ZDx+)aF9+*UGZNYASu8Iauwd)>+=>~> ze%YKzSImjcyXMC>Q##UM__UI87*qD>d!I;1xXUA&T_UCJP`k2=AmkuZLBw;?(XN2@ z`@Glo6F+&UX3A~G;%MJ7z}wguuCiWjPw{DVuEph}=)R0`X52~HRrYlwX)#7Op#><) zd{e_mlKA-a^4`(%=Hn6bNGD?g`~brl;fZi2BhY8TacGQiccq+&;trHx6RQA_Dx%A=0W`pvLrS-PqqYZVT^cB@=Mh>Cs zaIC|O{(zbVkj z)tdkiGirX3+5s7A(fu;cUB5uri#wXE?5$LT6tYekl{GY?srh(J=#VVy09y2KMv!fq zGmewa!4*)6*o)q>&%T~QNDyTUPubI+?#A$-Qv9Z0rm(3b8p^y~&-3Rq^m3$e<^#(+X#j5v$Sc;_#P z`AXNj@FmKdnyOpE1T|E0Il_!tJIfj4j^f+UrD@o4TYtGTaw%mJM-mX+z=oY7Hb5$h zk47JwGUy*K&Y~J&SC@ZQT93hG@rfsc+c zUq%&|_{0tK9JWQnDe+Y*G_pe#J|Bzc+4w}8QWU=17TgS~^18h)cBo2jbfs*cWi_!I z=jmc#lunnpRTvmTox6l5OHLs_MirsuNn#kv;}wgS=BHCg`ObW>KMwb^W+Ezk)mn>s zPz@%biXLPBkG}$AD((Z&S!%NiwTwOPmv5k&&^ZK6SU9n=9`Z(=4FejH_Z|0_*ZnWS z7g{suh$U;?QehlHO0|<;G>S9Q^Gp>{o3N7rSy*SqA&n@IjFH_W{xUTPpn`O}MaQ@mZew=jNH?Mg z{}@-GF~`ysG$w2*`5L!ud1#Bw4iyJ&%BLRG&?%e&a7;<-vfn@+iK}&77LXdYnOyJA zb=IWl1crwsg&raj00E5Ai&x0h4CaTrd+Z;zI+GC`s>M0|07dCtB74k{Xs2mc8tCnb z@>+mPx`N!GwdU1MFrLnZa$6qzTNNvTxjFiesWt{rWS3VQ_KK@oAjPZb6MguG##|;O zRcteX!Nc>KgMq1?v>uMtJwiYqWKETbqcK71ZG&x-3y28{Atcjj{T^#}C=R>0XLR|q zLn|Q|?MY*9##aJtcy=n7M^A-V@oV>#<$v>i(KDgcMYE&boy?A)8@hA_941G>63S|A zCB_^geb$Moe5QtlOk{(QdoYDa@3Px?+qT=GQ>@s=Ck)Y0+dV2Zgextf$48zI(WaeY zJPt;I2}DMX%89olx;-DBn2%d8$AR7PaBPlA*A($3cYpm4d&*J+^$Ts*6+D3GM5hoO zA2`dW6XUbqAe&}kGl$Kr=5zm2F0~w(CALMf%vmA)Q364V zGFTfvRv8SR%wku2?3uC*c(0U=-&s9Ht#Ab-6V>Dl@;mhoduj}nf|1L)Aj)EGXtDsg z+8Hj1waSz;g|kP>3$%euyc}b0ZnC&3e5~Fg-wIDM`h$DsAN$58mFr4pJN5J4P)+__ zr4G`Oht~o*aIOx8QA~a4m~zxL+Zm>5gApJ}JqM(-4x98@rh^ZLlY-ou>S~}y)?ULR zIsX1sdep17!2_s=pgSK;N4a+cH9POelg3lUYBNq5Pnt*M*QK9u63A!gmwFW!IoPQN zcMiQVzS)hm0>a@h3xtMMU5F^}jH2}o#}AoBra(%PeH5PK5%fVLQW{fSrgjIbFb@+l zk_WV_owLXdK4g~(Hk*-Xq*Ep$Kn|w`4u41ywD7GEE#lmn9^n)|8@;@-6g@ATR_c0# zr)ruP-0qqH>tUCt)j4oGK(XV|6o|?!xvv|PkB>dn>NZSurNz1M@?=I6|Dxg$H{$bw zf$zW&n7Nz{A~^*DJ|ve$2|Zqd5#ma8;>jpjk8uErl{{pfE#$s+cmG#qsTcd6Y8&UO zIIjrZOx5-4!Y-EK?U1Np1_wl{m{qMgI;QfLv1<}=v{XYnc$s3R;{)bg7;b}BNCqh4 zLM|l9;b6r{D>f=o!p%Cm6qahdzf(o2yy%6(R7VY< zR^UO1k<>veLnx@?u|EKFtxSM+`xRqklv$V0o~!>`ep-G+6>P*Z$ze|lc(I9uW3-!$ zj_3s^xUvnywAZ8u+e!|d)<6VddEknKt&l8_MbOd;qAEqD6Pz>(gK=1#CuGA#Z)kK zHr5@E&xc4O`2yk<0tnceNMpZCj*Ob%GPL0ZCSS(m+1KNHg=O6M*2IT; z=K9`KRNd|EVQKFYu{?Jh{K|rmqKzBt8GH-L3aF<2wKcvCUMmX>1OUz#;bJFIFj=l=sJe{eMa< zb!1qNv^YOE@3eAF~vncMpk?3J5TXaO#_P__fg>;Sm>15(C;7Q zA&)7lc1c=&!cK|x^#oupW`cciG4Ee`aHv#Ti6SbR8S4V7p+z7FvLT6#UT0fxSMUB$ z|NaB3r}z(a^8hmkBXl^aE9;8-G9({hA^#%fV{r8FXKEC!e#vVZ&bb0o;J~m`7M}mu z>Mc)L{ztP58De`xekpVeqXvy`u$Zm1>&ePb4lRe#bbCEw@2ln`}&Dv0ms1}W} zb<9*`qd{O@)e3HmRn{{MBQ3-HfrxztDc(GtouRO01%o6G3dtI>X~bLZ)jl${<2N%l z4RY4(t~m7@rpNd-^Oi8TwT&1RurH33>FlYQ(enoNL@de1g|HMg!w?%G0<5C#-6<~k z7m2pkS}wrjW=z7622DN}dtZmwK@H4N@iArT%6ua-C-w$YoHw(duSV2C$BbtSbJ*BI z=9j;ev1RNGDs8(5On!r*sj%oVw6)m+KW%f-V5e0PSWy0EThFi)LbZ}>SqF%bpwCag{50Yp|am=WSH=m1Tm3bwb`h2hYD*7y{lOi$Y&R#noJqe2*tnQ?`9 zdmAe?Hi-*ONVVB+ z`&zAd5an6y8ufk(L~4sI2|F}cx2d9e$9SwzwTj!L8a`SLlxYE6j{)W93KZ775wIpb zjK>HQ@E@pV2%dc!?8YGQw$L+VF87pc;%*0{Rvd-mWdfeTgeM$9kc6j6&udkps z)sx<-nyQh=9kuaTBqMhFSU&MYuw)0imCx78ittb-Cv79oTaZVuLL$~H;&V}uK(tRf zk_}dLggwpz9=Q?O3_OQYw`rP0G5H z-Q(_5m4PVvfo)Y#qD4$XMLk=o*YgPqfqE-Mc;s=helF5%WF!~JvjKaDiGNdBisgru zIKYM}0HhA2dFV$Jm6OFHk*8>S^Ejcr_%`k;6QhWt&SduI)Va7k@EiZ^qX}q!sZQFL zK-Yu*K`5cRBetxU3}ktFRo&5xW^@xxpwcR3qGLGJtFkge1@~06`~`e(8uVGGtN0kF zz^SW~=yLsZ?lead5Zkfgojt7#g|C-`>6EL8NKA0P2`Uo7$TH*e-CS;vaWPV&ul>F{ zqEzCEk4lj+ip-}^%W^tp*j6Q@N#V?@Ggo8qV~@N;Gv_yf}e}542j##dHzh+54NSdciW=-xO704nm?s zJ}ug@W=^U_>t)3XD#$d*iNM3M#U(_Rc>t_QPhy}`FB0Li8H7lP#ExRJy2jw0^b|5x z{qX{%0MXGWzjy%1OMyuPMX%KKIrQ$ z#dL>9?NVlY9M39x3Qz=aTG)<1W2qh)5q;V0h;?6Cu2n#KE_H8mp{kECG$0^B0jWOd z#hA9ABN=5VZ9EELM4=JrC%lvL;BK$)o z5bUSJ07T{piY_w@3X!_M+MR`($Erbhf{w^IV5I%aklxVU|Ksx_1fQe; z-e6O^Nq`4=sAKU^hWD7#khdal({r#1^FsRG8K4#xZ}cSVHbewk>%>o113`HrQ1uwL z3{^&0aN*3znchrqfTkI`561z{qDDE$=4d3r42hUKmLFZrvWe(PlJr*lLOXlZ;bd6@dkF_hk@5V!|7|p;S12CI3ZYmS*o(Mx6&E8Q z-#tOBMCqVDr!Eu_^hD6^j34ywp-9S3KG>68-DaGkUB(BNfV{GTjSp9BQe|}tWl9C+ zrxO@{I@b2 z3@%X1%`W*Rm=MtxdkNhT}N*0v~L zGD%lT`<)sY$b7kGxMUliRLyGZjbIrQ=uvuP=lNRp6<6nVKCm`cEQg2^QOFk%VS`Ze zT&S88D>>@q%gkFTo3ZcUhTCnoW;RP6axZc+boZHu2yiy+(KrkUsyI0D#RcPP4>w+v zc=A;|MIevkiKLfJ8_J8Af+l*k+NSGs^f56@zActskFEq=V@-y`()d=ohCkQe)juToTwlTlRZs-<@5~y!Bc67HFO=LPTLnj8 zpo%w)?4(hMw+oAx6zKRM#3U2OS7MpG-Heo4msaIlK9@RbF2y6&Y-9S^L>Q0F!_YIi z6zLOsRN;*C&BLEy{Xp&i%xZ|^D(^DO7O63fRD-kxsGH^3NQW#Tv=Fc9%M}ChRqic> zB?-sc&u}<_fRRQk^T)_izZ?U@sGx}W#U?RpZVZC{VDV#4YF7_g+RMJt@GVrPRH}W6 z4^VBQhYwv?3t8+3Eq#Ijqr;h=-&+wEq3G8!*>*7#npPwFT*%D~sLktc z`!{>N$U1h_Cag;CQ1P=rzH7Lg!|yMPU}%p}_m)MB(?Uql3Qx9xzQ;|izrU>anTdmq&)4vP ziP8303A+<$rk!3D!xUz|=+XL5Y#fpI#+MCdxycd6Y#pS^VTMXp@qle1HUKM8qJ;lNw)Sd9^@7wOP$Gv|| zsVEM!S1Ip-wVaO6TP5#Ni@3ZqlL581h(bpATG;k5DrEcn{`|MNq`xmnT7VwTC6GBs zfkoLdFUxzGd~lTK*2;Jex6Z1acueGc3U;qE-8uo4^FS@v;ktx@S4UYy#?uVsk)doM zTZv3PtCiQ^J@RR+5%W(H9-6m6CP$?pL`oVdOXraanF0nzYYz0>8Z*gy?!EXIUQqMi zKWzM&I+G9Tfps~APvNn>G5=b?>$G=?9o<1M{XKFTJPx*r z6xy9zPcp;<_fBghH&s~nz$wNA7BKk!oD#$FHT^f;5qR2iw&5=ZRz@g1N~fkiB8Qy^)p#act zWv=qK-CmmK6Q!mrJ`C2lkb@E8YX$e&ojh(GhG&P__^>jT83c5jdXQ$q2zJm5G2(Hf zGw+;y7gkIB1rvDy^GrQ;pUw4StXcI~w!fL=>wVX#9L*pUQ+#nlQAtWaOj;RJPsu|& zX)D{m8B~%_oGAmRL56a{Bq9Kbx{{{?x-cg^-pIf5G46InDDtb3j*sFJZi&&MH)nUFNri_fB5G2;yONnMk= zE^hKFcmBoez{kasotcaSH9kq0r0*yX%vuh$xu25`##92;v#ktgxn`Zg`><0(NEibM zGyPje@>X?lk{DV!EzI>cI?)3-{FiYG@tZ$H&*Y_h;XA!Tc$B%PZAimpZ`g&Q46ofZq_T?GhJFqul;F>81B{S9~I zP-dQq^^+6rzmJvhpdK7~G~sTcQ(zB74}M81oV@8NzpH`q>T4AwV>r(za)qv8-W!~g z;dhTW@QHl-xBq%GO8~XU5ECgp(BMDvs&R*EurTtU)ynnaO>97;&%p1}Qat6r4Ew=x zE>2R&@FuR{2Tq9A<*Zge4KBG(?#}2IEl=b@O6rXuWa4 zpQ8`p{`I8{xg674klgXM#96zx;5zv_HVZ4pLY~WMJ!kk|JxHQO!50*czIK@(&SW^Z z{$RtZIg|+>ThBVq(NIDT4`}(l-+F&m^eLgX?LdP^<}Zm>A&03y4*ZPdi5Ih{*-YNg z@dy|1a}XWr8qt+^@Uq5;)$mB(?mV)It=7Nu@-P`KNU3cqG!y>p={9~is=wK%0G8;- zmRrc&dFE64apMJHbnkj4f!Ms_d;ej#y+y$`{}4J(EuR=iT1+qgzHx86ZI(rNBFFpY zpWro0KVwJwcIRM!u4HLx*m_R;9JU53EacwO?GOBWK~JAlcsPDa<9d)}xLwTi63^y0 zxPdqG7thIk`;R{+S>v%;I)6ylFXK9~ZZs~! z5uUro+2DGXmmDe#rEqB&gw=8r&(p;PcV>9+uG~}f_ok}=qy^>#IT}q;7|7uu(23#$r?=Hv-yRA#y`jxAV?uo&m9k? zqw*e~5AP%c+=_)zc)=KpOd<2BS3U~m&khvm&mGTVBaj>&CUc!ASempBVrek(`N_~> zpa$}CFlHgGxg>F(;+OVQ`ai{`8=YOk0#ga^PEmHokpxwgudEJpx~{bVrO1x=dSf6( zO#Fd9(gXxT96FfAS7-cisqJS59-H~NQ~!RF(Ww2nGw@F<(Q_4k8oHYw`n|RB3lRl8 zoq>hJOG~J*vz&6pO#Y{m!a-gA#r)wjX7G)r&n`L7ET3%jZO46h@j_;XLBNZB^u(xT ztvb5|6%LxM6w}5-@8rGTTZ?y`d?v|s2L9lu7GFvEoP7F1{#F>?N6g^Bxz0d-Ko@_O zPu=Q8FL?NVLwC>RuckyI9Gp*%IT$G1{n!5|DDOwWXpP_x-(n7=!$M;Q)G$sqn=JMX z9Xz*)+2n^?VP-ciyAG!nhpd?UK9hufcQ{cIX46f*14}RDGbx>8&JYwGN+9V-|4NN5 z*|Ku~R+hgtpD^lUppUCV&KvL!ywc%uFjo2(dk;MZp@Gb^oI5T;-+6e#iuht5q1GiQ zfm(%wuY{ad#m{}vx-Y*!=Pa;ay26qppE{iV!fEqW*w$Ct($wPzh!fDM(2%Rr_3wfb%z&<0_fR9R2qz1-jdlvIqFD-Dk zH0somj?eQRTXS923PK*U+VvC0Rqz!S%-lbTwQgs zFG+8=AerXjGR;Mk_$jl4s}t^ zBJHGHhVvfBpM?f8Xxb zmi%q(W$mg6(djX6*=9b;{wSxHw!J_t@dVSp=xzRj*y$^-eW|R6KRz495FJ>E*+a>A zUi)MW64-;+elX~>wDp0!E;CM+ZD2D%xVVU>cNStj0v*TC$Q@L=s;S+`aYstK5L5O8 z+^;`K{`S9ky&^?mrby9{#qeOeft^u59q`okE_%;n_2t@F)}>{i){KbOTv04N`N|ILci)?Ivwy40&l zv`)rUol~?GE!|wNxklG^bA?3SFER7F+*lL+T2-#o6~A3hn) zHjlSH96nwuy)gZ1OFTF$f8}?6ViX(wD|`8KW#iR<$t9I5QUCAl?uqEtNAx{jb=CW8 z{~&J?PpmrI)i=T(0@1aJC$6hMLeq)k`c5vv5J0SU8jPs%y;mF&ZSoLk+t+4Hgj%}# zcYSy|X3@vyE8e*5dv;vn8pRL)RUg6VpRoC&yVT!#r<+|6sn{misqatEDgOKEb0nz`^Ly@VGrQq`=w(=Di)x>SySIO=w6ILxZ%$ zI`y?(A~dzk9CQu5;~5X@(8#l{z4@~{i={Tsr!W~#6m^_bY~sRQ`ZY7u)AWNPvx#XX zYRA1RxMyz1w|FX_lw|h|H{IJWBq1EJGkbk#twlz8H!LxPRLmN+spr>27A!ZR$6xz{ z|3E!T;D+_a&6w8t4U|N7ns(kP0T;UYCf=V#i5v7OpiE-M)MBt+aCe47=o+rF^asb> zh{wAJ7F{f5z7uJW73eMB@qKDpO|QgesXd3|E)Y>y`m;^fU@JaYb{27oXLSca9?-u# z{utL5Dbq`4WSs^huIj5Cl|cHg4wV`WG}UNY)TxVOMmXux%Jn2Cf!i3}7|0n)2@k3H zGD;_#gAPCP;J$8!Qnw6xgF<4v)9W940s+vb1s6|)tF`tibl+*XLI;^V6M<>9)REIs zUn_}I;}PhEc2!(vq@a1)!=@NHbUW0Iw~UsCn~}8s+o+h=PW=V-q2)Gp2e%c?2WOzV zd=IovhLxVw&{y*eL14vS-F{q9qVkFd@KGCxd{t{Du?a7{(WOZ(S`;hswY4{VCyIQ{ z25L2>^|(|Ya#JtW3%fAqd&TAtvY+9_VEh?Kem#e=j$XT}uYdiv)@SO2r-Jlw6J*i9Z@=W2!<4do=kNd- zh$yKkkJ@bJ;rwSW{-D-oN~llkm%V>JO7>bS^AXRn|0OR4-8+m_TUie6QR=@OVgHev z?@IY=JO0Ge*O0NG`B4*H63G|!{&*DW^ZNBfXQ0#5-rnXpDR{tZGNAMX!Wy!H+Bjf1 z>n=Gr3bT&P3}D2=|HtMf`d*vIM*ojC0sWhx>40?D1NwyiU;m0dKw0|dz4oVHjLiyi zW3n-dVZr_Ig&UTPg(7-@Ylr61=)RVb+E9|>0z@D(o}f?)0b&q>VgllxU7qY{6kuQ(?;y8h z5+kEpZLN3@xoccKo-6pV*&>QBA5~|ZZxRWHtM(Vz65znvo%$g*yJOMn^vR_sPdr^gWm#-K|u+0bg)2OKtIRz#_m$8<5zxRirp z_JIg)qC;8=xndLV^o!U>1`sFnqt!z$of9cL-gy{hdp-b`v2~@2&M%8Sz$MUUU{bJj z%;0~xO?S(K?SniR6(%~?q2gv&pw0Bx+(&~DG#ZdVl;6{&Ep!dgfK5C@N6!6{nAmrQd5qEfy_> zRAUB=XUq0cz!CIS7x(WJ<27*z;1Ptu)947Yud#N%as+*>U|vwEvXdumDt5ZX%JrZ4 z6h%K%q~Za>(^BBGZl=DyV$|BS7MsB{_|b9Dggs-}k?%bpVQ(rEU!8TSM!z}8UIG4S zf%2jO0;#sHaG~J=PiPepA)wKxoSSG@#0})Yl~h%~Y&OE?lW7BbGeRO0(qwr1uJn z*~<*;R1IP4o1?5+N?>97eByAMfd*?%9d!Ppi~%~xE)zsKt-P?NMcNs3|iV|@udEhtjciK-OvRtM=rOfY_g8aU;<+hC1@Wi;|JVq zt|EA3O#~dX{vFqqcD$7oJmf1UUjK-GIG&*iltCLU#FUfkb+vUZHmj@=0mcc97v!;n zx{!<6J0^cXsgRvI28+Bn9xW?oDYSpzxV zs=pry=oXX2#;C9IOa>_r=7t`yxjyyr-Wb-mhf>|n-bsvf{oW~ulf%zws@Q8sqwf}O zeh4UnmqRzT4xpp@Er0pyyN6F_`CA|PzJKlye>okAE|7lE+!gj&VkH{aDQTBY@jJoN zqAMfS_mAuOPK@%TX3gkPH$oA8^ZLB>NN=Rl9|H!^+QgH+K>=D3W)g!5Y7$Ba71AR@ zMtxIq%l09bL>juJGWrlT5jTA#O^rAe^f}JSqH?uq#2m>)Q1Lq-%+pi^g3Xg2FMLeww#x3}T z0^^&${FVm^nn?T`ZmSrW1h5FM!EcUn3=d0}Gb#iu@J9Q)6rAlby^|qT*>v#;jYyZ{ zsN&mjOJqpjHnfn8Tg*;Q8X@+oRs>=hgk+#8Tg1Fy_*bttnx-@4hLeeMC3F(9XeTL~ zYMPR?Pa*WHVWc!nU&?oVKbqIjDDixUto#zs0pv(8E3-S9P)-HI02yPF2)P8Ad%@$^ zHCfB=^OjPw_TDPqp3-SnI6>tY2?0gD`0*UAla7_h0c|u&4sI#WKOo`qNtEjC?)H$9 zEQO^;I99}^yM0^J1ni(e3@7aRC-2&+opTJ)-Eu~@a;Y$z=iwzmNa(EKPx8yMpYq58 zD&YpGhc{+76{TT!rjpsEH0gkDyVM_?mDk?)+eI{O!;RF1Lefa4Nx{!Vk}Th&Ze-vp zvxT3XBT?=gRKnO9(!>hn%T;gZ=H!{9yezr76dnhrT{*XdG(nSU&dMq^_s)hsiBAod z_@>WF^FE$8?rdiA6i2OZYxY|Fw^9m>+k*(R7H!oexTtNYi^@7A0c}` zO6E6cXU3uiBa%rS@q^Jj{;GcDrV}H$4G<_2AQwuHrAQ@-gEmS)YoS(6ODTxD9SDA8 zO(GRKqBT}aqcz9y(}A7%-q+{v!D2-`2#30mzgzZuTo{p^HrVA`_sP^mi)T1RpMhOq zl+Xg_Q$G)@eI+^qBMyTcJUQ@Dv#**og-<6BjWhqtJ~$Zwg4~lXRL@npqW^)aMCpJO zN|3tLO|Ib&A`^b+1dY;YD9;dd1h-1WZ5VZ-e?=VhMy!Qre#gqD(ti2yFye>^jpSZQ z$e{;8IylN#q+ek|oEnda^ySS(%z#dPN)#kSfJR-bZGSBSx(I3%1V+Hqq_C846r9ZD z)zW4WCLmL|LIfzSTfTVyCQUp5InZveE;nPRiD}jS6y#Jfip#8@4(AKZ1XWPJG(1VY zoEGN%HBl9;VXI&{lmgDI{#qaP%mf1~yt=Qu6P7ThOoI;8!=rhbZE+EF2eDzIkcEPR z8ui!XBFd(d^DssVESMK1`Ji5z3}sNq2kj{x`UQsJ^U{NOb_Z1z~1oMQWMQVg-P=FaTJet zEv-xRXzoA5-dMV5MhV{!<>Db|3J)Cf&M5{qP|c&|HIA-}*wDJ62EhJ6unZ~aF3n;-ce z*>W%&MMLGE`a^~@dW$R+a}xEY;SmjXD}s_m7wnpv&Y-`;ifPOm33ou^`<^Xh_DXj$ zgGy&zS7^87h0Dh<|l3Jf}+&rNH%2B`;_0qA>_sp+^uV)u{B-H0tAa>6O z>Y^?lW|tQjbX=_kqf3>dF#QAdq_~^!>&Ok#f1hAWYX+pdz-svo?i>mbx?ef{de{)P zVxb*1YQ@q43@+o5Ly(W6Ir7a6)~B|W+>13jMs3*59}iUL2zJzQVJ38ai{WHZgA=L) zk%LNi?+gu$ZN8Avi#jr@xt&F4XIW!-4E%*YG5mRUXU=Ye3+B7Qf>V!Q$hPPWH?X6W z6Ml0=+Dp~lFJxCUv-0v{+Z!uBXNP01YFyZl3TujmX7BLOrVXRcejzcN_93ZZ8^&C; z+HRcMb`;~FI(PQ7D9s3_hYPgKU`QH;(JH!F4%{KPR)(f|+DWFfUvUmrBvnio9rTxy zjhO!FrEo>HER@1GR))%X-#%Gm=%o&3UA$Ac+s--JDxTR-{?_Z>5lyNW*?e!C7rl^7 zYT^WeBynaVdhM>PxPPs!_G~FJuSVBzb;JxBUmg@}l|8@My)ynmd%ZG%?WDAFld#}i; z_Ry;1eDn!E2XA5960y~{hE~Nfr#$%>XV;qMn+898mFYf{jWh1c+qN02k?y!&%X+KvnF;-vdrdA^?bZ00-x0^Nw#0F)sDNQ(BATfcfcfRy-Ho! zOa&mRk0_KOh4d)iCe+ZPE{C@f&|bQrfg%={ecDGT9*{U(11j{za70RL67aFePo2q6&l+D7cs0jN($bh1n!H7P=V(Tykykq*# zcE>mP$3vLz@{el00!mUwfqZ6H>mqARg@XSuJQJGoR@7>2C7Y;skGJSQ3f&wIs`Ct5HQ7sobwuWLo({#u>lp5(W@RBrCWS&d~=gi4;Kzsd?FaGy9xOZ87{1WN~PT*2G2q#kVX# zPibDdU>2qiG@yg%5rH99Gfb3s){XM$xyG)%s;gk&WK$OmtV5Y!@dPx%M1f63d4fYM z)AU;4OBD?2>wMV@U~p(OCkT8>N6`k)g;!T>%=)TbKj)lvL8Yv%BUYXDP7bowEwbKV zSAlcx<+drl{qdac4CIOWMZy_p>~IyVWgH4jx1Knz2n+gcN_*?BzHF=X92!A;0)Ms= zhtAC~vfX6{AP}6vl&ykQM$sq>Q(tsh_^NCUp^8z$eo+*{5H#RhR|LiO{qU%qaX$4n zSkAfT2ENaQhC}Ujw5k7eBG-qf;wZ&dn5IAkdSLsmbab=f*p<&|DVEJME@H7{X`;#n z0c5FOU%q8C(2kvc9Cz@U)2`S2z(XU-G0>Io)!dv;hTPZ=3<0% z!tFdekpl!-r(#dDOhA)-{`Ny$`hx=ir5)c>F$1#3y($1$sHSR8ih50t2<~(>RC37T z6eCDY>P~f)9~NB8MfyWciywj25I4V3sAC;a5dzC@7Po9~}HrX`0cE6CoLwQqiHx!)j2d=(%6F4hrl$tKn zGa|$uNp~kxcQ&hq$4gf+q>oQd*DxWB`1D7q!%b4Ww4hHSJY;eU6Ds;%w^2V*TXDJq zva6m#0xEUw=UcQ=7UeFupSh#}OyGUs7$?c8A|nS8KOuh_*Wg9Ox$c%mnW&{ZC}x|; zqbmpG?u%hVNV>2N7JMDJ0=WTlAR#asQx!|`9812N#4R_av;IS_h^#jbmclKrZ+Qd6 zr!(13{NV6l?PrsntOd1TcTLq&lT(2KzEvbYz0n;o!h+?Qjmjkw`or_tOq>#<1RFJM zAUR6I8D=2Sp;bdkHwt*Z&aAR8pO%70T<7>(Cc|`vb!H5j4Lz|k> zmeZC~%+OjhnH0>qa-IFshHgEd(IdK8=MgcO`Lmfzw*WsO#3!PBp%Ue9hyF#B9xOl~-%lG&o^~AotkgFP=ffXiMMc;3)9XL{he%jH=TDAC zY6H@3@u+{0n{CZEl;}rCTOcvmjm)Y)95#}oJ0I<3;H5LkqY({sY; z9~CZ+%6hw6yr9RS;XFtZ@hj~I{&IUU&CI=~XRQ$E!Ja=zTovFmA!;+7^izKlDC?#G z|G@R1U(NY$>7r{hWiIEWTk=6_jxe15-ajkib8s{aVId%K$Ry#6UVz;*>knP& z(_$HhBSTY%4TZ&oxDIT%;j-Ui*zcFJXL!x&>r3}c0Ru&G+gXsxU3yH*Zg!`c4 z?mr3G;F*{O!`Mg%bndQe)v4#hCtE6B`^$e_F#pi>JyQlDi{oV$&Y}#|R?7w+A=VY- z<3hQBGVvrChju7{oet^JQZkS#;4;Ps_9U0+D!`5v00aB>fL*s*R^6S;hA;udtHk() z1Tes}o&2@q0M+$eap;yCS?g!Rt?`i-s@u@oj74LVTCsVDmbKErN@}IPbs^esMbucb zfYO5F51PJ@h zNMnJ-1D!A683w~jt=0-mE>?BT`9cU-2TjN!mNteP$vh}Ig+tm}m>l3UssL^w;q=J5 zCEbF+hKJ}T?e8-Kqb^KtU9jvAf8$1&jawUy8}D7=LM0aL`s=z@)G$ug^V=(){gI_W z!J*g)*TWe}g~=#eUer)ls#63VGoT$iw&gr8Or1dh{R2II$g!NJFbC~gSy60nOK8H5 z8}#qDnQ@jmD&R>Y_?y_cY~tE_ZA{bHnl~0lO+)x$RRc{x|3o6xuHWE{ z2gL>zMg9RIascNg5EiY>7tG-{@#ZwltiiO@&e#o516P6J2Oes*;DDKM^=IF4kBnYd z`T@h<3MetkvIkZ@GM!@N&)C7eMJ;ub7W&0S;3zJGTbji=%8ia^`iX9dovP9Zh!M@A z>JI6BBUoqPuxQLa&~FA*G{7ME#{2*L=Au)qPfr+iJ3@d_ycfPnv2GT1qC`Kgo)@$^ zCe{RD@~{kj9n*@z!F$gHDFpN4d|7N+MWZsQSF8za-*{dM&CJvX6%Bu~bW>ePyWuu& z)E$yOU&q}Yeve`n-%%e2c-APegl1l7w8;}J7vq_%N)1~x(sMqWcpX0YyJrqEVDCiG zc)(P|?lBYJ$;$xwQ6NTR;C4O0(3k1(X%t$&_ibaFS%hPLi1Axl#X3*3Xxfw7?l6lR z31O-vFQlfddLXTc4{}C|+v%hvk*ej<=q4npq@Fi~9s|&!u!b>A4~KCzSs1P zC|Yps{eP2QitJC?m()LXhu&3I;az60C+vf=Gv#iJUH93_8zbkfFSyY^4v+aq1)Vh{ zm*MlvQ?A8O(iQ`5cTf)0LU5?@uWiglB}hrl4bnc2le# zESByqHpXvp-W5$gdGZ$4p)`vAklC_N+3UBdFCQ*m+_5mSP}^N2E%J6uK$DzifjtdW zbIJ9VYF)O*@G@ZzAIhGcjrQXTm)eXYNZ`?vJe=wk;*Mx_g`_{7WK>mNN&=Q;OU!yR8D^yid1=WHPqXXPgdXL3$D2HMAN)= z6MTA=P4BqM2F;lK^zxSSq|oe`q3m1@q|e?1UM2Qi-}@FImv?DktGo5yEv@P2-g?;q z3H#`M`);*c)4wqm>S7&{{4Q?aiJq0Z2uc8zj0X-lnWr(iJ$(035IjBE zYfN7ho^$?6LrLXV+Axx`@}=h{pVLswwOZ}ON_0->i*^k1;Lgx>hXTBFZKw*E1oBt? zgZAW_?|k8j$xq*=fIU9<@5Cyw-q;Rm0ya2w)@RWpJS=JC&YQ%ZUvu>xfdK2T7PootYy+%lV29vZOM*5X<8EzHeq|eTu=Q6EcBJ`Y z^Ez%FoUh|Kh#|dS%c*PRR6C5VBxMyrS17 zvzn7_e}{m%t-%s7!APTn->H=a#|%ExXDx;6W4-;Kjfo`guYJifKf{Bz;5ARZAlgf2MURrytq4o$` zq)h4C!61MVJ4?4%2vmQ!;hg?&gFfn5+{$v#ZV`}Jx6Pit&L&dH+AbPo0|nIVs2WIO z#!Z0kNx-&ly5;ik-dt#`*caZl#e8Y#(ZLhh-uoWFT^WhpOZMuW>h~{zZMxGoEHS-_ z(RfY)Ew+tojQ!+CUeWNNrp`HKyR9?)4D3`16%5LmE*v_(#v>Q^@U648y)e=}K^uCP+9v-f=%wytAC|>h z5iXT4w>MkV8U&KsbIwI8oa4@lCnr~g6D$j+wV43C;!$JjuKWG= zUls-Nm<^tJmhzsf4lpOqMb&~pi>Z$(QbkrZ9pBm@tQD2L5W|8y*z-VL z(^&R>OLxSpgRP0DSf=Q>Lt2eQA)E#rO6L0EAxOBOnF+cfnJC^zKqW1OZ>_OZ47LHE zt{@iOfJE-k`@U&!wG-E@_a*4r$-Ede584ZE&v!<(1f_0m-;1V%`1XJPfl^}Dr>c$M*dgMCn*{6I;HT6j5w)=+hKgk!2ysvlAxsDIgAxzV z80q0{>nUzyTTM0ePMm|(1kubapw)#KhtCQ?^&AUFB`|*M*i9w(X18_k-t=%WAG)$g zeC-3u>3M(aYH|k8SIMx|CS~ZGp{%d?0^8#|XN1B@EN7RJTEI*nmp~dyjO+LeuC72D z3o*Icbi+LWJX;(DLX_!7S;txIBhfL3GO_oCs-TxZI3sN&FU2kzoi#6lufsTz3U(8(_=u@qD`!efx@ znpb5t+zy0ypc=5##9Y>yli@IFSAb+vdEz{;PW`D6`p#(cd>|Xd#VXX1REJOz4i>gd z$r7L?FL+(sLwC!H<9u?=u9%?9wNiVqpT;d`l5{9PYn)Oem2gLNki8hD*MDb^_FMn& z4v*&lpFea|Z+z-KHyT2X+GccXd^*?NaO%!QVGm_?n2nXmmoJtGTna_fDOGpFQNwC% zR60*HIcX6Mg~3!y2fAYk zm5e)tzE(4WvJrzBM&0OP0X?W01KZCqdF#$Fl!OO*X$~l1ngp}#!)w^v=O4^u((s}| zDdToLN+%|ppu3E_V24g5SxsidU*+1=@*jF+04p?Pu?4h>>gD97QETW%aFfWrED13j zcbK>_^6RIx3jHNV#F|~{;NJPWxM(tf73{D}2N&)D=LjWX&!?4w> zTY>Av6;daiS${or7pezEA(I$IUxbT}d%Jt>@)#W8#_!lGh7^MM&R8E7<884RG_Pi7 zakurNYzT+>Y@bh-0mR^okv9qfKp+KnVUn@n5?18J%uE0~gwx!`jEG1t+EX<=VQx=| z`@F^}ohPY8mf>w+Oo*fxL}@KffdE(hxaNUJUH{9cJjq0a(-^Ohkn(OhTQGvyJ34~+q7RGnsy|HeYlWH}ZZaV^a> zPfD+6VPf~oIVW%nP8eB~NSecWBXk0R=3sq0QVq(-q7%aZ=1+Z`;!YNEFzhBMhp3Dd z_nYC1bC;5cwENrbZfp^C5%BG2`73ycX6r(1s4A2tLvB>aU*q_ZTpMr-&tFK=O?j{iSWozOg7Z8_I>Vc(doQ($Rb4O*;kNh^i(KWW-jIpiZIDxs=0Try zk>RU^E`SB9905_d61>`lYGs6JoCgN(qmweB#I!9{qUzK&<%NF`yF7d@!@FTH7t;W~ zwKEnFu7tB*O|8+U$f={x)f*;ANz?MIQbxNBCz%P$7DgWzrZE-MO^7RR#CQoYA2o#+ z%aukjco%B2tmiXPeIBfZrpoNo)fbRPMbb@Dm!gUy{K{gkbhEvP$I2mv=AOcnwu}an zW)(R4Z;DSsRi%M}rSN*vDDs9v&FtHlfdGvVT*_Z6*sQufmN80D53MBiWiH{V%W(yRldIs4NJtneX0b_bLCbcfwo-1&k_O0^ z3jw`FO|QUMXUN2WGisw&INMgp;AB*V`1${mF4+_j2_rP5t}oMirqD~&A5&ytv=E_@ z$WAW71{$f)gjPU(Nv(9t9MhWLKMGcg<#V=6rc8 zWo??66zX%4xkH1TqZ*xY179xzx0W(Kp1{>#AN&g7{a{C|Zgbg>R3WibjEL;e-&i0Y}=Ap}` z&4YHj^4adk12&Do~ojQF!LY&R#gkIn@tORWx8ha0on9yqv)A=MYcK~r_I89q4h z8m?c>Ek6P@7$slJpqox?Y2Pm=NHH<@{c|ormqgKgiFPP2duJ#TPvpFzv$60$?<8gM z2rGK81f}x{AsYKtGC6?7hQ20NocT`t>Xtj}yT%|QjJhn$?9`Z>=+yQ=0ag{?bee-J zj$f^RKCIZ54A?UcWH_wSx0lJ{WO2TeZG_CBoR>Pg4u!B34sN(prP{-lv7{-e(Y_EYUY-h0_4dRfZyjz|=ABfU)WoI~k@8h9fplLSi znD8FM?22^SOl$)u1CwZn8kuOPhoSr)tCpkui42~YhWwVRyQcw?I6EI7m9heMVeH}V zseS|Pd`+Ba-sz46Lz(OqA+7bcmbbKfyLp#EDjEh34T4p>(;Gfkbw0z^l84=PZ|DoR z{{Y2*+4oO0zv}y;lQ^qePBbT<5Jf0#a(U%G&OtWlkSW0rvU{uFjzTP1JJoOnCOYXzYpSA z_L6vE+|M#j{VR4fcFbM-r0d_qQcE@u)z5iwb?msCJov3A|HO+f+2=y;;fE(O zD;Rmj4HcWBxHTE_-fg|m$i4~``lEjNt1FZ35LBXd6D`#M0;78U$&9>(0H>#UCaibO zoXAd3gQ@Nbm7`H!PLg=fsy&fA(fl=crLkwK-SvCb6U{AQ@TW3b)2mrQ>T;<&(@R&W(yZerN z2OuL#fWKr(9Mji-RWmZ3IoO`(s_2ZU9+ju}h&=$nAL&;JvT_d#K|NTG2~HeOYOl`K z^Odj4OYI(b^-2Q}YNZiZorzrO1>S`R+j03$*XwQ7Z90)_qGZsZma8R@9&9NSajUKJ zQf%B4j|Aq>l5=qFp7=vI;-?0QQ(A2#9%9j8FsoJHdEE7m$k#c=%6Yg|!Jq}Xa;(-f zI+N@$_Sm5nl(#g^@5ilu?+w&yh1qTbe+)4|t@JFG>2&K*l0942kB#;%XD)mBJl z7yWN}pHj(#4Y#dc!rs6X#9;4PLfniBMtD@VJ`}Gu>gV8`L|JdV3_Db4IoGcSy*a1# z=|)n?4kv7+nhuY-6T$UgJzBWe-uiM_>qJhRPtTH~UT|jws_}5pv)vizVCbzPP_{hK zYf!cHC<~lvOgIR4(T({B8muQmHqA4&RU0f^CF1s4s~wyLu0_ZC1UOF9Q&P2>qYhX7 zm*Y68Sog#`-sR2&JH}n(zDM)~XZyDJLAB^kJPDtGKJ=*}^Bwyq?K3s{ z?)5ON1C)m{@QpK$r59S8Y6oLl)dfhMrPrw1EGKYocB3+!>`=k-a#%;XSC@X7$ICro^+C#A}(;aw2z3Oo{ zUih&>4iNQt*}Iy7q7JTVz>oI61K^BSsg6e11;e2w>JFgx_|%-QpGEv;rWs4;Ig&Ns zoz4~2You3{QrSv_W?pVQm|JdqXb64mMKDb#a&@39=udtB!zjnq7%$g%bzh>LpPb4} z!QNoI=CG^QpgQj)gTRw#;v3yq{8;Bk9bvLfcYR6hv4$QM#wZ)nEX=Wi-qK(tegXex zGuMpsP?r{C=?D)uUToZKOawWe%?1KplRx)F6T;-Hg*irGy?zwF_(2iFpsa%BJu1K{ z2XhN?9nSaVIVLv1H0|-vxOV@Z`nLVD>h2WX!AbT3mDW&GY|042iXW!LSjr+07<=@^AdSxU89z$z0&Q(ZM9sWA!>Zk+fXSu5MFGm*@qIcVIueH$+9EL=hW8(!#Eol zKz{h#3o+$m)hiEBvIMZ1_JR-l)^_#(uY2{~Nw41r>`h$%^5RUSv{NO(KrkOpMMC=r zvMT|B^j9WRQ3JjhfJvqafJz!FbrOEm|MH;aqHNV+O%YydqJRl{o>~Ncvyw(->7YeT zfFb-OydpL!tvO}(-c5Bw<0w_x3Y%c*UpjPc*?vZjzf4=N@zu}DzdS5#>&u#Fj ze;8A)q3KdSAEcD1M$5c3D)B*@rCn1{du@=@ipjqGo)6 z<%bAkZ9O{{gg{D#e0S0icKc2Og!`Kg2@UDRtWoNA&$>(VrMyH!-drQqR2~vNq4cHE z*_)RmQLPLM1J((|U1oR{Tyb8w#AssVoADJd4;p1x+x1<=!U5(0w=Aa-ZUd^)b7oNl zVWdtmbAqL0-`Ap5U(R9spAKf#aA=Bys`;@|7nrFK?%GwjnF5q*(=6#h_;tp$LJUNQ z5I`q;n+wP5bOu2K%iqmr=Dmy>@?Dh6@ zMz8?P9LUfQ!vope26Cx^4T$?=ITKyzW=r9tV{UcE_vZGN;sXx{^I6jD`6`TMth@(e z-~q@bZC~W%F_1NXaoTMba|BhvP!t|&VT62NSknL>>Hp5Q9#)*@_T}qYmh*B$NoH}e zcP^IxY1-Bpg$6a{tp>vvl3(~$@08xM{6zp+2A~nMX$p^wW_&7eW!NaW%7TE=Ava^q z#nIDIu9A~bjMkH`YFQnNx^IM~Q>>ZVSeQ0Mvyqd9z$739q)QJ;7L{7Gc_3hEIhV`? zwb%$JGSfRGA80F)b7q7vMA8Y&1UOEdjyf_p{IhRh=Fsl1$!c)i39p3WeX9=W{7lx2 zp9-(|M?wW(F7BUmWqD8{RAZ>12?;u>GFfi=E5KM(Do1 zR+?YDBa8CGhX&QbITWcm7C>-ry`K8=cmT z%d_hbAM=yAb0Pd+x0Mgkw`FH&XoHBGu}0Zz#qNp^!T#K1v9rH}sP|N|~v%N62tI4la+t- zJqV9O^I2SAbRRyIq~^q;A1@RE285cI^LN~3)f>669_5arBQ1u^MjE%pSvNC%$Af#^urVk21vyq>|0M_&jKfv@l=>L&n9N<$sAV229 zd+dCez!d}Qqn=)l#|9118S1z&MZMiPFzUn?W*S&V-Mr)Q4|QJ$%*17Wv{0-UN!U6C zrf_(Vf<6Y%9u7aq2Ekn{j$za(KUo$Qp^Hj+miwlyj3n}^$&6AH4B)JorvZ4^NM4jm zgLW^pj4T3k+hAfDVZzxydQCs#{6YN66)A2|i zu`{OHI;3oh-}t@PQ|6w>ywRH#euavfi$xi=a)mB2=CcE&efXcOK~8c*nF3kX=Oshv zI@o@0j@v6TQR{S6pmyLgL{6g>^@EprNi`JDu>)Lv0=}xr&(6<(V!2F)(_gtY8>)p* zjEU2`hEF%#skvj$-7BTyuHfxqVaeHhSQPIQCHH5l;rZbHsd#58@&@)syNV$`!-M9G zoKpwxe`eh+uSUm<0TJlkaY1LQZftK36LvRkdOqv>V zmwh(jHEX;3IO&#l=8q*|<$js2ZXsOU14rpxZN=_QtZq4GpRtd8{s#alPBbas_-@gh zT6^!WS6{BVzyAxtOEwG1U${F46Z;)?cf98>UH6%P9`v@H=)lHY+wuh%e{l4QrT3Pu z*IYi)mebFT_kI@cVW;wv&FQW7h0dk+OASpvTxmS`IJ=_j*Ao(emPw-Redmt60vx(0 zzGExMV(Y27>eO}z#Bs+5PROx%$FN342fsPj15)clgJr)rya(D;{NU9Z3*3o+(|^|b>&xkCAyQr0%AkG)eH^a5 zvmHNp{guB+^WpLE3sjbMt^p2>szPCYlSR<^Xl-qwTdxd%``1A&R%XzP*J}(cW`Z_HwXAP+M8@8SH*W4 zkLqvNMv>QcN55aOfr)9br1GuLzDjkvm)|#e2xdnRZm+d+j?=mjgq`Rwl24Dx*2Mty zE)`!)%!;@gK~JsLS~rV>7o!h7zD33NnQHEclBhJ&O6KS)x)ylTL2nR|weoSSbRC## z9LJ6qD7u#$$7S=ViYe$s?*VZ5USru#DvyiSC*sPtP`E!5y~%QPRXlRq_Ok2!;=8T? z2p)OAPwCw>=v7-6qsq7b({2#K?PTm(o~bqUKzSo0E@KHq2CS8GxMvxY2LO1#I@7R;a$zww5Q42_w-(Sd9+0fi<#TwQR4>VRCwk)cRub|Xct%r{f7y2Q z%8W^}3}W9PFM-s7-xJX69&@JmSqIyLf!WF%`z&$?`&NnDV^4Q&0p%{fR{KRGT@|Bt z25`!of0-4s=sybhzP&X_pC=)LJ4>Q`nXz9ljW`&2?33R3(6ALJ#)FUVZRKwdsv13g zpt9)RlRVh-H^Nt7B3cihm48U2aJ)&K_4F%FE-kNMfoTiB~gkJ-D~WV`||oT z%K%cjdoHkVU0iPmIn+A39>;^Z;Er8S5+3Ym^ikHU!LGP|_0U~$eYG(d#Q!cXT50gj z@tDG>_~R9S)B0+3};^4LrTSZ5vJlAUjAxR83ezZ+mn^l{Ewg5Oq|^@BowsHwN$ zG|z~he~@(idBwc7*dmLPqR=mW;s>-N+QknV!b8?u0pJd=^Bp00z+2YAhz$szh5}{9 z`Cxs#KFrGF@KV=FP)k{?=}CAt{7I8bV=bOM?o=PP#+&`l`ic0WxSqvd{rQ>w|MLjz z|4Wmi|6XQR|GnJg`=)32f_MDefpp9r-{TJ5RCw4a&$o{kZ(TVMT}~z+Zyl1yi+9Tt za~H#*cdO$iW_TTUO79V+n;W+|tuJNKOW8(HzZVQ}sRkwv+Jdt)ev$d020$v!$n+=+ z2-YC(?Q729scSKD}Q`M<~{eEWy64_;^bKAJ}m!D?XoiiC#Ya z=iH`$;JknDhWMtNdytx&I%?-Ctj4JG;q=LeZ^E zWnz3jW9y_jK+)!)?_sY<~YRSw7@a@UG7krVPUzgcz9xVu6bA1gM4 zL$Z4|k%4Fw+pMP*N*EprFgo+i5Tql~AToEJhW{{c)K_D1tMX?cz&iQTnqU2?476jk z=g&7^Nd)*)fU%kzbStn?UHM<`GG2_$(G~xwXxuG2XThzUQp0^IFgs51OG#XOKoYr$ zOR@Px>@+S^hm-u%PHnU_tqxe;VE{!Gfie8ItxzdJA<>$kpW+jL7SgH@y9=C6dxk$ zQ3reSu8rc5Ma$d~A0C#~;zKU`QeAq)_W{q#dylw5lpk4{x;3hmPSq9y)vsV2e*(zDaque(-LKnQ#~b{utF&=OwT>{ zg7;?C&wSK9(uAgH0SwGL$#CB34y~{$Mm15e%ThvO=3zw$(N(v@yfXOGxjm+Pif+6s zaPIlM;l9W8SKd_vH+C-#&km1YbPupe#^-)!{&27q{1Oizv35jvXWdKZ=bkwht#ppW zz1d$59(%Oby!&h8)zN!G_rbAns{2gh)UJg^A@+-t)0Hdg*LIx@A9g2fDAl8IwkMc^ za$j~biJM|J=&Vqo)M=}Mrmy^y^Dkz^wm~=BaxTn;Q%O9rQrc(5Q}a{ZYND@H-CX&} zWFzj1v5??(x0BSI;aYK2yt46<7w>Y@rP}y^6-l@;d~w@t!GTHTw-$GmKG~~(G|^m8VTp$uwZ`$rUYQNg$^*OJcPzSaA$(C?X)V>7c5#gb6)z+;^`hEv-?VqaEPvij zm>};s(;=pHrqSIs|G>rMfm+B~3+04FquadF%*pksd)(X0(p?#RT8!rIaX<6u{_e@d zc(^&99YVWqn?50W#ku*?*JNCqm@cc}idu0d#^!gg6`dV>%O4c&A^T$dpIPL{ZRIq; zG#uv|^=a97UgcWmwk;>;A02bZS%6T)^qdRx`;r{0f9_W2$?^pO?T|468;m zoO7EdOG+l4k0s1mxy`NIP$6B=wd(Uj4C3tzPJM3Jo$4-zNf$gZ=QZXPTyc?+Ys-hq zW6HKrhilnD!YZDx{=q2^QQv2h__yCkPHEaX8-E8(Q4e5v-~PB7N2(aF=I`9Np^?oif|oZ(BBq5!v=$!ZIr6M#;D z4#os43%JG|Kfx{(Ot`H>^p1e|t4@WTkRLhiw*=<3F><(ZQy_p0LqogL_%$F!%4$N% zYagP=lho5sO}DlKAzHJ_8$b*dc!dw(k3%k;kDCGbEE)b7HtbN)D}uuYf!f8!+f#8o zF&pd)gBy+Eo2n3wsQ}SeFdl<+gFxCw)HHRiAd|5SkGep0D;jYQ;gc1^lq?a3p%0#s z-xD+>6^?nTubUypns6!BcYzUr*{J~AfLuCr9Q!SMel=lUouyzcN(JKWl#s1h-*4u@BkFXEy?jI;&G4-450dl+J?-%BqFb>tJY%Y)m_q z0HjL)418`ugVZaVCaHPMNn?S}(O>>fAPv(H*FHGy!Iu;`xFZojurqYHxTJy32|H#B zWkbyzN{g0eID>b3Sx%)IG8gNC=HJz1j_@B$k z^D(MSe4uw@c);|`$n$Bt2u+%aJRt5Z=xQ+K&1QRj(TA~fk+FhT5rqT2xaIY4gw zY_f7Gj1(hb0pWa_+fKrX(VVd$lQ$$Wy({M=a|~Whh47XmJ&x)B1|JC?8G0lb4hG(G z{tb~4Qfl9bfW3n{^Czqz^)EQCy+xW~YC4ThM0Wv>G(72Nrm^g&Br$+V5$lX3mWZ|I zNL@WY7pJ-VkPw;&IXY%NTFI4V)EDU)aFnP!$G895%nY><><5%COshIcoZ|S!ZAxDF zc#Fh=J=A`N?XWwfNSLvn#|xUr2V)9_s@IZZ(Xjx)G3heOt9^`;8{oOod{$tpw}DlI zuk0iv<`YUqH<4yy{(GvoN7G<05g*eo3}Ei*EJz^^9K#26-tvnUgFb6w(X+fLp{k)R zz^Uu(881zvX%oy@A`TULmR3V!D#oXAQX!Q(8kmyCG^Zy1PxjtEyp8KV6P+226~uLW zF{2SYh8YEOZ~zTKQW9xeMw!IM91fuoOi3h6yR0@%NtlvZ)~O{~c2wW)1_wAWfe5Na zn$D`dxf>FKRi$xmY=xWk_O@G6rV^!5ZX`v?s_AxXDRSy3H`z$C)!l<{N@S%xxK^D$%%5I znJJVuu3RoTiB(A##&B~x76vf3Hk}$#VcW$*xanZ2Cth*Ic!fm^mHG?lEWBR2*REAI zAHc#tu`qtHrD#;bvwVu+(gcdJA-@g`~exqGFyC; z>|J}qH6!W1EzM~nz8Bx0Dv0vNV%_+Pq8tEwxa_n)hc*?BpwND->U*aS1FtN!b@-28R ziK42!=-|V_d}{ds{5-Inz?3l>J;~gZxJ*{k8}bL89)xep#b-bIy7#NnkNvsj;fW}_ zI60h*KFTW}-7RUegS$X>To^t*uqcHLU;NlW^je$!;!eq-UH1mUgYNK#CEk3k&GJlf z$d>SOdH8gTgjuOK?gKDW1$z}_#zkMEf3+)kndXOr+zB_n4B)1;7qL*O#2*k)|)?8uRT zfy@X_Eg)$;KW82_x`L_8r7zihaqsmve+Xbm#@~d0`@}~ai75Zgnr@`|N9);oV_o{x zfkgA6L-xO4`4tIBn}5Ik0VWaYbI0F~F9Tzb{Ae)MT=Sr@Et`5tIL+VA@b zFzvcTmmfNlYThS3>Z>Pu{ylKY9e(qk=_+#k5>P>z6Un`7`p=bt;0`q5LVXhaxr5|| zH|g7^oH?PWXM`YA-s?HK+dLSDLJEuXVv+Bv;DvRpy;< z^ZODH4F=IS&{$H<&7x8*eUD!fZ~MMBC$%Keapyo|ce$@c)eywT(F zCUA5B{te@hnP{NRIoE>RWUBwWuHNT>F}(&Sj+cOpJ>vx}XluB-F?oVW^dG*@UkE_U zMf1xA9TR<*__qY=6n4nUMrJ+P8L%qy-*!KGu24S zbh}U?otBYgr#YLVsM2h;X~e|aE`&XYK|%$r*KJq&*v_Zyz$D`su+JTTg;`QC^aN|7 zCeJnW6qIip_f$f;3suu?uIEd@@+$TLc4FTn@bowLEY_HG{l4(BCu4S${hC6TvB+FTnM9n3Xk^+CqsP0@tS9h_E-968#&C#K);iUEBC`lp}2 z-)(jwg>@AzwSf6Ow%|*L@-GUBejdnaDMt-p1!7|*G5-*jm}Yb8SRM^DltKFa*PTmL z5cYRLF4i#G1p@gTva|f1{eL;+D+kGrW$$gL)hjF4F)(7(afbcgj$WvFjsVrp4!r1? zv8MBl$j1j+G(XYB;!S4@X7M2(! +rGq{5Rmt654tB64I{<#RTL<1+h#p0PFgxw8 zW26CI+#hZD$gB7?2)`QaRAlw*LK3?Xkk`hFeTuT<{_7>?(nqQ>or@I3d{}vt!iI7v z`W*0EjDH}x(`6HdMfkD zo;%(fzuIOEbZQVejpwU&P#CHPEx82-!+@LmvaP!K$aiFkc_RpN&3nqm@j_Gu;K}EA za|Lz~v*B|nI_UG{tlQ0|R#RZtl>!!JY5}&p+?=cIG(%a4z@jN_hL}?o^#ub%}$eQZ`Xlp%LLb(D=w zu%w~K3m;W`p5f=dD{{gL_F-KW{DAc4u?Ft6H2C_b^vZcclgnn15?FQ}`l8$z6xFr7 zq#@p{aW^Rp86PT;tDZNN)V8nOT_CY$frxCQ0L*>r7}(RP)nis}^*l}KhYJdPR+ogU z)F>u@nDpm;yVx8?h?Z3}u7g8N6B>BHa!`Vn8kUy`kfjFs%=w-ddtS2Z$4($&Xup^n`Y&DAbvHu zCY_s%=Ec!P(hHTWmMwKFz0VbGO($u?SjR#gEY0imSq&Z&LPJXXF`EgYqy=N7nT3ar z){c{HfX+NV$CNMnuM$w0;h|c6)^sH>PoGu0`lIXnQ=cxtv47lQ?Rw|(N<7I*i=?^c zrJ0}rzo*>wfBu27s@ycFj*{V6rc2ImY#D3p*0L5khYQmJ*bS@|2?yd;0t-dC=$6}B zl#Z2_?{9_l!HOfs@bPu5kVS^ex9!4_pf}cj^6!)VzZAJ}zf|ko+X|Npz+Xns?fvi7 z>iqu%QT`w2B0mq?KK_fdvE^vlcqDL!N;PB71|eb#_r>5|%eGgnNbBhce3T;>Q{G%8 zvSRu>P?{^iBDgn*85&XQ;Ex3Q1o(V-Cz4|TE6 zf$*0<^9cw9+5xr}@)1*SzT#Q#2k<}(!;^+S^nmd{ZLOUXg_6&l`@~!M_HC)PJ=PBD z?T_xY-Zakz#wc%FPDdX1L|0T4)jR3eogH+XJ=i<={AfkrBDR`s^qS?q23KXVC%WH1 z-Y-&o#tx=|L09RQ?B3B-6TUB_g+84<7>V_`bOx7O1P;&O7 z3!3S6eu8Nz(i*e>49V@ECqvrg<>;N+n{SJE=SPuH>6PFhL2cFtx{f*1%9 z1amP$oRNC3+rOMPw{SpTAUal81H~X3kE7 z^eT$yT`hB(gv}F>Q|XArG!oaa_Yct`Uj?8+znbttX`_%h80P$6dal8z*-+kWiwN(c zJzg>*miC%=8VIU~$Sk>%VV|bU*f_p69E72pxZeBPf(LKFd4OVofd}s$om>K%J++X> z#H($xL3un3!V56@PNH%%4$RSH9SPQDzif(`p0M^gj4KG=QpWrWsc-PtLXlAN&)`f7 zuRy!YEza~rOWm%!Avk(&*ZcheqK2dPsLKVQb*gCDPFQ&e|@NEKd0%OLuiAh7^2Ua;U} zE}W9HY({6zWVL$~F4{TAtCqY;U|bG1x!C)Y{L8sjQH`L@&8Qg zF(PKf%w!Ph1dVuQ`f<9q}5 z-U}WFNj~L}ZhJJ(d9>j~e!xrPiLsLX+H|iyO>*(_%;e*o+%{_G(+K!Ulmeso2R$hy zdS_{2+?!AAIKOJW=iAsf?lO7a+rpjorO0kiJjnQ&;Zpj{`10>{w=L9X>^_*gI!mtv zm&VC!J}vK0T@Wv1%i`&vNnct-5R%#i_V;t{*BtYX-&ots*PMmko`8#j=N1y~3aH6| z|9kV(AsXNXObsD>9$`N~R(o^g`)24j_lGxISIy!+$?YOPJ2>3?*>kbwOBVM<%&+%O#)!^726S-n6~l zPRCT&Y+uu3*DwsD;`IuM%)$=PmDH4a&{Oh+6;%m<*2kIh7ZnV*8J~62VWrk>E39a^ z<0WAXmHJUzVx3E4R~+)_K&Esu2)Cu%JYEDHKBi$bSqYRp6gW>$D%sVr<$K3zzX3D7 zHEYtMPD61VadYb8wyl0B3yEEfS(<l&%y zfXh_J4NCpc`qN(Bsm?v6ooz*Z)KPf5dlAido%b!tUTR-FV&{SsBrmNbH1sbny~ z6h%poX)!gX$2cavaN1X{e&MT1sfa$9!H{e#1EC?uo>6coOj+o$V2V??YIyBB#z33_ zB@N(<5=ER8xIY(y&$DpwXCRR_vr=$DSuZ3`M_e^h3aRJ)ndz zo@4^7;3*Glj35Iz>;O?!;FwneE0`!sTJeiIYA06GusrwVx5{7sAHa;~Ay*Q^x|AqV z2>`G*1S7N|wvH+lf$~|Rc2TYC3K?5Q^~Ee)TdoTf)E8BW6O(0t0>V9mc~9vl zidseoeIEy1OepxuRPK8fD0DodJ45CWR9itEmSQ4Ya0)eAg>ViY_F;F0dw|ANj-)C+ zfuDUwprBzia7ST{0T@kUw*{bjp<-jOQmn?!J5{Affypx|QYY6Wn?}t*Q5;#>S6_G< zi(?y15L_e%%M~)=DNAjL-llp*Q|`5d2@?%+ z5ENC8UI4Q*T@71sYsuWoz9ci_#^IjACN!g!KgDmus}-jR=-EFU1$G=ml3;m23KYsV z`Bz5mK(O2pV zS(p0IHAY2mLJBjQf@O-Xc;QbW;Zh7l$J2{i()BesmFN;1Z$-%_5`LC@3>2VjBn)p+ z3~*h*MX-m{W$P;9gYwBgz3o$IXN>j}3=5S)$=+&&$Oobu><=K0;MYv?oM-w$+7;7| z|5dVyUZu9T&0a`nFNm2O86}_dfv?^%?R%YSZQQpz91#`H3Utnyd2rk;zkp89hk`@o zpp`u0V)OuJ3yYhXH{-X#tLb}`PcQClcn2fEGqD zn$&aKu8V@gYvW#`;O#O;$sW`EC^>8nIsRJkPRb^38@$=@Zn%;9B{IIemCsO-46d9U z#~L}E;;WFLkFQCr8)0 z0XBdgmKoh|7liu=RG~VZD^AHv>E#7B&tffr!8}aIIElrv%?rqOH20>Ng=7eP_r7`l zed}ODTW3G#4JQExTM|0v!@;g&;2;Mr)rCr11*FZ>p8ZuWwF&IDQ@?c3*y0WRQXTYQ z&#YWLV+de#Rb?6~ielW^;(L9Lw;F0k7)K&j2;yhn@#Ot5|4OjgOMS0wx}{5ejSaRK zhH=h|Q>9B?0Cfa9_jvX*}btmRkihko=4283r}@3!AbEcO73eB*bp zxdw0fQyUqG%ge);!Q=(ZyqO$av#ss1i4NeT0~dGWr)m3z8-#Uv0HAKrY{x?fjpZ#& zzI=lPeP22<6PyOVZq-CH9tHiluMA4%NVW3a>|zfj84Twp1v$++)>obZKn$oC;A6aL ze6>2={HKzALP<0sMZ5h`@RmUl0L;JqMzUc(X!w%*>;ODv$zvEYF$CeMAuZZZTCyz7DibacdMgDiy%a&*wJwyjS`Mn~={U3P|lI4GZwyWpp< zyCR>hfjLq;e+Bjc>JB{PH+!W*E@PtEL3j3#3b)UDCJV07xM22<}j*IJR9 z#^^I&avy?B!zdSBtWSczW6l?H0XVN;2s)BxuKl%ocdoKx3cr`t)|}9c^h|FQ;Y!A#_J|2P=(KV`xt>zCm3i)im&Q%#b>}mp%3BZ+2s1?KI9C7(l(X zZ>@1aaYm@F-jBpP;!u}{{^^Lgy%|*`MZseL-aYJH`SVr#46IW@mFiQ95UUU_)-Y z3!)~_>+OLA2^y7|CNK?^ZriollBF?(DlNwIyx$@`UuTTH?p$MELHR@CVQj&PL1D%QliSEFOhnaf z(oX?vxge)6t>pA#)6axhMt}WN?-P99GQN-0m7D>+Hly zN<`PQTN`F=xIoe?rvTm!I$}0G?ajj&3v`^v2n*&4J@D#7a4T#o2h$}X` zV^;JX*RD*_04Q#!Gso=8W&c&yFgjI?;7uMUah0Uvj`(Y?Wf#U%YL+I@IF zc9sZsB&YbX>w7;5C|U8a3~LdhaXA2iXF<&1SeFTGX0e{PT&&M{0BSTryen+ra7fCg zV;4|z48*g-DosMrwv?j?V5or&w@9&acd)rbEE^ek9c$W~(c@#fVs$+KKc3R;jeoMz z>?QBU@AltKH(=%TPrC?%A%C6tF@WWp*8svVz8ed1+Z=%Q1c=N-Lh2g8PT@+r#1@_b zLX1y?Rd3ER#k7~WT~tOIF=MoWBZ-_os16zz2&xn|fq4h|%~()#0u~%r_A}5CwL@bZ z7M;53EvJp-14x)ai~GrX()ZX z8h{1?s(@YNvxt+^slaSrd%@o03O{Ap!Ep~pjWptdk7GcI&q7`YdH^xKuAR+w2QYGd zDL{+};vTh5Ac$py!LPMi!WuMb>*0_I)UopXWJT*I*Ph$EWDOcA22+9NUU3!2S>OxF zfIdmzBx)kxnJg8^)>W>FxU}VEVv?>xeIM%$+AHT>|0H8wW_GeMwd|6!gwL}4LGSYz z5IIt`c`$D3B|Cs5q1SyhKyeGqD1 zu*~|}bYQZ1+7r|+0ZbDh$!{7ht4r`UEf)Za5t5n<>e#Q_eDjeJd$8c}t%mRJ;`M?@ zi(l*U&~9v6J87CL!ryJ*SbKVG+|N9|yw&(h=WFIy+&cFPyu<51=^pK!s+~-q*_RLP zTj_Z^lq)Q_+#mE7Q{JD^WYnsg82aq!Brj?pU%^M#*-^4)?fNPEkt1!j>vq<3@~?|o zn~CBG3W(=<_RW&xogRhE?@n#>=_B^;)Am8DCwV+#=JWO=$DMTnT-9r{qo7`?>>ypT z&28zF^E`wxFlc~!)t#;{IQ`aT>Rm~8Tjk{Ssn03O9-A7~9=Fm9IBHTXmuGVaaYu~@ zVvO_LdBInOb*Bia2b*}dhUPKG?XxAdtkn$+^oJ}tMq-Ne%}EY}5vn%ELCDC*V9`)g zbb;l)vH;w|0lr}1+$QlL6JATe+J>0zv8w~sO}&0tUry*$IRn=Z7_6v*R=PU`O9}|H z8vHa0p4db>&HWUi4{dEZCVFk`ZWOx2fCp`2fZ>W%hs2MI1Qapx@E&D*3m$e67^Yrw z__EY*F7lp0DPHD6H^H^gF}0}0LP=op1E=pL7Q2mPCQJY2U#MZ^GCZg|5Th>v>Y{le z;*c;+0tUj>Q^u%JVj93f2Y?}fA;m9J7(Y7)G^`GZDx@$6aAUxTF$@{N!xe(%26&sW zbRZ4jaGoinlL9ISQWm3{>jN}v2OjoXk!UWkMIfsT(+u7rzST*}l1B!iY39OjMRx#I z6=CqsWmJ36%=lO`3aL;YdT{nWr<}LX*UtOLnewkrxLrvilLJSV#XZG zZ3@b9ftm?SzCu)@z*^vjwJ}jC$=NTa3hrRGq#&Ed zbculB&Nwj~%3?7E&^XqhMJ=Zl*iJ%q1s%%sfGN*AV}498>aPp#1^n%YUIV-r4&iJC z*_Ic;TXzYZ!Z5u}QAQ!6VZcO50s7le6@bFGy%Yryei9(F1UO?F;+P?gkQi3V8hoTs zHyR2DPBA@8G;9JqGBgJ=yAU~_z&Oq_^%aCfx)Yr@4yLNSd7F)E;0joR)Xj@R1r7|} zvTUF-Ey$)K<|BZ535M333K}|+$~lH#tRsu^)~Hrl+z2bEVA1;r|ku3Z=f|v}>lj39ckW8FJx4iKRwH zlNuDU36!n`isjl?-Z&XzF|G@I6^ zdb4g#kI6)f42EenhKs|_0qb7OA*^bBidN_fW9=|N7E##qj=Ud=Lf$#1XR9TuO`@p> zPN%QqTo?&`ggDdz0w+S!#_)NR5q>It5U_F+KF+>bxsb2d9NAQqP5BDG)Ra!47o~kh z@{|Easu0_N7Z$n&*dGi{7UL9Uadf)-&-FHW$cN>QO0EsHu@cI`ITiFt^&#wVOjd0_c57;9nPf?+6J zg#?D|JSjb@OTbv6DG0t~AuF-Tj$Vev6PS21m_!m|h85x?_x+}_36f8avVex-p^3z_ zI*dsUjde4wERg^erGx`4XtDXwNQU@TjSxqfr=y6efI5hwUlh^I6|^7u1s+I+7DJtj za23kp3y$e0bg3Qf2>a@%55$6#ZW%&+=%du96m$yILgvkev%G;N4?z6^g&Q@0*zkPf z>m9I>bk4X~-3XA?v34eI=lA(#VjT(MUn!WQ>nrV79MY2)08nBHo^X-~Q%2A%O{5D_ zMw9cAT7%X_$v7FXRN_T1zLL)w{@f!S)^_)`8Txr|I$?I1i1PU$d+q!Ez?Z>~j?QM` z&Q%!s*rTz$i-}+1DbKbKxOunI<07bntA#Hzm6y9+@ftghd4g>rbja;g5g(6OdD1LT z@PlTP@iIG-b~Zra>OlMxppMjNIbNaXNHY;%RZpncoE@|PbECx+pa$dUO1`KTNZlc; za}d3S5Ugz}%{|o^%TJT!gXljatJ&qEDzmV=gL|rECB6XxXBX+c+8@E>j&gnEp?Eo#y!9# zuR~GyG&Bq#=l}@jX~gZSJ>lOZCvPmA=-IMw@Q3UKgnFYtz5*)WJ^#wA{2gibz10?d zVgeM(c;q_sJ3uwwXTRz<3xD%fgokS7pKy*yQ|lzpxC1=Pn_3?r$wK<$(!%gp;*ux6 zHyS3A>*4pMg{au%Qm9Kp4kSH~@E11W}+!Q$U~q3paYu zj?KvhddEaB=>ZzMI|@zN#X@q~q*K^>_^B`dNXwic z=5Y)dX6R+YM$af>4{iEUl_(;P^F^c4F$qi?KXuSt zt_HavbrSJK!BCD=6Th>^I35tM5}}!wBK23D7jf5FV=nYnoPU0Pbxr zvSabe<>p)=b>6)M@b?%Q_%fR-93-#%&54wj!vXe(e$*Oub6+OVK`pV%k{BGXm?sJl z*g!9amEMAKe@-tp2Wo1t6R#7Pn?W)*U>x(K3xKg(Z&~zvz*$*GHnWp-^n-0&;=`20 zxk}t=Cr-&F$2+n6SU2={92@%FbWT3&+xjyhXr%KZEM$ojgoQvrna5sQ;=w?x3DGuA z{BZ%#@;!T#F5>-f`WOfR^W)o=w#CNe<^oR0m?s#4l7>TQ0!vt6y4VN#kl@BTTfVjf zZD&aD_7w)z5vs2PYW=z+k#0M4f+f`Ty&b#EOo^&+W&pkRaH(IYTYQEXliobcqu$m3 z^w&%1L0I6}(@q%bu`>h~O@;>7u5SX!?fqb)sz*-e*cks@FXM+98GWCgl~hu?r{iy>?g5ii|xyW;FtWDWK$Q%FizK+6K3=r zp(XDCBk!XhhDl~ma*hpEJ6L9lk{%p8PBZ_3;C|CI;OH8E`Q5P^RX8@eSWa=QG$mbu zD-siK#Yx8+aEQnwm}U<%tS*;?Tw{uaCY=|-JeKE3I2eGhq7b1FWnOMD2Ds)+d18Wv z?;&gxBM`BRfJM%gU)KJAesSbt-{L92!1W)ySNs!HV#;hg-BG$`izo2S^>^IZ`@!}_ z>p9{kLkJv&<@p?K{T;UJCtSy9I%A$^0+$y>&(hXAzJpB!aQB*{g5rYxGfYzW*I~M% z>;MUdDwqli4vA_ahFuu;CcuCXs)H&>Y@-;A87?Yke-?yEngi_qp|Jswh|QdgtY2?K|SA zS?_4LJ_XcE-e`Hkp`sCqQ zDeP>JP7_hSR2p~6`huN(Q*;OG3M|KWm&#Z871&ND1F;Uuc)bDTgM~i;sf0fYl>?_A z*keJYx@c!fsjsRUv*W zl9T0F30~U9?W}y|*##%p@EC``_CBCAjc&WBujjSWIpUqfe4a6@J)@i}Ux#!c0ydHCv0dcV0T>BAuFA5Ecgb+Q~`vkZoqjM zl7$XQgVcW7JxEi2XcJ9_!iz4jIs$6@IPXD-nA9b40y3qA44tLt^;Z@SD_1Yuaz^71iXfk6{aw*o&i%6>Md*Zb`He^R&e}r zpD4)_?%LDA1N-|mvt9z{uYMBni|h2~b94<;&vvR?&Cu4p-PP`hVh$W|F18JOBoewu z>!0A|tZ?-07MS6>6408O(+&qo`}WW2pLfE!las*Bbry_4HY5_NCB_|0`%yDw14P{9 z?r8;Wf&&jIrf|H(1{sGQkua~w&bcuaT${~$zxtr_=(Ruji^FEIrxUu4Ny7RpU#xEk zzTR95w6bmlmYKH9)UbHj=&}5DU6qF&l>F6{$v)4foo$l?=7I&aXfuG4h#`!M22P{+ zy0s~4E{LOKIJF060K0e_RuKTBYtC0jYhYKERlq~|4CK><{2<~MUJ~6_6bd2pR!Rk5 z+ODZzgI3wFq{MFv#L-KX%O0hVt+Vp41^JX`yA&}~QNf|u=+X_LhP8BDwgD70f%DX;$Ku3s;X$su#-6n0m?NH7>~XtBp_guF0HP|MlCdz20=f{HP`|ot8w0@8R)gDb zbKl`ya8ai!2=dD|2e?)@WYD(a$ z{*%_O3W$d=^mM>Fn$qQ0D5QEqFhDv0dUPe`_XY#;JUE3%Ofdmu%|ckbV8}hpvWUb* zFGXX=MV)YPAF%YtYsy!eL<>;>$yP#)T7%syy)n zHB1fP@Sb$EjHWnc;JslJa2kx?p|FpuWBS@>X$~f>n5P*_%#&anhK(RB1uBTp@(2`D`U9*{%0IfVL*9rM?^#z0|cxgOK?fTf>AcfB3b}= zwj>7XERv)_bXcs~sutzCLMmO`u^F0qI?%4J`Q;3%N69QW3KbbunJFUng{mAjB4sV9 ziXpq^!TCZ7e8oy!GCjl4+LohPtqoc~y~45WPApk4G>>`ki$O)8W>FbICRA3-RAQc} zH?S0nuu!Q4@Tn+jTMep$N8w*DEaIp|0S)3uy22f-cv_%04O^4W8e`It7$z379A*!S zH4N7B43M%8wx+@a7P9hDMB+>od|g(ELgd91wEK0K-eRZ&>D6Jr{PrChE#?!roA=%xDRXsRY@nb5fFx7F~k$I<6Fp`}y zh8P7=Tqp+Gqv9kuV@#twLD0r-uFXVDjR_!wD5; zF`-}mk8gzyPgUY;La0otSWwedM^?JpV`j)h5;M?YVLsK{VR{f1!aWIjmJ^YS@nxfJ zpE>0neYiYrrpp|dX`<>QvIG~1)PvH7i!Ef8ZA7vVyw@%##>Kn`Z{E08R2k30573LW zb$0u11--xCW7P;>v&|a74^i_H7;xmF0rVR%3q-2Bc-eFLvrb~csx3oH z9Wp}O?Uw^!8v#t*NIg_=4kr2+JV-8M*mMVZWX_LV@x9)WD80hP2~&L9{F}KkZ{RLI z?hV{yELpprH%uR(vRPR>z1QA(ao9Fb-C5adjaJt-&2?>W{4bF3h>U#MfL!mT;mF-i z<+L?0BiYPniXbo_F`&RaZ4I}B1Zx|>XzdsC{V9N$f9ObbInl?&bDUGmyBTXM>9(1fcBz-C~@OF^zs;=#^+Zm3A|r~5U4-QacIdbW?y)LzKHG|Vl_r@&P- zk+Ga4DZia%cRQcWg(N$7{vI%n2R;H(=7Enrw$T8-{O}{YH%glF#8XZ1LH7>++DONf z(cvo}Nkremiev+qLKbg)uwm>NAASscv1@JXcD=*K0T24W=6`VQPXJKA#6AXm`Jrl? zK)ARUE0Ae_m8vxSbkA4G+4?sI#a4+A~W`@pf zbXvS@K3v6W;1y6`w~H3$G({Zf4+A$vII1a71OY?D`|`DI{yGmj9)MaUK0WxK!Ne;- z*Z05#R1#`{X^%n4LZY>OrQsEzu4!c2?;tzgL9D;whd*c{H{S66`%Hf7k*DwPjt>8D zSBsgo73*Y&sfA6x?_ zbVcIlHlHHMedV_kiH7mnx!!R=-1cifA}eBRGTRkjl( z zjn6jjfpWv~Wa_8^^$&T^e z;cqEbPW=l)f%=ONIDNy9zwzs9qF(+fCw=Na4-BmJ?ET)QHT|P!Bo_6;jd5p6eZeKG z?)D32ZCtEfSOdZFrbR9}uP~hh52VmddKhBd;N(g$n~g%A0DM9S*7CXlQgtYpDsc`t z_emRJ$qo`F_hJw9F810W^gao8EBXNNTNEd7>VpP69?$tI=&u^W0`C5;*&*Km{Dun; zxM;Z_eb|DX!KWPtUpqVyT{CJw+$5Qcca|CkZzI4$<~=NsIpHpeTYN80e?rSVi8;Gi3UM1q|`j5rMPFdBsdDCZ)&XH3N=%&Q{xMTB2O z`}=+=&Y^3e*r`>)=rqqXA5}op3?@_i06rJ?SXC-uf5?H5o{oA8yZ`FxRlr@*j0db4 zgi0|!WDFhOg|_hU2i1edw;_RS3|vH01TwdF0dWpzoU2wOv1Xrr(S3#a#whw1Ldv%5 z75mQ((0Gksqf(&x_Z>vU>&hiyzAD84SF;LWPpCYM${STe&?jnoav%pHok|)31V$iW z+H`CdR1VmoseDyQmAs3-ZV%AXNc9wY4nTdd-hHJ~ZN{NhUg#@d^QAU6`pks$#RuLW z9e((35UYoMD~Wma{%&PJj}8xh2&~$HzjvgVN97aFf{{r(%Gw-UAv`T}18rS-Y=24{ zc$_L?V^WKHdlR=^%>{Qt9*ZfEBelq~2^hM@sXheA8WIqghOx+rb|Z$L=ju_ltoI;9 z8x*b!%6wee;+sQ~0(-Ol$M=9~-7w5)G2bKk(zsER44v6AVeNZ+m4faK^NzDoM$>CL z9|F<%c$fu$L`r6`fS=B#z+T42^)=JDSEapiJ8#2QVoEQno!r}hT|*Q{xYM4m8bQl8l~DN$uQ)_AHj>o} zD9B3!arlPfYY4*zCZVSKue1IRlDXV#Y4ic$%9&S4k|E^~s`&c{@wM$;q#+DFvSS}TuY-m~}%Kff5Ws7!tuF9LVxO|4aEfmS4N&2adc^xe=_V)Q7X9B~sgH?4fg$;oqbs1w-W~N`M ztWnPfwmKBO3$_x|z#hcT7%C7JfiT(DFAEhfgIF&rpf|Z3C5P3!i#277X^a4OHeh7| zsNTdM%-9l;-l~CWJjRvSvH%9ELo-}PRJ6W0{4T(J&8ASUpvfDp*Pkj_+;A(ObdNo4`G0qjpTjx+Jb)#Wz#G?vYh=cvr2-p3 zuwQ@4>K}$uXT+w%Zlq1O{jJ>~86)QIdg4dE8|*W0Zyq$)F90A;d83ojeWbuU7o09L zJjuTRR)hSHm^Lali-Q;jYiJ9Iem4u@0J&uZNdmY4R^S3#@DTR?{ap10HuUP)@`D(h zOyVoS$bFZww8x{UaZmAYzW@2p&d+=;MIz-M?bhSg9s-|CWykCt{c2}?|8sx*l zK)Mb7)hpjHA9Oa@Si)_cwg3Fl*+>v7_tW8^=oOX+5h>Z*6?`}t9ER8$01IkZ)n(f} zWY!!9oR*`n*o6g7YDQ0_Qw0SMZ~$EHW4s%V!>o29z+#vbIoPGFCYA%&o$oD{OMsY5 z@M;59qd1NYUKxJ7?%}q&6E9!l4F?!vxpa>kD|0RR>Lj=R_Q{VeS@3K0i>mP4er}Eg zo?kZ7Z5@c++;F_*JNqFfQFivhEp!0r(Kb7(eeEI2yu)p#Q+~K4c-`US9JnJ4FP(hZ zwvQUn3Q34z7E{4B$4F8h=e$n&Tp)v_Gcy|k3YK+Grsu674Z!=N3uu$0st=C_=z#2X z){U4uhkL*ZU3RC&OU0v3I{d0jlh^*Y4`GjdmaYk^7+4~fJ8PT1=lVmVMPk^-9czVo z8cz3~v-}7=Guqzdx7&;s63R z(E$5#yR0d(_ylkhC@ACT1u2Dwu!|g3|lA^ear_sg!T&D3+zoz0BPkWZjLP@ zw(poLlc7NkU>86DH)Bo0A$1d2*BdP5;Dg2Cz!lyY_hamKfml4IIRu{rdSDKcpb z+hv~dM@nd$Hi(dho(XZ5fne!4$X+@Iv~D0rum=EZ>JF3^_5nZ&6e-hB8AlN5rVf`% zQCtPtU#ERJB_}cQYY8JUlzeAxQB^(1>DKw@WR#1tHTWlz7K%a zwAJ#NZE3Jzp;HEl5b%leDk1y3=QM#5_nV=!fezthFsVazuGXAOB@Py@({y4eq-bf} z3*R9UN9<9;kqlNF=HR=}fM4r4YwRiqS_`{0*#vN{F1`e{Z9fH6_{~#t*M?O9@U=sh z2`ky)0tNcw{^=)ID-tG>LyGWur!WxX3hYRZ&lx>zPB3v3i4lMkW`Ga3KuN_+16~cW z4AqOMMrgUJAbA5b4HPnj+c1bUy*Eg441E~j1o^A4?|?M3+vl}{Y`Q}7@&z^QdiN!Vh9jtD}&teZqHO_N9}&2 zdM@w|xO&agW7;V0h{%cRm=A>R>iXUo5I7%R*=7g;6GkIINw_OtMhk|j9Q$dQ5v`xGPz)KBol3y^E&$j{zGD&JiK2?mCC|kh;>QKT$KjBV z1qXmY72fN1+)2jv*hKu1eAKf%3G{wt$OhN>&${kOL%*Vd`+%V@tk-_3*?zRJ>UnMjvP;Nb+9s0EP^REfaB>RXUGr!ItjJ z&=?LUDhHRJQsZnJA5+y*W;_?d1yI5=kabizjp`)C+9!3DGBhs_xS0_!P&P% zO4vtf^VZR#7Hg#oprxz29%Y#0YvJ~Dr z8uQ306AR2@&%5VhB0)ow*G;W1dc^NRlKMkCK#gcsYV6vFx5_>P=vZ2}@lJEmJn;dK zn2IN-^^T~1AngtBJ?yZCOlN>eMrBjN_d=E-DhtoI&cFKmS@2X9Gz2I_hxa-Q0H00D zuxTr5{WpXN!x)O=iiy3uJe*YQOaTNVw0#_Y7KPP1iliBLn%LXiJcx4HF$rb|0`1_& zSayX&YxX((-NS@z62H5mFa?`%Kc;d7hddTd2NV8b zS*}X48`axt9;hqqPw;!6=$Jyg!IhNgvbB2Wa~C~!nM3#S2OwUrFTLjH>5PRB^mQU9w`_PFvK;-XlT;(0$r zNXEj6gkL@X7nuNCISh!NVtv5D1!6KF4{kGfqmCP9g4-RX2p`Z}N3pSxMXwIt5TAi6 zia&|bP*zyx+)M+vK(KVCE8&v@jiZPaEd=*Ct_`*F4>+y}>+(2Nm8ItIwyqsgGH(YF ziuYXJ(l%#s4XELu+)%dREb=CMPPkoruf5+a27DiO0Qk%9)G9t%Zmm)A_b_gw1?!5v zWR)zs#YwlV}wl zMQ4MPCPztd$M$KP{=0qP|AMxSnD*XcfWUx;5?n7t@1D= zWDtoGhhi9D*%)D0|6MIpu-da1NUz_ndtJU5OxF>z`%Flbu_LVW*^!Ps=`*Sp{S zb@sn;>BB}V73C{V@>xda3TH|0O8bRJ(N>jt;?5I-A)4Twn_Q$?#?sLW(I{JONJ-7I zK#Aqq7PeJ#QnZOJz7n?3C5uE;_JCc;x=11~{|}Ka*2VB9K0=%xxR-1t99FV?<~1@nGt_0(K2L$W=C#)FTbXgb`}VpGmM=l zRu6L$=px>&B;UME>{be{K9`qY$i9mkp);g3cLRM;j*tKFcI{TlAMt;Kl;&8wrTGIg zn>RCx^GSd{9N_<;rM3IIFAv>(Aa}@LYaNF#u8#j$ejOvo8fZTAL?OvJD$5f$l=qa6 zrNYMKepUdXbH6M>f8av$I+4TfVfo>w_g!L3pn=c;r9N=oXE@?J4rD(tEZ@9PAQ?0Y zlU^@!yCxr>{l75GA-x!e@FY_(IQx(8Pj(k*7J_N*7Z`HfL-rssvideo{8#0iIZ2XQ zqK6G7*%Q>iz$R!I%qjc?kJim#EY;^>tVJ2*Zl*~2FAu(7-am!XmVYja9YyZ?TV>Od zysV+cD9kyl`Oua7YUIT~8AYABC~45Wh@)t;6s1_xnF>9>x7= z{);U64pPP9x)VG`H{u7ECz^gjI!j{DC2t09G71OI7rrbYzyY^f%D?Kvv7$@?(xJ)P zLXSL2TQ!8_$P~#(@%yNvxR{_Qj_ekH>psHrq>E)s$orO`si*c8)-K+W%{aH8X&=u% zfg3_$B50?+kO@W@dVPJp+qdni})-;lS`kcd{h!ILZ^B^XRHLchT9ROFlkiRcwFgy-#462Hd{Ao=?Tmt zn_8NA@y@~EIuZ)A8z-?aFJ2rBK@eCYDC@d*#65dB+{N;;L14OeQfn|8t)teiRt&O_ zQzsD(p=jK?(F#TA-1=x2hWAlY$6CWMpFB+*tzd}FrLG{FVlR%Pe!lOS0e2<;nIUe( z9GvqzzsvV`ecxkHtOa)~edK(3F7?>14>V}p-Os^1)Y|dmDY}383*VtD%i{4Ufjz;k z1h^HRLl~}uE9S?{VDw_NiVAN>V=mBX%V1!3mo42Mlx@1XUDtk`z_TsC7(cYht%x>r z41A`L8y9B40N+)^T&W{|Ii6vKzDvUbwO{_pGknL<;pq(g62pW7)%Q`Q>q-5F5;M1L z26o&-lZ>0!5>s}g8*bo`*g~%^VKvi?2JJ{XlIo}VVkZQ8nPV4HUeDtq$xRy zqJk7365&}mTkeB@O<69yYC%^XynfTxVNSTAt}B3FubF}SreGJ4;Xt&P3_OMFI0hif z8MCTV257I=%!6px-80*EbmH>Ku8H%N{~e(C(!f8 z2Q&1}%W>c?(Qnk=WT2hV(}II-bH@xCFfV!=RT;_;H4!1g1I~dOorymbH$_-7lHN3< zJIS_b?%0PcJ!!t|2h$WKj8i{z>Pi{+5re=e$uLlp%YATE>?!5Nb=V^L82Ui(V^F4M z@0cC4VdPg2(B!0I-ZrKJh}SI9!(NEArI@FT!r_kI!wRvT3B2X4kia{Q+FZ z(UuuWF2*k%HapAqodj)yO*6i)>n9onBj6{{-jSYXygK=zM5IBGd@!qUBtpfR?=`(H zQjOtR%cJIX6CJqXelloMR$s2sY+O#dQA3xinu(s8d)usRy6d~?kvX3X+VY~Ej0ZXe z)X9hVlv}{<5}u${ox*8AU@r%9;2lBk19@gfJ0_&WG#;7#B8OL!-Kvfbp_55B79cmRya0YpG&F$nL{Z%nL4~*xl zC7iGkTB11t$h&ZPsz_#FI~_4M9S-n8^IT^$uH1{ae0jm)?K2DQGH7@^o;$WX?m=`f z0X5x`d6@Xcbk{xdo(-^$iSnNFbk{Rg3gobI4CVDK!n z>2>G==B>De%hZ*LryX1pSwt)?=_FJ&e@yQLqU8GWLaA|Ee;>cP+ElG!G$UyQP(|0z zdzyOlYw;2KIoOlld%z%iV8IN~JXygyFGe+UJ3Y3?em4flr)>ehm-$M9DPcE+WdTfx zyaQ=3|Gy%QTQ#KsRRQ`!rtx0z?5fsz17en0Vg^P}w;uus_hMgMb$j2&Gn~*0hz?L4 zMcd7q+cLG}JkchLTHT@B@-;h&EQv?DVWE7nQ@Htr&Wv|o{zwgpuCH$4eju=g6FQ|eBfa(vowgh*M__U{#5Qp1#Im80L;!Hk1g7Aw z&;eJu> zrzn79Sy+gt>=79#%YEb@C@Lf&73@-X2jxvmgV-Uv8aYfW~v{19Jqjz^q&6)$! znPrfqg1Bb(91`t=Lg@e@fyt9B&K=3j{m^#oZaDtiIZh9yi7`eyRmfP@QbZwsLJqUl&X3#btgB0wx*jSNbk0Eb-MG?DBO>adBpz*&6EC|te-4iz zxpNCapjEaZ0z~HS;ki*tpJg1`DUrdrwc%PvNq{6Rp6k_qCh86Gfy96iFjMQNOj zyIPZcF*DXJ4wgWJ*kl2jtrkw{3~#*g5C1UVvCm9 zVyP4MlArZgAN#IMV`VGZhlItJ>%?qxN5r-gst-bSSn3VTH}!6+;Jc~Y6OJi8g1|W( zhF&NC->>VNM2evbL`2<^pI)^HQ`wt`|6a!sBM?^CqQbya&5c-U1Jg2rV$EEL1cX1X z4ii#BRhuJ{8gAiSrz_AM33L)^27k>7@m5`dmbxmJ@$yey)8)d+I3)%sXS!n@yndf? zDlw{7r`%>bdRw)+1v|Z*&OeI1Qtw*25f36yOhA0@nJDS->o|#I%aP;7v+<(CSmVA! zzpJcLVH%buB;-Yv&6z1=>4x{+92HVC&6_n0ai&T01|0y)l{ASX|n zFFWg^Y`c9#ut8`|wm!FxqE;v&p-^ZC7Vw0ekB##z+K|f! zoe(~vSZ>3P+bEL=APY&s+A=}DL-g2b!v#B*jGEAB_G3-ozd=byY42VF^WB!57lNaf(++ zMi>=f_BHJ3F%Kg*6#eW`GLg>Q^Zs%ZS@H|dpVjq;1rEo3HUhaDAAV8`Z|7=GzjWI4<2%WJS3&yjBzPB4X8K zq=_naaSx*2Xs{7^-Ov(^BX6Ml#YrWCr(Cf7*AAH%?X8*WN0_>JIPa~ycln|Mog*I&U53$8K+tw$~y?uwK__g0#WaN zL&k_dGWg02#o*kc3-G1;|8`-%V>)|;xpwp@PTbXHiV%Zo%^!LmVu8%NaZr`B4i#d0 z#*J6ZvbS;S2mM*U<0j?dY6`jQbiOrNEO9^OnzkTucmBcOJ0-QG`0A3yJ*OH zsbVNJ2-Kefe$cE=fy_XH40N5m^i_QqT@;;Ec7pq)P)Cj-zi$;G`hq%_-%N(`H4Dew zrPy9|xBcs`?mVU#!Xr*r$`5xocy1yOl=MVnj;NbRtX#%0r0~+&%pP<2M}<66d&(DG zlK$2)6ydI=3gMD%!m;09eqbAXDDFAC(ll;p%S6k~i&RbHegBf*6yl=2;ab%k9)8Qx zqv$+VZRxgq?EPz=_#(cIcSp~=7;)F5OTYv8jsS&VnFQbXH?qWl41hzM3?MJ~I$}Hr z2?~vIjKU+mhExf0)>0uz=MN~-d3P_~kEbcYlQwcOPL#b8JNIe~+ZXK6YTUFKC~9Q~ zPzl^@b~5r2xf^5#r%p?(ue=Dbpix1#hB zp{dTOR1!Pm2Si7x1;&u&NVoA*I>_Y4AccMQ!1N6RH_(QKm}Dp+PKU|V1UM5xF3sm5 zicZdA_OoDxM>c*IVP>4;R5>ao2nHM{Z0UUx^Q+G==esTxE^22{L}NizZiGFv+ZcnSj5RsumDm zv(pG)|9aL>OaOG>B~-@9bl17ur+!x;*#d3xzj+1mZ3K1E%o2{v>H^m@KRq1l2ltF zl*oSfwNL*cen4huOrGEXClCUJNMaIL2Rjx@L9%JDLd<=`_D{)znafwzE8yBS>jSsB zvwW^PKsSjE{}CIps3EoS7x>?XLv`Ry5PzNeqfg-W_~EIx&rlf8gWFyaol%oY-i0u{Q_tNr1wZdsYMcMB$Lm?c=ECy9|J*L zkct~Z3EG6|g7UdgFjW98!_()G5_@xG>}E7>5;MsDHD-e{b#^k2$W?0!$km3U{%+GK zzUL2;-R81y+<Gck%FlL93;6kZ?sfFinTiE9RLL#6)u|RKTgdpfWzsJ~rVMC>!2!mk7_4aIW`#YGInflLa0t0t(pTtb&!nU1rpk(!{yM|>UKG%IXY z3ziQS% zPQrvSSEu(1Y^yk>7t&X&4lv+{UZ`|(>4)^5a47?C)5iFo)F(5`BkUYDd+b`dW7zJB zdX_=qZ`%alnO-#oM>}2D!0=vFelm0jYSjop3ee7fcU@;AUU0L3+-Vx6DvWY=HUv{Z zF83xva$gudZJ!7xk=b1V!tbw72WBVf9GQuP++Z^@*Nc;|=1`sk=}N%pK&}<^oCFFj zw{9qn)LL4=yA5?xJR7Qz2~D|*dpV69P%gzqU>>MaVdg?Q{WUu zSxh3?bpxf`_Xg_=+6`?1#D(gBsZ!H%B^*j$?P-Na-{>`Q~rS=_w;NTpVY77oA7P zzD<(SEt+09*l66Dn%OqVpt}Z7rq-yiZ8&m}jBA;y52+#~%-T(mW7W<^e%9Xb@p&KT z1FQ!QgIMSmL~Y@S(f1Az0Xft*cq$c|Dp7`yk}eN@-;N9>nCa-In}b==o>33Zj785g zL$K^#Ky;!iTr2|y6;qG7jhozrJ@z}%ar3ab>mhOu2To5@ZnYQp;%;EDn!ZqZSHVJ{ z?xUa0I@5VBo=5FPn8^4xaRxjE7~NPhyh%9#m>+hJBlO7Mw`*?I8B`~TC_rk>sE(il zE_Jn=5VK*2?Ezy~=-UkDiH|;&Xh_--D0;>VgJ^X*_n$JN9XN+mlnpQzw`sh=`zWTG z(HB_>Y&Eanj7tf`e0Df_Yrb?~I@E3LO%j-qbiv*NU#Q(S z>NS{$i^3Dt{b>%Gu`ElHL+vjx?&OO-RpC{JFM2kVNM6=xIP)umE=UCfHJt4(VAE>lkvyVIwq9ac| zH(bloK6xX_H_(>*+K*@6NXF1o^#_@*+LX{X5Cto6v`XjYvAP7tI7f37ofqsoH9;y% zQF=iGEl=zL5tQ6SGPh|tdSKT~q&A7$g{uK4dZR1gKL1x=QASFd+*P$NeeMrJovgA& z5QrpOdp6p)kwht7fCqtXS)Kydj?CL`fgE{`KF@eEZf@F(Nv+v;Kj}M6CLI}9P&k!G zcyT;85ZPn9&094}$uGO;y!Y|8zq%L0GVrPED*=B3!%`;$+-@LH`$mXRYkZ<9W@=dFDKLY-Lj+1*6`CINbH6gEj&3A4J{!B9G%P}-uX?jum!?tT8&%IgKqP5 zTPPa^`VedOU4=1@lWp*^VljiY`KVp>t@TD;`w*sWt{GGp(aSn1ykR!(+2BL{QnviOaY&2%BZX_B(g&rmGg@?w^ zk`8Y8!Sn@M?I;w&442_v-lRyFR94-RoADF=rF}Q+U+SZ6RF{=WPxK=B2+=hn1$wiK zo&1fD=m#zj4RQ!UOi=WGYO3RoaWa5(^eCEi{-TX;6EpWU(~G`5m_A_*r>c;Bi~(Ji zB;@?;eka-WN%FG4PLu_I7Tj3ImM;IFGYwmArFK53%&Ujg(boKZV^J}hc287XlMsYs z7~`qp4E{}Mf{MV9V2mcjWP#G~Mbwy0KhW7q$6cdx&##&dzu>8#`I$|Bee#Kf@DtGd zE|4I!KsZCkcq-CdNM0mn!pa$`-?~Plo<3-%;M6zsO41JUoGg*HJZ9 zg7HIQEJ-v2`U6{Os4A=!+|Xrn;n?qc+UitC;XX$J0VRfo8p-IkbwoRdi9K|y{v1Q1 zl^u6z71W+4KVnIUnM2yz$^>=tw|`f3K}Z|5mHp%q8bd7nQiXXc4v8?nWFhp+d73S=Rkj&z5qbv<`|>>F;?P;tfI@XyzW4&&5bICNIgdblmlMrx&O z6eCh`qif3_{hSEIt05QI0I~%ir+LMUbcRImCrZud7%(woIE;`j(}%)Z!7oZ>s{iz; zskr>09ke+r;>&TRZ=cZRzU?e)h_{C+Dqa%7IX=5o1N zEe&GCB-o(sMD5`XnxEXVS~A>Ogf-v-UnA)(?ky5`!Rg$nRaE{GABg8ZS9rf#Z90Y$|f z`9pNKt23Ya^`|%$pbz9Tb`H3`X=mts2X<&x46l}Pdt9WX2tWT0Sca6u2%O;)GEnX~ zUygA>Gy8F)%o>%)G4`fHcn{LRj}|u#GkW!jZ~k&9ZU-b&P|m#hCHrkm7}ClF2Mw`X zPG9!i>1~g<$8hA}yKKk}^qEfQ&>SYIf4(t8`rWtz@6x~oBB5|6Ll#v638n1VSJLlJt~!vpZ&RECBe{=!Ntybf15gSJW0Mfom$V|D{jgo$i}GM zcLT_b_yruR`AJlC&TH)(MRN4w6yX~XQ3{^e+AW=e*GE1TJTaDwh6+-$BoU(%JSYy; zpDUz7VMgCpjn)n{BUim-#@s9M<+Q@p9rvq>D&QL2=w1TsEI2p3o22nYBEZGS@5e8D z=8-WT)&zYfD6$UI zF(cO0YY6Q|d=WlT@w1`OE5fprBY%>>Dkc3Cy6@RLCT{YK+IVim$7>!PvnTmX& zMo|`BK16`1zXTp+hMB)ZX<^I^-8N>|_}gh;8Zo=Dq@r0sxhavG&*iSbxw*~e+ync- z@7b4{j^+{tu5`;^PeVh$>k)I36D~lqf{Ue$pxWOL;0yE%-xOruHB%e5NZCOe($g74cQbfiAID%Of1WY6cPw%5=QX%45j5wwc)A@ZnU^* z-$57bTmk;~YV10IfSs9gyWJe8HKLqrJGw|PN|FF9`gdGGy4V9ee3NQ0{FCr5C6a0ht+_x{bvW_%!f9wIWxI+DE>4lpfmU<}`hV0q755mplfi zsE)+(X4{T%hmtx>Kj2h)Vk7`M#^S7w3SZ3${-t~ z--qcWv!^g!%Fq>CLBw!j*VUktpN{xn7D#|-3MPm*kDLR)Br{k{U>2l?zP9$v6+0Lj zF@@(6+E#~&Pi<^y^A9%`LxKJwrHI&4xri1M>b+@&htYWErUY;zUWXbp;-Wli zzMW8NI(B=})dOF+-gnMDB{R+1r6K@RQcoX2LC~q7e)B)(Etn)TM_jPUfQkx-*9dVq z0en)g0=b3oqsFA2BCavBV33F(p;|U;2mLLkr6yw=3(OT%aaKTM$8ZP!gyAF-$^u6= zF{>MH=JhzXsHMsm#z~Fd+>ttSs@bFC}qr5U^ zR7QO~H-C`acDES{IgHl8y@u=&rs+O7{2jv~L`{@l&02DhJfav7A@m#mnrEDxRGfR3 zhH$tTR4AcaGCh*JZd~}ejtc1kAMyG!y%K!$7nyWGmS_X_2Qws5_^bYLvpuP#YCEkM zPnbHJ&Zaj=D6awFQh@AOmO%v;4~BfNF&0lBrpp%g0!sV^3;6^tL0Hz&`>F+M-KpVa8s%pbVh?mmFI2o!nulrALF z#Dq41+lG4$PTQd^a)O#*OO%@Q4-yMU?oJ{{c}AcB8e~?{c?(tlO-CNr4`v zDkgu?OjCQQQ#lL(rwbW?!L*i4jW#2pMR6l4S1y~zRV|E)#n`Frl-7~1lZ+1aZN&B0 z{CvU176FHlMr^=!pz2D;)no5U?c|SXodi}dGSGGIURvM6sYyeGPTBV$wVGj#hN-ms zSVWp|V53|)Y%0PYwCaEdc;|E#>OMv=FjttNh+}u+N8XQkFsofa6}q^9_Bf^G9jm;H zZ`o~p`DJ<95Mhzxz!S8o4NCof^o+PTk4k%{Gn3(?WZ5**#q_W_8CMLHpVGtV#Gs|W z?kb6oH|#BU7_T|9`J^zK3OlmEmy2c~r8;!$G#tsjvwDWNl#T~MNqJ36MP3Gva3)Gi zp{;i{#0YfYBgi!v8GS$*W7~|I@%R?UUW#wT<+*@v{9(A?YIVd6?>Z7h+M#yWKaA|4 z%awh-VglF%Rm(_IWw*8E1IsdAeegdCN`ykU^AIIoRav>wm6?2Lpiim_(JZ$ya%@8) z>VbPmjpu%}i*Db-uPOD&lsm*iRm^TD>C2NNZMaKzFi^ zh2Md+p2dCXw&3q3!0dJMvFmUGqE?t4y&))j+&jA&^qaS9#bIIt7V0-F&>9 z-tv78Td=RGrVi4bDxVrb0wTq1bLe^@Bj?X+P$KwI_(Sj5B#tRaYp0js4gOf_&RrFH z&IrO;4!BPpUQ4uSSdB-Q>{zrIANsyEPf>{F5CNNl)#^U8k9K}6sYOSOS)hi=MYHJk zyqop6sLD6((4=B}u9OiKf){xnF%MdM!u;lk^?pkcxr)sMXE{R!WKDcmITNM?HI*#s zSTSUR=Na8>j>H4|wx)g`k?%ENVkVDhWiY{ihQr5=A%Gug8b9|iYA!YlG#A{ma~`)& zVBX836!{`ft=MTldPaTH}kVZl?gIh?bIpM^(mbl-w zRSZGJ8^`w`c?mjqvi;}yid?vB=#@Q~cKaxZJYgs?b7FyPi9;5n&p|p_W63yQYtb$j zx3lrMyBSDL@q+5urXeoLBK^S9VWVE0qdyWcD|;LrHP6#3VW<~xp3VZpRBPi|)GX-B zDTk4Mhs?0++5^q6|C5YnvZ%mfiGR~f2k4WQ0~kU2l0lwpYnKMaICSOhxS76e(i(8= z58QI3qDF|jb-nD~8bil+6NR44TGz{#nVw5NF5U*z6{$VZOFSp_7p;M837G?JztItG zc{wY-l*CfjIk`SS4+Wc2=7a!wRoFS=z!VyE>I;?PeMb@3Osi%Yj?@usxrr$=^4sz1 z#tc!q^B@q@(FGJ0!RnxF78~Wmf#SKC4Z~?=w0vzyp^y3?P(j=ixV5Ls1!VvY7U~2l z{0-4qK~bqk9l(@5U)hTn{b8~ZQ>P-V4B3^^qdN)75v_`$2ewe1r%}Yh$VK1Tg4+l! ztFh%uR=g1OmO2?7C;ytQ;iWp{g9uF4&{h(5$AWI`pP+uJZl=mnjiE^bm&$~>=_*u0 zi4naUBsBG}IapuMmcocN;MPDNBTmNFhu6%mCnNJ~ekYbZ{S?s2$+)O^q6D79ds81@ z*wcHGjEIps%THah7nR8?4$!v{y~u%WQkSH#yz(HLFfZ2Jwyh<%6LK6&Pza&83j~H? z$a<*@9yx>C#6)`l5xqJpLnsDy{;YSl+>gw8kg1>4HY z`1V+pX_h>sNwK5}q}-yP3z{*bHKPlreA7$BH^WXV)5=4* zj3(9uEg^N2#5c_lQ);A8EL1nN0u#$MCe;EsJ%}biqY~_uh6{cKq)3^idH>i#fTIokgDHEY( z2f>-)EsJ+d&anzvJySnJ8G_vzG^q$pgb4%-=aaD{G(K28wVEC$Pw^zded<~M4q&0^ zQGl%%;eCgwBW#pV0x7~TbN_1yJR~K^+7w!a5D|y3gj6JP0{y_@MBr6MJ`Ce?2QWf2 zh*fHT#HwzY(KJDs0^6WALYo&6;cjxQ;KYoii|&qD@Gqlboi&z}45om*TxbXhG6D(H zAh0Cl(Cgj*IxGB1$siCT2(-bw2&53hXmWIa2qGt1tr^DnLCbr%QBivYfRDwuQYQc9 zSd|E5^y!Y}VXapIyk@zX;fFSPp}5p!(b_$yZ7@)@?ybWu3E9LlgC*pu1VyP5 zC#etUm`OC31Mf{|(^c}!kdo-Wq;_&AOg|xdiGj#AhcP6UoeE3`WPNGb$45kUT3U^P z2rjb=m$pcn6mhF@2EX*zxs$zr5l+(1V~YY@QN-E^6DI!Er3#lR<#Vl9pSQIN58AZH zDW{JQ?3#Oujd-96&ICV2zIirJS*4-ah@#~zX*K}zf}Lay318Z%uq(abconn@aW7eY#+vLW#fitDwBfV)%Ay z$;@22JE&0VpGzqZ#Ax(wf19=yIS7s(C!z~xi7hA(ci@bC&?$_5^iQZgl8Fjwfq$?G z!c@0a2p~71f8j*^qyKkO9R0bOMtRVVvHy^v=$EF>mTjCJ5C$A7ZPTV*Uw9Kmiwjq& zHX|V7#h#E_fH?f&AM`w_zb=xU+ zzDeRe2Nafvx`g7B*tpIelaLoi>0+LTiO*k8{TmLC{6t;Q6h2A?Q4}gR{8jF2(_wbi z$WLiL25SeuHG>qAv&?Y@5#awPYSEAIv}Kmkp)Ls=Arh4X8&p#sv7G8}j_QAPgep=2 z2NGY_($tp-=@i;>#=zZN3mUNSQbE1VUi5VG%|9ZlLRN-_lUmKQRs}oyHkN$7Xlet$ zW`5D-0m6d6a6}|mQ(dNbWZ%P=79%&C37J@ffYT75Zu%UPzk$*KGLYefGCc}%H`o+W z4W>MLOD)pmuaHD!sp|W<(La`uLtm{hs4}&YYT5_wZ4BDRd$og!fCN6A&Aak*cB-uq z9X@e0x&|+htrO}mvYj3YpZUAu5Z=>6XMY}^EOsfp-YZ%7KaKga_}IeUMJH(!B^P~ zv`9Js;GfGm~g&+$*Nwhsc75{cY>#`zBy4F*y>}P zDIF!idCuQRn@?%j)r$dwbB+y1whka9??yLMHppXcgOxq$m6Ui5{~vQ$p%-b8bcFFp zy1%O6g|>^%kvsX%eq7)1MKa~gEAi7f0t5Mhfe>#6_bD!-RnIbq|9oYLVY)#>kMl-4 zo2Yi_-1!*0Q7{|~jx**lqMRM2)=gJ!!p$dkv+ zn53kni$PBs-P{sKg1(hHa3AviMY;{)eSNLzdQtmZ=3C#jPd7^A<>ozz2@ z0gb`n`3gN%to@>4l|>K{YE;N%m1&P=9v_;ext)pCg^ZmB1KiRl3W>UrWax@`LZ&nOcvQi7G) zVSiHcS*P96;E67(pTxW#p}%FKpM1P(Ru0XoIZ7W}#-wRM3|bWe4&ws#`w+mw$)M|! zNVMZ<*02(aU0IleO}673o<>Bv>_<~&BOIHl0MH3#U<3c2p!co+2H8kgOL^1ku`>$9 z5kL+&nO455WFa&RsSL41t^AE8w^U>v zCmD?5{D`9)d^uG;7O2b^mFb+kYxtlz8L!#LiQ2?8LRdS4HqPok3%&3IZ~(VDz`88) zG)Vl}pmdND#Hj26+9F1&GvyC-K{~@4`Bwdo`vCVJ=I|AiC8@)ijamrZITXCY;cNUs%D^!FO z@_A&;s{~7gwUA{$zucsM z=Jwt7KuT7#!Rr$nDqhC$#gmMbleJsnW@RsEE~t&kFG7h*<+6718*c)+@MGu~&DUM= z2btAmsmb&C zZn}XECM^1@FU~x~iOnn})B8b9QMquG5>P&=H0Q*X@Vk@IU45rWuhI@AK+)yPZp4mQQd5SsA5rS|lVA$w zn~|XFE62mjBbHW|hLJ7N0A6MZ1UOa7ziHv0Oss1yfeei3++Hz0DyxR@AUe__H~@?t zSZ!bNAkmzjFh!fC?onA|M$wha)s-Z^=AsQh<}Vaj*Xvf1aaJwVWyKNf9EaAiq5P>| z=1%^Pzo2hMiG&fvVLj|lIbj21)Z*b?IelXYRH25TX52J!s+!%LwKJ>ko>Of$OE$D5 zh5*4;681NUs2mKYXU{G9L4VD^=4n{>MyjA4)m1tUNr50yk^9SQ1HJIni zbw+IAJLe5A3>r{DSStDlCWT+0{0r?J2pu7-2z9A2t{KTA_3TJL1=mUChnxnQMsNfy zX~4zL#xJGm%#s8!oJ7En%%lHb(2*xN=kScz%T%k-4wnKrm@wOwkOqRa$~*=O&J> zBSjt(iOH;vS0EnP+uBSRaR>`&D|fgR1~$wLYa#q}N`_!1jGncjSn^V>4jc?D6w6Nj z(qGp%^c&5>tKT(7fl&w*dt{*l3S0-?#_W~*Xk_Zh9kA0${4!N+qK7rV=Xzvuwibb| zBV1!7!u35e&1-S}Iz69yLr3b4XSy&!X#-;9A@m9BP95kU5A*BNF03%qusqMnQTVBV zIfzw+S5fXk?F{M$nAL%>gnc@wkf|YDODE&e^u2T?hAhNsYgw;#BiB*@NyW6hI#cxw zZ>88M{V8Et=7==)``l;#ewYf;%(?;&xzdRHnY1C|P-q;khisr*?{61bh}u4~mrX65 zNN+T+K2}J7C4Ip+gU~ZA<8Z+4#hU4~+j|L$aFl{oSJFjx0F041RfeFxB7rW1m=-1s z)EDWI_PO)fxGww(RWfaTIA45ZE!>uhDM%0prDwWcd$Tw;G4iKt_OrDszL!85%!~BUk0Nv4RWF*sr18>WtUkq>qhxgosx4ey2@{Y=H3l!T zbDz1S^;^^)(6)9SXeI3@J%J)Of%-*?$U5{11UUO-SVM{-L=OFb9(Ukr&nOp@uoFp3)?#cDTOk?|nO z9=BBf8~wRH*3jQh*i7??5&jEW53W)37-)-GwI*%_aH*pITb_0H=Z#%3<9=p8W}&Q$ zF-|olmW^7YFpc}rOTn!o7SSf~$k_Hcn}eV;tu|W=eC(0N)SuE{sTh!fe$~py6`m9s z*CMrZ*(j=67{XNJb8q|SD@$-JI~FTGOPO}fOqlX$63=+nYkObW^?ipe(S^y8(l=QhYe#C;Y^dt$e~|) zed?!GL_w!OhZb zGI~kThhij&+pfVqp7#~|P#x1n4|Z9lNbfN`f;kJ1fP_F?peXm{7nC5OOMw_Jj-Ncz z&PO4%^r(^)1c5R0(Wbscw`#!vQc`Mki9Kq(CbCewU=^GSH%1|Q&z0@yrWTL(66$3TK?+hm1cbqc3p+q$RH4ZPdxln|VTSg?I|?L#WrnljlbN?9zdG z%QW*hX(lk!jKH3Eqp8h~f|U@Re~w+DK>mUXfsI^R_S0*Q)wo1@0W&#BFWJ2mSah5M zz}G$_S)s&I9RaX168e61iq(ipn8f=idMiJ+YDfBpj!_#{7{s2TChr(lsoXa<@Fj%R zAENkD{%-l13>|O0#%qA9`4sL z>?JCnTEt3V5U<*UNL?$E>$Nj+$z-x#|7<8l{mLCdg1`VRcwP(FGoq z1@#H;L(STZu221R7DY)&ZKIq?M#hv);wS^L zUS(ksQ)H%c=xOC$BO<tjfVEbh zTM}8|t{5&u9?rKuYX%2KA1#Gt<<3=W?zZZVj3->evBi1)MOS&bgTcsR@vd>5?E)UA zZZ>7s&dzW7cv5h#8nG^mwGql?H7=`mNceT`Q-56sC!~Qa6bq(67J43NDg;dz3{_bL zy)?iM(Qa;n1aeNJJN}|Sfm2}KmKOl%GhB<3k#Tbj_2EGGnQXGn#pKwh5C$_A#3?lJ zw1$NLKzhId5hw2>&CH9u@$+JvyeTS=9N`(k=M@#R1IPFlE-1eyj@AaQ4J zkDJlf?HykH1cd6>xzGJ-h(19iP?O-8$oPs@jEY1hwUVlCB7`*K6C?3!CJbQJA}C-6 zaW=kspWXG=V%q8OuX}HT3*Kj6^!72=WgM^8d=M+4+u%-W{?IctgGm%PJ}^TRiY^J5 z=p7b@C_xmSJkBa#a8K|KJ_}o;&V)V72{2Q#5lB>`F}(g2`?rdfs|dKX<)j8(Q5|*8vkgSbmZHtr%_Cxtw`;oR-koQJp>WtjSkm3Ajep;`h|`+# z5a_|cVYh2t@HZGk_^u}hs&`0K^u z@YmhaGaZV7L(%I=bUC8&L$o&CXE?NXV2(CMxs1gU-uN-Q$WU%0z2@Id19OBE88K8A zfG`5OkZ}>)>6Y0d?ZtqrV1<$zu}CdBEl84GawB};q+!lmOAE!C{R53kaj)47bF9-^ zA%P|tZd)+HAE1PgWziEDtY;)zs5FAWOypwQa$g{hL_iz zRfi2LlF=`f-Y&3&xpezh71NMgKxni1JR3rPx2F=P-4(ZWcrIJ zDLAGpp(ijLqX*rF*Z=$C!s_rQ8m&dWBn_9`V6zqvZQGO2pTzhWc1oBbWC@0fin2PJ%_fK^`F7@y&Wl-A_mG|?Wua`*wmPRy-c zf7o&Tj3fg*9 zsn7O)wfZ^8!YOJ8Pr^=bM+}MY~3- z=!TBdpm;c?F3J(WDjFh^6+1CnsLSQPZ$V!PVTrPHScWm?LpH3AMFt{|JII??$m(w< z1C&6}G}FG_eC%0?W@qgMzC2+b$F}n!;-zW!pZx#p>@yGmj!UDe`1O4SGEvdSLK zHbTSl4Y{1p;WfopxJnSkKT%4sFhspD28+-@2kD>9M1XuP`=Ek>+m^Kp{WY82B#>?-Th zOG}yv2{A~)#gmrFNSQYQY7j%Jq~y9fT`W+K6O-T-@1kbERo2fs7?hRGC@(9d*ka_ zluw-ll7LSAbK(pD5$*)3QBLcR9~P70Btj%SD90?vH|UnH`s_h4aFQ2K+S+ydj*;G- zq`(RaZQ3s6sK@ubPeIf`j*e8@Gi3S7(1KEj-@fv7HT!7&Lj!h3^p~%q%lZ&4A_t7f zJ^OuTnf#3dr1u$Smw>}yYZb^eRS+mf<@oxt{B>05d|5v*s{2TTw_tdtL`6X z&1P&l7WPPQ_#)FKnc0XNJo7S5bpt&{jdqT0N4ZF+L;Y;ozSIXvzHbXfCk=%%kAnIzf$=$T$(U7dpkL&=F+wF7EoXp*(>doAa#Zw z*j?AzWHH4SY?+}9ipNJ(I2KUJuJ06TPawUuBp#7g-Mwtqm&>sPluc;xspdkHn@+l(D1y0K}IESiQ8AR@iT* z92aJ|&(m^}%Cjg}h~2}C1SE-&+{x7d=8BKyTl86S9Y?O3!KXOJVc?iKcQo+zqN`Qd z`~bg}_@T=PipN>F3YyPQK=v=(C-a$&+!*!1sikyk*UTMKHwaND!L|?UI_W{=qbN>|J)4oUE zU$bMLHsUmOcxh^nMfr1pbca^Gnr_)-ob-xQ>Y5!;JquY-Z;g5A zbrRjyd$M0C6s0UN?CidshW}w%y-v_Q#purwihLj$W+wVh!md9zOp9KO`u?jY)D$!}Z^yIr%^{xbD zh^4_QcJ}}a1O$-PeG&yn^bdW-e!lqC0lV#1c2$mI;NxXKkN1l=eH>UCE|a5!(nQ1U zZJwhw?q9g0?T(lV^pj3AQkldwq6{FZB>;;AQJr3X@TJ+%od{lcGeDE6l4$u^mo1p$ zo*<35FQ2PEJ36?(R2=FcmsoQpH=M7N(jNincqJVMm*7+TDe`?s%Dn5g{4_fa#7kyo z&GSeU(uBg3N)dQ~qX|XQ0^e;W&o7LJz%HmHLX%1{%npdKxg|PS2(}_n$N+P*_`Tmq zigRGph#$03+uk>8$pn!(3P#r=50?;#kcUTDxalP^3MUhckkf>~>uz!ME73Yb?sJ_y z<3sy;-WfWkrN`Zt3@01v(2TKvKQkZUd zt!!C(C?jrVv#A|QXPd6F>U<~lOw&-k>XH?T$dqHSLIN47S0L;i+wBJOKcgq3&N|94 z8AA24jjRaJTK^4=oBtWW$+Fg=B*huD4Rvt4Jg3m-#55LY@Jo6*Vo&^Ty2aeP7@qmO zj33f%Xi(VMp=#9w^FOf?-lmp;G9kDU%@dgW`#~q*B`h4EuWXMi`LSf+*ye8}<*>-_ zg?)F)4HTw=qj`dyS`;;xUoh^)(JfoQ6bqs*_}6{Fb_9WHgzJ-X2I{o@j{b5_<3Cc) z^EMhv14XVFVO})sE*W0$15buZ!EP~#DiN6O8T<7@N`(f!7l9<9LK>J;5r^ut1cN~t zx}|QihV1&NxFV^ZkNMcMI!m}O%7lu4@|cNK>8#8)u#0#~Kn@zxjZ4PD*2yEpp2O|i z37a+X^pUiy-1>VW9t%&{Pv+IlbippzOU)5a$H&JHJ+&xYa41w|kQs`4Qtc971fQt9 zUjLWj3s4}lLwLkcFljzNpNBWuZAsCyb5xiKs@ch8K(j=VK`4z9>Lm(yP zmJ{P6z#*&}Gvzs+bU(xddfZudZ&J?lXC?980i*ZamX84i^_N0ac@X!-Z1e@Da>9)0 z76fD^;)3I6Wmw@9wSOMsf_8`q+KLWL>kiRQxB<00RgNhIixx}VPQpb%K%Sho$6#+I ze-gVArvfFiVlzFQ#0}W|xS88B?jj=qq@J@WaFpl<0i>=|5kx3ukw%cLc_xyX3d~W?+lZ1U>RYtB&un3fP1o1Oy>?3I}WAjG9wpBz@Ow zy;1{G(o~C;kUB0?A-+zlx`h-+T|w1eMU{S^duK=2#^vS>?gXhpS$&vCv*e^bvQIe^ z02DuZ%=D`^glB89(M{GOn+VgQ6!sF(L(&qaj?q72io32n7j06S+fG(C%}o~{I%+EW zF1BJhWsz|0TnVbsAc!Gf=`yHa&mAGuRje!Z(N}!$dtR-#mY(?yQ>L`#V`r8lH&c8V zyMakBQSnkR(mEpbE!5znd0@?DKWjX@6BjPAsRcn{7oXJ`B07QI7@drN+&r~%;DcrZHLYRkK7RPQuMlDaiCzcFYV@1{&F9$2*;<2;{5IoV+H;jHA9 zBq#(U)Ck0|@XM1Q*4iL$u7vZD&u8W>an(o>PcU>J3|XPivqN9C5A2cIw&Mvc7IT9x z>_%8lQn@c-h4Tg3%+wlP_U?MJ4&_5rfX_Op~-k~93PRsVPkm(jY6d`GNbNp zp1bMkVu+!i9pYJkFcTUBXJSDVMwT@z7>h4IG*nmCh*4-sGzQY0s^!|7BCzOzn%Fyo`ypbkX_;v>t6p zyhV-(Ku~sKRa41wk(-bkYYV?V@nd|?T&%bR zLHws$mlp{YCk=IqPtdeut`3Y$(#XGWHltB0Z{{&i@Llq=78=S~xG5gxhx3v2`+?bP zR%;1QhjXi}%UgsjKbtzOCy`2Z36mnJ`>BFc(5bF=-uma7=M=K!1w|nfhd31MJ+Gl( zGh54*woqV{m52)j^wir3i-^;*N`?T_4s;3>3MS0;^XUbi@5SONkea=~0|Y3*38#dT z%(De=TgY{_`$x5a5*MkSl!^lR){VJa~(E= zD^e_>m$DEB&2`^gOdQVOb;Jysxd}J7ZHFGZWYHg_6Yja_qE81HO+?Y9>e=l|vr%+( zNOq^?1mX85|9FJ&l;mYNd{Ks?pA2m38kK@JCd?*)#-%Y=j_=Sn_cKY#09oJV!(3}t*v*ah*cwaw(Dk72-T18qs}u?pN}%`^0?7JU;D@z2iyFqFgdipF|a;a zBxK~0K1MvCV@i1>UACh(6fMwa=|PDdT{&j%5y@V7X4?%v;=E?%?IP@%M)Obe0&|G>!s7uA3IKylN2<>8!3fm;u<1~7m{N<1HHN-4%ERQvkyHqb( z=F!mttboxvagL*5DTh2Xt2{)+B`c|E9yQsJib*Auhb^?(;uzWbHX#*$3KhkU^%%@`)= zQwmVJ!>NKU%2jjRLjUlY5cQ0^WZWl%sGoWX_o<)X^M_7gkIxBgfs3W~WHQ&e?b_&F zJl&Qjqb*6!vw`oFR->spuQFydFnCX>6!Lb-JJ~MlZQ@emOd`_u9fs)nBbo>h#jv{W zP0}A`xnn{x$c@-4>1Z@_=vU)ygsb%`ZE~M!F2p>Ni*Jk^s;JccO?lVyoulBg%$JIdr>AWM8ZMkao5AY zv{Z|};U*e27G4bVRK8SRoq;MsFDfn&&5Qzxh0s_j0~IIR-gorg6ZMeT+{9m_d2=a# znPeK#2C0Ob$-z6h(-Ltk8A&f<{4aMzI(8fW<#o#H^c`wNGctT=Q{5TX;-`c|2)7e6uv7BD;RH9wq~6-tlvn^;Q^r~(T!m7C)X};hh zaKobTAnIO5$5{6k?q5@F0_jZ9C;#kMAv45``4GC9`NU}-{XiKJ3Y>wT8MC>Ak@C%@ z5&r?IH>4>JGSf$qy~u<&tN2nn<>1X}0sNc46{6m7NLb_;LiSDiYA>NoXjZhkZM%6Bw8>_-VbgQEus~DGX7H`10#v^T zf&Rf)I6!3Lwjj8w%3($<=-8uFh}Q)I339l@u9J*EJzxnZKIs)i{_eHj5gd1J5c#aSAoy)PD{t}l`x#WyJ%Fcv1}&V>Bz@* zJr7eg7@OP@zg88}a7Z zjH1(7HY%!~9zqdw-<2B`ciGqH_1r)9yk(9V+o@yaJt1({B|;bQ0kr5|_FsMSO>68s zru_ZG`{mqgeKSj2=DGGK_p0k1+bW-_R-do0Pv<|G|AoAD<+sY6{!+c~>FQL~{l$DI zZm<8c*6X*=P)+Nc`Q(}Y_5Du2pX$`VSY1E+bnA?}TOX|qte?qMFC}yNfr4v%a^~r~ z<#UB++Ux7oJ>IC6|3L8vp0O{);JeBBxccFK_h$b$fBxS$W^1eSoGaDM8C%4Emp)t_ zK2y$BKc3H-b>pM_l}_c0aU)mEb#hbvFSc97r%Pv^z0%pQ*WdKH&Xo$Pzg{mCr+%io zzWz)*Kb4gG+3=MJe%3_o!%qF_`005lxZ->#ms@}9mx|B!Ins||Zsl&VlRNh__9NHx z<-vM?|Ji(nT|w&gOZ{hEfB!SzQHCwAF|=X{yYsnqF|Aa8+T_;H7R{M{H~i_osi$94 zL8?*jKU*kv);s*Czd>#JN_m1jqO@;EJDu|98|#Ii%72Kv^QC+%-=CXX|GDx+$t2GA z_s4}d`U@vN^Z%62dT( z0Y7t2ncJCG{b}MKevO?~b3ABUht&Ce_s9O-si$+fDOeXm6>cflS?5-BoKLS(o^!Mc zxtP;G?Mr8-svOw;efR-3;NP-eP7!c%YmM%mpL2V~ z@uD5g58N@fnk$zp{r&y(^FPp-d3vV5(f{<+)2;RO^7{G!Np#hYyLivBj`G&s^`myg)P>OKGU2<$b1Bbd| z>4`1833oHTb^q6OkX_DqfBB`){d@HfohzO##&hK}=f1c9SL)`|&s2V(UjFX>kLL%L z*8c~$9xYWPH@wvLxo6iuk^lIasQ(`~zVlc5k=FVr()QW){M6IY_xAtP`t;K$zL=}W zNqz7W>$&xhzg7MC8RWD6iH*6@x2n+}I{Wl%ef>XmVBp@zzq3$!tAG93b(3p6bI|xa zj~KcDWBrx-#bUHy9X@Qh{k~H9%xvde$DAonPtSJ>|Ky{&V#S{6ob6|Oj@Fq@`RrbQ z$F6tY>h!PMPmnp-|DU?|kB;NG&IP-hEoQ{fPIsX(Dvls(s!%g-fS?3Gu#7NH+|}p- z8x&;Cj39Ze=r{lbD70h8Btz% zs6<|o4DF|QleMVGNj94tlZ-aUN!}*=)zEQX_U!Iod-lB7oBWF&3|A8oJzw|dpdhB8AR=g@DT3DzKME9rtuvoxcv znkG*YQg<-_dDxc zI%1lK5$?W0>UN@3)2~T!7d;+p%P@_3@n{&iBP7&)K_;Ti(HCPTeaO6n!52H2A5s?G z$WfYC%AT;31q|&4G7@YA*07b2-6&M{q*7)aDMijO0_7wrn2qe-!T5oz_RMsw7pl77 zR)@IDxsri8!L4pr=tUcyql;6iY{s@)QuZJ%*3L0)ogkj?M7L0L*~nQ&S5Q*lq}0lW zGb&oLBSeL?4&6g2ID;>Rf~v_6^~=125il5_t0fw|ZE-b7>OKbN1IKsBkgKJ5sj(Uk z3e9<5Zqh|3qJAx2xYXz+OC%$tipVHsUV4g_YS7-z*=Dp&2fLhdxHz-sE6tWExIq~G zq9K-KGflAq3i8YsHl7p*Lf>GqI~W-A;m~NEKtxEAXN(PrIy5>-`ew!;JYx-;RPX-j z?cvN!p2W#!7{%N5l3k|$ZAz==N{E{bFZ43TXZUoy;D1CdPJLc#-aJ}7MTwqB=qY-e zQp|$~2*_VHD_+pP@tvOHuHN z45G8VEo$XA0d32UEf1X+2rOmfj=9PI{O91%_F_iW9g(mI&`6vHnQ4grtfCS*;@24m* zI^#HyWK>w$48{#ioy_i}%XCwbx)Z0|bLz~wD|es1(JJV2ehhBV-uCz4CV5&flV;K1`F$ z3uD|OgsRS$#>urNK`Qi{*|f4ea`~6-H^NocV~4mT`o`$UB3ug$ke7FL6JI73q6@NG zi*CikkApIe{8Y{O8bdEDGq`Y^S75gCT8#P0LDsoM6lXja3I@!Od7CE1omNQeX8Oaz z5VlE_yuReEvBZc*Kd4IKx1N=hEph(j!>ehAjKus_7B-4DtPNHMB~pe6nGe7lM-%O;11RXNGWT z&-T5=iW>BBQO8<>lCiA3Z|-bOpdq+x)N&%^+SF}{Tjo&@kY^5BYxrE3r|2>f*M9ML zEwwuoI0rxwBoi9jkR92?Pe8&(AR;KuD5Kd1jTlCTkrkCfBCKV)WSeurVI1s8u%X&) zkQypGErlYe2hKmgCxHS+c|;ia0lY~c7xjk<71jiykTngH+!0wk@Qk8mz8MklDV3=E z8NER*mB*ouyqG?^xn2Kq(aCK&Gc&}j&mh(5!R%G;(L<}k%2ap-$K(8Bd9()3vQUXN5`#o&Mw z-|3BM0PiYteACUs_v~&LgKVg*1RAUJo4(a;?kkj-X1JJu5ybT(7yGz`mU#*LX*8Z8 z1BAda#w|Ncyf*oor(f!N$*=P6bG-QGu>I~?E`)gR=8tq=hJ5hk1Y6{*Aq#e$3yT+e zRWLOYG^_M%G&U8m5nnyKNdnRIC+wA#-#zS)`aW6Q?4n=Xq?!)+7aoZV1paMvc5Ok@ zQ-NIABolD4>^|v4@hHs(Seu&?2V9Uc85|*FS2xcE(bh<|O^QMya70cEYSyJ@wk&+N z_0d6naor!{@1FI=Zq|LSudoouZ!@yNgW^m>?r)qZ>|bp@NS~fvJ<-c^q|(=&?*C&| z8Kr)CY;&c{@Acyy-PE6;A5<&5F5&fAnbOfN)w@ZTW*~;NcPO_Y)0SUrd_iWi&rm&> z%`YODD_Fy5@4x-;f)stWa0Qo4PUE=WjGb8^Lp&y}mRn!c@@ zyVO-Qz^6|spRW1%yJK<97xB_{N?Ez3L~ceYhCj{8bw4NF9Fq<$bE`?)T$R_MM>$-> zq`t;f*uUnZ0E9qx5?F{uR)P3uuN1}gJ$>aw^xhby<;Qz@^~@(e!LE-bZ$vpuh3Ku5$8;aS-yzvkErL;fZ?UUxC3D#toNw8uY!BoxZUG+2EG<-9#o>EuY z_3?4`;r9^pVU{&(XWqqoN$s{nnY0CU< zH=8n6X?=}$%fmFyVoPFBQ){_2VO4_G=a=I5u396Em+BjwDH22yZS^TGctN%t2$kYB;7>+sC`rSNt5ayX}F>^8snbgiEY^LTQsY<(7rsmxBa+>rg7#Y5%w?xg<-- zIw(az0RhR`@-(N?LSAsrwjPkan_Icb-529_^5aig{X$yqUIw%d}M~Jp`_Hv-aCXr|dsabs(02^nc?Y8S6hnYtIMPC%Q@POkhcP zd(by3vYW7uO(&;pMxvZU3JxNGa!W*MhU9F~3u^@n0a6usLn25ZW}Nb@BaoFP3lbMX zIt@J~1IN+w_{CqiMb_7QEy$9yjF&~bH(980!B;Q zK_}^Rgy$@eT?{MXX)_&#}wta9(gUQKF!UCxFI zL()ubh_%WhP8_odjn-KCl-11ixl6WB$z%pX!^rO3TJIb>6n@Q=OzC zzNs0_rY>2kgmq@)Kdz!2NDvYaFb*(uF%~l9{_Jx6<-hu&V`-Ni`No|HLi7f1RGzi; zmyY>XVO#X*u!ZmZ)VEa-YGX%&A9i)qrWZd#ZStHG)i@jh8Z{W)Xh^ix=Ymsv;lWs% z-Sp}r9IxBUv2npB;laS0v4RKwa9j4ukDZloHV)G(_nwurjpOoTW4Djo`+EA_WAUBI z%)*K0FNL4aW?!#;x5+;;qrUX}KR(cpw=uk3-TdyS#%>q=S7qn@F8Y-G?lBxFewXTx zkDir}Eu7FF56{Z~Rxa|k4EA^0^XKD-gHD5fI@sT7(Op6I^?hg0za&hP;`fXD$Zq|e z@U7&{#&t9$#6sXdbWE&b83KMzpnTx>ic ziD1YgTLH%@ydnhH2+JVB4Cr6y0D8yDwwPk*bs(B>9?c9&DLsi5ZZQvOU_ft6$ZRkf zOr=(I{lQNgUmE>qM#2AOOO-kPubVW4z$r9;>xejR!lE7U)EtM0ivBm>f9s=m&nf@7 z|L)<@OB2m%XHV~=eNkmCiaW6_8H7w5>mi5u*1Sj!_;V5SHr z?EA^^eO3P98*l$wIoRdzdU3$NB*=<@cS>~R%Ukoqlt&--i)r5_y2d0FO5YF}Qr^xc zsl{V90yN0ZLUK@%LWUOX`pMxo?0J|Ac3{|Q2#dGVK=`gTFhmP3Ev83=qrK5Mzb!@( zFib*1Nc}OWo!ly1TM(af5N0c}l-&5(m>6qRBv1~AslgEFJ4sU-z;*Uyi`c>{$Pqu1 z!+j!hHa@9RZ#$>m7XZB%*=lHFLse&+q<)x$4vVOZxVfyA0-6d8cbMc6M`}*S99|lQ zst&yrQ!^Y9?6e{(zipU?c{M9>8WG$dWMjsP6ZU;wNY0CET%gbPohO+_B(VRR*coA7fO zzQnbX`cO!I>7VW1bIeadt8K|ehkK`((mFwRM>DFJ+9JdPv-jG*UWj*OYYq8h>EgLh zwqaoC!sfvRjBgJ}4Bs$_2+$V7MPAZLCz~2p$PKy(-@MSM@Bv$cYM2R&i8^x@oTA&o z^DG?c-IiZtK{gl-NJ4;IUH|u=TprmQsD+tzQp()Vk~`>PC6xvOI7FvZpM-6Cp^sG% z@%g^+_&GM${$h2L#PVwU!L4w~S*T1bu7s-imwJ}nm3w9-SEeMtlEpf#>`TNu62`k< zk7YVSvZrz?`?w-m!TcSG8n6*JBiNsL*49cOYSEiLR#qGdX#a{JkzNrK@(laJ)Ic#a z2}zxPd1<)kuAXbJ|J6oTdMieu5xoWG191ret_+5BK9eA{<;&q*RFkzRxj^%A(ojyQ z!bPz{R&efc-PMI0<<(g)NaJvZd4Qe=e3}8oY2w!cU|v|lJh~R>D*AWK&NcuJW1ju2 zu#?GcU;UeR=5e~E19=kgP6lU6tF4;OF2wi|_|1U<6rO0fUX|!Yr)dLRz>0Ubcr5%kX&BWx4MPcmBjwrXAjFx_%znt&9GXNU{DcQ1A?9yvrS!EYUd+SI zA10gAa5T)O+6FBdgmI2+xT5wTk0@54opkGNX;%sy;y55&gmu=W%=B^_Lk7+hnn_=_ zfnI|jp2oNW5r%bS1L9x9ETo-1rX1ysLi3DTI;7U`B(~MZ*BH;o(zF=Avm-m32~3Kh zvhu{y#4>Y5v4h6cNz9PW#$AkAL@v-8LM-520W$Z@T%tu090E7YgVWd+l!IwajKsX1 zm(a>};(X_ie-H{n;QF(i^NwkNWjkq%Mq~$gDjeV#Fnl@P81f^#EA~NOGVB9qwFF*f zP-1wPi=!(6e;C&S<_tHiJ1}h6>ZU8|bN=|-_lUe=wz3wSEdJ(@Pl6r`a09f5Jd6NKe#b?PGMEx zl+gu_Nttk2+V(8W45LJkVZCm ziF=^;>&DE0a=dFRkDOALT6K5YTpgUleW3Di2Zhg8pIoH?eO5USS+7G)$AVS=vcY`7 zJY0MH%hQUfK2<@F_1ibU4|;GaE;u14{4{R(()QCdw6b>8!oIM2Hft$arW+(LP2WID zEm{ZGhr3&h42Ozpq>rKZ@||xXL<#8S`LWPJXTA0ht`*&yZK3lF2nW%&JUJn8W$XdE zM+>oI`DHY-CxP@vjx`SJn`VGKnucyr4|5fm1qSSC<37vaoeV7rH6!sGfSho;LDaRO zCnDkoN=3I?`i%xWsv^BfkdJMbjb8G@uy@EeXy;I0-FK9gKgJE_imPXun8LHNsRI!; ztTRLbz%&iRK86}_x_m>C&<-`|An?(HFYm&1-IDJ_?lJ*CeT%~}SO&J6N$3*#)e0st zO=QMKiaF?|m(!)6^>b>K;Rx6Ogb&ai5PO8rmOxz2Ee0`RA^uoqL`d9HfwHU%YrQNm z5y&0u$;vdN`iF;Tm%2=Oyg3^3MSCM$YBVmZhO_J3kpIjPzeP6p`ny(#x>TGI!ELj} z`({?N1tr5d(RJ_4uK9&Rg?5K8PJBB4baSrz@y+3`ChQaDD6>!a8KKt{yf1Z_{4zL& zZjLxa#-=pv_o2BUwD^x%hEfYjrGo({%OPBe(QK=CWdxq<{qj4{WXQX(gzD0|&2@N@ zceNVa?rtF?F#as-@hi&rd*m&<8Y@FR_DS#ZEJCYco;|2SWW317__ zYd~{ZW2&)6?x(|JYa~BLMej@_-^)HdVtst*7E*fRa_caq+nZ_90N@oiRJCPkE8;h0TcEEIJ;uwJ5%syG8{=Rv2LL$CloA?VS9_GGZ zvkH`cjZZ6uL#lv)D?_ujexO;MSNP;GDLgUTfVHHS&O=^c1#qIwT~&T&-&JLYPj=;G z>&=B1eKk_K?X786`b~DZRXOvCk)h*_`-AS6*x|6Y7}-yc0#N+9G<=C4rM1uAjtshI zDxbZx`ush>+FA&v@5xnGfM3)QSYK{cTQ770?0Wj3=s6iS|8eHAeGi@)moES1z;h~?vl*erai}1Gm|^q)6?cp-m_oI{`Ic?@~4tL z$!mXam;YS=uFjulOVwm#_t1$D5Ki+IhIQZoomGH_si!~a=hpn@Cz*QI4+4aZ1z>K~oh6C3gmygegdpukovuNDIOae$-Bv|;1)b-$S@pD7SW zJePB_)#p!hQg{hTia8s%t%E0}M6dasKg~(NE*Ip*mTkSZDP3ydy%VDkR4Ot1YVZSx zj*VX*9aW_c*}>iZ%kUr~07KuWT7Qq~*M0u1A7Q-IjsksQ?*Rc`T>I>v+1_m{{;>LT zaI&|5-GAz2dv4nB$hMXwb+jrt==%&94)n?b;eaF=xcUUMkRA%i3alp03?@SpQofMn z>}HQ)vXuiG>k`aiKgN!}@jv}Q&c2(F)Co?60Cx<9DaLFwRZd4l*8T45kd$ic5L;uB zw97-cLpaWSLV(#Brp%XndYeec%2oXLkTt*1k$Y=oGD0Q1(&+`%}e`mS*UP|ue@XU@^x&l-H%;=4(37lSArI4id! z*l-RchHc-Ykdo#Bm=5c?%p1&iPWwRHwpqs=++09v5N#||e?lxhp5tFw|A%+#R_km*;bbkO-xnu1=4?P-6&$F#NQ>?W-4Fb3%d zABS_>B$x+4f1Twdpuv5;axTs_Y-Gf^1Qh{KscJI6{qFzx&i1?gHBR6CB3mbA|8~wJ zfNbWy?C+ViFgZI(?NXpPoP>xh*dswy9S-%#Uc`K3Tol$h7hie}su^0#%I4OSW@<({ zrb<$^4TEzzhN0Ndbr2P041jrh*y?}wo^mh>;>Om8@%N|V(9BBUxsPW!=2gmDGGCpO z?6qez*;&&Vb^wXfK)1MhX2+CW{kvV?>&VN<=f2>N)uE_!X< zC*&s&5a!&W;S)p|_ykKp3{gd-;Ej;w7}Lu{OlIJ(hj2{@vZ?_M5?NYf{eB{tJULFi zKx4*)Vxo+X^=RHTHTwp=71Py&H1IK14is<{NgW0O4J-{bFYqH^gHe~V3&g%i+9Im- zT7U>6=5A~mHXy!?;4Md)kx`P0 zoNXv=sU?h8j`(Z|s5g=n05idN>AZo{_^d3<2_n+;Tkg_Lht`A`<~y9oZ#w_z1LIUu zy~x(c(keV9fDlyCD!q2soB2%V>&_n&Wtt5TIyUs8c~@rtUpL@o|N6nWs^8oA&G&0Z zeyo1bU;9a=Z`-VN)62}>gahoR(c&3Gee!9g&KbvfBj_7Hn>ul#*t?Xs zV;75Gq_YcykLc-@(Pjf+A9W5u&!UkEQ`wt(x{Y}tD!hK5kk$~OlTD7*L)J*PF$O1c zF{Wn-qPkfCsiV^`FJ33%bYml|KbYow7i=$eZd-rqy+4?g`!_Yv?^@#!$!M+ewyvwo zt5t+57QF-bOx{LPLb8X+$6IkcNmp}uJ>!e?F3QD{Oe?CYHjuT)8Q3M3DI9Zj0fJPS z#utddNF`r%hO?oA_IYQ7CQl-Q&g5khG8=g%7%{^%v5;DJ_sly6{k;94AK1I_Z^G{J zYr%%^g{l|+Af|4B1|zCrZe0Ns^LEs$eH%1C$B~(WbX#Ke!I2eDGDr!r3PHM>4wAiy zztIt70bjwU_OTVBQO!b-GE-{tO++k{V}F1Ex3R_$tDcv>3M$9505&66X_asUVb)*@(Z+3;xmAEVSLTz&HnLXJiG<9wg#vq#3WhhU9D*e1 z!H-IvDjF}^WAZae3b2M@aU6GouSxRH&j5L|ITD?gj_lHaM7a#y{AI<-DK@=QS^)#Z>591aY9-XBnmLcojB zSK>-+B}>ddC>17n;w6yd)>Jl4w5u#R##!OU*P8W9T#ocCp3BOv*@pBM;-8|; znFg6ShX|plf$d!gRJZ{t9hJ>sq?p2?nDf%3NRE3penw<-$WuVNc|AyrndtUZZE{|6m&>LIYf|!Q`x*b5meK?{m9jRxgy4FxwVuG%xo^YjaN45 zcxKT~vM0r)JN9xo*6aMly|<7kxT?;PJems$9qRFQewF(3jz?&MEGY!A!3dAsWX2$M zO3AzvBf~CLk|Dn&)3?g!lu+tpxn<%NZEt53S3_WF3v)ss$%hckXCVUacU2oB#mh`6 zcUn!GbR8O@Ys4ad@zqe=6#9AQNTfe%)rrQ-jR<{gtqH3>A_PwmM~Bjxuq>+T5-g1}=v<5gs1Q(q^iRMYjNv#&Y8>sT+f0uIP7)z&N@3x*FebsZ|M4~a z3JH~V9upe^f5R!#O?Mzw+sYpi88BIyIRH$>cDBeg4N$6~B7s6S#DFE-Po2os`UF`V zA!``Ts<6Gc8Usrar0!a*z^ll2w5pm7xOw|qC$@u3Tr`@KMtV1aVoEqg)^v<(n$C1Y z=ep+F3EV9U^AP6t_^2W<*#pUj(?IoLo-A5h0N(sEw0%8JGN_f)7Pq1$NBqR)TTQAN z;Jh$MJU0j@?Idq&feeO@yhKicfZJ~Pc?VVF7K{U()Qz8Lhl;jzx z#s=P6rH0)$qF4a52A$xgITtzryhCTAgkw#hS8<|(H8W##()_T`QHkoLMuKV!&nJwN z(}t9PJc_Y%mbAGq+nTvZFwvW@Q_-po<;TGSi`! z)Ntet`#J{Lw68X6rsV{N91fz7VU{B38!scG3)E_x1VO?6yMZDNqCW$Pznod3m zgGS(F4Sms0>+V1Q!M$X`&s}Z!Lt;<_W602*TnRk)=`B2eq+73avm`J5(iI)+*p*T4 zXwKa#pe(l*&qYtbASu1pR)6ik-mZjg?0dDwb6h@Q!`x1VT4}9IP)OKnjZ*shzznJY z{7i|nnY96TU>oWMu5js0PW89{dQE;|Tey*oT?sFXD`E>vqAhME_25R#4}K}hpJVU) zr)|A-qBRumVs^jJ5UfS+9l^a@!L*#HqLgAK*X_dIrKoskb_1b!b320bS8KqMR;&Tb(nocy3 zRClm~iD*pi^(+nJSz0@FcB+VcuAt!P=G5Z`w4(;yq53%o=RFr|S?l-0%6jxkd<9L{ zL^Xp}5<#6r)>0k(OiZnW$|lYU`lOF#T6FVu-VS!t=9OYQcuJAii+V=I^;^E3b!8zI zvq}O6T#t3u?RxROKy8NivfZO9=(*e?$yNVvY1n;K%=uyI>p|mhY3}%y`^BCLP$HST z4oBhjN~Zbf1+00A1;bho%v5Fp9lR>==WF|C3&_7iyuF*mFOZT+>^g?EH(+T^&<+5p zgT54sv2x}=?*lWeC4Ez8nmcmWPg2n$LRj}_+lT0P0XVhipK4q_b5&qbg)n^R@8*)b zyB}()_rqlt^_O^j1d9NOejc7hPR&g6kyV;I91qVP3ds8S=l*EtK;@;qZ1GJcHyLmm z{27%1(B%0-?!ngi&x&#@Y6A#F#+rS;w)8Izk(FX^rFH)ONQrv2gbb-OEC=)o301&0 zN{{e@i?LkD0Ys|sUfVzmv1832GcZ&Fv2uXxJ)e}(7}SgaegNf1rdrM4iO(MS1~AjR zMf;%>p?;uvFUJhgq4>z-t{g|bCxEK`$w$_Eb9g#~xGVf{CimOE3_iJ zj)WP%>qbbElD2_P?pyP_H6XWI>vX3D7BDqr^fkX51O;fKW(JgJkd0Wu_X63O5_~sQ zmpRi~FiS86buByqLM6<2(sf_JSTa^l3QqGN!^{mJ%ssuxkSd~OH;Q7}2~ zH{$;7xy>Z)|1)+8Yc#BLi8WG&$MZv~YrV@GV#gcai$jM;Gx;^&zb)Qp`{DQb47yHp ztf<*~KqArt_y+6^kcx`pH4s0AC3f0_+h$ zd|oYm28mBt0(#C0_igLD5`Ui8b(`ldCEDFh21aH#f`EVgOFuwIdXbXGQCVP{q_3$l zbnmGmmagosV|Ks!MQ+v+E4aWW zi@=6Rk9?B;6=XDYsO<#PoO+w@pDEz+4f{Tn zukfM8IQ5k?<>!cNd4Lel(_5ksAd0i)`7>}2ED30tI^|dAfnOo34QA8IRXFyL^oDoS zbOyuGHpW(4LZQ10ncQYhTXRf@lSY!J0aIHSPs(V^(s-gVvv5@vu!s_@{2_%le*>vul<_Uv50 zlYRvK*M1y32m1*UQNOx>$8I`w2iy0o-+c*iVA;RZfA*eejd|vicd5%oo~*s05jz_D zShqpi{5I2BNGJnS_8v2&BH7Gzo=K7vg$1WA04GJ&e((z4BbU!=vnV6_00ICgtqo&& zob_>Q&#ZOe?5uMw{=JVlr!h9UJ|KWc4)Y(|is%qqd`wMsHHL%I(9me~9HZS^Y?%0c z+vz5&Z|aimxk!71NCgcW45|hUJ+~Yi30~R+5Z!JAPJu>Yb@XI&Y8X);SlZ_{W7=4u zd$ob2x%H}_JBR!$q|!KKYbrOZM3Np?%W-uX>pH*x*qE!w+G1EQ>U+bn3P1S1&)xDF z)BqYpCIK`it>nX){z)a$=OWkILeC+{u|`68Mz|FSLh~U!0*yxm@V(zCWa3#DQ`Ep2 zZwXW_*>y>4!}%`QBmAs9E3KP(dbmn-{aarJ+Vg$~;G;D3#_o&0#;zrncv{^?FW z-hci#`FOwf-%~!`ziH0@eR^RBZEJt0|0de@51$9x_Mi9WZ$+eOyh4J4EF@AOyKZqt zf%O~?vP2vS<%9ny13}tK-o_W$j68R?$Tg>8i^4Vu`_CemZ++~5vysk*vjyLtn*45$qZ33egQCfi>w&yScnM+qzM%KTpTC85JqU$~sxg1@h>tKSl8Jh7WFn@3 z>FFTT%GyerZWOfaWG)J53$ql{3Z>pKFG!rTDD}Kl~WULJNW5FkZg_F`Y{Kg z#+EQ09wRmbyA#HlDCSaqG-$Zie$CQvJ?Ho(hva=Xkd`D9gaq3q4DJj+1oPu(-x-ZS z#E4cA(nm28f>TuDdn%mzVeV`M(N5&jA?6VXd`OZ2{d5yAz9MjIV}Gp3t@}w3WR7#( zVpA4(N|ooBn>X=f6bK?3Lj#{1eaBRf*f+LDUt_NI=u0`)PH9VG(3 zf9;@*02wAoZajwSp(&9)MHdfK6c!`9^Yw-lK5+`EUJW8=X*NcgUP?v<%7~Nq(wC>w zMKYB}C)1{5{b7*IBQe~*k4(y)*Zy4vdcjLwE8-FWRCFuxYM7JB&o;bt4q1wjC(GL| zAt&18utGEtFq^CyEY4~YS)lN;uBID76LPduC(vXrT%%>2poBsnA&3T!B#|x$e9AlE zc5;dC1Y$Y^(`3nl8@W(J&BO(w1?>Vv3!Ii3CKZ#K)bU(ISokfIO`p^iv4#0x?_<|mo&{ML4S3yo(bNfJgoAw}@4 zK8UQ3x&yM&QcB&WYCA#Ojze8o2o&>n+uKeew~6kH66EdbK3k)aNSC)6P$ks%qP*5h zrh&@>#nW1Y1)2N`mC&#pkH|h6+qe>v&v3ws@LL4=$k@qaFTs%xDu#-E2J<0-8yUdB zl&)p0X(b6YWM>_c)R}E1pcd7AN{$#;4WSCCNXp={n^-b|y9%7?&hxj325b+MIu84x z=?>%=y04f%KsTce_-nL^2d@fVFp|Cc1!V(YSJG zL>Z=920}CMg&wy14BwIp4yxatSC5Q@~YrpbW$oIpwuz9xf6lV<^ zusyh@%cU;9=DP`~1QEiR zZ)+KNAU+w4)V#${(HM2QjYQ5nALBlV1 z;^#@CEz5L1?%DB(I@gX4pl=|)i5rpBMJsUg?MAN6)}aNbqw66X*O&g(97M~9>(Y&y zPSHi;8_oxD&>C}di5?7=QJjwZXmA)E0m;VQ!9dfy*kFOIxz1i$NMV94^L0#iLi1Y% zY9Q^`UYqEJkA0fJi1_!B1ok1BU{FUWgHVsfy0qB?Gu9D>2e~qSAOg$Y6{~ zkhX>4sWI&*H{c1%sG14|p;bvDw9#>qb3e%@bF#3#;4%kit^3J-1;v0Ywa5WW zuwG(-zi}K-2@wGXjoi1A84F!MAGZiniD>)-ql5Q%lgiv6eduS4Z~3bF>ikJ^ zd@U}WjOn*0-NtjP4L~eel9_)ey+0^ror%ih)H7;7@od~^;VS92$6KC&fI_?mm}L*p+5l`{o>7?5cl#M3RnN$>%foJ#ii z03blPk|mdXyT>iXsf+c6Eisoz-6H`eGj5f#fk6VT(plk@|5}!pSiwEtBS@w+04yo) zz5E@gL+=pk{X*}o|15*I<*l$BvYZytif&eEMa-XS(&vGPAt&M69~#G)Eei-jyuFUXLs{A$RUZc$ z0C924e~rcgLj`6Br;af_uuX50XmadC+PXfReXn(HheiLuL0|rN^+N4668Y$cB0S_+;19~bZ(wsRq|n6 zt$DzFiQ>@;M}s(vrT~}BJJS+*fXFq9ssfL1+inuPX38x<1Q`^xn!Yb3zdHBjKhD5c zutLm6%96JIWYqIDup?9ASFgO9nEu14LkbtJH13run7q z3+P~4{wP3(a`FblFJTy5s~j`r<=LPGbc{RYIgIT#ruH3Z%2IHWN3nL!KROqFeD@D{ zH;_kVA7ZxmR+pWWgndXb8zT(hWH+;s!gjs~>i)DJ-Rw7WhQv!tFkv@PEW=KH+Ml%R zawpusS!Ee{TSmo&LFy(g0c#4Sm(A3W8{b>!2KXtm3 zc=vs@sQdPz{x0+d(9*A$kbvr|^&xa5GOL1)#&AvkmwAL9uy9G5~wMvBX^o= z+e1CICEy{g>$C@uAAlt_SGbpy!+E%gyNLj_!&w<=oDQBk*%<(^B*GFixTIC;!BIqB zfV|2v7U>g(v$KEqAKx2MaBQD_jj?|F+R)H&QhIJEx^51=z&~$t)PQH9vj90~&|h`X zOQN+Q90x}~+(vzV#yYWNCBU9BEtjdwYLV&kNZ&RMDv&4D1T6q)=9tx<0pCn5ezf4g zWCFVhnJJ|dVYH*)iPj(g=gMblXu!P6AX}BGF6IqqxBSg&w$iYm2N1g<-rdf3E*i7WGXa^%!eFoQvo4g8B zpMZvg)&{OBQKPjznwq^PO4BXaaBK#%vaAmq@9}%}p13U>s{n#-Esx{7NvzXjMVM3X z09hrq4SAO*oQ2Rbm2g`hX3e8Y^EpSjF?@^n~P0{!|lp9c<0{{aiMVMyS5qk@q3#I zAFaG?fRXQSontqTLQ`Qg3c_f^n`d->dsCv!0o*HpYYRIoo_bIwTa%Tbd@|}zZcU0A zsWgEonoNmTNF%SZxV9%2IAh0c8VqSXu?R($M z&noICeS#ff>0fg8^qK6OUpgcBdu4U<OuNnmFv5Ik0H&jqhBVX|%qm@1G*~^Y{&_s*}qx zej4sgPS6ca(2f&Y)!$U)YW#Z3Ee!kp_V^PMQzYCkrfFYwi}t;HDG2+nwCu@IidJBz zA%ix&OI2eeJvZ##<9x zOpLjo8VXCvsRLuFY6PqFshP}5-&>bjNbu@Ar=QC_^*-a||9`Vx`#{Ch=SUa;u?*S$ zuw1Js?cw=qFf0OHx9?VD>i~2MvULE^89_qeB`0h;NSK(gncy6HUwYa}<}))1^PCwk z*cDVX)&m5ZaY`f;u`_vu?=X@d#K<_BWXySiIw)tdtXG_`A*8<|ncM z8KyCoV%hIr73Up57isUdUgr`7T}f2hW#+QNu|DdcBq)lVV%n38h-6t1Ko1Ghzco^* zd`GH{U~76Dh%WF+kYOCGglh{;6&RvCL7{mqJsy`Zf>EwJuquEY$vL1CU%l@g$*=b2 z<00_|iyP!kfSGPHJAynyK1R+T85q0Na1_Gu;4?jvB~VI732@Q8Q%AO;D<+2k9A1f6 zM2Y(&g!RTjf}&KU&d@?OeOL>r*evjaDWq*fC+|dH7oQYfqN}<{i8~#8NpUuoON`8^ z{f)({ev)8{dp{uRVKL$0vGz7UMAEk!Z~gp!v(OsQz8Q(HKMRVHyd@YpvZj(2dEt02YVIirI66L6{A; zzkt=sgz1^c=1b;Oc_REbgV6=HFv*>@PkZ?yLTQ`()(n*>eT{<@wHynW1 z77F+noQ4f7t_oBc?dbIB{b@wg9yf`QSSbyjh3)`M-AuOlGM7Mc>a)y1JpM6R|WK#(#^UTHdRh?myr@(EP=_Ks6t-8FN$`lWyw(15~ z!)>fVFar{Y%6(+)P1tZzNZ>G*WNTb(hAeWK-r$LfoH>D|j)mqPXU=QivYFC#iOC^L z0+5UqmU2OG6vEL$E+WkN*fy_UYBKIxrG}I6B=3_3pJ7R_4S7lur0BZfMqedP7%NQ0 z3|j7{=axj&VdW6=?opI;O5Joc2owNSr=``W{4Dz8?K`hP&@@C6_g95r2^wWMKy$Eq z1w?=WiNteGv<-0wC^WDQ{v(#6k?3{-p@kb`AW3W(0TQVXDF$k}Aptbx(N&3%)ltYtB!ah7#{qEyB%TJ4oL3 z=3`Hg4cxSI&oI%^QGx3)OPeO+Kf1%Q28gRHYth*cm3|JMapa8I*0*}z0n;S%Tsun* zJO*?QK1%=%gWJL3tgCqY2G853DKo~M0aA~f9SU&uPD^ky!7&RC#wKhS(7Z^HTw+!v zAuiUv$Y7Q2G2fU8fdYQd{Z{jb8VrKZtV*KZB~iLOg>JE-bg_ggsE-^&E@qRDL0=?D z9dsfd8}QuW0#XY#26Khe46HvY69(p6RvxTMFt2B*#42AGJKizr8b^N_D@Do#h_g8jKYztZ(3vi7 zZwW4d9wf~qaWI<%HEFO;KuDf@AGmhyj-Nf$a0&xLaGYIS0fw?MWwVqI9sa;6tIcU#YG)9nqewh^?#Y zx$UJ>yzrs4M0=)q`0C+oth=(oH;T?hekql4;AXFX@$X^Ys(L@yYiU@DpAUw=9k0i~ z@tMi1PsLND7%V(1doLH2vzJdIBFMQD$=1}n*3Taa(l#sTZFm?Zm8Es|7{aDaF85}~ zF2yrUm1pPR*o;+*bY`v`OALNj4#L+#p2*hzMv>5-bo=0dSd=?TjyNGoWYS?xSU%aD zeRG1OHCRNE{3O=N4Q6KuD>Yu^@+hel`x08 zgQsI65aSijiD@~rOtVw%m>%Dp=koOn{xSPd5k_Ku-Ot9sSu9*XE9qFJA5U;7hSTtz z_Ki&y_rdjQ;Kg+u7`Rt*gX@;)1<^mdxrtHyMx%;baW&s~tbuiWouz8}aqj5zR}!cE z5tQJOu?kNB`OdHN&(6sCCmM&bxQ2h@FJA3HEq~p2HvUE{{^rAP$1^9wum6)6zdJY? ze*K$cFX8av(iNz+i{rX`;a?A{=Sx#WmHti?S@THpUxesOs-Hr$?)eoW`dZh6 z?0j+EFO3KIlequkH_)ilymTb)EV}m|@xv&M-ulTo7C!x3`;XnAhTZ94+ znibZ5fHQB2v$Jk#YOc51Dm^;h?_g!e^4!N~`B;1uPYpar3J)h(@C@00$^2RF7+iV1 zw}fo0=wZOL4?hmLs?_EhXmJ1dBcCd{=O4l2Q_63he(N1UU2X8OK178pOoH7q&&2>O(2!5znY96>1FXJOC!At@h^^N zN$pP_cvxI+$-@QVyg&ZQ@qKo$c1pwXX+L=&5$pc>51A&M-?49-n16}b^6vPhVOB}7 zmST+VkZ~pg^vt1E_B}Yq_HaC%3E1EG0e24MLzOijX#nDUi8sijzjrfnu{Jqpia_Vj z4nK<=vn)xc#*vP?^+4>1`J)F(*y*b|IoPg0_X9gC^{|}o?BQLus!@#qZ-aTs`Mt% z%-Yg@JgUYM>%Bk_ag{I{U*`mTe~y27eg{@-sI}8xM|^C5Z(KVAQ0}2$6t^r^lA;|Q z;cm7u!Y|HUf_|ObGZ#G)hvlt#;NV%OG=49Mt|aSF#enLOSctg?N0zeO$47}ibznvc zZdt=Fyoy(gUF)IE9_RmL?`@zXxvu-p>S77*9Yb`ZSVYP&LUp})-7H`*UPksh1E_}{X{lJ^@_4m& zvYrMT)=(LlAE6zdtWHcaR94w2_K;yV%*luL_dv-<$$B>@=Xm$*M|#Kx&>vOr^S*ok z_kZtIC6=XDfSvdP@|}9%FSl+MjIB}5&XZNU+I;u+k;*jMTP+X=$v60W_x-pmz0pZq zGTKO|XU`t$etK@y{rRt@W;+~dy9*o|H%q5BlRDvDat2OkO}hC7!FhR2RDDijPs#{J z1uu|JF`e^W=GJZ8%URAr2C{wWVll2AWl0P<-D8r0B=sPQM~kyfC+R?r6(p*)7&{nP z9p&1wuP5##6DFDEYWl8HpI8w)Pcxf0{_}fQ?l;PE9v6D6w-xTh6<{lefxs^G=5G6F z4|Zbe-u6WySH>du*43>j>51EBQx8&Y$Le96`qK?us~pyqEpCk>q?6`q#j_Fq@bXq8 zP@wHNN0?ZqYhOqCLlTzFE|3}djn-cBrY_D!q*1)~Dg`V6ircS@Y)xOQsh`{uuQ5N}U>KFmqxpxkn3)(T%FxMAESlSX!5FDSl+x>HaSMx{$>vc18;I0n*>E_I^C)HV>Q6S#v3 z>0V5|7vBi+-?^l{JR8G7U%Z4X$m-+sZr-OQ3vnpxs2D5pjiIo2wr3o zJ~>C{l2>6lj(c>N^RG=5kI5@1IkA9`@59~fT|U(=$hP9Pe*5iz`d|L%sNx?3X3kMn1<*Yl_Rgq16eed_U^{YNe5pm=&(o+xb-RG-2wjk8t(-Q1g~gE3Z)08&Xs(C=(m~8Ovs&zmdAFVW8fqk(wsvm4-@a)d zDca?Gzy0AeixS$-5B@Yi1eN*ay$6l>(O*h?lGw%iz4jZwc=?n{?$w7)&HuJI2P&>N z<;g-N>&q8|!mM&tWPz&0yPaSM56k0@$?vHqUT88?H`AWd`s(zkQvE8}(-YNbKjAmB z?%$jCYoGJAmIaU~u=A$Lb@$O|?0hWq-k@Gks}sO6)mLQd^-))ac_`Qph&(KLlOqfI zgsK!LZfHu97|D@dbT)V_{mHjy|0h^$d**{>sl+~&8-S;AnI|Wp z<)y}XFofWe=M@(OxVWjELrz+d@2jwz!h<5={<=z`_VW*xm|T`@n5W}@qqByN%2Hbm2ZFKdjKriDZTDZ1W%^5 zjyLtN_AdoDrRu60E~R28J>Va8C%ie`(qD?ago%VWbJo`<-S)ZQd8lvUEa`~CVqYK6 zk7Go`Gu_4PUq8KMu*8eqC3(6@pkt1$14Je%=~35N8ft@(G!My4%Mr6G^0QJ<@u2c( z=#|}3bDdVd`OP2KC900JR4L`-?&TB%n1#22Cr{ULu@@!0Oe!i_XfnyZ5R|fdQ8jL9 zm0X!S(Z!|JY-4Gx4jHCURamL1!E zp1Or~0J+g@PyQvSl=p25aX^?e5_iOgKO@a!pt`Vj^1iqu?jjeqqg&>iMASb@eLYZc`p%)N=XGQGMSaNbh+mbq8wDsgI26 zxw;+%iC)gk=_f`%r#s?_cu-3pNDp^Reux3_lM{k;Zgv04p%)+6 z6CsrnR+b%z;sKmMsTbDBa_L5#m!n=d;i6ErAuwV*8)Ht7q{T>@2)>`z5gcEWc=~uh z*VJ#~D#X%-nIDg&hBNViyt*w#+f_)j;~i68Rmb}ng5hu&W6C4=oS(Zd8Tf}9W;CE4 zNIOW~WHp^vdrmH9@Vu;7>Fm*H#nBQ3f#s7FF9)R|oON{osi`OA&1nT6(BV$~@0mgl zID;_IiBQt548hQGj;}gpP|i~5-6TyNiKhoK@M;#gvqHF#jY4Oy8`u5s=I)>T0*pJ? z={d3%dNtv(XRRcz$ijThM0z_-hIO(I5K`Yo1p$8xFwN)|G0cvUCC@m(z@c+82&r3D zfI*4wsx4MF$Bs&YzLMQ2(WrgHl~Ctpe*n?dyY_eQKkN7Mo^$ev%*;nhhwg-lJb569 zWHRKR_H=Y0K+KjsrH#`r+`(Z`9_bX&1DG-NBE1W2X`>?ie#0e?y$={xbH(x0Ktipa zk7r$>Ogr`BzB9XG4T>xn2{>=@tAk%>zwhZ+sxUFP1gKoT+zFCFS%V$#)=lZct96F=yXYLhvk#2ZAjQSW&L zR8T0r`uB@CA+1*~oc2rdAVNVmgmNM-?DWT=XaoFExJSvtEWoWgo+tXrpo|M2?q}Yp z_SaH~YBXIbI|w;m&8%4Q%A2UYytEu&2EL0TT^TM-3+HkSZ)Bs>Ob>|si@qC`ZgJJM z&%MjHM;C%7tXM^W+>3ExED-ODj5_Jb#1e#A)lO6sEA%v~VR45piahMkg)Cg)-Aort z`cMEDn`Mv`X$&W2q?sm8GsCx!3)Z}#S0u2D$<*F;(LCoz+~~k)=)ABpivm155{wSr zDhqQ#k#9NxVp2Mnb*qkySE}Og#`Y>TQJ{cE;^r#itbyDOa#eCS5u~(|6=t8Dfo2Yz zc6vy%*gy+cc>S!*&4G|uY0g4MD>vb_+kPQI&wet4;0&5Gm${DWE_L$KT()$o(TR*h z1KOUQ*$AbCly)-7_9R{xG}ZsP>gD~0&bx1~^` zFH}`VDu@fSh46)A9&?k0<=u;im4L(xyU3rcZD;m+jFaP(6)p>aLyPkhUKz@Xfefvh_4U^NT1 zl*Yljm&r77d-Ug`EVP`YmD3x^J?#F8N()7UK3_D4xi=Gw!GLnU$5An^vXmrk z#i%=~zinQcT3LBskAKGhcbPx9S#LbN@aX8*v&C$51~u^5_Q|D%fi|ztEpMMmPcEiw zoZzr^kEVHL8}t{S&#L+2$g6Q7R2RLQS4+)~({y zD}~#yE}EICZi_*y`iU)Zvrv_VCGnzg_fJ-@#Lu}8PRcu`ACGPYuB#rDzbanuzr64l z{a3`n@dw8q!sq9FOCME_9^rCnFaCi0wsI>47NZoJ33kMNPt*E;Wc@gQbCBZI?Tdd zDry}GxC>Wi-e_=YOK5ex!|f(lJ3C;UjqKwfPp?$BgvoCQ7FfQ2ertMk`OBL0jNjQ3 zr!8E$9X__Gu6?-HXswONhbJ>LCq{(f~fe= z`q4`h#hoL&EXE^Skf@H{8yRAa_x8iPKV5y>hm!VDx#m9;KCDCY%B97pRwf@=PruN) zHa@mC27XfnE~=3(Zs%w<%75oG)kl58udl8J%}a*|P)#AUec5tIyH9pr)Fbj-tjvq+ z%{N>7_JTNlZ|y^(u~s?apNVUa$Y&_NGWRZU-fH*gZ+|k~+Dp2`FHc-L_zku5b+I)v zwFn^h`TV5;OxU~L`LWt)b(zR-3Z8%~uF}Ce;oM{dJSL*27q8TI`#sm#xCmRcKIB7^ zgX?)@wX}Sq@{IqraPh>N*c`EKewu8C(dVPZzojOdb{?+<{&&Eou+x`pJo!|`#^u87 zY&=jKGEi=>g=0_`8&6*Zq|+or!*-x2^=Kc3O9nMyHo4MH-w}eU8##5M)8)Sf{yP2G zCYL5+IG^<6#m?k*`1chs)yMZp=4pAV6?Ma7sk8Gj5jEai8wzbU! zj=Ehy)O<%z`==LARGy-I$()@>La)!jpH1WL(M!>_Ft~V=3j&qZX>YfDP zTGp>c1*dy-lH4Y;)6~x6V&~2wTK;AY0F33*Tvvw$LAl>eT~qU>x$4-~K}dga6W72g z^M2@j;Ns9jhHO0sg`0cGx|}Z9R??i9`dCGp%HK&|b-FM^`QX^cZNa z)(?fvRV})H@mhFO7fEP6KoC<0El?^#smT)K?v8MHk(l1l9o0rO@d__rWpv@F#*G%+ zM&DAkW2+e2^}Eu}J<&yX@{u68B#uY5p4fPp47wkApjh*w{EnMsl=oVD?_QS=&h7pA zFkhRo>k;trAG|S>CNF=^KHVRPMHxXu(aExm{0*gN$Pl0@Nt1b})k05nN!f5|fU^iZ zI%6I(W=tRO^PMFPHtmruam^zh8^m>YTw_X{bkZYYuUlJYUYA?9i#R8(YBS#XS=l>y z6KLhu-fyU~==&|A`^U#?-Ukl7uXf~Kr*~ItCe3TVL_=aOxje`?7Q5k?CoP#)?v;x= zYpjFEf}4paLM6ei+;FFe7IZ za6e27$dHcSi|5U(L?D`D9Z15IF5!`}`tnc^7m}1gGQKxnz0LdGUT?t34XbX}LjkHgDTpYA|=5 zT||en8aMda+_Q6{v08S&a?0UYbIckP zx8k+G^5*|tc;&C1*k#OKdWN50`Nq$XKk)yAGW+#Eq|E-}4=A(0_#W@}{{M@4w|@lN z^;bVyz)Dy)5Q~b*Iz-peE5T?wgQ?1YO8fg!YRNKY-Rb0so z-jDkEBab$-{@%mdy(q^&cT#ZSJK684ZW1mTn`IxqmXyW3UX{AB417_ znyE>A+{u*`2Xy9>BW8 z528zlVl?d8rg6IObCMGfV}M?WOE0hHV&jJML8FrtNlTAeqGy^9rEWT!HcgtR^NZC{{0=%PqQZN5 zgcuW8jCdUMbFMisWu#WMCntfp^Lh7hha+k}(-W%(E#S_jP85|o{uqTRTzz<} zU7&%jlWH^+iv~WGa$s-wPrJD_T45(!8s^;?5qDt|MqgwWtTqNmsxET+X0?VVa+u4$G^Z@*BBu z^`Wwxf3-eTA4#i)(&`tLubs-H*((AC=DVHqSuRRPLo1~A zwjto}P^<=htXyL>0l&vn3OAcsOB*km?x{y&uR)}Io-CVRUAVn-T~wP6R5W{Dz8*~x zji=UDBORv4Rr#f~a69!+HvI6^BjV-W$oUz#-&fOA3%9cL)NG*w?7pgM**i9I+s*y? z5oYw{A{{xljg7cJxGZKDpCXV>J`~Ji0WU8c&gCpYh28V9dhQV)G?^TLvNJ8!=IoYV zWl<`|60dnMLox+@49?zXX72CD;;gLJ0W5`x^%-f*U4Qp|!f6XDV}=f-WE$|ED-ejf zQ7D_jNKYZQ+#`=u5U4 zpH zautstJXKysup{q=1$a_UwMqjz7AMBNw!Gag>}TS1q||^MKaMIN%p6U$=Z3p4G83v( zut5xDGj*bSMwTUbl`*jN$Wh?Tj_lzZAoiX@W65%!6Oev%n9^LFUx&h%%%B;7vbp$W~-*zWpl3|3hR3?Z8y zvvA^H{`q#aUWjB9j`E#8UvP{wky_}%X{3#9+$>JU(iT-Rs2vD4qJq|kFiMOnr&c9n zlp-oLI2w6pj^`Sdw$2^mx}|;Vk=Rn+^4fapwf!LTa(lAnd<`V~Z-3^;1Y@0Q$JxvI zI&ZTo)xD@blcgm3M6~2Kqb-q0WcnM?E-3&?_z0Yc7!zN!4%xAeg9nN`vh;G+-*{3S zAa&Z)OZU?vOn@gofl2QMB zMqUDhbe79>RCp;z6;ULtEgY_2ju=JsBD`~u7j3Vp!!qpTjm*zE$r7MHew1BC$TJ9M z8j+COp_-A%u#A)hFyxeh$KHALgC1>zdkTFT0wH5e9vqFMo|fh;k^qR;wTy+aVu=J4 zF8pv|u}O4dmM$|oO92RvrIK5a38k3D)=oX4*?%5h2djP2MkA$WT6uBdqDx!is@z~rMeJy$m&{1oioG7|1ow+n<8C=6l$58}5 zP))9FSi8ju)>Y09)ht@O7o3W;Rijj{NAX=Ko1vmzunWhi*_3Zd*9gs(*oh1b*D1v= zV@hML{i*xp=L(U&J!ma!)oy9g0&VUb=}bHk+%h`n*PogCpiVwD?f+7c|H|s+K%YEc z?{~rXZ|+PK`qlNt-jwoc?~3t@Mt#N)!(W(ean_MK(W^A&{7Me}bjgg8*5kQ@>PJ-XmOI%$?B z=es|@bTtUFM`b2PS{eJIfB~8bJkfxhEfIDpszr#6+ zWC!(wfgbQe@xXZZm29Q2`_P?=^V_m2IpNG{{3nm4T^-hgFszRU<5vl+&927ii$;j@ z^i&cIq?kRYpP!lf$aB}#m#frNeK2ia4)&)Dy%GIMA$fiYY4h*Y|@^{noVjJ`T4 zy}>_AVHT<$(3>jFD@1dCCO=I0aQc&c6MXeWjlr|{7`da=l92Z!VypN4xK(#3X;y= zbg1^f&ViM{xrZYJ+W&^Uyb)tP)>@bR^qeG z;hJ_|Y}slbq6SCwpsWpr@(wv^5y$l{(d)iE*ZJaz{k67qVq$BWj_cP>{_|kGWUK4c zywlC^lCEG`uk{W-Zi9+z8egp?DqeLOIyxCKDK+oK^~H=&g)AVFllmbu!=bEp);mqD zk#ZZ&4Q2r=i_ez$6ukm?1*2+YJ5z4WV_Dgb-1RT6ug!FvQU4hMO>dtN*Rff%T$@D4BS^<6!VaZOOqYQIT^j2!Uh!}mY@!j5q zz4L{y#?5-^T-;+wfG9}|S~DGB>&b2Z;xYZ=C8~+roDE5{RetG80ZdC0uD&~>9x!Dl z!Q^<`FmP8igU0W$hBXU*0OT~FwO2LR*v4TnT4kR&&32aRf?)kJQ>MjV`~4D07VZdc zZS{0%NnC&n61Ga)ppaILT5#ng^61qTXrBI$lb2QqSQEeWJ@b_;?14W&R0LGqy#F4%C&nAF=Z@Lh%MjTe_Ob8AxA{x@f=GfbVWH2X!e_5THD$K)h9(C} zqizRo4&0J~8wa?Av!pUPvV2ARXV4N1uKg*_STxkr^vrP@rtO-l=kTA18~7+a;b`$U zAK7EjQ`vD;O?gTrxvQ(Bh|Olir2nbxQcBH~*zPj?1x4O($lVWaiR1~<(07R~49o}wX&YEzxr+)6LYF(2X;1D9IGWo9i~rex7(mb6HyryqAno`6>iY*o zdu&7IneC@#PRV`JmoR}$lya`$2{!td^#-XnVvlQuFa(m#C?^u;Mau_4BiTcLp@+oJ)o!4C3 z&MxYAcPTjJ;~-0@`QqohnCF1uV3ByBk|D-#&5jkv5j@UpH!hzy?fZdzG<^Sm7=K^0 zwVVG;_D7dp?(WuZUi*J%?dE6If3%A9AHkvg#=bJpV3g<6(()r`JZH8rw&nX5qRE2g zOBN`9$Gf}|)`c6!d)>=3(-xW>bz|Z0zKIcv_+y#z1L9B_17(*z$!x}L)OFNS)nya0 zeqw7WfM9Qk4*y&c|K_*g9`GO^9kz+JVEzvtIbJ6FKoi}4#P9vE-*d`Rco18;s+ zhA8_t>)N4I+$`tMkFKruR9bsO=F@Z9@9*tbvul2OMqCKK6#VVUR&+ZNrymRyxYAi! zqbzL2O_n;hc19q8%rD-5z=u9^x*!h(mxIH(R%+DiclG#E23TaA%fUmyMXzS6j&;<9 z;f1X*m;|Xw9@thVQ&0D6S+T08rl&+6ccpvUzalX~l+e$oG8q1cBga=S3-w~!>QrKP zWp-p~dksqjcnQAP_y8k5l}8KzXLWD94R1^PZ3FX8W1;xO*n{kBAW|Tme3lHH{^&Qcm;Bq zaLv4bB0U>#L@xMHIh{(e>;B+pJY@fg_O_0*a=~C2&pwll6!*HHiFy(2fIH&$wm<(! zaOF|cLOMID;wAcl+{AHwF)#&Io+@J|JC~<)f%N42g=uFj_^kAEZZr42!lvn!q zVIKk8Hd?Hw=l{gsRwp{HjOd<| zYVY>=?8iG7B5Y`_)tal1ug)%Jr~i5!56)1dnEjj5zW|Ti@f`bOZpoPLYObQbCBB#% z20x|S@d9;6i`DuA+vR4K>sdanjnV_ibh)O@tu$|MMa;YYuzcYkc%}0}*pg1^$5d=S z9?eFN_~wc5kU#i%MT;+XqJ#1C>XoUxF`J=--r9F{zY6DMKju&8Nja)-n)+zQ#;TZ) zc1~XxsqUj8*e@aDEk)j^diJsGf%JR`-!ea2mxdOU;A%0>GoRDu|)UW+eDbUy<7}r4aR_zj{3yNWsY(DH|SU(7AvSp}2A|R2o8CNmaQ3 zfRJin2ZRpc7Ru2MfrARfZUw8oI)?&eTq4%hlF|K;-vMw+hdA17<)Y&$^Ti}5!!hJF zcRpS3;E{0iHmF-X;r6S=7cRbkH0R&}=GOoE$GC-#BD4xp1uG;pjS1ExSifTu(fyV$wRVoH%Es!7?!-|oB)KJT zFkGkd0`zB~ysW5?E2rNk(Iz4Yi4z&13!81ORE!b(mP{11wsZf0LBU8+{EVZo<;!0U z2rpg{I86P>k1!4yN-^?e8kxsg_x00JLMk86U0t{Jz;| zSLY7>ySam;DZ6EO+ZqtYia<2#qDY1Xi^p_)ofW?SPmASFDqa7fRpgYb$^*Yzyj@jv zao#Vc)jgz>xLKy{gK_eR>=YceGF#B5jAvUGDoaA>F9}yE?nRh00kjT)$u80eD94KP zz<)R%t@^s*UUivM&fViF+_rT$0kC}MYdgTj@u(l1uX59|< zIKFw5T8d8;z~WqmoKh=0%oBr_xZJ=XmbiMEo;c47DsfpcW?w;J=C(pRg6+aZ-u*L= zgMU`|7z+*-xU)HbFpj!h$VT=8X3lzCDy19NEkhPYUOF$0>JKJKR<d4syTIJ9&oXiRavcs&l3w8kXUd$jja-=emOz5|xO=5>| z_o4U&g+?*oED0OM#D->_U4|L)*6lYqB_k{%?%5!Boov%ffL)m-=j5GIOGQsujI>he zwo8UP$;c+IJz*JK`%rdy^$GewnC%f9!=xZM-cj&fk?gpSJXX?k9ake0i>Q)L`lp7! za8BOtAG$ApTLk;7vpqEd^Ght(wo`R;=N5>9pI?0niu|_U9 zCsQ3hn!WY?=cTB$q6emBeY%?6vppT+dsvwWURixbZq5FMsJavn9!vjcp?*c25xvLL zJH$=$o|n_}!PNQSE4U;+9)X0STj&m{uf(BQQju>59O(BE`=R!uqJnadl9*(3eo;I? zhH9Or!S&s_(SXV{bHQ94aCTuko;?Q^`db2WWS(0d_h~=7isBnCX9L|oBY`GQHZ$Hh z>A#vyPxXyb$yqs9eFaAQ+ zB8&0l>nn@ZI2=7vO(zK`*+RV5I#3>=Py)A3M(VtTELj+|StuV|4j*KZf17JfG+)U^&K z(i2r~_EYjVpTAyGb0m_twk+}Oi68)=c^c%E&%7wRrV{=yZQwtiMgD z^>AKm{uZRZYGi76j;71q!>a^-Z`4NL*nC(YvsGu-K9(L|@1E-=<=iv$plchSbzfSN2Jc6qAiL7{}fNcKoriT3I+Bj+sn&Fvo5;5QG&jD#IuFE_db zjK>G+UZZ|EErqeGYQqiPwvpFMv|D~KS%vjgL+6n9n8I;M63f4!Ba_qJLr_;J2Sll! z{=?~)ccZ;O*`kLp^c65AgEuyU$AsWvZm{!h-FZD){AQWDFOIzf_&AvY;556Y2A#E` zrKL~~qu+YDZE5HN_YK8677g7YQ6!*D<~7!_CYG z0XWL4ko#)H;_tir3@lRsn`87CK=!(- z3!2%|j*MQEi+3{7sWq+|4``ip<%j@OBMMmax0IS5nQ#_}8z0(8SyB-J)7atI^mvgXv2R)CoWYTrY zO$IJ}69jzuiV~&INDrQ-t7~`yL8M{&{+-V=b_K-3Trx{IUVQ( z_AaL_TjF$DY^RJDY8y_!#`GXbc-E42pxj9%Es`d23 z&;gNrD&5lYwFPs(r{^xsCGTnr_FrwkOxbxjBZMu}tgj2N@m=S||0V9E&CfXoit#$& z8@MZ*|0F{pDO_pw;;$ITs5X=#a7dJ?T22^*1?JFwsG)3i4&0vYcW(TpWKX*=CE<`B z*82kI*t0&=jT0LbM-@x))6Yr|I_9bv{dCq_O+F#h$5Cz0QXCl(p5-Yr-K62Gsa(lf zFRz{my~ot1V=A5@x97t_JxG^Lz}ZxC$++U>Xhno(=L75)Apm4mF^;>sOPT9ifO|x% zRIGY=9lLAb7#%Z>*Pibkzf$Yqt~#~lqjZpYg9+w@IDapyUHa;35d{n7DWqBj@&06K zKDnA(s8LT0B_w3nZ(@P2b4)sos)aCZ2sdi0Ih!WS_d5pGquGpwsc=Q_wN3%jIB2cL zgg>8(Mpkyups5er*5t>7e|g`(Pl~)Hd+gssAYVWEPS*Ww{M6`8*^lM`Z64Xp0owdQ z4$$VujLil5M(1CI=9B-Q%K^Iojq>RNX+6^n1agyT|Ai;gbbrdxS}r8w=lyo&eSXw* zCMp3opi|Bx%yx@3midY5xQjLJYLX6ANo%Co2c{Rl3HWl@1<-mt@Dp@)Ew`nJ+ai7I z%kRAR!5?|Hriy*E?e%}~$ZQ!MC;j1{@BMu5gJ$;+nq)O~$NB!>djCZHgix89Am@*} zF!IW3Q-=2h5Ve%>-@IH^V|u%p-5zaBuh#qNEx~lW5WTWJqFX6ZxkGu$Uy6^Xr~6Zp zp3br7o${j83Z2tqY0)pRcCW7$+rc7!eiXNaHdO?FBa3r|pH|Pv;~lN5!wpl*-2C}; zc)maaD?GM;BK?{F{wJcnxeHE7@!D`KSZ3c$6ImjK+EeOPW~En~p4$7S67Trfgmd2M zLhTZa7y_pW89gNPTXb}BFxADnO>txANidql1ttUoI~a=cdcoMuO%HO=xcJ46TRD+d zEjEw5=nqug6}r^wsJSH&sMOiVyQ}?TRxZ+;fACj-Zd&<{xCjJ#e%6qvSggZc$V1-!gdu>1K3?Y>y8{x z2h5K#15-N`V}qIF+tzk24VT~gAFo(EN7*SXdudq*VNlE*|2%&)0m#BQA7J1)lxdtO zoOH>SwG>+_brIw#A$^wP3=%K_@@Qd!?a3{jqHnK8ONu^d0LClz%lR1nxOPY1akwx4 z@e>Zp?jOM31#2B~fr!_!bFDKo!Ddt!CMtq%oZq)&0Xw`AytRk_75OO+xW|bRmOKPgLfNd>1K`(3}7G7 z(sqAZ(bwS{(mku~3#?^g6ZSr^`{p0Z(`Rpd-yh3$>_tem`p0%H=RY^>KXoksA3kEN z=p<+T56&?zRetAFNH%%WHQ5>A9GHTbK)6|&c&gMgI+6&m z%%sBm;waFcCaQpY<@$iM5-@RVt|Jk+#N2P~%73I{X^)djV-LJoaU=)Dfs@F>Wl80t z;EE5I)J)=w#vh&Q{SVp(Rk@-HcwO=b$#F^EqJ<_TpFgF&DzLc6%8Kw)a=6h+ut&vr z?5S>#W?tcRr02Wci#94 zZ4tIr_Rhn{7#p{R{q5S(3YR)~!Ah!b^eZv`7$p+7WSV9Q^f5?rh^#iUvr`A8v^HTQ z*0Rx|1^H>$u?cm@v|i?fWR#q~?X6qc<;YT8EFpsgOn&^Rjo3V3-Tm-s>&5b0uXGzG zQdsB}V7W7Tg>Kt3J@4YOvIpmJVVu${#^unQa-D&5S(E@sizYXDXuA;3nfIr<1xKJ| z63Xg5B$iKr8xQ5lQksli9Z&Y4`VR6)LUox^0)3!8;<9$|ltf>2m8hMQ4TH~?+U&VH zozi<%{UzCxWxta`R;X&Z1@7N{r}ozxt0h0Z>Z8iD&QUv*aW+V&4Z?uJ++rQ>IvDD7 z49yRhwv1bLb)uL=#=2ud@+6=a8JF#0B;FtsN71a?URAL+!WlF=inuJVU-y@K6t;|g z)uyWy&iQ*t?}$w$=dMozk)kHDpCY@>fMiBPug!KqQ`75gEc=!%yhVO{>R=TcX-=vq zG^?EC&ma>9ZB*t=iBmc+*k`$Pa+^CV#@&dE>pDkW`|aq{MSaM)-Qtu>NwxPi*gx+cRqY8m%R+!bz|<89@_ zRyKs#AbgZ#>4ls2uxnuY%ft`Iw42~?Yov}8yS;RtcVCQcu8|ynbtM?ybY9HTW`=x{ zB)h=N1Z#l&J9hsw48&1Y>cO6f&BV90JT8bVBCP~AikstmjBEa(z@b22;^GS&7B9R| zFevwBf+tE|d1(rlsFSisoZQ&3rd3%6DJO`I^rA$x*#Y)g)Q6ZbL=&RWsLK*VEAfLR zVcKru*{%r*Gv9-mj#_L}fsmucV5>2YdzHJlxgh0~UmR8M{OdoR?1^-4gEmfCUDga{ z3&vq&2a$>(lN0B+r_wnm&vJ>ODCumoGbOpFa3wQF6zx(uDJC^6pfyB2QmxpYrZsj1 zOYUVx*2KHyb2^&Lh*9Dc3cOY>{NC?f$D&w~xLu&JC&L>B#PsgbgU#XQvh7|b2Qzy* zqXT6ZQHT8L*-62M<4!PWJa7Sex?l2?=+sUG=McT`3qHJ_#v_oRx-Mr&-q%pOfAiFj zacFdDa)YyjFhxnoz>0agKw=Y#4-FgJ)lzD^P*fw`Y`cQOGj{tpQErb&cCy=Jg%lNo z;Z|L?G;_f@(8Di?^NYSLaUSsLyzC;XxtNo@v##tR2cb_gBnZh({tjFn&AXO7b&pFg zSQQfCt0@;B&P;K3^pAJ;$H-gS!ZMikz1&LYgj7L93S#ILv1hmuVpj<@g_!1AMR_?G zZF1DKN66!nniZ84Kk}=o3kAwa%_ftt*+IxFEZ};W?qNANX8zn{iE~f;RN-Z1S@eY^ zCL)=0d5$CwOed)W=4wO^e^fMEFnUo?+r+pDGsUQQcE`6DtGOfaEhg{Y2$@^zF0Mw+ z7$77@gB02h)_Q^z-Ii0^GHNlHd@*rF-7hkX3gOLaDlK&qV(Z+f;<3(HW>pq_XQh?6 zkclqCWaUn%GY6+vh*J?qk&dt+rUeE%5gHw z2;x{%6G8hv7QhIlgS7wRG$i^YW=_dG(y!&)GicZpWhXXQl?ZT1!1+@=fwMFC5!` z)4bUos?1%Pnq_5QRzkYS(A1*u+ z>#*6WEHBhL{kZg&~@>8GU2z_q}Weg20&Lg zymk94)Dx7EdExa%v3GGjtl8p#w~2AGyu4XCg>UB@gfuU$cf&35jrEI9b{Z$XGfo1Q zH}`g$Pe;@7=@Hl5_?M;5n{TpczhMri6Po2ayS#oYE-Uf`ldL(48iVrJ;+I>CbB*

#|=u@qlCl9CO^ekf|_~c*dF;NrS!-MjbrghYb=7+ z?wcJ7@a48RTGxLH{x&4?=DlrK?sa#@MaQM{wjvw+d1t^0-qa2WbDQ7$&hT!gkR2QV z`08$QbHj-hZL~x)S+!w7)Q(NxLSzcgrFUdiK#3PP*nYO! zqh{NrD=U1MXq3u~=zc2j#7F!+vf|RV61lJ?YDcaz-pEukvp|x^LFDG$JIRT&zVkg~ zJlTdP)1$;0$ThN8JA3`*2UbL$U!a9t&SpXpE~570hlRiUq9n1e4M*WejY5OJ@nKV9d-sMn63l~R}oS^>PYtdV2%3RsVic8-q+Wf<~2^;GPQE5vp+(RWCQrZ@@ zGS}{&-&ps{b3t|U0 zKfYLa^Seo}VZ$$r3*v?TNQcFs3i0PV(_t-t`{v(hw3u3!Ao?dxFx<7oXl&F@73`Ga z3oTB%U5-y1_0ZU`8JY7MuB`=+d35@?qiwuJ4aYkO9Aucsg;}AFAwKo&Sz1}c3E40V zXY+HDZocz#%> zYqV-OrMpLIVQ*!uutPP=~6Ap`#ZE>mwC zxpQQj13#zvG*UY|buT$u#j9-tbMh4eKw@V2O81aRJOP$3-QESn%P?cGV}nb|tfs^1 zZXD1h5we|rpEg!xbNw6r@-u(#{dcV>7U*4gb8%&>F>=PxxW`8l7W4=~Vm4NY%dzBl}aD3D2c& zhzT$0Cq#}?`>a3>CA$hafF9^#`~{EO4`KKyG=_=%UflCJsdI@Jv`dR5L`_9 zO8qE0U#WPXmsf&Lo|BwMqdaaCv~lf=74%1xmYNGHW)&FdqNdAjNLnZ%H+Gnx&K9ZT zP(UgFp)HRm^j(ket-M!b*isUxrx4y+0uzPCmhV^>p zYXy!#e%^<{U_aoD^4B2Z+ba0%-ze@zR=h1Zl^(qP1NxEbr@~i0^sM@eGyfoa_f+}; zz4FB~I5z+B+`|Dy4!hzL!ESZKXT*Cco$n$~+`B(F`vLuod|mDS^0o}$D{Lqa|Irl= zA0Hjvy^{U;>3_2mPyR@9=-Hooud?9mFUnhfc$wZC*K>x?eEq;PnfFE(#J`>x<{LIEPvF%oRXMDSVllcQOz`WO*g~#P@ ze5p)jL!u~jRL&m`C^50VLh>NOM0vua8KK0YzA_W`!Hlzx2fsPxtw_Xh zraC|T=Q@))>~vmy@88CBO!-*BO0a*QiGJnoGC) z<3IQdb@i@)_2c*b1`(1sDhXbl&W}Oa_La3>OD_7X;E_zZz)m% z6IBl;vrclFGqT_1mr3_z>Q(BpxoR}3S-)~bnp%3qpgDd)Mv!o+l(Lkag)N=@7DTxD zLM0{HgV=oYaHs1zrx(*V2g>ven1p_H%D)tu(PeYEb4T1K1I~CB1pi`X;p}J>YOMJb z3f#G@1|@g)iCAz{d)NZxh*d%>wU<`j<3mU8xcddx%51s;b-tFhwy`7j+In71smV85 z@#02xV+0KpQxIcH7~AR%e-Q6Y-I{pYmmHwgvw_IlDajNH%wc4(*=EzPOZ81e2nsW9 zF060nxsr-PgaZ|ap+)c>!V(Hdo{|nXI2)RAoQz{9olZ$KvlL^+N~ap*)Dlcao=>FY zoW&}5QKs5k!x!mRGAMo?mN3Rw88W9|T-ou*!=a?UG&O*rP&7uPR@VzeTA6|7a0-UO zf<6PoWJ%QKy;5^tX$8{M=+kQ4TxJHbf?1Ao0{oCm20)n#;WMOx#*zS_jPi=xYNQA` zD!1vKlmRS)jdhg8h-6PyNJ5IOO$wjDO;Y%Wl-8o9r0?(=r;Ik#sqTz~SNt7U`rcF2_bW?&Wfq(M zZmNn95V)i9RRyix}i)T}ojNH_}fGpwV>u(WE;6UwiU zaQV{jmPY;2BUvpy8mqgDBeM!#!At}2v>#55jE@I}s8?eSDqiJn(!;r$$4*)gZaRwa zX5KVO+B)>yL=ihc&)sya6J68`*ws6JP#>*_$6~$0Kn*H7T@^rDI@ZjJ@>f{(ve~(@v@fqwy`{`5BS_`JVyFQ zeD&kSWO-F9CKh7;L$Gjx4x-(tvqB_Q#P%BV!Njcloi(g-Xb_~Lm#k_|PSPj@Uc#!k zYFXe95rR{9xh|+$X{hC_#7Icr(O_uRqRAZ+0b@%3!ZAW3kiOt!_J&~9o_ak`TxA#yXb{q3KI0JG zZ{q7GQUZQ<&wz+nFV7L$`PjF>W69+&0aP4$qsvmGSzH^`M>BXf$ct4brNhhcCp3dW z(6tN93I@ZdZbsUP28ee&+%5uX7*ws4dhj&tT&P_2(Lveu$^m`JR!$Z^aCg>}9q?)8 zjIf#%jaM30!Ca;a4`WGjQuULJl-b->Nt7FuSsG-K8S;z}eZ%ie8(%jJ9iJlAHh(w~ z5ja8fgpT@=&9H2>737MUq~*k^+GZp-UqL<&-pB=2E6cJZHrY z0ia>A$Mqt5=cr2RmYMkg`dd;==%x50)V3TeQXMHY`oc=LZ(D z`AkT_@pk1U+Oe2?R0V8o7fE*!Aa-#-*Yio?$~U9LQ;I1=j%;!r%>Y;rJ*$>UmUfBR z##k86j$^`LFb+YmoU-lqMBs0&WSE7UYsN|vrd#~%rdKJBtk7OYO_vH*W)?<}mRy+a zQM#UX)!4B1Qs9Q07(K=g^6mieoo1T&AWFqZIgxdaIg($rbyLt-t3=pYY8OPEYu1?)Ix96=0+ES#!Xc z9lK)~+5v-R#OIPByE5sv-LCv;mo`7NMa8)eP&&&9DVY>oj*4XBegEGMcN~@}J`%n} zOPqi)U?z;F;m#oEVXltT+fkmJnwWwpnq-QRK#H04V{x_HsirnA6lBrsYI6$;FO39uH=|%tS4g9| zQXBcHpBx|8KYnl^yNjDMi=}!!P4!X4GpVAM)7n^;h6^`ocf~F&@>%A@3+WXYt16Eu z7t!a;@`EGQ8cI!8$vkBSn_5-EaQP`4r$sf!W~>|O+JfG55zHxZIWdCbcbf5=iMzRz zK9EN@E0P&!cRmv8w`c!#5JgXP7pqH)H!cPEQ-@Y=JYw?N0{Q6fo`0gYxLgSrqnX;+ z@-`5pkKFobyspkw}MwKlc9#lD=u@|)k8f?X1kvA z>R60}AX}Pz6A_+{&$$sNc@6uun+BstQqWrczcKa(U~*j5oo`jC+_c5ubd^d?G0c;v zTGiv07zN7_Jb%1osav`=Y7Jw%d)%5#6ve0~-Nxp5!Ey{qc-b)3x-E@BTFZ{I;bqC% zqs$~C3mZdt>~3BHYNrRBL_BN<5`W3Q4@~4uUe<4s{hTcOZL+-I>9GuU95!RmXr{Zm z>fUqDJ@=gd{hxCug7-$&u>5nueZf0|wz@&}|JdyHZwYsNnXCoBxuUzx?S_@*a@V(qDLUp_9!~17ZG$-snA{n{m{L-m?_c ze)08<3nw9)#vjn`msYm_DZ2{&368%q!u$5kE#)dCVy_Yq`vRKn*5^{dm8yGkW&J72 zrvRh@;PfKU1u&^O<@<{V52RHx7KT(quI+D03c`AwJFh>^J|oat*=bC7Z}OkG^VFna}a<=ZnZ@X4?gWFf)4{Y0#EySQQ zQRCxX0j0dgh3YnL1vl?m7lYa_WLaI_h+dK zCB-#JY%pLkBR2UW6lt#3QIs5Bijo=b`*_>RQt14I!3*g(B0IVg?0B{~u6*Z#{L>TO z)bpR;5B}oyi*K8;kqg*Nq49jxZk!GpHAEU$f80+FKW=pZV=hNzV2C(l$Xuu48^avD zBTeReQ8ND<*fMI>0*07A9O%Pol+bb#n5k2pxm>xyGKv{&TN@J&4C;vHFdmrT#k5L& z=E(YTurbk7BZ-xL|ApWFwsoNHnK;|FMYXuvO+4E=gv7>GGXExPxN51kB!sv*@*f~)UnW5i76q^}ZOU^#e2=X&ZO3ohlK5r3q(*Zeeu*73M)MU+w!k+^w0MT$ni~mKhJ`ehRncIQ zO#+HjOYsr}!FP@BqsFMPl`IMyPu4(|78Gh8c~A)6WjHn{am}+<8tIj##xoD7mA;^Gl1MPppJ|oJx{WfSZxQzt!Z!%5~G2ApEXxB?(uIScSE7fs%SpH!e;Aj>WEek(c7 z-~e&aM(i{Y7CtaqL9ulVwXX86)E!Cjn3AXO5|1=FGKCYIIoJQv_u^Z?OE1G)0w$$z z-Yg-!B&e34TdxF@0Dn#kU;n&-KsUdrUWG~V&L$=$DA_A8sh2>q?_1CK@6-RU*T?qJ zijzyULNKXs&Iq*iKPZd*-P>F(i~MSU>@^zma!KQlzSO03_JuF}Am9>C8txKWB@=)2 ztIQf+AQ+IJ^83{<$P)6>=rdPed+A@YF-}D`u~c~FbAR%^@5vor>jRsQ`kpIuewRmD zlbg?kxXm9jhrjh3^@mLL&{W(=tF53kgS$xZffEoXOA!IQ&egh$&DSN03QFKPtO8eU zH3I-HM@4JAQO5e49JmHxqEBei<|_85<9@jnm&WJUhRQ$&P~cZOY}G0QXiELobRSn| z9`|ctOmb`Sj1N=)munmpqtzvQV7~sM-HzDdo=I)67FWfkrm`|SnF6iHA*++RI|oI@ z#mEhqOq}QvYh?)YU_B7Nhkk(ybnM*I^a^AKe+G=q%8e0{o2f3QYf4$b6f<~7M0M=E zkKy8DLF&07EL}{E&Ikg{X|EpsrE(hqy^1)M#w$$PCW6gDvxV1?74dWj7t?I3%pW%c zkiw?q_^mMl$N3b&(0XN7G0Vh!1kMyjaflCcObq7wV=a2BwRX4)1Rw|iss~W-?Xo5KRxoCgi8Jb2t zw%92)1NKmnOceFe!z$^JtHkHJ?`qJM#4+4qP37X0^WlbB^D$LVP21KsZ{q3qZQWj8 z+(991*K7}h{W_g-OJp5*hp2-ww8y zsA{1)>vVDrF|X^y$REArjJ$DoxLPXq_559kgZ`z%p{}|*&+3}f<47-VoxdfFPf_}} zm^?I5J?G!(om7Lb|L*IfuD5U>PH$5u3!gQ*aT906Ip;QE^6vT=JYn$5j1^*{%6dfseJ5 ztvb$TeSIX>Iq!VD45LB~z!Xom*KQ0?HG6{_2A#NblTs#E-}>L#I!h?U4YWfQPQ+oI z3*lHfaumFh)mKHV4B)@kz(VeQ2ZSNzm9j(4g*7G&DitG3;7oUoYgkVbUyzA9TBs9a zgYhv^BHDYwU9d-`7xnd)2WHLma-uA~*7At@ZScuY0~N7N803G70rArnZ|v5p-htSGZnc_C;(!h;wc(vy7)8QL8P; zMKsDoVVagGm7D;>kWR&{w{$)Pv0!jqmE+&=#82394C7>}=|B9#Z$Kz+Y1=j%X#$s8 zUZV818bHSa-hNk$OU+(iZ&%~&Rk%sA(zlvMc}EsdfdM9{M*p@I8mI4U2+M$ zZF8f6|XV;veIKQ@MN*YG5x^3rY}4KqlZmO1p=9I))+4) z5U&x#Eu*$;;g!SxK5@92bY0k8k(byB+qVfk9r|kx<#iWbLT}JE+0x+ir9#OeVq_1N zR|i8(a+)}$>sBprByEN&mfP`sPX6&957~X0^T?~NyZM!KABn-oBHY=uD!jjR3r3-# zRulW2QS0D+nIl^75?_EvGvGX(JC(u$eHYabxVSFfN6vX^IiG!u(bxQ988WHnT+LDZVcf7`>_xEmqhlI?!Z`YJ;>5x`4YT_5&;McK28kW1(zd3Gtd>f)1#fbB zoEPmC$$-G~Bujy>AW|7tM*vx70XB!ECZ{6JK*k&M6e1Y}IZ$_`Hs{pX%995tK?_G*3`CR-z;RUENFDL0~U3fw>MS}-MLhK zkkYk39rZtS%a7?@dj9c4*L-Qk?CCd#n&Pcr6pj{^EwpmY*M5F#!9P8J0Z63+2IXc) z^o<4vUa>#EwGp#TQslz8Ib$8VKh_V{jMe{8y(m!C;>^9~aAmI8KYSTfW`4^@Tf2b)SG<@HGo@JqtosiyD842~%w868Lwq z2s1QUzzv`oFpnx&%;KFiP;LNCVhvab{C{NwbO0Xfvqxqo?MI*pU5MW7Y0w$idozz> zt6GN;XeLE+e@J>}<%bU49_5FAg6aa7w!4jw1j&&OQe1+`R&@o2$d05DSPtFbpCUKe?9i5cquEO4zs^Fux3LDCL*)qUAj~m~ zX+ZaogQBp(t(Z@TB?w8d4s~6lBM8HQA9)6J#_|Avm}s9r7B5v<(17*mkbzkRo*@-3 zG8buac705Z69G-WH0W-BVfRjJyXRyxkZ3-THCJdHgLHUjWWL4@_Tgm)M3t68x8ZN5zB!ZERXJeL&IZjiRnjbWd-278M>Q*?KM`a0De3JZ9_D~ zCWa~~Tw5ibKw5nw!|?=cWjq-TdQH!bLYdGX!XT+Zau`sQ8Xp$&UC9va3K*cErVTn^ zJyG*;F*&#ZaBW;i@Bc3ab7%{YUyn@^m{t_$s6Uum>&4`;6MLl{YdmP#W}M(VF~e5& zjE3E!6zuoMsR{%bS@so%gq(WGpHG90$5h&-W#sa2i!Iv z-oEqGK@z^p?vS9d;KP`L+!iHI&%4Q+uIWEUy^aE?kdp!3o>r;Lp>_8QGt1&W49{HA zsxr&th$9~;W9f8ALlmU=Y|3isT_pV&=zYu1qIRUcho@@k&K&8I}LRI7LbujI(|vZ_0#+?u*F zI3wjKuGgEiEq=K#-lT2)vuL@0cyQS(dH5F>ndOC zT_9}2*Sh($2Ve6pSNUTv)Ii+c@gnT6m-u6w7@O3_cz%=awKQUn!ARS@&x`7{d0!v> zo-@N7viSzgOzL-L<`qDU~c#K#EaU2B<)7*fsobP3u zAOGg7lUHvgzSwuaWFv)mG zF(wj`z_=Al7R->h46QAt1t1OHao5=TqU|` z)baiIg*WWBvS!7@h!U-%42@|X;RWD&KtmD1P>kqx2P;xwi^adrB(6LfkjSqWc!r8_ z#VyUYK9xgaxKx?v8Ur)sZ@WIn6m-14ICOZ7s!Cw+^PZ+7A{ufEqs`Xff`9 zd5gUcMv|=-qF{;mw#J&9s%m{qp_~$ncfb_Dl#s3(=a%6@%UZ*&kvS5v5;JB=+S(07OK8D3 zi>+Z)eD0<*Fa}Dl8Sv=hexi;!FLt!~=*PfJ2&c7bC!C~}gk?}wv_k9;6VNfGGTFpv zszZRpJ4D1#3sFB;6Axe0UgbI~SBlcB(lVF7038CCS)lp_ew9X*T1)btx$^ZMu9i)t zj`a9A66ZtQ^7UGCM`ng}gg!Ch*W~#oaTU&N!f^q_#XQ8#@l;)c(b1G}JQL-H@EVvx zOtUs%95y%r?^ zV9~g8Jhwh7ViqS3b$KRjbkK^wL&B!K!(;^kC6HHk64=1HBh6$Y@^mdKKt~eSuskw5 zWYQ4HNUua>67XON@u2CbplAY-atWtfVKE~HflpMw{og-mZLhoZq2$$VW|`P}E3xCm zX30gQqo-(1t942dd)6RpHDUHuA&Y93ahV$s2(7#`a!M$4EFY061ZKzkB6TO}*~W?< zof`{URka1&wQlnUg_Z)})+$jpO)j}z-$f)y2?|t|v!x8Ayjk)&NARXLY@O3{g?Xow z^pfYq>}T@<p~Jjkl^!Znk~+IK5h(XJ|D!FVEc-MpzzljbNtH{R&_{kE7SUSz zOncB6##$C`7gK;Z zms|VbNHx8;E$q8r#oN>UP84-hM@94#HIPjZ;R~Hm!_JV61(MzXZQ5{^rf@6bL3N&^ zqqHyBcishG!Xm=qo2UDiV}t&LA*bFGsRQ3s$6MzG85-oeaRRQkWkK1EZwWE0W<7P@ z|E}3B?Wo#%teG`?&1`F5DyxrtSkJsXV}IZCayyKz3*THV@pGAA~143rMSrAn>YXrNfW z*h|qnil>^>9LoAjZ52h;9j$tG@v(Q;ib90yA9*`)#N*v<3KYo#W3pOJtNO-kRP}av z;8Q|}l7HCzdg(W%+o+iLyvRMZ)mQ3dEx^mi=I#DPm`IK2hBT;U^PQ-F(_97{%0E1F@9Fv7dkhp1@Q_Y7^cUwQy{Bu< znNqlCp3@{jYT}vTT-x}{u6v*c5sFYw;0U5?oy8QO)s{Dv!kJoOQ&G5B{rSJLz9bh? zF|+*a7#V@(uA6hRO!S=(uu0H(E&{z-JG31p5eUe}kq=neAt0PPRWiSG?(m=EraQi7f6*MeeOtfSWkZ+-G`1%` zFk1}n6brmX>xjN*#C8aaCgWy@dtG;}y0vk+icN!~aYxMScihRw3%~SRcM1^=P=aJJ z`pOwVpnMF;JmAHMv@~N8&vQke$_dq?e^8B$KhsujQ`X9d>Y zM7c4hcDuKw(V+>*rb4@*E_UhYo!odVIegw)Gcdr;gYN+9VDuJ;u*QI2MnW7lM*%7| zG{BN3I9{BAms4nvsVKmb?-+}WL1Qe2dE8??SX{XB7tbVAvqb~6oS_wL$=s-Mdi!?g z5F&Y7b`91FY``y+xCq>V|JjB?4CFSLE>4ny8spWf(wa7F5x<|U=LdE*U zpQu;?oFTxM80Zf)Vre88ZY&Q56wG;*Z*ko>1fYwfDA!<76UUDZMaU0n+i%iQGm(x+k6ZZBFuw?EhF7dn_1hvN(k_ zOTz>Lu}ec}Q5T+tsrNKD+E|=si%?Pn3unTC0%vR84|S4Ic%}bwfg3}&|2XdpGS;e* zG0NHTyatJpn*}r$u$sTEX&@#UhJs*x@BXtNFsmG!AeAY=wi+rbJ-DC2qCHvyfBe=k zK?AY}S@uR*dK45kXN+aK9L(aFH65K&TcdmkoCAf=8o;rdvf_I}hgCp)r-+l5GA!^1 zYiw^KDS)N2Yfgm@_4h)x%506k^Wy72_ zmTi7(Q3+P;I!{^}W%FUVlOrt05l5Q3l23?v2Hj#45(o}$V;7N2Lhe$cXsdwQWEU#NHI>n87}E^D9UTa7j9joqXY)nLdJRg5YLkWixR z)UV?VSMBG&@a2HR@LDhz3ngj;GYI0ebr&6G$x2T!)mMU5%gFa&LAez z2PkPRC3-F`b_m!MTeIRxLIME9!NF90pPj;nF}hl8M>*7dW|T&VCIY~);#jdcD{)^> zgZ`F|%o;XG>Sx2)*K31PLB;z$4$b`bf!{7UhlBiDS^(oLn9`hmAkJYoeJ z(Pr)<9My(~TUWV`I&2y{mx&^IPF|XaK%{eA>xStJu)Fa<@GaD$Z5eU@8@u^9ZFkpG zpzn(9hia0D`O1IzLd-62ltHO-`*f*MD=DXu@0F-J0>7^oU^!B?8MjsIsEbVM69ltF zZwOdoD`N84M5bc^ByJ_?YTeBz?O4K?h-||Xq%y8VkUaz)ecQxa`+Q`1sW#jyUFyn@R5plv9^~^Xz6{4+$+&cHQax9D8a8 z)y3Cm)u&0+aW!jm5Y+47K)CmPiUS0}9ZMa8 z2xF~*>Z?m$FhlPFAk5GxMY?unpjS&2JW|>u6eo!prAEBL8M&lR8t*Qa85VWhZn;VLSfgbV=-T-=tQ{ab=UvBLthAu+0se(-rAyr-Z z+k&nIHix4{WUq+ihu}i=u1ltGr{i;dfcqaWxE&M(RfY2IXsOa&KTwwn<{~Csl0!>fX>|Vdw}tfFdg{ zN7AJN`o*szE9?c(J`Iru!bwY@$y$?CDzp6?%hfxvK39J0TfDpKht^r)m&IHtX3(0n z5#Q)805ys`2=Xw-UF25%G<6_WXntqhX*q+(AN=V?C{tt%b`!$mR)d`KDB`}_y74fo zVU>EevbY^ar6Yq2rwa)J{HHFB!zW<5K@)hDv5U<}x(ba5VUW=|w5;S96a>*Ri!5b$ zs?6h2(j0fIYyINtB?da3<76PeJ_CI-F4;Ijr6V(dA4!9>%K-ylQf8ail ze!?*saay+~T0K$}xrVE?vDDE#O13H{J$3oacmC4>TEye?nD-^26g#R@7sG52(voYk8cMHNH9~n5^tx9~Hp9&_kvu8?CGe ztrVF^D_GCl8fh8Y9yiWwP73qyBZ>wk6)cm!4|afU1>ZXEQve)PqPCX+^qKxrWS zMe&v}+1v>QVLgudM=oOKaYc-xq`b4nLu7j==HidzSh2k2%KCVr!}{r3Wt0H(hmCKx zv66SB;oO6;P!6`$E&iEuW9g_m^`Ngl)4fuK;$(E(yBVL)Kfu~Loj@bWs7+`h{S46KT(H>dr@O?uvFfLKrY&O6O%h$qE+*!lh$<1H`Q$K({6`N<;m-|lkr?tJ|slD5G9Sc7g z+#KLZT;KkIxyAEVe__gpt9Vq%N=fTIxEem}-WFw-;4a1dCXdJ^t7^saH;_u7 zh#68!f#k0a*liApD-lNFW4sw>`DB2Nz zc>?0iCaUo{pRrycnbE);6+8peDa&>i5T+ohF$$m*XoJ;O?3Tn;JT`GiAdO*iA_K|+ zvXDr^V)G;9;|2L7BAa0}2G;xE=c+gYdXr9o9r1hT&>I0FEn{8ut&8JTj^XYC%4tbE z`>ZsCB36TN5|4M7O#v0{DHTSvFPlxMDgThyExF^#_bJJ?ieu|=3vS~()bh<>#>ibveS z5&D?(lRN2nr&sr-@|2Et+VWmqCDdg=D>3{aempGZfx2%HD?G(or^^4&HxhjTd zn5AJSx;OkbC$;gYPj>zL!o}w@gRnNP^BMJNk55-b{~H~)gpWv&jt+v1G<1YmSTS)3 z_#<;^oye&IA&jk=OMqCzj5XK!GDibxxL9P~eeD{txqc6zN@sniv4k4dD9?QCDP%>Hp z*wvpXl4hMVp-xW?!Rs;42pA_npGrCGq?5K#V91eLwE!&aR@QD&* z?EBrWk7a*iRuIV{eq`4H`U#0}QdW_2pqPTx7UzXJ9s=V2_{_(h8Uu?l!Zqd&0k=-+q0a*UC9!<#Oa zcvGXVk+(bwpmMnjU&-Y^M+xNXl{eUY?ds3`>M!5#U%A1yGn8ry;FweGKDs`lICVOn5i(J+2!z0*>VgGj%qsu}RdNuDpNv&0c0zifQp!?lKxAs^HKjTTk+4aZNmL{H zrS6U{Xf8-xMr1%phtrwWe|Cr+Si1WR@63J zOlDgS(<(n2sj|Kfvceov`O5#crSyt3`~#fiBtO0p`r=yQ>UC$oR)BG645=I6V#k78XZExvmmw72B52Fd`3`A`+=2 z1?0EOrdhF7X{&zx&ER$AUPNB`&L+tRdP%i+diVJs_tijeQ{J06!Ppz02rFt<7f9#) zYO0Q;19PL_@rQeSy(eS{0%ITam~icCLHF;29u-pAt6@z08KUc$U=$TEI|Jq<3Zp_f zjwS-iLQBB1&~w@qRP0)5VX0$H6?9g6;cxy~V@g#CDe&S!S$34?XZJVLVIx>~PkLG1 z&PxM7MgRa;3knjTrwS?W&PKiPb&aUzqtUZ$$0 zNQ%jgvMw`RXe!kK>t}ok4A+J_=0``V<2Hu|+9r>P%d1btc4YRa)A!|Xki@3@+2KRr zpDM?adEyP>l0X%NY2^YKF+@bG08qFE{wQwCptMrWo#vt(u^QPXBOE7*hM8{1ZDvY4 z3DT{J%M6@Tj$tP1#LcbByZ#LkoY$5R5TmAt12UX=Mp39Fob;piH>Wzxpmmr21Dg8Q zucFT+FrjP>0q?c-;(y5m_;?W03+yMviMlTfLMTrX>1>F zBM}mFpuj1kxdYQ&UJp1|+FEw5Tv|^GmN^l#Z z!Ik9b3O$Ka26jO@&}3wHh=Y@0A;lp?r28X4c6nIJxgiZ~(YW=SKjC94p0&#QI{m5m7Q~MoBc@RZ$f4)B2Nf1W>U*;W=eD z!lLsQ=RdqXph8j*X;jDn-7r)T2g4|wq(0{^cFV?()R@bX%4Q&MD|`%+28%|-vFxQZ z(|}>2tzyKT5zxe~G)ET;o$FL?@A^#eSR9^KFaGT9%XU8Lg*`iG?dzNktc*duvCKhD zyj-{ugvkss*0bbeOer=!Xfv|u%i#7VNq(joptLh#DwfSy*cffaG1g7z;D>@5VSgL6 zozVmWyAW}Vgmp@}-}u8fSRtE_;WBEEX&0C(n6!O?`)PDqJf63sqXVRo)2lj#qDq?k z89nEb%L1VfeKcrqr0BCOzXz0>~i##hyLgyntOZXPufpZ zY!oq;SvYKf@J^~8JL<-q$_Jb?Kj9o*jro#GHYaKFIA&Q;NJZy)Bz@y4I|pQ|SQrNs z{-^?fIM`gfF$_n|^htPUqLtj8Jn71Rc>%k?SrMV`seo?3bWhIkO2A{|)M;0e&_-qm=bTOvbM>x1nE1*>%_ZVB@CM%JAn(@HZuZ;*_e{_Gux#`k{Q?8&c8l>6W)akY5rnN_bswJS(F zXTn1tn))E0ycy!n3!#5t$a&S>XdT|x$~?uU2%SlElUzKa_U_w#4j$(B#qJGDFv6az z7UBb19&-4-8lD%|hhHHV{xhMP*$UXu+37ufPm_Y^hu%KQ4ulVK-`v=)XIGogflQe? z(A{+NH=^G z1%N`$_qgOj6y7#yu1pU6=x9#%Uu3c!5BX)X=%C_UBB(E|d1qhV!KC2%7zjF{-`IBV#KN7+kqww7IdqwR$j>(p zr;moLgGkC6hw~Eyc1lCXn@dqnR$@%%*pk%&J_F6|AJL(dbXo&WxkRp&zat>Ney&UE z*IE@#WB7V(&Pe5`2T<&2{K;B#H&UJ;a}qJ!`IgEVIW_wm|KtswDrqT4no;BN%zYrY zElQCC013VB*&?{y`eDz%r}@Rn+`c!wD}pRVrsBArfy@B>F$9@mSG5gdhSNY3&5j_# ze6!;FP9JmEAd7Zhd_js@6Qbx$F*FwK3=5kH%{nj#_VT0H`%6 zTa61{R?$gYS{hQPt6y9mjK{=JenrjSx%{M7pQB>>ErGi7>+c0kd;|~PftECGOH(gL z0zPY+y7sL9x*g*%ESr~TAmeII<~TDcfON4#!7YWfL%nPx8N7@68DQF(GUei{05_zs z$|~J>ToF21rQU$OH=C1I1?~$egcbQh&FdEx(Ct#>BW+;i>P;2@fQqH)`wKx}edR~T zsLDo1^)-+*fgb7PVy!y@LwTG(Zi7LR14#$aNpQfoP~u%lC9Y8EM?8?fQ5q!Pr1G6{ z53i(Ju*6}2{^-ZB`@jJ&GYc7F@;RZHU7#L0AL%up6L8KygDTBDv7#8|{^Eb8T-p-j zeo0;Vtv_m9Rst=*?d(Xpix(g~k(&!{Br{-#KOH)#m!`+GqRL?lEw-bfKcpc8YEdSS z#%eIZ6p#+$SB+)!?h#I!pE(_|kgONK!3dB@8b_zdrRA5Pb`li75?Q;r1*!{9-<99CczPoz7ttpVU#8F zK}|vsz%neBzY?*$DEJ^;J6Rb&GK?^EN%DU~$)={1LO@i5H)lzSSSR++zA z8~!S->s48T2Vb2f_$rFod*A!L_xYWTZ>9p_T`lXr|9bQ4ieCS6Gi&iG{C4592VYsx z>$M1PR{_OWV|Z}ZUI|QoA0RM&HH0_&ncsRnK#|2a?xzYZ%svh_ub>iqF_9zQ9etU6 z^v?*yd+DXu`iI)_%g$u)g*(-2z59J$6Bkvy{g=ORvtRns)?0t&phLaUVMw;Y4h}q; zuT35cgCnzp8_Cr@QroXWDwskq>a-2}nr?nd9WiBH=zx*n*yVaZ#DVH;7?OTftvfyt z!bBlfc*IBIwZs9+Vs=`;>Mhjbn4kdME@vZ@@DB)!BL)eGh?Q0wvz1CztGaoffB5kO zjuvN_qlqCZ2zjB-rZ_%d9vYKRdpG-SN^Q*5-GMmaeK+6bxw#NsVDFGzMU;jTY`lM}=abPj{ z4P$L{F^H4-NS)nA6jTrP0gV`{N|M0UN}2Yb&9W}M`!70{1} z;%s3RDtPOBhc3tAesAc51z90vDUeujor6(ihu{jF{vCc1>aYkehElOv*`OZbBgMw( zT$@h_hX53t(pU}!wT-jflpQcJ#rE>83n|~o*-s@M#2Gv4a z^^IC;mz`mxe2&_Svv5Ah!z9%t9nQG=hMc4hl&8_tI=6^t=bCqsv*P8Y*@=bSLmiiP zZyT%56^$-CdeC=r)iwme)U>IGtxDhNKp4hU>pB!m+NsUiKoi_(cTdnBu7&xe`eK|p zyZ$^?o!*&!dg{f`y&e57Hl|9~p(&VVwxA>QBBjJXPe87`%zDj_1k7CqPEf0aEh$}W zFpxx_$O8c-e;a6`wylR2Uu$_5uQvDp&HC!4(_rL@FS$pxS7yGqea z16h`|U|LfUix@BGl^oFG#UuYG`qAdIjmnL_G9WJ68kFSJH@-kET>1B6nZ9Tf$mES0 zk1@rWC+rjW5hxa8OqLrQBW8mOz6gp}%!PzRchC9~bz8pK<&>suYx0G!)qw%ya1zXe z6J1LIP?3*H!R!G>njiZ`wH#JyWhe zGclja3G2_G?3(5xzGctxIdxHe{XcD)wwLX)d(cjdod74Cum%4ZVOb7fg$81WY6GYP z<%-=0mzwZZCKP$N(tUa^XnTxB0bphi0)fzyt`LxlgVm9CSQtryVgw;W{?5N}vf@q~ zIU}6K-mWJr%^F%TX%i>h7@U=aWO_x`_)P(_0rlQ3xQ?22nfJ)U9HsMG{sXk^fuaAVoL7{wtUnQeGpRNgXrPM&JvvkNrYT3q$@n|NQwd}c*p2H)pc6_lckQTSGP#jCeF;bx$ zm~V~p8Wss2K%amB>0=dw8&rZ;jpk`2-!ZlD{m*ZS*bYh`!&F5H$7Z0o zm~2cHcLlL@U|vnyHz+|jHTzILt>7t)ra)dYDY=x_rBlFzZfSl>$`=KCo~4Qxm0Y=; zqd9ud5BuX#?GV|EANWdA=iC}c_Fkm3i9R~T#5PM~QsUQO?vgE-LGW5-CvgXL9;U#y?x?Bm z?5!choy$YriPr|}0oBd=Pt~979rKs+FuOVYR50CMnxYkFVh)qN^wcwN(CT2*+z=f+ z=DRv<9|Xe7pLx&f89)2TUOzk=+@0?&ABj>n> z)!`Z642hecoVx6Ron^O{(~7&R8%5pt*g3($t^|J9CFbO!>8AEcl>(8-4y1d$o3ZX^ z#*YV|_3sboZv{5Z%+sh<8M8_g?U`{0x&OY%aMa`7k4*)*nH)AJt>pGYrw1mfe^_3p$| zE1!Y(<-c`HL<(S4;haf(s51o=bZ_9VRiK1r?!%|HDrx8(8=`gKiG0ujGRYS1j4&{u z;$X9a7j#)iD0)G2vvP%EW4mkx3e+%@?NwreH8LknmC8||FK1L!-m2B{>!Vr(! zG%b$IWf9siBlWe`m7-@5pyKw34YdlvivsvFh2(H2GR87}A0!fAM-Jv3mt_VxD*4OY zuDtsfwm@h)&q%pOgJov73e5~M9j?qwyz0@1`4k4&%;b}uCgdSDDBNYxlAa>bu1C-i zI*lGgBgTg`z*(VR%C8L6P*J;{;lrptx9(t5IUlkE|B4(#aId~#k0L45PRM;5xBhm; znQj6* zHgTLjWHOWtLSK%Ngxr|NRX|JRLu*!`8n$|tB47jz6U{1)geAC|s1|3P0s__EQn@#9 z(Vt=F{@r3@C=guJkZg$MTH&vLU0}8EO38^PZ75w)$P!1MhX&4-GavekX>yptSAbuM zYXk+mV8MSQ_?4P!89j?f35=4K8;OWCcdnB}Tt|d;D+kmw;F~$>dLjE{!l=F(-Z&3i4QpfiPwt_*Tg|n^Ll{7Y%xd z>3wghj6bPC-ulIR-+!%n78!=+GRSAT4u3nt-vZ8#+nhl-$+~A9$U8(EAs(#`YWO&( zy#J885{`2YBC1WUgdwlwp)hB$t@q{lRlqb-qMVDTrA(qk>$zeJT=;8=Yh_<$-PXX; zoV9qcIrB(VG8I2GFFgKvN^@cJE6a9{(Gd!SS>9W1YEZfKgmLB?ZlqJFEI7N%a zzy=BHDC-`Iq)`o@)fbej%BOE4`%-W*Bs)Gjjgi1<7zql-VT)5J&+!y~fRy!;b-@1A z2?ltSzDecsUl|h&4DgC1%g?=daFk^Ext9uMUHGgTK~5K511-8r_=5SiS#9eoeXZIO5ft2%m1VWY<3)w|W^ulioFVmQFB-4eB+BsjV%A z&?#<_V6bvZ)$>h)`dy{svkv&IVLP|xM|oVE8dhp}xvl!ti^1<>Z@wBUH&*2|_RfVW zhi>4rNv^I~6tnrfwFt)S-{jkhX0-pSA zSib#@e*F8 zhAa}I2?AJSv?e6|Bw?pg1UdRZWf1ip-#{QDbxu`5#b!wq6a$^-1m#pKY4jw5O`IF@ zMlGInhyazU-SJ=X&qa{@Ak^zLjMZd_cM=uTyU_?wDxylLVPwi9iP(TcM7+i1rNx9w z(n$V~C72@X%SEA~Hr%SVvAL2hDU!OF2#BAb}WJ zNC3tEc>35ix(7I*3zT~)5!oDs2V|E!X~nOEy2hh_^Za#PauZ`~Saqnga-@>Iw@tR7 zWnfpvid)AzQYFAytgj0eM(Jc%6IX>KuJU9CpJNu;poE`c$Z5*k=oWEIFT5=LQ-~7PR+8t2{V+Od(lOim#74~M86eld5H&Wc%DwK z=ngq;lOqZULpti-7_A8nHRO2gEeY3M5{ znIq}QZ9r&JX$C4HPm$>X1q*st%2N=7Ac-P1LNb z7U1R_%i351`ove0PKrqQ5b7y^h+!IOOvop~8`6t4{=RMh7GcR+VFZrpD4KIiXnj(l zWUy3{>+Z3UZsK$rv9DyXkVG;X#Zhc$asrolG(wRuesB0JGY*;fs2jI*PL@4&0llh@0& zRyO+dhD=|^hxKMON}{O_5@wx|4vj>}FAN}3ni92I?%nrPVbV_6y`c&RYabbU1Foyj zO0#4h#3A=H2r8H7a9;;_P3UvnmIDEFp~{TlD`r?U&lRB~Z3R8u5#A#Lv7VS$5F*it z-~9a_;F1^^kAvtn-5namzXetUCbXyyLj>WBL7q=30wJf{!Xzy+?&0`Y-Y>AYvHv3z zjhV<(xf>l4Q!TeZg2tA%AfJ+Z{aeSNC{>!3FrT)oy=HAK4nH~Y^YYWR2gBb}oWnBb zEu@{8;kNv_CKcJK0Z~5?sptS7ST)IYRZzmQj6w>lOe@S26$?598^KoArm|jGQ*AV} z6wtTE5(U^PatU@b!{7sNDO}!*e-{69c!xTK${Cfy z@I&RNciYtu22aH8wpiIs}M0Urzvz}_j&!et8` z8{F3**lQh}9uAeR#}w(`;a1t`p~*}R9mh&Hm+ zT(%EHQ{ZX4yd$a7JK}dmU$}3}_~Lolr?2>D!>Usb7lnB>*A=`-m{(OicQ9Q{wS)xn z4GuIed5h<%>jPdiN`hLv3khvKnzz53yeJURRbYsr!H6WBqqWt!B5ao#SR$3k^mhns(}bC`{iaHA z2A~k|NmGM(KE2UU5e9bx(hQ6fI3CN;inf1ns^!c1z4yU1*oEU5?!R`9gr^RX-lqfg z`O5j5#_gNF{x3)8!3o-e-H#>5Ok(Gag_%iv#4_o+2{6VAz!RY*@$Tc}1i_DIpQEr9 ztz8`@>}@P)E_%e{TJjMS31c-Oai>ZIe|Rdw9Ae!NA%6>}46unzFM!2vK|<_HyrUoS zSmDlB1Oxm`<@`>P6JPkdzr6_C{M!>OXU+z0t^FO@il$UB8dlzH<3D#F4tAjlp@sg&X*Nnp{p=;FO>f`h-0%+y^ ztycbs*BFT*leX*tAdi7v`fTuIuAw-TUaLM9uW> zo=4rN-M{L!YVZHog&lrO4<-2!3%Iy6S~zJ6G`D6YVlnGbNPE6L8E@pZZ`y=As4>s$ZIm3pnqkv(Z=pQf=Vyzt{Pslxxiz4MQetE%GoeZynB{EEBd zu$h($Gvk{&1*CwLkQmeVUfiE`%R#-9=DiA(|Nfkj~q_EsJ6(+Tb5VD0RUa zq9Hn{^gXB+-d|H04qzIn5=)9wCf*Z;iTzIpH6d(S=h-gECg z=iGD8J5lLnRXV}el-bEz&3<+bIU^Tg+mx6_FOaBJuHmp~tgqFF807)*`66L4H_`{s zTZUPKdr6Dl4~LoK{9t~>6H7bjHm`e5pZb%DYFy1FaW%$oaZi4KC`UNvn~6C#jtWKU z_Q4#Q0VNs5-&U{Lk9#}j3!{!8qAg?|ki$HMjoE(KJw#B1BS*e^dh>EA$864Y7GMT} zvO{i)jbURBCbA6ADqh+e4#3Ff*;)5(e`M8K?J1!N@{y= zBm4<|MBJ_M$-k*W+6KnhB(5bkl`yhf9AnXhdFFq!%z}ujK3uE~TA=%VGyO>V+KBpY*3? ziu7|+B}P|MsX31REF6UkiJ~QG1SIR7Ucxsv^OfF`k3kfz$g;&Q4PpHR_BTsf;CB= zvs_<(#i99g37K$0!Q_*$Q6~6OG1#Co{9L4aa6|8;JE^nKfC;L-H_$%;EM4CP9TZ*U zZ~o;`Kj+2d@>w3P)W`HNxCoSzUf!CEfExkNPkWy`L`34sLW$o%N+tCM)+Xxv$fY<9 z7hW>XZB@*(m$=nlq|TSnY+{x}x+p(ID_D1JMZ7wha$2HFO-rI6RYCd}psPQkT!3(F zDNMx@N^#j?=%ZdXQ6X4&Ojgm>Cdu<&d?_B}PJ2nsVGnua#i$|Z#wuhe%b#x1M4P=X+;ML#YQ|;2)1%o0@Gx7;6PzR66WfMj5kRI zv$9aoehp)0mE1bASR;WK6JXsCTpY$eM4Uo>OOd@#{ z=X@{@><4KRKg55OjCw5pz$6JabTO!c7e5T>^#!aUim2jcN4ha66x<`vTvR{AVb>fD z!v9gkXpZ3EN~NG}Xb5^J7eI>Xu&;-* z(KPt^oK{5yR-Q%3yhYlRU>-%Q9AlA?=*;#vXS#m$p;kKyo&?{BZ%=tQ9!6b}qL6-Q ze$b7*QPdo?3|sb;tf5R-X_N{JreK&&Foq_!?HZJ*JGcp8Diu=zNt+0ILV;cRNtVP< z(G-$G2ewDeA6{$5aHWm-O{Wj!5@DM-qgFWfWL6Nx;`Irg#Rnt-XHDi70T^J@P*4B71rrfAU$a5p&sIWZE;)I4Wl;e=wzC zoB~f@MN^$^S^D8M<)cJ^XQKm%(up?Q98ne}u&&U5w%I59i{@T*(P|4Qqj~dQG7zg; zjH0GNq&-fT8!D+up0#-*!UBZv(m)t|k4; zf8ceABvv`EPqihi0&Cs)Da0#;lyQzgP%Ru4RmU7Zt~e^yn4<|b=D*i)P?2cx+V?t$ zl?sNiM}8E869t+)mMRU$94(qvvD5tZ@D8azs42UbI>Uq(a_GP&i8|P;&RwiO!5{7py*B)>2hL26zhpg!rjp&YE;+t3 z-&v*0q6N$~=0Sx`25Ws1Zf;p?OnOi3T`{J9WO$n-9<&m__!7jm&8QS*Bt?N zzvD@qO*jlkJ4CD2miFiR0Rj1lhxG{&H#_x$pLjnX7 zpFIOpfxGnGXaCw`Vp3c!i42T@NHUrq(HpQ}2CmAcs|r>xfkT-WNM4~^t}-!GCHAt2 zbV;QP)$pUhHML66{Mt$ToN}y!HAhg{3x$*!J`rC4q-3GQHr}E$Z^~ybH*v{fwzEWX znxq+Wwwr94=+u<-LxUy!+dr{Uc;sdsVPh~&sFtL?+?i}N8G&fKVsL9^(JbB{RId)_`YlkhC> zO4GMKA`qhAvj}xUmaHg3Q-R;)y(mOB3AZlsYrE|j!Z0?FMls3Hot$qyzoZdR7zXCt#OFT1IBUEL= z87h)8UUQ8Xia*=f3qz>GYbMWxIg_Oxoi-16&?x{|wgN)3e7?5iY@0wu?WBXQ=)_nE#Aazr zQ`y@i|G6*$wCugxv2#LdOC1XrYKj>u&7b~hhv%U7L%Sr_w~~ z`=HzOyDdyC!P@|NX4{W17Kq)SeE#_S+noElO~02WOFaDBp0P!fVVdw%QnXySA`9!* zob_57w9(mp-vy!#SS34P+V5xG_)xdlD;wq<@j5YVL;rg(LHUabQJQGZ1*znS&m=T| ze!cyj7d;6F^9KpU3MW2(-uwv{6Pry6d;XXLT}+;Z(qzomLh0s>Z?&0eZb><}R$_IS zrXw5XAgnZ^)g9?Wkp86C=B`^hA7}Odtc0DZPJ92v?UtB2;xn{6Ud_HeWu>2?ncaV8 z8+7sE6m(~5-2kmSYbkEY;vvqN($=VX%ZxxH;Aa(@zk9SZzx@tL=ZhuXHy?PYonDx= zq@DJ=rQNK%fAPcMwA7asxu=|pYuWR>zcZaTcd{pLT{>$&HzdT~4HqxN)X{>zETcWc zbkD`@CiAmVp2aQsch4X6$?P;#vYRvgz2jr;oC^+sImG#PX5BQL4PQFjK{NwU9biTN z{b32Ho?_C*tLc`STiVK|3ltGKlTVB(jnTrPk|+#87LDFeFULv=a7f<_-yvrF$KkPB zrHID7UMZ}s5LJgWMIU<*(1Y&gq{1;g-0pMY)Zwj#CRvKD17#X?85&cUMj>3)))user_io( + .clk_sys (clock_24 ), + .conf_str (CONF_STR ), + .SPI_CLK (SPI_SCK ), + .SPI_SS_IO (CONF_DATA0 ), + .SPI_MISO (SPI_DO ), + .SPI_MOSI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable (scandoublerD ), + .ypbpr (ypbpr ), + .key_strobe (key_strobe ), + .key_pressed (key_pressed ), + .key_code (key_code ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) + ); + +dac #(.C_bits(16))dac( + .clk_i(clock_24), + .res_n_i(1), + .dac_i({audio,4'b0}), + .dac_o(AUDIO_L) + ); + +wire m_up1 = btn_up | joystick_0[3]; +wire m_down1 = btn_down | joystick_0[2]; +wire m_left1 = btn_left | joystick_0[1]; +wire m_right1 = btn_right | joystick_0[0]; +wire m_fire1 = btn_fire1 | joystick_0[4]; + +wire m_up2 = btn_up | joystick_1[3]; +wire m_down2 = btn_down | joystick_1[2]; +wire m_left2 = btn_left | joystick_1[1]; +wire m_right2 = btn_right | joystick_1[0]; +wire m_fire2 = btn_fire1 | joystick_1[4]; + + +reg btn_one_player = 0; +reg btn_two_players = 0; +reg btn_left = 0; +reg btn_right = 0; +reg btn_down = 0; +reg btn_up = 0; +reg btn_fire1 = 0; +//reg btn_fire2 = 0; +//reg btn_fire3 = 0; +reg btn_coin = 0; + +always @(posedge clock_24) begin + reg old_state; + old_state <= key_strobe; + if(old_state != key_strobe) begin + case(key_code) + 'h75: btn_up <= key_pressed; // up + 'h72: btn_down <= key_pressed; // down + 'h6B: btn_left <= key_pressed; // left + 'h74: btn_right <= key_pressed; // right + 'h76: btn_coin <= key_pressed; // ESC + 'h05: btn_one_player <= key_pressed; // F1 + 'h06: btn_two_players <= key_pressed; // F2 + // 'h14: btn_fire3 <= key_pressed; // ctrl + // 'h11: btn_fire2 <= key_pressed; // alt + 'h29: btn_fire1 <= key_pressed; // Space + endcase + end +end + +endmodule diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T65/T65.vhd b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T65/T65.vhd new file mode 100644 index 00000000..09253fe0 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T65/T65.vhd @@ -0,0 +1,564 @@ +-- **** +-- T65(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 more merging +-- Ver 300 Bugfixes by ehenciak added, started tidyup *bust* +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- 65xx compatible microprocessor core +-- +-- Version : 0246 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t65/ +-- +-- Limitations : +-- +-- 65C02 and 65C816 modes are incomplete +-- Undocumented instructions are not supported +-- Some interface signals behaves incorrect +-- +-- File history : +-- +-- 0246 : First release +-- + +library IEEE; + use IEEE.std_logic_1164.all; + use IEEE.numeric_std.all; + use work.T65_Pack.all; + +-- ehenciak 2-23-2005 : Added the enable signal so that one doesn't have to use +-- the ready signal to limit the CPU. +entity T65 is + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816 + Res_n : in std_logic; + Enable : in std_logic; + Clk : in std_logic; + Rdy : in std_logic; + Abort_n : in std_logic; + IRQ_n : in std_logic; + NMI_n : in std_logic; + SO_n : in std_logic; + R_W_n : out std_logic; + Sync : out std_logic; + EF : out std_logic; + MF : out std_logic; + XF : out std_logic; + ML_n : out std_logic; + VP_n : out std_logic; + VDA : out std_logic; + VPA : out std_logic; + A : out std_logic_vector(23 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T65; + +architecture rtl of T65 is + + -- Registers + signal ABC, X, Y, D : std_logic_vector(15 downto 0); + signal P, AD, DL : std_logic_vector(7 downto 0) := x"00"; + signal BAH : std_logic_vector(7 downto 0); + signal BAL : std_logic_vector(8 downto 0); + signal PBR : std_logic_vector(7 downto 0); + signal DBR : std_logic_vector(7 downto 0); + signal PC : unsigned(15 downto 0); + signal S : unsigned(15 downto 0); + signal EF_i : std_logic; + signal MF_i : std_logic; + signal XF_i : std_logic; + + signal IR : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + + signal Mode_r : std_logic_vector(1 downto 0); + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Write_Data_r : std_logic_vector(2 downto 0); + signal Set_Addr_To_r : std_logic_vector(1 downto 0); + signal PCAdder : unsigned(8 downto 0); + + signal RstCycle : std_logic; + signal IRQCycle : std_logic; + signal NMICycle : std_logic; + + signal B_o : std_logic; + signal SO_n_o : std_logic; + signal IRQ_n_o : std_logic; + signal NMI_n_o : std_logic; + signal NMIAct : std_logic; + + signal Break : std_logic; + + -- ALU signals + signal BusA : std_logic_vector(7 downto 0); + signal BusA_r : std_logic_vector(7 downto 0); + signal BusB : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal P_Out : std_logic_vector(7 downto 0); + + -- Micro code outputs + signal LCycle : std_logic_vector(2 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(2 downto 0); + signal Set_Addr_To : std_logic_vector(1 downto 0); + signal Write_Data : std_logic_vector(2 downto 0); + signal Jump : std_logic_vector(1 downto 0); + signal BAAdd : std_logic_vector(1 downto 0); + signal BreakAtNA : std_logic; + signal ADAdd : std_logic; + signal AddY : std_logic; + signal PCAdd : std_logic; + signal Inc_S : std_logic; + signal Dec_S : std_logic; + signal LDA : std_logic; + signal LDP : std_logic; + signal LDX : std_logic; + signal LDY : std_logic; + signal LDS : std_logic; + signal LDDI : std_logic; + signal LDALU : std_logic; + signal LDAD : std_logic; + signal LDBAL : std_logic; + signal LDBAH : std_logic; + signal SaveP : std_logic; + signal Write : std_logic; + + signal really_rdy : std_logic; + signal R_W_n_i : std_logic; + +begin + -- ehenciak : gate Rdy with read/write to make an "OK, it's + -- really OK to stop the processor now if Rdy is + -- deasserted" signal + really_rdy <= Rdy or not(R_W_n_i); + + -- ehenciak : Drive R_W_n_i off chip. + R_W_n <= R_W_n_i; + + Sync <= '1' when MCycle = "000" else '0'; + EF <= EF_i; + MF <= MF_i; + XF <= XF_i; + ML_n <= '0' when IR(7 downto 6) /= "10" and IR(2 downto 1) = "11" and MCycle(2 downto 1) /= "00" else '1'; + VP_n <= '0' when IRQCycle = '1' and (MCycle = "101" or MCycle = "110") else '1'; + VDA <= '1' when Set_Addr_To_r /= "00" else '0'; -- Incorrect !!!!!!!!!!!! + VPA <= '1' when Jump(1) = '0' else '0'; -- Incorrect !!!!!!!!!!!! + + mcode : T65_MCode + port map( + Mode => Mode_r, + IR => IR, + MCycle => MCycle, + P => P, + LCycle => LCycle, + ALU_Op => ALU_Op, + Set_BusA_To => Set_BusA_To, + Set_Addr_To => Set_Addr_To, + Write_Data => Write_Data, + Jump => Jump, + BAAdd => BAAdd, + BreakAtNA => BreakAtNA, + ADAdd => ADAdd, + AddY => AddY, + PCAdd => PCAdd, + Inc_S => Inc_S, + Dec_S => Dec_S, + LDA => LDA, + LDP => LDP, + LDX => LDX, + LDY => LDY, + LDS => LDS, + LDDI => LDDI, + LDALU => LDALU, + LDAD => LDAD, + LDBAL => LDBAL, + LDBAH => LDBAH, + SaveP => SaveP, + Write => Write + ); + + alu : T65_ALU + port map( + Mode => Mode_r, + Op => ALU_Op_r, + BusA => BusA_r, + BusB => BusB, + P_In => P, + P_Out => P_Out, + Q => ALU_Q + ); + + process (Res_n, Clk) + begin + if Res_n = '0' then + PC <= (others => '0'); -- Program Counter + IR <= "00000000"; + S <= (others => '0'); -- Dummy !!!!!!!!!!!!!!!!!!!!! + D <= (others => '0'); + PBR <= (others => '0'); + DBR <= (others => '0'); + + Mode_r <= (others => '0'); + ALU_Op_r <= "1100"; + Write_Data_r <= "000"; + Set_Addr_To_r <= "00"; + + R_W_n_i <= '1'; + EF_i <= '1'; + MF_i <= '1'; + XF_i <= '1'; + + elsif Clk'event and Clk = '1' then + if (Enable = '1') then + if (really_rdy = '1') then + R_W_n_i <= not Write or RstCycle; + + D <= (others => '1'); -- Dummy + PBR <= (others => '1'); -- Dummy + DBR <= (others => '1'); -- Dummy + EF_i <= '0'; -- Dummy + MF_i <= '0'; -- Dummy + XF_i <= '0'; -- Dummy + + if MCycle = "000" then + Mode_r <= Mode; + + if IRQCycle = '0' and NMICycle = '0' then + PC <= PC + 1; + end if; + + if IRQCycle = '1' or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DI; + end if; + end if; + + ALU_Op_r <= ALU_Op; + Write_Data_r <= Write_Data; + if Break = '1' then + Set_Addr_To_r <= "00"; + else + Set_Addr_To_r <= Set_Addr_To; + end if; + + if Inc_S = '1' then + S <= S + 1; + end if; + if Dec_S = '1' and RstCycle = '0' then + S <= S - 1; + end if; + if LDS = '1' then + S(7 downto 0) <= unsigned(ALU_Q); + end if; + + if IR = "00000000" and MCycle = "001" and IRQCycle = '0' and NMICycle = '0' then + PC <= PC + 1; + end if; + -- + -- jump control logic + -- + case Jump is + when "01" => + PC <= PC + 1; + + when "10" => + PC <= unsigned(DI & DL); + + when "11" => + if PCAdder(8) = '1' then + if DL(7) = '0' then + PC(15 downto 8) <= PC(15 downto 8) + 1; + else + PC(15 downto 8) <= PC(15 downto 8) - 1; + end if; + end if; + PC(7 downto 0) <= PCAdder(7 downto 0); + + when others => null; + end case; + end if; + end if; + end if; + end process; + + PCAdder <= resize(PC(7 downto 0),9) + resize(unsigned(DL(7) & DL),9) when PCAdd = '1' + else "0" & PC(7 downto 0); + + process (Clk) + begin + if Clk'event and Clk = '1' then + if (Enable = '1') then + if (really_rdy = '1') then + if MCycle = "000" then + if LDA = '1' then + ABC(7 downto 0) <= ALU_Q; + end if; + if LDX = '1' then + X(7 downto 0) <= ALU_Q; + end if; + if LDY = '1' then + Y(7 downto 0) <= ALU_Q; + end if; + if (LDA or LDX or LDY) = '1' then + P <= P_Out; + end if; + end if; + if SaveP = '1' then + P <= P_Out; + end if; + if LDP = '1' then + P <= ALU_Q; + end if; + if IR(4 downto 0) = "11000" then + case IR(7 downto 5) is + when "000" => + P(Flag_C) <= '0'; + when "001" => + P(Flag_C) <= '1'; + when "010" => + P(Flag_I) <= '0'; + when "011" => + P(Flag_I) <= '1'; + when "101" => + P(Flag_V) <= '0'; + when "110" => + P(Flag_D) <= '0'; + when "111" => + P(Flag_D) <= '1'; + when others => + end case; + end if; + + --if IR = "00000000" and MCycle = "011" and RstCycle = '0' and NMICycle = '0' and IRQCycle = '0' then + -- P(Flag_B) <= '1'; + --end if; + --if IR = "00000000" and MCycle = "100" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1') then + -- P(Flag_I) <= '1'; + -- P(Flag_B) <= B_o; + --end if; + + -- B=1 always on the 6502 + P(Flag_B) <= '1'; + if IR = "00000000" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1') then + if MCycle = "011" then + -- B=0 in *copy* of P pushed onto the stack + P(Flag_B) <= '0'; + elsif MCycle = "100" then + P(Flag_I) <= '1'; + end if; + end if; + + if SO_n_o = '1' and SO_n = '0' then + P(Flag_V) <= '1'; + end if; + if RstCycle = '1' and Mode_r /= "00" then + P(Flag_1) <= '1'; + P(Flag_D) <= '0'; + P(Flag_I) <= '1'; + end if; + P(Flag_1) <= '1'; + + B_o <= P(Flag_B); + SO_n_o <= SO_n; + IRQ_n_o <= IRQ_n; + NMI_n_o <= NMI_n; + end if; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + + process (Res_n, Clk) + begin + if Res_n = '0' then + BusA_r <= (others => '0'); + BusB <= (others => '0'); + AD <= (others => '0'); + BAL <= (others => '0'); + BAH <= (others => '0'); + DL <= (others => '0'); + elsif Clk'event and Clk = '1' then + if (Enable = '1') then + if (Rdy = '1') then + BusA_r <= BusA; + BusB <= DI; + + case BAAdd is + when "01" => + -- BA Inc + AD <= std_logic_vector(unsigned(AD) + 1); + BAL <= std_logic_vector(unsigned(BAL) + 1); + when "10" => + -- BA Add + BAL <= std_logic_vector(resize(unsigned(BAL(7 downto 0)),9) + resize(unsigned(BusA),9)); + when "11" => + -- BA Adj + if BAL(8) = '1' then + BAH <= std_logic_vector(unsigned(BAH) + 1); + end if; + when others => + end case; + + -- ehenciak : modified to use Y register as well (bugfix) + if ADAdd = '1' then + if (AddY = '1') then + AD <= std_logic_vector(unsigned(AD) + unsigned(Y(7 downto 0))); + else + AD <= std_logic_vector(unsigned(AD) + unsigned(X(7 downto 0))); + end if; + end if; + + if IR = "00000000" then + BAL <= (others => '1'); + BAH <= (others => '1'); + if RstCycle = '1' then + BAL(2 downto 0) <= "100"; + elsif NMICycle = '1' then + BAL(2 downto 0) <= "010"; + else + BAL(2 downto 0) <= "110"; + end if; + if Set_addr_To_r = "11" then + BAL(0) <= '1'; + end if; + end if; + + + if LDDI = '1' then + DL <= DI; + end if; + if LDALU = '1' then + DL <= ALU_Q; + end if; + if LDAD = '1' then + AD <= DI; + end if; + if LDBAL = '1' then + BAL(7 downto 0) <= DI; + end if; + if LDBAH = '1' then + BAH <= DI; + end if; + end if; + end if; + end if; + end process; + + Break <= (BreakAtNA and not BAL(8)) or (PCAdd and not PCAdder(8)); + + + with Set_BusA_To select + BusA <= DI when "000", + ABC(7 downto 0) when "001", + X(7 downto 0) when "010", + Y(7 downto 0) when "011", + std_logic_vector(S(7 downto 0)) when "100", + P when "101", + (others => '-') when others; + + with Set_Addr_To_r select + A <= "0000000000000001" & std_logic_vector(S(7 downto 0)) when "01", + DBR & "00000000" & AD when "10", + "00000000" & BAH & BAL(7 downto 0) when "11", + PBR & std_logic_vector(PC(15 downto 8)) & std_logic_vector(PCAdder(7 downto 0)) when others; + + with Write_Data_r select + DO <= DL when "000", + ABC(7 downto 0) when "001", + X(7 downto 0) when "010", + Y(7 downto 0) when "011", + std_logic_vector(S(7 downto 0)) when "100", + P when "101", + std_logic_vector(PC(7 downto 0)) when "110", + std_logic_vector(PC(15 downto 8)) when others; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + + process (Res_n, Clk) + begin + if Res_n = '0' then + MCycle <= "001"; + RstCycle <= '1'; + IRQCycle <= '0'; + NMICycle <= '0'; + NMIAct <= '0'; + elsif Clk'event and Clk = '1' then + if (Enable = '1') then + if (really_rdy = '1') then + if MCycle = LCycle or Break = '1' then + MCycle <= "000"; + RstCycle <= '0'; + IRQCycle <= '0'; + NMICycle <= '0'; + if NMIAct = '1' then + NMICycle <= '1'; + elsif IRQ_n_o = '0' and P(Flag_I) = '0' then + IRQCycle <= '1'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + + if NMICycle = '1' then + NMIAct <= '0'; + end if; + if NMI_n_o = '1' and NMI_n = '0' then + NMIAct <= '1'; + end if; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T65/T65_ALU.vhd b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T65/T65_ALU.vhd new file mode 100644 index 00000000..b1f6d632 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T65/T65_ALU.vhd @@ -0,0 +1,260 @@ +-- **** +-- T65(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 Bugfixes by ehenciak added +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- 6502 compatible microprocessor core +-- +-- Version : 0245 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t65/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0245 : First version +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T65_Pack.all; + +entity T65_ALU is + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816 + Op : in std_logic_vector(3 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + P_In : in std_logic_vector(7 downto 0); + P_Out : out std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0) + ); +end T65_ALU; + +architecture rtl of T65_ALU is + + -- AddSub variables (temporary signals) + signal ADC_Z : std_logic; + signal ADC_C : std_logic; + signal ADC_V : std_logic; + signal ADC_N : std_logic; + signal ADC_Q : std_logic_vector(7 downto 0); + signal SBC_Z : std_logic; + signal SBC_C : std_logic; + signal SBC_V : std_logic; + signal SBC_N : std_logic; + signal SBC_Q : std_logic_vector(7 downto 0); + +begin + + process (P_In, BusA, BusB) + variable AL : unsigned(6 downto 0); + variable AH : unsigned(6 downto 0); + variable C : std_logic; + begin + AL := resize(unsigned(BusA(3 downto 0) & P_In(Flag_C)), 7) + resize(unsigned(BusB(3 downto 0) & "1"), 7); + AH := resize(unsigned(BusA(7 downto 4) & AL(5)), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7); + +-- pragma translate_off + if is_x(std_logic_vector(AL)) then AL := "0000000"; end if; + if is_x(std_logic_vector(AH)) then AH := "0000000"; end if; +-- pragma translate_on + + if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then + ADC_Z <= '1'; + else + ADC_Z <= '0'; + end if; + + if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' then + AL(6 downto 1) := AL(6 downto 1) + 6; + end if; + + C := AL(6) or AL(5); + AH := resize(unsigned(BusA(7 downto 4) & C), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7); + + ADC_N <= AH(4); + ADC_V <= (AH(4) xor BusA(7)) and not (BusA(7) xor BusB(7)); + +-- pragma translate_off + if is_x(std_logic_vector(AH)) then AH := "0000000"; end if; +-- pragma translate_on + + if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' then + AH(6 downto 1) := AH(6 downto 1) + 6; + end if; + + ADC_C <= AH(6) or AH(5); + + ADC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1)); + end process; + + process (Op, P_In, BusA, BusB) + variable AL : unsigned(6 downto 0); + variable AH : unsigned(5 downto 0); + variable C : std_logic; + begin + C := P_In(Flag_C) or not Op(0); + AL := resize(unsigned(BusA(3 downto 0) & C), 7) - resize(unsigned(BusB(3 downto 0) & "1"), 6); + AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(5)), 6); + +-- pragma translate_off + if is_x(std_logic_vector(AL)) then AL := "0000000"; end if; + if is_x(std_logic_vector(AH)) then AH := "000000"; end if; +-- pragma translate_on + + if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then + SBC_Z <= '1'; + else + SBC_Z <= '0'; + end if; + + SBC_C <= not AH(5); + SBC_V <= (AH(4) xor BusA(7)) and (BusA(7) xor BusB(7)); + SBC_N <= AH(4); + + if P_In(Flag_D) = '1' then + if AL(5) = '1' then + AL(5 downto 1) := AL(5 downto 1) - 6; + end if; + AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(6)), 6); + if AH(5) = '1' then + AH(5 downto 1) := AH(5 downto 1) - 6; + end if; + end if; + + SBC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1)); + end process; + + process (Op, P_In, BusA, BusB, + ADC_Z, ADC_C, ADC_V, ADC_N, ADC_Q, + SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q) + variable Q_t : std_logic_vector(7 downto 0); + begin + -- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC + -- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC + P_Out <= P_In; + Q_t := BusA; + case Op(3 downto 0) is + when "0000" => + -- ORA + Q_t := BusA or BusB; + when "0001" => + -- AND + Q_t := BusA and BusB; + when "0010" => + -- EOR + Q_t := BusA xor BusB; + when "0011" => + -- ADC + P_Out(Flag_V) <= ADC_V; + P_Out(Flag_C) <= ADC_C; + Q_t := ADC_Q; + when "0101" | "1101" => + -- LDA + when "0110" => + -- CMP + P_Out(Flag_C) <= SBC_C; + when "0111" => + -- SBC + P_Out(Flag_V) <= SBC_V; + P_Out(Flag_C) <= SBC_C; + Q_t := SBC_Q; + when "1000" => + -- ASL + Q_t := BusA(6 downto 0) & "0"; + P_Out(Flag_C) <= BusA(7); + when "1001" => + -- ROL + Q_t := BusA(6 downto 0) & P_In(Flag_C); + P_Out(Flag_C) <= BusA(7); + when "1010" => + -- LSR + Q_t := "0" & BusA(7 downto 1); + P_Out(Flag_C) <= BusA(0); + when "1011" => + -- ROR + Q_t := P_In(Flag_C) & BusA(7 downto 1); + P_Out(Flag_C) <= BusA(0); + when "1100" => + -- BIT + P_Out(Flag_V) <= BusB(6); + when "1110" => + -- DEC + Q_t := std_logic_vector(unsigned(BusA) - 1); + when "1111" => + -- INC + Q_t := std_logic_vector(unsigned(BusA) + 1); + when others => + end case; + + case Op(3 downto 0) is + when "0011" => + P_Out(Flag_N) <= ADC_N; + P_Out(Flag_Z) <= ADC_Z; + when "0110" | "0111" => + P_Out(Flag_N) <= SBC_N; + P_Out(Flag_Z) <= SBC_Z; + when "0100" => + when "1100" => + P_Out(Flag_N) <= BusB(7); + if (BusA and BusB) = "00000000" then + P_Out(Flag_Z) <= '1'; + else + P_Out(Flag_Z) <= '0'; + end if; + when others => + P_Out(Flag_N) <= Q_t(7); + if Q_t = "00000000" then + P_Out(Flag_Z) <= '1'; + else + P_Out(Flag_Z) <= '0'; + end if; + end case; + + Q <= Q_t; + end process; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T65/T65_MCode.vhd b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T65/T65_MCode.vhd new file mode 100644 index 00000000..6c6c864a --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T65/T65_MCode.vhd @@ -0,0 +1,1052 @@ +-- **** +-- T65(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 302 minor timing fixes +-- Ver 301 Jump timing fixed +-- Ver 300 Bugfixes by ehenciak added +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- 65xx compatible microprocessor core +-- +-- Version : 0246 + fix +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t65/ +-- +-- Limitations : +-- +-- 65C02 +-- supported : inc, dec, phx, plx, phy, ply +-- missing : bra, ora, lda, cmp, sbc, tsb*2, trb*2, stz*2, bit*2, wai, stp, jmp, bbr*8, bbs*8 +-- +-- File history : +-- +-- 0246 : First release +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T65_Pack.all; + +entity T65_MCode is + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816 + IR : in std_logic_vector(7 downto 0); + MCycle : in std_logic_vector(2 downto 0); + P : in std_logic_vector(7 downto 0); + LCycle : out std_logic_vector(2 downto 0); + ALU_Op : out std_logic_vector(3 downto 0); + Set_BusA_To : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P + Set_Addr_To : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA + Write_Data : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH + Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel + BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj + BreakAtNA : out std_logic; + ADAdd : out std_logic; + AddY : out std_logic; + PCAdd : out std_logic; + Inc_S : out std_logic; + Dec_S : out std_logic; + LDA : out std_logic; + LDP : out std_logic; + LDX : out std_logic; + LDY : out std_logic; + LDS : out std_logic; + LDDI : out std_logic; + LDALU : out std_logic; + LDAD : out std_logic; + LDBAL : out std_logic; + LDBAH : out std_logic; + SaveP : out std_logic; + Write : out std_logic + ); +end T65_MCode; + +architecture rtl of T65_MCode is + + signal Branch : std_logic; + +begin + + with IR(7 downto 5) select + Branch <= not P(Flag_N) when "000", + P(Flag_N) when "001", + not P(Flag_V) when "010", + P(Flag_V) when "011", + not P(Flag_C) when "100", + P(Flag_C) when "101", + not P(Flag_Z) when "110", + P(Flag_Z) when others; + + process (IR, MCycle, P, Branch, Mode) + begin + LCycle <= "001"; + Set_BusA_To <= "001"; -- A + Set_Addr_To <= (others => '0'); + Write_Data <= (others => '0'); + Jump <= (others => '0'); + BAAdd <= "00"; + BreakAtNA <= '0'; + ADAdd <= '0'; + PCAdd <= '0'; + Inc_S <= '0'; + Dec_S <= '0'; + LDA <= '0'; + LDP <= '0'; + LDX <= '0'; + LDY <= '0'; + LDS <= '0'; + LDDI <= '0'; + LDALU <= '0'; + LDAD <= '0'; + LDBAL <= '0'; + LDBAH <= '0'; + SaveP <= '0'; + Write <= '0'; + AddY <= '0'; + + case IR(7 downto 5) is + when "100" => + --{{{ + case IR(1 downto 0) is + when "00" => + Set_BusA_To <= "011"; -- Y + Write_Data <= "011"; -- Y + when "10" => + Set_BusA_To <= "010"; -- X + Write_Data <= "010"; -- X + when others => + Write_Data <= "001"; -- A + end case; + --}}} + when "101" => + --{{{ + case IR(1 downto 0) is + when "00" => + if IR(4) /= '1' or IR(2) /= '0' then + LDY <= '1'; + end if; + when "10" => + LDX <= '1'; + when others => + LDA <= '1'; + end case; + Set_BusA_To <= "000"; -- DI + --}}} + when "110" => + --{{{ + case IR(1 downto 0) is + when "00" => + if IR(4) = '0' then + LDY <= '1'; + end if; + Set_BusA_To <= "011"; -- Y + when others => + Set_BusA_To <= "001"; -- A + end case; + --}}} + when "111" => + --{{{ + case IR(1 downto 0) is + when "00" => + if IR(4) = '0' then + LDX <= '1'; + end if; + Set_BusA_To <= "010"; -- X + when others => + Set_BusA_To <= "001"; -- A + end case; + --}}} + when others => + end case; + + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + Set_BusA_To <= "000"; -- DI + end if; + + case IR(4 downto 0) is + when "00000" | "01000" | "01010" | "11000" | "11010" => + --{{{ + -- Implied + case IR is + when "00000000" => + -- BRK + LCycle <= "110"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= "01"; -- S + Write_Data <= "111"; -- PCH + Write <= '1'; + when 2 => + Dec_S <= '1'; + Set_Addr_To <= "01"; -- S + Write_Data <= "110"; -- PCL + Write <= '1'; + when 3 => + Dec_S <= '1'; + Set_Addr_To <= "01"; -- S + Write_Data <= "101"; -- P + Write <= '1'; + when 4 => + Dec_S <= '1'; + Set_Addr_To <= "11"; -- BA + when 5 => + LDDI <= '1'; + Set_Addr_To <= "11"; -- BA + when 6 => + Jump <= "10"; -- DIDL + when others => + end case; + when "00100000" => + -- JSR + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDDI <= '1'; + Set_Addr_To <= "01"; -- S + when 2 => + Set_Addr_To <= "01"; -- S + Write_Data <= "111"; -- PCH + Write <= '1'; + when 3 => + Dec_S <= '1'; + Set_Addr_To <= "01"; -- S + Write_Data <= "110"; -- PCL + Write <= '1'; + when 4 => + Dec_S <= '1'; + when 5 => + Jump <= "10"; -- DIDL + when others => + end case; + when "01000000" => + -- RTI + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= "01"; -- S + when 2 => + Inc_S <= '1'; + Set_Addr_To <= "01"; -- S + when 3 => + Inc_S <= '1'; + Set_Addr_To <= "01"; -- S + Set_BusA_To <= "000"; -- DI + when 4 => + LDP <= '1'; + Inc_S <= '1'; + LDDI <= '1'; + Set_Addr_To <= "01"; -- S + when 5 => + Jump <= "10"; -- DIDL + when others => + end case; + when "01100000" => + -- RTS + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= "01"; -- S + when 2 => + Inc_S <= '1'; + Set_Addr_To <= "01"; -- S + when 3 => + Inc_S <= '1'; + LDDI <= '1'; + Set_Addr_To <= "01"; -- S + when 4 => + Jump <= "10"; -- DIDL + when 5 => + Jump <= "01"; + when others => + end case; + when "00001000" | "01001000" | "01011010" | "11011010" => + -- PHP, PHA, PHY*, PHX* + LCycle <= "010"; + if Mode = "00" and IR(1) = '1' then + LCycle <= "001"; + end if; + case to_integer(unsigned(MCycle)) is + when 1 => + case IR(7 downto 4) is + when "0000" => + Write_Data <= "101"; -- P + when "0100" => + Write_Data <= "001"; -- A + when "0101" => + Write_Data <= "011"; -- Y + when "1101" => + Write_Data <= "010"; -- X + when others => + end case; + Write <= '1'; + Set_Addr_To <= "01"; -- S + when 2 => + Dec_S <= '1'; + when others => + end case; + when "00101000" | "01101000" | "01111010" | "11111010" => + -- PLP, PLA, PLY*, PLX* + LCycle <= "011"; + if Mode = "00" and IR(1) = '1' then + LCycle <= "001"; + end if; + case IR(7 downto 4) is + when "0010" => + LDP <= '1'; + when "0110" => + LDA <= '1'; + when "0111" => + if Mode /= "00" then + LDY <= '1'; + end if; + when "1111" => + if Mode /= "00" then + LDX <= '1'; + end if; + when others => + end case; + case to_integer(unsigned(MCycle)) is + when 0 => + SaveP <= '1'; + when 1 => + Set_Addr_To <= "01"; -- S + when 2 => + Inc_S <= '1'; + Set_Addr_To <= "01"; -- S + when 3 => + Set_BusA_To <= "000"; -- DI + when others => + end case; + when "10100000" | "11000000" | "11100000" => + -- LDY, CPY, CPX + -- Immediate + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + when others => + end case; + when "10001000" => + -- DEY + LDY <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "011"; -- Y + when others => + end case; + when "11001010" => + -- DEX + LDX <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "010"; -- X + when others => + end case; + when "00011010" | "00111010" => + -- INC*, DEC* + if Mode /= "00" then + LDA <= '1'; -- A + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "100"; -- S + when others => + end case; + when "00001010" | "00101010" | "01001010" | "01101010" => + -- ASL, ROL, LSR, ROR + LDA <= '1'; -- A + Set_BusA_To <= "001"; -- A + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + when others => + end case; + when "10001010" | "10011000" => + -- TYA, TXA + LDA <= '1'; -- A + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + when others => + end case; + when "10101010" | "10101000" => + -- TAX, TAY + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "001"; -- A + when others => + end case; + when "10011010" => + -- TXS + case to_integer(unsigned(MCycle)) is + when 0 => + LDS <= '1'; + when 1 => + when others => + end case; + when "10111010" => + -- TSX + LDX <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "100"; -- S + when others => + end case; + + -- when "00011000" | "00111000" | "01011000" | "01111000" | "10111000" | "11011000" | "11111000" | "11001000" | "11101000" => + -- -- CLC, SEC, CLI, SEI, CLV, CLD, SED, INY, INX + -- case to_integer(unsigned(MCycle)) is + -- when 1 => + -- when others => + -- end case; + when others => + case to_integer(unsigned(MCycle)) is + when 0 => + when others => + end case; + end case; + --}}} + + when "00001" | "00011" => + --{{{ + -- Zero Page Indexed Indirect (d,x) + LCycle <= "101"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + ADAdd <= '1'; + Set_Addr_To <= "10"; -- AD + when 3 => + BAAdd <= "01"; -- DB Inc + LDBAL <= '1'; + Set_Addr_To <= "10"; -- AD + when 4 => + LDBAH <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 5 => + when others => + end case; + --}}} + + when "01001" | "01011" => + --{{{ + -- Immediate + LDA <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + when others => + end case; + + --}}} + + when "00010" | "10010" => + --{{{ + -- Immediate, KIL + LDX <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + if IR = "10100010" then + -- LDX + Jump <= "01"; + else + -- KIL !!!!!!!!!!!!!!!!!!!!!!!!!!!!! + end if; + when others => + end case; + --}}} + + when "00100" => + --{{{ + -- Zero Page + LCycle <= "010"; + case to_integer(unsigned(MCycle)) is + when 0 => + if IR(7 downto 5) = "001" then + SaveP <= '1'; + end if; + when 1 => + Jump <= "01"; + LDAD <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "10"; -- AD + when 2 => + when others => + end case; + --}}} + + when "00101" | "00110" | "00111" => + --{{{ + -- Zero Page + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + -- Read-Modify-Write + LCycle <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + LDDI <= '1'; + Write <= '1'; + Set_Addr_To <= "10"; -- AD + when 3 => + LDALU <= '1'; + SaveP <= '1'; + Write <= '1'; + Set_Addr_To <= "10"; -- AD + when 4 => + when others => + end case; + else + LCycle <= "010"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDAD <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "10"; -- AD + when 2 => + when others => + end case; + end if; + --}}} + + when "01100" => + --{{{ + -- Absolute + if IR(7 downto 6) = "01" and IR(4 downto 0) = "01100" then + -- JMP + if IR(5) = '0' then + --LCycle <= "011"; + LCycle <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDDI <= '1'; + when 2 => + Jump <= "10"; -- DIDL + when others => + end case; + else + --LCycle <= "101"; + LCycle <= "100"; -- mikej + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDDI <= '1'; + LDBAL <= '1'; + when 2 => + LDBAH <= '1'; + if Mode /= "00" then + Jump <= "10"; -- DIDL + end if; + if Mode = "00" then + Set_Addr_To <= "11"; -- BA + end if; + when 3 => + LDDI <= '1'; + if Mode = "00" then + Set_Addr_To <= "11"; -- BA + BAAdd <= "01"; -- DB Inc + else + Jump <= "01"; + end if; + when 4 => + Jump <= "10"; -- DIDL + when others => + end case; + end if; + else + LCycle <= "011"; + case to_integer(unsigned(MCycle)) is + when 0 => + if IR(7 downto 5) = "001" then + SaveP <= '1'; + end if; + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + LDBAH <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 3 => + when others => + end case; + end if; + --}}} + + when "01101" | "01110" | "01111" => + --{{{ + -- Absolute + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + -- Read-Modify-Write + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 3 => + LDDI <= '1'; + Write <= '1'; + Set_Addr_To <= "11"; -- BA + when 4 => + Write <= '1'; + LDALU <= '1'; + SaveP <= '1'; + Set_Addr_To <= "11"; -- BA + when 5 => + SaveP <= '0'; -- MIKEJ was 1 + when others => + end case; + else + LCycle <= "011"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + LDBAH <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 3 => + when others => + end case; + end if; + --}}} + + when "10000" => + --{{{ + -- Relative + + -- This circuit dictates when the last + -- microcycle occurs for the branch depending on + -- whether or not the branch is taken and if a page + -- is crossed... + if (Branch = '1') then + + LCycle <= "011"; -- We're done @ T3 if branching...upper + -- level logic will stop at T2 if no page cross + -- (See the Break signal) + else + + LCycle <= "001"; + + end if; + + -- This decodes the current microcycle and takes the + -- proper course of action... + case to_integer(unsigned(MCycle)) is + + -- On the T1 microcycle, increment the program counter + -- and instruct the upper level logic to fetch the offset + -- from the Din bus and store it in the data latches. This + -- will be the last microcycle if the branch isn't taken. + when 1 => + + Jump <= "01"; -- Increments the PC by one (PC will now be PC+2) + -- from microcycle T0. + + LDDI <= '1'; -- Tells logic in top level (T65.vhd) to route + -- the Din bus to the memory data latch (DL) + -- so that the branch offset is fetched. + + -- In microcycle T2, tell the logic in the top level to + -- add the offset. If the most significant byte of the + -- program counter (i.e. the current "page") does not need + -- updating, we are done here...the Break signal at the + -- T65.vhd level takes care of that... + when 2 => + + Jump <= "11"; -- Tell the PC Jump logic to use relative mode. + + PCAdd <= '1'; -- This tells the PC adder to update itself with + -- the current offset recently fetched from + -- memory. + + -- The following is microcycle T3 : + -- The program counter should be completely updated + -- on this cycle after the page cross is detected. + -- We don't need to do anything here... + when 3 => + + + when others => null; -- Do nothing. + + end case; + --}}} + + when "10001" | "10011" => + --{{{ + -- Zero Page Indirect Indexed (d),y + LCycle <= "101"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + LDBAL <= '1'; + BAAdd <= "01"; -- DB Inc + Set_Addr_To <= "10"; -- AD + when 3 => + Set_BusA_To <= "011"; -- Y + BAAdd <= "10"; -- BA Add + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 4 => + BAAdd <= "11"; -- BA Adj + if IR(7 downto 5) = "100" then + Write <= '1'; + else + BreakAtNA <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 5 => + when others => + end case; + --}}} + + when "10100" | "10101" | "10110" | "10111" => + --{{{ + -- Zero Page, X + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + -- Read-Modify-Write + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + ADAdd <= '1'; + Set_Addr_To <= "10"; -- AD + when 3 => + LDDI <= '1'; + Write <= '1'; + Set_Addr_To <= "10"; -- AD + when 4 => + LDALU <= '1'; + SaveP <= '1'; + Write <= '1'; + Set_Addr_To <= "10"; -- AD + when 5 => + when others => + end case; + else + LCycle <= "011"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + ADAdd <= '1'; + -- Added this check for Y reg. use... + if (IR(3 downto 0) = "0110") then + AddY <= '1'; + end if; + + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "10"; -- AD + when 3 => null; + when others => + end case; + end if; + --}}} + + when "11001" | "11011" => + --{{{ + -- Absolute Y + LCycle <= "100"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + Set_BusA_To <= "011"; -- Y + BAAdd <= "10"; -- BA Add + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 3 => + BAAdd <= "11"; -- BA adj + if IR(7 downto 5) = "100" then + Write <= '1'; + else + BreakAtNA <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 4 => + when others => + end case; + --}}} + + when "11100" | "11101" | "11110" | "11111" => + --{{{ + -- Absolute X + + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + -- Read-Modify-Write + LCycle <= "110"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + Set_BusA_To <= "010"; -- X + BAAdd <= "10"; -- BA Add + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 3 => + BAAdd <= "11"; -- BA adj + Set_Addr_To <= "11"; -- BA + when 4 => + LDDI <= '1'; + Write <= '1'; + Set_Addr_To <= "11"; -- BA + when 5 => + LDALU <= '1'; + SaveP <= '1'; + Write <= '1'; + Set_Addr_To <= "11"; -- BA + when 6 => + when others => + end case; + else + LCycle <= "100"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + -- mikej + -- special case 0xBE which uses Y reg as index!! + if (IR = "10111110") then + Set_BusA_To <= "011"; -- Y + else + Set_BusA_To <= "010"; -- X + end if; + BAAdd <= "10"; -- BA Add + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 3 => + BAAdd <= "11"; -- BA adj + if IR(7 downto 5) = "100" then + Write <= '1'; + else + BreakAtNA <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 4 => + when others => + end case; + end if; + --}}} + when others => + end case; + end process; + + process (IR, MCycle) + begin + -- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC + -- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC + case IR(1 downto 0) is + when "00" => + --{{{ + case IR(4 downto 2) is + when "000" | "001" | "011" => + case IR(7 downto 5) is + when "110" | "111" => + -- CP + ALU_Op <= "0110"; + when "101" => + -- LD + ALU_Op <= "0101"; + when "001" => + -- BIT + ALU_Op <= "1100"; + when others => + -- NOP/ST + ALU_Op <= "0100"; + end case; + when "010" => + case IR(7 downto 5) is + when "111" | "110" => + -- IN + ALU_Op <= "1111"; + when "100" => + -- DEY + ALU_Op <= "1110"; + when others => + -- LD + ALU_Op <= "1101"; + end case; + when "110" => + case IR(7 downto 5) is + when "100" => + -- TYA + ALU_Op <= "1101"; + when others => + ALU_Op <= "----"; + end case; + when others => + case IR(7 downto 5) is + when "101" => + -- LD + ALU_Op <= "1101"; + when others => + ALU_Op <= "0100"; + end case; + end case; + --}}} + when "01" => -- OR + --{{{ + ALU_Op(3) <= '0'; + ALU_Op(2 downto 0) <= IR(7 downto 5); + --}}} + when "10" => + --{{{ + ALU_Op(3) <= '1'; + ALU_Op(2 downto 0) <= IR(7 downto 5); + case IR(7 downto 5) is + when "000" => + if IR(4 downto 2) = "110" then + -- INC + ALU_Op <= "1111"; + end if; + when "001" => + if IR(4 downto 2) = "110" then + -- DEC + ALU_Op <= "1110"; + end if; + when "100" => + if IR(4 downto 2) = "010" then + -- TXA + ALU_Op <= "0101"; + else + ALU_Op <= "0100"; + end if; + when others => + end case; + --}}} + when others => + --{{{ + case IR(7 downto 5) is + when "100" => + ALU_Op <= "0100"; + when others => + if MCycle = "000" then + ALU_Op(3) <= '0'; + ALU_Op(2 downto 0) <= IR(7 downto 5); + else + ALU_Op(3) <= '1'; + ALU_Op(2 downto 0) <= IR(7 downto 5); + end if; + end case; + --}}} + end case; + end process; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T65/T65_Pack.vhd b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T65/T65_Pack.vhd new file mode 100644 index 00000000..e025e1bf --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T65/T65_Pack.vhd @@ -0,0 +1,117 @@ +-- **** +-- T65(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 Bugfixes by ehenciak added +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- 65xx compatible microprocessor core +-- +-- Version : 0246 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t65/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T65_Pack is + + constant Flag_C : integer := 0; + constant Flag_Z : integer := 1; + constant Flag_I : integer := 2; + constant Flag_D : integer := 3; + constant Flag_B : integer := 4; + constant Flag_1 : integer := 5; + constant Flag_V : integer := 6; + constant Flag_N : integer := 7; + + component T65_MCode + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816 + IR : in std_logic_vector(7 downto 0); + MCycle : in std_logic_vector(2 downto 0); + P : in std_logic_vector(7 downto 0); + LCycle : out std_logic_vector(2 downto 0); + ALU_Op : out std_logic_vector(3 downto 0); + Set_BusA_To : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P + Set_Addr_To : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA + Write_Data : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH + Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel + BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj + BreakAtNA : out std_logic; + ADAdd : out std_logic; + AddY : out std_logic; + PCAdd : out std_logic; + Inc_S : out std_logic; + Dec_S : out std_logic; + LDA : out std_logic; + LDP : out std_logic; + LDX : out std_logic; + LDY : out std_logic; + LDS : out std_logic; + LDDI : out std_logic; + LDALU : out std_logic; + LDAD : out std_logic; + LDBAL : out std_logic; + LDBAH : out std_logic; + SaveP : out std_logic; + Write : out std_logic + ); + end component; + + component T65_ALU + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816 + Op : in std_logic_vector(3 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + P_In : in std_logic_vector(7 downto 0); + P_Out : out std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T80/T80.vhd new file mode 100644 index 00000000..398fa0df --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T80/T80.vhd @@ -0,0 +1,1073 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 and Auto_Wait_t1 = '0' then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if T_Res = '1' then + Auto_Wait_t1 <= '0'; + else + Auto_Wait_t1 <= Auto_Wait or IORQ_i; + end if; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if (Auto_Wait = '1' and Auto_Wait_t2 = '0') nor + (IOWait = 1 and IORQ_i = '1' and Auto_Wait_t1 = '0') then + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T80/T80_ALU.vhd new file mode 100644 index 00000000..86fddce7 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T80/T80_ALU.vhd @@ -0,0 +1,351 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + OverFlow_v <= Carry_v xor Carry7_v; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T80/T80_MCode.vhd new file mode 100644 index 00000000..4cc30f35 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T80/T80_MCode.vhd @@ -0,0 +1,1934 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; +-- constant aNone : std_logic_vector(2 downto 0) := "000"; +-- constant aXY : std_logic_vector(2 downto 0) := "001"; +-- constant aIOA : std_logic_vector(2 downto 0) := "010"; +-- constant aSP : std_logic_vector(2 downto 0) := "011"; +-- constant aBC : std_logic_vector(2 downto 0) := "100"; +-- constant aDE : std_logic_vector(2 downto 0) := "101"; +-- constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0010"; + else + IncDec_16 <= "1010"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0010"; + else + IncDec_16 <= "1010"; + end if; + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T80/T80_Pack.vhd new file mode 100644 index 00000000..ac7d34da --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T80/T80_Pack.vhd @@ -0,0 +1,208 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T80/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T80/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T80/T80s.vhd b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T80/T80s.vhd new file mode 100644 index 00000000..5b612110 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/T80/T80s.vhd @@ -0,0 +1,190 @@ +-- +-- Z80 compatible microprocessor core, synchronous top level +-- Different timing than the original z80 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed read with wait +-- +-- 0211 : Fixed interrupt cycle +-- +-- 0235 : Updated for T80 interface change +-- +-- 0236 : Added T2Write generic +-- +-- 0237 : Fixed T2Write with wait state +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80s is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2 + IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80s; + +architecture rtl of T80s is + + signal CEN : std_logic; + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + CEN <= '1'; + + u0 : T80 + generic map( + Mode => Mode, + IOWait => IOWait) + port map( + CEN => CEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if T2Write = 0 then + if TState = "010" and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + else + if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end process; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/YM2149_linmix_sep.vhd b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/YM2149_linmix_sep.vhd new file mode 100644 index 00000000..6ed2498a --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/YM2149_linmix_sep.vhd @@ -0,0 +1,574 @@ +-- changes for seperate audio outputs and enable now enables cpu access as well +-- +-- A simulation model of YM2149 (AY-3-8910 with bells on) + +-- Copyright (c) MikeJ - Jan 2005 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- +-- Clues from MAME sound driver and Kazuhiro TSUJIKAWA +-- +-- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V) +-- vol 15 .. 0 +-- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132 +-- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order +-- to produced all the required values. +-- (The first part of the curve is a bit steeper and the last bit is more linear than expected) +-- +-- NOTE, this component uses LINEAR mixing of the three analogue channels, and is only +-- accurate for designs where the outputs are buffered and not simply wired together. +-- The ouput level is more complex in that case and requires a larger table. + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity YM2149 is + port ( + -- data bus + I_DA : in std_logic_vector(7 downto 0); + O_DA : out std_logic_vector(7 downto 0); + O_DA_OE_L : out std_logic; + -- control + I_A9_L : in std_logic; + I_A8 : in std_logic; + I_BDIR : in std_logic; + I_BC2 : in std_logic; + I_BC1 : in std_logic; + I_SEL_L : in std_logic; + + O_AUDIO : out std_logic_vector(7 downto 0); + O_CHAN : out std_logic_vector(1 downto 0); + -- port a + I_IOA : in std_logic_vector(7 downto 0); + O_IOA : out std_logic_vector(7 downto 0); + O_IOA_OE_L : out std_logic; + -- port b + I_IOB : in std_logic_vector(7 downto 0); + O_IOB : out std_logic_vector(7 downto 0); + O_IOB_OE_L : out std_logic; + + ENA : in std_logic; -- clock enable for higher speed operation + RESET_L : in std_logic; + CLK : in std_logic -- note 6 Mhz + ); +end; + +architecture RTL of YM2149 is + type array_16x8 is array (0 to 15) of std_logic_vector( 7 downto 0); + type array_3x12 is array (1 to 3) of std_logic_vector(11 downto 0); + + signal cnt_div : std_logic_vector(3 downto 0) := (others => '0'); + signal cnt_div_t1 : std_logic_vector(3 downto 0); + signal noise_div : std_logic := '0'; + signal ena_div : std_logic; + signal ena_div_noise : std_logic; + signal poly17 : std_logic_vector(16 downto 0) := (others => '0'); + + -- registers + signal addr : std_logic_vector(7 downto 0); + signal busctrl_addr : std_logic; + signal busctrl_we : std_logic; + signal busctrl_re : std_logic; + + signal reg : array_16x8; + signal env_reset : std_logic; + signal ioa_inreg : std_logic_vector(7 downto 0); + signal iob_inreg : std_logic_vector(7 downto 0); + + signal noise_gen_cnt : std_logic_vector(4 downto 0); + signal noise_gen_op : std_logic; + signal tone_gen_cnt : array_3x12 := (others => (others => '0')); + signal tone_gen_op : std_logic_vector(3 downto 1) := "000"; + + signal env_gen_cnt : std_logic_vector(15 downto 0); + signal env_ena : std_logic; + signal env_hold : std_logic; + signal env_inc : std_logic; + signal env_vol : std_logic_vector(4 downto 0); + + signal tone_ena_l : std_logic; + signal tone_src : std_logic; + signal noise_ena_l : std_logic; + signal chan_vol : std_logic_vector(4 downto 0); + + signal dac_amp : std_logic_vector(7 downto 0); +begin + -- cpu i/f + p_busdecode : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8) + variable cs : std_logic; + variable sel : std_logic_vector(2 downto 0); + begin + -- BDIR BC2 BC1 MODE + -- 0 0 0 inactive + -- 0 0 1 address + -- 0 1 0 inactive + -- 0 1 1 read + -- 1 0 0 address + -- 1 0 1 inactive + -- 1 1 0 write + -- 1 1 1 read + busctrl_addr <= '0'; + busctrl_we <= '0'; + busctrl_re <= '0'; + + cs := '0'; + if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then + cs := '1'; + end if; + + sel := (I_BDIR & I_BC2 & I_BC1); + case sel is + when "000" => null; + when "001" => busctrl_addr <= '1'; + when "010" => null; + when "011" => busctrl_re <= cs; + when "100" => busctrl_addr <= '1'; + when "101" => null; + when "110" => busctrl_we <= cs; + when "111" => busctrl_addr <= '1'; + when others => null; + end case; + end process; + + p_oe : process(busctrl_re) + begin + -- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns + O_DA_OE_L <= not (busctrl_re); + end process; + + -- + -- CLOCKED + -- + p_waddr : process(RESET_L, CLK) + begin + -- looks like registers are latches in real chip, but the address is caught at the end of the address state. + if (RESET_L = '0') then + addr <= (others => '0'); + elsif rising_edge(CLK) then + if (ENA = '1') then + if (busctrl_addr = '1') then + addr <= I_DA; + end if; + end if; + end if; + end process; + + p_wdata : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + reg <= (others => (others => '0')); + env_reset <= '1'; + elsif rising_edge(CLK) then + if (ENA = '1') then + env_reset <= '0'; + if (busctrl_we = '1') then + case addr(3 downto 0) is + when x"0" => reg(0) <= I_DA; + when x"1" => reg(1) <= I_DA; + when x"2" => reg(2) <= I_DA; + when x"3" => reg(3) <= I_DA; + when x"4" => reg(4) <= I_DA; + when x"5" => reg(5) <= I_DA; + when x"6" => reg(6) <= I_DA; + when x"7" => reg(7) <= I_DA; + when x"8" => reg(8) <= I_DA; + when x"9" => reg(9) <= I_DA; + when x"A" => reg(10) <= I_DA; + when x"B" => reg(11) <= I_DA; + when x"C" => reg(12) <= I_DA; + when x"D" => reg(13) <= I_DA; env_reset <= '1'; + when x"E" => reg(14) <= I_DA; + when x"F" => reg(15) <= I_DA; + when others => null; + end case; + end if; + end if; + end if; + end process; + + p_rdata : process(busctrl_re, addr, reg, ioa_inreg, iob_inreg) + begin + O_DA <= (others => '0'); -- 'X' + if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator + case addr(3 downto 0) is + when x"0" => O_DA <= reg(0) ; + when x"1" => O_DA <= "0000" & reg(1)(3 downto 0) ; + when x"2" => O_DA <= reg(2) ; + when x"3" => O_DA <= "0000" & reg(3)(3 downto 0) ; + when x"4" => O_DA <= reg(4) ; + when x"5" => O_DA <= "0000" & reg(5)(3 downto 0) ; + when x"6" => O_DA <= "000" & reg(6)(4 downto 0) ; + when x"7" => O_DA <= reg(7) ; + when x"8" => O_DA <= "000" & reg(8)(4 downto 0) ; + when x"9" => O_DA <= "000" & reg(9)(4 downto 0) ; + when x"A" => O_DA <= "000" & reg(10)(4 downto 0) ; + when x"B" => O_DA <= reg(11); + when x"C" => O_DA <= reg(12); + when x"D" => O_DA <= "0000" & reg(13)(3 downto 0); + when x"E" => if (reg(7)(6) = '0') then -- input + O_DA <= ioa_inreg; + else + O_DA <= reg(14); -- read output reg + end if; + when x"F" => if (Reg(7)(7) = '0') then + O_DA <= iob_inreg; + else + O_DA <= reg(15); + end if; + when others => null; + end case; + end if; + end process; + -- + p_divider : process + begin + wait until rising_edge(CLK); + -- / 8 when SEL is high and /16 when SEL is low + if (ENA = '1') then + ena_div <= '0'; + ena_div_noise <= '0'; + if (cnt_div = "0000") then + cnt_div <= (not I_SEL_L) & "111"; + ena_div <= '1'; + + noise_div <= not noise_div; + if (noise_div = '1') then + ena_div_noise <= '1'; + end if; + else + cnt_div <= cnt_div - "1"; + end if; + end if; + end process; + + p_noise_gen : process + variable noise_gen_comp : std_logic_vector(4 downto 0); + variable poly17_zero : std_logic; + begin + wait until rising_edge(CLK); + if (reg(6)(4 downto 0) = "00000") then + noise_gen_comp := "00000"; + else + noise_gen_comp := (reg(6)(4 downto 0) - "1"); + end if; + + poly17_zero := '0'; + if (poly17 = "00000000000000000") then poly17_zero := '1'; end if; + + if (ENA = '1') then + if (ena_div_noise = '1') then -- divider ena + + if (noise_gen_cnt >= noise_gen_comp) then + noise_gen_cnt <= "00000"; + poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1); + else + noise_gen_cnt <= (noise_gen_cnt + "1"); + end if; + end if; + end if; + end process; + noise_gen_op <= poly17(0); + + p_tone_gens : process + variable tone_gen_freq : array_3x12; + variable tone_gen_comp : array_3x12; + begin + wait until rising_edge(CLK); + -- looks like real chips count up - we need to get the Exact behaviour .. + tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0); + tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2); + tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4); + -- period 0 = period 1 + for i in 1 to 3 loop + if (tone_gen_freq(i) = x"000") then + tone_gen_comp(i) := x"000"; + else + tone_gen_comp(i) := (tone_gen_freq(i) - "1"); + end if; + end loop; + + if (ENA = '1') then + for i in 1 to 3 loop + if (ena_div = '1') then -- divider ena + + if (tone_gen_cnt(i) >= tone_gen_comp(i)) then + tone_gen_cnt(i) <= x"000"; + tone_gen_op(i) <= not tone_gen_op(i); + else + tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1"); + end if; + end if; + end loop; + end if; + end process; + + p_envelope_freq : process + variable env_gen_freq : std_logic_vector(15 downto 0); + variable env_gen_comp : std_logic_vector(15 downto 0); + begin + wait until rising_edge(CLK); + env_gen_freq := reg(12) & reg(11); + -- envelope freqs 1 and 0 are the same. + if (env_gen_freq = x"0000") then + env_gen_comp := x"0000"; + else + env_gen_comp := (env_gen_freq - "1"); + end if; + + if (ENA = '1') then + env_ena <= '0'; + if (ena_div = '1') then -- divider ena + if (env_gen_cnt >= env_gen_comp) then + env_gen_cnt <= x"0000"; + env_ena <= '1'; + else + env_gen_cnt <= (env_gen_cnt + "1"); + end if; + end if; + end if; + end process; + + p_envelope_shape : process(env_reset, reg, CLK) + variable is_bot : boolean; + variable is_bot_p1 : boolean; + variable is_top_m1 : boolean; + variable is_top : boolean; + begin + -- envelope shapes + -- C AtAlH + -- 0 0 x x \___ + -- + -- 0 1 x x /___ + -- + -- 1 0 0 0 \\\\ + -- + -- 1 0 0 1 \___ + -- + -- 1 0 1 0 \/\/ + -- ___ + -- 1 0 1 1 \ + -- + -- 1 1 0 0 //// + -- ___ + -- 1 1 0 1 / + -- + -- 1 1 1 0 /\/\ + -- + -- 1 1 1 1 /___ + if (env_reset = '1') then + -- load initial state + if (reg(13)(2) = '0') then -- attack + env_vol <= "11111"; + env_inc <= '0'; -- -1 + else + env_vol <= "00000"; + env_inc <= '1'; -- +1 + end if; + env_hold <= '0'; + + elsif rising_edge(CLK) then + is_bot := (env_vol = "00000"); + is_bot_p1 := (env_vol = "00001"); + is_top_m1 := (env_vol = "11110"); + is_top := (env_vol = "11111"); + + if (ENA = '1') then + if (env_ena = '1') then + if (env_hold = '0') then + if (env_inc = '1') then + env_vol <= (env_vol + "00001"); + else + env_vol <= (env_vol + "11111"); + end if; + end if; + + -- envelope shape control. + if (reg(13)(3) = '0') then + if (env_inc = '0') then -- down + if is_bot_p1 then env_hold <= '1'; end if; + else + if is_top then env_hold <= '1'; end if; + end if; + else + if (reg(13)(0) = '1') then -- hold = 1 + if (env_inc = '0') then -- down + if (reg(13)(1) = '1') then -- alt + if is_bot then env_hold <= '1'; end if; + else + if is_bot_p1 then env_hold <= '1'; end if; + end if; + else + if (reg(13)(1) = '1') then -- alt + if is_top then env_hold <= '1'; end if; + else + if is_top_m1 then env_hold <= '1'; end if; + end if; + end if; + + elsif (reg(13)(1) = '1') then -- alternate + if (env_inc = '0') then -- down + if is_bot_p1 then env_hold <= '1'; end if; + if is_bot then env_hold <= '0'; env_inc <= '1'; end if; + else + if is_top_m1 then env_hold <= '1'; end if; + if is_top then env_hold <= '0'; env_inc <= '0'; end if; + end if; + end if; + + end if; + end if; + end if; + end if; + end process; + + p_chan_mixer : process(cnt_div, reg, tone_gen_op) + begin + tone_ena_l <= '1'; tone_src <= '1'; + noise_ena_l <= '1'; chan_vol <= "00000"; + case cnt_div(1 downto 0) is + when "00" => + tone_ena_l <= reg(7)(0); tone_src <= tone_gen_op(1); chan_vol <= reg(8)(4 downto 0); + noise_ena_l <= reg(7)(3); + when "01" => + tone_ena_l <= reg(7)(1); tone_src <= tone_gen_op(2); chan_vol <= reg(9)(4 downto 0); + noise_ena_l <= reg(7)(4); + when "10" => + tone_ena_l <= reg(7)(2); tone_src <= tone_gen_op(3); chan_vol <= reg(10)(4 downto 0); + noise_ena_l <= reg(7)(5); + when "11" => null; -- tone gen outputs become valid on this clock + when others => null; + end case; + end process; + + p_op_mixer : process + variable chan_mixed : std_logic; + variable chan_amp : std_logic_vector(4 downto 0); + begin + wait until rising_edge(CLK); + if (ENA = '1') then + + chan_mixed := (tone_ena_l or tone_src) and (noise_ena_l or noise_gen_op); + + chan_amp := (others => '0'); + if (chan_mixed = '1') then + if (chan_vol(4) = '0') then + if (chan_vol(3 downto 0) = "0000") then -- nothing is easy ! make sure quiet is quiet + chan_amp := "00000"; + else + chan_amp := chan_vol(3 downto 0) & '1'; -- make sure level 31 (env) = level 15 (tone) + end if; + else + chan_amp := env_vol(4 downto 0); + end if; + end if; + + dac_amp <= x"00"; + case chan_amp is + when "11111" => dac_amp <= x"FF"; + when "11110" => dac_amp <= x"D9"; + when "11101" => dac_amp <= x"BA"; + when "11100" => dac_amp <= x"9F"; + when "11011" => dac_amp <= x"88"; + when "11010" => dac_amp <= x"74"; + when "11001" => dac_amp <= x"63"; + when "11000" => dac_amp <= x"54"; + when "10111" => dac_amp <= x"48"; + when "10110" => dac_amp <= x"3D"; + when "10101" => dac_amp <= x"34"; + when "10100" => dac_amp <= x"2C"; + when "10011" => dac_amp <= x"25"; + when "10010" => dac_amp <= x"1F"; + when "10001" => dac_amp <= x"1A"; + when "10000" => dac_amp <= x"16"; + when "01111" => dac_amp <= x"13"; + when "01110" => dac_amp <= x"10"; + when "01101" => dac_amp <= x"0D"; + when "01100" => dac_amp <= x"0B"; + when "01011" => dac_amp <= x"09"; + when "01010" => dac_amp <= x"08"; + when "01001" => dac_amp <= x"07"; + when "01000" => dac_amp <= x"06"; + when "00111" => dac_amp <= x"05"; + when "00110" => dac_amp <= x"04"; + when "00101" => dac_amp <= x"03"; + when "00100" => dac_amp <= x"03"; + when "00011" => dac_amp <= x"02"; + when "00010" => dac_amp <= x"02"; + when "00001" => dac_amp <= x"01"; + when "00000" => dac_amp <= x"00"; + when others => null; + end case; + + cnt_div_t1 <= cnt_div; + end if; + end process; + + p_audio_output : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + O_AUDIO <= (others => '0'); + O_CHAN <= (others => '0'); + elsif rising_edge(CLK) then + + if (ENA = '1') then + O_AUDIO <= dac_amp(7 downto 0); + O_CHAN <= cnt_div_t1(1 downto 0); + end if; + end if; + end process; + + p_io_ports : process(reg) + begin + O_IOA <= reg(14); + O_IOA_OE_L <= not reg(7)(6); + O_IOB <= reg(15); + O_IOB_OE_L <= not reg(7)(7); + end process; + + p_io_ports_inreg : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then -- resync + ioa_inreg <= I_IOA; + iob_inreg <= I_IOB; + end if; + end process; +end architecture RTL; diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/build_id.tcl b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/cmd_hvgen.v b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/cmd_hvgen.v new file mode 100644 index 00000000..f4812295 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/cmd_hvgen.v @@ -0,0 +1,36 @@ +module cmd_hvgen +( + output [8:0] HPOS, + output [8:0] VPOS, + input PCLK, + output reg HBLK = 1, + output reg VBLK = 1, + output reg HSYN = 1, + output reg VSYN = 1 +); + +reg [8:0] hcnt = 0; +reg [8:0] vcnt = 0; + +assign HPOS = hcnt; +assign VPOS = vcnt; + +always @(posedge PCLK) begin + case (hcnt) + 287: begin HBLK <= 1; HSYN <= 0; hcnt <= hcnt+1; end + 311: begin HSYN <= 1; hcnt <= hcnt+1; end + 383: begin + HBLK <= 0; HSYN <= 1; hcnt <= 0; + case (vcnt) + 223: begin VBLK <= 1; vcnt <= vcnt+1; end + 226: begin VSYN <= 0; vcnt <= vcnt+1; end + 233: begin VSYN <= 1; vcnt <= vcnt+1; end + 242: begin VBLK <= 0; vcnt <= 0; end + default: vcnt <= vcnt+1; + endcase + end + default: hcnt <= hcnt+1; + endcase +end + +endmodule \ No newline at end of file diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/cmd_sound.vhd b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/cmd_sound.vhd new file mode 100644 index 00000000..2207d673 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/cmd_sound.vhd @@ -0,0 +1,425 @@ +--------------------------------------------------------------------------------- +-- burnin rubber sound by Dar (darfpga@aol.fr) (05/12/2017) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- +-- gen_ram.vhd & io_ps2_keyboard +-------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +--------------------------------------------------------------------------------- +-- T65(b) core.Ver 301 by MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +--------------------------------------------------------------------------------- +-- YM2149 (AY-3-8910) +-- Copyright (c) MikeJ - Jan 2005 +--------------------------------------------------------------------------------- +-- Use burnin_rubber_de10_lite.sdc to compile (Timequest constraints) +-- /!\ +-- Don't forget to set device configuration mode with memory initialization +-- (Assignments/Device/Pin options/Configuration mode) +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity cmd_sound is +port +( + clock_12 : in std_logic; + reset : in std_logic; + + sound_req : in std_logic; + sound_code_in : in std_logic_vector(7 downto 0); + sound_timing : in std_logic; + + audio_out : out std_logic_vector(10 downto 0); + + dbg_cpu_addr: out std_logic_vector(15 downto 0) + ); +end cmd_sound; + +architecture syn of cmd_sound is + + -- clocks, reset + signal clock_12n : std_logic; + signal clock_div1 : std_logic_vector(8 downto 0) := (others =>'0'); + signal clock_div2 : std_logic_vector(4 downto 0) := (others =>'0'); + signal clock_500K : std_logic; + signal ayx_clock : std_logic; + signal reset_n : std_logic; + + -- cpu signals + signal cpu_addr : std_logic_vector(23 downto 0); + signal cpu_di : std_logic_vector( 7 downto 0); + signal cpu_di_dec : std_logic_vector( 7 downto 0); + signal cpu_do : std_logic_vector( 7 downto 0); + signal cpu_rw_n : std_logic; + signal cpu_nmi_n : std_logic; + signal cpu_irq_n : std_logic; + signal cpu_sync : std_logic; + + -- program rom signals + signal prog_rom_cs : std_logic; + signal prog_rom_do : std_logic_vector(7 downto 0); + + -- working ram signals + signal wram_cs : std_logic; + signal wram_we : std_logic; + signal wram_do : std_logic_vector(7 downto 0); + + -- sound req management + signal nmi_reg : std_logic; + signal nmi_reg_cs : std_logic; + signal nmi_reg_we : std_logic; + signal sound_code : std_logic_vector(7 downto 0); + signal sound_code_cs : std_logic; + + -- ay-3-8910 signal + signal ay1_bc1 : std_logic; + signal ay1_bdir : std_logic; + signal ay1_audio_chan : std_logic_vector(1 downto 0); + signal ay1_audio_muxed: std_logic_vector(7 downto 0); + signal ay1_chan_a: std_logic_vector(7 downto 0); + signal ay1_chan_b: std_logic_vector(7 downto 0); + signal ay1_chan_c: std_logic_vector(7 downto 0); + + signal ay2_bc1 : std_logic; + signal ay2_bdir : std_logic; + signal ay2_audio_chan : std_logic_vector(1 downto 0); + signal ay2_audio_muxed: std_logic_vector(7 downto 0); + signal ay2_chan_a: std_logic_vector(7 downto 0); + signal ay2_chan_b: std_logic_vector(7 downto 0); + signal ay2_chan_c: std_logic_vector(7 downto 0); + + -- digital filtering AY2 channel A + signal uin : integer range -256 to 255; + signal u3 : integer range -32768 to 32767; + signal u4 : integer range -32768 to 32767; + signal du3 : integer range -32768*4096 to 32767*4096; + signal du4 : integer range -32768*4096 to 32767*4096; + signal uout : integer range -32768 to 32767; + signal uout_lim : integer range -128 to 127; + +begin + +process (clock_12, cpu_sync) +begin + if rising_edge(clock_12) then + if cpu_sync = '1' then + dbg_cpu_addr <= cpu_addr(15 downto 0); + end if; + end if; +end process; + +reset_n <= not reset; +clock_12n <= not clock_12; + +process (clock_12, reset) + begin + if reset='1' then + clock_div1 <= (others => '0'); + clock_div2 <= (others => '0'); + else + if rising_edge(clock_12) then + if clock_div1 = "111111111" then -- divide by 512 (23.437kHz) + clock_div1 <= "000000000"; + else + clock_div1 <= clock_div1 + '1'; + end if; + if clock_div2 = "10111" then -- divide by 24 + clock_div2 <= "00000"; + else + clock_div2 <= clock_div2 + '1'; + end if; + end if; + end if; +end process; + +clock_500K <= clock_div2(4); --12MHz/24 = 500kHz +ayx_clock <= clock_div1(2); --12MHz/8 = 1.5MHz + +--static ADDRESS_MAP_START( audio_map, AS_PROGRAM, 8, btime_state ) +-- AM_RANGE(0x0000, 0x03ff) AM_MIRROR(0x1c00) AM_RAM AM_SHARE("audio_rambase") +-- AM_RANGE(0x2000, 0x3fff) AM_DEVWRITE("ay1", ay8910_device, data_w) +-- AM_RANGE(0x4000, 0x5fff) AM_DEVWRITE("ay1", ay8910_device, address_w) +-- AM_RANGE(0x6000, 0x7fff) AM_DEVWRITE("ay2", ay8910_device, data_w) +-- AM_RANGE(0x8000, 0x9fff) AM_DEVWRITE("ay2", ay8910_device, address_w) +-- AM_RANGE(0xa000, 0xbfff) AM_READ(audio_command_r) +-- AM_RANGE(0xc000, 0xdfff) AM_WRITE(audio_nmi_enable_w) +-- AM_RANGE(0xe000, 0xefff) AM_MIRROR(0x1000) AM_ROM +--ADDRESS_MAP_END + +-- chip select +wram_cs <= '1' when cpu_addr(15 downto 13) = "000" else '0'; -- working ram 0000-07ff .. 1fff +ay1_bc1 <= '1' when cpu_addr(15 downto 13) = "010" else '0'; +ay1_bdir <= '1' when cpu_addr(15 downto 13) = "001" or ay1_bc1 = '1' else '0'; +ay2_bc1 <= '1' when cpu_addr(15 downto 13) = "100" else '0'; +ay2_bdir <= '1' when cpu_addr(15 downto 13) = "011" or ay2_bc1 = '1' else '0'; +sound_code_cs <= '1' when cpu_addr(15 downto 13) = "101" else '0'; +nmi_reg_cs <= '1' when cpu_addr(15 downto 13) = "110" else '0'; +prog_rom_cs <= '1' when cpu_addr(15 downto 13) = "111" else '0'; + +-- write enable +wram_we <= '1' when wram_cs = '1' and cpu_rw_n = '0' else '0'; +nmi_reg_we <= '1' when nmi_reg_cs = '1' and cpu_rw_n = '0' else '0'; + +-- cpu di mux +cpu_di <= wram_do when wram_cs = '1' else + prog_rom_do when prog_rom_cs = '1' else + sound_code when sound_code_cs = '1' else + X"FF"; + +-- regsiter sound code and irq management +process (clock_12) +begin + if rising_edge(clock_12) then + if sound_req = '1' then + sound_code <= sound_code_in; + cpu_irq_n <= '0'; + end if; + if sound_code_cs = '1' then + cpu_irq_n <= '1'; + end if; + end if; +end process; + +-- nmi autorisation management +process (reset, clock_12) +begin + if reset = '1' then + nmi_reg <= '0'; + else + if rising_edge(clock_12) then + if nmi_reg_we = '1' then + nmi_reg <= cpu_do(0); + end if; + end if; + end if; +end process; + +-- nmi +cpu_nmi_n <= '0' when nmi_reg = '1' and sound_timing = '1' else '1'; + +-- demux AY chips output +process (ayx_clock) +begin + if rising_edge(ayx_clock) then + if ay1_audio_chan = "00" then ay1_chan_a <= ay1_audio_muxed; end if; + if ay1_audio_chan = "01" then ay1_chan_b <= ay1_audio_muxed; end if; + if ay1_audio_chan = "10" then ay1_chan_c <= ay1_audio_muxed; end if; + if ay2_audio_chan = "00" then ay2_chan_a <= ay2_audio_muxed; end if; + if ay2_audio_chan = "01" then ay2_chan_b <= ay2_audio_muxed; end if; + if ay2_audio_chan = "10" then ay2_chan_c <= ay2_audio_muxed; end if; + end if; +end process; + +-- AOP Rauch passe bande filter +-- +-- ----------o------------ +-- u4^ | | | +-- | --- C4 | | R5 | +-- | --- | | | +-- | | C3 | | +-- --| R1 |----o----||---o------|\ | +-- ^ | ------> u3 | \__o--- +-- | | | / ^ +-- |uin | | R2 --|/ | +-- | | | | | uout +-- | | | | +-- ------------o--------------o---------- +-- +-- +-- i1 = (sin+u3)/R1 +-- i2 = -u3/R2 +-- i3 = (u4-u3)/R5 +-- i4 = i2-i1-i3 +-- +-- u3(t+dt) = u3(t) + i3(t)*dt/C3; +-- u4(t+dt) = u4(t) + i4(t)*dt/C4; + +-- uout = u4-u3 + +-- R1 = 5000; +-- R2 = 10000; +-- C3 = 0.068e-6; +-- C4 = 0.068e-6; +-- R5 = 47000; +-- +-- dt = 1/f_ech = 1/23437 +-- dt/C3 = dt/C4 = 627 +-- +-- (i3(t)*dt/C3)*8192 = du3*8192 = ((u4-u3)/47000*627)*8192 +-- = (u4-u3)*109 +-- +-- (i4(t)*dt/C4)*8192 = du4*8192 = (-u3/10000 -(uin+u3)/5000 -(u4-u3)/47000)*627*8192 +-- = -u3(514+1027-109) - uin*1027 - u4*109 +-- = -(u4*109 + u3*1432 + uin*1027) +-- + +-- down sample to 23.437kHz and filter AY2 channel A +uin <= to_integer(unsigned(ay2_chan_a)); + +process (clock_12) +begin + if rising_edge(clock_12) then + + if clock_div1 = "000000000" then + du3 <= u4*109 - u3*109; + du4 <= u4*109 + u3*1432 + uin*1027*16; -- add gain(16) to uin + end if; + + if clock_div1 = "000000001" then + u3 <= u3 + du3/8192; + u4 <= u4 - du4/8192; + end if; + + if clock_div1 = "000000010" then + uout <= (u4 - u3) / 8; -- adjust output gain + end if; + + -- limit signed dynamique before return to unsigned + if clock_div1 = "000000011" then + if uout > 127 then + uout_lim <= 127; + elsif uout < -127 then + uout_lim <= -127; + else + uout_lim <= uout; + end if; + end if; + + if clock_div1 = "000000100" then + + audio_out <= ("000"&ay1_chan_a(7 downto 0)) + + ("000"&ay1_chan_b(7 downto 0)) + + ("000"&ay1_chan_c(7 downto 0)) + + ("000"&std_logic_vector(to_unsigned(uout_lim+128,8)))+ + ("000"&ay2_chan_b(7 downto 0)) + + ("000"&ay2_chan_c(7 downto 0)); + end if; + + end if; +end process; + +--------------------------- +-- components +--------------------------- + +cpu_inst : entity work.T65 +port map +( + Mode => "00", -- 6502 + Res_n => reset_n, + Enable => '1', + Clk => clock_500K, + Rdy => '1', + Abort_n => '1', + IRQ_n => cpu_irq_n, + NMI_n => cpu_nmi_n, + SO_n => '1',--cpu_so_n, + R_W_n => cpu_rw_n, + Sync => cpu_sync, -- open + EF => open, + MF => open, + XF => open, + ML_n => open, + VP_n => open, + VDA => open, + VPA => open, + A => cpu_addr, + DI => cpu_di, + DO => cpu_do +); + +-- working ram +wram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 11) +port map( + clk => clock_12n, + we => wram_we, + addr => cpu_addr(10 downto 0), + d => cpu_do, + q => wram_do +); + +-- program rom +program_rom: entity work.cmd_snd_rom +port map( + clk => clock_12n, + addr => cpu_addr(11 downto 0), + data => prog_rom_do +); + +-- AY-3-8910 #1 +ay_3_8910_1 : entity work.YM2149 +port map( + -- data bus + I_DA => cpu_do, -- in std_logic_vector(7 downto 0); + O_DA => open, -- out std_logic_vector(7 downto 0); + O_DA_OE_L => open, -- out std_logic; + -- control + I_A9_L => '0', -- in std_logic; + I_A8 => '1', -- in std_logic; + I_BDIR => ay1_bdir, -- in std_logic; + I_BC2 => '1', -- in std_logic; + I_BC1 => ay1_bc1, -- in std_logic; + I_SEL_L => '1', -- in std_logic; + + O_AUDIO => ay1_audio_muxed, -- out std_logic_vector(7 downto 0); + O_CHAN => ay1_audio_chan, -- out std_logic_vector(1 downto 0); + + -- port a + I_IOA => X"00", -- in std_logic_vector(7 downto 0); + O_IOA => open, -- out std_logic_vector(7 downto 0); + O_IOA_OE_L => open, -- out std_logic; + -- port b + I_IOB => X"00", -- in std_logic_vector(7 downto 0); + O_IOB => open, -- out std_logic_vector(7 downto 0); + O_IOB_OE_L => open, -- out std_logic; + + ENA => '1', -- in std_logic; -- clock enable for higher speed operation + RESET_L => reset_n, -- in std_logic; + CLK => ayx_clock -- in std_logic -- note 6 Mhz +); + +-- AY-3-8910 #2 +ay_3_8910_2 : entity work.YM2149 +port map( + -- data bus + I_DA => cpu_do, -- in std_logic_vector(7 downto 0); + O_DA => open, -- out std_logic_vector(7 downto 0); + O_DA_OE_L => open, -- out std_logic; + -- control + I_A9_L => '0', -- in std_logic; + I_A8 => '1', -- in std_logic; + I_BDIR => ay2_bdir, -- in std_logic; + I_BC2 => '1', -- in std_logic; + I_BC1 => ay2_bc1, -- in std_logic; + I_SEL_L => '1', -- in std_logic; + + O_AUDIO => ay2_audio_muxed, -- out std_logic_vector(7 downto 0); + O_CHAN => ay2_audio_chan, -- out std_logic_vector(1 downto 0); + + -- port a + I_IOA => (others => '0'), -- in std_logic_vector(7 downto 0); + O_IOA => open, -- out std_logic_vector(7 downto 0); + O_IOA_OE_L => open, -- out std_logic; + -- port b + I_IOB => (others => '0'), -- in std_logic_vector(7 downto 0); + O_IOB => open, -- out std_logic_vector(7 downto 0); + O_IOB_OE_L => open, -- out std_logic; + + ENA => '1', --cpu_ena, -- in std_logic; -- clock enable for higher speed operation + RESET_L => reset_n, -- in std_logic; + CLK => ayx_clock -- in std_logic -- note 6 Mhz +); + + +end SYN; diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/cmd_sprite.v b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/cmd_sprite.v new file mode 100644 index 00000000..4e2052c7 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/cmd_sprite.v @@ -0,0 +1,154 @@ + +module cmd_sprite +( + input VCLKx4, + input HBLK, + + input [8:0] HPOS, + input [8:0] VPOS, + + output reg [10:0] SPRAADRS, + input [15:0] SPRADATA, + + output [3:0] ARAMADRS, + input [7:0] ARAMDATA, + + output [11:0] SPCHRADR, + input [7:0] SPCHRDAT, + + output [7:0] DROMAD, + input [7:0] DROMDT, + + output reg [8:0] SPCOL +); + +reg [1:0] clkcnt; +always @( posedge VCLKx4 ) clkcnt<=clkcnt+1; +wire VCLKx2 = clkcnt[0]; +wire VCLK = clkcnt[1]; + +wire SIDE = VPOS[0]; + + +reg [19:0] SPATR0; +reg [36:0] SPATRS[0:31]; +reg [3:0] WWADR; +reg bHit; + +assign ARAMADRS = SPRAADRS[3:0]; + + +reg [7:0] WRADR; +reg [8:0] HPOSW; +reg [8:0] SPWCL; + +wire [36:0] SPA = SPATRS[{~SIDE,WRADR[7:4]}]; + +wire [3:0] SH = WRADR[3:0]+4'h4; +wire [3:0] SV = SPA[35:32]; + +wire [2:0] SPFY = { 3{SPA[1]} }; +wire [1:0] SPFX = { 1'b0, SPA[0] }; +wire [5:0] SPPL = SPA[29:24]; + +assign SPCHRADR = { SPA[7:2], ( SV[3] ^ SPA[1] ), ( SH[3:2] ^ SPFX ), ( SV[2:0] ^ SPFY ) }; +wire [7:0] CHRO = SPCHRDAT; + + +wire [8:0] YM = ( SPRADATA[15:8] + 8'h10 ) + VPOS[7:0]; + +assign DROMAD = { 1'b0, (~SPA[19:17]), SPA[33:32], WRADR[3:2] }; + +always @ ( posedge VCLKx2 ) begin + + // in H-BLANK + if ( HBLK ) begin + + // Sprite V-hit check & list-up + if ( SPRAADRS < 10'h20 ) begin + if ( SPRAADRS[0] ) begin + if ( bHit ) begin + SPATRS[{SIDE,WWADR}] <= { 1'b1, SPATR0[3:0], SPRADATA, SPATR0[19:4] }; + WWADR <= WWADR+1; + end + end + else begin + if ( YM[7:4] == 4'b1111 ) begin + bHit <= 1; + SPATR0 <= { SPRADATA, YM[3:0] }; + end + else bHit <= 0; + end + SPRAADRS <= ( SPRAADRS == 10'h1F ) ? 10'h34 : (SPRAADRS+1); + end + // Rader-dot V-hit check & list-up + else begin + if ( SPRAADRS < 10'h40 ) begin + if ( YM[7:2] == 6'b111111 ) begin + SPATRS[{SIDE,WWADR}] <= { 1'b0, 2'b00, YM[1:0], 8'h0, ARAMDATA, SPRADATA }; + WWADR <= WWADR+1; + end + SPRAADRS <= SPRAADRS+1; + end + else SPATRS[{SIDE,WWADR}] <= 0; + end + + if ( SPA ) begin + // Rend Sprite + if ( SPA[36] ) begin + HPOSW <= ( WRADR[3:0] ) ? (HPOSW+1) : { SPA[31], SPA[23:16] }; + case ( SH[1:0] ^ {2{SPFX[0]}} ) + 2'b00: SPWCL <= { 1'b0, SPPL, CHRO[7], CHRO[3] }; + 2'b01: SPWCL <= { 1'b0, SPPL, CHRO[6], CHRO[2] }; + 2'b10: SPWCL <= { 1'b0, SPPL, CHRO[5], CHRO[1] }; + 2'b11: SPWCL <= { 1'b0, SPPL, CHRO[4], CHRO[0] }; + endcase + WRADR <= WRADR+1; + end + // Rend Rader-dot + else begin + HPOSW <= ( WRADR[3:0] ) ? (HPOSW+1) : ({ (~SPA[16]), SPA[7:0] }); + SPWCL <= ( DROMDT[1:0] != 2'b11 ) ? { 1'b1, 6'b000100, DROMDT[1:0] } : 0; + WRADR <= WRADR+4; + end + end + else SPWCL <= 0; + + end + + // in H-DISP + else begin + SPRAADRS <= 10'h14; + WWADR <= 0; + WRADR <= 0; + SPWCL <= 0; + end + +end + + +reg [9:0] radr0=0,radr1=1; +wire [8:0] SPCOLi; +dpram #( + .widthad_a(10), + .width_a(9)) +linebuffer( + .address_a({SIDE,HPOS}), + .address_b({~SIDE,HPOSW}), + .clock_a(VCLKx2), + .clock_b(VCLKx2), + .data_a(9'h0), + .data_b(SPWCL), + .wren_a(radr0==radr1), + .wren_b((SPWCL[0]|SPWCL[1])), + .q_a(SPCOLi), + .q_b() + ); + +always @(posedge VCLK) radr0 <= {SIDE,HPOS}; +always @(negedge VCLK) begin + if (radr0!=radr1) SPCOL <= SPCOLi; + radr1 <= radr0; +end + +endmodule diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/cmd_top.v b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/cmd_top.v new file mode 100644 index 00000000..8890be13 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/cmd_top.v @@ -0,0 +1,195 @@ +/************************************************************** + FPGA Commando (Main part) +***************************************************************/ +module cmd_top +( + input RESET, // RESET + input CLK24M, // Clock 24.576MHz + output hsync, + output vsync, + output hblank, + output vblank, + output [2:0] r, + output [2:0] g, + output [1:0] b, + output [10:0] SND, // Sound (unsigned PCM) + input [7:0] DSW1, // DipSW + input [7:0] DSW2, // DipSW + input [7:0] CTR1, // Controler (Negative logic) + input [7:0] CTR2 +); + + +//-------------------------------------------------- +// Clock Generators +//-------------------------------------------------- +reg [2:0] _CCLK; +always @( posedge CLK24M ) _CCLK <= _CCLK+1; + +wire CLK = CLK24M; // 24MHz +wire CCLKx4 = _CCLK[0]; // CPU CLOCKx4 : 12.0MHz +wire CCLK = _CCLK[2]; // CPU CLOCK : 3.0MHz + + +//-------------------------------------------------- +// CPU +//-------------------------------------------------- +// memory access signals +wire rd, wr, me, ie, rf, m1; +wire [15:0] ad; +wire [7:0] odt, viddata; + +wire mx = rf & (~me); +wire mr = mx & (~rd); +wire mw = mx & (~wr); + +// interrupt signal/vector generator & other latches +reg inte = 1'b0; +reg intl = 1'b0; +reg [7:0] intv = 8'h0; + + +reg out1r = 1'b0; +reg out2r = 1'b0; +reg out3r = 1'b0; +reg sonr = 1'b0;//sound On + +wire vblk = (VP==224)&(HP<=8); + +wire lat_Wce = ( ad[15:4] == 12'hA18 ) & mw; + +wire sndw = ( lat_Wce & ( ad[3:0] == 4'h0 ) ); +wire iewr = ( lat_Wce & ( ad[3:0] == 4'h1 ) ); +wire mute = ( lat_Wce & ( ad[3:0] == 4'h1 ) );//mute +wire flip = ( lat_Wce & ( ad[3:0] == 4'h3 ) );//flip +wire out1w = ( lat_Wce & ( ad[3:0] == 4'h4 ) ); +//wire out2w = ( lat_Wce & ( ad[3:0] == 4'h5 ) );//NOP +wire out3w = ( lat_Wce & ( ad[3:0] == 4'h6 ) ); +//wire starw = ( lat_Wce & ( ad[3:0] == 4'h7 ) );//not used +wire iowr = ( (~wr) & (~ie) & m1 ); + + +always @( posedge CCLK ) begin + if ( iowr ) intv <= odt; + if ( vblk ) intl <= 1'b1; + if ( iewr ) begin + inte <= odt[0]; + intl <= 1'b0; + end + if ( sndw ) sonr <= odt[0]; + if ( out1w ) out1r <= odt[0]; +// if ( out2w ) out2r <= odt[0]; + if ( out3w ) out3r <= odt[0]; +end + +wire irq_n = ~( intl & inte ); + + +// address decoders +wire rom_Rce = ( ( ad[15] == 1'b0 ) & mr ); // $0000-$7FFF(R) +wire ram_Rce = ( ( ad[15:11] == 5'b1001_1 ) & mr ); // $9800-$9FFF(R) +wire ram_Wce = ( ( ad[15:11] == 5'b1001_1 ) & mw ); // $9800-$9FFF(W) +wire inp_Rce = ( ( ad[15:12] == 4'b1010 ) & mr ); // $A000-$AFFF(R) +wire snd_Wce = ( ( ad[15:8] == 8'b1010_0001 ) & mw ); // $A100-$A1FF(W) +wire vid_Rce; + + +wire [7:0] romdata; +cmd_prg_rom cmd_prg_rom ( + .clk(CCLK), + .addr(ad[14:0]), + .data(romdata) + ); + +// Work RAM (2KB) +wire [7:0] ramdata; +GSPRAM #(11,8) workram( + .CL(CCLK), + .AD(ad[10:0]), + .WE(ram_Wce), + .DI(odt), + .DO(ramdata) + ); + + +// Controler/DipSW input +wire [7:0] in0data = CTR1; +wire [7:0] in1data = CTR2; +wire [7:0] in2data = DSW1; +wire [7:0] in3data = DSW2; +wire [7:0] inpdata = (ad[8:7] == 2'b11) ? in3data : (ad[8:7] == 2'b10) ? in2data : (ad[8:7] == 2'b01) ? in1data : in0data; +// databus selector +wire [7:0] romd = rom_Rce ? romdata : 8'h00; +wire [7:0] ramd = ram_Rce ? ramdata : 8'h00; +wire [7:0] vidd = vid_Rce ? viddata : 8'h00; +wire [7:0] inpd = inp_Rce ? inpdata : 8'h00; +wire [7:0] irqv = ( (~m1) & (~ie) ) ? intv : 8'h00; + +wire [7:0] idt = romd | ramd | irqv | vidd | inpd; + + +T80s z80( + .RESET_n(~RESET), + .CLK_n(CCLK), + .WAIT_n(1'b1), + .INT_n(1'b1), + .NMI_n(irq_n), + .BUSRQ_n(1'b1), + .DI(idt), + .M1_n(m1), + .MREQ_n(me), + .IORQ_n(ie), + .RD_n(rd), + .WR_n(wr), + .RFSH_n(rf), + .HALT_n(), + .BUSAK_n(), + .A(ad), + .DO(odt) + ); + +//-------------------------------------------------- +// VIDEO +//-------------------------------------------------- +wire [8:0] HP; +wire [8:0] VP; +wire PCLK; + +cmd_video video( + .VCLKx4(CLK), + .HPOS(HP+3), + .VPOS(VP+1), + .PCLK(PCLK), + .POUT({b,g,r}), + .CPUCLK(CCLK), + .CPUADDR(ad), + .CPUDI(odt), + .CPUDO(viddata), + .CPUME(mx), + .CPUWE(mw), + .CPUDT(vid_Rce) + ); + +cmd_hvgen hvgen( + .HPOS(HP), + .VPOS(VP), + .PCLK(PCLK), + .HBLK(hblank), + .VBLK(vblank), + .HSYN(hsync), + .VSYN(vsync) + ); + +//-------------------------------------------------- +// SOUND //Todo +//-------------------------------------------------- +cmd_sound cmd_sound( + .clock_12(CCLKx4), + .reset(RESET), + .sound_req(sonr), + .sound_code_in(odt), + .sound_timing(snd_Wce), + .audio_out(SND) + ); + +endmodule diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/cmd_video.v b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/cmd_video.v new file mode 100644 index 00000000..63e691a4 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/cmd_video.v @@ -0,0 +1,194 @@ +module cmd_video +( + input VCLKx4, // 24.976MHz + + input [8:0] HPOS, + input [8:0] VPOS, + output PCLK, + output reg [7:0] POUT, + + input CPUCLK, + input [15:0] CPUADDR, + input [7:0] CPUDI, + output [7:0] CPUDO, + input CPUME, + input CPUWE, + output CPUDT +); + +//----------------------------------------- +// Clock generators +//----------------------------------------- +reg VCLKx2; +always @( posedge VCLKx4 ) begin + VCLKx2 <= ~VCLKx2; +end + +reg VCLK; +always @( posedge VCLKx2 ) begin + VCLK <= ~VCLK; +end + +//----------------------------------------- +// BG scroll registers +//----------------------------------------- +reg [7:0] BGHSCR; +reg [7:0] BGVSCR; + +always @ ( posedge CPUCLK ) begin + if ( ( CPUADDR == 16'hA130 ) & CPUME & CPUWE ) begin + BGHSCR <= CPUDI-3; + end + if ( ( CPUADDR == 16'hA140 ) & CPUME & CPUWE ) begin + BGVSCR <= CPUDI; + end +end + + +//----------------------------------------- +// HV +//----------------------------------------- +wire [8:0] BGHPOS = HPOS + { 1'b0, BGHSCR }; +wire [8:0] BGVPOS = VPOS + { 1'b0, BGVSCR }; + +wire oHB = ( HPOS > 288 ) ? 1 : 0; +wire oVB = ( VPOS > 224 ) ? 1 : 0; + + +//---------------------------------------- +// VideoRAM Scanner +//---------------------------------------- +wire BF = ( HPOS >= 224 ); +wire [8:0] HP = BF ? HPOS : BGHPOS; +wire [8:0] VP = ( BF ? VPOS : BGVPOS ) + 9'h0F; + +wire [10:0] SPRAADRS; +wire [3:0] ARAMADRS; + +reg [10:0] VRAMADRS; +always @ ( HPOS ) begin + VRAMADRS <= oHB ? + SPRAADRS : + BF ? { 1'b0, VP[7:3], 2'b00, HP[5:3] } : { 1'b1, VP[7:3], HP[7:3] }; +end + +wire [7:0] CHRC; +wire [7:0] ATTR; +wire [7:0] ARDT; + +wire [7:0] V0DO, V1DO; + +wire CEV0 = ( ( CPUADDR[15:12] == 4'b1000 ) & (~CPUADDR[11]) ) & CPUME; +wire CEV1 = ( ( CPUADDR[15:12] == 4'b1000 ) & CPUADDR[11] ) & CPUME; +wire CEAT = ( CPUADDR[15:4] == 12'b1010_0000_0000 ) & CPUME; + +wire [7:0] DTV0 = CEV0 ? V0DO : 8'h00; +wire [7:0] DTV1 = CEV1 ? V1DO : 8'h00; + +assign CPUDO = DTV0 | DTV1; +assign CPUDT = ( ~CPUWE ) & ( CEV0 | CEV1 ); + +GDPRAM #(11,8) vram0( VCLKx4, VRAMADRS, CHRC, CPUCLK, CPUADDR[10:0], ( CPUWE & CEV0 ), CPUDI, V0DO ); + +GDPRAM #(11,8) vram1( VCLKx4, VRAMADRS, ATTR, CPUCLK, CPUADDR[10:0], ( CPUWE & CEV1 ), CPUDI, V1DO ); + +GDPRAM #(4,8) aram0( VCLKx4, ARAMADRS, ARDT, CPUCLK, CPUADDR[3:0], ( CPUWE & CEAT ), CPUDI ); + +wire BGF = ATTR[5]; + + +//---------------------------------------- +// BG/Sprite chip data reader +//---------------------------------------- +wire BGFX = ATTR[6]; +wire [2:0] BGFY = { ATTR[7], ATTR[7], ATTR[7] }; + +wire [12:0] SPCHRADR;//Todo +wire [12:0] CHRA = oHB ? SPCHRADR : {CHRC, ( HP[2] ^ BGFX ), ( VP[2:0] ^ BGFY ) };//Todo + +wire [7:0] CHRO; +cmd_chr_rom chrrom( + .clk(VCLKx4), + .addr(CHRA), + .data(CHRO) +); + +//---------------------------------------- +// Rader-dot chip ROM +//---------------------------------------- +wire [7:0] DROMAD; +wire [7:0] DROMDT; +cmd_dot_rom dotrom( + .clk(VCLKx4), + .addr(DROMAD), + .data(DROMDT) + ); + +//---------------------------------------- +// BG/FG scanline generator +//---------------------------------------- +wire [5:0] BGPL = ATTR[5:0]; +reg [7:0] BGCOL; + +always @ ( posedge VCLK ) begin + case ( HP[1:0]^{2{BGFX}} ) + 2'b00: BGCOL <= { BGPL, CHRO[4], CHRO[0] }; + 2'b01: BGCOL <= { BGPL, CHRO[5], CHRO[1] }; + 2'b10: BGCOL <= { BGPL, CHRO[6], CHRO[2] }; + 2'b11: BGCOL <= { BGPL, CHRO[7], CHRO[3] }; + endcase +end + + +//---------------------------------------- +// Sprite Engine +//---------------------------------------- +wire [8:0] SPCOL; +cmd_sprite speng( + .VCLKx4(VCLKx4), + .HBLK(oHB), + .HPOS(HPOS), + .VPOS(VPOS), + .SPRAADRS(SPRAADRS), + .SPRADATA({ ATTR, CHRC }), + .ARAMADRS(ARAMADRS), + .ARAMDATA(ARDT), + .SPCHRADR(SPCHRADR), + .SPCHRDAT(CHRO), + .DROMAD(DROMAD), + .DROMDT(DROMDT), + .SPCOL(SPCOL) + ); + + +//---------------------------------------- +// Color mixer +//---------------------------------------- +wire bBGOPAQUE = ( ( BF | BGF ) & (~SPCOL[8]) ); +wire bSPTRANSP = ( SPCOL[1:0] == 2'b00 ); + +wire [7:0] OUTCOL = ( bBGOPAQUE | bSPTRANSP ) ? BGCOL : SPCOL[7:0]; +wire [3:0] CLUT; +cmd_col_rom colrom( + .clk(~VCLKx4), + .addr(OUTCOL), + .data(CLUT) + ); + +wire [4:0] PALA = SPCOL[8] ? SPCOL[4:0] : { 1'b0, CLUT }; +wire [7:0] PALO; + +cmd_pal_rom palrom( + .clk(VCLKx4), + .addr(PALA), + .data(PALO) + ); + +//---------------------------------------- +// Color output +//---------------------------------------- +always @ ( posedge PCLK ) POUT <= (oHB|oVB) ? 8'h0 : PALO; +assign PCLK = VCLK; + + +endmodule \ No newline at end of file diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/dpram.vhd b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..cda0f3cd --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/dpram.vhd @@ -0,0 +1,123 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY dpram IS + GENERIC + ( + init_file : string := ""; + numwords_a : natural := 0; -- not used any more + widthad_a : natural; + width_a : natural := 8; + outdata_reg_a : string := "UNREGISTERED"; + outdata_reg_b : string := "UNREGISTERED" + ); + PORT + ( + address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + clock_a : IN STD_LOGIC ; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + wren_a : IN STD_LOGIC := '1'; + wren_b : IN STD_LOGIC := '1'; + q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); +END dpram; + + +ARCHITECTURE SYN OF dpram IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + + COMPONENT altsyncram + GENERIC ( + address_reg_b : STRING; + clock_enable_input_a : STRING; + clock_enable_input_b : STRING; + clock_enable_output_a : STRING; + clock_enable_output_b : STRING; + indata_reg_b : STRING; + init_file : STRING; + intended_device_family : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + numwords_b : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_aclr_b : STRING; + outdata_reg_a : STRING; + outdata_reg_b : STRING; + power_up_uninitialized : STRING; + widthad_a : NATURAL; + widthad_b : NATURAL; + width_a : NATURAL; + width_b : NATURAL; + width_byteena_a : NATURAL; + width_byteena_b : NATURAL; + wrcontrol_wraddress_reg_b : STRING + ); + PORT ( + wren_a : IN STD_LOGIC ; + clock0 : IN STD_LOGIC ; + wren_b : IN STD_LOGIC ; + clock1 : IN STD_LOGIC ; + address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q_a <= sub_wire0(width_a-1 DOWNTO 0); + q_b <= sub_wire1(width_a-1 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + address_reg_b => "CLOCK1", + clock_enable_input_a => "BYPASS", + clock_enable_input_b => "BYPASS", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", + init_file => init_file, + intended_device_family => "Cyclone III", + lpm_type => "altsyncram", + numwords_a => 2**widthad_a, + numwords_b => 2**widthad_a, + operation_mode => "BIDIR_DUAL_PORT", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => outdata_reg_a, + outdata_reg_b => outdata_reg_b, + power_up_uninitialized => "FALSE", + widthad_a => widthad_a, + widthad_b => widthad_a, + width_a => width_a, + width_b => width_a, + width_byteena_a => 1, + width_byteena_b => 1, + wrcontrol_wraddress_reg_b => "CLOCK1" + ) + PORT MAP ( + wren_a => wren_a, + clock0 => clock_a, + wren_b => wren_b, + clock1 => clock_b, + address_a => address_a, + address_b => address_b, + data_a => data_a, + data_b => data_b, + q_a => sub_wire0, + q_b => sub_wire1 + ); + +END SYN; diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/gen_ram.vhd b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/gen_ram.vhd new file mode 100644 index 00000000..f1a95608 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/gen_ram.vhd @@ -0,0 +1,84 @@ +-- ----------------------------------------------------------------------- +-- +-- Syntiac's generic VHDL support files. +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- +-- Modified April 2016 by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +-- Remove address register when writing +-- +-- ----------------------------------------------------------------------- +-- +-- gen_rwram.vhd +-- +-- ----------------------------------------------------------------------- +-- +-- generic ram. +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +entity gen_ram is + generic ( + dWidth : integer := 8; + aWidth : integer := 10 + ); + port ( + clk : in std_logic; + we : in std_logic; + addr : in std_logic_vector((aWidth-1) downto 0); + d : in std_logic_vector((dWidth-1) downto 0); + q : out std_logic_vector((dWidth-1) downto 0) + ); +end entity; + +-- ----------------------------------------------------------------------- + +architecture rtl of gen_ram is + subtype addressRange is integer range 0 to ((2**aWidth)-1); + type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0); + signal ram: ramDef; + + signal rAddrReg : std_logic_vector((aWidth-1) downto 0); + signal qReg : std_logic_vector((dWidth-1) downto 0); +begin +-- ----------------------------------------------------------------------- +-- Signals to entity interface +-- ----------------------------------------------------------------------- +-- q <= qReg; + +-- ----------------------------------------------------------------------- +-- Memory write +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if we = '1' then + ram(to_integer(unsigned(addr))) <= d; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Memory read +-- ----------------------------------------------------------------------- +process(clk) + begin + if rising_edge(clk) then +-- qReg <= ram(to_integer(unsigned(rAddrReg))); +-- rAddrReg <= addr; +---- qReg <= ram(to_integer(unsigned(addr))); + q <= ram(to_integer(unsigned(addr))); + end if; + end process; +--q <= ram(to_integer(unsigned(addr))); +end architecture; + diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/pll.qip b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/pll.qip new file mode 100644 index 00000000..afd958be --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/pll.v b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/pll.v new file mode 100644 index 00000000..70025276 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/pll.v @@ -0,0 +1,309 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.4 Build 182 03/12/2014 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2014 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + inclk0, + c0, + locked); + + input inclk0; + output c0; + output locked; + + wire [4:0] sub_wire0; + wire sub_wire2; + wire [0:0] sub_wire5 = 1'h0; + wire [0:0] sub_wire1 = sub_wire0[0:0]; + wire c0 = sub_wire1; + wire locked = sub_wire2; + wire sub_wire3 = inclk0; + wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; + + altpll altpll_component ( + .inclk (sub_wire4), + .clk (sub_wire0), + .locked (sub_wire2), + .activeclock (), + .areset (1'b0), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 78, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 71, + altpll_component.clk0_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_UNUSED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "78" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.576923" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "71" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.57600000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "78" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "71" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/rams.v b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/rams.v new file mode 100644 index 00000000..4d579578 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/rams.v @@ -0,0 +1,64 @@ + + + +module GSPRAM #(parameter AW,parameter DW) +( + input CL, + input [(AW-1):0] AD, + input WE, + input [(DW-1):0] DI, + output reg [(DW-1):0] DO +); + +reg [(DW-1):0] core[0:((2**AW)-1)]; + +always @(posedge CL) begin + DO <= core[AD]; + if (WE) core[AD] <= DI; +end + +endmodule + + +module GDPRAM #(parameter AW,parameter DW) +( + input CL0, + input [(AW-1):0] AD0, + output reg [(DW-1):0] DO0, + + input CL1, + input [(AW-1):0] AD1, + input WE1, + input [(DW-1):0] DI1, + output reg [(DW-1):0] DO1 +); + +reg [(DW-1):0] core[0:((2**AW)-1)]; + +always @(posedge CL0) DO0 <= core[AD0]; +always @(posedge CL1) begin DO1 <= core[AD1]; if (WE1) core[AD1] <= DI1; end + +endmodule + +/* +module GLINEBUF #(parameter AW,parameter DW) +( + input CL0, + input [(AW-1):0] AD0, + input WE0, + output reg [(DW-1):0] DO0, + + input CL1, + input [(AW-1):0] AD1, + input WE1, + input [(DW-1):0] DI1 +); + +reg [(DW-1):0] core[0:((2**AW)-1)]; + +always @(posedge CL0) begin DO0 <= core[AD0]; if (WE0) core[AD0] <= 0; end +always @(posedge CL1) if (WE1) core[AD1] <= DI1; + +endmodule*/ + + diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/cmd_chr_rom.vhd b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/cmd_chr_rom.vhd new file mode 100644 index 00000000..eb8bbb01 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/cmd_chr_rom.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity cmd_chr_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of cmd_chr_rom is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"CC",X"EE",X"22",X"22",X"22",X"EE",X"CC",X"00",X"77",X"FF",X"88",X"88",X"88",X"FF",X"77", + X"00",X"00",X"00",X"44",X"EE",X"EE",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"00",X"00", + X"00",X"44",X"66",X"22",X"22",X"AA",X"EE",X"CC",X"00",X"CC",X"EE",X"FF",X"FF",X"BB",X"99",X"88", + X"00",X"22",X"22",X"22",X"AA",X"EE",X"66",X"22",X"00",X"44",X"CC",X"99",X"99",X"99",X"FF",X"66", + X"00",X"00",X"88",X"CC",X"66",X"EE",X"EE",X"00",X"00",X"33",X"33",X"22",X"22",X"FF",X"FF",X"22", + X"00",X"EE",X"EE",X"AA",X"AA",X"AA",X"AA",X"00",X"00",X"44",X"CC",X"88",X"88",X"88",X"FF",X"77", + X"00",X"88",X"CC",X"66",X"22",X"22",X"22",X"00",X"00",X"77",X"FF",X"99",X"99",X"99",X"FF",X"66", + X"00",X"66",X"66",X"22",X"22",X"AA",X"EE",X"66",X"00",X"00",X"00",X"EE",X"FF",X"11",X"00",X"00", + X"00",X"CC",X"EE",X"22",X"22",X"22",X"EE",X"CC",X"00",X"66",X"FF",X"99",X"99",X"99",X"FF",X"66", + X"00",X"CC",X"EE",X"22",X"22",X"22",X"EE",X"CC",X"00",X"00",X"99",X"99",X"99",X"DD",X"77",X"33", + X"00",X"88",X"CC",X"66",X"22",X"66",X"CC",X"88",X"00",X"FF",X"FF",X"22",X"22",X"22",X"FF",X"FF", + X"00",X"EE",X"EE",X"22",X"22",X"22",X"EE",X"CC",X"00",X"FF",X"FF",X"99",X"99",X"99",X"FF",X"66", + X"00",X"88",X"CC",X"66",X"22",X"22",X"66",X"44",X"00",X"33",X"77",X"CC",X"88",X"88",X"CC",X"44", + X"00",X"EE",X"EE",X"22",X"22",X"66",X"CC",X"88",X"00",X"FF",X"FF",X"88",X"88",X"CC",X"77",X"33", + X"00",X"EE",X"EE",X"22",X"22",X"22",X"22",X"22",X"00",X"FF",X"FF",X"99",X"99",X"99",X"99",X"88", + X"00",X"EE",X"EE",X"22",X"22",X"22",X"22",X"22",X"00",X"FF",X"FF",X"11",X"11",X"11",X"11",X"00", + X"00",X"88",X"CC",X"66",X"22",X"22",X"22",X"22",X"00",X"33",X"77",X"CC",X"88",X"99",X"FF",X"FF", + X"00",X"EE",X"EE",X"00",X"00",X"00",X"EE",X"EE",X"00",X"FF",X"FF",X"11",X"11",X"11",X"FF",X"FF", + X"00",X"00",X"00",X"22",X"EE",X"EE",X"22",X"00",X"00",X"00",X"00",X"88",X"FF",X"FF",X"88",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"EE",X"EE",X"00",X"44",X"CC",X"88",X"88",X"88",X"FF",X"77", + X"00",X"EE",X"EE",X"00",X"88",X"CC",X"66",X"22",X"00",X"FF",X"FF",X"33",X"77",X"EE",X"CC",X"88", + X"00",X"EE",X"EE",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"88",X"88",X"88",X"88",X"88", + X"00",X"EE",X"EE",X"CC",X"88",X"CC",X"EE",X"EE",X"00",X"FF",X"FF",X"11",X"33",X"11",X"FF",X"FF", + X"00",X"EE",X"EE",X"CC",X"88",X"00",X"EE",X"EE",X"00",X"FF",X"FF",X"11",X"33",X"77",X"FF",X"FF", + X"00",X"CC",X"EE",X"22",X"22",X"22",X"EE",X"CC",X"00",X"77",X"FF",X"88",X"88",X"88",X"FF",X"77", + X"00",X"EE",X"EE",X"22",X"22",X"22",X"EE",X"CC",X"00",X"FF",X"FF",X"22",X"22",X"22",X"33",X"11", + X"00",X"CC",X"EE",X"22",X"22",X"22",X"EE",X"CC",X"00",X"77",X"FF",X"88",X"AA",X"EE",X"77",X"BB", + X"00",X"EE",X"EE",X"22",X"22",X"22",X"EE",X"CC",X"00",X"FF",X"FF",X"22",X"66",X"FF",X"DD",X"99", + X"00",X"CC",X"EE",X"22",X"22",X"22",X"66",X"44",X"00",X"44",X"DD",X"99",X"99",X"99",X"FF",X"66", + X"00",X"22",X"22",X"EE",X"EE",X"22",X"22",X"00",X"00",X"00",X"00",X"FF",X"FF",X"00",X"00",X"00", + X"00",X"EE",X"EE",X"00",X"00",X"00",X"EE",X"EE",X"00",X"77",X"FF",X"88",X"88",X"88",X"FF",X"77", + X"00",X"EE",X"EE",X"00",X"00",X"00",X"EE",X"EE",X"00",X"11",X"33",X"77",X"EE",X"77",X"33",X"11", + X"00",X"EE",X"EE",X"00",X"88",X"00",X"EE",X"EE",X"00",X"33",X"FF",X"77",X"33",X"77",X"FF",X"33", + X"00",X"66",X"EE",X"CC",X"88",X"CC",X"EE",X"66",X"00",X"CC",X"EE",X"77",X"33",X"77",X"EE",X"CC", + X"00",X"66",X"EE",X"00",X"00",X"EE",X"66",X"00",X"00",X"00",X"11",X"FF",X"FF",X"11",X"00",X"00", + X"00",X"22",X"22",X"22",X"AA",X"EE",X"EE",X"66",X"00",X"CC",X"EE",X"FF",X"BB",X"99",X"88",X"88", + X"CC",X"22",X"99",X"55",X"55",X"11",X"22",X"CC",X"33",X"44",X"99",X"AA",X"AA",X"88",X"44",X"33", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"FF",X"33",X"FF",X"CC",X"00",X"00",X"00",X"00",X"CC",X"CC",X"FF",X"FF",X"EE",X"00",X"00",X"00", + X"BB",X"BB",X"BB",X"00",X"00",X"00",X"CC",X"FF",X"00",X"FF",X"FF",X"00",X"CC",X"FF",X"FF",X"33", + X"BB",X"33",X"00",X"00",X"EE",X"FF",X"33",X"33",X"DD",X"CC",X"00",X"00",X"77",X"FF",X"CC",X"CC", + X"33",X"00",X"00",X"EE",X"FF",X"FF",X"BB",X"BB",X"77",X"00",X"00",X"77",X"FF",X"FF",X"DD",X"DD", + X"00",X"00",X"EE",X"FF",X"FF",X"BB",X"BB",X"BB",X"00",X"00",X"CC",X"DD",X"DD",X"DD",X"FF",X"FF", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"D0",X"A0",X"50",X"A0",X"40",X"C0",X"E0",X"E0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"B0",X"70",X"B0",X"10",X"80",X"10",X"80",X"10",X"80",X"50",X"A0", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"C0",X"C0",X"A0",X"C0",X"A0",X"40",X"80", + X"70",X"B0",X"F0",X"70",X"F0",X"F0",X"D0",X"E0",X"F0",X"F0",X"E0",X"F0",X"D0",X"F0",X"F0",X"F0", + X"00",X"00",X"80",X"80",X"40",X"80",X"40",X"A0",X"C0",X"F0",X"F0",X"E0",X"F0",X"F0",X"F0",X"F0", + X"00",X"40",X"80",X"60",X"E0",X"D0",X"E0",X"D0",X"A0",X"50",X"A0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10", + X"10",X"30",X"10",X"20",X"10",X"30",X"10",X"30",X"10",X"00",X"10",X"00",X"10",X"10",X"10",X"10", + X"10",X"20",X"10",X"30",X"10",X"30",X"10",X"20",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"10",X"00",X"10",X"00",X"30",X"20",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"D0",X"E0",X"50",X"A0",X"40",X"80",X"80",X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"E0", + X"70",X"F0",X"50",X"A0",X"00",X"00",X"00",X"00",X"10",X"00",X"10",X"00",X"00",X"00",X"00",X"00", + X"E0",X"D0",X"A0",X"D0",X"A0",X"40",X"80",X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"A0",X"C0", + X"48",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"4B",X"4B",X"5A",X"78",X"84",X"0C",X"00",X"00", + X"78",X"78",X"D2",X"D2",X"96",X"96",X"E1",X"E1",X"C3",X"78",X"78",X"5A",X"4B",X"4B",X"D2",X"E1", + X"B4",X"B4",X"96",X"96",X"D2",X"F0",X"5A",X"5A",X"96",X"96",X"C3",X"78",X"3C",X"69",X"69",X"4B", + X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"48",X"00",X"00",X"C0",X"C0",X"B4",X"96",X"78",X"B4", + X"0F",X"FF",X"FF",X"EE",X"EE",X"EE",X"CC",X"44",X"0F",X"77",X"33",X"33",X"11",X"11",X"00",X"00", + X"7B",X"F3",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"4B",X"4B",X"5A",X"78",X"B7",X"3F",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"F3",X"7B",X"FF",X"FF",X"F3",X"F3",X"B4",X"96",X"78",X"B4", + X"0F",X"FF",X"FF",X"FE",X"FE",X"FE",X"FC",X"F4",X"0F",X"F7",X"F3",X"F3",X"F1",X"F0",X"F0",X"F0", + X"00",X"22",X"44",X"88",X"00",X"88",X"44",X"22",X"00",X"88",X"44",X"22",X"11",X"22",X"44",X"88", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"01",X"01",X"01",X"00", + X"0C",X"0E",X"0F",X"87",X"87",X"0F",X"0E",X"0C",X"61",X"41",X"C2",X"87",X"87",X"C2",X"41",X"A1", + X"0F",X"0F",X"0F",X"0E",X"0E",X"0C",X"08",X"00",X"1E",X"0D",X"0B",X"07",X"0F",X"0F",X"0F",X"0E", + X"0F",X"0F",X"0F",X"0F",X"0E",X"87",X"C3",X"61",X"C3",X"C3",X"C3",X"61",X"70",X"70",X"D0",X"80", + X"00",X"08",X"0C",X"0E",X"0E",X"0F",X"0F",X"87",X"0E",X"0F",X"0F",X"07",X"0B",X"0D",X"1E",X"10", + X"43",X"C3",X"86",X"0F",X"0F",X"0F",X"0F",X"00",X"80",X"D0",X"70",X"70",X"61",X"C3",X"C3",X"C2", + X"0C",X"0E",X"0F",X"87",X"87",X"0F",X"0E",X"0C",X"A1",X"41",X"C2",X"87",X"87",X"C2",X"41",X"61", + X"86",X"86",X"0C",X"0A",X"84",X"C0",X"84",X"80",X"42",X"86",X"94",X"96",X"1E",X"3C",X"48",X"18", + X"08",X"0C",X"00",X"E0",X"80",X"48",X"2C",X"00",X"E0",X"30",X"12",X"21",X"21",X"21",X"52",X"52", + X"08",X"2C",X"78",X"A4",X"0C",X"48",X"A4",X"B4",X"52",X"43",X"21",X"29",X"A5",X"90",X"30",X"E0", + X"00",X"08",X"08",X"00",X"08",X"86",X"E0",X"87",X"09",X"1C",X"3C",X"29",X"A5",X"94",X"86",X"42", + X"3F",X"1F",X"0F",X"87",X"87",X"0F",X"1F",X"3F",X"E9",X"EB",X"D3",X"87",X"87",X"D3",X"EB",X"E5", + X"0F",X"0F",X"0F",X"1F",X"1F",X"3F",X"7F",X"FF",X"1E",X"2F",X"4F",X"8F",X"0F",X"0F",X"0F",X"1F", + X"0F",X"0F",X"0F",X"0F",X"1F",X"87",X"C3",X"E9",X"C3",X"C3",X"C3",X"E9",X"F8",X"F8",X"F2",X"F7", + X"FF",X"7F",X"3F",X"1F",X"1F",X"0F",X"0F",X"87",X"1F",X"0F",X"0F",X"8F",X"4F",X"2F",X"1E",X"FE", + X"CB",X"C3",X"97",X"0F",X"0F",X"0F",X"0F",X"FF",X"F7",X"F2",X"F8",X"F8",X"E9",X"C3",X"C3",X"D3", + X"3F",X"1F",X"0F",X"87",X"87",X"0F",X"1F",X"3F",X"E5",X"EB",X"D3",X"87",X"87",X"D3",X"EB",X"E9", + X"97",X"97",X"3F",X"5F",X"B7",X"F3",X"B7",X"F7",X"DB",X"97",X"B6",X"96",X"1E",X"3C",X"7B",X"79", + X"7F",X"3F",X"FF",X"F1",X"F7",X"7B",X"3D",X"FF",X"F1",X"FC",X"DE",X"ED",X"ED",X"ED",X"DA",X"DA", + X"7F",X"3D",X"78",X"B5",X"3F",X"7B",X"B5",X"B4",X"DA",X"CB",X"ED",X"6D",X"A5",X"F6",X"FC",X"F1", + X"FF",X"7F",X"7F",X"FF",X"7F",X"97",X"F1",X"87",X"6F",X"3E",X"3C",X"6D",X"A5",X"B6",X"97",X"DB", + X"CC",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"99",X"FF",X"CC",X"88",X"00",X"00",X"00",X"00", + X"8F",X"8F",X"0F",X"8E",X"0E",X"0C",X"08",X"00",X"FF",X"8F",X"0F",X"FF",X"8F",X"8F",X"0F",X"0E", + X"6F",X"CF",X"6F",X"EF",X"6F",X"CF",X"6F",X"67",X"0F",X"0F",X"0F",X"07",X"07",X"03",X"01",X"00", + X"00",X"08",X"0C",X"8E",X"8E",X"0F",X"0F",X"8F",X"0E",X"0F",X"7F",X"FF",X"8F",X"7F",X"0F",X"8F", + X"67",X"CF",X"6F",X"EF",X"6F",X"CF",X"6F",X"EF",X"00",X"01",X"03",X"07",X"07",X"0F",X"0F",X"0F", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"CC",X"00",X"00",X"00",X"00",X"88",X"CC",X"FF",X"99", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0E",X"2E",X"26",X"00",X"00",X"00",X"00",X"00", + X"CE",X"6F",X"7F",X"7F",X"7F",X"2E",X"2E",X"0F",X"1F",X"2F",X"2F",X"0F",X"07",X"07",X"4F",X"0C", + X"0E",X"0C",X"88",X"CC",X"6E",X"2E",X"4C",X"8C",X"0D",X"4D",X"07",X"27",X"1F",X"0F",X"0F",X"0F", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"00",X"00",X"00",X"08",X"0C",X"8F",X"AE",X"8E", + X"FC",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F9",X"FF",X"FC",X"F8",X"F0",X"F0",X"F0",X"F0", + X"8F",X"8F",X"0F",X"9E",X"1E",X"3C",X"78",X"F0",X"FF",X"8F",X"0F",X"FF",X"8F",X"8F",X"0F",X"1E", + X"6F",X"CF",X"6F",X"EF",X"6F",X"CF",X"6F",X"E7",X"0F",X"0F",X"0F",X"87",X"87",X"C3",X"E1",X"F0", + X"F0",X"78",X"3C",X"9E",X"9E",X"0F",X"0F",X"8F",X"1E",X"0F",X"7F",X"FF",X"8F",X"7F",X"0F",X"8F", + X"E7",X"CF",X"6F",X"EF",X"6F",X"CF",X"6F",X"EF",X"F0",X"E1",X"C3",X"87",X"87",X"0F",X"0F",X"0F", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"FC",X"F0",X"F0",X"F0",X"F0",X"F8",X"FC",X"FF",X"F9", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"1E",X"3E",X"B6",X"F0",X"F0",X"F0",X"F0",X"F0", + X"DE",X"6F",X"7F",X"7F",X"7F",X"3E",X"3E",X"0F",X"1F",X"2F",X"2F",X"0F",X"87",X"87",X"4F",X"3C", + X"1E",X"3C",X"F8",X"FC",X"7E",X"3E",X"7C",X"BC",X"2D",X"6D",X"87",X"A7",X"1F",X"0F",X"0F",X"0F", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"B4",X"F0",X"F0",X"F0",X"78",X"3C",X"8F",X"BE",X"9E", + X"F0",X"B4",X"1E",X"1E",X"5A",X"5A",X"F0",X"F0",X"F0",X"D2",X"96",X"B4",X"A5",X"87",X"C3",X"F0", + X"F0",X"1E",X"F0",X"1E",X"1E",X"F0",X"1E",X"1E",X"87",X"87",X"F0",X"C3",X"87",X"B4",X"87",X"C3", + X"1E",X"D2",X"1E",X"3C",X"F0",X"1E",X"1E",X"3C",X"87",X"B4",X"87",X"C3",X"F0",X"87",X"87",X"E1", + X"F0",X"1E",X"1E",X"5A",X"1E",X"96",X"F0",X"3C",X"F0",X"87",X"87",X"B4",X"87",X"87",X"F0",X"C3", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"FF",X"33",X"3D",X"A5",X"42",X"86",X"16",X"92",X"FF",X"FC",X"8B",X"9A",X"A4",X"96",X"06",X"14", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FB",X"F3",X"FF",X"FF",X"FF",X"3F",X"1F",X"69",X"2D",X"0F", + X"82",X"06",X"96",X"52",X"85",X"1D",X"F3",X"FF",X"94",X"86",X"16",X"24",X"DA",X"CB",X"CC",X"FF", + X"F3",X"FB",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"0F",X"0F",X"0F",X"1F",X"3F",X"FF",X"FF",X"FF", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"F0",X"0F",X"0F",X"0F",X"0F",X"0F",X"50",X"0F",X"20",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + X"00",X"00",X"00",X"0C",X"0C",X"0E",X"0E",X"0E",X"00",X"0C",X"0F",X"0F",X"0F",X"03",X"01",X"01", + X"1E",X"0F",X"0F",X"87",X"E0",X"C0",X"C0",X"C0",X"0F",X"0F",X"0F",X"1E",X"1E",X"1E",X"1E",X"1E", + X"0F",X"0F",X"F0",X"50",X"F0",X"F0",X"F0",X"F0",X"0F",X"00",X"00",X"10",X"20",X"10",X"20",X"50", + X"00",X"0C",X"0E",X"0E",X"0E",X"00",X"00",X"00",X"0F",X"0F",X"0F",X"0F",X"0F",X"80",X"00",X"80", + X"87",X"0F",X"0F",X"0F",X"0F",X"E0",X"D0",X"E0",X"F0",X"0F",X"0F",X"0F",X"0F",X"F0",X"F0",X"0F", + X"0F",X"0F",X"0F",X"0F",X"F0",X"70",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"18",X"0F",X"0F",X"0F", + X"0E",X"0E",X"0E",X"00",X"00",X"00",X"00",X"00",X"0F",X"0F",X"0F",X"00",X"80",X"80",X"80",X"0C", + X"0F",X"0F",X"0F",X"F0",X"F0",X"3C",X"0F",X"0F",X"0F",X"0F",X"0F",X"3C",X"0F",X"0F",X"87",X"E1", + X"E1",X"0F",X"0F",X"0F",X"87",X"61",X"F0",X"F0",X"10",X"01",X"01",X"01",X"00",X"00",X"10",X"18", + X"0E",X"00",X"00",X"00",X"00",X"00",X"08",X"0E",X"0F",X"00",X"00",X"00",X"00",X"0E",X"0F",X"0F", + X"0F",X"00",X"00",X"00",X"0F",X"0F",X"0F",X"0F",X"0F",X"00",X"00",X"0F",X"0F",X"0F",X"0F",X"F0", + X"00",X"00",X"0F",X"0F",X"0F",X"0F",X"70",X"F0",X"08",X"0F",X"0F",X"0F",X"0F",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"0C",X"0E",X"0E",X"80",X"00",X"00",X"0C",X"0F",X"0F",X"0F",X"0F", + X"F0",X"2C",X"0F",X"0F",X"07",X"0F",X"0F",X"0F",X"0F",X"0F",X"07",X"01",X"00",X"0F",X"0F",X"0F", + X"07",X"01",X"00",X"00",X"0F",X"0F",X"0F",X"0F",X"00",X"00",X"00",X"08",X"0F",X"0F",X"0F",X"0F", + X"00",X"00",X"08",X"0E",X"0E",X"0E",X"0E",X"00",X"C0",X"0E",X"0F",X"0F",X"0F",X"0F",X"0F",X"C0", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"F0",X"0F",X"0F",X"0F",X"F0",X"0F",X"0F",X"0F",X"3C", + X"0F",X"0F",X"10",X"00",X"01",X"0F",X"0F",X"0F",X"0F",X"00",X"00",X"00",X"00",X"01",X"01",X"01", + X"0E",X"0C",X"0C",X"08",X"80",X"00",X"00",X"00",X"C3",X"0F",X"0F",X"0F",X"0F",X"78",X"00",X"80", + X"F0",X"F0",X"0F",X"0F",X"0F",X"0F",X"E0",X"F0",X"70",X"3C",X"0F",X"0F",X"0F",X"87",X"F0",X"0F", + X"1E",X"0F",X"0F",X"0F",X"03",X"10",X"0F",X"0F",X"07",X"03",X"03",X"00",X"08",X"0F",X"0F",X"0F", + X"0C",X"0C",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0F",X"C3",X"C3",X"E1",X"E1",X"E1",X"E1",X"E1", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"70",X"F0",X"30",X"B0",X"50",X"B0",X"70",X"B0", + X"18",X"08",X"00",X"00",X"10",X"00",X"18",X"28",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"07", + X"0C",X"00",X"00",X"00",X"80",X"80",X"80",X"08",X"0F",X"0F",X"0C",X"F0",X"78",X"1E",X"0F",X"0F", + X"C3",X"C3",X"C3",X"3C",X"0F",X"0F",X"0F",X"87",X"B0",X"50",X"F0",X"0F",X"0F",X"0F",X"0F",X"F0", + X"0F",X"03",X"00",X"03",X"0F",X"0F",X"0F",X"1E",X"00",X"00",X"00",X"00",X"01",X"03",X"07",X"07", + X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0C",X"03",X"01",X"01",X"C1",X"C1",X"C3",X"0F",X"0F", + X"00",X"00",X"70",X"F0",X"F0",X"70",X"F0",X"43",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"50", + X"00",X"00",X"08",X"08",X"0C",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"07",X"07",X"07",X"03",X"01", + X"00",X"00",X"00",X"00",X"08",X"0C",X"0C",X"0E",X"00",X"08",X"0E",X"0F",X"0F",X"0F",X"07",X"03", + X"0E",X"0F",X"0F",X"0F",X"07",X"01",X"00",X"00",X"0F",X"0F",X"0F",X"0F",X"00",X"00",X"00",X"00", + X"07",X"0F",X"0F",X"0F",X"0E",X"08",X"08",X"00",X"00",X"01",X"03",X"07",X"07",X"0F",X"0F",X"0F", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"00",X"00",X"00",X"13",X"13",X"1F",X"1F",X"1F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"07", + X"00",X"80",X"84",X"0C",X"0C",X"0C",X"0C",X"C0",X"30",X"BC",X"9E",X"8F",X"BC",X"BC",X"AD",X"8F", + X"1F",X"0F",X"0F",X"07",X"07",X"01",X"00",X"00",X"07",X"01",X"00",X"00",X"00",X"00",X"00",X"00", + X"C0",X"80",X"00",X"00",X"CC",X"EE",X"EE",X"00",X"8F",X"AD",X"2D",X"0C",X"0F",X"0F",X"07",X"00", + X"00",X"00",X"00",X"13",X"13",X"1F",X"1F",X"1F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"07", + X"00",X"80",X"84",X"0C",X"0C",X"0C",X"0C",X"C0",X"30",X"BC",X"9E",X"8F",X"BC",X"BC",X"AD",X"8F", + X"1F",X"0F",X"4F",X"EF",X"EF",X"6F",X"0F",X"06",X"07",X"03",X"00",X"00",X"00",X"00",X"00",X"00", + X"C0",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"8F",X"AD",X"2D",X"08",X"08",X"00",X"00",X"00", + X"00",X"00",X"01",X"07",X"07",X"0F",X"0F",X"1F",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"07", + X"00",X"EE",X"EE",X"CC",X"00",X"00",X"80",X"84",X"00",X"07",X"0F",X"0F",X"0C",X"3C",X"BC",X"9E", + X"1F",X"1F",X"1F",X"13",X"13",X"00",X"00",X"00",X"07",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"0C",X"0C",X"0C",X"0C",X"C0",X"C0",X"80",X"00",X"8F",X"BC",X"BC",X"AD",X"8F",X"8F",X"AD",X"21", + X"06",X"0F",X"6F",X"EF",X"EF",X"4F",X"0F",X"1F",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"07", + X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"84",X"00",X"00",X"00",X"08",X"08",X"3C",X"BC",X"9E", + X"1F",X"1F",X"1F",X"13",X"13",X"00",X"00",X"00",X"07",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"0C",X"0C",X"0C",X"0C",X"C0",X"C0",X"80",X"00",X"8F",X"BC",X"BC",X"AD",X"8F",X"8F",X"AD",X"21", + X"00",X"00",X"0F",X"8F",X"8F",X"87",X"87",X"0F",X"00",X"00",X"00",X"11",X"10",X"30",X"30",X"10", + X"00",X"00",X"00",X"C0",X"E0",X"69",X"0F",X"C3",X"00",X"00",X"00",X"0B",X"2F",X"6F",X"6F",X"6F", + X"0F",X"0F",X"0F",X"97",X"B7",X"37",X"03",X"00",X"01",X"34",X"34",X"34",X"34",X"00",X"00",X"00", + X"C3",X"87",X"3C",X"3C",X"A4",X"84",X"00",X"00",X"6F",X"6F",X"6F",X"6F",X"2F",X"0F",X"08",X"00", + X"CF",X"CF",X"4F",X"87",X"87",X"87",X"87",X"87",X"00",X"07",X"03",X"21",X"30",X"30",X"10",X"00", + X"00",X"00",X"00",X"00",X"00",X"84",X"A4",X"3C",X"00",X"08",X"0C",X"0E",X"0E",X"0F",X"0F",X"2F", + X"87",X"C3",X"C3",X"83",X"67",X"66",X"00",X"00",X"07",X"34",X"34",X"10",X"00",X"00",X"00",X"00", + X"3C",X"87",X"C3",X"C3",X"0F",X"69",X"E0",X"C0",X"6F",X"0F",X"EF",X"EF",X"EF",X"EF",X"67",X"01", + X"E1",X"69",X"C3",X"87",X"87",X"0F",X"EF",X"CF",X"03",X"01",X"07",X"34",X"30",X"30",X"30",X"31", + X"00",X"00",X"00",X"00",X"00",X"84",X"A4",X"3C",X"00",X"00",X"08",X"0C",X"0E",X"0F",X"0F",X"2F", + X"87",X"07",X"07",X"03",X"00",X"00",X"00",X"00",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"3C",X"87",X"C3",X"C3",X"07",X"69",X"E0",X"C0",X"6F",X"0F",X"EF",X"EF",X"EF",X"EF",X"67",X"01", + X"0C",X"86",X"F0",X"E1",X"E1",X"C3",X"C3",X"87",X"01",X"10",X"10",X"00",X"00",X"07",X"34",X"30", + X"00",X"00",X"00",X"00",X"00",X"84",X"A4",X"3C",X"00",X"00",X"08",X"0C",X"0E",X"0F",X"0F",X"2F", + X"87",X"C3",X"87",X"0E",X"0C",X"CC",X"88",X"00",X"30",X"10",X"10",X"00",X"11",X"11",X"00",X"00", + X"3C",X"87",X"C3",X"C3",X"0F",X"69",X"E0",X"C0",X"6F",X"0F",X"EF",X"EF",X"EF",X"EF",X"67",X"01", + X"00",X"88",X"CC",X"0C",X"0E",X"87",X"C3",X"87",X"00",X"00",X"11",X"11",X"00",X"10",X"10",X"30", + X"C0",X"E0",X"69",X"0F",X"C3",X"C3",X"87",X"3C",X"01",X"67",X"EF",X"EF",X"EF",X"EF",X"0F",X"6F", + X"87",X"C3",X"C3",X"E1",X"E1",X"F0",X"86",X"0C",X"30",X"34",X"07",X"00",X"00",X"10",X"10",X"01", + X"3C",X"A4",X"84",X"00",X"00",X"00",X"00",X"00",X"2F",X"0F",X"0F",X"0E",X"0C",X"08",X"00",X"00", + X"00",X"00",X"00",X"00",X"03",X"0F",X"0F",X"87",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10", + X"C0",X"E0",X"69",X"0F",X"C3",X"C3",X"87",X"3C",X"01",X"67",X"EF",X"EF",X"EF",X"EF",X"0F",X"6F", + X"CF",X"EF",X"0F",X"87",X"87",X"C3",X"69",X"E0",X"31",X"30",X"30",X"30",X"34",X"07",X"01",X"03", + X"3C",X"A4",X"84",X"00",X"00",X"00",X"00",X"00",X"2F",X"0F",X"0F",X"0E",X"0C",X"08",X"00",X"00", + X"00",X"00",X"66",X"67",X"83",X"C3",X"C3",X"87",X"00",X"00",X"00",X"00",X"10",X"30",X"34",X"07", + X"C0",X"E0",X"69",X"0F",X"C3",X"C3",X"87",X"3C",X"01",X"67",X"EF",X"EF",X"EF",X"EF",X"0F",X"6F", + X"87",X"87",X"87",X"87",X"C3",X"4F",X"CF",X"CF",X"00",X"10",X"30",X"30",X"21",X"03",X"07",X"00", + X"3C",X"A4",X"84",X"00",X"00",X"00",X"00",X"00",X"2F",X"0F",X"0F",X"0E",X"0E",X"0C",X"08",X"00", + X"66",X"EF",X"47",X"83",X"87",X"0F",X"0F",X"0F",X"00",X"07",X"07",X"03",X"43",X"70",X"70",X"61", + X"00",X"00",X"84",X"A4",X"3C",X"3C",X"87",X"C3",X"00",X"00",X"01",X"2B",X"6F",X"6F",X"0F",X"EF", + X"0F",X"0F",X"0F",X"0F",X"86",X"C0",X"0C",X"0E",X"21",X"21",X"21",X"10",X"10",X"10",X"01",X"01", + X"C3",X"0F",X"69",X"E0",X"C0",X"00",X"00",X"00",X"EF",X"EF",X"EF",X"67",X"01",X"00",X"00",X"00", + X"0E",X"0C",X"C0",X"86",X"0F",X"0F",X"0F",X"0F",X"01",X"01",X"10",X"10",X"10",X"21",X"21",X"21", + X"00",X"00",X"00",X"C0",X"E0",X"69",X"0F",X"C3",X"00",X"00",X"00",X"01",X"67",X"EF",X"EF",X"EF", + X"0F",X"0F",X"0F",X"87",X"87",X"47",X"EF",X"66",X"61",X"70",X"70",X"43",X"03",X"07",X"07",X"00", + X"C3",X"87",X"3C",X"3C",X"A4",X"84",X"00",X"00",X"EF",X"0F",X"6F",X"6F",X"2B",X"01",X"00",X"00", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"01",X"33",X"33",X"F7",X"A7",X"87",X"0F",X"0F",X"00",X"00",X"04",X"34",X"16",X"34",X"30",X"10", + X"00",X"00",X"00",X"C0",X"E0",X"69",X"0F",X"C3",X"08",X"0C",X"0C",X"0F",X"2F",X"6F",X"6F",X"6F", + X"0F",X"0F",X"87",X"87",X"87",X"83",X"00",X"00",X"10",X"10",X"10",X"30",X"34",X"16",X"34",X"04", + X"C3",X"87",X"3C",X"3C",X"A4",X"B7",X"FF",X"44",X"6F",X"6F",X"6F",X"6F",X"2F",X"0F",X"0F",X"00", + X"08",X"0E",X"E0",X"78",X"F0",X"C3",X"87",X"0F",X"03",X"34",X"07",X"43",X"70",X"70",X"70",X"30", + X"00",X"00",X"00",X"00",X"84",X"A4",X"3C",X"3C",X"00",X"00",X"00",X"00",X"01",X"2B",X"6F",X"0F", + X"0F",X"0F",X"0F",X"0F",X"03",X"01",X"00",X"00",X"30",X"01",X"01",X"00",X"00",X"00",X"00",X"00", + X"87",X"C3",X"C3",X"0F",X"69",X"E0",X"C0",X"00",X"6F",X"6F",X"6F",X"6F",X"2F",X"2F",X"0D",X"EE", + X"00",X"08",X"C0",X"C2",X"4B",X"0F",X"2F",X"6F",X"07",X"21",X"70",X"70",X"61",X"43",X"07",X"07", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"84",X"A4",X"3C",X"3C", + X"0F",X"6F",X"6F",X"6F",X"EF",X"67",X"01",X"00",X"07",X"07",X"07",X"07",X"47",X"67",X"22",X"66", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"87",X"C3",X"C3",X"0F",X"69",X"E0",X"C0",X"00", + X"00",X"08",X"C0",X"C2",X"4B",X"0F",X"2F",X"6F",X"07",X"21",X"70",X"70",X"61",X"43",X"07",X"07", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"84",X"A4",X"3C",X"3C", + X"0F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"07",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"4B",X"61",X"61",X"01",X"01",X"00",X"00",X"00", + X"00",X"00",X"01",X"03",X"0F",X"0F",X"0F",X"0F",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"30", + X"00",X"C0",X"E0",X"69",X"0F",X"C3",X"C3",X"87",X"EE",X"0D",X"2F",X"2F",X"6F",X"6F",X"6F",X"6F", + X"0F",X"87",X"C3",X"F0",X"78",X"E0",X"0E",X"08",X"30",X"70",X"70",X"70",X"43",X"07",X"34",X"03", + X"3C",X"3C",X"A4",X"84",X"00",X"00",X"00",X"00",X"0F",X"6F",X"2B",X"01",X"00",X"00",X"00",X"00", + X"00",X"01",X"67",X"EF",X"6F",X"6F",X"6F",X"0F",X"66",X"22",X"67",X"47",X"07",X"07",X"07",X"07", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"E0",X"69",X"0F",X"C3",X"C3",X"87", + X"6F",X"2F",X"0F",X"4B",X"C3",X"C0",X"08",X"00",X"07",X"07",X"43",X"61",X"70",X"70",X"21",X"07", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"3C",X"3C",X"A4",X"84",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"07", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"43",X"43",X"0F", + X"6F",X"2F",X"0F",X"4B",X"C2",X"C0",X"08",X"00",X"07",X"07",X"43",X"61",X"70",X"70",X"21",X"07", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"3C",X"3C",X"A4",X"84",X"00",X"00",X"00",X"00", + X"88",X"88",X"00",X"00",X"00",X"00",X"00",X"88",X"7F",X"7F",X"3F",X"0E",X"68",X"C0",X"00",X"BB", + X"69",X"69",X"4B",X"0F",X"B4",X"F0",X"30",X"22",X"01",X"01",X"01",X"01",X"10",X"00",X"00",X"33", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0E",X"0E",X"0C",X"08",X"08",X"6E",X"7F", + X"10",X"10",X"12",X"1E",X"0F",X"2D",X"69",X"69",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"01", + X"00",X"88",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"EE",X"00",X"00",X"00",X"00",X"00",X"00", + X"30",X"66",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"11",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"88",X"88",X"00",X"00",X"00",X"00",X"6E",X"7F",X"7F",X"7F",X"3F",X"0E",X"68",X"C0", + X"69",X"69",X"69",X"69",X"4B",X"0F",X"B4",X"F0",X"01",X"01",X"01",X"01",X"01",X"01",X"10",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0E",X"0E",X"0C",X"08",X"08", + X"00",X"00",X"10",X"10",X"12",X"1E",X"0F",X"2D",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01", + X"00",X"00",X"00",X"88",X"00",X"00",X"00",X"00",X"68",X"C0",X"00",X"CC",X"00",X"00",X"00",X"00", + X"B4",X"F0",X"30",X"DD",X"00",X"00",X"00",X"00",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"88",X"88",X"00",X"00",X"80",X"80",X"6E",X"7F",X"7F",X"7F",X"3F",X"0E", + X"0F",X"2D",X"69",X"69",X"69",X"69",X"4B",X"0F",X"00",X"01",X"01",X"01",X"01",X"01",X"01",X"01", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0E",X"0E",X"0C", + X"00",X"00",X"00",X"00",X"10",X"10",X"12",X"1E",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"88",X"00",X"00",X"3F",X"0E",X"68",X"C0",X"00",X"DD",X"00",X"00", + X"4B",X"0F",X"B4",X"F0",X"30",X"AA",X"00",X"00",X"01",X"01",X"10",X"00",X"00",X"11",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"88",X"88",X"0E",X"0C",X"08",X"08",X"6E",X"7F",X"7F",X"7F", + X"12",X"1E",X"0F",X"2D",X"69",X"69",X"69",X"69",X"00",X"00",X"00",X"01",X"01",X"01",X"01",X"01", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0E", + X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"8C",X"A8",X"88",X"20",X"20",X"20",X"00",X"00",X"1F",X"FF",X"F0",X"D0",X"D0",X"A0",X"C0",X"80", + X"CF",X"CF",X"DF",X"FE",X"FE",X"FC",X"FC",X"FC",X"3B",X"3B",X"3F",X"3B",X"3B",X"1D",X"11",X"00", + X"00",X"80",X"80",X"20",X"20",X"20",X"88",X"A8",X"EE",X"EF",X"88",X"88",X"EE",X"FF",X"FF",X"3F", + X"11",X"77",X"FF",X"FF",X"FF",X"FF",X"FF",X"EF",X"00",X"00",X"00",X"11",X"11",X"3B",X"3F",X"3B", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"80",X"00",X"00",X"00",X"00",X"00",X"00", + X"FC",X"FC",X"00",X"00",X"00",X"00",X"00",X"00",X"11",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"A8",X"A8",X"8C",X"A8",X"A8",X"00",X"20",X"20",X"FF",X"3F",X"1F",X"FF",X"F0",X"D0",X"D0",X"A0", + X"FF",X"EF",X"CF",X"CF",X"DF",X"FE",X"FE",X"FC",X"3F",X"3B",X"3B",X"3B",X"3F",X"3B",X"3B",X"1D", + X"00",X"00",X"80",X"80",X"00",X"20",X"20",X"00",X"00",X"00",X"EE",X"EF",X"88",X"88",X"EE",X"FF", + X"00",X"00",X"11",X"77",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"11",X"11",X"3B", + X"00",X"20",X"00",X"00",X"00",X"00",X"00",X"00",X"D0",X"A0",X"C0",X"80",X"00",X"00",X"00",X"00", + X"FE",X"FC",X"FC",X"FC",X"00",X"00",X"00",X"00",X"3B",X"1D",X"11",X"00",X"00",X"00",X"00",X"00", + X"00",X"20",X"A8",X"A8",X"8C",X"A8",X"A8",X"20",X"EE",X"FF",X"FF",X"3F",X"1F",X"FF",X"F0",X"D0", + X"FF",X"FF",X"FF",X"EF",X"CF",X"CF",X"DF",X"FE",X"11",X"3B",X"3F",X"3B",X"3B",X"3B",X"3F",X"3B", + X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"20",X"00",X"00",X"00",X"00",X"EE",X"EF",X"88",X"88", + X"00",X"00",X"00",X"00",X"11",X"77",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"11", + X"A8",X"00",X"20",X"20",X"00",X"00",X"00",X"00",X"F0",X"D0",X"D0",X"A0",X"C0",X"80",X"00",X"00", + X"DF",X"FE",X"FE",X"FC",X"FC",X"FC",X"00",X"00",X"3F",X"3B",X"3B",X"1D",X"11",X"00",X"00",X"00", + X"00",X"20",X"20",X"00",X"A8",X"A8",X"8C",X"A8",X"88",X"88",X"EE",X"FF",X"FF",X"3F",X"1F",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"EF",X"CF",X"CF",X"00",X"11",X"11",X"3B",X"3F",X"3B",X"3B",X"3B", + X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"EE",X"EF", + X"00",X"00",X"00",X"00",X"00",X"00",X"11",X"77",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"66",X"44",X"CC",X"88",X"00",X"00",X"00",X"00",X"F7",X"E6",X"4C",X"7F",X"E6",X"08",X"08",X"00", + X"5A",X"1E",X"C3",X"C3",X"96",X"0F",X"0F",X"07",X"61",X"43",X"03",X"30",X"10",X"01",X"00",X"00", + X"08",X"C0",X"C0",X"CA",X"CE",X"EE",X"AA",X"AA",X"E1",X"4B",X"3C",X"3F",X"7F",X"7F",X"F7",X"FF", + X"EF",X"EF",X"EF",X"EF",X"EF",X"EF",X"4F",X"FB",X"16",X"34",X"34",X"34",X"16",X"07",X"34",X"75", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"80",X"08",X"08",X"0C",X"A4",X"F0", + X"B4",X"A5",X"0F",X"6F",X"6F",X"6F",X"EF",X"EF",X"12",X"30",X"30",X"21",X"61",X"61",X"61",X"07", + X"00",X"00",X"08",X"0C",X"C0",X"80",X"00",X"00",X"00",X"E1",X"C3",X"1E",X"1E",X"3C",X"3C",X"84", + X"22",X"27",X"2F",X"2F",X"A7",X"A7",X"87",X"1E",X"00",X"00",X"00",X"00",X"10",X"10",X"10",X"03", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"08",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"0F",X"07",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"AA",X"AA",X"66",X"44",X"CC",X"88",X"00",X"00",X"F7",X"F7",X"F7",X"E6",X"4C",X"7F",X"E6",X"08", + X"4F",X"F7",X"5A",X"1E",X"C3",X"C3",X"96",X"0F",X"34",X"73",X"61",X"43",X"03",X"30",X"10",X"01", + X"00",X"00",X"08",X"C0",X"C0",X"CA",X"CE",X"EE",X"A4",X"F0",X"E1",X"4B",X"3C",X"3F",X"7F",X"7F", + X"EF",X"EF",X"EF",X"EF",X"EF",X"EF",X"EF",X"EF",X"61",X"07",X"16",X"34",X"34",X"34",X"16",X"07", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"3C",X"84",X"80",X"80",X"80",X"08",X"08",X"0C", + X"87",X"1E",X"B4",X"A5",X"0F",X"6F",X"6F",X"6F",X"10",X"03",X"12",X"30",X"30",X"21",X"61",X"61", + X"00",X"00",X"00",X"00",X"08",X"0C",X"C0",X"80",X"00",X"00",X"00",X"E1",X"C3",X"1E",X"1E",X"3C", + X"00",X"00",X"22",X"27",X"2F",X"2F",X"A7",X"A7",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"10", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"E6",X"08",X"08",X"00",X"00",X"00",X"00",X"00", + X"96",X"0F",X"0F",X"07",X"00",X"00",X"00",X"00",X"10",X"01",X"00",X"00",X"00",X"00",X"00",X"00", + X"CE",X"EE",X"AA",X"AA",X"66",X"44",X"CC",X"88",X"7F",X"7F",X"F7",X"FF",X"F7",X"E6",X"4C",X"7F", + X"EF",X"EF",X"4F",X"FE",X"5A",X"1E",X"C3",X"C3",X"16",X"07",X"34",X"76",X"61",X"43",X"03",X"30", + X"00",X"00",X"00",X"00",X"08",X"C0",X"C0",X"CA",X"08",X"0C",X"A4",X"F0",X"E1",X"4B",X"3C",X"3F", + X"6F",X"EF",X"EF",X"EF",X"EF",X"EF",X"EF",X"EF",X"61",X"61",X"61",X"07",X"16",X"34",X"34",X"34", + X"C0",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"1E",X"3C",X"3C",X"84",X"80",X"80",X"80",X"08", + X"A7",X"A7",X"87",X"1E",X"B4",X"A5",X"0F",X"6F",X"10",X"10",X"10",X"03",X"12",X"30",X"30",X"21", + X"00",X"00",X"00",X"00",X"00",X"00",X"08",X"0C",X"00",X"00",X"00",X"00",X"00",X"E1",X"C3",X"1E", + X"00",X"00",X"00",X"00",X"22",X"27",X"2F",X"2F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"CC",X"88",X"00",X"00",X"00",X"00",X"00",X"00",X"4C",X"7F",X"E6",X"08",X"08",X"00",X"00",X"00", + X"C3",X"C3",X"96",X"0F",X"0F",X"07",X"00",X"00",X"03",X"30",X"10",X"01",X"00",X"00",X"00",X"00", + X"C0",X"CA",X"CE",X"EE",X"AA",X"AA",X"66",X"44",X"3C",X"3F",X"7F",X"7F",X"F7",X"F7",X"F7",X"E6", + X"EF",X"EF",X"EF",X"EF",X"4F",X"FB",X"5A",X"1E",X"34",X"34",X"16",X"07",X"34",X"73",X"61",X"43", + X"00",X"00",X"00",X"00",X"00",X"00",X"08",X"C0",X"80",X"08",X"08",X"0C",X"A4",X"F0",X"E1",X"4B", + X"0F",X"6F",X"6F",X"EF",X"EF",X"EF",X"EF",X"EF",X"30",X"21",X"61",X"61",X"61",X"07",X"16",X"34", + X"08",X"0C",X"C0",X"80",X"00",X"00",X"00",X"00",X"C3",X"1E",X"1E",X"3C",X"3C",X"84",X"80",X"80", + X"2F",X"2F",X"A7",X"A7",X"87",X"1E",X"B4",X"A5",X"00",X"00",X"10",X"10",X"10",X"03",X"12",X"30", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"E1", + X"00",X"00",X"00",X"00",X"00",X"00",X"22",X"27",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"CC",X"02",X"08",X"6E",X"7B",X"F3",X"EE",X"88",X"97",X"F1",X"F3",X"E7",X"CF",X"16",X"32",X"11", + X"CF",X"7E",X"3D",X"F1",X"E4",X"CD",X"00",X"04",X"03",X"23",X"74",X"FC",X"FE",X"FF",X"77",X"00", + X"00",X"CC",X"EE",X"F8",X"7B",X"6A",X"4C",X"E6",X"02",X"00",X"DD",X"FC",X"E1",X"79",X"2F",X"4B", + X"00",X"9B",X"8F",X"2F",X"7C",X"EF",X"4B",X"F7",X"33",X"77",X"FE",X"ED",X"65",X"23",X"09",X"03", + X"8C",X"C0",X"C0",X"60",X"60",X"30",X"30",X"10",X"7E",X"F3",X"E6",X"C0",X"C1",X"80",X"80",X"80", + X"CB",X"FD",X"FE",X"FE",X"FF",X"66",X"00",X"00",X"FC",X"30",X"31",X"60",X"40",X"C0",X"81",X"80", + X"78",X"E6",X"EC",X"80",X"C4",X"EE",X"F7",X"E6",X"1E",X"A5",X"4B",X"0F",X"3D",X"E3",X"C3",X"9F", + X"6D",X"C3",X"69",X"BC",X"4B",X"CB",X"6D",X"9E",X"E1",X"63",X"31",X"32",X"77",X"FE",X"77",X"FE", + X"C4",X"EA",X"7F",X"7F",X"EA",X"C4",X"C8",X"68",X"4F",X"A5",X"F5",X"5A",X"69",X"C3",X"F9",X"B4", + X"D6",X"BD",X"E5",X"0F",X"5A",X"0F",X"DA",X"4B",X"77",X"FE",X"77",X"77",X"36",X"31",X"71",X"F0", + X"10",X"10",X"30",X"60",X"60",X"C0",X"C9",X"C0",X"00",X"00",X"80",X"A2",X"F7",X"FF",X"FA",X"FD", + X"10",X"10",X"54",X"FE",X"FC",X"FC",X"F5",X"CB",X"80",X"40",X"60",X"20",X"30",X"14",X"19",X"77", + X"60",X"30",X"30",X"10",X"00",X"00",X"00",X"00",X"C1",X"80",X"80",X"80",X"00",X"00",X"00",X"00", + X"FF",X"66",X"00",X"00",X"00",X"00",X"00",X"00",X"40",X"C0",X"81",X"80",X"00",X"00",X"00",X"00", + X"C4",X"EE",X"F7",X"E6",X"8C",X"C0",X"C0",X"60",X"3D",X"E3",X"C3",X"9F",X"7E",X"F3",X"E6",X"C0", + X"4F",X"CB",X"6D",X"9E",X"CB",X"FD",X"FE",X"FE",X"77",X"FE",X"77",X"FE",X"FC",X"30",X"31",X"60", + X"EA",X"C4",X"C8",X"68",X"78",X"E8",X"E2",X"80",X"69",X"C3",X"F9",X"B4",X"1E",X"A5",X"4B",X"0F", + X"5A",X"0F",X"DA",X"4B",X"6D",X"C3",X"69",X"BC",X"36",X"31",X"71",X"F0",X"E1",X"63",X"31",X"32", + X"60",X"C0",X"C9",X"C0",X"C4",X"EA",X"7F",X"7F",X"F7",X"FF",X"FA",X"FD",X"4F",X"A5",X"F5",X"5A", + X"FC",X"FC",X"F5",X"CB",X"D6",X"BD",X"E5",X"0F",X"30",X"14",X"19",X"77",X"77",X"FE",X"77",X"77", + X"00",X"00",X"00",X"00",X"10",X"10",X"30",X"60",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"A2", + X"00",X"00",X"00",X"00",X"10",X"10",X"54",X"FE",X"00",X"00",X"00",X"00",X"80",X"40",X"60",X"20", + X"0E",X"0E",X"0E",X"0C",X"0C",X"08",X"00",X"00",X"81",X"81",X"03",X"0F",X"0F",X"0F",X"0F",X"08", + X"F0",X"F0",X"E0",X"00",X"0F",X"0F",X"0F",X"0F",X"F0",X"70",X"30",X"0C",X"0F",X"0F",X"0F",X"07", + X"08",X"08",X"0E",X"0F",X"0F",X"0F",X"03",X"00",X"0F",X"07",X"07",X"03",X"03",X"00",X"00",X"00", + X"80",X"08",X"0C",X"0E",X"0E",X"0E",X"0E",X"0E",X"0F",X"0F",X"0F",X"C3",X"C3",X"C1",X"C1",X"C1", + X"0F",X"C3",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"0F",X"70",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"0F",X"0E",X"08",X"18",X"10",X"10",X"10",X"00",X"07",X"07",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + X"0C",X"08",X"00",X"80",X"80",X"80",X"C0",X"80",X"0F",X"0F",X"0F",X"0E",X"78",X"F0",X"78",X"1E", + X"F0",X"0F",X"0F",X"0F",X"0F",X"3C",X"0F",X"0F",X"78",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + X"0F",X"0F",X"0F",X"87",X"E1",X"C3",X"0F",X"0F",X"03",X"01",X"10",X"30",X"30",X"10",X"01",X"03", + X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0C",X"0F",X"01",X"81",X"01",X"01",X"01",X"83",X"43", + X"E0",X"D0",X"E0",X"D0",X"A0",X"D0",X"A0",X"D0",X"F0",X"F0",X"F0",X"F0",X"E0",X"F0",X"F0",X"F0", + X"30",X"10",X"30",X"70",X"78",X"78",X"3C",X"1E",X"0F",X"0F",X"0F",X"0F",X"07",X"07",X"07",X"03", + X"0E",X"0E",X"0E",X"0E",X"00",X"08",X"0E",X"0E",X"0F",X"0F",X"0F",X"01",X"08",X"0F",X"0F",X"0F", + X"0F",X"07",X"80",X"08",X"0F",X"0F",X"0F",X"0F",X"43",X"D0",X"68",X"0F",X"0F",X"0F",X"0F",X"F0", + X"10",X"70",X"0F",X"0F",X"0F",X"0F",X"07",X"07",X"08",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"00",X"00",X"00",X"00",X"00",X"08",X"0F", + X"0F",X"0F",X"00",X"00",X"00",X"0C",X"0F",X"0F",X"0F",X"0F",X"0F",X"00",X"0E",X"0F",X"0F",X"0F", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"01",X"00",X"0F",X"0F",X"0F",X"0F",X"0F",X"01",X"00", + X"00",X"00",X"08",X"0E",X"0E",X"0E",X"0E",X"0E",X"00",X"08",X"0F",X"0F",X"0F",X"07",X"0F",X"0F", + X"08",X"0F",X"0F",X"0F",X"07",X"00",X"0F",X"0F",X"0F",X"0F",X"0F",X"07",X"80",X"00",X"00",X"0F", + X"0F",X"0F",X"0F",X"50",X"20",X"00",X"00",X"00",X"0F",X"0F",X"20",X"10",X"00",X"00",X"00",X"00", + X"0E",X"0E",X"0E",X"0E",X"0C",X"00",X"00",X"00",X"81",X"81",X"0F",X"0F",X"0F",X"0E",X"80",X"80", + X"F0",X"F0",X"0F",X"0F",X"0F",X"0F",X"F0",X"F0",X"1E",X"1E",X"0F",X"0F",X"0F",X"0F",X"F0",X"78", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"66",X"EF",X"C7",X"C3",X"87",X"87",X"0F",X"00",X"00",X"00",X"14",X"34",X"16",X"34",X"10", + X"00",X"00",X"00",X"C0",X"E0",X"69",X"0F",X"C3",X"00",X"00",X"00",X"DB",X"2F",X"6F",X"6F",X"6F", + X"0F",X"0F",X"87",X"87",X"C3",X"C7",X"EF",X"66",X"10",X"10",X"34",X"16",X"34",X"14",X"00",X"00", + X"C3",X"87",X"3C",X"3C",X"A4",X"84",X"00",X"00",X"6F",X"6F",X"6F",X"6F",X"2F",X"0B",X"00",X"00", + X"00",X"00",X"80",X"C3",X"C3",X"C3",X"87",X"87",X"00",X"04",X"16",X"16",X"34",X"30",X"10",X"10", + X"00",X"44",X"FF",X"F3",X"E0",X"69",X"0F",X"C3",X"00",X"00",X"0F",X"0F",X"2B",X"6F",X"6F",X"6F", + X"87",X"87",X"87",X"C3",X"C3",X"C1",X"80",X"00",X"10",X"10",X"10",X"30",X"34",X"16",X"16",X"04", + X"C3",X"87",X"3C",X"3C",X"A4",X"B7",X"FF",X"44",X"6F",X"6F",X"6F",X"6F",X"2B",X"0F",X"0F",X"00", + X"61",X"E1",X"E1",X"E1",X"0F",X"0F",X"87",X"87",X"00",X"00",X"00",X"00",X"00",X"01",X"10",X"30", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"0E",X"0E",X"0E",X"08",X"0C",X"0C",X"1E",X"DE", + X"87",X"87",X"87",X"0F",X"D2",X"F0",X"30",X"CC",X"70",X"70",X"70",X"01",X"10",X"00",X"00",X"44", + X"80",X"80",X"00",X"00",X"00",X"00",X"00",X"88",X"EF",X"EF",X"EF",X"0E",X"E0",X"C0",X"00",X"44", + X"30",X"30",X"30",X"B4",X"B4",X"0F",X"B7",X"B7",X"00",X"00",X"00",X"44",X"10",X"10",X"74",X"30", + X"00",X"00",X"00",X"C0",X"E0",X"E0",X"2C",X"E0",X"00",X"00",X"80",X"80",X"C0",X"0F",X"8F",X"CF", + X"B7",X"B7",X"0F",X"B4",X"B4",X"30",X"30",X"30",X"74",X"30",X"10",X"54",X"00",X"00",X"00",X"00", + X"E0",X"2C",X"E0",X"E0",X"C0",X"00",X"00",X"00",X"CF",X"8F",X"0F",X"C0",X"80",X"80",X"00",X"00", + X"88",X"30",X"F0",X"D2",X"0F",X"87",X"87",X"87",X"22",X"00",X"00",X"10",X"01",X"70",X"70",X"70", + X"88",X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"99",X"00",X"C0",X"E0",X"0E",X"EF",X"EF",X"EF", + X"87",X"87",X"0F",X"0F",X"E1",X"E1",X"E1",X"61",X"30",X"10",X"01",X"00",X"00",X"00",X"00",X"00", + X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"DE",X"1E",X"0C",X"0C",X"08",X"0C",X"0E",X"0E", + X"40",X"68",X"2C",X"0F",X"0F",X"1F",X"1F",X"0F",X"00",X"01",X"03",X"43",X"43",X"61",X"61",X"01", + X"00",X"00",X"80",X"C0",X"C0",X"08",X"0C",X"48",X"00",X"00",X"10",X"3C",X"CF",X"EF",X"EF",X"CF", + X"87",X"C3",X"E1",X"E1",X"C0",X"00",X"00",X"00",X"00",X"10",X"30",X"70",X"30",X"10",X"00",X"00", + X"C0",X"91",X"80",X"44",X"00",X"00",X"00",X"00",X"0F",X"1E",X"3C",X"78",X"C0",X"11",X"22",X"00", + X"00",X"00",X"00",X"C0",X"E1",X"E1",X"C3",X"87",X"00",X"00",X"10",X"30",X"70",X"30",X"10",X"00", + X"00",X"00",X"00",X"88",X"44",X"80",X"91",X"C0",X"44",X"00",X"00",X"C0",X"78",X"3C",X"1E",X"0F", + X"0F",X"1F",X"1F",X"0F",X"0F",X"2C",X"68",X"40",X"01",X"61",X"61",X"43",X"43",X"03",X"01",X"00", + X"48",X"0C",X"08",X"C0",X"C0",X"80",X"00",X"00",X"CF",X"EF",X"EF",X"CF",X"3C",X"10",X"00",X"00", + X"C0",X"E0",X"F0",X"F0",X"E1",X"0F",X"0F",X"0F",X"00",X"00",X"10",X"10",X"00",X"00",X"01",X"01", + X"80",X"C0",X"86",X"0F",X"0F",X"0F",X"3C",X"28",X"10",X"30",X"30",X"83",X"0F",X"0F",X"0F",X"6F", + X"1F",X"97",X"C3",X"E1",X"30",X"00",X"44",X"22",X"10",X"10",X"44",X"00",X"11",X"00",X"00",X"00", + X"08",X"C0",X"E0",X"E0",X"C0",X"80",X"00",X"00",X"EF",X"EF",X"CF",X"1E",X"1C",X"00",X"00",X"00", + X"22",X"00",X"88",X"30",X"E1",X"C3",X"97",X"1F",X"00",X"00",X"00",X"11",X"00",X"44",X"10",X"10", + X"00",X"00",X"80",X"C0",X"E0",X"E0",X"C0",X"08",X"00",X"00",X"00",X"1C",X"1E",X"CF",X"EF",X"EF", + X"0F",X"0F",X"0F",X"E1",X"F0",X"F0",X"E0",X"C0",X"01",X"01",X"00",X"00",X"10",X"10",X"00",X"00", + X"28",X"3C",X"0F",X"0F",X"0F",X"86",X"C0",X"80",X"6F",X"0F",X"0F",X"0F",X"83",X"30",X"30",X"10", + X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"08",X"08",X"0E", + X"01",X"02",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0E",X"08",X"08",X"00",X"00",X"00",X"00",X"00", + X"F0",X"F1",X"F7",X"FF",X"FF",X"FF",X"FF",X"80",X"00",X"10",X"30",X"22",X"22",X"22",X"22",X"22", + X"00",X"00",X"C0",X"C0",X"E2",X"E2",X"E2",X"F3",X"80",X"FF",X"FF",X"FE",X"FC",X"FC",X"F8",X"70", + X"80",X"0C",X"0E",X"1F",X"08",X"34",X"00",X"00",X"22",X"22",X"02",X"01",X"07",X"01",X"01",X"00", + X"F3",X"F7",X"F7",X"77",X"66",X"C4",X"00",X"00",X"70",X"70",X"70",X"88",X"00",X"F0",X"00",X"00", + X"00",X"11",X"22",X"44",X"88",X"10",X"60",X"0C",X"00",X"00",X"00",X"00",X"00",X"01",X"05",X"03", + X"00",X"80",X"C0",X"E0",X"E8",X"FE",X"FF",X"FF",X"E0",X"70",X"30",X"30",X"77",X"FF",X"77",X"33", + X"0C",X"66",X"11",X"80",X"40",X"20",X"10",X"00",X"03",X"05",X"01",X"00",X"00",X"00",X"00",X"00", + X"F0",X"F0",X"F1",X"E6",X"EE",X"CC",X"88",X"00",X"30",X"70",X"F0",X"70",X"33",X"33",X"77",X"EE", + X"00",X"00",X"37",X"08",X"1E",X"0E",X"0C",X"88",X"00",X"01",X"01",X"07",X"01",X"02",X"20",X"20", + X"00",X"00",X"C8",X"60",X"70",X"F8",X"F8",X"FC",X"00",X"00",X"FF",X"00",X"80",X"77",X"77",X"77", + X"88",X"F0",X"F0",X"F0",X"F0",X"F8",X"FE",X"FF",X"20",X"20",X"20",X"20",X"20",X"33",X"11",X"00", + X"FC",X"EC",X"EC",X"EC",X"CC",X"CC",X"00",X"00",X"77",X"F7",X"F3",X"F3",X"F1",X"F0",X"F0",X"88", + X"00",X"33",X"77",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"15",X"17",X"15", + X"00",X"48",X"40",X"10",X"10",X"88",X"DC",X"DC",X"FF",X"FF",X"CC",X"CC",X"FF",X"FF",X"FF",X"1F", + X"EF",X"EF",X"EF",X"FF",X"FF",X"FE",X"FE",X"76",X"15",X"15",X"17",X"15",X"15",X"06",X"00",X"00", + X"DE",X"DC",X"D4",X"80",X"90",X"10",X"00",X"00",X"0F",X"7F",X"F8",X"E0",X"E0",X"D0",X"E0",X"C0", + X"00",X"33",X"77",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"15",X"17",X"15", + X"40",X"48",X"00",X"10",X"00",X"98",X"DC",X"CC",X"FF",X"FF",X"CC",X"CC",X"FF",X"FF",X"FF",X"1F", + X"EF",X"EF",X"EF",X"FF",X"FF",X"FE",X"FE",X"76",X"15",X"15",X"17",X"15",X"15",X"06",X"00",X"00", + X"DE",X"CC",X"D4",X"90",X"80",X"10",X"00",X"00",X"0F",X"7F",X"F8",X"E0",X"E0",X"D0",X"E0",X"C0", + X"00",X"23",X"47",X"7F",X"FF",X"FE",X"FE",X"FE",X"00",X"00",X"00",X"01",X"07",X"00",X"11",X"11", + X"00",X"00",X"00",X"98",X"98",X"C4",X"D0",X"D2",X"00",X"2E",X"FF",X"F3",X"F0",X"F0",X"F0",X"F0", + X"FE",X"FE",X"FE",X"FF",X"7F",X"47",X"23",X"00",X"11",X"11",X"00",X"07",X"01",X"00",X"00",X"00", + X"52",X"50",X"C4",X"98",X"98",X"00",X"00",X"00",X"F0",X"F0",X"E0",X"F0",X"F3",X"FF",X"2E",X"00", + X"76",X"FE",X"FE",X"FF",X"FF",X"EF",X"EF",X"EF",X"00",X"00",X"06",X"15",X"15",X"17",X"15",X"15", + X"00",X"00",X"10",X"80",X"90",X"D4",X"CC",X"DE",X"C0",X"E0",X"D0",X"E0",X"E0",X"F8",X"7F",X"0F", + X"FF",X"FF",X"FF",X"FF",X"FF",X"77",X"33",X"00",X"15",X"17",X"15",X"00",X"00",X"00",X"00",X"00", + X"CC",X"DC",X"98",X"00",X"10",X"40",X"48",X"00",X"1F",X"FF",X"FF",X"FF",X"CC",X"CC",X"FF",X"FF", + X"76",X"FE",X"FE",X"FF",X"FF",X"EF",X"EF",X"EF",X"00",X"00",X"06",X"15",X"15",X"17",X"15",X"15", + X"00",X"00",X"10",X"90",X"80",X"D4",X"DC",X"CE",X"C0",X"E0",X"D0",X"E0",X"E0",X"F8",X"7F",X"0F", + X"FF",X"FF",X"FF",X"FF",X"FF",X"77",X"33",X"00",X"15",X"17",X"15",X"00",X"00",X"00",X"00",X"00", + X"DC",X"DC",X"88",X"10",X"10",X"00",X"48",X"40",X"1F",X"FF",X"FF",X"FF",X"CC",X"CC",X"FF",X"FF", + X"00",X"00",X"11",X"77",X"7F",X"FF",X"EF",X"CF",X"00",X"00",X"00",X"01",X"03",X"02",X"06",X"15", + X"10",X"CE",X"DC",X"88",X"00",X"10",X"98",X"DC",X"00",X"77",X"FF",X"FF",X"FF",X"7F",X"3F",X"1F", + X"BF",X"FE",X"FC",X"F8",X"F0",X"F0",X"F0",X"30",X"17",X"33",X"37",X"33",X"33",X"11",X"00",X"00", + X"CC",X"DC",X"CE",X"DC",X"98",X"98",X"00",X"10",X"CF",X"F7",X"F3",X"F1",X"F1",X"B1",X"73",X"C4", + X"30",X"F0",X"F0",X"F0",X"F8",X"FC",X"FE",X"BF",X"00",X"00",X"11",X"33",X"33",X"37",X"33",X"17", + X"10",X"10",X"88",X"98",X"DC",X"CE",X"DC",X"DC",X"C4",X"73",X"B1",X"F1",X"F1",X"F3",X"F7",X"CF", + X"CF",X"EF",X"FF",X"7F",X"77",X"11",X"00",X"00",X"15",X"06",X"02",X"03",X"01",X"00",X"00",X"00", + X"DC",X"88",X"10",X"00",X"88",X"DC",X"CE",X"10",X"1F",X"3F",X"7F",X"FF",X"FF",X"FF",X"77",X"00", + X"E8",X"1F",X"DF",X"E3",X"E3",X"CF",X"C3",X"ED",X"11",X"21",X"21",X"57",X"57",X"43",X"43",X"12", + X"00",X"00",X"00",X"08",X"08",X"8C",X"8D",X"3F",X"00",X"00",X"0E",X"87",X"B7",X"9F",X"8F",X"87", + X"ED",X"C3",X"CF",X"E3",X"E3",X"DF",X"1F",X"E8",X"56",X"43",X"43",X"57",X"57",X"21",X"21",X"11", + X"3F",X"1D",X"0C",X"08",X"08",X"00",X"00",X"00",X"87",X"8F",X"8F",X"87",X"87",X"0E",X"00",X"00", + X"E6",X"1E",X"DE",X"E3",X"E3",X"CF",X"C3",X"ED",X"10",X"23",X"23",X"53",X"53",X"47",X"47",X"52", + X"00",X"00",X"00",X"08",X"08",X"8C",X"9D",X"3F",X"00",X"00",X"0E",X"8F",X"BF",X"97",X"87",X"8F", + X"ED",X"C3",X"CF",X"E3",X"E3",X"DE",X"1E",X"E6",X"52",X"47",X"47",X"53",X"53",X"23",X"23",X"10", + X"3F",X"1D",X"0C",X"08",X"08",X"00",X"00",X"00",X"8F",X"87",X"87",X"8F",X"8F",X"0E",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"CC",X"EE",X"FF",X"00",X"00",X"00",X"00",X"00",X"11",X"33",X"77", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"86",X"00",X"00",X"00",X"00",X"00",X"00",X"25",X"1E", + X"FF",X"FF",X"EE",X"CC",X"00",X"00",X"00",X"00",X"77",X"77",X"33",X"11",X"00",X"00",X"00",X"00", + X"78",X"80",X"20",X"00",X"00",X"00",X"00",X"00",X"0F",X"34",X"52",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"CC",X"EE",X"FF",X"00",X"00",X"00",X"00",X"00",X"11",X"33",X"77", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"68",X"00",X"00",X"00",X"00",X"00",X"00",X"52",X"E1", + X"FF",X"FF",X"EE",X"CC",X"00",X"00",X"00",X"00",X"77",X"77",X"33",X"11",X"00",X"00",X"00",X"00", + X"87",X"08",X"02",X"00",X"00",X"00",X"00",X"00",X"F0",X"43",X"25",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"10",X"00",X"14",X"5B",X"3E",X"78",X"00",X"00",X"00",X"02",X"01",X"00",X"00",X"50", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"18",X"84",X"CA", + X"16",X"29",X"10",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"B4",X"84",X"02",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"01",X"13",X"36",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"0C",X"84", + X"12",X"01",X"11",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"08",X"80",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"64",X"70",X"F5",X"E1",X"DA",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"00",X"00",X"00",X"84",X"C0",X"58",X"F4",X"3D", + X"C3",X"A5",X"72",X"21",X"22",X"00",X"00",X"00",X"00",X"00",X"10",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"B4",X"E8",X"20",X"80",X"00",X"00",X"00",X"00", + X"80",X"C0",X"42",X"60",X"B4",X"DA",X"87",X"D3",X"00",X"44",X"00",X"01",X"64",X"41",X"30",X"10", + X"80",X"22",X"00",X"08",X"74",X"C0",X"80",X"00",X"00",X"18",X"30",X"F0",X"7C",X"5A",X"78",X"2C", + X"0F",X"1E",X"A7",X"C3",X"5A",X"65",X"61",X"90",X"31",X"61",X"10",X"30",X"60",X"50",X"44",X"00", + X"A4",X"01",X"80",X"E0",X"30",X"08",X"22",X"80",X"87",X"9E",X"3C",X"5A",X"78",X"E0",X"30",X"11", + X"EE",X"FF",X"99",X"88",X"00",X"77",X"FF",X"88",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"66",X"11",X"FF",X"EE",X"00",X"EE",X"FF",X"11", + X"FF",X"77",X"00",X"77",X"FF",X"88",X"FF",X"77",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"EE",X"00",X"EE",X"FF",X"11",X"FF",X"EE", + X"44",X"88",X"FF",X"77",X"00",X"77",X"FF",X"88",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"22",X"99",X"FF",X"66",X"00",X"EE",X"FF",X"11", + X"FF",X"77",X"00",X"77",X"FF",X"88",X"FF",X"77",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"EE",X"00",X"EE",X"FF",X"11",X"FF",X"EE", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/cmd_col_rom.vhd b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/cmd_col_rom.vhd new file mode 100644 index 00000000..1eef2d60 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/cmd_col_rom.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity cmd_col_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of cmd_col_rom is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"01",X"02",X"04",X"0F",X"01",X"0F",X"0D",X"08",X"01",X"06",X"0C",X"0B",X"01",X"09",X"06",X"03", + X"01",X"03",X"04",X"05",X"01",X"05",X"0F",X"02",X"01",X"05",X"0F",X"02",X"01",X"02",X"05",X"08", + X"01",X"02",X"0F",X"04",X"01",X"04",X"03",X"0F",X"01",X"0D",X"09",X"0F",X"01",X"0F",X"08",X"00", + X"01",X"0F",X"09",X"02",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"02",X"04",X"0F",X"00",X"0F",X"0D",X"08",X"00",X"06",X"0C",X"0B",X"00",X"09",X"06",X"03", + X"00",X"03",X"04",X"05",X"00",X"05",X"0F",X"02",X"00",X"05",X"0F",X"02",X"00",X"02",X"05",X"08", + X"00",X"02",X"0F",X"04",X"00",X"04",X"03",X"0F",X"00",X"0D",X"09",X"0F",X"00",X"0F",X"08",X"00", + X"00",X"0F",X"09",X"02",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"01",X"02",X"04",X"0F",X"01",X"0F",X"0D",X"08",X"01",X"06",X"0C",X"0B",X"01",X"09",X"06",X"03", + X"01",X"03",X"04",X"05",X"01",X"05",X"0F",X"02",X"01",X"05",X"0F",X"02",X"01",X"02",X"05",X"08", + X"01",X"02",X"0F",X"04",X"01",X"04",X"03",X"0F",X"01",X"0D",X"09",X"0F",X"01",X"0F",X"08",X"00", + X"01",X"0F",X"09",X"02",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"02",X"04",X"0F",X"00",X"0F",X"0D",X"08",X"00",X"06",X"0C",X"0B",X"00",X"09",X"06",X"03", + X"00",X"03",X"04",X"05",X"00",X"05",X"0F",X"02",X"00",X"05",X"0F",X"02",X"00",X"02",X"05",X"08", + X"00",X"02",X"0F",X"04",X"00",X"04",X"03",X"0F",X"00",X"0D",X"09",X"0F",X"00",X"0F",X"08",X"00", + X"00",X"0F",X"09",X"02",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/cmd_dot_rom.vhd b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/cmd_dot_rom.vhd new file mode 100644 index 00000000..38ad297c --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/cmd_dot_rom.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity cmd_dot_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of cmd_dot_rom is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"03",X"03",X"03",X"01",X"03",X"03",X"01",X"03",X"03",X"01",X"03",X"03",X"01",X"03",X"03",X"03", + X"01",X"03",X"03",X"03",X"03",X"01",X"03",X"03",X"03",X"03",X"01",X"03",X"03",X"03",X"03",X"01", + X"02",X"03",X"03",X"02",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"02",X"03",X"03",X"02", + X"03",X"02",X"02",X"03",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"03",X"02",X"02",X"03", + X"03",X"03",X"03",X"03",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"03",X"03",X"03",X"03", + X"01",X"03",X"02",X"01",X"03",X"02",X"01",X"02",X"02",X"01",X"02",X"03",X"01",X"02",X"03",X"01", + X"03",X"03",X"03",X"02",X"03",X"02",X"02",X"03",X"03",X"02",X"02",X"03",X"02",X"03",X"03",X"03", + X"03",X"01",X"01",X"03",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"03",X"01",X"01",X"01", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/cmd_pal_rom.vhd b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/cmd_pal_rom.vhd new file mode 100644 index 00000000..76133e93 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/cmd_pal_rom.vhd @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity cmd_pal_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of cmd_pal_rom is + type rom is array(0 to 31) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"A0",X"25",X"3F",X"07",X"A4",X"2D",X"5D",X"27",X"A7",X"E0",X"B7",X"20",X"84",X"7A",X"FF", + X"00",X"3F",X"07",X"00",X"00",X"3F",X"07",X"00",X"00",X"3F",X"07",X"00",X"00",X"3F",X"07",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/cmd_prg_rom.vhd b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/cmd_prg_rom.vhd new file mode 100644 index 00000000..3b2b211f --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/cmd_prg_rom.vhd @@ -0,0 +1,1302 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity cmd_prg_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(14 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of cmd_prg_rom is + type rom is array(0 to 20479) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"C3",X"A0",X"00",X"2A",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20", + X"20",X"20",X"31",X"39",X"38",X"33",X"2E",X"30",X"39",X"20",X"20",X"20",X"20",X"42",X"59",X"20", + X"20",X"45",X"4C",X"53",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20", + X"20",X"20",X"20",X"20",X"2A",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"3A",X"00",X"A1",X"CB",X"5F",X"C0",X"3E",X"03",X"32",X"E4",X"9B",X"C9",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"F5",X"AF",X"32",X"81",X"A1",X"C5",X"D5",X"E5",X"DD",X"E5", + X"FD",X"E5",X"00",X"00",X"00",X"CD",X"5F",X"11",X"CD",X"C2",X"11",X"CD",X"88",X"0B",X"CD",X"56", + X"0F",X"CD",X"BD",X"0F",X"CD",X"EC",X"0A",X"3E",X"00",X"32",X"80",X"A0",X"FD",X"E1",X"DD",X"E1", + X"E1",X"D1",X"C1",X"3E",X"01",X"32",X"81",X"A1",X"F1",X"ED",X"45",X"00",X"00",X"00",X"00",X"00", + X"AF",X"32",X"81",X"A1",X"3E",X"01",X"32",X"83",X"A1",X"ED",X"47",X"AF",X"21",X"00",X"98",X"11", + X"01",X"98",X"01",X"FF",X"07",X"77",X"ED",X"B0",X"31",X"FF",X"9F",X"CD",X"01",X"07",X"CD",X"DB", + X"0A",X"21",X"FF",X"FF",X"22",X"F0",X"9B",X"AF",X"32",X"E6",X"9B",X"AF",X"32",X"F2",X"9B",X"32", + X"F3",X"9B",X"CD",X"02",X"06",X"3A",X"F4",X"9B",X"2F",X"47",X"3A",X"F5",X"9B",X"2F",X"A0",X"CA", + X"C6",X"01",X"3A",X"F6",X"9B",X"A7",X"C2",X"0D",X"01",X"3A",X"F7",X"9B",X"47",X"3A",X"F8",X"9B", + X"B0",X"CA",X"CB",X"00",X"2A",X"F0",X"9B",X"7C",X"B5",X"CA",X"3F",X"01",X"2B",X"22",X"F0",X"9B", + X"CD",X"CE",X"01",X"CD",X"33",X"01",X"AF",X"32",X"F9",X"9B",X"C3",X"E2",X"00",X"CD",X"B5",X"10", + X"CD",X"F2",X"12",X"CD",X"3F",X"02",X"AF",X"32",X"F9",X"9B",X"3A",X"F2",X"9B",X"A7",X"C2",X"6A", + X"01",X"3A",X"F6",X"9B",X"FE",X"02",X"DA",X"13",X"01",X"3A",X"F3",X"9B",X"A7",X"C2",X"78",X"01", + X"C3",X"13",X"01",X"3A",X"F9",X"9B",X"A7",X"C8",X"CD",X"B5",X"10",X"CD",X"F2",X"12",X"C9",X"3A", + X"FA",X"9B",X"A7",X"C2",X"56",X"01",X"3E",X"FF",X"32",X"FA",X"9B",X"3A",X"F7",X"9B",X"47",X"3A", + X"F8",X"9B",X"80",X"C3",X"C7",X"00",X"3A",X"F7",X"9B",X"47",X"3A",X"F8",X"9B",X"80",X"47",X"B8", + X"CA",X"CB",X"00",X"AF",X"32",X"FA",X"9B",X"C3",X"C1",X"00",X"AF",X"32",X"E3",X"9B",X"3A",X"F6", + X"9B",X"3D",X"32",X"F6",X"9B",X"C3",X"85",X"01",X"3E",X"FF",X"32",X"E3",X"9B",X"3A",X"F6",X"9B", + X"D6",X"02",X"32",X"F6",X"9B",X"AF",X"32",X"F2",X"9B",X"32",X"F3",X"9B",X"CD",X"16",X"07",X"CD", + X"3E",X"04",X"CD",X"3D",X"0C",X"3A",X"EE",X"9B",X"47",X"3A",X"EF",X"9B",X"A0",X"CA",X"8F",X"01", + X"AF",X"32",X"FC",X"9B",X"32",X"6C",X"9C",X"32",X"83",X"A1",X"32",X"54",X"9A",X"3E",X"FF",X"32", + X"FB",X"9B",X"CD",X"F2",X"12",X"AF",X"32",X"5D",X"9A",X"CD",X"2B",X"37",X"3A",X"6C",X"9C",X"A7", + X"CA",X"B9",X"01",X"C3",X"C1",X"00",X"3E",X"FF",X"32",X"F6",X"9B",X"C3",X"1A",X"01",X"3A",X"F6", + X"9B",X"A7",X"C0",X"CD",X"36",X"04",X"21",X"C2",X"3B",X"CD",X"84",X"10",X"3A",X"F7",X"9B",X"A7", + X"C2",X"EB",X"01",X"3A",X"F8",X"9B",X"A7",X"C2",X"28",X"02",X"C9",X"3A",X"F4",X"9B",X"4F",X"06", + X"00",X"CB",X"21",X"DD",X"21",X"77",X"3C",X"DD",X"09",X"DD",X"6E",X"00",X"DD",X"66",X"01",X"11", + X"E3",X"01",X"D5",X"ED",X"5B",X"59",X"9A",X"01",X"FF",X"03",X"7B",X"A1",X"4F",X"7A",X"A0",X"B1", + X"CC",X"84",X"10",X"E5",X"EB",X"11",X"00",X"02",X"19",X"EB",X"E1",X"01",X"FF",X"03",X"7B",X"A1", + X"4F",X"7A",X"A0",X"B1",X"CA",X"DD",X"0F",X"C9",X"3A",X"F5",X"9B",X"4F",X"06",X"00",X"CB",X"21", + X"DD",X"21",X"26",X"3D",X"DD",X"09",X"DD",X"6E",X"00",X"DD",X"66",X"01",X"C3",X"03",X"02",X"CD", + X"36",X"04",X"21",X"85",X"3C",X"CD",X"DD",X"0F",X"21",X"D6",X"3B",X"CD",X"DD",X"0F",X"21",X"C2", + X"3B",X"CD",X"DD",X"0F",X"3A",X"F6",X"9B",X"FE",X"02",X"DA",X"65",X"02",X"21",X"B0",X"3B",X"22", + X"85",X"9C",X"C3",X"6B",X"02",X"21",X"9F",X"3B",X"22",X"85",X"9C",X"2A",X"59",X"9A",X"01",X"FF", + X"03",X"79",X"A5",X"4F",X"78",X"A4",X"B1",X"CA",X"8B",X"02",X"01",X"00",X"02",X"09",X"01",X"FF", + X"03",X"79",X"A5",X"4F",X"78",X"A4",X"B1",X"CA",X"98",X"02",X"C9",X"21",X"8A",X"3B",X"CD",X"84", + X"10",X"2A",X"85",X"9C",X"CD",X"84",X"10",X"C9",X"2A",X"85",X"9C",X"CD",X"DD",X"0F",X"C9",X"3A", + X"F4",X"9B",X"FE",X"00",X"CA",X"E7",X"02",X"FE",X"01",X"CA",X"2F",X"03",X"FE",X"02",X"CA",X"5F", + X"03",X"FE",X"03",X"CA",X"77",X"03",X"FE",X"04",X"CA",X"FF",X"02",X"FE",X"05",X"CA",X"17",X"03", + X"C3",X"47",X"03",X"3A",X"F5",X"9B",X"FE",X"00",X"CA",X"8F",X"03",X"FE",X"01",X"CA",X"D6",X"03", + X"FE",X"02",X"CA",X"06",X"04",X"FE",X"03",X"CA",X"1E",X"04",X"FE",X"04",X"CA",X"A6",X"03",X"FE", + X"05",X"CA",X"BE",X"03",X"C3",X"EE",X"03",X"3A",X"F7",X"9B",X"C6",X"01",X"32",X"F7",X"9B",X"FE", + X"01",X"C0",X"3A",X"F6",X"9B",X"C6",X"01",X"32",X"F6",X"9B",X"AF",X"32",X"F7",X"9B",X"C9",X"3A", + X"F7",X"9B",X"C6",X"01",X"32",X"F7",X"9B",X"FE",X"01",X"C0",X"3A",X"F6",X"9B",X"C6",X"02",X"32", + X"F6",X"9B",X"AF",X"32",X"F7",X"9B",X"C9",X"3A",X"F7",X"9B",X"C6",X"01",X"32",X"F7",X"9B",X"FE", + X"01",X"C0",X"3A",X"F6",X"9B",X"C6",X"03",X"32",X"F6",X"9B",X"AF",X"32",X"F7",X"9B",X"C9",X"3A", + X"F7",X"9B",X"C6",X"01",X"32",X"F7",X"9B",X"FE",X"02",X"C0",X"3A",X"F6",X"9B",X"C6",X"01",X"32", + X"F6",X"9B",X"AF",X"32",X"F7",X"9B",X"C9",X"3A",X"F7",X"9B",X"C6",X"01",X"32",X"F7",X"9B",X"FE", + X"02",X"C0",X"3A",X"F6",X"9B",X"C6",X"03",X"32",X"F6",X"9B",X"AF",X"32",X"F7",X"9B",X"C9",X"3A", + X"F7",X"9B",X"C6",X"01",X"32",X"F7",X"9B",X"FE",X"03",X"C0",X"3A",X"F6",X"9B",X"C6",X"01",X"32", + X"F6",X"9B",X"AF",X"32",X"F7",X"9B",X"C9",X"3A",X"F7",X"9B",X"C6",X"01",X"32",X"F7",X"9B",X"FE", + X"04",X"C0",X"3A",X"F6",X"9B",X"C6",X"01",X"32",X"F6",X"9B",X"AF",X"32",X"F7",X"9B",X"C9",X"3A", + X"F8",X"9B",X"C6",X"01",X"32",X"F8",X"9B",X"FE",X"01",X"C0",X"3A",X"F6",X"9B",X"3C",X"32",X"F6", + X"9B",X"AF",X"32",X"F8",X"9B",X"C9",X"3A",X"F8",X"9B",X"C6",X"01",X"32",X"F8",X"9B",X"FE",X"01", + X"C0",X"3A",X"F6",X"9B",X"C6",X"02",X"32",X"F6",X"9B",X"AF",X"32",X"F8",X"9B",X"C9",X"3A",X"F8", + X"9B",X"C6",X"01",X"32",X"F8",X"9B",X"FE",X"01",X"C0",X"3A",X"F6",X"9B",X"C6",X"03",X"32",X"F6", + X"9B",X"AF",X"32",X"F8",X"9B",X"C9",X"3A",X"F8",X"9B",X"C6",X"01",X"32",X"F8",X"9B",X"FE",X"02", + X"C0",X"3A",X"F6",X"9B",X"C6",X"01",X"32",X"F6",X"9B",X"AF",X"32",X"F8",X"9B",X"C9",X"3A",X"F8", + X"9B",X"C6",X"01",X"32",X"F8",X"9B",X"FE",X"02",X"C0",X"3A",X"F6",X"9B",X"C6",X"03",X"32",X"F6", + X"9B",X"AF",X"32",X"F8",X"9B",X"C9",X"3A",X"F8",X"9B",X"C6",X"01",X"32",X"F8",X"9B",X"FE",X"03", + X"C0",X"3A",X"F6",X"9B",X"C6",X"01",X"32",X"F6",X"9B",X"AF",X"32",X"F8",X"9B",X"C9",X"3A",X"F8", + X"9B",X"C6",X"01",X"32",X"F8",X"9B",X"FE",X"04",X"C0",X"3A",X"F6",X"9B",X"C6",X"01",X"32",X"F6", + X"9B",X"AF",X"32",X"F8",X"9B",X"C9",X"2A",X"59",X"9A",X"23",X"22",X"59",X"9A",X"C9",X"3A",X"66", + X"9A",X"FE",X"0F",X"CA",X"55",X"04",X"FE",X"1F",X"CA",X"EE",X"04",X"CD",X"DB",X"0A",X"CD",X"8F", + X"07",X"CD",X"DB",X"0A",X"C9",X"CD",X"F2",X"12",X"3A",X"5D",X"9A",X"A7",X"C2",X"7E",X"04",X"3A", + X"8F",X"9C",X"A7",X"3E",X"00",X"32",X"8F",X"9C",X"C2",X"E1",X"04",X"3A",X"90",X"9C",X"A7",X"3E", + X"00",X"32",X"90",X"9C",X"C2",X"BB",X"04",X"DD",X"21",X"67",X"9A",X"C3",X"9A",X"04",X"3A",X"91", + X"9C",X"A7",X"3E",X"00",X"32",X"91",X"9C",X"C2",X"E7",X"04",X"3A",X"92",X"9C",X"A7",X"3E",X"00", + X"32",X"92",X"9C",X"C2",X"BB",X"04",X"DD",X"21",X"25",X"9B",X"DD",X"7E",X"00",X"32",X"8B",X"9C", + X"DD",X"7E",X"01",X"32",X"53",X"9A",X"DD",X"E5",X"E1",X"23",X"23",X"11",X"40",X"9A",X"01",X"11", + X"00",X"ED",X"B0",X"11",X"50",X"99",X"01",X"A0",X"00",X"ED",X"B0",X"CD",X"1E",X"14",X"CD",X"D1", + X"12",X"CD",X"09",X"14",X"CD",X"B3",X"12",X"CD",X"F7",X"0F",X"CD",X"2B",X"11",X"CD",X"5C",X"0E", + X"CD",X"E1",X"0A",X"3E",X"1F",X"32",X"66",X"9A",X"3E",X"03",X"CD",X"09",X"11",X"CD",X"E1",X"0A", + X"C9",X"CD",X"A3",X"12",X"C3",X"BB",X"04",X"AF",X"32",X"8B",X"9C",X"C3",X"E1",X"04",X"CD",X"6E", + X"15",X"CD",X"D0",X"20",X"CD",X"B7",X"21",X"CD",X"3B",X"24",X"CD",X"CF",X"25",X"CD",X"0B",X"28", + X"CD",X"AD",X"19",X"CD",X"0A",X"05",X"CD",X"12",X"05",X"C9",X"3A",X"59",X"9A",X"3C",X"32",X"59", + X"9A",X"C9",X"3A",X"51",X"9A",X"A7",X"CA",X"2D",X"05",X"3E",X"00",X"32",X"66",X"9A",X"32",X"51", + X"9A",X"32",X"8C",X"9C",X"CD",X"DB",X"0A",X"3E",X"08",X"CD",X"09",X"11",X"C9",X"3A",X"8B",X"9C", + X"FE",X"10",X"D8",X"DD",X"21",X"50",X"99",X"01",X"20",X"00",X"16",X"05",X"3E",X"00",X"DD",X"B6", + X"00",X"DD",X"09",X"15",X"C2",X"3E",X"05",X"A7",X"C0",X"AF",X"32",X"8B",X"9C",X"3E",X"06",X"CD", + X"09",X"11",X"CD",X"AA",X"05",X"CD",X"98",X"05",X"3A",X"40",X"9A",X"3C",X"32",X"40",X"9A",X"FE", + X"04",X"D2",X"8E",X"05",X"CD",X"0D",X"13",X"21",X"41",X"9A",X"11",X"42",X"9A",X"01",X"10",X"00", + X"36",X"00",X"ED",X"B0",X"3E",X"0F",X"32",X"66",X"9A",X"3A",X"5D",X"9A",X"A7",X"C2",X"86",X"05", + X"3E",X"FF",X"32",X"90",X"9C",X"C9",X"3E",X"FF",X"32",X"92",X"9C",X"C9",X"04",X"C9",X"AF",X"32", + X"40",X"9A",X"CD",X"D6",X"10",X"C3",X"64",X"05",X"3A",X"53",X"9A",X"3C",X"FE",X"04",X"D2",X"A5", + X"05",X"32",X"53",X"9A",X"C9",X"AF",X"32",X"53",X"9A",X"C9",X"CD",X"B5",X"10",X"CD",X"F2",X"12", + X"21",X"B0",X"44",X"CD",X"84",X"10",X"21",X"B9",X"44",X"CD",X"84",X"10",X"16",X"03",X"CD",X"51", + X"36",X"21",X"41",X"9A",X"0E",X"08",X"06",X"00",X"7E",X"A7",X"CC",X"8C",X"05",X"23",X"23",X"0D", + X"C2",X"C8",X"05",X"78",X"32",X"2B",X"86",X"4F",X"06",X"00",X"DD",X"21",X"C3",X"44",X"CB",X"21", + X"CB",X"10",X"DD",X"09",X"DD",X"6E",X"00",X"DD",X"66",X"01",X"22",X"5B",X"9A",X"DD",X"21",X"11", + X"45",X"DD",X"09",X"DD",X"6E",X"00",X"DD",X"66",X"01",X"CD",X"84",X"10",X"3E",X"08",X"CD",X"09", + X"11",X"C9",X"3A",X"E6",X"9B",X"A7",X"CA",X"5D",X"06",X"FE",X"0F",X"CA",X"92",X"06",X"CD",X"3E", + X"04",X"CD",X"21",X"06",X"3A",X"EE",X"9B",X"A7",X"C8",X"CD",X"CA",X"06",X"AF",X"32",X"E6",X"9B", + X"C9",X"3A",X"59",X"9A",X"E6",X"1F",X"C0",X"2A",X"E7",X"9B",X"23",X"22",X"E7",X"9B",X"E5",X"01", + X"A0",X"00",X"A7",X"ED",X"42",X"E1",X"D2",X"56",X"06",X"CB",X"3C",X"CB",X"1D",X"CB",X"3C",X"CB", + X"1D",X"01",X"D9",X"44",X"09",X"7E",X"32",X"54",X"9A",X"CB",X"45",X"C8",X"AF",X"32",X"55",X"9A", + X"3E",X"FF",X"32",X"56",X"9A",X"C9",X"21",X"00",X"00",X"22",X"E7",X"9B",X"C9",X"CD",X"B5",X"10", + X"CD",X"F2",X"12",X"CD",X"5C",X"0B",X"CD",X"DB",X"0A",X"AF",X"32",X"5D",X"9A",X"32",X"E3",X"9B", + X"32",X"EE",X"9B",X"3E",X"00",X"32",X"E4",X"9B",X"3E",X"0F",X"32",X"E6",X"9B",X"21",X"00",X"00", + X"22",X"E7",X"9B",X"22",X"87",X"9C",X"3E",X"01",X"32",X"EA",X"9B",X"32",X"52",X"9A",X"CD",X"A3", + X"12",X"C9",X"CD",X"E4",X"06",X"CD",X"0A",X"05",X"2A",X"E7",X"9B",X"01",X"FA",X"00",X"A7",X"ED", + X"42",X"D8",X"3E",X"08",X"CD",X"09",X"11",X"3E",X"FF",X"32",X"E6",X"9B",X"3E",X"0F",X"32",X"66", + X"9A",X"3E",X"FF",X"32",X"8F",X"9C",X"AF",X"32",X"90",X"9C",X"32",X"EE",X"9B",X"2F",X"32",X"EF", + X"9B",X"3E",X"01",X"32",X"52",X"9A",X"CD",X"F2",X"12",X"C9",X"3A",X"E9",X"9B",X"FE",X"03",X"D2", + X"D7",X"06",X"3C",X"32",X"E9",X"9B",X"C9",X"AF",X"32",X"E9",X"9B",X"CD",X"A5",X"3A",X"3E",X"08", + X"CD",X"09",X"11",X"C9",X"3A",X"59",X"9A",X"E6",X"7F",X"C0",X"CD",X"63",X"08",X"CD",X"9D",X"08", + X"CD",X"16",X"09",X"CD",X"83",X"0A",X"CD",X"B1",X"0A",X"2A",X"E7",X"9B",X"23",X"22",X"E7",X"9B", + X"C9",X"CD",X"B5",X"10",X"CD",X"F2",X"12",X"CD",X"0D",X"13",X"CD",X"6B",X"12",X"CD",X"D9",X"11", + X"3E",X"01",X"32",X"81",X"A1",X"C9",X"CD",X"B5",X"10",X"CD",X"FB",X"10",X"CD",X"07",X"0F",X"CD", + X"F2",X"12",X"CD",X"0D",X"13",X"CD",X"F7",X"0F",X"CD",X"A3",X"12",X"21",X"00",X"00",X"22",X"5B", + X"9A",X"3E",X"0F",X"32",X"66",X"9A",X"3E",X"01",X"32",X"EA",X"9B",X"32",X"EB",X"9B",X"32",X"52", + X"9A",X"CD",X"D5",X"0C",X"AF",X"32",X"EC",X"9B",X"32",X"ED",X"9B",X"32",X"51",X"9A",X"32",X"53", + X"9A",X"32",X"E6",X"9B",X"32",X"8B",X"9C",X"32",X"8C",X"9C",X"CD",X"B3",X"12",X"3A",X"E3",X"9B", + X"A7",X"C2",X"77",X"07",X"AF",X"3A",X"5D",X"9A",X"32",X"90",X"9C",X"2F",X"32",X"EF",X"9B",X"32", + X"8F",X"9C",X"AF",X"32",X"EE",X"9B",X"C9",X"AF",X"32",X"5D",X"9A",X"32",X"EF",X"9B",X"32",X"90", + X"9C",X"32",X"92",X"9C",X"3E",X"FF",X"32",X"91",X"9C",X"32",X"8F",X"9C",X"C3",X"72",X"07",X"CD", + X"37",X"08",X"CD",X"0D",X"13",X"CD",X"F2",X"12",X"3A",X"E3",X"9B",X"A7",X"C2",X"BE",X"07",X"3A", + X"E4",X"9B",X"A7",X"CA",X"B0",X"07",X"3D",X"32",X"E4",X"9B",X"3E",X"0F",X"32",X"66",X"9A",X"C9", + X"CD",X"51",X"11",X"3E",X"08",X"CD",X"09",X"11",X"3E",X"FF",X"32",X"EE",X"9B",X"C9",X"3A",X"5D", + X"9A",X"A7",X"C2",X"FE",X"07",X"3A",X"E4",X"9B",X"A7",X"CA",X"E1",X"07",X"3D",X"32",X"E4",X"9B", + X"3A",X"EF",X"9B",X"A7",X"CA",X"F3",X"07",X"AF",X"32",X"5D",X"9A",X"3E",X"0F",X"32",X"66",X"9A", + X"C9",X"CD",X"43",X"11",X"3E",X"08",X"CD",X"09",X"11",X"3E",X"FF",X"32",X"EE",X"9B",X"3A",X"EF", + X"9B",X"A7",X"C0",X"3E",X"FF",X"32",X"5D",X"9A",X"3E",X"0F",X"32",X"66",X"9A",X"C9",X"3A",X"E5", + X"9B",X"A7",X"CA",X"1B",X"08",X"3D",X"32",X"E5",X"9B",X"3A",X"EE",X"9B",X"A7",X"CA",X"2D",X"08", + X"3E",X"FF",X"32",X"5D",X"9A",X"3E",X"0F",X"32",X"66",X"9A",X"C9",X"CD",X"4A",X"11",X"3E",X"08", + X"CD",X"09",X"11",X"3E",X"FF",X"32",X"EF",X"9B",X"3A",X"EE",X"9B",X"A7",X"C0",X"AF",X"32",X"5D", + X"9A",X"3E",X"0F",X"32",X"66",X"9A",X"C9",X"3A",X"5D",X"9A",X"A7",X"C2",X"44",X"08",X"11",X"67", + X"9A",X"C3",X"47",X"08",X"11",X"25",X"9B",X"3A",X"8B",X"9C",X"12",X"21",X"53",X"9A",X"13",X"7E", + X"12",X"13",X"21",X"40",X"9A",X"01",X"11",X"00",X"ED",X"B0",X"21",X"50",X"99",X"01",X"A0",X"00", + X"ED",X"B0",X"C9",X"3A",X"87",X"9C",X"A7",X"C0",X"DD",X"21",X"B3",X"40",X"ED",X"4B",X"E7",X"9B", + X"CB",X"21",X"CB",X"10",X"DD",X"09",X"DD",X"7E",X"00",X"FE",X"FF",X"CA",X"97",X"08",X"FE",X"F0", + X"CA",X"8D",X"08",X"DD",X"56",X"00",X"DD",X"5E",X"01",X"CD",X"9C",X"33",X"C9",X"DD",X"56",X"00", + X"DD",X"5E",X"01",X"CD",X"B0",X"33",X"C9",X"3E",X"FF",X"32",X"87",X"9C",X"C9",X"2A",X"E7",X"9B", + X"01",X"28",X"00",X"A7",X"ED",X"42",X"D8",X"DD",X"21",X"E7",X"42",X"0E",X"07",X"DD",X"5E",X"00", + X"DD",X"56",X"01",X"A7",X"ED",X"52",X"CA",X"C4",X"08",X"DD",X"23",X"DD",X"23",X"DD",X"23",X"0D", + X"C2",X"AD",X"08",X"C9",X"DD",X"4E",X"02",X"06",X"00",X"CB",X"21",X"CB",X"10",X"DD",X"21",X"FC", + X"42",X"DD",X"09",X"DD",X"6E",X"00",X"DD",X"66",X"01",X"E5",X"E5",X"E5",X"E5",X"FD",X"E1",X"DD", + X"E1",X"0E",X"0C",X"DD",X"6E",X"00",X"DD",X"66",X"01",X"FD",X"7E",X"18",X"77",X"DD",X"23",X"DD", + X"23",X"FD",X"23",X"0D",X"C2",X"E3",X"08",X"DD",X"E1",X"FD",X"E1",X"11",X"00",X"08",X"0E",X"0C", + X"DD",X"6E",X"00",X"DD",X"66",X"01",X"19",X"FD",X"7E",X"24",X"77",X"DD",X"23",X"DD",X"23",X"FD", + X"23",X"0D",X"C2",X"00",X"09",X"C9",X"3A",X"88",X"9C",X"A7",X"C0",X"2A",X"E7",X"9B",X"01",X"64", + X"00",X"A7",X"ED",X"42",X"D8",X"01",X"24",X"43",X"CB",X"25",X"CB",X"14",X"09",X"E5",X"DD",X"E1", + X"DD",X"7E",X"00",X"FE",X"FF",X"CA",X"7D",X"0A",X"57",X"DD",X"5E",X"01",X"F5",X"CD",X"82",X"34", + X"F1",X"32",X"63",X"9A",X"47",X"3A",X"62",X"9A",X"4F",X"3E",X"01",X"32",X"62",X"9A",X"78",X"FE", + X"40",X"CA",X"84",X"09",X"FE",X"60",X"CA",X"A3",X"09",X"FE",X"70",X"CA",X"C2",X"09",X"FE",X"90", + X"CA",X"E1",X"09",X"FE",X"A0",X"CA",X"39",X"0A",X"FE",X"B0",X"CA",X"45",X"0A",X"FE",X"C0",X"CA", + X"51",X"0A",X"FE",X"F0",X"D2",X"7C",X"09",X"79",X"32",X"62",X"9A",X"C9",X"DD",X"5E",X"01",X"57", + X"CD",X"B0",X"33",X"C9",X"21",X"6B",X"45",X"CD",X"84",X"10",X"16",X"28",X"1E",X"88",X"26",X"8B", + X"2E",X"10",X"3E",X"00",X"CD",X"62",X"32",X"DD",X"21",X"97",X"41",X"FD",X"21",X"BB",X"41",X"CD", + X"5D",X"0A",X"C9",X"21",X"82",X"45",X"CD",X"84",X"10",X"16",X"28",X"1E",X"A0",X"26",X"AF",X"2E", + X"13",X"3E",X"01",X"CD",X"62",X"32",X"DD",X"21",X"C7",X"41",X"FD",X"21",X"EB",X"41",X"CD",X"5D", + X"0A",X"C9",X"21",X"93",X"45",X"CD",X"84",X"10",X"16",X"28",X"1E",X"B8",X"26",X"67",X"2E",X"12", + X"3E",X"02",X"CD",X"62",X"32",X"DD",X"21",X"F7",X"41",X"FD",X"21",X"1B",X"42",X"CD",X"5D",X"0A", + X"C9",X"21",X"A4",X"45",X"CD",X"84",X"10",X"CD",X"F6",X"09",X"DD",X"21",X"27",X"42",X"FD",X"21", + X"4B",X"42",X"CD",X"5D",X"0A",X"C9",X"FD",X"21",X"67",X"84",X"DD",X"21",X"BC",X"4C",X"DD",X"E5", + X"11",X"04",X"00",X"3E",X"06",X"DD",X"4E",X"00",X"FD",X"71",X"00",X"DD",X"4E",X"01",X"FD",X"71", + X"20",X"DD",X"4E",X"02",X"FD",X"71",X"40",X"DD",X"4E",X"03",X"FD",X"71",X"60",X"DD",X"19",X"FD", + X"2B",X"3D",X"C8",X"FE",X"03",X"C2",X"05",X"0A",X"DD",X"E1",X"11",X"0C",X"00",X"DD",X"19",X"11", + X"04",X"00",X"FD",X"21",X"67",X"8C",X"C3",X"05",X"0A",X"DD",X"21",X"B7",X"42",X"FD",X"21",X"DB", + X"42",X"CD",X"5D",X"0A",X"C9",X"DD",X"21",X"57",X"42",X"FD",X"21",X"7B",X"42",X"CD",X"5D",X"0A", + X"C9",X"DD",X"21",X"87",X"42",X"FD",X"21",X"AB",X"42",X"CD",X"5D",X"0A",X"C9",X"11",X"00",X"08", + X"06",X"04",X"0E",X"0C",X"DD",X"6E",X"00",X"DD",X"66",X"01",X"FD",X"7E",X"00",X"E6",X"F0",X"80", + X"19",X"77",X"DD",X"23",X"DD",X"23",X"FD",X"23",X"0D",X"C2",X"64",X"0A",X"C9",X"3E",X"FF",X"32", + X"88",X"9C",X"C9",X"2A",X"E7",X"9B",X"01",X"64",X"00",X"A7",X"ED",X"42",X"C0",X"21",X"23",X"85", + X"FD",X"21",X"23",X"8D",X"DD",X"21",X"0A",X"43",X"0E",X"0D",X"11",X"20",X"00",X"DD",X"7E",X"00", + X"77",X"DD",X"7E",X"0D",X"FD",X"77",X"00",X"DD",X"23",X"FD",X"19",X"19",X"0D",X"C2",X"9D",X"0A", + X"C9",X"3A",X"62",X"9A",X"A7",X"C8",X"4F",X"3C",X"32",X"62",X"9A",X"06",X"00",X"21",X"B5",X"45", + X"09",X"7E",X"FE",X"50",X"D2",X"D6",X"0A",X"5F",X"3A",X"63",X"9A",X"57",X"26",X"08",X"2E",X"00", + X"3E",X"00",X"CD",X"0E",X"32",X"C9",X"AF",X"32",X"62",X"9A",X"C9",X"21",X"17",X"9C",X"CB",X"C6", + X"C9",X"3A",X"E6",X"9B",X"A7",X"C0",X"21",X"17",X"9C",X"CB",X"CE",X"C9",X"3A",X"E6",X"9B",X"A7", + X"C4",X"36",X"0B",X"3A",X"17",X"9C",X"47",X"3E",X"00",X"32",X"17",X"9C",X"CB",X"40",X"C2",X"4E", + X"0B",X"CB",X"48",X"C2",X"49",X"0B",X"3A",X"16",X"9C",X"CB",X"47",X"C2",X"53",X"0B",X"3A",X"16", + X"9C",X"47",X"CB",X"F8",X"CB",X"80",X"CD",X"3C",X"0B",X"AF",X"32",X"16",X"9C",X"78",X"32",X"00", + X"A1",X"3E",X"01",X"32",X"80",X"A1",X"00",X"00",X"00",X"AF",X"32",X"80",X"A1",X"00",X"00",X"00", + X"3E",X"01",X"32",X"80",X"A1",X"C9",X"3E",X"00",X"32",X"16",X"9C",X"C9",X"3A",X"15",X"9C",X"A7", + X"3E",X"00",X"32",X"15",X"9C",X"C8",X"CB",X"C0",X"C9",X"3E",X"02",X"C3",X"1E",X"0B",X"3E",X"01", + X"C3",X"1E",X"0B",X"AF",X"32",X"16",X"9C",X"3E",X"04",X"C3",X"1E",X"0B",X"DD",X"21",X"CD",X"45", + X"FD",X"21",X"00",X"00",X"0E",X"30",X"3E",X"00",X"DD",X"86",X"00",X"FD",X"86",X"00",X"DD",X"23", + X"FD",X"23",X"0D",X"C2",X"68",X"0B",X"FE",X"F3",X"C8",X"21",X"CD",X"45",X"CD",X"84",X"10",X"21", + X"DD",X"45",X"CD",X"84",X"10",X"C3",X"79",X"0B",X"3A",X"E6",X"9B",X"A7",X"C0",X"3A",X"56",X"9A", + X"32",X"55",X"9A",X"3A",X"58",X"9A",X"32",X"57",X"9A",X"AF",X"32",X"56",X"9A",X"32",X"58",X"9A", + X"32",X"54",X"9A",X"3A",X"E3",X"9B",X"A7",X"CA",X"DE",X"0B",X"3A",X"00",X"9C",X"A7",X"C2",X"DE", + X"0B",X"3A",X"5D",X"9A",X"A7",X"CA",X"DE",X"0B",X"3A",X"80",X"A0",X"CB",X"5F",X"CC",X"37",X"0C", + X"CD",X"13",X"0C",X"3A",X"00",X"A0",X"CB",X"47",X"CA",X"1F",X"0C",X"3A",X"80",X"A0",X"CB",X"4F", + X"CA",X"25",X"0C",X"CB",X"6F",X"CA",X"2B",X"0C",X"CB",X"67",X"CA",X"31",X"0C",X"C9",X"3A",X"00", + X"A0",X"CB",X"5F",X"CC",X"37",X"0C",X"CD",X"07",X"0C",X"3A",X"80",X"A0",X"CB",X"47",X"CA",X"1F", + X"0C",X"3A",X"00",X"A0",X"CB",X"6F",X"CA",X"31",X"0C",X"CB",X"67",X"CA",X"2B",X"0C",X"3A",X"00", + X"A1",X"CB",X"7F",X"CA",X"25",X"0C",X"C9",X"3A",X"00",X"A1",X"CB",X"77",X"C0",X"3E",X"FF",X"32", + X"58",X"9A",X"C9",X"3A",X"80",X"A0",X"CB",X"57",X"C0",X"3E",X"FF",X"32",X"58",X"9A",X"C9",X"3E", + X"10",X"32",X"54",X"9A",X"C9",X"3E",X"20",X"32",X"54",X"9A",X"C9",X"3E",X"02",X"32",X"54",X"9A", + X"C9",X"3E",X"01",X"32",X"54",X"9A",X"C9",X"3E",X"FF",X"32",X"56",X"9A",X"C9",X"CD",X"5B",X"0C", + X"CD",X"32",X"0D",X"CD",X"BE",X"0D",X"3A",X"5D",X"9A",X"A7",X"C2",X"54",X"0C",X"3A",X"EA",X"9B", + X"32",X"52",X"9A",X"C9",X"3A",X"EB",X"9B",X"32",X"52",X"9A",X"C9",X"3A",X"5D",X"9A",X"A7",X"C2", + X"6D",X"0C",X"DD",X"21",X"0D",X"9C",X"FD",X"21",X"01",X"9C",X"C3",X"78",X"0C",X"DD",X"21",X"10", + X"9C",X"FD",X"21",X"07",X"9C",X"C3",X"78",X"0C",X"3A",X"FD",X"9B",X"A7",X"C2",X"D5",X"0C",X"2A", + X"5B",X"9A",X"7C",X"B5",X"C8",X"DD",X"7E",X"02",X"85",X"27",X"DD",X"77",X"02",X"DD",X"7E",X"01", + X"8C",X"27",X"DD",X"77",X"01",X"06",X"00",X"DD",X"7E",X"00",X"88",X"27",X"DD",X"77",X"00",X"21", + X"00",X"00",X"22",X"5B",X"9A",X"DD",X"E5",X"E1",X"AF",X"ED",X"6F",X"FD",X"77",X"00",X"ED",X"67", + X"7E",X"E6",X"0F",X"FD",X"77",X"01",X"23",X"ED",X"6F",X"FD",X"77",X"02",X"ED",X"67",X"7E",X"E6", + X"0F",X"FD",X"77",X"03",X"23",X"ED",X"6F",X"FD",X"77",X"04",X"ED",X"67",X"7E",X"E6",X"0F",X"FD", + X"77",X"05",X"CD",X"D1",X"0E",X"3A",X"5D",X"9A",X"A7",X"C2",X"E6",X"0C",X"21",X"66",X"80",X"FD", + X"21",X"01",X"9C",X"C3",X"ED",X"0C",X"21",X"E6",X"82",X"FD",X"21",X"07",X"9C",X"11",X"20",X"00", + X"06",X"06",X"FD",X"7E",X"00",X"77",X"19",X"FD",X"23",X"05",X"C2",X"F2",X"0C",X"3A",X"52",X"9A", + X"CB",X"47",X"CA",X"1C",X"0D",X"11",X"00",X"08",X"19",X"11",X"E0",X"FF",X"19",X"06",X"06",X"36", + X"00",X"19",X"05",X"C2",X"0F",X"0D",X"19",X"AF",X"32",X"FD",X"9B",X"C9",X"11",X"00",X"08",X"19", + X"11",X"E0",X"FF",X"19",X"06",X"06",X"36",X"10",X"19",X"05",X"C2",X"26",X"0D",X"AF",X"32",X"FD", + X"9B",X"C9",X"3A",X"E3",X"9B",X"A7",X"C8",X"3A",X"5D",X"9A",X"A7",X"C2",X"81",X"0D",X"DD",X"21", + X"67",X"80",X"FD",X"21",X"E7",X"82",X"01",X"01",X"02",X"3A",X"59",X"9A",X"5F",X"E6",X"3F",X"CA", + X"8F",X"0D",X"7B",X"C6",X"20",X"E6",X"3F",X"C0",X"DD",X"71",X"00",X"DD",X"36",X"20",X"1E",X"DD", + X"36",X"40",X"19",X"01",X"00",X"08",X"DD",X"09",X"06",X"03",X"3A",X"52",X"9A",X"CB",X"47",X"CC", + X"7C",X"0D",X"DD",X"70",X"00",X"DD",X"70",X"20",X"DD",X"70",X"40",X"C9",X"3E",X"FF",X"CB",X"E0", + X"C9",X"DD",X"21",X"E7",X"82",X"FD",X"21",X"67",X"80",X"01",X"02",X"01",X"C3",X"49",X"0D",X"3E", + X"7F",X"DD",X"77",X"00",X"DD",X"77",X"20",X"DD",X"77",X"40",X"FD",X"70",X"00",X"FD",X"36",X"20", + X"1E",X"FD",X"36",X"40",X"19",X"01",X"00",X"08",X"FD",X"09",X"06",X"03",X"3A",X"52",X"9A",X"CB", + X"47",X"CC",X"7C",X"0D",X"FD",X"70",X"00",X"FD",X"70",X"20",X"FD",X"70",X"40",X"C9",X"DD",X"21", + X"0D",X"9C",X"FD",X"21",X"10",X"9C",X"DD",X"7E",X"00",X"FD",X"BE",X"00",X"DA",X"0E",X"0E",X"C2", + X"E7",X"0D",X"DD",X"7E",X"01",X"FD",X"BE",X"01",X"DA",X"0E",X"0E",X"C2",X"E7",X"0D",X"DD",X"7E", + X"02",X"FD",X"BE",X"02",X"DA",X"0E",X"0E",X"DD",X"21",X"0D",X"9C",X"FD",X"21",X"73",X"9C",X"DD", + X"7E",X"00",X"FD",X"BE",X"00",X"D8",X"C2",X"19",X"0E",X"DD",X"7E",X"01",X"FD",X"BE",X"01",X"D8", + X"C2",X"19",X"0E",X"DD",X"7E",X"02",X"FD",X"BE",X"02",X"D8",X"C8",X"C3",X"19",X"0E",X"DD",X"21", + X"10",X"9C",X"FD",X"21",X"73",X"9C",X"C3",X"EF",X"0D",X"DD",X"7E",X"00",X"DD",X"46",X"01",X"DD", + X"4E",X"02",X"FD",X"77",X"00",X"FD",X"70",X"01",X"FD",X"71",X"02",X"FD",X"E5",X"E1",X"DD",X"21", + X"6D",X"9C",X"AF",X"ED",X"6F",X"DD",X"77",X"00",X"ED",X"67",X"7E",X"E6",X"0F",X"DD",X"77",X"01", + X"23",X"ED",X"6F",X"DD",X"77",X"02",X"ED",X"67",X"7E",X"E6",X"0F",X"DD",X"77",X"03",X"23",X"ED", + X"6F",X"DD",X"77",X"04",X"ED",X"67",X"7E",X"E6",X"0F",X"DD",X"77",X"05",X"3A",X"E3",X"9B",X"A7", + X"C2",X"6D",X"0E",X"21",X"87",X"81",X"DD",X"21",X"6D",X"9C",X"C3",X"77",X"0E",X"21",X"87",X"81", + X"DD",X"21",X"6D",X"9C",X"C3",X"77",X"0E",X"11",X"20",X"00",X"E5",X"36",X"11",X"19",X"36",X"12", + X"19",X"36",X"4D",X"19",X"36",X"1C",X"19",X"36",X"0C",X"19",X"36",X"18",X"19",X"36",X"1B",X"19", + X"36",X"0E",X"19",X"E1",X"E5",X"2B",X"19",X"0E",X"06",X"DD",X"7E",X"00",X"77",X"19",X"DD",X"23", + X"0D",X"C2",X"99",X"0E",X"E1",X"01",X"00",X"08",X"09",X"E5",X"0E",X"08",X"06",X"08",X"3A",X"52", + X"9A",X"CB",X"47",X"CC",X"7C",X"0D",X"70",X"19",X"0D",X"C2",X"B6",X"0E",X"0E",X"07",X"E1",X"2B", + X"06",X"00",X"3A",X"52",X"9A",X"CB",X"47",X"CC",X"7C",X"0D",X"70",X"19",X"0D",X"C2",X"CA",X"0E", + X"C9",X"3A",X"5D",X"9A",X"A7",X"C2",X"E1",X"0E",X"11",X"EC",X"9B",X"21",X"E4",X"9B",X"C3",X"EA", + X"0E",X"11",X"ED",X"9B",X"21",X"E5",X"9B",X"C3",X"EA",X"0E",X"1A",X"A7",X"C0",X"FD",X"7E",X"00", + X"A7",X"C2",X"FD",X"0E",X"3A",X"FE",X"9B",X"47",X"FD",X"7E",X"01",X"B8",X"D8",X"7E",X"3C",X"77", + X"3E",X"FF",X"12",X"CD",X"F7",X"0F",X"C9",X"3A",X"FF",X"9B",X"E6",X"03",X"47",X"3A",X"E3",X"9B", + X"A7",X"C2",X"19",X"0F",X"0E",X"00",X"C3",X"1B",X"0F",X"0E",X"FF",X"78",X"FE",X"00",X"CA",X"2E", + X"0F",X"FE",X"01",X"CA",X"38",X"0F",X"FE",X"02",X"CA",X"42",X"0F",X"C3",X"4C",X"0F",X"3E",X"02", + X"32",X"E4",X"9B",X"A1",X"32",X"E5",X"9B",X"C9",X"3E",X"03",X"32",X"E4",X"9B",X"A1",X"32",X"E5", + X"9B",X"C9",X"3E",X"04",X"32",X"E4",X"9B",X"A1",X"32",X"E5",X"9B",X"C9",X"3E",X"05",X"32",X"E4", + X"9B",X"A1",X"32",X"E5",X"9B",X"C9",X"21",X"80",X"86",X"11",X"20",X"00",X"0E",X"08",X"FD",X"21", + X"4B",X"3D",X"FD",X"7E",X"00",X"77",X"19",X"FD",X"23",X"0D",X"C2",X"62",X"0F",X"21",X"80",X"8E", + X"3E",X"00",X"0E",X"0A",X"77",X"19",X"0D",X"C2",X"74",X"0F",X"3A",X"F6",X"9B",X"FE",X"64",X"D2", + X"A7",X"0F",X"A7",X"CA",X"B4",X"0F",X"47",X"0E",X"01",X"AF",X"81",X"27",X"05",X"C2",X"8A",X"0F", + X"FD",X"21",X"60",X"87",X"47",X"E6",X"0F",X"FD",X"77",X"20",X"78",X"CB",X"3F",X"CB",X"3F",X"CB", + X"3F",X"CB",X"3F",X"FD",X"77",X"00",X"C9",X"FD",X"21",X"60",X"87",X"3E",X"28",X"FD",X"77",X"00", + X"FD",X"77",X"20",X"C9",X"FD",X"21",X"60",X"87",X"AF",X"FD",X"77",X"20",X"C9",X"3A",X"E3",X"9B", + X"A7",X"CA",X"D7",X"0F",X"3A",X"00",X"9C",X"A7",X"C2",X"D7",X"0F",X"3A",X"5D",X"9A",X"A7",X"CA", + X"D7",X"0F",X"AF",X"32",X"83",X"A1",X"C9",X"3E",X"01",X"32",X"83",X"A1",X"C9",X"E5",X"DD",X"E1", + X"D9",X"DD",X"6E",X"02",X"DD",X"66",X"03",X"DD",X"4E",X"00",X"11",X"20",X"00",X"3E",X"FF",X"77", + X"19",X"0D",X"C2",X"EF",X"0F",X"D9",X"C9",X"3A",X"5D",X"9A",X"A7",X"C2",X"04",X"10",X"21",X"E4", + X"9B",X"C3",X"07",X"10",X"21",X"E5",X"9B",X"7E",X"A7",X"CA",X"4E",X"10",X"F5",X"CD",X"4E",X"10", + X"DD",X"21",X"41",X"84",X"11",X"40",X"00",X"F1",X"FE",X"08",X"D0",X"4F",X"DD",X"36",X"00",X"7C", + X"DD",X"36",X"FF",X"7B",X"DD",X"36",X"20",X"7E",X"DD",X"36",X"1F",X"7D",X"DD",X"E5",X"D5",X"11", + X"00",X"08",X"DD",X"19",X"DD",X"36",X"00",X"1C",X"DD",X"36",X"FF",X"1C",X"DD",X"36",X"20",X"1C", + X"DD",X"36",X"1F",X"1C",X"D1",X"DD",X"E1",X"DD",X"19",X"0D",X"C2",X"1C",X"10",X"C9",X"21",X"41", + X"84",X"11",X"20",X"00",X"3E",X"7A",X"0E",X"10",X"77",X"19",X"0D",X"C2",X"58",X"10",X"21",X"40", + X"84",X"0E",X"10",X"77",X"19",X"0D",X"C2",X"63",X"10",X"21",X"41",X"8C",X"3E",X"00",X"0E",X"10", + X"77",X"19",X"0D",X"C2",X"70",X"10",X"21",X"40",X"8C",X"0E",X"10",X"3E",X"00",X"77",X"19",X"0D", + X"C2",X"7D",X"10",X"C9",X"E5",X"DD",X"E1",X"D9",X"DD",X"46",X"00",X"DD",X"4E",X"01",X"DD",X"6E", + X"02",X"DD",X"66",X"03",X"E5",X"C5",X"11",X"20",X"00",X"DD",X"7E",X"04",X"77",X"19",X"DD",X"23", + X"05",X"C2",X"99",X"10",X"C1",X"E1",X"11",X"00",X"08",X"19",X"11",X"20",X"00",X"71",X"19",X"05", + X"C2",X"AD",X"10",X"D9",X"C9",X"21",X"40",X"80",X"0E",X"FF",X"11",X"80",X"07",X"71",X"23",X"1B", + X"7A",X"B3",X"C2",X"BD",X"10",X"21",X"40",X"88",X"0E",X"00",X"11",X"80",X"07",X"71",X"23",X"1B", + X"7A",X"B3",X"C2",X"CD",X"10",X"C9",X"CD",X"E0",X"10",X"21",X"00",X"50",X"22",X"5B",X"9A",X"C9", + X"3A",X"5D",X"9A",X"A7",X"C2",X"F1",X"10",X"3A",X"EA",X"9B",X"C6",X"01",X"27",X"32",X"EA",X"9B", + X"C9",X"3A",X"EB",X"9B",X"C6",X"01",X"27",X"32",X"EB",X"9B",X"C9",X"21",X"01",X"9C",X"11",X"02", + X"9C",X"01",X"12",X"00",X"AF",X"77",X"ED",X"B0",X"C9",X"06",X"FF",X"0E",X"FF",X"0D",X"C2",X"0D", + X"11",X"05",X"C2",X"0B",X"11",X"3D",X"C2",X"09",X"11",X"C9",X"21",X"00",X"80",X"01",X"FF",X"07", + X"16",X"FF",X"72",X"23",X"0B",X"78",X"B1",X"C2",X"22",X"11",X"C9",X"3A",X"5D",X"9A",X"F5",X"AF", + X"32",X"5D",X"9A",X"CD",X"D5",X"0C",X"3E",X"FF",X"32",X"5D",X"9A",X"CD",X"D5",X"0C",X"F1",X"32", + X"5D",X"9A",X"C9",X"21",X"6A",X"3D",X"CD",X"84",X"10",X"C9",X"21",X"7E",X"3D",X"CD",X"84",X"10", + X"C9",X"21",X"92",X"3D",X"CD",X"84",X"10",X"C9",X"21",X"9F",X"3D",X"CD",X"84",X"10",X"C9",X"3A", + X"00",X"A0",X"CB",X"7F",X"3E",X"00",X"28",X"14",X"3A",X"13",X"9C",X"A7",X"CA",X"80",X"11",X"32", + X"15",X"9C",X"2F",X"32",X"13",X"9C",X"CD",X"9F",X"02",X"C3",X"80",X"11",X"2F",X"32",X"13",X"9C", + X"3A",X"00",X"A0",X"CB",X"77",X"3E",X"00",X"28",X"14",X"3A",X"14",X"9C",X"A7",X"CA",X"A1",X"11", + X"32",X"15",X"9C",X"2F",X"32",X"14",X"9C",X"CD",X"C3",X"02",X"C3",X"A1",X"11",X"2F",X"32",X"14", + X"9C",X"3A",X"00",X"A0",X"CB",X"67",X"C3",X"BD",X"11",X"3A",X"19",X"9C",X"A7",X"C0",X"2F",X"32", + X"19",X"9C",X"32",X"15",X"9C",X"3A",X"F6",X"9B",X"3C",X"32",X"F6",X"9B",X"C9",X"AF",X"32",X"19", + X"9C",X"C9",X"3A",X"80",X"A0",X"CB",X"7F",X"CA",X"D3",X"11",X"CB",X"77",X"C0",X"3E",X"FF",X"32", + X"F3",X"9B",X"C9",X"3E",X"FF",X"32",X"F2",X"9B",X"C9",X"3A",X"80",X"A1",X"2F",X"32",X"FF",X"9B", + X"5F",X"3A",X"00",X"A1",X"2F",X"57",X"CD",X"F3",X"11",X"CD",X"23",X"12",X"CD",X"48",X"12",X"CD", + X"59",X"12",X"C9",X"7B",X"CB",X"3F",X"CB",X"3F",X"E6",X"07",X"21",X"F4",X"9B",X"FE",X"00",X"CA", + X"2C",X"12",X"FE",X"01",X"CA",X"30",X"12",X"FE",X"02",X"CA",X"34",X"12",X"FE",X"03",X"CA",X"38", + X"12",X"FE",X"04",X"CA",X"3C",X"12",X"FE",X"05",X"CA",X"40",X"12",X"FE",X"06",X"CA",X"44",X"12", + X"36",X"FF",X"C9",X"21",X"F5",X"9B",X"7A",X"E6",X"07",X"C3",X"FD",X"11",X"3E",X"00",X"77",X"C9", + X"3E",X"01",X"77",X"C9",X"3E",X"02",X"77",X"C9",X"3E",X"03",X"77",X"C9",X"3E",X"04",X"77",X"C9", + X"3E",X"05",X"77",X"C9",X"3E",X"06",X"77",X"C9",X"7B",X"CB",X"7F",X"C2",X"53",X"12",X"AF",X"32", + X"00",X"9C",X"C9",X"3E",X"FF",X"32",X"00",X"9C",X"C9",X"7B",X"CB",X"5F",X"C2",X"65",X"12",X"3E", + X"03",X"32",X"FE",X"9B",X"C9",X"3E",X"05",X"32",X"FE",X"9B",X"C9",X"21",X"BC",X"3D",X"11",X"1A", + X"9C",X"01",X"10",X"00",X"ED",X"B0",X"21",X"CC",X"3D",X"11",X"2A",X"9C",X"01",X"10",X"00",X"ED", + X"B0",X"21",X"DC",X"3D",X"11",X"3A",X"9C",X"01",X"10",X"00",X"ED",X"B0",X"21",X"EC",X"3D",X"11", + X"4A",X"9C",X"01",X"10",X"00",X"ED",X"B0",X"21",X"FC",X"3D",X"11",X"5A",X"9C",X"01",X"10",X"00", + X"ED",X"B0",X"C9",X"21",X"37",X"3F",X"11",X"40",X"9A",X"01",X"11",X"00",X"ED",X"B0",X"AF",X"32", + X"53",X"9A",X"C9",X"DD",X"21",X"20",X"9A",X"DD",X"36",X"03",X"80",X"DD",X"36",X"04",X"80",X"DD", + X"36",X"00",X"FF",X"16",X"80",X"1E",X"E8",X"26",X"D3",X"2E",X"1A",X"3E",X"00",X"CD",X"62",X"32", + X"C9",X"DD",X"21",X"40",X"9A",X"0E",X"08",X"06",X"01",X"50",X"C5",X"DD",X"7E",X"01",X"A7",X"F5", + X"CC",X"51",X"36",X"F1",X"C4",X"A6",X"36",X"C1",X"DD",X"23",X"DD",X"23",X"04",X"0D",X"C2",X"D9", + X"12",X"C9",X"21",X"00",X"80",X"0E",X"40",X"06",X"FF",X"70",X"23",X"0D",X"C2",X"F9",X"12",X"21", + X"00",X"88",X"0E",X"40",X"06",X"FF",X"70",X"23",X"0D",X"C2",X"06",X"13",X"C9",X"21",X"00",X"98", + X"11",X"01",X"98",X"01",X"3F",X"02",X"36",X"00",X"ED",X"B0",X"DD",X"21",X"00",X"98",X"FD",X"21", + X"3B",X"3E",X"0E",X"09",X"11",X"10",X"00",X"CD",X"C3",X"13",X"DD",X"19",X"FD",X"23",X"FD",X"23", + X"FD",X"23",X"0D",X"C2",X"27",X"13",X"DD",X"21",X"90",X"98",X"FD",X"21",X"56",X"3E",X"0E",X"02", + X"11",X"10",X"00",X"CD",X"C3",X"13",X"DD",X"19",X"FD",X"23",X"FD",X"23",X"FD",X"23",X"0D",X"C2", + X"43",X"13",X"DD",X"21",X"B0",X"98",X"FD",X"21",X"68",X"3E",X"0E",X"05",X"11",X"20",X"00",X"CD", + X"E9",X"13",X"DD",X"19",X"FD",X"23",X"FD",X"23",X"FD",X"23",X"0D",X"C2",X"5F",X"13",X"DD",X"21", + X"50",X"99",X"FD",X"21",X"86",X"3E",X"0E",X"05",X"11",X"20",X"00",X"CD",X"F6",X"13",X"DD",X"19", + X"FD",X"23",X"FD",X"23",X"FD",X"23",X"0D",X"C2",X"7B",X"13",X"DD",X"21",X"F0",X"99",X"FD",X"21", + X"5C",X"3E",X"0E",X"03",X"11",X"10",X"00",X"CD",X"E9",X"13",X"DD",X"19",X"FD",X"23",X"FD",X"23", + X"FD",X"23",X"0D",X"C2",X"97",X"13",X"DD",X"21",X"20",X"9A",X"FD",X"21",X"65",X"3E",X"0E",X"01", + X"11",X"20",X"00",X"CD",X"E9",X"13",X"DD",X"19",X"FD",X"23",X"FD",X"23",X"FD",X"23",X"0D",X"C2", + X"B3",X"13",X"C9",X"FD",X"7E",X"00",X"DD",X"77",X"01",X"FD",X"7E",X"01",X"DD",X"77",X"02",X"FD", + X"7E",X"02",X"DD",X"77",X"0E",X"C9",X"FD",X"7E",X"00",X"DD",X"77",X"01",X"FD",X"7E",X"01",X"DD", + X"77",X"02",X"FD",X"7E",X"02",X"DD",X"77",X"03",X"C9",X"FD",X"7E",X"00",X"DD",X"77",X"01",X"FD", + X"7E",X"01",X"DD",X"77",X"02",X"C9",X"FD",X"7E",X"00",X"DD",X"77",X"01",X"FD",X"7E",X"01",X"DD", + X"77",X"02",X"FD",X"7E",X"02",X"DD",X"77",X"1F",X"C9",X"DD",X"21",X"50",X"99",X"01",X"20",X"00", + X"16",X"05",X"1E",X"00",X"DD",X"73",X"07",X"DD",X"09",X"15",X"C2",X"14",X"14",X"C9",X"3A",X"52", + X"9A",X"CB",X"47",X"CA",X"14",X"15",X"21",X"44",X"80",X"06",X"7F",X"0E",X"00",X"11",X"64",X"03", + X"70",X"23",X"1B",X"7B",X"B2",X"C2",X"30",X"14",X"21",X"44",X"88",X"11",X"64",X"03",X"71",X"23", + X"1B",X"7B",X"B2",X"C2",X"3E",X"14",X"DD",X"21",X"40",X"84",X"06",X"7A",X"0E",X"00",X"26",X"0B", + X"11",X"20",X"00",X"CD",X"B9",X"14",X"DD",X"21",X"40",X"8C",X"41",X"26",X"0B",X"11",X"20",X"00", + X"CD",X"B9",X"14",X"DD",X"21",X"4B",X"84",X"06",X"7F",X"26",X"11",X"11",X"20",X"00",X"CD",X"B9", + X"14",X"DD",X"21",X"4B",X"8C",X"26",X"11",X"06",X"00",X"CD",X"B9",X"14",X"DD",X"21",X"95",X"3E", + X"FD",X"21",X"CB",X"3E",X"0E",X"36",X"FD",X"6E",X"00",X"FD",X"66",X"01",X"DD",X"7E",X"00",X"77", + X"FD",X"23",X"FD",X"23",X"DD",X"23",X"0D",X"C2",X"86",X"14",X"DD",X"21",X"CB",X"3E",X"0E",X"36", + X"11",X"00",X"08",X"06",X"01",X"DD",X"6E",X"00",X"DD",X"66",X"01",X"19",X"70",X"DD",X"23",X"DD", + X"23",X"0D",X"C2",X"A5",X"14",X"CD",X"CF",X"14",X"C9",X"DD",X"E5",X"FD",X"E1",X"2E",X"1C",X"FD", + X"70",X"00",X"FD",X"19",X"2D",X"C2",X"BF",X"14",X"DD",X"23",X"25",X"C2",X"B9",X"14",X"C9",X"DD", + X"21",X"67",X"80",X"DD",X"36",X"00",X"01",X"DD",X"36",X"20",X"1E",X"DD",X"36",X"40",X"19",X"DD", + X"21",X"E7",X"82",X"DD",X"36",X"00",X"02",X"DD",X"36",X"20",X"1E",X"DD",X"36",X"40",X"19",X"06", + X"03",X"3A",X"52",X"9A",X"CB",X"47",X"CC",X"7C",X"0D",X"DD",X"21",X"67",X"88",X"FD",X"21",X"E7", + X"8A",X"DD",X"70",X"00",X"DD",X"70",X"20",X"DD",X"70",X"40",X"FD",X"70",X"00",X"FD",X"70",X"20", + X"FD",X"70",X"40",X"C9",X"21",X"44",X"80",X"06",X"7F",X"0E",X"10",X"11",X"64",X"03",X"70",X"23", + X"1B",X"7B",X"B2",X"C2",X"1E",X"15",X"21",X"44",X"88",X"11",X"64",X"03",X"71",X"23",X"1B",X"7B", + X"B2",X"C2",X"2C",X"15",X"DD",X"21",X"40",X"84",X"06",X"7A",X"0E",X"00",X"26",X"0B",X"11",X"20", + X"00",X"CD",X"B9",X"14",X"DD",X"21",X"40",X"8C",X"41",X"26",X"0B",X"11",X"20",X"00",X"CD",X"B9", + X"14",X"DD",X"21",X"4B",X"84",X"06",X"7F",X"26",X"11",X"11",X"20",X"00",X"CD",X"B9",X"14",X"DD", + X"21",X"4B",X"8C",X"26",X"11",X"06",X"10",X"CD",X"B9",X"14",X"CD",X"CF",X"14",X"C9",X"DD",X"21", + X"20",X"9A",X"CD",X"A1",X"15",X"CD",X"65",X"16",X"CD",X"D7",X"16",X"DD",X"7E",X"00",X"A7",X"C8", + X"DD",X"7E",X"05",X"A7",X"C0",X"CD",X"7F",X"17",X"DD",X"7E",X"06",X"A7",X"C0",X"CD",X"4B",X"18", + X"CD",X"8A",X"18",X"3A",X"59",X"9A",X"DD",X"86",X"02",X"DD",X"A6",X"01",X"C0",X"CD",X"D5",X"18", + X"C9",X"DD",X"7E",X"05",X"A7",X"C2",X"F4",X"15",X"0E",X"0B",X"FD",X"21",X"00",X"98",X"CD",X"C4", + X"15",X"11",X"10",X"00",X"FD",X"19",X"0D",X"C2",X"AE",X"15",X"DD",X"7E",X"05",X"A7",X"C8",X"DD", + X"36",X"06",X"3F",X"C9",X"FD",X"7E",X"00",X"A7",X"C8",X"21",X"E4",X"45",X"FD",X"46",X"04",X"3E", + X"E8",X"96",X"B8",X"D0",X"23",X"3E",X"E8",X"86",X"B8",X"D8",X"23",X"FD",X"46",X"03",X"DD",X"7E", + X"03",X"57",X"96",X"B8",X"D0",X"23",X"7A",X"86",X"B8",X"D8",X"DD",X"36",X"05",X"FF",X"21",X"16", + X"9C",X"CB",X"C6",X"C9",X"3A",X"59",X"9A",X"DD",X"86",X"02",X"DD",X"A6",X"01",X"C0",X"21",X"16", + X"9C",X"CB",X"C6",X"DD",X"7E",X"06",X"FE",X"30",X"CA",X"50",X"16",X"D2",X"1B",X"16",X"FE",X"20", + X"CA",X"57",X"16",X"FE",X"10",X"CA",X"5E",X"16",X"C3",X"1F",X"16",X"DD",X"36",X"0F",X"E3",X"DD", + X"56",X"03",X"1E",X"E8",X"DD",X"66",X"0F",X"2E",X"19",X"3E",X"00",X"CD",X"62",X"32",X"DD",X"35", + X"06",X"C0",X"3E",X"FF",X"32",X"51",X"9A",X"DD",X"36",X"05",X"00",X"DD",X"36",X"00",X"00",X"DD", + X"36",X"07",X"00",X"DD",X"36",X"09",X"00",X"DD",X"36",X"0F",X"D3",X"DD",X"36",X"12",X"00",X"C9", + X"DD",X"36",X"0F",X"E7",X"C3",X"1F",X"16",X"DD",X"36",X"0F",X"EB",X"C3",X"1F",X"16",X"DD",X"36", + X"0F",X"EF",X"C3",X"1F",X"16",X"DD",X"7E",X"07",X"A7",X"C8",X"3A",X"59",X"9A",X"E6",X"01",X"C0", + X"DD",X"7E",X"08",X"D6",X"02",X"DD",X"77",X"08",X"06",X"05",X"CD",X"8A",X"16",X"DD",X"7E",X"08", + X"C6",X"08",X"06",X"06",X"CD",X"8A",X"16",X"C3",X"97",X"16",X"DD",X"56",X"1E",X"5F",X"26",X"0B", + X"2E",X"00",X"78",X"CD",X"0E",X"32",X"C9",X"FD",X"21",X"25",X"46",X"06",X"00",X"0E",X"06",X"DD", + X"66",X"1E",X"DD",X"6E",X"08",X"CD",X"B7",X"16",X"78",X"A7",X"C2",X"C8",X"16",X"0D",X"C8",X"11", + X"03",X"00",X"FD",X"19",X"C3",X"A5",X"16",X"7D",X"FD",X"BE",X"00",X"D0",X"7C",X"FD",X"BE",X"01", + X"D8",X"FD",X"BE",X"02",X"D0",X"06",X"FF",X"C9",X"DD",X"36",X"07",X"00",X"3E",X"05",X"CD",X"5D", + X"18",X"3E",X"06",X"CD",X"5D",X"18",X"C9",X"DD",X"7E",X"09",X"A7",X"C8",X"3A",X"59",X"9A",X"E6", + X"01",X"C0",X"DD",X"7E",X"1D",X"A7",X"C2",X"5F",X"17",X"DD",X"7E",X"0C",X"A7",X"C2",X"01",X"17", + X"DD",X"7E",X"0B",X"DD",X"BE",X"11",X"DA",X"01",X"17",X"D6",X"02",X"DD",X"77",X"0B",X"C3",X"37", + X"17",X"DD",X"66",X"0E",X"DD",X"6E",X"0D",X"E5",X"FD",X"E1",X"DD",X"7E",X"0C",X"A7",X"CA",X"22", + X"17",X"11",X"02",X"00",X"FD",X"19",X"3D",X"C2",X"11",X"17",X"FD",X"7E",X"00",X"FE",X"80",X"CA", + X"47",X"17",X"DD",X"7E",X"0B",X"FD",X"86",X"00",X"DD",X"77",X"0B",X"FD",X"7E",X"01",X"DD",X"86", + X"0A",X"DD",X"77",X"0A",X"DD",X"34",X"0C",X"DD",X"56",X"0A",X"DD",X"5E",X"0B",X"26",X"0C",X"2E", + X"00",X"3E",X"04",X"CD",X"0E",X"32",X"C9",X"DD",X"36",X"1D",X"FF",X"DD",X"36",X"0C",X"03",X"DD", + X"56",X"0A",X"DD",X"5E",X"0B",X"26",X"0A",X"2E",X"00",X"3E",X"04",X"CD",X"0E",X"32",X"C9",X"DD", + X"35",X"0C",X"C0",X"DD",X"36",X"09",X"00",X"DD",X"36",X"1D",X"00",X"16",X"08",X"DD",X"72",X"0A", + X"1E",X"10",X"DD",X"73",X"0B",X"26",X"0F",X"2E",X"00",X"3E",X"04",X"CD",X"0E",X"32",X"C9",X"DD", + X"7E",X"06",X"FE",X"FF",X"C0",X"3A",X"59",X"9A",X"DD",X"86",X"02",X"DD",X"A6",X"01",X"C0",X"FD", + X"21",X"CE",X"4F",X"06",X"00",X"DD",X"7E",X"12",X"D6",X"03",X"A7",X"CA",X"A6",X"17",X"FD",X"23", + X"FD",X"23",X"3D",X"C2",X"9E",X"17",X"FD",X"6E",X"00",X"FD",X"66",X"01",X"E5",X"FD",X"E1",X"FD", + X"6E",X"0D",X"FD",X"66",X"0E",X"FD",X"7E",X"0C",X"A7",X"CA",X"C4",X"17",X"11",X"04",X"00",X"19", + X"3D",X"C2",X"BC",X"17",X"7E",X"FE",X"80",X"CA",X"1B",X"18",X"FD",X"86",X"04",X"FD",X"77",X"04", + X"5F",X"23",X"7E",X"FD",X"86",X"03",X"FD",X"77",X"03",X"57",X"23",X"46",X"23",X"4E",X"C5",X"E1", + X"FD",X"74",X"0F",X"DD",X"7E",X"12",X"CD",X"62",X"32",X"FD",X"34",X"0C",X"FD",X"7E",X"0B",X"FE", + X"10",X"C2",X"00",X"18",X"DD",X"7E",X"03",X"D6",X"03",X"FD",X"BE",X"03",X"D0",X"C3",X"09",X"18", + X"DD",X"7E",X"03",X"C6",X"03",X"FD",X"BE",X"03",X"D8",X"DD",X"7E",X"03",X"D6",X"02",X"57",X"1E", + X"DE",X"26",X"09",X"2E",X"00",X"3E",X"06",X"CD",X"0E",X"32",X"C9",X"DD",X"36",X"06",X"3F",X"DD", + X"36",X"05",X"FF",X"21",X"16",X"9C",X"CB",X"C6",X"16",X"F8",X"1E",X"F0",X"26",X"FF",X"FD",X"74", + X"0F",X"2E",X"0F",X"DD",X"7E",X"12",X"CD",X"62",X"32",X"3E",X"06",X"CD",X"5D",X"18",X"FD",X"36", + X"05",X"FF",X"FD",X"36",X"06",X"1E",X"FD",X"36",X"1E",X"00",X"C9",X"DD",X"7E",X"07",X"A7",X"C0", + X"3E",X"05",X"CD",X"5D",X"18",X"3E",X"06",X"CD",X"5D",X"18",X"C3",X"6C",X"18",X"16",X"08",X"1E", + X"10",X"DD",X"73",X"08",X"26",X"0F",X"2E",X"00",X"CD",X"0E",X"32",X"C9",X"3A",X"57",X"9A",X"A7", + X"C0",X"3A",X"58",X"9A",X"A7",X"C8",X"DD",X"36",X"07",X"FF",X"DD",X"36",X"08",X"DA",X"DD",X"7E", + X"03",X"DD",X"77",X"1E",X"21",X"16",X"9C",X"CB",X"D6",X"C9",X"DD",X"7E",X"09",X"A7",X"C0",X"16", + X"08",X"1E",X"10",X"DD",X"73",X"0B",X"26",X"0F",X"2E",X"00",X"3E",X"04",X"CD",X"0E",X"32",X"3A", + X"55",X"9A",X"A7",X"C0",X"3A",X"56",X"9A",X"A7",X"C8",X"DD",X"36",X"09",X"FF",X"DD",X"7E",X"03", + X"DD",X"77",X"0A",X"C6",X"10",X"DD",X"77",X"10",X"DD",X"7E",X"04",X"DD",X"77",X"11",X"DD",X"36", + X"0B",X"DA",X"DD",X"36",X"0C",X"00",X"21",X"FC",X"45",X"DD",X"75",X"0D",X"DD",X"74",X"0E",X"21", + X"16",X"9C",X"CB",X"CE",X"C9",X"3A",X"54",X"9A",X"CB",X"47",X"C2",X"E9",X"18",X"CB",X"4F",X"C2", + X"03",X"19",X"DD",X"36",X"0F",X"D3",X"C3",X"2F",X"19",X"DD",X"7E",X"03",X"C6",X"01",X"FE",X"DE", + X"D2",X"FC",X"18",X"DD",X"77",X"03",X"CD",X"1D",X"19",X"C3",X"2F",X"19",X"DD",X"36",X"03",X"DE", + X"C3",X"2F",X"19",X"DD",X"7E",X"03",X"D6",X"01",X"FE",X"1C",X"DA",X"16",X"19",X"DD",X"77",X"03", + X"CD",X"1D",X"19",X"C3",X"2F",X"19",X"DD",X"36",X"03",X"1C",X"C3",X"2F",X"19",X"DD",X"7E",X"0F", + X"FE",X"D3",X"CA",X"2A",X"19",X"DD",X"36",X"0F",X"D3",X"C9",X"DD",X"36",X"0F",X"D7",X"C9",X"DD", + X"56",X"03",X"1E",X"E8",X"DD",X"66",X"0F",X"2E",X"1A",X"3E",X"00",X"CD",X"62",X"32",X"3A",X"54", + X"9A",X"CB",X"67",X"C2",X"4E",X"19",X"CB",X"6F",X"C2",X"65",X"19",X"C3",X"7C",X"19",X"DD",X"7E", + X"04",X"D6",X"01",X"FE",X"22",X"DA",X"5E",X"19",X"DD",X"77",X"04",X"C3",X"7C",X"19",X"DD",X"36", + X"04",X"22",X"C3",X"7C",X"19",X"DD",X"7E",X"04",X"C6",X"01",X"FE",X"96",X"D2",X"75",X"19",X"DD", + X"77",X"04",X"C3",X"7C",X"19",X"DD",X"36",X"04",X"96",X"C3",X"7C",X"19",X"DD",X"7E",X"03",X"C6", + X"10",X"57",X"DD",X"5E",X"04",X"CD",X"B5",X"31",X"C9",X"DD",X"21",X"B0",X"98",X"CD",X"B4",X"19", + X"DD",X"21",X"D0",X"98",X"CD",X"B4",X"19",X"DD",X"21",X"F0",X"98",X"CD",X"B4",X"19",X"DD",X"21", + X"10",X"99",X"CD",X"B4",X"19",X"DD",X"21",X"30",X"99",X"CD",X"B4",X"19",X"C9",X"CD",X"89",X"19", + X"CD",X"77",X"1F",X"C9",X"CD",X"CD",X"19",X"DD",X"7E",X"00",X"A7",X"C8",X"CD",X"43",X"1A",X"3A", + X"59",X"9A",X"DD",X"86",X"02",X"DD",X"A6",X"01",X"C0",X"CD",X"25",X"1B",X"C9",X"DD",X"7E",X"07", + X"A7",X"C8",X"DD",X"6E",X"08",X"DD",X"66",X"09",X"E5",X"FD",X"E1",X"FD",X"7E",X"00",X"A7",X"C8", + X"3A",X"59",X"9A",X"FD",X"86",X"02",X"FD",X"A6",X"01",X"C0",X"FD",X"7E",X"04",X"C6",X"08",X"FD", + X"77",X"04",X"FE",X"F0",X"D2",X"04",X"1A",X"DD",X"7E",X"12",X"A7",X"C2",X"15",X"1A",X"3E",X"FF", + X"CD",X"21",X"1A",X"C9",X"AF",X"CD",X"21",X"1A",X"FD",X"E5",X"E1",X"3E",X"0D",X"CD",X"70",X"20", + X"DD",X"36",X"07",X"00",X"C9",X"FD",X"7E",X"03",X"FD",X"86",X"08",X"FD",X"77",X"03",X"C3",X"FE", + X"19",X"A7",X"CA",X"36",X"1A",X"FD",X"7E",X"0E",X"FD",X"56",X"03",X"FD",X"5E",X"04",X"26",X"0D", + X"2E",X"00",X"CD",X"0E",X"32",X"C9",X"FD",X"7E",X"0E",X"11",X"F0",X"08",X"21",X"FF",X"FF",X"CD", + X"0E",X"32",X"C9",X"DD",X"7E",X"05",X"A7",X"C2",X"96",X"1A",X"CD",X"6E",X"31",X"A7",X"C8",X"FD", + X"21",X"20",X"9A",X"DD",X"7E",X"03",X"C6",X"06",X"FD",X"96",X"0A",X"DA",X"64",X"1A",X"FE",X"10", + X"D0",X"C3",X"67",X"1A",X"FE",X"10",X"D0",X"DD",X"7E",X"04",X"C6",X"00",X"FD",X"96",X"0B",X"DA", + X"78",X"1A",X"FE",X"10",X"D0",X"C3",X"7D",X"1A",X"ED",X"44",X"FE",X"10",X"D0",X"DD",X"36",X"05", + X"FF",X"DD",X"36",X"06",X"30",X"21",X"16",X"9C",X"CB",X"DE",X"3E",X"00",X"32",X"29",X"9A",X"CD", + X"60",X"20",X"CD",X"80",X"20",X"C9",X"DD",X"7E",X"06",X"A7",X"CA",X"E3",X"1A",X"FE",X"10",X"CA", + X"A7",X"1A",X"3D",X"DD",X"77",X"06",X"C9",X"DD",X"7E",X"11",X"A7",X"C2",X"C5",X"1A",X"DD",X"56", + X"03",X"DD",X"5E",X"04",X"CD",X"A6",X"33",X"DD",X"7E",X"06",X"3D",X"DD",X"77",X"06",X"21",X"50", + X"00",X"22",X"5B",X"9A",X"C9",X"DD",X"56",X"03",X"DD",X"5E",X"04",X"26",X"EF",X"2E",X"19",X"DD", + X"7E",X"1F",X"CD",X"62",X"32",X"DD",X"35",X"06",X"DD",X"36",X"0C",X"40",X"21",X"00",X"02",X"22", + X"5B",X"9A",X"C9",X"DD",X"7E",X"11",X"A7",X"C2",X"00",X"1B",X"C3",X"91",X"1B",X"DD",X"56",X"03", + X"DD",X"5E",X"04",X"21",X"F0",X"08",X"DD",X"7E",X"1F",X"CD",X"62",X"32",X"CD",X"09",X"1F",X"C9", + X"DD",X"7E",X"0C",X"A7",X"CA",X"ED",X"1A",X"FE",X"20",X"CA",X"11",X"1B",X"3D",X"DD",X"77",X"0C", + X"C9",X"DD",X"56",X"03",X"DD",X"5E",X"04",X"26",X"F3",X"2E",X"10",X"DD",X"7E",X"1F",X"CD",X"62", + X"32",X"DD",X"35",X"0C",X"C9",X"DD",X"7E",X"05",X"A7",X"C0",X"CD",X"3E",X"1B",X"DD",X"7E",X"11", + X"A7",X"C2",X"48",X"1B",X"CD",X"66",X"1B",X"CD",X"9E",X"1B",X"CD",X"14",X"1C",X"C9",X"3A",X"8B", + X"9C",X"FE",X"0E",X"D8",X"CD",X"80",X"20",X"C9",X"DD",X"7E",X"12",X"A7",X"C2",X"59",X"1B",X"CD", + X"53",X"1D",X"CD",X"14",X"1C",X"CD",X"70",X"1C",X"C9",X"CD",X"E7",X"1D",X"CD",X"47",X"1F",X"CD", + X"14",X"1C",X"CD",X"62",X"1E",X"C9",X"DD",X"7E",X"03",X"C6",X"02",X"DD",X"77",X"03",X"FE",X"F0", + X"D2",X"8E",X"1B",X"DD",X"7E",X"12",X"A7",X"C2",X"84",X"1B",X"DD",X"56",X"03",X"DD",X"5E",X"04", + X"CD",X"BC",X"33",X"C9",X"DD",X"56",X"03",X"DD",X"5E",X"04",X"CD",X"82",X"34",X"C9",X"CD",X"57", + X"20",X"DD",X"56",X"03",X"DD",X"5E",X"04",X"CD",X"B0",X"33",X"CD",X"09",X"1F",X"C9",X"FD",X"21", + X"B0",X"98",X"0E",X"05",X"11",X"20",X"00",X"3A",X"53",X"9A",X"06",X"06",X"FE",X"02",X"DA",X"B3", + X"1B",X"06",X"08",X"FD",X"7E",X"00",X"A7",X"C4",X"FE",X"1B",X"FD",X"19",X"0D",X"C2",X"B3",X"1B", + X"78",X"A7",X"C8",X"3A",X"23",X"9A",X"DD",X"96",X"03",X"D8",X"FE",X"10",X"D0",X"DD",X"36",X"0B", + X"00",X"DD",X"36",X"14",X"01",X"DD",X"56",X"03",X"DD",X"5E",X"04",X"C5",X"CD",X"B0",X"33",X"C1", + X"DD",X"36",X"11",X"FF",X"CB",X"48",X"C2",X"F4",X"1B",X"CB",X"50",X"C2",X"F9",X"1B",X"3E",X"03", + X"DD",X"77",X"1F",X"C9",X"DD",X"36",X"1F",X"01",X"C9",X"DD",X"36",X"1F",X"02",X"C9",X"FD",X"7E", + X"1F",X"FE",X"01",X"CA",X"0E",X"1C",X"FE",X"02",X"CA",X"11",X"1C",X"CB",X"98",X"C9",X"CB",X"88", + X"C9",X"CB",X"90",X"C9",X"3A",X"59",X"9A",X"DD",X"86",X"02",X"DD",X"46",X"01",X"CB",X"20",X"CB", + X"C0",X"A0",X"C0",X"DD",X"7E",X"13",X"3C",X"DD",X"77",X"13",X"FE",X"60",X"D8",X"DD",X"36",X"13", + X"00",X"16",X"09",X"FD",X"21",X"00",X"98",X"01",X"10",X"00",X"FD",X"7E",X"00",X"A7",X"CA",X"48", + X"1C",X"FD",X"09",X"15",X"C2",X"3A",X"1C",X"C9",X"FD",X"36",X"00",X"FF",X"DD",X"7E",X"03",X"DD", + X"46",X"04",X"FD",X"77",X"03",X"FD",X"70",X"04",X"FD",X"36",X"06",X"00",X"FD",X"36",X"05",X"00", + X"FD",X"77",X"08",X"FD",X"36",X"09",X"E8",X"FD",X"36",X"0A",X"00",X"FD",X"36",X"07",X"02",X"C9", + X"DD",X"4E",X"0D",X"DD",X"46",X"0E",X"CB",X"21",X"CB",X"10",X"CB",X"21",X"CB",X"10",X"DD",X"5E", + X"14",X"FD",X"21",X"A3",X"40",X"16",X"00",X"CB",X"23",X"CB",X"12",X"FD",X"19",X"FD",X"5E",X"00", + X"FD",X"56",X"01",X"D5",X"FD",X"E1",X"FD",X"09",X"FD",X"7E",X"00",X"FE",X"80",X"CA",X"E5",X"1C", + X"DD",X"86",X"03",X"DD",X"77",X"03",X"57",X"FD",X"7E",X"01",X"DD",X"86",X"04",X"DD",X"77",X"04", + X"5F",X"FD",X"66",X"02",X"FD",X"6E",X"03",X"DD",X"7E",X"1F",X"CD",X"62",X"32",X"DD",X"7E",X"03", + X"FE",X"F0",X"D2",X"F4",X"1E",X"FE",X"10",X"DA",X"F4",X"1E",X"DD",X"7E",X"04",X"FE",X"10",X"DA", + X"F4",X"1E",X"FE",X"F0",X"D2",X"F4",X"1E",X"DD",X"6E",X"0D",X"DD",X"66",X"0E",X"23",X"DD",X"75", + X"0D",X"DD",X"74",X"0E",X"C9",X"3E",X"01",X"DD",X"46",X"0A",X"DD",X"34",X"0A",X"B8",X"DA",X"10", + X"1D",X"FD",X"46",X"01",X"ED",X"5F",X"CB",X"47",X"CA",X"44",X"1D",X"78",X"CB",X"3F",X"CB",X"3F", + X"CB",X"3F",X"CB",X"3F",X"DD",X"77",X"14",X"DD",X"36",X"0D",X"00",X"DD",X"36",X"0E",X"00",X"C9", + X"DD",X"7E",X"14",X"FE",X"00",X"CA",X"2A",X"1D",X"FE",X"04",X"CA",X"37",X"1D",X"FE",X"06",X"CA", + X"2A",X"1D",X"FE",X"07",X"CA",X"37",X"1D",X"C3",X"F1",X"1C",X"DD",X"36",X"14",X"06",X"DD",X"36", + X"0D",X"00",X"DD",X"36",X"0E",X"00",X"C9",X"DD",X"36",X"14",X"07",X"DD",X"36",X"0D",X"00",X"DD", + X"36",X"0E",X"00",X"C9",X"78",X"E6",X"0F",X"DD",X"77",X"14",X"DD",X"36",X"0D",X"00",X"DD",X"36", + X"0E",X"00",X"C9",X"DD",X"7E",X"14",X"FE",X"03",X"CA",X"61",X"1D",X"FE",X"01",X"CA",X"61",X"1D", + X"C9",X"DD",X"7E",X"0D",X"FE",X"05",X"C0",X"3A",X"23",X"9A",X"DD",X"96",X"03",X"DA",X"76",X"1D", + X"FE",X"20",X"D0",X"C3",X"31",X"1C",X"ED",X"44",X"FE",X"20",X"D0",X"C3",X"31",X"1C",X"FD",X"21", + X"00",X"98",X"01",X"10",X"00",X"2E",X"09",X"FD",X"7E",X"00",X"A7",X"CA",X"95",X"1D",X"FD",X"09", + X"2D",X"C2",X"87",X"1D",X"C9",X"FD",X"36",X"00",X"FF",X"DD",X"36",X"07",X"FF",X"DD",X"7E",X"03", + X"FD",X"77",X"03",X"DD",X"7E",X"04",X"FD",X"77",X"04",X"FD",X"36",X"05",X"00",X"FD",X"36",X"06", + X"00",X"FD",X"36",X"07",X"01",X"FD",X"E5",X"E1",X"DD",X"75",X"08",X"DD",X"74",X"09",X"3E",X"E8", + X"FD",X"77",X"09",X"3A",X"23",X"9A",X"DD",X"96",X"03",X"DA",X"D8",X"1D",X"CB",X"3F",X"CB",X"3F", + X"CB",X"3F",X"CB",X"3F",X"FD",X"77",X"08",X"C9",X"ED",X"44",X"CB",X"3F",X"CB",X"3F",X"CB",X"3F", + X"CB",X"3F",X"2F",X"FD",X"77",X"08",X"C9",X"DD",X"7E",X"0B",X"E6",X"F0",X"C2",X"32",X"1E",X"3A", + X"52",X"9A",X"DD",X"BE",X"0A",X"D8",X"3A",X"23",X"9A",X"47",X"DD",X"7E",X"0B",X"E6",X"0F",X"C2", + X"1A",X"1E",X"DD",X"7E",X"03",X"90",X"D8",X"FE",X"20",X"D8",X"DD",X"36",X"0B",X"F0",X"DD",X"36", + X"0C",X"08",X"DD",X"34",X"0A",X"DD",X"36",X"16",X"00",X"C9",X"78",X"DD",X"96",X"03",X"D8",X"FE", + X"20",X"D8",X"DD",X"36",X"0B",X"FF",X"DD",X"36",X"0C",X"08",X"DD",X"34",X"0A",X"DD",X"36",X"16", + X"00",X"C9",X"CD",X"57",X"1E",X"DD",X"56",X"03",X"DD",X"5E",X"04",X"26",X"BF",X"2E",X"11",X"DD", + X"7E",X"1F",X"CD",X"62",X"32",X"DD",X"7E",X"0C",X"3D",X"DD",X"77",X"0C",X"C0",X"DD",X"7E",X"0B", + X"2F",X"E6",X"0F",X"DD",X"77",X"0B",X"C9",X"DD",X"7E",X"04",X"3C",X"FE",X"90",X"D0",X"DD",X"77", + X"04",X"C9",X"DD",X"7E",X"0B",X"E6",X"F0",X"C0",X"DD",X"7E",X"07",X"A7",X"C2",X"CF",X"1E",X"DD", + X"34",X"0C",X"DD",X"7E",X"0B",X"E6",X"0F",X"C2",X"8D",X"1E",X"CD",X"B0",X"1E",X"DD",X"7E",X"03", + X"C6",X"02",X"DD",X"77",X"03",X"FE",X"F0",X"D2",X"F4",X"1E",X"C3",X"A0",X"1E",X"CD",X"C2",X"1E", + X"DD",X"7E",X"03",X"D6",X"02",X"DD",X"77",X"03",X"FE",X"10",X"DA",X"F4",X"1E",X"C3",X"A0",X"1E", + X"DD",X"56",X"03",X"DD",X"5E",X"04",X"DD",X"7E",X"1F",X"CD",X"62",X"32",X"DD",X"34",X"0C",X"C9", + X"DD",X"7E",X"0C",X"CB",X"47",X"CA",X"BD",X"1E",X"26",X"BB",X"2E",X"11",X"C9",X"26",X"B7",X"2E", + X"11",X"C9",X"DD",X"7E",X"0C",X"CB",X"47",X"CA",X"EF",X"1E",X"26",X"C7",X"2E",X"11",X"C9",X"DD", + X"7E",X"0B",X"E6",X"0F",X"C2",X"E8",X"1E",X"26",X"CB",X"2E",X"11",X"DD",X"56",X"03",X"DD",X"5E", + X"04",X"DD",X"7E",X"1F",X"CD",X"62",X"32",X"C9",X"26",X"CF",X"2E",X"11",X"C3",X"DB",X"1E",X"26", + X"C3",X"2E",X"11",X"C9",X"16",X"08",X"1E",X"FF",X"26",X"FF",X"2E",X"FF",X"DD",X"7E",X"1F",X"CD", + X"62",X"32",X"CD",X"09",X"1F",X"CD",X"57",X"20",X"C9",X"DD",X"46",X"07",X"DD",X"4E",X"08",X"DD", + X"56",X"09",X"DD",X"5E",X"12",X"DD",X"E5",X"E1",X"23",X"23",X"23",X"3E",X"1D",X"36",X"00",X"23", + X"3D",X"C2",X"1D",X"1F",X"DD",X"36",X"00",X"00",X"DD",X"70",X"07",X"DD",X"71",X"08",X"DD",X"72", + X"09",X"DD",X"73",X"12",X"C9",X"DD",X"7E",X"07",X"A7",X"C8",X"DD",X"6E",X"08",X"DD",X"66",X"09", + X"E5",X"FD",X"E1",X"CD",X"04",X"1A",X"C9",X"DD",X"7E",X"07",X"A7",X"C0",X"DD",X"7E",X"16",X"3C", + X"DD",X"77",X"16",X"FE",X"04",X"D0",X"DD",X"7E",X"0B",X"47",X"E6",X"F0",X"C0",X"78",X"E6",X"0F", + X"CA",X"6D",X"1F",X"3A",X"23",X"9A",X"DD",X"BE",X"03",X"D0",X"C3",X"7E",X"1D",X"3A",X"23",X"9A", + X"DD",X"BE",X"03",X"D8",X"C3",X"7E",X"1D",X"3A",X"59",X"9A",X"E6",X"3F",X"C0",X"3A",X"89",X"9C", + X"FE",X"08",X"D2",X"8A",X"1F",X"3C",X"32",X"89",X"9C",X"C9",X"AF",X"32",X"89",X"9C",X"3A",X"8B", + X"9C",X"47",X"3A",X"8C",X"9C",X"4F",X"CD",X"C5",X"1F",X"90",X"D8",X"C8",X"91",X"C8",X"D8",X"3A", + X"8A",X"9C",X"FE",X"09",X"D2",X"B8",X"1F",X"4F",X"3C",X"32",X"8A",X"9C",X"06",X"00",X"21",X"4F", + X"3F",X"09",X"5E",X"16",X"10",X"C3",X"D0",X"1F",X"AF",X"32",X"8A",X"9C",X"3A",X"4F",X"3F",X"5F", + X"16",X"10",X"C3",X"D0",X"1F",X"3A",X"FF",X"9B",X"CB",X"77",X"3E",X"10",X"C8",X"3E",X"18",X"C9", + X"3A",X"53",X"9A",X"FE",X"00",X"CA",X"E5",X"1F",X"FE",X"01",X"CA",X"0F",X"20",X"FE",X"02",X"CA", + X"14",X"20",X"C3",X"39",X"20",X"26",X"00",X"DD",X"21",X"B0",X"98",X"01",X"20",X"00",X"2E",X"05", + X"DD",X"7E",X"00",X"A7",X"CA",X"FE",X"1F",X"DD",X"09",X"2D",X"C2",X"F0",X"1F",X"C9",X"DD",X"36", + X"00",X"FF",X"DD",X"72",X"03",X"DD",X"73",X"04",X"DD",X"74",X"12",X"CD",X"4F",X"20",X"C9",X"26", + X"FF",X"C3",X"E7",X"1F",X"DD",X"21",X"F0",X"99",X"01",X"10",X"00",X"2E",X"03",X"DD",X"7E",X"00", + X"A7",X"CA",X"2B",X"20",X"DD",X"09",X"2D",X"C2",X"1D",X"20",X"C9",X"DD",X"36",X"00",X"FF",X"DD", + X"72",X"03",X"DD",X"73",X"04",X"CD",X"4F",X"20",X"C9",X"ED",X"5F",X"E6",X"03",X"FE",X"00",X"CA", + X"E5",X"1F",X"FE",X"01",X"CA",X"0F",X"20",X"FE",X"02",X"CA",X"14",X"20",X"C3",X"14",X"20",X"3A", + X"8C",X"9C",X"3C",X"32",X"8C",X"9C",X"C9",X"3A",X"8C",X"9C",X"3D",X"F8",X"32",X"8C",X"9C",X"C9", + X"3A",X"8B",X"9C",X"3C",X"32",X"8B",X"9C",X"3A",X"8C",X"9C",X"3D",X"F8",X"32",X"8C",X"9C",X"C9", + X"36",X"00",X"23",X"23",X"23",X"0E",X"00",X"D6",X"03",X"71",X"23",X"3D",X"C2",X"79",X"20",X"C9", + X"3A",X"53",X"9A",X"FE",X"02",X"D2",X"9F",X"20",X"FD",X"21",X"50",X"99",X"01",X"20",X"00",X"1E", + X"05",X"FD",X"7E",X"00",X"A7",X"CA",X"AB",X"20",X"FD",X"09",X"1D",X"C2",X"91",X"20",X"C9",X"FD", + X"21",X"70",X"99",X"01",X"20",X"00",X"1E",X"04",X"C3",X"91",X"20",X"FD",X"36",X"00",X"FF",X"DD", + X"7E",X"03",X"FD",X"77",X"03",X"DD",X"7E",X"04",X"FD",X"77",X"04",X"AF",X"FD",X"77",X"05",X"FD", + X"77",X"06",X"FD",X"77",X"0C",X"FD",X"77",X"17",X"FD",X"77",X"18",X"FD",X"36",X"1E",X"00",X"C9", + X"DD",X"21",X"F0",X"97",X"11",X"10",X"00",X"DD",X"19",X"DD",X"E5",X"E1",X"01",X"90",X"98",X"ED", + X"42",X"C8",X"CD",X"E8",X"20",X"C3",X"D4",X"20",X"DD",X"7E",X"00",X"A7",X"C8",X"DD",X"7E",X"07", + X"FE",X"02",X"C0",X"CD",X"11",X"21",X"DD",X"7E",X"05",X"A7",X"C0",X"DD",X"7E",X"00",X"A7",X"C8", + X"3A",X"59",X"9A",X"DD",X"86",X"02",X"DD",X"A6",X"01",X"C0",X"CD",X"1D",X"21",X"CD",X"58",X"21", + X"C9",X"DD",X"E5",X"FD",X"E1",X"DD",X"7E",X"05",X"A7",X"C2",X"3F",X"31",X"C9",X"DD",X"7E",X"04", + X"FE",X"D4",X"D0",X"C6",X"02",X"DD",X"77",X"04",X"5F",X"DD",X"56",X"03",X"26",X"0D",X"2E",X"00", + X"DD",X"7E",X"0E",X"CD",X"0E",X"32",X"DD",X"7E",X"04",X"FE",X"D4",X"D8",X"DD",X"7E",X"03",X"FE", + X"80",X"D2",X"4A",X"21",X"21",X"4D",X"46",X"C3",X"4D",X"21",X"21",X"37",X"46",X"DD",X"75",X"0B", + X"DD",X"74",X"0C",X"DD",X"36",X"0A",X"00",X"C9",X"DD",X"7E",X"04",X"FE",X"D4",X"D8",X"FE",X"E9", + X"DA",X"7C",X"21",X"DD",X"36",X"05",X"FF",X"DD",X"56",X"03",X"DD",X"5E",X"04",X"26",X"0A",X"2E", + X"00",X"DD",X"7E",X"0E",X"CD",X"0E",X"32",X"DD",X"36",X"06",X"08",X"C9",X"DD",X"66",X"0C",X"DD", + X"6E",X"0B",X"E5",X"FD",X"E1",X"DD",X"7E",X"0A",X"A7",X"CA",X"95",X"21",X"11",X"02",X"00",X"FD", + X"19",X"3D",X"C2",X"8C",X"21",X"FD",X"7E",X"01",X"DD",X"86",X"03",X"DD",X"77",X"03",X"57",X"FD", + X"7E",X"00",X"DD",X"86",X"04",X"DD",X"77",X"04",X"5F",X"26",X"0D",X"2E",X"00",X"DD",X"7E",X"0E", + X"CD",X"0E",X"32",X"DD",X"34",X"0A",X"C9",X"DD",X"21",X"E0",X"99",X"11",X"10",X"00",X"DD",X"19", + X"DD",X"E5",X"E1",X"01",X"20",X"9A",X"ED",X"42",X"C8",X"CD",X"CF",X"21",X"C3",X"BB",X"21",X"DD", + X"7E",X"00",X"A7",X"C8",X"CD",X"F1",X"21",X"3A",X"59",X"9A",X"DD",X"86",X"02",X"DD",X"A6",X"01", + X"C0",X"CD",X"69",X"22",X"CD",X"99",X"22",X"CD",X"22",X"23",X"CD",X"91",X"23",X"CD",X"18",X"24", + X"C9",X"DD",X"7E",X"05",X"A7",X"C2",X"49",X"22",X"CD",X"6E",X"31",X"A7",X"C8",X"21",X"EC",X"45", + X"FD",X"21",X"20",X"9A",X"DD",X"7E",X"04",X"47",X"96",X"FD",X"BE",X"11",X"D0",X"23",X"78",X"86", + X"FD",X"BE",X"11",X"D8",X"23",X"DD",X"7E",X"03",X"47",X"96",X"FD",X"BE",X"10",X"D0",X"23",X"78", + X"86",X"FD",X"BE",X"10",X"D8",X"DD",X"36",X"05",X"FF",X"DD",X"36",X"06",X"07",X"FD",X"36",X"09", + X"00",X"21",X"50",X"00",X"22",X"5B",X"9A",X"CD",X"60",X"20",X"DD",X"56",X"03",X"DD",X"5E",X"04", + X"CD",X"A6",X"33",X"21",X"16",X"9C",X"CB",X"DE",X"C9",X"3A",X"59",X"9A",X"DD",X"86",X"02",X"DD", + X"A6",X"01",X"C0",X"DD",X"35",X"06",X"C0",X"DD",X"36",X"00",X"00",X"DD",X"36",X"05",X"00",X"DD", + X"56",X"03",X"DD",X"5E",X"04",X"CD",X"B0",X"33",X"C9",X"DD",X"7E",X"05",X"A7",X"C0",X"DD",X"7E", + X"00",X"A7",X"C8",X"DD",X"7E",X"03",X"C6",X"02",X"FE",X"FC",X"D2",X"88",X"22",X"DD",X"77",X"03", + X"57",X"DD",X"5E",X"04",X"CD",X"9C",X"33",X"C9",X"DD",X"36",X"00",X"00",X"DD",X"56",X"03",X"DD", + X"5E",X"04",X"CD",X"B0",X"33",X"CD",X"57",X"20",X"C9",X"DD",X"7E",X"08",X"A7",X"C2",X"E7",X"22", + X"DD",X"7E",X"05",X"A7",X"C0",X"FD",X"21",X"F0",X"97",X"11",X"10",X"00",X"0E",X"08",X"FD",X"19", + X"FD",X"7E",X"00",X"A7",X"CA",X"BC",X"22",X"0D",X"C2",X"AE",X"22",X"C9",X"FD",X"36",X"00",X"FF", + X"FD",X"36",X"07",X"08",X"FD",X"36",X"05",X"00",X"FD",X"36",X"06",X"00",X"DD",X"7E",X"03",X"FD", + X"77",X"03",X"DD",X"7E",X"04",X"C6",X"0A",X"FD",X"77",X"04",X"DD",X"34",X"08",X"FD",X"E5",X"E1", + X"DD",X"74",X"0A",X"DD",X"75",X"09",X"C9",X"DD",X"34",X"08",X"DD",X"7E",X"08",X"FE",X"1E",X"CA", + X"18",X"23",X"FE",X"06",X"CA",X"1D",X"23",X"D0",X"DD",X"66",X"0A",X"DD",X"6E",X"09",X"E5",X"FD", + X"E1",X"FD",X"7E",X"04",X"C6",X"02",X"FD",X"77",X"04",X"5F",X"FD",X"56",X"03",X"26",X"0B",X"2E", + X"00",X"FD",X"7E",X"0E",X"CD",X"0E",X"32",X"C9",X"DD",X"36",X"08",X"00",X"C9",X"DD",X"36",X"07", + X"FF",X"C9",X"DD",X"7E",X"07",X"A7",X"C8",X"FD",X"21",X"80",X"98",X"11",X"10",X"00",X"0E",X"02", + X"FD",X"19",X"FD",X"7E",X"00",X"A7",X"CA",X"3E",X"23",X"0D",X"C2",X"30",X"23",X"C9",X"FD",X"E5", + X"D1",X"DD",X"66",X"0A",X"DD",X"6E",X"09",X"E5",X"FD",X"E1",X"FD",X"46",X"03",X"FD",X"4E",X"04", + X"FD",X"36",X"00",X"00",X"FD",X"36",X"07",X"00",X"D5",X"FD",X"E1",X"FD",X"36",X"00",X"FF",X"FD", + X"70",X"03",X"FD",X"71",X"04",X"FD",X"36",X"05",X"00",X"FD",X"21",X"20",X"9A",X"FD",X"7E",X"03", + X"D5",X"FD",X"E1",X"FD",X"77",X"08",X"DD",X"36",X"07",X"00",X"E5",X"FD",X"E1",X"16",X"08",X"1E", + X"08",X"26",X"00",X"2E",X"00",X"FD",X"7E",X"0E",X"CD",X"0E",X"32",X"21",X"16",X"9C",X"CB",X"E6", + X"C9",X"DD",X"7E",X"07",X"A7",X"C8",X"3A",X"53",X"9A",X"FE",X"03",X"C2",X"A7",X"23",X"FD",X"21", + X"50",X"99",X"0E",X"04",X"C3",X"AD",X"23",X"FD",X"21",X"30",X"99",X"0E",X"05",X"11",X"20",X"00", + X"3A",X"52",X"9A",X"FE",X"03",X"D2",X"B9",X"23",X"0D",X"FD",X"19",X"FD",X"7E",X"00",X"A7",X"CA", + X"C7",X"23",X"0D",X"C2",X"B9",X"23",X"C9",X"FD",X"E5",X"D1",X"DD",X"66",X"0A",X"DD",X"6E",X"09", + X"E5",X"FD",X"E1",X"FD",X"46",X"03",X"FD",X"4E",X"04",X"FD",X"36",X"00",X"00",X"D5",X"FD",X"E1", + X"FD",X"36",X"00",X"FF",X"FD",X"70",X"03",X"FD",X"71",X"04",X"FD",X"36",X"05",X"00",X"FD",X"36", + X"06",X"00",X"FD",X"36",X"0C",X"00",X"FD",X"36",X"17",X"00",X"FD",X"36",X"18",X"00",X"FD",X"36", + X"1E",X"00",X"DD",X"36",X"07",X"00",X"E5",X"FD",X"E1",X"16",X"08",X"1E",X"08",X"26",X"00",X"2E", + X"00",X"FD",X"7E",X"0E",X"CD",X"0E",X"32",X"C9",X"DD",X"7E",X"07",X"A7",X"C8",X"DD",X"66",X"0A", + X"DD",X"6E",X"09",X"E5",X"FD",X"E1",X"FD",X"36",X"05",X"00",X"FD",X"36",X"06",X"00",X"FD",X"36", + X"0A",X"00",X"FD",X"36",X"07",X"02",X"DD",X"36",X"07",X"00",X"C9",X"DD",X"21",X"80",X"98",X"11", + X"10",X"00",X"DD",X"19",X"DD",X"E5",X"E1",X"01",X"B0",X"98",X"ED",X"42",X"C8",X"CD",X"53",X"24", + X"C3",X"3F",X"24",X"DD",X"7E",X"00",X"A7",X"C8",X"CD",X"76",X"24",X"DD",X"7E",X"05",X"A7",X"C0", + X"3A",X"59",X"9A",X"DD",X"86",X"02",X"DD",X"A6",X"01",X"C0",X"DD",X"7E",X"00",X"A7",X"C8",X"CD", + X"2D",X"25",X"CD",X"41",X"25",X"C9",X"DD",X"7E",X"05",X"A7",X"C2",X"E6",X"24",X"FD",X"21",X"20", + X"9A",X"CD",X"6E",X"31",X"A7",X"CA",X"A2",X"24",X"21",X"E8",X"45",X"FD",X"56",X"10",X"FD",X"5E", + X"11",X"CD",X"BA",X"24",X"DD",X"7E",X"05",X"A7",X"CA",X"A2",X"24",X"FD",X"36",X"09",X"00",X"C3", + X"D7",X"24",X"21",X"E8",X"45",X"FD",X"56",X"1E",X"FD",X"5E",X"08",X"CD",X"BA",X"24",X"DD",X"7E", + X"05",X"A7",X"C8",X"FD",X"36",X"07",X"00",X"C3",X"D7",X"24",X"DD",X"7E",X"04",X"96",X"BB",X"D0", + X"23",X"DD",X"7E",X"04",X"86",X"BB",X"D8",X"23",X"DD",X"7E",X"03",X"96",X"BA",X"D0",X"23",X"86", + X"BA",X"D8",X"DD",X"36",X"05",X"FF",X"C9",X"DD",X"36",X"06",X"04",X"DD",X"36",X"07",X"05",X"21", + X"00",X"02",X"22",X"5B",X"9A",X"C9",X"3A",X"59",X"9A",X"DD",X"86",X"02",X"DD",X"A6",X"01",X"C0", + X"DD",X"7E",X"06",X"A7",X"CA",X"02",X"25",X"26",X"EB",X"2E",X"19",X"CD",X"20",X"25",X"DD",X"35", + X"06",X"C9",X"26",X"F3",X"2E",X"12",X"CD",X"20",X"25",X"DD",X"35",X"07",X"C0",X"DD",X"36",X"00", + X"00",X"26",X"FF",X"2E",X"0F",X"16",X"08",X"1E",X"10",X"DD",X"7E",X"0E",X"CD",X"62",X"32",X"C9", + X"DD",X"56",X"03",X"DD",X"5E",X"04",X"DD",X"7E",X"0E",X"CD",X"62",X"32",X"C9",X"DD",X"7E",X"04", + X"FE",X"70",X"D8",X"FE",X"A8",X"D0",X"FD",X"21",X"20",X"9A",X"FD",X"7E",X"03",X"DD",X"77",X"08", + X"C9",X"DD",X"7E",X"03",X"FE",X"10",X"DA",X"58",X"25",X"FE",X"F0",X"D2",X"58",X"25",X"DD",X"7E", + X"04",X"C6",X"02",X"FE",X"E8",X"DA",X"75",X"25",X"DD",X"36",X"00",X"00",X"DD",X"36",X"05",X"00", + X"26",X"FF",X"2E",X"0F",X"16",X"08",X"DD",X"72",X"03",X"1E",X"10",X"DD",X"73",X"04",X"DD",X"7E", + X"0E",X"CD",X"62",X"32",X"C9",X"DD",X"77",X"04",X"3E",X"E8",X"DD",X"96",X"04",X"47",X"CB",X"28", + X"DD",X"7E",X"08",X"DD",X"BE",X"03",X"CA",X"AA",X"25",X"DD",X"96",X"03",X"CB",X"7F",X"C2",X"9E", + X"25",X"B8",X"DA",X"98",X"25",X"DD",X"34",X"03",X"DD",X"34",X"03",X"C3",X"AA",X"25",X"ED",X"44", + X"B8",X"DA",X"A7",X"25",X"DD",X"35",X"03",X"DD",X"35",X"03",X"DD",X"7E",X"0F",X"FE",X"DB",X"CA", + X"B9",X"25",X"DD",X"36",X"0F",X"DB",X"C3",X"BD",X"25",X"DD",X"36",X"0F",X"DF",X"DD",X"56",X"03", + X"DD",X"5E",X"04",X"DD",X"66",X"0F",X"2E",X"14",X"DD",X"7E",X"0E",X"CD",X"62",X"32",X"C9",X"DD", + X"21",X"30",X"99",X"11",X"20",X"00",X"DD",X"19",X"DD",X"E5",X"E1",X"01",X"F0",X"99",X"ED",X"42", + X"C8",X"CD",X"E7",X"25",X"C3",X"D3",X"25",X"DD",X"7E",X"1E",X"FE",X"00",X"C0",X"DD",X"7E",X"00", + X"A7",X"C8",X"DD",X"36",X"01",X"0F",X"CD",X"1A",X"26",X"CD",X"4B",X"26",X"DD",X"7E",X"05",X"A7", + X"C0",X"3A",X"59",X"9A",X"DD",X"86",X"02",X"DD",X"A6",X"01",X"C0",X"DD",X"7E",X"00",X"A7",X"C8", + X"DD",X"34",X"06",X"CD",X"C7",X"26",X"CD",X"9F",X"27",X"C9",X"DD",X"7E",X"04",X"FE",X"60",X"D8", + X"DD",X"7E",X"17",X"A7",X"C0",X"FD",X"21",X"30",X"99",X"11",X"20",X"00",X"0E",X"05",X"FD",X"19", + X"0D",X"CA",X"42",X"26",X"FD",X"7E",X"00",X"A7",X"CA",X"2E",X"26",X"FD",X"36",X"0A",X"FF",X"C3", + X"2E",X"26",X"DD",X"36",X"0A",X"00",X"DD",X"36",X"17",X"FF",X"C9",X"DD",X"7E",X"05",X"A7",X"C2", + X"98",X"26",X"CD",X"6E",X"31",X"A7",X"C8",X"FD",X"21",X"20",X"9A",X"21",X"F0",X"45",X"DD",X"7E", + X"04",X"96",X"FD",X"BE",X"11",X"D0",X"23",X"DD",X"7E",X"04",X"86",X"FD",X"BE",X"11",X"D8",X"23", + X"DD",X"7E",X"03",X"96",X"FD",X"BE",X"10",X"D0",X"23",X"DD",X"7E",X"03",X"86",X"FD",X"BE",X"10", + X"D8",X"DD",X"36",X"05",X"FF",X"FD",X"36",X"09",X"00",X"21",X"00",X"03",X"22",X"5B",X"9A",X"DD", + X"36",X"06",X"04",X"DD",X"36",X"0F",X"F7",X"C9",X"3A",X"59",X"9A",X"DD",X"86",X"02",X"DD",X"A6", + X"01",X"C0",X"DD",X"56",X"03",X"DD",X"5E",X"04",X"DD",X"66",X"0F",X"2E",X"12",X"DD",X"7E",X"1F", + X"CD",X"62",X"32",X"DD",X"35",X"06",X"C0",X"DD",X"36",X"00",X"00",X"CD",X"F6",X"2F",X"DD",X"36", + X"17",X"00",X"DD",X"36",X"18",X"00",X"C9",X"DD",X"66",X"0E",X"DD",X"6E",X"0D",X"E5",X"FD",X"E1", + X"DD",X"7E",X"0C",X"A7",X"CA",X"0C",X"27",X"11",X"04",X"00",X"FD",X"19",X"3D",X"C2",X"DA",X"26", + X"FD",X"7E",X"00",X"FE",X"80",X"CA",X"0C",X"27",X"DD",X"7E",X"03",X"FD",X"86",X"01",X"DD",X"77", + X"03",X"57",X"DD",X"7E",X"04",X"FD",X"86",X"00",X"DD",X"77",X"04",X"5F",X"FD",X"66",X"02",X"FD", + X"6E",X"03",X"DD",X"7E",X"1F",X"CD",X"62",X"32",X"DD",X"34",X"0C",X"C9",X"DD",X"7E",X"18",X"A7", + X"CA",X"3A",X"27",X"21",X"63",X"46",X"C3",X"94",X"27",X"ED",X"5F",X"E6",X"7F",X"47",X"3A",X"59", + X"9A",X"80",X"47",X"3A",X"52",X"9A",X"17",X"17",X"4F",X"3E",X"3F",X"91",X"B8",X"DA",X"3A",X"27", + X"21",X"63",X"46",X"DD",X"36",X"18",X"FF",X"C3",X"94",X"27",X"21",X"E9",X"46",X"DD",X"7E",X"03", + X"BE",X"DA",X"58",X"27",X"23",X"BE",X"DA",X"6C",X"27",X"23",X"BE",X"DA",X"80",X"27",X"23",X"3E", + X"FF",X"BE",X"CA",X"58",X"27",X"C3",X"3D",X"27",X"DD",X"7E",X"06",X"FE",X"08",X"D2",X"66",X"27", + X"21",X"63",X"46",X"C3",X"94",X"27",X"21",X"8E",X"46",X"C3",X"94",X"27",X"DD",X"7E",X"06",X"FE", + X"08",X"D2",X"7A",X"27",X"21",X"7C",X"46",X"C3",X"94",X"27",X"21",X"AF",X"46",X"C3",X"94",X"27", + X"DD",X"7E",X"06",X"FE",X"08",X"D2",X"8E",X"27",X"21",X"85",X"46",X"C3",X"94",X"27",X"21",X"CC", + X"46",X"C3",X"94",X"27",X"DD",X"74",X"0E",X"DD",X"75",X"0D",X"DD",X"36",X"0C",X"01",X"C9",X"DD", + X"7E",X"04",X"FE",X"A0",X"D8",X"DD",X"7E",X"18",X"A7",X"C2",X"E6",X"27",X"DD",X"36",X"01",X"0F", + X"DD",X"56",X"03",X"1E",X"A0",X"DD",X"73",X"04",X"DD",X"36",X"06",X"00",X"DD",X"36",X"09",X"00", + X"DD",X"36",X"0B",X"00",X"DD",X"36",X"0C",X"00",X"26",X"83",X"DD",X"74",X"0F",X"DD",X"36",X"15", + X"00",X"DD",X"36",X"17",X"00",X"DD",X"36",X"18",X"00",X"DD",X"36",X"1E",X"FF",X"2E",X"12",X"DD", + X"7E",X"1F",X"CD",X"62",X"32",X"C9",X"16",X"08",X"DD",X"72",X"03",X"1E",X"10",X"DD",X"73",X"04", + X"26",X"FF",X"2E",X"0F",X"DD",X"7E",X"1F",X"CD",X"62",X"32",X"DD",X"36",X"00",X"00",X"DD",X"36", + X"17",X"00",X"DD",X"36",X"18",X"00",X"DD",X"36",X"06",X"00",X"C9",X"3A",X"59",X"9A",X"E6",X"0F", + X"C2",X"1F",X"28",X"3A",X"6D",X"99",X"3D",X"C2",X"1C",X"28",X"3E",X"8F",X"32",X"6D",X"99",X"DD", + X"21",X"30",X"99",X"11",X"20",X"00",X"DD",X"19",X"DD",X"E5",X"E1",X"01",X"F0",X"99",X"ED",X"42", + X"C8",X"CD",X"37",X"28",X"C3",X"23",X"28",X"CD",X"91",X"28",X"DD",X"7E",X"00",X"A7",X"C8",X"DD", + X"7E",X"1E",X"FE",X"FF",X"C0",X"3A",X"26",X"9A",X"A7",X"C0",X"3A",X"25",X"9A",X"A7",X"C0",X"CD", + X"AB",X"29",X"DD",X"7E",X"05",X"A7",X"C0",X"3A",X"6D",X"99",X"FE",X"8F",X"C2",X"63",X"28",X"DD", + X"36",X"0A",X"FF",X"3A",X"59",X"9A",X"DD",X"86",X"02",X"DD",X"A6",X"01",X"C0",X"DD",X"7E",X"00", + X"A7",X"C8",X"DD",X"7E",X"09",X"FE",X"00",X"CA",X"89",X"28",X"FE",X"20",X"CA",X"8D",X"28",X"CD", + X"0A",X"2B",X"CD",X"65",X"2C",X"CD",X"FB",X"2C",X"C9",X"CD",X"78",X"2A",X"C9",X"CD",X"40",X"2E", + X"C9",X"DD",X"7E",X"11",X"A7",X"C2",X"6F",X"29",X"DD",X"7E",X"07",X"A7",X"C8",X"DD",X"66",X"14", + X"DD",X"6E",X"13",X"E5",X"FD",X"E1",X"FD",X"7E",X"05",X"A7",X"CA",X"BA",X"28",X"CD",X"3F",X"31", + X"FD",X"7E",X"00",X"A7",X"C0",X"DD",X"36",X"07",X"00",X"C9",X"3A",X"59",X"9A",X"DD",X"86",X"02", + X"E6",X"07",X"C0",X"FD",X"66",X"0C",X"FD",X"6E",X"0B",X"FD",X"7E",X"0A",X"A7",X"CA",X"DC",X"28", + X"23",X"23",X"3D",X"C2",X"D0",X"28",X"7E",X"FE",X"80",X"CA",X"FD",X"28",X"FD",X"7E",X"04",X"86", + X"FD",X"77",X"04",X"5F",X"23",X"FD",X"7E",X"03",X"86",X"FD",X"77",X"03",X"57",X"26",X"0B",X"2E", + X"00",X"FD",X"7E",X"0E",X"CD",X"0E",X"32",X"FD",X"34",X"0A",X"C3",X"13",X"29",X"FD",X"7E",X"04", + X"C6",X"03",X"FD",X"77",X"04",X"5F",X"FD",X"56",X"03",X"26",X"0B",X"2E",X"00",X"FD",X"7E",X"0E", + X"CD",X"0E",X"32",X"FD",X"7E",X"04",X"FD",X"BE",X"09",X"D8",X"FD",X"7E",X"09",X"FE",X"E8",X"D2", + X"56",X"29",X"21",X"40",X"9A",X"DD",X"5E",X"10",X"16",X"00",X"CB",X"23",X"1D",X"19",X"36",X"FF", + X"DD",X"36",X"11",X"FF",X"DD",X"36",X"12",X"02",X"DD",X"56",X"10",X"CD",X"FB",X"36",X"FD",X"36", + X"00",X"00",X"16",X"08",X"1E",X"10",X"26",X"00",X"2E",X"00",X"FD",X"7E",X"0E",X"CD",X"0E",X"32", + X"21",X"16",X"9C",X"CB",X"DE",X"C9",X"FD",X"36",X"05",X"FF",X"FD",X"36",X"06",X"03",X"FD",X"56", + X"03",X"FD",X"5E",X"04",X"26",X"0A",X"2E",X"00",X"FD",X"7E",X"0E",X"CD",X"0E",X"32",X"C9",X"DD", + X"7E",X"11",X"FE",X"0F",X"CA",X"8A",X"29",X"DD",X"35",X"12",X"C0",X"DD",X"36",X"11",X"0F",X"DD", + X"36",X"12",X"02",X"DD",X"56",X"10",X"CD",X"13",X"37",X"C9",X"DD",X"35",X"12",X"C0",X"DD",X"36", + X"11",X"00",X"DD",X"56",X"10",X"CD",X"A6",X"36",X"21",X"40",X"9A",X"DD",X"5E",X"10",X"16",X"00", + X"CB",X"23",X"1D",X"19",X"36",X"FF",X"DD",X"36",X"07",X"00",X"C9",X"DD",X"7E",X"05",X"A7",X"C2", + X"0F",X"2A",X"DD",X"7E",X"09",X"FE",X"20",X"C2",X"2F",X"2A",X"3A",X"54",X"9A",X"A7",X"C8",X"DD", + X"7E",X"04",X"FE",X"E6",X"D8",X"FD",X"21",X"20",X"9A",X"FD",X"7E",X"03",X"D6",X"10",X"DD",X"BE", + X"03",X"D0",X"FD",X"7E",X"03",X"C6",X"10",X"DD",X"BE",X"03",X"D8",X"DD",X"36",X"05",X"FF",X"DD", + X"36",X"06",X"50",X"21",X"00",X"03",X"22",X"5B",X"9A",X"DD",X"56",X"03",X"DD",X"5E",X"04",X"DD", + X"7E",X"0B",X"FE",X"10",X"CA",X"FC",X"29",X"26",X"77",X"C3",X"FE",X"29",X"26",X"6B",X"2E",X"12", + X"DD",X"75",X"0F",X"DD",X"7E",X"1F",X"CD",X"62",X"32",X"21",X"16",X"9C",X"CB",X"EE",X"C9",X"DD", + X"35",X"06",X"C0",X"DD",X"36",X"00",X"00",X"DD",X"36",X"1E",X"00",X"DD",X"36",X"05",X"00",X"DD", + X"36",X"09",X"00",X"DD",X"36",X"0C",X"00",X"DD",X"36",X"15",X"00",X"CD",X"F6",X"2F",X"C9",X"21", + X"F4",X"45",X"FD",X"21",X"20",X"9A",X"FD",X"7E",X"07",X"A7",X"C8",X"DD",X"7E",X"04",X"96",X"FD", + X"BE",X"08",X"D0",X"23",X"DD",X"7E",X"04",X"86",X"FD",X"BE",X"08",X"D8",X"23",X"DD",X"7E",X"03", + X"96",X"FD",X"BE",X"1E",X"D0",X"23",X"DD",X"7E",X"03",X"86",X"FD",X"BE",X"1E",X"D8",X"FD",X"36", + X"07",X"00",X"DD",X"7E",X"09",X"FE",X"12",X"C2",X"DB",X"29",X"21",X"00",X"03",X"22",X"5B",X"9A", + X"21",X"16",X"9C",X"CB",X"EE",X"C3",X"13",X"2A",X"DD",X"7E",X"07",X"A7",X"C0",X"FD",X"21",X"87", + X"47",X"11",X"03",X"00",X"0E",X"00",X"DD",X"7E",X"03",X"FD",X"BE",X"01",X"D2",X"9B",X"2A",X"FD", + X"19",X"0C",X"79",X"FE",X"03",X"CA",X"9B",X"2A",X"C3",X"86",X"2A",X"79",X"A7",X"CA",X"DE",X"2A", + X"DD",X"71",X"10",X"21",X"40",X"9A",X"5F",X"16",X"00",X"CB",X"23",X"1D",X"19",X"7E",X"A7",X"C2", + X"DE",X"2A",X"DD",X"36",X"0B",X"10",X"3A",X"40",X"9A",X"FE",X"00",X"C2",X"DA",X"2A",X"CD",X"0B", + X"30",X"A7",X"CA",X"C8",X"2A",X"CD",X"2A",X"30",X"DD",X"36",X"09",X"10",X"21",X"E8",X"47",X"DD", + X"74",X"0E",X"DD",X"75",X"0D",X"DD",X"36",X"0C",X"00",X"C9",X"CD",X"2A",X"30",X"C9",X"0C",X"DD", + X"71",X"10",X"DD",X"36",X"09",X"10",X"DD",X"36",X"0B",X"20",X"DD",X"7E",X"10",X"FE",X"04",X"CA", + X"F8",X"2A",X"21",X"C7",X"47",X"C3",X"FF",X"2A",X"21",X"09",X"48",X"DD",X"36",X"0B",X"10",X"DD", + X"74",X"0E",X"DD",X"75",X"0D",X"DD",X"36",X"0C",X"00",X"C9",X"DD",X"7E",X"09",X"FE",X"10",X"C0", + X"DD",X"7E",X"07",X"A7",X"C0",X"FD",X"21",X"6F",X"47",X"11",X"03",X"00",X"0E",X"08",X"DD",X"7E", + X"04",X"FD",X"BE",X"00",X"D2",X"36",X"2B",X"DD",X"7E",X"03",X"FD",X"BE",X"01",X"D2",X"36",X"2B", + X"FD",X"BE",X"02",X"D2",X"3F",X"2B",X"FD",X"19",X"0D",X"C2",X"1E",X"2B",X"C3",X"6A",X"2B",X"21", + X"40",X"9A",X"7E",X"FE",X"00",X"CA",X"56",X"2B",X"DD",X"5E",X"10",X"16",X"00",X"CB",X"23",X"1D", + X"19",X"7E",X"A7",X"CA",X"5D",X"2B",X"CD",X"0B",X"30",X"A7",X"CA",X"6A",X"2B",X"DD",X"7E",X"15", + X"FE",X"03",X"D2",X"6A",X"2B",X"CD",X"2A",X"30",X"A7",X"C8",X"DD",X"66",X"0E",X"DD",X"6E",X"0D", + X"E5",X"FD",X"E1",X"11",X"04",X"00",X"DD",X"7E",X"0C",X"A7",X"CA",X"92",X"2B",X"FD",X"19",X"3D", + X"C2",X"7D",X"2B",X"FD",X"7E",X"00",X"FE",X"80",X"C2",X"92",X"2B",X"DD",X"36",X"0C",X"00",X"C3", + X"6A",X"2B",X"DD",X"7E",X"03",X"FD",X"86",X"01",X"57",X"DD",X"77",X"03",X"DD",X"7E",X"04",X"FD", + X"86",X"00",X"5F",X"DD",X"77",X"04",X"FD",X"66",X"02",X"DD",X"74",X"0F",X"FD",X"6E",X"03",X"DD", + X"7E",X"1F",X"CD",X"62",X"32",X"21",X"16",X"9C",X"CB",X"F6",X"DD",X"34",X"0C",X"FD",X"21",X"87", + X"47",X"11",X"03",X"00",X"DD",X"4E",X"10",X"0D",X"CA",X"D0",X"2B",X"FD",X"19",X"C3",X"C7",X"2B", + X"DD",X"7E",X"03",X"FD",X"BE",X"01",X"D0",X"FD",X"BE",X"02",X"D8",X"3A",X"40",X"9A",X"FE",X"00", + X"C2",X"16",X"2C",X"21",X"40",X"9A",X"DD",X"5E",X"10",X"16",X"00",X"CB",X"23",X"1D",X"19",X"7E", + X"A7",X"C2",X"16",X"2C",X"DD",X"7E",X"10",X"FE",X"06",X"CA",X"10",X"2C",X"DD",X"7E",X"0B",X"FE", + X"10",X"CA",X"0A",X"2C",X"21",X"E3",X"48",X"C3",X"56",X"2C",X"21",X"9A",X"48",X"C3",X"56",X"2C", + X"21",X"2C",X"49",X"C3",X"56",X"2C",X"DD",X"7E",X"10",X"FE",X"06",X"CA",X"53",X"2C",X"ED",X"5F", + X"47",X"3A",X"59",X"9A",X"80",X"DD",X"86",X"02",X"EA",X"3F",X"2C",X"DD",X"7E",X"0B",X"FE",X"10", + X"CA",X"39",X"2C",X"21",X"87",X"49",X"C3",X"56",X"2C",X"21",X"72",X"49",X"C3",X"56",X"2C",X"DD", + X"7E",X"0B",X"FE",X"10",X"CA",X"4D",X"2C",X"21",X"9C",X"49",X"C3",X"56",X"2C",X"21",X"AD",X"49", + X"C3",X"56",X"2C",X"21",X"5D",X"49",X"DD",X"74",X"0E",X"DD",X"75",X"0D",X"DD",X"36",X"0C",X"00", + X"DD",X"36",X"09",X"11",X"C9",X"DD",X"7E",X"09",X"FE",X"11",X"C0",X"DD",X"36",X"15",X"00",X"21", + X"40",X"9A",X"DD",X"5E",X"10",X"16",X"00",X"CB",X"23",X"19",X"7E",X"A7",X"CA",X"83",X"2C",X"DD", + X"36",X"0A",X"FF",X"DD",X"66",X"0E",X"DD",X"6E",X"0D",X"11",X"04",X"00",X"DD",X"7E",X"0C",X"A7", + X"CA",X"98",X"2C",X"19",X"3D",X"C2",X"93",X"2C",X"DD",X"7E",X"04",X"86",X"DD",X"77",X"04",X"5F", + X"23",X"DD",X"7E",X"03",X"86",X"DD",X"77",X"03",X"57",X"23",X"46",X"23",X"4E",X"DD",X"70",X"0F", + X"23",X"7E",X"FE",X"80",X"CA",X"C3",X"2C",X"C5",X"E1",X"DD",X"7E",X"1F",X"CD",X"62",X"32",X"DD", + X"34",X"0C",X"C9",X"CD",X"F6",X"2F",X"21",X"40",X"9A",X"7E",X"FE",X"00",X"C2",X"E5",X"2C",X"DD", + X"5E",X"10",X"16",X"00",X"CB",X"23",X"1D",X"19",X"7E",X"A7",X"C2",X"E5",X"2C",X"36",X"FF",X"DD", + X"56",X"10",X"CD",X"A6",X"36",X"DD",X"36",X"09",X"12",X"21",X"40",X"9A",X"DD",X"5E",X"10",X"16", + X"00",X"CB",X"23",X"19",X"36",X"FF",X"DD",X"36",X"06",X"10",X"C9",X"DD",X"7E",X"09",X"FE",X"12", + X"C0",X"DD",X"7E",X"0A",X"A7",X"C2",X"65",X"2D",X"DD",X"35",X"06",X"C0",X"DD",X"7E",X"07",X"A7", + X"C0",X"CD",X"0B",X"30",X"A7",X"CA",X"2C",X"2D",X"DD",X"7E",X"15",X"FE",X"03",X"D2",X"2C",X"2D", + X"CD",X"2A",X"30",X"A7",X"CA",X"2C",X"2D",X"DD",X"36",X"06",X"10",X"C9",X"DD",X"7E",X"0F",X"FE", + X"FF",X"CA",X"3A",X"2D",X"CD",X"F6",X"2F",X"C3",X"60",X"2D",X"DD",X"7E",X"10",X"21",X"A3",X"47", + X"11",X"04",X"00",X"19",X"3D",X"C2",X"43",X"2D",X"5E",X"DD",X"73",X"04",X"23",X"56",X"DD",X"72", + X"03",X"23",X"46",X"DD",X"70",X"0F",X"23",X"4E",X"C5",X"E1",X"DD",X"7E",X"1F",X"CD",X"62",X"32", + X"DD",X"36",X"06",X"10",X"C9",X"DD",X"36",X"15",X"00",X"DD",X"7E",X"10",X"FE",X"06",X"DA",X"8E", + X"2D",X"5F",X"FE",X"08",X"CA",X"00",X"2E",X"ED",X"5F",X"E6",X"7F",X"EA",X"8E",X"2D",X"21",X"40", + X"9A",X"16",X"00",X"CB",X"23",X"19",X"36",X"00",X"23",X"7E",X"A7",X"C2",X"00",X"2E",X"21",X"68", + X"4A",X"DD",X"7E",X"10",X"3D",X"CA",X"9D",X"2D",X"23",X"23",X"C3",X"94",X"2D",X"7E",X"DD",X"77", + X"04",X"23",X"7E",X"DD",X"77",X"03",X"DD",X"7E",X"10",X"FE",X"03",X"CA",X"C2",X"2D",X"FE",X"04", + X"CA",X"CC",X"2D",X"FE",X"05",X"CA",X"D6",X"2D",X"21",X"C7",X"47",X"DD",X"36",X"0B",X"20",X"C3", + X"DD",X"2D",X"21",X"09",X"48",X"DD",X"36",X"0B",X"10",X"C3",X"DD",X"2D",X"21",X"E8",X"47",X"DD", + X"36",X"0B",X"10",X"C3",X"DD",X"2D",X"21",X"E8",X"47",X"DD",X"36",X"0B",X"10",X"DD",X"74",X"0E", + X"DD",X"75",X"0D",X"DD",X"36",X"0C",X"00",X"DD",X"36",X"09",X"10",X"21",X"40",X"9A",X"16",X"00", + X"DD",X"5E",X"10",X"CB",X"23",X"19",X"36",X"00",X"DD",X"34",X"10",X"DD",X"36",X"0A",X"00",X"C9", + X"DD",X"7E",X"10",X"FE",X"08",X"CA",X"12",X"2E",X"21",X"BE",X"49",X"DD",X"36",X"0B",X"20",X"C3", + X"19",X"2E",X"21",X"E2",X"49",X"DD",X"36",X"0B",X"10",X"DD",X"74",X"0E",X"DD",X"75",X"0D",X"21", + X"68",X"4A",X"DD",X"7E",X"10",X"3D",X"CA",X"2E",X"2E",X"23",X"23",X"C3",X"25",X"2E",X"7E",X"DD", + X"77",X"04",X"23",X"7E",X"DD",X"77",X"03",X"DD",X"36",X"0C",X"00",X"DD",X"36",X"09",X"20",X"C9", + X"DD",X"7E",X"04",X"FE",X"E8",X"DA",X"7F",X"2F",X"DD",X"66",X"0E",X"DD",X"6E",X"0D",X"11",X"04", + X"00",X"DD",X"7E",X"0C",X"A7",X"CA",X"5D",X"2E",X"19",X"3D",X"C2",X"58",X"2E",X"DD",X"7E",X"04", + X"86",X"DD",X"77",X"04",X"5F",X"23",X"DD",X"7E",X"03",X"86",X"DD",X"77",X"03",X"57",X"23",X"46", + X"DD",X"70",X"0F",X"23",X"4E",X"C5",X"E1",X"DD",X"7E",X"1F",X"CD",X"62",X"32",X"21",X"16",X"9C", + X"CB",X"F6",X"DD",X"34",X"0C",X"DD",X"7E",X"0B",X"FE",X"10",X"CA",X"98",X"2E",X"3A",X"54",X"9A", + X"CB",X"47",X"C2",X"FA",X"2E",X"C3",X"A3",X"2E",X"3A",X"54",X"9A",X"CB",X"4F",X"C2",X"FA",X"2E", + X"C3",X"BB",X"2E",X"DD",X"7E",X"03",X"FD",X"21",X"20",X"9A",X"FD",X"BE",X"03",X"DA",X"31",X"2F", + X"D6",X"14",X"FD",X"BE",X"03",X"D2",X"31",X"2F",X"C3",X"D0",X"2E",X"DD",X"7E",X"03",X"FD",X"21", + X"20",X"9A",X"FD",X"BE",X"03",X"D2",X"31",X"2F",X"C6",X"14",X"FD",X"BE",X"03",X"DA",X"31",X"2F", + X"DD",X"36",X"01",X"0F",X"FD",X"36",X"06",X"FF",X"DD",X"7E",X"0B",X"FE",X"10",X"CA",X"E6",X"2E", + X"21",X"06",X"4A",X"C3",X"E9",X"2E",X"21",X"37",X"4A",X"DD",X"74",X"0E",X"DD",X"75",X"0D",X"DD", + X"36",X"0C",X"00",X"DD",X"7E",X"1F",X"FD",X"77",X"12",X"C9",X"DD",X"7E",X"0B",X"FE",X"10",X"CA", + X"0C",X"2F",X"DD",X"36",X"0B",X"10",X"21",X"E8",X"47",X"C3",X"13",X"2F",X"DD",X"36",X"0B",X"20", + X"21",X"C7",X"47",X"DD",X"74",X"0E",X"DD",X"75",X"0D",X"DD",X"7E",X"01",X"FE",X"0F",X"CA",X"28", + X"2F",X"DD",X"36",X"01",X"0F",X"C3",X"2C",X"2F",X"DD",X"36",X"01",X"03",X"DD",X"36",X"0C",X"00", + X"C9",X"DD",X"7E",X"03",X"FE",X"E6",X"D2",X"6A",X"2F",X"FE",X"1B",X"DA",X"6A",X"2F",X"DD",X"66", + X"0E",X"DD",X"6E",X"0D",X"11",X"04",X"00",X"DD",X"7E",X"0C",X"A7",X"C8",X"19",X"3D",X"C2",X"4C", + X"2F",X"19",X"7E",X"FE",X"80",X"C0",X"DD",X"7E",X"0B",X"FE",X"10",X"CA",X"64",X"2F",X"21",X"C7", + X"47",X"C3",X"74",X"2F",X"21",X"E8",X"47",X"C3",X"74",X"2F",X"3A",X"54",X"9A",X"A7",X"CA",X"FA", + X"2E",X"21",X"91",X"48",X"DD",X"74",X"0E",X"DD",X"75",X"0D",X"DD",X"36",X"0C",X"00",X"C9",X"DD", + X"66",X"0E",X"DD",X"6E",X"0D",X"E5",X"FD",X"E1",X"11",X"04",X"00",X"DD",X"7E",X"0C",X"A7",X"CA", + X"98",X"2F",X"FD",X"19",X"3D",X"C2",X"92",X"2F",X"DD",X"7E",X"03",X"FD",X"86",X"01",X"57",X"DD", + X"77",X"03",X"DD",X"7E",X"04",X"FD",X"86",X"00",X"5F",X"DD",X"77",X"04",X"FD",X"66",X"02",X"DD", + X"74",X"0F",X"FD",X"6E",X"03",X"DD",X"7E",X"1F",X"CD",X"62",X"32",X"21",X"16",X"9C",X"CB",X"F6", + X"DD",X"34",X"0C",X"DD",X"7E",X"04",X"FE",X"E8",X"D8",X"DD",X"7E",X"03",X"FD",X"21",X"20",X"9A", + X"FD",X"BE",X"03",X"DA",X"E0",X"2F",X"DD",X"36",X"0B",X"20",X"21",X"C7",X"47",X"C3",X"E7",X"2F", + X"DD",X"36",X"0B",X"10",X"21",X"E8",X"47",X"DD",X"74",X"0E",X"DD",X"75",X"0D",X"DD",X"36",X"0C", + X"00",X"DD",X"36",X"01",X"03",X"C9",X"16",X"08",X"1E",X"10",X"DD",X"73",X"04",X"26",X"FF",X"DD", + X"74",X"0F",X"2E",X"0F",X"DD",X"7E",X"1F",X"CD",X"62",X"32",X"C9",X"FD",X"21",X"20",X"9A",X"DD", + X"7E",X"03",X"C6",X"20",X"FD",X"BE",X"03",X"DA",X"28",X"30",X"DD",X"7E",X"03",X"D6",X"20",X"FD", + X"BE",X"03",X"D2",X"28",X"30",X"3E",X"FF",X"C9",X"AF",X"C9",X"FD",X"21",X"00",X"98",X"11",X"10", + X"00",X"FD",X"7E",X"00",X"A7",X"CA",X"4A",X"30",X"FD",X"19",X"FD",X"E5",X"E1",X"01",X"90",X"98", + X"ED",X"42",X"CA",X"48",X"30",X"C3",X"31",X"30",X"AF",X"C9",X"DD",X"34",X"15",X"FD",X"36",X"00", + X"FF",X"FD",X"36",X"05",X"00",X"FD",X"36",X"06",X"00",X"FD",X"36",X"07",X"04",X"FD",X"36",X"0A", + X"00",X"DD",X"36",X"07",X"FF",X"FD",X"E5",X"E1",X"DD",X"74",X"14",X"DD",X"75",X"13",X"DD",X"7E", + X"09",X"FE",X"12",X"CA",X"E8",X"30",X"DD",X"56",X"03",X"DD",X"5E",X"04",X"26",X"67",X"2E",X"12", + X"DD",X"7E",X"1F",X"CD",X"62",X"32",X"DD",X"7E",X"03",X"D6",X"04",X"FD",X"77",X"03",X"DD",X"7E", + X"04",X"D6",X"06",X"FD",X"77",X"04",X"21",X"40",X"9A",X"7E",X"FE",X"00",X"CA",X"C2",X"30",X"DD", + X"5E",X"10",X"16",X"00",X"CB",X"23",X"1D",X"19",X"7E",X"A7",X"C2",X"C2",X"30",X"DD",X"7E",X"10", + X"21",X"9F",X"47",X"3D",X"CA",X"BB",X"30",X"23",X"C3",X"B3",X"30",X"7E",X"FD",X"77",X"09",X"C3", + X"C6",X"30",X"FD",X"36",X"09",X"EB",X"DD",X"7E",X"10",X"FE",X"06",X"CA",X"DC",X"30",X"DD",X"7E", + X"0B",X"FE",X"10",X"C2",X"E2",X"30",X"21",X"31",X"47",X"C3",X"36",X"31",X"21",X"58",X"47",X"C3", + X"36",X"31",X"21",X"F3",X"46",X"C3",X"36",X"31",X"DD",X"7E",X"10",X"21",X"A3",X"47",X"11",X"04", + X"00",X"19",X"3D",X"C2",X"F1",X"30",X"7E",X"DD",X"77",X"04",X"5F",X"D6",X"08",X"FD",X"77",X"04", + X"23",X"56",X"DD",X"72",X"03",X"FD",X"72",X"03",X"FD",X"36",X"09",X"EB",X"2E",X"12",X"DD",X"7E", + X"10",X"3D",X"CB",X"4F",X"CA",X"28",X"31",X"26",X"2B",X"DD",X"74",X"0F",X"DD",X"7E",X"1F",X"CD", + X"62",X"32",X"21",X"58",X"47",X"C3",X"36",X"31",X"26",X"33",X"DD",X"74",X"0F",X"DD",X"7E",X"1F", + X"CD",X"62",X"32",X"21",X"1A",X"47",X"FD",X"74",X"0C",X"FD",X"75",X"0B",X"3E",X"FF",X"C9",X"3A", + X"59",X"9A",X"DD",X"86",X"02",X"DD",X"A6",X"01",X"C0",X"FD",X"35",X"06",X"C0",X"FD",X"36",X"00", + X"00",X"FD",X"36",X"05",X"00",X"FD",X"36",X"06",X"00",X"FD",X"36",X"07",X"00",X"FD",X"36",X"0A", + X"00",X"11",X"F0",X"08",X"21",X"FF",X"FF",X"FD",X"7E",X"0E",X"CD",X"0E",X"32",X"C9",X"3A",X"29", + X"9A",X"A7",X"C8",X"3A",X"3D",X"9A",X"A7",X"C0",X"FD",X"E5",X"FD",X"21",X"20",X"9A",X"21",X"F8", + X"45",X"FD",X"7E",X"11",X"96",X"FD",X"BE",X"0B",X"D2",X"B1",X"31",X"23",X"FD",X"7E",X"11",X"86", + X"FD",X"BE",X"0B",X"DA",X"B1",X"31",X"23",X"FD",X"7E",X"10",X"96",X"FD",X"BE",X"0A",X"D2",X"B1", + X"31",X"23",X"FD",X"7E",X"10",X"86",X"FD",X"BE",X"0A",X"DA",X"B1",X"31",X"3E",X"FF",X"FD",X"E1", + X"C9",X"AF",X"FD",X"E1",X"C9",X"DD",X"E5",X"FD",X"E5",X"DD",X"21",X"3C",X"4C",X"FD",X"21",X"0C", + X"4F",X"3A",X"5D",X"9A",X"47",X"3A",X"00",X"9C",X"90",X"FE",X"01",X"C2",X"D6",X"31",X"3E",X"00", + X"92",X"57",X"3E",X"00",X"93",X"5F",X"0E",X"04",X"DD",X"6E",X"04",X"DD",X"66",X"05",X"FD",X"7E", + X"00",X"CB",X"DF",X"77",X"DD",X"6E",X"00",X"DD",X"66",X"01",X"FD",X"7E",X"01",X"82",X"77",X"DD", + X"6E",X"02",X"DD",X"66",X"03",X"FD",X"7E",X"02",X"83",X"77",X"C5",X"01",X"04",X"00",X"DD",X"09", + X"DD",X"09",X"FD",X"09",X"C1",X"0D",X"C2",X"D8",X"31",X"FD",X"E1",X"DD",X"E1",X"C9",X"DD",X"E5", + X"FD",X"E5",X"DD",X"21",X"3C",X"4C",X"4F",X"06",X"00",X"CB",X"21",X"CB",X"10",X"CB",X"21",X"CB", + X"10",X"CB",X"21",X"CB",X"10",X"DD",X"09",X"3A",X"5D",X"9A",X"47",X"3A",X"00",X"9C",X"90",X"FE", + X"01",X"CA",X"37",X"32",X"C3",X"3F",X"32",X"3E",X"00",X"92",X"57",X"3E",X"00",X"93",X"5F",X"DD", + X"4E",X"00",X"DD",X"46",X"01",X"7A",X"D6",X"02",X"02",X"DD",X"4E",X"02",X"DD",X"46",X"03",X"7B", + X"D6",X"02",X"02",X"DD",X"4E",X"04",X"DD",X"46",X"05",X"CB",X"DC",X"7C",X"02",X"FD",X"E1",X"DD", + X"E1",X"C9",X"DD",X"E5",X"FD",X"E5",X"DD",X"21",X"FC",X"4B",X"4F",X"06",X"00",X"CB",X"21",X"CB", + X"10",X"CB",X"21",X"CB",X"10",X"CB",X"21",X"CB",X"10",X"DD",X"09",X"3A",X"5D",X"9A",X"47",X"3A", + X"00",X"9C",X"90",X"FE",X"01",X"CA",X"8B",X"32",X"C3",X"97",X"32",X"3E",X"00",X"92",X"57",X"3E", + X"00",X"93",X"5F",X"7C",X"EE",X"02",X"67",X"DD",X"4E",X"00",X"DD",X"46",X"01",X"7A",X"D6",X"08", + X"02",X"DD",X"4E",X"02",X"DD",X"46",X"03",X"7B",X"D6",X"08",X"02",X"DD",X"4E",X"04",X"DD",X"46", + X"05",X"7C",X"02",X"DD",X"4E",X"06",X"DD",X"46",X"07",X"7D",X"02",X"FD",X"E1",X"DD",X"E1",X"C9", + X"DD",X"E5",X"FD",X"E5",X"DD",X"2A",X"60",X"9A",X"7A",X"CB",X"3F",X"CB",X"3F",X"CB",X"3F",X"FE", + X"1C",X"D4",X"94",X"33",X"06",X"00",X"D6",X"02",X"DC",X"99",X"33",X"4F",X"FD",X"21",X"1B",X"84", + X"CB",X"21",X"CB",X"10",X"CB",X"21",X"CB",X"10",X"CB",X"21",X"CB",X"10",X"CB",X"21",X"CB",X"10", + X"CB",X"21",X"CB",X"10",X"FD",X"09",X"7B",X"CB",X"3F",X"CB",X"3F",X"CB",X"3F",X"D6",X"04",X"4F", + X"06",X"00",X"A7",X"FD",X"E5",X"E1",X"ED",X"42",X"E5",X"FD",X"E1",X"7A",X"E6",X"07",X"CB",X"3F", + X"4F",X"06",X"00",X"21",X"00",X"00",X"C5",X"E1",X"CB",X"21",X"CB",X"10",X"CB",X"21",X"CB",X"10", + X"CB",X"21",X"CB",X"10",X"CB",X"25",X"CB",X"14",X"09",X"E5",X"C1",X"DD",X"56",X"00",X"DD",X"5E", + X"01",X"DD",X"09",X"01",X"20",X"00",X"2E",X"05",X"FD",X"E5",X"DD",X"7E",X"02",X"FD",X"77",X"00", + X"FD",X"09",X"DD",X"23",X"2D",X"C2",X"3A",X"33",X"FD",X"E1",X"FD",X"E5",X"FD",X"2B",X"2E",X"05", + X"DD",X"7E",X"02",X"FD",X"77",X"00",X"FD",X"09",X"DD",X"23",X"2D",X"C2",X"50",X"33",X"3A",X"52", + X"9A",X"CB",X"47",X"CC",X"92",X"33",X"7A",X"FD",X"E1",X"01",X"00",X"08",X"FD",X"09",X"01",X"20", + X"00",X"FD",X"E5",X"2E",X"05",X"FD",X"77",X"00",X"FD",X"09",X"2D",X"C2",X"75",X"33",X"2E",X"05", + X"FD",X"E1",X"FD",X"2B",X"FD",X"77",X"00",X"FD",X"09",X"2D",X"C2",X"84",X"33",X"FD",X"E1",X"DD", + X"E1",X"C9",X"53",X"C9",X"3E",X"1C",X"16",X"E0",X"C9",X"3E",X"00",X"C9",X"21",X"1C",X"4F",X"22", + X"60",X"9A",X"CD",X"C0",X"32",X"C9",X"21",X"7A",X"4F",X"22",X"60",X"9A",X"CD",X"C0",X"32",X"C9", + X"21",X"A4",X"4F",X"22",X"60",X"9A",X"CD",X"C0",X"32",X"C9",X"53",X"C9",X"DD",X"E5",X"FD",X"E5", + X"DD",X"21",X"46",X"4F",X"7A",X"CB",X"3F",X"CB",X"3F",X"CB",X"3F",X"06",X"00",X"D6",X"02",X"DC", + X"99",X"33",X"4F",X"CB",X"21",X"CB",X"10",X"CB",X"21",X"CB",X"10",X"CB",X"21",X"CB",X"10",X"CB", + X"21",X"CB",X"10",X"CB",X"21",X"CB",X"10",X"FD",X"21",X"1B",X"84",X"FD",X"09",X"7B",X"CB",X"3F", + X"CB",X"3F",X"CB",X"3F",X"D6",X"04",X"06",X"00",X"4F",X"A7",X"FD",X"E5",X"E1",X"ED",X"42",X"E5", + X"FD",X"E1",X"7A",X"E6",X"07",X"CB",X"3F",X"4F",X"06",X"00",X"C5",X"E1",X"CB",X"21",X"CB",X"10", + X"CB",X"21",X"CB",X"10",X"CB",X"25",X"CB",X"14",X"09",X"E5",X"C1",X"DD",X"56",X"00",X"DD",X"5E", + X"01",X"DD",X"09",X"01",X"20",X"00",X"2E",X"03",X"FD",X"E5",X"DD",X"7E",X"02",X"FD",X"77",X"00", + X"FD",X"09",X"DD",X"23",X"2D",X"C2",X"2A",X"34",X"FD",X"E1",X"FD",X"E5",X"FD",X"2B",X"2E",X"03", + X"DD",X"7E",X"02",X"FD",X"77",X"00",X"FD",X"09",X"DD",X"23",X"2D",X"C2",X"40",X"34",X"3A",X"52", + X"9A",X"CB",X"47",X"CC",X"BA",X"33",X"7A",X"FD",X"E1",X"01",X"00",X"08",X"FD",X"09",X"01",X"20", + X"00",X"FD",X"E5",X"2E",X"03",X"FD",X"77",X"00",X"FD",X"09",X"2D",X"C2",X"65",X"34",X"FD",X"E1", + X"FD",X"2B",X"2E",X"03",X"FD",X"77",X"00",X"FD",X"09",X"2D",X"C2",X"74",X"34",X"FD",X"E1",X"DD", + X"E1",X"C9",X"DD",X"E5",X"FD",X"E5",X"DD",X"21",X"60",X"4F",X"7A",X"CB",X"3F",X"CB",X"3F",X"CB", + X"3F",X"06",X"00",X"D6",X"02",X"DC",X"99",X"33",X"4F",X"CB",X"21",X"CB",X"10",X"CB",X"21",X"CB", + X"10",X"CB",X"21",X"CB",X"10",X"CB",X"21",X"CB",X"10",X"CB",X"21",X"CB",X"10",X"FD",X"21",X"1B", + X"84",X"FD",X"09",X"7B",X"CB",X"3F",X"CB",X"3F",X"CB",X"3F",X"D6",X"04",X"06",X"00",X"4F",X"A7", + X"FD",X"E5",X"E1",X"ED",X"42",X"E5",X"FD",X"E1",X"7A",X"E6",X"07",X"CB",X"3F",X"4F",X"06",X"00", + X"C5",X"E1",X"CB",X"21",X"CB",X"10",X"CB",X"21",X"CB",X"10",X"CB",X"25",X"CB",X"14",X"09",X"E5", + X"C1",X"DD",X"56",X"00",X"DD",X"5E",X"01",X"DD",X"09",X"01",X"20",X"00",X"2E",X"03",X"FD",X"E5", + X"DD",X"7E",X"02",X"FD",X"77",X"00",X"FD",X"09",X"DD",X"23",X"2D",X"C2",X"F0",X"34",X"FD",X"E1", + X"FD",X"E5",X"FD",X"2B",X"2E",X"03",X"DD",X"7E",X"02",X"FD",X"77",X"00",X"FD",X"09",X"DD",X"23", + X"2D",X"C2",X"06",X"35",X"3A",X"52",X"9A",X"CB",X"47",X"CC",X"BA",X"33",X"7A",X"FD",X"E1",X"01", + X"00",X"08",X"FD",X"09",X"01",X"20",X"00",X"FD",X"E5",X"2E",X"03",X"FD",X"77",X"00",X"FD",X"09", + X"2D",X"C2",X"2B",X"35",X"FD",X"E1",X"FD",X"2B",X"2E",X"03",X"FD",X"77",X"00",X"FD",X"09",X"2D", + X"C2",X"3A",X"35",X"FD",X"E1",X"DD",X"E1",X"C9",X"DD",X"E5",X"FD",X"E5",X"15",X"5A",X"CB",X"23", + X"16",X"00",X"DD",X"21",X"FC",X"4E",X"DD",X"19",X"DD",X"5E",X"00",X"DD",X"56",X"01",X"3A",X"5E", + X"9A",X"4F",X"06",X"00",X"C5",X"E1",X"CB",X"21",X"CB",X"10",X"CB",X"21",X"CB",X"10",X"CB",X"21", + X"CB",X"10",X"CB",X"21",X"CB",X"10",X"CB",X"21",X"CB",X"10",X"CB",X"25",X"CB",X"14",X"CB",X"25", + X"CB",X"14",X"09",X"E5",X"C1",X"DD",X"21",X"BC",X"4C",X"DD",X"09",X"01",X"20",X"00",X"D5",X"FD", + X"E1",X"2E",X"04",X"DD",X"7E",X"00",X"FD",X"77",X"00",X"FD",X"09",X"DD",X"23",X"2D",X"C2",X"93", + X"35",X"D5",X"FD",X"E1",X"FD",X"2B",X"2E",X"04",X"DD",X"7E",X"00",X"FD",X"77",X"00",X"FD",X"09", + X"DD",X"23",X"2D",X"C2",X"A8",X"35",X"D5",X"FD",X"E1",X"FD",X"2B",X"FD",X"2B",X"2E",X"04",X"DD", + X"7E",X"00",X"FD",X"77",X"00",X"FD",X"09",X"DD",X"23",X"2D",X"C2",X"BF",X"35",X"D5",X"FD",X"E1", + X"FD",X"2B",X"FD",X"2B",X"FD",X"2B",X"3A",X"52",X"9A",X"CB",X"47",X"CC",X"4B",X"36",X"D5",X"FD", + X"E1",X"01",X"00",X"08",X"FD",X"09",X"01",X"20",X"00",X"2E",X"04",X"DD",X"7E",X"00",X"FD",X"77", + X"00",X"FD",X"09",X"DD",X"23",X"2D",X"C2",X"EB",X"35",X"D5",X"FD",X"E1",X"01",X"00",X"08",X"FD", + X"2B",X"FD",X"09",X"01",X"20",X"00",X"2E",X"04",X"DD",X"7E",X"00",X"FD",X"77",X"00",X"FD",X"09", + X"DD",X"23",X"2D",X"C2",X"08",X"36",X"D5",X"FD",X"E1",X"01",X"00",X"08",X"FD",X"2B",X"FD",X"2B", + X"FD",X"09",X"01",X"20",X"00",X"2E",X"04",X"DD",X"7E",X"00",X"FD",X"77",X"00",X"FD",X"09",X"DD", + X"23",X"2D",X"C2",X"27",X"36",X"D5",X"FD",X"E1",X"01",X"00",X"08",X"FD",X"2B",X"FD",X"2B",X"FD", + X"2B",X"FD",X"09",X"01",X"20",X"00",X"FD",X"E1",X"DD",X"E1",X"C9",X"01",X"0C",X"00",X"DD",X"09", + X"C9",X"3A",X"40",X"9A",X"FE",X"00",X"CA",X"76",X"36",X"FE",X"01",X"CA",X"8E",X"36",X"7A",X"FE", + X"04",X"DA",X"6D",X"36",X"3E",X"05",X"32",X"5E",X"9A",X"CD",X"48",X"35",X"C9",X"3E",X"04",X"32", + X"5E",X"9A",X"CD",X"48",X"35",X"C9",X"7A",X"FE",X"04",X"DA",X"85",X"36",X"3E",X"01",X"32",X"5E", + X"9A",X"CD",X"48",X"35",X"C9",X"3E",X"00",X"32",X"5E",X"9A",X"CD",X"48",X"35",X"C9",X"7A",X"FE", + X"04",X"DA",X"9D",X"36",X"3E",X"09",X"32",X"5E",X"9A",X"CD",X"48",X"35",X"C9",X"3E",X"08",X"32", + X"5E",X"9A",X"CD",X"48",X"35",X"C9",X"3A",X"40",X"9A",X"FE",X"00",X"CA",X"CB",X"36",X"FE",X"01", + X"CA",X"E3",X"36",X"7A",X"FE",X"04",X"DA",X"C2",X"36",X"3E",X"07",X"32",X"5E",X"9A",X"CD",X"48", + X"35",X"C9",X"3E",X"06",X"32",X"5E",X"9A",X"CD",X"48",X"35",X"C9",X"7A",X"FE",X"04",X"DA",X"DA", + X"36",X"3E",X"03",X"32",X"5E",X"9A",X"CD",X"48",X"35",X"C9",X"3E",X"02",X"32",X"5E",X"9A",X"CD", + X"48",X"35",X"C9",X"7A",X"FE",X"04",X"DA",X"F2",X"36",X"3E",X"0B",X"32",X"5E",X"9A",X"CD",X"48", + X"35",X"C9",X"3E",X"0A",X"32",X"5E",X"9A",X"CD",X"48",X"35",X"C9",X"7A",X"FE",X"04",X"DA",X"0A", + X"37",X"3E",X"0D",X"32",X"5E",X"9A",X"CD",X"48",X"35",X"C9",X"3E",X"0C",X"32",X"5E",X"9A",X"CD", + X"48",X"35",X"C9",X"7A",X"FE",X"04",X"DA",X"22",X"37",X"3E",X"0F",X"32",X"5E",X"9A",X"CD",X"48", + X"35",X"C9",X"3E",X"0E",X"32",X"5E",X"9A",X"CD",X"48",X"35",X"C9",X"CD",X"55",X"37",X"3A",X"6A", + X"9C",X"47",X"3A",X"6B",X"9C",X"B0",X"C0",X"3E",X"FF",X"32",X"6C",X"9C",X"AF",X"CD",X"B5",X"10", + X"C9",X"3A",X"76",X"9C",X"3C",X"32",X"76",X"9C",X"06",X"0F",X"0E",X"26",X"0D",X"C2",X"4C",X"37", + X"05",X"C2",X"4A",X"37",X"C9",X"CD",X"41",X"37",X"3A",X"FB",X"9B",X"A7",X"CA",X"5D",X"39",X"AF", + X"32",X"FB",X"9B",X"32",X"6A",X"9C",X"32",X"6B",X"9C",X"32",X"84",X"9C",X"32",X"80",X"9C",X"32", + X"7E",X"9C",X"21",X"70",X"00",X"22",X"82",X"9C",X"DD",X"21",X"01",X"9C",X"21",X"78",X"9C",X"11", + X"6A",X"9C",X"CD",X"9F",X"37",X"DD",X"21",X"07",X"9C",X"21",X"7A",X"9C",X"11",X"6B",X"9C",X"CD", + X"9F",X"37",X"3A",X"6A",X"9C",X"47",X"3A",X"6B",X"9C",X"B0",X"C8",X"CD",X"A5",X"3A",X"C9",X"FD", + X"21",X"64",X"3B",X"CD",X"16",X"39",X"A7",X"C8",X"FD",X"21",X"5A",X"9C",X"CD",X"16",X"39",X"A7", + X"C8",X"3E",X"FF",X"12",X"FD",X"21",X"4A",X"9C",X"CD",X"16",X"39",X"A7",X"CA",X"2F",X"38",X"FD", + X"21",X"3A",X"9C",X"CD",X"16",X"39",X"A7",X"CA",X"65",X"38",X"FD",X"21",X"2A",X"9C",X"CD",X"16", + X"39",X"A7",X"CA",X"9C",X"38",X"FD",X"21",X"1A",X"9C",X"CD",X"16",X"39",X"A7",X"CA",X"D9",X"38", + X"FD",X"22",X"7C",X"9C",X"ED",X"4B",X"7C",X"9C",X"71",X"23",X"70",X"21",X"5A",X"9C",X"11",X"0F", + X"00",X"19",X"EB",X"21",X"5A",X"9C",X"2B",X"01",X"3F",X"00",X"ED",X"B8",X"21",X"1A",X"9C",X"23", + X"54",X"5D",X"2B",X"3E",X"FF",X"77",X"01",X"0F",X"00",X"ED",X"B0",X"11",X"1A",X"9C",X"DD",X"22", + X"7C",X"9C",X"2A",X"7C",X"9C",X"01",X"06",X"00",X"ED",X"B0",X"2A",X"7C",X"9C",X"11",X"01",X"9C", + X"A7",X"ED",X"52",X"C8",X"2A",X"78",X"9C",X"11",X"10",X"00",X"19",X"22",X"78",X"9C",X"C9",X"01", + X"5A",X"9C",X"71",X"23",X"70",X"21",X"5A",X"9C",X"23",X"54",X"5D",X"2B",X"3E",X"FF",X"77",X"01", + X"0F",X"00",X"ED",X"B0",X"DD",X"22",X"7C",X"9C",X"2A",X"7C",X"9C",X"11",X"5A",X"9C",X"01",X"06", + X"00",X"ED",X"B0",X"3A",X"84",X"9C",X"A7",X"C2",X"60",X"38",X"3E",X"FF",X"32",X"84",X"9C",X"C9", + X"AF",X"32",X"6A",X"9C",X"C9",X"01",X"4A",X"9C",X"71",X"23",X"70",X"21",X"4A",X"9C",X"11",X"5A", + X"9C",X"01",X"0F",X"00",X"ED",X"B0",X"21",X"4A",X"9C",X"23",X"54",X"5D",X"2B",X"3E",X"FF",X"77", + X"01",X"0F",X"00",X"ED",X"B0",X"DD",X"22",X"7C",X"9C",X"2A",X"7C",X"9C",X"11",X"4A",X"9C",X"01", + X"06",X"00",X"ED",X"B0",X"DD",X"21",X"4A",X"9C",X"CD",X"40",X"3B",X"C9",X"01",X"3A",X"9C",X"71", + X"23",X"70",X"21",X"5A",X"9C",X"11",X"0F",X"00",X"19",X"EB",X"21",X"5A",X"9C",X"2B",X"01",X"1F", + X"00",X"ED",X"B8",X"21",X"3A",X"9C",X"23",X"54",X"5D",X"2B",X"01",X"0F",X"00",X"3E",X"FF",X"77", + X"ED",X"B0",X"DD",X"22",X"7C",X"9C",X"2A",X"7C",X"9C",X"11",X"3A",X"9C",X"01",X"06",X"00",X"ED", + X"B0",X"DD",X"21",X"3A",X"9C",X"CD",X"40",X"3B",X"C9",X"01",X"2A",X"9C",X"71",X"23",X"70",X"21", + X"5A",X"9C",X"11",X"0F",X"00",X"19",X"EB",X"21",X"5A",X"9C",X"2B",X"01",X"2F",X"00",X"ED",X"B8", + X"21",X"2A",X"9C",X"23",X"54",X"5D",X"2B",X"3E",X"FF",X"77",X"01",X"0F",X"00",X"ED",X"B0",X"DD", + X"22",X"7C",X"9C",X"2A",X"7C",X"9C",X"11",X"2A",X"9C",X"01",X"06",X"00",X"ED",X"B0",X"DD",X"21", + X"2A",X"9C",X"CD",X"40",X"3B",X"C9",X"DD",X"7E",X"00",X"FD",X"46",X"00",X"B8",X"DA",X"57",X"39", + X"C2",X"5A",X"39",X"DD",X"7E",X"01",X"FD",X"46",X"01",X"B8",X"DA",X"57",X"39",X"C2",X"5A",X"39", + X"DD",X"7E",X"02",X"FD",X"46",X"02",X"B8",X"DA",X"57",X"39",X"C2",X"5A",X"39",X"DD",X"7E",X"03", + X"FD",X"46",X"03",X"B8",X"DA",X"57",X"39",X"C2",X"5A",X"39",X"DD",X"7E",X"04",X"FD",X"46",X"04", + X"B8",X"DA",X"57",X"39",X"C2",X"5A",X"39",X"3E",X"00",X"C9",X"3E",X"FF",X"C9",X"DD",X"21",X"78", + X"9C",X"CD",X"8D",X"0B",X"FD",X"21",X"6A",X"9C",X"3A",X"6A",X"9C",X"A7",X"C2",X"87",X"39",X"DD", + X"21",X"7A",X"9C",X"3E",X"FF",X"32",X"5D",X"9A",X"CD",X"8D",X"0B",X"FD",X"21",X"6B",X"9C",X"3A", + X"6B",X"9C",X"A7",X"C2",X"87",X"39",X"C9",X"3A",X"76",X"9C",X"E6",X"3F",X"C0",X"2A",X"82",X"9C", + X"2B",X"22",X"82",X"9C",X"7D",X"44",X"B0",X"CA",X"29",X"3A",X"3A",X"54",X"9A",X"57",X"FE",X"01", + X"CC",X"03",X"3A",X"7A",X"FE",X"02",X"CC",X"16",X"3A",X"CD",X"64",X"3A",X"3A",X"56",X"9A",X"A7", + X"CA",X"FE",X"39",X"3A",X"93",X"9C",X"A7",X"C0",X"3E",X"FF",X"32",X"93",X"9C",X"3A",X"7E",X"9C", + X"FE",X"1C",X"CA",X"29",X"3A",X"3A",X"7E",X"9C",X"FE",X"1B",X"CA",X"3D",X"3A",X"3A",X"80",X"9C", + X"FE",X"03",X"C8",X"D0",X"6F",X"26",X"00",X"DD",X"4E",X"00",X"DD",X"46",X"01",X"09",X"22",X"7C", + X"9C",X"DD",X"2A",X"7C",X"9C",X"3A",X"7E",X"9C",X"4F",X"06",X"00",X"21",X"6A",X"3B",X"09",X"7E", + X"DD",X"77",X"06",X"3A",X"80",X"9C",X"3C",X"32",X"80",X"9C",X"CD",X"A5",X"3A",X"C9",X"AF",X"32", + X"93",X"9C",X"C9",X"3A",X"7E",X"9C",X"FE",X"1C",X"CA",X"10",X"3A",X"3C",X"32",X"7E",X"9C",X"C9", + X"3E",X"00",X"32",X"7E",X"9C",X"C9",X"3A",X"7E",X"9C",X"FE",X"00",X"CA",X"23",X"3A",X"3D",X"32", + X"7E",X"9C",X"C9",X"3E",X"1C",X"32",X"7E",X"9C",X"C9",X"AF",X"FD",X"77",X"00",X"32",X"7E",X"9C", + X"32",X"80",X"9C",X"21",X"70",X"00",X"22",X"82",X"9C",X"CD",X"A5",X"3A",X"C9",X"3A",X"80",X"9C", + X"FE",X"00",X"CA",X"FA",X"39",X"4F",X"06",X"00",X"3D",X"32",X"80",X"9C",X"DD",X"6E",X"00",X"DD", + X"66",X"01",X"09",X"22",X"7C",X"9C",X"DD",X"2A",X"7C",X"9C",X"DD",X"2B",X"3E",X"FF",X"DD",X"77", + X"06",X"C3",X"FA",X"39",X"21",X"6A",X"3B",X"06",X"00",X"3A",X"7E",X"9C",X"FE",X"1B",X"CA",X"85", + X"3A",X"FE",X"1C",X"CA",X"95",X"3A",X"4F",X"09",X"7E",X"32",X"F8",X"85",X"3E",X"FF",X"32",X"18", + X"86",X"32",X"D8",X"85",X"C9",X"3E",X"1B",X"32",X"D8",X"85",X"3E",X"1E",X"32",X"F8",X"85",X"3E", + X"0B",X"32",X"18",X"86",X"C9",X"3E",X"0E",X"32",X"D8",X"85",X"3E",X"17",X"32",X"F8",X"85",X"3E", + X"0D",X"32",X"18",X"86",X"C9",X"00",X"CD",X"B5",X"10",X"3E",X"01",X"32",X"D5",X"84",X"3E",X"02", + X"32",X"D3",X"84",X"3E",X"03",X"32",X"D1",X"84",X"3E",X"04",X"32",X"CF",X"84",X"3E",X"05",X"32", + X"CD",X"84",X"DD",X"21",X"1A",X"9C",X"21",X"15",X"85",X"CD",X"F5",X"3A",X"DD",X"21",X"2A",X"9C", + X"21",X"13",X"85",X"CD",X"F5",X"3A",X"DD",X"21",X"3A",X"9C",X"21",X"11",X"85",X"CD",X"F5",X"3A", + X"DD",X"21",X"4A",X"9C",X"21",X"0F",X"85",X"CD",X"F5",X"3A",X"DD",X"21",X"5A",X"9C",X"21",X"0D", + X"85",X"CD",X"F5",X"3A",X"C9",X"E5",X"06",X"06",X"11",X"20",X"00",X"DD",X"7E",X"00",X"77",X"DD", + X"23",X"19",X"05",X"C2",X"FB",X"3A",X"06",X"06",X"11",X"00",X"08",X"19",X"11",X"E0",X"FF",X"19", + X"3E",X"00",X"77",X"19",X"05",X"C2",X"12",X"3B",X"E1",X"11",X"20",X"01",X"19",X"06",X"0A",X"11", + X"20",X"00",X"DD",X"7E",X"00",X"77",X"DD",X"23",X"19",X"05",X"C2",X"22",X"3B",X"06",X"0A",X"11", + X"00",X"08",X"19",X"11",X"E0",X"FF",X"19",X"3E",X"01",X"77",X"19",X"05",X"C2",X"39",X"3B",X"C9", + X"2A",X"7C",X"9C",X"11",X"01",X"9C",X"A7",X"ED",X"52",X"C8",X"2A",X"78",X"9C",X"DD",X"22",X"7C", + X"9C",X"ED",X"5B",X"7C",X"9C",X"A7",X"ED",X"52",X"D8",X"2A",X"78",X"9C",X"11",X"10",X"00",X"19", + X"22",X"78",X"9C",X"C9",X"00",X"00",X"03",X"00",X"00",X"00",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F", + X"10",X"11",X"12",X"13",X"14",X"15",X"16",X"17",X"18",X"19",X"1A",X"1B",X"1C",X"1D",X"1E",X"1F", + X"20",X"21",X"22",X"23",X"4D",X"4D",X"FF",X"FF",X"FF",X"FF",X"11",X"02",X"13",X"85",X"19",X"1E", + X"1C",X"11",X"FF",X"1C",X"1D",X"0A",X"1B",X"1D",X"FF",X"0B",X"1E",X"1D",X"1D",X"18",X"17",X"0D", + X"02",X"50",X"85",X"01",X"FF",X"19",X"15",X"0A",X"22",X"0E",X"1B",X"FF",X"18",X"17",X"15",X"22", + X"0E",X"02",X"50",X"85",X"01",X"FF",X"18",X"1B",X"FF",X"02",X"FF",X"19",X"15",X"0A",X"22",X"0E", + X"1B",X"1C",X"10",X"01",X"51",X"85",X"19",X"15",X"0E",X"0A",X"1C",X"0E",X"FF",X"16",X"18",X"1B", + X"0E",X"FF",X"0C",X"18",X"12",X"17",X"13",X"01",X"4C",X"85",X"0C",X"18",X"12",X"17",X"FF",X"0A", + X"FF",X"FF",X"01",X"0C",X"18",X"12",X"17",X"FF",X"01",X"19",X"15",X"0A",X"22",X"13",X"01",X"4C", + X"85",X"0C",X"18",X"12",X"17",X"FF",X"0A",X"FF",X"02",X"0C",X"18",X"12",X"17",X"1C",X"FF",X"01", + X"19",X"15",X"0A",X"22",X"13",X"01",X"4C",X"85",X"0C",X"18",X"12",X"17",X"FF",X"0A",X"FF",X"03", + X"0C",X"18",X"12",X"17",X"1C",X"FF",X"01",X"19",X"15",X"0A",X"22",X"13",X"01",X"4C",X"85",X"0C", + X"18",X"12",X"17",X"FF",X"0A",X"FF",X"04",X"0C",X"18",X"12",X"17",X"1C",X"FF",X"01",X"19",X"15", + X"0A",X"22",X"13",X"01",X"4C",X"85",X"0C",X"18",X"12",X"17",X"FF",X"0A",X"FF",X"FF",X"01",X"0C", + X"18",X"12",X"17",X"FF",X"02",X"19",X"15",X"0A",X"22",X"13",X"01",X"4C",X"85",X"0C",X"18",X"12", + X"17",X"FF",X"0A",X"FF",X"FF",X"01",X"0C",X"18",X"12",X"17",X"FF",X"03",X"19",X"15",X"0A",X"22", + X"13",X"01",X"4C",X"85",X"0C",X"18",X"12",X"17",X"FF",X"0A",X"FF",X"02",X"0C",X"18",X"12",X"17", + X"1C",X"FF",X"03",X"19",X"15",X"0A",X"22",X"D6",X"3B",X"ED",X"3B",X"04",X"3C",X"1B",X"3C",X"32", + X"3C",X"49",X"3C",X"60",X"3C",X"13",X"01",X"4D",X"85",X"0C",X"18",X"12",X"17",X"FF",X"0B",X"FF", + X"FF",X"01",X"0C",X"18",X"12",X"17",X"FF",X"01",X"19",X"15",X"0A",X"22",X"13",X"01",X"4D",X"85", + X"0C",X"18",X"12",X"17",X"FF",X"0B",X"FF",X"02",X"0C",X"18",X"12",X"17",X"1C",X"FF",X"01",X"19", + X"15",X"0A",X"22",X"13",X"01",X"4D",X"85",X"0C",X"18",X"12",X"17",X"FF",X"0B",X"FF",X"03",X"0C", + X"18",X"12",X"17",X"1C",X"FF",X"01",X"19",X"15",X"0A",X"22",X"13",X"01",X"4D",X"85",X"0C",X"18", + X"12",X"17",X"FF",X"0B",X"FF",X"04",X"0C",X"18",X"12",X"17",X"1C",X"FF",X"01",X"19",X"15",X"0A", + X"22",X"13",X"01",X"4D",X"85",X"0C",X"18",X"12",X"17",X"FF",X"0B",X"FF",X"FF",X"01",X"0C",X"18", + X"12",X"17",X"FF",X"02",X"19",X"15",X"0A",X"22",X"13",X"01",X"4D",X"85",X"0C",X"18",X"12",X"17", + X"FF",X"0B",X"FF",X"FF",X"01",X"0C",X"18",X"12",X"17",X"FF",X"03",X"19",X"15",X"0A",X"22",X"13", + X"01",X"4D",X"85",X"0C",X"18",X"12",X"17",X"FF",X"0B",X"FF",X"02",X"0C",X"18",X"12",X"17",X"1C", + X"FF",X"03",X"19",X"15",X"0A",X"22",X"85",X"3C",X"9C",X"3C",X"B3",X"3C",X"CA",X"3C",X"E1",X"3C", + X"F8",X"3C",X"0F",X"3D",X"09",X"01",X"50",X"85",X"10",X"0A",X"16",X"0E",X"FF",X"18",X"1F",X"0E", + X"1B",X"0A",X"0A",X"0A",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"0C",X"1B",X"0E",X"0D",X"12", + X"1D",X"FF",X"00",X"0B",X"01",X"B5",X"85",X"12",X"17",X"1C",X"0E",X"1B",X"1D",X"FF",X"0C",X"18", + X"12",X"17",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"00",X"34",X"85",X"FF",X"01", + X"1E",X"19",X"FF",X"10",X"0A",X"16",X"0E",X"FF",X"18",X"1F",X"0E",X"1B",X"FF",X"FF",X"10",X"00", + X"34",X"85",X"FF",X"02",X"1E",X"19",X"FF",X"10",X"0A",X"16",X"0E",X"FF",X"18",X"1F",X"0E",X"1B", + X"FF",X"FF",X"09",X"00",X"74",X"85",X"10",X"0A",X"16",X"0E",X"FF",X"18",X"1F",X"0E",X"1B",X"05", + X"00",X"B4",X"85",X"1C",X"1D",X"0A",X"1B",X"1D",X"10",X"00",X"4E",X"85",X"24",X"FF",X"01",X"09", + X"08",X"03",X"FF",X"0F",X"0A",X"15",X"0C",X"18",X"17",X"FF",X"FF",X"FF",X"00",X"00",X"07",X"05", + X"00",X"00",X"0F",X"0A",X"15",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"06",X"08", + X"00",X"00",X"0E",X"15",X"1C",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"05",X"05", + X"00",X"00",X"14",X"FF",X"22",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"03",X"09", + X"00",X"00",X"1D",X"14",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"03",X"08", + X"00",X"00",X"1D",X"1C",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"0E",X"00",X"C9",X"96", + X"0D",X"18",X"FF",X"17",X"18",X"1D",X"FF",X"1B",X"0E",X"20",X"1B",X"12",X"1D",X"0E",X"FF",X"FF", + X"0B",X"00",X"6B",X"96",X"16",X"0E",X"16",X"18",X"1B",X"22",X"FF",X"0D",X"0A",X"1D",X"0A",X"FF", + X"FF",X"FF",X"FF",X"FF",X"03",X"00",X"30",X"96",X"0E",X"15",X"1C",X"0F",X"00",X"07",X"0F",X"01", + X"08",X"0F",X"02",X"09",X"0F",X"03",X"0A",X"0F",X"04",X"0B",X"0F",X"05",X"0C",X"0F",X"06",X"0D", + X"0F",X"07",X"0E",X"0F",X"08",X"0F",X"0F",X"09",X"01",X"0F",X"0A",X"02",X"0F",X"1A",X"00",X"0F", + X"1B",X"00",X"0F",X"1E",X"00",X"03",X"1D",X"00",X"0F",X"0B",X"00",X"0F",X"0C",X"00",X"0F",X"0D", + X"00",X"0F",X"0E",X"00",X"0F",X"0F",X"00",X"0F",X"10",X"03",X"0F",X"11",X"04",X"0F",X"12",X"05", + X"0F",X"13",X"06",X"0F",X"14",X"07",X"0F",X"15",X"03",X"0F",X"16",X"04",X"0F",X"17",X"05",X"0F", + X"18",X"06",X"0F",X"19",X"07",X"3D",X"3D",X"3D",X"3D",X"3D",X"3D",X"3D",X"3D",X"42",X"7A",X"7A", + X"7A",X"7A",X"7A",X"7A",X"3A",X"43",X"7A",X"3A",X"37",X"41",X"3C",X"43",X"39",X"41",X"39",X"40", + X"3F",X"3F",X"3E",X"3D",X"3D",X"38",X"3C",X"7A",X"7A",X"7A",X"7A",X"7A",X"7A",X"3B",X"37",X"7A", + X"7A",X"7A",X"7A",X"3C",X"7A",X"7A",X"7A",X"3B",X"3A",X"37",X"39",X"4F",X"84",X"6F",X"84",X"8F", + X"84",X"AF",X"84",X"CF",X"84",X"EF",X"84",X"0F",X"85",X"2F",X"85",X"4F",X"85",X"50",X"84",X"70", + X"84",X"90",X"84",X"B0",X"84",X"D0",X"84",X"F0",X"84",X"10",X"85",X"30",X"85",X"51",X"84",X"71", + X"84",X"91",X"84",X"B1",X"84",X"D1",X"84",X"F1",X"84",X"11",X"85",X"52",X"84",X"72",X"84",X"EF", + X"86",X"0F",X"87",X"2F",X"87",X"4F",X"87",X"6F",X"87",X"8F",X"87",X"AF",X"87",X"F0",X"86",X"10", + X"87",X"30",X"87",X"50",X"87",X"70",X"87",X"90",X"87",X"B0",X"87",X"11",X"87",X"31",X"87",X"51", + X"87",X"71",X"87",X"91",X"87",X"B1",X"87",X"52",X"87",X"72",X"87",X"92",X"87",X"B2",X"87",X"73", + X"87",X"93",X"87",X"B3",X"87",X"94",X"87",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"30", + X"40",X"20",X"40",X"20",X"30",X"40",X"20",X"30",X"40",X"20",X"40",X"20",X"30",X"20",X"30",X"FE", + X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE",X"10",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE", + X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE", + X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE", + X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE", + X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE", + X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE", + X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE", + X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE", + X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE", + X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE",X"00",X"93",X"10",X"FE", + X"00",X"93",X"10",X"80",X"62",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B", + X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B", + X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B", + X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B", + X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B", + X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B", + X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B", + X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B", + X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B", + X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B",X"10",X"02",X"00",X"8B", + X"10",X"80",X"73",X"98",X"4B",X"78",X"4A",X"DC",X"4A",X"AA",X"4A",X"CA",X"4B",X"3A",X"4B",X"05", + X"40",X"5F",X"3F",X"10",X"58",X"12",X"58",X"14",X"58",X"16",X"58",X"18",X"58",X"1A",X"58",X"1C", + X"58",X"1E",X"58",X"20",X"58",X"22",X"58",X"24",X"58",X"26",X"58",X"28",X"58",X"2A",X"58",X"2C", + X"58",X"2E",X"58",X"30",X"58",X"32",X"58",X"34",X"58",X"36",X"58",X"38",X"58",X"3A",X"58",X"3C", + X"58",X"3E",X"58",X"40",X"58",X"42",X"58",X"44",X"58",X"46",X"58",X"48",X"58",X"4A",X"58",X"4C", + X"58",X"4E",X"58",X"50",X"58",X"52",X"58",X"54",X"58",X"56",X"58",X"58",X"58",X"5A",X"58",X"5C", + X"58",X"5E",X"58",X"60",X"58",X"62",X"58",X"64",X"58",X"66",X"58",X"68",X"58",X"6A",X"58",X"6C", + X"58",X"6E",X"58",X"70",X"58",X"72",X"58",X"74",X"58",X"76",X"58",X"78",X"58",X"7A",X"58",X"7C", + X"58",X"7E",X"58",X"80",X"58",X"82",X"58",X"84",X"58",X"86",X"58",X"88",X"58",X"8A",X"58",X"8C", + X"58",X"8E",X"58",X"90",X"58",X"92",X"58",X"94",X"58",X"96",X"58",X"98",X"58",X"9A",X"58",X"9C", + X"58",X"9E",X"58",X"A0",X"58",X"A2",X"58",X"A4",X"58",X"A6",X"58",X"A8",X"58",X"AA",X"58",X"AC", + X"58",X"AE",X"58",X"B0",X"58",X"B2",X"58",X"B4",X"58",X"B6",X"58",X"B8",X"58",X"BA",X"58",X"BC", + X"58",X"BE",X"58",X"C0",X"58",X"C2",X"58",X"C4",X"58",X"C6",X"58",X"C8",X"58",X"CA",X"58",X"CC", + X"58",X"CE",X"58",X"D0",X"58",X"D2",X"58",X"D4",X"58",X"D6",X"58",X"D8",X"58",X"DA",X"58",X"DC", + X"58",X"DE",X"58",X"E0",X"58",X"E2",X"58",X"E4",X"58",X"E6",X"58",X"E8",X"58",X"EA",X"58",X"EC", + X"58",X"EE",X"58",X"F0",X"58",X"FF",X"FF",X"F5",X"84",X"F4",X"84",X"F3",X"84",X"F5",X"84",X"F4", + X"84",X"F3",X"84",X"15",X"85",X"14",X"85",X"13",X"85",X"35",X"85",X"34",X"85",X"33",X"85",X"1F", + X"20",X"21",X"1F",X"20",X"21",X"1C",X"1D",X"1E",X"19",X"1A",X"1B",X"4B",X"4B",X"4B",X"4B",X"4B", + X"4B",X"4B",X"4B",X"4B",X"4B",X"4B",X"4B",X"55",X"85",X"54",X"85",X"53",X"85",X"55",X"85",X"54", + X"85",X"53",X"85",X"55",X"85",X"54",X"85",X"53",X"85",X"75",X"85",X"74",X"85",X"73",X"85",X"16", + X"17",X"18",X"16",X"17",X"18",X"16",X"17",X"18",X"13",X"14",X"15",X"4B",X"4B",X"4B",X"4B",X"4B", + X"4B",X"4B",X"4B",X"4B",X"4B",X"4B",X"4B",X"95",X"85",X"94",X"85",X"93",X"85",X"95",X"85",X"94", + X"85",X"93",X"85",X"B5",X"85",X"B4",X"85",X"B3",X"85",X"D5",X"85",X"D4",X"85",X"D3",X"85",X"10", + X"11",X"12",X"10",X"11",X"12",X"0D",X"0E",X"0F",X"0A",X"0B",X"0C",X"4B",X"4B",X"4B",X"4B",X"4B", + X"4B",X"4B",X"4B",X"4B",X"4B",X"4B",X"4B",X"F5",X"85",X"F4",X"85",X"F3",X"85",X"F5",X"85",X"F4", + X"85",X"F3",X"85",X"F5",X"85",X"F4",X"85",X"F3",X"85",X"15",X"86",X"14",X"86",X"13",X"86",X"07", + X"08",X"09",X"07",X"08",X"09",X"07",X"08",X"09",X"04",X"05",X"06",X"4B",X"4B",X"4B",X"4B",X"4B", + X"4B",X"4B",X"4B",X"4B",X"4B",X"4B",X"4B",X"75",X"86",X"74",X"86",X"73",X"86",X"75",X"86",X"74", + X"86",X"73",X"86",X"95",X"86",X"94",X"86",X"93",X"86",X"B5",X"86",X"B4",X"86",X"B3",X"86",X"FA", + X"FB",X"FC",X"FA",X"FB",X"FC",X"F7",X"F8",X"F9",X"F4",X"F5",X"F6",X"0B",X"0B",X"0B",X"0B",X"0B", + X"0B",X"0B",X"0B",X"0B",X"0B",X"0B",X"0B",X"D5",X"86",X"D4",X"86",X"D3",X"86",X"F5",X"86",X"F4", + X"86",X"F3",X"86",X"15",X"87",X"14",X"87",X"13",X"87",X"35",X"87",X"34",X"87",X"33",X"87",X"F1", + X"F2",X"F3",X"EE",X"EF",X"F0",X"EB",X"EC",X"ED",X"E8",X"E9",X"EA",X"0B",X"0B",X"0B",X"0B",X"0B", + X"0B",X"0B",X"0B",X"0B",X"0B",X"0B",X"0B",X"35",X"86",X"34",X"86",X"33",X"86",X"35",X"86",X"34", + X"86",X"33",X"86",X"35",X"86",X"34",X"86",X"33",X"86",X"55",X"86",X"54",X"86",X"53",X"86",X"01", + X"02",X"03",X"01",X"02",X"03",X"01",X"02",X"03",X"FD",X"FE",X"00",X"4B",X"4B",X"4B",X"4B",X"4B", + X"4B",X"4B",X"4B",X"4B",X"0B",X"0B",X"4B",X"08",X"00",X"00",X"0A",X"00",X"01",X"0C",X"00",X"02", + X"0E",X"00",X"03",X"10",X"00",X"04",X"12",X"00",X"05",X"14",X"00",X"06",X"97",X"41",X"C7",X"41", + X"F7",X"41",X"27",X"42",X"B7",X"42",X"57",X"42",X"87",X"42",X"24",X"FF",X"01",X"09",X"08",X"03", + X"FF",X"2A",X"29",X"28",X"27",X"26",X"25",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02", + X"02",X"02",X"02",X"02",X"10",X"30",X"12",X"30",X"14",X"30",X"16",X"30",X"18",X"30",X"1A",X"30", + X"1C",X"30",X"1E",X"30",X"20",X"30",X"22",X"30",X"24",X"30",X"26",X"30",X"28",X"30",X"2A",X"30", + X"2C",X"30",X"2E",X"30",X"30",X"30",X"32",X"30",X"34",X"30",X"36",X"30",X"38",X"30",X"3A",X"30", + X"3C",X"30",X"3E",X"30",X"40",X"30",X"42",X"30",X"44",X"30",X"46",X"30",X"48",X"30",X"4A",X"30", + X"4C",X"30",X"4E",X"30",X"50",X"30",X"52",X"30",X"54",X"30",X"56",X"30",X"58",X"30",X"5A",X"30", + X"5C",X"30",X"5E",X"30",X"60",X"30",X"62",X"30",X"64",X"30",X"66",X"30",X"68",X"30",X"6A",X"30", + X"6C",X"30",X"6E",X"30",X"70",X"30",X"72",X"30",X"74",X"30",X"76",X"30",X"78",X"30",X"7A",X"30", + X"7C",X"30",X"7E",X"30",X"80",X"30",X"82",X"30",X"84",X"30",X"86",X"30",X"88",X"30",X"8A",X"30", + X"8C",X"30",X"8E",X"30",X"90",X"30",X"92",X"30",X"94",X"30",X"96",X"30",X"98",X"30",X"9A",X"30", + X"9C",X"30",X"9E",X"30",X"A0",X"30",X"A2",X"30",X"A4",X"30",X"A6",X"30",X"A8",X"30",X"AA",X"30", + X"AC",X"30",X"AE",X"30",X"B0",X"30",X"B2",X"30",X"B4",X"30",X"B6",X"30",X"B8",X"30",X"BA",X"30", + X"BC",X"30",X"BE",X"30",X"C0",X"30",X"C2",X"30",X"C4",X"30",X"C6",X"30",X"C8",X"30",X"CA",X"30", + X"CC",X"30",X"CE",X"30",X"D0",X"30",X"D2",X"30",X"D4",X"30",X"D6",X"30",X"D8",X"30",X"DA",X"30", + X"DC",X"30",X"DE",X"30",X"E0",X"30",X"E2",X"30",X"E4",X"30",X"E6",X"30",X"E8",X"30",X"EA",X"30", + X"EC",X"30",X"EE",X"30",X"F0",X"30",X"F8",X"30",X"FF",X"FF",X"FF",X"FF",X"01",X"01",X"34",X"31", + X"2E",X"2B",X"7F",X"35",X"32",X"2F",X"2C",X"7F",X"34",X"31",X"2E",X"2B",X"7F",X"35",X"32",X"2F", + X"2C",X"7F",X"34",X"31",X"2E",X"2B",X"7F",X"35",X"32",X"2F",X"2C",X"7F",X"34",X"31",X"2E",X"2B", + X"7F",X"35",X"32",X"2F",X"2C",X"7F",X"01",X"01",X"36",X"33",X"30",X"2D",X"7F",X"7F",X"7F",X"7F", + X"7F",X"7F",X"36",X"33",X"30",X"2D",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"36",X"33",X"30",X"2D", + X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"36",X"33",X"30",X"2D",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F", + X"A0",X"E0",X"A0",X"D8",X"A0",X"D0",X"A0",X"C8",X"A0",X"C0",X"A0",X"B8",X"A0",X"B0",X"A0",X"A8", + X"A0",X"A0",X"A0",X"98",X"A0",X"90",X"A0",X"88",X"A0",X"80",X"A0",X"80",X"A0",X"80",X"A0",X"80", + X"A0",X"80",X"A0",X"80",X"A0",X"80",X"A0",X"80",X"A0",X"80",X"A0",X"80",X"A0",X"80",X"A0",X"80", + X"A0",X"80",X"A0",X"80",X"A0",X"80",X"A0",X"80",X"A0",X"80",X"A0",X"80",X"A0",X"80",X"A0",X"80", + X"A0",X"80",X"A0",X"80",X"A0",X"80",X"A0",X"80",X"A0",X"80",X"A0",X"80",X"A0",X"80",X"A0",X"80", + X"05",X"00",X"91",X"85",X"0B",X"18",X"17",X"1E",X"1C",X"06",X"00",X"6B",X"85",X"05",X"00",X"00", + X"FF",X"4C",X"FF",X"00",X"00",X"00",X"05",X"00",X"10",X"00",X"15",X"00",X"20",X"00",X"25",X"00", + X"30",X"00",X"35",X"00",X"40",X"00",X"45",X"00",X"50",X"10",X"10",X"20",X"01",X"02",X"02",X"02", + X"00",X"10",X"01",X"01",X"01",X"02",X"02",X"10",X"20",X"00",X"00",X"20",X"20",X"10",X"10",X"10", + X"01",X"01",X"01",X"02",X"02",X"02",X"10",X"10",X"10",X"20",X"20",X"01",X"01",X"20",X"10",X"20", + X"20",X"10",X"01",X"01",X"02",X"02",X"02",X"10",X"10",X"10",X"10",X"10",X"01",X"01",X"02",X"02", + X"00",X"23",X"45",X"2B",X"45",X"33",X"45",X"3B",X"45",X"43",X"45",X"4B",X"45",X"53",X"45",X"5B", + X"45",X"63",X"45",X"04",X"01",X"51",X"86",X"00",X"00",X"00",X"00",X"04",X"01",X"51",X"86",X"FF", + X"05",X"00",X"00",X"04",X"01",X"51",X"86",X"01",X"00",X"00",X"00",X"04",X"01",X"51",X"86",X"01", + X"05",X"00",X"00",X"04",X"01",X"51",X"86",X"02",X"00",X"00",X"00",X"04",X"01",X"51",X"86",X"02", + X"05",X"00",X"00",X"04",X"01",X"51",X"86",X"03",X"00",X"00",X"00",X"04",X"01",X"51",X"86",X"03", + X"05",X"00",X"00",X"04",X"01",X"51",X"86",X"04",X"00",X"00",X"00",X"13",X"02",X"0F",X"85",X"4D", + X"4D",X"4D",X"FF",X"05",X"00",X"FF",X"18",X"1B",X"FF",X"02",X"00",X"00",X"FF",X"19",X"18",X"12", + X"17",X"1D",X"0D",X"02",X"0C",X"85",X"4D",X"4D",X"4D",X"FF",X"02",X"00",X"00",X"FF",X"19",X"18", + X"12",X"17",X"1D",X"0D",X"02",X"09",X"85",X"4D",X"4D",X"4D",X"FF",X"03",X"00",X"00",X"FF",X"19", + X"18",X"12",X"17",X"1D",X"0D",X"02",X"06",X"85",X"4D",X"4D",X"4D",X"FF",X"05",X"00",X"00",X"FF", + X"19",X"18",X"12",X"17",X"1D",X"30",X"32",X"34",X"36",X"38",X"3A",X"3C",X"3E",X"40",X"42",X"44", + X"46",X"48",X"4A",X"4C",X"4E",X"50",X"52",X"54",X"56",X"58",X"5A",X"5C",X"5E",X"0C",X"03",X"54", + X"85",X"0D",X"18",X"17",X"1D",X"FF",X"1B",X"0E",X"20",X"1B",X"12",X"1D",X"0E",X"03",X"03",X"0D", + X"86",X"0E",X"15",X"1C",X"07",X"08",X"09",X"09",X"0A",X"08",X"0A",X"0B",X"09",X"0A",X"11",X"13", + X"06",X"07",X"07",X"07",X"06",X"04",X"08",X"08",X"03",X"05",X"04",X"04",X"FE",X"01",X"FE",X"00", + X"FE",X"01",X"FE",X"00",X"FE",X"01",X"FE",X"01",X"FE",X"01",X"FF",X"02",X"00",X"02",X"01",X"02", + X"02",X"01",X"02",X"01",X"02",X"01",X"02",X"00",X"02",X"01",X"02",X"00",X"02",X"01",X"02",X"01", + X"01",X"00",X"00",X"00",X"80",X"9C",X"10",X"F0",X"B4",X"4E",X"62",X"B4",X"9E",X"B2",X"CC",X"20", + X"32",X"CC",X"76",X"8B",X"CC",X"CE",X"E0",X"01",X"FD",X"03",X"FF",X"02",X"03",X"01",X"FD",X"03", + X"FF",X"02",X"03",X"01",X"FD",X"03",X"FF",X"02",X"03",X"01",X"FD",X"03",X"FF",X"01",X"03",X"03", + X"01",X"02",X"FD",X"01",X"03",X"03",X"01",X"02",X"FD",X"01",X"03",X"03",X"01",X"02",X"FD",X"01", + X"03",X"03",X"01",X"02",X"FF",X"A7",X"13",X"02",X"00",X"A7",X"13",X"02",X"01",X"A7",X"13",X"02", + X"01",X"A7",X"13",X"02",X"00",X"A7",X"13",X"02",X"FF",X"A7",X"13",X"80",X"02",X"FE",X"A7",X"13", + X"02",X"00",X"A7",X"13",X"80",X"02",X"02",X"A7",X"13",X"02",X"00",X"A7",X"13",X"80",X"02",X"00", + X"AF",X"13",X"02",X"00",X"AF",X"13",X"02",X"00",X"B3",X"13",X"02",X"00",X"B3",X"13",X"02",X"00", + X"AF",X"13",X"02",X"00",X"AF",X"13",X"02",X"00",X"AB",X"13",X"02",X"00",X"AB",X"13",X"80",X"02", + X"FE",X"B3",X"13",X"02",X"FE",X"B3",X"13",X"02",X"FF",X"B3",X"13",X"02",X"FF",X"AF",X"13",X"02", + X"FF",X"B3",X"13",X"02",X"FE",X"B3",X"13",X"02",X"FE",X"B3",X"13",X"80",X"02",X"02",X"AB",X"13", + X"02",X"02",X"AB",X"13",X"02",X"01",X"AB",X"13",X"02",X"01",X"AF",X"13",X"02",X"01",X"AB",X"13", + X"02",X"02",X"AB",X"13",X"02",X"02",X"AB",X"13",X"80",X"18",X"30",X"50",X"60",X"80",X"A0",X"B0", + X"D0",X"E9",X"FF",X"FD",X"00",X"FD",X"FF",X"FE",X"FE",X"FE",X"FD",X"FD",X"FE",X"FE",X"FD",X"FF", + X"FD",X"00",X"FD",X"01",X"FD",X"01",X"FD",X"02",X"FD",X"02",X"FD",X"03",X"FE",X"02",X"FE",X"03", + X"FE",X"03",X"FF",X"03",X"FF",X"03",X"FF",X"03",X"00",X"80",X"FE",X"00",X"FE",X"FF",X"FD",X"FF", + X"FD",X"FF",X"FD",X"FE",X"FD",X"FE",X"00",X"FE",X"03",X"FE",X"03",X"FE",X"03",X"FF",X"03",X"FF", + X"80",X"FD",X"00",X"FD",X"01",X"FE",X"02",X"FE",X"03",X"FD",X"02",X"FE",X"03",X"FF",X"03",X"00", + X"03",X"01",X"03",X"01",X"03",X"02",X"03",X"02",X"03",X"03",X"02",X"02",X"02",X"03",X"02",X"03", + X"01",X"03",X"01",X"03",X"01",X"03",X"00",X"80",X"FE",X"00",X"FE",X"01",X"FD",X"01",X"FD",X"01", + X"FD",X"02",X"FD",X"02",X"00",X"02",X"03",X"02",X"03",X"02",X"03",X"01",X"03",X"01",X"80",X"A2", + X"F0",X"E8",X"A2",X"B2",X"9E",X"A2",X"62",X"4E",X"BA",X"34",X"2C",X"BA",X"84",X"7C",X"BA",X"D2", + X"CE",X"D2",X"A8",X"A4",X"D2",X"48",X"44",X"A2",X"E7",X"B9",X"A2",X"97",X"69",X"A2",X"47",X"19", + X"BA",X"60",X"41",X"BA",X"B0",X"91",X"BA",X"E0",X"D0",X"D2",X"97",X"78",X"D2",X"3F",X"20",X"A4", + X"A4",X"A4",X"BC",X"BC",X"D4",X"D4",X"D4",X"9C",X"C0",X"37",X"12",X"9C",X"70",X"37",X"12",X"9C", + X"42",X"2F",X"12",X"B4",X"6A",X"2F",X"12",X"B4",X"98",X"37",X"12",X"CC",X"C8",X"37",X"12",X"CC", + X"92",X"2F",X"12",X"CC",X"3A",X"2F",X"12",X"00",X"FE",X"4B",X"12",X"00",X"FE",X"4B",X"12",X"00", + X"FE",X"4F",X"12",X"00",X"FE",X"4F",X"12",X"00",X"FE",X"53",X"12",X"00",X"FE",X"53",X"12",X"00", + X"FE",X"4F",X"12",X"00",X"FE",X"4F",X"12",X"80",X"00",X"02",X"3F",X"12",X"00",X"02",X"3F",X"12", + X"00",X"02",X"43",X"12",X"00",X"02",X"43",X"12",X"00",X"02",X"47",X"12",X"00",X"02",X"47",X"12", + X"00",X"02",X"43",X"12",X"00",X"02",X"43",X"12",X"80",X"03",X"00",X"83",X"12",X"03",X"00",X"83", + X"12",X"03",X"00",X"83",X"12",X"03",X"00",X"83",X"12",X"03",X"00",X"3F",X"12",X"02",X"02",X"3F", + X"12",X"02",X"02",X"43",X"12",X"02",X"02",X"43",X"12",X"02",X"02",X"47",X"12",X"01",X"02",X"47", + X"12",X"00",X"02",X"43",X"12",X"00",X"02",X"43",X"12",X"00",X"02",X"3F",X"12",X"00",X"02",X"3F", + X"12",X"00",X"02",X"43",X"12",X"00",X"02",X"43",X"12",X"00",X"02",X"47",X"12",X"00",X"02",X"47", + X"12",X"00",X"02",X"43",X"12",X"00",X"02",X"43",X"12",X"00",X"02",X"3F",X"12",X"00",X"02",X"3F", + X"12",X"00",X"02",X"43",X"12",X"00",X"02",X"43",X"12",X"00",X"02",X"47",X"12",X"00",X"02",X"47", + X"12",X"00",X"02",X"43",X"12",X"00",X"02",X"43",X"12",X"00",X"02",X"3F",X"12",X"00",X"02",X"3F", + X"12",X"00",X"02",X"43",X"12",X"00",X"02",X"43",X"12",X"00",X"02",X"47",X"12",X"00",X"02",X"47", + X"12",X"00",X"00",X"87",X"12",X"00",X"00",X"87",X"12",X"80",X"FD",X"01",X"57",X"12",X"FD",X"01", + X"57",X"12",X"FD",X"01",X"57",X"12",X"FD",X"01",X"57",X"12",X"FE",X"02",X"57",X"12",X"FD",X"02", + X"57",X"12",X"FE",X"03",X"57",X"12",X"FF",X"03",X"57",X"12",X"00",X"03",X"57",X"12",X"01",X"03", + X"57",X"12",X"02",X"03",X"57",X"12",X"01",X"01",X"83",X"12",X"00",X"00",X"87",X"12",X"00",X"00", + X"87",X"12",X"00",X"00",X"83",X"12",X"00",X"00",X"83",X"12",X"00",X"00",X"87",X"12",X"00",X"00", + X"87",X"12",X"80",X"FD",X"FF",X"5B",X"12",X"FD",X"FF",X"5B",X"12",X"FD",X"FF",X"5B",X"12",X"FD", + X"FF",X"5B",X"12",X"FE",X"FE",X"5B",X"12",X"FD",X"FE",X"5B",X"12",X"FE",X"FD",X"5B",X"12",X"FF", + X"FD",X"5B",X"12",X"00",X"FD",X"5B",X"12",X"01",X"FD",X"5B",X"12",X"02",X"FD",X"5B",X"12",X"01", + X"FF",X"83",X"12",X"00",X"00",X"87",X"12",X"00",X"00",X"87",X"12",X"00",X"00",X"83",X"12",X"00", + X"00",X"83",X"12",X"00",X"00",X"87",X"12",X"00",X"00",X"87",X"12",X"80",X"00",X"02",X"57",X"12", + X"01",X"03",X"57",X"12",X"03",X"02",X"57",X"12",X"03",X"01",X"57",X"12",X"01",X"00",X"83",X"12", + X"00",X"00",X"87",X"12",X"00",X"00",X"87",X"12",X"00",X"00",X"87",X"12",X"00",X"00",X"83",X"12", + X"00",X"00",X"83",X"12",X"00",X"00",X"87",X"12",X"00",X"00",X"87",X"12",X"80",X"00",X"02",X"57", + X"12",X"01",X"03",X"57",X"12",X"03",X"02",X"57",X"12",X"03",X"02",X"57",X"12",X"00",X"00",X"87", + X"12",X"80",X"00",X"00",X"6F",X"12",X"00",X"00",X"6F",X"12",X"00",X"06",X"73",X"12",X"00",X"00", + X"73",X"12",X"00",X"00",X"73",X"12",X"80",X"00",X"00",X"7B",X"12",X"00",X"00",X"7B",X"12",X"00", + X"FA",X"7F",X"12",X"00",X"00",X"7F",X"12",X"00",X"00",X"7F",X"12",X"80",X"00",X"00",X"77",X"12", + X"00",X"00",X"7B",X"12",X"00",X"FA",X"7F",X"12",X"00",X"00",X"7F",X"12",X"80",X"00",X"00",X"6B", + X"12",X"00",X"00",X"6F",X"12",X"00",X"06",X"73",X"12",X"00",X"00",X"73",X"12",X"80",X"03",X"FF", + X"4B",X"12",X"03",X"FF",X"4B",X"12",X"03",X"FF",X"4F",X"12",X"03",X"FF",X"4F",X"12",X"03",X"FF", + X"53",X"12",X"03",X"FF",X"53",X"12",X"03",X"FF",X"4F",X"12",X"03",X"FF",X"4F",X"12",X"01",X"FF", + X"4B",X"12",X"03",X"01",X"3F",X"12",X"03",X"01",X"3F",X"12",X"03",X"01",X"43",X"12",X"03",X"01", + X"43",X"12",X"03",X"01",X"47",X"12",X"03",X"01",X"47",X"12",X"03",X"01",X"43",X"12",X"03",X"01", + X"43",X"12",X"01",X"01",X"3F",X"12",X"FD",X"FF",X"5B",X"12",X"FD",X"FF",X"5B",X"12",X"FD",X"FE", + X"5B",X"12",X"FD",X"FE",X"5B",X"12",X"FD",X"FE",X"5B",X"12",X"FE",X"FD",X"5B",X"12",X"FE",X"FD", + X"5B",X"12",X"FF",X"FD",X"5B",X"12",X"00",X"FD",X"5B",X"12",X"01",X"FD",X"5B",X"12",X"01",X"FD", + X"5B",X"12",X"02",X"FE",X"5B",X"12",X"80",X"FD",X"01",X"57",X"12",X"FD",X"01",X"57",X"12",X"FD", + X"02",X"57",X"12",X"FD",X"02",X"57",X"12",X"FD",X"02",X"57",X"12",X"FE",X"03",X"57",X"12",X"FE", + X"03",X"57",X"12",X"FE",X"03",X"57",X"12",X"00",X"03",X"57",X"12",X"01",X"03",X"57",X"12",X"01", + X"03",X"57",X"12",X"02",X"02",X"57",X"12",X"80",X"A0",X"B8",X"A0",X"68",X"A0",X"18",X"B8",X"70", + X"B8",X"C0",X"D0",X"C0",X"D0",X"68",X"D0",X"40",X"03",X"10",X"8B",X"10",X"03",X"01",X"8B",X"10", + X"03",X"01",X"8B",X"10",X"03",X"01",X"9F",X"10",X"03",X"02",X"9F",X"10",X"03",X"03",X"9F",X"10", + X"02",X"03",X"9F",X"10",X"02",X"03",X"9F",X"10",X"01",X"03",X"8F",X"10",X"00",X"03",X"8F",X"10", + X"01",X"02",X"8F",X"10",X"00",X"03",X"8F",X"10",X"80",X"22",X"FD",X"00",X"93",X"10",X"FD",X"01", + X"93",X"10",X"FD",X"01",X"93",X"10",X"FD",X"01",X"A3",X"10",X"FD",X"02",X"A3",X"10",X"FE",X"03", + X"A3",X"10",X"FE",X"03",X"A3",X"10",X"FE",X"03",X"A3",X"10",X"FF",X"03",X"8F",X"10",X"00",X"03", + X"8F",X"10",X"FF",X"02",X"8F",X"10",X"00",X"02",X"8F",X"10",X"80",X"55",X"00",X"03",X"8F",X"10", + X"FF",X"03",X"8F",X"10",X"FF",X"03",X"8F",X"10",X"FF",X"03",X"A3",X"10",X"FE",X"03",X"A3",X"10", + X"FE",X"02",X"A3",X"10",X"FD",X"02",X"A3",X"10",X"FD",X"02",X"A3",X"10",X"FD",X"02",X"93",X"10", + X"FD",X"00",X"93",X"10",X"FD",X"01",X"93",X"10",X"FD",X"00",X"93",X"10",X"FD",X"00",X"93",X"10", + X"FD",X"FF",X"93",X"10",X"FD",X"FF",X"9B",X"10",X"FD",X"FE",X"9B",X"10",X"FD",X"FE",X"9B",X"10", + X"FE",X"FD",X"9B",X"10",X"FE",X"FD",X"9B",X"10",X"FE",X"FD",X"8D",X"10",X"FF",X"FD",X"8D",X"10", + X"FF",X"FD",X"8D",X"10",X"00",X"FD",X"8D",X"10",X"80",X"00",X"00",X"03",X"8F",X"10",X"01",X"03", + X"8F",X"10",X"01",X"03",X"8F",X"10",X"01",X"03",X"9F",X"10",X"02",X"03",X"9F",X"10",X"02",X"02", + X"9F",X"10",X"03",X"02",X"9F",X"10",X"03",X"02",X"9F",X"10",X"03",X"02",X"8B",X"10",X"03",X"00", + X"8B",X"10",X"03",X"01",X"8B",X"10",X"03",X"00",X"8B",X"10",X"03",X"00",X"8B",X"10",X"03",X"FF", + X"8B",X"10",X"03",X"FF",X"97",X"10",X"03",X"FE",X"97",X"10",X"03",X"FE",X"97",X"10",X"02",X"FD", + X"97",X"10",X"02",X"FD",X"97",X"10",X"02",X"FD",X"8D",X"10",X"01",X"FD",X"8D",X"10",X"01",X"FD", + X"8D",X"10",X"00",X"FD",X"8D",X"10",X"80",X"44",X"00",X"FD",X"8D",X"10",X"01",X"FD",X"8D",X"10", + X"01",X"FD",X"8D",X"10",X"01",X"FD",X"97",X"10",X"02",X"FD",X"97",X"10",X"02",X"FE",X"97",X"10", + X"02",X"FE",X"97",X"10",X"03",X"FE",X"97",X"10",X"03",X"FF",X"8B",X"10",X"03",X"FF",X"8B",X"10", + X"03",X"FF",X"8B",X"10",X"03",X"00",X"8B",X"10",X"80",X"61",X"00",X"FD",X"8D",X"10",X"FF",X"FD", + X"8D",X"10",X"FF",X"FD",X"8D",X"10",X"FF",X"FD",X"9B",X"10",X"FE",X"FD",X"9B",X"10",X"FE",X"FE", + X"9B",X"10",X"FE",X"FE",X"9B",X"10",X"FD",X"FE",X"9B",X"10",X"FD",X"FF",X"93",X"10",X"FD",X"FF", + X"93",X"10",X"FD",X"FF",X"93",X"10",X"FD",X"00",X"93",X"10",X"80",X"73",X"00",X"88",X"01",X"80", + X"00",X"80",X"01",X"88",X"02",X"88",X"03",X"80",X"02",X"80",X"03",X"88",X"14",X"88",X"15",X"80", + X"14",X"80",X"15",X"88",X"16",X"88",X"17",X"80",X"16",X"80",X"17",X"88",X"18",X"88",X"19",X"80", + X"18",X"80",X"19",X"88",X"1A",X"88",X"1B",X"80",X"1A",X"80",X"1B",X"88",X"1C",X"88",X"1D",X"80", + X"1C",X"80",X"1D",X"88",X"1E",X"88",X"1F",X"80",X"1E",X"80",X"1F",X"88",X"20",X"88",X"20",X"80", + X"00",X"A0",X"62",X"9A",X"21",X"88",X"21",X"80",X"01",X"A0",X"62",X"9A",X"22",X"88",X"22",X"80", + X"02",X"A0",X"62",X"9A",X"23",X"88",X"23",X"80",X"03",X"A0",X"62",X"9A",X"34",X"88",X"34",X"80", + X"04",X"A0",X"62",X"9A",X"35",X"88",X"35",X"80",X"05",X"A0",X"62",X"9A",X"36",X"88",X"36",X"80", + X"06",X"A0",X"62",X"9A",X"37",X"88",X"37",X"80",X"07",X"A0",X"62",X"9A",X"38",X"88",X"38",X"80", + X"08",X"A0",X"62",X"9A",X"39",X"88",X"39",X"80",X"09",X"A0",X"62",X"9A",X"3A",X"88",X"3A",X"80", + X"0A",X"A0",X"62",X"9A",X"3B",X"88",X"3B",X"80",X"0B",X"A0",X"62",X"9A",X"3C",X"88",X"3C",X"80", + X"0C",X"A0",X"62",X"9A",X"3D",X"88",X"3D",X"80",X"0D",X"A0",X"62",X"9A",X"3E",X"88",X"3E",X"80", + X"0E",X"A0",X"62",X"9A",X"3F",X"88",X"3F",X"80",X"0F",X"A0",X"62",X"9A",X"7F",X"7F",X"7F",X"7F", + X"47",X"46",X"45",X"44",X"79",X"78",X"77",X"76",X"00",X"00",X"00",X"00",X"05",X"05",X"05",X"05", + X"05",X"05",X"05",X"05",X"10",X"10",X"10",X"10",X"15",X"15",X"15",X"15",X"05",X"05",X"05",X"05", + X"7A",X"7A",X"7A",X"7A",X"4A",X"46",X"45",X"49",X"79",X"78",X"77",X"76",X"00",X"00",X"00",X"00", + X"05",X"05",X"05",X"05",X"05",X"05",X"05",X"05",X"00",X"00",X"00",X"00",X"05",X"05",X"05",X"05", + X"05",X"05",X"05",X"05",X"7F",X"7F",X"48",X"7F",X"47",X"46",X"45",X"44",X"7A",X"7A",X"7A",X"7A", + X"00",X"00",X"01",X"00",X"05",X"05",X"05",X"05",X"05",X"05",X"05",X"05",X"10",X"10",X"11",X"10", + X"15",X"05",X"05",X"15",X"05",X"05",X"05",X"05",X"7A",X"7A",X"4B",X"7A",X"4A",X"46",X"45",X"49", + X"7A",X"7A",X"7A",X"7A",X"00",X"00",X"07",X"00",X"05",X"05",X"05",X"05",X"05",X"05",X"05",X"05", + X"00",X"00",X"07",X"00",X"05",X"05",X"05",X"05",X"05",X"05",X"05",X"05",X"7F",X"51",X"4F",X"7F", + X"53",X"52",X"50",X"4E",X"79",X"78",X"77",X"76",X"00",X"06",X"06",X"00",X"06",X"06",X"06",X"06", + X"04",X"04",X"04",X"04",X"10",X"16",X"16",X"10",X"16",X"16",X"16",X"16",X"04",X"04",X"04",X"04", + X"7A",X"5B",X"59",X"7A",X"5D",X"5C",X"5A",X"58",X"79",X"78",X"77",X"76",X"00",X"06",X"06",X"00", + X"06",X"06",X"06",X"06",X"04",X"04",X"04",X"04",X"00",X"06",X"06",X"00",X"06",X"06",X"06",X"06", + X"04",X"04",X"04",X"04",X"7F",X"7F",X"7F",X"7F",X"57",X"56",X"55",X"54",X"7A",X"7A",X"7A",X"7A", + X"00",X"00",X"00",X"00",X"06",X"06",X"06",X"06",X"04",X"04",X"04",X"04",X"10",X"10",X"10",X"10", + X"16",X"16",X"16",X"16",X"04",X"04",X"04",X"04",X"7A",X"7A",X"7A",X"7A",X"61",X"60",X"5F",X"5E", + X"7A",X"7A",X"7A",X"7A",X"00",X"00",X"00",X"00",X"06",X"06",X"06",X"06",X"04",X"04",X"04",X"04", + X"00",X"00",X"00",X"00",X"06",X"06",X"06",X"06",X"04",X"04",X"04",X"04",X"7F",X"65",X"63",X"7F", + X"67",X"66",X"64",X"62",X"79",X"78",X"77",X"76",X"00",X"08",X"08",X"00",X"08",X"08",X"08",X"08", + X"01",X"01",X"01",X"01",X"10",X"18",X"18",X"10",X"18",X"18",X"18",X"18",X"01",X"01",X"01",X"01", + X"7A",X"6F",X"6D",X"7A",X"71",X"70",X"6E",X"6C",X"79",X"78",X"77",X"76",X"00",X"08",X"08",X"00", + X"08",X"08",X"08",X"08",X"01",X"01",X"01",X"01",X"00",X"08",X"08",X"00",X"08",X"08",X"08",X"08", + X"01",X"01",X"01",X"01",X"7F",X"7F",X"7F",X"7F",X"6B",X"6A",X"69",X"68",X"7A",X"7A",X"7A",X"7A", + X"00",X"00",X"00",X"00",X"08",X"08",X"08",X"08",X"01",X"01",X"01",X"01",X"10",X"10",X"10",X"10", + X"18",X"18",X"18",X"18",X"01",X"01",X"01",X"01",X"7A",X"7A",X"7A",X"7A",X"75",X"74",X"73",X"72", + X"7A",X"7A",X"7A",X"7A",X"00",X"00",X"00",X"00",X"08",X"08",X"08",X"08",X"01",X"01",X"01",X"01", + X"10",X"10",X"10",X"10",X"08",X"08",X"08",X"08",X"01",X"01",X"01",X"01",X"7F",X"D4",X"D2",X"7F", + X"7F",X"D5",X"D3",X"7F",X"7A",X"7A",X"7A",X"7A",X"00",X"09",X"09",X"00",X"00",X"09",X"09",X"00", + X"01",X"01",X"01",X"01",X"10",X"19",X"19",X"10",X"10",X"19",X"19",X"10",X"01",X"01",X"01",X"01", + X"7A",X"D4",X"D2",X"7A",X"7A",X"D5",X"D3",X"7A",X"7A",X"7A",X"7A",X"7A",X"00",X"09",X"09",X"00", + X"00",X"09",X"09",X"00",X"01",X"01",X"01",X"01",X"00",X"09",X"09",X"00",X"00",X"09",X"09",X"00", + X"01",X"01",X"01",X"01",X"DC",X"DA",X"D8",X"D6",X"DD",X"DB",X"D9",X"D7",X"7A",X"7A",X"7A",X"7A", + X"09",X"09",X"09",X"09",X"09",X"09",X"09",X"09",X"04",X"04",X"04",X"04",X"19",X"19",X"19",X"19", + X"19",X"19",X"19",X"19",X"04",X"04",X"04",X"04",X"DC",X"DA",X"D8",X"D6",X"DD",X"DB",X"D9",X"D7", + X"7A",X"7A",X"7A",X"7A",X"09",X"09",X"09",X"09",X"09",X"09",X"09",X"09",X"04",X"04",X"04",X"04", + X"09",X"09",X"09",X"09",X"09",X"09",X"09",X"09",X"04",X"04",X"04",X"04",X"0D",X"87",X"CD",X"85", + X"8D",X"84",X"2A",X"85",X"6A",X"86",X"27",X"87",X"C7",X"85",X"67",X"84",X"0F",X"FC",X"FC",X"00", + X"0E",X"FC",X"00",X"00",X"0E",X"00",X"FC",X"00",X"0F",X"00",X"00",X"00",X"02",X"12",X"BC",X"BA", + X"B8",X"B6",X"B4",X"BD",X"BB",X"B9",X"B7",X"B5",X"C6",X"C4",X"C2",X"C0",X"BE",X"C7",X"C5",X"C3", + X"C1",X"BF",X"D0",X"CE",X"CC",X"CA",X"C8",X"D1",X"CF",X"CD",X"CB",X"C9",X"7F",X"B2",X"B0",X"AE", + X"AC",X"7F",X"B3",X"B1",X"AF",X"AD",X"00",X"10",X"88",X"86",X"84",X"89",X"87",X"85",X"8E",X"8C", + X"8A",X"8F",X"8D",X"8B",X"94",X"92",X"90",X"95",X"93",X"91",X"7F",X"82",X"80",X"7F",X"83",X"81", + X"01",X"11",X"9E",X"9C",X"9A",X"9F",X"9D",X"9B",X"A4",X"A2",X"A0",X"A5",X"A3",X"A1",X"AA",X"A8", + X"A6",X"AB",X"A9",X"A7",X"7F",X"98",X"96",X"7F",X"99",X"97",X"09",X"19",X"E6",X"E4",X"E2",X"E0", + X"DE",X"E7",X"E5",X"E3",X"E1",X"DF",X"E6",X"E4",X"E2",X"E0",X"DE",X"E7",X"E5",X"E3",X"E1",X"DF", + X"7F",X"DC",X"DA",X"D8",X"D6",X"7F",X"DD",X"DB",X"D9",X"D7",X"7F",X"DC",X"DA",X"D8",X"D6",X"7F", + X"DD",X"DB",X"D9",X"D7",X"05",X"15",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F", + X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F", + X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"7F",X"50",X"99", + X"70",X"99",X"90",X"99",X"B0",X"99",X"D0",X"99",X"21",X"8A",X"48",X"C3",X"6D",X"2F",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/cmd_snd_rom.vhd b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/cmd_snd_rom.vhd new file mode 100644 index 00000000..75a9efbe --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/cmd_snd_rom.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity cmd_snd_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of cmd_snd_rom is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"F3",X"C3",X"00",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"F5",X"DD",X"E5",X"E5",X"C5",X"D5",X"FD",X"E5", + X"00",X"00",X"00",X"CD",X"46",X"01",X"CD",X"32",X"03",X"CD",X"F9",X"05",X"FD",X"E1",X"D1",X"C1", + X"E1",X"DD",X"E1",X"F1",X"FB",X"ED",X"4D",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"21",X"00",X"20",X"11",X"01",X"20",X"01",X"FF",X"03",X"36",X"00",X"ED",X"B0",X"31",X"FF",X"23", + X"DD",X"21",X"67",X"06",X"0E",X"10",X"16",X"00",X"7A",X"DD",X"46",X"00",X"CD",X"57",X"06",X"DD", + X"23",X"14",X"0D",X"C2",X"18",X"01",X"DD",X"21",X"67",X"06",X"16",X"00",X"0E",X"10",X"7A",X"DD", + X"46",X"00",X"CD",X"5F",X"06",X"DD",X"23",X"14",X"0D",X"C2",X"2E",X"01",X"FB",X"00",X"CD",X"86", + X"01",X"00",X"00",X"C3",X"3D",X"01",X"3E",X"0E",X"CD",X"49",X"06",X"CB",X"7F",X"C2",X"59",X"01", + X"26",X"00",X"6F",X"22",X"00",X"20",X"C3",X"75",X"01",X"CB",X"BF",X"67",X"2E",X"00",X"CB",X"3C", + X"CB",X"1D",X"CB",X"3C",X"CB",X"1D",X"CB",X"3C",X"CB",X"1D",X"CB",X"3C",X"CB",X"1D",X"CB",X"3C", + X"CB",X"1D",X"22",X"00",X"20",X"DD",X"21",X"02",X"20",X"DD",X"34",X"07",X"DD",X"34",X"0F",X"DD", + X"34",X"17",X"DD",X"34",X"2F",X"C9",X"ED",X"5B",X"00",X"20",X"21",X"00",X"00",X"22",X"00",X"20", + X"CB",X"43",X"C2",X"F7",X"01",X"CB",X"3A",X"CB",X"1B",X"CB",X"43",X"C2",X"86",X"02",X"CB",X"3A", + X"CB",X"1B",X"CB",X"43",X"C2",X"3C",X"02",X"3A",X"33",X"20",X"A7",X"C0",X"CB",X"3A",X"CB",X"1B", + X"0E",X"07",X"DD",X"21",X"87",X"06",X"CB",X"43",X"C4",X"C8",X"02",X"CB",X"3A",X"CB",X"1B",X"DD", + X"23",X"DD",X"23",X"DD",X"23",X"DD",X"23",X"0D",X"C2",X"B6",X"01",X"DD",X"21",X"02",X"20",X"CD", + X"E8",X"01",X"DD",X"21",X"0A",X"20",X"CD",X"E8",X"01",X"DD",X"21",X"12",X"20",X"CD",X"E8",X"01", + X"DD",X"21",X"2A",X"20",X"CD",X"E8",X"01",X"C9",X"DD",X"7E",X"07",X"FE",X"20",X"D8",X"DD",X"36", + X"07",X"00",X"DD",X"36",X"00",X"0F",X"C9",X"3E",X"0F",X"32",X"02",X"20",X"32",X"0A",X"20",X"32", + X"12",X"20",X"32",X"1A",X"20",X"32",X"22",X"20",X"32",X"2A",X"20",X"DD",X"21",X"67",X"06",X"0E", + X"10",X"16",X"00",X"7A",X"DD",X"46",X"00",X"CD",X"57",X"06",X"DD",X"23",X"14",X"0D",X"C2",X"13", + X"02",X"DD",X"21",X"67",X"06",X"16",X"00",X"0E",X"10",X"7A",X"DD",X"46",X"00",X"CD",X"5F",X"06", + X"DD",X"23",X"14",X"0D",X"C2",X"29",X"02",X"AF",X"32",X"33",X"20",X"C9",X"AF",X"32",X"02",X"20", + X"32",X"0A",X"20",X"32",X"12",X"20",X"32",X"1A",X"20",X"32",X"22",X"20",X"32",X"2A",X"20",X"3A", + X"33",X"20",X"A7",X"C0",X"3E",X"FF",X"32",X"33",X"20",X"DD",X"21",X"77",X"06",X"16",X"00",X"0E", + X"10",X"7A",X"DD",X"46",X"00",X"CD",X"57",X"06",X"DD",X"23",X"14",X"0D",X"C2",X"61",X"02",X"DD", + X"21",X"67",X"06",X"16",X"00",X"0E",X"10",X"7A",X"DD",X"46",X"00",X"CD",X"5F",X"06",X"DD",X"23", + X"14",X"0D",X"C2",X"77",X"02",X"C9",X"3A",X"1A",X"20",X"A7",X"C0",X"DD",X"21",X"1A",X"20",X"DD", + X"36",X"00",X"FF",X"DD",X"36",X"01",X"01",X"DD",X"36",X"02",X"00",X"21",X"7A",X"08",X"DD",X"75", + X"03",X"DD",X"74",X"04",X"DD",X"36",X"05",X"00",X"DD",X"21",X"22",X"20",X"DD",X"36",X"00",X"FF", + X"DD",X"36",X"01",X"01",X"DD",X"36",X"02",X"00",X"21",X"C6",X"09",X"DD",X"75",X"03",X"DD",X"74", + X"04",X"DD",X"36",X"05",X"01",X"C3",X"AC",X"01",X"DD",X"7E",X"02",X"FE",X"03",X"CA",X"E1",X"02", + X"FE",X"00",X"CA",X"E8",X"02",X"FE",X"01",X"CA",X"EF",X"02",X"FD",X"21",X"12",X"20",X"C3",X"F3", + X"02",X"FD",X"21",X"2A",X"20",X"C3",X"F3",X"02",X"FD",X"21",X"02",X"20",X"C3",X"F3",X"02",X"FD", + X"21",X"0A",X"20",X"FD",X"7E",X"00",X"A7",X"CA",X"04",X"03",X"DD",X"7E",X"03",X"FD",X"BE",X"05", + X"CA",X"2D",X"03",X"D0",X"FD",X"36",X"00",X"FF",X"FD",X"36",X"01",X"01",X"FD",X"36",X"02",X"00", + X"FD",X"36",X"07",X"00",X"DD",X"6E",X"00",X"DD",X"66",X"01",X"FD",X"75",X"03",X"FD",X"74",X"04", + X"DD",X"7E",X"03",X"FD",X"77",X"05",X"DD",X"7E",X"02",X"FD",X"77",X"06",X"C9",X"FD",X"36",X"07", + X"00",X"C9",X"CD",X"52",X"03",X"DD",X"21",X"2A",X"20",X"CD",X"32",X"04",X"DD",X"21",X"02",X"20", + X"CD",X"32",X"04",X"DD",X"21",X"0A",X"20",X"CD",X"32",X"04",X"DD",X"21",X"12",X"20",X"CD",X"32", + X"04",X"C9",X"3A",X"32",X"20",X"3C",X"32",X"32",X"20",X"FE",X"01",X"C0",X"AF",X"32",X"32",X"20", + X"DD",X"21",X"1A",X"20",X"CD",X"6F",X"03",X"DD",X"21",X"22",X"20",X"CD",X"6F",X"03",X"C9",X"DD", + X"7E",X"00",X"A7",X"C8",X"FE",X"0F",X"CA",X"08",X"04",X"DD",X"7E",X"01",X"3D",X"DD",X"77",X"01", + X"C0",X"DD",X"6E",X"03",X"DD",X"66",X"04",X"DD",X"4E",X"02",X"DD",X"34",X"02",X"06",X"00",X"CB", + X"21",X"CB",X"10",X"CB",X"21",X"CB",X"10",X"09",X"E5",X"FD",X"E1",X"FD",X"7E",X"00",X"FE",X"FF", + X"CA",X"C2",X"03",X"DD",X"77",X"01",X"DD",X"7E",X"05",X"FE",X"00",X"CA",X"CB",X"03",X"FE",X"01", + X"CA",X"DA",X"03",X"16",X"04",X"3E",X"07",X"CD",X"49",X"06",X"CB",X"97",X"CB",X"EF",X"4F",X"C3", + X"E6",X"03",X"DD",X"36",X"02",X"00",X"DD",X"36",X"01",X"01",X"C9",X"16",X"00",X"3E",X"07",X"CD", + X"49",X"06",X"CB",X"87",X"CB",X"DF",X"4F",X"C3",X"E6",X"03",X"16",X"02",X"3E",X"07",X"CD",X"49", + X"06",X"CB",X"8F",X"CB",X"E7",X"4F",X"7A",X"FD",X"46",X"01",X"CD",X"57",X"06",X"7A",X"C6",X"01", + X"FD",X"46",X"02",X"CD",X"57",X"06",X"7A",X"CB",X"3F",X"C6",X"08",X"FD",X"46",X"03",X"CD",X"57", + X"06",X"3E",X"07",X"41",X"CD",X"57",X"06",X"C9",X"3E",X"07",X"CD",X"49",X"06",X"4F",X"DD",X"7E", + X"05",X"FE",X"00",X"CA",X"20",X"04",X"FE",X"01",X"CA",X"25",X"04",X"CB",X"D1",X"C3",X"27",X"04", + X"CB",X"C1",X"C3",X"27",X"04",X"CB",X"C9",X"3E",X"07",X"41",X"CD",X"57",X"06",X"DD",X"36",X"00", + X"00",X"C9",X"DD",X"7E",X"00",X"A7",X"C8",X"FE",X"0F",X"CA",X"42",X"05",X"DD",X"7E",X"01",X"3D", + X"DD",X"77",X"01",X"C0",X"DD",X"4E",X"02",X"DD",X"34",X"02",X"06",X"00",X"21",X"00",X"00",X"09", + X"09",X"09",X"09",X"09",X"09",X"DD",X"4E",X"03",X"DD",X"46",X"04",X"09",X"E5",X"FD",X"E1",X"FD", + X"7E",X"00",X"FE",X"FF",X"CA",X"9A",X"04",X"FE",X"FE",X"CA",X"9F",X"04",X"DD",X"77",X"01",X"FD", + X"5E",X"01",X"3E",X"07",X"CD",X"50",X"06",X"47",X"DD",X"7E",X"06",X"FE",X"03",X"CA",X"8A",X"05", + X"FE",X"00",X"CA",X"A8",X"04",X"FE",X"01",X"CA",X"B8",X"04",X"16",X"04",X"CB",X"4B",X"C4",X"DC", + X"04",X"CB",X"53",X"C4",X"E1",X"04",X"48",X"C3",X"E6",X"04",X"DD",X"36",X"00",X"0F",X"C9",X"DD", + X"36",X"02",X"00",X"DD",X"36",X"01",X"01",X"C9",X"16",X"00",X"CB",X"4B",X"C4",X"C8",X"04",X"CB", + X"53",X"C4",X"CD",X"04",X"48",X"C3",X"E6",X"04",X"16",X"02",X"CB",X"4B",X"C4",X"D2",X"04",X"CB", + X"53",X"C4",X"D7",X"04",X"48",X"C3",X"E6",X"04",X"CB",X"80",X"CB",X"D8",X"C9",X"CB",X"98",X"CB", + X"C0",X"C9",X"CB",X"88",X"CB",X"E0",X"C9",X"CB",X"A0",X"CB",X"C8",X"C9",X"CB",X"90",X"CB",X"E8", + X"C9",X"CB",X"A8",X"CB",X"D0",X"C9",X"CB",X"43",X"C2",X"15",X"05",X"7A",X"FD",X"46",X"02",X"CD", + X"5F",X"06",X"7A",X"C6",X"01",X"FD",X"46",X"03",X"CD",X"5F",X"06",X"3E",X"06",X"FD",X"46",X"04", + X"CD",X"5F",X"06",X"7A",X"CB",X"3F",X"C6",X"08",X"FD",X"46",X"05",X"CD",X"5F",X"06",X"3E",X"07", + X"41",X"CD",X"5F",X"06",X"C9",X"3E",X"0B",X"FD",X"46",X"02",X"CD",X"5F",X"06",X"3E",X"0C",X"FD", + X"46",X"03",X"CD",X"5F",X"06",X"3E",X"06",X"FD",X"46",X"04",X"CD",X"5F",X"06",X"7A",X"CB",X"3F", + X"C6",X"08",X"06",X"10",X"CD",X"5F",X"06",X"3E",X"0D",X"FD",X"46",X"05",X"CD",X"5F",X"06",X"C3", + X"0E",X"05",X"3E",X"07",X"CD",X"50",X"06",X"47",X"DD",X"7E",X"06",X"FE",X"03",X"CA",X"76",X"05", + X"FE",X"00",X"CA",X"61",X"05",X"FE",X"01",X"CA",X"68",X"05",X"CB",X"D0",X"CB",X"E8",X"C3",X"6C", + X"05",X"CB",X"C0",X"CB",X"D8",X"C3",X"6C",X"05",X"CB",X"C8",X"CB",X"D0",X"3E",X"07",X"CD",X"5F", + X"06",X"AF",X"DD",X"77",X"00",X"C9",X"3E",X"07",X"CD",X"49",X"06",X"CB",X"D7",X"CB",X"EF",X"47", + X"3E",X"07",X"CD",X"57",X"06",X"DD",X"36",X"00",X"00",X"C9",X"3E",X"07",X"CD",X"49",X"06",X"47", + X"16",X"04",X"CB",X"4B",X"C4",X"DC",X"04",X"CB",X"53",X"C4",X"E1",X"04",X"48",X"CB",X"43",X"C2", + X"CC",X"05",X"7A",X"FD",X"46",X"02",X"CD",X"57",X"06",X"7A",X"C6",X"01",X"FD",X"46",X"03",X"CD", + X"57",X"06",X"3E",X"06",X"FD",X"46",X"04",X"CD",X"57",X"06",X"7A",X"CB",X"3F",X"C6",X"08",X"FD", + X"46",X"05",X"CD",X"57",X"06",X"3E",X"07",X"41",X"CD",X"57",X"06",X"C9",X"3E",X"0B",X"FD",X"46", + X"02",X"CD",X"57",X"06",X"3E",X"0C",X"FD",X"46",X"03",X"CD",X"57",X"06",X"3E",X"06",X"FD",X"46", + X"04",X"CD",X"57",X"06",X"7A",X"CB",X"3F",X"C6",X"08",X"06",X"10",X"CD",X"57",X"06",X"3E",X"0D", + X"FD",X"46",X"05",X"CD",X"57",X"06",X"C3",X"C5",X"05",X"3A",X"33",X"20",X"A7",X"C8",X"3D",X"32", + X"33",X"20",X"FE",X"04",X"D0",X"AF",X"32",X"33",X"20",X"3A",X"1A",X"20",X"A7",X"C0",X"DD",X"21", + X"1A",X"20",X"DD",X"36",X"00",X"FF",X"DD",X"36",X"01",X"01",X"DD",X"36",X"02",X"00",X"21",X"7A", + X"08",X"DD",X"75",X"03",X"DD",X"74",X"04",X"DD",X"36",X"05",X"00",X"DD",X"21",X"22",X"20",X"DD", + X"36",X"00",X"FF",X"DD",X"36",X"01",X"01",X"DD",X"36",X"02",X"00",X"21",X"C6",X"09",X"DD",X"75", + X"03",X"DD",X"74",X"04",X"DD",X"36",X"05",X"01",X"C9",X"32",X"00",X"50",X"3A",X"00",X"40",X"C9", + X"32",X"00",X"70",X"3A",X"00",X"60",X"C9",X"32",X"00",X"50",X"78",X"32",X"00",X"40",X"C9",X"32", + X"00",X"70",X"78",X"32",X"00",X"60",X"C9",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"3F",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"1F",X"37",X"10", + X"00",X"00",X"00",X"60",X"09",X"00",X"00",X"A7",X"06",X"02",X"04",X"03",X"07",X"00",X"05",X"CB", + X"06",X"03",X"06",X"FB",X"06",X"00",X"07",X"7C",X"07",X"01",X"08",X"0B",X"07",X"01",X"09",X"49", + X"07",X"00",X"0A",X"49",X"07",X"00",X"0A",X"04",X"02",X"F0",X"00",X"00",X"0E",X"02",X"02",X"A0", + X"00",X"00",X"0E",X"02",X"02",X"90",X"00",X"00",X"0E",X"02",X"02",X"80",X"00",X"00",X"0E",X"02", + X"02",X"70",X"00",X"00",X"0E",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"02",X"02",X"F0",X"00",X"00", + X"0E",X"02",X"02",X"00",X"00",X"00",X"00",X"02",X"02",X"F0",X"00",X"00",X"0E",X"02",X"02",X"00", + X"00",X"00",X"0E",X"02",X"02",X"F0",X"00",X"00",X"0E",X"02",X"02",X"00",X"00",X"00",X"00",X"02", + X"02",X"F0",X"00",X"00",X"0E",X"02",X"02",X"00",X"00",X"00",X"00",X"20",X"05",X"00",X"10",X"07", + X"09",X"FF",X"FF",X"20",X"05",X"00",X"20",X"0F",X"09",X"0F",X"0F",X"02",X"02",X"00",X"02",X"00", + X"0F",X"02",X"02",X"00",X"00",X"00",X"00",X"02",X"02",X"80",X"01",X"00",X"0F",X"02",X"02",X"40", + X"01",X"00",X"0F",X"02",X"02",X"00",X"00",X"00",X"00",X"02",X"02",X"20",X"01",X"00",X"0F",X"02", + X"02",X"00",X"00",X"00",X"00",X"02",X"00",X"10",X"00",X"00",X"0F",X"05",X"02",X"E0",X"00",X"00", + X"0F",X"05",X"02",X"20",X"01",X"00",X"0F",X"FF",X"FF",X"05",X"02",X"00",X"02",X"00",X"0C",X"02", + X"00",X"00",X"00",X"00",X"00",X"05",X"02",X"00",X"01",X"00",X"0C",X"02",X"00",X"00",X"00",X"00", + X"00",X"05",X"02",X"00",X"02",X"00",X"0C",X"02",X"00",X"00",X"00",X"00",X"00",X"05",X"02",X"00", + X"01",X"00",X"0C",X"02",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"08",X"02",X"00",X"01", + X"00",X"0E",X"08",X"02",X"08",X"01",X"00",X"0E",X"08",X"02",X"10",X"01",X"00",X"0E",X"08",X"02", + X"18",X"01",X"00",X"0E",X"08",X"02",X"20",X"01",X"00",X"0E",X"08",X"02",X"28",X"01",X"00",X"0E", + X"08",X"02",X"30",X"01",X"00",X"0E",X"08",X"02",X"38",X"01",X"00",X"0E",X"08",X"02",X"40",X"01", + X"00",X"0E",X"08",X"02",X"48",X"01",X"00",X"0E",X"08",X"02",X"50",X"01",X"00",X"0E",X"08",X"02", + X"58",X"01",X"00",X"0E",X"08",X"02",X"60",X"01",X"00",X"0E",X"08",X"02",X"68",X"01",X"00",X"0E", + X"08",X"02",X"70",X"01",X"00",X"0E",X"08",X"02",X"78",X"01",X"00",X"0E",X"08",X"02",X"80",X"01", + X"00",X"0E",X"08",X"02",X"88",X"01",X"00",X"0E",X"08",X"02",X"90",X"01",X"00",X"0E",X"08",X"02", + X"98",X"01",X"00",X"0E",X"08",X"02",X"A0",X"01",X"00",X"0E",X"08",X"02",X"A8",X"01",X"00",X"0E", + X"08",X"02",X"B0",X"01",X"00",X"0E",X"08",X"02",X"B8",X"01",X"00",X"0E",X"08",X"02",X"C0",X"01", + X"00",X"0E",X"08",X"02",X"C8",X"01",X"00",X"0E",X"08",X"02",X"D0",X"01",X"00",X"0E",X"08",X"02", + X"D8",X"01",X"00",X"0E",X"08",X"02",X"E0",X"01",X"00",X"0E",X"08",X"02",X"E8",X"01",X"00",X"0E", + X"08",X"02",X"F0",X"01",X"00",X"0E",X"08",X"02",X"F8",X"01",X"00",X"0E",X"08",X"02",X"00",X"02", + X"00",X"0E",X"08",X"02",X"08",X"02",X"00",X"0E",X"08",X"02",X"10",X"02",X"00",X"0E",X"08",X"02", + X"18",X"02",X"00",X"0E",X"08",X"02",X"20",X"02",X"00",X"0E",X"08",X"02",X"28",X"02",X"00",X"0E", + X"08",X"02",X"30",X"02",X"00",X"0E",X"08",X"02",X"38",X"02",X"00",X"0E",X"08",X"02",X"40",X"02", + X"00",X"0E",X"08",X"02",X"48",X"02",X"00",X"0E",X"FF",X"FF",X"0A",X"8F",X"00",X"09",X"02",X"01", + X"00",X"00",X"0A",X"AA",X"00",X"09",X"26",X"01",X"00",X"00",X"0B",X"AA",X"00",X"09",X"01",X"01", + X"00",X"00",X"0B",X"A0",X"00",X"09",X"01",X"01",X"00",X"00",X"0B",X"8F",X"00",X"09",X"01",X"01", + X"00",X"00",X"0A",X"55",X"00",X"09",X"0E",X"01",X"00",X"00",X"0A",X"55",X"00",X"09",X"0E",X"01", + X"00",X"00",X"23",X"6B",X"00",X"09",X"0D",X"01",X"00",X"00",X"0A",X"8F",X"00",X"09",X"02",X"01", + X"00",X"00",X"0A",X"AA",X"00",X"09",X"26",X"01",X"00",X"00",X"0B",X"AA",X"00",X"09",X"01",X"01", + X"00",X"00",X"0B",X"A0",X"00",X"09",X"01",X"01",X"00",X"00",X"0B",X"AA",X"00",X"09",X"01",X"01", + X"00",X"00",X"0A",X"8F",X"00",X"09",X"0E",X"01",X"00",X"00",X"0A",X"8F",X"00",X"09",X"0E",X"01", + X"00",X"00",X"23",X"A0",X"00",X"09",X"0D",X"01",X"00",X"00",X"0A",X"A0",X"00",X"09",X"02",X"01", + X"00",X"00",X"0A",X"BE",X"00",X"09",X"26",X"01",X"00",X"00",X"0B",X"BE",X"00",X"09",X"01",X"01", + X"00",X"00",X"0B",X"AA",X"00",X"09",X"01",X"01",X"00",X"00",X"0B",X"A0",X"00",X"09",X"01",X"01", + X"00",X"00",X"0A",X"8F",X"00",X"09",X"02",X"01",X"00",X"00",X"0A",X"AA",X"00",X"09",X"26",X"01", + X"00",X"00",X"0B",X"AA",X"00",X"09",X"01",X"01",X"00",X"00",X"0B",X"97",X"00",X"09",X"01",X"01", + X"00",X"00",X"0B",X"AA",X"00",X"09",X"01",X"01",X"00",X"00",X"0B",X"BE",X"00",X"09",X"01",X"01", + X"00",X"00",X"17",X"8F",X"00",X"09",X"01",X"01",X"00",X"00",X"0B",X"AA",X"00",X"09",X"01",X"01", + X"00",X"00",X"0B",X"97",X"00",X"09",X"01",X"01",X"00",X"00",X"0A",X"BE",X"00",X"09",X"0E",X"01", + X"00",X"00",X"0B",X"7F",X"00",X"09",X"01",X"01",X"00",X"00",X"11",X"8F",X"00",X"09",X"01",X"01", + X"00",X"00",X"05",X"97",X"00",X"09",X"01",X"01",X"00",X"00",X"0B",X"8F",X"00",X"09",X"01",X"01", + X"00",X"00",X"0B",X"7F",X"00",X"09",X"01",X"01",X"00",X"00",X"0B",X"8F",X"00",X"09",X"01",X"01", + X"00",X"00",X"0B",X"A0",X"00",X"09",X"01",X"01",X"00",X"00",X"0B",X"AA",X"00",X"09",X"01",X"01", + X"00",X"00",X"0B",X"BE",X"00",X"09",X"01",X"01",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"23",X"53",X"01",X"08",X"01",X"01",X"00",X"00",X"0B",X"AC", + X"01",X"08",X"01",X"01",X"00",X"00",X"23",X"53",X"01",X"08",X"01",X"01",X"00",X"00",X"0B",X"AC", + X"01",X"08",X"01",X"01",X"00",X"00",X"17",X"1D",X"01",X"08",X"01",X"01",X"00",X"00",X"17",X"53", + X"01",X"08",X"01",X"01",X"00",X"00",X"17",X"AC",X"01",X"08",X"19",X"01",X"00",X"00",X"23",X"53", + X"01",X"08",X"01",X"01",X"00",X"00",X"0B",X"7D",X"01",X"08",X"01",X"01",X"00",X"00",X"23",X"53", + X"01",X"08",X"01",X"01",X"00",X"00",X"0B",X"7D",X"01",X"08",X"01",X"01",X"00",X"00",X"17",X"FE", + X"00",X"08",X"01",X"01",X"00",X"00",X"17",X"40",X"01",X"08",X"01",X"01",X"00",X"00",X"17",X"AC", + X"01",X"08",X"19",X"01",X"00",X"00",X"0B",X"40",X"01",X"08",X"07",X"01",X"00",X"00",X"05",X"AC", + X"01",X"08",X"01",X"01",X"00",X"00",X"17",X"AC",X"01",X"08",X"01",X"01",X"00",X"00",X"0B",X"40", + X"01",X"08",X"07",X"01",X"00",X"00",X"05",X"AC",X"01",X"08",X"01",X"01",X"00",X"00",X"17",X"AC", + X"01",X"08",X"01",X"01",X"00",X"00",X"0B",X"1D",X"01",X"08",X"07",X"01",X"00",X"00",X"05",X"AC", + X"01",X"08",X"01",X"01",X"00",X"00",X"17",X"AC",X"01",X"08",X"01",X"01",X"00",X"00",X"0B",X"1D", + X"01",X"08",X"07",X"01",X"00",X"00",X"05",X"AC",X"01",X"08",X"01",X"01",X"00",X"00",X"17",X"AC", + X"01",X"08",X"01",X"01",X"00",X"00",X"17",X"1D",X"01",X"08",X"01",X"01",X"00",X"00",X"11",X"1D", + X"01",X"08",X"01",X"01",X"00",X"00",X"05",X"FE",X"00",X"08",X"01",X"01",X"00",X"00",X"0B",X"1D", + X"01",X"08",X"01",X"01",X"00",X"00",X"0B",X"53",X"01",X"08",X"01",X"01",X"00",X"00",X"0B",X"AC", + X"01",X"08",X"01",X"01",X"00",X"00",X"0B",X"53",X"01",X"08",X"01",X"01",X"00",X"00",X"05",X"1D", + X"01",X"08",X"07",X"01",X"00",X"00",X"05",X"1D",X"01",X"08",X"01",X"01",X"00",X"00",X"05",X"FE", + X"00",X"08",X"01",X"01",X"00",X"00",X"05",X"1D",X"01",X"08",X"07",X"01",X"00",X"00",X"05",X"1D", + X"01",X"08",X"01",X"01",X"00",X"00",X"05",X"FE",X"00",X"08",X"01",X"01",X"00",X"00",X"23",X"1D", + X"01",X"08",X"0D",X"01",X"00",X"00",X"FF",X"53",X"01",X"08",X"01",X"01",X"00",X"00",X"0B",X"1D", + X"01",X"07",X"0D",X"01",X"00",X"00",X"11",X"1D",X"01",X"07",X"01",X"01",X"00",X"00",X"05",X"FE", + X"00",X"0A",X"01",X"01",X"00",X"00",X"0B",X"1D",X"01",X"07",X"01",X"01",X"00",X"00",X"0B",X"53", + X"01",X"07",X"01",X"01",X"00",X"00",X"0B",X"AC",X"01",X"07",X"01",X"01",X"00",X"00",X"0B",X"53", + X"01",X"07",X"01",X"01",X"00",X"00",X"05",X"1D",X"01",X"07",X"07",X"01",X"00",X"00",X"05",X"1D", + X"01",X"07",X"01",X"01",X"00",X"00",X"05",X"FE",X"00",X"0A",X"01",X"01",X"00",X"00",X"05",X"1D", + X"01",X"07",X"07",X"01",X"00",X"00",X"05",X"1D",X"01",X"07",X"01",X"01",X"00",X"00",X"05",X"FE", + X"00",X"0A",X"01",X"01",X"00",X"00",X"23",X"1D",X"01",X"07",X"0D",X"01",X"00",X"00",X"FF",X"FF", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/commsega.zip b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/commsega.zip new file mode 100644 index 0000000000000000000000000000000000000000..0d92c5306c298e3b20b1aa7e28c47a4a28b15ddb GIT binary patch literal 19296 zcmZ5{Q?Mwovh1>L+qP}nwrz7S+qP}n_FlGa`|k7J*Ev6#WF}Rak5o;kd!ir>41xjx z1ONd5(49^Q%CeIf3IzZFfB*mh_RknQo0=Okx}y6!pe*~k-+nsfMTp4LY!L^@Fa^=& zD5o8TCp=lT5EKf6A%a_;{jF2rc5YZ?CeSCgi2otHsWrwZVPA@McBJu(rggs2n!dTW zF$Dw3S-qE{!yEwyLH%0m`Pu2>4rkCIv-iJ!{r1zhSI0llI^=)fc6gL^HrMxO2JK26 zIox)qiO_$tKBoIkYTph?c`p{mQH_RPvv)f9*#6~GAtJ2;(e7r7Y@yiM2=E?!%QO5c z;h%^A7FJ6@iNfzmI|_WSa$-*^4hrz_a_3AD-m0bOi>mWjJl@BqqBq_N=6^1dGTopg zC668WwG`zkG8mxst(lgT+@)|1o&N5As!3c9>UL3+lsru~Z0c{xRa&`bJ$)2Iv)P5_DNSp0%&07Whkei5A(S$ws?ti(PhPa}4A`tUGn+XENxpcpAA@*DRE2vwkWkGg z%|JjEwWR}ym~2PR_dp@;^?t_qqu}|@lu^f#yVY|RCtQcWhCzuN=OlFHanCbLVhCKQ ziJZHxh`xdg)Y4Lco5aAy6IY9+TSfR86A*eTyIFhz4|!$^)y%{!f2H~N_u}$|E$|d% zH{_dcKwwUxOq;!;9_vYP#;;~Ao0D#>n{&(%`a~-1nqdiU(^3s&(^T(#UK!2-)&mT; z-#PuEJ*S^}1d_+!5nzrl%x@5|U~MkS95rh$*d1UoKTkC}>Tb~VE>`;A_ym!*@2(TN z>xuY-vz=YFZfkz#j9z4Irx)q26O?y$Qt~GKj{9%R4+?yRO-8E>Te03cT-Gbcb;SuJ zISVmfF|DOQgcS8rb*iIOuoaq@x59FyoF#a$d-+C}T+qsR=T&m9dHJcT?H1*=$=xiK zXQ&WUcDpPork)N_l2Stn=?3MaVl59&&!eaxM6Smq>RXZ6RTog-Lik*$qc+Me`k<)4 zQ{@^pIqn*INKBx<<=bY~9di89Vgz z474fDM=tdCMe3+1Q^zhSaVams970>=>v6=O{y>gZ7@8y5*f%muNp&`PT9WO*XZpGx zY0?)UwmFU0Ja5_1;92vuPR-IM#5zDY@}YvP(DP>KE;n$?0j_0M95FcIdqar6Ez(*< zZNYbV=-GJl^(y3WSb6~0fjb4(O~CYW0VnaRGp3E;tzBALK^x&!`Zk*|JyP+#`2kP~ zUTt#PbjT>zwf2I&Zsm-m*0m18cK82Auoe-XZ-#yf%L#l74y7_$hQT=mEvp&V}R~6rat<>BJr~{7@h}^phVo20x+Y= zRGZDTR5EY$DED-jiKcss>?R;E54+0R;^}GmZZd|Bz!nNKg7X4PIQPXsg#_Z__ooWI z;QVfFQF+t|4Rfg7;*~iFv3DwX{AVNdo{mlM{MTc3pVs7+pBOfS@T><#if-==NAQSO zkgF03x^*l{_Gwe9{unn44zB5I7e7Gr8`W! z@(RBIpxPXxa;ULS-B2jsuXsL1X&cdaQ&&)d+ z^S-197VPgr^ZZHqD9VaeABZR-RGs>^E$yDx;nVBhuK1K6*SV()=kS>9Up9x#+IDBN zqP|}$f-imK0h$1*QWu8`!#XY5=Q0~zPg>U#NW#=3KzbaaLUwvU>+Y~EgkyMEnAy81 zCzv0=1^Dzxe>=qdyiYRMVC11y|iP&)h zvuKX0TW~bTwXF{kWUOt;HP7l-_ymm9w8z4)=XLy)qQN+jfZgJ^Yk`4!Kri@AFCes_ z?vhwNp!@xe8AR5uyW;`uuKo&K`J}6VTBf$CHBBF6i_>P&{C%Ji{LvO3u*eQJD3c_! zDB(ni7zx^t_5(J`!PWc=ckk?MVc$k?yz6;a?_cti-|bTB&IY~!9Wk$mpyyJewKg}Z zog0MDboVV1>{5~$gb7kEXKN_DpSEEOtJI_=VJUsatjeK|(SHrg*`Rri&iV1cS)bJt z-Uz;lMX*ziwMgP-EUP3A!oW_7mnmA|Tu)Pn>eL`M5@4HlNzve^P4M7vH5mLEPbW48RW*-;F#tO# ziCuX-QyCbARRSlmg2%KCG|EakI|z)Fkq(}isZM|wj79%ETE6|Id|AWII+tB^hL z=^|EkbO5jz)2v!x4UhJE`q&h(2F!u4ARF8boP13QBX7Z}Z=%8AreF1kt zt8;x$Q>*iSoY3@x2Ea2M!_YAR)~3Lsy#GWUXXB-OLj4L4c{yf zteR>ts~~X6(+KUnLX0iQP9ldj{;MQKaSS+N_zGVy9P|nw;2zcCA?qly7LAH&l~D5e zcsLw^^!#C^ACd^?19YxjFpEa;1c62gkzibTJfzYTh+zgniwr{Qf2NXMYq&2G5Vo4~ z$4^fn5KM|vBE}J;8V9Ql!>kP=1gY&*sp&Y{Ze?}A#XK$$ov}4=w z0{PNG?L&ofjk2<`!kLAaE2%>Z^{FgW7WyDWr=X}5_bzPkl=7CV<4ve3sfYS}NtSZu z)Xut!2vw6A#UnX!pu;$Poj6p^!|Ec}4c{u;DPi|3jEFb;~|AkaD>E-Tk{}-t;rJ(!TU@w2qn&(|}xZU84MfCZ$Fkl0< zr90W^IYSl}FUKb~+Ckb71BxwKZZsyxabARB7f@Mu*-<4y>}d$FD*m>VXtOJ_P@HVJ zab|&QR;9*Yt43*T08~kcM}-b^-@e{t$EEafE#b>rWW>cRk0ECcqlridJ~Jh)Q;)Iqo>X+Gwpl3a8g*Tuuts2- zTD$pQ-~X{bdcD9(i0tIc@S}*EWv60w?uAMs`!2`52Hti)d9rr)nn-7wo?7mKdPLPP z?NF$Wjyz8t+;DLQ>@lH?i*ymiYy=C2$B0db=>?+Fo)j19EQHydvJcM?DA3T#fzmsdBKywKFNwKYw;()Gz=&nPfb_ zcDqmgc(}bbD((GJ?|Pg0c!+Yl?>bRRy178$eyoPLoOoL44lVJ(o7$pCtzk&d^k?ae z=ShR2g7IR3{X5$|HqfLkcZj3i{qyquu&gY8+~xp8UTyd6OaEL|mQ)8zzIAb`7qQ+4 zayKL3rDu|7&P~IV9Rf(S$c_@HjDn$JHwu`T&)??d%$y1bT%&%kVOP8j+-xlHS#Z!G zI9v#?z5o``dJIYwvuv4HQ+N%uK{Vf6=fOec{M>t*SurWHQR=aVZHi~VA`v^FnR=v= z-4dS-YR;=K=J*@@!Ngm-P}Sf#Y9Gb)2FdN#TF#f3`mWa7S#e;Uz!v-9O*n#g7>Zn= z>#wl-UL5lYxM3&|2_M}Xw|j1wNaxkJO5t;MgSyx2`?XWt4udNd+1=rzMyRBEKW-9E z7)&$Es9A{$)-xI)MH&CjlMD(5-xz3U6R&q);O>i+OYU63fN3VN$M!6XFSk|P3#MVo z9RrCbrHnF_14yImhh;E@H0>NJWq<1ieCkJ}%NHJo$%8XCl%w+3Asfcss6l6vleU z?U7|d2mZs{Xn?NanjwcFOU_VZ+Jb@O`qpOyr>{_1b`J+=nVyj}$7wsj{mGu~8NnW| zISvne)q}I&7B;R#r_waULoqAS_TLd^JUn=@`*`4<3w+8-WxvsuAdCI3CceZI z9WH{V8w6Bz4o4*Hx^9cln4P%=64LrlMvIW{hq5_uvB&xMzvP|i)q%|_y19ntKqf?w zibUcA&wIy8L@*Vd{cvKg-w2!vqj?Y7_R&kS{78a?i zVC99?e)m`CwhFL{Bm#;|?hC~_2G4iZ{PmegY!tE|9h0=75LoNCmQ(KrZrEP)ZY|sj z-xZy-3Olga)dW^EHvHj@N*b-Tj0+AgZ|h}h^M_!W+{91&e$*dJ*I2gLXK@Pkr8AZb z*?-WZEpc;LTnGa4Rftg-tiU_T+bh+!P?&faK;MJFb6C_U;2Gi>p$iH?(;Ni;oJE<} z2;Lbg+CoyXl7O~IzQwP062;m6|?vG>KIhpb*RF4ZLKE~_CK4~Y}EhPmYpyMjl zn2j>1l;0Czb@p(GTG)fNcrfiSd}=75mriY-r)dQc9@efS0=JQSm=cc&y$K}O6zO%9 zGo06*EDSlaV3k=aR{H={rx?}antKX_i$1#`Ov}%>KEWB}dsspX<9m{Ey-Pw}Au&&( zh=`UAYrs%#PyLyk`y<0=xnS5xNZ!nwDWx8y@HUJfVWX4yY$>IYxLlqgss)Le$QCwl z0MUaX)LWnWE-Lssoz4yx%!eVQO&lOTWC*Jpn=i`<#e=n6E@^=dw)snCQh!sW57y%+ z{w?wJ-&d z(G_96L*NJu;2I6qy~{DJj7k-h%b_n$qVN2Pd0Avx8mKsru;sR`;MU+{NE1JG+kg|E)`-sobr&hn{7x6q18`^(uIfSct?cknea$4#7Zao7uS*d` z?Slje&8GwiL7N?Q24Cj4rbwK8nmxSm6SnhqGG&?Jv^nvxXV%AKxTTC1k#lomuu*(# zC?jmqhNgttS28gFxeA)Zie?%wvgRVVO|9;FJ4j6l0ZW5)loc0L9llSaAy}(TVL2Hq zgxew9+?k_8tum`gkw!ftHXfj3hc+e zr9-->OGGN!^EQQT&S*zpbfNKrs-+{XmLF&2-|~e}ipWkRg%ibRnB7fR-v_fmWzs$I232GP2k4Zi{Maq<~IU>7Zat^1w!y#xZFI<&(nWpP7DOy zb9oUj*W>v#_Ao2ThSqPiCdCQ!lZf%33j+(ozS-1MK!F}1@ z0Bh28cwf8vnLabL4FOGVN$7?&E)2pcM&T$@0UFvad07ujl_h~nHy?kX5Oj^DrAQg2 zmGWYaXQ0VUbT7j-NJFZDZD%3imMx@!P_ANoOLMxF;mZNbAK%UFKD*_8<39U7>prFv z$TOQnu4B@?u!j715cGLPi)bgu1tNPo2_|jXSWqcRVFiRW@!)EL<8gKm$=>PXKx?Vs zGpJPA9;#Ay;6`~VZ^OY#E7*I^+vbi2BR7YRw~RwF5v$$$OR++n6Yp>5t8B*XR+J#s zO^yplhXCpbuRiQzChMe!LeT-DnOnu7VC1K{M<$pKU8Y-)+>$EGb*Ux2Ec=oRv@9qG zZ2j*ry+d&d&5p~L!@=y3^Qe=8FLijqbb?IFc{b}8(S(Yrc}B%&l(NaRND1raWAX?y5wT5;No1^rD?1QR&*%r)d)}kqx^|mxw6vIX*Qn9v zf?0I++-!vZuGq*PiorFvwE5TLVv@0gc02(C3q-1*h5=&n)-sFgP=t3!E4?gcSdf~; zXh+P!#d#Hb^F!>B;46(oNU&-)?|Dp&7U%KacjM9*!|OI%G=jdo{ol2q0~2HZdfLMY zs;i z=KMB^Qf+g^f}Ch?Ct`Qh!I(2KpW$58>C_Wc3hDIms?WIgv+VfxVEv`>09 zXfRCEN?KYla*$U6z%}J);CctNZ1uZ3OSTX8*f%xLsVoMjBjWEB#)3@t7C70V z2UH_*lGnE+W@EamxrYw=CuzqRK$KU8{F1Ua8nPPOwiA33paZ>Zq!GeLCyjtxTo6N_ z(4SlzC9<$Eh6lvsLu9x+0}~$QF6qqTL!)B%JApSs;^k4iOLno*CpFdfRv{XYX6!$! z3mwt;KmU1Xnt%Ti33s`_E9*t-e9U-!rx7^3r$1z_yF~AAy6yb1?*3i}V?RpDip&ip z??gYZJP-1=Q$2x_Xi3^cfu+95o+$rA9b+!d4#~jl!i_6V7*>S@WN^7DlzL zS;dEAKA12h5Ee`sqHrf!)~S!=LNuEUf<(Ht8^U5V9H2ri8Bs#RNNx@}hZ++usqTFL zQPylwijN^_LJOj~h`P5!dI{;#4u}$lH7U-OtYEM5=Ki81EAbq*$^`+o8cGj_gu}rz z#*w1Jby`H+aoac!0nlpnau0ixsQd5%&$cK302rCzv*qM`-7f(JDW!2WI3~ajOpBK+caLXFtPIXegXWhN^Cfu(P?v#}1ce%jwloDJ z!oLp36pl*T#wqogD65Wf!Oy)?lHF8ISSS{M%(+V2H*m~*48M%6HhUd&U*xNN^I ziHNJxC4z}`qA|2rh+oYz{yj3%D$UR1(_;TB@(BN;BI5&Q zJ?FSBS5|Q;e!j<9@N1mQ%m9IAPj&prIbNc0QdFPRN?B_uJHUMGubz>72i*%oiK2}d zm4xpGBtc4EpA68q#C|7Mf5_(je9Ju;5R2@;qUzRc6t9!P;m?)aY@uG#gAUumTpF;DMz%D)6+tZseFkYvxd%;k$({RjyGi2 zs^vvtEw}=xAf$at)eKo0{OzvC+3m-A145BW`_WVBUMxc^G@5a9QDMY)glb}|9mAl5 zw;F*-lOC}NsKCf^JZT*k08bH+!HorMg{kl0SEEuRtHKXw)ETP30OY6+GX?;iu#rZw zKvu3`W=t-(A4?aZG&c$t!j09GYRS{c>oDFTkU*tCZFZNeW{9{AGFpEp?h5hp#p|w6 zx5VIYJ37*5r~Y|(fYLSU-oKpLK<{TBFG=vU&aHiQ zo);Z8w}*1?Xic=?HZo#q<{hI8e??J-+IVYT@jOQqHmSj&C_ko%UpBD9|BRkD2)E_IXj-Bt($NJH zPb;E3ntUQp4kjBnJK@pU?aT$3Pa~2I62PhXbs?9&TJ+08D0%T10b?RC$v_4%k17QO z@ntqxy;w&YFd|`ptGU(OM1-Ev!m?ei$=odo zgZ5BTJE(~8Xf-pf?aJ5`0#IKijP+ zB;O2mgR3IsIk-8aaXNFd<8=(=GE*_s-NOIQ@JCuYg9Q*Pqe!+z*BXDmT*Y?;X7Z0p zh$}&{)$#NFR?am?&3d21%l0Qv-|PEF&+TI_?~I+Hqm}Wwb^*`67ZZnQ-=^?Rp}iek zPU>h++!}*m@-4Q#$?qvA)A!89%qSHVVyj zsUNG}Fj}T9eo0LO?FSpvM=s1?kTy|pi0Don_A6m<*K=%mf=O~+`b8nvpCYMe65hNq z%0yJt?&d~aV$w6A+w}X+$sb_YnP5jn6g(dd))l}CkcBSE$q&%3TS$!oeN(nQmBgQd zd6f9vCuEZLb!;Id*pcP;PtL#`!&^8WTh-es<`>MMI7MRNY*6`-xJBZkul)&bq~Kcg z%c>IkbXC7 znRWR4t!^Ir(PI@InCc=qYyLE8grhns~DO$mf_k7>tFc z`{fw0n{p?anISTC;ZuDG+|G>R=V$MGF~;^b&ZR|naKR5cLTOOp-;d;8Plb8XI+&Qt5e@*jhaVJavK9j$i>JsyqHcJ3n%q)v!{g5^?ZH$5JW^4=$X4%DYv+KT>R#b$bPsg;wsUXqGdEcnXXp!RDr!TbO}3- z=T9^WbWQ?HwQmw_8+YMcjQB$dF5=IQ_4;7Jnb6sebwQERSvm?*@jSE=1*s!>{BQLi zPN{?3lx*>m#Y@C#Oj0{FCp_h3t=OuPyvMtu&m)Bj=FA?cc1cOp11IYJQPqxmSMGfe zSs$ojJ=tV|t^5f84Y@Dp#fw_bbCW#~5r@WcU+hsnE0CIANVUK*_~(&h%t+Cyv}|k= zn3W!9BvSxXF>+E<^;iAt5H8&DYk###<)meam{?W%)8dnHXeBmx4{n+Sf@Aam-&`#9 zo>5ig5#V7nz|j@}jeT~m(F71xbr+I?Dry$VdDjp^$kNLGP3#|BgSGv|*P1`vR0FkU&PFIh zY(s-MljV1ekZf9kDRdtmCJnFEf5Ch1ztZSY@eba{n8B(4vS#MhoYlHMl#qM=2#{%) zi@bYMR(!}y&HAxTErv4?vfe?4KXi5$}AW*IVbUl}+-9aJE`(A8yEGp>$*uovg!vnZ*Oi z;t2+}^S!}?=VI!}!JoL{$OJ5QEx)=d*aDL-%J7GH%ET;57Y%#3l#5uDt=i32{)-J8 z21bZQXwuNSc2zyJzOk~iuzu`hf9K)5jqT0hZ!m|4Nmo`&dwui5Wm-3Pa6hqPmp8X; zx+GgnxxQ_9zscKJRW)R<4wxpsqN-RIypiVSzDBFpwRQfmc8sQOt&ZKoT@&3Xno6mf zk8%m7Q5L-eZqUg&%@S7C;5uX2=_!S(ho^;WWR$Bx@v^+OuYuhn&fK`8ZilO#G#H3_L zBDf5fO%XD%G7Z>PdP=2DyS8hxG4g!H*o>tIO*hUjN9}VU@TIhmK-mnLwkb6hO&y&? zWV~D);;$7T1f~qcI(N6LF8t$lV_)r(*&m{%3vG?y7}gC<-=@O(Cft}I^at-IQ6=mri&4NrYUi^ zVZ4Z&@YvYs;jpl_vF3<^@CTJ-LOvu}sIic=KcM@(`^bT^_Oj$l$b*pk-42o-`t8IV zivv%5`^9&S4w`QQZz>L@uh374*c$uJp{i}-gF)Hx`}#;3V)qI#l6M6gD%kVcn6>|-OJmGxPJP!fB%Pxn!i-* z4)|Xv!#b1d?E|}x+dnsbgd5@b*qIP^*-)?tQvQn$6Qp=@H+udxA$Bt<+)$gV5XZAgJ z_wZ}hem0}S`Ia<=i1uUx>;4y2ODm;~=+)_FXN%eM+%qs^&OH3A-y&L+{AE}~MhyLB zz;6v7{D1%_S{T6rqtpN^cGv|c#+U)Qi2-}e81CdiWO@uJJ4loR7SVi?Y zCp!+>0g-MLNhe6!k+Zg+$p?2=Adp+r)91V2quxR0( z4wBVdz#yL2KcicPE@j3ss#~)*8GZ`(f$)9FpV#F3Q2xjBcYuG;)=AGUZEgbo=<|V> zvy`ZlsFJ9KsKm%)WcSDKc2@uP=lw=(rz9T5is zwqfs2Zal=qUJ&0r{Kt?021u|W1OQAhibQZiJY10>jENAM$&kl*piVl(y8?i6K13PS+WbK7m^Mxt8&2;TXN(z|>xa%xiz#~&ktly4IGM;2 zdU6X42@UrP40#KKf`WsCfrNzq^alW>C`W)=+W_-)0cJ0RgO=eZuY|i}KSW`>;n+CB zT5I-}9$%@>l3QHyUNSiWc|ZI7vRT=S-~SoVJY$Pe)MLe+eDn*(31{Lo*?-+-G?3O% z5MSanu%aHFtf#@1I}NC)!EhBCz`3Zg|CV?}%qy*|oEw|Rjb+Vc6+BiIL}e*LoV6}7(Ispf4jYUSvoG<8sZ zzm&B#-+cMoa%{5d_ojESGWO!E*W{HgEbDcl{P2*!i ziQ3E)HenJa1if_n#7Q?~^zZC{(>0y3Yent_d-+vulPxl~)pv(CxhL?$v0sO1@Zl4R z&zHPgSGH6Zwl=o5S^F83Vb;R__jO7r9^p002ejtHO`3YGhXEL4!G=U0v{%Sx+fJR3;E1^5-LfS1TxAADf&zqZ%Vom z(TFw=Z~GGVOu^s`yo%^zLK*%d z9%11OIrT+LjHRMvMV9RIg-MHzm~-AIBX7V+)vZWUu_H|{B z5`x`!H3fuAK|w&7;WdpFV`JAYn-lfPUM_1ex0!~`kB(CLEG-kgD3=w(Ma8fQXy@F# zZPqb6@7|Zf(-KeTs2J;zKlOM>gFn9xg-a8iOBI`@b-hY2&xs>ZohNIyzWmVW-8{Sg zHL+YWTo(+Qt<5eI{*&kBOFJj`+5D%BPC~*Fu?fid^cNVe8=I4pvw75)|FWjn@ATMr z@B5yqd(KvnetI0$F5LX39kUZx@gb<8#wVeT2Up2X)T6rnxg(75k&qzql;~_?zKboA zjS_}#{G>4n{gmUb708(Ts|ZyoUCFMps@|sds+aTlLoGake9Zjcbc^0M z_*~EbVidL#bwdm7Rn*=&sUmi=r`&FhiG1HgQz`DuW%?8ge~pYDNrPZ$NI8wjS8=17 z2Jn~`(y1kjirR>Xoj8~df3&cM*5vf`FKURdB5cnS%ni~?)5d!Ij0=hTlZ-@(ISav^ z(u?bC?>wAMN5gsSK~KNe+(+NjE$3P8Mb{wdIg^i`L$G%jBO{GTZ7YcYQe-5u>*HrH zk$W4lRBqJsFl6K_+-$fC!&UEj^POPRlW$lT*_~tHSH7hE9p>M>R(J@V z@y#c?xyu2A`1k$FwcQOducx5&;e%3nmb|;Z^aVEjTCPh%E&syY?U$ z!tgDG|K#L!Y5fR{A0FI4Z58Y5k$t-N$6Fra74KmCl%SuD$l(^4?X_3qXy=vlM|tei zYKF0@<&X)Do?&|Q<1)ilB2RII#h+aA#$>u=(t*3sa7(Lpr(F><_QjkDwrg}H;`f6% zA$%A2-E|YLLUV(+i*rxlHGi*6*=bwrU}ZNqKiW~v?rL5FnfQ8 zXLxOIaIGGf+?kPW9KkpkhLDZc1froM04BrNAiO~^G|ARaa<)Dv4FlWcKg)mSOeAa> zmq{cLX0sbg?suV+Wm>qQLJ%^N{@tare^?q5Hv(?8D_B01Zi zUA&U7mj~ys7p`UAXYGBWr$M$pxce*a=Sn}*rk}aOUsV13p2IBv-yj@^=WP2{8;Kzy z*UKFJ?%o~2UK=&PC2kqNyi4CUwk-(j8gct)pE1{U1|&$;l-;U2>?nl%P5m}4wx{t@ zFB(PznT4kh;Z7CXYHH`9#e3Grp|+U_ez;w~&)~_qxSqn6=9NYDjA?c0ytuq{Zyqkg zAMW2({%>KdlpENg+?R_6eXYi7GNjQw*zvtM>=*yu)Z--ugE;%8KoJGrCtuix1^8hx zOYU#X21Oz^ClQ+?51{%4Vk2VlVL5xA{O}kYL~PFg9|&I?M{M|iq1+Iw!HUMX_uVq> zEBd{&kld@lsJu)k$$F6~DrBE}rAqKW+9*8)ItuD`=xEreym~r!i!A8q=%hEY3F1dVCQ5o?ni&cbr{Nrk{Gv(!HX5A1lo$G(G-1hE7b z*@pR;5C~Ac=b_Ldo=Di$B%r205r_C46_iiuN>Q9Pno!0zB@;WWYM;~7W(gw&;ru~t z(GP!2g1)rrpD-chSH7y*$foMOAucGeWAw7fKw8PX`=;y`SOx$%_g=+SAbhrJoqZ*} zAZJYkw{?m&Y^{cG`TL*HuQ)FHK={b1Q=p9Q>Uy?n#i8uN@!}exJ{EDMX^WL8zlg?i z=mX(MZ)mYeYAdby=xJ&CyV_~;)G>b_7MR>zgeOta(TaWW;BwTDm&zfu^Ti|>$uTXY z)oZu`@?Z_6K@hgzv2;M0^#A}pASuXl+(fe7#MMwGv?WFY?~4*qAo{!aBS#V?IYeNE zpI`zzEE?3P&1R%V3?%DH>yct!Ewi`#kYurY5v(0kA~Ux60Fn=$e1YLGX=eIcU0i$w zB*=^z(*#0!=3@duHew5TB_^S!h_0T41Y)Gq_vnS#^#6oS^rJQvCVEJu9@>~85OS5n zUraWwof80|K1v0|pg1-Q-h;Frn4H@X+xYNjQc@H zs-La7hk4}OCbX>g)ANypV-14hVZ!6_lq+wB^0lTE;@JyC1I#Ie?SUaZiwR?E6aCRm z38@x#)Rnutjk=45KDTeS>B?48omm;oWyHq~SajeWqSRVB@j~U}vYM0%8N&MalOiH= zwMh7EO9*_HDvw-ATbrR^?T=Mvsqwyj%N0RweH;rupN~d>q>A<5%dFIrBnJGo^!wT& zT@wp|)MurMR%lQU+yE3Hc`fu#gStzCBiVDhoWOF)j2fmVG~>FTeuU`OrjkMS3-p`W z`J4~lV9d2KKdN>^3m{JJu4bpOZkyEvE}Qj?0lY0oV-PVpx|!KVj^vuoZ>A1_PYx7B zr+C4B+NF%H5LMvlv^FLr;nm@KOj4%!VM$obn<9SU+tk!P$v%}u!kAF7jSr3~ zQ-eL>pW4`9-3KR0@&}s;0}ZC{z^s}RwASsR{nbGPzkYqXKwzf^#oev1qpifq)g_y4 z5N<;bCyXF|XmKg&Q@-`BYWB#H%$x;*x=VvF=x=b3!nD+50e`TFgqZ&CmX^Zz@zrhL z6B(M7iN==)`%gmQCTRSV#<=N&jg9aAQF-GAX7kQ2-|x8wd`gn6Dbpr~>pJQx8U34c zPFE`jhd-CUfX~kCbtcX-{;Hbzm^eJHm1W{~m%(myr?&8zs^)m`ZKoU3Iy`l2ZYke4 z3(XAJX-htT$&^fvBpG>Y_-98XOzZsAjzBF(a@}JmkLKt6lHDTTj%KlV9ZWt_f5Dly z>--*i@I@3T3k56!Pkj*zzg<8A> zpILNPe^kDx;yTItUo@RHRTW!(5{MeCuDslEcP+Qi%3p26>xM{P{?51c9TV+3eZ&7Z zz)%O8fMh({DcB?I@2o{+S`7c0H?CkI&bq!uZJz@ohNIk46s!Kk67nKQoMo6a@E% zMVCPSk@Q4=&5~2ax9R@pGq}{=6#MdWxq5^SqOD!tefKn5Y-eMGCcN!NWu7qbl- zTaXaqWp5YiWe+Nf*DkKE{VC|l@e{qK2W_Ai5c5)s$qiSXY4lEuY!e{v%`PQX65p8U|Oc< zCS~#QF==r#r~jDkvZOT7G>|rdH8NFn({Vo?ny`C@5pVJysP=IF_xWh8#+VUrx`MARwuUvL*imP>+ z%5#tNJ*7IBVPniXA-d@uYLva^rIAm8gBdldjW+ac(NDW$N8a3Aj7Y0$Q~52Enj`nn zu&~?RxE-1rE99z~&y0Qdm7jE*28(1-YT8rnUFp82mv$$28bObUhBSR1_v}-BpU?)R zhz6#(IGN?M3@~|)9qBu7Pp^+-NcuR^yTt+3EUbt=zZ2R7X#V$yCltB4E{{CP?lfs> zWBy&99iDfSbILc`uS%ZLI61VNyP_s}{T{F91JQT6^P+~3xJ>%o9^9!;6u&1+Y|2glYT)}VkqHnJYFF7ZHh;&_3{}> z?=VWl6ezqw$hFEj?CteM`(K5v-&FdvsWyA;hy+9cIm=G9XMfMnGJlM>jE^D_{vV{G z1S@|}7c{!Rb#LpG+XI%Ixpbg}eIDbt&VRUK-7!E)o*tOqMuh$H!oGrp;a!=d5#;)F zbMNaqKPmY>RJQm@{fdf$@(yK64$qgGcB6m1K39NGheY^$G3O;(`sl!CJbcW+HvD=z zPCNjh4xVl~0#8|R>3i|zg=LqV_c+2lawArQS#q@oX#bozd~Zt)+-Qmpws?x#=3^rhjo#F}&HUWx+L;uvjp*o*g4LUHq% zVWmVA56ZQtTy-rRkxV#bdG^B9oP0AO%|}J*XKX490z*k0fFtlwNM7RCd^$1IuP8TH z{-|rE-(TY3EsD$(`Y)WAHV~fUE{_afCK^bn2ux`chGTt?2xi-mF);*XX`~YgsHT6J z7Fc5-Ek`6#a|P~)nnDahXB)|!8wDrTS}Gba$L*w~(<}NJ4Elto@fo?bkD~TyOS5Y#m=+i_d%OvtraqoNhZ8R9KQb&#u8CN%b zDFky&+MH^+z9w%0xd-D{g_MWO;=|mmemO#0R9a^rlXvCvJZ!`|AB*Dq=Q5R4E#?_| z3zyn8PY)EO`jfh&2lljF1;nAF1pLroOb# z$#&qeGsNlBTTzkBPP8%yDMgla`*HvoaGm24v|`c23r;Tz3`phfzh{F(96H;g+5WDLi*t5V|P<<8u5m~vx9|yAbWi?n2t00 zlp9ALpmVw-eBlY>I=P1|ND@cVP-|!K!qr?yRa^Rhb=-M0lzSfl@UaY)J!Q|XcyEM} za=q`oo^#&k zIlsT=e7?Uq&-s3z^Lx&3`2+$LJ{WUK)O7Au*F#Awwl~%_4h$iZyk8Bp;?a6s; z{b-|Vec|n;(GkK%7tIqIbM80{W@2t#7PY2mopqC|QeV~h3yDW!u{=-GPPQ%WKDrDC z_CbwjH`u~;!oNv|F7fcsmRM#NiG%6fc`rlyKN1ekdks40*mjlB3Xy_zhy8;Ae&bX( z4lrOapuOzk5$J4or0CvOi(y36nGdqb(JkTvR;E~uT#Y(st3!B8aq$K*!Hb^prfi71 zJPr3vc6|OS2Zez6O-+8DNKPu}@>#i4a754q`oK~OjgYyFIy*GgQKSQz{P}FSlCP_5 zXlkY4yDsTLENrXQQgMTG5%#P#dU5iyKy$9AJ0-0r*tIT%)RpK)^V@hOK1Z)t$A7T& z5EJv5do`Sod(th@B3Pv%D%eq$)nY~^Hjno@`wz)y8ZVc;`&Ra*EKDf*{FFubt)4#$ zitiy(;Bt?DM_rV7xLxx}_u%xKmS%&?LZS<3dy9zUX0Yd<K)^6+M}MIgE(1h%ZB$YaKiHj6zjiYf~YqCYH-bq_eN_fO~??1KiLl#3VZMh zc*uVtWl4s2++7R`>rj3=`u8>6sbP0yV(rK#SK!3t^5zioZNk+B<2v+PUwwO+Zo7Z; z*@dX!1l7#(S>w=$pG%!1)UrfVQ357$zG#(Hl&wVrB{G6wnR>ob1m^Mx`?9(Wi?43n z&H$^%&q7O%q3@R76;I2qs`o>M%C*9Cy)+hByTy$@f>t@gj8ELsHoqYt7r!=h+W!po z@_TCeAO`C<n_Eo`V?R8E@XqN& zWhZN2LCe`js27mA9f&8|MNS$O4%g`g#OI5&l&Hatpwps$5K?#lvMh4!JT|!7ue*xo zSGq=`@i`S=v3@XTNWBdXvG`6M3ldvXZ~J>I*do!BtyzcUVkCvwdav{JAW09ls!Jf* zT{lU@U}wM?xk8=|uI>W_oUjBz;f_e@=#zEwy$iK@hFY(*qSODf`bj;b2FGn}I!i`f zkc{fJE!h51FkKKgvyd2589j|(X?&_D+L42q8rpk5e5H=Z53oRf8@2NmAYdZV8yKfm&g~c zk)FcYn0yapO6Yub51f)z|Gj+)>w*1~Sl~XvDct1WN1WU~g(+Fd+=0Ji)0nbLE{m8r zCri%2AcNMm=rn^Z>q8-m*4;V1wm2D~7M|Gg<9)ArZ{v@N=`Us6jkBeqGT5PDJQqq3 zg^QO_sX+KFBqO|e^h1@i!b<-*uyp(pQQlY7YGnI(<<$B>dspqs!S{uYWBR65d?q&L z!A6h-{h%>SbxNX~ldY*6yV}iG(LuARJFQ%yeBOMsGWhHG7J(Fg2WeipBJ&4Edg;+D zl*8UE6!lpbd;ki9Qo!rrWAL#k8&oy~&1k>Ao?tLl74MKR7HQBl9f!l2DriP^6B(0u%R4w66bjWiZT_0}!gne{!oZBd#=~{dxis5xa34 zGBveYI9dE+W4WaNJ#dnQ5 z&;a+%FipqNJ;Rtg*#F;vi#3@hPHN9+01a?e1k+e3?wQj-1DvH`nnl$;qX{&?4}Ye4 ztFvdcfCe}|V4CqWdqx{*fR(~DY!?5m8z2G}1ryorqTLb!B49Bv5qcNxmIe?3lbVUv zchPPt0ueA{naF`rjeGg)XaoLrI2MS9aaS=?HkI*{5XjlV$;r&#+1<*~(acoYOiR^R I2LjRhH+$PIr~m)} literal 0 HcmV?d00001 diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/make_commando_proms.bat b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/make_commando_proms.bat new file mode 100644 index 00000000..c38ac8c3 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/make_commando_proms.bat @@ -0,0 +1,15 @@ +copy /B csega1 + csega2 + csega3 + csega4 + csega5 JUNGLER.ROM +make_vhdl_prom COMMANDO.ROM cmd_prg_rom.vhd + +copy /B csega7 + csega6 gfx1.bin +make_vhdl_prom gfx1.bin cmd_chr_rom.vhd + +make_vhdl_prom gg3.bpr cmd_dot_rom.vhd + +make_vhdl_prom csega8 cmd_snd_rom.vhd + + + +make_vhdl_prom gg1.bpr cmd_pal_rom.vhd +make_vhdl_prom gg2.bpr cmd_col_rom.vhd + diff --git a/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/make_vhdl_prom.exe b/Arcade_MiST/Namco Rally X Hardware/Comando_MiST/rtl/roms/make_vhdl_prom.exe new file mode 100644 index 0000000000000000000000000000000000000000..1e5618bf9417eaeb90556e3021a78e9860a815e8 GIT binary patch literal 119861 zcmeFa34D~*^*4T>XXcqD3p0TP!#R;I3im94{WDd))P*nEKjw;3-)UlQLkgOB&vHgLsaCW=mlXa{` zB=P6lm;e@v{KDCr72jJL2<`Y#zVq?1{Yk!c9UVkEOl{aj(9wTgqPA~#laeRfnks`n z77K^+LSEnO;;I^=ZlJFn_)xxu_}KmmMPc9UShLJGMD(5b5Z`h_l7EHBcMg}ipW^%Q zq578KWBWt9ET2=bSW@2Gj-Vf(ui+zwOS1eb6#nIN<`qcz!BGg>(Kwk1-;yNjOY+TM zAn_-%5cGm?G{Pemiv%R!f|Dier}o$hzBGg*sL_*usPFPQC+ADToEq}F!Xz}UXelia|q(bTM{vTLqWVGH!yJ9BqINk@a{c}cH89T z74$V;w(Qz>1_#T}-fO%84jNW_C9i^ZTeK$`imi_u7XwZhPvd)AUo7+xP1u2D$R)J* z(LwwTya^SP$oenDhfto)GWazG31j=^D2#vL8ovPcVhLk79{;vBm#iXp*FN^sSHO7J8l7z;{oQO)Wz z*Hnitd%G7gC5Z{IwNko=(t(9~YH|a?ZTmyBhZ4)&ml5@l7bM@-g-H6)0H*ffOQHB-nQAvuAx-BS z1@9+}?*r*RqWQK?24ljw9q6_`-_|g&y~eLwRF5T$D^0f1h}iaiX9|_zN@FvLN*F(! zB_+nvf(3mKgFzHLIoLn&5&8g)vL_XpXI;<*ByLPcB?s<+h8svffnu{ZE+hJ*gINbJ z1%R4(k)-aQXrTUqhrv>k$l8rk1h+jOYe7zTLQKJvp@cY;w)Oc~{?;dBflzm!=6k^3 z^Yoff`le&x8LUS_@yF5WgQ3KNClGnb=>_{6lk+E$_WHmN zz*N#xtCiQkRTh79;1-#tc_ik-qGw6%oxb&G&J;tB&pU4zryMz=v zpF#a zgeDCQkZo_EQy#)36a%l0qu3Z?WyGHmLG!66>!Ac>_oUx}VBlw9+H0H+CK?b2_kk%C z|K(to_Yz=p2?0j`*Vkmjdop<$-?6+iU#jLgs40V{~BG z$CyaHa(3gJ;;%zI{SA~;{4KWl)uH(B!BZJ8_lM%Evj@_^(0#Grff1AlW``2~P>$^<-^f{*4q9 z4<3Nf10v=|(gRN@2}Qf8LmsBuk+9Xo$b!!R91p%mXwfcWu(;+BSC0``Ld>fNO5?vQ z+BJe0sK-dm>tiH?&(1K<&hRs0uqy6Bo1P$fgAlflB)oPE32wWDFDZui7u(8!Ig%{H z*IGS#SU@Kq&s$Lo-1i2r7ZQ>;i|>XFM1V4Na3F^EiU!!uLRM zzwd#4XvmAW5?s)!;OP#2tRZ86r<+R@>Iv@0I5{lG36;%i6c^Y-@_|zY9gp_AeG#=1 z_rQ<>B}f7G7$fZ^rnRmm>jK4a#4ce-50ol~emlbu33-ZPkDXyiE4vj#pPhjo!d4mn z04;(-4#|QxKo-N}is2!%9>lb1p&Zhk2KbSRO2kX8}T(D>;-f~N`=p|On* zc~JC$pJzd0B7Gk*+(!(F^gV#pLUlU`Wj!Uid2)RfioZhSyn*XwnzGzLD875(3Yn-3 zJaOZ4lF|u+lnufbA~X|w{AIL!{yDoLWH9Sgszw|z6O+%Yft4f^!c{U0;^ejRUg%6FJd>2CE9-9*54wr?B5Pd zw*)%+U_U6TLOUhb!JiXB7V&mP_&x~ceBt$Z_uGMiGtdg?;Dpg$Pj%nlISRcQu$E7% zd{|K*#Ny|@`LviR1|xOlz!gvirSU%5`sHAG0vdEVBFo}^56RVh&w?K}&|Yim+j513 zRr;^7<`2a`D4p@z4+8)T1`nM~{fmS>;C#aQiMJ%4`(dIoExuYfD)A(BeiG{5tA%E~ z91nWptDT|l$Fb-g48$gc;{O=P!upn0`+cEpgPkYJavVGrjo15d0Oc#inC(gb;W}EP ze<#NJ;owBX$3HyuTiPI6^HJ)HMWI9n=3qjPKYH1l;0j#!kK*E$0pHfEAxsYCjVpN| z7NGvVEB{Dz8jP_^)j*tMwlC)Y803qx`L^cM;KqE!{_&jip%LVGmNVikxd1h1#E}f} z$)^VyMo9NOq-H|@E))hcjneb@et)?WtJV!5tMOsykn(B##}4|g#QacWKlYj&_r7g) zNMw%vZB~{~gHM)rIil6LACj#a{I|%#@7p#($&jO~$dd6LQ^qIe&>I{gqu~96ek7FT zljHrTJl>xJ|G~wGO3shIgK2hLK5^6}_$78;+uoNI_HF$mQp$O7Ax46n2fqfTu~+fS z`Tb4sOYVaYBZ~F4ikIcT%!=QRc-CQ1$7|7t@2NhFofwMOKx-y$$n8QM-}PnGGAhNg6`zY8&CsA17AY&q1*VxV;d3Z97J z@%49t5F3iWS{gq*@MoX{hw;@b%{$5VD_U)}@LFghndeJo@h3V*Q-7$|DLOB?UPz=b zslzaO(s%VgkSlsR2WYV1t>pZL?pge+Xl7ZW&>u_`ddjrNfcq}*276KW9u1q4?4rfb zbiRn0JuneZ6igm$pnY3^2nKABD|&JpN*{g8Q6B$&nPb-DwWN)L{-V7>M57L`Aw^A=KnmC<$75 zU^ylM3NZ=^6RV+r)2~Iuszgb^GccXzhmueG&7vAI@pQjkTauXiT9`KGZ^cqWJ&^-w z?xJ(g+r8I#3{@~iDH1rpm zu_uJ#6Tr&kN|0dR!7~8r(S6C+@SW<9;bP7kNWe~a!*GRP|jQhb>)>Dq%=;~deMEQ=Agfn~ar9*eaB6M&LRpa^2sc4cn0n7d@Nu-k9 zW7||@RFWum2Jv9omJK9P?ZIl+w+&}ZXw%(kvfi7h4||q<@ao`T=})OK!ALET7=^T+ zBHsgjA?-snLiZ6^TT)_cH%;z7;_+?mr)KX-_ajsA^oRBai6RE(z|hcr1kb_Cfnj8I zzFIotmt_ubS-czrcXfZ!F1bA23^p!8^tyvPQHB!VgIduCeWDACsVSwG?W2N}&gd`K z_LaqhoK&YAmLch(-7@M?Dij3A4s5DLsXD)>a*)GlG_ifHBq4=jJr{en+PL>i!bn16tAheO<9TD1Q)=?1%0`rD9K^LcVRJ#}4M>E997veV%NFTW3*E6{CfU zJ&8)szzm2)>pTqdzy!dy)h_A3#>*C$pB;1m4a?OMB&z^okOE#>n zH}skDMTmd2pbt${m$)fH7?F&66-t5zR(z?oe%J$_o_9jAU*pikm z?%(8bgrJ$8il#yX<&`bo*ZEdK-`{qtnHVU5RrR?6H<1Zo$M;~R%lBX?69aY$vhMy942b7?vN21q3-x??cithNn(ye>ywKv0 zV$)S$hvM&&-fKlhSbhCgZ4PM7XxiJTAhcm%njk%asr)nwR7VAR2BQN7LPqIlP)Xvi zhGsk^`47HHT1KvZ1GM(vit$0!c^ey>^r@7#7Yqf@BlW0Iy-`7_d$Q6H_#Uj$U2*Kz zurajd_t%$@=3FyPB`o9PWE$gTM1-_`s6KT-Vdl0cV{_5|eccDq{566aAr2MvSRU+u z?=PPofc19U{+KV+eF$^^F*L_xodX5Whh&Z@>X7v$m$#GhJ^=MX%&-VME9TayFT=8bT#(IUpaI&%nXBB zD>ujj;VH8iMe}V_3m#H~i%+C|Lzv>@#&|>?454^D>-Ya|$o5^@Cs4hg(54m^RMc<+ z>;?(rTSVx=S^`UmP(15KLeZ(elY?~l{sRk4!vU)x_WkkQv6&cbBhg8Jbz!*^e|a$T z33Ni|`zYBp)J(Fu55^9w^)yCK&w{<+Jmi-8C%(IOSQ~(fRJ7`xC|mYiX{= zT%@21@tj=)oRsRJtyCpz^;8&2OqfHZ+%@-(H)h>>5}>_!3WE_=k=?NqLLdAp6rV7G zIJ);(%TCx&u&@}+%20XHsY0OJzt**o3O%Fb5Bom!ZW5vu-2uw!YH%qrR>hQQ0~v*q8{x#JJ$=h}vuX?HnPzPSLm5_%k4C zY*gc2favF^u_q73gM9$|6}WFOYl>{6^h-e)%vu0sFzd<)7R4k)j@As&1`az&0+xz# z<9k$u9tkc7cyKeCQjSn_{-f#z=aQV0AqQ12143GC9#%BZNYa932znE#bcFW!;ENcX zBSPE$3|)uEUMPN$M)5g*G7Dg>Vw6&np7htL4m{uGhSt(I3F8jL73`1yA`~ZCsiszf zVt6IOvNER3?~NsmzwpLL@Qg8sp*y@)*L0igal$bj7|6#zuK94==4O!;#Xrc zV5Y;e4b^?J^Djv9{@IkI21%0QwvsrM@C<(_Ug;nB64o!^d`5Df2+l(9)6CX8A@FavaAN~gyF?=`-FZ~7a| z+E5RPk6}GvERp=N=~B{OV>(bd!szKo@nco|O#^?0IzMy`WaWV}m~{zBcxqrjQLkrh z*4ukVWoQ}Q&!HKb9UT+8?4ZQDy&^PALNa#KA44;6#^)7l&l;-!=m~3*I*n4^B zUi18E*cg}O9{!E-7P{v*fL{6i8wXzL`$n|j<=?*2_sW~EP52ce-Z;?pRxsxK%`30` z<2UE#9)8#72j}kJy!^^vZRkbM{^k|@OUBDG4^CZ(di3@VPCb>wH5`sW9}xW$#z!-5 z#;+L0e+A=DaCj4k&vCes!$uBYHS1 z%JQCId==x5FmB5IOP$K+bq+TU3%||yaK078_*OAKdRTZW<7+rP|2W|#On*-V(M^tFBc5u@A`_ucXX>z=X7RZ zFB{R!hou?+EI*q}{6FFU-4+OUL}KBl){S+|O%37pI^5fg#3Iq~hPu{<=15eC>MgCY zy3K(lfvFvV#-`>7cvaZe8A}n-bpp3Mr^fU%?Cgk0cy>puA>7=yzNtQ3P_S_R?7HUWnZz@@wX-D>1r_l`T$++1BCWBe*cQsU z36k5}qOm|;ityGqUl>4vP>_HnjIxk_-nxc{=gy|x6}8qLyrV_VvB@f9@O zh^>o8>$c?O2as`KYQqd-vr2x9ypWN%qiKC>T{8&?Qwf(yQA?Hu@}(PQC?KKYDO}eird*-7o`r*t1exMIQdtxF%oTTZrc=y*0rvWn8_>F1gln* zRh&6PRMtgfO=zg*wvGF8{Z zQOCvF+5#Od7>?9+bdfpIj!0A|(h$g7y{g14#p>1zTQRUy@npHfEp=$}Xf$tzoI0ra z)Q-HV>t_b0uAdPIR3}tB+yvb)QkbQM74JjItpDMnA#rLP}dP?Z3{HD)UA)q>cFsUYHJmNz?!CLth289 zjLrzABPB-J8_@@t4C}VUA{d>q0Cl&LqFP-bomr>$j!0)i8>-&iR$oUlX{g8A>f4$F z=$j5AOl_F0O7rRI)-_>{HC+_3^S6i&u~F2EsDR=S&>Q&opTGZ$Er7MGh7aB8_9I-2 zj}ve$!b>x7{TOf;!h5l)%mlm>;Vf69X*93ekkm zmjSmU?7-(MfV&W0h0j+3_aeLjpI*Q_5Ppkrz&jD1Jx+*Q0M{an;j;s97sBibLfj2F zfG`Jk@|}S55iSnkJP&Xo!b|aahWHVF6`vOX_abbbEX2!z+Yxr)GeA5D-^Ax_z=si@ zorCMyfNK#pOhY?-5&Q^m!zTcE2g1Ynp8}Y|4tz=g zcOm=^K4pM+BK#Pi8sdSbx*DHaz`Y31IuUsSu0>dn&t|~w2=Bt@%Yb(x^uzG56)=S} z@#zJekMIaSHvkqhh4=`cZxIZOYzsd318zt74nBJTA4d4q*=QfYy$GknuKgPE|L5<2 zd<$r(q2|owa4MPPOG%#<8lbsay?(GRWfB+s66yBbYWC!`Bs@sJjEqa<|a#~k&JaL zgUWaZrzgIsjgMs7dDGk??G8`AyVliiR66_ge#ED{x1~GMf8@>g)VkYUeX^`(dE8Fn zp6kfhYqfS+wz_Z z7%p=-Zsx)Ak=1ekPU%fXwci5$bRG2kwMkm$t$6?G`Xp|L%5G3t1BYMcu$RMcbNEvZ zpW*NThwpOeyiv)S$l+`bzrf)-4x=1?mBTwYe1OA#4&UNX#|0$%OW|-Lhch`0ada7{8puUJiF~_+1Vk=I|*FU*qsFhaYn2xmigb$>Deo^Ek}sa0!Pc9F}pohQsqY zY~-+=!_6FC&f!%YUdQ2f4)5UbUJmc)@DUF8ariukuW|SX4i9tqA%|vr{bwAgmiYhs zICx2vM4DkfD8?=hJFwBYjz2M=VI2N~{A3FK=t;Y>tGa{h~;S)kGuVyipP&N|fpt_KltGrLB!^ zMItUKTRLKqmKyA^iaJ(clSGiXlVWO`>MtyA!|qFn5A@Pj)D6axi;k*gsiQ1XxA7>l zsBo0E)isnUd&rr%V&#xqu}bV~+oCPBPnE)9Z281d6>CO0S9G?@&09^~y5@)&Bx-S8 zJ6Rcu+t84BPt@fEt*ou>!p?S+8BHABB1AgH@Ro0N>!zkwwA0s|)sfihR%O#^2yU*A zw9`HgwM4Iodz{tHkx09E&{-3SwluZY#Uf^Bh)0|?%^hfhHFeFM5%IM1xI)B1CufSZ zWDI$t3YpPZf%xs_AFR-UHP^SbZj|v@B?Bj8R$Y60n2aw%tWy-2p3u&6H;&#H;kx>k zhUQkW1yD-|Y$TMeNQiK~g8nGNjr5i>mgAZfjYew0E1R%d)n6zU>R~SF>w37eRnorg zs9Oi)l(^r4K@W-$KXKGY==GgP97<-Nqp=V`cJ%vrCyNtv zoyvA3#0qCeEZU6BL@7b7^)2n9k|6xYuFSd7ECQ)7S_k}J_?#ZBS`{ptH+MF=oU+YC zp8sy2mX3|}(U@66D&_zDKfk~5n3b$$de^XX0*jgH{bP=u-s1ZY@Nd}yMLSi$m2h}& zm%sg;nV%qkIxI|z z-_#>1pUVGKfyv*?`X%#I`4^sS^6zB+J)g?|O{@&LJmU%_r+fkA7->}br>-&i3j>OO zCT-x4@u&FzagNE~KDkhGIgY_gB*ouzp2^?E{BM1F`(I%4w@)jSk`Epy10{dbmrefK z6BYk)*tt9hEdF-p|EbL7=r1LI;^n6N{F9XYr$4oQ=EK6E+F#64{L}TLWfMiok8L;k z+vh0$3y;nIAL?gpffsYF`LC^9wK`B7m_K{r?72dlJ$sJzAG-o|2sI1qqB;DDY>wax z$DDPYP0bDJyJ1d}aqjH=*##WAdC|h~!ufQFHA^zgn>z>VR~s`V!h)?j_MJ=>QayCd zRllJwDs+z<`-Am3Cy!vOEp?t&1W>1Yp3`y)Cn)E9Zb56!IS1cb-q^pH0Q zZ@9Q(RZVbhjp%pkUvXW8^0_JtLT%U`>v5My<^;-IMY)P89#`c&MM*Hl@2Z@yC|_kt zwySc1qVzB&;Hq4xC|5Hj&&69_ZiZ`Is)6!d<(rE;Ffw|XFyB=jSznAAUhBG1HsK;7 zlz?y@6P6Gm2*UMDIE4r+K)8VkrxIZ$2sbjJkOnkI2>n(@D}l}x`gTUw0-Y!H+Ze3{x=`p}V{`-1lZF0uM%!Igb(@9$4MsP+s_KE> zE>TBLm*%Q!0KS9quK-^M{F{vT0`F)S`W=klLh-=wWPAt3Hwpb)jNc8s0r*{v?*zU` z=-*~^7tqB*{|=*lKnqaqyBXg{IO=^5EiMBNheIKXZ;dPZn z)^)D8BA(=kyS*+lA1%k-g8B_LZ8FQJIBussZUydP$k?Yjc9)8^rY|RchNJt2MO*2g zWrlrTk$Pt7s^t|GWx^RD4U@Y3teT*3ezA<;Gf7D}qol4h?xJDNWr_dX98iYFWjqmEp>oDq$4-oTRQ!66W4zWwUU;Ft$sy za!o~P35Ek{snp_7QI*htOzKby68cYkD2>yTi|LO-R70-*#3_V?idL1B1%>`LC3H|G z^bz_=8fEK{*(%CRshypkE08QrlSjqefKd-(PZ`pY2jghR3GUvvp@d&6tX%fr=0Yl7jTs$kK)xk#jUxE{gUMk+20!!z5W z4S2Jj6^L-b@)+yvP}EMQ>aLo)^@_C7MIEc>I9*k^XcFBRX~4AF#6-g-Eu9tZ_3~-4 znUlMi+z5ja9*J96HR0JncF}6sWNF3-{UYX1vt-W|`j?nE!c~HMMingM%Phk$sYwwR zGk2yX0<-!OCXP0h@}-iT`On|n==^d^)lIFc_|@S5$|{pe`exku+%C3a40!`$Psc=3h)aEF8nTOW*1`6(UCM(DWa< zPKO?GgaA{cY=VneUJ%Immr{} zb}<3^5d_rbAtpc}f&dNpFcY8wLBP}DznB2c2LhfCKV?F%BtS?1j0rm=0b2SIChU|1 z($ha@N}r;jtbI)BR}>WXQKlSF6qNQcrW{rj6n8gMx*Sv((%5^L0>5#xGe}L##@FBp zPuG7Sm2=jL=2&&zM$GG-F6s^77yyd$LrEF!@}dK!gs+M z`H0CdLO70ES?P zd{@+6wRulD6U@7b(?hj(aE)}4F40O8*V5}G({g+p;nMP=mBBDvfQCcC zB3zskg?g_4x9Mns2=2<^KB&;A`qk2nNcHQQ@%*306rCu*r!(#(Jlc#jc}#Ihj=JcE z2Gnc@6Fnf(iH0nAcbg{XC#nR*ga(?IQjE}F^s2*Q!&EXMu7>pMDIgg%=oBSE1> z${fZsC5O=S86OS2xv@?bvw&&YptWsmZ4>%jri=vzcki(Fm#v}aj3<^zOB0?N^O+}? zNm!|4>CePzDj{a>LjSvHM?EJG6lB;M!4vFcf4+QTogy-*QHeoLOH5PQ$Ril{3dd1B zqc8HWN1r(=j}@~3DV-jQH~Vx&X<5+h)J*+)|7agNwY&~@V_PwHZ{Xqz-i=f=^06SQ zd?Ux<`G?asOq>YDHx4QEoBV2-?{x8Kt!b;?(z33tSsjV#H*>rvDO5&7<}DnR=Bmaa zT}5MsJnO1!Hud_goTuMajBR0EJ*EOCUQ<1iZs(|xW}Db+rr+jYimIEHE-9)h3YU~( zKUY&xbrxK^KI^}T>dmKM)@JNEE)M21iX-%2m^Cx=7$!*X_vb^7nN5Y*igV)Q-9CD z8+=aB&Bq@xSkWKW-5ERarX1#^95WuJ0dj;IGhVq!(sOvsq%g{3CN+a+q8c-4jPjUC zXOzdx2u69#_!!Mpqr;z}7S-8mbYyTWkB*Uy^5_`Fh2+tZ$taJGEJk^BjAoQa#|ez` z=*VW2N5>e>h)2g*MtO9MW0Xh7ct&}2OkhzwIwms8qhk_RkVi*=(MmNsCNsKLjgBdd z)~eBw!x?Q*qa&BmW;HsdX3(V9bJ|UElPm-T5GPlD$-qeU_N6{EoEAvP~RkMXQl zkK<}^cr<-k#yPOGLs#ML1G;b^^i#Pc!bP_tOf7m^25EWPrVQ7wg>tOvIoVcGhUB3a zWo$wYSUI6AW?_>YLa&r1Fk@=Us>8)aWo65YiciNTGV{kW?L+t;q0u#DAFZ-{G(;r? zxxWT=j7AT?-%~uT=fv1h>8k3QqE*Gga9B8<{i#{Fbl=&EivbP7*)O-AIka~*xj-Bb z7N>_qI4Wx@D#K;LHNi65vIvg`tQm#dX;3j7WuMAq7*in52%`*DHLEL2SFNZh5*ysx zT}MWvvFq0f_iem460YWUbE_lVUvn)-J!sw6++GstxG>h%F5F*dq94SXrWkh1?r$(D z+tq+qcHOtLumI4rgnI|0xfCm(Lhf%eDUUc5=?*5%BrbU)g`STc!hI)4RLRG=))nzqe3?XDj8cRTR(TZSERaMbhVjQ8x3La1J z>gr%sNpMB!s$hwjKm=tanyA1tsm_xKW`lSx!PtgL*;5HwZDP|1qm@`qX?ale$);ak zRDnUpJ7L|*~7^$ejHbd;TMFmU370bVXb(+{?@g!-FOB%^Dxt@@e;uT`A0?Mjk z2-_!NymeF!D?UsSR*_q+=bB(q?C~CE+7+~ zp6lMhARULDfV|1%x!%%oc)w2Gd~2e;gy)7Az&7b5tVeLzQH<9uCWLXRiSApeJ8lh< zV&OOj!YEf4vP=eD1Sq}db_bF>!Wh1=6?%WfE+aC#_9)TNa6&2-}{(oo#if|n&D*u3Lb-TH{Nr|va0Y53fM6jPwGV|1TR zo~-m5k`~+ywTcutxiIM2HH9QaV1UMUPf>F4irGe-W5{Uq%eNtF8nF&7!BJV?$XWlL zvaZ49Icm=vRj%s(9x#$4riW=)yna&{IZ-We1&*!+hH(xQmUo{P<%dzA@CMjEVJOh< z)iiC%cr;#PX=O-g-_^bV1P|HoK^TEP0#H)oncmRZ-i*tiu}HYR9rw(TPlwRDA>oIJ zol;j%2#v-mbsGsJYEIq8W}$75LN_vEUKf z*A=?<#Ae#hYTwYvj;x(^V)8ky-L8>YS-&ccBCYG*`m%Hluccrp4D0Q_x68 zGFUgXH;MEpky2mRB?C|=IVlrK)(ZN z7Y>iik0a(a#NhAb84&za7T5=Z_Pbe=gjhhYlnsJqK^p)n)1q?#%%)dS@~;DQGU|nw z%kBes>c~QZMTkR9XlqHt?-ADpwnZ-j5Q}LVUcxNjG+9%$Ua&44PS2l-S@12H#r#Tu zQ%4n24&rtWwG*`kt)TA*%fjK2`CAb)27@@i7r+GsYzJ^PfCXCsyaZrjB}?k!F#j&Z zOoHWG{y9CX&_qi#EXvAp@zy?KZk8ivCy$h0a9Dzrs{-gbQrgaY>7q}ckSta zEYtUMI`eRUADFMU(*K0gXTmNlmZEh;N*UprwiK{%4NO+Z73dUC3&-Su=4oZ*eheee zMp7h5(@bn%A{7DTDvJ5$!2luC=<&8Rof6*hk)$|1+GM<(xAa>`qD|HD3_+4&B++K7 zJeToBU~P`dDPu35mM0_4sbX0;ytye{C$vQ~foqz=FA~~fg=f$rah=6lPpnJMv{>uI zU|p*4rSnlu?bK^zr2l3-xRx%}Kq>sDq&Ph!YUx}mWRW5*rOQWJF;~Btk_Tx^gW~s7 z%nC!+Z|S!PSxK8CO`D4c0(5UFCGt9)U4=-6X$>mWa0RuO*Wod#xNHq&QK_hYlL}th z-PKA)u1TjZmk~88B0Cu&AK&uny;{YMH{@3Pr9@v@>ZL<8=f$ zYH26cXzdDB*FO=mff8%lX>=VzJ5>%gU@xO?+G!^CV`{rX6N4obEy>u?15P{1HsG|m zO8nCQjR7}gtQ}*J89q~dmkr0Kp!Q^%HnpE4U z@;Yu|>X4o(;?+exEgXdwp=qO`7k4PRR&;y2VrZlh4h9c1Ed4xsRy=|#=%O5b@A)h@ zo5H+k{ygtCnU^HZ@F^WdGcyvJ`(YFn_0Q*F?ofA;u)(1kT>M#Uun8Bk>g%En|H>MS zLZS39cJQ2+&;mbGl_(rmiO2Bx(Z%;ZYbEe=ULBq7|B5Pf@D0&(sS5u`7tC~Z!R)_% zq3nP65}6@yO$f&cWQj23oe@XV5j3}+=XTD$ ziv+5a#$A-s;JX~g+l1M!ZW!w7hJL*38ZOU2kie}S(}-uBlz9S%zsoZL-yUrqzP;ZA zyZ2oBB1ojLagvOG))5Q#Yk9`3Obxx3Di@=C#8S~%Rkul=Mi{d*_aQmXPE&)e4M#`M z;b>2)6<6BY5ZNq@e2(!aV~TM+xEu$t9k?*VvDvBWMCt5Ew2katc#k)e3XK!iRI-)X z&ytLJ9F;5hd~JATjQN>V_hZEhW2LO8p?3J%gufw|H0-4twzP&ZF?i>2u2u=U_6@X1 z`d{&-olDNT)A6D*Kq^@Jeo2i29MLXcn$pfE?h)<%<(lv271IPW>K-9_4vvp3Hh9I4TsvfS;I-ADTNyb-_exnGyo@%uoFo1 z36v53veAsO=4fQSs_2c{5fIy1rl}gRQG5!88>8CnMrtArCa*tGII|cP)3mW46EcUa z96cA4$&fz+u9`8ja+59cyo9?YcFjmU0w{f6eemUjYdmUlu;%R9kCEbl~M%ew-V<(**D@=ma6YoAI;((+E2 z&GJqtTiyw@Ebj_2E$_*wq?LV-?6zuLl}OSam$adlcSK}#+K2Jr}%L?jS92TKu|9*-%DR#-g|sMHfdq@H95 z^+X}5CmBLLQAp~ELZzMvQtC<4EcHYft0&1K)e}LMdLqP9PlQ-~>PZqvJt+#QCxVoEBFIutgh=&7fK5FSYN{uKho~nauzFIUQcnb%>WN@W zJrR;rPlVaj6QQi02(;9bLQM6Pj7qAaJ+j+|t0z-l@?elCQawq4)f2(TP){Pd2%>WL7$dLrDWo@}V4o`_~wPcALofUBwvIDz4-p4upFAykz)BX8gt38hqq zA?qgI2D~#Rv{A%{r7lE7T8D}lBSq{OHmM=vDiR@6kKxoFrBf_N4BDhWD>c_{E~kD9 zTo?4hz-L-cZH{e@$sdsa9N#?{KzCC$>rgs~=;EK(B_WNBhTEKN*^ zrHKh4O)NP`6Dt6kSOL()k_DPr5uk}Bfi$tAkR~QbX<~vbO-zW?#01zhF`=d=CU}S@ zCIV|>1u9KUu&Id&wlpyzNli?cO%oH!nwUUK6D!2j#K|bTCN_DJw8v#v4qYe`m(;`( zU` zG1_Ep4XEbyJ)5U*C#)7f#OO^?wui~YGd&G9FO^I>{1sXbv9u@2@X;%@Tq1slh&YYG zYf?g+N~vE51p}O>gjd74Jh{8k7RfnP%bA+GV>-@84kt5TL}}=E6GhroKw36splNAi zC>W!VbXkkB(1#-^Gm$orBF9e$LBneTDF}VG#9qhUd}83UN%1;%GIdCDOnp+b^Kn@C znI03kav{%vot7StU)D<)Sv`e8k7)AgA!tCP(nz9N)FPX3V;Sx05qs% zfd*9sXi!NY4XP-lK?zbClpsrk5+XGy0X7XvsHs5-9-={sz#3G6N`n$?YEXhL4N6E- zgA!)bpoFppCD78K3NbZkGAgMp_sDJ=zLquRCD*b*Pw*kG^h==G$_&R8q_GFap?H^ate;Rn+D3zyJ>a;E|loPMd=;4(`a^w z!*myGBVOxK*I_86ODpLc5sRJlF4jSC*Lf^%y38W95qB!)K4$iM?g1esDI9*S=s=wA zy>-w9qtq8vf?VFmdp?4eOtNpRuWyD|FN-~m*#pcj9v?|M@Oz(C2i8Ypri-=$Qw=&g@P-TdS?JOpLeyt)+VC$nMmjz8MvI}5xyJP&727E-k8az2Zl0p# zm?1;Q^Tv8Dub3S(+)U4+99x9tm_fxjy*Htw;h2GP!IkZ#1nXU(gXmEI%bHXe4eCZhL5Dn~0mW;tx4INs2^0^p?ToGk zI*%MPsMuPd(lLWVHvpB685G*?VaE&#-Rxn<41|(n1`j)CQ21AXE5{59?**gTi+LmyQ_}x(ldu%%IRdpvp0W!uJu5df&s+`w2(I z?`8aD!cp`47(YNbUMBf2;{$|C#|%o|Vc^O!gTjw!X%FKlj~p|2j&{uOwu-`TO1^<^ z`Cr(_(sy`0!yPjyv3Gkt$8gM`;&$5OEXN8@v&da4)|$SSV+NJDZ&6U?*tYud^`(xPnFvfz@b1A;lEgua;`?TW_m9JcQ z7;{O3syuM;ZETmQ>63vJRJwAa@DmN$4{@{bDXVk zQd0?!>Hi={;&%TBVNgfLyj4HM|G_NKl}@nxKUk)y4l#nd zjCg!BK->zaSc&_@2x_--6F;{9gRet`e+T(LxEIsaW4___V~NreFX{ilR?2+xe?Ym* z(vdR&0sjYz02KuS+V(*vKr4ZOmfFPxs38!bXC7h#^bQEp|ACSLMFWELf1n6ZFd#_( z2a3=u3DW<8BJ7X^>Hk0xc1nWsf1oIRih{ECnI%ya6!uZGD2js8KE{;8ih|JGma!GBqPj3cI#*zHG zwtNLnzgE&vMD^Z#HD2Q(pIz*)AW!ef*bZBYXBE6@3H|DfnGj6#qr9mDjtH*Hpp0qZ zH~baw>!nydC(Wbo51IFs^cy$=D==lK$HR*6GU+#RT&69~`URd2EPOZ~Yc(@1UD?O4 zXyJA};&0~o@x0c=H7R@YTQZa$3s})ZQs2taQ#`{jHtE}0FfKN+e}G}_q~DgY3(e&8 zP{TVtdjMx?^xnw}fLzl+M9NQjrPAdz9s%d4zf$Qk3=%imvRHUhcH)K96R>?`iv@wo zVnGmDEMy3a1%+g>kRdD<6q3b)LS?ZaNLef-&9Yb!#uf|7A}tmKSr!XIEQzu}}n9EF^&}7K%a^3xbrzf}jw#*YdSILZrol0Gq{vP}5>T z@DPgy5!hm(KxMHY*tA#>Y*{P_Nm?ujvso+%Ws3!Ymc>FLro|!|Ww%(EJW1N)vMYz$ ze2Gh1EF{1d3xbbfu^_VD=BwD)VnK*yv5=gm#exvK#e#5~#lnVK77L=;Ef(qFaC;bj zxWbLNt0&xZ=(<=o#ss{5m7pnCRKS)w=0ZPim$7e{qSgkrmDI+nRgM?~AL{stJgJnl zaf+yok+0rXG%CeSyHZ@@8?PeuF)PT$pSf~?L|(^e6BL7EjCJMFS{Yk!N=>A#BUW5k z_}WUTP1=JAH5S+9l-asE7z#&dJ!P5|aLG`k&9rF|&7M#Q3{MFdjEgdGLyVNUb}ns) zx8vQ4@j;kd)-^YE;FU62TA`gs3)%M(H;xp&c0N7fs*vgUlBSOKx)|O8jPfQE*AH%)hAu|F6VD>Fo?<@%YO4a-ioy}RekXt0P%Dtd4{)(_ zCKiGjR(050o=byp!VhzTIgzZbyvQ9#<^&O~Sn=*e(|@Ng;p z{+jgLqb>X%TDAypbWkDIw|4T2b|`+b5&Q6J9Bwyq?xtPkDkLgJNye*J^C(3F`4!Uo zh}t#Uto375>pZ-@VKvKc5_c~ssvY)F*{{sTm(xR!*b%f=2t$T^L{1WuA}yWab|rgO z1?XN!AJ=mPjnb=zv2IqZvoDgYg_jpXvJiobsm*sCK_h6|WE+CF30RtV5arTE7|-(0 zWXzW@5q!?RMolNaW=LxX(~9-)W47YcBh7g#TF&Vy!MCBg3J}mqi~BpW)AwxY42){2H`_7#nhd~At4{oF8Ay-WVUihkZ(P&L>Bxmx9x=zNO84#;ZA7T9iZcyb9M+@7uYPSM^% z{0)Fo=?hev9`sg(TAxJgnmWj@oBEv>y+Jdz#ifBlu)|_D1~1k^k)@;TIL9GrXM>b3 z%dU-}vR_MhT>)aLX!|5Km$5^@MnpTBad_^N1-~}n!@DC|1{FiUwov%3qQDC$Zq8f3 zIiojfU0jB*a)@hFjZ~CIp-rSJju?y5WN69a|5(%v&eee1gpr0J@{*G#xYR<_Q43JnQz{NQ~AA0MUTS{k!wh>m|n#e0$JNcGt~LyX$6M z9!K!805z9hU3zvfTqBGdvvgoeoa-(U2UjJg%jBURl)d5dU^yHWhL;yrmln%?XjQrN z=_&GE=ZqK)9hO3S7SlfFI(Ni;5}qScipYDWbYdbmHLmkG#$$^yfAq_B{s?-54@y6U zHluB=au4eYkC-NfWv7t!KO$VU%oa$oQr0mkH>HMtyvwzY@jPK1x9G0=5obeiDz)-T zR3VL;2ftnFbX}7{ug#7aZuWEaW>EP?*v)>fYbDKci8jofmFMcoxC^Q?MVkFwS7)3I z!PG9&?B}{JgEGcLFJ+k7&vm^N3$tI!P_v)w29EHjSf)GE?B}|X<1%e=HoKkcCXUZe z#@h{duA4c2e2O|^9%}Y;-IDQ5**yU(dPwS9IeJRUaI>FlI}6UmJEF%lkGgKl*o|g# zd#K@kmR-)BaxShe__3tmRV;zZE=LgAgDNZI8i&9ci8 z#&$W$BJFYnS#~)>EV~>bmR*hzvdc*hvdbv|b~y#WE+<)Fms14THSU%Dctj^va!@Gy-&$L zy@Za5q+ev@SZ0cs1hAEx;y1E?X>HY~XRr~8D%^C?^d2T@w)UNSNPb&$1AIWK-)q$F zF*E6i)T=8}@cgt}steCZxa-&;wEIXALb;1flA?XL9zwFhVfnL!Vf+$d8-9UO`=_S8 z1NvyRa}*domPU6(VI%wJy9Cnj5o-S&fT9*BG_(zAVxi^081{9T8M0w3#Bag?r{vkP zzZhOe9Jztzdfn}zp@cVm;Xn&NC8G?ZcyU5AmrQR?E|iH1 z;g#k?$QzGennXN--vnvGM2tC<`r22(rC$r5jUItj-y~WyWwq2rFT`q5nmJ|L%AWz% zexzw-;Nf=t(OW20V4cwJr)PHno%0jwoB-TsJ@5r8@Z|eZ+QVFovvUeTf-fNC{W}Pm z@(d!Mf;XipF9VncuRBxd)$Pjx(eo52vVA7#F zyh3%L>b)wfhk;7tRA~EUXW)l9+apc$@UueZOqEjiLWHn* zJ&|m>%IC;q8s&f&p1T$6NiDGBq6~W^eePtul}@AhUY0~FH?3bA2_e%0SaRg$qbFB` zE3XK^x+wt80PuYR8Ufss1E3SYGXQdP0OX!PUtWC8(sEUv3pvc|0`(m*PHQL831CZd zWd+1k>MfIR2V%8Xv}ygsor8(@{G9;Y6kEZ7w8cmuu``d)%Gx7&Q z3KTLCdu3{VRQvmJ)C_M>cdL@QJ)|Ed;?-re3Ypu%@&naiwaoJ0%tJh!fe|iF#i77w z+Gn=ozC(TN^W4p}Pg8X}>qHg)1qTo2Hq*SisCQ}iqtX6-Y{1w6nLiWbh`fiQ8FDw` z_~I-KNJH*M9MLz3Zn^@=Muc@A$xyoy$HuEbb$Kc%k>wqP%*tp0`^H1JZ#)dTVkB2D z&VuJCi{wVcIhUGA<*7JseoD%w-+D2A@-anP-a{xK+l?f64^eGwZdHc;*o&J=S%e|( zAvU+QF1P=5fRXF}sRL_rGWd{BYh$XPE+5dc9Pan%rvr>>Owow~d^+P!!pSGUk;fF5 z|xRK-Z)X^}A z88`XqeK8zjCig}59}F;V=6Fw16#rm=aSKP8`?O&Wt&LkbCx7Z}%4s{J$NZ51<2HX5 zs$f8`$aa&2T6|=m_^iB+ z_6UC1aA!OPHI4?AbHtNj&XMxE3)-UC`CS-^nmecl=wxL4*82NR_YU&Az!6F znjxDR=BB`ng@$EGQ&iqq-hwAf zMkOZOr@G!Zre)BCG?m`bGZ74_Sk$>ZpTY($p7AHl*0f`L<~NpQ+yD`%uj!fJIF*Ym z0(Sc-+&n{E}mMVqsLsvK^fi zwxWz5AYr=GxF%x>RH&db#YZG?&np(3q*D1SZoXY^s`P_TB#@PTA7T-*NV32Cb${I zC7lg;;Yk>0a}1ubbR1}$!+09TXENJ!nd&zmb4O=voF{8wj;CWVoS%6P3g+@q@iMHR zZJ-}_aP(gZ+DQI!2S-1xnNfBuN39=saP;3I6VtC#8KLrulGSBF;rJz`8>NMzFq>dP zh$J5@TDDe*M%296!(^U{iLPZ|3_Q#3gM93JSQU-VrO0uA!idjm$L!-Nsg2J7MV#>&VS-^bTDO4r5w+d0&-Ws(_FVOkg- zHpG3Q~bo{wpZ|R>Y|MS5p4h5-Rf#QT_*kVw}Vw zBA48=p(uP_yfPBwcEC91r3Y@2$s+Y~QTB0|o+rfLWs$(q3$Z@~K^3QgiZfNVO@!LU zHRCwB$m@GTYu9K*_OoD-R|rgq8Aw%v%WX<#lw_*G)In7|ssV$W>CV~ZvaF_v4i?o3 zQGF1V6Ilgo*5!90`9YAB5jGyVtE^lB9Bq>9X*sWRujrfbn;CL~i`bJIHdB|N+f z+Cn!d`!pI}Vn!jp;FFreGmw5V3>V~$zK=TW!C7YBk5S&Lb9Pe`PE~T@>mOaRX9=bo z+=g>m9;dRb0?JGsSpP(0Rcnfb_5|tWFCxk|Bw>YC{`bvSH-&ak`vxTTaQH0QDIqGq5XxbI(`lnM`-U*wN3*9Taw$rd>u&} zJ6PcCh#;q~x~N9CekSV;c`$5jFUbEq?KkEx*Vms|NQD*&j1XNzHrN7_`QEDy=b$6? zC8(M%zWiA$u)e;Y-s1f{%iqrBo_Ufg|3O*)&;A4F$rEsWr`Cst_!qxDYZ;S1%~o{W z`)v4qUyMoITeMCD9Vz4Rv~c5ihED_uR40N2(TSi8aUw_|oe0VhCxR5xi6DjQM35kL zA}DFri6CKoA}Cqpi6BANi69}?i69}?i69|#A}BfNL{I@Z5mW$91SJbj1Qh`%f|5Wd zf{H>Xf&{4(L4vFkK|z2oix$1Qn=G1PL}z1PQiI1PMu=2oh#H z5hRpP1PQcG1QlYQ2qvTKCxRwVlJ>al%Aq&)iA$acN`OxU2|mV&Ad#sDRgnfKDK?AR+b>LBee(f;QAT5hR-ZM9@PnR>IPARcaS0POJ@ZBDKD`ZCzb+nEb=y z`H-oZ^Y$*Dzn##Ttr)>6IKLT9033H0sws{87c{nq3L+=>5ERgMvH(9TfJY(dF|en$ zq72}eG9HEK$Oi%HIfsyYfT$~Ow7}LDXl7DVhd{%nQ;u)rGeY?4NROwz2}IL;ZG@yN zB*k)*5P_qZx&MGzucND5mHPO}L=_$wx>x~C^_kTF`i?N1chlqc^HiYu+-@JuROOzE zE9j;H|KG=AZ_|X%w6yi6OG1dCT9K0-cGKaz3D9Yk^AV0}9;$R5~9}XuHAA2Nb&5VCMsblJfzBoewDd zE5McW0fqMhSI!3%ehbA*=K~7gLGjZ0fWq$vuAC1jd?#?}d_bYQfJ)~B3he``oDV2` zAK|F?J+fwwoPNSl@p~D6nQ+wnKE@9aE}ajk^aF%T=K~5q3|u)MQ1}teD-WCDe84!` z`M|mq*&=YNDNT7c=L0JB4zDrX`GAVJ+iM)d`GAVsX^*p<2RzLc*rj5v>1#P3P>K77 zMO*2g<@9hqkizGCbekcC&-Y${x=u0A_tFvZX)Cc5>$&gDzlRdqPwkQfSp1x~N>mCa zbh||DP6krg$-rMBCzW7@pQP<3f)uPMGc`(^=Ft~xXX8yz15N~>UvN8giKZrma9vFE zZ>csYr=gR0muXiF;XQRI?`alqdbq5pYGsg?H^G(o(M^xONc%aGj+l)vU#HLuWv;$6 zI_nx#wnbVhqEO}`>Gb6?N2kr@f#FuA6?&U%Jd%)-HC-N%2-p!tYI(ujMMXmYqU+b7 zc#iGz;Cc@P@fbT({?=WL6^bzE(qm_bqINP>H*78s_ys(JE#nQCGn-tBXc*FoK}CDL z^h2|mle?H~xjazK>`~;Tzk-XHKh2Vj`S&Fzjxfm9opgDiWcVdDDdJ-0&a^~e%3i|6 z(Wb_|)TL5qD}v?nKvBmVN4q?r7Q-XOz>D;iq=nZQ@~(y0*L=>+Cf_EF^W%Gzg^L{U)KN6n%r z3QGGJQw}Q%io2UBT@EUYa(Td|;m#l(EE``Fqp%tM!T)OSUEu4gs{HYD?@80srVY1G zQYdf>1tOO8QbH-vmZV8bQ__+)X-UiDCQWW0Hjis^(+5@>X;D#Vc(T5GSh z_S*aGbIv~blzC4IEO|iQz;R&71Hu&k2tV3=J;Gs@Q&4dgT6uk)6aB9G6l6h706{N^ z=H*@j;kV?->?II%@L|{#S^`01^TvgjK+ssU_L`h)AYlCCdbdGH>~X}`SvXWxE_4c( z*H_4*_ks*JnmH0Igzu@1~?NJTX@2!4-uwlvXV#tW&Bh~mv0lEn||wf43& zws+8nts|I#;|mG7pt$Qo$N4a3<7cVclohN`EAi*po;L!Th_bJ>Rfbh&B@SJ-S2iH9TdawC-SzgX3ES?q*IOA z@qA#6YD{9ep`Ai{7F|)B^v4<;8j-Upws3KGi?$un@L*Xe&Y|Xp7jyaYFT{nPNXOM^ z@kCtv;e8>#v^|xga`p$IMPwf75{b-yfOhBWgVO?MFagPhP79DgCB{03;8VO#iV4i) zx~jw%NjjTO>?NghzP6I=FP#R>{O_+!;?bA^YhfeHrn%jg7v^Q+B=a3wsOgw$4{w6 zcO^y{@8+5Dt-IiJ#83@M^S=6Pg83n|yjO|MxMX!zE#?K+)UDfyr9;0Mc@4v~Sj?nq%FVlzz8R6lg_Yn|!fx>xTiV!MrtslO`AD3KLSB*HTs;k1+>yvT^yK?!m z^;bBFyt`)3!(4m5deJ5C(=*G76$Dpc%}7iZ(PyXX@HHviEosIZhIxO@1W^#+!_3IA zasw~#?wQYn5&D6Ayhqc7Z`xL4k;>j`dNC{SGc$j$_{Q>8e$n@z^7hSKt+4TYl@;)u zdv_O~8st-RVUk9CwKs2w5yiPRQ{&{kdsw@9`L$_$OIW`kbuS}JVDns-aEkK|DAn`T zC7AlEY~Gh=(j5pg1l59-`pV3GN?$J@>8r1YKHAG?{+7>7%D-wG9xH0CYokw1J9!V! z`~ugT*wm&v8`Eug;MmFgDxWBVruax{Hy-kL^1e3nW7;0@GC9So$)ztQhskq!_sw)L zxi;QAGYZOFgihYqm2dO1eeaC>c0P(?fl~FlDiT3*OKJyRV~fnL1zx`H!FW8Of5sg^ zPXvt?Az<-iJ=IqlvgVQyvCVl1(Qk&3{B!Rf;}f>hn1H z)J3>^p5QZA@qX%0a3*gdahQ%iIJs?Msi{7m-S@R{BJa{KMRLL4@cvSi{VYVxPi!hkL!}`R_iM*SrZvzT-r)t|`d+?e9)_?`In&PDogHlR*jV0b% zQidaZFBm*%%{wi*j3f_T0!g^rv{j2*Muz$Y;SiS^RY9mLE=6&YtKUn;ci+%r`BPXs zFuK9*JeDC@`}-*IbCT7DXQ=eDEKXzxMe)YVfR&YGZy+Upq%nBCcq>iizK{HK-C~S7 z$U_I1aRPxHx%um0S=0b<7C8t{6DTKgPcen}kxxu>vQSJ;uQ&LyO3#STIty$tBKU9_ zamzZ*kJX=Y9{NUn>XT_ElW9*CTkAJQBj=EnCb(@(gZG{hzs@prUB@*X2)^}tKD~>2 zLg$*wTB8vKd0NSZAn`!i;cMOIg>x#DU}%;18cx>{$+B;G4s ziF~gD8`d!;9CbIVKM>ev}Q!kokSu|8V7Q8OXsNF zlt`p%8lk7o!SQ@>pEfO0;Pak-a^PTwQ4X1!q#{>>z}LQL8nj;wVY5h>=6i}?!2%L< zD)WGjr1I=MslGaUS}_>Ro{ZXb$73CK*Llb52R*@=4mRBr&cEoH@?7 zB6=R&{PyiWw*>OYaEAEo5+}?7&w^Z}>UORn)_jW#kY3+qu;k^kiBzrgjKnCa_3jca zv*6rGiUyG|kBb3SHBBR_;Q6OTE||71vOd4QU?YrQQUK6#=9fAb;ADb!Q5<6?U#X2M z)8T@^A*5YMJcuRnAf}}O1p4rc#xa|P1qjipsKdoUsZ?SSkvPsJ!GeUp)HiRI-uTkG zIN|b1C1p`#PoTR;>LxuNWNr|@j;JyrcH7Kgv1HiD!dcf zNZ(|4%l(K%s6GCk08!5TltptYMyLNDdG52>HPtVZ6~wN0q0u`2-1@ ziIk~E6U+w8>a3-a=j-Z>4>xiz+{p2av$6+xP@A8qJMV&U=RHX}@5w=z6-uvslJv^4 zV6QwS*eg#pQqg(qUYWXWzgM1N+%Pk2&y&TTMSew8|1pbMawmPtaPe?zI04NLhX=KH z>T9{vqSnsgLD6zX;4G{YH)nP5%n2giNvH(v7Y=z0tHhq;#h&l11qNDF*m5Qk!XkXwFi>y1HZt*P{_*o-wNQsH&Bz9u-60fXQU2>xVLix~i_+qzc5X zlf0u>IjyS_8LK!-4 z0-A~i5;C1VGY1znNH{A{40LmK<~!Tei%OppI0Wx=b<`o)q`tZn$QcyD6r`0OCIO8U zJ(P*Y>0wZQI5Uiw%-{tRSZGXS!hd489@!(JT&hl%_$;JrqtJ+mM$tK|9H@z;$2>pK z)CI;klj~@(LH$r5s8v$MurnOn7@+XbBv@0KMNr8Jt-%Z=&=!Jo6-cjS#gmL=v;(Q! z6lr`@g9Ddo!GVhmQdC2cxdmii%q;|C%NYCQfUyxnMS(+9Ie2-3v#01$->EwM=u#w< zZmf%uoOU-7^ic9RM&RTpbap|@jxyIHo|U*$4lub(nMpc8?w|@}KsreeASUZd7nP< zGE#~;AwDqr%IXcYMp~E|Y+f%rc6?J-H-ALp=&^oXH6JUpqOG@VZe`<17 zO|xP`bv{k1jyyZtoZ8&p*fl@XnV#R*+cQ7MG;MoVQ%7HO%JD@22ul%)6C`PVy0>`? zZc{Wl4)oV6ilds_+Pk_kC2cT*qi=U;80h9yi-u{*sZ4LPKIqLfL7!!z!uZ}b*_ z(|sY58FGJhqgUciIpX$a+{p*s-o@_Zmb|F@(!>_@7Z3Ce0RHlXRe+Cf-9P`DrI+G( z|AYY?Keu(&U*X_yCS-8%{jCSDb_+^gd1>gEz}=w=yt;MYqlY$nOWn^!>b)yBx-Z>0 zu<7sIL%TBW6Hdue+_;bCm*l$zHvx*ceXDMEC%%4V)rU6p^=;UyPPXK?yFYeXytAtM zUU>Sq-g&>=>wbDyCi%nE5--uycH5&5xm&zd?uyqNuluAsai4dlH{acS%$@oC{~dI{ zrMJeeQ(F#!U;{2`$0H=s3jfa@aBITu#Aze39%Var=-zD^9ULc1GK9 zzoH4RMB}~-F?vI3^ws0n=mbSPqOhYEFJfqQ-cfW1S_3X*qDNI1q`{xU&Yl zd7Ipi?b`32*0OhKlUrEtZa>oZ*zWW0aC;BJSMJG?s0-`=0wto(ckp|ho;X4EHZ6Vh zZce{HD_JObC7 zt3p(T0ja{YNMz}=k)_cH6d!xYZ_jMc1lkTg_!z}2t$!(N{6)GGJhX#HG1}<{G%6nK zAi@!3XMg$nw>u|NUw&xiro`Z*y&E?@wQ19ar5msA!`~*iZ@?`$_{xtPILeED0Wg5|m8qJu@Lt_m2$cv7PKx%!bsn`rIXpuHG zw4h;%Nm3YSsI+uy83B&_&-kd0JOB0T9<5r^>6R^a4?Fc2^tmUMxL@A2&-;P<4^BOx zgVD2Q52fRt9u7`Uw!RQce>j$OD26=V=|jEMSGF#_va0!VciSrN^WE5yO>WnIcS`+l z?{7Vi_>A^pnE@#Chi9Z@0i>2`cI#B*LjQGY2LButUoJ}1->(bFmxyu zqt2^<{>MZle~tweqsK$60V&5)S-cFDMl78asebI5{^r$fS8rUhW!ly$e|3+0YP~lz zdg%=JdavF+$&2@4nECtP_qhcFeIM;p`KcZSvDhPikJD<7`K|z2AN`c9kMB;4OjjLk znaUC8;Pi3wK0%|3|AHJ5e1u6SiLF?%s->5Gqxy3V4|_Qh%qn(Xm{Uf^bkL+C?&U3R zdA)nN7vJQ);_Y#dIo_(nXpNt8XO*~rz00fjezw=U3G$4)XIH&9_kC`kH`PnL;oaf>ljH4kCmwvvo#EZ&PC8ia&UxM4 zyszAyP~vX8>0-BVF;YsUd&-e7?si-1-T3oM+*ro_#;#-Ttmm)X>(0z9aVKQlt=`ln zmtV5_Hn+u_x^%A_TfD@blyNtBi?3{TPt7d3%{_?Ap`N}f_d}6`QM$IhOSS61*|=cgFl5*O&k9nX6lWf7PSsuipCT`|2yOC(_;{ z?&QU8Z@oL^VB045hE*%wg8KR1^{XHKnOD>aG0Xn_qfc+#wEKG$3)@N-{%-3JS3h_y zlJXMJ(gk3CCV$(N9dFNnQ6=>)#|XE;oA&e%v8nUVt6#TwpF4Hc-pl&-s@%N^kvg^u zxWIBFoIPYI5L_-!U!aD#iO~(H*>BB5ik`+w$2tgJxaHmIB|7`x}SHJhV-?wff zC+xsa^bq}QxUMhdZXI|-xdzwrCp|yyjeBCzDD0)5(0uSOXFDgfq5x_eNPEMkMrtnd zDv`S&a^HX6w#kj}bDNKR>H6Kf+cqRNyOZnP%)TXM6_K^SJ>ocXi8?5N5kEJaU!=o;|=w-ZTzIWeHGHi4?p03byv&Ht><0i##XsK z`+s`bk_+ZnKeMf;cXgYa+3&_~x_0vd_mov``?0^@y2&l@rnDY;9wsK| zT&XzHJ7dwZadc`@iXg@y->lQ^?Td$lyfBqc& z&u^W-1ix3dp2#`H5CrQXJdS%B^FN#ngCsx>yktBvO;8STs#G~>zGv{e?C zMJozDXP!QE8u!lDnl z<%RK^^U4d0_lzqqOzh6TqVO;#7^4#l6Tm%=lTU!^$@0S3Q_BjyXIJ9>h1x{V1JldY z@fjKoJrkRtreBYv!<-+^E_1=B2z8Q~vH6DYI@D`b!5ZQYdoZ2D(=F{x2SxW#y>`2> zSj)u1A|Ox;?}=pv-E{PLVXXWKG85C29waX<(>4M8aDJm#lVqlf?oiM+Tzv@t3g~58 zC{IyqdcqH}+#o)e+)|WFV1zC+8ed>OsNU`<1;@uHqGpBOAe^R}@5#_+T|?sl0st)#dWT#$9D$ z&DFyMT@{?w!TjVyuE>dM3;Mez+8A*76$RTuM;im~UtSPh6F5YpDGwbEZx@RDN6?1k zGLGiMX{#)3xIyem=lkPj3O`BxIu6-`@bbyIml!{SJ<`z)!x&^$!LWWKf7TN_pgilt*r+JhCUhyl~O(@s))G z5j5LHz@QNpBbCIFN{Wz5V$UL-d}mcb^gAP*#`1m?hoql;aw3oO7xepJv|@68&F=g? z<8IEo)m=65@$x6ipIr8AIkN0iq4u4tJ&`^7$H7kLlmWs+D(YAJo$#_~XAR@Ye}tFS zG-{deb4OT2MnVH_A#IED&)Pp&Me0^)HbpC`~zp42U~6lIB@EQPs9 zar4_(qM4i5ih>ooUGsU0KPo3HT+#|ww4pt3Ak220kXgUK40wr*{)1$%o5@~# zC|-7tL(`9TO)M-121YA_(PD@a@2M3qTrmt6hvAA~xLEm9+IZkK5C6npmTr97@K^P$ zVf&$}sBO6TC;TmVr^>&eVLrprlieNxy$tx(bECk)ZfR1E{7UC#F|r06(-yLu>WR2t zqU45+AB zY}vDcev;yfzE`8~kSVEG*JaJ?N4sszOq@kukE zT_f{Bmtut#vi((r&I&A@GRS|#U*1=|+wfO$g>0s}*_8#+72Me=50ZVToV*6MpEp!i$FIi}5~)w zR|Vvo2ebx;S&3gW<)t~)Hv-I(#QGf8@$o+q(5bGzs45+JbOY+PboW4zCREGn<@g9j z5)0*K+VOTU)auFfrIV=k7XR@8Hcw+Zom3y&O(ykizs>m4WtYPX?S;Nx5mo{puwpI5 z5csSWKIEJBZxpe5*`Lu6an(3Fxi=Yp4vLs8Y+*Dax~ztm;EZPKAuMpo~Mb7Q6DB-+e7<_fDq z-D%#oF4frE-Q_48RV`Refpw&FHFWTUE_YO@Rhh9mbDu+B8Ek9pYVJt&IN_yeBv`F> zknM$$-kx5*hTgm$iGt3CEZB<$G}M|CX<11li-1-~qP39FwD57k^qM+eBCG-ri!?Uj zIWN3!-i~+T)5=ej;+(9{zqT9Bw3e-YNt_g^3>?u48fwA1z*L|fF^<_UbYM&WU`ZHFB>sAnV*GU)Fb7;5G{(FpvS!6gKy z*?8KBPT+cMrqoVD4-fYLPPcUD#@*LiQzV0Jl$ zG-Wh2KUc|YqJAd2iT6}#fp;5ROyE5RS0wPw1{W8Y*4L&D{E7wsn877{I8W1&HzQFw z;5}K}WjN2^iUl5LaB+cYJrmkcwn$*l;9>&D49*ky3yf3BXg20oH2wz9p+ud;;9-U* z@%44YsS)rDM&Wy810OC^Y$h=KQ+OXZC8&FStrCMqw1z|h5gJtBUs;ievrfQcj2h=` zcP==0P!2^eP-g1`)H~7RA$H@peRtZr9^!M~@M+SXz$<)X)rtl^TsK}xxfml%|CCXRs2E=lvCw23(o zGa6xjrGmnoJe|#(aHfQY#3QtV6m4MrpA1g)1EfZbaE@kd$mebg z&Xty%DD&aj(P>nvln(1trM=?v@x5e*iTa!(3*i zZ>!UGiLY0UfRbS%&IVi923^ejO5G(gCmQVsvx^7M84eoS$cnV`-gVLuD;N&2d)4|n zC`XxH;P3kJzbzr~_YBVJLZ#dhra`p7JtzlKFo&~`GW~M_-U9#H;1UA=#^5X+q}(e^ zqjZo1DVReCF&-CFb`W?bpQMgP;JCqg0+$$ELSVVaLU!fT)^09ikXfyBj4&it*Dpm3 zi41e(jFVvK0^XA{0xvMQn7|7Su1H{-9HLDPsN~=}jU#In34Fc5#RP6JI8WeDFitU) zg8@TWB=BB?iwXQmgYyKwE69*xeuu*?TjQsf&a?jJb@nw7M6q08^V~ta?6gi;nUXcB*wtc0;YUat%$tGpt3nk zXGF12QX`;|zqcW~SS=%@(IEQ>C_V@~03`%(a%AjoCR+_STZ?t)Dw0Uo|d2bY6 zvX@w@WJJ`tU{K%{J}xmRun0zL5isMET`(x{4U7YsfZqv_2`oC(s8HaTA2JsV3M>^N zI)N(#bOIaa*9a&V;8ZbzKjarp3<|v0$6YWeutaLELF@Tk9jwf#Hq=zW3LmxhYYa+e z0F{8x8miwh=&}x=67VD+wN`4h(MQ#6Wl*L?P*CbKV5pe8zZ0LI!WgQaz~W~lNb#@8 zB{G3UFvtWP$yh_I%)Pv)%qH-C1{V|feuFC#__GEV7x;4qS1j-s3@#z?HyMYNbJUT8 zZv_Yie%#=S1%ATd;sQTua76;k)gk3SfsYzGPvHCb;!P>zJB0z!_%Xj=V(*sSfh#veAv)=0?*^lPbtIa{he594`X0Vddi^26(xT;>-hv6f&pB+^GPsz)Lk8yw+{unp3d%tjBS}GlyA3WOaN6LC1%9u=#RaCNW@rPy zB7yr1E+(*Cp@Gg5_(i5u3TigyS6u!%Mj=oH6ul8B0`6c|pt^xU;XXn*J>v6TE1=XB z!)^f$@3l5>$#=fuqW4F9-t_{C^U-|?C}JZ{y@28YPzh)>sJAt!^F=f8ChyPkZBip( zgOA!EjQ+-;9%4`~Q83&Q&=_+=wzwfii2l?Q{|n=O$@_?Nt;i7}xjO8ZS%H7yJq3%v z#|$neu#8jm;|Wk~j~e#wmj{)$mlQf`LLWj#?+z+zwZ_c|9bOkcvF4P*jd6(GBo;XXqq z;En*y%1rZN-iu(@xPFN>?`GY};4;J|5SSR-0 zXi#F?-3BFg6r&*pNu7VfIbI5@> zDo0Mt;n!+$h8Puotrl&hj)e17W1gzyK^+z~IRSB~;n_ z<16(J7$;c5#ly>%Q!@JsjkDFNV1$swoSx~oN4>;cFL8E{bLLq^gEH{A(U)UIi^!3i zhq;nxKNtT1?&D z49*jH7UPrv5l!Dope;vp711wh3UxKjpudZA@i_ro2z<7| z#RQgnJFsIyV3`*t+X`G`%KGfqcnSPhrd&+m2&X`@vkw~_y`--; z8PX8HZ2d*%AoGW<1eD@A4D%>czu=d$0``e45<6gj%M^d~nON2pIX`BST=`0_A*Y*~ zdjc;sxP-tL8=Pg0GCo%xpb>bP!Nmk#VQ@tPH!@D8AUW6^AQZUC;9>$d8=NQbhl32| z;3I~xNZ^keTuk6w4Q|-lu45YbUO>?Y$x74^jydwzR%T#sELh<%z$7vhP_fOpPx2nP zn85NN8*oJe-)`vQ0^ezH#RBK^SO^|C>d3)(MuK6nz@EXy1)gAVMFLMWxR}5(gYyKQ z#W*Ec4o)$I#RAKOHI#`9Ec2RFV}VaIWn%)LZg7@I#me`wRp3zprOs&01W55|iL ze379`2)xkXVgi>LoG0)v3@(vfn^k=75btwb>B&=)%YBk{0t)9GMi)Um+Ef9IYu4KvD=w%V&)PaW{}vTs_+#nTj~K_(DznUC5i93J*jH3Ay> za<#103;c2+)yNI331CwhR62o%UnH@9hEN~0UL)aemZ`{bEp+qRKBqw4h za61!`x#jO=k3<4@!T%BJn20qXG$9zUL0*b{D zjy9v3Y(}p!;@@~r5i0QS3@#?Hq$AKJ1eQ4{;6|K}k|_)-E3iyBP+5Ux8UZ*@;9EH_ zQQ6_@aI&BL)(I#q(V}INL^$PWuK9^~PV;}(u z>QbNMIsupZs2Tx{D(gg*4xegWwkkPB|#~h|7PQ_dn*n+y(wOKK7e&7K1;x{1EeNXF2lt z!i#*ICC(9g$^HFIccSRe;|98j_iK4Cci804T=rc#x#OL!?}_HOm-YE9@3ZedX3HN< z??0DbCU6dL{5{NjnZ3#8FI|M>aLGZ^75usM+2#MMk4swGJ5msG5&r-5w&S!${Es7r zM9Wo3#ECoZFtPm+l!)P9(KuL{B~2^{laGJbY3ylLvoc-~(}V*x!=h>E=nnkH@$Z-F zNoDlPafap|oNvItmIc6}d5YQiH#A?z5w$Nv^E5EDX&PFDh*%f-7&`Y4_@_5|sgw>< z8oqu*VW?zD2Ua|3-sU{*W2h93*XbQxT?#a6U6p_GX>=*a`GvvY8&s&4+Mpz?`Wu{+ z#~d}jq!~*fX;A5s%km|gd*yOU*DF%YCCsj5yJ0jAXgAV^--(6*P)XX*KoQWa#P8HF zO^>0WhT=xf2%VRMKLH>w)4v;`U#ekvqmgwSsF7&oer5sa+{lY_;fF929G%XrCn=h0 zZogr&c}zpG=tim`k|H3yUCcCO6*rQ=FQ=#g*$SqaqG-zaC_n(PjgyIL2P%sLL5Y#-*di7+FQN9lJ_O zBKd+mpnYKziOy?4t#$5f+>%OeZENmGrhB?ONpotI#7yfBa+ZkxHYu_rCU?jGejw^X(eFYnv_lGl)s5JXzov2Bk(0MrjoiJ zouK3B#CedkvNvjR)XsE^`xXeOhT)C8Oz%NxFOxOxjamW4zHS9!UlFy`o%$7BcUb_- zj@}bh_cF-R(K~$I?><}V{v@b#*ZuwPpzhN^Gg{s6_UrC{rwtghZHEnY-Q$QugAYO< zB0N%-?st;O?aj$Xtgs8D%Bxs#3YZ&oU#T%v`co*C_Dk6@b{}ZM8PaZF#4W6p^h7mW z+Kt2jg*RzC)bo*b-3ax*;Z52O%?#zPggym#SBeUWREZ%0{Ar z>4hyxa3jU|4aW!b*+lg+vZR#WGfnxTk!T=m?xszfDnX-Vh3!Y2N{FVsyu55A8ddko za^K6U?o`@rTA#{I4L}X2Gf`7}Z#+k0{wX+p0ii=1wf6`8n7`Xr8r0OoQol+bcO< zwY^afn*e&G9+vXPwJ5FI&YPgN#Zm7`eWva`m)e4Wq281FOx=490h1NaJnsD(&T#MP ze+UpLf4dhv`njd#YJ<{tG!50AYKKCBP1+9GhQ<_bBphEvDs86$Flm~ThWnjcabCBb z9DH~bw;eQe){W%ocU1gTRZygx*a+*4Qz|yjJzrwuKClb7L8779sDd)OFW5;aYa_om z06UuB>mWh<{a2v2^&y`=f`9E(iX^h8*`!bT9#A~GP^*BNFCuDMx`rEIpGIvlis&%# zLqg+^Ky)dx>U1NPA@On?$J)yliSOk!PL1Z}0nlhKlaIoiWXL^0YcCf83P(7Vpw|7& z1>(W|!+P*Z--Fwzn6;4yNuSX?SPnkggHM9mHZ6JZ75r-tt^^HfZ#MDZkAc!2418ab z$)v>{P~IV5nDPQ0k1zUBXgFUGKeFN0g<`|Qz>rtM8?}PPU^3c>C?7Q1K2>1`IFh>m z5wNa%;JcCm>Z6dQ>yEK;j=E#nN_>kFEe=CCz8dAL0AsNyz>j=jw&SrFMS`}NDKC)p z?{@-0cFH*h;2cHcpV6XsA#P6Uv1lvUoh)MfJz2iPxBL+w9|Wjx>I0J)kZxp7IB75; zMfhRBqeb{tz6X;ifxoP+0jOE1l4< zz6~j}g*Ry_=Yvk$C;YKZp{BWDZJ*pNh3NhOnmCj(vptjHnFnx2MYv)$8<@i(%sIf6 z;os1ZKNE0hxWyUo(0uDDiktjMi%S53!nyMpduIsem8{4Rk%l&Daip_uadSiG=|K96 zhXGTpxe=lX_vUitTLTF+d~+jkQ;v-y;hu7dgr_k zM)<&)JHDE_;l^;Z4b6$n^wzvkMHlpIXRj#(=5Q17ISy#788atB3%_dP-fioO+ zw7j_fkUWz~t1LsMK$hF5Jm2z8{9Xn}Xulgh1kxk?icMrcYS((6P0s2))0ETE$TU@( zNS{$?%Bd|5M?*3wHr|8FHl4BQp>CoMZxkCzgr4pz<#p#U4P}Y%!RhSN@JSqrFE)ct z`+`4innig9{Hc90dOKS=+-@3=@|Tx)=k-TwAS4KWpwKpMywyq)Q(B zhVManQX;64z8;)BOIr7Z5J}pHH)`E+{EybUi=d2-goU8SU)H9s3m`$a+##IJ-Ewb0 zQ5`MjYqP>C*_*>!$Zpw7-I%=QHzzH&Huff91LgAdYmu@in1QB8Grz5X(Dg+Hidn zzIDpJP&E6AW*SF=!aN0x?=L?Rv~-FDx_>%PQOeKQBEfEL(k~A|L;OM3iz33`%NXEQ zV05&U`sW0YXrcQqI$Gx9RCo+Pv=l8LyH29zIrx(94Td+0mjCdhr2@9GH_C}+NLEOj z(E0s#M*uuUR6qVliYU70Qigvx5qu5K*wxo>VWAFVVZ$C5W;+bN+Ca+QuhHf5W+kLOd9_xNBJ?Y>qWkxd*ovu z)B2o8==I{TvySI_Wuf4Y#52X2j_2(-eR`0@k+#zh0w@ceVcr}Y#eCy?B<8J`pG67&B`yxyiK1TcMw4|`mYFj0>~^}UYu7lwp{$J};br`f6baD~%woo&PiVPh~K0j3OR6lXsUwayfWe-Ev*dJw)^_e-gJnxZLKVUsxYrAM|? zsD(Beq0#7D$6-8lo(?1qp92k5Pv092`-12w4o|;H^3Mji&GswB;R?it&Oem(?2Y2^ zjfBMEPhq=oy{H7mVHwb)#o^hQ2hure21?lCC=TE6$Kgs_8DJ<5%iu2^hX;TmE0|5< zuoU{}IK<7;PR#w8j>z{Zt)E9)bpZ6m7Jy?(vyaTf8RnD6rIMOTPG1UB1W zTLNb_DETLi!_i`OG=EWB9s-l$+Op{Lvc!*LN%zMRzAUGtorWNDFW!&Fid5vdg1IOI ze}yom9nc_zSvVDkjN!Y$W0O8)NvEfDLb6K9A0f=b*U(r`g!Ef2>7|x*%C=$YLnlZ& zjUhvvFQO$dLYUI&mh|^n(q9>q-*2&`&$Fb{>vti277kd_UmKJ3J1yz-d~ZlrX{9Co z8B6+`W0L-+C4CZ7MObe%a?j4rjo2|Ngmh_@ANx$EcPBWOHnwDN`N&ll2 zb@4GtKVV7UX-Usm(q~(BFCLThXD#XUPExq;`z`6$ThbF_l1}5pkgSW|vZTLZN&kW+ zebJbtzhp^&&XWGDCH*E#dfAwyzhz0M&l-fRQ98+LaYroaE5{`LIZHaN4;z+#$f|qV zl3p_==|?T;hb-w2Thd!B>GflhKFP{;rIzLCJ&cew7QSXlZy1yGSFF0fYSsOiRrgO@ z(%Z%){Z&i)8d_Sxfp8mh|nG^zCDke#DZ#-;#d6C4GY>y?;#7 zU$&&bWJ!O{lKv4(`YmIUe!C^T(vnVdx)5i^{0k3SecZs9q(5Rwztxhy$C93~>VD^# zq(5v)-(yMNX-O}(qz{cr`W{RATub_FOZrWgV9BM(j6<) z&bBfwEvgxgx*u559~qPMyREv{S#__r>i&{t`NLz9K43{-Y)LP*r0=(+9~qPMm}U9J zmgQ+?J8bzsT9!XLCh3Q*y5DWp{dTMFm6r4u#w6Xd>ORk^JFR3AuKUj{=`W8-`V&^& z@3-oHw^jFQOZqEgl77sRe$0~ok|q6ZS1ZP*c z?$;n%hO4{Gs{J?Ct8}r%YStZ0svg(tqDqPI;b|_OF6|;h&s&B!t6s-7cTsOgo#-qY zmeP!}@{V8@My*`;W_&C&Cv}!|S`juRtMoZb`Y}vzGmXsK%o&UHxt8>umUNoA4(YS- zW$~AP578Tw^kPf;9!vU8OZw}U^w^lBS6b2!S<)Z2q~B^;zGzI+J1pswO#adH*rj=q zY|C%5qAorr>1~$uJWKjpR^3-x(u>C=J#IC-Lg*ILr+Ea?N52Fxl zU$vy4Zqw?2liwJ~fZ72E~me{MF zdW36OqqBeYXY9jur>9YetGit5{WsRDbP{Z*>jmd#ZBmQrGJYQ68a6Gl5usMqwb^~Jz4ZM|H&ddfUsgx6Rns;PwkOq;7Dw>h~=TWGUx5L z1w*5lJ?v#oa|Bj zSEj{r%HmWi&U}6j8W{uVQhx$QuHQB06l7wV`@);89ou?8&Gk!*CFML2IPwx0O-I#c-uV1`09?F42~2y-(q^mHe7EbDG6h4=w0 zV3JLGb&FU$SoZ^J7Qs)2zQwK21fC*cp4j9Q}s0CT9*>P5)l(twBk22G`l9j+1JJa3W=R(qV0#g*S z*oO(@^8w)eH89PgQu~1k>vIU0H$pUYAG-{twe-$ZXH$9y;zvEV6K7xi18C&QG#wki z0%i!M$dnpG&$%`O#0g+J8#@qX0OLWco&lONzZOY)p=foT@;mX+d@clyj8Zh_a$sc4 zrZF@Mrp-vd9vGSP)HFMQ3AbFj3n62EP4lP4~&d1G|fK&b1Y=BUjXwgPU@N} zJz%`JUoXPU049yS(Qqy>^}vuw&3Pd(_lNkb1*SMeLvPH>lY6>U2AJFZQjMGOG6qWM zy906N{2|a7S;-{cdrl@n6^zw8KoiF72j*6vGo5<|7#Xi>>HiE&1J2Nq#=NEYlm%Kr z0Um^G2wCGadNeX*=L>+@;iXn8pvjFu~@6gCo|WvvHhdx&!vFbz0w?A#BGjDK{g zTY;H`Ok(_X7ceF^@P?X7tm$}A`qx1tb7)bgwj-4yf68pL=KOuokUx!2Uj}9X7&;$y zT6$9{%CrsfAm?9!=B-df{SlbMp?Z0k7@ilRnaxwhrWOlB9k z&F7n-sRn3dy#&m);HP!&ZEx*rL>4~~D)n>FJmS|2#Ll09q0Q7QHVNyuglJ9&MrMSf z4wUI?>P$N?#Dn@Q0!?Me&Q}8SYDmM)!0ZfRwgD6N*9U=_9g4BrfXReP(VNP&nSSRn zU>*+9{0JC%-VZ0Ry#h>Li1Y7&xieJLLJYy;pw-rB=}9#<Nx zp4YP00CS5fr9JI9*8roRUlk9w1M`UQW$<)%1M{$N!4op#8A}ZO^+1(6Z^n=Fa-q%4x7>XwP$NPtP0r8EH&U1k2_v=nH7XtH0TsRY^ z5}0R0Ijn4hR)Q9xB6PQW9 zEEILV2+Yn9=22kkaK`ZY0WgO`H2(}tS%~KU0kb$n^A<3)k+tX_nHUilkBc>AWnjwT zT2{-p9;`lu2={4l$~hgS=J~COF!O++&3L)e!mI}-p+stIfFt7Tuw({WSh|d|l1EL36-N(?;IK0Q1#-4aYos)4?(wy4d*P3kXY3yoE^~zy; zS4+3Rjhi?3q_)aYM>}2>;zBJw^jrcT&?taGx+Gwb+2Xx%wN__)*Ve|4_U0Oh>r7=* zJu4f#nmbZG4%Qb)Hl@=^T5=0rcwqm7%xLaamDIlznNZ zt+6-R)RgJ&ajtIfS{*(oi}i0)OOFQ%$?93OiER%%|7&KGBGTLGo zsqg4gmxRrvvpH1NNA)^-QmyJ#=Z<7YQ+L-^ZG&WUstM^hneN6w7FI*&6*|^7=4L4- zuU)<}iS@0zdy;KzY&k>Hk}1J%gAK6|R;py-1*N46om6LEQom41kbccR+1k~YOl@yU zr8Di_T^7Hd#`fNntfvJpuJ29ttj6kE%X_GfS~;x4)CV-bcL#J&irzEV8sbo8y(BJA zyL)!PVcTo5{0e0CI>~gZ{lY~HlRbT1nfA^U$|1_Igl3OJic?ic@k=gok{c+(uuNuE zCjw?!BZd;m742QkHOrY-*5R@pYbc6E!7EZ3rd!e7Q{LQ+g)bnSwKpd#x}irFr{&vI zO->RtHOm9Ct9sXTcTu$(H+Q6}x+?m5dQx2(Md0&Ib@g>7+dGvdI@&k)H1_OB(lb9s za%(D+?CjlYRzh?_M_9Vy;!@N-+1#CM?daazi1`QDhRPcZHIQD1Ow|q(-H>X=SuAhU z2i6o70w+htqgZFUBh`s&fg?M#wYR0Qy`!%u+X%D^-$4t1n4FmWnAl-_+~K>10QHFX@rowy@L? zG&VQ;48jGuX=Ty(AOg3htRl&}>RP&r-Q0+&wcxT<=aW>-dqVEI^=s;?RxeN1)Gl9N zc~x@V^6IN9lGRnUbr@$R$;%WXoVluyXUiF@ukn-6e={`4@0L_gSE}Q}1<6L}sAH5I zqrW|(m?bOgu38u7%_BA~NKXN3cwMGrLp!o%W5@cgZDXaq+@8$bYyya`?`}Y-91gz9+4H&y{ehBAXWq+4Yl;xL&2)!Z)}3z@IiZ1uTrQN z0iNt`Ar+gpP=w-jR_%c9&B>O&E~!?sv8l7UqYJ#lC1}B$9z+27th4bwNT0oZn|oCS zl3Pr7Xj$zrqMvw_Y4oU;eX+JLg+wQ8+Oyas8#{Yj zk#W%}8WMfQqMf3zr;IO1S=G_P!_-G6JJJ=Ma2xt;In&+Ij1->E1kyLhB&VjjHoCB^ zLOV@m7**5L-Gn>{TwO;m&`7a;DW?v39D$ih@o9*_!-LsXNLD0!)2XKRmiDHA$Prq} z@->yPEW))K*{CnQ0=}XyV0l+YSxVg0mTF9g{Hhz42{^V8jf4Cakc%aI0+q<1v*CEe zI3tB!|AMgRi_%a=5VmKewsV-oKsBsbw@#S^{bO=7I!JBqipF#X`I>Vz z2+%jEejc4gYZqmA74UF)JK6=>pb9X=N^dus52XY2?9I-wIYpa>EW-nJh^Q*B<129O zBA%CiCrK0mg6>(OqmFu4_FWnyNp^tBmts{iAYWD`lNEO6Otz-fz!D2ZqVqv~HRsC3 z)GStaH}`d<^x&1!H-){Hf|CKqhIw$0-KcC&@uX(XlIZD`MYlFJbs%A&1JxGgsAyu& zx$3KpmfQK{5TyCkc8FsMDo6FHNXDh5M0QgkvUOTjpBZ8;Q6Vb{XtC(20z*@k+HzzB zj#^3)W;B(<`aC13S?4fus5d}vXZ2M6tV#8t)4&x%6QUR6G8!5yefZ)|AMm{j$%B$1 zyK39Iw;@UT!NZ|L_jQxu(5Jdo`NJoxxrOb~8VIJ53K3Jz@VcML(d^~&j;n?GKnr|< z4ad}ir0>b_z!jDF-Alz1lnL9Gfc zB|_H)O-RkB%P6RwuBt-)QU?Zxsh(s@M`NoVdSN`ar8lz$*DDa4m3q|tM|KlztLj1s zqxDj5t<~4`dSq-I;Ezhe14A;SVmIsnP4}g?+RC0hA)~9B6{n`Z!oai{ql1u*`DT(X zsi)#c8uX!2SpDnp7Ycd^#Jtr+dw9@Gx*OA&;g_@n2{r#xLb@LRLPCX!x@|?Z=4(K{ H%=`ZUglwLC6 zDE%N0x-Rjb>Ri$*gRGdO|7L>7FpuASN@CldNwcuhv_X5R9Hmd+#&jQN(79a-{u6W%`k52_# z0LAIt=|jnb&M{yED*&Abp$_PNrVnMD@*D+j1{5WJj`ZPofWhm*`!c*dmwapngmX~; zBm>3kTmxJ{w~UKD8rUJk1v6JfMhO^ zJ``8ATFH~zgh1hvhxk{UQ@c{Vs14~}GSOL}>#05zAw}4q0*?WTTEfP-@DI}0{f`35 zBVKf0!pHicaPc6Xr2l2z-2{~F;dE`~%Y7)*3Qx(`HbC@Bp2~B{gU%%%y7qt@0HG8g zhX9?0TVW-QGdYX)2LbV;dYA5t#;IU+AIf-@;W}UqpeXUFd+Enm9|o_>u)pm?87KNX z2Vi3#LO_>_(sc>H(g)p-0y=*JkQ@eKP&NvG8Ytr>pF4r_UT3vIf%s9K3(9t@vv^Vc zh@Q?L2E>Zuq^HU&JrFM?oK7!JRY#&f2%;w_I4X`sNOAn_KIpELmqaYyN+@MMc$WMJ zL2-lkgFNV3^}ZYrW!SBN=#{)lx4s3GJm{?Z=YpmEN!eD)b4l-1=aOC-FWyzQGF;*k z4+<;cxp-21NxwX6j4j*3QrU>M`c8qa)qlJT_)9>#rtw#2>0}9C?}P4jS%#NqwXxlR z@Rea|w}YU#K~UKT?+cC=c@p2^ql8cPLHFWOI;wUgdOF_^h&NrApfL4GC2Uv*Bs0+} z;THk*7v;UiqmsAf&W`}M0n$&!YkVrh6#f7poRYC@62TjROO}AbN>G$|5Qq=i1L9L- z$6bBUxTA5V1jUutI{$xtSQ;ii1plTFYX_jDKX?}Zf-+2es2v#QI7nv)+r?lzUG7?w zA72Ah|0Rf@0XCMsytfbHLkYyb@F-aPN%n*E&XlK;hq9ZOTuU27{bvd4R|T@s1Pa%^ z#;R+9p+5Wqp!@#{=sXFC7o7#)2k2b#C!S?LmV8LQx-Q#BDGc4K|I%6Zkoq)%+WIR2 z*}8uOlyiMO5=~@AkcLQx|duA&r7dM zy^Q!CH>j1?m?4y9}maTx|WvfY+ z3X_diwl$?w_yjP>lV}UnUUgQS&cZK{Yy`TN?WnWp{Bj?3{T~6HWmn6#*I72-&jGqF z!*pMQbgl&HUT$x*`xC zI;$<~tbRgaI_qAbYlW4dFx87d{HTnwpXG~}P}Wa*|8hWcB4xPh?VW(a1RB3|uRcq5 zv_RKC2o!h4aj^eY-HHAnl=Q??31yhhq9f3?cv2buGa$VxLHA4H(IxOjU@&Nq2VG0| zO8PpBoi^WAo{&B@%Sk5$o#v*oB<_Ka8S8E!G#R))%gaY@ zTXmK>PMv)IZ4*l(qZ8(gmqecacK(|u^zEll{9Lg&zT%?iN^-{WCztY!v!0yr!ZYSs zmM^Jy8!e7Cqbe!Kwna<{k;7GN5mc+Bj%yhOibCa6W`DLq=GmHqE0r{@(7N|V$7Ct< zn{#6M4*9vRa&?6i<4Lz|4ck#;5`L`6RVwnB1ZjA%ZYA-h?e?ex`sQmBYgjltkaa&a z+sxMzKieB|Mjb1fYzF&5(W%_`R&c%vAatbof6}(Ij zG`~52u3Tpxe?n!RdA4O!p1a5fhtodldG`mFC2~%IFOX86%=o1g z%jJ5(aJF1!&MwFCbB8Tj`1>*C3#c9Yf@;9GaX5l@=2*?POz6$kv7(K+w3&K{$AS;C zzG7|24;SObS!b{w_{(!_wHE$K$!>Z6KW{Iu&hosR46I-He(T)Sa8ZtUK_w?Q{Mf=} z8FbF)3*Fkzjge)G`NT)%wy0{1KZ|l$ecd?oz+rnJKN2hv%>U$ZafP^%e4b z10VS1m#eOy57d{u+`V-3tD2+17dPG?hoO#ZKc8RUx<3v+KXYU26GQHG&&-5B9DMPE zzjgGWOWJq5ZuH6cnVXbn$vIq;U%%-En>}>IdpP#YP3^102Pxs9W^wb`4;bO9?#>cU zZsOMb8@}f(k(?$u{rNfen#&;lr{QG+&oStQVl#AB$DR{__mSQxeb;lOE0qD z@C(o9B=^Y_&p71UrY_G|BF~lZg($H|me`|1t1gJbni>1~vA3Pw8qsOQ)~FqO<^}d;fmi%)%pA%fy~t5bo;*=`9?m0xZbT`BxhK2d2#lY9zwRnBLSEui*i>3B6rg87+%g;FN zi3yjH!1tf?q}Pe4xs&)Wh#@1)H~gm;?v(IJB|q1I=TO+QLwkB1J3Cx3cEPM3YyMyS z^4U>8U1~~s!F0@eAr2*`@Q>cB?)rkwZJ*K}pa1tCKAo`7F75&=;05bTzP-Ho=gBxm z6`m)HULDQzfx2h$$}rm+{=guh_M?FH|zU$~rI=#k`kx4Y}sz5npS-BbNy zcXFnUzeraM4bO)O`~1##!~OHbw6CotW(UcunxTyF%QtE-#;Y0|uY2a^oj)AR&AhX9 zaLB#%ciCW~%_!_PDfW{rJ%>-3?I$nP?BS#Ee!>Qm{>`iY;p|lCbg5CV3)b~&#^XZu zmNmQnPwzM#<7XFl0S&B%b??xNvxi3f%gk#pUoG>)A6-6TAat4OQ{qqCzJI~7t*p$qq{&}*qnEge@7G-f}R~J}f7fxT9)K4$itjmkj-4}4_?8WKs z^W7lAUJzR6^JE*V-9Ha=^wF_@cg2fl_k}aNqhlYr{aky?h(`^Uz@JY&M{ju+djM+3 zdS6?D{tRxDQ>2+cy5kfvW$+oBeQW{v(|=LsI{)(p9{bLpp%TN3jFpl&)ANOv*oAV4 zzrDuFGp()Dr@O#)d9I!8$xJpL`P{+_;7^V{%a9AY1Li_=_8eo$SroPY)en*Sl>0+2 z*i86^+~9q|ebNi3g5O47{Qq9&vGwBq?icrWpGCj8T+(8eV!4>J54+II#%Iq#nM3V( z5N_<8?7a-epX%Blz=MBV!2Im@m6vCCHW>OS7qR{P$IcGRNvQ{zoWJR}Pl`UffC0(P z|EsyP%X_-i=Vo9nNa;k>H~z-CRp$bhLA(#-=ecSSX3pD*4>sbTTmAoulguFFFZLEz_1Rz>7|Ndwm5= z<%?3jw(f#Xv*(n*M1AGK6)*1nKF=<6Krhe3T5S!WDK6*#eCtVJXB0r6u1-DWRZ#jb zfL$mzzUq7j*hTVZQqsjfYcZdBB`hs4JdwM|oask${uC?W0}DYcqV&rusSV&YmkUv;V};g#czogB==;*t#l6y`eWv2YpaGg?zW06E zx??fHqVZA2TT8V}5knQr11;#H%2K^-%CzxY z&;RCse@=WPP(N2-OA7HVhAou8q;} zm8+bb4eH`LHo*y@UNRV7BERiNFCOkUY#)Y{^Nb;;zbz6gYXS8eTdQEtA9$7FeeS7W zS(tw2PJ3(?3)#cy9<~u^S`Qwq55F}@pA2>+ojcpZcIx=DS4UHkZRtrZ*WF1Vp-FpMW|tukzP61o64N&Gme49ATM^cD#$@Hc<;FZsbK z`r3XXgq1GHOqEvL#gobYdXy_>O#=bOapj4)E;3~b$+(XrvLAUzWw13YFtB)G6tz?~ z-OwTvbJk@9=0bHTW{K9C|8L*Dh+x^P6U0;0g%Q3a9qTt-uUMVQ1e^=?)JOFAe;Ayb zS&nZz4 zOZ4S-rPipBI8LmDPBls6$}*nK`@UC8 zLZ`vCgaEfEyGI&MvVQSPnMB8a{YPHhrSlKZvEb%t*03}SRU&A-^M}5p zxH|C|FWhz)uBh?Kz|C@(w@XVaPdQ3d-OtQ_;WlJEihMn%I=Y5rjES+&pX zy2w}10xWW8f|h5Cp_?%g-RJ1r;;N4%#9Fq#_RUjFQ=M#lk~6AUoBNz{hoivHkX}4I z`mZjA7J#814^?WFL6*zZX^?4@9Wz5MX#HenUAYCv{pbGl%J7nL}(M@1167 zw2I?~#gT-b6o7Ao$x@T0^};j5P$?;fcPGjbrlrE;({Q09XE``;{H+un;osT{hgNU}nABW`1;?;H8klmJ`1xJm1u=1CDriA(ip;QHVlgeKyeZBt z$(P!M;nW^AM4;jK!2XAK6KqrE6dl))qhw%?#WkH#fyD3gncB<^4B!{LErZLjXJ{2| zr#1iIKI)f^Mmc<`(uolBWgl721)w42rSBBA*rHD{fhHn#eEwRu9j(AL0HfPuD{6um z0ra`o$>57fWfZ08N5N25W^r{Wh~0QYvsT$^kfnjWiF^_b-yOR0&tAsxBRq*Kneacf zJP{hBQWdILa-l4q$+@oiVABYcM5Eb3(+c|H52J~XD6eYAv^GPp2>QfHuX{l=z9`=)&3_$7`DLn=WszyR(^WZr|VB(cZkXy|t$gHH{u{ z8Lz|Pkd{G*Y0)Io_6KfxS$|Gf?*D`mpwg56 z!VRN>%DWJs#I3OWAFJmS(X~bcyQP14af;u*;0<40ArFCG!>#RV4;{EHwwjxh``sD* zs?F6|EK`&tN!-I&-{bM-cIGxJ&CQKF+qK4_`uDyvy{C?&XT{jaoAL8vZ035nrrwGZ zcW7gBpWDRAaar$a?TGz@0Up)C`VhlOoLrH)!Bh3j*?$=hVffk)4BMgJlTQmYzbB5p zv`{B3WE=~OagW0Bv8zeAv1%L{PZ|q9`~(bmaiagNbw!X3zbnIw$TPT*6Lxze#`Q|9 zF>Lt+mSx8ef4pv8feTT>^*@errV5}i82+MksIECmAnsJCXq*A=VXXLxG7d@Mm5jxz z0g)C-54OFyPdaJg6DQW28%A80fNsEZp*je7{0n{kS8-KRT=s-&P2?0JWcu6%vRuHv zA)G*b2zICuf@+Os5LaBBVwCJMs?C-6LJ(3DV}-kv9$Z{E!?*m6zGarkHKl|UnG*A# zbV?yZPg1v%J_bHb7FUenV+08iuai_ff^BQ7Tv>!n-$aIZ)5qY5HyY* ziKS@T=pmAj;f|kpP(wFFKhvnq=ndTXe8wHk)ep`U$j~whezM@ zvO=GzIcZOfC@71{W0}e|;--2fb=Wa=+V?jtd7g;d6vI>|rI0#3iMQ@u!(l)5YI0Hb z{g?57NkLlV=MQ~4wHb|ds3!*kzSmZ}bBoG0R+TgjY7_YK_ zV~qxSC@M^%Acg1v1bnpky-f~Wj8)w=4H_42`0#&=?Qm0#*07>6yu#Y#-WTR;?a&%) zsY8RA@XFuS2bvgvqGZOQI`7=#QL@9ik+rlfWwIkmGGy3yk!5!P9HY#U3cgngp&Xh| zYSGd$;VN3?qcXcA|AgzNjyj5>2Rj`6?DUJ?>%uc8X3nP+q&b^vGL=QE*&gF-?9hRc#T^UI(1RUB z*tq^DtAqFFb*-hX)L5!~fE`~f#V#oHjn1~foS1GXK3r!&^~PlC(Oyl@K;tD+dJ{6D zZtXFShdy5c=X;5Pf6%oyX~=D%CK}H#IsTKMED(~xEjo|^)+71>kVUd4i(o<&Xz*iv zfG#5( z?T48|A<`9?1URJ%x2#8gqrcQ2RTxjK8paG@3?PZ8=p`{pfSrzX$`Y&gif%lXAVjeQ#g%B0yJgYYlyUR_#q6P|i5ke<#JG6m=zqMkC_!wgwx}18 z-G^t4c?3OA^X%!~Wxk-#NOO%EQaVvA*lW0d~6D*tugH%5!Ld*)jk;VKs-;KpISke7& z)T(Niz#z(gR5_inkaE5;)>nQrHPdh6OAED-eBgqDG5{N<%1{&Z$X1N!V4qua0`o(d z(jB>asQe;8V+n&N7kdNw3`EENb${WHURHWY+9GZV4y9JmG9{o^`a(1)=SLnhXPT5p z|6p*|98SiqETRUE1|hNiJOhQNhc4t`POFdKJjvYFMCgq;BhIDncsL$D%6O!Kq1mLe z=%UBN1w;!J%8*6snzz#|9(?mlF}%!8Dii3oe+eh!VgDzrVeFXi2qTsf)dKE;i<9FP zLh83Ye9>@ReIl3$-L&rZCW3WlSubI|ZcCCgt$9Q4KA2oJ~xQl8{Nn?9_E31$6eVBj6c+IU}>O;=mx7?@|HSOrleucqzEO^ z(ApnzJsL6*V_ntOoeA}i|JqbZEWlUVmaMg#J6!p=(Y0-4i;)~94F|j>XfX|C1HCcY zMJg6;Bhmt?WAT}0XoLlEZVGb0c*q$Js(5Nnv(}5ZZSnAa@GHzRV^X1HNy0BM4sV|v zWaNE{oGGE)hRNbeDO#fr0@TTn#9ZO-%}sOLk4TSy^FySpNmH7gJKgbV*^0wS&t^_1B$?R{@0cGT{QDx*lzA>Vr7{{RH#u^h$UE1 zw&H`=ec|&aQ~VwOnQKo#H)w5?5vss5gWD!v!gdv7QZW@|2Ja?0Q8^edjs{U2+5LXp zI0&ZQs;lLHUB#pzu}{y#KW(I??)*po8s5+}-`;G;zO4D^1YwW^Mx)BYq8-Q<5L?z^ zF=7CmxL_bE@P6y>2ZdU&mB<{n+-Vu^CD4t?sAgmkrv*S$B+ElTl+)Lq9diP!i7^x> zaP@YCx`YD71NT@rFXQ_+3ZL|F4b{l{XHfzq<3Yg?FSIzp)tR+2<`KQTpDWr1=! ziz;A`$4N<5+MrA*CcRw@2UHRzMUbKa1uJ(Gf_(?_+wse-`Rjh#>IT#u*aBo+2u7&- z^~t$IoR&|gO(+M*7Q>=0j3kZ7ax2bspCx$f*8Cr>Zx$H>h(*{C##e1QCAJzQI#wO z24n*tnUF1ja;rB#+(;}9@N7C@X5eREO9GfC)-VBQUGHMTBByC(lybZvVC3M9w3D8# zDghVJ&!N;tm=f*q6HYZQLYmpwjTLo^Sn*75H386!8qo8N*Z}EjCC;Dr@cawikmXwF^{8T0s3M)W}%X zS)e9gLZiFwcZ_9Vun%i(2PDZywv2x``1czBp4cx%&Tre^wPhY@NZKc)O z5Hr*)>&hQ`SrWvkpy}|{3r3YW_{nQmd);o;$__OTHS*g9mz2J6tb7sFL z7}^;$z0K5aOp!dT@{(KV=@|Ni=s;qC16_7eG~yrm&o8;EC5m)~j5Cqbap+DHN;TPQ z=D~ta1wWpN%!0)@f z$u8A6#_cT@Iavf9(-7@V<_H?1u{FV`y;;?2wq>>_8}hW8B(-j`Dw|1~$0mQK));bP zSnHoA*I7rs%J{mtHZ>a5rmhZZlk0-)=*rquccigx7FTxsZ<%9(C5M9pjoah*eyg%%k|d^B_jSpL!nugOY{O)Tf$JcWS5A*|swnR~mV{yRL2f6JdbUOvcW&TXbc7;$f|n<43b@jUQcJ zO0^J`{Ao`7nBtHyG{a(+;b{o@(Qf6IzZ-vgm+N$fhI$jzJ0REj>2Q2H4$Nxi-&iw` zb*tmEcRSH)YP=f+w|dPuh^`%KjZcp_Y`3j6cMVn6xR>6PPD}^ZRdY?2$t@gY-|lEn zF1rdkcW&We79Kf{A2HP~7aE@wRxUNVcsR$Sf5_@gCF8S4CzJWPBjblerUf?+Q{8y}r+;|6dPMTWCs-Gq-_?jTOzp+V z0k$Ys>HUVLOz2|xbGX&>|KiCPJ?Mc6f#p5u1zRl3Bag8+&-Akx0QoU=m;>?E1QZg$EsZ%MDA2i z1L{b7OV^uf=Lv3DmBuK`KrWJtnHzK*l!zQ=jngdjlx33rW7w7JBYR&xSuOec{jWAt z-*k9{LaCdv_$P;^)Ep19vJu|iUBzbJ)C)OX8NRLkAia-){pI=<--q6Zs? zaaY}GjPY7ydM;l3#rN33T>P53k+wH^(|B+ECM?R8BhI12-uNNplhh_#ag(LjsRwKA z$8tMp=0lB*-c}4Q>tP#PW)p=??c}hxp^;--O2D;Bo*+;NOm;(Y|73991Szw5cc-C$^s?2q&-Ujw;T|6|EkJ&Q_ z6Qe55AebHYqH5-%fE1tRSi$YesIs}N<4u8*@iVC=sAp!J%sf6)yT7AXr&Es@lwWa1 zD$RTZok4jlY9L39QH7@~Y|>;F+oVAZ1;Ruk&$ZlN2wDZStRuClJfk)#Vxm;4BZ715 z#{d4EQa)Tc$wU9d22^k^)T*6KdAN!(jW?qv=pB~Ym`%CWcjLN}4FEfR3k(#u!j>>S zQv3SD2p4xz*l9(K*%m)!4rEVAZ@f#q2sJ5VmrmQw#Ri+nh!UOfWkLeUwI|nwlc+`kxh6d<_~4 zSAN|=9E@`KB;yoKw)kU~N|O6jGUyW?)xtL&|-a)~TpK|ICniS_YB>tf;$Lj`4bD>0Z! zP~?potGGsWlCh$nsO~}AW1J0BrNn8&f>HRAR#uEMecF$IZdDI?fcKDO?Z@OJDsq~n z%M79I8H2DC*VLq`IL0in`gRf0$BdKJH40u*@~j)5(S%f@q||B~Rb(7Q_tp853a;jmdVF&mEbm%q4k5EBi_J;;-~}1m0_cv58Nx7(BW=uI`De z3B!!~Hp>sh4$?soYHeA0m!+p{e8@|i{j+dj5t zUgkZLP5e^g-JE^p;%xjA(bPkhiBNfp&CP~LaWHC>8TzOOo0;$Zr1QP?PIbQF?pSNb zJ8%^y-t{H-n78Su_YwED1D7RnH+yo&hP?;YSLdFTGhOqh5_jgYhw&V4%O>_*)m~G- zwRLn=^uZ*#vmIUhL~A0P9iQFxvS{0MaC5eqBF&J&HQSVDs_sz8OKI|%>V|ygp?o|! zx++VKL{qcuc*eWPU-ABSW6!p32X7xQ#kwJ%njK?Esohhz)_Awn_XiJLb5V@198)ok zUvod;dCW}AOzqvVHuhLNzNP-;j+!^@EO5FdntHf1^i(!6yT3j&^{|z7n5JKKpI3LC z@!!F>3if6;)H^wfI$W=^wTz=RV}3DH2uX}*L#Ml%@si|PV3giutVQ1Eea5rHM-Ht@ zw`~E_b;-Qv<+y#>(N!R~YMyiJ z@Qmloy!|cK8h2Nt_r+Ozd=`1Z2?d-@#+>C1l9A?j&gNyjE~jULO=?6pU$Z>3VGqw4s> zM^`adfRc^TFC0NI9que=Dip1FuP@H#{HyTQbC=QHk#&b8}a ziza+*%kacKM~7C<{At&7j;>klbY2$BRCmZ>%d)c;|bf-kQ#_O!)!D8l* zVonY1@ORyryV^!nV{m3Me=t4^!CSqfD9_Q!26Kaw7+bF&wsMlp$|jugs;&3EUt?8j z7yfwdu6B*eVK$@i9P@mn;>Rnk$rhEKt*_KpJBJ?joSTCTC2CRahZ(W){Buh=y9`LT zf_9Q=3XhuZR`$lLEBRa}bD6obVkRb%MQ{Jrw|s|LcBiTb_YbI_rr$>2Siz?Qn7NY; zc09_Q+OaiMO?P0L*7Cq^Y*JUtbI4>b7xK$emrJe^^M$M(*{$XiSwoNgyWisDSVNCpVZM>I_iLN=kSALh_A|@RhBTk$mo~kX#T>&Ik!>@1sw~&wO~>+l$h)?rwg{xx*W}lL_Ty zm*d{r_@TfnjzbSM-jxM&Lsw;c;;A3bv-~S1CevdhgcY%KO<%kjDQj;GF+t?Sh0F`JV)G$Js9Z)Uk{3qVR1I zPNyAC9I{v}2fwm}{I?Msa>Uo5miD_@zA1t}vge zBsJ^<>O}r449bahw`bNhe^u<2m1dq2{7PCen3tsJx1}N!5wJ}3*^e_M;&n8n!K(`~ z3}l7%4EL2zQ`0&0x;gc4N=Lts6VJ^Nt>;O(waiV4`hF^R@zsT6~ayfPA3tVC;I=zgYLN}11&Wr0FX!+SBJvQ;ulLr|7)3-zCu?8!XMXu**&n5snv$IH?mYeuEiW+|;VSIEBib1|odm=YX`| zp_1&wKP5gf0pN4GAfA}1#8aaXn{6>l_j?*XANc|noY{%O5w=7NXAoh%{TyqUvyEdSV>e;E$HU{UBV#3rn4+w$ zq)d>I$-%sIrM9Jw@y1e#^*UQ)1%w%B;Da+1%q0Q<laNi;+x8pz2?(l!NxkXd75 z&KLDyGB3B1-A=gGiDrAfWB>9l!v}mu&JK2{F~%o{5-Z>}ELqcYb2nn2L$4mjZ0>3L z_CA;L22HC8dS(g9D>Y*lP*+gG3=#FBh_beLu}T)VlH6*|Z~dw%y`Hbo%rkY8Lx>sN zSaVfD#J(%Dfsj|4Km++gL%0A6T?s)db)`g5Da2Z&LyTm# zbupcpfu^aV{tfc6AyI&E7gvxhkkghjiV#|_{(+aMD+Jg-z!8ySwD~cMN=Sm*3~dlo z&lw63Rk=3E#B?DM?g#mWCv!`5IDha@s8q#oXav*(T(D?zF@k}1Gq7dWOQ|?OEI2`d z5sUC36U71vDWzU$R3%BZCI9iiuliMap<;z-bivKE2!zX{cO*oW5nf0WKo>Vuh4eE! zXeyn7gvFZ$wyk))Nl9d>N5?qi|zG?DhRBhCn$ThX`|4+T5ne;hRf_-WO0G=FuZE5yecqkf++b^ zy;04AJ;B6#-1i1Skku(MZ^HPo#)A!ZMmK9m8e8Mb8`GP4SyjL*Najo^Yt=?s3yD$| zl~A;cGOM0cY??jTkm9PXPB>Q^`}^r*&Ef%o?Q=oC!Sm~F$4YK>qm2#vi`bo67dLs; zO53Zzw#y~vVU%J)$5c>36%+$t_@Jk+|KiV7JKH|N zWO~#7gW+B7w%I@0v~J{!v+iWG*yFcmxHFu8AitW??Cpp4dGW5{2fd-UGnM-0p=r54hg>8Og)uAm;*17g+t=2x8#FgQCz=LPZ>2J{rL8AAZaAe+} z8Dw5`!n14B?M5p}z`~^eOj7y0H(Q;V?2fwK$-Fi-)@gp`?_S#3whk^U%=?O+Q~?x$M!la7@-$&P(c1y7L*MW#V$j1gBgI6 zeww^w3X{cpMoi7<{^G~JbNV&!DVUgMTj4|6*_b3H7g_egcdnb9|I2S}4@QQt zlcH_x{A219`){UO*=_TDSXOiP#EpY>Z=~^Ak0%Hl?o`6mx3;?>4J?sj+uIK91$5!u zOp+zcn2Qg!1vLqjx#%6s>m!=vNUCAd$(_!1N$Xj6WoKI$c$;k=zUT!LO*Z)jY!y80 zcB)akdIO7y=tSEYj)xt#$LWE!#EVw?=;V`n*$*27zu4pzpeSxpcI2RE*64uLLiDdo z!-sCzVwiC_gblNy#YFu4&;2S3E$t7nAAC^=p^qqq7q~yz3C_PNTu2 z4^6x!I6Q>L+!l~N8xKhkuC-bHU{D|5xr;4u0m304)e^JT!Qw^1i+OztGGUt=Q~5B; z&Oj{O7z2VVhVqN(v6B@wq#PqI@vsG}Hqlx#S zxBqP%{pnvLqaXaRb=4fZ7-yTQp8lNPwR;6=+%UdW=ch&rVeqj5o%ngRnCE4h9c?kfOeJbY~ z-DK@!aoyl#6bz=xvCrLh@;1R=yML>BM(&>bx0(m-?)k*f|I!ET?!3NrfBZk^k-ufO z3I5eOOj_j6JWQgddsm*c9{KurunW&c zn)5J-3dt{4WkJ{)p)}&5!Y|Rt3a!|H3AZfYWql5-XnUMnbSzf(xj!#rFi+#!onGWI zVa(nMriWu9kSj(o9;f^8O=VLNEs%ABbN99b=erX2~IH z+J$|YWVotA?6bzrgg#c6wZXhOkGRSU9M(;|D9Lwtg`Hj= zliFeW!Oy*P!ONiZ-Kjj=;AvMJLTps|Wn1fA_792g)FuU9-3?yTiHAH>n@9 z?9_6pZK@>7?I7ym_s=+N&x|X9#F9=lc|i-Ka#MFrcK)o?2BbcEApnx%1m)0NAtWyD z`%}zl-A87XjYNpd^gCcCPmpAA%nnK4u3b!(l2Gpt@*S0jNhBI9sW|vVDZm_cU=hce zpL^JsA z3Ib5$HGO`t0#?(&fPMY1y~Hn*Qc9C=uBaLF;G5Y+k3O67(p*TAFCZ8Dt;7mr^LAN3 zEK1|UTNv37T+0e*ZXNbKEv5>hSzd@+tBlzYqD}G+Gxb+@Hsbj6bzRYQnWo+GbUnu_ zE3nkN8S9oNyAGkbq_LR#;BAjVPk&If=3jBUxD$|1nA{@*`i2jgWPJIFwcFQpxideQ{Ij5NtP^ht2VbOB(Vb=5`j z+S5Y4Ro5isb-cVp5(m$E;HeeVE8E*2^3WNro%(h}`!O5#^qzKhAQ~ja0s4NipKvj- zR^b6_BNDjvRf@GZvB7S8lj%)g{i$NbtIr>b0TC@1Y6R%-e6@B9pkP7H4A0bI}xo1ucC&k$$M3USoFSvM9j_C)( zIJETQEc!vv(`B{PbXw7||M9jWC6X;J&?&?z*P5m0QXZwo6NC&4BLEsvCEP$iYtc=B z7S6dg2ceqZ(eTfcA4kx$!_;}cUi1yQqLO8vfFu_&fA*RD;=XZ zYJYr9BALpMczMjmkcYf{kKJJ#r{S`e_jpBbe7Gs{ymBv0d9N9-5>0#I!GKB%9N!)e z!}!=AeO@YIdAsL4_K~R=w35qttuj1p&g!dTFJUq*ug%64CavRSF4-F2+2Amlv!p3I z;Yd7IKjQJ8)p&LCu?9>2$z2U9ITjyjh@1Ujb6+#cd%cZK0(#V?UL8E#+a2!C!cfh2 z{?C6stv->l7tN&%9>WOMl%@-`S;)MT5sR1Yu{adQkI^O`m%W2|#ywAy=L#O9kBa>X zb`ut$_h5`3M3?PzJnY7ke?td?xYL}t=PFW8jL#& zvtZ9M_L6iV9#^v4Vq04swX4ZvYod2sX5*gDT*v0esaap2!KhW($yH%<;2|)v$MKf> zoHhuS56Go%BM;fRKgyYkqDAPHB3FF8o*v|tlC3M&+WR+J^MA~{ria+xNUyqgVvG%7 ztP#zuZcfa0JT~R!a{JA9J@PfHE$WPKBxU00HoZ}B{9&e@V8&)&Wv#-z2Yd0zHN-|T zH=j$WOI&-jDWMLNBxH(ZG;BATRIKH5P?h#RUiW)Fd$hOP_IKO!Kd{&8vFA-&+;&eq z97pQM_r~6M-go}1ZX7?6#j7GDV;+~}-ks?h?{ZdLP0Xg$-^?m~Vk7#iIp)2`*mYH9 z{~@x$ag5*xV=zftaD?iqQ_|9m6^6*9gY%ly_Z-i2L z>t+~WjnaEm58n}7YtR4TPczi)Rs;8PDuo`Gy00d*^DJQ&SZB*;R>zM`oof!w(#v06 z9P?XvvN6+UQWTgL2XR9`hED8Nr}}%S_qcd5lgs zKZ=&_MXQ(y^NwheMNT?Qb(+2QWD+u^Qjv~86?S@#&kG$x-f24QVB^kz_}z5PtSng8 zQQZ5SwBrx`h^D_Z$??T*)xCA~(Tclfb*FNhdLpz3`q2SqG#W6ok4Fg+7$5hDC-<^> z)1p4R78@5)o13$&G5pq9Sm7x^^+Z*(%XYPHS~NS~!4LNxx%IrFl~xqfxjp*(7$Um^ zd!Of~L7m-%ESH&At0Mccs<#;n?y4-|WxVK%>&2Y|OtK_gyqB4Sqyn0F&N?!ur&rl@ z%;Xw-8naw4XT^$v10FzeI^8A{=J`SNyA?(mgImj5f0Kh`#%7UDZ)b*_=Kpw%#|_!r z&dw8XAUkFTR8Y$d!}u{vXBUW(ol|TjT$rl}DVT&CWoU##&Hh4*_RO5xvH$Y^lV=jn zdeaEGvPx8v1x4vq`Y_Q{e;wyXprFrkqo!77LPXeqr(-GhJnHTnZf0mg^`0WFJ zRd48#nPL1GM#9Kz**P!r*^v>kJG1FKb37&ODP#K-PX(|^(DgVB&0=z~tFTC9g3N&` zF@Oi8m-k@LpaSNg2GYwyx=l5g#^aZ1@A2t?8eIx$MIkBmEtoA%I?liCniR_jWoRV4 zZJA-4onNtUXL3|{JwNcjboeN8&F7H?TcUi;n9KOVl71Q_A=W+n#$8|R8!GAmHq9f{F3e7Hyh0vLf= zVcZI>Adct-C<(T*&Z&dl(SI1r`o9lAx;ooJf{bTk!@O0f$hge0?o4Ei*mFml?rXPwX*_nZJ5;?y zDRcXkL3<}i8wJw6^m3cKx3|_`bU4o*b&p^?ys1^6%P;NvpAAk(*(VQDI*L8^`lEU1 z@3}K>ym@E0`{8gU+fM)l{>H8aZ_{ekuOJcVRxQcSPJ<0?p!Na(|sbIt=wBblJ8+I-JSbX zuy^Gv542| zyiN81Y-rJn`fJ1b90;Fw!KqOjHHJ5@hs5IE?QrbzLFuAi_VKs~=NQ!WE*3=VnOvj&J=9kye8g z+Z^=JR-VqWy}->p9$c+veC&p4w~UwD4^_6_fdihmTiV9E4+}lfIy>BFDQyrj^)hEe z%iH9QW@@%+Ti-;uCBTk=TS+h^6qz1>f2_hQL0DYdl9%z@y(ZF6vmy<;`%ekgUSN(gSYqG&<#E0 z8t&JZJvjG&E7UhKMG0n80=ehZIx=A@m{O7V{x!0QA6bMj%D> zt3&A!A`|r43U?G~y0jO!HQa+Qv$+yN-*hMJs4`Q?1;IjFjqWLcFP$J)mrpy{ z=~{|Hu~F_YE$jypfc}Q}^qa4dJYjGt`6#irfzh459i|CzT((kLkWRCRtpZ~c}`&E;= zWCbpZN<}lYAKQnTX~By)6*LHG)*~c@V}lrr>T44(H;E*%g_Nc<)5EZe%8FK$#;pY< zcS3|ZYL_}s$7bd>!E4E((V4zZeIWmju6cRSywj0Tbh4;0st6R^^2of$4iEag%-v(} z31as7v}78&sXOZoGaC}17A{{NOm)Zg{(!rdAN0a7FtarHPcUGVt@$G>c-b+;EuI-;H^@`<1D9D* zSXnPU6D}LO``WkEGwb&~rjcX?)0EML zR!y5q!YIt|Xj`GT`6Xksu=Ls1+PHNPP1wzx#(}l<$c7O!8}vaXUT1WBK7t$ zuS83HrW7}$m~3gvne;IK7#Ymr^6F`YIpkGyNNsCWnIJa2qL3e-ETZl%;Wo3O!R!Rh z+LY5w-LxL@UeZ_F{`i!t9!ZQz!?41<1cNX?#!a+M1{Bf!#9=>&sM(r=QWe6lsX&C> zy292`GUqVA?gI`i}^kL||H%k}?x$IvWqJeu|Ayj;BFsG=MagE~vd z7dMvG(WVsTXejn+>%?gCKUW*os^DT@WQlGMLjA)Eo z*dZqf4HP7L+kZH>S(R_A7a{XRWk#J_#VO;8de3n}P-W&*_-Uf0|8TA@sIn7*T2;@$ z570QI8&q0Hn(zE?VwnsAN;e3F+0L*B50!xk8pd)k|2@B%iUl8Yh<`zv$>J$(CsbML zOgVhJOQbx`kbfUFwOQIDb%l`}*D2JOJ+Z#_yCm8Kt05|FMQj=P;@?z60L3cXe$jiR zA}D7KP{W3Tf=cTLSH(niC5qG$RRIIEWF(mX`JXgr_>+cn5VPz^z)H|{T2ZM|)rfAX zh)XDJy3+I+6>!2fhJ@@Oh+55I^CNZi?NS(;0^Lp&>$SO`Y@hMhhLt+j1d+8~& ztQZyAEMY+aWP*^w!zLaZt`+p*SKbP-*@7dYx?TRV}K zXk$V3R#@o)ci7?US1LQPUQuyY_{c5aDcet9u??KPk~L;1xIQnNo3ZMKoC|_x-58sV3n$ z9DUT)XFndbtTIW+g{y2Xnc^eBsCHqh>rNvHg6nbwwE|Fbj%-}`g}*P-x@NPnCQJ;# zI`Yxwh9(E7(g?9+2~q=wTX`m$7*U4dkXV!t-BaCAMQDW5hx50+Ms-XepbOjD%RpS9 z_8C@us?Covh0r{c{o?exD`BrFDr@T-F;o)94va#_I=b;>i#t?fNSz;KT?(FN*WS7t&?)J%d$ z|GF=RK3>=?#6v6>Dulq`QQqPfhZmuu>!2Y@v7wLj6fMMGd*q@b;lPo2(CJv7Yt?la z2%wP^acv4J_`T=_jUp{*iwbf4fccMqst_aBh0>79@M*Xvh>dHQG}K~lnLO%?LbVUw z!6+76IfR(_LNP%X&cEwxeo;wjQ1I#Z*(Gnm%Ytm^ZV1GMB%?SZ9tuU_%^g%t1m|_f z{@{;`jHD_g%Ge@#>z-*ry1H_Vv#dQ2f;nr!y#X}E55u)t(U4MgBXXIHsEq7IX8xak z0Rje_`b%9f4w~Uo<2}Qqp9TEc6pUfWc%`Oqq+PeG^b33GMU9|Tp`N!X{W!fY{h4W7 zEq!5b_W|aG)Rq_&==xOW+ubYgW{p;$iBp|@x@CFZ`a`hLWKM||x!d*wdI@IY)>T7v z6Y=>Enu%A*k@`ItY})9lqa3yAFd5>QNka=5sYkQk3J=3m@+C*;toaD#(?H{63TsfX zl)`pUz(C}k(R#%xXxcuNvH5kJq{kY}o+cTlR^dT#ZK zJFuId>S>e1sMBnZ@*y8-MA6}9h?5w+NH!#lczriajd|%dA z?m>DR-}h#G9aT9evrzUf7rtNb+}$Z=Q4T_goq27;F_YxjC{u@?nYB<0fe_VVg z-etfhKz+*yf4&;NzBQu*JX6KSt>!q&W(GK5BTM89*8U>j0a(g=}Q^W6Ne+s>%j<-OAbqPa26kxnH%DaLj za|$OlH0q+V_3KMtS9-&-m#JGrM*WYPf?-Z8IZTcfcCp^Q+ex~K~(Nv$| zaxa1Mhcluyp7PEgc*6%xkt3xlyk1#8`*w1RuRI*u>ANy!1eps8>FS~b!KmFL=gxjk z6~#%P`ey0mFZE(69Wg%0a4!9n#Rl_XxpP7aIi|!aTXgL5H~sJK z_+HSB4egV^0Mx!qdJOa(ATt{3TEisTr_l-v^mdQk19`UaXVu=*+rtZq_qW@G(Z`%VYq;i9^f@gVx@nd%h?+TcW2T|JK7?p1 zS!QRh_ex?7dh~^1+>BYYOYWF##+K@3vf@!&%Cf&n0(WC*bxDSQ#FGWVy?^Bt-1$Wx zP?U*w;TyCfC+k6JzyM}C4qX$?jRZg|M^zC4kh1?t3C-3~|4U8YCKMWTT~kjKqCljC zBv%mq^Wiu(=+&hdb5Dp(68M+3Nn$@E{d?49FlqrQX=L7fb2QZE#R5hp!l>Pl1gnV(ZE5NDOmUfK}(P>xCDTp$nLH_I^yD6=?7#Syj2p!hHH+ z3WWlM`G#)D));${WZ`nqYe{B4>&0S0#lk(sL{pJp6JCxZ5eXJMG zaKNG{bBN)ZR&5s1ntG&ox!Y=Gt#oJ47)y9Cp%(qXs2Y+IV8*>C{2;YO8YAtH2>d_7 z=YM03W@1=W#n~nUA~h35m{~bG<89w^p5P zLjJ&|Qi!tkqy2?%(xPlglN0^6vU4Rx@fD*6LIzX$+@VlJ@MHk(5ZO2wgal-Y;h)r$ z@Y&yECY(W&l28V@=zXrW5J{3O2yI3KCHFOE^}(QCxcUEid;jP-uItXTx>$nRwwwUP zHqt>9x$2?VF19F&1UXs+n~l339-D<0L{hNg;c9Yhvfbu%Fi9*q+>DQRXI)kO05z7- zh+;T%lsFqVT5W{MC}WD@@$qDm7^EPZNwmk3qhxhvW=|-Eb~2gW3B@RmHnTI{&#MM0 z$OrAPGS6K}kSmt^fz zc9c(YwdXe6+T7hFA>|y~B7hciJwzq*AvRJ(!&|L$Q^xq_Bk{p@$gmf;Cwag@QBl(i zQjLqu6eu09SmNRdd%VIetubHLMvPL^sNu-g1IkeiUP8Yi0ZQnYiMIH}y8iF4C2)gl zO((b?SzvTY8}rDp>tm@q-i`8&G~`K=avut`m)5r^hfRVOjojzbWZoY>;DgokjTk5P zA3pUiBS}W0%xw@Ml-f6U9X_}y9ZHk=I_SzxWOX(cf%NX;FF&yB|NzWKrGn!fQAv*qy{X-CctFT~;Ze=kok z4*9)qQl9_4`A)76>2U0GcGFh=xY?cID~RKR(bNdQz5nU<%uSA`Q0T5=UtyZ-cGz#? zuB0p*U&0o9gw7a5Y$_>+(}=1jwbxWMF0N!#a0BN)vsWP946&I@7$06?m>4O+Nb?56 zV^(s_vxL+cgilP1auqEod~R@uNvmVAxKqIP8-Rd1h6t7s?eT8PoplPXG2Z=(F z9!B@E)O)aNb|4f@oWX2h_96`b7mcrdHDxwncA375{W5Dlgyd3XmSb=IC;I7|p?lj~ zZ~u6>mie7mOp;4)lIro}!x_Ku1Cxh;^m~Y@O(e@Y981Z=_2#So-uS%x4YCs4!z*J~ zvo)Hr_OmcOEa#knC9<#@(5TsCSO^L}(&vF1Zle z+QgVMeNl$+JUH)*VRX*xeP;>JC%LSgU&bYW{C^PgFjxddITpc~nM$rtFg>$boM(@* zQtuZi73}8M?0W*DCs5#gZ5n56sJBFJ+!f{_I>YBCnBy(tHmF0>dIA+pGX4@^`Bpfw zE#c!HOZGSZ^eJe7Ipk_DF+3=TSq1idLkIy9f|C{=DYGwu%Z-B+6?w)h)Gc3QzV(OC zZ$0M|bAx>OpF5hH4_^|;C4G31lj7a@s~_);WxX*xge9ya@@o++TE@=jf$CCzTh5X) zX>D86lx@^wOZ|tsPro2WzyV0eIbw_hJrxBHmY6l$Quv3@QQ9C6unnipa&*~ZTYlGL zT@+veMx!zG)^K6w_pp^Nl7o4^iV0%sA2nG5_$k0nDY8GblxQRO9p0MXCV=J>6Q-N) z!3*IB_ec7Y2`1?n_0F}WowMHO*XMXr^MpqQJ2A4Pf(We=x(VM~oTek)^F^1N_F2`kA{jbdz4f^sQc+9-8}KfB1hpX0oo0=kksfVs18Ev&QIg@a?}Ptk3k3g-%JTmIRT=)T*T~HR!LqScAb1cQKKI^?kr*7f_)TJR zvT~g08x73yZ>G>xcYJN*KaYh^5^`M43OeLpE%eRq1w0@Yrdf|RaRa^&vp;^Q9p;(( zMn;X3V7vv)64Kp7wub(-0E#lpi%3^@TloDqUaA=WY=dvyGco2S?~id&&~X~_OyHKU z>E%ifL$G?Np~f#w_{&vH&afHX8IofffUE*Hfj~Ezw8O7`oO3V|46TPjK*~qs>9R=@ z#(Q7chPPb{Sv#nKiQ%D)8qdY7X{>;^@t_0wjnaIS^0rN%xP|CRGjs_~i|`;UDe$)F zvi$N74jQ7F8Ado`hqNWKcvlLdTt3R>9L3OKQ0*v>|A>4gZRVYT2X;~lO(}Q`JMN9m zO)6c(VMHaP=dvd~2Vs%$H*n~_H*iHMt`$G?*zFzL-H0vsm|nFPD3|c8D(ILK);5As z$NM|%;tcKCwONCo2*nr6m2y|IG7OT!t}b^%7GrpR7fw}}OlmB5mE(!J1#m;CGhL5I z!x15R$9YDXDPhONuuj8{Awhcf`M{UuasiUF*unIK84;3ksw6MD@ z^eV{~X7MeLU9Ci3VG`Pdz$OS-Vv}TmAX#R{p!;xSR``3rV*+GCLd!c_YG9#UiPP1KQjbKk zt4hYJPPI@8MCP9JQC8a2Nh(8hNLM(W0RC_bm)Eo!dPZ9qOZsR$(_YZVe8eb7g0j$W zPdhA?A;BLFw;9M1ho;2%Q4~QMJ=d|JaUV-dDl)MtcF@@1obb`OJ0zaWNG>&TEH;^2 zc_;?I_-f(^Y(VHOJJv#i1c~!M{+`jme4R!jE8^@bEQU^Rn+*ygY!r}jzKHeTFj$i( zqN0V+Pla(Aqbs+tEBdqbocn=MI*{rK#*FVeDRL9nyS_#g-~TJOnQ7KwVg%<)a8H`L z5FCKzq?Q*2tiJJ`q(kosL9HHpMTF@Y=*SxSgOG$wLG&2=ro8~9(|l~yf*TRK0~5eu zr1C%B1)1e5af(jI)+k3*IhKZ9^X%;{N9H^1LuV2pLEfNFB<1jm7}r=316d3wInx{S zGQWu#Lx{7yk>RI5c^_OMWS&NAsfME{4?rJS0k>ug^T(t4&zp%F7IcVUlQo}ml=GQy;O^Eq^oiy+Wl!@m5bCEB4;99{x|H2guyNQyCl z_9Opt8w*ya%khfitwn5v+$^0crRr#`mEMSTy}fjoiX-=GRCz7Zt!VRw%XhBI%^%ix zh4*#0d44mct7$WB6s+m;)g`pTjdz#Jm7;6bf>$FU_n!=>rpl|}DngHkf0Sm=g%bjpme7B^oiSapUqmeX%?!-U zo&Z^PjpxpcUOnDf!3yUHTG9_#IqS<_5VpNwJxKbp?Frp4^%m+~JB}BU$z@^p+<(0* zIjUdm5+}wFKh%Bv&baaUF?GLUBm46Ysm6{+;~!J;(wlLd>@78}Dg9{aWi?Qz+=J1f zIIKQeqP(5>x=QurHY6rBDX%PEbBITG5R`Q@^n&sHJ&5`DEPa@8i&0*4}ALlurAHC*OTU znUi4}R5y5`G5FE)*x~xMv1iNMe@s364WDyoDStch>{Dy1JMsFRcOFuW;Ll4Xc4hzh zouvZ z7qjql_vTEN>Wk%Vadp}5P5$94?>eHqXUl7f<8T_mVC=vfO0ntwfO-0mBIyjy7Tvo_ zU)v1yz7i|thcArp`tSu_V+G*DIS;|{Egs`Qn&^obZ9E=i7MCi zw-b7&`Kq@V>tc@bxZYc5(RxwaG5;F_MOXV3^O0Pv*iYy|YuX#AnF0!3>WNQ$1yUa= zKLy*<=bura3T(Eg4uNZSv^N|GeL_1E(Hrr6Z|q=1PWuaE1FE&Jxrwp<@6Aq z74l%0enY|KvJ_9GQ+Gyt!b^>TOFH9A;3vuNb;r($klp_AKyWuk_Nlm`vvi=QVd#-= zVjEb=@Y5Tz6XWEK;A_J=ZTH}0gB5ElZj2aEYoI0yu@R9q@tHT@3(y1>CTZZnM4P!s%$;ZoS z)qr<>Hj}_6!>tJ;42CXxurN7 z%%+Ltp{~^^P@Q1Rk(OoX0`>HxU?65q4g=jJWrW$8*8O}x3Nw~f9gEMAq2@{KHkC=3 zjmVL~mO~fQ6J9P39kR*Xo?tW`CPqRJG^HSW+by`&6Yu{QwwWy87*mZ33PYCYr6Pw- zUFnI)%RYH$IiUVyvHT+l4Ci&76VtU&Y}4>UP@jbR7<7son#Z(Z24wP*38U(0=B+BS z4r*8Dot^?hGtN|R-^3c4R=v^v!5XwDz-LYkpu=TVXf}An<59rg+KMnq~ ziVsj=tQ8EvEim8`DIOlqK-a-zDbq2qp`NP^h)hli*4z@~Me~QxXdT1t<_Hn#8VrIq zi#}yW{7!rzXhMOte`!aUg?pDo?@X1Mg3kP;C5{b<-9|48_&U;TT#n7Dq` zY#( zofnR$3LT@UmG#Lmd9viCcJ;QfJYmj6N+~3lh}+odEkg{bCxipMg|nTdwpW0$9+4|q z2sqQph=rr*wWvG+U6W2cA^hV6h^(ifasU2*Au=Z5t+T{6tAbMTm^PO2bZNRLIja-3 zPECdL`^Q;)?Un8#p`{#_PfwHYKt$32$7r@|;gWwmOR_-}n`%49e4r*}v8tbde&9zp ziH?(ueM?NJINicp0sYt=Z?t>TbpHBhKSk$e3p)#G_<<~(2r}oumC{@x+*6tlw)v0H z$b`y*(jZ`WJl)!}%cRgV>UTkcARad12ha>?k=~5M6)n4gQ`yC>_TbFpM~hluR~-@0 zW*3zkl!6htx*5j}yP1v#Zjer@?pokZWVcOuPEz>U_oUdYnyu13B{wQR5}qm7vU>5j zdv9b%u`i=JqAvCdAXw7mE*0Dkp}I~z5C*f#Kz3tgWW|=X?%5y$mfzc=l1D6}Xg+h; zE-~I#$4oH81Q9ZdsKG{v;UX$d?;?kT5InpgzCC)*zt3@N)9x=fGdb_y_CR^|)mNKo z?X}s`>R8j?UE1Mp%0_fq&Fv4`Q8<4aT#oioj?b(o+aC$VD$6Vy(JmyHLuSX$W>|wM zoy+muWwo&@91oZ65Lzn^rulv;emiJNajd>aCF6nJUe!7nY3iE8<_oFIVrup2=)Q1U z6*DS6_qBJ82Oqm6KtS$Mm6lXHp9|#XZ9bV0%E;t%8+#%Rt<~S8~C>8`_vI(8DXM$61SW#i+ zOuMof&UVfyE3pquhmFhdGzp%M!LOc*(~ixSlCV?x*)Y7CZkDIpVcc_1xvSq=|Km}@ zq0ky6lwn7?BnCiOcMk{9+mXE_3)EIYB6%d+Oi@&@rVe{h7@=A_JEq$nH7l)%;wA!# z-V;i1++ltP9&*~iFo;)}Cbp2tnHb4j2whp0WN-ZMClSy5r(El<$qn!_Yc@St63z)H ztvORQ$5N+*DQ*oSO<@K-9UeW+7+O=F&4@se8ov^b>QqDyUdMQm@7KcTg2YZnsC^Jx zGOc%)i;^KWU}!Runk_Zc;`*6y(;ObhY$>qsccVsxO$INXxLlGoBXN_MhkD6bS@Y>M z7@KjrOyEiXG0Oab2Hv8Jp&AXgg%TWDgc0;w9Hvf7bczmJQ|Rp~@PV=5EBo93*Bcm- z$o+5;#FH|EsW;N_pA>w{ukA1Slubin@jm!(iaJ6x{umYtW}n6+T@EY_k116fL{Y@X zCFgVi;$lU(Ox(*7U~!dp<~ikK8O$xmu>Z{ye?Tir#4?Is%!D&KV#%5)P@m6IrcAG_ zX=Cf9@rBIz!YQxBmT+Mm%TjA~AtsW@+m5YJ8W^wUc-#sX0{_+OU_+B-QD8_C``Fm^ zv-ert`W;E?jK?jdICgvfQi+r1WZ5r=waRT}0)tD6bKZKT@Z}MzfkHd){6&5$Vn-yQL0c}$gDUck4^i18gbV*J&f?`1M{!t149+z6~_PP&eg(Q(W8-qy#cTFafXNEf1{V98LH zdr{&$m<%r~93sARxGOe_5jNVGu;l7Qw3?L8g4~#QB{a})&SVX9C(0@}HJ$X+fm?g_ z1KTh;HG(p|SsI{dDvFNzD)9D8Zq5xC<{%RmA`{F~MqW}Qn)Mx3atjRt^@5X#IbbcY5**y6+2{;%akk$iAT62LB)+A6Q1B^d~30MgN z&;!}A!LJO;UL|;bEPMWB06GD=>VZHUndeu;d`zXosqlcaC>G`qXtAIo+@2S^s1AuU z{3?bsrU=8n$I|4&59NT^6Xf`u_CN9YI}S&bptw;Q-*Iu_>)o%n9<5(oczW-Te(Oa2 z1Mi#o(B`fS&E-ec%c{R`;=%gI2m8+48(fsnOdgCr{>A2f<%7|IXDY6HU@$An52z`3 zta@#1;P>Rh_$TA=!c_2j%$z=ZPW{woXfVMZu``g}(mC~Ma)RXIg>d2dgQ}h`ys+4> z1ha1h!QIVA=Km)(5Sd&&C*abc5*}#jMPMuLQT@7lP%SRI{%fU&2%r}~eC{#LR-X@d zd(H6v?~iw1n*j+rF=NNgCo(pL$glkxP(-!A{lG%KdNMrP+VMrPw*A^CT4&vf2V((H zBE`fv{OF5;J#JUUqopr$tqJOE&_ZHLDA&YB7@lbtJ_!9NjxH8i#!v zYZ@pknAmB^Xhx<0zI2Ld?^~p$1)Dk5Wc(?>|Z!Fc5SjxVODie)+EI5 z0$Q2c^{jHL&$*ufnVKp?dS(M%ovdz)8)+e21eNM$KV3fBg?6j4ywH6-ZVZG64BG8U zk;c_8h70Ne6(5<8W6seKFK)i9oCMIvyxR^B=wNwalLi@$w^0wYaSlkUL6qkQ1D|2- zi6j`IKc9KHh^gD78ei`&1UoX*=lagV(zm3zyHYzF0Fdq|t?w)ExF9u{Rpo9~exP*V zi_I*3Rs|LNzyQa0@KD)XUILMF%ZxG@S5t7{`9N8{3RD9~i9}z^`e#6p+Ey|K8r z9dxWp?*?q*Qt@a0xOhL?t)A%oS_!GFx+-{j>MA@-kBPfaSe5?1z`t9}{E`2lxLcGD z`>)sK-6zanDerEU5puy0{S14y*bi5sDlSN4^`&k)Xj=7iP2mkt80LeT_aHnOt2_%ru@?|AWg zu2R))$MlcwYzC_pBq)PZM}Unc8Q9&)%AVu zd9l9Nl~}J0jrKC>dN!F4Jtf6eVp*%f|DDeHm_LU$B{azz+H56=3L0 zh8~%CRjmen2AKW@f!$M|`0VWm%H3w?QY5A~RW)^gti%${f$p+7)@;M}Z#Mh}wdcDXn)dyItM)%ZE_8lo|YTxibg|W%U<-^LAFB++9vN z34+3%gZ(UQQem?o4Nw_bo5+}f<_v-vOEA7#*RdYgxEU#JfzMR}>{Omh1zTNTP{7m?Tj|>sMg^z5V3I7-0eJ1>W zy=<+&mAtXP2HyMHmD{MGuK9li)XrZ5wF~AStSH|KUTls%B#wv|MN55LzFcXk9r7%( zMuc}xFktWs2BltPfmGws*4Ulpx$%`CTFL>yT8Us8L>X_In)kuH%`JG!cevCf?Yrb_ zrEcePxDs{Od_e}{?(+4`Pt)+NN6qmHw_fBoeA_FYQlB_~!-REz?c>Yeyo1y2W((Z; zV-LlTxK4Teq`O~^i&-uAi}K{&AfBpa0|V#WD^U|QOCe*+^KW0EETc&+X@>GxCMyIf z0{dq(*HwxgTRjpwqLH~RIl5oX>iwW9^=EMJE(E&ns8dolMYChqnb(nalE7D2gTm=B zmB?te?7Q(Za{GXv8qBC$E1gvg>r)PN_7+j*k4&y`Zd)LNEmUo3`SrJ*pAoiHc3}UFR)|U z-E3d~>|=S8_z3Pv5Z)81K_Q?`hwk4GQi!-gG23Bd~8FQmz&D43YR zz#Ldw4|)<+OgMYa_9O#7mz5r(qN!7f?-1Z5fgD6qf|P_EM~2L*Y}0d0%q?|K(iv@u zFaPp;feHOI)c1&vUG_UKWd*?7&O>@3-M$Kl+t`mE#>Gp!8 za8Q?zt{%^hrN^@B4qa%=J$GLJkM|vkgZVL0TF|bE)1%}}xJv`+B?Zd|4bdieH7qa? z8|(CL*C#6Kh|3`nfqyxSh2_~=f-w-=gs0UmovDlQq_{2VmneSf5Va{K8`9Cbqiubu zO0n*z0!z87v>C=V@PTiC?!D=Y@=^D9WV$*2l-O}D7`Inn%A(TO!>@-o)Kt8?6mkq~ z9Qix#$urHJHyW;io zk4Z`i+~#E;k3z+gx10~AT46&pRpYXG}naZT$%CMfEm{AGY&2k9KB@zZpg*B#oQa>1o595R z#h@UQ&Cs2zcU#hHWpaK=Uk<~SktZT|I;>vP%}kH~Nv4W-skG6le5ECuzZ-OJ{KXqq zWF$B86uEEt!l{$kr{NsfKHyxsXRqS z4>G37yIB!V(~>g&_A~Fo*@@yMX{SC&7M&gOoXPi<#%;1%glE#lp%B(0vSBt!kkZY> znGl@~I}AeQOR+2>98K$(-iWnkVToP9t5I7Y%QT$Po4VHCtdwI88>z)Vk*NxSL6TmI9$H6={Cq!}A$LT(#xwCeW7_ zepA=N!)F*72uu1NSwB26H!-*2SDGe9q(Zt2Hb)PbC%v;Fb9REv zW@FAV5;|~|D>kE4=E71N5{x#C#AJaRPZ3T%_lVUTL zacuTO7~z3^{KhLFM=z%V4s5V;WSa{1!epz#^@eSZ@<;@-%)6GAJQ-54S0d!oEUYJ~ zb6Q!S`_bF-E`;`Uy{Kp`dD86}E{3&ie;k-JK+*?UY{Up+4Lb#t1#iT3Q>Il%o>pnS zXuZG-OYtR(wQ#Y&&V(N{?UPa{pzg8twy-d+`xbsJL;zbZ_>O z*s(cZd-qPeV&7eoPc$!l4p+W1e@va2ZpU>MitH<_mx_<2yW@`p)#vYAT?^cWqYqy$PxPf) zJ#jg{nl1-{&b|_Nu4Tc6@|mMY#fOi^9|@=H=OTTmw4v@Isq-;8t>6Dk_HyZyqH(mJ zHZI9$^vmJ?@)!KgqZ8^ZbL&p0e06ev{7c7Y*W^76-Ok{$tc#x!uL)f$R#3XKKpJbf zDq&iU$_xOpr|o6J?OqI3xV%43o4ez54~crOZC-AJ7G4f_b2{L)EL{)8;pHcTIR2^9 z+==?`c=5@0+ ze&LUR?2d}bhq_BYFXhrJZ4+dx@uT6+K}iF#$VmmZ|8f6U<;Qe%rXj_3g72VX-y`pC zi8PVLq}c%)WC(O>^6yegT`qNnEO)0E^2f3?ZcxRh3*>kdR5yJ7Y^%wILO-sk2yrl7 zxu*DYX(bqt(>FH=c9%O(D!%c&&c9IwzKrK8AMPgog*>Z|OuBM>$Rzf4gR|v{OR;<+ zV|(2X`1f7_CVMx|-tOqkct^4ZG zpmu@irPkDUE0KD$T|h4~@k$i*tS*F)>GM8cRdR@&g0!?7H^$|W zmS2?y9qcU31De&J=$I{vOaCXy`5vA^dRPv|%nrKXZiCas3<+xuVg^eG_M(@L$vaY|>QxyuL8tK|fEsJX&hxLR0ZB#FGE;+==MO4VvuQ98<0M(&rragm= zCgf#N8fwrwB~tPl9}f@g8mJ@lhq>tyQX$17^UsKh&T+js*arfAPR%@5dVn;%eM@gD z#d*EOnYGF1?|66zD5v`L6-ps#gax&ryt8-MkIBf$qk zFdnO+7v?{{e4{*_QqDElnb}EyYGUja@N2eTN;m6c)~kl$fZ>)Y;(HWg$R+onJKt0a zS1;qw?8cD=GgemZP1UlNiq-+$cL`HWKA)VK1tYC~s0;H|bpdQ_toq;!*2;r`rJw2) z9tdXS(Rq1{Zj18QB7oV^fjU3^q18jt;C&&ubwz0* zG92frywm7|g|$Fx!4qwZEH_-br6ReH5G!m%8*#B%vj_hAgYH7NK_Dir1LsZvZh}0) zAW!%A&8?~4zDTm&(jS07%7_2hAZzcl#KZTMUsU2lU9v7YLCU8K7s`8;?2Sp;d79M6 z|Mho!W9PyDmdZf&EOyZOrK5i`DI6w`#{!BF`Bi5_qF((I%p6valGWHmPq4olvdn{k zwb$x!H#OP~oT%EbLs&|7uSiKWoh>w+ajXTCumH;YyZBO8yUbx#)8pMYR6r3T`d|Z* zPP}CJ+aH6?;-g>so&)X$af2X;1kbIG%Q$_W6i$;hxXZsL8Bqkw17x%e&TY7aQsFHY z#f+^5t`Soy0+4{gm5|wt#l0iC*W^l*vpQ3#cl#ty9*TQoodQJ{W+^ zdLsJN{L6UuMOgeiOE=L0r?dSbwfL>?jLP3F z%E3J27T+yGeO?$M*nMG_Oh|uTjJS!x74dTjKw&0}hwha~;)tAX;-}BP65jz>gVR9i zF#_g+yAe%v9#k=`I!%o=m}XG815WM7P#uLLf9+r2K7MC+8R2(peHo_pwd2+y(YEes zHjjvQwQz{_BfO768rO;tVwG?}tex5~SR0xl#6bWWm?nM8t`|l@F2~*AY8+I+7Ew+VwT2}or&;-`=$o;0SbSq11ufOp-?}QO6pDMrnH#sV5tEllm zHyM7fMt^1gnxmrrYMCc*%kUe#;GBw+@_oHU0X`Mbp^LoW(6f^YtO3`C9hIQT+)J#*cNLP&uUeBP0l#q{W+w zf*&3dL+&HZEYM7jBp!J4AHQw$=$EJOm!=1*}r5)zVR|W*>?V zrlc2wRNXm$XDdJYkzaqY__DX3fH35=LGt7L7s6#zm~~N_vHutD9HlbdM{UY#2B1(W-f6E) z8IS)L9BW0}#!-$tihK-ICKj#9>2GLKVq)T19cKrM#?PB7`2PXhB|)Xlb!9 z!Cnr=(XxK?BZMclcUuQ_xap0Beng_DC+c=kV^#+ylftSwCYoY^QFXvG^wCOVV=Cem zx0^Xu)Zyr6A_EZ$nGl>=9(zroJaN2$l%{Q(Xl!GDGG;b*`h%#W^)~s1-{lLmA(MhE z6DG-!8l(1)UzWQHJGap-iqP;m5g2C4OQ$dmjB1jlHg8L*1-q&kApqmBms)$Kty(~8 zq*&$iM!~Z^#W7q&%*;zM#pepD$vN6bzR3J(h5o=LJr6rq7`LH-_do|RNX+pDY6Be9 z{8=FwWTO-WVvNCTtZ`>zf5|hE3UoNw;Rwr&jeAOQhsa9Ok<;@lc{FG;nLm1F8|1H0 zq~R!lO(XN2orQWP3T5lZ&#)I31cIi#OF>ddxhq)>+%;|ZF3-6y`DHfJW@f4A)s zu_>%5AqRkMu7oH(pBZNS93kN;fWJOr3HiBNcK4AZ^8V z>ke?$)M{bnLf1Ym!2BB-a>e4Np4Gl%AzZ8?&ZWqMj?`(z;4ow)L`maEX6NpF%FZ(83)D+kp0=fhuIJz^>|pk=mWvDzCewVfgIFR!m4XE6 z7Ygub6e#iSjk3y-r&4jAK3N+;L!_XHJXPVG^qpDA!22E`Pxso6E~ zf8IP@mL&QnlQtJ|iAl0ynlpmMwC}PqVRow)!thw+*|O$XCmeH`9(9%+UKz<{0Xca? zemc3FhwrFg5EvHH7x;!OGJHs)C3#0%o`WOHNA!|cw8Ur1{H7Uu$Pk_uG0QY=+7RrA z9(6wWZ*PZ_0A72+&xWLt>i9&!9=Zbaxd~eqz=i(00YQg zRTbj|DZu7f9gr0r!?{ET+$=LUo2MH%N|ugKvtMs`GlVXopa{C`eB#$wG|AsKAMw!s z@ULM4begW^zoFQO##@hY_|&|=_3#`+`1Oxn8Jw#ZGeN;zRq@;=Q(Oja6em0us-&e)>>6bkbf#wNj_B$20S@i1ZoT4uDPK+%DP zF~OJBl(f7leO)71Cdblz2z~GK?eg$LzIcC^ab#~OC%aB;eP~*pbgb~LR+abqFaA2? zVFt#qnLnr~PlgYmOK?`+!5}8i&3AJi$G8r~C^p^Z>-nhN{M>X^jXIzEH%!l#F*K7>l@N;YI``jve864u{oWFD%t7lZk)Iu74-S?}uRcq!< z*`p0p-tpx{K75U=C&wDyum7=8Fm~2i*8lj1wKYi86m}_&vk*$|=|7_RaJ1+T$8RUt zUObSROBtwJ0{FfV(TD_{W1P4h{~7I&0Z<9>4c)$Z_2K`!u!Ap}8bh@;MmGp{I?gOxG!`uqx$k}b)A1(efWjbrVar6D9XSu(1o>fB*WIr4MJ(8Hp z=Z~CukA@!7Gl&U(5VmOCbt5YqL$>4}VjGT>`4BVoqJS;#cYf-cukvXKw;w+><;@mR3FGdAGkp_Wb^gk->NQ%i{bNDZb`R(nOEjM?|hhdNM9H} zzWd|a8~3l8b!@_SrZE;M3~mjPcyy3t9)_`IbB1>r)FE)0?Z$F#0CFmN&-R z7;%H@Z{6A4pUEobK1R1$0nJU&um1WY{*7kz{X#ZXtNuy#vIx|tbv&)V+MS=))Uil` zchb@mW7#Li)+WpD-n-=wo!t7yYwF5!{l=!g2M_IFSI>TG^@^VDKKWhW8T&8so#Jn& zV_#xhP5kOj(#}tvm6Z!kE#x;L?6bcP+bR{@lK`0+En*a1mX+85fH3ii5f6#FrToK4 z;sx8=5hr;}NJe76`3egvTc7Y1&&eCR^@&-dVv%I)D_5_K1obDI>K-{uvc=0%UD3~7 z(W6&Z%c}q+oDUQJ++=6$xI10?L2)9L&C<>hF8u|$N8hul=ciXW%j<=1H2scC?|j)m zF&>&`UljW{cRI7L$oX5%>JIw5nx6Tgsq$DQeJ=XJ=CIlN%incvZL8VuA5swC)og}= z+#=u)=L+T1B~vV}D*BV`ZS3!3Vfkqx5JhBc_`sV?>}0*(2nO|Dv#}mj*Ok=>kW?d0 z7BB|avz93v>(Z-SlP6U5i>~_yjeJYjPQ{K})z|qr_lux7WTcnt&G_%9SL2FU;E1nog@TP_yC{XL1SP#{z zW|gdeqFr5nO@6XS<9AUkqh8OrjXA!XsM zuT|IUZC)&{H+Khz>oo~j!HOAZ?-tOSW^nKq93XhyA<`=vdUKZ$nGYsQKWnBnblZ@hU z5G~K#u;26s&E_KgyFgmZw_5D+pWV+6CCVa@LUhCo<5tg^V;XkY=u>~DuNe8@Wc;Q0 zWXz_6vN?5Ysr*#gA$)c9w`z@-FEQ^=2-4s>QWr+l0Z%e9( zfQ87+BXCF{Zq{edw4%9zB6CMmP(WFuj3aG@h##vkc9kn_tRjYxEx{Vpbcxj0druV1 zxjrz2gt>w{J>##92`+{1@D^)^{#nDW27_j=!pbXYom=7*iYj=Ts8*bILm+Xd6(r2Q ztj;Rw0e2|nFjRKPO0&(7%Ibh^f_6*>hbk`RtVoY^H^L8oJ*md=*gr8gla`(k2p za&5aQ{{u5Th~9d@9FZ`@*}x?5v?a@hEI8*nhQzWAiPngI6Q=J`_lxRTb(q{8?MM!< z&xLx6l95LLghlQx}75O2zXRl@rgG%&?$j%w7zL$VApxv5^lF z8bS#%PQ!r?otmjEed6ceHTQa{l=y{-r`e%Su15Cs_6gsobw=kcVxWxyXfHaAe$W_M zB%^_bwnoRynV6JVqQcq9R!c6PR4=PifH?rBH9~?9#c-1@%FqN1Q&TkCG1BU+Y6lx1 z7f0hO;THzCyW@-wwGT56PO3gVRxL0xZ_!}(heyl5LC!+LU{-rhb)78i6cea z2o!0~rQoD0@oC+d8kMudND(^+>^A9V1LzT8(TuahL={W+87#gWUjzk69*AVC!>ZN13gr~&Zldj(Q`18r}2qQ6(igax|TPLs> z6KlS)^@fmJWH8#o7UUyf>&=8_TDqwnT$E(oQO&snHRn8_=DGh(QAE43J502!iRgaC zOly>h09Gs;Gj4vR{C@K%o*UI;nnJy9nPVNPWWs1nVq{DP^34a8f)Hv^MT`~)_1Mfk zXcyyglNqoaJKvU#OngN}Sa9_SMr$rGD(avbhRzI&20hDzpeGZIm#`&bvGP#YVg(3S zx%Nu;#=XC=Q92wwTPjSX>15jXtLYlZ+r&1;g_-##IoNR)WHK~8Ze$n-2|S5<+%%$$ zp(lQ8{(yl(^<79AL&LS5f)^SD5aaP1(jxU~pGky7Leg14T*s{edre z&z7Df@xjRE+StU}c2S<1PN3v%N@8poGOGK5)ohGZ#X8dy(mf=VvTd0SIiXcQ$sIi8 zqorm`>}-M~OgT0KjlrT5b>kjn>vbdOUhq&i4;|B$8yEh{8w;qA|MXWHMuHk6v4G^p7Usml zeW*#6oyIb2W5Jwj1}5^ZVMEOLnB`^TfdF@oERHO4jWC9krE#Vdjf7B2b>&98ih$rn zdVcowz8Sy2w>(XiZ4BAlW_(YGEJN@cdcDO`Zl%rKpZk%+F~VC#%SUkNQ1G8pC(f$b zKVZ5a;LbAV=SBtP!(*a22ZmfZV!RV0 zaDCS1ku|4^c@sTVyArSLr}PaR(MXKG_vdWmArj=fZdDYf1V|p|i5nq%%f1uPQ0=KH z*}oOG8%BhAz?dz;r3MTZ6s2CwzA1xs5h?l`#fFT?m=$B^aU5t7&B6)pw?uW_Of>a# z>Isbs8LMJh|L)Y)DBVjb1iw(7WbqlFYj@h`RTI!IhpT%312h8Z?=FP^?V)xt4hFCwbnDtxLj7fo=btN2pf@duLZ#|LV zf<#n8oqZtmq~; zj5$I1Aa%K-2k0*zZpDyrO0AS|Q;m@wEx-9&zd!)yx>N=CJDsPerYKAhnxve!n89>o zran4rcGBgZOix)R2hBW^%ycsplHD!IYs3%_v<}L-Yq+LndX8#&)MEk)LvG(F%!x&@ z4l6@q9)y0AsAma>4EhjYMb5%+q#szlaVo6TYl8iagZhd_EKFt?K#-rqM-W%0WG$fs_{f?mfQZbpi|inxi^Le4%XFAa)gne=q)KU!z91OFCg}Yvhrt;<*NyON zAAGNCcr%f%`R0Hxj@1r1RU*Nqdz%QitN^4i{w04KTy88wDVAiT!#FXr-# z(4g8T3XSC{^>{3`Mx`05(KkQz+Z!c!E(I8#;i$d-8MVs7R;w;rBexjdI zED5#vS7R#N5)`8Xi7g37s0dT(Gwd5N(S$*V0W*K)$Ebl<#*gJ^Mlbd>EQ6I)mKiKdwsBDik8XNzv>(D~1gBY*7uAK}nrczICvfJGk`k-zTkH_|^n-k? zH<8$7G|*{a-9|AkfYSFbzNm0$b737Ll&JdY(|b7_0BPaoZ}XUVWm)Y-21Qf`iZ<~i zZ(0`*PUVvePDs2cvdW-&e_g5=pJ_ja&NAiPhW;BNCnHnoH<2Vsq!VZrhYSzC!O<=m zz&p2<(Hfjt2(rslCenEtYnx(6FmN}e0Ha}BSfyan%E-and*{%!fGp*T43dHHXqr@Bw&dyNSyE z4hG<8a;L43jQq3yv_zResa2AvHsC3^kT$#yz7&vyO`APGV#u8Cf~Tme0+mgTiL` zF!`0fNSs6!rA3^fnSsJ5e(sL>y`{NalPAz&yXvp)oj`ro5Ye~AKBg(WFnoEa5Dw-< zN(|YMDYz)atn~&c)bKgEynSokj1&gkDQ*5Lm0Mh_&) zm=^MQ+J-#X6Av#j9}3YU11D}XGruOku0T(&s!bI&oCCQRg`G34V6Sm;aaRBlhz^vz zs#UqIjmJXRY(n@~e(Sc`XG_nPQo_`|Ov-y{JO{V7nQy;s9?)jrh@rvjMIMO!$kNGFfQi_(?(B))peF7`uMBZMawrPEBNwzZS1d!@EfnmWq1i{e@$sKGK%jq zqWQce0wRaTKv;_=cv!s{zuYzH3rL9p!e05n`I3RnjhA5jY`{2T=g`IBf1Ag^Q*Os} zOxCb!IG&B%vOJad*F?vdX956%(HQ?lUsiFWgg+q_2?bDsz%l6?2e*!$G2Q~8>Oge@ zQ;`MGJhwDUU;2jy_kI&R_k3%jgXXw1%mub#-&+Hd*t8~P*le0iWS}>r&EA%zA|Zx( z7@S`Hs%px)5vWx21GPtC@{G>V38Rl#-a%8~UGl=HeW`087V{62M-IZbAN`)YN(Z9} zqG#7EOW6}^Qz)=tau#pVVqB`E(r=+MWK$E(=wVa@|9N;&%D^)^vbnoe*;FU4F*#zf zb9V|)*Kh`Mj4UxZn!yRAY$NUsgFvCf7&}HO{*&%|=Erg|Aqe6KUVL7I$<06t-O2A| ze&xOhnB++s|wdp;|j%C zj7_9(kE1}j*=1FsT)h5M`h2MnmAzDSkXkQIjkSIUW03#8X^a@g3{XpA!!ai}C+x&{ zfp%4+n~nA0r_{mvY~Ku1eG~pTxK*YIKNA5)ip!XwoGOSrtaB{yBr!b>6?#NiA0B*B zjbT}OW77x6ua+-A|()?ab0peoPLGV&x30c8>mFvlwriV^t5hi z4XmHTaAsQtXz9PY=UBuXO{xhTsHT&hZTV3$Z?o_;V!(+CPA+5Lw4`x6ZpO-3ccv0t zyGF+959sh!8C3GPo%Kj2oT0an8vy8l%05276dZ2wN;lvLWN5(G-U$Endk#nbSb*LF z^7xbq+SfysjUl}yq_`}`jfs0FP$bXpDYKYh9tP!ruK^lqFRnN1*Hm^wT6+{zF%$r= z4A+>L@iP1ZptHph(W@r|rR!ZMWsWhf0qXbVpWb#bI!FcV+?sLX2*Gj{P>_fQH2)SI zXf8M#U|wUyVztY7121xI{#K`F{>wsJHOq7oyXM%(IbCaXT{;{B$XB{pJ!<9xy~%h;(teDL;T zky$SVS7%jHJS~VsZ1`>rq8SA9U=~Dmlc3)+-W&KLlc0f-P4DxMjb5Wp?XbD{TKz(h zIrC2AtV)0nBG#cyEaVBK39qCL0#*@if#MF7JRk3m%{ZBVDI@hCzIsH>n-v&iDyAp; zQ!ayrc{4q^MNML6dto;l!FmPLhB*jE7^p4YRe@6rK|Jp-NuxR=zRG&$y}YnB)gaUJ@3o_ zLs{PQ)eS+A00!O9`+WSL&-ZQm#>KPV175>oKp7$+2EM=+!4E|ROwy%Fttut;s<)j{ z;yEo5is%i2cXaKk?}!&1&7?@F+T=uplxjK|S1?DQOm&yfMNJ3jQjr*Kh67@0l%0A3 zE(RZ`oqCHKwJUS42Nf&0UvN$66(j*`^vKty+x^K|1VlDz~(DHR}!HS*_9}DXQ zQ>1C~7Aa_Q1!+|-Mt9_4@x2ew3t)V_z)>lA`x!ALkV_k z;wm_htVjl3QiMH{jnLB3Z{gjBc1Kx1_741>j}szov*ze>5L z4WWmLAs!cZY!J*s&Xq}vM`Mt-Qs)^{?TN8;$+V|njHrK~7*H1CdQ77T;3H@<22@3Y1>_)UIMGtQRx&A3Vo8Cf1JD)1*$I>>64EHX zuTI7qh*|f3j{oD=ON0g~u9(jq`Q7Zv@QF+`21BB^{*~|N3eS&{oh5rn$|lGvM@C!`#SB}t3o46(F(Lshp~n-dZLJ_yo>|(cg?D=k{4AKeKwd`pCe%p1h>k02 z%kwLgk7zR@NQ_7Nx`O{}kN$yq>u3njIXP}F;*k@-H#ArUs_a@#$2Un`v~yD?zXo zI^JX9g^>3QgE2(5VvwwmKJ22u=vPU{aiUCvkj9g-g4{cJX$NEwW5|? z8V6v;_e?{)w!!Y*=xgG_epsPIHx4-~`lQgv&8%1X!2pN|N#bA!3#QYC;(iTl@tHqeUTgyY~ zO-HbefNvf8j$D%>}&yJq< zAAah6l({pJ+myl?*sP*e@F_R*FU#oDBq0rYg#TWqe%V5Y2;_GPc6fK_kC?@y!rAud zioD=KN99%YsE&DsmJFg9Fo|onRW&QpoVVzv0X$V}4L>F0D>@fQPCe~^=Ppn9Jl$a_rMkj##^p()(fSS zzXYHd0)Wzg5hCGAYjVR*F(^^vlG3-;w{++fGX@@0Z)3sfC`2@u0X*fZ)rDk<`Jh3y zYfeXsqILQyGA&Tgo}%+9daSkiL{r8~zWYmOm|UF2i!&pRNOT*N_5^U#e*qb|0LPQ* zgiftiV);^Q=*fx{1S4-(xNEJn%_zmJdLtawt>92vpMpJPQt(L7qeR--CMK3Q^IvO5 zj?4pgB&0awf8y_kW|I*QY?fXyQ&=vYdhWgpIy%H^Q+5e~RLnRgZ^6v_NxmcMsTL85 zw#kt> zfa;(*KJgVY#~g~N4d~3pv?N)#{CH80rEGK-%7!5tu zGRYs+^va25pzE2$p``hzpUcm=)HB74N|$flr8d78Zt!~;c3*RZ*XVZK4waxWtdl}? zACZMe;`BqJx*{#;Ee}C(usX_)u&6yiOV5kOL=fd~Ew%lpj0qF9Xs zU%ki=d_N$+jRO5s8V~|uNCsxKRWNtf>w8N{n@IQ#N0daoB?sYpbfrU|M!VSx*D}kH z=o2kT-ukQOE{;+olT=^XV@qv!YC5IvAx43o^a+9Q;wmM4398H4GW1Brt=}@iCv{(F zPqATDFMG2b&<8WZ=wwJ5r-K`E*CI>>-*u zyUySZfe}A%VMWW*6e!}pmWwGYA%E(&`l9?J$ILR*jkrcvr7k{ta?)86W7uH{K2p0z zlOUKT{f44$ZV|3QNcTPBt3h2TBU_28Ca%$;xfX;W(vegp7JLH@BufF|DDYy*77eY4 zoF9`h=)j)K?|U_*J6$kHml!kQ5qh$?9V%oT8H-3QpNii`rNmqy^I~4shgyj)fHyKr z0=%VLt~9VxW>F)FuxVfZikEx91mqY z93a-t(Fmy2fhV0}si?$wPi7zr)piM~n7M4e@Z=B)9Bv5TI8Km}BE_=`6T5t zkF@`I6W>S!pywNpHvQ**n!M$KZi);1qor&&A$buBc=c&Q@FtkaMTjcJvk_8}rgZft zHc?N`N5NEU^9Se>1GxuvP>vbNI6o^A^eGJi{+)opyhza*?H$#5ErW)n{dV(e`^#r^ zNN#f&w#$*1t$Qb@CMm}vX>Q(qVOP|@RgLnZ#0B7!lvVZ5h+*_yQp+H;)8p%5Fvm}k z6aG1b5FJ&J9oLW~HeHjhE*^R-!ZVWJii4(%27~gS{~~;uCAJg8rZar+RBJEwRSgLP zn9I_U7W|M@J5@u9DuB~>MkIb%cF@SMe8hEsK)y{aB&%z3453GJ1_fA_9Bc!wbbyAI zj4hvLA_!WrZXyS!$bS1So{-_lsPJ@~MhVGE;x5rJMtA$X;a`9TgVz&L*pw)7S7|h~ z!aJ&)WJFiO`@%!DyTj-4)wE>9uDW`|Z>HFFRUsuVL;;Lz@I0o+Wz<7g82RUk?_3GJ8%B=E&FH* z5bLrtop52geQ#?5o(`g(1V2~{3nv1K34VkFL{YmIjm=?QMSfIzlp%l0o3o)+JrIg7 z0D{GrXvVM-MRK#iI@xG-Es9pCMI_SoJf-Qm_Qe;5-yR(;#EF~Wr%4GIgvk+v5AsE( z69lw^8YSlizz_{o@HvPauO}-3ZCP&#*r^v8v+zm>$jaF_WHF|y8x=S&DU-P?E`$#ks$d>q!OhYQK4IN` zBzE-AaoY=lYE-s^NpC^6q0K>!xG52sSok7)AsSK@l=4x=X0%}GxRlZ063};TnX3>Ty)P>-V3L_3{NZ0gwxCh0+br^4iah(LaupMrN;YpYm zNXoC%Yc9Y7O9;84U{4T3j8qs;y%+&{(#H`Wl?`9}-G6vAn#REM|mQ>JvPoPB2U<2rX zUn~_<$u2;guBbG+DI%#^T?GT8--lL8u67vsxI2|8(bPYZx6^ZXo zXclXFzVL^Sj0)z+$ZWbkPAZ9nX+fEYc{g9ucQhr=g@_u+lWKWUE7GDwb=tgL!{lOl z))b(rX6(9>+(4Lvu#`A{Hu}ik7L+-Ntu^AlnLNbkPs7*#t^aaJX{JR3L4-RwjdR#T zi}E}R&@Aez4WIGbERVP(BeBgWgOMZS9r}=rEMWiwrOMVW5@;>pu@=J6A=M70K`0WF z1>&~xRbgpa>FWbnL6Du!G%5o*{7JHd)< z*j&PX+)sb?{f9<)Y;TgoKS^9O-rmcG7qk0oJ7j3+CjuwXCvek_L8ARW9ZHtX{M#ZT zVEY|&=^K@KYZg60tEFBfhCqE~5gaA`E`k^!WtOaj64uOM-}&UZFASA$Wk_G=`ihK_ z{kJ0|bPA5Z^j(%{A<((XP-L(I4Xlb6-wCv|l0|AU2ujOugxeMTd8TOrYX~Y>lh`C& zZZl~`B8ID576rVBG2k)oTQ6K+)9~94Z0HMo3krMx6;K22K-b1u`9jb-(qiFAU3U z0qK(|qZjRoI7jS;zv;iky|pm&p+))>0YM`xiI~5J<-8QdP-X>-UPj5`Lj48w8SF(a zXorTFJ}(q~rg}{>l?`%1$y1hOx`5LG8KSy&|IaaQAxdJ97|19q$cs`9STYMi!rZ$` ztCMIGbr7}hSuzl>Of;Ar(I>d$7NJ&-K#r;r-C#*^(P}Jj1i}T9d?U)h6^$sFktP3S zo|7!7*RgX`3PI;xe{2sZM-a1116)DZQ_O)(pi_sRMd_;nFI`^1C@c%bz!T9KF1`_L zbeS=0kwofnVMj5TP}vBSq`)vMTB~Oj>0)P@o^ehRBF(YfA<+$vc3CI5BkII;^ku@o zS}`mcfCuz7XvcJ{^c#d~ZMV!#FV=iD_kzbPFVJ=%3<9bSGJDcvNgKtWYuu_icn%C^ zO)MAm#$xg_*S>IshjFrdkZt`o9kqv)OW=8La}R=~5-GYd2eAy?;f^ePB-+r=8NCL4pIfcX#3h(SE~XFTKDvG2ac z1{)IV7M)RGprEMW=sNZj2E3X9C~(uYc@HS?2Sp3dQXSpjC3D z#1!u}7`yNl@Yz!Eq(}h+jgjREuwf!yX$qXjL)Buj9kTpX396 zIyeg)#9I;8BflSCeeSu|2v3J3NrDinhvryL=D1M#9d$uyTtl8xSM}NpjiDO5prJz0 zQ`6AGn6NfF+{U?+{RBRV8o3Q$AO~8YMco7%d&pAugMb87EtN{XfeUcv@>rUgS@aEwXQdLMp$j ztM`3!9Qh862^vcG{FLJXC$vK}DMC5sOvQsq9AC{p7UKHE1F+SUpwf^S7=Ko3i^eh( z>NiBvB0B6?Hy|mfzTCX}f!k!zS@x)*CwM-8?0i8@k?3fzvm+oPA0jao@dF=&9HOf0 zbXg*676g_eCMbWget)Gz&8|FWMIqC&>`Uf-L}Q|}l*2vB^igBkqM}5=cNjaOXeZ8w zQs%Yq|J=*rgCQH`3#ud=_bA-u04%uJXNndRf~jle@VlO32j0Z;6;lQ3_3%^RJ&*ms zis_yU!a4wD8yc(zd}aKRpbM`l$s(P6#L`V&`S(TttE)Gb=O&1kq*=__VC{)1yEP$_ zMbXSYDWbixgd*%prpArG0c!ORS*&B?>ZC>$`sxrfxDE}xNlvSnQDJPXANoEktM%R9S zS%;56y;Qkr!%FqXW)Ov|3v~1uB2vasrD!56BVt#mD5)JVdW)*=h12MUtUtagkxmjbN^=YSHYuFceqR3upykU?a9u zk9e0E4Wna7ScaMyEKnw^2jL^rL9^Yg0Kmiu9qcJ#wR09M-SBE-S zTaKQWu&tNN!y75DDCOb(OZA{us)XAiXI@kIrbjJ&=I89BrwLFLc%lG9-Yfh)C)@jB z5T+zW=fD0VgUU-xY^|mx!k#`~uqQzn5zVE&SjW%1}5&4tkKe58Src zGS&N%rC^7*Sc^66Q}WiMAIx{3@gM%)kI6Km?8w6ZVUm;f^q!VGDY`n)m>><6vK$B{ zItx5iFbsgd3%6R4Xh`w2z?vWUe)vfV-%b)HpeKfi2Adbv7J%NUOU(-K)v{sMdn*#r zARjsuCz=m`iLx%|#TdpUC_X{WP(sN;tp)Xgy%r`Q^m<)~+^2-wNZpD|(SrM(qNBX9 zj(nmS#3WjR$7EH9_TCc%L^v*;8n4}}gsLHrWVT(pd#&J3=Wq~J#( z|8&OWw*DpI*B5tKqtJjzqU6DFz*jesjx z?>#2NX7mMA;jR`?0~4)-A7a% z?+6N822s4_lF%kuV(zS6k?fM+1?Z0JTI{ ziFnZmUg9yhVM>XdVhYZaZLzicgK{)`AdK#jP1KZ`Bw-I{3?vupL}$bdD*-aZ2H|a`w_8(5o7NL;Q?5ZLeL|E~*6fQ18(C+$*wb z(GlwM^Pprde$q1(yUp?V4h~(bj{r9i>trCOBnslHsINi^EJ{dKY>uls{b}~R&{^Ub zM9$J+CxZ-DEm3=6RfH6MMM8=&Cv5|YRztSmEY_&Z?YeT!N`VH{g8`UQEl~Psk9bRJ z47$u9(nA*-SqGZiHTv!Z-e4@=ILNjzZst|>qVhp7__>s*3%v0|}JY~sP@FVBl zDe9W8OLV)7e?Se;%c3m;2r|ZY4bBi$_v1g_ilR%DONaJiID3J^XhNb12CQ-8)PCU# z_$NeTcGY59TqccEj+G^WoVy}1`HX$-(08wtzeO({PcA#}$Ii2B48Yeh5tiG3iC5>b z1?=1{Dla9f5k2AN`sdt+h_7f#6jd~pY%_O4)Ef#URne{!|9}wjSRuJ6CfN!p#N)`Z zBI&h3%v1h1|M^XGIrgctHPjUpZj&RhvwA#5BCNGf3s)qxz^bL*;^DMfOl6UW^{5dw z;DhdgX9S=0=C?xU?GSY_f>37)U=G(~z<}N#ZQ?}=2SlMf*oC1|OP4Msr#v(V*3hL` zpI}3#NjKD`p)O4lkfBdVYyxdDrI?Ujg;nzrH8|5(7pj4ZuQQO^vuK$-7IwlpPHT{E z8*xr|Y$;Z_IjlO6_AN@wK?&duW+*#WCCQb5*dXS5?sxJrCj?{k9PZ&VO68L3LQJ0) zn1a6}>(Y^u#E)nO^z{4!zZX*(LLI?o8pKQ$fiW zWj=wg*@lzAlOzFPt}Q)qg;SK|sB7OVTbfC_T>+*6v&KOh=UgVOf@dGlO!=0FR&{+C<4g2ROnI-M^tL@T*NGz<9R0 z6qcoGb}!G;m=p)l``AT0u?506u0+{eYP1Rpddw4o_{jKiFfZYGSVd!^3WtsyM2BH3 zFKul!fau=nfTT?pnN2=GnEP)2*2*R z4g`bgc|jje@ss+R*uFbD6Aw0%^Prt+NCLxMeExsI`LVPq0WblBsHi)LX7MvLeU~aQyIvy!Ezw1Wuz=p+p|DaX43qb8K@r}fELEc9H5N=lYm%|r06J7ra>-cnW7+BtAso- zy=qaYAN3AsS|qL{Tvp2}Q{XD`e1<^vtIb;GS(P2a4k??GN7X0Bv17L_klFn{$JW>Z4k~Amf z_s>LYO!@>_`?drW(sX&Ntl(Q2g+m*=z{aZVC;6G4;9Jv5}mhRg5TI7JN(R*gNycBuI7NM@8 zI|6cB{&w%qXWh}k0fgNR!vvOc)CVEmQ~r^{`?Y0Idmz*;Orwv9>>fsO1{MnEDO!2> z8~QRfT=}DzTCjR6@jvoabcL-q( z8piyfnv#POfl0*9P+Qj^pqMwbL+Yg)^~LIa-jU#KnL=caxC~a@PY&C&3EWSbwriw( z1Q{vz*$y3x>>7e(e-h!-^WVMs5D$Oi=o84`SsNeV;4hC=jl`kWb>ngpcnm zlP~w#Bj$;xn zV+ksu1TV=+I;Nul&^wbL=4lN^_i6XLINYTD$HJ zQi1K^SR`ymEu^4Q+^BKe60I#ye6f&=LJ3aOEn9TV;sLKr))?Ua4}f0sbLvc7GB#_i zN=X%!vSM~n%Pv2_L-rer@qDB?#Mu?RP!)Hbuwd_WqDWv}zyiCM%jlQHKBkUNYdG>6 zgw^mLJKHD-7*lBVYuH%ZTj;2}J!(IU=X;*`IztQzzL^*kA!U)pP<|GR3Il+gT^-b^ zdYQ2x;py1sT2&=MOCONkVbpi2Nl@heeYAFzV8-$z`Fe&m^({aj+CV zYq;W1)(;gQsN;iWHy7F3HYiWjE7lI;!BBlc+Ohn*KuCps;L+uh7#Rm;W)$~s`|X?d zF=e5Pd#+0^u(ZCHogU1G515&DqurpdR>HKa8z_@%q{`CqYmYiqPb%VcJsZo#7rfVl ztx)RaOebRd&^4pUlHve4|nvU!=0F;(Rvudq{200Ss5N7H(IRr=|CK|Y2x*Z%3OGPybv&xSMt4QLc z6rm{s=a+F!*x#~6GeI)sstoKT2D`#h`mcz+$uT6@TnuIWr+~o`A?#4Y>aiE-<606X zE}-s>4T^P=Zjd~Yr1ak##fX(tG2!0>64VhSK#=UC!V<99l#~WY?2xjAWLp~{URt7H zq}FY-uu=WrMK6bm-fl+C+?ElNHQ#9VZb>cY|RkAn8|}wBu#r(~yJ2#C4zE`U|x_%u!kf+s>c`ud+L8!WDJAvi(JQAMqs(K$2M=lDk|C#MFk&AGlHmj10 zU@ZCrToXn?ne0bFpE&sLLi=P{_H>Fr6Um7=a`dT00{z8{-fGE-0d_^V;c;0Ce2|4_ zACMfy6ZC2JGJ@j)uA#Jp%KSNq{4hGO#h25!7$zhUU&Mb}JTCfhRM8JoNeutUfBWON za!RhQvgH_rn266$BD;wJ)E2bUNC2N|KsM#)1!>C)$XGbsU7_i61(l1S9!3E7ut(hn zjh5<>s&mTJ-i9$~D0xD7ObJrEE(*dE$3I(Z&HW-xhKsn7L zdE9{2)oan*G-Wt|mUmm73@YAehL#1!j5u5Qb(W;4scp#IWlgajxVx5ZMKVt$C3PIj z%GGDSa#Hrf$%~2!j)f!gIK70p46g9%t5IKxv|5t7p_J6adCP#K!x>Wcgu9(kL|Z%T z-CtRpT_9z-pTA)Fflv~>t~QB^qvVi?rwaIssi5MKQ_r%@Ff#P%&u*XfP)0tL=LybwT)!6-cZFfG z*(Zyyy6~O0X($U-;#W#V+*CwTrQhb5C6%T{>B5#e;oZcQhZun(wb+)VQ(ofFc}F_L z1XHzB)D}_^r2?F!Hc1CULZ-iZ^9ri20h92Ws%?ucjY+bkLA!1xs8%gtW|+uS(F>#SOH+7B9(&LY z_R09(Dj#m`gp?d+ZkLECaV##_ge1DRGbE}M;c-C~v+=9wL9erndmtd`0TV231tkgw zc)G}+--om9Iu(kyI6851`o%(Ua@1dtLMkpG$e!R&BDZ3mdi2qk@o`;@WYA-r8as^| zv|enN-`ydp3s4HGJk=p22tZ%)DufqtpC&>!KgQZ>K)6Rmr2-NKL8UG*sjFe~>xyi+ z$bVFg4`?@@z{ept8f;)U4U%)53L}1n;;D=&VR(WCz@}+9JLHJr36D^nwpWYL?<$(5 zfJ?FGp4>D8xgol1RXvXK-sXU0IY0DZmI;?+lvtFBm&2uEAPTgJ7(xs4)lupx*xN8Q z)YJbqPlnj_acpc9Ex(tq5gIh@yt?KFQ8gm9S~vber62~Xx)ezc2~lbp-ep5PbObD& z+rrBk3_McqMvoA^IM1pnC+&4qoLN~QjdSu5K}r-my7mu}ljVbSkc1SM$vUhI--~{u zqRasd2(3$#_!dUffRY*?4eF5|VryaD`i16^TUU!FE#bSvLlxsNo{nK>$^u%EC>xlB zBx-pXlVo0-6o+xI=+t6Xfk%l{F^$8&AbJfb$;Wv{Qzztu^P9((Qc+`;)O(3;%Xi>Y zspH9vO_lN*NB{!#`9zjaN=Yf1$P)aUeaAz~rO1QlLCqP+)b&GgSNPs~gJz}akg#+@ z8aFzmOb7+gCO}~JZ(1V{$RID2u{$5JO;YC(Zzn3G`ec#ELX)XERop158j2N=&v8d2 zC@)X|yd*o5q3rfT;Nw>CFLHWXNVqF;9EoZ>z@xAkd81b25`=NGnT+{wf+p(m3Htr( z)hlIvpr&XPC71DWalx{`ZP5F6;}fAtCsACAc)rG0denO-J`u%@`94(ua+Wv3f~Yr+ z8!lfZ7 zr2{2Vcqlkh9a>aDyoFbxMk8@t!o;Fvd8hxJ{ly&71StYcB%ITvETZ&^uz6q}q1B@d zA#t=!NrFTnts#m*Y^j%kh!pBhtVSl1)xy$c56z0AIg7(CktA|9SsyPPlEfPuMFIsQ zs5~82*;pVzMXfb|wE5&i&vT4pSK&$Tqz5M_C$a;B`|Pj_ZSTe$zIJz9d9m77h)>wn zrAY7x(NkDn#=S(P3*Om!BjdPMJU$jEREq(3W0#7Y*THNzDIxS_D|806&(om`+8+G( zg6E%Qh*9SzFoY# zeo_Z4_lpnGp$dfQ@Q%v_Q3GRXsEq(*p|yd_^FzEIdIeoi`$vxL8B0Ff%QzEJDwmOQ z<_RHUzydW%3YBtj{2ofJaHrz3G|e#>r1>D>idEzI!iC`e3MG3{c19;=X?~;cPz6Qs zwAKw(Cw^m(^m9eMp@uE=jy09ct_oPZqMuyiSc z77?)EXTN8tOOq*1k#w{Ob3VqLOE8NS&eBkosT=Wrs5++1s!~g2eUzyEEHQIgaJBIJYQ zWtxAaHYZz62MY!w8u{SHDDp;8Dh8-5&Y0Wo@X8V7mqfQAxo&VcygzuLek9lq&r!b& zGdAeT;iX+M_AZF#S36#V0U@rO5@Er78Dt=akvtvXT6y7Lu^mB5hiLsCiZ0Z}_R`H8 znbeML*B0gGD8A$2=%dC^jTDrYsRSvSvlN`r8`|v~a&GBDSiYZp{kV7?2-U;H;(PiP zGLH99ltP0DPMWNU!@wii$O1GND_76Gxod}R!imX}9P{)Id6XQ*+};bQK~-a~T@TRv zibA~rtIQJxlefsdAPTdxS_?{X?g@u9@YF3GSAp%k34qc19ypyE`E^kiV6pXxj7H3l z77Sh|dCGq?*mI=(Svj#7M>xT;ZtM4QaHl)&vIi9W=~IMma5_NGZ1lrEIXOymwh(m!QU?SP(TO>w~?d?0m$e*B^tz*`uE#;!bSnnx;=-k}N= z4KPA-1_||MEUXaeYICmmio_!*briWerM6J2(8!L*gZ%9371SNe6C0!h+tqhc(LJn4 zqN_e#j^duYFhM|%?L;8E1LylmgG_oDts3eIFfcSk?D^$7`pqHM| z7{MEhT&AdvIbt|OtXbwDVmZt|@!x#z$886yklrMdndrAi3$Sc$chxlaa31y zx+l36=UOo0FgMEtN?Ef>p1W{uBU>a zMarcny|NM9kDKL(@WgNgF2%8wikae|Qt_A+4)Ph(1f-jY>WqKnKi+sN$HT~m3b2Wx z9J=O=Fp+t3oLP(C?sFwhd13jK*cWAkIV(b5fYJ_z6PIhO;t*JkOC>4@(iFz3Id_iS zr6;Fu>I&2YbG5}1M~bPyz}-DAbptS5cNTd_#`ia+pWnqy;JZyVL*pmkamQJhlEwGQ z>mw)MFShGCtx^q)h8TuZ#CCEkB&W54@lGOMsT$0`BO@4;5W1vREMiazL%C4@16k`J zh|(<@Mnt{Ec5F+cn64F`@jvnqMZ7+xMDBu{9McL%$HsH4uTN!9QM(tW+@;HJ4asx3 zF6P+FCSp@zWkgKX&H~EUcq6<|kR5j@;d`&#!F&M*@B>!_0*P^jc&vulhqMQV<_(@r z*L>x~4IByG=jr&8P%QGs8m3J-nqr5}L3S>~M#*{L0kJPSgc9}MsMA{!HZ|LjBFuJ$ z84+D>)MVB}(lMEL9JriXCYFRgVJ3zhF&_FvrbEK4%gu}ar+*oTDOxG~gEXC-L8tJu zK(4YQ^g$`r@YGa6V5QIre1o-tCR5upL9Aei$Xy5}IF$J)SSbZk=F)|egJiauFxI)b zRwAkxYv-sV%kj}NdJUAEdeOi2|I{5xri#e<)ieM+f2Njf+WB*zlMvsx`C6exbjL128 zbR+wB9$YiUiiHL;mmUpHTlNNZ-7BFRx=i6#a$?5)-;jgm8;~bl6tUxM50V03&%>Gy zj1hN3Xsk%VfvFw=q=fRE{})ecVfWK>X-mPtX|16opm-{0hl>MDl+l+Sm2g4gF07{? z$tm%FjC7=4w#^}A>=@)IZ3&wsU6<2m zmtT>*s&DD8G=jyo1;L}rNsS~kn9uNw{^@IZB;IEz!(%|EjueQjq$IIJ;^1Xf zoAo0iO=Gc0>4&>_*CN%$RHfLr04JXps_mdF@FQ9|J4`3(_YRQBVLl)R*DDdJ6;sc; zDD9#davZ(Cg8g+@Z~bR%u#*S$bv4vwvOvVH%W2Xz0;=EB()qT?srykhqXCX%KhTF3968(6&`IO%Jm3P<+)#{2$=Pdw(*pI+vBuK z;B4lTw1B8V97qi} z?;UTR&M++e5)rr5cE0oXH}ystG;@1?UaNyUj*+}4P~n--Si#a7LQ^|93RjteK&0ZA zL|ui@*8?4o2-*vtZikOahf_3xto-`*i@SqVSU?{hup0eJq?aJADy7WpSNgq9|Ue>re5S1|hK-1#~ zTt0LPsW7%d{`|D;*O7yU0M?8Co4-l@X^m3?Shy!5&Vf?G0Hq*7L--1@ zh^-RD8Rb|le~ra0aS0OSb?St7lwJ-In1}-O!Y3;I;Qw_NKsifaPe%~^Hi_$I$Y3BH zHU__IJY0j@;# zpq3^u-R4+3n547`65ZuT%hK&uM?k||zi zS&EQ{%OiccE-mzK$%f}^Co&{tH?My6k7P4wA7RI7TncF2I}KvFIccHnsOq4=iW_yg zYS&}apa>-~>e9=q&~Wjr4e2U}pR7~h3f`$}Fd$APE!hr<0^n}<;b((vAS=glAvA~v zWQodKp~QX$fR!iiyDhm%y1#vL8IteW7W^G|r47&}g3kk&B?RJX0)jB2Cagpe`UtDJ zPpAX2kPL&jD{t4kV^=>K#u8R)qT#V<8bb;a7;FoCL9`UdF8Y7J#2NhqQNfaqUqD$t zCJn+sQrrG(z|e$&7#RRwLwq%AB)#mD<``vjG8Z9ORD&7(cf7i&gs@iPixu`J*Vm?0fE@J}`XosTF1cm71dlHNPhf2+7fkn}P z-Z7B)To%X*#50IibSj6@in~L?nJ(C}gade7`EwmGXg$+%6O90AWjhj8fBb^>U_7z* z+(6?-BN#mGMzAhniSyp}R#S@_7|;hk0!df~N>;*KjbSN#6NE>k#;4iIZg`Zv4$<*s}=*ywX84p%r&hGT@n1Z$aXcmpdhuzx^ zz9)6YhEV&=9iSD-qhLk3EX-8|GJ*t-*4dcl32&wJ57-J4$Wv&jp;u6X9^MLeNwVFI zXWtdkFdK+EXh;x5l!}m?p(xpxBw&y)|GwydbMk#h%EUJPQUr;=8$Tk?DeQtkqItp< z&$>c(E{|sDGF>M>{Fg@OB;I*|=W@EUa9qcia{TEJi+odo&ffKj)8KgAg*c)#%yAK- zadD`&1UfpH_|aUms&&m=YvP84)0u3D{y~mU{$JN8n!4dZBE$#XEBO7M5xW%BM4H_& zh*CUY+Qqv#rI6f`{6hGRyFdBlfGk}=*)jA&vEb=_e|92(tMV{}WAC_gagzWGy7D8Z%7g?Z!C1IblscXx$KSn| zmVfxmHxCj{d7L00RMF5VOqY25y?{}b#Fvxj0McTh8PVKMq7Nd8d{A{z9C!&OLi+zg zKFN*Lgy~1$fSIG68x6PN&FHX6Ls4SoD3mIY*M~0K~x-kRIQuX7fK5X_H zw8J~(QQG}T%Kt;%PfK4^+FJn!4s8?{`8t3rnH(k4V=#raz7zWP2}@3&;E{TqwD03H zr|jwTJeXd>rt9)4=@WABlQ2}#cyow2fb1RSvN%2>dTO*HyU6#br%S%~quO)t_K^}| zaafWmUC$P+FWQ#ub%w$|Pj|c{Rmyw6q>n13oyxvi*=@|I#UukW6SzedI#8j2r-o#X zoeI?yt7=NMhdiVgE{kVzD8E#dm#Xc`$57c%;ku8A`#vD`=$;eTc`5H>#jKUaQ)5}l z)OsYtVY-Z_^|a4J66wZ}FmaBKA-&bo5`~k(wABBQo+#apfl=$H-cJP2K}BH|p$1oA?4AkP``UBpP;8-XRWqkl1G9R`>p%hM}D1_#i^d7yI*N}=Pmx96{VBv}8 zn}50I;A5i)WRtYP0sZp0Q63xRCMI{>H6blSB(JCyY=rbL!+vF#Vu0S^B@ESth0EID zKjl3}i&aaxSBUJANM6LUW$87}nOJUzh-o7X9IU+W&IVNQ+E4t&(Gc#j=V#sZ(ZRh1 z8MU99mb!CzFYAXSZPA4)Y{w zL$xJNP`a7iVP?f=Y^54@AK`SpQJ=c@SP2YzKzH-mz-KB@ zdTxjrP~AbTa%w9($WXzcMp| z=36Oc0`uLs@fJY%+pJ-le6d~)NSudJnkVNCffnV*j)j!9hv2UshZ9h0q`4mC@>NO zApd!VKUeELDrEp5d>5oUKt^l=Rp=${ZjRg}oshV^Z#cV#{qUFG{{S`pkt}h^EP0s2 z^wORdQ|d0}a6Oo#;VJ1t7{J$sS`c8y`dMjR(d#3QrEpRrIF!+?1z<7(GaV^pmWm$d%`vy)vFyN+$m%`u=X*B_nM{2Fk=PE8{NYsi(zwYWTAJ=w#rVRM zUMwNU5IJO}fe**T`{g?sCc(C9Y(#F?PX?lr5A<~t8@f)~dh$!vsyLW{P(g9Fr6*6y zmZPw)H=w8d=l=Qz(C3`Yg%%K%Y;qqlq{N6!2jIsMTjwYbY{P5U&~yadtAUcan*3E} z&%W^~LEpaF0Q^Jj8}cNLkX=d4wo;+q(%gHum``2%)^B0q2S+_N29KNU3O&!j6=yLS znxdZB=&F5;y?}uxHVkn0(FbdaQ?p@F@~C>XfHAACPZ5!pNnZv9t6jZ-BO+afv?0!9 z4UG3ntxhzb{8>3}uHX4mQ>}5HEXBj=aVvx+sGHe0X;2&~D^$9|u&Eq>K+26dYj~tc zfGVkYIcs}St5^hVpi!IhLCpEx=qOr%?^^_L@T8tR4z$Cr4T&#h$Ce0pH$Z#zK{W3H z5?7gl+`}vw^M(^8cZmrew0F>ywK}7W#ZH~?6PaA888`K$^ap%lwb}3 z-c7c(8kVu?9Uat_W5G3EgrIU{3L|1N0K+^MCBof2d)J!(^e<;dO=Ev_%#*_e#(Xas z=AmzHJW+6Me~mK)lsSBJ5)J3$B&e<@M~$qw zm~!;26(6Grk=4REGqz^7A|nh>jUMn%rbh9WAgpxC^ZPAj40~Df8+M%K{?!xQ-8I}e zXWyAK{H2unr@SyATMA5LIHd^3t8~eylaK|5%}KFAv(PjR>M{n;3eA#B{zX4am~M-C zZw3x#F}b2)a0c5<6Ez5o!u+~Bhx+C+XT6+6pHFTXHVt>?GdbgAl0BOnZlv*ekS4jc zOTHbOYeC*MlE|>RZxR>me8Fgyjn-&F3yS$4$KvQze$q|jmr_c!Z~0+tQYf0ENfVCd zlNFQVacFRov=!dtG2Ccn##<}jf-8{4nIEiIUPqND|L{G|&gE{7>A*5WXlL$3_xO1) zu>-2dCfXS|!M8O(`0gxAW088-+&%U;pS^k5fnqDI%P-j7tLra!J_-Gi{wm}% z6!czPk#7?fWX3l?cyo9OqLU=s=O?*+HMj7g@nTJ##KP5n(>t2(KauiN>d&0Ho7dY( z62d4kMd?4uX#){cQ!JamRH&!eWW_@ucxWEhNhM6CDPPS-KNv>Gv!hYQi)%p#zSbz7 z^A35&EP<%!F&h?cjqZCj%VpU``}A|~>l6F```@>I=E3W)5hL3lcxf?+;I4ngJAl*w z{wIF+MyKr#N5|7g`~zyqG)|URM%2j7#{Qet8RcdB3;8(b8!I@+LUXja$8oJ=O99rj zRy0qh&R%o4Y1Y=v6(!~tolFcTtEE0iVyf`T(Wq)>%y}AWCG!>;D+$T{cJ zrD4-x?Bx)LQQ* zu#C@t^cH74mwA4fN6+$;!c2f#+A5gzhdEk+-{)a!Dv2`RFyb7iPvC?v`X`HqG38kI z`2I?vd4pC*e%bB>VI${&7w9U}1$lpF%A*{~p{Zp)R6JrWnURxY^GNBM|11|jHk=mJ zYe{;!6z4G5LNlj~+m9*#qT+UIJUDlsZ)O>rM7g5Rfi=`h6$dZoc!JHInaH7ws^=|pOs;rPa)8QYY!^ikyQt zf5?5_zcl4~@ks4bVfMjxR7C8v`7d~vqkDY!i^qIptT5@%U$%|4`qr4md5RpLp;R)H zU*dqy#LI4&Y3>0aOIE3DZ`u%a(N`<#g~fH(c+wloGSBo6+dR6!tX2FC?@H>e2V;{> z``>UzW#HU230jUl`$0bmk4;|mP=ycMR&1&`xAJvg;X~7h)}y1oy)W{Y&IiSOu(lqI zo5rCaR_1Il<(H$2-kP$E6R{b5!}OOp1SkvghJTC+>T=WRAkIkJyR<8 zS9cl;_^kyhVc^xwZcj4v9w08hRP!ARv!6HpvadoFps@nEnGar~6C6mA`O!r`cC*)- z6HzNddd59XN*42=vpv(qQ0R8d`0UYNGp7t9l3Y+gldu`b`XB#Uta6GkxVvr7gtniX z4EE(!hPeIP3no9nA>?Aqk9q9!8vKsgU|P;clO(N*2ZqZ#Vt0$p5{`L~@0dox;V_so zCs!H98T(Lq_?BU-iJ`=~)%2mzh&vwTfKPwkv`?nPX|57Ab7jBa28OaTEYl9S+^ppn zt>I{jGe-Bx^kc$3m4D`h(8zxQaxf!u+6IFef9Fl<)6M8IzaA){y&3pwpL_M=e>(FOJH1?3GLu-n zt}JiH49_TIzv4Uww|tj3Y<7nI%<_CAF2iee#&)RDpjoj6#yJ5)ei9Oh7KrQN`5|tO z?cFdW4;%)OA%~UcW2;pzFk4wLQpSG9npP`#^0JeoY6jL{g!!)P=9U7p>LTI@DH>%b zHRp$tvd@)(UQtG#_bW?hf!&vH$m1np0K0!XY>wrI`UMi@oIEs9R)1^yZ{_(ig)}kO z4M;a^Z^kOPb1baZ2~{{IQ(_z}QSfc9V-s`v>3Kh5 zldK&#-DWP{gx`5kF@M?d^QqBv)}y$&Znx&(itl>7r4Z+vZ(hBzYQ~mp1Rp9E;#^_I zA1Y-zadGGynnQGPrEHZAM`iGkvW4B`<(6s7=VqI{t18Of%ta^o zC+{>>>HFV4&(de?%MnrsOW|_c zXu?!}X*GwYLJ`Y>GLCbVz}7ID1t)jR$ravuxCGdiPI{vLw&7)$41Zp^pCv#Ck}D?1 zT84;_5>pn^?pw-%5(Rt=&YW_vgPdDsE*D#?mT}omoz>jgR)UkvrE%h;T}>-qv0|$L zP8ImWD>iFUoU45Qwr?3HoKs&omMJf}N8M@NHR_l%#A-9D(hekcaFtsVCI*fbD-xA} zFZh3O5=`^sS{i|xP;&#Hv@$t2x8M(k#VgM9Ehm4>N!H8JONkjYoiyJ(eg4L=&i<0O z|Bd8;f0w_w{_(SqR#g4cnW+z@A1UW206>FZj z@EhSGPmgN0gT=VgEU<}aEf<`4{DeK0tv?h{qb=Ckl2vQnm7Yk)nzy?*t+vm`o1JEA z#GA=J|BG4b__uemRd227uies2o2%*O;@F*Ew9^+?J4rg`b;_$Z)SgK;Pke59#eZh~ zGv(WeHCE0ad*spP4PQJEJXyX^{n^iV${+SF74~HZpAN#ry`wO{FYwGe3S*C{!trSC zvD#MnVef2s$eXQID)r!0=Cy-Lb98f-u7$-e+l)BE`_R7(3ejYss!8U};^@*=5;vFf zrImJCXf28DyY8LI?YUN_4bob4ELOx{f4{r=!Ri;wW7+;wr#k1V{>p#nPJ1g~C{K>5 zch)}RTw=p$Vd+~`;fnURRp-Fu%PMn6zD?p>h+k0qA0#F@s^;5;@E4R9yh`1u81WEE z^-A;yVJB2c!`n`z%;01uJ6bz+yTF4s_ZCQ0pDbL-Xo|Qw|B2L&ADwFYO*h%}A$8NY z3vklSQ5*8}rNrO#RCCp{nyVcz_Wdl~^c(JamX`J>cdogKm#rtOS$pr;7a?`;*zI3= z@aor}%oVA;tLZ8Kjz)>Yp2(Lg)>9PpBnqxm(|dp z_+RX7jXk(|R~S604sP-Aqx2a4{*PNpD;!=ADXTR$DxPus@#bM_h9igUE0t&OWptvm z*O1D~^v9ZUr}liZdHL1{$HtqT(7XK1=Yp~I=$YRiIrM=m;j<%SE6oe``UjTtg|pSp z!Pe90#mIX4a}V0hW_6q8Ht(RHkp*KD=Sb3@9a-JnDxLMOWSi7AnvJcG#<|ka+JjQF zJF2Q*n79~ze1G|B5Kh0+e6V@9XTKFxk5t+!`%qSDPaOQzVZWowhr`AJzbv&HGXy}M z95EV0v3crgp})|o^Q4Mu=U%8+M&l}pme*0M{qYvAS9R7gt*&acAPzf;(;+ zcl?xnrGBB1l>dC;fI8Zg!%YrXe=(d{?6_m)M-Sg=9sF|8sjLah>5akGuoP^DB0oTI z*f;G~D71{_D8VM{Vf9fzA5^c}_Nvc)n=d^x-fBK`b8GFTXP`55+MlINlU8pjowq3{ zt!{p!dWvH*ThFlYR@10H`wd3hs$MRj`n8@lJazk~`pEC*;*OfWWbbd+js5Lk8+$N3 z;$0}X5B}vZwd>5QPMtdO$8O@)n8(Y(Oy9^j zj}!jpjM5%jsT8G8rzTyPw8{RV&DR_Ma->Q1F?wc=nsTT$0- za&ztRJ0J92%RB=qhC-*1LI14=xDRpne+}v2Q%|S9ga|Z zWPZ$iD-0W99$_Cu3u9K7D|tgLWt`enMyoizCkh}hqf|*I>tt;d)v}w_RkNv_^=wmE z#LunL`47DGtZLcKpw&zp%P1*fl?QT6wj!!Zfo-Rh_;SW-?yaAGu{FZ>{Pu`i1}!fix@3f8K9-uT>O}yuV(M~Hu{I$fBEA#Hdphl`Bhp8{3<(Z;5o{%Fx~z@ zWVE)XF}mjFM+>d?^qy6JQ?;V%EpVcMQTfyEO=zjR={rp(z;!|l5LJodt7lrPi^ zZ-on`V;mK*keSbQ9;;i~b6dCAZ_OWek7iYGAw}?JD{QHm^$=TnUJ0evl@MUr6L?yu=@jXEPb@VLm#b#;rK0(KdP{5TC3Ebx@RpL;_T(D2O`qG%+i_=dEcclNKtkEw zk{KBnvlv7mGY-a*o1zc@=R;XSBhvf&l+y|PM}owRRbYQRSU%Rwl%IX0*)D9IDx^Vv ze3T%&kPn7mEXO&HK~h1oX2q|Co08!;vr|#6U`LB9Zqf+~&Ciq{w_A5cg)=o{wNtgn zE^P&I)AL?yem05;h?tQLyLph18fKT!@~#?dB{B?BsUKPGYzG>VZr> z7;(&UczfoS_gOF3^2UC1=4s-KD!*xbkQ{N5gx?~dy_oq`{5UUY~QQ@ z=tBAR^jGXx@4Ha0rB9Uqo7tZ{aNoD1YsOAaU zD8I&ke&f^r#=d>u?p`L*mw71RGI#D==Cy6rseL4t8HArq+{JBy`pJ(EqUdi{NdNyg?-+4hZ@)s zx$-gl4E@2(V!9dO@4WcRr@~sg|woC+6hAm5b!GaKz!9p-3HT6+ZCTqc;&ppNVeg`X2dB&?L~eJ?iR- zGKyQ?m5y2VOF1eQWa+kA+jBCZd9^PvoUloZ#u<{W@~shs7z=sh$>c@jiRto>2mP zziQ6Am-9v;NQ_&3!;r?j3@Y%1$6D+qS!!}jw3|;0!&DAb-eyw5 z3rX1!E}2ti`6xkVr4Vj6A4({<6BH}Y^D{~7A* zxoVCaoLWwzem_W@%nP%}incxKPe$tF=2`MTm{W_bkaEo1fAD?zGMq6zfUDp+$J*YL z!IXW+K6j=;RmJD=JFfGXmsi8Eu;8CCl3+|(93f)tL%9oq;XiMi2^VZ$jwyQIy!K3b zlEnu8l6fXvDZ&N{0a6j%XOUo`D~bQX8(;KMP^TV{W*Na(|LXmQtM=8(-aga4YxHDj z8{@f7XQgt${?MtVZ1m$nWic5`NAhTdnVX`L!99LB``OYO=Qg|$ zsq}^?lPi0zvt^c3%Fg|AL~kOQef#I{Hm0V0&g+~tvneM~xu_6tjH-V#JDUDa{&?oD zd*!=>>eAIf70(?%Hh0#GX3dwQCtgpJ_0htUqr)#Q&Ls~mEv3IcwUSd~Y+SL8_*Cuk zlcQtaP_%ZRy|hKblsZFI_pG06zLcn+isIk!i3}IB0p^mZGR_2S$v)^mw&)eFUic+^&^@CEO(&;3+ne>w3Y{ATN>C%X=zk0en1wR# z_Of3nI9B|dqlG0-S`jpIyj1O}g|Ro%^pYHDyq`HQ+A7LGso`eMF)vaXX$8I!CeKqG z2e>FSSYFLAE-tFKo?VF3^pYP^rSiB~*|#(9Qg;J84zmM~#SH!*u%bS z&G@gUBecIb{*?Puxjy5!%GBxNp%RzR`!$EyxLLAj7Wi$^77H6My>bfl;4KuW)nwVtsQXW1u&(P-Nm?>59>;EYid1IAifY3GHzg_}nT8*Vi*p9<_huBGL~kLD*i0)ArjOpyF>u6zpNjnGufurpp_GW(i|rGmhB zT+r{5;pp-pBv7nC!6=MV=~Jb!989f3Rq|%56@81^zGZupA0@k zU`@H`>mC)s{m4Gb>|`cSM`EOqA1~C}cbXkt9?5JY%WB*gxHgs)>~j*3$8wZ)xEZ@{ zIlnrRU&&`_z<5cz2O*DbW^3cAxz;Wp^7iGk>cnWGP9_4+v(%eM&v}=!xwGN_!`RzE z$8lYEo>he+-C`7{t59ebTNG69_3PF{10;ba#K4GScRduEg(gG+En17i@j5^YqG3k1 zBt~(#nw&jd)zx4%(G)?L@-QAJ0iYHQ%Sueqw1=7F9Rm<(Gl~*RjN;|yWD*h9WH~%>?S_?@1-&=76NB0_U{vyJSV$iQ8& zC9;nN0zK}4ZfQ(0rKmSC1~7#IMjO*YP)sjNo$r%`Uu7}92!me16Mf-RztW}hY_jWcF9t`sJc zH1Rvc)TJUeKP_C)g(+%zpwhe-A~LRc|SHgpW^ zvWs;r>YjqSMuDGFq~kP*O~;NKF@82y7VEgS8ICZ3Z@!K@-us@;G_<_ylv zh=xg(&G?+ED&6;2aYt{0Hds+jN{f+l7sDOpgbV*R2}k>@HeEC2B=D@L;Fyv7oTbdCIulz z(1GBsXr1|s0+B2Mn<=Q!eH?C5F>gweatP6&lPJz6g4-OC7ug;DI`dW;waTj$-Jqau zL=<$t`LAAx@k$9mR2CK0 z@^gHwLJ-224l3PdR=$eh1r}_*CVQ1$R*0EW*~g&*mQ1MeP@Q$Lku{ppJcKn1jF`3R z)>Wi>y?)R03A#)4WICE`hoC#kLwnf3k7?maZIXRrQ4>@!QGu4MQe=VN_i$;{%w zRPwBTG^_UaPPsGw7jkY`zaCb<{Hfqi%$e%*d}i+8;hEy~DpRr-!?VqAECq8fFU*D6 zSLXZ~zxo6J`tb{0SgM8JG%lLWf#UA2VQ)RiO=VtT&{MHvg}u`!ojGS1wa$3&)c&r* zTTitNP0+n`;Bm6gPCe_KcUHw@W{7cYPJLs$QeJd+X=>*hJ0MX|6$fxGwESSRs!!czy~4wjY+j#R+v9 z+rX8B;X{|lX52Gjom@OK+4x8(N{1K333hzX(c`2!R{Tohc;<_|y5;v>{<3YJVY5!{ z*|BG*n(PE?@8WOdK0dt2hFL(JzTy4M85e)J3Po`B_Gkb0h7mk54M*gAnI@ydZ{acL zd|DLKqj>C0B*bafsVAChnoSHR`dmL{QU-yhLVK$|qs2J82h+~PIwRCxSsqTQ@t4B!KqCoaE^ zw-4WS7WI=W7sDnqlX%vmUSD$gG5~Y9R|A;w^Kz?n>>EGRl$AcdWy~?Ym z7WzG=C;GLEZj<6gO9d!s0VYv6vza;OdoG{ZUB|^=^PUNp!so7e-c=`d(z_YDuP@Og zZUFq~8`UK?U-uD*Us&V8!@=uIBs==XU=tZ*2W4-s=x;p=G9KyPV5gW0StAr;k9=Ws zd*U2j+}&<;I)|y4Ly{C_yV!-&OWGg?@MG=f;6=8mwI?48cCvRCo)Jss{@0Q-XxZ-J zXPoIt@6xb}A`j|G&yE#u!+Ssr?O5_PGZ0V$=?!fOM5P#f)?Ctx!EMexkv-2_ml}Gb zC-f`w!$I<`aAElMS9Z@tH<7q9+_6+hE||Ec{zbF+3V!1(tsVZ`K0bJ_sDh6=%_mNn zgZK7(Z#j%9?mTtAyVgVj5(r8+7}+CFwj`hN&*OrU*Vt*1KQEwD69By*%OBa8fcD=p z#@mx=epZ7e&6vSgSrf`kbZ_oEwp7(){ku(X{$sUR#dc%a2`_MQ8OaIH!vXd1l@K$n z(xidl?L3&*5`AGPboBMpW*EcW9x2v$J@ma_Rs^i=K9~=53jykjZkri9@yy0fb^V}o`0KGV8VjH#b^ko=*0DQU1VtJ^WaBY0OEgwkr~2 zp;ZbaB`LL<4!`u_VGa}s&9%7dunWJUqV)(H>@Nr&Uo7Aofwe#Cu+9VC(<~@)EDQA* zakI_c#|SAlb%tV_>(xhHX(WK!Q47S=W(@aCLckz-%CrKFtJpC6F!$+6)Gczs8=ADe zZyx>UAAcDza4CtAIN=sKXEVnq9|f zVWXc1d!2sJ!{mW*o+ACevTD{sY9Dn&x?%=sWU$$^4uqb2gY%j2b*^E4K;KtFKukh2 z&F4dEo|&ig_(BMY^y^EzPgY9}1U>D2&O6>{V~~}?;RE~MSH%*>4uQN3}U_yI&Nrg8B1hRck@3AyZqnw6V(s zk?7^X&PQ(&UC_TN<6HWqTp5^FsgpiMb=F;$o}z4&?=P0~m!GHc1HKe^S?EBPxmUsI zb^%8>FCfATB<~IA9xG+f@>5DE3V%VT8P}{6M#(38LIOTb@ zVjHTS_sX7!Fn&i9j&UFl$8hAq-WS08lq&K(qv5pI5*}Yn#4q|yJ+ST#hIv!R2FcC# z(6!E+OK!#Ez&v@J*iFW?GX*no#@)vx9GJ1==3@f1(D)sF-2Oi{u;~VKWtpQJ2=@Ec zx8G;4|26L10i(0QOs@gGJ{qA{aLPyTOK+gpv-rgZdi_v@Uf*_q`gsuCJs_?d0QV>S zg{uRcM&e$Cu+;se}}zB1o!_Be7y^Tqjv#wMQg^IPxZgo zn!7ytXRhge_WB8a_o7yQ3h271w+9h}y~}|SRjYScm-WN}8W$=Ehb7y2eax@hxQPpT z<0VWRltjhM=$Nnp+(4mR3(iz9EyJ0!l=<|Sa7(x=TiP~JPk_sTmt?9X=b0Qx(uxF^ z4@Ymfu>%4g{jB3eQWd~Fh!%C{Ubx4!_SPvC9>sfK$gsw1HomNlU*p3h8$VZYa+lyY zM&G~xMI-kRUtkB(KY2Vgdb*`ZCqK6-G*dYmR~(*(gSMqRN4y}N5l6wy9gc<&#bHbSyqNuomJq$1ClH*aD3(9n$cPj8IZ2B~AIY7&P*}hLa z_3vU}aTNTh;)C%iDLIAyi}#rw+GTx@vM07vAH$HCUm;G()Q1%`H0qQF@#HF8pvo6? z>@}Gc049MmN<|On;OI>Sphpm#V29?*eNNCvhd1Y(#`LtWg5&NrDuPo6n9|FJ)Hqiy z)hQ37E`6^fez)rv;6U0y3c5q#%vVa$;)nVuqh#(4bW~*l45^DSU>USPhxcu*`zrQh zy>HlFA`Ot)G-Rl%Xe=7EO86!ZAYjJu8dZftIH5xPB)P+ziasQtAPq`<%3hxAJ}_j2 z%9JPgK32`lov8$VpjJw*#6MA$;#5xeW-y-T%CK8L3$(Ds3`j~1NKzf)N9KX|mW8Ly zl%(#dZsY(g;Z$9&={u7&18d7X=5lEH2QYn_!4xnp8};W&w-Mm#s&e7Oyrxh_r&npk zcP4!Z%$4r4nF)IwDXy9j!|JZig;KUu`lDZa#G4QUHc>}JT6tWjjxPtnvVa(abWWJG z5@|0Mgw&NU>ti1IctR6dTTa#YZ=`5cbFLa{2xLD8*VJa_AF`=jX+`h-cIrB}vpnD12P_5y_ zMA_q_us8v^nza!0Gj9^R8?<6Waw_Hfy{0(kR27nmbxglPDvN*(IbJmNfVO3W4^8Pq zs?$|smZnmapq>I8yafk9&^s(d{<_U#PQzapOS+vw6tu~I z-+63HA!uu|LbHqi-=F+|%`>5n{Z&aTDW3p4L1XNV`!Fc9qC{pTFGKbQAe^K`<=rNc zEK>IK95x4rj7fQ4mLT0$cs|tKsq}0_-n;NZ;)D7CJ$RUh>w*ucWS#_;Z>ts0VU61> ze{Okl`dLGXFA7NvX?oO!mN(%e2G&j+n=7Q}v6MW<8}@0$bv&9sjlc}ZiSFnyh?atd z$SW;)bJvu{gKCV2(%cYi*=AxjiB}GI2XUHgo>}TRPW@74Q#?@6U_4>iJVUu_L&-<~ z*Kc9Ypo+v3WNDk*})|*GiS3!;TH~3fe)NHf9s!+OO=m*O_Im3}!Vl@##8_JEpPgm4oH9bk4y5bBYeu1QwL9TF&xJ8sS4W<=+ zKi&eVVlyi#2?3b172a2aN-MPGY{7f)+KBTjGSkF$WZUyp&f%Z+MKInfI2% z?zM{I<`@0tKo94A#8uq>pA*BFeMG`3SFg~3sh*|gDO!(JUnH%HS%?W*WxkAvuzJv+ z2n>qFL?9b<5sHYrmuZx+V9ticdn)&YdWeag_f;#_#Wz<%9-HyzgUY>RvB(>-Vm3qo zVwy0*kUVuyS7Vw7?wK>;o;$C6PpX`90!Nbi1KBN-!I)P{<#1Dvph9G85e66&G1{st zINh58Uv{aEy<}?Et!~oiZOaP+8Gau+s2UxA5?nJ~w=c}&o)e)F8^_7Ct^~6#f0)Pb z4Z6*9j*l(fBI*t&5Zwg~tQ3SF{hUn4gC-|phiDw~2uUjl%_2|9rI=iKB>_-Q2`=8m zy<96YjdMinTx`w&mpYgw;HK2<*7t|LndkQeSgg>&%H3f_?z-%o4Eky(<{`G>R8*$h z7F}xoVHhe1G1?Ucv+L>K__>OTTiKRz`$5blbhgCD84QaXA#~YgfXK5Ddmzm#2JyGq zfK3sufaG5Cpvx$pa`kR^Ja{Kiikz@l$6`e{jCExVQ+ZK0mCuAyWs7_Kf*T9Z@z{9a z4#gTr-5?fL&ai=cj%BbL`%B`4KOb}iv2K2Y{cSX#G2dhhy)L^h<_DJXxPMTYVpf0_ zQXpHL&Nz}9PWS0m*kjC40nf$Kqh*E{!PMn}-+jwh2~;COLI^@46=bNPIJ9p@qFpbx z(<@fP*p2V~)w1*13kS-VQWFC^vcpHjZ8p|v9DR@!7wjb4U205UFt6~(Yhw?3W{UNS zvD5|n(m?S=v1gI(BJ3=Ys+q+BGndPrGH2}UtLD2NTj4v+t<}crRO5;1Z0}g(>t=3B z_w+H*xL~fCC9iOlmuqDI#gBx=iF);q&y+sDWccRim-N-?a#&G!g)4q$iT_}QmS4QM z)O3s2kH6$s-VG7wJ3n@(p`TcLIaoS){dJFDfBl8qs{{X$(?gKR^nWO0=3Z5IBb_`Tu_EXjIv)!J765Jc8`wbtu)UGvsTqW+K= zOMcH^NF4o)&Z^UwrYK+rThOfuPaMg9-TVgsdS9Te^v$G8bjHxd%z#(zamU=T;)+{m z+SJ)h|JZ{IpE>j8sUUIPo2t(kRqZ$sTiu%ryn$bsvGd0s?wr`E(_`uE4^Pak{blCP^Yk!(Dy;wF z(v08v_PG5pZYylU&l4i3{YB=2NVRk{jdt!$9iCY5cxMUzAsipQE7G1uvex$>Wlp^c zaBhTX^`$2dKjC@X7Te)DQhkZ%%}{9^#lExX zJ;;mVB7D@MICBOZ_akQQcHk6O_#X%R+{0ugI1XSu{C8`tzX!=#V8$1N2ohg>E%L}_ zJb&A*-~LNWF5fV>+nsy8uAV}%HcC?KZNH9EZJkc%;7RWpFtJhorKY$M=qHN9uk^Gh zU;6ju3w_tfwE&RGgWili#7*(sg8l+u*G9wIQu(=`n8{`q#ncJbx ziVo&or42U0J9^6?ixBBvrpcD)*E-a2?~|RGH^Zex-niK)?pVvNFWhvCV1d7*7miQU zqdo!q{&INuC)Xd$_Xgz~+uNV$Ekpg7{Zi^3;OUQrX!QAV)YlLNf`GZ5<>WKwonles ze_AZ^Y|9P-UfWV^mc2^Q7ArDjgO#%iMus8=0^RLvCI%~u9mNB@#wj0gn&CQdIZM0v z7ZL4T?ReIV9bf9HUG={xMlfAErU4yy@t~=<&*9yXw6a8N*TWb;S+#FF)6(>x7n-zo zG-zhCN6eDgM{k(=esOql_sNC-jq{9uW;G(@C+qiQZ{1FG8xHo2lzQp8Li0CFXhMrb zPBjNn)mg6{DfWqI8Wk_l&F#sK3+1z|?fU$o{MP`Kyyx5Fz-7yVETD^0Bu>-IZ;5IOY6`I&O|`yKaWHy@83 z-aHRT-1E-V(r9IA_#i$RBdD2=xXo`<26e!yUtP*9`^8tB+EVEAM+OyVNX;s2o{l({ z-08U3)Nw$ukE>{Pve?XYoBKt!N#pwBZbH|i3F{g^3YNYQ3gR_ld_KI4h=})akZL;`yvr`+n%ar* zc&L2$U0k11yC^b?;r`2=Y#zecNm}FAjSC$z#Ha{qK*CzfiOx^<3uvebWu3GW%{u%z zNk_qg8%4JhqXnXj0u~T{Q>-7Sh-#W5+0?MIT|iS)LdYqYPobkBI$dy31_6U{%oEV# z3jcx_Tne8TozAk41?D8lQmC_C{KC4Le2ZQX5VQZ*YUgC~8qBz;@TM~#t`-Avg`O$p zuh5GEfgG^-o2LHNrQ3(rXsz_JbaLs=@#B?MKO70`OT)$62R{PZd7dkk#T;B$Aoc-V z#xA;;kvhwV5ro3ZWV@VK0C%r5Sl2}C%@8wVzFddS_P~smCk(L|OWqBh>ABg*y%PN5kgbgIjXr= zfr*!DR55o1DJnB5KywfsS_A%Xixps*4ln6mu$!)#b=5TYH*oA_HnfGNE3%`!BdC@5 zhl2<0RUzPK1o|Cc6l1k@r%%Msh?LqmBeD(;)rNdIZaynciHzGTQjWRZw{H#mt{ME^ z^nm(w!G~F(O5opE{}1DJciGf;U_v?;lhX^mZ~~azK@o_-273a^+r(J5=udcEz)f-_ zW}&U_0@FQShC(bU13&v4nyD>^{3Qs?1a0dGZty0^k(NSc70YKhHz z5`D)EK$^j!hoRt2#EvV=Yn(Qal|mbwPx@iy*7-~C*td3WVC0kbt;}8M%AU$yuph6U zbnZmZb5ty(?pJi)$5;IBKO5hRjmL=J z0Fi8bAAQch{Ia4~z@oyx&ELH5@7XZiSJEvQYm}%CHM#AEelORn=lLiVscXTj)a#}D z&2EG5*SqyucbQb^o~a7t3{%)!koDZ7b=$g`SpsvY(rGm~Y=>(+HGM%);|tddePQ(_ zku0ZO{hZmS7hB5#IkcYfPEkroCj-k&$?i_K@g2u(tR>k{`nq5WbWmZ1uTw0>OAgyl zE6wc{<$*7Mz=mhWnCTKL>XB;TU&5iKgmc?;lxTCyh9$(#%K z2tM@YuBPY$!X_S^A@G;+IwHw}rwH>mgS?ah_Vn zcq9c>YJB(CKadue*+3bFos#x!AA!O?6T?vEn#*F|?vT63EIG3Zb*iyKB(W2OVEZOG z^KxH(ZtS4aszMy}UPl!L|8*9ttci2s*%hyTR^%Y)*c4yv>gaWeI7GFG&%xG6N!6YD za>|$Mn(uK?1_+tXQI%klxz=X47*cWb(7y&(kE<9*_`4F!Fxw`JyiB^0H_1ozam}sE z4Yl2^82%>o2k5!5=M9XX$*OtwR;XdtT_(6l;481aTMoLQu-mn<1*K} z3C(KSHrYaogrxCt-TIuH%-M07(oWsdvRgyUU!Z+X2!}ATqCi>b65y}8Qc=nRlhqx^ zshAA{t$+#Hyl|%6J?whRbXd*Xsv|ik|Lze*C)8m~6!g=gF7MFw4!h)~kC-Vn-aX+-=Uk45k%&MHOK5u_GtlseyG=Uc>US3f1u0t$kReimlo_i zllOX$IF3@*>%uQnw#@WS5U*2u=8C;S>j4zu&`5Ws$yuU{W0dzIO36R$Q&Kjl$-&Fk zlGf{HyFGBtmxWvRR<$p;@`2#{0LCW7X1THyB=uxAH|DWJ*Il2MSEK>w;;Pb|VRVKq zQ(>JKJ-%0nRTQrZ^nN9flbgwquT1DE6}Yi0!-7>jYYho;Z~u4;h%ZJEgK7@Rq>C~I zEKn*cRHUO{QcfXbl_H~q*$}^XyX@fwFn&}>!7`VsMl2YP!Q@p`;#DxRsI3sa+Jk|z zj)6Ukd9W8Cnay}>Rk~4pExw5Dj&X$P0%9xDtOiagVe>{(O1FtDK|t3EjF*O7`gys4!p>pBxW)X>VatT(+s7xmL5DlWr9uqOf)t;cW>C4Ru*5dzJdiL< zErtqBi?aps-L4PdM;LH|n2b<8WFko840fWT7+lh@plOuDU)Pidk-Y%(c^=PHE3yT1 zGZaHVp|S%#Zzy~SS<^5Q)EuYXz62?4DARl{Qi&=V%uZbWH1+}@r5pdYM7yVDFmO*A|3@Ah5e991*O}C zgb~7UoOp1Jcu}|Zt)H}@2jWbizc7|8dOD_zMDn)gDRHd_04uK9#9lI7Ubkf-7%=rDQGM8e#TKHYP1}Sq zLZ1rDp=mFJsuGH*WK>Dd6<~dASY;?YeY}x7=&K#7C>SwuBePA)Q>qX;pg2{kNDU1? zNoh(mYO0*VTOj<1dtgVujP8Yv__I`b$(Cw>PYIGvkp)|~QfdjX+=OfrDVV20tG$H{ z-8aRAHLxh7GY6|MwmG`;jdC{lgL>ok?Trq`JXKgU$Wk{@qTWrmDbdn0%p#_4WznYN zy0lHP7TL0mIfUuqO5*{}FAiRTsV6X?sI?ITX~&hJ4j#gnSU~8=S(Xn1VA2NqT6*Wd zAl-=JQv!+Me;b3wP`!$6m-E-iDrRHFk@4nnxs^`p6~n^}5VC-E2>{M<8H@-_y8I#%aegB${Uy8_XZcpGl)Ci+06)=D(-GSZ% z$(Jn|$3)x?$YKGOE2a`c09Gn^iAf9#2=<9t7laaLlWP^V+r4q~z9<^YocJ7#mwa?* z2d*+Dq6x*@u`Q*2oBmi&efYJWZR^@;ZGX>wz2)uYt%t7}DN-fx8Y%YgM(MS-@?7?s zCKklDvkCo}Q9SRaf(Oqg#9^|CQaY%ICh7}`1V3$p&`qV916kynWJ!WThcIXDILoyDnaZ+WjT+;T>FlC3#Hh~de=`06cLa(3XX2TAGX zm;Tx-Q+UiOExDgq#Bm950S0@_A0$J zrQOf9FHW{@dx0FCIxLSRo4RMZ-BWJ$&_X%E%P;jcj=eMy-G(@W46K6k5s~$trI*X7 z21(U1VU|U?j}EDOS+`MK6qRpth-VL-o^n3oln1kguC-!eMdT44c0T&A<&i~!ZN^fb zP>xkcsF?r@r4lE|PxlEb0%XZ(ZrfsO;+BY<46@?m1XO29t1 zUzngY`fC>MIGfQ?8vtb16`8TnE&f{HSeONW^h#mp)L}vbyud9|1%xFvi_*HwKXn7?bYVpGLw+M=8k!7r|hS{ zIJWJ91F!T%`q#5GzXXaGA<3q_tOGn8LwUMeCGD73I|JI$C7;W+xTHJidbjX0WyhLy z24eZ_X7HmX1x7ovkZRL!mmquXEOeHe$JQPZ=c%|;be}3ruh-u?exdxl^3rzQMSa1d zx+e4={bq|z<|%Y(P%R=g{+tf9dyq==G_NmC0vu9N+MOo$Iy?P1*B^*-79KEe_n?fa zBlL4NgrtS58kJw@$oQj3m|yp<;dZdOdFQad4x&O%@OZA=Xf@}6C?2GT7c~n^BTfAc zxesUi#bf3+SrmL(R_)LcZf{-2THBGajSt5+zL~>-+mx*mcFUop0JVR zjr{5d^s|%6(NhoTeroi$9?%!*J1BhdeQ(9hBF7oLvONhV?qo~hE(R5<5CBLwDC!@| z^Ju%06*>SDHNO;ema__;Lg%Ag>?{2K{l4Z1r>3^R7dzDlM#eQT0O?~(kB@9 ztC4U;Xn+51{(v)2C!bIy^tnQG)NY)IVPk3N7UeWr#L_Dy*N%OIC!eujooLdh?VF>c zTspX*ots!J9P_*fbPB51O|p=%4%zd&>pf_`R6JtdF?BS`Iq8dav~6c!O#shbq`4ze z-GeCCdX`fCrHf_dhJdpJC>B5?{M?ra>tZiy?2$uF8q_}S}Y@WJ3lumWrY(pa&R;94P^$4%t#6$L_JZ`dZb@+wkDF^O&i_5`34@h2J-x< z^gyEN)XaPOQ_&v`^_=^x?I|^z*S0{gEu*La^pa91%_`^0 zo2?5}L3^P|VnNFwZEAzJ4;AtdS4UMI4hO=e*d`{4n}60(_x_)8L&=t+;VL;e-r&9s z(Y}G11~si`Yx2CaZL{9CaEOm+4JOa0O(wERP*jpI7vRf9 z6sUw7)~QMCxt4j_KS9uw47QbF>?uQu{Ad#3SiuHxtbe4i*|R0@iD|_n(xs16$#zo* zLRe*=w z@6gbF6m!a~-I*ZVI|2XFjeb12fba!D_pzjm%hnm|Z;|>}b<*izRiF#~QQGN9cu%ww zgt8YE2GVoTAA<>YI^LzDEGVH^!R^9iwzO3H_kxvvSlg})ezt&8!Gj-no^DkJ??uBM zFh6w`PA=b=P917qNkVOjWoGO|6^@uRZe$h9ATo{s06gU=LMv- z3UJ#EGr5c590hARk|WZ&l8gfrI^#+?q(Hcf4s8+%1XG3nK8JZ}q-2&ggnOFO+MgdX zfb@3+gkSnZhK#)1(JN|W!_os^-5huVSBMb63uS6 zZy`95j>FwICm-IcXYDe>$4V(fVNc$hrx2+}hn`&r)qq$EtKd|Uu40HGydjdlBftrw z6&Pv^8ymJLU`KZwX)*eABl>yvaT5Yw8hpIZruZWbaL!EAKu#|j`kT3+MLI0c!Yx82 zIOK^`nr!0&;{u}xE$oB6=se$)#O%IWVbWZKy4aHXy3<;5&3*iv>H71 zOA$Xkar&u_jp7CGHHe?sz>SHk8wCT}`B!rrxbc-pt-A3xQN@72i7E!XYpj2DlVflE zHz$XrR(~sT&wRd^hz0z zB?$51FVL+vZEcOYm{Zxd7^jwxtILFk{D!a08Yo!T*wj~7OvpQmP<%o?3ij7A$vjqd zdW9HaZozlX>dil7%34Pc5^~`@vFYBjWxzmx>%*!8nTy3*BIj@!E>;ESbDU3Sbseax ztmD0?2I(VO0$E%}Miv*B`btuO&q6zp7R6EVp4naMY}rDRFs)EZt8}xld?pjA;-Gv% zbe5AGbVs)#;j=;SBe)pRPWsk}E3gMh;FgVT7Az-MZL z>8IdS!vHZxB-zf>M?!6$bZO0(y0fFVq`dg4IhErM;&2a zW(o>pHzs(_lk!IyzQN~}fI3)yY8qw8SO$8N0TiGFRg7m!evlDrS2QQxfi;x7vvl-F z=DO%{kYYX+utB~hA3HgrxC5)sIo)~I&0Of)*Q2>@iryxK9Lciayg>^r#64cFGNF?u z)&Mq8GiFHE1ak&oCKW|sN;0iEYcxu}C)pDB^6-}=_*0ngT_BB}U-tW^$Q;yfk7*ATh1g)PpRvrG@68Go?wTj_Swo~gg8=hp+G3R0Nt$+Anm)8Qg z3p5{}LyqZz4y}jACp`V}vZhgEIjbk>T>m*rY>4_;*SGmAw(f563=Sx(JLvqpe~OE$ znKPeQ)p?^_6$i`If%0_^=he2;`c$%9mKy#lW-g_N{Cq3`h|9-bRA*_tc$oz&1&YFY zPyt??jC~*Js!WWFfDe$luI^wj3x4Id@39nZgrL{QH42(T6b;F+SP(!*dL2Y7vOeiE zCdqG!CMmWdEGo5vzGM}J5-e+aCD2sI9BRRagK9epEDbib~6-27fk>LXr(2j@~sWwEEXz_r$gH-~dc#aoW2V+Byb7$9U zm6+7T-!MxNp~mGInvA?`!siVsUp6pTDOO8<)s~!!VsixSd}RcP8~~!y5+N&537A4G zWg7W6(G0ElY6V;cy{rT%ZWxpNa2#tIGu+9l*gk*KTfusiq;bv0+BePCvWHaxi_k?+ zkze%UkOy1Z3aSAUoi4jxvsKQ-wywtS+2+$ttuh^FD-8Jp0r9Bh;q`Ty!R+GR4~FDn z7q@WclOrA4q)4g>9brl;; zmTF}!uEPev(n%RtrtW^6ri46rwHfgQSzmFCw%B+AQ-@M%*6GxbVXjDQC7KN_&>G@7 zHu94dO7kjlc{h{hxfSy=O(4w6lQp5{Bi3ZW*%H!?V<=8VG$&&-D6`3c5?w)#w0bi7 zhHw~WtT*0Pg3~ARs*tcDY(}OBGT;Ty&H^n&$HAzp5*_!5lo#f`+^J9l5g}F)I5aUM zC^H=1Y;1wV&Gv$diMZ+z4x~YUbmblg`y!Dr6cW+%vIM}kU<7&0`(?gc22g7#T6P6h z(nXuWb+^f+#vFINuGW|}r_UN*UYwzO{W_K7v4j$!#u}_S3%a954=I@7O2r8=1tmaK zWEX95?Kmdpan*%{^Hh`NB>@Y#jt~oHmge!XW<&0)N3?o^E5=EU|g}Ob8ug zQ{?-EOI)c;f{r^cehZ_B_#YlE+m|Jj^_I5Fv|9`I$mkp&?a6y(|B!kj;SIOsFFR7O z)gHFl2QWmiGMP0qeVN7+g5y$xsIYWJwwO?JQQyEoV-#RbR2RmFMn*|Ri(Gd;AmWEV z@6I~Z_MNSu!to$qs3(AY0Dk{$ek6j&F|7 zIRxz+7xVnPU%h9zB?~M_F%R+o{FZGvtx!+PpQ8LBr6c-Jm~y^^(Wuz)iMHw9oF;j# zddwbJ1QqK>&|n#$p5q%sfi;=sRTP~-5F?IA+>j#jic4r^vzu4w>ojJ;5K&2-h296L zGU`(&f1#*8y z?m|#4nU8tj7pI)B7~a;E%>O)jwD-!8ZvXLz_i7Jo`?u}*&`Evb^Cxt=pY0sZ_$^KtXC0Bz0nCMKs*qiC0S z*O?Q^^C9~;{_w@(#j(RPQ!igI&V)nXF7JUbaf*8#f9;%{xIu$}mea)Q9-A8umZxNV8<<)Jr)@N@Gdj74* z{GH48dV6aRJz4mzGTmDJBjbUUxo00(zw|#QF5G`!`)r@~p{}*6IBc_>#*?er%$e+q z-xK<3Us9=_G8=7f*=u}FpEDb$_#Sg=;SX0oT%YSj6?G&{?9_)=3zZk9_>9;mj-C?> z?#$58MgP^|tHsIJzw+VXDerkUbCA13F9+o;d)ws~Sd;A&Vqf!w*zdckAAath%sT>{bI;f??sq-mUHbYU z3b7q^|7;LK(yLcbr|||SjkoPZeejzulFyyN>9Su%Y0o1ZDgJ%Os+Ux}%Hw$2#zPI6 z;yAc^!)V6CPJ~t21|TiclH(RrRVYg%Ma;`!)y1WyEIB3a@=?GUMv;a|#Rb2~cC~%5 zeXgw!N<00RtGlbdeN)$xtvwXw0Em&+))$^}I~Jd5H`7~^H@~Q-Uk~~p_uBri6aj!B z4P?aMd}acrTeX`LHguQ^d&{4&XL??^N$GQigU)QO_S2!_$6nI+nQeZoc5sR2_D&4G zOcQR2rhd%%!^Yt0+(}=bpeT-7LfESv+S7CNf8aI0+2dE1c2@~I-zTrRGd;+5Z|*(m zuj@FSyPi;(@loTf z#>jS{h*7;?CIlx_?YwDwfP%Ox(`%*{cP9>3?z(%+2 zI&}84@dcXw)1}d+Ht%t=iv_f_)WsIb-U*hake`CZl-35%YA35Uf?miqHD|P1tbZ?V zlj6&kxEiuKE{S%tmOL+@aT}wZnar5;DMKG?fJ?U4P=HCy)9Df|s?Ym>BCIk>Pb$y* zBzvp)pQQ9NDLH?HdZLuNPfHGfUFvNm0+xvzprL*N-@uy-968x9{Anwtw*Gx@-5Vvl z3@BX>raqd03KPuL8Cl|;pNvYZmcn0ho+>Rut=L0wV?~nk-*QHwOw$=5AkR;n?eQ4t zv~`bk5;Qs1ubFeAzr{iZc$BMMS>v@OplCE;he(zE!9$Ztd+e3{<-?mRXxgqW6Bx16 zNulCv=WwUPeGFY8yUxcBrEVERQcs66((@r@glt=AML$KCVuFXqB3)e#47T|aq<(en z4+!AnP88>AlNq#ngZQ+L3xe7Hh4Ke#OAscSkG1xvJR`#Wa9e>SGQLpxTAwKrX&T{cUC`r5cH~l4?q_Rrq zT4#ZWySiQ}WW|+3#;pgAO7>PA1e&Hjk$~h?Ci9x1WigGk12>Ek zYq8Y>2@7hbuj5W1QIiCa9`;i7>^{f!F8xFBF1nye^NZm=N1AausOWP$Gd#3A3nP4o zpSrbD7@yiNc>jQ55TzF_W|oXD+8DurnC)isp#`mLbm60bb>typyL#F81kYyzB7^D2 zV>%nrcp@i^e*0yI>*&~|!is8>=vARBdhPgP%B#=;r2@3LL}?S$GU|Ph#!jaL@@!lZ z9b~2$yS&#)JrOdfTH~Cms2%wgv4(^6QVb#>cj$7Z5dh;U+@tfQl8aG7WZvn^X+^a(P58;>8-2giC`B+VTZlp6Kd`14{w*DxjncpvbP%3 zpS*sU-3p%HN=b~- zZZj^=XERA+n-+4gIOO=AKJIxIm7}MT0aYK4je9Gc1{G|_h(tC< zU03XJ*X$yF3x!29-kGwsB8tkJ}&aBQCmL*Z{uo6^HHG zr+?y=ANAd~**?9!x$(_LZGi}|zK47taDJ`#s(ZIZ5OQu*c70FKxj|Uh#Xq8BH0c3n zqb>kiaJMKczB$6)t26sg02)_>Vh1>WM4&wxViQ>!2jp_o;yOj=5 zUEr?|Z8!@!UMp}!a0JI89LNX%#AD0w6P%6zS5(`PP$STdudyM=2=qw@%9RjhUzZt< z@_1d`bX3XXHh^m^Z<-FOS^)B4M68$(U9@#vLHXy__kO~A z;*IbF@>_rA33q?scmIJ4BHcLf_p|!_tdsPgW?S8nm63tUoSs_I_iE-gf=vi_dtgGJ}3gC``C^s5V1Tm>H|no0DA+$!`~hms!BWn@opj^H!E&(~bTRQfUV5_M6t6ZZG zvLL_&+ir}SL5)@Hv=`IcWPlwTmjd{#576LA+_nY_%;s?^_A13 z<_^NsO80{`bjfH+?_A>qS>}dTleg<~{w+^;{gmnfNxaFYbsrfByEBEOqDd@6sVkmI zzGClis)if9hEjUAS1~TSb_~9cEv*DA&cK4bQd#9tCUO0=KNyolUS~Z{U)QR;&;FI) z{J@S}c9dxLeflff+%F|~!3MU$8 zH0KzpmtafwnA!oaO}JFhS9O1p(B{J+k?;5yINJ@&WW>d!o#}JNg*}r95V1c^OKfVE zJ`zmWP@!uE1{4d|KY_rBz07PkFd1qGdX`70dzWw&be46Ry8W5&j;EsAA_N@K8VI-m zOQect%kdrxERlyk71_+Rq6mNmDWYrAb|J$qMc70td%C4MD08QCJ3m>jsz{L5LX`~k z8f4hJ$MG-?kFgLlK-vg#fM^S7v|Zbh#Yb;`P)f87(t$w82Dp^nPYlc!Gva8N)zDk! zl?c0sB|EPg_D~Piph>iCl?BX;=b+cq@0g4?WGe&M7pV+|h5Mn6bXjVLl06Oc=m-!j z6!MU8(?SBPd(J@;a%HoG_pRvXzv^HK?ZkA@$)rcpYF-d|o7$?dxSYUMVrjz)E9qE7 z+2W=P*eC@RupO)?aJpExF+{;U^Ul4f%MK3JXSKj!V;8Zxb&3u{*X@nll0K+_VN23< zYzR{nWL!jgQSe7RJHL{PqdoQ<=sSvha_Fq1zzM#HVbHvc2NWydCbSk1!zx|A z0xUj+s7FB^pmGgy0?C%_D2`}avV;N`Drgtp7r(@%+Z;MSboj|>xf7C9RGXBt&rqTl zl)NgT)`~0{Y?kIn2}KJHO^R>mIAu;X2{)RN^lj9`4SZ#RD|an*K#i{p)F+>1Fqtwi zXMo6Bu}6=qHu|ai{~_&dpyRmCE5WK_k#5UB=_(YOg%(ZKd;PjuXn-Wpgcyji; zW&wsMpasb=<8go%M8k9xiHz*%_{^@Ws$Y{05exwu%22VA08mS&WqD1}v?Dv2V*rM1 zI&mzKrgNA~=7eNuud`=nOfpQOWHyt%1u2dbCp$Z5TOu0hpQ`usy}$e2?|zmo;3h*U z)*qqjsh=Er$4pAu=I>}lr4mu;?M9~`ZMc)PlW2oA&b~ktma`a zh*tsQ612H*F7u>WF`b#?eL>#_@WmkW901#8X$zVJ5||~tY%0H(qZUjEP6st!qqpDn zEeoOK13p61G#}SZ`^i%6ZBU4j&TGuryd-c-2aQ6~s)Dx0Kf}%8?~r1x*8oiFgVkIg zTHA?O>#8~117{%fBUCUGz=vn9q*FBwGd6mz%bnJQAK5Dz>-D%rIYv+xrDeS_-sr;h zHV(PgMQNvIjkIwKZ>Eho0#~BMtMUTFPn>sdVZJ$Aj?z>KN!( z1@g5f+GBl0d74i#n)LTskJjHoli}(Cem2b5*F4k&BL}iL`4sMg2c!5GYECs~Gn$)$ zEdjfxJNOjZ1s#li3|h!Bt<>0%?ii`WL}Bo6Y(?WeNNRbhs(D!h^>&%J5!d z$BG|&0GXpuORA{gim*6C zYz$ofU@Y~3I~oB-8zJ$79>zTYpnY_qg9wi(si^>c7EeiA)wBh2<3E0)>+IG-={+oW z(|GBrIxeAUm@n5=I)3@FCko_w#tL@5<+#VQ^m==*irVX;=yy3!=u;uMBff8 zV)7`1+JE0S#MGcaDaxBV9~R%f>SOS4A6)siJ0fQc>8E7xx9N!F{eaPJlWMTCjLkc7^~HmV6LA6Xp{f0Px;ta z?UTaWwn_p@M{rv(Cr~&$`5affYd)r3qyeTu`QV0w~3{JOi+< zY1|h@*Tp)O6r8F~ypWBU-xy)M{`$F0mH?lr-U0Yub^a?#JXDAz#ofq zBiH`(9i1b&?jiu5(#{qDm-+9usI4C_TsNZ1p^t4e%a7-uyMMSFI2_&U-hHtJLCX7o ze+Ph`2M+*}5&eI?i-bUsiWQRMQN!thrkr&U{Bdq_9?3{(j&oQwe zqJKBjcg>h{>wtW?+ksKH*Ch>QmLlKPZ821QzWY8Oa+vJ5|5VLXO79`1><2!+h4M}geB+43Gj{ky;0qWNg#{?W;fWIhAZsI`(MI{YN! z?ukJY1d=U)5}A*iyE3Z)Kv{kXvA+*aX7$N^{&HGvj!gBZC+k5 zhHeTm+)&y@uk3Fc!;L3h@aY;$Ao(@W9s8eDqWV`U0Q?17fBn>NMR4@kOb z7~O9F=qNM``bH;n>STW*@<$(lB<8PHu+t{mQ$I_oc;I_2OH}lKhI*AU3ZKVDmukjl zv#5RP=Mr0KdDbuq+4HQy4(fJ03LnmwiiUO4OkXN2!4r#j9uX5saB>eX{)%-8=Mn!= zrk}AEQEK!fpKbK(a-ji;ssXsQ0U&s|QBQdRwtz{Qf9Q^x#aowNzd{W2S;|^r59!3A z;AfT$uM86vt?Do;!f@nb(cO!5^6r}eO!WkX6d>qeE}8yb(ILz$`dzgxUi^g7|3=4i{CS{_u*tVGp za8dBD}{ZC;anv0b7XZE)gP3smR zX>pPa3-%t8EX*WLDBxt;X@Hao%<~#CV8X0jcNy6e^Gy{KFfBw~l|6lD2Q4;1h%-Sx zqMOWj)BxLK`6MzIpOdaC2B?~pOZ010IQT#Zef4kEy`=j+WY7JRt(XAV-M7$|{gtva z^0EF_j3t3^{*URbwQ9Qk4~|&F;$bU!H8EHO2qsi@po5<3GMFxWG!UXC*zb@I7$4)_ zEigkfS^x3!mwDcQyf9C*$shycyCO`MKg*e4IY5xE59$@7A5>=azi*}mQ~g4dq`@%v zOfCJvhJrgPul~i@f%aSf@#EgmO@hwKj~KRs_;z7|0j>0ZkLsY6Dj&2-MSRat`#)$X z{bCiM=!3a?H1AW`>QbWI!?d2A*dSfxsd19WJ_yMKfHcC1l7&0#;m@Gv7t2e+^dIF- z`r7qTF;3c3k6C|oKp$>C4AJCK5kkK<9RziA4CNgbk4&O@_95eHYIqHd0|!nN;Jmkf z?U~_by+7jODPsGhcP0+@o-{RHLO7$ZF4v8;?Z!O&HU+I}Gvgl0`5g63LwgNVB9KOt zebA=9M(idu8L&;aSy~g@`^hltJ6TCz;syWUf;7x2HsT`1+2)3NPzUkL*|07n3#8dw$g8Gjn&VM~#{3imv0R#RN zE?AA<5HbC67OOWkP~U_Fk%a0e5?I6E|Nr__v~Hgliv0%{IU*G?p;S0 zua$3FZ@`Ohpp<|)aiKTxPMKWs7DN0xpwqj=zk*Z#G*Pw_0P&k5sILR2{3#LC{3V7% zF&@Kg$Q0H;{x`{efs=CCN~oVd{tsK-+yjLraAZQvb7n9t$`)i?yDIk)6ur5X0~K71u}W& zD#3}-q_Not(h6-e8?nk1fO!BUa>kNrX(NQwMu4(o$~nm6Br&ZaalVl=4R%dD8;oN41xLCQu>fnGA=b!3+Tx1CsTCLIi^E*Qbz&sG4SnICKeb>_3#|YEHG- zvgtO`qH2Uue19AgI)O;OIMyuNEpR_JV=Tq=Y0XIvKn3)kg-aU$W!eKc5C@~1OT;6I+-Js`y7??uAgQr0$&nJyp_>4PwJhwf9)YpE0~t4 zQBbJHsrNllajU)@jRbs~ky7Wzrar^a`;G6)-DI07CO9ctT8pyC=tRL zW+88T(#-)~9zS9uNS>w{^0ZVa1$!kxfa91_BO2B^--ku`2?V2@Owf!Fi&$jce(|#~ zKquBZH6}xpT`I=3#)gBeIT)$wsrZ;_IGWRKfJ8^3;jTRkc{rRq@r_6c;jZy|1M@|u zn+IT)M_D02x3!xlm$90QR1f-ycW|5#$3hi;)FeAs!W>rm)FgJ8dn{J}rUP69hQ46TFKo0Og%Kw^C5OE6e}G$Gr3|%(r@8@pl^##m?M@$ zwRQ}jf|vq+2C`y0)$9t|qYZU!x9WnhtLC&2p8wUrt)|__dFP~PE^x;>>Gn4$(mWt_ zPs+PaB-G|UE=Qng+hpFRth*72(*Q}CLohzoVY(YYly4yrPu}i*IlW#Y4Z~Sc7V;U8 zXw!ab76UTn8x$GqwOY(Eeq#ZrJfQ=fRYW`ls55RsP%YIVZlDWPZ9E85XkKMpDE=1x(aotQyunGC(DsV-Jz$;9 zDD+csy}0H;ApJEkA-q(`16x&$1a}#Z6y-pw#;GPlwcOCWKpU6XIy>`Vz$w5CD+#b0 zs(^SXJS#;8?fce-+Q^Sfe2( zJS*0K(#Z&Lv6tKd-y(3EI23*Cpeb=xHyxLF*d#8b36y1YJ$ltiLa%B0G{<;JdN5QK z*a|L-Yc$qdjdGv==!LftC&rB6Xt=n8;V{dn!04xD%G)SgxS<*nf!=Qg5c$i-0{2wr zwWtJlNH!3<#D$&Yd(_h~r3CA!yt5HABfM0&9}3%Lc`y}x4juImRc#qXLjh5WkTVPk zmr1HnOOaMOWw=meNUJo|(<5e(U}lzu+Trsdqq_r-idg4WSOn_l=tUi)$Fnce2vKti zkU=agu~9c}^vF0VsgqIM!U4d{Q!wP$~@gh@ctME(RoKZibh`2)9bE&GCdsmt2-; zL-B|7v6vt_R1dXumG*XOKA6Q2`>4i+>S||+byj2NFf*XbVm;6}Y4lz?PTpm=Rpybn zK`yrg_#ti99Nsi$td);2%8F~~ZY_Iq3Sr3AnI>!UDi0vwQ$AniF1y%y3 zO)|cdMLm@u6L(iI^sq~`|$;-L+MFZ?u}n8xi3;W=RS~1uaRNy^Lj>cL4CF8JrxiMn3RT_0yJMJbpo@XrbVcSsZPZRWGO=}|f`zRzj ztMTz9?7PwkxU9pyjKu(1NY+EbvAf^S`82t(#3Y#X*k73U%Gfp=4pT!|o9`iDS{b@5 z^aT78cZv^P^(rmzH8(+3f^&^NP~Z`V*TdyVAo!fEecfJ_dsPJ zRvJ$=u7iKqI#TNRRmQD$?WzCNqW4|?%JuTwStpX2aFBVfE~3%uL7=%$9i;pG<1XYL z3kZ^=?V@seP?jX$v6kp=mO;F|N^WwVhz4S6GqNN7z!4X_!6-EO8S^(uHM&$)05jD!sQ$)> z?DHJic5ZQ=lSw(lMdLn5xGfq_Le~*Go!O|7ij^=*88K3FYY18W+Afum_xK6QR@4Z= z1Va+n8*rq`X_^L&u-GzYw5ka1#w2mm1w!efartng^;xlJL#yiDdfxyFIrv0Q?cyMO zA#$57<+j@CN~4L8(F*8)0$=DjkkbLuXwPAP!HWznN(R~0gm@<)5rg)$Ll*@elqjU# zz-+x>fF!?HEMTg*{hdEjHuv6@(SUm}7FH$|fGR~;KOfYPj-}X#0xlv%c-7607z-dA zQLlkm+?zSt@%~}VK2QAySK4m(`3lI3O;ivHpT`X5LP~L-)AU(B+BgG&%uToz!F(By zU_d9Cs*;sfL2{SuVk1o2&T&)tyB)gaXgTY~AHXPg-K~0X-eX!zmKpSHCGdygk&FPv z(qRj2)=;fzEi?m!GNpmKVok;({;mP+DiL+9bR0k?6>Rl1$q@$INWycF|5tZTbO9o(9jpx%h#ftm(8d#eY#_m)KHLp-pVV;IX#Fjk8& zFohix+yhm)SOxPI-1>by@gZS1(yx0~6LbBt96*sWG8Miq1lFqiUVJCaQgJvpV_umA zOp||}M*a}3xZi(J&^lK54?X~c9|h!Sp0dOa67{2ek<%0rD8C&CaL@Pl%qM8sAVdRT zRuK23XZX2lGuMOwYZJps=1+2OjADqvuuKFT9+I?41zojHV0c-6oXfKW1bGR%`<@Psmro0u>!0q%bX+DS0XMQ8}Ie6!o@Vy zpxQryW6F^TOAs#Fh}WSpFWCU!d(RdB;(A{8n>KqB7rR~fi7e*-0@8X@0TH3nZ-gZO z6s9GUG(78=78rQ{7BKeXtNa*<`q!C&h;RnL^-rw3{|TD)|9X*QZ{~JC_HSPV%)JB> zdy~1BM11!{26FJ0{{i+Sqz^m5z{1HSnJ_#%NX?i*O4g9?0Ken7Z%fafipP=WWrnQ< zwd)bAH2uSR{IHy!1m8)%`Cq-YfrP@YHi%*S zQGKVGfoTSwCr-81B6=oFPGNg&)*vz+%T6L)@QrV*A)xHfa zDpe4z=O)0P%Yqp?KULE+`XaxIt$(OS*b$NqEQ=F?vf$^KiZ3FR>Fv%2OuJ#yl*r|x z#J&iOf2iu)um{FSO!nxVs)w1|3X($$1!1BM=d2Oe^Km<+jvvzTO+0x~vat%)c0?ks zq8&n=0@^a&YGDV`7eyT`)IBYk5U|-b#Y&P96|D~3#t6B>4B$YwBW6|z%o zC9Nm*0tp32E~WE=TZe2IUNRx)gfmWvLnz)(3!$$m$Q5?my@lCW&hol;j05IL<*XiV zM-HX|79b|h#%9$j`UYPyyx_Pt9Zep=EQFpc4ZAH5lRK@>37MQ_me}XHSJun&Xgi+gZ-m{gn<5m1~pGJ50?%hl~6AIEbPu&65p2l93;E#|F| z0xk3ygwnbwW=&&bBpt{@IxQy$9UbUa3(dD;v)U3T7hrPxM zSVdQs7JH7OiR`Zko-uN z?!od&yRVgQH2dZP*CF&_e;H3uk^8#khe@7^FfvmNi}LN?|BeFrO!DAZ&pwwNr)+4A zg1`6sW|Xr|o2)|HHzH5g#Eb^&hG?DQ>5CSHNS6U2g>j~IRHg}bBfW&pRLz-KYgR*A z1!q1TP-LeVQp;BAeG}u)6|5;<=;dOj4AFU)Y?}F!xaw;IxtE~z;UhPa8cG6$0ezUo z>3FP|SQ(TKBK=2yg>jatO23>+(@BW!jm1gerJ^{kw*3t^0I+~LjqGDbVf}gJ#{(D! zYEa}=W1Jf!oXhDfdWLCIxB}74Zb2xX@oR#sbV@37~>2CPoj~$Y!{_t33Mt z4GE&sO8Hcr-Xvk;!;$L~N0rHW)Ckr398+*gk3y`2bQEdTpkkmo-61KYR^uD8mVi-7~u4bH8hg{VnUTNI6aN=d?$pGxOp=FI;$$f97sIn1z!zj5kOi zEIFVB4BtgHtc%o21wQ7IjPAqCju0&vN`Q>@cQ>M_>%ZYga&xrnqkpT8yZD8L%#V@p zrGgHK5SOWAD4O@f@Id37M(5RZ;17ypsx4f#EyQ5B(;(cT=pot$h-%92H*NWyWBlB7E3@EX4&*=G6WM4PBNXi+^#!&O?5evK=0OEAbaAN}5 zXE)V!?rAu);_lPy&6~7$viS!lao5*3Dk3QwS|WtZAWEAG0E- zq?2CkiyD}t6_-=ILe=bT?%JR-q6vJC%d4JF%Ij^4FXMsN@W8ci{FewbkTTG!c^Wz$ zYdxG*$N)6?#wQ#KBCf8?=w^-b6ud9QIL1(53Plez38lFb^)ypDOT@vvf|n^RQH7T^ z0@xArnOLt=axX2hO3bRt?@Ys9LwyV{9%Vd~^IRF1lBHdGGBBPMa}!~Y?^k$w0BZqY zI_&xk3VaI@9|`<}E7g1u=p@FK0zTO&HHXni=}j|hC~_FRSxLJ7$@P(NgZwTKV^mE` z5Nw{H(2iacSZEDpONr3HH43VSx+m9fP0dFx0-u#ytSX*M>7;B&%t4eMijSx?^b4ET z37dd{!}UAOs1kQdTJ8-HSyBG%GjEB7ui$94(Sb{ZNFHGxKu0na+m<_htUDgoe~2u( z=^zz3O!c1JG=mA}N|}ZRnktIV<}EXViLUQ_l0I1PMHn*O za&r-{1`VlmN9q{kNP&gYv0)c5oLk(8k#P?(9gei`f<6w3iJS`5YFfp_1$0!A5{W`> z71mUt&&F&Np0d5$rCJ0HR@ z4L61pQ6v=wiv!kEgzrl|!f-wk@eAMFh^By1ZgM0WWx-Jv9OuitW_{Z-%a>wd{gB85 zg&ToUm@=wvTQzfH^duQvCDToE^ueA2oa~Wt)STZ+3TmNkk!{T#_yF10zUA-~?7a$B zUT-g*p(lH3twgIVIA#s?1Z7I%!Vmc46>$NN45l{&>jd7 z1^AeM)j}SSt39JA;Qn1XTA9vO%;D+nq{BF|cqlkc+eaH;`dzw2zS(%{k1MAU7T5qI zMR^Q4aTX2$U;~NlKz;1<9pw-C^)dDkd;jUaChhnY_M_|8QuomYxL5DI*E-QW$8l_z z%KHE&rS`2s8ctup=wG0B{orTV!zOZ@7CLa;#y4k?xl?-%*Yp4&|^WDaXz1ei@``aL4 zXw>(A&Pq5|E^6TZd~ZE1<7bbJRUEUDWBOLBUk61_M+h${XUJ8yA!OPDx+PE$DWJG_edKK(M*eP|;Co_t^1jLDsC=i-Qm=wS4N1zZsaFyIy zVAdI201Xn6^lTTWXvzA4H?*(a3Ds6b(1 z-FPhIpo52V5!yPj`&$qEqSBWFqAa{sK8O-d?iXWI{hAyG-|m*!hw`$zyXn=H3v;7r z)1Ll258SY}{Gw{1OUQ4s&;nJ^`x^@dV3@MP+NJ70 z)I40bb+7W@4l*?VS78j-fjjm004^C&6CRvMN(TZzY#OuPqCix!P%QV=|GJ4ioT)VM z1L(w{?jTc4!t0ZfUn1@V?5`Z# z&O;R?QpzRnnY*#VVylLmB+oFvyvxMeh_Mzf0o}afD6)r5%7ml)PcDyV}vBn2wXr_(Man9WWC`O<&*I{ zQEHZxJ_po?0AA)jSRfLTtzL-}s2aYTdw)WEsP~KjgIH;kBknfV-h=`{AG!iCVpVys zi9gFgIN8p}-`(dWsDQF?09jl@^S0>c>Cv*{KO&U=zh+G71eG$Ou&tpyZ}8d%brb$v zd1u* zd*?aK2(}E@B{XaFH`)a-wgQLX(VzQYmPPz$Y_ETbk0mj(>v_EYzk_Ulmq;NNufCbX z%hq0KEB@XqKuUkCt@x9{zxTyA-+=o5*BETy zUx({{iotgNE6&rFkWoKe{pqO))U#-sLI3%|jc`)@v84c^+=*7umH zwO3#hQ64d@{wa&is0AJ3NJNGLIZPgsR<(HK^&#$ZLx% z*7s!>IHs(V)Hz4>-G9_+jbaN7aibE;o)m$P@6t6Vp0hX~n)CyFi*3ZQEyNxY$0t&V zR7wMfLZ#0+89bJM;?!H10BRSmf(eq>MY|Q~WZZZB051dsFHz>FtlVfE>KIW}CLw(e z&N5M(aQPid1r?s!8S7Jf^rGrV)3G+Fg-d)-6T<=LJj{{G8W=c8l#IVIl?74NTrhhT z1V3?*QmXOSKL7Rw!b*$oTDn&N%0TR$I^zSkPz2fu6Bi;MFs}Hwci~+gRc5ebY>Uw# z%M-v6>L*2)``PFSRA60odsY!2mN`x#F~u|-?=7YW!Y%0GnmtIEVAgqLNjZ-UI4aN% ziQyVXdXeZg&BqB}7oYrlLV1U?9s!_=`K{`s=U3P61^elvY@~{u_EV8D7 z!6Bt{b@ghDooa6+O#sVCzh)Mp;jg;mM@%*@c_Elw-8Lyj&Kl(+-D3%d7`-CHQ|9N( z%a(#Uk0ZD68k5TjRj8tbz$e3#+=*6t9AlM@Ik$4(81D0P2J);Uc;*O#YtFjP97e%kE=~F& zrov;s!}O^xD>P60SOOA||MB^oY?ii`{owUd6?X}#-FcwQJ|HPK+l25;VK^j%x z`9J+0Hxpcwbh0i&@xwlW-JQ1beKyd|yL$b_x+a3k z6~CZXe{}mDBs2&;$@~58nFz zW*odRs{-joa68y79H0%^XG>!i`i5T0*=X1j0JgUVo7|B_fFUfVpee|5J_~IVj7LWs zXL2}>qDXK*jOHLt@i`XkjC4os1z?+mRXY zt*%@k=J-6%sB=3;AURNt!M1gsMc;Cv7^-B9Ky{-}o3%+ZN(wY<<0e6L%x_=e%TMJi4-GzxD^C36GH+7-893ph#J9!!{`jBF?Lbh>PEQ>M46#Z_m9 zca!r5Rb0@VuyIIF)XOS@Yg=NCwrFJ>Nc|}YTwBtxtjI$`WVFB*j>%xfcM`Z$G2I}u zlp)x4q_t(2%)pz-cwS>;WT2atBF~&;*bvPkZiJJxmgXmcH}`8kA<9Q0gKL>hMCrNl z?0;YqF^N(%E5p$YVY+R}pck|K7Coa{wMokgH@Ogs1SpZ8Gx)n~jy;s4$?QpDPF1kF z1bmQyPxp%3IT?jK))`Qj+=M{e4^^W~HSz-fc7>!jjms;G%u2j(61afUx0tN5jt+A5 zO0Yma#QIZHlJvUo{o75;ggs`@F(q@FTrq$pZIbT-SyPqL1x3%zR%2tj+i)c92kF7R zW@s={pqi1PqRa-m({d7~C=V%ispDlnWZEe{K<8cX=RBPgK8^vp(H}H%CIyEym2pR7 z=I9-7b8|^J8txrZ%k#XBn2~HZ$<&h(Tv84iC%ClaO{K!w4Gm+NI2@4#}A7-Hid76`$x(TEWf5{)~{Q3xZbT&3yBktgcE9yAk1a++w zM=1Ug+CPz<7Lh=O&jTNF~$)MOm;oKsP&u0iEneK>LgUS0`LVncP`T z&^=6QG9(&wQbRPk*XTCuu+kZAZN;wXi-5K?*|{e291D)^W7-1EJ@Rx#ggWX%l=OTs zKH=Jb{|m^2&Q)61X}R^3AL?EMp>*XmQG<}5p@JKgJYRW!u%OfwK|_<-W{F#QPveW zx)QK}EmNll2D{AReB+1idIz%%yUSPRiU}bZBL5YN>iK|TLF=OtoU6(1(1dXe+q1+q zFoyyE#QYs8G*ofW4RygC0n#F`hI%M1eOaIt)&6*rM9l1zzUK8{*F*y4L2W=MW(PBg z-O0BwdF{8}e&i&f_uLAMeeIi9+xX?^QZ(-)0nfydr{^bHPqlyAY&+~u$b%Q6OZKYU z_Olbm{S(&Vsg;lH7`c<5uvP|UBK|G%%&KiXjjVve|5p3BIkQT(9CrP$5b|C7cL1-f zwAZTGUN2gi^S#GQ#l=c{1`da9?1Y%BJjzx+ctTv|ALFaN+v2ZZlo#BI>nHHy=lFIz z|5Y*ZgS~P6fSepUBuYd1*8}tV^yB=i)@Y$Tw)7emFArXD*RtXvp?AV*+JBMh?YGNj zzkRvTdfPnE_g5LZSAMkTk;;AK8~(5T^)i{RmW=XMEB=ySu{YPJGf`pV7R2>r-ZfQU zX{WE*m!i@WnG5#r_NNcD)(%hf0)A}~#$VLt+Y2xIFq2Q4A3x;xPEC{6MOMoZt@l$z z(vOe5G*YpTF?n#}XlANb$({`!f|OXX$+z6S)tL`^*d*$c& zy@TIc8mD)iI;*EYa)1P(f=sl=0Ef}m@yAe-Zk^KM*h>eJ;vqHb0Y~y@LvDUy9=pcKLPIf z{O0;P@L9iXqslFBJ{^sY`**TqEz1LUB0+a#-I=G;{!1gj;@XX7t686$*aOcyK7Aga zDuP&c9G|23Qs5$A%}ld!qLu@)vW+IlDH1w}NBH1P+r`r-{ILKCPRmyN^X2=5c3*U% zI4So0rM2bz6u2GIlW&EB;3K?JxP1OXfnA4U*ml1EYIJ|_2uHpUMFGm{;K~fyl>fBQ zEKE=Mj|?J{@>Tyr;oPCao9`Ijb@yVf{zQMX4Ak>=(SKJ9^cD^Jp^@zUPv0r_R8DV} z?;;%&0HgjQv()m<1~N}Phs?SEVSe!WUET%bRxg-#Mj6?49vcDiuJttkkdeKAddEbz z@34Opi6UtS6c*wJ|v1^fX}@ZoKI>j<7F5scg2 z{H8cl`Wrj@=vuRSQbyOEsSx+>09|Jt_gM-mV z|DCxVuG93hBMqd8F=Ty_?(u_{`~=v0-A7=wZQo@*?l0!jhX{U0<`77=q_!GJFx^<_ z2dA%%stCi}m3-Jpa&p`?e{NzEY6M)FB5N}8`mC5hl;{<9uKHygVM$}aC2jeNj+EWm zN3S;vuQd(@PqJ?N`%5C~oGS-g?U|9u4uMSEub0I#u-T6Otv2!*vPDDm>!HxI#?pc8 zO>65!QQMjcI?6NPQHo~yuCKjSA!hV`>n=-j@Z9!1OO^f48CF~KVfobS2*5PY2S~`$ zq8y|z*{H3xwCjw2>CK)@uvz7<&710{1vsQnB{koWB=;~=cM7uxeEW=jRU&5#Rq1qe z6_Ysi&eD(DW0MQUaohi;bG(0SXrYwZv#*0*S-kK!U9yv1LaCdit_BM=A{m z*Br5@2K$4nX6%nWjeIh|PTOL13NokA1+m#Y5d)?Lj67xl6$iLkSHbVb0W-T|w?gV0 z8C-HI%}kNRpHSpWqIhHkP#?rbnJuG*Qs;$(;5|wnAWz3Wu+XekJ9?O2k1GNUIyuhv zPeyVdVu*c(?G^rlv9R6??Gn9!OU~T1%;2@()rNO<@8M7Q{gLTD-i@K5?AM?Ah_ye1 z5}Qjv2fyMMT7D?c`Av+z;Io+MjHwefp4#Up1L{NmH1gW)*XzgvuAL!EB)ZGGZZ%t` zugdG0g84dRkqsM0Rl|W#V?Yz|gEjaccvnb4;eOE(B4-pHfO^-jHY(fuw>gj@D2mt zomP4eX)3Rs z#^5rLTf?4_MsJzeW}1(=R`2fM8=^f@iIUg6)o<|e2pW>F$&np&#y`^J|Mh$04Vc|| zzoltL&Sbm{tQRiGs*LVo{IWeyyvt)R`xL+S_}F~jiR~jW?AlsGSc&EqP7~YxvmbA&c7?s^~vD4!Z- zTiq-|m2#d|Yv4-{5J!!6oSOE}2Q^ukC$%}GKcUKaYQJ9l%TM+Q8I)5#ce#>lLVT*im3%x( zS^8Aa$y%w@a+cm@2EqUSdw^xTMA@zK_nAk@jzLz_qAPKCK-)ARI<7m_MY$EmG~%$C zIKtV%R0_RAQ3caQrFW*(J+Lu>nE|&&P`Vpx=3NY8oFPr;akhlXtjk`D#^qMGklM-D z5I?{XaM7oF`nNZwV_|%^ zi+lowX93JP)p%S^1sV4xKsGw!*sH>sfCbGa9aWZLK0cAVj`09Mm$W+WA} z@}WW`#*Zjqw~qI@;hgQgowsl3GaASS(U})QxSB_GCx6b;aR7ac-BGmI;m>bSqGs1% zCKb^<6hjhpCuNgkP+%U5qqKbol_shY)zl2p@<0L7jWsZvsxs7OZIi=SKK858Z-fg=X3T#?t{L_G1%*>WRH}?S{ zSYR1<5kq7qik@;ouyn~v;GDCo(RPYJGM0|#N@v6bk(e&N=-#v^pDhhFXP{$Ye>T#O zkAjX<@k!@(prIpi=4D&!?4R%P zEmkG1Z5RtRn;v+fuRSgemca$tX9fA+pIWd?dnP&w@tbi{>ZGc(QrTJ^n25j?_ucv6 zA^+smL;ALf%qSfqqg+h;RPC7mh(Ry7{0WyL)`{Sr14bHzT++CQ9rHmT!z>2O89Pw?E=$R?l2eym+o`SCl+3bmLKO#y zD9{WQoKxh(Ch5tEVGIHvspX@tKk>uKIH)le>xt|!cfa=EbpUF$k~_es`l1L*y1}Uc zuUvudq{P5r34j$T(=nvF^hkmH^o$1Ilk^ZP-tb*5jDMAz!9f|B$01OummAoac&FfT zry)@pG>^n-%$bOjc6SOjALw2TPj_&QhsTfyq_`8bNSY)U^$mZOkdTkOE-18M&0n`JRD3}N#wh*rc z6-NiCPB~t8fOJy$I~CuxZ~X4*E(=qwDVIzaKvzJ4k*lto2jPwaZ894hY(ROaF$d68 z1H`YS6YgZGVw$0bzFF{H2DozxJNEH>kk{HDQGJs{KG7(v-}tkRP$PZ;K;9Dw$0Hi5gh#ZTbS^vzK%*N=JV3SJ zams3C6&}`xZd3R#IJn9{Oi|fHOF^Mz2S(Hnu^U=)rO6q9&u}gPz=r#hWf3V!;Gi^c zWGSL0h%{w6y7V1v-%YoRrdL@`C0$4=(?QHGGh>^OhtLQ_wx=RDNs~hn!jP&FL~20R z*KC`_4@4Ct_#~XgA>4lG6Yj{U3MYX##irovsOz9m5`dMi>hU|ufIS^Q*3njise~4F z5*53tvu6Lp-@R2hoWDIv!_#(y662KX!7QfLV_=jZ-cyMN5%`>7^E5n( z^%o32(V&ZrD7}Oy!o2M|!r%YD{nmUY=|$P$z0f3f$i3ZQ!23_VPo4GbSrT)3D~RD5|_PbwBj z>cH9(%LC_q5b@gf4(^fw!M|uAq+lg<`pYF5s~vn0G*zrc;2ztn0hVY82=|}DwVYAP zkFqc#oNCOYx~aT3ew%`sDNJsKp|t9nN-tcnXrUxN0UXvWB1=0L%0H1oIZ|SS>ae@O9W&J#`7S?& zux!Oyqlm@_hRl``qrS?+$8j*Vmy>vW47xEEC^M>ZBlF8|G_rr+2WKTxZ;?z`-g{aOEEq%%^Hq9sYUyGj47umK#9G8+*LO6F6 z3F}{VKS$i@Bk?Ld*7M?@v(@Z@Cr{GthdWoZ(~~S%u-I6>DmyK^C_h%&-x+KZpPAen zksMJwjZyxHdCdBZ|KM410Xf?9ajQvpWuJ}MeDEDm2%GJ|LHz}CH2y7(+ZK;w~-93v2 zg#AopCI2#_i}wWwpD$&B*yf9Ig4>o}qsVq%zf7OsER&CAF24XG?IC;p2^aZ1=fHRq z%-Gz{D{}e*WlbY`l(I{W%Fr7aFo3*A%6;!0DBjiSI zilcG8(R@Fk&S}8L$GYpOPyCH-B4WG)$wZ2Um*y`tK+VPP&LRSzA&3ar?Ld-MrJB8; zY%A<+eXhINA@-L)5j4)4e`ROC&`e;cXR^=z34alM(L+I2yV5*If!%IJL~jzPjhOeQ z@zmwXByfIsvIAwo8ufj0lk*P?C|H`n!(QBVBKf;W6VMfr)Y+&hUi~UKu7ICkT^XUd zYTS?HI>rtJpdzpH4%)G6xPc5kji`NzHc`P{$8Dr#eu$7OwF?dP;F=q8d#k%3%;R=6 zn6%;*6H<$V0M?@kxv&e|PE75%_*S#Mc>qD{05dxg$!*k6ANa&ZFmnz2glrzLvm+?{ zAsZx55-szC>y=t(>LS+O1pY44ss4GaoLJ@`O~fn{eZ@UVMjMLw_2$fc z%YKY3?n171T00crTS>z0^&h)B)eh>0%>&uKYwTQQqg?nfJiK5W`)BEqn|5{^+|c+6 z$gT;J{p(1U@JQx7Ml>6Z`?U06vvuUsRGV(`)yO|W8o zbwa%oSKNhCJxQo>niN$CHq`gOuz(Ioh{)NTIvy+DSR)vGxE3uSgLrE2!_hJ^v&bB< zAvoAfS{>BY1;ZTFy(IzZ%xkPUnojNU?bMze(pc#yqLZ3L zH-zBB>=6McIcEJwge}<4)jxyNK>?FbxZhv%hT6g!DqqKucpLKvdTQXtcIduU!18oGPn0$A+K^t|u$KF|00 zK0n^K_ZXZfz}RJ!lsZ4x zN(U-JTh$}4)JDAflBg>8Bj}{WFEva0h)dJ8^e!#K?gQ5OS)=lX+q@j|vV#gm>%8+1 z|Menm>57f|IN(!?J5e>N26XY0a`*rxlJpZPF5lfZy*NDxE-=!Q`^emrzwL~ErFe-W zKZCaYR`5TxD%AofTcA^Lx%)1YmAcZTj9*Qk4?XpQPu+pLj?S}?{vwTq*loCF%(R9;DHOuoVEgRqaU5o#i5(P(L zvKT|NxL0`^GaRmf>>y7MII7^5xp9s{VNy`<0Vgex0B&4a znkP*gA}ITXcE?OVvCZXt&QYM=AMpx0Hn$wM8cR-Acc}Xhrd50&8C=CB+O4N%r}M0A zmS<(psHb&y_VbND%5#|aZ{_!%d8(MV*5X+?W%4%p3dx4j4EqzdAybZzdG%a6shcg430ZrzN}JExQQp&pa2bkkyS zmOSzW!t@h^>ba^)(%39ML@?VV!&Tr$Yvuc!gjVTNb945q9&LK3(}?!7x^rJz;XWEa0%&p=tK8^?=3M9@)W}>EgMj=~uSt4=d5-`^mrcp{iu@Y*pMGI}-hu zEp}0FE|tINa>LT;`#xkm6rS_H=(4$Y+Bi3KqQX6e<4Mtt?ouR>izGnGYlRa*tjf=y z^wWKf(y1t(rR}$=ZlBL;LW~Q4&-J0<7n;PcY#TNl`OGF8hY1avQCcADWY{TlNNG0XUt-YU zG

k;^*0>M^hoKRb}JC?RWPvwJEaZX?0MYDO4ZKO3i<4o>tK#ZRm(m-B&iH1~%s!wBBr>O55 z(G%Ama=e(7OWaJ0_Fl^-Gs7CXSLc8I=kJ;^ZyEPliw`y#$m!UqyvRycpHw7|tBX_+ zFBSb>Op4p_H)pNGg{9@`HIsYl6|II^s}2uFYE)g>;~Lw>b~;1d(582bV=2|ppSi&e znGYI^s>y?ZGsY_q(g(;PprQpl_XsQ zFxfgD0bPZFbC@n#!JUi#lo`iASR$M3^DBAnQnB2oPFR}O zmyQa&c@gCgBAG^0u}vCe22%G;>(4O`Tfg{>Dc6&?>*4F4fAp_3|1WFs6CX`I#NDTU z`ZI_~MmKqvh?WnSv3S`}c*LR~qB=SQc;^NDPRWehTsyFKUOUInc7ZO_pJO6r$LHk@ z`2gO|`(wH~6|bZi6D8&n<7BK&&VVtES!G*MQ!$>0QrnW>F9r_6q7 zVhp?Z2lq=SEBgxQj!_@4CWS>6z=3(mrF446Bp(`(I?JCl+0)7fH`7>}KEjQ$EuJ)j z-6sh#t2{epxbm#g7DRmSoi;1cU=B;u$5y66AKq!d`oGK4vSL~oGbZzC0`dG#YbR6X zRoGe6k1XE0$c*F{@^E=2zm1U;|H~!H54$hf`QuN_oZ2*q2`h!zkQ*B8p`1nV$K02G zm@<2Lnpsy0Mk-HFMYHX2L~zKwIoyg%@)|M~hVjBrz39nF>_ow$y}M7Z^BQ@#^pJR_ z5y%F<0PTDz{f(5d#`65pU*d#iro+n0p`ZxQIIfUDJ`H3VarmL|z;HlOv*-%Z4V$vs&{$t#-1X(bN*3WL|mh#fBuxt1X_lVhqxK*kjgc=*v@ z3r^~VC^462{_3NXi=@rR*8}boin*)|`JgMaKO-~NdzZPUmL}2p3|fjjXa>yqz;Ad+ zi)X(pvXqOLD@}%&zmxm(GMp>9pi`05``;-WS9jkjE4A}aS0_4OMMII@t^j6=0&RDM zi$gYogy{*=BHT3oIL=SDVe^~!iBVq!yV0*+EOF3+v9te=^!wib7xQ`VA=M0iJm-TaRoL?P#B3Y z3FR7w-)8IrEb`f`rLs*|3IqJM85plW{jiBXEtV`vTvx>?@&`Xo9vBdB75VdELKlgL~Uq4&D9X2@(;AU`Rqjh^b@WcRXJ% z$LD9$xO8vT{i)f7q&oYmdTD7gD(B(!KkqrmRtWK|_lEU*KmH+?=wqv24pZgJM?CkN zA6SG@adt`I&!-5q8H26_CAPV@YVuUbQ&vkqwN!ZDQ--hKW%;O3{Cw&C@8T)_uC;@5 z!NU;YqLc`gjaAFLcCP={Vpw{h^(M#HJRm3Mr7QCnR;J^xZ_;M3w*b62*C@}{ZR}->frVR?|l9b$fs2b)a%rIabZ}LWR>eB>Y5Ymcb2VX z)HqGo?}nbOPs^zZVG^0H+ewp*J5ptiqP{l@P*ts7B=Vz7DQ_Hf#@$X9c2>E_$|z{I zj|9U?Eb zoNq|kCsvu-?;Ldw`G@?bTyF8?*MoSQfsrj-GtVh@ppRRfWK{2S8y?RL{f=elV~cpJ z>&ajJkuzBBY<#EngTOiFzZNil(%S9L+2CZb7z7rV^|E4R*r>#r?{^sM*zq>_!?eYlx4_@SIr@;yL;exPD31rh;;HufsrL2KV=FVI_NmPa zZ*1O7im>sK@B4kTpOKX%#2f{f`$UY2p(4IfK+|Vu-1=;AtaaIWr^|nXhxzK<3Y?R{ zvfd9~jfZpG`e|WHzP*=Qo$+cv|IWg`TtI(M*5{YMMzB2#lSL4-9vNY#$w}DczF6#c z9A~*C59|8LV7+wr^&mL4$<4;+-I#KFlKH*R8;AY+SgAHZ*2$MjjyvEnyzy ze9Boq7%cJa9AweaBCA=B;-M;+y{%$-VQb$B->d7FD;b}|BOl<;st=Y?k3!jPxQzu8 zse8*nr)_$-9oD>Q1dAtwVENScHV5m-qR-Rbpo~GcKMH+s)aqxUB0rg53j#Y?aAl7b z2fcp9x#_DScj0gXIenAwX7dP2HmDAY3#{J!!Uu{SCvyheA_+hqz*O~e{7lo9Ar0su zT__AFO2>M_1CSe(PuE$}_24n~9>!_B{zZ4qG!RACC#OD8_EZ}cnhYqSFl^e6X@@@X z;ZpEYu=G;UZW_y0AiZ%cdC@Hoij_T&Ui5v}tDD%F)h1~iJ| zQRX67Yo^CjBfi><<1|h86Ye0%VCt3%-OmQ$l6fcy4q@B=a!}$j zhi6k-1m*G`DA4W?yY?vXvcPYLWS%A_6WxCFAK3+}y7pSNnylfCYl(^81V*#T0^x!0 z!9gONb43pKbXgN`-1Vk>Dm;;sT7G^RBto4s^O<6QBOQe+=}rGN=gr_vR_bWbZntp2 zq6?x8K;=TAl8%2jdn0?hXR&M%G6{88@u}6}_K{n6% z^XzX`S&NZ48>7H&D+G+NbK%&?EfU#udtskD5(cew%oY_#@bmDkpeu$hc5Jxl^7M9Yk%8tnQNj%>Iwpa5V%gTN1@Urj zOw01{hSD!b?sQU`$8JWDOuW;D~Q+t)#pMR_Zrnkj{IbZp1T zR{04yLDTZfG6&OB2_{T;Xx$H6xBRcL7<~4z;2;C>WlD&X2cIrO0vjFFi>}iA3a`In zlH_GQDzV~-V5R7%tyBS*=NKY*HB^nt4+OSXCiD>Br)=+H4FidoJw91pt z-w#@R*5TKJ*MeINBv=kGW4WH|&fD>*I&e@6!{&4VJ0Hf*A6z4ELrFjl*uS4tIUtBx zLxGnA3sAk<#9WvPrlNtjFY7;cdLe#Z^eatw-3Kel(KrfwO0w>ypy2={cB#bXK0}U9 zf$nh$x5vl3J@m4NVA6aD?w3FL;Yc(SyRBw>?LC!Y%|;MPf${g0h5s})FW@(>D@EV7Bi^POe}e5Cg=o(U6BsvewF{x^5?BM*z67Y-#-_P8f1ibrZ!_Y(?P;eXy0j z8NEK}mR&H6cNacJq$I423i?`hfO{Kl%|Wg_bIF9;r;95q(>fx?U^Ar#-9gxMdw2}S zA@-(&2*$!lY||ZZ0_e&jIE-*_#gdzB@x*(ZRLy@aJ20l3DwbHh1)oAtlMHxI#^mF?}u%2 zVFWS7WDL2PFk*pQ z_fLL<)j2;4t`Fzf_0qsSV#uO{UK09sOYBF7#m2eIZX$DHC{rCAEzts^4zR_1P9VyH zp0eLD`&oU(@A`*d3LqyP5WZA`r88*O&?EwjM~7VG(E*Zh6k4i=`|Cgb;Yt-lgT|y$ zbuHltMm#Wwi{#H^LFwWRFdpWrk_;8y*x2Boq%K&p%LX)7l)WS!`)((zt7iRHYa0cD zvo(E!Y`i(5OOmxM7@?D$>~p0MT*83Fi%&2qy8YO{m7)?fy&A2>dn$WG(yp;&Hu1e; zI5ccyMRvki(1x)NMpQo?iw0X*Y_2K-exglks&7W)a48E9F$kLHI3@};LH-b7FPUqC!CI{j3$$MPqjL6`uRK-`s=G zK_D>i`E$c+xsuIA!z!_35uKl`A<*;?RGJBAErKN9SCD%TpRr3D?F0oHP$IK8QcRqv zBlK6ClGVm+gg0WtuCbtM!z#NVM%Z66uKNSLCm5N}#C`qhT_C>X4lg9bnrbZ6)?y`M zj!gWGP$L~B1jy%#o7Sf>A1tg45Y*e`AECWp&sis8t0ggqvh-l4Q($UFEMR&Jk-KPKC&pEc7LC9trFM zExn978u^Cn_gvpY2~u>14}dMYKl==<8w+9>RUrl3)4dXJRY_&OiJ*n&m4cNOV7n=> zi?1;Sm{dn?BzTc}7BaC;3b)qcnHR0XViPCXfX#&7n`qum|DAwwFI!NAl6ACnr6lD9 zJ$iXFYc}e3U_3fL+?Dg&|Ie#j5fh@rTq*cdVg`~80ACo3xYz)Y!C%u6OY^%LK--9< z6;=#y0k8CUWWX{Y*ItA0vvkCl`yItw9lhkjWSN_m1*eD!^2P1v~B&QGpV9 zl&tNsfkk)+nGVy)^_L}0FR%pKq?HkN>Is@W5`+V~^$1)HZH<>`CHCr>f(xhs(B{1$ z%W?T|?)@Ic@m(&c7){2_FaO{dHHjtV4y2S_+IDcOKwA@?m5-Mk5 zH*(o?1>3Zf#Bu64o4(ank>fbvvzFhNe;>n@V3=c&2XhOBhGeh|R!~5mNnrk5K&PYH zlJcoDj`|c<;)~JcOCTl-DN!40>~z$%?!(RzwT$OYt(9&d2q239p<{g+FsXqqJj-|c zLVksq=&S5}<(hO#M8v12F<(h)Cc{9pmV8klO||58K%x*h!Ycj@>YxbdPJ}cWiBNeH zo?_C=l+}-@r53i)4i2X%B9 zu?#oCSv-kgnUNNYcpX^>&l>psvC}6S?0Jl3*L_J8tI@38>)9Jq$9(gU|Lx#xP|~9@ zmJgN=HR9Ap0sxEKLTQIU z1UAA{luxkWp?-o>slbdJ31__i%Xb@bRKWO9(gQG_t*RJ?cg;EK95%(a@LuRKD`&Wu z+{-Rk8~A<)4(*NW@C4NdEaa$fSvB-uajl+&Y-lD~g(H}G2mD=;#7UFjLwlwuQ|(7b z_dQ)tN#$CE5O*wsi#-1OY^5dmDAs$4w?|bZ5h%_~q(OomKLB(gsub2z|E@q6Pl_+y z$W{kr#f6@NffMY3=7Mh+Y2fzyQ=jdIo<&L}Sa~gAR3HXfI0zlhm>&6CQA5Js)ppoV z#6&w{UwUT7rP;f2lpvv+U#KN(Yp@tT)-#(+s>sY@nSPF@D3RGu!QB4X?=D9h=(@c^zwsKYoksj`bwXJ9e!05L1{iR5${8iB&vo$`vNSjyZjD-^bW~ zA@>%mZZ(RH^87-!cRrVpt7b|kQ&}z^3=kb5FzOKh_NV$A^+X8+=gJc&5g{GZOW;~v zKy$Tzwwr#Zg=x{?dL+~Ln=(WT9#fPCr z;PaYfluxKm9W#^N8(`8z9rc`ce(lf5i$Q`ZY9vXVkP8}+vSbk&IA;b^qL6YjxL&&F zp1ZMd@wGiKosu$1;+Rs0%Jos|eaO!30SqiMi`QTthruHU>EPHU7fTP{uxf~P@G|@x zD>hmsdBY`S=ED1oKl$nhD3RdFKt>5wa5bj*F~5s5#5q5ff<^T4Gdrx?1RS|1o{t|4 zA?W1UB);ZRW-J0VNfu)M-kC1N78c20J{b5m6?F*p|{UUYRSSxN0Yc{t}P^Nmw(IC_Wjbtc{GLGFiwlVD#PZko0;XR-}SgamU z1TOGdDj7F>?cPAu-|12eYXnc?>4PIdOZdIG5F8ONtSY{Kvt}CLD-hWp3Up z%r}VL3&NU26*Z1Y7Ed<*#m`HT2FpnS53$lg3m1)WSaZT6qmtDIRkz_~pD9LlS+L-k zf5x#mhPh;o!~SEQK2`WX+_rR#XrTBG?4T26flPe~f&X13XBsRG`1@-T&i*wAJxV=U=(F z5U*u(ka`z=xaPQ$Oe2ztv9VIQRKoq8S21{i3rd+O1Ok>uEHkkY61UiXEixDC7n>w< zyrkK`WYe_Xp z6cpGE{G;d-*7lI-5?F)-7|_64ru>5&_6PMr3)6trPYm|bcRp5@(<+3Usmj)zw^m!r zs?ZG+8DVBL7PTonubkYzP6p?Tgwhe&Xx}saju`@raA6^yk{YvXiDE>2K<4|(Al$*W zw&C_x0G_dI4&Wjci5g(n#KR5(k5t5ySu$(a|itqTJA{vq7VVWHaOr%aL_O34> zE-@8A#P@_U8-|ij#&YI$tDBF<}#_aQwil82V*|*$| z)k6nyukVpY$>HdPIawJ}l1ZbxKUn&uUQQUylCbsRSBz%2 zOcvcf@G#MrIQzH;R?WHs(t9xc6@R3}ESMF;(PI)kKnPylVouPsjZA@yDB&cUlaQM+ z(Lk3u>fx?;*;)15jN^)2K(_|i)Flww*g-0w5J3H&5*x4o!iNct5g{(MHl&zAh#n=v z6_-pw590IOpF;BtrLBB}LL|JEwT2_+%Y+>wGT0oPz3!f-%vB6ZZw6^#wIqKtA)Blu zX~GO&6H1DspKGrWS9!c!x*L5dqcB?>kGw!lqr%o+LL{*4L{P`0ub;Yc{jm$wM6W-# zqB|(0AjyBvE8Kz^qP{H3K!SgwvB^~>v?10Qv>@o)j(^ODcu--vg+Xz~_gl^3?2$=3 z#Da8CNGn9;<&Re`F5_99wvXJnDA1vYxbuVWKVRPW!*cnVSiaW3F#kh${v76;7}PJSQxUAli%DAezZSJ za=qCqy%q$cd@V)S;ZNouZ1*U3Vx1jHHtv!?I!|`5_x6`Q{e1btH#cQ3C#U$$ixnxOCGSL_Pg+=&4aX?1fMjap~{- zkm?p|H3#uo818-aMy?>{4N2 zeh-A6g`_H^+9qH5r+n_=k4cI%W&m-G zjm(1vtcrms#f?tSve>LNiirS8olK|Cx@=2@~Xj>H;@G@eBTbfS0`wd3X-KBGp=tFlGbf7n5TM&r{f%3Ga@p~P z0Ur!bi|VDXmO#w%d_?H)(Ps2=a02V~g?!o@m|gD3NTGb|x2WuZwN)1jh8?gzM99qc|#~IFGZcW(VwSmWm&|_Nb$sDy=ZG za_wcL#CTABy{pautjC0%8{%mJ%R7xjOa(U4CJX72P4R=Xj`JdAYk=Q3Am_{5C2=gA zUQGtWt<Sja*0LjN)&67e~2#s4*6Z0Y03*G*^C2} zdl4|CMRc3c@6-jvbG6w#P7~p&O`-^TY9g~20oHhz(9pbcm-7e|zy+}fFU`VsXdJ<| zR!C*|OHhku^RTFVf$C{x4>|U%*h$Hakw2(I28iG!X4l&AFMft#sldTBG{=!YEG$U3 zMPkC0P$kWJq*ZhR2tcXd?sYbZw3Vfs6(%Z0sF^{+JVoBeAq!r2>lVmyR5N9GT!7;S z5EQ=O@HSHNPe9JIgC&@7y**7V z*rt#0nS_HQ7_J9RrdY) z{>3>LeG7eGp+$hgL`FML{fx$YaFf^04FEQRo0^CpG@oJdwYxiYAvKn#<5bM=SqzZi zX9P458Gw*|yc@jB5lqs8$Fxk*D4G@#3dGGKiRh#NAL&SNQOwU+h)FRG=R~2THjIdc zW1!_Z4&VNt{%kO7>&6$4S1QtDl9e{xV1*pL^je1yS*feYt|3ZHT z-4PKJ+|?&U1W!+<2H}7T=&v}IS{9bNDDjqL#sm-ISS7KXWjCDbjOM6ezWXVHtQU zc|iG5DbX1Ddo{fl9Pxvewd7bnp;tf{pYwu>G-Y8__hko(OFOi+N@S^5a3bn2-Ty(6 zsEjH}U{c(svsy(jsKZH|!MHF!xWU!qZ8C3=*7f!cjE@!KDt!wWQgD_4(eFAhiNttX zg*|Ud(VbJ;cG~3b2s-k_0?tPSMhg(uw>EsLPoE*cK5%*@D0Y?8_*`w8j+_V;FE5B> z8(y5iSzNb{e5lljwqHP2;%$)HGf5g_K{f`II#ci^K|4{X+;x$}z)%e|);oO0)4fC+YKFC#icF>!-hUeWEFS0xk@u00Rq#A~wTa2Qju zSjx8qs+K{h<862g%q3nE1RMAqHmD*C&B6kA=eX;hr+CuvicUt|QXDfM2QH8;!;Nmy z=*+DgD;ERu^3csOY@j}7UUy<>_mltX1N1*i$0kV~MNRc0a7KLi=-OGSvU^hD}T8{7qeqb<%GofJ0=jZPBO6!A>l z`tASrr=cUzUv@wOuoBcuo)&gsY)fl%OzK{H6wZBl1)FMXHw^r2D9}-VY3;U|2NLc1 zQfrVzl5H*>q}31rAa2W{N%9X+*=L47&uo+5Q=|V&Bxdvl0 zj+PKU^EHVJM77s1lETY;)i?W=ubFeMJU2f-B@qirdk~I18BBB!;KJ2cd~uVS)@`nr zra23Ycts)uw$lQYEs7+gmZV^Wk3sKptw!zOI-XM>g}B~+{g(eLPP!d{U4Z!UT&X4H z4gA3e4)llrCC;)-K2VAA?xy~C=KjJUMyU#q5|*-surN)bv4^iYhsbyG*uH*}Q1r%n znSw{&rv6p;MLyq+Qi+(jF5&~7b`6dQP&;9>qcXqOCq^J*A$v!NpsRt+!_tvBXJ>oe z%2uP2VsA;EW^9LS0YJAq!Jqv*)3iTV#SXloWKvP8p`<;7fKEN|H?RzN=km(k!PPjX zJDXjdIDQfY;)?5i6G|W3@3x&D2f*Q{5we*t~?BS<$EoMB)6Q2_E@FGPwPC9O7gg zm1utc9vU3`4?jv$AAlmktL90vkT4cz=N@HXC42*Tz+6$XtFZ_KNEQ9^u(L58rsRQ8 zu=fF8g2-faa6g`{FVZ$nH-h+uB}dkha19WK;4uNkT1$s$9Wxa7X9?D5(eK>!Bm5oC zZytVKtEy^k2p}6PbVqRtdwcr2T=T}_$xS152|vlENFI;&CYCby#ritZVTv!Vr`TiQ zT?mqQuweKp7lM;L(QCkcoNLT}`of^az8v0xh534xlf?bOGia9~z(a>b-d z@_L|DuMK$Z@2t!v^mXUX7}zR60N18U1bM6iUqr+d&;1Z9n$gpF1yH4-2WX z-3m%vUZ`brLP1Uhrvb1p=y4BCC{&h{&293MA+$^F_C7UnRLtH)+9zx)6o!8PIQSvu;Y^ ziQ8?E-U!e^Wt$*@XgJ2#Cq~2RkSVpa->2H7OD_X|&?V2}-SnL|f<{0~Q77fkSuPS4 zusf-}@mD<|pc<1(rN>0Lv=$GPfCF#p58<3*&U-u0k!b2`I-|A2wYzWpg4Gq zq}((oA`_Xr9P-(g^zu=g#f-Jd7+{KO6uE^%w)AL1q|;k*_EA?C^&U}R6G9wtDbS#z zU_)^-Y;}fRuTGj0-q}J8m>|;T@y|b{@t}eQ##sZa$f_0cMP!yT^(5Il99WY}kuITm zd7A!O^u?h3MAkk{sE(nSLOXKH6YLQWQOklaggBh~X9FVlBZ!It`IKqMlki2=L(x6B z2Uc+xK_iu1SJKE9K6OH?%R5)Uc&SW3n$SB4SD6K5H(qs!jLpME#D%~ZQkhZ~?X4&R z&Hq*in*tvR?qDIgtWX3t>cGKF&+-Vn)HSF6nq!e9DQ(N$bC;bbs2CRpH3AaP?4+PC zRa$4t^>BSGAoJpB9OUQzr9}*C0OUiEKqUoyjAz!nzIJ^uGvE_>gA6ECA6pyvzNb=0 zVYRv8lJuh20vRhp!OVB@i(#m+i*OlD@(-tYg@Bu`;?D~6h#6{vDg_Fm@Fyh#v9;Ud z;4mRMZ?AWv>Nhv%%JJHe-JP$_SMh$jBg;$Baf)>Wk&KB4&d=g3Uv=4qSK{tEN#=*h zW87kX6Thd6m}r!$eL&*<{lVcZREuv0K`O2)05)NiN)^ETQMZ!$RQpGDj23p5E0Xc+ zKb!`Upj|I;%H9PIP>j~9q71^j6~O`*5cB71+s#E{7v`t%dGw2n9k)%5owUCpnyIgc zJ&{Kh5IN(GejW=|H(Mw0FA#D&=<*NC&(FY@S5rw+=v>5UCM&28W_=}ZqmFyy&VKsucDhV4wR?hOl@CUK1horeJf`|g1X{i z*~v&Hl2nuGDfft4aguj%!vt0%ys*_=2BX;Jibjd`4OP3B=gqr-EZRWm&(I_sEEZSI zBK6T!61AKn*&rZYs1_8H62hl&3CGiBux%{gqxZVw*%?^Rrtb&iLO(2@>9T^%lMBu_ zyge?xVbzf%YV6$%zJmLgqU3VQCcxmOQjtURiDr~CC8H4f7)_r>3&qY)aZ@ZYD+t`b z@rQC_3cLAA^|>UgRXE*^>>pU}?q^uqQ?Zt)tE_-AgDr!8QAU=!<)w-i)zm^}Oj1VH z7_ir+mQ@!21vry!Ln##)tt{Zom9b zYz*Vs@`XZbOE8zsf}F~g7P&<%PdYZ5%`|0sQdwCHvE36qsKYt@P@?|{wirZe46`}Y6*-(4y< zHw)|2=gd?|4u@Te=4qeJGUklM?ZboV^?S&17_sUyDXeSDfD(DbdE=7Hu1w_D< z?K3ig3jUptEb@uQRR`5-g0W;2nJ0HZgs#^-Ran^Ljh8xOqQ7wfA7rOBFT$@QbLnoL zfBaWJ#*GrbaJJzFLdiBRH%N9cQ|h%8vXI}MiakwX-O21x%Yno8Y+E??oXTuS_C zT$O#agT3uX*AW6un=`lk*8*CS$i0Zm0ZX?_i!af6H!u6VL

&FA2{n_HzlJBK?dr z6*90@8cL@Z`@Hxnq2J zdfnyNX5F2NV)T4^s!d-K?J_9VlR#;fKF914)!D-Gfd+P01_ACc(pf9gCkSN^#XBTc zSs%{+}X0;Dh>@(PN~8Bgbuj&2rdrO{~@kZo;9 z6o_yzC0r-6InEWR80w;-vXKlsqyDmF3QmAr}g-CR_0=2?IE$AU0BjdPf#w zK}h~R#n9!*0`jXNj}O2zSA!MR=q`$Fw|%mq+ob?SEx?fAY_z%hy$HITdolVV=z?5* z5vGl@Qg0PQ0nUIi8>*F>B8))mmYl$qm~0S$V3BF-!^nJl7n2bdY@nz74*qQ=1=CN8 z{qpgUV#FcOlBJGF3U^G;K^hV7cC@gg+n@M92eZdF%l5FUo`qu#_bxzsw}=i8xY#`t&`+6yhQ!+;>=+?}Mu51>Rq7)xN1Hr|rKTsWI z(jLe{vqqAFk8c0lry`sdF`95t3NGvmCWsQ2qSr~LuC-o%gRYM1oT;IvJb)56mCHu= zr%G^xGK>_S8x)0a+1My_CsqO=HO+SI zJ7d7_k{~9(I&%7~5uriiBsyKYI|j0GLdwB0I z&5n*DTf3`#STf;-B?jhm;Cis6Bh*fC7J}NubrTxOOYB6YMAsSpEr>({)!mW&y|D;{ z6c+B0Q*m{h3oXPV6SdNCXl<5ar%oV)@1!B6PbL{TFlLsC<=s^P4-kZF!?E}{9I3Ev zrXaBw6X8EhNi#^|GG4X|p+UJ+qszBH!VL!qF1V-oLXAqPSKFgU!36TXYS0)x zn+TBr&ux^Dq^}57UqZULS#{yhCZ=6C>cK&0<;_59%EU<}I=yN2#+XG|hEGw@k+KC> zfo>4qurv~E?fj2@@STg*IGOMO4IH{#*ku2z0vxABq%xI(lJ5}iImO;=2Ev9eG+iDd zC)xDk_vk|CZ17gc-ws+Y1qKc0xJxLPfEj~@KGUiohA!nfRy74vxB~ur=j2m%Tz#Qj z;r0>dYtPetsN4nJW0NTEGOm0s#Xy8$l&9I3wg#(qfe=!a0KStZX=>T2RyXl!m^H;h z40~Z*halA<_yDYI36h@JfZl{<(HwL)N?1kqQ*giC`!m0vm=U(fwe+Q;%m4jHIa(AJ z%-x#nvNOSD=O-G-Pf8&c6qoNS6#Y?JBH@uVvZ`LFh}5{s#FO(0&>`;b))}sXtNm4f zX%&rOM8}xc!`P5i#6|xjtcc92qLc>H^rZTqF@Dwy%$&r2JHMOajzhfe_hd;z~4J0q#G_34PB85|!itc#I%!?v=Sp-^FYU~L#~Qb#)y(AihZMC?ao ze~=$6Sz1a>N#9{E^uWy#HxXV@Q}f+0bb&*@cWvuG`cL3?hf!nWA}L@ac#;OpH!gs)Iit z41`&;Lz$Q^T^LH+{ma3l_h+H7^a#d}A>=tB=6USj?9tNzglM8YP~;q)c>;i%8{PD8 z`m7Kc7fIr*>)T_>5T(3^&f~2d8)60k>zsvL6Vb`m7CaX&D?Ip)P~W}U8!!saY7`Pn&g56 zN`kACYVA7rdVml}xt#MGNNjRjAXtlDPF)}dKE%B#xzj%UWs|Mn$}lLcWtNY&8`Q(fCrmNsp#c-8?LiJKooIj)z3$2QY+kyS;N6m3yt zgJ|5M>%|AVb1RU630!~_jE-f(f-~ospVUiTq()mB*J}n4*{fx_3G#lpE`at0=$P&z zuUmrJeCatxx8M46ZbV0NTS}OFFoz+DWSV0{Go;QsnAJEuYqf_oi3e z`OLo}i(FWX=Xezz|G?#ZLz?BNsJ`gvoFomYGA4#557ZWcm}sms=(72c>|dV2$QQt7 z7nLph)Fd{=%b$VYNHMP^t^||fRI4lHXUkGCmeeI72*B!WK-O7y6igRhMC@!0IJW)4 z^RxB~+%l6c4t9Xx$MHUTS+V*^6(xxe1uawOrC2eIKt#n77B8jJ;iwIqx$j3>`gV0# zB@Q(y42WU$r&eyYlG54W9aKMe>&Ky@0kz(!KrSq}ejV?qj?L8F0Li%(yqw2D3P+UD}zB#;;ZIz~9FoN>49C0J-(gsDlP zU8USuRg`rq$#{wSliyysg?p<{HKjUoP}n+@Ju1+OecMHFFSrmbQk;H&Om>bCC$FIC z1(3a6U%ClPU7ttHYp<5~lotvE(%#aw3R2s2TEOne9bupv-+>{kgHS@7%1j;o(%4PT zNDs@)s+?((RU19!rKVbaljDV?mjFMm@dp+dU6W17bYlQ`?EhPJ4dO%%v7{bvxp?-}ChJZDmXzTETmk3Ds0?&eQmv4cMbHr93Dljk4kbA{S20Mrk_Z=mN060~zsFNTTX*HHqpP=n=1~GZ=_bNBI46Zh zV{w_n-KBxrh?{H#I(dOUY&lX6rU8P`ZQTc=h_*=np$#%%78bd(vsv;?bcRIGCUh2FmnuAIZ4fFMsm`aiuyd<>v~=kl-Ac1WQ6+HCqh{ z3`NgHsidceeI5`oo8$8syt*RM7;c;-7VNFM%?MXQzYdTxEWHzk!6ou*FWI2u0&ix7 zF8EFeA}&@Bu1Zf(Rs*pX>g&985VlZ+m4jW-n2NNoJ4ymko%$=-tOx<}Dpypj55JcO zzGCk6*FQ#Holq>6?jTH&23%rJ9FLeGD#fT4Ed~T_5hh34txpEEKB`M(#3GL5Q*dL% z2{pJ;4f}Ued2P4F2}HlrMGKZwM@NtVy!5?2m)vB;f+aojAH=otEk8%O%LhjWvq$bB zoe1bAYl@EscNtyt2t#iMfI4k!denkiG1S4!5Ose81VHEUiul*vtO|3H1ypI8g*KV) zL;fm0I_i>K)i7$4KgI%U9PXNZKCG~fT7S!U?ku1Y-7f!MHl&#^O5!y-v>VhUt4i6K z%1>4mV5bG7bkAd(SC>!H020UeAsDnb4k9+PZ&-bBf^cYJL6L|k!%ljAD5$#TEZ_1Q z&dOQfJzqS4kfBk5n15~!cZefklSEAo>Iwv`vyM~#B-z5~Mt_!%Zdk={Zq;x(a-=ho z^H^?DM?y_F&HN z)yV-L23}Hw^>U&^CKbXzHBsu zQv%D{0Kqdpi&ExRW8vkGKf3hpcB;sE)U0O5rJw`G!fQB4+gXU z?!;hrr(D+G^E(_hvX{W0u>nqQvrdnSv^kL7U|hQaBLM59^2bzOeQJPp>4(HudJ|!7 z>nTKMcpxxQY#<4*cd%v6MUj4b;U;i(nX;pdi_Z}!#y3g#NeWre>SqrZbm?$d#kbNL zmNiILO2%|4Q(Q}?cfEb;2Hp118L37=lBs;O`y9dPMP z@Fv0Ql^}0(m6fP0O_N>PJ9ujFR76;Zewt))kUqmQ+|Rx7VO@pCyUNuT$ly>_6DUtk zz?RTgbY5r#|IFOY@Fd1#bm#Mr4<&fs;147kyK)H9w1Mht%SD(2^>wa12p@Lb{mvqg zvHY6UxS6qNuTD+80`p>bOHkS4yDnD6$rr>1dBVi__CNawP0La%5b?pc8C_BGNnD>r z!edK%2t0!oeq-}yK01+}H0%)-hq`ka6^RWy+H5cygOeM+QFz~U;tVZ)6z|8 zLUypbXOjFmuTJbQKaN9ubse$c0#KPe!y#279-wqY?56a((q<|y5{VHsaxw0Hcw+N{ zsU$)8jBIIi5}GD;Fj3M4t?v*U{O1mkQCl7P5jEV@{>@~p~G zae=lQDvjRQ>z!FvzWiHefn5OUq7}_(*I(NqedF9j;7upFP zNDffQaXwa^qWpevzm05ZyBN|04H+fer8$%jN#qgw5&|$-z0n|tzR744Oe2-Cc6**k zm&zewE4n0)NNj{lm~KaahO&)+(BV2_A&hdSlsD}*rz|%I(ZS&f^zAbzR!iwnH7%cICY_!UMH52XoaIII7XGc+1v#iXgW@FlnqPm%WJs?F_XM!UToq|5Zw-_UEwFvziE z)1#1(QOj26NVHXJNlvCD2_4Z5UOKMt=g5KAg0lfs^YAVC7rAmCOQ}h<>s~qPj$Hkz zeA1m!mro$!n!Ya>efRB;Np5eJdx)&bsW9&Ryo@$qS``RwA(1(~oi0DN-PCEm6k8IR zF=!kCSysl%=~;CI%TV)Wr%}Kle<}FhVN=w&)t83*BV=xuP7*Pbi-&DBbEes1d@e3j#MSF zmOm@0rV-}OH+BzPYIBm&>O~`ML63x761oa9AlUD;zS6zzbdTW+3G6x53P-`BJx?!G zIh8mj&aYv)J%-!f9jc`NzU+O3vA$ZKlk;`m*!vwwYz+;dpMZ~%{y$=LZit3+SPZ6{ zDLzW3Ab8HmSWqe?jDfBAq!`5?${2|ehgFoRMi(yx{b?eQF)v;HY`1^YN4L*Hxqycy zog!-@P^vDon*}5|S$H}u(iHsEQSgC?fimY|XBAj( z`92LX`oMG8IVw<&n$rY^iHT)89iao12FL{DLxovXzW-mme5p)J?CcM5<>#^b%kCEK zQd?CaZ!VqN*Brc@u*5|PaDl0bVQZ^mY-4~N;|>XQMM?EHszsVlVrD@(fxB8I89gD{ zcg1}%zTz~xT#y7$GiX_IZ2=ez^|>U`!L#NBKA+$a=txij2nY>=DE*^fwY58kr_mM6 zem6F+pa5VfMk4?a0QWQZoNTYNO#}uRbH?(7lF~NY0z+2`3WL5lD^eH}6cmRJmMD|J zAcRGP5L`e!Xts1eLO|4hFNd=4U7&$-;pJ9^x>%YKi;lSfy0jak{6)(qMw4bxDB#{k zgB}Uar_o*$Ndofd8&h4+@7YlnCaJWIiMMpdb(B;*Cz1Jkf@J0*YI$(cuHt#`mVc8k z^-IXjH(Hip5`?JI{BHcVONNCE*#S8x;NuY$jPYvZY*=<~jvQnDgS$BHh@0rStg^13 z9-vS~ZzR(5Z!t#1$4A0UKAn*%rbps@^od9kbI9!aMkMf5i5;K1NBqSSsk2ianBBeD1^yU0Q3^*-aB?>CvTy zt`AX886?RY9jocWrH);sa0#t^P7YpYq?9hja`g9KMx=-sGZPxEOV;92!PnayFX9Lq zx0j@ZFL9}8y57b{=)MQ{`II-BQ%0Y*i9W!^wjMoJvU{)nDY>1E(Am+$y8+JqXUX|?%z8zeNOz37(q_F6D7fResbec`c^S) z&5+PDq^SM63=GX-Z6xO+p-yCpztC7&A@r1N8YiZ8*oK0;{Ep8y*<(JsAPue-92hE$ zvg?3pTFQeT$1hSR6oN3x+Y3&fIP$z4dUK9`d_MT{JOobFIHXUB%_t#<5}J~x6SrUt~MId1W>6*jMt^x}*V4)32pmhRO$(4nDU~WCt6L5l~NPA_s)n3}hL|S6Y!maEl;(IwXS>^tD=Qw zE<54SlLba#ia*(>y^B<+E1E?vlPd^t+m_NTpD-014YMXz=HEk<=Y=96Yho}cAA1NdUw+zzNJHQRD zU$iivIJ3jv4|rP#o|dEEyeal{%1KpZd5#7|+}f5c$t3;)#g9SN9x9rmN!#KgrA6V+ z@G6{fuQ?GMOu8Jeh3e z`;R?q6xZ8dfLHCNa&XPqK6xpDG5wv;_e_vR&ZX762Qs>;jn1wQmSQ(;RUrSPw zjExGF1&W+CNlEow5#`}u5?yQ_wxHjFWRUP1h)3>N0g=t>N@NL1l+>19XvwZT{=F%> zucVMGhDUQ<)?lZM9vxnu?ohZ$Ix|ga@_KpYF{$WqxdDmIDS(>jus>2Efwp#5{AOau zOi$}_o%neyJ2a2^N}0>0z}eQmM9$yVO(yr2@5NN$Uk3)CR_(#6H^pKrNrz96b?4}> zk!%FI@$r=3s$^Ii%)O>iCcVn6@yf~e%*oB;d0qEgn|gRU)>7K*wSXF86X4;FDNlyS zG)Y@|3JI^ays#yCfMsl%CB~^ViCOQZGv)1hcmF(qI7b>hsNAQA*|M7h=CCYsAry*yTF@_^tvkrNXxOE#?l#SX_P&*^V3|z zmM$#?KVsD~K&+jH?YcMhS%;El=C_=an28uQ*Tp@balf@mvVM!>{hlgTUhdL*-mzRl zmffBe9LxDtNi1{IJYj|TH~Kv>7ToEi`$D|H_RRF19HbaiGCtXnFc6FB;@t9(^*#SQ zu{U05cI4IK{vO7=EEQ9WECA^=nLAbubul5)m94!`4<9L_yliGP6+|ar591q;a<+@^ zr4}Qug5Go3pg1?wlY}2m0NA0N&we_H8c`ZgMI*u>q^DR}BtXqI(t^$Op+n!`Bbq_0NL_gU=en+OG3WFDQT(+0M4?h}$&CaE`&8j+|S zymc?$J0Dz^vMDvi#gn?b_%T{qrVU6T^TQnf3WiH^JQc}htMywxAZ>o=xA)(p6OZiEf)Nrc9{^!YhNy@feLjG$ zq?i+Fwo?LTNjs)%4e~iMOl-H_C-u!?*YwQ%f26$+bQ{-sFE}$AD~RK!z-Ww)5mlMF zxP*ov^$(&|KJ9CRxx9de5G0W>t?+1b8WM&ThA*yUMsaceJcQ7^p4ekh36*!3`L|uZ7t(5}3 z`gwx!#RNNKzfsU}vLXaXdYOP4R_+=i)lMD(v>7YsF=gSpBo0F2qaQ=Uw#}GV4M1G4 zz@EjKqXf0RbR1RCR905QqY%wSfME zscn?QDda1Z!dVAu4;vk^2^>KQ2CZHY%C())KwL_yE$Z!&f$$#QN3papApI}#ZKebi z`=IqQI2F_I3uh0yfR&&o%P_~Q3+sO8H{JzY6w?^w&VX^-mUt$EGGD1R-ct2b3NlDtKE^d~Lnl z7CvmYNVdrF5J6)A9FCR0!G}5f==eFftI}hYzG0h8Jg%(oo!8+?*upSyxakTW(AAHV z_hw)_kb|+JD0`gpUO~nw2-hHVsiTSqU^nhMg|;_&+bfs5@q2@9^C7W$>1hF6kiMM6 z)m8~=d)7i`C}lXCZQS{Tq!h8;{|u!E(-$fdvGGuEh`u0P^9oln0>r|Ip*1%Atl%gB z`B`{fc~*sExWY{33$NeXE-AJF(MV4LWNzO{u%4?VO5ar$a7poQ86LKU`+9Hn{{DzPou zD}20a%C-Rq(@EfK0Zo#y5{iabFAg1slosmpvKXo~&;SxIlc|{Ga_7U-=k~)CuX6KW zr4!j2NoG0y8k86=yf5FvU@TdNA$K``SaHEN^u`<5xd6fdgP|3!0uQ#Cs$%7Dr#qCB zucL4uR0ptqZ3j#mm}l0tQK40~5Cl~boJei)75D2c6yG&xL2+5~_B9~=kbSlbHkF|+ z1BMU^6Z2@=9-{@rFV9Ja+saYAWkX;wFJ4v`!Nr( z@1ZUcTCHM>7hH)qtt>I*;B$AyU$|HRe*k*p*y;+!21HN%bs5L_sJp?J%yCNRaWv>n zJcHcJ+#owJ$60l`;W5~?>pQGj-p3RbQzWC1Av zgg6q4mf;C;91+*G;yC1ypGb>fV2p7Rc zDX73U+tp-kGG%@aMgV&jUtQM9Y zhE+^TA0Z`BR0R{A2iVsRy;tS*3$NWLH5Oc?m5n69@FXgiS1FYa0O}HPb`i=Fm+IDi z7cF23lX&{adZ2K3dbYjvWhtoV5bLE7hI65#nhe92JUI{w4(JA1V~vIif)Ll4KWHDF zCkVn}7TOzIQNHz$azcPi*t7vFN$Ym3KX%~T7z-EA1b$jyKa4VcHUT)2W&a-jIqQ!(l7_(R1gC1pvmnvr>i%Ozd;F(WOZ8-plP8GP{DVH z(K5)CrZEU|;4{7uo}emJ(z{AA)Yn})GpTbGNChk~_M03<*JpysaK8uO%pS&ByC%TG z4erUH90Htl(x1y65ELT-kDfzBgYXW)`>GD>&dGcNM(DO#+!hXuEO;#mU3 zAeGpiY$G^)m!3_T6xtRI)IJaU`#j|f@ViiP00dhK1~NX|B+*mlKoA4xb@v(W$4N6^ zPHRxOm^24HBEQ@Zp2W#h$O%Z?T5dm({8pz{E}rhm1Mrjp|FG}=JxW6QH&W?B$N)CP zb?&WzHlTEu2dK0Drsaar*(7vWbC*AcFepq3WStQQ$*=0o@BWi4gjw;vp&qdDp4r}R z<&gpb#gm?(GVcm~R)nlcqx0|5ya;a~xlm{_cd?t4Ws7Uuu{5M{s3A^6TM|9m94({} z5HY}i6wIuyx}G=B?2_g|F*007~J{z%roT0M_OwJk|dRQH9WfI0ObGv|cmT~12ZbDMIva^(@=H(ek?WnX(R0-m?CcT}=z0Jcf z_MkF52+(xA>cOIB0W%=ml;ED{Nn0e5s6lez-$@}kD*c(Z_gaB{?c2ex!V6$UV0AJo z0w-5|EQk<_wNa*ZkRUKi$;HNAzinl|aP}S27X&MzL?MrmN@!FJgT77cZjdTf2pTM; zsl{dA%FiQr?_41`088aw|N9E>*Yig>m37zXn7A zfM`Kf05)Ltu>;y538|8!NI{gx{4&5~Y4rvEgfI7l|Kpu+mr`t~RVkIQMcWgSKA>E8 zctbKN{g$OaxGJVH9*{hc|E+G;JFf$Q0x~MC{=s(CA|Ri6nX3fIr^|(x+ytD5!!Pl$XKw zg$fL(46xcsbm_86QUPjdZP4{7W||!=prk0R%eA*x?|R}F)4whIS{Y&Zft zRs#6;fOF}fAy-?xIE0b#evad~2&-MOblc08482PoAUzbB1A~XMFE9PPT|zs6}9y? z^4AwXfO9~KC^f`QEM?o30Jnuh8ibFZTM-WI_UyoD{^6x+HHUPz+yDP0Gw;a!~j=$ zjxq`%jr9D)aEbW{%aJjWk^_*Yy&J1H|FM010F-e%epums@^<|AHu`fo-e3sKe^EZ7 zl|V|*ZSKPfxLf+mGU7cr4m`24!k+vpd!*!mJ6HJQ5d8i?j>GIVa08j0^%d@q-{Jm> z(z~(jpxznG2MPt*Sz$i%1gk;B+sMZZZAtnH`!W0D3{ui}dObk>-Psf<7JL?T%N@~_ zXR+g|Z{xo74$)vYFFWPZ;n{~vtLz_NVgGGCbN+(tQ9_1N3ccI_Ff+IDu{)oDtIPjH z9fE^%spKO-=Z2h7ekU4gZ{E9=|AKUW5281xEkI9Hj;u&N;^g*6N%7Ckm;f7l6Z4q_ zZer)$M-wu}kSf;&{@}xm-nKkn_;1=>?}645_5cZ_P2a^3Rp1hz5NlxZl6u{Z4tVwy!;+qZwYEiuSlWB6evG1o^58C08i@)*r*Ef-7JX^ev)S44q1|WaTisUG2db(CxR0lw#7}t8U6Vk1{Tu?L3Dm znQJlEi%PrSyd#D-9Jwk?I`W-mzAs z?VXh%8qr|Y$}VHL&^~sgA{TwnTQ<_2m2a2PO<}SrvO9ARA2`}%43SK=iM1D!x2u&kr!81&OB0 zxLv4#LP$aob>Ya{NR53xWYId7KM`MVIV@faVZ7t^Be|X5OYX z%g8a3W*KrR<#9zS;oIC<=p*J4bPrkCOT7wEg-oyS_sTA#`GX9A38uZkPg~{V)dTOW zN|!=a(s1poI3Z;2?OKz|Q$nCP+wOtXnidk~K**|cdl39LhJMgIk{l96YA=qh0hs~( zhCd!0gVKB%@(4PQaH*Ge%SKPh(N%}cQKz<9C*d)jZhy8h;k)u}3@ZV(1X6EDVK-mS zRFONEM+{*qih&Mi2d9?HasyoLC)AR>HV!?MA2KDP7Bb1kd2}xjR!FXd!>~8$wpgx+ z5>yh{tzm?1Gc_(=V^7H417ozJau+TM#QlfEu$v3q+DG%1@sI1UoSCX*T& zx=u2ndh^il$gLxRJSbadCytuMFh~Vd-m#kIs$8{s0eMH&s$6vl9lCJfEF2sUL)^an zx5CubLOcvRsIc)CmAeNlZ1WMDr+vHaM-&1^YGI~*J?NjKSobC$!xRWyXw|pE=rb0n zN?V0V^)Numw2Fptut*jmv=8WAq3SJHRcsB3Zo6q_3P)v$Fe6e40*NiX)*U5D^0^0GWM`lp#G*p{=m*rGJu62WE>pnuJJP zSfFPJA?>cne{pYDWv+;{H#VDPa$nzZCSg0$X^P_V>6s=y|M~7K0PT5DQ)D-;mtwk7#JES{g~7cl-ccl{Wh&=!$R9|+Iz;~ zU(HsK#*%j7wpEaD8Jrd}Uy&x`dj1N3ng1yWljd7a#@YK;`lQkUc7bh-7C4*~53#|e zWRmP*gtnV9 zR#U3nl~q}J0lG-!@Bk5FU*r)bVo$H^YwylJ0XqRL!fZhwhoKPArid-+EP)!keM-G@ z|yOsYlKimg6MBapRJP#{)Q#}r#18w>iET^>~R zt(Y+_(9U^ZN_U}Q6(7Rl>D*=za*zu}VPth1*0x^*V2tdh8=av6YM1!eo_hC4Swyw0 zrr1kH&C{X;M`NH;0%JH8FS}L=*og3zI90uAR|!&$q-Iq08ghL7m|Ggb)lqlSrz$oH z*CII<7HfhSyr3y$kt&L4`GEx< zrSw1{{SJ%|3bm0JSoEXrkocg7%STb`R8`xHm}Q!RH{p{MB?wU0-+oq6aIP6X9P~%< zg!H08vr^S@KcEWpha8m%byLJB5ygqdf#0IC z78Om%ECtdiSaMT9K?ouA$%=S^oBptm)TB`GOaSK)EJMK}-^u@w>-v)BgYe`&0Md^RHh-a&`4fGU;Fa;$Pd? zr&Tq|X?Mv@4~Ce9LI-HpRkJMOWQWN}Yc8wxx=!?rFCf_9vSV$<(IGCkmo26EYM@&? zbVKlHx1Q9dLbbS!vqj$~u(7i!lyh}9rDfp}sv_Ia+3t9>hcDuYB4dOJ&(?$ek&;q9 zW%jH6=v#ihme(kf07{1&!|uYoa4pOHNLK3{91F5qTgq)LuwrB0tTJVwl_1*kMVx9` zt8%ne!vH{R6jl{_T7^2&+wDfa&jWCvsPPSa1YMgd4~P;S^R^B{TKf&od-j5Sy**@v{;*(M#r{ ziA@wC)0VCIO7=dhu+2r6jAeO~S^zC5mjYTOtEcr5A1SVu(w)R|DvT zDXO~MSTwQ`8=7gWi>)I^_m6Pj^A)3SkYx$b>#Ju~$9BpXhDQR@43sHA4V_x{jO!-V zZgpZL7^w$}LHx9%+GV)HQ?JG?=ma^jU_b)jb=kuBDI>I>Hu*e4hEyLu)%U#ponK z3A@fHl%S?4c#EN2=snqLJ!kd6VefRx6rma=GnwBqHf5M73h2Sa%VLm4waevGn7x%8 zTCT;Ag7%Zt(Ls;f4bRC}Mp$;nO+~Ed-20!j^uxXg=A5h>o2Rv;80AWNtEqSfx?h?m zk48qEXry!PZj*82&?E0~4X56-)95gVG3hCup+SfB*W$E=Weie&MA_ihoQ$>G5L*dx zwx;W5W2TZNxv?O3+Rys`#lf`dNN=E|&O4o7ca1KfCeGTWP7-%p>o5C9%rnfRg;UJ3 zxB13otWgO9Hf87v4({yUVG4iRyc`Oz#XEbM{Zah7#l|{#D@_u11xtChS-tLeQ~_lVJ>F5u66% zm(`CsRW-0x1LO?3RVojbP*`-vn$mfG2I^Q^Eb0VUs3-}k%8eV}`#XgyHMUj+_<%qf z0joElHjyb@QdMi3QY4s<$uyi;*U)fq2&fEs{Rv17VY@fB|CyrdWf^+wTy`EKAu3e9G{mgBgvMNxvHPpfJ~Saja0 z>Pw4I)=rSs{Q!RO>KVs5{PYF=uXy z!sI%Rg4C*^L{GD%X&5OkbR}tM%D(^nuFh9|oGAtCQ-kB9V&#HfX>yIga216pRc)9E zV(V4Cx@Hqm>>d}nI%|Za>mk*W%RY2wij|o|z8`p>Fv;3!@`6U3O*`F`HffOMiL9^D zJfd40UWd(L38)us`v?pX2Ry2(_MMyWRus7J>Sg>NK*K62*MSDZahk4ijX347ZTvU5 zy}ojTK_Zl?44HL=kr&5wWfE=)-i{eeUf&Fb{r0iaXF&P2|6U!1fF)rSfGDWJqML&21+9a!aR3Z!0Dh>rMb`m!0WGKlVYci9 z)fv{WvHnFbBgN=l9OmtX23^DY7 zfrVwNaF^t@Zaopsm^Xg?R@PdkuB}196Of#?Lk3Aus-CZrLeeAP(T^WxnagD&(k&$q+2P*t1)n+}T7HV7FfB+fR zs+xe~FQ!XXZEK-G^eD;ryFra$f*N_fiX(Vh{Dna}%{^P({M zF2jn@8g^kYinmz`GbsKz4_8OKVg82!QY`mX%k#$wNnIkxjm_3(t9zSeZ4A;&>CG5l zo7s#FF?B5{*V5Z8fmZ7s6E68~aE&gp?!Oe7iSAL7f3lpuWfbCnHJ7@HXy=*G`C{gJ z@H}bxTf){(cQJLDygJ_^VjyGARHZ*>j&?7v2n*A2rC_c}I)54iLlI~%L=rtNTFS8kHd7O3jur9Cj zX*N2_`xp3{j$4E$ani=$r4MYqaNJ2=nMKY!imy^Up_iXj;6v1_w-nKDgzAFExD;5`gC%p(6P+e zN$T*OW6$cJzfQbY((8JQ$0`>y-SxGs51~~&RiSRYO#2r|$7|&#>-cjx1HIKIy4_~cF3GB&XT6K>-r((E}F zUM35r$1VS5axUJiULd2+CcunF{50E3(~p~1Qcar1bA|DFqlP!o)Ub~iBp>o0V})0P zlE0}u&a4LB@JhOwBI394X8FjnS5mZP$+x7$Bp!F{u-=5TH&yZvk(ADN6MKp6rs-|w zCN@sk48Q|+r9^dv{d12!Hjbp-1oQ<7q z&XjM=SSLjjC8x3PeU)6m{1?VZ{Tl5t>aV=`Mb^CEdiZ9UZ@K?$?BY(=#p@q0S_{Sx zti%WH&oZJ5CH#y(r)rYTd;R}pU05$1s z#`dx;`T6aiaayhPP1D@Ro8{w~ea;~3DzE-d_AS37UP^V5W5I^RbI{iv7mQQA+0(|c zp#Ilno&>XG;Cu&~!cJSXb3St{pcuxt!H7=u`ZpQte8PRn_BZON zDG!?bhGlf|LNj)9ZV+G&P*uO~|Bx|9zbFZ+6Sf4Pfe4b*gAeoWUd?CiV1s5xBRM=}f$Wx_knuR3#paf!EuH|b8cc6>f2 zf$72%U26tt7daW+w2Y3h)S$D;-k#J_WopiRbS&Zs=Bad5JN7?vL@U=?tFV0$%}R<50KG3{2yS z1ODyPu7=4$vgp#}LdJ{iWl7J!Mw>ZhcAasuY0k&u!wq+*_wpY%xtwCL!9qlQ9c`$& zn=IeOH&_>cIgbi0cEXBIs!Q9`Alh2Ei6o|oh3-Q@$}jamM;&^NPy7^uW*6E4p|_WcX3S3e>S(k zbm2kFe%mh(xE+>um?toU=xH`^o;pG#@n_m`ngz{6l^GP}<@9VRpDj}-G04&Q+MCOx z#6x3b-*>gRq1C@)dB%k6Gvlyg9O zFm5-1m(yW{FT0@7s+UM-=xH#-vm~f47;(Q$6QC4JrPTrdLzu9%bB`AyiH90r5Hl>B z@tu>wtAUyn5GaT<9_sfN^oy@>qJFD+B(G;75|5^I&+F6!mejKs*ieJ|pj?9kd6k-) zt=}-?yLkHCwhhLvitK&!D{+*MdezI#V?hH3*o#pjm7gqwOy-i%9IlX#cbO`y!SndO;9ad-Q*Sg;QY)r2X0w9BM8%huEHbcZT zb464OiVZCusg{GliAR#=X+%lOZnow{9OW`u8`X?>Xz6j2grjp?i51tp9o(nR2W(O`Z#4r*ipUp7>9!sIee`iiU)|RF0(8jxh8r4F%IQt#&ti$f8#u>e#p!>1@gt zOQIE@#b10zL?@;2psipNW6@VKf~cFA5_IZWqKi!}c>mc;_`@(^Q);&^f=zv{2s(&9 zomc2?N-meXh1#j7y;opxNws3W?+5RUU-_j4?;14dl^qLSIXvb)*7u&C9k2Lr9%b(_ zcf9G=pK{N|4dTKRmZWO!LsrHZjdZ?k&&URXbUF^H_QO)!?SPa-CN`{?&`{Gu}+E+|&<0 zCH<5Q;&t~rzZSlMdvTlecRp-e@Z|$w2lC(KXizH$R{V@5MuJH%f~PF`zpddhoA4v? z&sa^X8FWOPK-3YeSp|5LORb>Qp(RgaO$2Zy4j0)D0VN9pvM6y<%Y>&m(*(8+%19jVQ0G$4YwIeHK_mklgD_;Ip{ZbjEU>5y+)!!2EvU; zYuCa-m-KGx-Bq`qZL+dsbl26x#pNf1EkaA1XRK+ykMOTpJ*F=Z7*3lde>0#l@%14F zgu0URUVPc_2=wW(O+`qkCn%>vH=_I%+T&Y^8Pe%NIeDF@dq!}!*G-T9Wnx{At&zv4srifvU@$NOsm|-vY+J60od3a<>_i2AjS>zJ0Qv1Cz4tqffn%59X zr*&hug{Q{_Yv^9Q?AeC4hZ+4Up5WSUx~WJx@p3qSE>S{Hh#PoFI*MD;4*idJWUnmujV^gPe{8;PjzhzAtiMz~wITI@=f-C8_XC?Ur+UzpvzP2_(Ge%r zD23l2a{WDpL!&HYPW&bRb?POsD!<#UOan30Ck+ZGKp{?U%v7>8*kJ*4yaY+YX)}+UCR>Mr-@)$Yp2azBp67Gs&8 z>wdpp4Lp6TTL&zbYN%5r7OK8dC#vnu3>m~m0;5hUR49P6Esx+fdv^$Eafe!}t(dHQX3kTd}>CMRqxEH?2_b z1oN{YUuOGt+t4k4y66Y9bdkjgU(P>^)PO%J%$cIXc9BJFu)yGsqU7VlxPEZGN~&aLhb0g`Sc%+)Reeys_zX)d5jBx z#2E;Tn#yst0n@mjUI_v<)9FQs6>KHlj@D(koCncJF~-kiHd&*zuSFDRmI?TWuF}dy zcFW{AoC_n0gFYij!Qrgg7^DK6qtfn(1whkiW#;O3^g;opoer+qs5zUc?A8c}`(>4$Bl9anP z?a)!Wio>7@gO=f-0CqR}U6pEefFWQ!6v8pckWvnDkBu+kqeC{G1$ zz6YSvBb58E|3zM_G7*|$EuuR;AP>-G9P7u`_foB@6R%V7h;R5&;ZW5VQL~7|DdK3x zM+CEB_mSo46*)LVel#>A!iU!*y5-Z#Rw4?gxZ=1l3}wYu@f5!7HF1sk_<@b_@0`0w zW&)KeKBI4~Z1#D;R1Gl}RLve@I0P6b^pIqVV^ePEwiXCZy+wfPYIfOA53#H^67D6+ z=JiVFBS9a^IFv=$2+E!82Ho$7>>w4^$3dLYtx-ndMD=NhheBQPkgAH{*B|}jJ7V`+ z?~K`N*TwXd&X-U@<0vMLDJ1Gp8mb=8>WiFbhva+@$L_%Hf)|F*#Xbvs5^OaAX(zR4 z#^6%^029OcbCAs^aQnp=B{keFa@IC7qxjiwQolNHGDx_d)Bg7gK;vz+f5N=vd!$cS z;)Xur{g(Ihm^(-P=Ui$c6^4orO0c{(No9Io7^J0m54;JlPxp}RE)xhRwIA#$8a-}b z43)6MAy2AEO2>_&QE`~z#S3XobVRu5xNmr*EF5H${Yc-VLR7iv@%@U=vxI-ZJy=PN zRfm|L48L8bm6Xq~t{eIXo2eZtd%!R?^BG;qTZF$esxCTiRCWDDpTHRVwuS;3brC5L zl+AnwS?RS@1TssfR86EdqU@-;$iOToQ`J11v{=<_86za6GpZny%8(|?aGE_$k&00$ zm3A1VDh~4I8hh@2yVz(3?$_W!1Us$usi!+OUOae)@9{rpPSF`RzvQfU%A|0ORN@bu zCjYVCGz#Q3jzfXz9;>*pIkqFUg`duUm>nteawQ)Tn38gYeubW*C-(0l{A>>}GeVv& zciv*g#BQgf^^xSm^B)NjI6gMM*Vz9gE7Rf=r8Dj(wx9ff^~BFRab!mJhg(Lki;oUz z9m}M9;{y4#yQ$=N{v}^7_qW(b%FXn)d;&PZbvkcuJm?oso8*^CU#qm^79-t9&pIEe zKh1yH&9^FrH%g@VJ;bGNy!>P~_EP6)%wKn{RT@pqIPVR4CEsy9FrR*8-QQW>x<3iX zcfHfz2gvEp?jEP~o{od5Yfh!sf5p!X?Rc8Hy&qIGuz!44R`c7-QpHyuRrpRfeR1Z?6q=Nh86}ffQ`R2wBP~Wxk8)w*ZotYAAj5$ zwjKb4cEWoPC1O3o%bn^sS>ZyjcSQhB^!BH^I>?FmW321JW3~DWKQP#s<_Elz-+v)9 z*eEV=!p`Bc8o$lOxVLk#u_?cs z-dJyKVteTgYyG41spH!>n2!P9UdQnwG&vMsN;QAsWUcR33h&ugzm+Nw zUkB(M7$<)$KYqdT09dCIgWhB8JsVH{<*^8mpsk8wlfj`V$b;!DhYnsSpN*l!vzZZ(E|m3nq>Ee@gM9p4a(4_*G`G`^@LE{n z8)?_}4ZWOpJ#5u~pIj*E-YlW7x0>ahuR5c2JoKJm3nWxW(?>mEtL0mNQc+^}zlt^8 z&Bwp)=Js!YZ#*nj0CvYjtmB*q4o~i5Ls4i>*smdO{lCl`n8mB4Tpv9MUl&;x>>3ENlpTp&$ykajD~U#>$ELjL0?fBSBQl4IeDfjQQvS6KYQ1>;fw8jr;pk*1)CB zDRj=jW^Ja%2BYIbIaE7N1AKd$SOZTKZted+6|;*Rcf4KvJ^3J4dguX+5Zuj^Kr~sx z7>+%BHaX2cI7Bt`y~ezAxje&+Tn}os*9{@B;^s=_u3W8Dd89cQWK*g@WaAscc+)S; zlIIwu9!nt|(cGKwN==q3tn1;x>*C4SF#ixoefJ)^v(I{&Yl4oi-IKspX(sm=emXTM zw@oEHoPU1eweTUjmmLs;v^!%cxhA=R=^81ObybYZoD%OA_6ixK8)@?9%M%JU;}(jb zQ^WK@N28rorTa1@7K!cDevT?P`WSxjlJL7&f&n4V#utnkxAGV>f@x+%t)?R!n^~U( z=qq$S3VneJ_3~yHsXV4%Cc3zq*OZhVI1VPAFO=6#4ieYsjv;v?A?#ove_+Pq`T3m1 zY4RSq0}gRrrj$9cp5r~lijr#&>QUA3`kEvN=0JuMFISKbI+$SlNm85U$!9XNJQ=7giOv8mmmn&H zWluh>A7&YnoxsDP|K;7HCnlo7^-%4pvOhJ1mb;ZY=nU}3cy@xnKkw2lbUlu?ivz-z zRjDYs$X?0JkgQ>#Xds)o0QxtHPMuPltw$!DF}B%4{*I?h^glK$B6pn;?FOkRw!RqR zJX}M|S@WEDw5nDx$7xNLuT?q`xhRWaRo%(}3&9({@ehTp^%=6+$~M_#GWI+({Ic0A z4(G%BC2CCBgOr7zEgLkaCD><+1+vCL`Iz%uxzC^AL0<$FT9?bT&+37NEIx}^k6G8x zuC=)5TD3sjv*;br7E#1IjgRZpw_1fWh##qMOvT{klBq`=zw^-=9~#c^eU#qAH*qpB zUz~TUjZme;Xf1VyF*9}Z%fFKKV=7;7242gH5uTf)*-ty=?597Zd;(=voBjaLAyuXU zx7J+%+%A6g3UGx{XOz+qfnG+{ns2j4lZyHkfY#vKqna4VjD%63+Dz$|S2+qt+9g0Q z0h9w5PXiPnmoq|}mKg~&>}r?G&(iD+W7#tdZ=tt-W%G#lHvosX{7bMm;BG*~qrocD zyowONvU34Iu>`Cayf#9N?<)wgM6mxw!1~_;&u`<^ZvoFg+S7*M-^(BGX%q7+=B_q1 z*Yb~>lALR71%+<|=sWT8_@Vi_{9#`kv%XCcK=Ai+d9fc#JpZ48-@9%j`d`Sj@9o*w z0d`A7|5I>dRuFys@YEoR?=DMb36Br^IlltXyD=&s@b3&t@I_!u;)ghXcY@fZMD3;d zK|gnI#~+#g@=3GvDXAEPLF^z(?Y^3Uh>sqEjjYRs3=7igF z({GsW3G>be9XB>~1E}eL)e9Y!?+SUQcUKJ`+ZVhVpw*Ow$iVnG1Pb;4&dNg(PlrqN z*FI}U6nsV7VV3;q_Lq%-q78ztK0$8(;qBjLXlbh}&)z66R4*B1QzCweyX9xglpG^_ zP?r9{5qicCCeVH*wD~>eTqb=U!2!>7?hx=ZM zv9->#O9t)bUf?PL#u=%TgtAD0TCJ&3;l}ujzD}r=DInUSS9MRA5Fn zBZEc(yiEqMGu7`ACw$4DbA*E2SNCYHpfRNw20-(wM+2>-T;=L+Y869|>rgdZ^q~{$ zB3DXLeYa@?S(r7mO^;QSR$4#Vff_+7W+_{*rGUwh8W0&0Z)heJxeG3Dv|NM<+%v3H zPwGXK2pq{rp6MCOB1dXOh!Kp4t=*}RMU;T$3k|AI|T?X zTqH%LA~harEP*nx?q~V}qSWr;*=r1?uEMWVJw3{5r>O5KMZkm4Svn62MnzgqKxVGsWSVy zu&+h?*DBSDNSTd{H4>Wn;mspQ#kA{9hW`hx3*sFqePGPL-r8)S6wPQkoNaX%t>P(! z`HPhRMPtX!eEy2ts_@#vdSh4=)ur)(^07NzQ8n@vuUJO& z?>7I1Q$vRds*AzI1kn#xfC4nllzz-}r{O~yzqXAIlr8r~(sI910WL79vrX&8aqsiq zSFHuB90dMIaKb!p9&>^+gy}1(Q4asd*gq8dea6R!AWF;T9;4puc&2IcT4sI!%YF;x zw_PluldS8J3jgpnzPH!FtqYVpVi#WZ!eG?nnZ9-BS?5{D-`|)s3mD+r9|WpPj4D6F z_xly^g)f^_H72nte85jp)J&K25yH}*_yfAvC_Lg-Z+_{US-eIe$LUt$GUZi~Dtq4K zj612KRuqef`Z}dg1(aHw!Oc#)TmdvT?PhhT1P#ks1?pThBefoyg5g9Fwr&(vASzcq zT_iGG*^26aD=;ASJirBzP9nlXQ;es~jvj}t+<>DtohEvAZeIMa@R-~a)X3^Qdx@5m zQZNe~g+;O1yA7Cm5pVHq#Esrd1@Z@_%kaDVVU0(G5}#oxZI<=eNOq~w)M;O2IhIN- zb2Jbwl!Gt`MBu1Zy$Vv_pHb8a`3Bw8$8zsW} zl$ud2c#T5gka;@@W4dQ+9+W()*1^V;&qv@c)+kYh#{zt^Ue!GC9)-l3ZFa}Zo;-lb zD@ax7-QJWw6~2IS;*Lg4^DB0!XEn>dhXqj=GytOvjI01~YkN>0(=@BIYN#i4`fNh)V#f5R`7ASta^sJGR|&Dl@y{QwQr(|giz?VD{a6mZjSxqMdbu5PjmXsp z0N=tat|GudD=SdF%>t1(OnobUrI~5l?^(fKa_x#Jb2L8=)Qp60ZjW{9;wFp)1|`UdvxBrFD#cbhRj5LcKq+ z*LKj@d5?)jpZlFSfz#2lk!WNI46va`0gYBw;-SmSuW}s}3vCRYZHg^~nBkz(nuH&z zeC@1?)mP*Iv~0_-h8edei*vcH``JjE!n5nv{YueU6AjgF6`rCjU!EEY-7%lI9<^0y zfT~ssyl=F6ra36#P!gVkYrcg7UYNK5 zxhTm-)TrXRDz2gMDiG^T_Buxat(I2%;>cs+B^)5Rr~K&8-aVxeXDl0mIEWUcMy}4J zZij(3vMdPaB+Cxc4YbG*zU9iuDETR0w}EbR`~C>?1U?yJG7>=1uIKDIIat*w>Q&YD zA`GkTGFQPjtb$w)De72}7}vRS3JlBYJtOC%j$~2Itv}xJMI+k#prC@J+5J8XAscI=b(`+P*7Fj zyeK!mm$#9U(5AF1ZwXaGPk}?ozKr7VLpltEyDAXFYPcsj_6~yQvRW)IVmwfdb zONJe)PM}1ark6#xT+O*>(L_=lU0ohpoR3{4I6R`n{j4;Gn`5l8^>EJzNE`ewvsP?y;V zTIV8DQl`;~;d*WD5#dN9%hW_4q+7@E0)~nK%*tzVPqDl#uIO_}GTy=MTNf_b8FwQ= z&cU^N{F8j?1G{^stzlYNF0-<&4d)vzzb>GXS)t7GxQoq0`{-$&U;aqG!ahXzk)@%H z%f(aXi%yA6Et_eT6k{{|LpAsCk@WXEh|Y)eEn@?>{JgthE%%o8x_q;FEcZud|JR55 za{RNVaj-=p!MNfN1E1aR#i3P{0Ylyww-fr)OD?aTR>ZeEOCDY@570-Cm-&qm;G<*i(pg2c8;#I?K zLw)n~08#hSzH6L>TJ1~z1zzTTA_$USG(*R^XL7!edG@WniK_p}a#;T?Kfumdd-#FJ z-C@7Kd4Kd3l0xxoL%WQGX}xh>BDUZ3ZzIYiz5)(Qg!jRngO`B!4mS9Q&&5##J3~DhJfM*^C)QAh3y`NfU#O z6KI5AS8bwRtJy)U{^oioZ z$&H+jzUbNQ08>9!soY;5M$>r8%kbQS@wu1>-0Mp-b9`?rF*tRx@w^qg#r?6g0e{Lc zn;#o!L)$8-5R6=B7mW8eyi}9yeqgbc_>%b&*9}zArq9K&UOWFnp+fl@NiC8(_#BqOSyyG01!rjmXEb zP|fY};Y<5in0%wicd?ycvQGJhbL+%6xx)AG>L4%Zq8{0KttNrn1NZRVsRQ@qO!|z3 zh=t=ciFI*!%IyVKT?h@BHQden35c~|g%k<)4f8z|z$Umm>g9A4t5!p`dh7Fls#LK~ zxGBikSGagI6#KZi=i*n{d_`O|^?_nRhn>Rgoo@)B&w0!e*yp{$I7SlELv*3s5&J7T z14P`I|JC>~v`cbuY7aF4mNv*v<|EJ6Ks<7>e;J5Zv7QrnAA=*J{z7#*=IwnT^ID2qm`w*-Cg) z)C&}#?rbi=Cl5>kX_nw@AZyrT;)Hx$nsXxB%ndYl6HtMwGhbQS3ojDfg@2Yd z;L^ZvwRH#xi|js#pZc)u0P72|+fSle2MJotlkqIzx6kr~ept3747ZBf;UaD<>NW{5 z+xx5$u>7i2J;Qu&-az4U*&rj-frQRF@l2s}J_+1(fe`OrC#%`2BEUlxZvb#xq-vI~ z0diXf2g5;sU#p3<&=7~u&2^j>NCTsSE$Jy)8nY_Asusj4$vdTRR8@ZT(RT?7KV7Ie zuV{`c-JzD7$t!!fQiXEzlvaO}WdEL{0tjFP?@&{b$C#sZ3Uw26((Lr5E|M*gE}lI= z;I{O_$nP_oT!9z-VPLlalaos=CHK{$KG5)z=KpvubFy*X(5OEHcuV3iT zrKooXo4Y!7)Cs6Az5$Q+^0l8m>LVmUmOP^tMh(A*m_(^h$JQKWCEK(hXcDhTYPNkQJsk*pm7Ml6-!`QN&|M$5?&teH@AE#_ z698TYp5j*Zt$*~~9XR$N;>%zkv*PJ(GVH9WVP7Cv-fp~*fM0`d1X?kKVgT9V1i-jPcnRC{Xe`xS(Qq#Q$6;_N zuqb|(g=6cZP6E2N^K7YiYd5ZprV7mVl0;&&2L#Gy7 zDcv{Z-Zz^^^gMsx*fHQ74^;$vPU5uKe>T9qj2cb_Mbp z9&j2=4IsDN;L@V`aVGikfjlb($i&*{YzzP`k1ZAGK(EZB2C9OFp`m5xD^TJAiM4B-;YxnfZ(B{bG#19_;DfUO5z z7`tQj*xaC5H)-ScsSez)AOP&>eyPNqOxAf+>_sr7eUH-tQF%YjP3*~M#)cLa>aPTc zkj(kCb6AAC{riwPSGyn%0Gx;9MgC=B_~G66_wUJwVKHvM1QVP`qfy&RWU?8^9z2>7 z7{J>18DN^B)p6F?DQj|fjNn?&pU222n{LtoUAqo=Zvr_E+0M?J7vGiDUEscm!)rtr zW7%=G0=GZ4+J^E5HYPJHRhcqO`EhAW_|crecVx~*>8&x?0GP|hHd(_``A7{Kp(SnZ z+0M8l5q-1yJUst8y#Sm|i1~Dq11J~J&XFq)kcSHnuUU}RX7@51oH)XN349}a6Exm{ zXNngiqV`V*%dOPQWwMrMfimXb3>;5@G4+8nen8?ifCbmbqE;C$-gy8H9AIR7AV(dc zOML=9;sovoN4~)?Vb5}>tVwM>e{&8voyQ%i%)AB9V7BV8Lyl)e%h1%Y8VTI$dcrX! zKE*Q{?6m{_rBnjnVe<))gyBfpYapb7zh&S3`C*r~g6!A$+9E%PY5}I{x62aJVOQPL^6YPS758C3-J1NKZ0{2?P9%a!{mo|LGpW{{R5nM36 zWc*#nA);x?`~XD53$wtNn$5isb4vgzlodADxc>`xZ?YuFXV&-2H^p02j6A@)vl}nn z9*>q^1y|n7%_>l{_ZxNp!ic+nXAzdkK(g+Y6F@&l225rjWq|6ehH+kwiO(5xZLnh} z?8Ofi{a4jO#jUM1ROv!gGtN7c{Fu{_!LyuTf1iJ^PEA-PL$>*v!|Pj)J1H8l13Lq^ zs&2?bGJH+ljzI7Cji`qKf#ndS(1t%uedFd6ze4ofR1wW)Rzza4O`*2Z0D;!^*ehxV z$j}hVgJ~%#o5PWm(iBMFwW?N>&n#Oq7&6PWXxNAzP@+J^KZHWI{n(Q5a?DtlqfH z$`Qp{s%~&DJfl1e>_u61Uoi`l1F&;63BjDA3_*f4^XnAJX0kb$UJRiv#5DFpDGZ~o4 zO%{y`j8C74SW%OBR|27I&x~-rmxUS8EW4iz62*nfDV0B_hP@ zi>WYM8a9>Q(zpm>M`DqnijQIlfWmE&EnL<^anRAAngviFt((n&>z)o9L=WB>5pOa5 zz3hPwit(mkyo9f<|3nash>{g7c4_rWBsTT4=$9LjNj87RZ(DF`USb*o=GbKs^#Kbt zg|p!U{6obef`D7$mraI2B+#+Y)fGk?1|fPn91#P={yBnTgdp-zMn*`A|YvW zk&u2#?SeFjNAC?30N71T=(t8KQsuz4LuUo==ylfY8(=RjLJMlGOF^95r**% z7O@p=N|Xp1Atk>hA^$|7bP5BeZdBC?iB!!;zU*a4U-Mmk(3S=KThGKQ?UJZu#0eNM ztmMy7P@uc3)j%F|eAqFGX}jKP6z>Y=;C9q<7Gj*JPvp^Xy-``#v5IrLlq{_^Utt|70VCCR5w6TuspuDJm z{2$BP|M$P~?k4-vV4a;4$LRH2fhalAr=vr2%hij`BJc+PBlgkL2gR{~Ex)j6&;xd9 zc+IK5vLUWCA1lz?#X1JiG3P!zz9Ch6{9O6MDRl4hsTq}HS7l=X zQiQK4#$J$R_H(n1mYjioU2awCiFz|($wIZZphIq_OYAaZt?K7|g*iynlbyT{WApSe zXQHfzc0JL!OS*ICc*94#J74|}@1VicuLksq05T3uNLReXbpQBWc5YaG?k`ehYDLbU zd$Ox2`!6hNmfrB2SWZtrcsKpZpj56l)8}Z*w+H3RgRd zgvN)Q+RwT6{$!!D9U_=<^Oxlt@(?6do4kyWoDegOoyUWn$HuXT^wa)HzkQ?3SgI6V zAD8({Hq7IcJ>a+#Cw=+|#A@5a92MaIiPQJz3YVqPxZVE8@f?NNG*V25ix=GwSL@9* z0V`*(n=Ce$GQkj3Cp8GF0n4Rpnv`qYSFeN3YY%S>pH1Bli@K)r7B!W3t@R|I>422$ zzj6&ES){^3JK_zV0OiaBKvfI8#&$L?NU#f6@aD@}KW`&HeG|y8|4OGNOY1qrB-`{A z(0+lq)%wGtz2>>;Bedddm&= z+LbkWK49g`%?E?`KG8g7UkLa^&9NsQi%zrtLSgzkP}Ua}e^HD8;KP!06tHVA2Y?SI zTNZ#yp`Xhgl*b@MA%U!Zj2)5B+dKI&C@8E=ck0hQPCUiRvj9E;s-)Z+D(UrV?n%OApfn&2UVf zOwHCB*^y3od|Fdh*wU%53xGf9!}~ zt|G&HPSV0%0A!&e@C?A)y|xc+g@+bip#aR@@E@1IE($L=IV-$@JOYDbPsv9Afdb?M z^memQZO9zn$Z_Zw=Z;E5g0$`TNxGb;ZIBCP#u#8SXX>g$o)XKKU%y@jiroRI28R8d3XmT1MJCM-Jx6X_8O2L)#5;L^lM0(>910W~E;|{1uK0rX|7phYI)r>G zbPnv*H#tZ6Vy~lNPgz-)@4oO3#{8*E&x>CVpw}=?lge=bY|GQv>X)1OjAut{bS!zk zS%f|WAg$I)^B00}gPx$tld)-ZaMTTir^C;r{wCt78@+7DD)qj(doe3@UQ+AV+_(*O@suV zZ(;~w!)ne8$W%edo7?Oe#2Vg&JOJ3z5KI99v#u;ux)rV=mN111#zxeZizP17`K;MK z_^AN8%Z{#Q>m)M)2xLJ+0QOy0&)TGPX3Wv-{4yL5)t8@n^&RA~Ak!;`FG{vSRb|(C zh<%(m&`c2IpvecmDOzKgd=F3%@joch-j(W|;E4@PR-ViQI|XNn4H=3b7BkQaDU<%z8u*JafqOFc5mvC`bvy-u;&V^eV7ddtB;Y_9SX=uo_RK0^_SN*H3CNgPH$DU#KQ?-jI1>c9;9Bp`jlqu5wU#NFnEv5K2e=RE zRZHf}pgIGiZf($bH$}KcO%JdQxKg)2{6LtY3dVj;nX;0k{9P<`FEjMBgR+#nrs8`V z04ZP6K{XyMKj1X1w&^@7YgXazkL=}3#4e^*0OIezQu`Oa`k?G9EYBND|7 zP*n9YWxG}couWjOS&8PlLYs`5ULT-0B#w~Yn#B=Kd{Z;+`v&#YhvaGg{Y8*SVh(o* zw?synCHGq~jP?6H#u*Joo>PJM{4wMsr;YnFVYhn(1qm!K|yqt83P_(8TU z6mg3d?qIb0Hnx9`?|b@=$iw4fe?Lh3Ce_5!ZQiYxRRDYT$D^WeR)0Wn;*M6tW&U02 z?KVXFeWcm%gL?lKxT=xfgHHZ$7`%Xrw`s25gL*YjR%6EBhxKl&MQH7cztE)HA5_5j z+kDyj_rxN;(HAs>mP&@rN;FHu4Cv*+X)`KOu9l40ejD)<*Tk!nfwoVdDfkywtss1biC-DAK!idvU4OYU2*$r7?^X^koIgkCs9O6A6#R9 z0AFh#9KUh`AKht6P-9xMFmQS06S?S7znL9(%PH_K7N~GGMO)0me+Dc8U4ZA^RXJz7 z{BsE4@Y*T{EtnGX9C%tIF(d$<0Q4-;g%?CIQMv75^JMbXBsG8rl+aOYEpgB7v!BnV z%_Q;XQxYXpVm-0Gk&2fYcV`u0Rh3vPKo>i{38snQZWC>lgkb*b z+kt#*%`Y|B&q;DbMV__E;DpTyy(&9w;Gj^4fb%7AOQJR$uOK^cdwiLlSxDWkNos%s zdp0jw-}t?qf%NRTG=zA=CJxa}iR^j1Y|c{xco5GRtssR{LP)hStzzRSa;YugB3Y|z zK590;!p9{E)eR1$$up&EOE=yDVt@}%&Rcijqj}@ABn&LLg)u6_fK-6dbHF+#NdvQj zC)w?f{WU<-H13$a6dsbPTa?E5@pr!Xc8}Bg)Z2&fdF_uODCk-6zENcS%aJG-8u;ej zLw8N31$&Ei*XT-a$lRwca%VqvZk*nt;cv=)ok{}g&hmxM=ZyRKQ5D!ocg!{Fon8Ov z1q#RUVoh$*i2v%ni{ZuUnK@?}2fJ?{ivXcM_Te-NekN(ruKHI@a+<&KaAK+tjdvW^T`4oSyUILGt!i=&*3Kb$s-+IqIgR!8~5i1Di$cv zK}ZFXpYcWWZynlQ6(F~Ea^JFf!^O@PKX5E}MyPXJ z`3j)EsGZI#SXY4O%&2xbIwbMXK{e#;QO+el z>~l&Ub2>^`T+_VreZR34)e~?e6DoPniDaBMWob#J>KR?J{2RCGrtAAu_~32CroHKM z{1R-1Vi!0b&jUC zF40)CN(42)yyh~5JD~DoZePnPY&f)MM=sLJEdKFtgSU^9PMAeg^`#=Nujr_Vtt1Ky zr|Aawy1ug zD}!~O??`5NFbs4bSU$rB5mmyo+`yyeW`KDSD6C>R#+mV;qQ>56)bV`tmp*5CL+kzs zo;0JjDzVAgau(6LOAc2QVojG%Xreg-l>-<#S6C zQxqC6hKdZliCq$9H3a5D@|k~PP{J^j&`zQ$x!ihY_6#(&lH{ee=xKXT1{|HN>t1x* z*hYII;>!rNBgI1|pp5yLt3|w%5}|axAedsoL9}EHdYKTCv_a$VGW5A)PEUYc+r1K1 zGq8rCRE%MQGL$iIKlm;5sj#yeAkYrPJELMNA)$%Rhr~gB96{v)L)KV(H|HXNpr8em z5onvXfn`WYJXnuQ6am8@4~_9{dDdC{XyB<4euFUfI**OEe`wq@?8grL)GD$@-6}PG z6gkOeuz)0b`z~W5j6~DVo9Lz37nd>w<)W>Eg)J!RLZ#Li$FwJ6Q?(78cwCgoDkIpLZ!`hL&wOo2JCW`q`9VaOa~9^%T<`J>N5b#X|t2 zf{N7@iaMZ)w>GOv7S_(_^MX@?Lcx^8OKGMsIzcU2Wnca;Vxus%QKWCOH&f>cdWj8} zS}8f;ROM@L;=qHh8WR5(dqV!csD5H&p%{(l_a)EUSLy&)kuafXcZ27@CKpt#l{_{l zPr2%lYae^p*h9(cT;e`FCha_1bIuJPY0tRj_kuy+=f@G-2jjSM$=NGwr<`l3g3&=IK~%IX|CGJZu&u4`Efy`7kE=4&Y)(hu1}`3z5ypS5B_|?EswRjxWy&KLK+WB<_DL~xw0p5DhI|A1JD?EUajzA|X6CrR;i@a9)nA3bvRkLaL& z&Oa}zd!DqPA=K{ew$NZ-J#tEbFzGCnT?z!B3 z;^Ahhm6F*uD1R>!X^X|`+_m7qJ?fbkfvO`X^9Ft_ed!MY7`(R8XM2$W%qkZ_No;C$ zjQT?I_WN#luE6c>v&k~Bb>x5ELCcHX$6XLNl|IVnmsuaws;jTbz5^~TcWu4BQ&!;w z0PZINJRNPEH1lh626*Tzvj3pHq|X3t_fJ`o;cU|eqZ#N0$~2Y-4t6k?hiXUB%{!MD zUi{=wxF7g4x&a+hPzRgGI{@cSI&=Pk>b_iervJ#NnsTgB+Ti`+TPIq;#{mx>*eLMG zdC`5#$@|!ndL0u->6@-QeNg`5bm2V!3_)d<4K2g$E?sAZzy57^sRQX}&UXWZ<$VfS zV0X_ksTG{3CHT?PP~o^22VVut_+hBQ9+99l|A`A^_aSMu1N9u$-<;gF4Zuz2Dt!r- ziK6Pj1hA{Wq)!U3gI=BJ_hUeFelYdBgh25Gsw2k_gOyKGA$y=xYTFX`Y zXWJuq4ye0AY2knjfGHmUO3n^Y0(_PElP7?uZvmq$7*`A6ZdYykMxr0{sA&uo(fbOBGg}0 z0H@UXNCff=jX*~v>f&2__Tb5ibKOe+W6&4YjO(2hv|S-LV7;8IZRAMl*?V*ylx8IM zeFn_QOSf@Ry67i-`=JE` zX?OlQ0-mwT0b}?1`(r-}04P3q^O`!HiTcmeF zQ@DXF;=9r=S?SZ?d3AUGi8Gg}`8pQWs)=|5ILae^MtWo6iwt?v=1B@?;>ZF+DlJT5 zgbQu}-@~a0;#>oYx>bf@a#ne7?QySmfaU^!JntNZ@zv?i0=e#2ROOPaKa?Ggivzwdm`P!v0G{e#n9kV&yLl zNFES9Kw?yew&C!-iCUTk9y97L1y*vtOP1c>g(;CNU6d>CQYIS#Xtu#9$gVZX%hHT9 z=y2MWM-<@ZGiT-#ui18^(rcZ^UCN}p=o}c&O6It0&>NXcAsMy2b!})D0iVTdCRn(! zA*N^sNp*ceB}iEOkkx*r12)5QW@XPn*b4c%hKP;W;DFO@d{Mb5vU93zCD-2tfItQC zTd7*IHYZ-nq1qy6vFHXS*}qHgZ*omD+2}&zrHN5`EqLb{*Mu-~&kj?lMDV&mgt}+~ zF!u$yPeFX*!y;bTLZBL^txM+HhzAS-BlmL`1tc~Y&0iY`!0{yi+gRz&a&G_vpA`1X zNa9VB2y5gD@+cy*sXXXgS_+m|4VG0TLJiHYNTGuiQQ6u=dMq|u>tf=#`GpVvx64qx zDgL(l@{bgd_^xd759vohH~Al=W>Ngsj}dV$ozqwO_SN7Vj0douUktXjpnq1q4b9iy zR>inny94k~{?^;H=ihsun*?!WM7So^Qyv0e*3ez56%rS`F7=#WNVJ zh6@%P(k$`Dhb^)Wy7G4Sg$0Z8?KrUfwe^oz0ApVNlw86;P~b#ED${#2fi_lYi}AfM zQv>9#FO55mW*XR2D(NCQEGR-a!1PRTSYop=#)3`uv+vufuLDE>&I_aM2VW?`557D& zEJLuMi~ss zPz|r{XxwZh`*7^1)7EO`{FYlj?6vneeR!LO0Ti6j-@S z1J}DD9GM9NHS7y!QKI5O5KE~P8!(&p7_vU@s)>$Sv>F3hz9OsYHJ|{uPZS=b7F%}5 zsF+FtNU5xyVKkA14$q}(J{>XP^ph1Ck4G!;SIjMym$Ok#(_t?dkO*=1|l2(s=e*IK3s90x^Y%GGuOGJ_W)>C_F-b@SSaMSSP9zIRy+HeLtHC zGvpi#V03wqf^`?KD9(epDI_!kko>Bs#W;_tnqr(tBJd$?7_^m{) z#glHrOkEuCa%rtEmN(d>-xF#KHJV6H8`yhi)a6eBq1_{0EYXP->;;eri5ja5#z}N} z#JEmPa3xve*O2#z%6-9Mg3UznXPud{anO0{kE=F9ZECD7OnA`enHVvm;i%)cw*qjq z@3GUL2T}BzD5UIDAk(O-*6pgGW1YO;+ZvXSo z5PX8l3KUTax*RF+JKT%qDOwTh2oPry2+!Ig5N!mYryCN@1yXF-u_cB#39)Z5Aw7om z+9ZMGC@Pv5kLH;Hx)aDX8daBb0r{W*JT@td1vSwXF~iU>gL#=1qh?y-6BILRY+%DK z*+Ii>f|8?92ShWVgH4@!f$9TJX4JNH1dD?ai^e5X>&xSI5*18iU0d4~-9s@H>LRM$ z{>yiTu8F_`o(xE(=Tq3^%_IhGhGe1I%>xj#IdbOEhSiQzR<>issxJsRk_bic=s@`K zP9)`I3}H2;i$Mfj7sM@yXq!=Nd650k1>EkC%N*UdN1lH@!MLaocOoF>9Vo2bnImKIg>ZA_ND!!snrKCy_BI%*U9jsoV* zF}dfOrm)v_?eWl(F=*XTk-{vf!U;s!q!V3Y0_&{JZ;X@ZwFAhgWTx>RR zZUK+<@%wk<@gO*%`w^*TuvTF7ESYR7^$ez`h8Uew4_f?(Bn%q_dW(#rd4nuGwm{R5 z!S*&`G)A!09c$TI^mgHb0{;lk#M}x(jb?EF&LV6kwC0F8{0SSIWISfO&5huIKSWJ( zz%Nqzl0CA8jb*lM*N4;@^z*Ekv00^Efum70fb2yV4X?Vi&*zm}|FzlftXgbbT`d3G zsGCp`U3c;lDB$%&r?Ayx>5YW0$rFyX5;d@0IxC}WwHs0}CCBCBbt@9JwFrb|5u=|S zgKZnsmM|g3z}KRZvi^@3Uk^-G4ALuZFy^JSy|A8rg1(uq1%BK7-J#-KF!2;!_sAwZlMM7Rx2U>In?G)~rJ~9;7miNQ7Xo(CVq;5Q zPx!Z4bmWXHvE$$Ca_dnVvayz|wnR`>j;gj~d4o0V8v?A-@>-+Ts!odfs+8qbhH&4c zFXD}10Z$AJhx&`sAD7>G?(R z(cVJxj9Kuf>Fezm+@!xxEhns%pf0;$R5=R#$E6OK6r0K>Ed~SVM%9#`>lZ1wn*E}ZIJo$w2H?vg_N{wJut6Xvn<4}P zHgydbCMO};U~OOf@FTfs<~#q--61&L8Rnl4LiFe#U0H8XVk1k0Z^9py=R=NM)rNfdRn7-MFCgo%5OPw2# z&IOSeD9|w(g#co}eBE7oGnxKEC=|(zp^dULm$jA$ykmC%Zn!nNlNRB=tly~Y zVE%#9!GH~$fR=3R2soThcWzQTv|}5c+)tkdL|NFf@wVU(+Z$uHIJv8*@ihblfi>Q{ zUJi9#8Zt^&PuHcaTe8u=H8#HPM{kTTgI~;-KvT1qP8o6P*!eKnQ`@3SUPh{N>&A3*Q&H+GvNSy zt5eq-eX%sxos?0+Vb}pyoa&yWhF63$BO~BJJ^4q+?qb6mG+};#|3?EDt~~(H6p2l# z;ZLxv8QQ7uZ(DI3i=)O2k?V$)r*2jHSfD+`ghOcT1`1^Z^^}pNi>NIL4syrLj_d-? zEu+3{0T{n+lX`5ewFn5B=4H}C=*~`u2{P7ck0b_3zxlE&CW$U{Mw+C zPOAa3!M4J=2z{h`Xirt;=TtTMV7fG5GgE4R5wOXCWv_K7MJPL_YA6vo>AHRRw-%rZ@E}QndkR87R*?s>eaNl>4OD`^JPVO&tUko%3`Ac1# zzP*7PY!l7x{jImP3MSv)2JX|BYuiBNrMI_%`yTRl@&~BB-@ljKk3loPN67sye)uD< z@?H4wZ&VYWIQS0oHvM)!Nx+3k@=)r7@upuo$$j02y`%wf8#b{f=(eu}NjEi?jncXg zeDEAJWig`#fI*-Gc{G6fXuM$ujSEbooi#{k4-jCv^D_qfe9O@vQ+*XJl#ryjObotn zDM^iw{wo;fZ@*w>|In*Lw9Byl^0p1?ANu}>|Garmxz{E&o0{Epl?Dp#%KGmmj!FC3 z3AYH~i+15Q?q~NjX=Jypk`*;8Q0Te7?l+PFFjP{jX2t>}y}_`Rm2U+yKWLS)D(sbf z#i`zqJ|shB*&LLdHC9FTnyt*50cDRJgv*HI8{{zr$qX##nfOW&DHz9f<1`l{_ip=c zJ3GhVU|oaLGGe+@0CeCfs-$4QnHnHzuz6U8Rzm1mKF>$z!1i&00H7%-kD;Ap@tZ8N z7n2C+mY0l67fiE~pXmZ)WW}twh!u%lc#@tajL7_#c;!74JFy}Rl7uj`=*xK``SVXMdq;f=V-;+Fe@~th@~+ zxyr@Ta0=400=}`BHK;dTA5Lw=J?D8ML#sO;?2R_D6WD`V=memlMHPAp8gf3_#O_ko zd>MW^;cCUj@%YH5TFtas077FgOSw2iOMK)|;F4k=I|?$!gB1IQ9SZDZqG8TV#BaUz znJgAz!%x^|Fd8HUaoTwj2x?O$uA8SkIOHUW-Cr_;IQccF=sLUQXmmW|ag--Q?@geH zyrT!L0i(7mG2h$ECdDv2X+ULf;MGRTE<%tXv&x+KbpTA%Ly6IP~tt3JR^3)VYQQ(8koegEecE{gfpDLzYUDg z0#bpI=D`<7gW)Q`2i$WGynKAprmNeIuj?%c(3ZlKLVXy>23c(9qpT^0OC8@p1a9)_< zoG9#Cwfq3XU`4O66C%|j9#tiWB7H{4jOEn8-90l#Un1Yx+TpuJHwBY0LrBj#$B_@^ zt~f)!L45r4OaTi)hYeJcjTAB}ItHvGLTdDkfq8q86sQRTKLyr<%f(QX7U(wUq_K(a zj{8`lo>6U>VIaGryT1D?yMj&X!Qew;4xXT9syfAfNwj2y${a$w*x=mb9PZ^T5_5ev zFsC^hszc)xbsfJU5(5)P(SlK=w8B$F8~(k_81w$U@^{5-$fqfsZ1 zA2lFxeZ~;Pz4?(5@6ZPER_Q{(y&afDQBySob@_-f2qVyf0W0F}uPKvj0%gd!C1U`V zQlgni!^%c1#o*RJ1kT+eW1zxuW;PTm3SQLqnubgEoB+7U28eGmGeP8c4*ZlNjFSC3 z=oE`#%h2)@Hr}(A?UT=?Gf^9O6e65PTjefFk|f}(Da`j}q(K1r*kAyE$E0@yPzi6C zpoIk0&IaRX_)9=}dkg^75^y39>mF0mic@6Vy4d9ujj~h3Nbf+AqNm>Xj{Wv39Wo&j zy9(=@fk3*brXuVV)-hO!w%P*j=vfVI@<71@ofTQVmY4WDX5@M4C04_SV5fyAFECV{ zx3lh31%5g(T_`zVrs|qHhooWgSSmwTg~t*#e1jti2|fC$KX?cMf!L>}8zQ)r=$o10 z6+0`&92ElEdjgsmODI2{0A`p#Pr`Vr`<6g#U2cO%=njCOxJ)>SlXcsM?t?+&9Y7V) z!Q(TS|E=X*riUdFG&>7e1D225;;%6K0yUEuS49gQTMq^@C6Gf$m>yXI1-0-GMaIiZ z@r0rQ=3k7JFSbS{`o|_fzfFccKZ(1Hg^^1HS$M%}BzSag2U6meSXwWf^3XewSJ=Rj zH^2EPE;pQV6YYSmk|5=UBH#%*6jNf2B48$vP^lbdHasd`Sqq~|TSb5lQDS|X@|-nH z@g=NoyRwTy&lxDH=-DLO#LX7? zrUR!1OH2YagV+Ls9pjNFJgbL?46r$;vchXJb|CE&#YRJ6two($b9$>raXIo^>3kZ^ z%TOUH2;|?ofojCMg(gNN%-lb*3%qeuXm}CRF$soS=>T&Qa()29VcJAJ6YxLhP4V)HZKti2gr zq1YP}`R&-{anFB(s?>gi@%xI@pBxVwJ8J%F-gif?V4I5Kz}<3(n_IG+b2@0Aiw9nHa7RQtq5r}0R&VIoh@Svxgp*N4>bK)NLb6uqdfxY1bz^_G|VcJ+qL zt?j8@ojtBzh`z%63-zS9H6hA2qPCSuVdu3#YO?MZR%fFcV^2GUGf(4~{N+7O&_5dd z_S{E8>^w%tDBWLvaL@m0S1#F&X~r2}_(C(rLh)G|e8GO1(nq$Y#Cc>MRqMa$WG_d# zf#iahFT1B^GmvR4Yy4TvfNcB3WI5pF7iO<85}X@Ps{Qh$A6{a-^uqXBtGY*}_l!r+ z&r!c$et2~pVafd0`9|I@(-&J8TwHJrJ72eC;{m7khW^RN_jG;#?7CBXw%mLIDuUde zbjln-`vpGphd&d~ZNSf(rUm-y_30B6*r{u_IG-%Nc7h)7$Qp$z=&wUYwL6?{+%tIN zd6&;V`+CA1_TCPJ1H@DWE!Fb@@Vt9NB+y}oDI^ePEnJW%SKYl1q*P60p3mrGpWKm5 z3Q;IuW<^U*Qg;*Tp9Mcbey;Q5~GA1)qfEhE)I)@Wa+8fumHxcw+#qE*+6a#DVE~`4LT<^lu2r3Lt^}#RDIe$ha$xz z8wV&|nmus6+@FG>c?je(?%6JsK()pz7?u4ZFgO521q0+ta0&Vp>Fio7 zv%xmT9^&gjvA|0_4#!1Pv<4Dc;MXdB8%;iW0_tQZN{1Y1D1s=8%<;TcdUN=lQ`ASx zF;M36FOI!6;V$j5Q2x$Q-87kpgqbXzMow{u`4g3yDyEZVFcnb-6giqwRdp|#1e`BU zs#feD?pS-JL&A7O_U6^k49so)4BdyZVIv9$NaQILN8sQ{*pb|C%5MFa*bZW8EKZJTm z2~qBAU|X61Nlmr%o783qXL1ev@cBea5n6R{;rbQDE6m_z3T%5q?Q*|WSm2N%*u^y@ zHa^vXoEbo`cq8|igt&oGe-_%h7zzcSTL1#qB?STN_H zcB8`M4j|B5wT}`On}Fl40vM}U$mahr9Rf?ZVkH&q*|}u)4zU3)RIvbOW#=R=&2o`s z1}Xq6al9^jLvF9Si6nuL0V{Oajvf|KfT$vSidorjGt`q&0`rn1WeD9vbah{@tC@yp zR;;?(R@Inwl_qE65QqebLUKsAer+9gmcwt}suR|u#HVuDPB|Xv1U_o3$-3C~9keJ^<*Q*3(a`ln` zNiRZuZ4F`sS0P~X(3anq%QFpe7%(b~Yiy!`x#5_cutxxsU(jLFj41F0rC#urC zg8&1y7)rR#G#&`BPzqgMRDy8xd-Tn40K{z!z=`8F1~SOsA5uO{4Sf-PNd^1t<_Avv zNWso z-*^7}k?-_Jeu@u2{>OLicg3}QQd^}fv=3O+JnP%TzX{ce%4s&oUhZ$?m3vP3=lmgH zXgM>;yL;rG3@6L4MOR%>U7H<+QeCL9a{6vkU*}ONkxC`<5|o&%v+{GALCE*O((elr zaCLB2tYCM!X9PAA&h(g$>zDs+z^^yOOqj_BpLAwaz$bt&epRMs$$zG77lcate#i#n z^xgl?A}SjIxm$8XCntC_DV{MlSb@ge6_|vpvv61HiC^iMh+8nU zD3a@KPJ!1O?#<$VMtbhb9{()g4^UK*Bx|8!l*TaUz`%jxqB07Wgt(BL7lh0M$+B!0@K!*Y9t9r<{8Zzy zfBBQ(iR1!fDzL%R7fGLhC`fw#(1JftL*x#^J(5}Ld6wvYs*~^%06$K~!$J})SxFET zJJx*LGb!%GX>8~+*?0`k5}QuQC`!vcpeulJJo<*z#d_{9v_l*3Q1HGu{UXBv+?i>XxEzW?C6BHLC(LOM|*DSAiS&q3zn2JC(t%l(Z5A_k^#TM+1GjH&8-7en# z#9xqM?fYT@Y#RzJX)nP%wjcPo9pgGa+=UgxaU8sUX2v_>RUqA41$*~A z=b^&DK_}v9{gb-&VE7sEoNER+cVrIY73h$Bu55%B*<}CxA2Tn>QN+s8x8aB*(N<(? zGm%}jdVbO{<{3aoteH62<^bt{uOWRJ7xjz+aLAGYKE`%lXAm2)sXJ*8>1+VCVtj)I z4~NDS7E5emXC+`On&x%?`!FE@5Jh{Emd6YYpuwppL(ptRkzfV^(6lqiXu;)BW&o!K znh!Sx2w{QZ69_u$;C@4>ABunu!C(jk`X+E4&x{SvBJ>j}O?>A2$&Pcs5pOfk(Sy52 z*BAk&k0pS(n-r};+$imM{ZC141+>~SWIyjD0N6Y9&lJ) zSti0xs45z(1%XP;T6t#SNi5(UI@9wIY7{(cQLy4RAQ!3&2G~}EXj$pM^^5z+{185h zxpYk21HU3yE-^Ve%Qj?^%`DrN+t7dEOWbk*jCnLFU62Gjwv!pmV%l5K4GE?b@>=6( z{6!q@U2qp6Z&0wt?A`)+rWRnt^a@NDGr0NZZ;=U*3-wgx+E`8aSyU2E!1YmCEI|>n z5CuSS@IbgLs>#>=XUsv3ip6@Os8zPSWQRM0WSX6BS=|dFuE=VNX$a!>PV`^TicOCJ zy~HnRx=)$GXTI~3o=HN}hY1OiUkrSgP}HXe;s_?Z?P*dsB5DIwffp{LS%7+e0t~cd z1c(D6MCNIf4{FC&U?ZU!8#JO@SOftfOjzhbH@`iL-hea0z|dF01P&0+Byn%Q z?}yRGsBPcyQFV8^p*NjoDU?y~;CCVJgoOrhUu=fxKMHs{f;XsMfNY*gJ};iY-c=bl z3Nu;|K*|-YPr7t*it8!>bEpSFf}0oq(wj^1Ibj2=4XnKVaDJ%EqPq?r1pQc#_Uvu~ z);>OlUpgugVuNz64z%H`Idocqo(bEO3dB;-F_YNBctrb%gR`+pc7Z#o^UcGz{s4U+ zqZ7*qngQUfg|$R6MSMTBrWo#!#ma`K;^-qB(?Dpou`^t1Vy3`0AgRJL#EA*=te2*k zf&e#Wck6j02H2*XN4GCPBn%c3{P#y+4=zlUFxb}-V5wYm+>tG3W~x2zTymnI ztcH_Mj*mKXrweQ_Hv!E}cGWrN?v>?ae6}%IY+PxG+6O8?z1TAdVkB#fPWsU#7g1cK zNy7SUF{mfM&Vq;R$EWXdX%UMdn*ud~D-aD87~Q&;7Gd1kZs3=bt^D%XgKm5!z*w>n zN|@n)05NX9<|0h z*E2$h5&9eX;Fv;8zn^+lw{G3Kb?>cPx7OeIu9-iy-2mhl%<=6zY8-ww5 z^Sk}cJMYHUwJuzL*T&1u*z|Y}L|b=gPgKd>{&VN_4t;!25q}_Wr$5cUO|)#bpf<*_ zzqI7isno_+PhViM&W-C^aJ_PfM)x4j75d63AzTbw>NF004b2Mg>l1DXD1C@^}Gg1Y(!#clf#j^`7ab}z=f;UlbUd z_OfENV$&jhvTtfn5!b;SzGf5ZT7q0&fm*(iwhYc(QP>q>4&1n>Xj_lniXrX3&PJO) zW9-bjdUa;2-S-)DBjj+Pj#p#8KJ%*{w!5pG4Qz}i??##-J#s~T#(bcPZE^MCuix@q z;DkOmd&E4OPQX~8yT zLiGPuW5RswcZ+5i>Oa(ITstALJ9%|q%5Gq*OYSEpuWw*YOsCC_mlFj7sO`*MoW&ll z(3@(H3cR<`C3qx0dI1||t5D`6;f}kKkuc~@wTFq$^P_2YRj))FW}=x6nT#{bAya7vjAb?kz#a*|A_XY@7s%RyWQNiqpd-@-w%xxou{HHxxwCGs07P zpBctjR*R#Vx@_C+eYP!@<|3>2fxi(aRW)71N_d;iZJZgXn#x^Ya@UAFq6&Z3b_$at zW}K-H`ppq^35(%Ge=g(hb&O!Fv?D+(E|pie%ztVaqtgsF&(ZElS1bS=Y(LA!XRy~u zp4o40I&K>CrM^M8DLZo65-Z)z6$~ou4I($0A)=RT=h?; zBN2$=AL0vpq`dkK8!}vpK%1co5CtHRgDtYeE@*Z$=jt?bt3NHlXrh$;^qzl>xo*PS z&S_rW4$fIahO6y>{=r+?>bY@Ow*8(rcYvq(?kGy1H+LI%+T4bXbf!j7UbAs>voYb- zzy8*lfQe8O9#{4MItm)c%7YDTbIjb|kXMe1M_DXZ3(pmEC>!oo8KSV-y75G5y}<3( zpWWalxRdUfYN#E=m+WaY+tV@--fd*_{V0ui)>v16h`rRVdUt0d)zm+OOJB)-{C~b> zrUj3T5)`d8-W|wfZt#gy;lY|exkC9fsn9;hQYnQW6*BHFqHVG`W2^q~2)m?hT2(YD z&^D**X;^b>-rj-8A>EsC5z8%kD;mE@T1)Kn#^wWBB(A3FTPn})cf_A?*H5Qm;MRU~|- zFTQ!(gLK61=o;WqOyUQz!`W*+_BvoF;{*+h5zfKW3)$LFaMH=kmfmbzZ^&Ln%y8lT z>&Zb_o+O;~_KVBt_POfz=Tmm_QB*qhIsZw{v-3GQDXR{HULpmr4zS53ld1UfW!5{) zb5+0Z@CEN;xV$=L=trh~w*gx;0O{2wS`ph~HrmFDd z<1h=9gCW#s)Qp{`u%SqfQH$Ww3`EEP^J z;(03C69yNB+0ce@Uc<97;sK$|y& zNj?ECr4nk%(jfkv*+nSUj=bdtEYZ16NF~{gyhh(Ys=t6mz5FeBdqfWjFNo<>Nrn8n zK$=Jcsw`wlPipb@0Jf}NL(L9`vaAo$|7bapzxGWv$U@JQ!!+c1Uf1?T4vPzJ@4s0T8_U2_*{-+vNGo1 zJF;wLsW$;TRb0NoF$Mw0DFcKxUBbLFAcXW~q#P|#${@*T{iL&A^pPJsRYV;(|Bn;_ zr(HC_cupcMWF}{q^9ci8NSmgZC(?1&6mW-y+xO?;{ITd=%+Xlga1Uj+kwaHotV4yimv5$PNa%Dr*VzS02bRWXxB1Ak4U1ggh1^%I<_+ORC7k zo29H^W)ESauYjC!Qm=C8mpfRz{FOmw85GDfFe6AahY>MmAG54Q#g_7q0NyRd!yYT< zL`jKE??$f3T*(>5Eawj5o(HOu+(lnI#{>sMhazJ)Fi0aTIj{)gmTP>@asYolPZ#o- zi^ZdtaG#Wfm0V_Sw@J}l7~ZpFP_Rr7__oK5l5t~jhxijZoL*+d+=y2K)9JuVFMhaC z+fed}+Y+f@$Z1At#p$ScCEw@SPnXIzmO*EZZ767c(!M-^%Z1WJDs{?v791zT5Ce2i zILOpS(~x|K+CB^nAQX>vCPgB_n#u})TgW1iZwjLg|A|eFTFu;=_UC_E_t&zv;(LiT z8CfTG*$8J!?KH<08V+SNyGldjHEL$kh8t+Q3q*Kpv9_CJ-I_?nJyk+S>v~>o!IaLi zcBQ=aY-P}t+&kF$;HJZx=o$MLZ_*qB2AUF&tMYBoA_XyPD# zOJw#r*c@0jJYcC!20)c?n*(eS-1?*yfr+FmAT5q$V1VxRG>Z=mxCU;@fhdO#|C(3G zNzb@3oj@h>9XOqphDwqOSc0RcPz}_q5M&nS6f-DdH!DJWJOjl-KrtwdT`P;QWYR-v zt|B#OBh#p>zkr>dH5iyPVlLE@svuB?f6@Y|wZab(LuDnLk*8TxT{Onaa+Xv};#oEZ zD{{+uAE@^7*h}B>i!0P_4Yk*$PKJpBRXb%(DNw=1IZ7m_pF(pSfzl|k!A=5<11%U76%A+DdAXinWPefjA z3wa^t3N2zcM9F(c`K^Ir`zRa+@&FTHGL2cXmiRedg7<`?y&+=(a_nDfGQ1Fjvw=~+*t`kJ(9U;J4?XX`66&m8umfB;N(7Pg0$L`K3@z_G(#y#tX0|2SP%MA=o^FNG{ zpuo~>Us_FB8h}H@{Jq;9*6LI`-mEbO$1I@RrVZG*#3mH%VF>?(Y#y;&_#i>e?x5hQ z%D86P$*9m*p=O}aV6U>Z<{80M%pN9cGGRvP(qx{yUR9RE^pG=PpDZ;S;YAPs7$Kk_ zQNW3WhANPxi1n6!iTOu(YrYU@rGMnDCUUmC?7{9Q_ZA?iBO6~#TYO&68yH0QdTq(3 z>YA@a%|$O^+CIifRn)9PyXX^f zzL5P9HYLeNhat@|SeQ1{oMnxRYW+XrGJ11(bP9Hwyo$64o`p|b87q6WR>?1Xo zfL!CZl6!9?^vyAcX-Wc*0bqOiJcYrgX`AJ5ok@rB^q(0GY2PQo%@(u z*2RY73=AmW_9Vx&F#J2imq*xQaA+?vD;c_Mu*jT)7jr{*1_W4Ggf2W(I#666g+r6$ zPhB%>OE2G}Is$_{J@P#MfKBozn1^Jeu-Qh5oS4Pu8tK_c21#5=5i@Tz$2K~m& z73IDj!Z~op8_&OR`Qh8%8GE_b*u+F2+tJc;6d01g(!X#>}N7oG=&6Kj;US z+4;V{Z~8f+0S<$JqsT-}?uG7GV2n|K?hy=;gjR z*I&w&M^sSz1j!ojjy!)heOtj@8D1|w`95HIjewaMK@;R4q{ zB2398mk6n>PS6r}p3z*%k!6pUrqi+{H_TXMQA1ZB|Mq$HvX^5$!@{oWH{2T7){VE~ zL=0dpKS#?V_4M;2|DYt|FfkystU%_8+u9>e?rdsc>5=6}GUo{rAt)4SW8dgL{}A4Ory&#(TR&%|Zw_5s+_CkNhE zzjBfw2>rq%>!TY4x>~?;o^{lgAW~m^zP_?DG67?U>Ch>xA`+(}Yqv-Nbr*=MICrsZ z0}}$e!m|cE8Q_p;nQ$RJ&EzFt!Ff!@8zW>2hAGZ>+$W|zg8!AO_k4tc@DT4W6FH;? zk~RcsbW1sBr;BMn6bXy1=i|*LRD4e{^&U7L!3mO)DH%z4PP1kUP=tJDM*w(Xp_gUd zww6B?rxH4fs2FM$^BC+FR$YVj&<3@GqN)lXd-CD#v=1qI^*X`y;m5uUL){z&HW~*l zx5i^pe-1MmTVLqw0z-9wFkQT5K*nsCN`H0e0$3}}q~MHS;nd$W-d0-+l|Cd?}aKYhJE?0~9);>Ni0MUanaM zn$6!*^)61>?g>huVSgX7;`b3JCm+hb1hxt8()QQHSM9|X(mM8B^>v?>Tc&>I- zt>IDKO%+m&vKdxEQ67OpRd0X6wGb9(Plq`9-_oizXba!;i=oU$%jDSox) zdRBY3UG>?$sR=P5|Bt6hu`#?m7-$Sfj``38aHYffoh2FAMy*HU8D-_FQUr{6%&fER zN6~pCo)BPyaI-)2USvd;j?fG|KOW^GpU#$K6)0N@ z`ciOz-%hsev%>$0U}`S1X|uu0!Uxjrx{5ouIHs|Jl&wSUEG22?_?<&-%HCwFQ(eQc z*et3TkTWgY26G6K&)4o32jk2qd{Rmo{(QvUO^5gYRYip3Wl8ft^?S)!Ef_BPH`q>p zpNBrtvGH)56;W74zrk4&ff&!|DHgXR zii6Ns&c_^b0_L_~TjRV$^nDBVSc-&4xjY|J^z3HDz3p{7`0HJ zQh^vM&<6rEMGmgd^DkcCwoY=ZkU3i&Q0bU^+5`7{DeoCJ=?3t2!(uVzbNKb6L=dqe(|4p_8iZ zdxB87eia@K0dvJR2YgPITF2B#dE!XPrfEO}@T-4+McIq=c@_%>YJCty7=gs|n}CGw zU~xZS5LlG`>cxjx8{FxOn=(x>v}Y|MbV!vJ=d_TzVgOIW#KG*5c#%`NKQvggy{wWuVRh?$76QFrmLw61a&sYwDz@}8p{Ri#!R5gHdphO8B;VWWt z^9_*(yeU>1Q)=}(xH%JB_U$Y!wuzNj=mEfRaBHpHDTN7!7LeninTpvFHf>bzlMEW- zx+dPlHZv`*#tfNqDZjpQ_#>Z@9y0mXN)vF_8y#a)eG5_?dS8I@jq224QHvQI(l6M6 zz#Ogxhu}i#6oe#>KZLJ>@l=uqc<>t9DlbU{Em7%o(18F6V(3fFYW^D?-be}36grmb zEyg>#i~iEI6mJV~i7f|e6@-%+5w7Auny9*zB}pa}#uWn%MLXwVaZ$0U{^BG%5ySvg z?eF2d8B|ye3OE{04W|JGLqk)CY=oZbD$w*L?HydcSha&V5v#8NP4NB zXG_d^3fUyGHo$jx#xle@em|ziyy{R4!VmUKAyQ~{Z3N)P%to*ep$&#I?gv%PMj4(& zS;Yx|!%$Ufc_tS47i;y0uaDqu6T1tYQUKFqf-e>J11WR9qxx}p-5jY|-&UN|KS<B4@O zF2tuDel9#bu3?SQ>Jmq1E);yg;w(TckX(204>E@34M}X>zIcdh2#Sf$Nt}T;GOiVD zgbHH#{=?saGGeo_Q8Pp^;YGb#%nW2P=)oF3qYACE1 z3))~<7$fh!{uQ3oE$ z)RSn#IIh6j9L6w1816*LRlb$)s|p5TEl2VJ1?Wx?t@0_S=jCiDq7|O&>frU@Np^aX zUrOR%oR4A*sogQeh-G%jMi^cZSu3Q0QbU#cLW_i(QBT|{bw3u8VAu|zKhU)B<+sX)B3ubvrOIAS7vY>sW3K}B>kAkVilnl>xhsAGQ3+Jt- zVd^jty)7w-!QUK^^6K{gcCHLqXzH3YN{Sm??cw&7i`n;u0Sh+OFKg&|$Pud4bTc4Q zBc^4lg$=EZP^(B`)?k4@rBq4SjHQ3rDLIf=IPKQH{~N!s_EYHr{i~W@B?La+TB zHqYR-GP2b#^p$S1x^tN~XV4F2J|+6Fs5uC;xnG$AIW!k?`kX+-6_OTDEJa^gv2b2L+4t-YHz zYE#(YttT3fKb)T>a@4pky9KOfdN_c>Sa5I$*F}T}c6UYtJ$fL5{~JiaRHxY~^3HGT ztxuY%JEQix5@q|wElkY8-KPTN4)(IW9nKI!hg0IGB)gEj@_v73_0oTfMJUh7+Fgqf zJLfSD;m%3i1I!`&aWiiBm)-l){#1Z%)%BPXTM zV^=wvIFF+iSzvd#qlB()26I*37#+q~c~(q^SMdQ7^9ahc(H^rMc7+O_rWXK+-{zzy z|3P+{r4&N|&0c3Z{5gM{bJgL$`c88K6&DQ?)8VDXmVf8KH;T`+H{)i!Xbj4m`G@e_ zYaZB_C%_>))HxJ~*oHXhq9b2;Wwfe@O<HKF8DH?c2_o7zgSbHZaJ}KgK&)rNH}G$%!Sie2r!}aHX#mrrWqb!nxEBs)}c2clg*7 zS%*aU@b04;x-S*Cbf-%Dldv|{UL88go{M?#{-2L;*pQ4wn1cKgW}GH!JWknIfO^=! zenSnG7~d#xZ3w3B>}$9d3&xg|A%c&kKn2^$kVgOnQLL-2n@o}eD&}dyX|ImuHOt+3VLUR6O@a`;bwFMj8}6}@=_3an4JG}{vy zwu)l|pr3^+baQh{uKdxyz6>ZKb3a+A8=ZHJ0$J*7V z0VxtJKy{Qw-N(`(4$y@vNGg6b%3?7vpN1;g1LfUOJ-1%Yc~QTcf`?u@FDm8@(PPI9 zHwI&$9F?sKclm7x6AA%AT+gq&kafnlC1z%>OIes;s$G6fi+Tt1;KwC=5e5-BVPy`C z0EQSu!fHAnvHV$`WO~SKKelrCFQ;NyD-64U6|BhErYO$QWitU&eF+O9PhikAAE!EI zX(ct+XrvIe0f-CNvN z+<{t*!7)$G-DV?=gw+;PQ8gD=A<9gvq4Bov z-cfQBB4l)(Me6v?G7HNpQ>V@!Or-KciwQ?TrgoT0jbbT~Xlvs0-;S~HWEK#KBU+J( z8K@tB+OfMSbt~4L$hXbXB^NZxyS$jgd#qaPUuJ_QYo->V!BbO#1O25T7y~vY>vlrp z1#0%U(gosloLN|=J^Y1NGu=Iji4oh2FHzn~>(|i{95H0#ugDpblN!UJ3SZoG?!B0( z5S+)A=}*~#iAS)456{9?Z^^|s4J;UNa3)^Q;0VwCWr!c!4!vPg zr81+Bc+lANlBhEXtO6b)scd4huOIdFbk&-P(lez4b9KOJ1>pxSLNH- zpwAd!H2B-bwY7JY8hF|cW5*=Mh-SMO9Eb7Xo54x+s}S9xdO0*_l&S=1_Ul;|pQ!l* z5r47k7;GyZ?eSTno({H!UgWi5Hz@656nOmR^JlSIa99I_ZEcz5;C!akZrRNV+kVxl zdsUQiB3mNdBZX3lf!~X+SVe>3%KF=p{1Fxz+);ptsdrwvg=KIn)&<6EQe5wcm95)i z`+)dxR+GtE9`nH}jshnH+Z@&gb)8pk|ux-RL_%p@eBmh#BFlVdOrXg1c5wFu`O&Ixvu%d#Q zbkLq6vRU#ZBm6U^MG3)1ZNV$Hoo*G6pz z6M7neMkWx0hq2~#3KS32>pWUw){Kf~R<3H4na6?{Y6(G-G%uuBixmQDO3-j*Ie9R^ z^g}E|+8ypJ-GLGT>0OtsV#Z#` zDJ`(5QyD3ShJtH60smY9Ntza~WO*E)vS)2dWsI(r>4UJ{hp!nbB+)NW&2Z2KQU<15S!}Ih0;3UGcM3KI4k51DQl{f+FMa$g*P^tfW`gGAbRboO z3rtypoT&_cga-%#iZj3c$Rz^5yJ&q+3%Ev3p;-bs-(f$qpqxB@u91?idjc+AdW@CC!s=k ziEzA?T1!pm?1watq1&C~w18hKc7Fh4OvhjI~lSkU0 zpJD-rbZg+)Ht3q zmVs}y?W7MK`r4+o-WtdB8^Fd=KN_W8U>FW2EqBV^-{DbqSE*qpM#NLv<0jFuc$nbTC{F3=a;`5?#l1ufqYJbUx4>OH?2-Qa!VauloT7wul}H~f7!*1Rva zXW5U=MpnufivqicRay*J6}RUod!6CHYR-0c#g@XDHE8~;bH-~PP=${~24ah@F?i`< zjOo3cEaKI|Q6?SiAxx7q#bzB7j>A{Q)?JNk5B$i~bn&UN_HdOGf!lZZ#Zimfz_9z- z&fZcHzk^X6fg0XQ+(^oYai#S{pA?Hii*S540+%;NDhdMZ9stAsQG<~sTkjCh6><7d zDhWBSfgbr(h1 z!9|0yO+7OB(OXsBa&j@Y5L+B;C(_zH=7&ml!GMCG8t%;2&~ixQlV8uRaR|{=!1*F( zMJhiLq%cQA7etj2qE#11!{9!q6XYBWAec`ghKoa+yVQ`ANm4F_1!lj}6_VtJI#O&- zV)vs;VsU`f`FE{JiYwFlhLVSRfFBI*AsPsFV*3%8KNwYlU2V zYTn)z@2Q@qg?aY{As#*Ec3TZjQL$tx@ZV|+?S zfU7h|XYH&}a+_umgb4jh>>%O=;)?wQ{C0gkc%6WS5`{4ZT_*7DTp$i>)e}GI5}}PX zgsJfW#N5Yz#+=26W{RU6(>8N=;LXg<`YcbO2&K&uhNTLJm56QvDJ#~t2?OrS3Ytkp zgSdnX7!&;l;XqY785epgt;fd~%ZfC*O-r$`qy_ik_np@n7gGmo>^QchIWB2#oFl%W z!YI)ZrzI27?!BN9{R2`B;YE+R*hUS=x4SmVH}Z9h>nL zP>z3o@+$|R9RBpLAwyuDv-C0>rZIrz(U$PMWhTVjv0Y=LaHd#dkxXJ0$xI`|JY=N= z&6*)a{IN;oHpCo~$1@h$6UpFlSSKeHsf8OBK6t3R@0h2vfT8n`^i{fFW}lzgAG}zm z)3|5QX>Kj7G+T6`4Z%)m$icHSWjX#M&K0V~VU`#z1`Qb_LRzHR2!%sPjp02+gd)g~ zMVC;H6qREH99GS?=t|Ko%N7%0 zXTp4#l`BuRN}xoZQwM6rHZDZt$ZQ?TfBN^&iD<5@#v;#yD%n{8@Y>?fqL~GtY$`pH zxR#w7bRJ|t5>%l$AnZZ|fTqkeh)BpV(^@z)AG92iDujef05XmCY z6`fSmKjRfq@KHHsTZdqZYDx(mzFRsCB?n^@ZIcQI=^H^8h-2kY7uG;dm^xSt(i4+9 zH3Q%Og%BM_;44g|)akY&U}hrD@F35{0qRIX8zf1|l0vzXJs=qfDCr4tq2y~;FYuN& z`Rdi5I|ofjjwS^b&1W>+%BN6NoYQdjtYz7gg&Jdz%1I)LB$Sp2SBI|ATxB?c4)FuX zh@T5>pZ@u`N_On`G9KkJOPG0By!Kq$%S&-+5hnvlV)bLyi)96uDkPcgP4>scZnq4f zOm)Y*-xdg%3*-mz@&)&_Tb>@9m}{j>DLBay2FoRbDWgOfzHBxMVjuv?V>Wg}s(JWd zpW6&6N34Tcd@-h68GBSg^*YUJJGKrfQV7*#d%5XegnhmdV*x+>l}-nO*m+{y?F5W6 z`s9@^WcCwl)KO0sDfBL!EB3f<3n58C*20J6 z!5)?_7JB4Y3VfwK6-Qpk$^mZCw{)J81Ki4M(e?$+@&I`kDiJb(6paea zmpDk~YuzKg#KIvmYbMHwT*G$=D%}!~`xhm_moGz#2a(XCwt`o=sUG^tKM^cTvSNIK zQwZurQ4)ao%M2|Kj!Id_L(>8<$p||lKVlZ^U&+K&V!vi)G%|o< zBqAVcI(S5x?pAoDfbNCicO{>(?Y|PD3r=6SP z1DuLV`KN#Pd;|Q{b0y!v|AvVqgbt6U-Yt@AHpgJ6Sud8hV-uX+Vxj?0-9~^C?B^)= zSdoNgIhSeJ&liSqt?K(|RL$Xe@nAKrulN7)ws`bWx<$Mf_(7e_{>R=9h7k%HqgLLs z%LWu@Z1a_>LGlro2((VkLcU0+2(%pFAO%)X>`~oCN6-Fefv)c}Wy@V4Bj62Adl{yL=>II5hi)kWwp}6~U6^HI680_t=rOP4e z3Vr>aQG&{mD?&?`uhHY5tMN7K%ssvLGXXBZlNUgRKmklrhYX?2so@n&$Q6x{w|p(io;VM<0ym-d zK$D&h=?Dsu5WGI+k##1_{;b|?)ytoT-sB-4iVkEo+8&)LVX7_1 zf&xkdOn0%h+<{D={*V(^K>+$wxO($c-F^5E1g+$ic43JS@k@*bk|35*15TG}p!5a6 z=!#?Dx?DCf0myz8X`K9I)o`IY22Xvvhn-8K^MC&$CUUq7_(Nx=Z7D64O#EaZ%A|E{ z$}mlSnjvmwb21@O=Dx0m2t%G~O z5J*UHa#F?;=q6#60wySma&<~?^*r}~vA<_bl2&AIv(5rC=_0|{Yf`s#ngS=T$aWQS zVC?Ts5A4c-b(xse^46N1u1EuBzY(8DaVXy^PIJv?i05(0ANulUL4)jakiY>pJxJSH!u$D+DZ}`>-UGSlT z6D;Pbr1Tvc)%-(Uk$ds^N&jXN%Q3m$Mp$lz_OUcmm_`hmd%hwt_&N(hfA-!vDJWC-7NhFn6V}1zC=wkvGN~ zkW*J{q1;y?MXPJQMWKQ(6F8%+4ErGS>{v2rdnz2|fnLl^TM`Rx+Pt2uKlsE!~J2NXvt z%`y|(>kqzsOLp zpA=Vo@yqAKyQHLISn6G&qMC?jq7$J^!&k&K#GC38>JXDeP-8AW$xj{&Rpro!zrBe3 zY(;7D<}`k%L#2M{Hy1x#rqU+6<+0>=W{DWc^LLG$Ss6!v{YH*HCzB7;$C48DQiA=- zXT3RavceJAmQWB*zMLhYo4+pDA_Hm3mk|A#Rrzx3{5REtSGKV)trjedwlkc9Sslya z5c<@LqX*2wH5~4A(r=zGlp#q7;q+5Qs{iC==PZ`6l;*Mc?!>=U#Bg=dUm)NgmC_^E zY}`F^eX&A+`Aoh@DdiJmT-m?0G%7yUmPtvnH~mw5k! zLH`mJpXkw>fSm|K$G-oO!B{4%pQ7L`;{B(ju^ z(w~4au}__`P`jk4Jbxj(P<~ho|G{nGE8`2-3U9;t?Tf##X7y?Lz&%<%yM-)y0?5)7 zbvjSqFOwNt^EK2hPfzvqWBl)E`mvyOTH*PlA(!5Q413i?k}&FfBDnYH~yB^>pB zzFa%%?hG$~V68k=INt>9O^hvpf!7^LOXPpuN6SrP%W5!xUAg`CPoDp}EjyK$Z)lXB zN<&^Z?{fF`>sEFuF9GcA+tAO@TE4XIuxOw^TZO-ALO+oS{Z#1eb@O(4z_G3ful?lY z1hT)Gd+nE}`{X3X?a2WJ0F^@@tDi0$ul?>MAbagcuYM9QEKslkcn2=t&{U^>nvw?fG zq&)xlZzanmSg7JZetdaYfRwTSVO6 zv!wUar+#js^fTMWxuocg$NSmaIT|1Oo$8xj z=|}m;FX@%u)r?c&KxdjtFD|cRbaLigV4+EGJd^qYV6RMa>4~v_Lg(hEUpgC}j3+@E zv3mmOUw)#SV{!Veo*;kswOKM3XKei1`(OR$Oq^==e!44vE`s*zl27t(!THFli(1_f zO$*;83r{GXPW*=7d>?X1a~Y9!^ySv47>47*{*h=A2igz?SESyow0YE@f!sv3Zn z zO*W0aT*5~LHmq_cWh+X$r z|2?NhR&o{=#z_zhh4PcJbzN~2Mq>s5SERdtP;tUC$pU6mgM-hu~=wDYM*S#!*-Gdt>w)VFT81rSVYjt{k{P?M;Gw3 U3D~L0rN_!9Pds$! 6502, "01" => 65C02, "10" => 65C816 + Res_n : in std_logic; + Enable : in std_logic; + Clk : in std_logic; + Rdy : in std_logic; + Abort_n : in std_logic; + IRQ_n : in std_logic; + NMI_n : in std_logic; + SO_n : in std_logic; + R_W_n : out std_logic; + Sync : out std_logic; + EF : out std_logic; + MF : out std_logic; + XF : out std_logic; + ML_n : out std_logic; + VP_n : out std_logic; + VDA : out std_logic; + VPA : out std_logic; + A : out std_logic_vector(23 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T65; + +architecture rtl of T65 is + + -- Registers + signal ABC, X, Y, D : std_logic_vector(15 downto 0); + signal P, AD, DL : std_logic_vector(7 downto 0) := x"00"; + signal BAH : std_logic_vector(7 downto 0); + signal BAL : std_logic_vector(8 downto 0); + signal PBR : std_logic_vector(7 downto 0); + signal DBR : std_logic_vector(7 downto 0); + signal PC : unsigned(15 downto 0); + signal S : unsigned(15 downto 0); + signal EF_i : std_logic; + signal MF_i : std_logic; + signal XF_i : std_logic; + + signal IR : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + + signal Mode_r : std_logic_vector(1 downto 0); + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Write_Data_r : std_logic_vector(2 downto 0); + signal Set_Addr_To_r : std_logic_vector(1 downto 0); + signal PCAdder : unsigned(8 downto 0); + + signal RstCycle : std_logic; + signal IRQCycle : std_logic; + signal NMICycle : std_logic; + + signal B_o : std_logic; + signal SO_n_o : std_logic; + signal IRQ_n_o : std_logic; + signal NMI_n_o : std_logic; + signal NMIAct : std_logic; + + signal Break : std_logic; + + -- ALU signals + signal BusA : std_logic_vector(7 downto 0); + signal BusA_r : std_logic_vector(7 downto 0); + signal BusB : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal P_Out : std_logic_vector(7 downto 0); + + -- Micro code outputs + signal LCycle : std_logic_vector(2 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(2 downto 0); + signal Set_Addr_To : std_logic_vector(1 downto 0); + signal Write_Data : std_logic_vector(2 downto 0); + signal Jump : std_logic_vector(1 downto 0); + signal BAAdd : std_logic_vector(1 downto 0); + signal BreakAtNA : std_logic; + signal ADAdd : std_logic; + signal AddY : std_logic; + signal PCAdd : std_logic; + signal Inc_S : std_logic; + signal Dec_S : std_logic; + signal LDA : std_logic; + signal LDP : std_logic; + signal LDX : std_logic; + signal LDY : std_logic; + signal LDS : std_logic; + signal LDDI : std_logic; + signal LDALU : std_logic; + signal LDAD : std_logic; + signal LDBAL : std_logic; + signal LDBAH : std_logic; + signal SaveP : std_logic; + signal Write : std_logic; + + signal really_rdy : std_logic; + signal R_W_n_i : std_logic; + +begin + -- ehenciak : gate Rdy with read/write to make an "OK, it's + -- really OK to stop the processor now if Rdy is + -- deasserted" signal + really_rdy <= Rdy or not(R_W_n_i); + + -- ehenciak : Drive R_W_n_i off chip. + R_W_n <= R_W_n_i; + + Sync <= '1' when MCycle = "000" else '0'; + EF <= EF_i; + MF <= MF_i; + XF <= XF_i; + ML_n <= '0' when IR(7 downto 6) /= "10" and IR(2 downto 1) = "11" and MCycle(2 downto 1) /= "00" else '1'; + VP_n <= '0' when IRQCycle = '1' and (MCycle = "101" or MCycle = "110") else '1'; + VDA <= '1' when Set_Addr_To_r /= "00" else '0'; -- Incorrect !!!!!!!!!!!! + VPA <= '1' when Jump(1) = '0' else '0'; -- Incorrect !!!!!!!!!!!! + + mcode : T65_MCode + port map( + Mode => Mode_r, + IR => IR, + MCycle => MCycle, + P => P, + LCycle => LCycle, + ALU_Op => ALU_Op, + Set_BusA_To => Set_BusA_To, + Set_Addr_To => Set_Addr_To, + Write_Data => Write_Data, + Jump => Jump, + BAAdd => BAAdd, + BreakAtNA => BreakAtNA, + ADAdd => ADAdd, + AddY => AddY, + PCAdd => PCAdd, + Inc_S => Inc_S, + Dec_S => Dec_S, + LDA => LDA, + LDP => LDP, + LDX => LDX, + LDY => LDY, + LDS => LDS, + LDDI => LDDI, + LDALU => LDALU, + LDAD => LDAD, + LDBAL => LDBAL, + LDBAH => LDBAH, + SaveP => SaveP, + Write => Write + ); + + alu : T65_ALU + port map( + Mode => Mode_r, + Op => ALU_Op_r, + BusA => BusA_r, + BusB => BusB, + P_In => P, + P_Out => P_Out, + Q => ALU_Q + ); + + process (Res_n, Clk) + begin + if Res_n = '0' then + PC <= (others => '0'); -- Program Counter + IR <= "00000000"; + S <= (others => '0'); -- Dummy !!!!!!!!!!!!!!!!!!!!! + D <= (others => '0'); + PBR <= (others => '0'); + DBR <= (others => '0'); + + Mode_r <= (others => '0'); + ALU_Op_r <= "1100"; + Write_Data_r <= "000"; + Set_Addr_To_r <= "00"; + + R_W_n_i <= '1'; + EF_i <= '1'; + MF_i <= '1'; + XF_i <= '1'; + + elsif Clk'event and Clk = '1' then + if (Enable = '1') then + if (really_rdy = '1') then + R_W_n_i <= not Write or RstCycle; + + D <= (others => '1'); -- Dummy + PBR <= (others => '1'); -- Dummy + DBR <= (others => '1'); -- Dummy + EF_i <= '0'; -- Dummy + MF_i <= '0'; -- Dummy + XF_i <= '0'; -- Dummy + + if MCycle = "000" then + Mode_r <= Mode; + + if IRQCycle = '0' and NMICycle = '0' then + PC <= PC + 1; + end if; + + if IRQCycle = '1' or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DI; + end if; + end if; + + ALU_Op_r <= ALU_Op; + Write_Data_r <= Write_Data; + if Break = '1' then + Set_Addr_To_r <= "00"; + else + Set_Addr_To_r <= Set_Addr_To; + end if; + + if Inc_S = '1' then + S <= S + 1; + end if; + if Dec_S = '1' and RstCycle = '0' then + S <= S - 1; + end if; + if LDS = '1' then + S(7 downto 0) <= unsigned(ALU_Q); + end if; + + if IR = "00000000" and MCycle = "001" and IRQCycle = '0' and NMICycle = '0' then + PC <= PC + 1; + end if; + -- + -- jump control logic + -- + case Jump is + when "01" => + PC <= PC + 1; + + when "10" => + PC <= unsigned(DI & DL); + + when "11" => + if PCAdder(8) = '1' then + if DL(7) = '0' then + PC(15 downto 8) <= PC(15 downto 8) + 1; + else + PC(15 downto 8) <= PC(15 downto 8) - 1; + end if; + end if; + PC(7 downto 0) <= PCAdder(7 downto 0); + + when others => null; + end case; + end if; + end if; + end if; + end process; + + PCAdder <= resize(PC(7 downto 0),9) + resize(unsigned(DL(7) & DL),9) when PCAdd = '1' + else "0" & PC(7 downto 0); + + process (Clk) + begin + if Clk'event and Clk = '1' then + if (Enable = '1') then + if (really_rdy = '1') then + if MCycle = "000" then + if LDA = '1' then + ABC(7 downto 0) <= ALU_Q; + end if; + if LDX = '1' then + X(7 downto 0) <= ALU_Q; + end if; + if LDY = '1' then + Y(7 downto 0) <= ALU_Q; + end if; + if (LDA or LDX or LDY) = '1' then + P <= P_Out; + end if; + end if; + if SaveP = '1' then + P <= P_Out; + end if; + if LDP = '1' then + P <= ALU_Q; + end if; + if IR(4 downto 0) = "11000" then + case IR(7 downto 5) is + when "000" => + P(Flag_C) <= '0'; + when "001" => + P(Flag_C) <= '1'; + when "010" => + P(Flag_I) <= '0'; + when "011" => + P(Flag_I) <= '1'; + when "101" => + P(Flag_V) <= '0'; + when "110" => + P(Flag_D) <= '0'; + when "111" => + P(Flag_D) <= '1'; + when others => + end case; + end if; + + --if IR = "00000000" and MCycle = "011" and RstCycle = '0' and NMICycle = '0' and IRQCycle = '0' then + -- P(Flag_B) <= '1'; + --end if; + --if IR = "00000000" and MCycle = "100" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1') then + -- P(Flag_I) <= '1'; + -- P(Flag_B) <= B_o; + --end if; + + -- B=1 always on the 6502 + P(Flag_B) <= '1'; + if IR = "00000000" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1') then + if MCycle = "011" then + -- B=0 in *copy* of P pushed onto the stack + P(Flag_B) <= '0'; + elsif MCycle = "100" then + P(Flag_I) <= '1'; + end if; + end if; + + if SO_n_o = '1' and SO_n = '0' then + P(Flag_V) <= '1'; + end if; + if RstCycle = '1' and Mode_r /= "00" then + P(Flag_1) <= '1'; + P(Flag_D) <= '0'; + P(Flag_I) <= '1'; + end if; + P(Flag_1) <= '1'; + + B_o <= P(Flag_B); + SO_n_o <= SO_n; + IRQ_n_o <= IRQ_n; + NMI_n_o <= NMI_n; + end if; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + + process (Res_n, Clk) + begin + if Res_n = '0' then + BusA_r <= (others => '0'); + BusB <= (others => '0'); + AD <= (others => '0'); + BAL <= (others => '0'); + BAH <= (others => '0'); + DL <= (others => '0'); + elsif Clk'event and Clk = '1' then + if (Enable = '1') then + if (Rdy = '1') then + BusA_r <= BusA; + BusB <= DI; + + case BAAdd is + when "01" => + -- BA Inc + AD <= std_logic_vector(unsigned(AD) + 1); + BAL <= std_logic_vector(unsigned(BAL) + 1); + when "10" => + -- BA Add + BAL <= std_logic_vector(resize(unsigned(BAL(7 downto 0)),9) + resize(unsigned(BusA),9)); + when "11" => + -- BA Adj + if BAL(8) = '1' then + BAH <= std_logic_vector(unsigned(BAH) + 1); + end if; + when others => + end case; + + -- ehenciak : modified to use Y register as well (bugfix) + if ADAdd = '1' then + if (AddY = '1') then + AD <= std_logic_vector(unsigned(AD) + unsigned(Y(7 downto 0))); + else + AD <= std_logic_vector(unsigned(AD) + unsigned(X(7 downto 0))); + end if; + end if; + + if IR = "00000000" then + BAL <= (others => '1'); + BAH <= (others => '1'); + if RstCycle = '1' then + BAL(2 downto 0) <= "100"; + elsif NMICycle = '1' then + BAL(2 downto 0) <= "010"; + else + BAL(2 downto 0) <= "110"; + end if; + if Set_addr_To_r = "11" then + BAL(0) <= '1'; + end if; + end if; + + + if LDDI = '1' then + DL <= DI; + end if; + if LDALU = '1' then + DL <= ALU_Q; + end if; + if LDAD = '1' then + AD <= DI; + end if; + if LDBAL = '1' then + BAL(7 downto 0) <= DI; + end if; + if LDBAH = '1' then + BAH <= DI; + end if; + end if; + end if; + end if; + end process; + + Break <= (BreakAtNA and not BAL(8)) or (PCAdd and not PCAdder(8)); + + + with Set_BusA_To select + BusA <= DI when "000", + ABC(7 downto 0) when "001", + X(7 downto 0) when "010", + Y(7 downto 0) when "011", + std_logic_vector(S(7 downto 0)) when "100", + P when "101", + (others => '-') when others; + + with Set_Addr_To_r select + A <= "0000000000000001" & std_logic_vector(S(7 downto 0)) when "01", + DBR & "00000000" & AD when "10", + "00000000" & BAH & BAL(7 downto 0) when "11", + PBR & std_logic_vector(PC(15 downto 8)) & std_logic_vector(PCAdder(7 downto 0)) when others; + + with Write_Data_r select + DO <= DL when "000", + ABC(7 downto 0) when "001", + X(7 downto 0) when "010", + Y(7 downto 0) when "011", + std_logic_vector(S(7 downto 0)) when "100", + P when "101", + std_logic_vector(PC(7 downto 0)) when "110", + std_logic_vector(PC(15 downto 8)) when others; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + + process (Res_n, Clk) + begin + if Res_n = '0' then + MCycle <= "001"; + RstCycle <= '1'; + IRQCycle <= '0'; + NMICycle <= '0'; + NMIAct <= '0'; + elsif Clk'event and Clk = '1' then + if (Enable = '1') then + if (really_rdy = '1') then + if MCycle = LCycle or Break = '1' then + MCycle <= "000"; + RstCycle <= '0'; + IRQCycle <= '0'; + NMICycle <= '0'; + if NMIAct = '1' then + NMICycle <= '1'; + elsif IRQ_n_o = '0' and P(Flag_I) = '0' then + IRQCycle <= '1'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + + if NMICycle = '1' then + NMIAct <= '0'; + end if; + if NMI_n_o = '1' and NMI_n = '0' then + NMIAct <= '1'; + end if; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T65/T65_ALU.vhd b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T65/T65_ALU.vhd new file mode 100644 index 00000000..b1f6d632 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T65/T65_ALU.vhd @@ -0,0 +1,260 @@ +-- **** +-- T65(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 Bugfixes by ehenciak added +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- 6502 compatible microprocessor core +-- +-- Version : 0245 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t65/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0245 : First version +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T65_Pack.all; + +entity T65_ALU is + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816 + Op : in std_logic_vector(3 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + P_In : in std_logic_vector(7 downto 0); + P_Out : out std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0) + ); +end T65_ALU; + +architecture rtl of T65_ALU is + + -- AddSub variables (temporary signals) + signal ADC_Z : std_logic; + signal ADC_C : std_logic; + signal ADC_V : std_logic; + signal ADC_N : std_logic; + signal ADC_Q : std_logic_vector(7 downto 0); + signal SBC_Z : std_logic; + signal SBC_C : std_logic; + signal SBC_V : std_logic; + signal SBC_N : std_logic; + signal SBC_Q : std_logic_vector(7 downto 0); + +begin + + process (P_In, BusA, BusB) + variable AL : unsigned(6 downto 0); + variable AH : unsigned(6 downto 0); + variable C : std_logic; + begin + AL := resize(unsigned(BusA(3 downto 0) & P_In(Flag_C)), 7) + resize(unsigned(BusB(3 downto 0) & "1"), 7); + AH := resize(unsigned(BusA(7 downto 4) & AL(5)), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7); + +-- pragma translate_off + if is_x(std_logic_vector(AL)) then AL := "0000000"; end if; + if is_x(std_logic_vector(AH)) then AH := "0000000"; end if; +-- pragma translate_on + + if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then + ADC_Z <= '1'; + else + ADC_Z <= '0'; + end if; + + if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' then + AL(6 downto 1) := AL(6 downto 1) + 6; + end if; + + C := AL(6) or AL(5); + AH := resize(unsigned(BusA(7 downto 4) & C), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7); + + ADC_N <= AH(4); + ADC_V <= (AH(4) xor BusA(7)) and not (BusA(7) xor BusB(7)); + +-- pragma translate_off + if is_x(std_logic_vector(AH)) then AH := "0000000"; end if; +-- pragma translate_on + + if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' then + AH(6 downto 1) := AH(6 downto 1) + 6; + end if; + + ADC_C <= AH(6) or AH(5); + + ADC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1)); + end process; + + process (Op, P_In, BusA, BusB) + variable AL : unsigned(6 downto 0); + variable AH : unsigned(5 downto 0); + variable C : std_logic; + begin + C := P_In(Flag_C) or not Op(0); + AL := resize(unsigned(BusA(3 downto 0) & C), 7) - resize(unsigned(BusB(3 downto 0) & "1"), 6); + AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(5)), 6); + +-- pragma translate_off + if is_x(std_logic_vector(AL)) then AL := "0000000"; end if; + if is_x(std_logic_vector(AH)) then AH := "000000"; end if; +-- pragma translate_on + + if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then + SBC_Z <= '1'; + else + SBC_Z <= '0'; + end if; + + SBC_C <= not AH(5); + SBC_V <= (AH(4) xor BusA(7)) and (BusA(7) xor BusB(7)); + SBC_N <= AH(4); + + if P_In(Flag_D) = '1' then + if AL(5) = '1' then + AL(5 downto 1) := AL(5 downto 1) - 6; + end if; + AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(6)), 6); + if AH(5) = '1' then + AH(5 downto 1) := AH(5 downto 1) - 6; + end if; + end if; + + SBC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1)); + end process; + + process (Op, P_In, BusA, BusB, + ADC_Z, ADC_C, ADC_V, ADC_N, ADC_Q, + SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q) + variable Q_t : std_logic_vector(7 downto 0); + begin + -- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC + -- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC + P_Out <= P_In; + Q_t := BusA; + case Op(3 downto 0) is + when "0000" => + -- ORA + Q_t := BusA or BusB; + when "0001" => + -- AND + Q_t := BusA and BusB; + when "0010" => + -- EOR + Q_t := BusA xor BusB; + when "0011" => + -- ADC + P_Out(Flag_V) <= ADC_V; + P_Out(Flag_C) <= ADC_C; + Q_t := ADC_Q; + when "0101" | "1101" => + -- LDA + when "0110" => + -- CMP + P_Out(Flag_C) <= SBC_C; + when "0111" => + -- SBC + P_Out(Flag_V) <= SBC_V; + P_Out(Flag_C) <= SBC_C; + Q_t := SBC_Q; + when "1000" => + -- ASL + Q_t := BusA(6 downto 0) & "0"; + P_Out(Flag_C) <= BusA(7); + when "1001" => + -- ROL + Q_t := BusA(6 downto 0) & P_In(Flag_C); + P_Out(Flag_C) <= BusA(7); + when "1010" => + -- LSR + Q_t := "0" & BusA(7 downto 1); + P_Out(Flag_C) <= BusA(0); + when "1011" => + -- ROR + Q_t := P_In(Flag_C) & BusA(7 downto 1); + P_Out(Flag_C) <= BusA(0); + when "1100" => + -- BIT + P_Out(Flag_V) <= BusB(6); + when "1110" => + -- DEC + Q_t := std_logic_vector(unsigned(BusA) - 1); + when "1111" => + -- INC + Q_t := std_logic_vector(unsigned(BusA) + 1); + when others => + end case; + + case Op(3 downto 0) is + when "0011" => + P_Out(Flag_N) <= ADC_N; + P_Out(Flag_Z) <= ADC_Z; + when "0110" | "0111" => + P_Out(Flag_N) <= SBC_N; + P_Out(Flag_Z) <= SBC_Z; + when "0100" => + when "1100" => + P_Out(Flag_N) <= BusB(7); + if (BusA and BusB) = "00000000" then + P_Out(Flag_Z) <= '1'; + else + P_Out(Flag_Z) <= '0'; + end if; + when others => + P_Out(Flag_N) <= Q_t(7); + if Q_t = "00000000" then + P_Out(Flag_Z) <= '1'; + else + P_Out(Flag_Z) <= '0'; + end if; + end case; + + Q <= Q_t; + end process; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T65/T65_MCode.vhd b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T65/T65_MCode.vhd new file mode 100644 index 00000000..6c6c864a --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T65/T65_MCode.vhd @@ -0,0 +1,1052 @@ +-- **** +-- T65(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 302 minor timing fixes +-- Ver 301 Jump timing fixed +-- Ver 300 Bugfixes by ehenciak added +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- 65xx compatible microprocessor core +-- +-- Version : 0246 + fix +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t65/ +-- +-- Limitations : +-- +-- 65C02 +-- supported : inc, dec, phx, plx, phy, ply +-- missing : bra, ora, lda, cmp, sbc, tsb*2, trb*2, stz*2, bit*2, wai, stp, jmp, bbr*8, bbs*8 +-- +-- File history : +-- +-- 0246 : First release +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T65_Pack.all; + +entity T65_MCode is + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816 + IR : in std_logic_vector(7 downto 0); + MCycle : in std_logic_vector(2 downto 0); + P : in std_logic_vector(7 downto 0); + LCycle : out std_logic_vector(2 downto 0); + ALU_Op : out std_logic_vector(3 downto 0); + Set_BusA_To : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P + Set_Addr_To : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA + Write_Data : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH + Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel + BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj + BreakAtNA : out std_logic; + ADAdd : out std_logic; + AddY : out std_logic; + PCAdd : out std_logic; + Inc_S : out std_logic; + Dec_S : out std_logic; + LDA : out std_logic; + LDP : out std_logic; + LDX : out std_logic; + LDY : out std_logic; + LDS : out std_logic; + LDDI : out std_logic; + LDALU : out std_logic; + LDAD : out std_logic; + LDBAL : out std_logic; + LDBAH : out std_logic; + SaveP : out std_logic; + Write : out std_logic + ); +end T65_MCode; + +architecture rtl of T65_MCode is + + signal Branch : std_logic; + +begin + + with IR(7 downto 5) select + Branch <= not P(Flag_N) when "000", + P(Flag_N) when "001", + not P(Flag_V) when "010", + P(Flag_V) when "011", + not P(Flag_C) when "100", + P(Flag_C) when "101", + not P(Flag_Z) when "110", + P(Flag_Z) when others; + + process (IR, MCycle, P, Branch, Mode) + begin + LCycle <= "001"; + Set_BusA_To <= "001"; -- A + Set_Addr_To <= (others => '0'); + Write_Data <= (others => '0'); + Jump <= (others => '0'); + BAAdd <= "00"; + BreakAtNA <= '0'; + ADAdd <= '0'; + PCAdd <= '0'; + Inc_S <= '0'; + Dec_S <= '0'; + LDA <= '0'; + LDP <= '0'; + LDX <= '0'; + LDY <= '0'; + LDS <= '0'; + LDDI <= '0'; + LDALU <= '0'; + LDAD <= '0'; + LDBAL <= '0'; + LDBAH <= '0'; + SaveP <= '0'; + Write <= '0'; + AddY <= '0'; + + case IR(7 downto 5) is + when "100" => + --{{{ + case IR(1 downto 0) is + when "00" => + Set_BusA_To <= "011"; -- Y + Write_Data <= "011"; -- Y + when "10" => + Set_BusA_To <= "010"; -- X + Write_Data <= "010"; -- X + when others => + Write_Data <= "001"; -- A + end case; + --}}} + when "101" => + --{{{ + case IR(1 downto 0) is + when "00" => + if IR(4) /= '1' or IR(2) /= '0' then + LDY <= '1'; + end if; + when "10" => + LDX <= '1'; + when others => + LDA <= '1'; + end case; + Set_BusA_To <= "000"; -- DI + --}}} + when "110" => + --{{{ + case IR(1 downto 0) is + when "00" => + if IR(4) = '0' then + LDY <= '1'; + end if; + Set_BusA_To <= "011"; -- Y + when others => + Set_BusA_To <= "001"; -- A + end case; + --}}} + when "111" => + --{{{ + case IR(1 downto 0) is + when "00" => + if IR(4) = '0' then + LDX <= '1'; + end if; + Set_BusA_To <= "010"; -- X + when others => + Set_BusA_To <= "001"; -- A + end case; + --}}} + when others => + end case; + + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + Set_BusA_To <= "000"; -- DI + end if; + + case IR(4 downto 0) is + when "00000" | "01000" | "01010" | "11000" | "11010" => + --{{{ + -- Implied + case IR is + when "00000000" => + -- BRK + LCycle <= "110"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= "01"; -- S + Write_Data <= "111"; -- PCH + Write <= '1'; + when 2 => + Dec_S <= '1'; + Set_Addr_To <= "01"; -- S + Write_Data <= "110"; -- PCL + Write <= '1'; + when 3 => + Dec_S <= '1'; + Set_Addr_To <= "01"; -- S + Write_Data <= "101"; -- P + Write <= '1'; + when 4 => + Dec_S <= '1'; + Set_Addr_To <= "11"; -- BA + when 5 => + LDDI <= '1'; + Set_Addr_To <= "11"; -- BA + when 6 => + Jump <= "10"; -- DIDL + when others => + end case; + when "00100000" => + -- JSR + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDDI <= '1'; + Set_Addr_To <= "01"; -- S + when 2 => + Set_Addr_To <= "01"; -- S + Write_Data <= "111"; -- PCH + Write <= '1'; + when 3 => + Dec_S <= '1'; + Set_Addr_To <= "01"; -- S + Write_Data <= "110"; -- PCL + Write <= '1'; + when 4 => + Dec_S <= '1'; + when 5 => + Jump <= "10"; -- DIDL + when others => + end case; + when "01000000" => + -- RTI + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= "01"; -- S + when 2 => + Inc_S <= '1'; + Set_Addr_To <= "01"; -- S + when 3 => + Inc_S <= '1'; + Set_Addr_To <= "01"; -- S + Set_BusA_To <= "000"; -- DI + when 4 => + LDP <= '1'; + Inc_S <= '1'; + LDDI <= '1'; + Set_Addr_To <= "01"; -- S + when 5 => + Jump <= "10"; -- DIDL + when others => + end case; + when "01100000" => + -- RTS + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= "01"; -- S + when 2 => + Inc_S <= '1'; + Set_Addr_To <= "01"; -- S + when 3 => + Inc_S <= '1'; + LDDI <= '1'; + Set_Addr_To <= "01"; -- S + when 4 => + Jump <= "10"; -- DIDL + when 5 => + Jump <= "01"; + when others => + end case; + when "00001000" | "01001000" | "01011010" | "11011010" => + -- PHP, PHA, PHY*, PHX* + LCycle <= "010"; + if Mode = "00" and IR(1) = '1' then + LCycle <= "001"; + end if; + case to_integer(unsigned(MCycle)) is + when 1 => + case IR(7 downto 4) is + when "0000" => + Write_Data <= "101"; -- P + when "0100" => + Write_Data <= "001"; -- A + when "0101" => + Write_Data <= "011"; -- Y + when "1101" => + Write_Data <= "010"; -- X + when others => + end case; + Write <= '1'; + Set_Addr_To <= "01"; -- S + when 2 => + Dec_S <= '1'; + when others => + end case; + when "00101000" | "01101000" | "01111010" | "11111010" => + -- PLP, PLA, PLY*, PLX* + LCycle <= "011"; + if Mode = "00" and IR(1) = '1' then + LCycle <= "001"; + end if; + case IR(7 downto 4) is + when "0010" => + LDP <= '1'; + when "0110" => + LDA <= '1'; + when "0111" => + if Mode /= "00" then + LDY <= '1'; + end if; + when "1111" => + if Mode /= "00" then + LDX <= '1'; + end if; + when others => + end case; + case to_integer(unsigned(MCycle)) is + when 0 => + SaveP <= '1'; + when 1 => + Set_Addr_To <= "01"; -- S + when 2 => + Inc_S <= '1'; + Set_Addr_To <= "01"; -- S + when 3 => + Set_BusA_To <= "000"; -- DI + when others => + end case; + when "10100000" | "11000000" | "11100000" => + -- LDY, CPY, CPX + -- Immediate + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + when others => + end case; + when "10001000" => + -- DEY + LDY <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "011"; -- Y + when others => + end case; + when "11001010" => + -- DEX + LDX <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "010"; -- X + when others => + end case; + when "00011010" | "00111010" => + -- INC*, DEC* + if Mode /= "00" then + LDA <= '1'; -- A + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "100"; -- S + when others => + end case; + when "00001010" | "00101010" | "01001010" | "01101010" => + -- ASL, ROL, LSR, ROR + LDA <= '1'; -- A + Set_BusA_To <= "001"; -- A + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + when others => + end case; + when "10001010" | "10011000" => + -- TYA, TXA + LDA <= '1'; -- A + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + when others => + end case; + when "10101010" | "10101000" => + -- TAX, TAY + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "001"; -- A + when others => + end case; + when "10011010" => + -- TXS + case to_integer(unsigned(MCycle)) is + when 0 => + LDS <= '1'; + when 1 => + when others => + end case; + when "10111010" => + -- TSX + LDX <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "100"; -- S + when others => + end case; + + -- when "00011000" | "00111000" | "01011000" | "01111000" | "10111000" | "11011000" | "11111000" | "11001000" | "11101000" => + -- -- CLC, SEC, CLI, SEI, CLV, CLD, SED, INY, INX + -- case to_integer(unsigned(MCycle)) is + -- when 1 => + -- when others => + -- end case; + when others => + case to_integer(unsigned(MCycle)) is + when 0 => + when others => + end case; + end case; + --}}} + + when "00001" | "00011" => + --{{{ + -- Zero Page Indexed Indirect (d,x) + LCycle <= "101"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + ADAdd <= '1'; + Set_Addr_To <= "10"; -- AD + when 3 => + BAAdd <= "01"; -- DB Inc + LDBAL <= '1'; + Set_Addr_To <= "10"; -- AD + when 4 => + LDBAH <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 5 => + when others => + end case; + --}}} + + when "01001" | "01011" => + --{{{ + -- Immediate + LDA <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + when others => + end case; + + --}}} + + when "00010" | "10010" => + --{{{ + -- Immediate, KIL + LDX <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + if IR = "10100010" then + -- LDX + Jump <= "01"; + else + -- KIL !!!!!!!!!!!!!!!!!!!!!!!!!!!!! + end if; + when others => + end case; + --}}} + + when "00100" => + --{{{ + -- Zero Page + LCycle <= "010"; + case to_integer(unsigned(MCycle)) is + when 0 => + if IR(7 downto 5) = "001" then + SaveP <= '1'; + end if; + when 1 => + Jump <= "01"; + LDAD <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "10"; -- AD + when 2 => + when others => + end case; + --}}} + + when "00101" | "00110" | "00111" => + --{{{ + -- Zero Page + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + -- Read-Modify-Write + LCycle <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + LDDI <= '1'; + Write <= '1'; + Set_Addr_To <= "10"; -- AD + when 3 => + LDALU <= '1'; + SaveP <= '1'; + Write <= '1'; + Set_Addr_To <= "10"; -- AD + when 4 => + when others => + end case; + else + LCycle <= "010"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDAD <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "10"; -- AD + when 2 => + when others => + end case; + end if; + --}}} + + when "01100" => + --{{{ + -- Absolute + if IR(7 downto 6) = "01" and IR(4 downto 0) = "01100" then + -- JMP + if IR(5) = '0' then + --LCycle <= "011"; + LCycle <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDDI <= '1'; + when 2 => + Jump <= "10"; -- DIDL + when others => + end case; + else + --LCycle <= "101"; + LCycle <= "100"; -- mikej + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDDI <= '1'; + LDBAL <= '1'; + when 2 => + LDBAH <= '1'; + if Mode /= "00" then + Jump <= "10"; -- DIDL + end if; + if Mode = "00" then + Set_Addr_To <= "11"; -- BA + end if; + when 3 => + LDDI <= '1'; + if Mode = "00" then + Set_Addr_To <= "11"; -- BA + BAAdd <= "01"; -- DB Inc + else + Jump <= "01"; + end if; + when 4 => + Jump <= "10"; -- DIDL + when others => + end case; + end if; + else + LCycle <= "011"; + case to_integer(unsigned(MCycle)) is + when 0 => + if IR(7 downto 5) = "001" then + SaveP <= '1'; + end if; + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + LDBAH <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 3 => + when others => + end case; + end if; + --}}} + + when "01101" | "01110" | "01111" => + --{{{ + -- Absolute + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + -- Read-Modify-Write + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 3 => + LDDI <= '1'; + Write <= '1'; + Set_Addr_To <= "11"; -- BA + when 4 => + Write <= '1'; + LDALU <= '1'; + SaveP <= '1'; + Set_Addr_To <= "11"; -- BA + when 5 => + SaveP <= '0'; -- MIKEJ was 1 + when others => + end case; + else + LCycle <= "011"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + LDBAH <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 3 => + when others => + end case; + end if; + --}}} + + when "10000" => + --{{{ + -- Relative + + -- This circuit dictates when the last + -- microcycle occurs for the branch depending on + -- whether or not the branch is taken and if a page + -- is crossed... + if (Branch = '1') then + + LCycle <= "011"; -- We're done @ T3 if branching...upper + -- level logic will stop at T2 if no page cross + -- (See the Break signal) + else + + LCycle <= "001"; + + end if; + + -- This decodes the current microcycle and takes the + -- proper course of action... + case to_integer(unsigned(MCycle)) is + + -- On the T1 microcycle, increment the program counter + -- and instruct the upper level logic to fetch the offset + -- from the Din bus and store it in the data latches. This + -- will be the last microcycle if the branch isn't taken. + when 1 => + + Jump <= "01"; -- Increments the PC by one (PC will now be PC+2) + -- from microcycle T0. + + LDDI <= '1'; -- Tells logic in top level (T65.vhd) to route + -- the Din bus to the memory data latch (DL) + -- so that the branch offset is fetched. + + -- In microcycle T2, tell the logic in the top level to + -- add the offset. If the most significant byte of the + -- program counter (i.e. the current "page") does not need + -- updating, we are done here...the Break signal at the + -- T65.vhd level takes care of that... + when 2 => + + Jump <= "11"; -- Tell the PC Jump logic to use relative mode. + + PCAdd <= '1'; -- This tells the PC adder to update itself with + -- the current offset recently fetched from + -- memory. + + -- The following is microcycle T3 : + -- The program counter should be completely updated + -- on this cycle after the page cross is detected. + -- We don't need to do anything here... + when 3 => + + + when others => null; -- Do nothing. + + end case; + --}}} + + when "10001" | "10011" => + --{{{ + -- Zero Page Indirect Indexed (d),y + LCycle <= "101"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + LDBAL <= '1'; + BAAdd <= "01"; -- DB Inc + Set_Addr_To <= "10"; -- AD + when 3 => + Set_BusA_To <= "011"; -- Y + BAAdd <= "10"; -- BA Add + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 4 => + BAAdd <= "11"; -- BA Adj + if IR(7 downto 5) = "100" then + Write <= '1'; + else + BreakAtNA <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 5 => + when others => + end case; + --}}} + + when "10100" | "10101" | "10110" | "10111" => + --{{{ + -- Zero Page, X + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + -- Read-Modify-Write + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + ADAdd <= '1'; + Set_Addr_To <= "10"; -- AD + when 3 => + LDDI <= '1'; + Write <= '1'; + Set_Addr_To <= "10"; -- AD + when 4 => + LDALU <= '1'; + SaveP <= '1'; + Write <= '1'; + Set_Addr_To <= "10"; -- AD + when 5 => + when others => + end case; + else + LCycle <= "011"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + ADAdd <= '1'; + -- Added this check for Y reg. use... + if (IR(3 downto 0) = "0110") then + AddY <= '1'; + end if; + + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "10"; -- AD + when 3 => null; + when others => + end case; + end if; + --}}} + + when "11001" | "11011" => + --{{{ + -- Absolute Y + LCycle <= "100"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + Set_BusA_To <= "011"; -- Y + BAAdd <= "10"; -- BA Add + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 3 => + BAAdd <= "11"; -- BA adj + if IR(7 downto 5) = "100" then + Write <= '1'; + else + BreakAtNA <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 4 => + when others => + end case; + --}}} + + when "11100" | "11101" | "11110" | "11111" => + --{{{ + -- Absolute X + + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + -- Read-Modify-Write + LCycle <= "110"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + Set_BusA_To <= "010"; -- X + BAAdd <= "10"; -- BA Add + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 3 => + BAAdd <= "11"; -- BA adj + Set_Addr_To <= "11"; -- BA + when 4 => + LDDI <= '1'; + Write <= '1'; + Set_Addr_To <= "11"; -- BA + when 5 => + LDALU <= '1'; + SaveP <= '1'; + Write <= '1'; + Set_Addr_To <= "11"; -- BA + when 6 => + when others => + end case; + else + LCycle <= "100"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + -- mikej + -- special case 0xBE which uses Y reg as index!! + if (IR = "10111110") then + Set_BusA_To <= "011"; -- Y + else + Set_BusA_To <= "010"; -- X + end if; + BAAdd <= "10"; -- BA Add + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 3 => + BAAdd <= "11"; -- BA adj + if IR(7 downto 5) = "100" then + Write <= '1'; + else + BreakAtNA <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 4 => + when others => + end case; + end if; + --}}} + when others => + end case; + end process; + + process (IR, MCycle) + begin + -- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC + -- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC + case IR(1 downto 0) is + when "00" => + --{{{ + case IR(4 downto 2) is + when "000" | "001" | "011" => + case IR(7 downto 5) is + when "110" | "111" => + -- CP + ALU_Op <= "0110"; + when "101" => + -- LD + ALU_Op <= "0101"; + when "001" => + -- BIT + ALU_Op <= "1100"; + when others => + -- NOP/ST + ALU_Op <= "0100"; + end case; + when "010" => + case IR(7 downto 5) is + when "111" | "110" => + -- IN + ALU_Op <= "1111"; + when "100" => + -- DEY + ALU_Op <= "1110"; + when others => + -- LD + ALU_Op <= "1101"; + end case; + when "110" => + case IR(7 downto 5) is + when "100" => + -- TYA + ALU_Op <= "1101"; + when others => + ALU_Op <= "----"; + end case; + when others => + case IR(7 downto 5) is + when "101" => + -- LD + ALU_Op <= "1101"; + when others => + ALU_Op <= "0100"; + end case; + end case; + --}}} + when "01" => -- OR + --{{{ + ALU_Op(3) <= '0'; + ALU_Op(2 downto 0) <= IR(7 downto 5); + --}}} + when "10" => + --{{{ + ALU_Op(3) <= '1'; + ALU_Op(2 downto 0) <= IR(7 downto 5); + case IR(7 downto 5) is + when "000" => + if IR(4 downto 2) = "110" then + -- INC + ALU_Op <= "1111"; + end if; + when "001" => + if IR(4 downto 2) = "110" then + -- DEC + ALU_Op <= "1110"; + end if; + when "100" => + if IR(4 downto 2) = "010" then + -- TXA + ALU_Op <= "0101"; + else + ALU_Op <= "0100"; + end if; + when others => + end case; + --}}} + when others => + --{{{ + case IR(7 downto 5) is + when "100" => + ALU_Op <= "0100"; + when others => + if MCycle = "000" then + ALU_Op(3) <= '0'; + ALU_Op(2 downto 0) <= IR(7 downto 5); + else + ALU_Op(3) <= '1'; + ALU_Op(2 downto 0) <= IR(7 downto 5); + end if; + end case; + --}}} + end case; + end process; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T65/T65_Pack.vhd b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T65/T65_Pack.vhd new file mode 100644 index 00000000..e025e1bf --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T65/T65_Pack.vhd @@ -0,0 +1,117 @@ +-- **** +-- T65(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 Bugfixes by ehenciak added +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- 65xx compatible microprocessor core +-- +-- Version : 0246 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t65/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T65_Pack is + + constant Flag_C : integer := 0; + constant Flag_Z : integer := 1; + constant Flag_I : integer := 2; + constant Flag_D : integer := 3; + constant Flag_B : integer := 4; + constant Flag_1 : integer := 5; + constant Flag_V : integer := 6; + constant Flag_N : integer := 7; + + component T65_MCode + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816 + IR : in std_logic_vector(7 downto 0); + MCycle : in std_logic_vector(2 downto 0); + P : in std_logic_vector(7 downto 0); + LCycle : out std_logic_vector(2 downto 0); + ALU_Op : out std_logic_vector(3 downto 0); + Set_BusA_To : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P + Set_Addr_To : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA + Write_Data : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH + Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel + BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj + BreakAtNA : out std_logic; + ADAdd : out std_logic; + AddY : out std_logic; + PCAdd : out std_logic; + Inc_S : out std_logic; + Dec_S : out std_logic; + LDA : out std_logic; + LDP : out std_logic; + LDX : out std_logic; + LDY : out std_logic; + LDS : out std_logic; + LDDI : out std_logic; + LDALU : out std_logic; + LDAD : out std_logic; + LDBAL : out std_logic; + LDBAH : out std_logic; + SaveP : out std_logic; + Write : out std_logic + ); + end component; + + component T65_ALU + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816 + Op : in std_logic_vector(3 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + P_In : in std_logic_vector(7 downto 0); + P_Out : out std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T80/T80.vhd new file mode 100644 index 00000000..398fa0df --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T80/T80.vhd @@ -0,0 +1,1073 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 and Auto_Wait_t1 = '0' then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if T_Res = '1' then + Auto_Wait_t1 <= '0'; + else + Auto_Wait_t1 <= Auto_Wait or IORQ_i; + end if; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if (Auto_Wait = '1' and Auto_Wait_t2 = '0') nor + (IOWait = 1 and IORQ_i = '1' and Auto_Wait_t1 = '0') then + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T80/T80_ALU.vhd new file mode 100644 index 00000000..86fddce7 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T80/T80_ALU.vhd @@ -0,0 +1,351 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + OverFlow_v <= Carry_v xor Carry7_v; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T80/T80_MCode.vhd new file mode 100644 index 00000000..4cc30f35 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T80/T80_MCode.vhd @@ -0,0 +1,1934 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; +-- constant aNone : std_logic_vector(2 downto 0) := "000"; +-- constant aXY : std_logic_vector(2 downto 0) := "001"; +-- constant aIOA : std_logic_vector(2 downto 0) := "010"; +-- constant aSP : std_logic_vector(2 downto 0) := "011"; +-- constant aBC : std_logic_vector(2 downto 0) := "100"; +-- constant aDE : std_logic_vector(2 downto 0) := "101"; +-- constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0010"; + else + IncDec_16 <= "1010"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0010"; + else + IncDec_16 <= "1010"; + end if; + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T80/T80_Pack.vhd new file mode 100644 index 00000000..ac7d34da --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T80/T80_Pack.vhd @@ -0,0 +1,208 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T80/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T80/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T80/T80s.vhd b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T80/T80s.vhd new file mode 100644 index 00000000..5b612110 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/T80/T80s.vhd @@ -0,0 +1,190 @@ +-- +-- Z80 compatible microprocessor core, synchronous top level +-- Different timing than the original z80 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed read with wait +-- +-- 0211 : Fixed interrupt cycle +-- +-- 0235 : Updated for T80 interface change +-- +-- 0236 : Added T2Write generic +-- +-- 0237 : Fixed T2Write with wait state +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80s is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2 + IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80s; + +architecture rtl of T80s is + + signal CEN : std_logic; + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + CEN <= '1'; + + u0 : T80 + generic map( + Mode => Mode, + IOWait => IOWait) + port map( + CEN => CEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if T2Write = 0 then + if TState = "010" and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + else + if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end process; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/YM2149_linmix_sep.vhd b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/YM2149_linmix_sep.vhd new file mode 100644 index 00000000..6ed2498a --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/YM2149_linmix_sep.vhd @@ -0,0 +1,574 @@ +-- changes for seperate audio outputs and enable now enables cpu access as well +-- +-- A simulation model of YM2149 (AY-3-8910 with bells on) + +-- Copyright (c) MikeJ - Jan 2005 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- +-- Clues from MAME sound driver and Kazuhiro TSUJIKAWA +-- +-- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V) +-- vol 15 .. 0 +-- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132 +-- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order +-- to produced all the required values. +-- (The first part of the curve is a bit steeper and the last bit is more linear than expected) +-- +-- NOTE, this component uses LINEAR mixing of the three analogue channels, and is only +-- accurate for designs where the outputs are buffered and not simply wired together. +-- The ouput level is more complex in that case and requires a larger table. + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity YM2149 is + port ( + -- data bus + I_DA : in std_logic_vector(7 downto 0); + O_DA : out std_logic_vector(7 downto 0); + O_DA_OE_L : out std_logic; + -- control + I_A9_L : in std_logic; + I_A8 : in std_logic; + I_BDIR : in std_logic; + I_BC2 : in std_logic; + I_BC1 : in std_logic; + I_SEL_L : in std_logic; + + O_AUDIO : out std_logic_vector(7 downto 0); + O_CHAN : out std_logic_vector(1 downto 0); + -- port a + I_IOA : in std_logic_vector(7 downto 0); + O_IOA : out std_logic_vector(7 downto 0); + O_IOA_OE_L : out std_logic; + -- port b + I_IOB : in std_logic_vector(7 downto 0); + O_IOB : out std_logic_vector(7 downto 0); + O_IOB_OE_L : out std_logic; + + ENA : in std_logic; -- clock enable for higher speed operation + RESET_L : in std_logic; + CLK : in std_logic -- note 6 Mhz + ); +end; + +architecture RTL of YM2149 is + type array_16x8 is array (0 to 15) of std_logic_vector( 7 downto 0); + type array_3x12 is array (1 to 3) of std_logic_vector(11 downto 0); + + signal cnt_div : std_logic_vector(3 downto 0) := (others => '0'); + signal cnt_div_t1 : std_logic_vector(3 downto 0); + signal noise_div : std_logic := '0'; + signal ena_div : std_logic; + signal ena_div_noise : std_logic; + signal poly17 : std_logic_vector(16 downto 0) := (others => '0'); + + -- registers + signal addr : std_logic_vector(7 downto 0); + signal busctrl_addr : std_logic; + signal busctrl_we : std_logic; + signal busctrl_re : std_logic; + + signal reg : array_16x8; + signal env_reset : std_logic; + signal ioa_inreg : std_logic_vector(7 downto 0); + signal iob_inreg : std_logic_vector(7 downto 0); + + signal noise_gen_cnt : std_logic_vector(4 downto 0); + signal noise_gen_op : std_logic; + signal tone_gen_cnt : array_3x12 := (others => (others => '0')); + signal tone_gen_op : std_logic_vector(3 downto 1) := "000"; + + signal env_gen_cnt : std_logic_vector(15 downto 0); + signal env_ena : std_logic; + signal env_hold : std_logic; + signal env_inc : std_logic; + signal env_vol : std_logic_vector(4 downto 0); + + signal tone_ena_l : std_logic; + signal tone_src : std_logic; + signal noise_ena_l : std_logic; + signal chan_vol : std_logic_vector(4 downto 0); + + signal dac_amp : std_logic_vector(7 downto 0); +begin + -- cpu i/f + p_busdecode : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8) + variable cs : std_logic; + variable sel : std_logic_vector(2 downto 0); + begin + -- BDIR BC2 BC1 MODE + -- 0 0 0 inactive + -- 0 0 1 address + -- 0 1 0 inactive + -- 0 1 1 read + -- 1 0 0 address + -- 1 0 1 inactive + -- 1 1 0 write + -- 1 1 1 read + busctrl_addr <= '0'; + busctrl_we <= '0'; + busctrl_re <= '0'; + + cs := '0'; + if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then + cs := '1'; + end if; + + sel := (I_BDIR & I_BC2 & I_BC1); + case sel is + when "000" => null; + when "001" => busctrl_addr <= '1'; + when "010" => null; + when "011" => busctrl_re <= cs; + when "100" => busctrl_addr <= '1'; + when "101" => null; + when "110" => busctrl_we <= cs; + when "111" => busctrl_addr <= '1'; + when others => null; + end case; + end process; + + p_oe : process(busctrl_re) + begin + -- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns + O_DA_OE_L <= not (busctrl_re); + end process; + + -- + -- CLOCKED + -- + p_waddr : process(RESET_L, CLK) + begin + -- looks like registers are latches in real chip, but the address is caught at the end of the address state. + if (RESET_L = '0') then + addr <= (others => '0'); + elsif rising_edge(CLK) then + if (ENA = '1') then + if (busctrl_addr = '1') then + addr <= I_DA; + end if; + end if; + end if; + end process; + + p_wdata : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + reg <= (others => (others => '0')); + env_reset <= '1'; + elsif rising_edge(CLK) then + if (ENA = '1') then + env_reset <= '0'; + if (busctrl_we = '1') then + case addr(3 downto 0) is + when x"0" => reg(0) <= I_DA; + when x"1" => reg(1) <= I_DA; + when x"2" => reg(2) <= I_DA; + when x"3" => reg(3) <= I_DA; + when x"4" => reg(4) <= I_DA; + when x"5" => reg(5) <= I_DA; + when x"6" => reg(6) <= I_DA; + when x"7" => reg(7) <= I_DA; + when x"8" => reg(8) <= I_DA; + when x"9" => reg(9) <= I_DA; + when x"A" => reg(10) <= I_DA; + when x"B" => reg(11) <= I_DA; + when x"C" => reg(12) <= I_DA; + when x"D" => reg(13) <= I_DA; env_reset <= '1'; + when x"E" => reg(14) <= I_DA; + when x"F" => reg(15) <= I_DA; + when others => null; + end case; + end if; + end if; + end if; + end process; + + p_rdata : process(busctrl_re, addr, reg, ioa_inreg, iob_inreg) + begin + O_DA <= (others => '0'); -- 'X' + if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator + case addr(3 downto 0) is + when x"0" => O_DA <= reg(0) ; + when x"1" => O_DA <= "0000" & reg(1)(3 downto 0) ; + when x"2" => O_DA <= reg(2) ; + when x"3" => O_DA <= "0000" & reg(3)(3 downto 0) ; + when x"4" => O_DA <= reg(4) ; + when x"5" => O_DA <= "0000" & reg(5)(3 downto 0) ; + when x"6" => O_DA <= "000" & reg(6)(4 downto 0) ; + when x"7" => O_DA <= reg(7) ; + when x"8" => O_DA <= "000" & reg(8)(4 downto 0) ; + when x"9" => O_DA <= "000" & reg(9)(4 downto 0) ; + when x"A" => O_DA <= "000" & reg(10)(4 downto 0) ; + when x"B" => O_DA <= reg(11); + when x"C" => O_DA <= reg(12); + when x"D" => O_DA <= "0000" & reg(13)(3 downto 0); + when x"E" => if (reg(7)(6) = '0') then -- input + O_DA <= ioa_inreg; + else + O_DA <= reg(14); -- read output reg + end if; + when x"F" => if (Reg(7)(7) = '0') then + O_DA <= iob_inreg; + else + O_DA <= reg(15); + end if; + when others => null; + end case; + end if; + end process; + -- + p_divider : process + begin + wait until rising_edge(CLK); + -- / 8 when SEL is high and /16 when SEL is low + if (ENA = '1') then + ena_div <= '0'; + ena_div_noise <= '0'; + if (cnt_div = "0000") then + cnt_div <= (not I_SEL_L) & "111"; + ena_div <= '1'; + + noise_div <= not noise_div; + if (noise_div = '1') then + ena_div_noise <= '1'; + end if; + else + cnt_div <= cnt_div - "1"; + end if; + end if; + end process; + + p_noise_gen : process + variable noise_gen_comp : std_logic_vector(4 downto 0); + variable poly17_zero : std_logic; + begin + wait until rising_edge(CLK); + if (reg(6)(4 downto 0) = "00000") then + noise_gen_comp := "00000"; + else + noise_gen_comp := (reg(6)(4 downto 0) - "1"); + end if; + + poly17_zero := '0'; + if (poly17 = "00000000000000000") then poly17_zero := '1'; end if; + + if (ENA = '1') then + if (ena_div_noise = '1') then -- divider ena + + if (noise_gen_cnt >= noise_gen_comp) then + noise_gen_cnt <= "00000"; + poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1); + else + noise_gen_cnt <= (noise_gen_cnt + "1"); + end if; + end if; + end if; + end process; + noise_gen_op <= poly17(0); + + p_tone_gens : process + variable tone_gen_freq : array_3x12; + variable tone_gen_comp : array_3x12; + begin + wait until rising_edge(CLK); + -- looks like real chips count up - we need to get the Exact behaviour .. + tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0); + tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2); + tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4); + -- period 0 = period 1 + for i in 1 to 3 loop + if (tone_gen_freq(i) = x"000") then + tone_gen_comp(i) := x"000"; + else + tone_gen_comp(i) := (tone_gen_freq(i) - "1"); + end if; + end loop; + + if (ENA = '1') then + for i in 1 to 3 loop + if (ena_div = '1') then -- divider ena + + if (tone_gen_cnt(i) >= tone_gen_comp(i)) then + tone_gen_cnt(i) <= x"000"; + tone_gen_op(i) <= not tone_gen_op(i); + else + tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1"); + end if; + end if; + end loop; + end if; + end process; + + p_envelope_freq : process + variable env_gen_freq : std_logic_vector(15 downto 0); + variable env_gen_comp : std_logic_vector(15 downto 0); + begin + wait until rising_edge(CLK); + env_gen_freq := reg(12) & reg(11); + -- envelope freqs 1 and 0 are the same. + if (env_gen_freq = x"0000") then + env_gen_comp := x"0000"; + else + env_gen_comp := (env_gen_freq - "1"); + end if; + + if (ENA = '1') then + env_ena <= '0'; + if (ena_div = '1') then -- divider ena + if (env_gen_cnt >= env_gen_comp) then + env_gen_cnt <= x"0000"; + env_ena <= '1'; + else + env_gen_cnt <= (env_gen_cnt + "1"); + end if; + end if; + end if; + end process; + + p_envelope_shape : process(env_reset, reg, CLK) + variable is_bot : boolean; + variable is_bot_p1 : boolean; + variable is_top_m1 : boolean; + variable is_top : boolean; + begin + -- envelope shapes + -- C AtAlH + -- 0 0 x x \___ + -- + -- 0 1 x x /___ + -- + -- 1 0 0 0 \\\\ + -- + -- 1 0 0 1 \___ + -- + -- 1 0 1 0 \/\/ + -- ___ + -- 1 0 1 1 \ + -- + -- 1 1 0 0 //// + -- ___ + -- 1 1 0 1 / + -- + -- 1 1 1 0 /\/\ + -- + -- 1 1 1 1 /___ + if (env_reset = '1') then + -- load initial state + if (reg(13)(2) = '0') then -- attack + env_vol <= "11111"; + env_inc <= '0'; -- -1 + else + env_vol <= "00000"; + env_inc <= '1'; -- +1 + end if; + env_hold <= '0'; + + elsif rising_edge(CLK) then + is_bot := (env_vol = "00000"); + is_bot_p1 := (env_vol = "00001"); + is_top_m1 := (env_vol = "11110"); + is_top := (env_vol = "11111"); + + if (ENA = '1') then + if (env_ena = '1') then + if (env_hold = '0') then + if (env_inc = '1') then + env_vol <= (env_vol + "00001"); + else + env_vol <= (env_vol + "11111"); + end if; + end if; + + -- envelope shape control. + if (reg(13)(3) = '0') then + if (env_inc = '0') then -- down + if is_bot_p1 then env_hold <= '1'; end if; + else + if is_top then env_hold <= '1'; end if; + end if; + else + if (reg(13)(0) = '1') then -- hold = 1 + if (env_inc = '0') then -- down + if (reg(13)(1) = '1') then -- alt + if is_bot then env_hold <= '1'; end if; + else + if is_bot_p1 then env_hold <= '1'; end if; + end if; + else + if (reg(13)(1) = '1') then -- alt + if is_top then env_hold <= '1'; end if; + else + if is_top_m1 then env_hold <= '1'; end if; + end if; + end if; + + elsif (reg(13)(1) = '1') then -- alternate + if (env_inc = '0') then -- down + if is_bot_p1 then env_hold <= '1'; end if; + if is_bot then env_hold <= '0'; env_inc <= '1'; end if; + else + if is_top_m1 then env_hold <= '1'; end if; + if is_top then env_hold <= '0'; env_inc <= '0'; end if; + end if; + end if; + + end if; + end if; + end if; + end if; + end process; + + p_chan_mixer : process(cnt_div, reg, tone_gen_op) + begin + tone_ena_l <= '1'; tone_src <= '1'; + noise_ena_l <= '1'; chan_vol <= "00000"; + case cnt_div(1 downto 0) is + when "00" => + tone_ena_l <= reg(7)(0); tone_src <= tone_gen_op(1); chan_vol <= reg(8)(4 downto 0); + noise_ena_l <= reg(7)(3); + when "01" => + tone_ena_l <= reg(7)(1); tone_src <= tone_gen_op(2); chan_vol <= reg(9)(4 downto 0); + noise_ena_l <= reg(7)(4); + when "10" => + tone_ena_l <= reg(7)(2); tone_src <= tone_gen_op(3); chan_vol <= reg(10)(4 downto 0); + noise_ena_l <= reg(7)(5); + when "11" => null; -- tone gen outputs become valid on this clock + when others => null; + end case; + end process; + + p_op_mixer : process + variable chan_mixed : std_logic; + variable chan_amp : std_logic_vector(4 downto 0); + begin + wait until rising_edge(CLK); + if (ENA = '1') then + + chan_mixed := (tone_ena_l or tone_src) and (noise_ena_l or noise_gen_op); + + chan_amp := (others => '0'); + if (chan_mixed = '1') then + if (chan_vol(4) = '0') then + if (chan_vol(3 downto 0) = "0000") then -- nothing is easy ! make sure quiet is quiet + chan_amp := "00000"; + else + chan_amp := chan_vol(3 downto 0) & '1'; -- make sure level 31 (env) = level 15 (tone) + end if; + else + chan_amp := env_vol(4 downto 0); + end if; + end if; + + dac_amp <= x"00"; + case chan_amp is + when "11111" => dac_amp <= x"FF"; + when "11110" => dac_amp <= x"D9"; + when "11101" => dac_amp <= x"BA"; + when "11100" => dac_amp <= x"9F"; + when "11011" => dac_amp <= x"88"; + when "11010" => dac_amp <= x"74"; + when "11001" => dac_amp <= x"63"; + when "11000" => dac_amp <= x"54"; + when "10111" => dac_amp <= x"48"; + when "10110" => dac_amp <= x"3D"; + when "10101" => dac_amp <= x"34"; + when "10100" => dac_amp <= x"2C"; + when "10011" => dac_amp <= x"25"; + when "10010" => dac_amp <= x"1F"; + when "10001" => dac_amp <= x"1A"; + when "10000" => dac_amp <= x"16"; + when "01111" => dac_amp <= x"13"; + when "01110" => dac_amp <= x"10"; + when "01101" => dac_amp <= x"0D"; + when "01100" => dac_amp <= x"0B"; + when "01011" => dac_amp <= x"09"; + when "01010" => dac_amp <= x"08"; + when "01001" => dac_amp <= x"07"; + when "01000" => dac_amp <= x"06"; + when "00111" => dac_amp <= x"05"; + when "00110" => dac_amp <= x"04"; + when "00101" => dac_amp <= x"03"; + when "00100" => dac_amp <= x"03"; + when "00011" => dac_amp <= x"02"; + when "00010" => dac_amp <= x"02"; + when "00001" => dac_amp <= x"01"; + when "00000" => dac_amp <= x"00"; + when others => null; + end case; + + cnt_div_t1 <= cnt_div; + end if; + end process; + + p_audio_output : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + O_AUDIO <= (others => '0'); + O_CHAN <= (others => '0'); + elsif rising_edge(CLK) then + + if (ENA = '1') then + O_AUDIO <= dac_amp(7 downto 0); + O_CHAN <= cnt_div_t1(1 downto 0); + end if; + end if; + end process; + + p_io_ports : process(reg) + begin + O_IOA <= reg(14); + O_IOA_OE_L <= not reg(7)(6); + O_IOB <= reg(15); + O_IOB_OE_L <= not reg(7)(7); + end process; + + p_io_ports_inreg : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then -- resync + ioa_inreg <= I_IOA; + iob_inreg <= I_IOB; + end if; + end process; +end architecture RTL; diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/build_id.tcl b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/dpram.vhd b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..cda0f3cd --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/dpram.vhd @@ -0,0 +1,123 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY dpram IS + GENERIC + ( + init_file : string := ""; + numwords_a : natural := 0; -- not used any more + widthad_a : natural; + width_a : natural := 8; + outdata_reg_a : string := "UNREGISTERED"; + outdata_reg_b : string := "UNREGISTERED" + ); + PORT + ( + address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + clock_a : IN STD_LOGIC ; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + wren_a : IN STD_LOGIC := '1'; + wren_b : IN STD_LOGIC := '1'; + q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); +END dpram; + + +ARCHITECTURE SYN OF dpram IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + + COMPONENT altsyncram + GENERIC ( + address_reg_b : STRING; + clock_enable_input_a : STRING; + clock_enable_input_b : STRING; + clock_enable_output_a : STRING; + clock_enable_output_b : STRING; + indata_reg_b : STRING; + init_file : STRING; + intended_device_family : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + numwords_b : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_aclr_b : STRING; + outdata_reg_a : STRING; + outdata_reg_b : STRING; + power_up_uninitialized : STRING; + widthad_a : NATURAL; + widthad_b : NATURAL; + width_a : NATURAL; + width_b : NATURAL; + width_byteena_a : NATURAL; + width_byteena_b : NATURAL; + wrcontrol_wraddress_reg_b : STRING + ); + PORT ( + wren_a : IN STD_LOGIC ; + clock0 : IN STD_LOGIC ; + wren_b : IN STD_LOGIC ; + clock1 : IN STD_LOGIC ; + address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q_a <= sub_wire0(width_a-1 DOWNTO 0); + q_b <= sub_wire1(width_a-1 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + address_reg_b => "CLOCK1", + clock_enable_input_a => "BYPASS", + clock_enable_input_b => "BYPASS", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", + init_file => init_file, + intended_device_family => "Cyclone III", + lpm_type => "altsyncram", + numwords_a => 2**widthad_a, + numwords_b => 2**widthad_a, + operation_mode => "BIDIR_DUAL_PORT", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => outdata_reg_a, + outdata_reg_b => outdata_reg_b, + power_up_uninitialized => "FALSE", + widthad_a => widthad_a, + widthad_b => widthad_a, + width_a => width_a, + width_b => width_a, + width_byteena_a => 1, + width_byteena_b => 1, + wrcontrol_wraddress_reg_b => "CLOCK1" + ) + PORT MAP ( + wren_a => wren_a, + clock0 => clock_a, + wren_b => wren_b, + clock1 => clock_b, + address_a => address_a, + address_b => address_b, + data_a => data_a, + data_b => data_b, + q_a => sub_wire0, + q_b => sub_wire1 + ); + +END SYN; diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/gen_ram.vhd b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/gen_ram.vhd new file mode 100644 index 00000000..f1a95608 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/gen_ram.vhd @@ -0,0 +1,84 @@ +-- ----------------------------------------------------------------------- +-- +-- Syntiac's generic VHDL support files. +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- +-- Modified April 2016 by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +-- Remove address register when writing +-- +-- ----------------------------------------------------------------------- +-- +-- gen_rwram.vhd +-- +-- ----------------------------------------------------------------------- +-- +-- generic ram. +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +entity gen_ram is + generic ( + dWidth : integer := 8; + aWidth : integer := 10 + ); + port ( + clk : in std_logic; + we : in std_logic; + addr : in std_logic_vector((aWidth-1) downto 0); + d : in std_logic_vector((dWidth-1) downto 0); + q : out std_logic_vector((dWidth-1) downto 0) + ); +end entity; + +-- ----------------------------------------------------------------------- + +architecture rtl of gen_ram is + subtype addressRange is integer range 0 to ((2**aWidth)-1); + type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0); + signal ram: ramDef; + + signal rAddrReg : std_logic_vector((aWidth-1) downto 0); + signal qReg : std_logic_vector((dWidth-1) downto 0); +begin +-- ----------------------------------------------------------------------- +-- Signals to entity interface +-- ----------------------------------------------------------------------- +-- q <= qReg; + +-- ----------------------------------------------------------------------- +-- Memory write +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if we = '1' then + ram(to_integer(unsigned(addr))) <= d; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Memory read +-- ----------------------------------------------------------------------- +process(clk) + begin + if rising_edge(clk) then +-- qReg <= ram(to_integer(unsigned(rAddrReg))); +-- rAddrReg <= addr; +---- qReg <= ram(to_integer(unsigned(addr))); + q <= ram(to_integer(unsigned(addr))); + end if; + end process; +--q <= ram(to_integer(unsigned(addr))); +end architecture; + diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jng_hvgen.v b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jng_hvgen.v new file mode 100644 index 00000000..56e6ec98 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jng_hvgen.v @@ -0,0 +1,36 @@ +module jng_hvgen +( + output [8:0] HPOS, + output [8:0] VPOS, + input PCLK, + output reg HBLK = 1, + output reg VBLK = 1, + output reg HSYN = 1, + output reg VSYN = 1 +); + +reg [8:0] hcnt = 0; +reg [8:0] vcnt = 0; + +assign HPOS = hcnt; +assign VPOS = vcnt; + +always @(posedge PCLK) begin + case (hcnt) + 287: begin HBLK <= 1; HSYN <= 0; hcnt <= hcnt+1; end + 311: begin HSYN <= 1; hcnt <= hcnt+1; end + 383: begin + HBLK <= 0; HSYN <= 1; hcnt <= 0; + case (vcnt) + 223: begin VBLK <= 1; vcnt <= vcnt+1; end + 226: begin VSYN <= 0; vcnt <= vcnt+1; end + 233: begin VSYN <= 1; vcnt <= vcnt+1; end + 242: begin VBLK <= 0; vcnt <= 0; end + default: vcnt <= vcnt+1; + endcase + end + default: hcnt <= hcnt+1; + endcase +end + +endmodule \ No newline at end of file diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jng_sound.vhd b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jng_sound.vhd new file mode 100644 index 00000000..12f35807 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jng_sound.vhd @@ -0,0 +1,425 @@ +--------------------------------------------------------------------------------- +-- burnin rubber sound by Dar (darfpga@aol.fr) (05/12/2017) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- +-- gen_ram.vhd & io_ps2_keyboard +-------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +--------------------------------------------------------------------------------- +-- T65(b) core.Ver 301 by MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +--------------------------------------------------------------------------------- +-- YM2149 (AY-3-8910) +-- Copyright (c) MikeJ - Jan 2005 +--------------------------------------------------------------------------------- +-- Use burnin_rubber_de10_lite.sdc to compile (Timequest constraints) +-- /!\ +-- Don't forget to set device configuration mode with memory initialization +-- (Assignments/Device/Pin options/Configuration mode) +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity jng_sound is +port +( + clock_12 : in std_logic; + reset : in std_logic; + + sound_req : in std_logic; + sound_code_in : in std_logic_vector(7 downto 0); + sound_timing : in std_logic; + + audio_out : out std_logic_vector(10 downto 0); + + dbg_cpu_addr: out std_logic_vector(15 downto 0) + ); +end jng_sound; + +architecture syn of jng_sound is + + -- clocks, reset + signal clock_12n : std_logic; + signal clock_div1 : std_logic_vector(8 downto 0) := (others =>'0'); + signal clock_div2 : std_logic_vector(4 downto 0) := (others =>'0'); + signal clock_500K : std_logic; + signal ayx_clock : std_logic; + signal reset_n : std_logic; + + -- cpu signals + signal cpu_addr : std_logic_vector(23 downto 0); + signal cpu_di : std_logic_vector( 7 downto 0); + signal cpu_di_dec : std_logic_vector( 7 downto 0); + signal cpu_do : std_logic_vector( 7 downto 0); + signal cpu_rw_n : std_logic; + signal cpu_nmi_n : std_logic; + signal cpu_irq_n : std_logic; + signal cpu_sync : std_logic; + + -- program rom signals + signal prog_rom_cs : std_logic; + signal prog_rom_do : std_logic_vector(7 downto 0); + + -- working ram signals + signal wram_cs : std_logic; + signal wram_we : std_logic; + signal wram_do : std_logic_vector(7 downto 0); + + -- sound req management + signal nmi_reg : std_logic; + signal nmi_reg_cs : std_logic; + signal nmi_reg_we : std_logic; + signal sound_code : std_logic_vector(7 downto 0); + signal sound_code_cs : std_logic; + + -- ay-3-8910 signal + signal ay1_bc1 : std_logic; + signal ay1_bdir : std_logic; + signal ay1_audio_chan : std_logic_vector(1 downto 0); + signal ay1_audio_muxed: std_logic_vector(7 downto 0); + signal ay1_chan_a: std_logic_vector(7 downto 0); + signal ay1_chan_b: std_logic_vector(7 downto 0); + signal ay1_chan_c: std_logic_vector(7 downto 0); + + signal ay2_bc1 : std_logic; + signal ay2_bdir : std_logic; + signal ay2_audio_chan : std_logic_vector(1 downto 0); + signal ay2_audio_muxed: std_logic_vector(7 downto 0); + signal ay2_chan_a: std_logic_vector(7 downto 0); + signal ay2_chan_b: std_logic_vector(7 downto 0); + signal ay2_chan_c: std_logic_vector(7 downto 0); + + -- digital filtering AY2 channel A + signal uin : integer range -256 to 255; + signal u3 : integer range -32768 to 32767; + signal u4 : integer range -32768 to 32767; + signal du3 : integer range -32768*4096 to 32767*4096; + signal du4 : integer range -32768*4096 to 32767*4096; + signal uout : integer range -32768 to 32767; + signal uout_lim : integer range -128 to 127; + +begin + +process (clock_12, cpu_sync) +begin + if rising_edge(clock_12) then + if cpu_sync = '1' then + dbg_cpu_addr <= cpu_addr(15 downto 0); + end if; + end if; +end process; + +reset_n <= not reset; +clock_12n <= not clock_12; + +process (clock_12, reset) + begin + if reset='1' then + clock_div1 <= (others => '0'); + clock_div2 <= (others => '0'); + else + if rising_edge(clock_12) then + if clock_div1 = "111111111" then -- divide by 512 (23.437kHz) + clock_div1 <= "000000000"; + else + clock_div1 <= clock_div1 + '1'; + end if; + if clock_div2 = "10111" then -- divide by 24 + clock_div2 <= "00000"; + else + clock_div2 <= clock_div2 + '1'; + end if; + end if; + end if; +end process; + +clock_500K <= clock_div2(4); --12MHz/24 = 500kHz +ayx_clock <= clock_div1(2); --12MHz/8 = 1.5MHz + +--static ADDRESS_MAP_START( audio_map, AS_PROGRAM, 8, btime_state ) +-- AM_RANGE(0x0000, 0x03ff) AM_MIRROR(0x1c00) AM_RAM AM_SHARE("audio_rambase") +-- AM_RANGE(0x2000, 0x3fff) AM_DEVWRITE("ay1", ay8910_device, data_w) +-- AM_RANGE(0x4000, 0x5fff) AM_DEVWRITE("ay1", ay8910_device, address_w) +-- AM_RANGE(0x6000, 0x7fff) AM_DEVWRITE("ay2", ay8910_device, data_w) +-- AM_RANGE(0x8000, 0x9fff) AM_DEVWRITE("ay2", ay8910_device, address_w) +-- AM_RANGE(0xa000, 0xbfff) AM_READ(audio_command_r) +-- AM_RANGE(0xc000, 0xdfff) AM_WRITE(audio_nmi_enable_w) +-- AM_RANGE(0xe000, 0xefff) AM_MIRROR(0x1000) AM_ROM +--ADDRESS_MAP_END + +-- chip select +wram_cs <= '1' when cpu_addr(15 downto 13) = "000" else '0'; -- working ram 0000-07ff .. 1fff +ay1_bc1 <= '1' when cpu_addr(15 downto 13) = "010" else '0'; +ay1_bdir <= '1' when cpu_addr(15 downto 13) = "001" or ay1_bc1 = '1' else '0'; +ay2_bc1 <= '1' when cpu_addr(15 downto 13) = "100" else '0'; +ay2_bdir <= '1' when cpu_addr(15 downto 13) = "011" or ay2_bc1 = '1' else '0'; +sound_code_cs <= '1' when cpu_addr(15 downto 13) = "101" else '0'; +nmi_reg_cs <= '1' when cpu_addr(15 downto 13) = "110" else '0'; +prog_rom_cs <= '1' when cpu_addr(15 downto 13) = "111" else '0'; + +-- write enable +wram_we <= '1' when wram_cs = '1' and cpu_rw_n = '0' else '0'; +nmi_reg_we <= '1' when nmi_reg_cs = '1' and cpu_rw_n = '0' else '0'; + +-- cpu di mux +cpu_di <= wram_do when wram_cs = '1' else + prog_rom_do when prog_rom_cs = '1' else + sound_code when sound_code_cs = '1' else + X"FF"; + +-- regsiter sound code and irq management +process (clock_12) +begin + if rising_edge(clock_12) then + if sound_req = '1' then + sound_code <= sound_code_in; + cpu_irq_n <= '0'; + end if; + if sound_code_cs = '1' then + cpu_irq_n <= '1'; + end if; + end if; +end process; + +-- nmi autorisation management +process (reset, clock_12) +begin + if reset = '1' then + nmi_reg <= '0'; + else + if rising_edge(clock_12) then + if nmi_reg_we = '1' then + nmi_reg <= cpu_do(0); + end if; + end if; + end if; +end process; + +-- nmi +cpu_nmi_n <= '0' when nmi_reg = '1' and sound_timing = '1' else '1'; + +-- demux AY chips output +process (ayx_clock) +begin + if rising_edge(ayx_clock) then + if ay1_audio_chan = "00" then ay1_chan_a <= ay1_audio_muxed; end if; + if ay1_audio_chan = "01" then ay1_chan_b <= ay1_audio_muxed; end if; + if ay1_audio_chan = "10" then ay1_chan_c <= ay1_audio_muxed; end if; + if ay2_audio_chan = "00" then ay2_chan_a <= ay2_audio_muxed; end if; + if ay2_audio_chan = "01" then ay2_chan_b <= ay2_audio_muxed; end if; + if ay2_audio_chan = "10" then ay2_chan_c <= ay2_audio_muxed; end if; + end if; +end process; + +-- AOP Rauch passe bande filter +-- +-- ----------o------------ +-- u4^ | | | +-- | --- C4 | | R5 | +-- | --- | | | +-- | | C3 | | +-- --| R1 |----o----||---o------|\ | +-- ^ | ------> u3 | \__o--- +-- | | | / ^ +-- |uin | | R2 --|/ | +-- | | | | | uout +-- | | | | +-- ------------o--------------o---------- +-- +-- +-- i1 = (sin+u3)/R1 +-- i2 = -u3/R2 +-- i3 = (u4-u3)/R5 +-- i4 = i2-i1-i3 +-- +-- u3(t+dt) = u3(t) + i3(t)*dt/C3; +-- u4(t+dt) = u4(t) + i4(t)*dt/C4; + +-- uout = u4-u3 + +-- R1 = 5000; +-- R2 = 10000; +-- C3 = 0.068e-6; +-- C4 = 0.068e-6; +-- R5 = 47000; +-- +-- dt = 1/f_ech = 1/23437 +-- dt/C3 = dt/C4 = 627 +-- +-- (i3(t)*dt/C3)*8192 = du3*8192 = ((u4-u3)/47000*627)*8192 +-- = (u4-u3)*109 +-- +-- (i4(t)*dt/C4)*8192 = du4*8192 = (-u3/10000 -(uin+u3)/5000 -(u4-u3)/47000)*627*8192 +-- = -u3(514+1027-109) - uin*1027 - u4*109 +-- = -(u4*109 + u3*1432 + uin*1027) +-- + +-- down sample to 23.437kHz and filter AY2 channel A +uin <= to_integer(unsigned(ay2_chan_a)); + +process (clock_12) +begin + if rising_edge(clock_12) then + + if clock_div1 = "000000000" then + du3 <= u4*109 - u3*109; + du4 <= u4*109 + u3*1432 + uin*1027*16; -- add gain(16) to uin + end if; + + if clock_div1 = "000000001" then + u3 <= u3 + du3/8192; + u4 <= u4 - du4/8192; + end if; + + if clock_div1 = "000000010" then + uout <= (u4 - u3) / 8; -- adjust output gain + end if; + + -- limit signed dynamique before return to unsigned + if clock_div1 = "000000011" then + if uout > 127 then + uout_lim <= 127; + elsif uout < -127 then + uout_lim <= -127; + else + uout_lim <= uout; + end if; + end if; + + if clock_div1 = "000000100" then + + audio_out <= ("000"&ay1_chan_a(7 downto 0)) + + ("000"&ay1_chan_b(7 downto 0)) + + ("000"&ay1_chan_c(7 downto 0)) + + ("000"&std_logic_vector(to_unsigned(uout_lim+128,8)))+ + ("000"&ay2_chan_b(7 downto 0)) + + ("000"&ay2_chan_c(7 downto 0)); + end if; + + end if; +end process; + +--------------------------- +-- components +--------------------------- + +cpu_inst : entity work.T65 +port map +( + Mode => "00", -- 6502 + Res_n => reset_n, + Enable => '1', + Clk => clock_500K, + Rdy => '1', + Abort_n => '1', + IRQ_n => cpu_irq_n, + NMI_n => cpu_nmi_n, + SO_n => '1',--cpu_so_n, + R_W_n => cpu_rw_n, + Sync => cpu_sync, -- open + EF => open, + MF => open, + XF => open, + ML_n => open, + VP_n => open, + VDA => open, + VPA => open, + A => cpu_addr, + DI => cpu_di, + DO => cpu_do +); + +-- working ram +wram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 11) +port map( + clk => clock_12n, + we => wram_we, + addr => cpu_addr(10 downto 0), + d => cpu_do, + q => wram_do +); + +-- program rom +program_rom: entity work.jng_snd_rom +port map( + clk => clock_12n, + addr => cpu_addr(11 downto 0), + data => prog_rom_do +); + +-- AY-3-8910 #1 +ay_3_8910_1 : entity work.YM2149 +port map( + -- data bus + I_DA => cpu_do, -- in std_logic_vector(7 downto 0); + O_DA => open, -- out std_logic_vector(7 downto 0); + O_DA_OE_L => open, -- out std_logic; + -- control + I_A9_L => '0', -- in std_logic; + I_A8 => '1', -- in std_logic; + I_BDIR => ay1_bdir, -- in std_logic; + I_BC2 => '1', -- in std_logic; + I_BC1 => ay1_bc1, -- in std_logic; + I_SEL_L => '1', -- in std_logic; + + O_AUDIO => ay1_audio_muxed, -- out std_logic_vector(7 downto 0); + O_CHAN => ay1_audio_chan, -- out std_logic_vector(1 downto 0); + + -- port a + I_IOA => X"00", -- in std_logic_vector(7 downto 0); + O_IOA => open, -- out std_logic_vector(7 downto 0); + O_IOA_OE_L => open, -- out std_logic; + -- port b + I_IOB => X"00", -- in std_logic_vector(7 downto 0); + O_IOB => open, -- out std_logic_vector(7 downto 0); + O_IOB_OE_L => open, -- out std_logic; + + ENA => '1', -- in std_logic; -- clock enable for higher speed operation + RESET_L => reset_n, -- in std_logic; + CLK => ayx_clock -- in std_logic -- note 6 Mhz +); + +-- AY-3-8910 #2 +ay_3_8910_2 : entity work.YM2149 +port map( + -- data bus + I_DA => cpu_do, -- in std_logic_vector(7 downto 0); + O_DA => open, -- out std_logic_vector(7 downto 0); + O_DA_OE_L => open, -- out std_logic; + -- control + I_A9_L => '0', -- in std_logic; + I_A8 => '1', -- in std_logic; + I_BDIR => ay2_bdir, -- in std_logic; + I_BC2 => '1', -- in std_logic; + I_BC1 => ay2_bc1, -- in std_logic; + I_SEL_L => '1', -- in std_logic; + + O_AUDIO => ay2_audio_muxed, -- out std_logic_vector(7 downto 0); + O_CHAN => ay2_audio_chan, -- out std_logic_vector(1 downto 0); + + -- port a + I_IOA => (others => '0'), -- in std_logic_vector(7 downto 0); + O_IOA => open, -- out std_logic_vector(7 downto 0); + O_IOA_OE_L => open, -- out std_logic; + -- port b + I_IOB => (others => '0'), -- in std_logic_vector(7 downto 0); + O_IOB => open, -- out std_logic_vector(7 downto 0); + O_IOB_OE_L => open, -- out std_logic; + + ENA => '1', --cpu_ena, -- in std_logic; -- clock enable for higher speed operation + RESET_L => reset_n, -- in std_logic; + CLK => ayx_clock -- in std_logic -- note 6 Mhz +); + + +end SYN; diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jng_sprite.v b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jng_sprite.v new file mode 100644 index 00000000..c84bdd88 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jng_sprite.v @@ -0,0 +1,154 @@ + +module jng_sprite +( + input VCLKx4, + input HBLK, + + input [8:0] HPOS, + input [8:0] VPOS, + + output reg [10:0] SPRAADRS, + input [15:0] SPRADATA, + + output [3:0] ARAMADRS, + input [7:0] ARAMDATA, + + output [11:0] SPCHRADR, + input [7:0] SPCHRDAT, + + output [7:0] DROMAD, + input [7:0] DROMDT, + + output reg [8:0] SPCOL +); + +reg [1:0] clkcnt; +always @( posedge VCLKx4 ) clkcnt<=clkcnt+1; +wire VCLKx2 = clkcnt[0]; +wire VCLK = clkcnt[1]; + +wire SIDE = VPOS[0]; + + +reg [19:0] SPATR0; +reg [36:0] SPATRS[0:31]; +reg [3:0] WWADR; +reg bHit; + +assign ARAMADRS = SPRAADRS[3:0]; + + +reg [7:0] WRADR; +reg [8:0] HPOSW; +reg [8:0] SPWCL; + +wire [36:0] SPA = SPATRS[{~SIDE,WRADR[7:4]}]; + +wire [3:0] SH = WRADR[3:0]+4'h4; +wire [3:0] SV = SPA[35:32]; + +wire [2:0] SPFY = { 3{SPA[1]} }; +wire [1:0] SPFX = { 1'b0, SPA[0] }; +wire [5:0] SPPL = SPA[29:24]; + +assign SPCHRADR = { SPA[7:2], ( SV[3] ^ SPA[1] ), ( SH[3:2] ^ SPFX ), ( SV[2:0] ^ SPFY ) }; +wire [7:0] CHRO = SPCHRDAT; + + +wire [8:0] YM = ( SPRADATA[15:8] + 8'h10 ) + VPOS[7:0]; + +assign DROMAD = { 1'b0, (~SPA[19:17]), SPA[33:32], WRADR[3:2] }; + +always @ ( posedge VCLKx2 ) begin + + // in H-BLANK + if ( HBLK ) begin + + // Sprite V-hit check & list-up + if ( SPRAADRS < 10'h20 ) begin + if ( SPRAADRS[0] ) begin + if ( bHit ) begin + SPATRS[{SIDE,WWADR}] <= { 1'b1, SPATR0[3:0], SPRADATA, SPATR0[19:4] }; + WWADR <= WWADR+1; + end + end + else begin + if ( YM[7:4] == 4'b1111 ) begin + bHit <= 1; + SPATR0 <= { SPRADATA, YM[3:0] }; + end + else bHit <= 0; + end + SPRAADRS <= ( SPRAADRS == 10'h1F ) ? 10'h34 : (SPRAADRS+1); + end + // Rader-dot V-hit check & list-up + else begin + if ( SPRAADRS < 10'h40 ) begin + if ( YM[7:2] == 6'b111111 ) begin + SPATRS[{SIDE,WWADR}] <= { 1'b0, 2'b00, YM[1:0], 8'h0, ARAMDATA, SPRADATA }; + WWADR <= WWADR+1; + end + SPRAADRS <= SPRAADRS+1; + end + else SPATRS[{SIDE,WWADR}] <= 0; + end + + if ( SPA ) begin + // Rend Sprite + if ( SPA[36] ) begin + HPOSW <= ( WRADR[3:0] ) ? (HPOSW+1) : { SPA[31], SPA[23:16] }; + case ( SH[1:0] ^ {2{SPFX[0]}} ) + 2'b00: SPWCL <= { 1'b0, SPPL, CHRO[7], CHRO[3] }; + 2'b01: SPWCL <= { 1'b0, SPPL, CHRO[6], CHRO[2] }; + 2'b10: SPWCL <= { 1'b0, SPPL, CHRO[5], CHRO[1] }; + 2'b11: SPWCL <= { 1'b0, SPPL, CHRO[4], CHRO[0] }; + endcase + WRADR <= WRADR+1; + end + // Rend Rader-dot + else begin + HPOSW <= ( WRADR[3:0] ) ? (HPOSW+1) : ({ (~SPA[16]), SPA[7:0] }); + SPWCL <= ( DROMDT[1:0] != 2'b11 ) ? { 1'b1, 6'b000100, DROMDT[1:0] } : 0; + WRADR <= WRADR+4; + end + end + else SPWCL <= 0; + + end + + // in H-DISP + else begin + SPRAADRS <= 10'h14; + WWADR <= 0; + WRADR <= 0; + SPWCL <= 0; + end + +end + + +reg [9:0] radr0=0,radr1=1; +wire [8:0] SPCOLi; +dpram #( + .widthad_a(10), + .width_a(9)) +linebuffer( + .address_a({SIDE,HPOS}), + .address_b({~SIDE,HPOSW}), + .clock_a(VCLKx2), + .clock_b(VCLKx2), + .data_a(9'h0), + .data_b(SPWCL), + .wren_a(radr0==radr1), + .wren_b((SPWCL[0]|SPWCL[1])), + .q_a(SPCOLi), + .q_b() + ); + +always @(posedge VCLK) radr0 <= {SIDE,HPOS}; +always @(negedge VCLK) begin + if (radr0!=radr1) SPCOL <= SPCOLi; + radr1 <= radr0; +end + +endmodule diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jng_top.v b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jng_top.v new file mode 100644 index 00000000..aa6b9dca --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jng_top.v @@ -0,0 +1,195 @@ +/************************************************************** + FPGA Jungler (Main part) +***************************************************************/ +module jng_top +( + input RESET, // RESET + input CLK24M, // Clock 24.576MHz + output hsync, + output vsync, + output hblank, + output vblank, + output [2:0] r, + output [2:0] g, + output [1:0] b, + output [10:0] SND, // Sound (unsigned PCM) + input [7:0] DSW1, // DipSW + input [7:0] DSW2, // DipSW + input [7:0] CTR1, // Controler (Negative logic) + input [7:0] CTR2 +); + + +//-------------------------------------------------- +// Clock Generators +//-------------------------------------------------- +reg [2:0] _CCLK; +always @( posedge CLK24M ) _CCLK <= _CCLK+1; + +wire CLK = CLK24M; // 24MHz +wire CCLKx4 = _CCLK[0]; // CPU CLOCKx4 : 12.0MHz +wire CCLK = _CCLK[2]; // CPU CLOCK : 3.0MHz + + +//-------------------------------------------------- +// CPU +//-------------------------------------------------- +// memory access signals +wire rd, wr, me, ie, rf, m1; +wire [15:0] ad; +wire [7:0] odt, viddata; + +wire mx = rf & (~me); +wire mr = mx & (~rd); +wire mw = mx & (~wr); + +// interrupt signal/vector generator & other latches +reg inte = 1'b0; +reg intl = 1'b0; +reg [7:0] intv = 8'h0; + + +reg out1r = 1'b0; +reg out2r = 1'b0; +reg out3r = 1'b0; +reg sonr = 1'b0;//sound On + +wire vblk = (VP==224)&(HP<=8); + +wire lat_Wce = ( ad[15:4] == 12'hA18 ) & mw; + +wire sndw = ( lat_Wce & ( ad[3:0] == 4'h0 ) ); +wire iewr = ( lat_Wce & ( ad[3:0] == 4'h1 ) ); +wire mute = ( lat_Wce & ( ad[3:0] == 4'h1 ) );//mute +wire flip = ( lat_Wce & ( ad[3:0] == 4'h3 ) );//flip +wire out1w = ( lat_Wce & ( ad[3:0] == 4'h4 ) ); +//wire out2w = ( lat_Wce & ( ad[3:0] == 4'h5 ) );//NOP +wire out3w = ( lat_Wce & ( ad[3:0] == 4'h6 ) ); +//wire starw = ( lat_Wce & ( ad[3:0] == 4'h7 ) );//not used +wire iowr = ( (~wr) & (~ie) & m1 ); + + +always @( posedge CCLK ) begin + if ( iowr ) intv <= odt; + if ( vblk ) intl <= 1'b1; + if ( iewr ) begin + inte <= odt[0]; + intl <= 1'b0; + end + if ( sndw ) sonr <= odt[0]; + if ( out1w ) out1r <= odt[0]; +// if ( out2w ) out2r <= odt[0]; + if ( out3w ) out3r <= odt[0]; +end + +wire irq_n = ~( intl & inte ); + + +// address decoders +wire rom_Rce = ( ( ad[15] == 1'b0 ) & mr ); // $0000-$7FFF(R) +wire ram_Rce = ( ( ad[15:11] == 5'b1001_1 ) & mr ); // $9800-$9FFF(R) +wire ram_Wce = ( ( ad[15:11] == 5'b1001_1 ) & mw ); // $9800-$9FFF(W) +wire inp_Rce = ( ( ad[15:12] == 4'b1010 ) & mr ); // $A000-$AFFF(R) +wire snd_Wce = ( ( ad[15:8] == 8'b1010_0001 ) & mw ); // $A100-$A1FF(W) +wire vid_Rce; + + +wire [7:0] romdata; +jng_prg_rom jng_prg_rom ( + .clk(CCLK), + .addr(ad[13:0]), + .data(romdata) + ); + +// Work RAM (2KB) +wire [7:0] ramdata; +GSPRAM #(11,8) workram( + .CL(CCLK), + .AD(ad[10:0]), + .WE(ram_Wce), + .DI(odt), + .DO(ramdata) + ); + + +// Controler/DipSW input +wire [7:0] in0data = CTR1; +wire [7:0] in1data = CTR2; +wire [7:0] in2data = DSW1; +wire [7:0] in3data = DSW2; +wire [7:0] inpdata = (ad[8:7] == 2'b11) ? in3data : (ad[8:7] == 2'b10) ? in2data : (ad[8:7] == 2'b01) ? in1data : in0data; +// databus selector +wire [7:0] romd = rom_Rce ? romdata : 8'h00; +wire [7:0] ramd = ram_Rce ? ramdata : 8'h00; +wire [7:0] vidd = vid_Rce ? viddata : 8'h00; +wire [7:0] inpd = inp_Rce ? inpdata : 8'h00; +wire [7:0] irqv = ( (~m1) & (~ie) ) ? intv : 8'h00; + +wire [7:0] idt = romd | ramd | irqv | vidd | inpd; + + +T80s z80( + .RESET_n(~RESET), + .CLK_n(CCLK), + .WAIT_n(1'b1), + .INT_n(1'b1), + .NMI_n(irq_n), + .BUSRQ_n(1'b1), + .DI(idt), + .M1_n(m1), + .MREQ_n(me), + .IORQ_n(ie), + .RD_n(rd), + .WR_n(wr), + .RFSH_n(rf), + .HALT_n(), + .BUSAK_n(), + .A(ad), + .DO(odt) + ); + +//-------------------------------------------------- +// VIDEO +//-------------------------------------------------- +wire [8:0] HP; +wire [8:0] VP; +wire PCLK; + +jng_video video( + .VCLKx4(CLK), + .HPOS(HP+3), + .VPOS(VP+1), + .PCLK(PCLK), + .POUT({b,g,r}), + .CPUCLK(CCLK), + .CPUADDR(ad), + .CPUDI(odt), + .CPUDO(viddata), + .CPUME(mx), + .CPUWE(mw), + .CPUDT(vid_Rce) + ); + +jng_hvgen hvgen( + .HPOS(HP), + .VPOS(VP), + .PCLK(PCLK), + .HBLK(hblank), + .VBLK(vblank), + .HSYN(hsync), + .VSYN(vsync) + ); + +//-------------------------------------------------- +// SOUND //ToDo +//-------------------------------------------------- +jng_sound jng_sound( + .clock_12(CCLKx4), + .reset(RESET), + .sound_req(sonr), + .sound_code_in(odt), + .sound_timing(snd_Wce), + .audio_out(SND) + ); + +endmodule diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jng_video.v b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jng_video.v new file mode 100644 index 00000000..e455df1d --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jng_video.v @@ -0,0 +1,194 @@ +module jng_video +( + input VCLKx4, // 24.976MHz + + input [8:0] HPOS, + input [8:0] VPOS, + output PCLK, + output reg [7:0] POUT, + + input CPUCLK, + input [15:0] CPUADDR, + input [7:0] CPUDI, + output [7:0] CPUDO, + input CPUME, + input CPUWE, + output CPUDT +); + +//----------------------------------------- +// Clock generators +//----------------------------------------- +reg VCLKx2; +always @( posedge VCLKx4 ) begin + VCLKx2 <= ~VCLKx2; +end + +reg VCLK; +always @( posedge VCLKx2 ) begin + VCLK <= ~VCLK; +end + +//----------------------------------------- +// BG scroll registers +//----------------------------------------- +reg [7:0] BGHSCR; +reg [7:0] BGVSCR; + +always @ ( posedge CPUCLK ) begin + if ( ( CPUADDR == 16'hA130 ) & CPUME & CPUWE ) begin + BGHSCR <= CPUDI-3; + end + if ( ( CPUADDR == 16'hA140 ) & CPUME & CPUWE ) begin + BGVSCR <= CPUDI; + end +end + + +//----------------------------------------- +// HV +//----------------------------------------- +wire [8:0] BGHPOS = HPOS + { 1'b0, BGHSCR }; +wire [8:0] BGVPOS = VPOS + { 1'b0, BGVSCR }; + +wire oHB = ( HPOS > 288 ) ? 1 : 0; +wire oVB = ( VPOS > 224 ) ? 1 : 0; + + +//---------------------------------------- +// VideoRAM Scanner +//---------------------------------------- +wire BF = ( HPOS >= 224 ); +wire [8:0] HP = BF ? HPOS : BGHPOS; +wire [8:0] VP = ( BF ? VPOS : BGVPOS ) + 9'h0F; + +wire [10:0] SPRAADRS; +wire [3:0] ARAMADRS; + +reg [10:0] VRAMADRS; +always @ ( HPOS ) begin + VRAMADRS <= oHB ? + SPRAADRS : + BF ? { 1'b0, VP[7:3], 2'b00, HP[5:3] } : { 1'b1, VP[7:3], HP[7:3] }; +end + +wire [7:0] CHRC; +wire [7:0] ATTR; +wire [7:0] ARDT; + +wire [7:0] V0DO, V1DO; + +wire CEV0 = ( ( CPUADDR[15:12] == 4'b1000 ) & (~CPUADDR[11]) ) & CPUME; +wire CEV1 = ( ( CPUADDR[15:12] == 4'b1000 ) & CPUADDR[11] ) & CPUME; +wire CEAT = ( CPUADDR[15:4] == 12'b1010_0000_0000 ) & CPUME; + +wire [7:0] DTV0 = CEV0 ? V0DO : 8'h00; +wire [7:0] DTV1 = CEV1 ? V1DO : 8'h00; + +assign CPUDO = DTV0 | DTV1; +assign CPUDT = ( ~CPUWE ) & ( CEV0 | CEV1 ); + +GDPRAM #(11,8) vram0( VCLKx4, VRAMADRS, CHRC, CPUCLK, CPUADDR[10:0], ( CPUWE & CEV0 ), CPUDI, V0DO ); + +GDPRAM #(11,8) vram1( VCLKx4, VRAMADRS, ATTR, CPUCLK, CPUADDR[10:0], ( CPUWE & CEV1 ), CPUDI, V1DO ); + +GDPRAM #(4,8) aram0( VCLKx4, ARAMADRS, ARDT, CPUCLK, CPUADDR[3:0], ( CPUWE & CEAT ), CPUDI ); + +wire BGF = ATTR[5]; + + +//---------------------------------------- +// BG/Sprite chip data reader +//---------------------------------------- +wire BGFX = ATTR[6]; +wire [2:0] BGFY = { ATTR[7], ATTR[7], ATTR[7] }; + +wire [11:0] SPCHRADR; +wire [11:0] CHRA = oHB ? SPCHRADR : { CHRC, ( HP[2] ^ BGFX ), ( VP[2:0] ^ BGFY ) }; + +wire [7:0] CHRO; +jng_chr_rom chrrom( + .clk(VCLKx4), + .addr(CHRA), + .data(CHRO) +); + +//---------------------------------------- +// Rader-dot chip ROM +//---------------------------------------- +wire [7:0] DROMAD; +wire [7:0] DROMDT; +jng_dot_rom dotrom( + .clk(VCLKx4), + .addr(DROMAD), + .data(DROMDT) + ); + +//---------------------------------------- +// BG/FG scanline generator +//---------------------------------------- +wire [5:0] BGPL = ATTR[5:0]; +reg [7:0] BGCOL; + +always @ ( posedge VCLK ) begin + case ( HP[1:0]^{2{BGFX}} ) + 2'b00: BGCOL <= { BGPL, CHRO[4], CHRO[0] }; + 2'b01: BGCOL <= { BGPL, CHRO[5], CHRO[1] }; + 2'b10: BGCOL <= { BGPL, CHRO[6], CHRO[2] }; + 2'b11: BGCOL <= { BGPL, CHRO[7], CHRO[3] }; + endcase +end + + +//---------------------------------------- +// Sprite Engine +//---------------------------------------- +wire [8:0] SPCOL; +jng_sprite speng( + .VCLKx4(VCLKx4), + .HBLK(oHB), + .HPOS(HPOS), + .VPOS(VPOS), + .SPRAADRS(SPRAADRS), + .SPRADATA({ ATTR, CHRC }), + .ARAMADRS(ARAMADRS), + .ARAMDATA(ARDT), + .SPCHRADR(SPCHRADR), + .SPCHRDAT(CHRO), + .DROMAD(DROMAD), + .DROMDT(DROMDT), + .SPCOL(SPCOL) + ); + + +//---------------------------------------- +// Color mixer +//---------------------------------------- +wire bBGOPAQUE = ( ( BF | BGF ) & (~SPCOL[8]) ); +wire bSPTRANSP = ( SPCOL[1:0] == 2'b00 ); + +wire [7:0] OUTCOL = ( bBGOPAQUE | bSPTRANSP ) ? BGCOL : SPCOL[7:0]; +wire [3:0] CLUT; +jng_col_rom colrom( + .clk(~VCLKx4), + .addr(OUTCOL), + .data(CLUT) + ); + +wire [4:0] PALA = SPCOL[8] ? SPCOL[4:0] : { 1'b0, CLUT }; +wire [7:0] PALO; + +jng_pal_rom palrom( + .clk(VCLKx4), + .addr(PALA), + .data(PALO) + ); + +//---------------------------------------- +// Color output +//---------------------------------------- +always @ ( posedge PCLK ) POUT <= (oHB|oVB) ? 8'h0 : PALO; +assign PCLK = VCLK; + + +endmodule diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jungler_mist.sv b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jungler_mist.sv new file mode 100644 index 00000000..ef65a4ba --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jungler_mist.sv @@ -0,0 +1,175 @@ +module jungler_mist ( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "Jungler;;", + "O2,Rotate,Off,On;", + "O34,Scanlines,None,CRT 25%,CRT 50%,CRT 75%;", + "O5,Test,Off,On;", + "O6,Service,Off,On;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + +assign LED = 1; +assign AUDIO_R = AUDIO_L; + +wire clock_24, clock_12; +pll pll( + .inclk0(CLOCK_27), + .c0(clock_24)//24.576MHz + ); + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoublerD; +wire ypbpr; +wire [10:0] audio; +wire hs, vs; +wire hb, vb; +wire blankn = ~(hb | vb); +wire [2:0] r, g; +wire [1:0] b; +wire key_strobe; +wire key_pressed; +wire [7:0] key_code; + + +wire [7:0] iDSW1 = ~{ m_down1,"0000000"}; +wire [7:0] iDSW2 = ~{ status[5], 1'b1, "000", "000"};//Test,Cab,CoinB,CoinA +wire [7:0] iCTR1 = ~{ btn_coin, 1'b0, m_right1, m_left1, m_fire1, status[6], 1'b0, m_up2}; +wire [7:0] iCTR2 = ~{ btn_one_player, btn_two_players, m_left2, m_right2, m_fire2, 1'b0, m_down2, m_up1}; + + + +jng_top jng_top( + .RESET(status[0] | status[6] | buttons[1]), + .CLK24M(clock_24), + .hsync(hs), + .vsync(vs), + .hblank(hb), + .vblank(vb), + .r(r), + .g(g), + .b(b), + .SND(audio), + .DSW1(iDSW1), + .DSW2(iDSW2), + .CTR1(iCTR1), + .CTR2(iCTR2), + .LAMP() + ); + + +mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video( + .clk_sys ( clock_24 ), + .SPI_SCK ( SPI_SCK ), + .SPI_SS3 ( SPI_SS3 ), + .SPI_DI ( SPI_DI ), + .R ( blankn ? r : 0 ), + .G ( blankn ? g : 0 ), + .B ( blankn ? {b,1'b0} : 0 ), + .HSync ( hs ), + .VSync ( vs ), + .VGA_R ( VGA_R ), + .VGA_G ( VGA_G ), + .VGA_B ( VGA_B ), + .VGA_VS ( VGA_VS ), + .VGA_HS ( VGA_HS ), + .rotate ({1'b1,status[2]} ), + .scandoubler_disable( scandoublerD ), + .scanlines ( status[4:3] ), + .ypbpr ( ypbpr ) + ); + +user_io #(.STRLEN(($size(CONF_STR)>>3)))user_io( + .clk_sys (clock_24 ), + .conf_str (CONF_STR ), + .SPI_CLK (SPI_SCK ), + .SPI_SS_IO (CONF_DATA0 ), + .SPI_MISO (SPI_DO ), + .SPI_MOSI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable (scandoublerD ), + .ypbpr (ypbpr ), + .key_strobe (key_strobe ), + .key_pressed (key_pressed ), + .key_code (key_code ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) + ); + +dac #(.C_bits(16))dac( + .clk_i(clock_24), + .res_n_i(1), + .dac_i({audio,audio[4:0]}), + .dac_o(AUDIO_L) + ); + +wire m_up1 = btn_up | joystick_0[3]; +wire m_down1 = btn_down | joystick_0[2]; +wire m_left1 = btn_left | joystick_0[1]; +wire m_right1 = btn_right | joystick_0[0]; +wire m_fire1 = btn_fire1 | joystick_0[4]; + +wire m_up2 = btn_up | joystick_1[3]; +wire m_down2 = btn_down | joystick_1[2]; +wire m_left2 = btn_left | joystick_1[1]; +wire m_right2 = btn_right | joystick_1[0]; +wire m_fire2 = btn_fire1 | joystick_1[4]; + + +reg btn_one_player = 0; +reg btn_two_players = 0; +reg btn_left = 0; +reg btn_right = 0; +reg btn_down = 0; +reg btn_up = 0; +reg btn_fire1 = 0; +//reg btn_fire2 = 0; +//reg btn_fire3 = 0; +reg btn_coin = 0; + +always @(posedge clock_24) begin + reg old_state; + old_state <= key_strobe; + if(old_state != key_strobe) begin + case(key_code) + 'h75: btn_up <= key_pressed; // up + 'h72: btn_down <= key_pressed; // down + 'h6B: btn_left <= key_pressed; // left + 'h74: btn_right <= key_pressed; // right + 'h76: btn_coin <= key_pressed; // ESC + 'h05: btn_one_player <= key_pressed; // F1 + 'h06: btn_two_players <= key_pressed; // F2 + // 'h14: btn_fire3 <= key_pressed; // ctrl + // 'h11: btn_fire2 <= key_pressed; // alt + 'h29: btn_fire1 <= key_pressed; // Space + endcase + end +end + + +endmodule diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/pll.qip b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/pll.qip new file mode 100644 index 00000000..afd958be --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/pll.v b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/pll.v new file mode 100644 index 00000000..70025276 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/pll.v @@ -0,0 +1,309 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.4 Build 182 03/12/2014 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2014 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + inclk0, + c0, + locked); + + input inclk0; + output c0; + output locked; + + wire [4:0] sub_wire0; + wire sub_wire2; + wire [0:0] sub_wire5 = 1'h0; + wire [0:0] sub_wire1 = sub_wire0[0:0]; + wire c0 = sub_wire1; + wire locked = sub_wire2; + wire sub_wire3 = inclk0; + wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; + + altpll altpll_component ( + .inclk (sub_wire4), + .clk (sub_wire0), + .locked (sub_wire2), + .activeclock (), + .areset (1'b0), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 78, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 71, + altpll_component.clk0_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_UNUSED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "78" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.576923" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "71" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.57600000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "78" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "71" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/rams.v b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/rams.v new file mode 100644 index 00000000..4d579578 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/rams.v @@ -0,0 +1,64 @@ + + + +module GSPRAM #(parameter AW,parameter DW) +( + input CL, + input [(AW-1):0] AD, + input WE, + input [(DW-1):0] DI, + output reg [(DW-1):0] DO +); + +reg [(DW-1):0] core[0:((2**AW)-1)]; + +always @(posedge CL) begin + DO <= core[AD]; + if (WE) core[AD] <= DI; +end + +endmodule + + +module GDPRAM #(parameter AW,parameter DW) +( + input CL0, + input [(AW-1):0] AD0, + output reg [(DW-1):0] DO0, + + input CL1, + input [(AW-1):0] AD1, + input WE1, + input [(DW-1):0] DI1, + output reg [(DW-1):0] DO1 +); + +reg [(DW-1):0] core[0:((2**AW)-1)]; + +always @(posedge CL0) DO0 <= core[AD0]; +always @(posedge CL1) begin DO1 <= core[AD1]; if (WE1) core[AD1] <= DI1; end + +endmodule + +/* +module GLINEBUF #(parameter AW,parameter DW) +( + input CL0, + input [(AW-1):0] AD0, + input WE0, + output reg [(DW-1):0] DO0, + + input CL1, + input [(AW-1):0] AD1, + input WE1, + input [(DW-1):0] DI1 +); + +reg [(DW-1):0] core[0:((2**AW)-1)]; + +always @(posedge CL0) begin DO0 <= core[AD0]; if (WE0) core[AD0] <= 0; end +always @(posedge CL1) if (WE1) core[AD1] <= DI1; + +endmodule*/ + + diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_chr_rom.vhd b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_chr_rom.vhd new file mode 100644 index 00000000..7936c894 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_chr_rom.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity jng_chr_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of jng_chr_rom is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"80",X"C0",X"20",X"20",X"60",X"C0",X"80",X"00",X"30",X"70",X"C0",X"80",X"80",X"70",X"30",X"00", + X"20",X"20",X"E0",X"E0",X"20",X"20",X"00",X"00",X"00",X"00",X"F0",X"F0",X"40",X"00",X"00",X"00", + X"20",X"20",X"A0",X"A0",X"E0",X"E0",X"60",X"00",X"60",X"F0",X"B0",X"90",X"90",X"C0",X"40",X"00", + X"C0",X"E0",X"20",X"20",X"20",X"60",X"40",X"00",X"80",X"D0",X"F0",X"B0",X"90",X"80",X"00",X"00", + X"80",X"E0",X"E0",X"80",X"80",X"80",X"80",X"00",X"00",X"F0",X"F0",X"C0",X"60",X"30",X"10",X"00", + X"C0",X"E0",X"20",X"20",X"20",X"60",X"40",X"00",X"10",X"B0",X"A0",X"A0",X"A0",X"E0",X"E0",X"00", + X"C0",X"E0",X"20",X"20",X"20",X"E0",X"C0",X"00",X"00",X"90",X"90",X"90",X"D0",X"70",X"30",X"00", + X"00",X"00",X"00",X"E0",X"E0",X"00",X"00",X"00",X"C0",X"E0",X"B0",X"90",X"80",X"C0",X"C0",X"00", + X"C0",X"E0",X"A0",X"A0",X"20",X"20",X"C0",X"00",X"00",X"60",X"90",X"90",X"B0",X"F0",X"60",X"00", + X"80",X"C0",X"60",X"20",X"20",X"20",X"00",X"00",X"70",X"F0",X"90",X"90",X"90",X"F0",X"60",X"00", + X"40",X"40",X"20",X"00",X"00",X"00",X"00",X"00",X"40",X"40",X"80",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"00",X"00",X"00",X"00",X"00",X"10",X"20",X"20", + X"40",X"40",X"40",X"00",X"00",X"00",X"00",X"00",X"40",X"40",X"40",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"40",X"40",X"40",X"00",X"00",X"00",X"00",X"00",X"40",X"40",X"40", + X"80",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"20",X"20",X"10",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"20",X"40",X"40",X"00",X"00",X"00",X"00",X"00",X"80",X"40",X"40", + X"00",X"00",X"00",X"00",X"90",X"F0",X"52",X"61",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"90",X"F0",X"A4",X"68", + X"30",X"20",X"28",X"28",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"40",X"41",X"41",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"0C",X"00",X"F0",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"30",X"E0",X"A4",X"78", + X"10",X"F0",X"00",X"0C",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"78",X"A4",X"E0",X"30",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"28",X"28",X"20",X"30",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"41",X"41",X"40",X"E0", + X"61",X"52",X"F0",X"90",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"68",X"A4",X"F0",X"90",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"C0",X"70",X"52",X"E1",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"00",X"F0",X"80", + X"E1",X"52",X"70",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"F0",X"00",X"03",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"81",X"F0",X"D2",X"61",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"18",X"F0",X"B4",X"68", + X"30",X"10",X"18",X"18",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"80",X"81",X"81",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"0C",X"00",X"10",X"F0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"70",X"E0",X"A4",X"69", + X"F0",X"10",X"00",X"0C",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"69",X"A4",X"E0",X"70",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"18",X"18",X"10",X"30",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"81",X"81",X"80",X"C0", + X"61",X"D2",X"F0",X"81",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"68",X"B4",X"F0",X"18",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"E0",X"70",X"52",X"69",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"00",X"80",X"F0", + X"69",X"52",X"70",X"E0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"F0",X"80",X"00",X"03",X"00",X"00",X"00",X"00", + X"00",X"77",X"44",X"44",X"77",X"00",X"77",X"44",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"EE",X"22",X"22",X"EE",X"00",X"EE",X"22", + X"44",X"77",X"00",X"55",X"55",X"55",X"77",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"22",X"EE",X"00",X"EE",X"22",X"22",X"22",X"00", + X"00",X"E0",X"C0",X"C2",X"C2",X"C0",X"E0",X"00",X"00",X"04",X"10",X"61",X"61",X"10",X"04",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"E0",X"E0",X"80",X"80",X"80",X"E0",X"E0",X"00",X"30",X"70",X"C0",X"80",X"C0",X"70",X"30",X"00", + X"C0",X"E0",X"20",X"20",X"20",X"E0",X"E0",X"00",X"60",X"F0",X"90",X"90",X"90",X"F0",X"F0",X"00", + X"40",X"60",X"20",X"20",X"60",X"C0",X"80",X"00",X"40",X"C0",X"80",X"80",X"C0",X"70",X"30",X"00", + X"80",X"C0",X"60",X"20",X"20",X"E0",X"E0",X"00",X"30",X"70",X"C0",X"80",X"80",X"F0",X"F0",X"00", + X"20",X"20",X"20",X"20",X"E0",X"E0",X"00",X"00",X"80",X"90",X"90",X"90",X"F0",X"F0",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"E0",X"E0",X"00",X"80",X"90",X"90",X"90",X"90",X"F0",X"F0",X"00", + X"E0",X"E0",X"20",X"20",X"60",X"C0",X"80",X"00",X"90",X"90",X"90",X"80",X"C0",X"70",X"30",X"00", + X"E0",X"E0",X"00",X"00",X"00",X"E0",X"E0",X"00",X"F0",X"F0",X"10",X"10",X"10",X"F0",X"F0",X"00", + X"20",X"20",X"E0",X"E0",X"20",X"20",X"00",X"00",X"80",X"80",X"F0",X"F0",X"80",X"80",X"00",X"00", + X"C0",X"E0",X"20",X"20",X"20",X"60",X"40",X"00",X"F0",X"F0",X"00",X"00",X"00",X"00",X"00",X"00", + X"20",X"60",X"E0",X"C0",X"80",X"E0",X"E0",X"00",X"80",X"C0",X"60",X"30",X"10",X"F0",X"F0",X"00", + X"20",X"20",X"20",X"20",X"E0",X"E0",X"00",X"00",X"00",X"00",X"00",X"00",X"F0",X"F0",X"00",X"00", + X"E0",X"E0",X"00",X"80",X"00",X"E0",X"E0",X"00",X"F0",X"F0",X"70",X"30",X"70",X"F0",X"F0",X"00", + X"E0",X"E0",X"C0",X"80",X"00",X"E0",X"E0",X"00",X"F0",X"F0",X"10",X"30",X"70",X"F0",X"F0",X"00", + X"C0",X"E0",X"20",X"20",X"20",X"E0",X"C0",X"00",X"70",X"F0",X"80",X"80",X"80",X"F0",X"70",X"00", + X"00",X"80",X"80",X"80",X"80",X"E0",X"E0",X"00",X"70",X"F0",X"80",X"80",X"80",X"F0",X"F0",X"00", + X"A0",X"C0",X"E0",X"A0",X"20",X"E0",X"C0",X"00",X"70",X"F0",X"80",X"80",X"80",X"F0",X"70",X"00", + X"20",X"60",X"E0",X"C0",X"80",X"E0",X"E0",X"00",X"70",X"F0",X"90",X"80",X"80",X"F0",X"F0",X"00", + X"C0",X"E0",X"20",X"20",X"20",X"60",X"40",X"00",X"00",X"50",X"D0",X"90",X"90",X"F0",X"60",X"00", + X"00",X"00",X"E0",X"E0",X"00",X"00",X"00",X"00",X"80",X"80",X"F0",X"F0",X"80",X"80",X"00",X"00", + X"C0",X"E0",X"20",X"20",X"20",X"E0",X"C0",X"00",X"F0",X"F0",X"00",X"00",X"00",X"F0",X"F0",X"00", + X"00",X"80",X"C0",X"E0",X"C0",X"80",X"00",X"00",X"F0",X"F0",X"10",X"00",X"10",X"F0",X"F0",X"00", + X"E0",X"E0",X"C0",X"80",X"C0",X"E0",X"E0",X"00",X"F0",X"F0",X"10",X"30",X"10",X"F0",X"F0",X"00", + X"60",X"E0",X"C0",X"80",X"C0",X"E0",X"60",X"00",X"C0",X"E0",X"70",X"30",X"70",X"E0",X"C0",X"00", + X"00",X"00",X"E0",X"E0",X"00",X"00",X"00",X"00",X"E0",X"F0",X"10",X"10",X"F0",X"E0",X"00",X"00", + X"20",X"20",X"20",X"A0",X"E0",X"E0",X"60",X"00",X"C0",X"E0",X"F0",X"B0",X"90",X"80",X"80",X"00", + X"00",X"00",X"00",X"60",X"60",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"C0",X"20",X"10",X"50",X"50",X"90",X"20",X"C0",X"30",X"40",X"80",X"A0",X"A0",X"90",X"40",X"30", + X"C0",X"E8",X"E4",X"E0",X"E0",X"E0",X"C0",X"00",X"30",X"79",X"78",X"FC",X"78",X"78",X"30",X"00", + X"E0",X"C0",X"68",X"E0",X"68",X"C0",X"E0",X"00",X"00",X"10",X"F0",X"21",X"F0",X"10",X"00",X"00", + X"C0",X"20",X"80",X"C0",X"80",X"20",X"C0",X"00",X"10",X"30",X"70",X"F0",X"70",X"30",X"10",X"00", + X"00",X"00",X"00",X"00",X"10",X"00",X"3F",X"56",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"11", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"08",X"08",X"4F",X"A6", + X"25",X"2A",X"8B",X"26",X"15",X"00",X"00",X"00",X"11",X"11",X"01",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"A2",X"4C",X"84",X"82",X"88",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"3B",X"AC",X"8A",X"98",X"00",X"00",X"00",X"00",X"01",X"00",X"00",X"00", + X"00",X"00",X"00",X"04",X"08",X"88",X"88",X"00",X"00",X"00",X"00",X"04",X"15",X"8B",X"14",X"18", + X"51",X"46",X"0D",X"A9",X"66",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"00",X"00",X"00",X"00", + X"04",X"08",X"00",X"00",X"00",X"00",X"00",X"00",X"8B",X"E2",X"26",X"C6",X"09",X"08",X"00",X"00", + X"00",X"00",X"11",X"2A",X"49",X"21",X"95",X"45",X"00",X"02",X"01",X"00",X"00",X"11",X"23",X"22", + X"00",X"00",X"00",X"00",X"02",X"0C",X"88",X"88",X"00",X"02",X"8A",X"45",X"C6",X"11",X"AD",X"C4", + X"5C",X"26",X"90",X"04",X"8A",X"01",X"01",X"00",X"11",X"01",X"02",X"13",X"04",X"00",X"00",X"00", + X"00",X"06",X"08",X"00",X"00",X"08",X"08",X"00",X"A8",X"0A",X"91",X"66",X"81",X"00",X"00",X"00", + X"00",X"18",X"AC",X"84",X"13",X"38",X"91",X"23",X"01",X"00",X"11",X"2E",X"47",X"54",X"40",X"06", + X"09",X"0A",X"02",X"05",X"08",X"00",X"0C",X"03",X"04",X"04",X"05",X"CE",X"3E",X"31",X"39",X"89", + X"2F",X"59",X"42",X"A8",X"6F",X"10",X"01",X"01",X"3A",X"32",X"11",X"05",X"08",X"01",X"01",X"01", + X"88",X"C4",X"4C",X"8E",X"01",X"00",X"00",X"00",X"BA",X"32",X"4D",X"06",X"B3",X"4A",X"01",X"01", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"02",X"04",X"00",X"64",X"00",X"40",X"02",X"00",X"18",X"40",X"01",X"D5",X"01",X"04",X"18", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"18",X"F0",X"B4",X"68",X"C0",X"80",X"81",X"81",X"81",X"F0",X"D2",X"61",X"30",X"10",X"18",X"18", + X"90",X"F0",X"A4",X"68",X"C0",X"40",X"41",X"41",X"90",X"F0",X"52",X"61",X"30",X"20",X"28",X"28", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"21",X"43",X"53",X"E1",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"88",X"0C",X"0E",X"4F", + X"D3",X"61",X"43",X"21",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"2E",X"8C",X"08",X"00",X"00",X"00",X"00", + X"00",X"80",X"C0",X"E0",X"E0",X"C0",X"80",X"00",X"00",X"10",X"30",X"70",X"70",X"30",X"10",X"00", + X"80",X"C0",X"E0",X"E0",X"C0",X"80",X"00",X"00",X"10",X"30",X"70",X"70",X"30",X"10",X"00",X"00", + X"C0",X"E0",X"E0",X"E0",X"C0",X"00",X"00",X"08",X"70",X"70",X"70",X"30",X"10",X"00",X"00",X"03", + X"E0",X"E0",X"E0",X"C0",X"00",X"00",X"08",X"0C",X"70",X"70",X"30",X"10",X"00",X"00",X"03",X"07", + X"E0",X"C0",X"80",X"00",X"00",X"08",X"0C",X"0E",X"70",X"30",X"10",X"00",X"00",X"01",X"03",X"07", + X"C0",X"80",X"00",X"00",X"08",X"0C",X"0E",X"0E",X"30",X"10",X"00",X"00",X"01",X"03",X"07",X"07", + X"80",X"00",X"00",X"0C",X"0E",X"0E",X"0E",X"0C",X"30",X"00",X"00",X"01",X"03",X"07",X"07",X"07", + X"00",X"00",X"0C",X"0E",X"0E",X"0E",X"0C",X"08",X"00",X"00",X"01",X"03",X"07",X"07",X"07",X"03", + X"00",X"80",X"C0",X"E0",X"E0",X"C0",X"80",X"00",X"00",X"10",X"30",X"70",X"70",X"30",X"10",X"00", + X"00",X"00",X"80",X"C0",X"C0",X"80",X"00",X"00",X"00",X"30",X"70",X"F0",X"F0",X"70",X"30",X"00", + X"00",X"00",X"80",X"81",X"81",X"01",X"00",X"00",X"00",X"70",X"F0",X"F0",X"F0",X"F0",X"E0",X"00", + X"00",X"00",X"01",X"03",X"03",X"03",X"01",X"00",X"00",X"E0",X"F0",X"F0",X"F0",X"E0",X"C0",X"00", + X"00",X"01",X"03",X"07",X"07",X"03",X"01",X"00",X"00",X"80",X"C0",X"E0",X"E0",X"C0",X"80",X"00", + X"00",X"03",X"07",X"0F",X"0F",X"07",X"03",X"00",X"00",X"00",X"80",X"C0",X"C0",X"80",X"00",X"00", + X"00",X"0E",X"0F",X"0F",X"0F",X"0F",X"07",X"00",X"00",X"00",X"01",X"81",X"81",X"80",X"00",X"00", + X"00",X"0C",X"0E",X"0F",X"0F",X"0F",X"0E",X"00",X"00",X"01",X"03",X"03",X"03",X"01",X"00",X"00", + X"C0",X"E0",X"F0",X"F0",X"E0",X"C0",X"00",X"00",X"00",X"10",X"30",X"30",X"10",X"00",X"00",X"00", + X"80",X"C0",X"E0",X"E0",X"C0",X"80",X"00",X"00",X"10",X"30",X"70",X"70",X"30",X"10",X"00",X"00", + X"C0",X"E0",X"E0",X"C1",X"81",X"00",X"00",X"00",X"30",X"70",X"70",X"30",X"10",X"00",X"00",X"00", + X"E0",X"E0",X"C1",X"83",X"03",X"01",X"00",X"00",X"70",X"70",X"30",X"10",X"00",X"00",X"00",X"00", + X"E0",X"C1",X"83",X"07",X"07",X"03",X"01",X"00",X"70",X"30",X"10",X"00",X"00",X"00",X"00",X"00", + X"C0",X"83",X"07",X"0F",X"0F",X"07",X"03",X"00",X"30",X"10",X"00",X"00",X"00",X"00",X"00",X"00", + X"80",X"06",X"0F",X"0F",X"0F",X"0F",X"06",X"00",X"10",X"00",X"00",X"01",X"01",X"00",X"00",X"00", + X"00",X"0C",X"0E",X"0F",X"0F",X"0E",X"0C",X"00",X"00",X"00",X"01",X"03",X"03",X"01",X"00",X"00", + X"C0",X"E0",X"F0",X"F0",X"E0",X"C0",X"00",X"00",X"00",X"10",X"30",X"30",X"10",X"00",X"00",X"00", + X"00",X"C0",X"E0",X"F0",X"F0",X"E0",X"C0",X"00",X"00",X"00",X"10",X"30",X"30",X"10",X"00",X"00", + X"08",X"60",X"F0",X"F0",X"F0",X"F0",X"60",X"00",X"01",X"00",X"00",X"10",X"10",X"00",X"00",X"00", + X"0C",X"38",X"70",X"F0",X"F0",X"70",X"30",X"00",X"03",X"01",X"00",X"00",X"00",X"00",X"00",X"00", + X"0E",X"1C",X"38",X"70",X"70",X"30",X"10",X"00",X"07",X"03",X"01",X"00",X"00",X"00",X"00",X"00", + X"0E",X"0E",X"1C",X"38",X"30",X"10",X"00",X"00",X"07",X"07",X"03",X"01",X"00",X"00",X"00",X"00", + X"0C",X"0E",X"0E",X"1C",X"18",X"00",X"00",X"00",X"03",X"07",X"07",X"03",X"01",X"00",X"00",X"00", + X"08",X"0C",X"0E",X"0E",X"0C",X"08",X"00",X"00",X"01",X"03",X"07",X"07",X"03",X"01",X"00",X"00", + X"00",X"80",X"C0",X"E0",X"E0",X"C0",X"80",X"00",X"00",X"10",X"30",X"70",X"70",X"30",X"10",X"00", + X"80",X"C0",X"E0",X"E0",X"C0",X"80",X"00",X"00",X"10",X"30",X"70",X"70",X"30",X"10",X"00",X"00", + X"C0",X"E0",X"E0",X"E0",X"C0",X"00",X"00",X"08",X"70",X"70",X"70",X"30",X"10",X"00",X"00",X"01", + X"E0",X"E0",X"E0",X"C0",X"00",X"00",X"08",X"0C",X"70",X"70",X"30",X"10",X"00",X"00",X"01",X"03", + X"E0",X"C0",X"80",X"00",X"00",X"08",X"0C",X"0E",X"70",X"30",X"10",X"00",X"00",X"01",X"03",X"07", + X"C0",X"80",X"00",X"00",X"08",X"0C",X"0E",X"0F",X"30",X"10",X"00",X"00",X"01",X"03",X"07",X"0F", + X"80",X"00",X"00",X"08",X"0C",X"0E",X"0F",X"0D",X"30",X"00",X"00",X"01",X"03",X"07",X"0F",X"0B", + X"00",X"00",X"08",X"0C",X"0E",X"0F",X"0D",X"09",X"00",X"00",X"01",X"03",X"07",X"0F",X"0B",X"09", + X"00",X"80",X"C0",X"E0",X"E0",X"C0",X"80",X"00",X"00",X"10",X"30",X"70",X"70",X"30",X"10",X"00", + X"00",X"00",X"80",X"C0",X"C0",X"80",X"00",X"00",X"00",X"30",X"70",X"F0",X"F0",X"70",X"30",X"00", + X"00",X"00",X"80",X"81",X"81",X"00",X"00",X"00",X"00",X"70",X"F0",X"F0",X"F0",X"F0",X"E0",X"00", + X"00",X"00",X"01",X"03",X"03",X"01",X"00",X"00",X"00",X"E0",X"F0",X"F0",X"F0",X"E0",X"C0",X"00", + X"00",X"01",X"03",X"07",X"07",X"03",X"01",X"00",X"00",X"80",X"C0",X"E0",X"E0",X"C0",X"80",X"00", + X"01",X"03",X"07",X"0F",X"0F",X"07",X"03",X"01",X"00",X"00",X"80",X"C0",X"C0",X"80",X"00",X"00", + X"03",X"06",X"0F",X"0F",X"0F",X"0F",X"06",X"03",X"00",X"00",X"00",X"81",X"81",X"80",X"00",X"00", + X"07",X"0C",X"0E",X"0F",X"0F",X"0E",X"0C",X"07",X"00",X"00",X"01",X"03",X"03",X"01",X"00",X"00", + X"C0",X"E0",X"F0",X"F0",X"E0",X"C0",X"00",X"00",X"00",X"10",X"30",X"30",X"10",X"00",X"00",X"00", + X"80",X"C0",X"E0",X"E0",X"C0",X"80",X"00",X"00",X"10",X"30",X"70",X"70",X"30",X"10",X"00",X"00", + X"C0",X"E0",X"E0",X"C1",X"81",X"00",X"00",X"00",X"30",X"70",X"70",X"30",X"10",X"00",X"00",X"00", + X"E0",X"E0",X"C1",X"83",X"03",X"01",X"00",X"00",X"70",X"70",X"30",X"10",X"00",X"00",X"00",X"00", + X"E0",X"C1",X"83",X"07",X"07",X"03",X"01",X"00",X"70",X"30",X"10",X"00",X"00",X"00",X"00",X"00", + X"C1",X"83",X"07",X"0F",X"0F",X"07",X"03",X"01",X"30",X"10",X"00",X"00",X"00",X"00",X"00",X"00", + X"83",X"06",X"0F",X"0F",X"0F",X"0F",X"06",X"03",X"10",X"00",X"00",X"01",X"01",X"00",X"00",X"00", + X"07",X"0C",X"0E",X"0F",X"0F",X"0E",X"0C",X"07",X"00",X"00",X"01",X"03",X"03",X"01",X"00",X"00", + X"C0",X"E0",X"F0",X"F0",X"E0",X"C0",X"00",X"00",X"00",X"10",X"30",X"30",X"10",X"00",X"00",X"00", + X"00",X"C0",X"E0",X"F0",X"F0",X"E0",X"C0",X"00",X"00",X"00",X"10",X"30",X"30",X"10",X"00",X"00", + X"08",X"60",X"F0",X"F0",X"F0",X"F0",X"60",X"00",X"01",X"00",X"00",X"10",X"10",X"00",X"00",X"00", + X"0C",X"38",X"70",X"F0",X"F0",X"70",X"30",X"00",X"03",X"01",X"00",X"00",X"00",X"00",X"00",X"00", + X"0E",X"1C",X"38",X"70",X"70",X"30",X"10",X"00",X"07",X"03",X"01",X"00",X"00",X"00",X"00",X"00", + X"0F",X"0E",X"1C",X"38",X"30",X"10",X"00",X"00",X"0F",X"07",X"03",X"01",X"00",X"00",X"00",X"00", + X"0D",X"0F",X"0E",X"1C",X"18",X"00",X"00",X"00",X"0B",X"0F",X"07",X"03",X"01",X"00",X"00",X"00", + X"09",X"0D",X"0F",X"0E",X"0C",X"08",X"00",X"00",X"09",X"0B",X"0F",X"07",X"03",X"01",X"00",X"00", + X"00",X"80",X"C0",X"E0",X"F0",X"D0",X"90",X"20",X"00",X"10",X"30",X"70",X"F0",X"B0",X"90",X"40", + X"80",X"C0",X"E0",X"F0",X"D0",X"90",X"20",X"00",X"10",X"30",X"70",X"F0",X"B0",X"90",X"40",X"00", + X"C0",X"E0",X"F0",X"D0",X"90",X"20",X"00",X"00",X"30",X"70",X"F0",X"B0",X"90",X"40",X"00",X"00", + X"E0",X"F0",X"D0",X"90",X"20",X"00",X"00",X"00",X"70",X"F0",X"B0",X"90",X"40",X"00",X"00",X"00", + X"F0",X"D0",X"90",X"20",X"00",X"00",X"00",X"00",X"F0",X"B0",X"90",X"40",X"00",X"00",X"00",X"00", + X"D0",X"90",X"20",X"00",X"00",X"00",X"00",X"00",X"B0",X"90",X"40",X"00",X"00",X"00",X"00",X"00", + X"90",X"20",X"00",X"00",X"00",X"00",X"00",X"00",X"90",X"40",X"00",X"00",X"00",X"00",X"00",X"00", + X"20",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"E0",X"90",X"C0",X"E0",X"E0",X"C0",X"90",X"E0",X"00",X"10",X"30",X"70",X"70",X"30",X"10",X"00", + X"C0",X"20",X"80",X"C0",X"C0",X"80",X"20",X"C0",X"10",X"30",X"70",X"F0",X"F0",X"70",X"30",X"10", + X"80",X"40",X"00",X"80",X"80",X"00",X"40",X"80",X"30",X"60",X"F0",X"F0",X"F0",X"F0",X"60",X"30", + X"00",X"80",X"00",X"00",X"00",X"00",X"80",X"00",X"70",X"C0",X"E0",X"F0",X"F0",X"E0",X"C0",X"70", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"E0",X"90",X"C0",X"E0",X"E0",X"C0",X"90",X"E0", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"20",X"80",X"C0",X"C0",X"80",X"20",X"C0", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"40",X"00",X"80",X"80",X"00",X"40",X"80", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"00",X"00",X"00",X"00",X"80",X"00", + X"80",X"C0",X"E0",X"F0",X"D0",X"90",X"20",X"00",X"10",X"30",X"70",X"F0",X"B0",X"90",X"40",X"00", + X"80",X"C0",X"E0",X"F0",X"D0",X"90",X"20",X"00",X"10",X"30",X"70",X"F0",X"B0",X"90",X"40",X"00", + X"C0",X"E0",X"F0",X"D0",X"90",X"20",X"00",X"00",X"30",X"70",X"F0",X"B0",X"90",X"40",X"00",X"00", + X"E0",X"F0",X"D0",X"90",X"20",X"00",X"00",X"00",X"70",X"F0",X"B0",X"90",X"40",X"00",X"00",X"00", + X"F0",X"D0",X"90",X"20",X"00",X"00",X"00",X"00",X"F0",X"B0",X"90",X"40",X"00",X"00",X"00",X"00", + X"D0",X"90",X"20",X"00",X"00",X"00",X"00",X"00",X"B0",X"90",X"40",X"00",X"00",X"00",X"00",X"00", + X"90",X"20",X"00",X"00",X"00",X"00",X"00",X"00",X"90",X"40",X"00",X"00",X"00",X"00",X"00",X"00", + X"20",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"80",X"C0",X"E0",X"F0",X"F0",X"E0",X"C0",X"80",X"30",X"40",X"10",X"30",X"30",X"10",X"40",X"30", + X"80",X"C0",X"E0",X"F0",X"F0",X"E0",X"C0",X"80",X"30",X"40",X"10",X"30",X"30",X"10",X"40",X"30", + X"C0",X"60",X"F0",X"F0",X"F0",X"F0",X"60",X"C0",X"10",X"20",X"00",X"10",X"10",X"00",X"20",X"10", + X"E0",X"30",X"70",X"F0",X"F0",X"70",X"30",X"E0",X"00",X"10",X"00",X"00",X"00",X"00",X"10",X"00", + X"70",X"90",X"30",X"70",X"70",X"30",X"90",X"70",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"30",X"40",X"10",X"30",X"30",X"10",X"40",X"30",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"10",X"20",X"00",X"10",X"10",X"00",X"20",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"10",X"00",X"00",X"00",X"00",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"50",X"A0",X"50",X"A0",X"50",X"A0",X"F0",X"00",X"50",X"60",X"50",X"60",X"50",X"20",X"10",X"00", + X"00",X"F0",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"00",X"10",X"20",X"50",X"60",X"50",X"60",X"50", + X"A0",X"60",X"A0",X"60",X"A0",X"40",X"80",X"00",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"F0",X"00", + X"00",X"80",X"40",X"A0",X"60",X"A0",X"60",X"A0",X"00",X"F0",X"50",X"A0",X"50",X"A0",X"50",X"A0", + X"A0",X"50",X"A0",X"50",X"A0",X"50",X"F0",X"00",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"F0",X"00", + X"00",X"F0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"00",X"F0",X"50",X"A0",X"50",X"A0",X"50",X"A0", + X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"60",X"50",X"60",X"50",X"60",X"50",X"60",X"50", + X"60",X"A0",X"60",X"A0",X"60",X"A0",X"60",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0", + X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"20", + X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"20",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50", + X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"40",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50", + X"40",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0", + X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50", + X"C0",X"20",X"50",X"90",X"90",X"50",X"20",X"C0",X"30",X"40",X"A0",X"90",X"90",X"A0",X"40",X"30", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"20",X"40",X"20",X"90",X"20",X"40",X"20",X"90",X"50",X"A0",X"50",X"20",X"50",X"A0",X"50",X"20", + X"20",X"50",X"A0",X"50",X"80",X"20",X"50",X"80",X"20",X"50",X"A0",X"50",X"80",X"20",X"50",X"80", + X"20",X"50",X"A0",X"50",X"00",X"20",X"10",X"A0",X"20",X"90",X"40",X"20",X"50",X"A0",X"50",X"20", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_col_rom.vhd b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_col_rom.vhd new file mode 100644 index 00000000..49e9603b --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_col_rom.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity jng_col_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of jng_col_rom is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"0F",X"00",X"00",X"01",X"0F",X"00",X"00",X"02",X"0F",X"00",X"00",X"04",X"0F", + X"00",X"00",X"0C",X"0F",X"00",X"00",X"0E",X"0F",X"00",X"00",X"0F",X"0F",X"00",X"01",X"00",X"0F", + X"00",X"01",X"01",X"0F",X"00",X"01",X"02",X"0F",X"00",X"01",X"04",X"0F",X"00",X"01",X"0C",X"0F", + X"00",X"01",X"0E",X"0F",X"00",X"01",X"0F",X"0F",X"00",X"02",X"00",X"0F",X"00",X"02",X"01",X"0F", + X"00",X"02",X"02",X"0F",X"00",X"02",X"04",X"0F",X"00",X"02",X"0C",X"0F",X"00",X"02",X"0E",X"0F", + X"00",X"02",X"0F",X"0F",X"00",X"04",X"00",X"0F",X"00",X"04",X"01",X"0F",X"00",X"04",X"02",X"0F", + X"00",X"04",X"04",X"0F",X"00",X"04",X"0C",X"0F",X"00",X"04",X"0E",X"0F",X"00",X"04",X"0F",X"0F", + X"00",X"0C",X"00",X"0F",X"00",X"0C",X"01",X"0F",X"00",X"0C",X"02",X"0F",X"00",X"0C",X"04",X"0F", + X"00",X"0C",X"0C",X"0F",X"00",X"0C",X"0E",X"0F",X"00",X"0C",X"0F",X"0F",X"00",X"0E",X"00",X"0F", + X"00",X"0E",X"01",X"0F",X"00",X"0E",X"02",X"0F",X"00",X"0E",X"04",X"0F",X"00",X"0E",X"0C",X"0F", + X"00",X"0E",X"0E",X"0F",X"00",X"0E",X"0F",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"01",X"0F", + X"00",X"0F",X"02",X"0F",X"00",X"0F",X"04",X"0F",X"00",X"0F",X"0C",X"0F",X"00",X"0F",X"0E",X"0F", + X"00",X"0F",X"0F",X"0F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"01",X"02",X"09",X"00",X"0F",X"09",X"02",X"00",X"02",X"01",X"04", + X"00",X"0C",X"0F",X"0A",X"00",X"07",X"05",X"08",X"00",X"0D",X"04",X"06",X"00",X"02",X"04",X"0B"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_dot_rom.vhd b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_dot_rom.vhd new file mode 100644 index 00000000..74c632c5 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_dot_rom.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity jng_dot_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of jng_dot_rom is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"02",X"02",X"00",X"00",X"02",X"02",X"00",X"00",X"00",X"00",X"00", + X"00",X"02",X"02",X"00",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"00",X"02",X"02",X"00", + X"00",X"02",X"02",X"00",X"02",X"01",X"01",X"02",X"02",X"01",X"01",X"02",X"00",X"02",X"02",X"00", + X"00",X"00",X"00",X"00",X"00",X"02",X"00",X"00",X"02",X"02",X"02",X"00",X"00",X"02",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"00",X"00",X"01",X"01",X"00",X"00",X"00",X"00",X"00", + X"00",X"01",X"01",X"00",X"01",X"01",X"01",X"01",X"01",X"00",X"01",X"01",X"00",X"01",X"01",X"00", + X"00",X"01",X"01",X"00",X"01",X"02",X"02",X"01",X"01",X"02",X"02",X"01",X"00",X"01",X"01",X"00", + X"00",X"00",X"00",X"00",X"00",X"01",X"00",X"00",X"01",X"01",X"01",X"00",X"00",X"01",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"02",X"02",X"00",X"00",X"02",X"02",X"00",X"00",X"00",X"00",X"00", + X"00",X"02",X"02",X"00",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"00",X"02",X"02",X"00", + X"00",X"02",X"02",X"00",X"02",X"01",X"01",X"02",X"02",X"01",X"01",X"02",X"00",X"02",X"02",X"00", + X"00",X"00",X"00",X"00",X"00",X"02",X"00",X"00",X"02",X"02",X"02",X"00",X"00",X"02",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"00",X"00",X"01",X"01",X"00",X"00",X"00",X"00",X"00", + X"00",X"01",X"01",X"00",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"00",X"01",X"01",X"00", + X"00",X"01",X"01",X"00",X"01",X"02",X"02",X"01",X"01",X"02",X"02",X"01",X"00",X"01",X"01",X"00", + X"00",X"00",X"00",X"00",X"00",X"01",X"00",X"00",X"01",X"01",X"01",X"00",X"00",X"01",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_pal_rom.vhd b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_pal_rom.vhd new file mode 100644 index 00000000..78dca849 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_pal_rom.vhd @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity jng_pal_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of jng_pal_rom is + type rom is array(0 to 31) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"07",X"38",X"3C",X"3F",X"8C",X"E0",X"27",X"AA",X"8C",X"1F",X"B6",X"C0",X"C7",X"F8",X"FE", + X"00",X"3F",X"FE",X"67",X"00",X"3F",X"FE",X"67",X"00",X"3F",X"FE",X"67",X"00",X"3F",X"FE",X"67"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_prg_rom.vhd b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_prg_rom.vhd new file mode 100644 index 00000000..7b2b0c96 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_prg_rom.vhd @@ -0,0 +1,1046 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity jng_prg_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of jng_prg_rom is + type rom is array(0 to 16383) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"AF",X"32",X"81",X"A1",X"C3",X"24",X"14",X"FF",X"85",X"6F",X"D0",X"24",X"C9",X"FF",X"FF",X"FF", + X"7B",X"C6",X"20",X"5F",X"D0",X"14",X"C9",X"FF",X"87",X"CF",X"5E",X"23",X"56",X"C9",X"FF",X"FF", + X"7D",X"D6",X"20",X"6F",X"D0",X"25",X"C9",X"FF",X"7B",X"D6",X"20",X"5F",X"D0",X"15",X"C9",X"FF", + X"E1",X"DF",X"EB",X"E9",X"FF",X"FF",X"FF",X"FF",X"7E",X"FE",X"40",X"C8",X"12",X"23",X"D7",X"18", + X"F7",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"AF",X"32",X"81",X"A1",X"32",X"80",X"A0",X"3A",X"2C",X"99", + X"32",X"30",X"A1",X"3A",X"2D",X"99",X"32",X"40",X"A1",X"21",X"00",X"9C",X"11",X"14",X"80",X"01", + X"0C",X"00",X"ED",X"B0",X"21",X"10",X"9C",X"11",X"14",X"88",X"01",X"0C",X"00",X"ED",X"B0",X"21", + X"24",X"9C",X"11",X"34",X"80",X"01",X"08",X"00",X"ED",X"B0",X"21",X"34",X"9C",X"11",X"34",X"88", + X"01",X"08",X"00",X"ED",X"B0",X"21",X"44",X"9C",X"11",X"34",X"A0",X"01",X"08",X"00",X"ED",X"B0", + X"CD",X"5E",X"2D",X"CD",X"84",X"2D",X"3A",X"00",X"A0",X"2F",X"32",X"03",X"98",X"3A",X"80",X"A0", + X"2F",X"32",X"04",X"98",X"3A",X"00",X"A1",X"2F",X"32",X"05",X"98",X"CD",X"C2",X"2F",X"CD",X"0E", + X"30",X"CD",X"DB",X"2F",X"21",X"E8",X"00",X"E5",X"3A",X"20",X"99",X"F7",X"D4",X"01",X"01",X"04", + X"D0",X"07",X"35",X"0A",X"D0",X"0C",X"6B",X"0E",X"CD",X"69",X"30",X"CD",X"8D",X"30",X"CD",X"5F", + X"33",X"21",X"02",X"98",X"34",X"21",X"00",X"98",X"7E",X"A7",X"28",X"01",X"35",X"2A",X"06",X"98", + X"7C",X"B5",X"28",X"04",X"2B",X"22",X"06",X"98",X"3E",X"01",X"32",X"81",X"A1",X"C9",X"4A",X"55", + X"4E",X"47",X"4C",X"45",X"52",X"40",X"43",X"52",X"45",X"44",X"49",X"54",X"40",X"4C",X"4F",X"4F", + X"50",X"20",X"40",X"42",X"4F",X"4D",X"42",X"20",X"54",X"49",X"4D",X"45",X"52",X"20",X"40",X"48", + X"49",X"20",X"53",X"43",X"4F",X"52",X"45",X"40",X"50",X"55",X"53",X"48",X"20",X"53",X"54",X"41", + X"52",X"54",X"20",X"42",X"55",X"54",X"54",X"4F",X"4E",X"40",X"4F",X"4E",X"45",X"20",X"50",X"4C", + X"41",X"59",X"45",X"52",X"20",X"4F",X"4E",X"4C",X"59",X"20",X"20",X"20",X"40",X"4F",X"4E",X"45", + X"20",X"4F",X"52",X"20",X"54",X"57",X"4F",X"20",X"50",X"4C",X"41",X"59",X"45",X"52",X"53",X"40", + X"4F",X"4E",X"45",X"40",X"54",X"57",X"4F",X"40",X"01",X"55",X"50",X"40",X"02",X"55",X"50",X"40", + X"47",X"41",X"4D",X"45",X"20",X"4F",X"56",X"45",X"52",X"40",X"53",X"43",X"4F",X"52",X"45",X"20", + X"52",X"41",X"4E",X"4B",X"49",X"4E",X"47",X"40",X"50",X"4C",X"41",X"59",X"45",X"52",X"40",X"45", + X"4E",X"44",X"40",X"45",X"4E",X"45",X"4D",X"59",X"40",X"50",X"4F",X"49",X"4E",X"54",X"53",X"40", + X"5C",X"20",X"4B",X"4F",X"4E",X"41",X"4D",X"49",X"20",X"01",X"09",X"08",X"01",X"40",X"50",X"4C", + X"41",X"59",X"45",X"52",X"20",X"4F",X"4E",X"45",X"40",X"50",X"4C",X"41",X"59",X"45",X"52",X"20", + X"54",X"57",X"4F",X"40",X"21",X"F0",X"01",X"E5",X"3A",X"21",X"99",X"F7",X"F1",X"01",X"1B",X"02", + X"27",X"02",X"34",X"02",X"44",X"02",X"56",X"02",X"67",X"02",X"6E",X"02",X"97",X"02",X"F8",X"02", + X"C9",X"3E",X"01",X"32",X"83",X"A1",X"32",X"2F",X"99",X"CD",X"0A",X"02",X"CD",X"05",X"1B",X"3E", + X"1E",X"32",X"00",X"98",X"CD",X"1B",X"03",X"C3",X"FC",X"03",X"CD",X"84",X"1A",X"21",X"0E",X"01", + X"11",X"85",X"81",X"0E",X"BA",X"CD",X"DA",X"16",X"C3",X"48",X"30",X"3A",X"00",X"98",X"A7",X"C0", + X"CD",X"D1",X"1A",X"C0",X"C3",X"FC",X"03",X"3A",X"23",X"99",X"A7",X"CA",X"FC",X"03",X"3E",X"07", + X"32",X"21",X"99",X"C9",X"3A",X"23",X"99",X"A7",X"20",X"F4",X"AF",X"32",X"21",X"99",X"3E",X"05", + X"32",X"20",X"99",X"C9",X"3A",X"23",X"99",X"A7",X"20",X"E4",X"CD",X"B9",X"19",X"D8",X"3E",X"FF", + X"32",X"00",X"98",X"C3",X"FC",X"03",X"3A",X"23",X"99",X"A7",X"20",X"05",X"3A",X"00",X"98",X"A7", + X"C0",X"CD",X"1B",X"03",X"C3",X"FC",X"03",X"CD",X"D1",X"1A",X"C0",X"C3",X"FC",X"03",X"3A",X"23", + X"99",X"A7",X"20",X"0A",X"AF",X"32",X"21",X"99",X"3E",X"04",X"32",X"20",X"99",X"C9",X"3E",X"01", + X"32",X"83",X"A1",X"32",X"2F",X"99",X"21",X"38",X"01",X"11",X"16",X"85",X"0E",X"A3",X"CD",X"DA", + X"16",X"CD",X"17",X"0F",X"C3",X"FC",X"03",X"CD",X"75",X"03",X"11",X"15",X"85",X"3A",X"23",X"99", + X"FE",X"01",X"20",X"05",X"21",X"4A",X"01",X"18",X"03",X"21",X"5D",X"01",X"0E",X"A3",X"CD",X"DA", + X"16",X"3A",X"04",X"98",X"E6",X"C0",X"C8",X"21",X"23",X"99",X"E6",X"80",X"28",X"0C",X"7E",X"D6", + X"01",X"27",X"77",X"3E",X"00",X"32",X"10",X"99",X"18",X"13",X"7E",X"FE",X"02",X"D8",X"D6",X"01", + X"27",X"D6",X"01",X"27",X"77",X"CD",X"4E",X"03",X"3E",X"01",X"32",X"10",X"99",X"AF",X"32",X"11", + X"99",X"CD",X"27",X"03",X"CD",X"48",X"30",X"CD",X"AD",X"1A",X"CD",X"FB",X"33",X"3E",X"1E",X"32", + X"00",X"98",X"CD",X"1B",X"03",X"C3",X"FC",X"03",X"3A",X"00",X"98",X"A7",X"C0",X"CD",X"D1",X"1A", + X"C0",X"21",X"A2",X"88",X"11",X"20",X"00",X"06",X"03",X"36",X"8E",X"19",X"10",X"FB",X"21",X"62", + X"8B",X"06",X"03",X"36",X"8E",X"19",X"10",X"FB",X"C3",X"F4",X"03",X"3E",X"20",X"32",X"01",X"98", + X"21",X"00",X"84",X"22",X"52",X"98",X"C9",X"3E",X"03",X"32",X"00",X"9F",X"AF",X"32",X"01",X"9F", + X"32",X"02",X"9F",X"32",X"0A",X"9F",X"3A",X"34",X"99",X"A7",X"28",X"05",X"3E",X"FF",X"32",X"00", + X"9F",X"21",X"01",X"9F",X"34",X"CD",X"94",X"03",X"3E",X"0A",X"32",X"03",X"9F",X"C9",X"3E",X"03", + X"32",X"40",X"9F",X"AF",X"32",X"41",X"9F",X"32",X"42",X"9F",X"32",X"4A",X"9F",X"3A",X"34",X"99", + X"A7",X"28",X"05",X"3E",X"FF",X"32",X"40",X"9F",X"21",X"41",X"9F",X"34",X"CD",X"AB",X"03",X"3E", + X"0A",X"32",X"43",X"9F",X"C9",X"21",X"00",X"99",X"06",X"10",X"36",X"00",X"23",X"10",X"FB",X"21", + X"00",X"9F",X"06",X"10",X"36",X"00",X"23",X"10",X"FB",X"21",X"40",X"9F",X"06",X"10",X"36",X"00", + X"23",X"10",X"FB",X"C9",X"7E",X"FE",X"19",X"38",X"02",X"3E",X"17",X"21",X"C2",X"03",X"CF",X"7E", + X"32",X"08",X"9F",X"3E",X"19",X"CF",X"7E",X"32",X"09",X"9F",X"C9",X"7E",X"FE",X"19",X"38",X"02", + X"3E",X"17",X"21",X"C2",X"03",X"CF",X"7E",X"32",X"48",X"9F",X"3E",X"19",X"CF",X"7E",X"32",X"49", + X"9F",X"C9",X"00",X"03",X"04",X"05",X"04",X"05",X"06",X"07",X"04",X"07",X"07",X"07",X"05",X"07", + X"07",X"07",X"05",X"08",X"08",X"08",X"06",X"08",X"08",X"08",X"07",X"00",X"02",X"03",X"04",X"03", + X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"05",X"05",X"05",X"04",X"06",X"06",X"06",X"04", + X"07",X"07",X"07",X"04",X"21",X"20",X"99",X"34",X"23",X"36",X"00",X"C9",X"21",X"21",X"99",X"34", + X"C9",X"21",X"1F",X"04",X"E5",X"3A",X"21",X"99",X"F7",X"20",X"04",X"42",X"04",X"52",X"04",X"8F", + X"04",X"F3",X"04",X"3F",X"05",X"16",X"06",X"8B",X"06",X"A6",X"06",X"B6",X"06",X"D2",X"06",X"C9", + X"AF",X"32",X"08",X"98",X"3C",X"32",X"83",X"A1",X"32",X"2F",X"99",X"21",X"00",X"9F",X"7E",X"A7", + X"28",X"04",X"35",X"C3",X"FC",X"03",X"21",X"0A",X"9F",X"7E",X"36",X"00",X"32",X"04",X"9F",X"C3", + X"FC",X"03",X"3A",X"01",X"9F",X"32",X"01",X"99",X"CD",X"84",X"32",X"C0",X"CD",X"C3",X"1A",X"C3", + X"FC",X"03",X"CD",X"B8",X"1A",X"CD",X"0A",X"02",X"CD",X"8F",X"31",X"3A",X"10",X"99",X"A7",X"20", + X"29",X"21",X"2F",X"01",X"11",X"C2",X"82",X"CD",X"E7",X"30",X"21",X"2F",X"01",X"11",X"C1",X"82", + X"CD",X"E7",X"30",X"CD",X"DD",X"04",X"21",X"00",X"9F",X"11",X"00",X"99",X"01",X"10",X"00",X"ED", + X"B0",X"CD",X"06",X"19",X"CD",X"57",X"19",X"C3",X"FC",X"03",X"CD",X"B3",X"31",X"18",X"E4",X"CD", + X"1D",X"17",X"CD",X"72",X"17",X"CD",X"FB",X"17",X"CD",X"84",X"18",X"3A",X"03",X"99",X"32",X"0F", + X"99",X"CD",X"B8",X"3F",X"3E",X"78",X"32",X"00",X"98",X"21",X"20",X"1C",X"22",X"06",X"98",X"CD", + X"65",X"2E",X"CD",X"25",X"2E",X"CD",X"E5",X"2D",X"CD",X"A0",X"2D",X"CD",X"63",X"1F",X"CD",X"BA", + X"1F",X"CD",X"09",X"20",X"CD",X"58",X"20",X"CD",X"AD",X"23",X"06",X"0A",X"11",X"71",X"85",X"CD", + X"18",X"05",X"06",X"09",X"11",X"8E",X"85",X"CD",X"13",X"05",X"C3",X"FC",X"03",X"21",X"98",X"01", + X"11",X"46",X"80",X"0E",X"A3",X"CD",X"DA",X"16",X"21",X"70",X"01",X"11",X"A5",X"80",X"0E",X"A3", + X"C3",X"DA",X"16",X"3A",X"00",X"98",X"A7",X"20",X"0E",X"06",X"0A",X"11",X"71",X"85",X"CD",X"2E", + X"05",X"CD",X"BB",X"33",X"C3",X"FC",X"03",X"21",X"BE",X"01",X"11",X"71",X"85",X"01",X"20",X"00", + X"C3",X"5B",X"06",X"21",X"EC",X"98",X"18",X"03",X"21",X"D4",X"98",X"1A",X"77",X"CB",X"DA",X"23", + X"1A",X"77",X"23",X"CB",X"9A",X"D7",X"10",X"F3",X"C9",X"21",X"EC",X"98",X"18",X"03",X"21",X"D4", + X"98",X"7E",X"12",X"CB",X"DA",X"23",X"7E",X"12",X"CB",X"9A",X"23",X"D7",X"10",X"F3",X"C9",X"2A", + X"06",X"98",X"7D",X"A7",X"CC",X"12",X"07",X"CD",X"47",X"2A",X"CD",X"65",X"2E",X"CD",X"A8",X"28", + X"CD",X"25",X"2E",X"CD",X"F5",X"26",X"CD",X"E5",X"2D",X"CD",X"DE",X"25",X"CD",X"A0",X"2D",X"CD", + X"63",X"1F",X"CD",X"BA",X"1F",X"CD",X"09",X"20",X"CD",X"58",X"20",X"CD",X"AD",X"23",X"CD",X"A7", + X"20",X"CD",X"59",X"1B",X"CD",X"C6",X"1B",X"CD",X"E5",X"1C",X"CD",X"54",X"1E",X"CD",X"3A",X"25", + X"CD",X"7C",X"21",X"CD",X"E5",X"21",X"CD",X"7D",X"22",X"CD",X"15",X"23",X"CD",X"3C",X"3F",X"CD", + X"3C",X"3E",X"CD",X"33",X"39",X"CD",X"D4",X"31",X"3A",X"04",X"99",X"A7",X"CA",X"05",X"06",X"FD", + X"21",X"80",X"98",X"DD",X"21",X"04",X"99",X"DD",X"7E",X"01",X"FD",X"B6",X"01",X"CC",X"6B",X"17", + X"DD",X"7E",X"02",X"FD",X"B6",X"02",X"CC",X"F4",X"17",X"DD",X"7E",X"03",X"FD",X"B6",X"03",X"CC", + X"7D",X"18",X"DD",X"7E",X"01",X"DD",X"B6",X"02",X"DD",X"B6",X"03",X"C0",X"FD",X"7E",X"01",X"FD", + X"B6",X"02",X"FD",X"B6",X"03",X"C0",X"CD",X"C0",X"33",X"CD",X"0A",X"34",X"3E",X"78",X"32",X"00", + X"98",X"CD",X"1B",X"03",X"3E",X"0A",X"32",X"21",X"99",X"C9",X"CD",X"C0",X"33",X"3E",X"78",X"32", + X"00",X"98",X"CD",X"1B",X"03",X"3A",X"00",X"99",X"21",X"0A",X"99",X"B6",X"C2",X"FC",X"03",X"CD", + X"20",X"34",X"C3",X"FC",X"03",X"CD",X"0B",X"06",X"C0",X"18",X"DF",X"21",X"80",X"98",X"7E",X"23", + X"B6",X"23",X"B6",X"23",X"B6",X"C9",X"3A",X"00",X"98",X"FE",X"01",X"38",X"08",X"28",X"59",X"CD", + X"4A",X"06",X"C3",X"E2",X"1E",X"CD",X"D1",X"1A",X"C0",X"3A",X"00",X"99",X"21",X"0A",X"99",X"B6", + X"28",X"15",X"3A",X"10",X"99",X"A7",X"28",X"0C",X"3A",X"40",X"9F",X"21",X"4A",X"9F",X"B6",X"28", + X"03",X"CD",X"FC",X"03",X"CD",X"FC",X"03",X"C3",X"FC",X"03",X"3A",X"00",X"99",X"21",X"0A",X"99", + X"B6",X"C0",X"21",X"80",X"01",X"11",X"8E",X"85",X"01",X"20",X"00",X"7E",X"FE",X"40",X"C8",X"D5", + X"E5",X"CD",X"72",X"2D",X"3A",X"02",X"98",X"0F",X"0F",X"E6",X"07",X"21",X"83",X"06",X"CF",X"7E", + X"12",X"D1",X"E1",X"13",X"09",X"EB",X"18",X"E3",X"CD",X"05",X"1B",X"11",X"8E",X"85",X"06",X"09", + X"C3",X"29",X"05",X"87",X"8E",X"95",X"A3",X"87",X"9C",X"95",X"BE",X"3A",X"10",X"99",X"A7",X"20", + X"0A",X"3E",X"03",X"32",X"20",X"99",X"AF",X"32",X"21",X"99",X"C9",X"3A",X"40",X"9F",X"21",X"4A", + X"9F",X"B6",X"28",X"ED",X"18",X"10",X"AF",X"32",X"21",X"99",X"21",X"00",X"99",X"11",X"00",X"9F", + X"01",X"10",X"00",X"ED",X"B0",X"C9",X"3A",X"2E",X"99",X"32",X"83",X"A1",X"32",X"2F",X"99",X"3E", + X"01",X"32",X"11",X"99",X"21",X"00",X"99",X"11",X"00",X"9F",X"01",X"10",X"00",X"ED",X"B0",X"C3", + X"F4",X"03",X"3A",X"00",X"98",X"FE",X"01",X"38",X"06",X"CA",X"05",X"1B",X"C3",X"E2",X"1E",X"CD", + X"D1",X"1A",X"C0",X"3A",X"04",X"99",X"FE",X"09",X"38",X"14",X"3E",X"08",X"32",X"04",X"99",X"21", + X"0A",X"99",X"34",X"7E",X"FE",X"08",X"38",X"06",X"36",X"00",X"21",X"00",X"99",X"34",X"3E",X"01", + X"32",X"21",X"99",X"21",X"00",X"99",X"11",X"00",X"9F",X"01",X"10",X"00",X"ED",X"B0",X"CD",X"41", + X"03",X"C9",X"7C",X"FE",X"10",X"30",X"28",X"E6",X"03",X"20",X"24",X"3A",X"65",X"98",X"FE",X"38", + X"30",X"05",X"C6",X"08",X"32",X"65",X"98",X"3A",X"68",X"98",X"FE",X"38",X"30",X"05",X"C6",X"08", + X"32",X"68",X"98",X"3A",X"6B",X"98",X"FE",X"38",X"D0",X"C6",X"08",X"32",X"6B",X"98",X"C9",X"7C", + X"FE",X"17",X"28",X"10",X"FE",X"13",X"28",X"41",X"FE",X"0B",X"28",X"38",X"FE",X"11",X"C0",X"AF", + X"32",X"18",X"9C",X"C9",X"CD",X"A5",X"2F",X"E6",X"03",X"32",X"1A",X"98",X"4F",X"3A",X"2F",X"99", + X"A7",X"28",X"05",X"21",X"BC",X"07",X"18",X"03",X"21",X"C6",X"07",X"7E",X"32",X"08",X"9C",X"23", + X"7E",X"32",X"19",X"9C",X"23",X"79",X"87",X"CF",X"7E",X"32",X"18",X"9C",X"23",X"7E",X"32",X"09", + X"9C",X"C3",X"2F",X"34",X"AF",X"32",X"1A",X"9C",X"C9",X"CD",X"A5",X"2F",X"E6",X"03",X"21",X"1A", + X"98",X"BE",X"28",X"F5",X"4F",X"3A",X"2F",X"99",X"A7",X"28",X"05",X"21",X"BC",X"07",X"18",X"03", + X"21",X"C6",X"07",X"7E",X"32",X"0A",X"9C",X"23",X"7E",X"32",X"1B",X"9C",X"23",X"79",X"87",X"CF", + X"7E",X"32",X"1A",X"9C",X"23",X"7E",X"32",X"0B",X"9C",X"C3",X"2F",X"34",X"7C",X"0F",X"94",X"8C", + X"94",X"BC",X"5C",X"BC",X"5C",X"8C",X"7F",X"0F",X"5C",X"84",X"5C",X"54",X"94",X"54",X"94",X"84", + X"21",X"EE",X"07",X"E5",X"3A",X"21",X"99",X"F7",X"EF",X"07",X"06",X"08",X"16",X"08",X"39",X"08", + X"96",X"08",X"B6",X"08",X"82",X"09",X"B1",X"09",X"C4",X"09",X"D4",X"09",X"F5",X"09",X"C9",X"21", + X"40",X"9F",X"7E",X"A7",X"28",X"04",X"35",X"C3",X"FC",X"03",X"21",X"4A",X"9F",X"7E",X"36",X"00", + X"32",X"44",X"9F",X"C3",X"FC",X"03",X"3A",X"41",X"9F",X"32",X"01",X"99",X"CD",X"84",X"32",X"C0", + X"CD",X"C3",X"1A",X"C3",X"FC",X"03",X"CD",X"B8",X"1A",X"CD",X"0A",X"02",X"CD",X"8F",X"31",X"CD", + X"B3",X"31",X"CD",X"87",X"08",X"21",X"40",X"9F",X"11",X"00",X"99",X"01",X"10",X"00",X"ED",X"B0", + X"CD",X"06",X"19",X"CD",X"57",X"19",X"C3",X"FC",X"03",X"CD",X"1D",X"17",X"CD",X"72",X"17",X"CD", + X"FB",X"17",X"CD",X"84",X"18",X"3A",X"03",X"99",X"32",X"0F",X"99",X"CD",X"B8",X"3F",X"3E",X"78", + X"32",X"00",X"98",X"21",X"20",X"1C",X"22",X"06",X"98",X"CD",X"65",X"2E",X"CD",X"25",X"2E",X"CD", + X"E5",X"2D",X"CD",X"A0",X"2D",X"CD",X"63",X"1F",X"CD",X"BA",X"1F",X"CD",X"09",X"20",X"CD",X"58", + X"20",X"CD",X"AD",X"23",X"06",X"0A",X"11",X"71",X"85",X"CD",X"18",X"05",X"06",X"09",X"11",X"8E", + X"85",X"CD",X"13",X"05",X"C3",X"FC",X"03",X"21",X"98",X"01",X"11",X"46",X"80",X"FF",X"21",X"74", + X"01",X"11",X"A5",X"80",X"FF",X"C9",X"3A",X"00",X"98",X"A7",X"20",X"0E",X"06",X"0A",X"11",X"71", + X"85",X"CD",X"2E",X"05",X"CD",X"BB",X"33",X"C3",X"FC",X"03",X"21",X"C9",X"01",X"11",X"71",X"85", + X"01",X"20",X"00",X"C3",X"5B",X"06",X"2A",X"06",X"98",X"7D",X"A7",X"CC",X"12",X"07",X"CD",X"47", + X"2A",X"CD",X"65",X"2E",X"CD",X"A8",X"28",X"CD",X"25",X"2E",X"CD",X"F5",X"26",X"CD",X"E5",X"2D", + X"CD",X"DE",X"25",X"CD",X"A0",X"2D",X"CD",X"63",X"1F",X"CD",X"BA",X"1F",X"CD",X"09",X"20",X"CD", + X"58",X"20",X"CD",X"AD",X"23",X"CD",X"A7",X"20",X"CD",X"59",X"1B",X"CD",X"C6",X"1B",X"CD",X"E5", + X"1C",X"CD",X"54",X"1E",X"CD",X"3A",X"25",X"CD",X"7C",X"21",X"CD",X"E5",X"21",X"CD",X"7D",X"22", + X"CD",X"15",X"23",X"CD",X"3C",X"3F",X"CD",X"3C",X"3E",X"CD",X"33",X"39",X"CD",X"D4",X"31",X"3A", + X"04",X"99",X"A7",X"CA",X"7C",X"09",X"FD",X"21",X"80",X"98",X"DD",X"21",X"04",X"99",X"DD",X"7E", + X"01",X"FD",X"B6",X"01",X"CC",X"6B",X"17",X"DD",X"7E",X"02",X"FD",X"B6",X"02",X"CC",X"F4",X"17", + X"DD",X"7E",X"03",X"FD",X"B6",X"03",X"CC",X"7D",X"18",X"DD",X"7E",X"01",X"DD",X"B6",X"02",X"DD", + X"B6",X"03",X"C0",X"FD",X"7E",X"01",X"FD",X"B6",X"02",X"FD",X"B6",X"03",X"C0",X"CD",X"C0",X"33", + X"CD",X"0A",X"34",X"3E",X"78",X"32",X"00",X"98",X"CD",X"1B",X"03",X"3E",X"0A",X"32",X"21",X"99", + X"C9",X"CD",X"C0",X"33",X"3E",X"78",X"32",X"00",X"98",X"CD",X"1B",X"03",X"3A",X"00",X"99",X"21", + X"0A",X"99",X"B6",X"C2",X"FC",X"03",X"CD",X"20",X"34",X"C3",X"FC",X"03",X"CD",X"0B",X"06",X"C0", + X"18",X"DF",X"3A",X"00",X"98",X"FE",X"01",X"38",X"09",X"CA",X"78",X"06",X"CD",X"4A",X"06",X"C3", + X"E2",X"1E",X"CD",X"D1",X"1A",X"C0",X"3A",X"00",X"99",X"21",X"0A",X"99",X"B6",X"28",X"0F",X"3A", + X"00",X"9F",X"21",X"0A",X"9F",X"B6",X"28",X"03",X"CD",X"FC",X"03",X"CD",X"FC",X"03",X"C3",X"FC", + X"03",X"3A",X"00",X"9F",X"21",X"0A",X"9F",X"B6",X"20",X"1A",X"3E",X"03",X"32",X"20",X"99",X"AF", + X"32",X"21",X"99",X"C9",X"AF",X"32",X"21",X"99",X"21",X"00",X"99",X"11",X"40",X"9F",X"01",X"10", + X"00",X"ED",X"B0",X"C9",X"3E",X"01",X"32",X"83",X"A1",X"32",X"2F",X"99",X"3E",X"00",X"32",X"11", + X"99",X"21",X"00",X"99",X"11",X"40",X"9F",X"01",X"10",X"00",X"ED",X"B0",X"AF",X"32",X"21",X"99", + X"3C",X"32",X"20",X"99",X"C9",X"3A",X"00",X"98",X"FE",X"01",X"38",X"06",X"CA",X"05",X"1B",X"C3", + X"E2",X"1E",X"CD",X"D1",X"1A",X"C0",X"3A",X"04",X"99",X"FE",X"09",X"38",X"14",X"3E",X"08",X"32", + X"04",X"99",X"21",X"0A",X"99",X"34",X"7E",X"FE",X"08",X"38",X"06",X"36",X"00",X"21",X"00",X"99", + X"34",X"3E",X"01",X"32",X"21",X"99",X"21",X"00",X"99",X"11",X"40",X"9F",X"01",X"10",X"00",X"ED", + X"B0",X"CD",X"68",X"03",X"C9",X"21",X"57",X"0A",X"E5",X"3A",X"21",X"99",X"F7",X"77",X"0A",X"29", + X"0B",X"2F",X"0B",X"79",X"0B",X"45",X"0C",X"70",X"0C",X"91",X"0C",X"AA",X"0C",X"AD",X"0C",X"B0", + X"0C",X"B3",X"0C",X"B6",X"0C",X"BF",X"0C",X"3A",X"23",X"99",X"A7",X"C8",X"4F",X"3A",X"04",X"98", + X"E6",X"C0",X"C8",X"E6",X"80",X"28",X"0A",X"AF",X"32",X"20",X"99",X"3E",X"05",X"32",X"21",X"99", + X"C9",X"79",X"FE",X"02",X"D8",X"18",X"F0",X"AF",X"32",X"11",X"99",X"FD",X"21",X"12",X"99",X"DD", + X"21",X"40",X"98",X"DD",X"36",X"00",X"00",X"21",X"42",X"99",X"06",X"0A",X"E5",X"22",X"52",X"98", + X"FD",X"7E",X"02",X"BE",X"38",X"48",X"28",X"02",X"18",X"12",X"FD",X"7E",X"01",X"2B",X"BE",X"38", + X"3D",X"28",X"02",X"18",X"07",X"FD",X"7E",X"00",X"2B",X"BE",X"38",X"32",X"E1",X"2B",X"2B",X"E5", + X"05",X"78",X"32",X"47",X"98",X"28",X"0F",X"87",X"87",X"87",X"87",X"4F",X"06",X"00",X"21",X"CF", + X"99",X"11",X"DF",X"99",X"ED",X"B8",X"E1",X"FD",X"7E",X"00",X"77",X"23",X"FD",X"7E",X"01",X"77", + X"23",X"FD",X"7E",X"02",X"77",X"06",X"0C",X"23",X"36",X"5B",X"10",X"FB",X"18",X"1C",X"DD",X"34", + X"00",X"E1",X"11",X"10",X"00",X"19",X"10",X"A4",X"CD",X"FC",X"03",X"CD",X"FC",X"03",X"CD",X"FC", + X"03",X"CD",X"FC",X"03",X"CD",X"FC",X"03",X"C3",X"FC",X"03",X"AF",X"32",X"41",X"98",X"32",X"42", + X"98",X"21",X"E0",X"99",X"06",X"0C",X"36",X"5B",X"23",X"10",X"FB",X"3A",X"21",X"99",X"FE",X"06", + X"30",X"0B",X"3E",X"01",X"32",X"83",X"A1",X"32",X"2F",X"99",X"C3",X"FC",X"03",X"3A",X"2E",X"99", + X"32",X"83",X"A1",X"32",X"2F",X"99",X"C3",X"FC",X"03",X"CD",X"88",X"19",X"C3",X"FC",X"03",X"CD", + X"B9",X"19",X"D8",X"CD",X"23",X"0C",X"CD",X"5B",X"1A",X"3A",X"47",X"98",X"87",X"21",X"98",X"01", + X"11",X"06",X"8D",X"83",X"5F",X"0E",X"87",X"CD",X"F2",X"30",X"3A",X"42",X"98",X"06",X"95",X"CD", + X"5F",X"0C",X"3A",X"41",X"98",X"0E",X"95",X"CD",X"54",X"0C",X"3A",X"21",X"99",X"FE",X"06",X"30", + X"0C",X"CD",X"DD",X"04",X"21",X"08",X"07",X"22",X"06",X"98",X"C3",X"FC",X"03",X"CD",X"DD",X"04", + X"21",X"08",X"07",X"22",X"06",X"98",X"C3",X"FC",X"03",X"3A",X"02",X"98",X"E6",X"07",X"C0",X"2A", + X"06",X"98",X"7C",X"B5",X"CA",X"32",X"0C",X"CD",X"06",X"2D",X"28",X"5F",X"3A",X"16",X"98",X"CB", + X"47",X"28",X"2E",X"21",X"42",X"98",X"CB",X"4F",X"7E",X"32",X"43",X"98",X"28",X"0A",X"34",X"7E", + X"FE",X"1B",X"38",X"0B",X"36",X"00",X"18",X"07",X"7E",X"A7",X"20",X"02",X"36",X"1B",X"35",X"3A", + X"43",X"98",X"06",X"8E",X"CD",X"5F",X"0C",X"3A",X"42",X"98",X"06",X"95",X"CD",X"5F",X"0C",X"18", + X"2A",X"21",X"41",X"98",X"CB",X"4F",X"7E",X"32",X"44",X"98",X"28",X"0A",X"34",X"7E",X"FE",X"0C", + X"38",X"09",X"36",X"0B",X"18",X"05",X"7E",X"A7",X"28",X"01",X"35",X"3A",X"44",X"98",X"0E",X"8E", + X"CD",X"54",X"0C",X"3A",X"41",X"98",X"0E",X"95",X"CD",X"54",X"0C",X"CD",X"AB",X"1B",X"20",X"33", + X"3A",X"42",X"98",X"FE",X"1A",X"28",X"3B",X"21",X"E0",X"99",X"3A",X"41",X"98",X"CF",X"3A",X"42", + X"98",X"C6",X"41",X"77",X"21",X"41",X"98",X"7E",X"32",X"44",X"98",X"34",X"7E",X"FE",X"0C",X"38", + X"02",X"36",X"0B",X"3A",X"44",X"98",X"0E",X"8E",X"CD",X"54",X"0C",X"3A",X"41",X"98",X"0E",X"95", + X"CD",X"54",X"0C",X"21",X"E0",X"99",X"11",X"E4",X"85",X"06",X"0C",X"7E",X"12",X"23",X"D7",X"10", + X"FA",X"C9",X"ED",X"5B",X"52",X"98",X"13",X"21",X"E0",X"99",X"01",X"0C",X"00",X"ED",X"B0",X"CD", + X"88",X"19",X"C3",X"FC",X"03",X"CD",X"B9",X"19",X"D8",X"3E",X"1E",X"32",X"00",X"98",X"CD",X"1B", + X"03",X"C3",X"FC",X"03",X"11",X"C4",X"8D",X"3C",X"47",X"D7",X"10",X"FD",X"79",X"12",X"C9",X"21", + X"61",X"8F",X"4F",X"3E",X"1A",X"91",X"CF",X"70",X"EB",X"D7",X"78",X"12",X"D7",X"78",X"12",X"C9", + X"3A",X"00",X"98",X"A7",X"C0",X"CD",X"D1",X"1A",X"C0",X"3A",X"10",X"99",X"A7",X"C2",X"FC",X"03", + X"AF",X"32",X"20",X"99",X"3C",X"32",X"83",X"A1",X"32",X"2F",X"99",X"3E",X"03",X"32",X"21",X"99", + X"C9",X"3E",X"01",X"32",X"11",X"99",X"FD",X"21",X"17",X"99",X"DD",X"21",X"40",X"98",X"DD",X"36", + X"00",X"00",X"21",X"42",X"99",X"06",X"0A",X"C3",X"8C",X"0A",X"C3",X"29",X"0B",X"C3",X"2F",X"0B", + X"C3",X"79",X"0B",X"C3",X"45",X"0C",X"3A",X"00",X"98",X"A7",X"C0",X"CD",X"D1",X"1A",X"C0",X"AF", + X"32",X"20",X"99",X"3C",X"32",X"83",X"A1",X"32",X"2F",X"99",X"3E",X"03",X"32",X"21",X"99",X"C9", + X"21",X"EA",X"0C",X"E5",X"3A",X"21",X"99",X"F7",X"F7",X"0C",X"07",X"0D",X"17",X"0D",X"31",X"0D", + X"6F",X"0D",X"77",X"0D",X"21",X"0E",X"2C",X"0E",X"50",X"0E",X"3A",X"23",X"99",X"A7",X"C8",X"AF", + X"32",X"20",X"99",X"32",X"21",X"99",X"C9",X"AF",X"32",X"10",X"99",X"32",X"11",X"99",X"CD",X"75", + X"03",X"CD",X"27",X"03",X"C3",X"FC",X"03",X"3A",X"01",X"9F",X"32",X"01",X"99",X"CD",X"84",X"32", + X"C0",X"CD",X"C3",X"1A",X"C3",X"FC",X"03",X"CD",X"B8",X"1A",X"CD",X"0A",X"02",X"CD",X"DD",X"04", + X"21",X"00",X"9F",X"11",X"00",X"99",X"01",X"10",X"00",X"ED",X"B0",X"CD",X"06",X"19",X"C3",X"FC", + X"03",X"CD",X"1D",X"17",X"CD",X"72",X"17",X"CD",X"FB",X"17",X"CD",X"84",X"18",X"3A",X"03",X"99", + X"32",X"0F",X"99",X"CD",X"B8",X"3F",X"3E",X"3C",X"32",X"00",X"98",X"21",X"20",X"1C",X"22",X"06", + X"98",X"CD",X"65",X"2E",X"CD",X"25",X"2E",X"CD",X"E5",X"2D",X"CD",X"A0",X"2D",X"CD",X"63",X"1F", + X"CD",X"BA",X"1F",X"CD",X"09",X"20",X"CD",X"58",X"20",X"CD",X"AD",X"23",X"C3",X"FC",X"03",X"3A", + X"00",X"98",X"A7",X"C0",X"C3",X"FC",X"03",X"2A",X"06",X"98",X"7D",X"A7",X"CC",X"12",X"07",X"CD", + X"B0",X"3E",X"CD",X"47",X"2A",X"CD",X"65",X"2E",X"CD",X"A8",X"28",X"CD",X"25",X"2E",X"CD",X"F5", + X"26",X"CD",X"E5",X"2D",X"CD",X"E6",X"2B",X"CD",X"A0",X"2D",X"CD",X"63",X"1F",X"CD",X"BA",X"1F", + X"CD",X"09",X"20",X"CD",X"58",X"20",X"CD",X"AD",X"23",X"CD",X"A7",X"20",X"CD",X"A3",X"1C",X"CD", + X"C6",X"1B",X"CD",X"E5",X"1C",X"CD",X"54",X"1E",X"CD",X"3A",X"25",X"CD",X"7C",X"21",X"CD",X"E5", + X"21",X"CD",X"7D",X"22",X"CD",X"15",X"23",X"CD",X"3C",X"3F",X"CD",X"3C",X"3E",X"CD",X"D4",X"31", + X"3A",X"04",X"99",X"A7",X"28",X"3A",X"FD",X"21",X"80",X"98",X"DD",X"21",X"04",X"99",X"DD",X"7E", + X"01",X"FD",X"B6",X"01",X"CC",X"6B",X"17",X"DD",X"7E",X"02",X"FD",X"B6",X"02",X"CC",X"F4",X"17", + X"DD",X"7E",X"03",X"FD",X"B6",X"03",X"CC",X"7D",X"18",X"DD",X"7E",X"01",X"DD",X"B6",X"02",X"DD", + X"B6",X"03",X"C0",X"FD",X"7E",X"01",X"FD",X"B6",X"02",X"FD",X"B6",X"03",X"C0",X"C3",X"FC",X"03", + X"CD",X"0B",X"06",X"C0",X"3E",X"08",X"32",X"21",X"99",X"3E",X"78",X"32",X"00",X"98",X"C3",X"1B", + X"03",X"3E",X"78",X"32",X"00",X"98",X"CD",X"1B",X"03",X"C3",X"FC",X"03",X"3A",X"00",X"98",X"FE", + X"01",X"38",X"06",X"CA",X"05",X"1B",X"C3",X"E2",X"1E",X"CD",X"D1",X"1A",X"C0",X"21",X"00",X"99", + X"11",X"00",X"9F",X"01",X"10",X"00",X"ED",X"B0",X"3E",X"01",X"32",X"21",X"99",X"C3",X"41",X"03", + X"3A",X"00",X"98",X"FE",X"01",X"38",X"06",X"CA",X"05",X"1B",X"C3",X"E2",X"1E",X"CD",X"D1",X"1A", + X"C0",X"AF",X"32",X"20",X"99",X"3E",X"03",X"32",X"21",X"99",X"C9",X"21",X"95",X"0E",X"E5",X"3A", + X"21",X"99",X"F7",X"A2",X"0E",X"A5",X"0E",X"22",X"0F",X"84",X"0F",X"AE",X"0F",X"E1",X"0F",X"44", + X"10",X"60",X"10",X"6E",X"10",X"B4",X"10",X"D8",X"10",X"E0",X"10",X"36",X"11",X"52",X"11",X"66", + X"11",X"F3",X"11",X"FE",X"11",X"3A",X"23",X"99",X"A7",X"C8",X"AF",X"32",X"20",X"99",X"32",X"21", + X"99",X"C9",X"C3",X"FC",X"03",X"21",X"23",X"01",X"11",X"B0",X"84",X"0E",X"A3",X"CD",X"F2",X"30", + X"21",X"23",X"01",X"11",X"AA",X"84",X"0E",X"A3",X"CD",X"F2",X"30",X"21",X"98",X"01",X"11",X"7A", + X"86",X"0E",X"BA",X"CD",X"DA",X"16",X"21",X"A3",X"01",X"11",X"1A",X"85",X"0E",X"8E",X"CD",X"DA", + X"16",X"21",X"A9",X"01",X"11",X"B0",X"84",X"FF",X"21",X"A9",X"01",X"11",X"AA",X"84",X"FF",X"CD", + X"17",X"0F",X"DD",X"21",X"A0",X"13",X"21",X"78",X"86",X"CD",X"13",X"12",X"DD",X"21",X"A0",X"13", + X"21",X"76",X"86",X"CD",X"13",X"12",X"DD",X"21",X"A0",X"13",X"21",X"74",X"86",X"CD",X"13",X"12", + X"DD",X"21",X"8F",X"13",X"21",X"6E",X"86",X"CD",X"13",X"12",X"DD",X"21",X"A0",X"13",X"21",X"68", + X"86",X"CD",X"13",X"12",X"C3",X"FC",X"03",X"21",X"B0",X"01",X"11",X"42",X"85",X"0E",X"BA",X"C3", + X"DA",X"16",X"DD",X"21",X"CB",X"13",X"21",X"98",X"85",X"CD",X"18",X"12",X"DD",X"21",X"BE",X"13", + X"21",X"96",X"85",X"CD",X"18",X"12",X"DD",X"21",X"AD",X"13",X"21",X"94",X"85",X"CD",X"18",X"12", + X"DD",X"21",X"D4",X"13",X"21",X"8E",X"85",X"CD",X"18",X"12",X"DD",X"21",X"AD",X"13",X"21",X"88", + X"85",X"CD",X"18",X"12",X"3E",X"0A",X"32",X"F4",X"85",X"3C",X"32",X"14",X"86",X"3C",X"32",X"F6", + X"85",X"3C",X"32",X"16",X"86",X"3C",X"32",X"F8",X"85",X"3C",X"32",X"18",X"86",X"3E",X"BA",X"32", + X"F4",X"8D",X"32",X"14",X"8E",X"32",X"F6",X"8D",X"32",X"16",X"8E",X"32",X"F8",X"8D",X"32",X"18", + X"8E",X"C3",X"FC",X"03",X"AF",X"32",X"10",X"99",X"32",X"11",X"99",X"CD",X"75",X"03",X"CD",X"27", + X"03",X"CD",X"B8",X"1A",X"CD",X"C3",X"1A",X"21",X"00",X"9F",X"11",X"00",X"99",X"01",X"10",X"00", + X"ED",X"B0",X"AF",X"32",X"45",X"98",X"3E",X"3C",X"32",X"00",X"98",X"C3",X"FC",X"03",X"3A",X"00", + X"98",X"A7",X"C0",X"3A",X"45",X"98",X"21",X"57",X"12",X"87",X"4F",X"87",X"81",X"CF",X"7E",X"23", + X"5E",X"23",X"56",X"23",X"E5",X"EB",X"CD",X"E3",X"16",X"E1",X"7E",X"32",X"46",X"98",X"23",X"5E", + X"23",X"56",X"EB",X"CD",X"00",X"17",X"3E",X"20",X"32",X"62",X"98",X"32",X"65",X"98",X"C3",X"FC", + X"03",X"CD",X"89",X"3F",X"CD",X"E5",X"2D",X"CD",X"C9",X"3E",X"CD",X"A0",X"2D",X"CD",X"63",X"1F", + X"CD",X"BA",X"1F",X"CD",X"AD",X"23",X"CD",X"A7",X"20",X"CD",X"E5",X"1C",X"CD",X"3A",X"25",X"CD", + X"7C",X"21",X"CD",X"E5",X"21",X"FD",X"21",X"80",X"98",X"DD",X"21",X"04",X"99",X"DD",X"7E",X"00", + X"A7",X"28",X"16",X"DD",X"7E",X"01",X"FD",X"B6",X"01",X"C0",X"ED",X"5B",X"02",X"9B",X"3E",X"77", + X"CD",X"72",X"2D",X"3E",X"AB",X"12",X"C3",X"FC",X"03",X"FD",X"7E",X"00",X"A7",X"C0",X"3E",X"4A", + X"ED",X"5B",X"42",X"9B",X"CB",X"DA",X"12",X"CB",X"9A",X"3E",X"76",X"CD",X"72",X"2D",X"3E",X"4A", + X"12",X"C3",X"FC",X"03",X"21",X"45",X"98",X"34",X"7E",X"FE",X"03",X"30",X"0B",X"3E",X"04",X"32", + X"21",X"99",X"3E",X"3C",X"32",X"00",X"98",X"C9",X"3E",X"3C",X"32",X"00",X"98",X"C3",X"FC",X"03", + X"3A",X"00",X"98",X"A7",X"C0",X"CD",X"FC",X"03",X"AF",X"32",X"12",X"9C",X"18",X"18",X"3A",X"00", + X"98",X"A7",X"C0",X"AF",X"32",X"10",X"9C",X"32",X"12",X"9C",X"21",X"00",X"9B",X"CD",X"47",X"1B", + X"21",X"40",X"9B",X"CD",X"47",X"1B",X"3A",X"45",X"98",X"21",X"57",X"12",X"87",X"4F",X"87",X"81", + X"CF",X"7E",X"23",X"5E",X"23",X"56",X"23",X"E5",X"EB",X"CD",X"E3",X"16",X"E1",X"7E",X"32",X"46", + X"98",X"23",X"5E",X"23",X"56",X"EB",X"CD",X"00",X"17",X"3E",X"20",X"32",X"62",X"98",X"32",X"65", + X"98",X"C3",X"FC",X"03",X"21",X"70",X"85",X"11",X"20",X"00",X"06",X"04",X"36",X"20",X"19",X"10", + X"FB",X"CD",X"E5",X"2D",X"CD",X"A0",X"2D",X"CD",X"BA",X"1F",X"CD",X"63",X"1F",X"CD",X"AD",X"23", + X"3E",X"3C",X"32",X"00",X"98",X"C3",X"FC",X"03",X"3A",X"00",X"98",X"A7",X"C0",X"C3",X"FC",X"03", + X"CD",X"89",X"3F",X"CD",X"E5",X"2D",X"CD",X"C9",X"3E",X"CD",X"A0",X"2D",X"CD",X"63",X"1F",X"CD", + X"BA",X"1F",X"CD",X"AD",X"23",X"CD",X"A7",X"20",X"CD",X"E5",X"1C",X"CD",X"3A",X"25",X"CD",X"7C", + X"21",X"CD",X"E5",X"21",X"FD",X"21",X"80",X"98",X"DD",X"21",X"04",X"99",X"DD",X"7E",X"00",X"FD", + X"B6",X"00",X"CA",X"FC",X"03",X"DD",X"7E",X"01",X"FD",X"B6",X"01",X"CA",X"FC",X"03",X"3A",X"46", + X"98",X"21",X"68",X"21",X"DF",X"7B",X"32",X"42",X"98",X"7A",X"11",X"70",X"85",X"CD",X"B1",X"30", + X"3A",X"42",X"98",X"C3",X"B6",X"30",X"21",X"45",X"98",X"34",X"7E",X"FE",X"0B",X"30",X"0B",X"3E", + X"08",X"32",X"21",X"99",X"3E",X"3C",X"32",X"00",X"98",X"C9",X"3E",X"3C",X"32",X"00",X"98",X"C3", + X"FC",X"03",X"3A",X"00",X"98",X"A7",X"C0",X"ED",X"5B",X"02",X"9B",X"3E",X"77",X"CD",X"72",X"2D", + X"3E",X"AB",X"12",X"C3",X"AE",X"0F",X"AF",X"32",X"62",X"98",X"32",X"65",X"98",X"CD",X"C1",X"11", + X"3A",X"05",X"99",X"A7",X"28",X"0F",X"3A",X"02",X"98",X"E6",X"3F",X"20",X"08",X"3E",X"FF",X"32", + X"70",X"98",X"CD",X"E5",X"11",X"CD",X"E5",X"2D",X"CD",X"A0",X"2D",X"CD",X"63",X"1F",X"CD",X"BA", + X"1F",X"CD",X"AD",X"23",X"CD",X"A3",X"1C",X"CD",X"E5",X"1C",X"CD",X"3A",X"25",X"CD",X"7C",X"21", + X"CD",X"E5",X"21",X"FD",X"21",X"80",X"98",X"DD",X"21",X"04",X"99",X"DD",X"7E",X"01",X"FD",X"B6", + X"01",X"C0",X"ED",X"5B",X"02",X"9B",X"3E",X"77",X"CD",X"72",X"2D",X"3E",X"AB",X"12",X"C3",X"FC", + X"03",X"3A",X"47",X"98",X"A7",X"C8",X"AF",X"32",X"47",X"98",X"3A",X"05",X"99",X"A7",X"28",X"08", + X"11",X"AA",X"85",X"3E",X"60",X"C3",X"B6",X"30",X"3E",X"05",X"11",X"6A",X"85",X"CD",X"B1",X"30", + X"3E",X"00",X"C3",X"B6",X"30",X"21",X"6A",X"85",X"11",X"20",X"00",X"06",X"04",X"36",X"20",X"19", + X"10",X"FB",X"C9",X"3E",X"3C",X"32",X"00",X"98",X"CD",X"1B",X"03",X"C3",X"FC",X"03",X"3A",X"00", + X"98",X"A7",X"C0",X"CD",X"D1",X"1A",X"C0",X"CD",X"88",X"19",X"32",X"20",X"99",X"3E",X"04",X"32", + X"21",X"99",X"C9",X"11",X"20",X"00",X"18",X"03",X"11",X"E0",X"FF",X"DD",X"46",X"00",X"DD",X"23", + X"DD",X"7E",X"00",X"77",X"DD",X"23",X"DD",X"7E",X"00",X"CB",X"DC",X"77",X"CB",X"9C",X"19",X"10", + X"01",X"C9",X"05",X"28",X"13",X"DD",X"23",X"DD",X"7E",X"00",X"77",X"DD",X"23",X"DD",X"7E",X"00", + X"CB",X"DC",X"77",X"CB",X"9C",X"19",X"10",X"ED",X"DD",X"23",X"DD",X"7E",X"00",X"77",X"DD",X"23", + X"DD",X"7E",X"00",X"CB",X"DC",X"77",X"C9",X"06",X"9F",X"12",X"04",X"17",X"13",X"06",X"B7",X"12", + X"06",X"2F",X"13",X"06",X"CF",X"12",X"08",X"47",X"13",X"08",X"E7",X"12",X"08",X"5F",X"13",X"08", + X"E7",X"12",X"07",X"5F",X"13",X"08",X"E7",X"12",X"06",X"5F",X"13",X"08",X"E7",X"12",X"05",X"5F", + X"13",X"08",X"E7",X"12",X"04",X"5F",X"13",X"08",X"E7",X"12",X"03",X"5F",X"13",X"08",X"E7",X"12", + X"02",X"5F",X"13",X"08",X"E7",X"12",X"01",X"5F",X"13",X"06",X"FF",X"12",X"08",X"77",X"13",X"58", + X"86",X"78",X"86",X"98",X"86",X"B8",X"86",X"D8",X"86",X"F8",X"86",X"18",X"87",X"38",X"87",X"58", + X"87",X"78",X"87",X"98",X"87",X"B8",X"87",X"56",X"86",X"76",X"86",X"96",X"86",X"B6",X"86",X"D6", + X"86",X"F6",X"86",X"16",X"87",X"36",X"87",X"56",X"87",X"76",X"87",X"96",X"87",X"B6",X"87",X"54", + X"86",X"74",X"86",X"94",X"86",X"B4",X"86",X"D4",X"86",X"F4",X"86",X"14",X"87",X"34",X"87",X"54", + X"87",X"74",X"87",X"94",X"87",X"B4",X"87",X"4E",X"86",X"6E",X"86",X"8E",X"86",X"AE",X"86",X"CE", + X"86",X"EE",X"86",X"0E",X"87",X"2E",X"87",X"4E",X"87",X"6E",X"87",X"8E",X"87",X"AE",X"87",X"48", + X"86",X"68",X"86",X"88",X"86",X"A8",X"86",X"C8",X"86",X"E8",X"86",X"08",X"87",X"28",X"87",X"48", + X"87",X"68",X"87",X"88",X"87",X"A8",X"87",X"B8",X"85",X"98",X"85",X"78",X"85",X"58",X"85",X"38", + X"85",X"18",X"85",X"F8",X"84",X"D8",X"84",X"B8",X"84",X"98",X"84",X"78",X"84",X"58",X"84",X"B6", + X"85",X"96",X"85",X"76",X"85",X"56",X"85",X"36",X"85",X"16",X"85",X"F6",X"84",X"D6",X"84",X"B6", + X"84",X"96",X"84",X"76",X"84",X"56",X"84",X"B4",X"85",X"94",X"85",X"74",X"85",X"54",X"85",X"34", + X"85",X"14",X"85",X"F4",X"84",X"D4",X"84",X"B4",X"84",X"94",X"84",X"74",X"84",X"54",X"84",X"AE", + X"85",X"8E",X"85",X"6E",X"85",X"4E",X"85",X"2E",X"85",X"0E",X"85",X"EE",X"84",X"CE",X"84",X"AE", + X"84",X"8E",X"84",X"6E",X"84",X"5E",X"84",X"A8",X"85",X"88",X"85",X"68",X"85",X"48",X"85",X"28", + X"85",X"08",X"85",X"E8",X"84",X"C8",X"84",X"A8",X"84",X"88",X"84",X"68",X"84",X"58",X"84",X"08", + X"77",X"AB",X"80",X"B0",X"80",X"B0",X"80",X"B0",X"80",X"B0",X"80",X"B0",X"A0",X"B0",X"C0",X"6A", + X"06",X"77",X"AB",X"80",X"B0",X"80",X"B0",X"80",X"B0",X"80",X"B0",X"C0",X"6A",X"08",X"76",X"4A", + X"80",X"88",X"80",X"88",X"80",X"88",X"80",X"88",X"80",X"88",X"A0",X"88",X"C0",X"88",X"06",X"76", + X"56",X"80",X"98",X"80",X"98",X"80",X"98",X"80",X"98",X"C0",X"98",X"04",X"76",X"4F",X"80",X"90", + X"80",X"90",X"C0",X"90",X"08",X"76",X"56",X"80",X"98",X"80",X"98",X"80",X"98",X"80",X"98",X"80", + X"98",X"A0",X"98",X"C0",X"98",X"07",X"76",X"4F",X"80",X"90",X"80",X"90",X"80",X"90",X"80",X"90", + X"A0",X"90",X"C0",X"90",X"06",X"76",X"4F",X"80",X"90",X"80",X"90",X"80",X"90",X"A0",X"90",X"C0", + X"90",X"05",X"76",X"4F",X"80",X"90",X"80",X"90",X"A0",X"90",X"C0",X"90",X"04",X"76",X"4F",X"80", + X"90",X"A0",X"90",X"C0",X"90",X"03",X"76",X"4F",X"A0",X"90",X"C0",X"90",X"02",X"76",X"4F",X"C0", + X"90",X"01",X"76",X"4F",X"3A",X"00",X"40",X"FE",X"55",X"CA",X"00",X"40",X"31",X"00",X"A0",X"ED", + X"46",X"F3",X"32",X"80",X"A0",X"21",X"00",X"98",X"11",X"01",X"98",X"01",X"00",X"08",X"36",X"00", + X"ED",X"B0",X"21",X"00",X"80",X"06",X"40",X"36",X"00",X"23",X"10",X"FB",X"01",X"C0",X"07",X"11", + X"41",X"80",X"36",X"20",X"ED",X"B0",X"32",X"80",X"A0",X"21",X"00",X"88",X"06",X"08",X"36",X"BA", + X"23",X"10",X"FB",X"06",X"18",X"36",X"20",X"23",X"10",X"FB",X"21",X"00",X"88",X"11",X"20",X"88", + X"01",X"E0",X"03",X"ED",X"B0",X"21",X"00",X"88",X"06",X"40",X"36",X"00",X"23",X"10",X"FB",X"21", + X"42",X"88",X"11",X"20",X"00",X"06",X"1C",X"36",X"8E",X"19",X"10",X"FB",X"21",X"00",X"8C",X"11", + X"01",X"8C",X"01",X"00",X"04",X"36",X"48",X"ED",X"B0",X"21",X"3F",X"A0",X"06",X"10",X"36",X"00", + X"23",X"10",X"FB",X"21",X"80",X"A1",X"06",X"08",X"36",X"00",X"23",X"10",X"FB",X"21",X"21",X"15", + X"11",X"00",X"9E",X"01",X"11",X"00",X"ED",X"B0",X"21",X"32",X"15",X"11",X"40",X"99",X"01",X"A0", + X"00",X"ED",X"B0",X"3E",X"02",X"32",X"1E",X"99",X"3A",X"80",X"A1",X"2F",X"4F",X"07",X"E6",X"01", + X"32",X"34",X"99",X"79",X"07",X"07",X"E6",X"01",X"32",X"2E",X"99",X"79",X"E6",X"07",X"21",X"19", + X"15",X"CF",X"7E",X"32",X"26",X"99",X"79",X"0F",X"0F",X"0F",X"E6",X"07",X"21",X"19",X"15",X"CF", + X"7E",X"32",X"29",X"99",X"AF",X"CD",X"78",X"33",X"3E",X"00",X"32",X"2D",X"99",X"3E",X"01",X"32", + X"83",X"A1",X"32",X"2F",X"99",X"3A",X"34",X"99",X"A7",X"C2",X"DF",X"15",X"C3",X"D2",X"15",X"3E", + X"01",X"32",X"81",X"A1",X"32",X"80",X"A0",X"18",X"FE",X"01",X"02",X"03",X"04",X"11",X"21",X"31", + X"33",X"FF",X"05",X"F6",X"80",X"32",X"17",X"9C",X"C9",X"DD",X"21",X"74",X"98",X"FD",X"BF",X"24", + X"AE",X"46",X"00",X"00",X"02",X"48",X"49",X"52",X"4F",X"53",X"48",X"49",X"54",X"41",X"5B",X"5B", + X"5B",X"5B",X"80",X"99",X"01",X"49",X"4E",X"4F",X"55",X"45",X"5B",X"5B",X"5B",X"5B",X"5B",X"5B", + X"5B",X"5B",X"50",X"88",X"01",X"4E",X"55",X"4D",X"41",X"5B",X"5B",X"5B",X"5B",X"5B",X"5B",X"5B", + X"5B",X"5B",X"00",X"64",X"01",X"46",X"55",X"4A",X"49",X"4E",X"41",X"4B",X"41",X"5B",X"5B",X"5B", + X"5B",X"5B",X"10",X"13",X"01",X"46",X"55",X"4B",X"55",X"54",X"41",X"4B",X"45",X"5B",X"5B",X"5B", + X"5B",X"5B",X"60",X"05",X"01",X"54",X"41",X"4D",X"4F",X"54",X"53",X"55",X"5B",X"5B",X"5B",X"5B", + X"5B",X"5B",X"90",X"90",X"00",X"4F",X"53",X"48",X"49",X"54",X"41",X"5B",X"5B",X"5B",X"5B",X"5B", + X"5B",X"5B",X"30",X"90",X"00",X"54",X"53",X"55",X"44",X"41",X"5B",X"5B",X"5B",X"5B",X"5B",X"5B", + X"5B",X"5B",X"90",X"86",X"00",X"4D",X"49",X"59",X"4F",X"53",X"48",X"49",X"5B",X"5B",X"5B",X"5B", + X"5B",X"5B",X"10",X"82",X"00",X"48",X"41",X"52",X"41",X"5B",X"54",X"5B",X"5B",X"5B",X"5B",X"5B", + X"5B",X"5B",X"11",X"BA",X"84",X"21",X"D3",X"16",X"0E",X"8E",X"CD",X"DA",X"16",X"18",X"16",X"11", + X"44",X"80",X"21",X"BF",X"16",X"0E",X"87",X"CD",X"DA",X"16",X"11",X"BA",X"84",X"21",X"BF",X"16", + X"0E",X"87",X"CD",X"DA",X"16",X"11",X"B8",X"84",X"21",X"A3",X"16",X"0E",X"BA",X"CD",X"DA",X"16", + X"11",X"F8",X"85",X"21",X"B3",X"16",X"0E",X"BA",X"CD",X"DA",X"16",X"11",X"D8",X"86",X"21",X"B9", + X"16",X"0E",X"BA",X"CD",X"DA",X"16",X"11",X"98",X"85",X"3A",X"26",X"99",X"0F",X"0F",X"0F",X"0F", + X"E6",X"07",X"3C",X"CD",X"B1",X"30",X"11",X"78",X"86",X"3A",X"26",X"99",X"E6",X"07",X"CD",X"B1", + X"30",X"11",X"B6",X"84",X"21",X"AB",X"16",X"0E",X"BA",X"CD",X"DA",X"16",X"11",X"F6",X"85",X"21", + X"B3",X"16",X"0E",X"BA",X"CD",X"DA",X"16",X"11",X"D6",X"86",X"21",X"B9",X"16",X"0E",X"BA",X"CD", + X"DA",X"16",X"11",X"96",X"85",X"3A",X"29",X"99",X"0F",X"0F",X"0F",X"0F",X"E6",X"07",X"3C",X"CD", + X"B1",X"30",X"11",X"76",X"86",X"3A",X"29",X"99",X"E6",X"07",X"CD",X"B1",X"30",X"11",X"B4",X"84", + X"0E",X"BA",X"21",X"CD",X"16",X"3A",X"2E",X"99",X"A7",X"28",X"03",X"21",X"C4",X"16",X"CD",X"DA", + X"16",X"06",X"06",X"C5",X"06",X"00",X"C5",X"32",X"80",X"A0",X"3E",X"87",X"32",X"B8",X"8D",X"32", + X"98",X"8E",X"32",X"B6",X"8D",X"32",X"96",X"8E",X"10",X"F0",X"C1",X"10",X"E9",X"C1",X"10",X"E3", + X"C3",X"0F",X"15",X"43",X"4F",X"49",X"4E",X"01",X"20",X"20",X"40",X"43",X"4F",X"49",X"4E",X"02", + X"20",X"20",X"40",X"43",X"4F",X"49",X"4E",X"20",X"40",X"50",X"4C",X"41",X"59",X"20",X"40",X"54", + X"45",X"53",X"54",X"40",X"55",X"50",X"20",X"52",X"49",X"47",X"48",X"54",X"40",X"54",X"41",X"42", + X"4C",X"45",X"40",X"4E",X"4F",X"52",X"4D",X"41",X"4C",X"40",X"E5",X"D5",X"CD",X"F2",X"30",X"D1", + X"E1",X"FF",X"C9",X"11",X"00",X"9B",X"01",X"18",X"00",X"ED",X"B0",X"32",X"04",X"99",X"21",X"80", + X"9A",X"11",X"81",X"9A",X"01",X"0C",X"00",X"36",X"00",X"ED",X"B0",X"AF",X"32",X"60",X"98",X"C9", + X"11",X"40",X"9B",X"01",X"18",X"00",X"ED",X"B0",X"32",X"05",X"99",X"21",X"A0",X"9A",X"11",X"A1", + X"9A",X"01",X"0C",X"00",X"36",X"02",X"ED",X"B0",X"AF",X"32",X"63",X"98",X"C9",X"21",X"04",X"99", + X"7E",X"A7",X"20",X"03",X"3E",X"08",X"77",X"CD",X"4F",X"1E",X"32",X"62",X"98",X"21",X"48",X"17", + X"11",X"80",X"9A",X"01",X"0C",X"00",X"ED",X"B0",X"21",X"53",X"17",X"11",X"00",X"9B",X"01",X"18", + X"00",X"ED",X"B0",X"AF",X"32",X"60",X"98",X"C9",X"01",X"01",X"05",X"10",X"0F",X"0A",X"05",X"00", + X"02",X"10",X"07",X"EF",X"85",X"EE",X"85",X"ED",X"85",X"0D",X"86",X"0E",X"86",X"EE",X"85",X"ED", + X"85",X"0D",X"86",X"ED",X"85",X"0D",X"86",X"0E",X"86",X"EE",X"85",X"3A",X"03",X"99",X"E6",X"03", + X"28",X"44",X"21",X"79",X"84",X"22",X"40",X"9B",X"21",X"7A",X"84",X"22",X"42",X"9B",X"21",X"42", + X"9B",X"11",X"44",X"9B",X"01",X"16",X"00",X"ED",X"B0",X"3A",X"05",X"99",X"A7",X"20",X"0F",X"21", + X"03",X"99",X"7E",X"A7",X"C8",X"35",X"CD",X"B8",X"3F",X"3E",X"09",X"32",X"05",X"99",X"CD",X"40", + X"1E",X"32",X"65",X"98",X"21",X"A0",X"9A",X"11",X"A1",X"9A",X"01",X"0C",X"00",X"36",X"03",X"ED", + X"B0",X"AF",X"32",X"63",X"98",X"C9",X"21",X"7A",X"87",X"22",X"40",X"9B",X"21",X"9A",X"87",X"22", + X"42",X"9B",X"21",X"42",X"9B",X"11",X"44",X"9B",X"01",X"16",X"00",X"ED",X"B0",X"21",X"03",X"99", + X"7E",X"A7",X"C8",X"35",X"CD",X"B8",X"3F",X"3E",X"09",X"32",X"05",X"99",X"CD",X"40",X"1E",X"32", + X"65",X"98",X"21",X"A0",X"9A",X"11",X"A1",X"9A",X"01",X"0C",X"00",X"36",X"00",X"ED",X"B0",X"AF", + X"32",X"63",X"98",X"C9",X"3A",X"03",X"99",X"E6",X"03",X"28",X"44",X"21",X"82",X"84",X"22",X"80", + X"9B",X"21",X"62",X"84",X"22",X"82",X"9B",X"21",X"82",X"9B",X"11",X"84",X"9B",X"01",X"16",X"00", + X"ED",X"B0",X"3A",X"06",X"99",X"A7",X"20",X"0F",X"21",X"03",X"99",X"7E",X"A7",X"C8",X"35",X"CD", + X"B8",X"3F",X"3E",X"09",X"32",X"06",X"99",X"CD",X"40",X"1E",X"32",X"68",X"98",X"21",X"C0",X"9A", + X"11",X"C1",X"9A",X"01",X"0C",X"00",X"36",X"02",X"ED",X"B0",X"AF",X"32",X"66",X"98",X"C9",X"21", + X"7A",X"87",X"22",X"80",X"9B",X"21",X"9A",X"87",X"22",X"82",X"9B",X"21",X"82",X"9B",X"11",X"84", + X"9B",X"01",X"16",X"00",X"ED",X"B0",X"21",X"03",X"99",X"7E",X"A7",X"C8",X"35",X"CD",X"B8",X"3F", + X"3E",X"09",X"32",X"06",X"99",X"CD",X"40",X"1E",X"32",X"68",X"98",X"21",X"C0",X"9A",X"11",X"C1", + X"9A",X"01",X"0C",X"00",X"36",X"00",X"ED",X"B0",X"AF",X"32",X"66",X"98",X"C9",X"3A",X"03",X"99", + X"E6",X"03",X"28",X"44",X"21",X"83",X"87",X"22",X"C0",X"9B",X"21",X"82",X"87",X"22",X"C2",X"9B", + X"21",X"C2",X"9B",X"11",X"C4",X"9B",X"01",X"16",X"00",X"ED",X"B0",X"3A",X"07",X"99",X"A7",X"20", + X"0F",X"21",X"03",X"99",X"7E",X"A7",X"C8",X"35",X"CD",X"B8",X"3F",X"3E",X"09",X"32",X"07",X"99", + X"CD",X"40",X"1E",X"32",X"6B",X"98",X"21",X"E0",X"9A",X"11",X"E1",X"9A",X"01",X"0C",X"00",X"36", + X"01",X"ED",X"B0",X"AF",X"32",X"69",X"98",X"C9",X"21",X"7A",X"87",X"22",X"C0",X"9B",X"21",X"9A", + X"87",X"22",X"C2",X"9B",X"21",X"C2",X"9B",X"11",X"C4",X"9B",X"01",X"16",X"00",X"ED",X"B0",X"21", + X"03",X"99",X"7E",X"A7",X"C8",X"35",X"CD",X"B8",X"3F",X"3E",X"09",X"32",X"07",X"99",X"CD",X"40", + X"1E",X"32",X"6B",X"98",X"21",X"E0",X"9A",X"11",X"E1",X"9A",X"01",X"0C",X"00",X"36",X"00",X"ED", + X"B0",X"AF",X"32",X"69",X"98",X"C9",X"21",X"A7",X"80",X"11",X"E0",X"FF",X"3A",X"00",X"99",X"FE", + X"05",X"30",X"1C",X"4F",X"3E",X"04",X"91",X"28",X"06",X"47",X"36",X"20",X"19",X"10",X"FB",X"79", + X"A7",X"28",X"0C",X"47",X"36",X"5E",X"CB",X"DC",X"36",X"AB",X"CB",X"9C",X"19",X"10",X"F5",X"21", + X"24",X"81",X"11",X"E0",X"FF",X"3A",X"0A",X"99",X"FE",X"09",X"D0",X"4F",X"3E",X"08",X"91",X"28", + X"06",X"47",X"36",X"20",X"19",X"10",X"FB",X"79",X"A7",X"C8",X"47",X"36",X"5F",X"CB",X"DC",X"36", + X"AB",X"CB",X"9C",X"19",X"10",X"F5",X"C9",X"3A",X"01",X"99",X"FE",X"19",X"D0",X"4F",X"21",X"A7", + X"8B",X"11",X"E0",X"FF",X"06",X"06",X"36",X"89",X"19",X"36",X"89",X"19",X"36",X"89",X"19",X"36", + X"95",X"19",X"10",X"F2",X"21",X"A7",X"83",X"41",X"36",X"5D",X"19",X"10",X"FB",X"3E",X"18",X"91", + X"C8",X"47",X"36",X"20",X"19",X"10",X"FB",X"C9",X"11",X"78",X"8C",X"01",X"18",X"04",X"3E",X"8E", + X"CD",X"6D",X"1A",X"11",X"18",X"8D",X"01",X"18",X"06",X"3E",X"BA",X"CD",X"6D",X"1A",X"11",X"F8", + X"8D",X"01",X"13",X"0C",X"3E",X"95",X"CD",X"6D",X"1A",X"21",X"8A",X"01",X"11",X"3A",X"85",X"0E", + X"BE",X"CD",X"DA",X"16",X"AF",X"32",X"40",X"98",X"C9",X"3A",X"02",X"98",X"E6",X"01",X"FE",X"01", + X"D8",X"11",X"D8",X"84",X"21",X"47",X"1A",X"3A",X"40",X"98",X"47",X"A7",X"28",X"05",X"23",X"1B", + X"1B",X"10",X"FB",X"7E",X"12",X"11",X"B8",X"84",X"21",X"51",X"1A",X"3A",X"40",X"98",X"47",X"A7", + X"28",X"05",X"23",X"1B",X"1B",X"10",X"FB",X"7E",X"12",X"11",X"78",X"84",X"3A",X"40",X"98",X"47", + X"A7",X"28",X"04",X"1B",X"1B",X"10",X"FC",X"C6",X"01",X"27",X"CD",X"B1",X"30",X"11",X"18",X"85", + X"21",X"42",X"99",X"01",X"10",X"00",X"3A",X"40",X"98",X"A7",X"28",X"06",X"1B",X"1B",X"09",X"3D", + X"20",X"FA",X"06",X"00",X"7E",X"CD",X"C9",X"30",X"2B",X"7E",X"CD",X"C9",X"30",X"2B",X"7E",X"CD", + X"B6",X"30",X"11",X"F8",X"85",X"21",X"43",X"99",X"01",X"10",X"00",X"3A",X"40",X"98",X"A7",X"28", + X"06",X"1B",X"1B",X"09",X"3D",X"20",X"FA",X"06",X"0C",X"7E",X"12",X"23",X"D7",X"10",X"FA",X"21", + X"40",X"98",X"34",X"7E",X"FE",X"0A",X"C9",X"54",X"44",X"44",X"48",X"48",X"48",X"48",X"48",X"48", + X"48",X"53",X"4E",X"52",X"54",X"54",X"54",X"54",X"54",X"54",X"54",X"11",X"9B",X"87",X"06",X"1A", + X"3E",X"41",X"12",X"1B",X"3C",X"10",X"FB",X"EF",X"21",X"9F",X"01",X"FF",X"C9",X"C5",X"41",X"D5", + X"12",X"1B",X"10",X"FC",X"D1",X"F5",X"D7",X"F1",X"C1",X"10",X"F2",X"C9",X"21",X"40",X"98",X"7E", + X"C6",X"01",X"27",X"77",X"21",X"2F",X"01",X"11",X"82",X"81",X"D5",X"E5",X"FF",X"21",X"1F",X"FF", + X"19",X"EB",X"3A",X"1E",X"99",X"06",X"00",X"CD",X"C9",X"30",X"3A",X"1D",X"99",X"CD",X"C9",X"30", + X"3A",X"1C",X"99",X"CD",X"B6",X"30",X"E1",X"D1",X"0E",X"87",X"C3",X"F2",X"30",X"21",X"12",X"99", + X"06",X"0A",X"36",X"00",X"23",X"10",X"FB",X"C9",X"21",X"00",X"98",X"06",X"00",X"36",X"00",X"23", + X"10",X"FB",X"C9",X"21",X"00",X"9A",X"11",X"01",X"9A",X"01",X"FF",X"03",X"36",X"00",X"ED",X"B0", + X"C9",X"AF",X"21",X"34",X"9C",X"06",X"08",X"77",X"23",X"10",X"FC",X"32",X"10",X"9C",X"32",X"12", + X"9C",X"32",X"14",X"9C",X"32",X"16",X"9C",X"32",X"18",X"9C",X"32",X"1A",X"9C",X"2A",X"52",X"98", + X"06",X"20",X"36",X"20",X"CB",X"DC",X"36",X"BF",X"CB",X"9C",X"23",X"10",X"F5",X"22",X"52",X"98", + X"21",X"01",X"98",X"35",X"C9",X"21",X"A4",X"83",X"11",X"E0",X"FF",X"06",X"08",X"36",X"20",X"19", + X"10",X"FB",X"AF",X"21",X"34",X"9C",X"06",X"08",X"77",X"23",X"10",X"FC",X"32",X"00",X"9D",X"21", + X"00",X"9B",X"CD",X"47",X"1B",X"21",X"40",X"9B",X"CD",X"47",X"1B",X"21",X"80",X"9B",X"CD",X"47", + X"1B",X"21",X"C0",X"9B",X"AF",X"32",X"10",X"9C",X"32",X"12",X"9C",X"32",X"14",X"9C",X"32",X"16", + X"9C",X"32",X"18",X"9C",X"32",X"1A",X"9C",X"06",X"0A",X"3E",X"20",X"5E",X"23",X"56",X"23",X"7B", + X"B2",X"28",X"03",X"3E",X"20",X"12",X"10",X"F3",X"C9",X"CD",X"AB",X"1B",X"C0",X"3A",X"04",X"99", + X"A7",X"C8",X"DD",X"21",X"74",X"98",X"DD",X"7E",X"00",X"A7",X"28",X"07",X"DD",X"23",X"DD",X"7E", + X"00",X"A7",X"C0",X"CD",X"A5",X"33",X"3A",X"61",X"98",X"DD",X"77",X"10",X"3A",X"6C",X"98",X"DD", + X"77",X"20",X"3A",X"80",X"9A",X"E6",X"03",X"87",X"21",X"A3",X"1B",X"CF",X"7E",X"DD",X"77",X"30", + X"23",X"7E",X"DD",X"77",X"40",X"3E",X"FF",X"DD",X"77",X"00",X"C9",X"02",X"00",X"00",X"02",X"FE", + X"00",X"00",X"FE",X"03",X"00",X"00",X"03",X"FD",X"00",X"00",X"FD",X"21",X"15",X"98",X"3A",X"2F", + X"99",X"A7",X"3A",X"04",X"98",X"28",X"03",X"3A",X"03",X"98",X"0F",X"0F",X"0F",X"0F",X"CB",X"16", + X"7E",X"E6",X"07",X"FE",X"01",X"C9",X"3A",X"71",X"98",X"A7",X"28",X"07",X"DD",X"21",X"76",X"98", + X"CD",X"27",X"1C",X"3A",X"72",X"98",X"A7",X"28",X"07",X"DD",X"21",X"78",X"98",X"CD",X"65",X"1C", + X"3A",X"73",X"98",X"A7",X"C8",X"DD",X"21",X"7A",X"98",X"DD",X"7E",X"00",X"A7",X"28",X"07",X"DD", + X"23",X"DD",X"7E",X"00",X"A7",X"C0",X"3A",X"02",X"98",X"E6",X"0F",X"C0",X"32",X"73",X"98",X"CD", + X"A9",X"33",X"3A",X"6A",X"98",X"DD",X"77",X"10",X"3A",X"6F",X"98",X"DD",X"77",X"20",X"3A",X"E0", + X"9A",X"E6",X"03",X"87",X"21",X"9B",X"1B",X"CF",X"7E",X"DD",X"77",X"30",X"23",X"7E",X"DD",X"77", + X"40",X"3E",X"FF",X"DD",X"77",X"00",X"C9",X"DD",X"7E",X"00",X"A7",X"28",X"07",X"DD",X"23",X"DD", + X"7E",X"00",X"A7",X"C0",X"3A",X"02",X"98",X"E6",X"0F",X"C0",X"32",X"71",X"98",X"CD",X"A9",X"33", + X"3A",X"64",X"98",X"DD",X"77",X"10",X"3A",X"6D",X"98",X"DD",X"77",X"20",X"3A",X"A0",X"9A",X"E6", + X"03",X"87",X"21",X"9B",X"1B",X"CF",X"7E",X"DD",X"77",X"30",X"23",X"7E",X"DD",X"77",X"40",X"3E", + X"FF",X"DD",X"77",X"00",X"C9",X"DD",X"7E",X"00",X"A7",X"28",X"07",X"DD",X"23",X"DD",X"7E",X"00", + X"A7",X"C0",X"3A",X"02",X"98",X"E6",X"0F",X"C0",X"32",X"72",X"98",X"CD",X"A9",X"33",X"3A",X"67", + X"98",X"DD",X"77",X"10",X"3A",X"6E",X"98",X"DD",X"77",X"20",X"3A",X"C0",X"9A",X"E6",X"03",X"87", + X"21",X"9B",X"1B",X"CF",X"7E",X"DD",X"77",X"30",X"23",X"7E",X"DD",X"77",X"40",X"3E",X"FF",X"DD", + X"77",X"00",X"C9",X"3A",X"70",X"98",X"A7",X"C8",X"AF",X"32",X"70",X"98",X"DD",X"21",X"74",X"98", + X"DD",X"7E",X"00",X"A7",X"28",X"07",X"DD",X"23",X"DD",X"7E",X"00",X"A7",X"C0",X"CD",X"A5",X"33", + X"3A",X"61",X"98",X"DD",X"77",X"10",X"3A",X"6C",X"98",X"DD",X"77",X"20",X"3A",X"80",X"9A",X"E6", + X"03",X"87",X"21",X"A3",X"1B",X"CF",X"7E",X"DD",X"77",X"30",X"23",X"7E",X"DD",X"77",X"40",X"3E", + X"FF",X"DD",X"77",X"00",X"C9",X"FD",X"21",X"74",X"98",X"CD",X"EE",X"1C",X"FD",X"23",X"FD",X"7E", + X"00",X"A7",X"C8",X"FD",X"7E",X"20",X"FD",X"86",X"40",X"FD",X"77",X"20",X"4F",X"FD",X"7E",X"10", + X"FD",X"86",X"30",X"FD",X"77",X"10",X"2F",X"E6",X"F8",X"26",X"00",X"6F",X"29",X"29",X"79",X"E6", + X"F8",X"0F",X"0F",X"0F",X"CF",X"11",X"00",X"84",X"19",X"7E",X"FE",X"E8",X"D2",X"DF",X"1D",X"EB", + X"3A",X"05",X"99",X"A7",X"28",X"3B",X"DD",X"21",X"C4",X"98",X"CD",X"E4",X"1D",X"20",X"32",X"21", + X"05",X"99",X"35",X"20",X"1E",X"AF",X"32",X"71",X"98",X"3E",X"40",X"32",X"81",X"98",X"CD",X"BF", + X"31",X"28",X"03",X"32",X"B1",X"98",X"3E",X"01",X"32",X"91",X"98",X"32",X"A1",X"98",X"CD",X"11", + X"1E",X"18",X"03",X"CD",X"F8",X"1D",X"3A",X"05",X"99",X"CD",X"40",X"1E",X"32",X"65",X"98",X"18", + X"7E",X"3A",X"06",X"99",X"A7",X"28",X"3B",X"DD",X"21",X"C8",X"98",X"CD",X"E4",X"1D",X"20",X"32", + X"21",X"06",X"99",X"35",X"20",X"1E",X"AF",X"32",X"72",X"98",X"3E",X"40",X"32",X"82",X"98",X"CD", + X"BF",X"31",X"28",X"03",X"32",X"B2",X"98",X"3E",X"01",X"32",X"92",X"98",X"32",X"A2",X"98",X"CD", + X"11",X"1E",X"18",X"03",X"CD",X"F8",X"1D",X"3A",X"06",X"99",X"CD",X"40",X"1E",X"32",X"68",X"98", + X"18",X"3D",X"3A",X"07",X"99",X"A7",X"C8",X"DD",X"21",X"CC",X"98",X"CD",X"E4",X"1D",X"C0",X"21", + X"07",X"99",X"35",X"20",X"1E",X"AF",X"32",X"73",X"98",X"3E",X"40",X"32",X"83",X"98",X"CD",X"BF", + X"31",X"28",X"03",X"32",X"B3",X"98",X"3E",X"01",X"32",X"93",X"98",X"32",X"A3",X"98",X"CD",X"11", + X"1E",X"18",X"03",X"CD",X"F8",X"1D",X"3A",X"07",X"99",X"CD",X"40",X"1E",X"32",X"6B",X"98",X"AF", + X"FD",X"77",X"00",X"C9",X"DD",X"6E",X"00",X"DD",X"66",X"01",X"AF",X"ED",X"52",X"C8",X"DD",X"6E", + X"02",X"DD",X"66",X"03",X"AF",X"ED",X"52",X"C9",X"FD",X"E5",X"21",X"60",X"00",X"3E",X"FF",X"32", + X"47",X"98",X"22",X"15",X"99",X"22",X"1A",X"99",X"CD",X"FE",X"30",X"CD",X"EB",X"33",X"FD",X"E1", + X"C9",X"FD",X"E5",X"21",X"00",X"05",X"3E",X"FF",X"32",X"47",X"98",X"22",X"15",X"99",X"22",X"1A", + X"99",X"CD",X"FE",X"30",X"CD",X"EF",X"33",X"FD",X"E1",X"C9",X"00",X"2A",X"28",X"26",X"24",X"22", + X"20",X"1E",X"1C",X"1A",X"16",X"00",X"2C",X"2A",X"28",X"26",X"24",X"22",X"20",X"1E",X"1C",X"1A", + X"21",X"2A",X"1E",X"CF",X"3A",X"01",X"99",X"3D",X"86",X"FE",X"39",X"D8",X"3E",X"38",X"C9",X"21", + X"35",X"1E",X"18",X"EF",X"DD",X"21",X"76",X"98",X"CD",X"71",X"1E",X"DD",X"23",X"CD",X"71",X"1E", + X"DD",X"23",X"CD",X"71",X"1E",X"DD",X"23",X"CD",X"71",X"1E",X"DD",X"23",X"CD",X"71",X"1E",X"DD", + X"23",X"DD",X"7E",X"00",X"A7",X"C8",X"DD",X"7E",X"20",X"DD",X"86",X"40",X"DD",X"77",X"20",X"4F", + X"DD",X"7E",X"10",X"DD",X"86",X"30",X"DD",X"77",X"10",X"2F",X"E6",X"F8",X"26",X"00",X"6F",X"29", + X"29",X"79",X"E6",X"F8",X"0F",X"0F",X"0F",X"CF",X"11",X"00",X"84",X"19",X"7E",X"FE",X"E8",X"30", + X"3C",X"3A",X"04",X"99",X"A7",X"C8",X"EB",X"2A",X"C0",X"98",X"A7",X"ED",X"52",X"20",X"07",X"3A", + X"60",X"98",X"FE",X"A0",X"38",X"0D",X"2A",X"C2",X"98",X"A7",X"ED",X"52",X"C0",X"3A",X"60",X"98", + X"FE",X"80",X"D8",X"CD",X"E7",X"33",X"21",X"04",X"99",X"35",X"20",X"0A",X"3E",X"40",X"32",X"80", + X"98",X"3E",X"01",X"32",X"90",X"98",X"7E",X"CD",X"4F",X"1E",X"32",X"62",X"98",X"AF",X"DD",X"77", + X"00",X"C9",X"FD",X"21",X"74",X"98",X"06",X"08",X"CD",X"2B",X"1F",X"FD",X"23",X"10",X"F9",X"CD", + X"3A",X"25",X"3A",X"D3",X"98",X"A7",X"20",X"03",X"CD",X"47",X"2A",X"CD",X"65",X"2E",X"3A",X"D2", + X"98",X"A7",X"20",X"03",X"CD",X"A8",X"28",X"CD",X"25",X"2E",X"3A",X"D1",X"98",X"A7",X"20",X"03", + X"CD",X"F5",X"26",X"CD",X"E5",X"2D",X"CD",X"DE",X"25",X"CD",X"A0",X"2D",X"CD",X"63",X"1F",X"CD", + X"BA",X"1F",X"CD",X"09",X"20",X"CD",X"58",X"20",X"C3",X"AD",X"23",X"FD",X"7E",X"00",X"A7",X"C8", + X"FD",X"7E",X"20",X"FD",X"86",X"40",X"FD",X"77",X"20",X"4F",X"FD",X"7E",X"10",X"FD",X"86",X"30", + X"FD",X"77",X"10",X"2F",X"E6",X"F8",X"26",X"00",X"6F",X"29",X"29",X"79",X"E6",X"F8",X"0F",X"0F", + X"0F",X"CF",X"11",X"00",X"84",X"19",X"7E",X"FE",X"E8",X"D8",X"FD",X"36",X"00",X"00",X"FD",X"36", + X"10",X"00",X"C9",X"2A",X"02",X"9B",X"11",X"00",X"84",X"A7",X"ED",X"52",X"7D",X"E6",X"1F",X"87", + X"87",X"87",X"C6",X"04",X"32",X"6C",X"98",X"CB",X"3C",X"CB",X"1D",X"CB",X"3C",X"CB",X"1D",X"7D", + X"E6",X"F8",X"C6",X"04",X"2F",X"32",X"61",X"98",X"3A",X"60",X"98",X"07",X"07",X"07",X"E6",X"07", + X"C8",X"47",X"4F",X"3A",X"80",X"9A",X"E6",X"03",X"21",X"B2",X"1F",X"87",X"CF",X"3A",X"61",X"98", + X"86",X"10",X"FD",X"32",X"61",X"98",X"23",X"3A",X"6C",X"98",X"41",X"86",X"10",X"FD",X"32",X"6C", + X"98",X"C9",X"01",X"00",X"00",X"01",X"FF",X"00",X"00",X"FF",X"2A",X"42",X"9B",X"11",X"00",X"84", + X"A7",X"ED",X"52",X"7D",X"E6",X"1F",X"87",X"87",X"87",X"C6",X"04",X"32",X"6D",X"98",X"CB",X"3C", + X"CB",X"1D",X"CB",X"3C",X"CB",X"1D",X"7D",X"E6",X"F8",X"C6",X"04",X"2F",X"32",X"64",X"98",X"3A", + X"63",X"98",X"07",X"07",X"07",X"E6",X"07",X"C8",X"47",X"4F",X"3A",X"A1",X"9A",X"E6",X"03",X"21", + X"B2",X"1F",X"87",X"CF",X"3A",X"64",X"98",X"86",X"10",X"FD",X"32",X"64",X"98",X"23",X"3A",X"6D", + X"98",X"41",X"86",X"10",X"FD",X"32",X"6D",X"98",X"C9",X"2A",X"82",X"9B",X"11",X"00",X"84",X"A7", + X"ED",X"52",X"7D",X"E6",X"1F",X"87",X"87",X"87",X"C6",X"04",X"32",X"6E",X"98",X"CB",X"3C",X"CB", + X"1D",X"CB",X"3C",X"CB",X"1D",X"7D",X"E6",X"F8",X"C6",X"04",X"2F",X"32",X"67",X"98",X"3A",X"66", + X"98",X"07",X"07",X"07",X"E6",X"07",X"C8",X"47",X"4F",X"3A",X"C1",X"9A",X"E6",X"03",X"21",X"B2", + X"1F",X"87",X"CF",X"3A",X"67",X"98",X"86",X"10",X"FD",X"32",X"67",X"98",X"23",X"3A",X"6E",X"98", + X"41",X"86",X"10",X"FD",X"32",X"6E",X"98",X"C9",X"2A",X"C2",X"9B",X"11",X"00",X"84",X"A7",X"ED", + X"52",X"7D",X"E6",X"1F",X"87",X"87",X"87",X"C6",X"04",X"32",X"6F",X"98",X"CB",X"3C",X"CB",X"1D", + X"CB",X"3C",X"CB",X"1D",X"7D",X"E6",X"F8",X"C6",X"04",X"2F",X"32",X"6A",X"98",X"3A",X"69",X"98", + X"07",X"07",X"07",X"E6",X"07",X"C8",X"47",X"4F",X"3A",X"E1",X"9A",X"E6",X"03",X"21",X"B2",X"1F", + X"87",X"CF",X"3A",X"6A",X"98",X"86",X"10",X"FD",X"32",X"6A",X"98",X"23",X"3A",X"6F",X"98",X"41", + X"86",X"10",X"FD",X"32",X"6F",X"98",X"C9",X"3A",X"05",X"99",X"32",X"40",X"98",X"21",X"64",X"98", + X"11",X"6D",X"98",X"DD",X"21",X"81",X"98",X"CD",X"04",X"21",X"3A",X"40",X"98",X"32",X"05",X"99", + X"A7",X"20",X"03",X"32",X"71",X"98",X"3A",X"06",X"99",X"32",X"40",X"98",X"21",X"67",X"98",X"11", + X"6E",X"98",X"DD",X"21",X"82",X"98",X"CD",X"04",X"21",X"3A",X"40",X"98",X"32",X"06",X"99",X"A7", + X"20",X"03",X"32",X"72",X"98",X"3A",X"07",X"99",X"32",X"40",X"98",X"21",X"6A",X"98",X"11",X"6F", + X"98",X"DD",X"21",X"83",X"98",X"CD",X"04",X"21",X"3A",X"40",X"98",X"32",X"07",X"99",X"A7",X"C0", + X"32",X"73",X"98",X"C9",X"3A",X"04",X"99",X"A7",X"C8",X"3A",X"40",X"98",X"A7",X"C8",X"3A",X"61", + X"98",X"96",X"30",X"02",X"ED",X"44",X"FE",X"08",X"D0",X"47",X"EB",X"3A",X"6C",X"98",X"96",X"30", + X"02",X"ED",X"44",X"FE",X"08",X"D0",X"A7",X"28",X"03",X"78",X"A7",X"C0",X"21",X"40",X"98",X"3A", + X"04",X"99",X"BE",X"38",X"24",X"3E",X"40",X"DD",X"77",X"00",X"CD",X"BF",X"31",X"28",X"03",X"DD", + X"77",X"30",X"21",X"40",X"98",X"7E",X"36",X"00",X"DD",X"77",X"10",X"21",X"68",X"21",X"DF",X"EB", + X"22",X"15",X"99",X"22",X"1A",X"99",X"C3",X"FE",X"30",X"3E",X"40",X"32",X"80",X"98",X"21",X"04", + X"99",X"7E",X"36",X"00",X"32",X"90",X"98",X"C9",X"00",X"00",X"80",X"00",X"60",X"01",X"40",X"02", + X"20",X"03",X"00",X"04",X"80",X"04",X"60",X"05",X"40",X"06",X"00",X"08",X"21",X"80",X"98",X"7E", + X"A7",X"C8",X"35",X"28",X"2F",X"7E",X"FE",X"2A",X"28",X"4F",X"FE",X"15",X"28",X"51",X"FE",X"3E", + X"C0",X"CD",X"AD",X"33",X"21",X"02",X"9B",X"3A",X"90",X"98",X"3D",X"28",X"0B",X"47",X"04",X"3E", + X"74",X"5E",X"2C",X"56",X"2C",X"12",X"10",X"F9",X"5E",X"2C",X"56",X"3E",X"20",X"12",X"3E",X"64", + X"32",X"00",X"9C",X"C9",X"3A",X"90",X"98",X"3D",X"28",X"19",X"4F",X"0C",X"11",X"02",X"9B",X"21", + X"50",X"9C",X"7E",X"3C",X"87",X"47",X"7E",X"81",X"77",X"78",X"85",X"6F",X"EB",X"CB",X"21",X"06", + X"00",X"ED",X"B0",X"3E",X"20",X"32",X"00",X"9C",X"C9",X"3E",X"68",X"32",X"00",X"9C",X"C9",X"3E", + X"6C",X"32",X"00",X"9C",X"C9",X"21",X"81",X"98",X"7E",X"A7",X"C8",X"35",X"28",X"35",X"3A",X"A1", + X"98",X"A7",X"20",X"67",X"7E",X"FE",X"2A",X"28",X"56",X"FE",X"15",X"28",X"58",X"FE",X"3E",X"C0", + X"CD",X"C5",X"33",X"21",X"42",X"9B",X"3A",X"91",X"98",X"3D",X"28",X"0B",X"47",X"04",X"3E",X"74", + X"5E",X"2C",X"56",X"2C",X"12",X"10",X"F9",X"5E",X"2C",X"56",X"3E",X"20",X"12",X"3E",X"64",X"32", + X"02",X"9C",X"C9",X"3A",X"91",X"98",X"3D",X"28",X"19",X"4F",X"0C",X"11",X"42",X"9B",X"21",X"50", + X"9C",X"7E",X"3C",X"87",X"47",X"7E",X"81",X"77",X"78",X"85",X"6F",X"EB",X"CB",X"21",X"06",X"00", + X"ED",X"B0",X"3E",X"20",X"32",X"02",X"9C",X"AF",X"32",X"A1",X"98",X"32",X"D1",X"98",X"C9",X"3E", + X"68",X"32",X"02",X"9C",X"C9",X"3E",X"6C",X"32",X"02",X"9C",X"C9",X"7E",X"FE",X"3E",X"C0",X"3A", + X"2F",X"99",X"A7",X"28",X"04",X"3E",X"34",X"18",X"02",X"3E",X"37",X"32",X"02",X"9C",X"21",X"42", + X"9B",X"5E",X"2C",X"56",X"3E",X"20",X"12",X"2C",X"5E",X"2C",X"56",X"12",X"C9",X"21",X"82",X"98", + X"7E",X"A7",X"C8",X"35",X"28",X"35",X"3A",X"A2",X"98",X"A7",X"20",X"67",X"7E",X"FE",X"2A",X"28", + X"56",X"FE",X"15",X"28",X"58",X"FE",X"3E",X"C0",X"CD",X"C5",X"33",X"21",X"82",X"9B",X"3A",X"92", + X"98",X"3D",X"28",X"0B",X"47",X"04",X"3E",X"74",X"5E",X"2C",X"56",X"2C",X"12",X"10",X"F9",X"5E", + X"2C",X"56",X"3E",X"20",X"12",X"3E",X"64",X"32",X"04",X"9C",X"C9",X"3A",X"92",X"98",X"3D",X"28", + X"19",X"4F",X"0C",X"11",X"82",X"9B",X"21",X"50",X"9C",X"7E",X"3C",X"87",X"47",X"7E",X"81",X"77", + X"78",X"85",X"6F",X"EB",X"CB",X"21",X"06",X"00",X"ED",X"B0",X"3E",X"20",X"32",X"04",X"9C",X"AF", + X"32",X"A2",X"98",X"32",X"D2",X"98",X"C9",X"3E",X"68",X"32",X"04",X"9C",X"C9",X"3E",X"6C",X"32", + X"04",X"9C",X"C9",X"7E",X"FE",X"3E",X"C0",X"3A",X"2F",X"99",X"A7",X"28",X"04",X"3E",X"34",X"18", + X"02",X"3E",X"37",X"32",X"04",X"9C",X"21",X"82",X"9B",X"5E",X"2C",X"56",X"3E",X"20",X"12",X"2C", + X"5E",X"2C",X"56",X"12",X"C9",X"21",X"83",X"98",X"7E",X"A7",X"C8",X"35",X"28",X"35",X"3A",X"A3", + X"98",X"A7",X"20",X"67",X"7E",X"FE",X"2A",X"28",X"56",X"FE",X"15",X"28",X"58",X"FE",X"3E",X"C0", + X"CD",X"C5",X"33",X"21",X"C2",X"9B",X"3A",X"93",X"98",X"3D",X"28",X"0B",X"47",X"04",X"3E",X"74", + X"5E",X"2C",X"56",X"2C",X"12",X"10",X"F9",X"5E",X"2C",X"56",X"3E",X"20",X"12",X"3E",X"64",X"32", + X"06",X"9C",X"C9",X"3A",X"93",X"98",X"3D",X"28",X"19",X"4F",X"0C",X"11",X"C2",X"9B",X"21",X"50", + X"9C",X"7E",X"3C",X"87",X"47",X"7E",X"81",X"77",X"78",X"85",X"6F",X"EB",X"CB",X"21",X"06",X"00", + X"ED",X"B0",X"3E",X"20",X"32",X"06",X"9C",X"AF",X"32",X"A3",X"98",X"32",X"D3",X"98",X"C9",X"3E", + X"68",X"32",X"06",X"9C",X"C9",X"3E",X"6C",X"32",X"06",X"9C",X"C9",X"7E",X"FE",X"3E",X"C0",X"3A", + X"2F",X"99",X"A7",X"28",X"04",X"3E",X"34",X"18",X"02",X"3E",X"37",X"32",X"06",X"9C",X"21",X"C2", + X"9B",X"5E",X"2C",X"56",X"3E",X"20",X"12",X"2C",X"5E",X"2C",X"56",X"12",X"C9",X"3A",X"2F",X"99", + X"A7",X"C2",X"65",X"24",X"3A",X"04",X"99",X"A7",X"28",X"0E",X"3A",X"80",X"9A",X"C6",X"02",X"E6", + X"03",X"87",X"87",X"C6",X"10",X"32",X"00",X"9C",X"3A",X"05",X"99",X"A7",X"28",X"0E",X"3A",X"A1", + X"9A",X"C6",X"02",X"E6",X"03",X"87",X"87",X"C6",X"24",X"32",X"02",X"9C",X"3A",X"06",X"99",X"A7", + X"28",X"0E",X"3A",X"C1",X"9A",X"C6",X"02",X"E6",X"03",X"87",X"87",X"C6",X"24",X"32",X"04",X"9C", + X"3A",X"07",X"99",X"A7",X"28",X"0E",X"3A",X"E1",X"9A",X"C6",X"02",X"E6",X"03",X"87",X"87",X"C6", + X"24",X"32",X"06",X"9C",X"3A",X"61",X"98",X"C6",X"FA",X"32",X"10",X"9C",X"3A",X"6C",X"98",X"C6", + X"F8",X"32",X"01",X"9C",X"3A",X"11",X"9C",X"E6",X"7F",X"32",X"11",X"9C",X"3A",X"64",X"98",X"C6", + X"FA",X"32",X"12",X"9C",X"3A",X"6D",X"98",X"C6",X"F8",X"32",X"03",X"9C",X"3A",X"13",X"9C",X"E6", + X"7F",X"32",X"13",X"9C",X"3A",X"67",X"98",X"C6",X"FA",X"32",X"14",X"9C",X"3A",X"6E",X"98",X"C6", + X"F8",X"32",X"05",X"9C",X"3A",X"15",X"9C",X"E6",X"7F",X"32",X"15",X"9C",X"3A",X"6A",X"98",X"C6", + X"FA",X"32",X"16",X"9C",X"3A",X"6F",X"98",X"C6",X"F8",X"32",X"07",X"9C",X"3A",X"17",X"9C",X"E6", + X"7F",X"32",X"17",X"9C",X"C9",X"3A",X"04",X"99",X"A7",X"28",X"0C",X"3A",X"80",X"9A",X"E6",X"03", + X"87",X"87",X"C6",X"10",X"32",X"00",X"9C",X"3A",X"05",X"99",X"A7",X"28",X"0C",X"3A",X"A1",X"9A", + X"E6",X"03",X"87",X"87",X"C6",X"24",X"32",X"02",X"9C",X"3A",X"06",X"99",X"A7",X"28",X"0C",X"3A", + X"C1",X"9A",X"E6",X"03",X"87",X"87",X"C6",X"24",X"32",X"04",X"9C",X"3A",X"07",X"99",X"A7",X"28", + X"0C",X"3A",X"E1",X"9A",X"E6",X"03",X"87",X"87",X"C6",X"24",X"32",X"06",X"9C",X"3A",X"61",X"98", + X"2F",X"C6",X"F9",X"32",X"10",X"9C",X"3A",X"6C",X"98",X"2F",X"C6",X"19",X"32",X"01",X"9C",X"3A", + X"11",X"9C",X"38",X"07",X"E6",X"7F",X"32",X"11",X"9C",X"18",X"05",X"F6",X"80",X"32",X"11",X"9C", + X"3A",X"64",X"98",X"2F",X"C6",X"F9",X"32",X"12",X"9C",X"3A",X"6D",X"98",X"2F",X"C6",X"19",X"32", + X"03",X"9C",X"3A",X"13",X"9C",X"38",X"07",X"E6",X"7F",X"32",X"13",X"9C",X"18",X"05",X"F6",X"80", + X"32",X"13",X"9C",X"3A",X"67",X"98",X"2F",X"C6",X"F9",X"32",X"14",X"9C",X"3A",X"6E",X"98",X"2F", + X"C6",X"19",X"32",X"05",X"9C",X"3A",X"15",X"9C",X"38",X"07",X"E6",X"7F",X"32",X"15",X"9C",X"18", + X"05",X"F6",X"80",X"32",X"15",X"9C",X"3A",X"6A",X"98",X"2F",X"C6",X"F9",X"32",X"16",X"9C",X"3A", + X"6F",X"98",X"2F",X"C6",X"19",X"32",X"07",X"9C",X"3A",X"17",X"9C",X"38",X"07",X"E6",X"7F",X"32", + X"17",X"9C",X"18",X"05",X"F6",X"80",X"32",X"17",X"9C",X"C9",X"DD",X"21",X"74",X"98",X"FD",X"21", + X"24",X"9C",X"06",X"06",X"CD",X"5C",X"25",X"FD",X"23",X"DD",X"23",X"CD",X"5C",X"25",X"FD",X"23", + X"DD",X"23",X"CD",X"9D",X"25",X"FD",X"23",X"DD",X"23",X"10",X"F7",X"C9",X"DD",X"7E",X"00",X"A7", + X"28",X"37",X"3A",X"2F",X"99",X"A7",X"28",X"19",X"DD",X"7E",X"10",X"2F",X"C6",X"FF",X"FD",X"77", + X"10",X"DD",X"7E",X"20",X"2F",X"C6",X"1F",X"FD",X"77",X"00",X"38",X"18",X"FD",X"36",X"20",X"0C", + X"C9",X"DD",X"7E",X"10",X"FD",X"77",X"10",X"DD",X"7E",X"20",X"C6",X"FE",X"FD",X"77",X"00",X"FD", + X"36",X"20",X"0C",X"C9",X"FD",X"36",X"20",X"04",X"C9",X"FD",X"77",X"10",X"C9",X"DD",X"7E",X"00", + X"A7",X"28",X"37",X"3A",X"2F",X"99",X"A7",X"28",X"19",X"DD",X"7E",X"10",X"2F",X"C6",X"FF",X"FD", + X"77",X"10",X"DD",X"7E",X"20",X"2F",X"C6",X"1F",X"FD",X"77",X"00",X"38",X"18",X"FD",X"36",X"20", + X"08",X"C9",X"DD",X"7E",X"10",X"FD",X"77",X"10",X"DD",X"7E",X"20",X"C6",X"FE",X"FD",X"77",X"00", + X"FD",X"36",X"20",X"08",X"C9",X"FD",X"36",X"20",X"00",X"C9",X"FD",X"77",X"10",X"C9",X"3A",X"04", + X"99",X"A7",X"C8",X"CD",X"06",X"2D",X"3A",X"17",X"98",X"A7",X"C2",X"6D",X"26",X"3A",X"62",X"98", + X"21",X"60",X"98",X"86",X"77",X"D0",X"21",X"8A",X"9A",X"11",X"8B",X"9A",X"01",X"0B",X"00",X"ED", + X"B8",X"21",X"15",X"9B",X"11",X"17",X"9B",X"01",X"16",X"00",X"ED",X"B8",X"3A",X"16",X"98",X"4F", + X"21",X"80",X"9A",X"96",X"E6",X"03",X"28",X"06",X"FE",X"02",X"28",X"73",X"18",X"29",X"79",X"21", + X"DD",X"26",X"DF",X"2A",X"00",X"9B",X"19",X"7E",X"FE",X"EC",X"30",X"10",X"FE",X"E8",X"30",X"7A", + X"22",X"00",X"9B",X"3A",X"80",X"9A",X"E6",X"03",X"32",X"80",X"9A",X"C9",X"3E",X"00",X"32",X"60", + X"98",X"3E",X"FF",X"32",X"17",X"98",X"C9",X"79",X"21",X"DD",X"26",X"DF",X"2A",X"00",X"9B",X"19", + X"7E",X"FE",X"E8",X"3A",X"80",X"9A",X"30",X"C7",X"22",X"00",X"9B",X"3A",X"80",X"9A",X"E6",X"03", + X"87",X"87",X"81",X"C6",X"04",X"32",X"81",X"9A",X"79",X"32",X"80",X"9A",X"C9",X"3A",X"16",X"98", + X"4F",X"21",X"80",X"9A",X"96",X"E6",X"03",X"C8",X"E6",X"01",X"28",X"13",X"79",X"21",X"DD",X"26", + X"DF",X"2A",X"00",X"9B",X"19",X"7E",X"FE",X"E8",X"D0",X"AF",X"32",X"17",X"98",X"18",X"C9",X"AF", + X"32",X"60",X"98",X"32",X"17",X"98",X"2A",X"04",X"9B",X"22",X"00",X"9B",X"3A",X"80",X"9A",X"C6", + X"02",X"E6",X"03",X"32",X"80",X"9A",X"32",X"81",X"9A",X"C9",X"D6",X"EC",X"E6",X"03",X"4F",X"3A", + X"80",X"9A",X"E6",X"03",X"87",X"87",X"81",X"21",X"E5",X"26",X"CF",X"7E",X"4F",X"21",X"DD",X"26", + X"DF",X"2A",X"00",X"9B",X"19",X"7E",X"FE",X"E8",X"30",X"02",X"18",X"8C",X"79",X"C6",X"02",X"E6", + X"03",X"4F",X"21",X"DD",X"26",X"DF",X"2A",X"00",X"9B",X"19",X"C3",X"58",X"26",X"E0",X"FF",X"01", + X"00",X"20",X"00",X"FF",X"FF",X"01",X"01",X"03",X"03",X"00",X"02",X"00",X"02",X"01",X"01",X"03", + X"03",X"00",X"02",X"00",X"02",X"3A",X"05",X"99",X"A7",X"C8",X"3A",X"D1",X"98",X"A7",X"C2",X"77", + X"28",X"3A",X"65",X"98",X"21",X"63",X"98",X"86",X"77",X"D0",X"21",X"AA",X"9A",X"11",X"AB",X"9A", + X"01",X"0B",X"00",X"ED",X"B8",X"21",X"55",X"9B",X"11",X"57",X"9B",X"01",X"16",X"00",X"ED",X"B8", + X"3A",X"C0",X"98",X"E6",X"1F",X"47",X"3A",X"40",X"9B",X"E6",X"1F",X"90",X"32",X"41",X"98",X"3E", + X"03",X"30",X"02",X"3E",X"01",X"32",X"42",X"98",X"2A",X"C0",X"98",X"29",X"29",X"29",X"7C",X"E6", + X"1F",X"47",X"2A",X"40",X"9B",X"29",X"29",X"29",X"7C",X"E6",X"1F",X"90",X"32",X"43",X"98",X"3E", + X"00",X"30",X"02",X"3E",X"02",X"32",X"44",X"98",X"3A",X"A0",X"9A",X"E6",X"03",X"4F",X"21",X"DD", + X"26",X"DF",X"2A",X"40",X"9B",X"19",X"22",X"50",X"98",X"7E",X"FE",X"E8",X"30",X"3C",X"CD",X"A5", + X"2F",X"E6",X"07",X"28",X"4A",X"21",X"08",X"99",X"BE",X"D2",X"13",X"28",X"3A",X"41",X"98",X"A7", + X"20",X"05",X"3A",X"44",X"98",X"18",X"0A",X"3A",X"43",X"98",X"A7",X"C2",X"42",X"28",X"3A",X"42", + X"98",X"47",X"CD",X"A5",X"2F",X"E6",X"0F",X"FE",X"02",X"38",X"78",X"79",X"90",X"E6",X"03",X"28", + X"7B",X"E6",X"01",X"28",X"1A",X"48",X"79",X"C3",X"4E",X"28",X"CD",X"A5",X"2F",X"E6",X"01",X"28", + X"0E",X"79",X"E6",X"01",X"3A",X"42",X"98",X"28",X"03",X"3A",X"44",X"98",X"4F",X"18",X"09",X"CD", + X"A5",X"2F",X"F6",X"01",X"81",X"E6",X"03",X"4F",X"21",X"DD",X"26",X"DF",X"2A",X"40",X"9B",X"19", + X"7E",X"FE",X"E8",X"30",X"18",X"79",X"32",X"A0",X"9A",X"22",X"40",X"9B",X"21",X"A1",X"9A",X"7E", + X"E6",X"03",X"87",X"87",X"81",X"C6",X"04",X"77",X"AF",X"32",X"71",X"98",X"C9",X"79",X"C6",X"02", + X"E6",X"03",X"4F",X"21",X"DD",X"26",X"DF",X"2A",X"40",X"9B",X"19",X"7E",X"FE",X"E8",X"38",X"D5", + X"3A",X"A0",X"9A",X"E6",X"03",X"4F",X"21",X"DD",X"26",X"DF",X"2A",X"40",X"9B",X"19",X"7E",X"FE", + X"E8",X"30",X"4B",X"CD",X"A5",X"2F",X"E6",X"1F",X"28",X"10",X"18",X"13",X"CD",X"39",X"34",X"CD", + X"A5",X"2F",X"E6",X"07",X"21",X"09",X"99",X"BE",X"30",X"05",X"3E",X"FF",X"32",X"71",X"98",X"2A", + X"50",X"98",X"22",X"40",X"9B",X"C9",X"79",X"E6",X"01",X"78",X"20",X"03",X"3A",X"41",X"98",X"4F", + X"18",X"86",X"79",X"E6",X"01",X"3A",X"42",X"98",X"28",X"03",X"3A",X"44",X"98",X"4F",X"21",X"DD", + X"26",X"DF",X"2A",X"40",X"9B",X"19",X"7E",X"FE",X"E8",X"DA",X"D5",X"27",X"18",X"B5",X"3E",X"80", + X"32",X"63",X"98",X"3E",X"F0",X"32",X"D1",X"98",X"21",X"00",X"03",X"22",X"15",X"99",X"22",X"1A", + X"99",X"CD",X"F3",X"33",X"C3",X"FE",X"30",X"21",X"D1",X"98",X"35",X"20",X"16",X"21",X"05",X"99", + X"7E",X"32",X"91",X"98",X"36",X"00",X"3E",X"40",X"32",X"81",X"98",X"CD",X"BF",X"31",X"C8",X"32", + X"B1",X"98",X"C9",X"7E",X"0F",X"E6",X"07",X"21",X"A0",X"28",X"CF",X"7E",X"32",X"63",X"98",X"C9", + X"C0",X"C0",X"A0",X"A0",X"80",X"80",X"60",X"60",X"3A",X"06",X"99",X"A7",X"C8",X"3A",X"D2",X"98", + X"A7",X"C2",X"1E",X"2A",X"3A",X"68",X"98",X"21",X"66",X"98",X"86",X"77",X"D0",X"21",X"CA",X"9A", + X"11",X"CB",X"9A",X"01",X"0B",X"00",X"ED",X"B8",X"21",X"95",X"9B",X"11",X"97",X"9B",X"01",X"16", + X"00",X"ED",X"B8",X"3A",X"C0",X"98",X"E6",X"1F",X"47",X"3A",X"80",X"9B",X"E6",X"1F",X"90",X"32", + X"41",X"98",X"3E",X"03",X"30",X"02",X"3E",X"01",X"32",X"42",X"98",X"2A",X"C0",X"98",X"29",X"29", + X"29",X"7C",X"E6",X"1F",X"47",X"2A",X"80",X"9B",X"29",X"29",X"29",X"7C",X"E6",X"1F",X"90",X"32", + X"43",X"98",X"3E",X"00",X"30",X"02",X"3E",X"02",X"32",X"44",X"98",X"3A",X"C0",X"9A",X"E6",X"03", + X"4F",X"21",X"DD",X"26",X"DF",X"2A",X"80",X"9B",X"19",X"22",X"50",X"98",X"7E",X"FE",X"E8",X"30", + X"3C",X"CD",X"A5",X"2F",X"E6",X"07",X"28",X"4A",X"21",X"08",X"99",X"BE",X"D2",X"C6",X"29",X"3A", + X"41",X"98",X"A7",X"20",X"05",X"3A",X"44",X"98",X"18",X"0A",X"3A",X"43",X"98",X"A7",X"C2",X"F5", + X"29",X"3A",X"42",X"98",X"47",X"CD",X"A5",X"2F",X"E6",X"0F",X"FE",X"08",X"38",X"78",X"79",X"90", + X"E6",X"03",X"28",X"7B",X"E6",X"01",X"28",X"1A",X"48",X"79",X"C3",X"01",X"2A",X"CD",X"A5",X"2F", + X"E6",X"01",X"28",X"0E",X"79",X"E6",X"01",X"3A",X"42",X"98",X"28",X"03",X"3A",X"44",X"98",X"4F", + X"18",X"09",X"CD",X"A5",X"2F",X"F6",X"01",X"81",X"E6",X"03",X"4F",X"21",X"DD",X"26",X"DF",X"2A", + X"80",X"9B",X"19",X"7E",X"FE",X"E8",X"30",X"18",X"79",X"32",X"C0",X"9A",X"22",X"80",X"9B",X"21", + X"C1",X"9A",X"7E",X"E6",X"03",X"87",X"87",X"81",X"C6",X"04",X"77",X"AF",X"32",X"72",X"98",X"C9", + X"79",X"C6",X"02",X"E6",X"03",X"4F",X"21",X"DD",X"26",X"DF",X"2A",X"80",X"9B",X"19",X"7E",X"FE", + X"E8",X"38",X"D5",X"3A",X"C0",X"9A",X"E6",X"03",X"4F",X"21",X"DD",X"26",X"DF",X"2A",X"80",X"9B", + X"19",X"7E",X"FE",X"E8",X"30",X"4B",X"CD",X"A5",X"2F",X"E6",X"1F",X"28",X"10",X"18",X"13",X"CD", + X"39",X"34",X"CD",X"A5",X"2F",X"E6",X"07",X"21",X"09",X"99",X"BE",X"30",X"05",X"3E",X"FF",X"32", + X"72",X"98",X"2A",X"50",X"98",X"22",X"80",X"9B",X"C9",X"79",X"E6",X"01",X"78",X"20",X"03",X"3A", + X"41",X"98",X"4F",X"18",X"86",X"79",X"E6",X"01",X"3A",X"42",X"98",X"28",X"03",X"3A",X"44",X"98", + X"4F",X"21",X"DD",X"26",X"DF",X"2A",X"80",X"9B",X"19",X"7E",X"FE",X"E8",X"DA",X"88",X"29",X"18", + X"B5",X"3E",X"80",X"32",X"66",X"98",X"3E",X"F0",X"32",X"D2",X"98",X"C3",X"68",X"28",X"21",X"D2", + X"98",X"35",X"20",X"16",X"21",X"06",X"99",X"7E",X"32",X"92",X"98",X"36",X"00",X"3E",X"40",X"32", + X"82",X"98",X"CD",X"BF",X"31",X"C8",X"32",X"B2",X"98",X"C9",X"7E",X"0F",X"E6",X"07",X"21",X"A0", + X"28",X"CF",X"7E",X"32",X"66",X"98",X"C9",X"3A",X"07",X"99",X"A7",X"C8",X"3A",X"D3",X"98",X"A7", + X"C2",X"BD",X"2B",X"3A",X"6B",X"98",X"21",X"69",X"98",X"86",X"77",X"D0",X"21",X"EA",X"9A",X"11", + X"EB",X"9A",X"01",X"0B",X"00",X"ED",X"B8",X"21",X"D5",X"9B",X"11",X"D7",X"9B",X"01",X"16",X"00", + X"ED",X"B8",X"3A",X"C0",X"98",X"E6",X"1F",X"47",X"3A",X"C0",X"9B",X"E6",X"1F",X"90",X"32",X"41", + X"98",X"3E",X"03",X"30",X"02",X"3E",X"01",X"32",X"42",X"98",X"2A",X"C0",X"98",X"29",X"29",X"29", + X"7C",X"E6",X"1F",X"47",X"2A",X"C0",X"9B",X"29",X"29",X"29",X"7C",X"E6",X"1F",X"90",X"32",X"43", + X"98",X"3E",X"00",X"30",X"02",X"3E",X"02",X"32",X"44",X"98",X"3A",X"E0",X"9A",X"E6",X"03",X"4F", + X"21",X"DD",X"26",X"DF",X"2A",X"C0",X"9B",X"19",X"22",X"50",X"98",X"7E",X"FE",X"E8",X"30",X"3C", + X"CD",X"A5",X"2F",X"E6",X"07",X"28",X"4A",X"21",X"08",X"99",X"BE",X"D2",X"65",X"2B",X"3A",X"41", + X"98",X"A7",X"20",X"05",X"3A",X"44",X"98",X"18",X"0A",X"3A",X"43",X"98",X"A7",X"C2",X"94",X"2B", + X"3A",X"42",X"98",X"47",X"CD",X"A5",X"2F",X"E6",X"0F",X"FE",X"0C",X"38",X"78",X"79",X"90",X"E6", + X"03",X"28",X"7B",X"E6",X"01",X"28",X"1A",X"48",X"79",X"C3",X"A0",X"2B",X"CD",X"A5",X"2F",X"E6", + X"01",X"28",X"0E",X"79",X"E6",X"01",X"3A",X"42",X"98",X"28",X"03",X"3A",X"44",X"98",X"4F",X"18", + X"09",X"CD",X"A5",X"2F",X"F6",X"01",X"81",X"E6",X"03",X"4F",X"21",X"DD",X"26",X"DF",X"2A",X"C0", + X"9B",X"19",X"7E",X"FE",X"E8",X"30",X"18",X"79",X"32",X"E0",X"9A",X"22",X"C0",X"9B",X"21",X"E1", + X"9A",X"7E",X"E6",X"03",X"87",X"87",X"81",X"C6",X"04",X"77",X"AF",X"32",X"73",X"98",X"C9",X"79", + X"C6",X"02",X"E6",X"03",X"4F",X"21",X"DD",X"26",X"DF",X"2A",X"C0",X"9B",X"19",X"7E",X"FE",X"E8", + X"38",X"D5",X"3A",X"E0",X"9A",X"E6",X"03",X"4F",X"21",X"DD",X"26",X"DF",X"2A",X"C0",X"9B",X"19", + X"7E",X"FE",X"E8",X"30",X"4B",X"CD",X"A5",X"2F",X"E6",X"1F",X"28",X"10",X"18",X"13",X"CD",X"39", + X"34",X"CD",X"A5",X"2F",X"E6",X"07",X"21",X"09",X"99",X"BE",X"30",X"05",X"3E",X"FF",X"32",X"73", + X"98",X"2A",X"50",X"98",X"22",X"C0",X"9B",X"C9",X"79",X"E6",X"01",X"78",X"20",X"03",X"3A",X"41", + X"98",X"4F",X"18",X"86",X"79",X"E6",X"01",X"3A",X"42",X"98",X"28",X"03",X"3A",X"44",X"98",X"4F", + X"21",X"DD",X"26",X"DF",X"2A",X"C0",X"9B",X"19",X"7E",X"FE",X"E8",X"DA",X"27",X"2B",X"18",X"B5", + X"3E",X"80",X"32",X"69",X"98",X"3E",X"F0",X"32",X"D3",X"98",X"C3",X"68",X"28",X"21",X"D3",X"98", + X"35",X"20",X"16",X"21",X"07",X"99",X"7E",X"32",X"93",X"98",X"36",X"00",X"3E",X"40",X"32",X"83", + X"98",X"CD",X"BF",X"31",X"C8",X"32",X"B3",X"98",X"C9",X"7E",X"0F",X"E6",X"07",X"21",X"A0",X"28", + X"CF",X"7E",X"32",X"69",X"98",X"C9",X"3A",X"04",X"99",X"A7",X"C8",X"3A",X"62",X"98",X"21",X"60", + X"98",X"86",X"77",X"D0",X"21",X"8A",X"9A",X"11",X"8B",X"9A",X"01",X"0B",X"00",X"ED",X"B8",X"21", + X"15",X"9B",X"11",X"17",X"9B",X"01",X"16",X"00",X"ED",X"B8",X"3A",X"80",X"9A",X"E6",X"03",X"4F", + X"21",X"DD",X"26",X"DF",X"2A",X"00",X"9B",X"19",X"22",X"50",X"98",X"7E",X"FE",X"E8",X"30",X"79", + X"CD",X"A5",X"2F",X"E6",X"07",X"FE",X"01",X"38",X"70",X"3A",X"05",X"99",X"A7",X"28",X"05",X"2A", + X"C6",X"98",X"18",X"0E",X"3A",X"06",X"99",X"A7",X"28",X"05",X"2A",X"CA",X"98",X"18",X"03",X"2A", + X"CE",X"98",X"22",X"58",X"98",X"3A",X"58",X"98",X"E6",X"1F",X"47",X"3A",X"00",X"9B",X"E6",X"1F", + X"90",X"28",X"1C",X"06",X"03",X"30",X"02",X"06",X"01",X"2A",X"58",X"98",X"7D",X"E6",X"E0",X"6F", + X"ED",X"5B",X"00",X"9B",X"7B",X"E6",X"E0",X"5F",X"ED",X"52",X"C2",X"EE",X"2C",X"18",X"17",X"2A", + X"58",X"98",X"7D",X"E6",X"E0",X"6F",X"ED",X"5B",X"00",X"9B",X"7B",X"E6",X"E0",X"5F",X"ED",X"52", + X"06",X"02",X"30",X"02",X"06",X"00",X"3E",X"FF",X"32",X"70",X"98",X"79",X"90",X"E6",X"03",X"28", + X"5D",X"E6",X"01",X"28",X"04",X"48",X"79",X"18",X"0D",X"AF",X"32",X"70",X"98",X"CD",X"A5",X"2F", + X"F6",X"01",X"81",X"E6",X"03",X"4F",X"21",X"DD",X"26",X"DF",X"2A",X"00",X"9B",X"19",X"7E",X"FE", + X"E8",X"30",X"14",X"79",X"32",X"80",X"9A",X"22",X"00",X"9B",X"21",X"81",X"9A",X"7E",X"E6",X"03", + X"87",X"87",X"81",X"C6",X"04",X"77",X"C9",X"79",X"C6",X"02",X"E6",X"03",X"4F",X"21",X"DD",X"26", + X"DF",X"2A",X"00",X"9B",X"19",X"7E",X"FE",X"E8",X"38",X"D9",X"3A",X"80",X"9A",X"E6",X"03",X"4F", + X"21",X"DD",X"26",X"DF",X"2A",X"00",X"9B",X"19",X"7E",X"FE",X"E8",X"D2",X"8F",X"26",X"2A",X"50", + X"98",X"22",X"00",X"9B",X"C9",X"CD",X"A5",X"2F",X"E6",X"0F",X"20",X"08",X"CD",X"A5",X"2F",X"E6", + X"03",X"3C",X"4F",X"C9",X"AF",X"C9",X"3A",X"2F",X"99",X"A7",X"28",X"29",X"0E",X"04",X"3A",X"05", + X"98",X"CB",X"7F",X"20",X"17",X"0D",X"3A",X"03",X"98",X"CB",X"6F",X"20",X"0F",X"0D",X"3A",X"04", + X"98",X"CB",X"47",X"20",X"07",X"0D",X"3A",X"03",X"98",X"CB",X"67",X"C8",X"79",X"3D",X"32",X"16", + X"98",X"3E",X"FF",X"A7",X"C9",X"0E",X"04",X"3A",X"04",X"98",X"CB",X"4F",X"20",X"17",X"0D",X"3A", + X"04",X"98",X"CB",X"67",X"20",X"0F",X"0D",X"3A",X"03",X"98",X"CB",X"47",X"20",X"07",X"0D",X"3A", + X"04",X"98",X"CB",X"6F",X"C8",X"79",X"3D",X"32",X"16",X"98",X"3E",X"FF",X"A7",X"C9",X"21",X"50", + X"9C",X"7E",X"A7",X"C8",X"47",X"36",X"00",X"3E",X"20",X"2C",X"2C",X"5E",X"2C",X"56",X"12",X"10", + X"F9",X"C9",X"21",X"00",X"9D",X"34",X"08",X"7E",X"87",X"87",X"6F",X"73",X"2C",X"72",X"2C",X"08", + X"77",X"2C",X"EB",X"C9",X"3A",X"00",X"9D",X"A7",X"C8",X"47",X"21",X"04",X"9D",X"AF",X"32",X"00", + X"9D",X"5E",X"2C",X"56",X"2C",X"7E",X"12",X"2C",X"CB",X"DA",X"7E",X"12",X"2C",X"10",X"F2",X"C9", + X"3A",X"04",X"99",X"A7",X"C8",X"32",X"40",X"98",X"21",X"99",X"2F",X"11",X"48",X"98",X"01",X"03", + X"00",X"ED",X"B0",X"21",X"05",X"9B",X"87",X"CF",X"E5",X"DD",X"E1",X"3A",X"40",X"98",X"21",X"80", + X"9A",X"CF",X"E5",X"FD",X"E1",X"3A",X"60",X"98",X"07",X"07",X"07",X"E6",X"07",X"32",X"41",X"98", + X"21",X"11",X"9C",X"22",X"54",X"98",X"CD",X"A5",X"2E",X"21",X"56",X"98",X"11",X"C0",X"98",X"01", + X"04",X"00",X"ED",X"B0",X"C9",X"3A",X"05",X"99",X"A7",X"C8",X"32",X"40",X"98",X"CD",X"7B",X"2F", + X"3A",X"40",X"98",X"21",X"45",X"9B",X"87",X"CF",X"E5",X"DD",X"E1",X"3A",X"40",X"98",X"21",X"A0", + X"9A",X"CF",X"E5",X"FD",X"E1",X"3A",X"63",X"98",X"07",X"07",X"07",X"E6",X"07",X"32",X"41",X"98", + X"21",X"13",X"9C",X"22",X"54",X"98",X"CD",X"A5",X"2E",X"21",X"56",X"98",X"11",X"C4",X"98",X"01", + X"04",X"00",X"ED",X"B0",X"C9",X"3A",X"06",X"99",X"A7",X"C8",X"32",X"40",X"98",X"CD",X"7B",X"2F", + X"3A",X"40",X"98",X"21",X"85",X"9B",X"87",X"CF",X"E5",X"DD",X"E1",X"3A",X"40",X"98",X"21",X"C0", + X"9A",X"CF",X"E5",X"FD",X"E1",X"3A",X"66",X"98",X"07",X"07",X"07",X"E6",X"07",X"32",X"41",X"98", + X"21",X"15",X"9C",X"22",X"54",X"98",X"CD",X"A5",X"2E",X"21",X"56",X"98",X"11",X"C8",X"98",X"01", + X"04",X"00",X"ED",X"B0",X"C9",X"3A",X"07",X"99",X"A7",X"C8",X"32",X"40",X"98",X"CD",X"7B",X"2F", + X"3A",X"40",X"98",X"21",X"C5",X"9B",X"87",X"CF",X"E5",X"DD",X"E1",X"3A",X"40",X"98",X"21",X"E0", + X"9A",X"CF",X"E5",X"FD",X"E1",X"3A",X"69",X"98",X"07",X"07",X"07",X"E6",X"07",X"32",X"41",X"98", + X"21",X"17",X"9C",X"22",X"54",X"98",X"CD",X"A5",X"2E",X"21",X"56",X"98",X"11",X"CC",X"98",X"01", + X"04",X"00",X"ED",X"B0",X"C9",X"3A",X"48",X"98",X"2A",X"54",X"98",X"CB",X"7E",X"77",X"28",X"02", + X"CB",X"FE",X"DD",X"56",X"00",X"DD",X"2B",X"DD",X"5E",X"00",X"DD",X"2B",X"21",X"50",X"9C",X"34", + X"7E",X"87",X"85",X"6F",X"73",X"2C",X"72",X"DD",X"56",X"00",X"DD",X"2B",X"DD",X"5E",X"00",X"DD", + X"2B",X"21",X"50",X"9C",X"34",X"7E",X"87",X"85",X"6F",X"73",X"2C",X"72",X"21",X"40",X"98",X"35", + X"20",X"13",X"DD",X"66",X"00",X"DD",X"6E",X"FF",X"22",X"56",X"98",X"DD",X"66",X"FE",X"DD",X"6E", + X"FD",X"22",X"58",X"98",X"C9",X"DD",X"56",X"00",X"DD",X"2B",X"DD",X"5E",X"00",X"DD",X"2B",X"FD", + X"7E",X"00",X"FD",X"2B",X"ED",X"53",X"56",X"98",X"21",X"28",X"3F",X"85",X"6F",X"46",X"25",X"3A", + X"41",X"98",X"86",X"CD",X"72",X"2D",X"3A",X"4A",X"98",X"B0",X"12",X"DD",X"66",X"00",X"DD",X"6E", + X"FF",X"22",X"58",X"98",X"DD",X"56",X"00",X"DD",X"2B",X"DD",X"5E",X"00",X"DD",X"2B",X"FD",X"7E", + X"00",X"FD",X"2B",X"21",X"14",X"3F",X"85",X"6F",X"46",X"25",X"3A",X"41",X"98",X"86",X"CD",X"72", + X"2D",X"3A",X"4A",X"98",X"B0",X"12",X"3A",X"40",X"98",X"3D",X"28",X"29",X"47",X"C5",X"DD",X"56", + X"00",X"DD",X"2B",X"DD",X"5E",X"00",X"DD",X"2B",X"FD",X"7E",X"00",X"FD",X"2B",X"21",X"00",X"3F", + X"85",X"6F",X"46",X"25",X"3A",X"41",X"98",X"86",X"CD",X"72",X"2D",X"3A",X"4A",X"98",X"B0",X"12", + X"78",X"C1",X"10",X"D9",X"47",X"3A",X"49",X"98",X"B0",X"12",X"C9",X"21",X"04",X"99",X"BE",X"28", + X"07",X"30",X"0A",X"21",X"9C",X"2F",X"18",X"08",X"21",X"9F",X"2F",X"18",X"03",X"21",X"A2",X"2F", + X"11",X"48",X"98",X"01",X"03",X"00",X"ED",X"B0",X"C9",X"2B",X"06",X"30",X"0F",X"02",X"10",X"16", + X"03",X"18",X"0A",X"01",X"08",X"D9",X"21",X"0F",X"9E",X"11",X"10",X"9E",X"01",X"10",X"00",X"ED", + X"B8",X"21",X"10",X"9E",X"3A",X"07",X"9E",X"AE",X"32",X"00",X"9E",X"21",X"02",X"98",X"86",X"D9", + X"C9",X"D9",X"3A",X"03",X"98",X"0F",X"0F",X"0F",X"21",X"22",X"99",X"CB",X"16",X"7E",X"E6",X"07", + X"FE",X"01",X"C0",X"CD",X"A1",X"33",X"3E",X"01",X"C3",X"3E",X"30",X"3A",X"03",X"98",X"21",X"27", + X"99",X"07",X"07",X"CB",X"16",X"7E",X"E6",X"07",X"FE",X"01",X"C0",X"EB",X"CD",X"A1",X"33",X"21", + X"30",X"99",X"34",X"EB",X"23",X"7E",X"C6",X"10",X"77",X"47",X"23",X"7E",X"90",X"D0",X"7E",X"4F", + X"E6",X"F0",X"C6",X"10",X"2B",X"ED",X"44",X"86",X"77",X"79",X"E6",X"0F",X"18",X"30",X"3A",X"03", + X"98",X"21",X"24",X"99",X"07",X"CB",X"16",X"7E",X"E6",X"07",X"FE",X"01",X"C0",X"EB",X"CD",X"A1", + X"33",X"21",X"2A",X"99",X"34",X"EB",X"23",X"7E",X"C6",X"10",X"77",X"47",X"23",X"7E",X"90",X"D0", + X"7E",X"4F",X"E6",X"F0",X"C6",X"10",X"2B",X"ED",X"44",X"86",X"77",X"79",X"E6",X"0F",X"21",X"23", + X"99",X"86",X"27",X"77",X"30",X"02",X"36",X"99",X"11",X"06",X"83",X"21",X"16",X"01",X"FF",X"21", + X"BF",X"FF",X"19",X"EB",X"3A",X"23",X"99",X"CD",X"B1",X"30",X"21",X"06",X"8B",X"11",X"20",X"00", + X"3E",X"A3",X"06",X"06",X"77",X"19",X"10",X"FC",X"C9",X"3A",X"2A",X"99",X"A7",X"C8",X"21",X"2B", + X"99",X"7E",X"A7",X"20",X"07",X"36",X"30",X"3C",X"32",X"84",X"A1",X"C9",X"35",X"28",X"09",X"7E", + X"FE",X"18",X"C0",X"AF",X"32",X"84",X"A1",X"C9",X"21",X"2A",X"99",X"35",X"C9",X"3A",X"30",X"99", + X"A7",X"C8",X"21",X"31",X"99",X"7E",X"A7",X"20",X"07",X"36",X"30",X"3C",X"32",X"86",X"A1",X"C9", + X"35",X"28",X"09",X"7E",X"FE",X"18",X"C0",X"AF",X"32",X"86",X"A1",X"C9",X"21",X"30",X"99",X"35", + X"C9",X"FE",X"0A",X"4F",X"38",X"0F",X"4F",X"0F",X"0F",X"0F",X"0F",X"E6",X"0F",X"12",X"D7",X"79", + X"E6",X"0F",X"12",X"D7",X"C9",X"3E",X"20",X"18",X"F4",X"4F",X"0F",X"0F",X"0F",X"0F",X"E6",X"0F", + X"CD",X"D6",X"30",X"79",X"E6",X"0F",X"28",X"04",X"04",X"12",X"D7",X"C9",X"78",X"A7",X"28",X"03", + X"AF",X"18",X"F6",X"3E",X"20",X"18",X"F2",X"7E",X"FE",X"40",X"C8",X"3E",X"20",X"12",X"23",X"D7", + X"18",X"F5",X"CB",X"DA",X"7E",X"FE",X"40",X"C8",X"79",X"12",X"23",X"D7",X"18",X"F6",X"3A",X"20", + X"99",X"FE",X"04",X"D0",X"3A",X"11",X"99",X"A7",X"20",X"79",X"FD",X"21",X"12",X"99",X"11",X"A2", + X"80",X"21",X"78",X"01",X"FD",X"7E",X"03",X"FD",X"86",X"00",X"27",X"FD",X"77",X"00",X"FD",X"7E", + X"04",X"FD",X"8E",X"01",X"27",X"FD",X"77",X"01",X"3E",X"00",X"FD",X"8E",X"02",X"27",X"FD",X"77", + X"02",X"E6",X"0F",X"FE",X"02",X"28",X"0A",X"FE",X"07",X"28",X"06",X"AF",X"32",X"02",X"99",X"18", + X"03",X"CD",X"9A",X"3E",X"DD",X"21",X"1C",X"99",X"FD",X"7E",X"02",X"DD",X"BE",X"02",X"38",X"49", + X"28",X"02",X"18",X"14",X"FD",X"7E",X"01",X"DD",X"BE",X"01",X"38",X"3D",X"28",X"02",X"18",X"08", + X"DD",X"7E",X"00",X"FD",X"BE",X"00",X"30",X"31",X"FD",X"7E",X"00",X"DD",X"77",X"00",X"FD",X"7E", + X"01",X"DD",X"77",X"01",X"FD",X"7E",X"02",X"DD",X"77",X"02",X"D5",X"E5",X"CD",X"84",X"1A",X"E1", + X"D1",X"18",X"16",X"FD",X"21",X"17",X"99",X"11",X"62",X"83",X"21",X"7C",X"01",X"18",X"85",X"FD", + X"21",X"12",X"99",X"11",X"A2",X"80",X"21",X"78",X"01",X"FF",X"21",X"3F",X"FF",X"19",X"EB",X"FD", + X"7E",X"02",X"06",X"00",X"CD",X"C9",X"30",X"FD",X"7E",X"01",X"CD",X"C9",X"30",X"FD",X"7E",X"00", + X"C3",X"B6",X"30",X"FD",X"21",X"17",X"99",X"11",X"62",X"83",X"21",X"7C",X"01",X"18",X"DA",X"21", + X"0F",X"99",X"7E",X"A7",X"C8",X"35",X"7E",X"FE",X"03",X"28",X"03",X"3E",X"40",X"C9",X"3E",X"40", + X"32",X"B0",X"98",X"C9",X"3A",X"01",X"99",X"E6",X"03",X"06",X"9C",X"20",X"02",X"06",X"8E",X"21", + X"B0",X"98",X"11",X"BB",X"8F",X"CD",X"FA",X"31",X"23",X"11",X"5B",X"8C",X"CD",X"FA",X"31",X"23", + X"11",X"41",X"8C",X"CD",X"FA",X"31",X"23",X"11",X"A1",X"8F",X"7E",X"A7",X"C8",X"35",X"28",X"11", + X"CB",X"56",X"3E",X"00",X"28",X"02",X"3E",X"87",X"E6",X"3F",X"4F",X"1A",X"E6",X"C0",X"B1",X"12", + X"C9",X"78",X"18",X"F4",X"3A",X"04",X"99",X"A7",X"C8",X"3A",X"02",X"98",X"E6",X"3F",X"C0",X"CD", + X"A5",X"2F",X"E6",X"07",X"FE",X"03",X"D0",X"FE",X"01",X"38",X"3C",X"28",X"1D",X"3A",X"07",X"99", + X"A7",X"28",X"04",X"32",X"73",X"98",X"C9",X"3A",X"05",X"99",X"A7",X"28",X"04",X"32",X"71",X"98", + X"C9",X"3A",X"06",X"99",X"A7",X"C8",X"32",X"72",X"98",X"C9",X"3A",X"06",X"99",X"A7",X"28",X"04", + X"32",X"72",X"98",X"C9",X"3A",X"07",X"99",X"A7",X"28",X"04",X"32",X"73",X"98",X"C9",X"3A",X"05", + X"99",X"A7",X"C8",X"32",X"71",X"98",X"C9",X"3A",X"05",X"99",X"A7",X"28",X"04",X"32",X"71",X"98", + X"C9",X"3A",X"06",X"99",X"A7",X"28",X"04",X"32",X"72",X"98",X"C9",X"3A",X"07",X"99",X"A7",X"C8", + X"32",X"73",X"98",X"C9",X"3A",X"01",X"99",X"E6",X"03",X"0E",X"1D",X"20",X"02",X"0E",X"0F",X"21", + X"08",X"98",X"7E",X"47",X"34",X"87",X"87",X"87",X"6F",X"26",X"00",X"29",X"29",X"11",X"41",X"84", + X"19",X"78",X"A7",X"CA",X"1D",X"33",X"FE",X"1B",X"CA",X"3E",X"33",X"E5",X"3A",X"01",X"99",X"3D", + X"E6",X"07",X"21",X"43",X"34",X"DF",X"EB",X"11",X"0C",X"00",X"05",X"28",X"03",X"19",X"10",X"FD", + X"EB",X"E1",X"36",X"F8",X"CB",X"DC",X"CB",X"F1",X"71",X"CB",X"9C",X"23",X"36",X"20",X"23",X"06", + X"0C",X"CB",X"F9",X"CB",X"B1",X"1A",X"0F",X"0F",X"0F",X"0F",X"E6",X"0F",X"FE",X"0F",X"28",X"2D", + X"C6",X"E8",X"77",X"CB",X"DC",X"FE",X"F5",X"28",X"2C",X"71",X"CB",X"9C",X"23",X"1A",X"E6",X"0F", + X"FE",X"0F",X"28",X"1D",X"C6",X"E8",X"77",X"CB",X"DC",X"FE",X"F5",X"28",X"1C",X"71",X"CB",X"9C", + X"23",X"13",X"10",X"D1",X"36",X"F8",X"CB",X"DC",X"71",X"3E",X"FF",X"A7",X"C9",X"3E",X"20",X"18", + X"D1",X"3E",X"20",X"18",X"E1",X"36",X"BE",X"18",X"D1",X"36",X"BE",X"18",X"E1",X"CB",X"F1",X"36", + X"FA",X"CB",X"DC",X"71",X"CB",X"9C",X"23",X"CB",X"B1",X"06",X"19",X"36",X"F9",X"CB",X"DC",X"71", + X"CB",X"9C",X"23",X"10",X"F6",X"36",X"FA",X"CB",X"DC",X"71",X"3E",X"FF",X"A7",X"C9",X"36",X"FA", + X"CB",X"DC",X"CB",X"F9",X"CB",X"F1",X"71",X"CB",X"9C",X"23",X"06",X"19",X"36",X"F9",X"CB",X"DC", + X"71",X"CB",X"9C",X"23",X"10",X"F6",X"36",X"FA",X"CB",X"DC",X"CB",X"B1",X"71",X"AF",X"C9",X"21", + X"F0",X"99",X"7E",X"A7",X"C8",X"35",X"F5",X"23",X"7E",X"CD",X"78",X"33",X"F1",X"C8",X"3D",X"06", + X"00",X"4F",X"5D",X"54",X"23",X"ED",X"B0",X"C9",X"32",X"00",X"A1",X"3E",X"00",X"32",X"80",X"A1", + X"00",X"00",X"00",X"00",X"3E",X"01",X"32",X"80",X"A1",X"C9",X"F5",X"FE",X"05",X"28",X"07",X"3A", + X"20",X"99",X"FE",X"04",X"30",X"09",X"21",X"F0",X"99",X"34",X"7E",X"CF",X"F1",X"77",X"C9",X"F1", + X"C9",X"3E",X"05",X"18",X"E5",X"3E",X"07",X"18",X"E1",X"3E",X"06",X"18",X"DD",X"AF",X"CD",X"8A", + X"33",X"3E",X"02",X"CD",X"8A",X"33",X"3E",X"0F",X"C3",X"8A",X"33",X"3E",X"01",X"C3",X"8A",X"33", + X"3E",X"81",X"C3",X"8A",X"33",X"3E",X"03",X"CD",X"8A",X"33",X"3E",X"08",X"CD",X"8A",X"33",X"3A", + X"01",X"99",X"E6",X"03",X"C0",X"21",X"04",X"99",X"7E",X"A7",X"C8",X"FE",X"09",X"D0",X"34",X"7E", + X"CD",X"4F",X"1E",X"32",X"62",X"98",X"C9",X"3E",X"09",X"18",X"9F",X"3E",X"0B",X"18",X"9B",X"3E", + X"04",X"18",X"D9",X"3E",X"19",X"18",X"93",X"3E",X"0A",X"18",X"8F",X"3E",X"10",X"CD",X"8A",X"33", + X"3E",X"11",X"CD",X"8A",X"33",X"3E",X"12",X"C3",X"8A",X"33",X"AF",X"32",X"18",X"9C",X"CD",X"8A", + X"33",X"3E",X"13",X"CD",X"8A",X"33",X"3E",X"14",X"CD",X"8A",X"33",X"3E",X"15",X"C3",X"8A",X"33", + X"3E",X"16",X"CD",X"8A",X"33",X"3E",X"17",X"CD",X"8A",X"33",X"3E",X"18",X"C3",X"8A",X"33",X"3E", + X"0D",X"C3",X"8A",X"33",X"3E",X"0C",X"C3",X"8A",X"33",X"3A",X"04",X"99",X"A7",X"C8",X"3E",X"0E", + X"C3",X"8A",X"33",X"53",X"34",X"53",X"34",X"8B",X"35",X"8B",X"35",X"C3",X"36",X"C3",X"36",X"FB", + X"37",X"FB",X"37",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"24", + X"44",X"0F",X"24",X"44",X"0F",X"20",X"F2",X"0F",X"24",X"44",X"0F",X"35",X"55",X"1F",X"35",X"55", + X"1F",X"76",X"F3",X"1F",X"35",X"5B",X"6F",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"76",X"FF",X"FF", + X"FF",X"F7",X"6F",X"24",X"44",X"44",X"40",X"F2",X"44",X"A6",X"F2",X"0F",X"20",X"F7",X"6F",X"35", + X"55",X"55",X"51",X"F3",X"55",X"51",X"F3",X"1F",X"31",X"F7",X"6F",X"DF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"F7",X"6F",X"24",X"44",X"44",X"44",X"44",X"0F",X"24",X"44",X"44", + X"40",X"F7",X"6F",X"35",X"55",X"55",X"55",X"5B",X"6F",X"35",X"55",X"55",X"B6",X"F3",X"1F",X"FF", + X"FF",X"FF",X"FF",X"F7",X"6F",X"FF",X"FF",X"FF",X"76",X"FF",X"FF",X"24",X"44",X"0F",X"20",X"F7", + X"6F",X"24",X"44",X"0F",X"76",X"F2",X"0F",X"35",X"55",X"1F",X"31",X"F3",X"1F",X"35",X"55",X"1F", + X"31",X"F3",X"1F",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"24",X"44",X"44",X"40",X"F2", + X"0F",X"24",X"44",X"44",X"40",X"F2",X"0F",X"35",X"55",X"55",X"51",X"F7",X"6F",X"35",X"55",X"55", + X"51",X"F7",X"6F",X"FF",X"FF",X"FF",X"FF",X"F7",X"6F",X"FF",X"FF",X"FF",X"FF",X"F7",X"6F",X"20", + X"F2",X"0F",X"20",X"F7",X"6F",X"20",X"F2",X"0F",X"24",X"4A",X"6F",X"31",X"F3",X"1F",X"76",X"F3", + X"1F",X"31",X"F7",X"6F",X"35",X"5B",X"6F",X"FF",X"FF",X"FF",X"76",X"FF",X"FF",X"FF",X"F7",X"6F", + X"FF",X"F7",X"6F",X"24",X"44",X"0F",X"76",X"F2",X"44",X"40",X"F7",X"84",X"40",X"F7",X"6F",X"35", + X"55",X"1F",X"76",X"F3",X"55",X"B6",X"F3",X"55",X"51",X"F3",X"1F",X"FF",X"FF",X"FF",X"76",X"FF", + X"FF",X"76",X"FF",X"FF",X"FF",X"FF",X"FF",X"20",X"F2",X"44",X"A6",X"F2",X"0F",X"78",X"44",X"44", + X"44",X"44",X"0F",X"31",X"F3",X"55",X"51",X"F3",X"1F",X"35",X"55",X"55",X"55",X"55",X"1F",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"20",X"F2",X"44",X"44",X"44",X"0F",X"20",X"F2",X"44", + X"40",X"F2",X"0F",X"76",X"F7",X"95",X"55",X"5B",X"6F",X"76",X"F3",X"55",X"51",X"F7",X"6F",X"76", + X"F7",X"6F",X"FF",X"F7",X"6F",X"76",X"FF",X"FF",X"FF",X"F7",X"6F",X"76",X"F7",X"6F",X"20",X"F7", + X"6F",X"76",X"F2",X"44",X"44",X"4A",X"6F",X"76",X"F7",X"6F",X"76",X"F7",X"6F",X"76",X"F7",X"95", + X"55",X"55",X"1F",X"76",X"F7",X"6F",X"76",X"F7",X"6F",X"76",X"F7",X"6F",X"FF",X"FF",X"FF",X"76", + X"F7",X"6F",X"76",X"F7",X"6F",X"76",X"F7",X"6F",X"24",X"44",X"0F",X"76",X"F3",X"1F",X"76",X"F7", + X"6F",X"31",X"F7",X"6F",X"35",X"55",X"1F",X"76",X"FF",X"FF",X"76",X"F7",X"6F",X"FF",X"F7",X"6F", + X"DF",X"FF",X"FF",X"78",X"44",X"44",X"A6",X"F7",X"6F",X"24",X"4A",X"6F",X"24",X"44",X"0F",X"35", + X"55",X"55",X"51",X"F3",X"1F",X"35",X"55",X"1F",X"35",X"55",X"1F",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"20",X"F2",X"0F",X"20",X"F2",X"0F",X"24",X"44",X"44",X"40",X"F2",X"0F",X"76", + X"F7",X"6F",X"76",X"F7",X"6F",X"79",X"55",X"55",X"B6",X"F7",X"6F",X"76",X"F7",X"6F",X"76",X"F7", + X"6F",X"76",X"FF",X"FF",X"76",X"F7",X"6F",X"76",X"F7",X"6F",X"76",X"F7",X"6F",X"76",X"F2",X"0F", + X"76",X"F7",X"6F",X"76",X"F7",X"6F",X"76",X"F7",X"6F",X"31",X"F7",X"6F",X"31",X"F3",X"1F",X"76", + X"F7",X"6F",X"76",X"F7",X"6F",X"FF",X"F7",X"6F",X"FF",X"FF",X"FF",X"76",X"F7",X"6F",X"76",X"F7", + X"6F",X"24",X"4A",X"84",X"44",X"44",X"0F",X"31",X"F7",X"6F",X"31",X"F7",X"6F",X"35",X"55",X"55", + X"55",X"55",X"1F",X"FF",X"F7",X"6F",X"FF",X"F7",X"6F",X"FF",X"FF",X"DF",X"FF",X"FF",X"FF",X"20", + X"F7",X"84",X"44",X"4A",X"6F",X"24",X"44",X"0F",X"24",X"44",X"0F",X"31",X"F3",X"55",X"55",X"55", + X"1F",X"35",X"55",X"1F",X"35",X"55",X"1F",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"24", + X"44",X"44",X"40",X"F2",X"0F",X"24",X"44",X"0F",X"20",X"F2",X"0F",X"79",X"55",X"55",X"51",X"F7", + X"6F",X"35",X"55",X"1F",X"76",X"F3",X"1F",X"76",X"DF",X"FF",X"FF",X"F7",X"6F",X"FF",X"FF",X"FF", + X"76",X"FF",X"FF",X"76",X"F2",X"0F",X"20",X"F7",X"6F",X"20",X"F2",X"44",X"A6",X"F2",X"0F",X"76", + X"F3",X"1F",X"76",X"F7",X"6F",X"76",X"F3",X"55",X"51",X"F7",X"6F",X"76",X"FF",X"FF",X"76",X"F7", + X"6F",X"76",X"FF",X"FF",X"FF",X"F7",X"6F",X"76",X"F2",X"44",X"A6",X"F7",X"6F",X"78",X"44",X"0F", + X"20",X"F7",X"6F",X"76",X"F3",X"55",X"51",X"F7",X"6F",X"79",X"55",X"1F",X"76",X"F7",X"6F",X"76", + X"FF",X"FF",X"FF",X"F7",X"6F",X"76",X"FF",X"FF",X"76",X"F7",X"6F",X"76",X"F2",X"44",X"44",X"4A", + X"6F",X"76",X"F2",X"44",X"A6",X"F7",X"6F",X"31",X"F3",X"55",X"55",X"55",X"1F",X"31",X"F3",X"55", + X"51",X"F3",X"1F",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"20",X"F2",X"44",X"40",X"F2", + X"0F",X"24",X"44",X"0F",X"24",X"44",X"0F",X"76",X"F3",X"55",X"B6",X"F7",X"6F",X"35",X"55",X"1F", + X"35",X"5B",X"6F",X"76",X"FF",X"FF",X"76",X"F7",X"6F",X"FF",X"FF",X"FF",X"FF",X"F7",X"6F",X"76", + X"F2",X"0F",X"76",X"F7",X"6F",X"20",X"F2",X"44",X"40",X"F7",X"6F",X"31",X"F7",X"6F",X"31",X"F3", + X"1F",X"76",X"F3",X"55",X"51",X"F7",X"6F",X"FF",X"F7",X"6F",X"FF",X"FF",X"FF",X"76",X"FF",X"FF", + X"FF",X"F7",X"6F",X"20",X"F7",X"84",X"44",X"44",X"0F",X"76",X"F2",X"44",X"40",X"F7",X"6F",X"31", + X"F3",X"55",X"55",X"5B",X"6F",X"76",X"F3",X"55",X"51",X"F3",X"1F",X"FF",X"FF",X"FF",X"FF",X"F7", + X"6F",X"76",X"FF",X"FF",X"FF",X"FF",X"FF",X"24",X"44",X"44",X"40",X"F7",X"6F",X"78",X"44",X"0F", + X"24",X"44",X"0F",X"35",X"55",X"55",X"51",X"F3",X"1F",X"35",X"55",X"1F",X"35",X"55",X"1F",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"20",X"F2",X"0F",X"20",X"F2",X"0F",X"20",X"F2",X"0F", + X"20",X"F2",X"0F",X"31",X"F3",X"1F",X"31",X"F3",X"1F",X"31",X"F3",X"1F",X"31",X"F3",X"1F",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"20",X"F2",X"0F",X"20",X"F2", + X"0F",X"20",X"F2",X"0F",X"20",X"F2",X"0F",X"31",X"F3",X"1F",X"31",X"F3",X"1F",X"31",X"F3",X"1F", + X"31",X"F3",X"1F",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"20", + X"F2",X"0F",X"20",X"F2",X"0F",X"20",X"F2",X"0F",X"20",X"F2",X"0F",X"31",X"F3",X"1F",X"31",X"F3", + X"1F",X"31",X"F3",X"1F",X"31",X"F3",X"1F",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"20",X"F2",X"0F",X"20",X"F2",X"0F",X"20",X"F2",X"0F",X"20",X"F2",X"0F",X"31", + X"F3",X"1F",X"31",X"F3",X"1F",X"31",X"F3",X"1F",X"31",X"F3",X"1F",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"20",X"F2",X"0F",X"20",X"F2",X"0F",X"20",X"F2",X"0F",X"20",X"F2",X"0F",X"31", + X"F3",X"1F",X"31",X"F3",X"1F",X"31",X"F3",X"1F",X"31",X"F3",X"1F",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"20",X"F2",X"0F",X"20",X"F2",X"0F",X"20",X"F2",X"0F", + X"20",X"F2",X"0F",X"31",X"F3",X"1F",X"31",X"F3",X"1F",X"31",X"F3",X"1F",X"31",X"F3",X"1F",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FD",X"FF",X"FF",X"FF",X"20",X"F2",X"0F",X"20",X"F2", + X"0F",X"20",X"F2",X"0F",X"20",X"F2",X"0F",X"31",X"F3",X"1F",X"31",X"F3",X"1F",X"31",X"F3",X"1F", + X"31",X"F3",X"1F",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"20", + X"F2",X"0F",X"20",X"F2",X"0F",X"20",X"F2",X"0F",X"20",X"F2",X"0F",X"31",X"F3",X"1F",X"31",X"F3", + X"1F",X"31",X"F3",X"1F",X"31",X"F3",X"1F",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"3A",X"1A",X"9C",X"A7",X"C8",X"3A",X"04",X"99",X"A7",X"C8",X"3A",X"19",X"98", + X"A7",X"20",X"44",X"21",X"1A",X"9C",X"11",X"0B",X"9C",X"3A",X"10",X"9C",X"96",X"30",X"02",X"ED", + X"44",X"FE",X"08",X"D0",X"47",X"EB",X"3A",X"01",X"9C",X"96",X"30",X"02",X"ED",X"44",X"FE",X"08", + X"D0",X"CD",X"34",X"34",X"CD",X"D5",X"33",X"3E",X"40",X"32",X"19",X"98",X"3A",X"2F",X"99",X"A7", + X"28",X"04",X"3E",X"34",X"18",X"02",X"3E",X"37",X"32",X"0A",X"9C",X"21",X"00",X"05",X"22",X"15", + X"99",X"22",X"1A",X"99",X"C3",X"FE",X"30",X"3D",X"32",X"19",X"98",X"C0",X"AF",X"32",X"1A",X"9C", + X"C9",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"80",X"88",X"80",X"88",X"FF",X"98",X"FF",X"98",X"90",X"FF",X"90",X"FF",X"FF",X"98",X"FF",X"98", + X"90",X"FF",X"90",X"FF",X"A0",X"A8",X"A0",X"A8",X"FF",X"B8",X"FF",X"B8",X"B0",X"FF",X"B0",X"FF", + X"FF",X"B8",X"FF",X"B8",X"B0",X"FF",X"B0",X"FF",X"C0",X"C8",X"C0",X"C8",X"FF",X"D8",X"FF",X"D8", + X"D0",X"FF",X"D0",X"FF",X"FF",X"D8",X"FF",X"D8",X"D0",X"FF",X"D0",X"FF",X"3A",X"18",X"9C",X"A7", + X"C8",X"3A",X"04",X"99",X"A7",X"C8",X"3A",X"18",X"98",X"A7",X"20",X"44",X"21",X"18",X"9C",X"11", + X"09",X"9C",X"3A",X"10",X"9C",X"96",X"30",X"02",X"ED",X"44",X"FE",X"08",X"D0",X"47",X"EB",X"3A", + X"01",X"9C",X"96",X"30",X"02",X"ED",X"44",X"FE",X"08",X"D0",X"CD",X"34",X"34",X"CD",X"D5",X"33", + X"3E",X"40",X"32",X"18",X"98",X"3A",X"2F",X"99",X"A7",X"28",X"04",X"3E",X"34",X"18",X"02",X"3E", + X"37",X"32",X"08",X"9C",X"21",X"00",X"05",X"22",X"15",X"99",X"22",X"1A",X"99",X"C3",X"FE",X"30", + X"3D",X"32",X"18",X"98",X"C0",X"AF",X"32",X"18",X"9C",X"C9",X"3A",X"02",X"99",X"A7",X"C0",X"2F", + X"32",X"02",X"99",X"D9",X"21",X"00",X"99",X"34",X"CD",X"06",X"19",X"CD",X"F7",X"33",X"D9",X"C9", + X"3A",X"04",X"99",X"A7",X"C8",X"3A",X"02",X"98",X"E6",X"1F",X"C0",X"CD",X"A5",X"2F",X"E6",X"07", + X"FE",X"03",X"D0",X"3E",X"FF",X"32",X"70",X"98",X"C9",X"3A",X"04",X"99",X"A7",X"C8",X"3A",X"62", + X"98",X"21",X"60",X"98",X"86",X"77",X"D0",X"21",X"8A",X"9A",X"11",X"8B",X"9A",X"01",X"0B",X"00", + X"ED",X"B8",X"21",X"15",X"9B",X"11",X"17",X"9B",X"01",X"16",X"00",X"ED",X"B8",X"2A",X"00",X"9B", + X"11",X"E0",X"FF",X"19",X"22",X"00",X"9B",X"C9",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"40",X"80",X"80",X"40",X"FF",X"C0",X"FF",X"80",X"00",X"FF",X"80",X"FF",X"FF",X"40",X"FF",X"00", + X"40",X"FF",X"C0",X"FF",X"40",X"80",X"80",X"40",X"FF",X"C0",X"FF",X"80",X"00",X"FF",X"80",X"FF", + X"FF",X"40",X"FF",X"00",X"40",X"FF",X"C0",X"FF",X"40",X"80",X"80",X"40",X"FF",X"C0",X"FF",X"80", + X"00",X"FF",X"80",X"FF",X"FF",X"40",X"FF",X"00",X"40",X"FF",X"C0",X"FF",X"DD",X"21",X"74",X"98", + X"DD",X"7E",X"00",X"A7",X"C4",X"4E",X"3F",X"DD",X"23",X"DD",X"7E",X"00",X"A7",X"C8",X"FD",X"21", + X"86",X"98",X"06",X"06",X"FD",X"7E",X"F0",X"A7",X"28",X"2A",X"FD",X"7E",X"00",X"DD",X"96",X"10", + X"30",X"02",X"ED",X"44",X"FE",X"04",X"30",X"1C",X"FD",X"7E",X"10",X"DD",X"96",X"20",X"30",X"02", + X"ED",X"44",X"FE",X"04",X"30",X"0E",X"AF",X"DD",X"77",X"00",X"DD",X"77",X"10",X"FD",X"77",X"F0", + X"FD",X"77",X"00",X"C9",X"FD",X"23",X"10",X"CC",X"C9",X"3A",X"05",X"99",X"A7",X"C8",X"3A",X"65", + X"98",X"21",X"63",X"98",X"86",X"77",X"D0",X"21",X"AA",X"9A",X"11",X"AB",X"9A",X"01",X"0B",X"00", + X"ED",X"B8",X"21",X"55",X"9B",X"11",X"57",X"9B",X"01",X"16",X"00",X"ED",X"B8",X"2A",X"40",X"9B", + X"11",X"20",X"00",X"19",X"22",X"40",X"9B",X"C9",X"3A",X"03",X"99",X"A7",X"28",X"2A",X"FE",X"08", + X"D0",X"21",X"A4",X"8B",X"11",X"E0",X"FF",X"47",X"4F",X"36",X"96",X"19",X"10",X"FB",X"21",X"44", + X"8B",X"36",X"A4",X"21",X"A4",X"83",X"47",X"36",X"38",X"19",X"10",X"FB",X"3E",X"07",X"91",X"D8", + X"C8",X"47",X"36",X"20",X"19",X"10",X"FB",X"C9",X"21",X"A4",X"83",X"11",X"E0",X"FF",X"06",X"08", + X"36",X"20",X"19",X"10",X"FB",X"C9",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_snd_rom.vhd b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_snd_rom.vhd new file mode 100644 index 00000000..daa71a58 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_snd_rom.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity jng_snd_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of jng_snd_rom is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"21",X"00",X"20",X"06",X"00",X"C3",X"B2",X"01",X"32",X"00",X"50",X"3A",X"00",X"40",X"C9",X"FF", + X"32",X"00",X"70",X"3A",X"00",X"60",X"C9",X"FF",X"78",X"CF",X"79",X"32",X"00",X"40",X"C9",X"FF", + X"78",X"D7",X"79",X"32",X"00",X"60",X"C9",X"FF",X"87",X"85",X"6F",X"7C",X"CE",X"00",X"67",X"7E", + X"23",X"66",X"6F",X"E9",X"FF",X"FF",X"FF",X"FF",X"D9",X"08",X"CD",X"40",X"00",X"08",X"D9",X"C9", + X"3E",X"0E",X"CF",X"B7",X"28",X"09",X"F2",X"79",X"00",X"CB",X"BF",X"CD",X"6C",X"00",X"C9",X"21", + X"00",X"20",X"06",X"0C",X"AF",X"77",X"23",X"10",X"FC",X"C9",X"21",X"00",X"20",X"06",X"06",X"0E", + X"07",X"BE",X"28",X"05",X"23",X"23",X"10",X"F9",X"41",X"79",X"90",X"C9",X"CD",X"5A",X"00",X"C8", + X"AF",X"77",X"23",X"77",X"C9",X"13",X"23",X"22",X"28",X"32",X"1A",X"20",X"CD",X"5A",X"00",X"28", + X"04",X"23",X"36",X"00",X"C9",X"3A",X"1A",X"20",X"21",X"75",X"00",X"06",X"02",X"BE",X"28",X"19", + X"23",X"10",X"FA",X"06",X"02",X"BE",X"28",X"21",X"23",X"10",X"FA",X"AF",X"CD",X"5A",X"00",X"28", + X"3A",X"3A",X"1A",X"20",X"77",X"23",X"36",X"00",X"C9",X"AF",X"CD",X"5A",X"00",X"28",X"05",X"FE", + X"04",X"FA",X"C9",X"00",X"CD",X"37",X"01",X"18",X"58",X"AF",X"CD",X"5A",X"00",X"28",X"05",X"FE", + X"04",X"F2",X"C9",X"00",X"CD",X"62",X"01",X"18",X"40",X"21",X"1A",X"20",X"46",X"0E",X"00",X"21", + X"00",X"20",X"3D",X"87",X"5F",X"51",X"19",X"70",X"23",X"71",X"C9",X"CD",X"37",X"01",X"CD",X"62", + X"01",X"B7",X"28",X"2D",X"3A",X"17",X"20",X"B7",X"28",X"1F",X"3A",X"18",X"20",X"21",X"06",X"20", + X"CD",X"26",X"01",X"CD",X"2E",X"01",X"57",X"3A",X"17",X"20",X"21",X"00",X"20",X"CD",X"26",X"01", + X"CD",X"2E",X"01",X"BA",X"F2",X"09",X"01",X"18",X"08",X"3A",X"18",X"20",X"21",X"06",X"20",X"18", + X"06",X"3A",X"17",X"20",X"21",X"00",X"20",X"B7",X"C8",X"3D",X"87",X"4F",X"06",X"00",X"09",X"3A", + X"1A",X"20",X"77",X"23",X"70",X"C9",X"3D",X"87",X"4F",X"06",X"00",X"09",X"7E",X"C9",X"21",X"87", + X"07",X"06",X"00",X"4F",X"09",X"7E",X"C9",X"3A",X"00",X"20",X"CD",X"2E",X"01",X"32",X"12",X"20", + X"3A",X"02",X"20",X"CD",X"2E",X"01",X"32",X"13",X"20",X"3A",X"04",X"20",X"CD",X"2E",X"01",X"32", + X"14",X"20",X"3A",X"1A",X"20",X"CD",X"2E",X"01",X"32",X"15",X"20",X"CD",X"8D",X"01",X"32",X"17", + X"20",X"C9",X"3A",X"06",X"20",X"CD",X"2E",X"01",X"32",X"12",X"20",X"3A",X"08",X"20",X"CD",X"2E", + X"01",X"32",X"13",X"20",X"3A",X"0A",X"20",X"CD",X"2E",X"01",X"32",X"14",X"20",X"3A",X"1A",X"20", + X"CD",X"2E",X"01",X"32",X"15",X"20",X"CD",X"8D",X"01",X"32",X"18",X"20",X"C9",X"21",X"12",X"20", + X"3A",X"15",X"20",X"06",X"03",X"4F",X"7E",X"B9",X"F2",X"9C",X"01",X"4F",X"23",X"10",X"F7",X"79", + X"06",X"03",X"0E",X"01",X"21",X"12",X"20",X"BE",X"28",X"06",X"0C",X"23",X"10",X"F9",X"0E",X"00", + X"79",X"C9",X"70",X"23",X"7C",X"FE",X"24",X"20",X"F9",X"F9",X"ED",X"56",X"21",X"00",X"30",X"22", + X"0C",X"20",X"77",X"01",X"3F",X"07",X"DF",X"E7",X"32",X"0E",X"20",X"32",X"0F",X"20",X"CD",X"C8", + X"02",X"CD",X"CC",X"02",X"CD",X"D0",X"02",X"CD",X"D6",X"02",X"CD",X"DA",X"02",X"CD",X"DE",X"02", + X"FB",X"3E",X"0F",X"CF",X"E6",X"80",X"20",X"F9",X"3E",X"0F",X"CF",X"E6",X"80",X"28",X"F9",X"F3", + X"3E",X"01",X"32",X"10",X"20",X"3A",X"01",X"20",X"B7",X"3A",X"00",X"20",X"CA",X"04",X"02",X"CD", + X"AC",X"02",X"18",X"03",X"CD",X"92",X"02",X"FB",X"00",X"00",X"F3",X"3E",X"02",X"32",X"10",X"20", + X"3A",X"03",X"20",X"B7",X"3A",X"02",X"20",X"CA",X"1F",X"02",X"CD",X"AC",X"02",X"18",X"03",X"CD", + X"92",X"02",X"FB",X"00",X"00",X"F3",X"3E",X"03",X"32",X"10",X"20",X"3A",X"05",X"20",X"B7",X"3A", + X"04",X"20",X"CA",X"3A",X"02",X"CD",X"AC",X"02",X"18",X"03",X"CD",X"92",X"02",X"FB",X"00",X"00", + X"F3",X"3E",X"04",X"32",X"10",X"20",X"3A",X"07",X"20",X"B7",X"3A",X"06",X"20",X"CA",X"55",X"02", + X"CD",X"AC",X"02",X"18",X"03",X"CD",X"92",X"02",X"FB",X"00",X"00",X"F3",X"3E",X"05",X"32",X"10", + X"20",X"3A",X"09",X"20",X"B7",X"3A",X"08",X"20",X"CA",X"70",X"02",X"CD",X"AC",X"02",X"18",X"03", + X"CD",X"92",X"02",X"FB",X"00",X"00",X"F3",X"3E",X"06",X"32",X"10",X"20",X"3A",X"0B",X"20",X"B7", + X"3A",X"0A",X"20",X"CA",X"8C",X"02",X"CD",X"AC",X"02",X"C3",X"E0",X"01",X"CD",X"92",X"02",X"C3", + X"E0",X"01",X"21",X"A1",X"07",X"EF",X"B7",X"20",X"1B",X"E5",X"21",X"01",X"20",X"3A",X"10",X"20", + X"3D",X"87",X"D5",X"5F",X"16",X"00",X"19",X"D1",X"36",X"01",X"E1",X"C9",X"B7",X"C8",X"21",X"D5", + X"07",X"EF",X"B7",X"C8",X"57",X"21",X"00",X"20",X"3A",X"10",X"20",X"3D",X"4F",X"06",X"00",X"09", + X"09",X"15",X"28",X"01",X"70",X"23",X"70",X"C9",X"06",X"08",X"18",X"06",X"06",X"09",X"18",X"02", + X"06",X"0A",X"0E",X"00",X"DF",X"C9",X"06",X"08",X"18",X"06",X"06",X"09",X"18",X"02",X"06",X"0A", + X"0E",X"00",X"E7",X"C9",X"3A",X"10",X"20",X"3D",X"21",X"ED",X"02",X"EF",X"C9",X"F9",X"02",X"02", + X"03",X"0B",X"03",X"14",X"03",X"1D",X"03",X"26",X"03",X"CD",X"C8",X"02",X"0E",X"09",X"CD",X"2F", + X"03",X"C9",X"CD",X"CC",X"02",X"0E",X"12",X"CD",X"2F",X"03",X"C9",X"CD",X"D0",X"02",X"0E",X"24", + X"CD",X"2F",X"03",X"C9",X"CD",X"D6",X"02",X"0E",X"09",X"CD",X"3B",X"03",X"C9",X"CD",X"DA",X"02", + X"0E",X"12",X"CD",X"3B",X"03",X"C9",X"CD",X"DE",X"02",X"0E",X"24",X"CD",X"3B",X"03",X"C9",X"3A", + X"0E",X"20",X"B1",X"32",X"0E",X"20",X"06",X"07",X"4F",X"DF",X"C9",X"3A",X"0F",X"20",X"B1",X"32", + X"0F",X"20",X"06",X"07",X"4F",X"E7",X"C9",X"06",X"06",X"3A",X"10",X"20",X"FE",X"04",X"FA",X"53", + X"03",X"E7",X"C9",X"DF",X"C9",X"06",X"06",X"3A",X"10",X"20",X"FE",X"04",X"FA",X"63",X"03",X"78", + X"D7",X"4F",X"C9",X"78",X"CF",X"4F",X"C9",X"3A",X"0E",X"20",X"A0",X"B1",X"32",X"0E",X"20",X"4F", + X"06",X"07",X"DF",X"C9",X"3A",X"0F",X"20",X"A0",X"B1",X"32",X"0F",X"20",X"4F",X"06",X"07",X"E7", + X"C9",X"3A",X"10",X"20",X"3D",X"21",X"8A",X"03",X"EF",X"C9",X"96",X"03",X"9D",X"03",X"A4",X"03", + X"AB",X"03",X"B2",X"03",X"B9",X"03",X"01",X"08",X"FE",X"CD",X"67",X"03",X"C9",X"01",X"10",X"FD", + X"CD",X"67",X"03",X"C9",X"01",X"20",X"FB",X"CD",X"67",X"03",X"C9",X"01",X"08",X"FE",X"CD",X"74", + X"03",X"C9",X"01",X"10",X"FD",X"CD",X"74",X"03",X"C9",X"01",X"20",X"FB",X"CD",X"74",X"03",X"C9", + X"3A",X"10",X"20",X"3D",X"21",X"C9",X"03",X"EF",X"C9",X"D5",X"03",X"DC",X"03",X"E3",X"03",X"EA", + X"03",X"F1",X"03",X"F8",X"03",X"01",X"01",X"F7",X"CD",X"67",X"03",X"C9",X"01",X"02",X"EF",X"CD", + X"67",X"03",X"C9",X"01",X"04",X"DF",X"CD",X"67",X"03",X"C9",X"01",X"01",X"F7",X"CD",X"74",X"03", + X"C9",X"01",X"02",X"EF",X"CD",X"74",X"03",X"C9",X"01",X"04",X"DF",X"CD",X"74",X"03",X"C9",X"3A", + X"10",X"20",X"3D",X"21",X"08",X"04",X"EF",X"C9",X"14",X"04",X"1B",X"04",X"22",X"04",X"29",X"04", + X"30",X"04",X"37",X"04",X"01",X"00",X"F6",X"CD",X"67",X"03",X"C9",X"01",X"00",X"ED",X"CD",X"67", + X"03",X"C9",X"01",X"00",X"DB",X"CD",X"67",X"03",X"C9",X"01",X"00",X"F6",X"CD",X"74",X"03",X"C9", + X"01",X"00",X"ED",X"CD",X"74",X"03",X"C9",X"01",X"00",X"DB",X"CD",X"74",X"03",X"C9",X"3A",X"10", + X"20",X"FE",X"04",X"30",X"05",X"C6",X"07",X"47",X"DF",X"C9",X"C6",X"04",X"47",X"E7",X"C9",X"3A", + X"10",X"20",X"FE",X"04",X"30",X"04",X"C6",X"07",X"CF",X"C9",X"C6",X"04",X"D7",X"C9",X"3A",X"10", + X"20",X"FE",X"04",X"30",X"09",X"3D",X"87",X"47",X"4D",X"DF",X"4C",X"04",X"DF",X"C9",X"D6",X"04", + X"87",X"47",X"4D",X"E7",X"4C",X"04",X"E7",X"C9",X"3A",X"10",X"20",X"FE",X"04",X"30",X"0A",X"3D", + X"87",X"67",X"24",X"CF",X"6F",X"7C",X"CF",X"67",X"C9",X"D6",X"04",X"87",X"67",X"24",X"D7",X"6F", + X"7C",X"D7",X"67",X"C9",X"FE",X"04",X"D0",X"F5",X"CD",X"E4",X"04",X"F1",X"B7",X"20",X"02",X"77", + X"C9",X"21",X"B4",X"04",X"87",X"87",X"4F",X"87",X"81",X"4F",X"06",X"00",X"09",X"3A",X"10",X"20", + X"3D",X"EF",X"77",X"C9",X"07",X"05",X"0C",X"05",X"11",X"05",X"16",X"05",X"1B",X"05",X"20",X"05", + X"25",X"05",X"2A",X"05",X"2F",X"05",X"34",X"05",X"39",X"05",X"3E",X"05",X"43",X"05",X"48",X"05", + X"4D",X"05",X"52",X"05",X"57",X"05",X"5C",X"05",X"61",X"05",X"66",X"05",X"6B",X"05",X"70",X"05", + X"75",X"05",X"7A",X"05",X"21",X"B4",X"04",X"3A",X"10",X"20",X"3D",X"EF",X"C9",X"2A",X"0C",X"20", + X"7B",X"A5",X"6F",X"7A",X"A4",X"67",X"22",X"0C",X"20",X"C9",X"2A",X"0C",X"20",X"7B",X"B5",X"6F", + X"7A",X"B4",X"67",X"22",X"0C",X"20",X"C9",X"11",X"3F",X"FF",X"18",X"E1",X"11",X"FF",X"FC",X"18", + X"DC",X"11",X"FF",X"F3",X"18",X"D7",X"11",X"FC",X"FF",X"18",X"D2",X"11",X"F3",X"FF",X"18",X"CD", + X"11",X"CF",X"FF",X"18",X"C8",X"11",X"80",X"00",X"18",X"D0",X"11",X"00",X"02",X"18",X"CB",X"11", + X"00",X"08",X"18",X"C6",X"11",X"02",X"00",X"18",X"C1",X"11",X"08",X"00",X"18",X"BC",X"11",X"20", + X"00",X"18",X"B7",X"11",X"40",X"00",X"18",X"B2",X"11",X"00",X"01",X"18",X"AD",X"11",X"00",X"04", + X"18",X"A8",X"11",X"01",X"00",X"18",X"A3",X"11",X"04",X"00",X"18",X"9E",X"11",X"10",X"00",X"18", + X"99",X"11",X"C0",X"00",X"18",X"94",X"11",X"00",X"03",X"18",X"8F",X"11",X"00",X"0C",X"18",X"8A", + X"11",X"03",X"00",X"18",X"85",X"11",X"0C",X"00",X"18",X"80",X"11",X"30",X"00",X"C3",X"FA",X"04", + X"DD",X"7E",X"00",X"FE",X"FF",X"C8",X"CD",X"8B",X"05",X"AF",X"C9",X"DD",X"35",X"01",X"C0",X"3A", + X"42",X"20",X"DD",X"77",X"01",X"DD",X"CB",X"00",X"46",X"C2",X"AB",X"05",X"DD",X"7E",X"07",X"D6", + X"01",X"FA",X"AB",X"05",X"DD",X"77",X"07",X"4F",X"CD",X"3E",X"04",X"DD",X"35",X"00",X"C0",X"DD", + X"6E",X"02",X"DD",X"66",X"03",X"7E",X"47",X"E6",X"1F",X"CA",X"46",X"06",X"FE",X"1F",X"C2",X"62", + X"06",X"23",X"DD",X"75",X"02",X"DD",X"74",X"03",X"78",X"E6",X"E0",X"0F",X"0F",X"0F",X"0F",X"4F", + X"06",X"00",X"21",X"DB",X"05",X"09",X"5E",X"23",X"56",X"EB",X"E9",X"EB",X"05",X"09",X"06",X"1F", + X"06",X"3C",X"06",X"3C",X"06",X"3C",X"06",X"3C",X"06",X"3C",X"06",X"DD",X"6E",X"02",X"DD",X"66", + X"03",X"4E",X"CB",X"21",X"06",X"00",X"21",X"95",X"06",X"09",X"5E",X"23",X"56",X"ED",X"53",X"40", + X"20",X"DD",X"73",X"04",X"DD",X"72",X"05",X"18",X"23",X"DD",X"6E",X"02",X"DD",X"66",X"03",X"4E", + X"06",X"00",X"21",X"2D",X"07",X"09",X"7E",X"32",X"42",X"20",X"DD",X"77",X"01",X"18",X"0D",X"DD", + X"6E",X"02",X"DD",X"66",X"03",X"7E",X"DD",X"77",X"06",X"DD",X"77",X"07",X"DD",X"6E",X"02",X"DD", + X"66",X"03",X"23",X"DD",X"75",X"02",X"DD",X"74",X"03",X"C3",X"AF",X"05",X"0E",X"00",X"CD",X"3E", + X"04",X"DD",X"36",X"00",X"FF",X"C9",X"CD",X"50",X"06",X"0E",X"00",X"CD",X"3E",X"04",X"18",X"37", + X"78",X"E6",X"E0",X"07",X"07",X"07",X"47",X"3E",X"01",X"18",X"01",X"07",X"10",X"FD",X"DD",X"77", + X"00",X"C9",X"C5",X"CD",X"50",X"06",X"C1",X"78",X"E6",X"1F",X"3D",X"07",X"4F",X"06",X"00",X"DD", + X"6E",X"04",X"DD",X"66",X"05",X"09",X"5E",X"23",X"56",X"EB",X"CD",X"5E",X"04",X"DD",X"4E",X"06", + X"79",X"DD",X"77",X"07",X"CD",X"3E",X"04",X"DD",X"6E",X"02",X"DD",X"66",X"03",X"23",X"DD",X"75", + X"02",X"DD",X"74",X"03",X"C9",X"B5",X"06",X"B9",X"06",X"BD",X"06",X"C1",X"06",X"C5",X"06",X"C9", + X"06",X"CD",X"06",X"D1",X"06",X"D5",X"06",X"D9",X"06",X"DD",X"06",X"E1",X"06",X"E5",X"06",X"E9", + X"06",X"ED",X"06",X"F1",X"06",X"6B",X"08",X"F2",X"07",X"80",X"07",X"14",X"07",X"AE",X"06",X"4E", + X"06",X"F3",X"05",X"9E",X"05",X"4E",X"05",X"01",X"05",X"B9",X"04",X"76",X"04",X"36",X"04",X"F9", + X"03",X"C0",X"03",X"8A",X"03",X"57",X"03",X"27",X"03",X"FA",X"02",X"CF",X"02",X"A7",X"02",X"81", + X"02",X"5D",X"02",X"3B",X"02",X"1B",X"02",X"FD",X"01",X"E0",X"01",X"C5",X"01",X"AC",X"01",X"94", + X"01",X"7D",X"01",X"68",X"01",X"53",X"01",X"40",X"01",X"2E",X"01",X"1D",X"01",X"0D",X"01",X"FE", + X"00",X"F0",X"00",X"E3",X"00",X"D6",X"00",X"CA",X"00",X"BE",X"00",X"B4",X"00",X"AA",X"00",X"A0", + X"00",X"97",X"00",X"8F",X"00",X"87",X"00",X"7F",X"00",X"78",X"00",X"71",X"00",X"6B",X"00",X"65", + X"00",X"5F",X"00",X"5A",X"00",X"55",X"00",X"50",X"00",X"4C",X"00",X"47",X"00",X"57",X"42",X"34", + X"2C",X"25",X"21",X"1D",X"1A",X"0C",X"0B",X"0A",X"09",X"08",X"07",X"06",X"05",X"21",X"6F",X"07", + X"11",X"20",X"20",X"01",X"18",X"00",X"ED",X"B0",X"3A",X"43",X"20",X"07",X"4F",X"07",X"81",X"4F", + X"06",X"00",X"21",X"01",X"0D",X"09",X"11",X"22",X"20",X"CD",X"65",X"07",X"11",X"2A",X"20",X"CD", + X"65",X"07",X"11",X"32",X"20",X"7E",X"12",X"CD",X"6C",X"07",X"7E",X"12",X"23",X"13",X"C9",X"01", + X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"01", + X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"0E",X"07",X"06",X"01",X"04",X"03",X"05", + X"0C",X"02",X"0A",X"09",X"08",X"0D",X"0F",X"11",X"12",X"13",X"14",X"15",X"16",X"17",X"18",X"19", + X"0B",X"E4",X"02",X"09",X"08",X"43",X"08",X"71",X"08",X"D3",X"08",X"1A",X"09",X"AB",X"09",X"F5", + X"09",X"57",X"0A",X"BC",X"0A",X"FD",X"0A",X"60",X"0B",X"B0",X"0B",X"F7",X"0B",X"2E",X"0C",X"74", + X"0C",X"13",X"0D",X"17",X"0D",X"19",X"0D",X"21",X"0D",X"25",X"0D",X"27",X"0D",X"2F",X"0D",X"33", + X"0D",X"35",X"0D",X"C5",X"0C",X"00",X"00",X"24",X"08",X"64",X"08",X"92",X"08",X"EB",X"08",X"40", + X"09",X"C3",X"09",X"12",X"0A",X"77",X"0A",X"D5",X"0A",X"1F",X"0B",X"7A",X"0B",X"CA",X"0B",X"11", + X"0C",X"4B",X"0C",X"8F",X"0C",X"1B",X"0D",X"1D",X"0D",X"1F",X"0D",X"29",X"0D",X"2B",X"0D",X"2D", + X"0D",X"37",X"0D",X"39",X"0D",X"3B",X"0D",X"E2",X"0C",X"3E",X"03",X"CD",X"94",X"04",X"CD",X"81", + X"03",X"21",X"00",X"01",X"CD",X"5E",X"04",X"0E",X"0C",X"CD",X"3E",X"04",X"AF",X"32",X"51",X"20", + X"32",X"50",X"20",X"C9",X"3A",X"50",X"20",X"3D",X"32",X"50",X"20",X"E6",X"03",X"20",X"12",X"CD", + X"78",X"04",X"3A",X"51",X"20",X"C6",X"DB",X"32",X"51",X"20",X"AD",X"E6",X"7F",X"6F",X"CD",X"5E", + X"04",X"AF",X"C9",X"3E",X"01",X"CD",X"94",X"04",X"CD",X"81",X"03",X"0E",X"10",X"CD",X"3E",X"04", + X"21",X"40",X"0D",X"CD",X"5E",X"04",X"CD",X"4F",X"04",X"3D",X"FE",X"04",X"28",X"11",X"4F",X"CD", + X"3E",X"04",X"AF",X"C9",X"CD",X"78",X"04",X"2D",X"28",X"E6",X"CD",X"5E",X"04",X"AF",X"C9",X"3D", + X"C9",X"3E",X"01",X"CD",X"94",X"04",X"CD",X"FF",X"03",X"01",X"1F",X"06",X"CD",X"49",X"03",X"21", + X"00",X"04",X"CD",X"5E",X"04",X"0E",X"0F",X"CD",X"3E",X"04",X"AF",X"32",X"53",X"20",X"32",X"52", + X"20",X"C9",X"21",X"52",X"20",X"35",X"56",X"CD",X"78",X"04",X"3A",X"53",X"20",X"C6",X"B5",X"32", + X"53",X"20",X"AD",X"6F",X"7A",X"E6",X"0F",X"20",X"05",X"25",X"20",X"02",X"26",X"01",X"CD",X"5E", + X"04",X"7A",X"E6",X"3F",X"20",X"19",X"7C",X"FE",X"01",X"20",X"14",X"06",X"06",X"CD",X"57",X"03", + X"0D",X"0D",X"CD",X"49",X"03",X"CD",X"4F",X"04",X"3D",X"28",X"06",X"4F",X"CD",X"3E",X"04",X"AF", + X"C9",X"3D",X"C9",X"3E",X"00",X"CD",X"94",X"04",X"CD",X"81",X"03",X"21",X"40",X"00",X"CD",X"5E", + X"04",X"3E",X"20",X"32",X"55",X"20",X"AF",X"32",X"54",X"20",X"C9",X"3A",X"55",X"20",X"3D",X"32", + X"55",X"20",X"20",X"02",X"3D",X"C9",X"CB",X"47",X"28",X"07",X"0E",X"0C",X"CD",X"3E",X"04",X"AF", + X"C9",X"CD",X"78",X"04",X"3A",X"54",X"20",X"3C",X"32",X"54",X"20",X"85",X"6F",X"30",X"01",X"24", + X"CD",X"5E",X"04",X"0E",X"00",X"CD",X"3E",X"04",X"AF",X"C9",X"AF",X"CD",X"94",X"04",X"CD",X"81", + X"03",X"21",X"40",X"00",X"CD",X"5E",X"04",X"0E",X"00",X"CD",X"3E",X"04",X"3E",X"08",X"32",X"59", + X"20",X"32",X"58",X"20",X"3E",X"DB",X"32",X"56",X"20",X"3E",X"AA",X"32",X"57",X"20",X"AF",X"C9", + X"3A",X"56",X"20",X"3D",X"32",X"56",X"20",X"20",X"02",X"3D",X"C9",X"FE",X"C3",X"38",X"24",X"28", + X"15",X"FE",X"CF",X"38",X"0A",X"CD",X"4F",X"04",X"3C",X"4F",X"CD",X"3E",X"04",X"AF",X"C9",X"0E", + X"00",X"CD",X"3E",X"04",X"AF",X"C9",X"0E",X"0C",X"CD",X"3E",X"04",X"21",X"1F",X"00",X"CD",X"5E", + X"04",X"AF",X"C9",X"3A",X"58",X"20",X"3D",X"32",X"58",X"20",X"28",X"02",X"AF",X"C9",X"3A",X"59", + X"20",X"32",X"58",X"20",X"21",X"57",X"20",X"CB",X"0E",X"38",X"0C",X"CD",X"78",X"04",X"3E",X"20", + X"85",X"6F",X"CD",X"5E",X"04",X"AF",X"C9",X"CD",X"78",X"04",X"3E",X"E0",X"85",X"6F",X"CD",X"5E", + X"04",X"CD",X"4F",X"04",X"3D",X"4F",X"CD",X"3E",X"04",X"AF",X"C9",X"3E",X"00",X"CD",X"94",X"04", + X"CD",X"81",X"03",X"21",X"30",X"00",X"CD",X"5E",X"04",X"0E",X"08",X"CD",X"3E",X"04",X"AF",X"32", + X"5A",X"20",X"C9",X"21",X"5A",X"20",X"35",X"7E",X"28",X"29",X"57",X"FE",X"E8",X"28",X"0C",X"38", + X"11",X"CD",X"4F",X"04",X"3D",X"4F",X"CD",X"3E",X"04",X"AF",X"C9",X"0E",X"0F",X"CD",X"3E",X"04", + X"AF",X"C9",X"CD",X"78",X"04",X"01",X"02",X"00",X"09",X"CD",X"5E",X"04",X"7A",X"E6",X"0F",X"28", + X"E0",X"AF",X"C9",X"3D",X"C9",X"AF",X"CD",X"94",X"04",X"CD",X"81",X"03",X"0E",X"0C",X"CD",X"3E", + X"04",X"21",X"90",X"00",X"CD",X"5E",X"04",X"AF",X"32",X"5B",X"20",X"3E",X"AA",X"32",X"5C",X"20", + X"AF",X"C9",X"21",X"5C",X"20",X"CB",X"0E",X"30",X"02",X"AF",X"C9",X"3A",X"5B",X"20",X"3D",X"32", + X"5B",X"20",X"FE",X"EC",X"38",X"18",X"FE",X"F6",X"28",X"0C",X"CD",X"78",X"04",X"3E",X"F0",X"85", + X"6F",X"CD",X"5E",X"04",X"AF",X"C9",X"21",X"90",X"00",X"CD",X"5E",X"04",X"AF",X"C9",X"CD",X"78", + X"04",X"3E",X"10",X"85",X"6F",X"CD",X"5E",X"04",X"CD",X"4F",X"04",X"D6",X"02",X"20",X"02",X"3D", + X"C9",X"4F",X"CD",X"3E",X"04",X"AF",X"C9",X"3E",X"01",X"CD",X"94",X"04",X"CD",X"81",X"03",X"21", + X"00",X"05",X"CD",X"5E",X"04",X"0E",X"0E",X"CD",X"3E",X"04",X"3E",X"02",X"32",X"5E",X"20",X"AF", + X"32",X"5F",X"20",X"32",X"5D",X"20",X"C9",X"3A",X"5E",X"20",X"3D",X"32",X"5E",X"20",X"20",X"28", + X"3E",X"02",X"32",X"5E",X"20",X"21",X"5D",X"20",X"35",X"28",X"1F",X"7E",X"57",X"CD",X"78",X"04", + X"7A",X"FE",X"E0",X"38",X"18",X"E6",X"07",X"20",X"01",X"25",X"3A",X"5F",X"20",X"C6",X"C3",X"32", + X"5F",X"20",X"AA",X"AD",X"6F",X"CD",X"5E",X"04",X"AF",X"C9",X"3E",X"FF",X"C9",X"E6",X"0F",X"20", + X"E9",X"CD",X"4F",X"04",X"3D",X"4F",X"CD",X"3E",X"04",X"C3",X"9A",X"0A",X"AF",X"CD",X"94",X"04", + X"CD",X"81",X"03",X"21",X"C0",X"01",X"CD",X"5E",X"04",X"0E",X"0F",X"CD",X"3E",X"04",X"3E",X"48", + X"32",X"60",X"20",X"AF",X"C9",X"3A",X"60",X"20",X"3D",X"32",X"60",X"20",X"20",X"02",X"3D",X"C9", + X"FE",X"02",X"38",X"12",X"E6",X"07",X"28",X"02",X"AF",X"C9",X"CD",X"78",X"04",X"01",X"D4",X"FF", + X"09",X"CD",X"5E",X"04",X"AF",X"C9",X"0E",X"0F",X"CD",X"3E",X"04",X"AF",X"C9",X"3E",X"01",X"CD", + X"94",X"04",X"CD",X"81",X"03",X"21",X"40",X"00",X"CD",X"5E",X"04",X"0E",X"03",X"CD",X"3E",X"04", + X"3E",X"20",X"32",X"61",X"20",X"32",X"62",X"20",X"3E",X"08",X"32",X"63",X"20",X"AF",X"C9",X"3A", + X"62",X"20",X"3D",X"32",X"62",X"20",X"28",X"25",X"FE",X"1A",X"28",X"0C",X"38",X"11",X"CD",X"4F", + X"04",X"C6",X"02",X"CD",X"3E",X"04",X"AF",X"C9",X"0E",X"0F",X"CD",X"3E",X"04",X"AF",X"C9",X"E6", + X"01",X"28",X"08",X"CD",X"4F",X"04",X"3D",X"4F",X"CD",X"3E",X"04",X"AF",X"C9",X"3A",X"63",X"20", + X"3D",X"32",X"63",X"20",X"20",X"02",X"3D",X"C9",X"3A",X"61",X"20",X"32",X"62",X"20",X"AF",X"C9", + X"3E",X"01",X"CD",X"94",X"04",X"CD",X"81",X"03",X"0E",X"0E",X"CD",X"3E",X"04",X"21",X"FF",X"00", + X"CD",X"5E",X"04",X"3E",X"40",X"32",X"64",X"20",X"AF",X"C9",X"3A",X"64",X"20",X"3D",X"32",X"64", + X"20",X"20",X"02",X"3D",X"C9",X"E6",X"07",X"20",X"08",X"CD",X"4F",X"04",X"3D",X"4F",X"CD",X"3E", + X"04",X"3A",X"64",X"20",X"E6",X"08",X"28",X"0C",X"CD",X"78",X"04",X"3E",X"F0",X"85",X"6F",X"CD", + X"5E",X"04",X"AF",X"C9",X"CD",X"78",X"04",X"3E",X"10",X"85",X"6F",X"CD",X"5E",X"04",X"AF",X"C9", + X"3E",X"00",X"CD",X"94",X"04",X"CD",X"81",X"03",X"21",X"7C",X"00",X"CD",X"5E",X"04",X"0E",X"0F", + X"CD",X"3E",X"04",X"3E",X"3F",X"32",X"65",X"20",X"AF",X"C9",X"21",X"65",X"20",X"35",X"7E",X"28", + X"24",X"FE",X"11",X"38",X"15",X"FE",X"30",X"38",X"08",X"CD",X"4F",X"04",X"3D",X"4F",X"CD",X"3E", + X"04",X"CD",X"78",X"04",X"2D",X"CD",X"5E",X"04",X"AF",X"C9",X"E6",X"02",X"0E",X"07",X"28",X"EE", + X"0E",X"0F",X"C3",X"DE",X"0B",X"3D",X"C9",X"3E",X"00",X"CD",X"94",X"04",X"CD",X"81",X"03",X"0E", + X"0D",X"CD",X"3E",X"04",X"21",X"FF",X"00",X"CD",X"5E",X"04",X"3E",X"0F",X"32",X"66",X"20",X"AF", + X"C9",X"3A",X"66",X"20",X"3D",X"32",X"66",X"20",X"28",X"02",X"AF",X"C9",X"3E",X"0F",X"32",X"66", + X"20",X"CD",X"78",X"04",X"3E",X"F0",X"85",X"D0",X"6F",X"CD",X"5E",X"04",X"AF",X"C9",X"3E",X"00", + X"CD",X"94",X"04",X"CD",X"81",X"03",X"21",X"90",X"00",X"CD",X"5E",X"04",X"0E",X"09",X"CD",X"3E", + X"04",X"3E",X"F4",X"32",X"68",X"20",X"AF",X"32",X"67",X"20",X"C9",X"21",X"67",X"20",X"35",X"7E", + X"E6",X"07",X"20",X"11",X"CD",X"78",X"04",X"3A",X"68",X"20",X"3C",X"28",X"15",X"32",X"68",X"20", + X"85",X"6F",X"CD",X"5E",X"04",X"7E",X"E6",X"08",X"0E",X"09",X"20",X"01",X"4F",X"CD",X"3E",X"04", + X"AF",X"C9",X"3D",X"C9",X"3E",X"01",X"CD",X"94",X"04",X"CD",X"81",X"03",X"21",X"D0",X"00",X"CD", + X"5E",X"04",X"3E",X"08",X"32",X"69",X"20",X"32",X"6A",X"20",X"AF",X"32",X"6B",X"20",X"C9",X"3A", + X"6A",X"20",X"3D",X"57",X"32",X"6A",X"20",X"20",X"1E",X"3A",X"69",X"20",X"32",X"6A",X"20",X"CD", + X"78",X"04",X"3A",X"6B",X"20",X"3C",X"32",X"6B",X"20",X"FE",X"4E",X"20",X"03",X"3E",X"FF",X"C9", + X"4F",X"06",X"00",X"09",X"CD",X"5E",X"04",X"7A",X"E6",X"02",X"0E",X"03",X"28",X"02",X"0E",X"0C", + X"CD",X"3E",X"04",X"AF",X"C9",X"3E",X"01",X"CD",X"94",X"04",X"CD",X"81",X"03",X"0E",X"0E",X"CD", + X"3E",X"04",X"3E",X"05",X"32",X"6D",X"20",X"21",X"04",X"00",X"CD",X"5E",X"04",X"AF",X"32",X"6C", + X"20",X"C9",X"21",X"6C",X"20",X"35",X"7E",X"28",X"16",X"FE",X"DA",X"20",X"06",X"21",X"6D",X"20", + X"35",X"20",X"E4",X"CD",X"78",X"04",X"01",X"0C",X"00",X"09",X"CD",X"5E",X"04",X"AF",X"C9",X"3D", + X"C9",X"6A",X"0D",X"91",X"0D",X"B6",X"0D",X"D7",X"0D",X"17",X"0E",X"37",X"0E",X"49",X"0E",X"5E", + X"0E",X"71",X"0E",X"3E",X"00",X"18",X"26",X"18",X"33",X"18",X"31",X"18",X"38",X"18",X"3D",X"18", + X"42",X"3E",X"01",X"18",X"18",X"18",X"25",X"18",X"23",X"18",X"2A",X"18",X"2F",X"18",X"34",X"3E", + X"02",X"18",X"0A",X"18",X"17",X"18",X"15",X"18",X"1C",X"18",X"21",X"18",X"26",X"32",X"43",X"20", + X"CD",X"3D",X"07",X"AF",X"CD",X"94",X"04",X"CD",X"81",X"03",X"AF",X"C9",X"AF",X"CD",X"94",X"04", + X"CD",X"81",X"03",X"AF",X"C9",X"DD",X"21",X"20",X"20",X"C3",X"80",X"05",X"DD",X"21",X"28",X"20", + X"C3",X"80",X"05",X"DD",X"21",X"30",X"20",X"C3",X"80",X"05",X"1F",X"0E",X"3F",X"0B",X"5F",X"09", + X"6D",X"6F",X"72",X"6D",X"6F",X"72",X"6D",X"6F",X"6F",X"71",X"74",X"6F",X"71",X"74",X"6F",X"74", + X"72",X"72",X"72",X"74",X"74",X"74",X"36",X"36",X"36",X"36",X"36",X"36",X"36",X"36",X"B6",X"A0", + X"FF",X"1F",X"0E",X"5F",X"09",X"6A",X"6B",X"6F",X"6A",X"6B",X"6F",X"6A",X"6B",X"6C",X"6D",X"71", + X"6C",X"6D",X"71",X"6C",X"6D",X"6F",X"6F",X"6F",X"70",X"70",X"70",X"32",X"32",X"32",X"32",X"32", + X"32",X"32",X"32",X"B2",X"A0",X"FF",X"1F",X"05",X"5F",X"09",X"8C",X"60",X"8C",X"60",X"6C",X"6C", + X"8E",X"60",X"8E",X"60",X"6E",X"6E",X"69",X"69",X"69",X"6A",X"6A",X"6A",X"2C",X"2C",X"2C",X"2C", + X"2C",X"2C",X"2C",X"2C",X"AC",X"A0",X"FF",X"1F",X"0E",X"3F",X"0C",X"5F",X"09",X"70",X"70",X"60", + X"70",X"90",X"71",X"71",X"60",X"71",X"91",X"93",X"91",X"70",X"71",X"70",X"71",X"90",X"71",X"73", + X"71",X"73",X"91",X"93",X"91",X"2E",X"2F",X"30",X"31",X"2F",X"30",X"31",X"32",X"30",X"31",X"32", + X"33",X"31",X"32",X"33",X"34",X"32",X"33",X"34",X"35",X"33",X"34",X"35",X"36",X"34",X"35",X"36", + X"37",X"35",X"36",X"37",X"38",X"A0",X"FF",X"1F",X"0E",X"5F",X"09",X"6C",X"6C",X"60",X"6C",X"8C", + X"6E",X"6E",X"60",X"6E",X"8E",X"90",X"8E",X"6C",X"6E",X"6C",X"6E",X"8C",X"6E",X"70",X"6E",X"70", + X"8E",X"90",X"8E",X"A0",X"A0",X"A0",X"FF",X"1F",X"08",X"5F",X"09",X"AC",X"A0",X"A0",X"80",X"87", + X"AC",X"A0",X"A0",X"80",X"87",X"A0",X"A0",X"A0",X"FF",X"1F",X"0E",X"3F",X"0B",X"5F",X"09",X"69", + X"69",X"60",X"6C",X"60",X"69",X"60",X"67",X"89",X"8C",X"6E",X"70",X"73",X"B5",X"FF",X"1F",X"08", + X"5F",X"09",X"69",X"69",X"60",X"6C",X"60",X"69",X"60",X"67",X"89",X"8C",X"6E",X"70",X"73",X"B5", + X"FF",X"1F",X"02",X"5F",X"08",X"69",X"69",X"60",X"6C",X"60",X"69",X"60",X"67",X"89",X"8C",X"6E", + X"70",X"73",X"B5",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jungler.zip b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jungler.zip new file mode 100644 index 0000000000000000000000000000000000000000..8cfd27804c2cb52aa9000dcad7bc957f12f8a019 GIT binary patch literal 13766 zcmZ{r19W7~*7rM^7!%vJZQHhO+njh}+qRQQCbn(cnmGCL-1px1dA_yodwNw@_v!ts zs$OfKbN*F(m%P+B5M%%V0stsVJs?IASNn+%0090fkN_Y61G^JF6Fn`P0idt1uiu2# zZFppL?fl}Sug}QHh}mUu=;`EiZGB?W$VmQQ?EphS02;sAnK>*`LI2-&0RL%+-OxzC zrMB+MBe$zu%y%tdkMDzF`BO@45b$sOYaD&5uta@n7Ec|JUpzbj0Q^-k7+Nd&*ek1{ zbU*s6Ke{$tk++1@Ow_cOi=7og*5AHWHZtK?#hi0U?5{f`B3s7GH~zF_j8k zlkVzMR)eNQI}To5h0-rH(35Bs7H};l%L4Mr!f|2L4K2f znw0GEplBrrO)2_u)4Ms3%ZeY&WKS2fL3n7e2t;?RP`FJKKH6h7D-?V=K=OSAAW>Oj z%}(qj4k~WIvuQ8B6AK1!z%v#qMEOGya8g;~z%Ic%Gye*;zU1PwTo zD;O!*{&3FapqWn*qasR;lmcZ`8ni%87`QzNB_$Ye^nC|}AQQiziE5s0wVZ1K6-6>k+RriA=PU)5#%{6Cj3~+omPRbZU}9vtLiG^AXKQr5z-O@l<~`Dd zPUu?&n@~p;Pgr(Stnie&c!^GO@G*sy*gZ}p!K#4@k!QbPDsFSEpr4I_u%7`%SeGpd z!HdxuaXvUT@!UIV#I#Rx)G?JR$PAAv=&5%uv6ceo9FDh`&0|8+Qz2UlNrwF`O#0^~ z0n18x)({*&t3^0|H8Iu9$i9?fy{v7OMAE}J*-5?IQi8c-N#Z&ITS+x?FI=&)o}!Rd z{+QinYgwo`MjFpk%7l*lU}!2HJg$?K1&frgkc6*J(F``!GBVBlDHQJf@Pia90)8Be zBP`dN3X+2=ll&kYDuTgu+Haw`#&q^#bt=zHYrzi-fE-K7s3B&oR97MKS^Zlei=-pL z3aAT#gSy2hI*05BziixGKN*n6&rBjT@px?#ym+jA)Hb2!Q@19bRq+cpV}iDlu4-E4 zI#2EAVn!j1Sh>;Hea&ac=YV;tcga<%s$^3MqoScFDBkF;UhwOd8`Dl?wY@TTY*u?r zpI~18BLz6lfSCNCW7vD5M!crH6a}W$nC5&La~jR?)FbY-R?2X$RHa{D+lM`pA3lIQX6UQ(y?rib!Yueo-Hc3eR1(AMcvF;@^U3=%O5 zVAoRhxecV5vY9EP=MaKNAEIBZUSxi8&SOx1XA7AM8H3V<@`S1!RwH~RGKzK(O=B2& z3S<~awcs`xXZ*koAL{`kS*BWp=rbLMpf1|b8DAF}e?+ZAA5I*P2r?be8gHisa%6vS z{3hJ|>X13X9Em?v&H5XII8j~Gp%SEKS7;WQjKt8W?KmoGO#B+gS;@UcaK?thDTRJZ zx0f>Ij#o-!iQyW@)?5Om_s3*mc&3Jw<#()KT+u7yf`OVV^tn)WNAR1{&irjD%0yv5 zncOg}+;W1s`0BzKf(p=ATTKJC+b{XrX}dHZ)i}HVM;pM5zTPqELgWU_&Y^OjVnhjh92v zhkt`a=zE~jMk_#W3f)v8KtC}wr83Z`(lDuDDr0?zBU3bi9f&N8P*fKrU}zUSf|4fx zY^1JG1EqTO_{dkeCiFt7E!*DDHe;|a`BV{^%V7`P6yxxWWfpHBm%HoiFNxiYxLYc8 ztR~IL-meZ2sWiE?Tpqwg{g%MdYgJ>KB&%UXlV~NOSC&r^y#u+axwrti0}gjINxj#H zvp(Eib4RxG7Am{@20M`Bx^z=iX~ZDkuUJ^Vn|LU`!tqA)%?TY-1{-dzZk&q#5%jRy zto97HbJi2}+gMsGZUUBV%Kgbsacu#d%=#K&21{5^P8q|JKvdtXUqrP7%i|;(zEc6D z&kMZ5pQ{K?*6S&e&j+MqX1n01HREZM^@fRDPD_R4B%-{>^KB0)jbdaz(=Q_=D+M~V z3tM)BoChJG=q{0dHBU}~> zE)9jAfzQ>Pl=)Bte3;+zumb?VMHK_P5iaX;^m8OMcIL}`Tf1h8rsj!<5#yu z<@12F-2uHw=-Jzy{yngWoT!!j`YD~e5Vrx_J4i&$(%VExB5+|GM1h2efJVHbOfB<+ zR77z7re(0)$nOyTj-;Uc!CF_kn>a&5yA4w?v5M`&a1pWsN9~i9F4zbQEfhFKpu4De zj|Inpe+cl&H6c-tSJ?aEd(Zpw{a`J0g`6XYR^}Q=Eja1L885h1lMdMDS;oEn+3Bx6 zIN23!>{IK1q?HT8fw|x~E{WH#+iD(SXJDas2259lTXP^TeD>q3F?9>da$QCAI!gD| z?jM1`7-oAqxca^)?w!f*bUxPvw04Z@AG*aabvs&na`DA?g|9dYI{Cg%nAX5mwxt~C z;3chHxWZZa8f%<7@aAa9b#_!cU0tgg4;)3*ploR?*E#gl!|Xv|3#{-Hxr6-7y_HIm z9YWv^6y1Tq2oQ-##KsqaP?&k{y1{{g@^=>N%*i>kW_{)Nns|p@Kjh`ap?Tev2g-SE zKO}jI-y?SNjs%;;Gxgwwp9GiP%u3sE`{b7ncFlRSN;0LK7Fy$eyS=nX^8EGZqy(Dj z`m*2>5fw+Y^{Q7^$cEeFiNr5x%j5V>kgtl5{^|SqB~b* zHhC`Ex>Y+;U2=cPsnEoo)2@@XeH2mQT$L&F38Z39yS10FLo^OZ8Z zlSV>4|G1e^@z|uGxVXB#Fgd(of{rNf6;>}G*kWY*I{HF-c6tVJc6wbCs%;U;1nHaqqaO{_V%#DP;E}%*XOr#s2 ze_TK|6LCE@d-U)k-Te5C2qL=M8(%j1rU>$j++&9Pu%-mx$c2sJ@u2yNIBCGGfdZ;$sxK zh|4Sj$SCo-W|?r0Y%arI8?7Fn$+%iZRtAG+j>(?|ZjT&&;zLeb+)R(uFsxuUNeugR zmseMxUSPQpy;zSFf%cDT!X4q=gri8Wd;zs*xgSDsy>Rb8drw9myYh(w;NL6GL%iBT zb85VhbwdI`1l>_Q5q$ynl$o9zT~ME?ekIFP?cmQpBMNq<5WQ8osj@#Q{jhJZuIc?) zF;wt_6W+N1ULU%Dt^zKVZpqf)Q5=-~#l4cdJE#1FV(;&9&b`R!EcKLtD|l`~m-~Kz$Wf zCME_N23iJsgN8U(wia+83okEdd=qd(s{oPnDu2Mg@xSiC9lx5$TNE+}7{9Qu+5W$9 zc19-#MvgDstSMRm3V;vOC;jnhep1ZkRR_PAB&b$6@PNCaO)p(y=%fWdh}3kV2RT=k z+P?M2V{Pm2TfMm&ED=i8qL$6SXYpWP9ay^9nmIE3QiHZe7D3-!y7-lRW)pew5YgTj zfNN;6f}7I5xL19DE_BRt01ruCF2F$Cm5+)%Sxz%xE+rjtnNA9xuganxwMw3@$swez zKWix;RcyJSigFWf*uVKawHdTn&Oqw<>%#Z$>T_y*(tGQ3>S4s~N^(3c&9d9UJtkYS z=#m@13Mad)gfq1IS{o{q=1P+7`_zJxTNm^nru+G0v7s*M9!r=y@WA0ilTJv^^j6r2U98<`JqQbvfnlq>?LCNO|z)LK7f`Y1K8hLVEt-|yUmIr zs~V&Y<+D(1vMQxICiM~nuVb|Z*naY%UAcqE5?mg^#cc+6glo06JpnazLs_A)F)w65w}6q7krJx-O*7l-oJ1@UN-;|G>q8#8s}aEl0Rsp@D)2+_z}hRFlG!LV~R0 zZ|L+RipB33zHLvx_@UazTBS$}f}D>M+T*N6iNWLAMsg)Jsjc14LjxQXaBsS!QKrnn zABkzwEcCzZM9NDrBi z(yr}B$elf;53da(;5_cwvg#+Susc8pYLU~b4IPALVxcQQtY;J0O6_vyGjE=haMR1Kz8N$Wh}iKM`|Xm z5L13H-$Cs;CD7tNEHS42t{xzg$Ffcew;PPL`b5IEv-l?@0*TcNm$G2s{c(G04AMOd zz}+jLMp!f>OK9GOUPDdlFh%F=6FNoR+k(8KB+@!jRGXezvXg=e&f42dV1YV}T%+ZG zMEl#Q$lZ*h>(ILM%Gx^V+5~ZPZ^veL;$qokx5`kBi5gB~HU2e3@K6F|BI76_VEhh}^8uVpF}N+MO6X48bkqgJ$mb z3x?V#zfsV(iJ(!wgP84-$yaa&vfB`g%H7ZXU_*}XPYw4yyoLmv3-fuoM?&L9-!l=t zpKpUW7?J{ZdZ4WDFwR1y{GElH^v5ufC52e4{P?Kb_lczJj=**BdgK}8_@3ts!sDHb z20EbFuEXUf2{}jl-KX%^PEn9^orOBL#&)-c(KtugVe(Zq&k3a@B>TCHo{|+q6z*;Z zCysS}$&)`9%>y1%&yWyN2!2l34_q3sc(K zi>jfTTgV2E4~)q1H=nfKfy6x+x&a;DrGMEEE9g1LwvV0X<2#k8>O94JL`#l zbFMp}kk_|XGES}&znl{sDJM!Lb*L^EG(aZf!}nDwJpX_W-{~uH`4~fE;Z+<5El`lkZ{;3_K0X z$(L^$TpP@tmF-Ur80Dnf8~tID#V7B9z<(zk1x)^PGKbG}m3*muv-A6tusam2#je=u zO^Rqw!N50!eZ09|XxvZBBZ{R;1Uwc>&N9OzqgwZb?%G)SVwE;c5j?BTZ9P~Qv`zAn zl(mKmaN1Z?M|3-)O0pl==Lpx9Es7Pc@Qb%ukJT>D+jyf%mPuOyOHh*HF6X}$2sX0# z%d-Yx0{xFi(BpSoJ*L?Ma1%ktQ#_X_Lr(KFuYi@Sa3lKnNy?YNuoM(69+haFD%A|% zNFozSD7Qd^jKQ63d9(J34&JqEcF_qx_9OnW!q?lSK@-5b*Xir2LYh_8&&F9{`ID23_2BHd z{36c(wI?ql24^D`PLId!l5hn#kv~i!DUV9(2_YBO5?Q85bQeg=Fq=ogRL;7dtXHr) z#bW1}swekQqKCV{e6SaTZPGj~0Q-n59UF`!+)tBH7IrYeh%^)K^A?`zqVP7wqvkYc z|JQjP(q$V+Gut&8hqd=d&Qa|~!w2sV6U0=t=agrvgamw8{0VW*a75J0G@mS84Kfv3 zA{k=AIUoIj2CarZ1M7)`m?4~oyVcw539N|<2i=p-p69?jo}(ez?qzCSstwB&13`5XNihI$*WB^N8^jX zk*!wjr)gE}=j`Z0JnC&`X z<|o>ozWQ5`0n}lM_HNSFk^Yj1UtyL16=aNAYF_q8BIsLVdx#2a9rL000&Oo^u~3SnozQGqmYxzn*788E|_N;H!BWN zz2+6)mE@6&p(Hkb5hnu26u4bnK3+V&`#yGT{MwixlE(|6Ko^iOpNThszhh4@pj?m| z7)nmhH*EO${k%&$G)Z)b95XOLHJGd_0^aQa;~FMI>kH9Mp5r$8OlpCO|yiLc2;wMU>Ne%-=x`ng~TFQlg$|93UO@7T*co$(SW|qt8 zRI-+xE$FfoRw`yIHB;)5`;nWKIxWPuOZt381{NuzB{S+Zo`qLR_RAU;IGYq~l-Md* zMxlySR!U*W`KVkM3KmPL=2cw^R>_FkM05%Dh&%QjEYwdEV&@5I;ye!?91}X#|BT2! z$KEH+Q&pv;7Y@v-K67{^VaFehnhpDj>xpX>9Tlo5imy_)j6^$TacfN`JWAw8wDjg#>2oSJat z?&^%1`QSE9>!HUGE)@}`UN31}eth51Er zw1xRlV5u9FnbOsE{l37Wm9uo!^6DK+>``5Pj;7k3h}HJrNolObfLArvU|=;<{IN=9 za(fs0#!`ZWta z$+-A{TR85N&tv~&u8{S>PImel#*AHGRB}}Qc55Jw57E%mkjnGor-k zGKo6ATDro7SDifiuJ9DAtcwz&qTuSA=xB&q@9p$F9hJjwpSS6j<_?uy_&Rpo%s?@o ziS#E{lAUwD4Er+>Ov71rShI{9F{DNOz^cIBCNZgA@E9q08f*ayWDn>3&j@Zi4-v6o zu=K$b8Z-TLg5YA=fdh=%n49oU4Ed|CYS;w`0c+5yEr^?2trrYsg#3m?FgiBQki#1^ z=KgdY#O5_fZc)|dY_7S-s*oC1#=&XoQKRKnbkNodYn;s`KDQIBL}qc3+%q%z>dz6Z z(mxx{%rpe@n(fDP_)$Coa~7+Q>I#3Zo(T^DQB}}Sw!g_|9`5R}3Ik(V%^maqiSNNJz$a zYJsW$-%b8$AwZ7GaV@&(O`Q$d%bL%k00Vuc5jj5 zWudv&^_ctw_&6YBq=FBpYDTmpPfvx?BBRTl>(K2J$Bn*U{h(7o3Wo#MHuE$H9@ zLh-m4#M=Z1gS3MIc?jMgErzGCH%wu$fQO86ZcaERQwz^`%m|eO{LV{oOBoT3TGQI! z8hfy3HQ70Vv$~s8tQCVK17inQ+flI4Xuh%+mPBaBxM3+8x|==D8VnK%P|OUlU;-Q> z11QwPf+cB4)nkXKQxP-_z_WG~w9+LZ9*KJ4GGcvQ%dYtcEd*X{ih6^>#NExyK^Q%5 z_uhiU{cK|FQ}PaYg~n`!r0zjz$b`1+a#OI5yE*Z7(j80aE%8wf6(jf-#zB<~NQ>N+CZrFJpQ!D(IF2fDafW_z_5+uZXMQ|4 zT$!D-$S$N1@4SkCI)DucRk#wUEe37r+}~Nnc3lAfO!GquNB(5q?TDL9ZX17jf+1*m zYVQTkB0wKToW=+Qhv-?Q?$HX~#^~?nmWb72)=7b4HA3`}zIHGl`;A9@?V|Ct2J%6@ z%O>6HB&8!4;p|5wzA5_bWh>qIng6(kU-9+MXB!U@dN+jE6Xh za7CUxU*c)&DYWYrKBU?ePd=8vZOO*u&GLe9l1d zMZw~2Sp_Q(8e|T&n^697y|0>z9MgUS0;i8egoF&32LT|Vs0__*dU0Pk60dVgtobCm zwh44#&uzZ4{Vf{_zhvX;w{af!uW-%(CmWffQ_L!7<&lS=X$EN6XV_a?DZkfVVu@t3 zBR)#5d)Xm*$7r@FAhqa{U!o&MbCLQgIOL%?h(?nNzvDAhqenA&9G}q4z3(*n9KB6( zd~V`hfX+HJ6{%+mC?7cvj8?*QpL7#zcul0UD9C0?7+x5%G&y1{E+3rYyc=9)Y&n|1pfV`mnShroAx+q5ECRw`FXx>m>wWVy#5Lpu_ zijV=Ck(zcl%o0E}#|U?V@CrAF3cjdh|Dm523Xb<86DL&Oyc6LMhCjI8k6d?1o z0iUGF0ND*HBPyrMK?#n%@GV8r_NQ7R44G4bjBYkXfH7f6 zO%t-V;wZ(vgbM0Q5qI2E+~IKPwoKtK`PCth!=KjNtq!1LYV028DBOD@q=mD_O}r+R zqM#435*Le4g(e@M6{f!;2(mq#){T~gvq$dPb-40PUUHM&@gUd8EcU?qTJu(0zt#uH zK3ShEQucY7M4h*$$(A>$ELKt(JK+Oe#&I zCRpVmmWxQYVu`(iOv~z^^u(%kj`3-lWT{20{8D=%VUql-vfz7A@TNa)nKa40Y-#W& zl=$(lf=YlZW4kO zotf1E-{R=1)}&uiP>?*BG6J!o+rP`;-*Ui6d@TS3?DUO5J`DrUq^*>YdYKA%KS|7) zH7>fN7eTAef3vp3ni4vg4M;;{5)~{W@Ogo$A+$+ z%)mG}j*-!b_JO00)a_3O&m2=dl9&5n?KABOpG#YQA&@dKw26;33Bl7y zEwx=d>!2#}B`jwr)GAuyEXdoCeu}a|09299r4=u9g_lK;B{ZtmfcqNiJUt}_`w=V9 zF-QMO3cnGGG<9u5E0MZ-mKk~X)ZQzsbqP;BdyM;L&!j)P>K5i6UV7hU*kx?;AIf3m z*#3z^ly4aajKEl@EH@wuMYr^hHTF`0nkzCBS##WOutY@A9We}sQZ)MqH)Jw)PkjC@axH`NKu9mkyQo%7kx^m8}-?VFtN&|EIU0Fy|c)6d;Dv71z&DOH>)D4eM> zZtmQr#{j=y?+2B3q#a!%^R}bYrmP!vGLz(WNqyYEI%TaZ??@eBNZiRqM$N@TFuCCm zU?=m8C2mhD+4|5;6mCyS+1}~8Y^*C@q!QTzQv;GxWyrG-_=C@Mjj6m~2r*DW>0TsP zRe?LcX(k)RO$E$wa0k9pz-(-&y0e%Eu59?pH>_$Yz@!5kxd2= zlRkqQQ755~6JwHy_5!K4gfyBaHOF?t64G(wq97rq^^af0^bj*JB&BM=;Hj~c&?cwu zirRs}kcuDITB^2qUIVIQrfdSe;`dPQ1*boW#gcsEdaD}IFkh*Lnb-(M^fyWnDm{cqtxMUOap$86 zBkeYD*oV7Eo6}Z@*(J|a*HA`h?-pVmQ zvR{r?*G|-Y+kp^A+s7FjNXslM(QZ)?)Yv)VpqBGa`sFFohGg>^75xRZoJ0u*>8_)% z;(&%EBh9$#KCvB~C)$%H*Sx=3srJ5Nmbp;6Kcy#vl8xbNm;N+rr$5E_iW--BE`F$( znMW=8GQ_E0tfBRfo%DxwEBdV*Cv~olc0FA9XhIg@co$t$zec!wWuaH?M06=u9SJLl zpHXGdt7=Q~1sg;Xsx+}!gd*kBt>?b0|E?ELboB=dqGgY0G*h3sG~o1U?A2%(D(a+{ zm@($`ORCm6&1AX3o7!I3cBoa#**n#v$2OU%(=3b zJc)-3&NYxlt#O|AS{n62a@Oe1CJ0$5tO=AF>~~j{`8K@fR`0AoN>JjHEd6` zckFZBBnkH59&Aj6cf4~t8mrJEKg=$pkK)GncCn_gL6qa`Mh@yE*jWcXz=^Em?ujo8 zxUSD&bq_9o*Rajuy#Z+XP1-Tku6;&ay9N|)fiYuajX!Z?Pc~=Epy)&4^!+O#pZogFnf6t&b4d$?Vl&l zyD-B=4~~IM1e%bNP=+Y^;}nZQuuN&bPdp!3zawvjrc%Nl$cp#1wHoi?O4442F-LKc zbKKCNE|^2ip6nr-{}f z?xDt5a~UWaj~~apG;s00oU*pLZr>(wOMkD?o}C$q5;iq7#5Tq>9Vw`0<7*n*zGslFfn5D?L}sH<^9f2^P&9qp9J-8wZgZ?RDm$O{$6C>5(x@`zjs+V|yT zjs};1rhMM&eT;3z9d91%@)Qq!KlyQgd$<3baP%mv8ul`w06-(G1e3zcHSqg|KxQ$ufFmxW$ul-3_@Hu$436 z1)Sw7MRo>D6_>YVwMeRwI4DUki$CeHPwFy1vGuR8fPKnm9#AaJ%WI=lLGAn3Lz%4_ z$htiA7||Yy5v=2K6J@TbpjC!s8}q&4>!9uTC>y}*ON*41WZYu>JxQJa+HunQNHnYZ z^&I&tjRpFvayGPQWOibpr{ypXne2fDR)F9az%Q*P?EbXPTK13S`1MV=KU_S*RDCiW zCO#hnwJNaCJXGWipCa90hV-xVjj(^6zG#t{frl%&77|BUOuWgq>A0|4&6xW99e{>lBf+@ilZnJ*>rKbc1VWd2+D>u+Wg z7UGh(=>lG4%GiiOM(6+mjEzd OFSoA*S`MbazWqNkJsueV literal 0 HcmV?d00001 diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/make_jungler_proms.bat b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/make_jungler_proms.bat new file mode 100644 index 00000000..b93d9228 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/make_jungler_proms.bat @@ -0,0 +1,15 @@ +copy /B jungr1 + jungr2 + jungr3 + jungr4 JUNGLER.ROM +make_vhdl_prom JUNGLER.ROM jng_prg_rom.vhd + +copy /B 5k + 5m gfx1.bin +make_vhdl_prom gfx1.bin jng_chr_rom.vhd + +make_vhdl_prom 82s129.10g jng_dot_rom.vhd + +make_vhdl_prom 1b jng_snd_rom.vhd + + + +make_vhdl_prom 18s030.8b jng_pal_rom.vhd +make_vhdl_prom tbp24s10.9d jng_col_rom.vhd + diff --git a/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/make_vhdl_prom.exe b/Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/make_vhdl_prom.exe new file mode 100644 index 0000000000000000000000000000000000000000..1e5618bf9417eaeb90556e3021a78e9860a815e8 GIT binary patch literal 119861 zcmeFa34D~*^*4T>XXcqD3p0TP!#R;I3im94{WDd))P*nEKjw;3-)UlQLkgOB&vHgLsaCW=mlXa{` zB=P6lm;e@v{KDCr72jJL2<`Y#zVq?1{Yk!c9UVkEOl{aj(9wTgqPA~#laeRfnks`n z77K^+LSEnO;;I^=ZlJFn_)xxu_}KmmMPc9UShLJGMD(5b5Z`h_l7EHBcMg}ipW^%Q zq578KWBWt9ET2=bSW@2Gj-Vf(ui+zwOS1eb6#nIN<`qcz!BGg>(Kwk1-;yNjOY+TM zAn_-%5cGm?G{Pemiv%R!f|Dier}o$hzBGg*sL_*usPFPQC+ADToEq}F!Xz}UXelia|q(bTM{vTLqWVGH!yJ9BqINk@a{c}cH89T z74$V;w(Qz>1_#T}-fO%84jNW_C9i^ZTeK$`imi_u7XwZhPvd)AUo7+xP1u2D$R)J* z(LwwTya^SP$oenDhfto)GWazG31j=^D2#vL8ovPcVhLk79{;vBm#iXp*FN^sSHO7J8l7z;{oQO)Wz z*Hnitd%G7gC5Z{IwNko=(t(9~YH|a?ZTmyBhZ4)&ml5@l7bM@-g-H6)0H*ffOQHB-nQAvuAx-BS z1@9+}?*r*RqWQK?24ljw9q6_`-_|g&y~eLwRF5T$D^0f1h}iaiX9|_zN@FvLN*F(! zB_+nvf(3mKgFzHLIoLn&5&8g)vL_XpXI;<*ByLPcB?s<+h8svffnu{ZE+hJ*gINbJ z1%R4(k)-aQXrTUqhrv>k$l8rk1h+jOYe7zTLQKJvp@cY;w)Oc~{?;dBflzm!=6k^3 z^Yoff`le&x8LUS_@yF5WgQ3KNClGnb=>_{6lk+E$_WHmN zz*N#xtCiQkRTh79;1-#tc_ik-qGw6%oxb&G&J;tB&pU4zryMz=v zpF#a zgeDCQkZo_EQy#)36a%l0qu3Z?WyGHmLG!66>!Ac>_oUx}VBlw9+H0H+CK?b2_kk%C z|K(to_Yz=p2?0j`*Vkmjdop<$-?6+iU#jLgs40V{~BG z$CyaHa(3gJ;;%zI{SA~;{4KWl)uH(B!BZJ8_lM%Evj@_^(0#Grff1AlW``2~P>$^<-^f{*4q9 z4<3Nf10v=|(gRN@2}Qf8LmsBuk+9Xo$b!!R91p%mXwfcWu(;+BSC0``Ld>fNO5?vQ z+BJe0sK-dm>tiH?&(1K<&hRs0uqy6Bo1P$fgAlflB)oPE32wWDFDZui7u(8!Ig%{H z*IGS#SU@Kq&s$Lo-1i2r7ZQ>;i|>XFM1V4Na3F^EiU!!uLRM zzwd#4XvmAW5?s)!;OP#2tRZ86r<+R@>Iv@0I5{lG36;%i6c^Y-@_|zY9gp_AeG#=1 z_rQ<>B}f7G7$fZ^rnRmm>jK4a#4ce-50ol~emlbu33-ZPkDXyiE4vj#pPhjo!d4mn z04;(-4#|QxKo-N}is2!%9>lb1p&Zhk2KbSRO2kX8}T(D>;-f~N`=p|On* zc~JC$pJzd0B7Gk*+(!(F^gV#pLUlU`Wj!Uid2)RfioZhSyn*XwnzGzLD875(3Yn-3 zJaOZ4lF|u+lnufbA~X|w{AIL!{yDoLWH9Sgszw|z6O+%Yft4f^!c{U0;^ejRUg%6FJd>2CE9-9*54wr?B5Pd zw*)%+U_U6TLOUhb!JiXB7V&mP_&x~ceBt$Z_uGMiGtdg?;Dpg$Pj%nlISRcQu$E7% zd{|K*#Ny|@`LviR1|xOlz!gvirSU%5`sHAG0vdEVBFo}^56RVh&w?K}&|Yim+j513 zRr;^7<`2a`D4p@z4+8)T1`nM~{fmS>;C#aQiMJ%4`(dIoExuYfD)A(BeiG{5tA%E~ z91nWptDT|l$Fb-g48$gc;{O=P!upn0`+cEpgPkYJavVGrjo15d0Oc#inC(gb;W}EP ze<#NJ;owBX$3HyuTiPI6^HJ)HMWI9n=3qjPKYH1l;0j#!kK*E$0pHfEAxsYCjVpN| z7NGvVEB{Dz8jP_^)j*tMwlC)Y803qx`L^cM;KqE!{_&jip%LVGmNVikxd1h1#E}f} z$)^VyMo9NOq-H|@E))hcjneb@et)?WtJV!5tMOsykn(B##}4|g#QacWKlYj&_r7g) zNMw%vZB~{~gHM)rIil6LACj#a{I|%#@7p#($&jO~$dd6LQ^qIe&>I{gqu~96ek7FT zljHrTJl>xJ|G~wGO3shIgK2hLK5^6}_$78;+uoNI_HF$mQp$O7Ax46n2fqfTu~+fS z`Tb4sOYVaYBZ~F4ikIcT%!=QRc-CQ1$7|7t@2NhFofwMOKx-y$$n8QM-}PnGGAhNg6`zY8&CsA17AY&q1*VxV;d3Z97J z@%49t5F3iWS{gq*@MoX{hw;@b%{$5VD_U)}@LFghndeJo@h3V*Q-7$|DLOB?UPz=b zslzaO(s%VgkSlsR2WYV1t>pZL?pge+Xl7ZW&>u_`ddjrNfcq}*276KW9u1q4?4rfb zbiRn0JuneZ6igm$pnY3^2nKABD|&JpN*{g8Q6B$&nPb-DwWN)L{-V7>M57L`Aw^A=KnmC<$75 zU^ylM3NZ=^6RV+r)2~Iuszgb^GccXzhmueG&7vAI@pQjkTauXiT9`KGZ^cqWJ&^-w z?xJ(g+r8I#3{@~iDH1rpm zu_uJ#6Tr&kN|0dR!7~8r(S6C+@SW<9;bP7kNWe~a!*GRP|jQhb>)>Dq%=;~deMEQ=Agfn~ar9*eaB6M&LRpa^2sc4cn0n7d@Nu-k9 zW7||@RFWum2Jv9omJK9P?ZIl+w+&}ZXw%(kvfi7h4||q<@ao`T=})OK!ALET7=^T+ zBHsgjA?-snLiZ6^TT)_cH%;z7;_+?mr)KX-_ajsA^oRBai6RE(z|hcr1kb_Cfnj8I zzFIotmt_ubS-czrcXfZ!F1bA23^p!8^tyvPQHB!VgIduCeWDACsVSwG?W2N}&gd`K z_LaqhoK&YAmLch(-7@M?Dij3A4s5DLsXD)>a*)GlG_ifHBq4=jJr{en+PL>i!bn16tAheO<9TD1Q)=?1%0`rD9K^LcVRJ#}4M>E997veV%NFTW3*E6{CfU zJ&8)szzm2)>pTqdzy!dy)h_A3#>*C$pB;1m4a?OMB&z^okOE#>n zH}skDMTmd2pbt${m$)fH7?F&66-t5zR(z?oe%J$_o_9jAU*pikm z?%(8bgrJ$8il#yX<&`bo*ZEdK-`{qtnHVU5RrR?6H<1Zo$M;~R%lBX?69aY$vhMy942b7?vN21q3-x??cithNn(ye>ywKv0 zV$)S$hvM&&-fKlhSbhCgZ4PM7XxiJTAhcm%njk%asr)nwR7VAR2BQN7LPqIlP)Xvi zhGsk^`47HHT1KvZ1GM(vit$0!c^ey>^r@7#7Yqf@BlW0Iy-`7_d$Q6H_#Uj$U2*Kz zurajd_t%$@=3FyPB`o9PWE$gTM1-_`s6KT-Vdl0cV{_5|eccDq{566aAr2MvSRU+u z?=PPofc19U{+KV+eF$^^F*L_xodX5Whh&Z@>X7v$m$#GhJ^=MX%&-VME9TayFT=8bT#(IUpaI&%nXBB zD>ujj;VH8iMe}V_3m#H~i%+C|Lzv>@#&|>?454^D>-Ya|$o5^@Cs4hg(54m^RMc<+ z>;?(rTSVx=S^`UmP(15KLeZ(elY?~l{sRk4!vU)x_WkkQv6&cbBhg8Jbz!*^e|a$T z33Ni|`zYBp)J(Fu55^9w^)yCK&w{<+Jmi-8C%(IOSQ~(fRJ7`xC|mYiX{= zT%@21@tj=)oRsRJtyCpz^;8&2OqfHZ+%@-(H)h>>5}>_!3WE_=k=?NqLLdAp6rV7G zIJ);(%TCx&u&@}+%20XHsY0OJzt**o3O%Fb5Bom!ZW5vu-2uw!YH%qrR>hQQ0~v*q8{x#JJ$=h}vuX?HnPzPSLm5_%k4C zY*gc2favF^u_q73gM9$|6}WFOYl>{6^h-e)%vu0sFzd<)7R4k)j@As&1`az&0+xz# z<9k$u9tkc7cyKeCQjSn_{-f#z=aQV0AqQ12143GC9#%BZNYa932znE#bcFW!;ENcX zBSPE$3|)uEUMPN$M)5g*G7Dg>Vw6&np7htL4m{uGhSt(I3F8jL73`1yA`~ZCsiszf zVt6IOvNER3?~NsmzwpLL@Qg8sp*y@)*L0igal$bj7|6#zuK94==4O!;#Xrc zV5Y;e4b^?J^Djv9{@IkI21%0QwvsrM@C<(_Ug;nB64o!^d`5Df2+l(9)6CX8A@FavaAN~gyF?=`-FZ~7a| z+E5RPk6}GvERp=N=~B{OV>(bd!szKo@nco|O#^?0IzMy`WaWV}m~{zBcxqrjQLkrh z*4ukVWoQ}Q&!HKb9UT+8?4ZQDy&^PALNa#KA44;6#^)7l&l;-!=m~3*I*n4^B zUi18E*cg}O9{!E-7P{v*fL{6i8wXzL`$n|j<=?*2_sW~EP52ce-Z;?pRxsxK%`30` z<2UE#9)8#72j}kJy!^^vZRkbM{^k|@OUBDG4^CZ(di3@VPCb>wH5`sW9}xW$#z!-5 z#;+L0e+A=DaCj4k&vCes!$uBYHS1 z%JQCId==x5FmB5IOP$K+bq+TU3%||yaK078_*OAKdRTZW<7+rP|2W|#On*-V(M^tFBc5u@A`_ucXX>z=X7RZ zFB{R!hou?+EI*q}{6FFU-4+OUL}KBl){S+|O%37pI^5fg#3Iq~hPu{<=15eC>MgCY zy3K(lfvFvV#-`>7cvaZe8A}n-bpp3Mr^fU%?Cgk0cy>puA>7=yzNtQ3P_S_R?7HUWnZz@@wX-D>1r_l`T$++1BCWBe*cQsU z36k5}qOm|;ityGqUl>4vP>_HnjIxk_-nxc{=gy|x6}8qLyrV_VvB@f9@O zh^>o8>$c?O2as`KYQqd-vr2x9ypWN%qiKC>T{8&?Qwf(yQA?Hu@}(PQC?KKYDO}eird*-7o`r*t1exMIQdtxF%oTTZrc=y*0rvWn8_>F1gln* zRh&6PRMtgfO=zg*wvGF8{Z zQOCvF+5#Od7>?9+bdfpIj!0A|(h$g7y{g14#p>1zTQRUy@npHfEp=$}Xf$tzoI0ra z)Q-HV>t_b0uAdPIR3}tB+yvb)QkbQM74JjItpDMnA#rLP}dP?Z3{HD)UA)q>cFsUYHJmNz?!CLth289 zjLrzABPB-J8_@@t4C}VUA{d>q0Cl&LqFP-bomr>$j!0)i8>-&iR$oUlX{g8A>f4$F z=$j5AOl_F0O7rRI)-_>{HC+_3^S6i&u~F2EsDR=S&>Q&opTGZ$Er7MGh7aB8_9I-2 zj}ve$!b>x7{TOf;!h5l)%mlm>;Vf69X*93ekkm zmjSmU?7-(MfV&W0h0j+3_aeLjpI*Q_5Ppkrz&jD1Jx+*Q0M{an;j;s97sBibLfj2F zfG`Jk@|}S55iSnkJP&Xo!b|aahWHVF6`vOX_abbbEX2!z+Yxr)GeA5D-^Ax_z=si@ zorCMyfNK#pOhY?-5&Q^m!zTcE2g1Ynp8}Y|4tz=g zcOm=^K4pM+BK#Pi8sdSbx*DHaz`Y31IuUsSu0>dn&t|~w2=Bt@%Yb(x^uzG56)=S} z@#zJekMIaSHvkqhh4=`cZxIZOYzsd318zt74nBJTA4d4q*=QfYy$GknuKgPE|L5<2 zd<$r(q2|owa4MPPOG%#<8lbsay?(GRWfB+s66yBbYWC!`Bs@sJjEqa<|a#~k&JaL zgUWaZrzgIsjgMs7dDGk??G8`AyVliiR66_ge#ED{x1~GMf8@>g)VkYUeX^`(dE8Fn zp6kfhYqfS+wz_Z z7%p=-Zsx)Ak=1ekPU%fXwci5$bRG2kwMkm$t$6?G`Xp|L%5G3t1BYMcu$RMcbNEvZ zpW*NThwpOeyiv)S$l+`bzrf)-4x=1?mBTwYe1OA#4&UNX#|0$%OW|-Lhch`0ada7{8puUJiF~_+1Vk=I|*FU*qsFhaYn2xmigb$>Deo^Ek}sa0!Pc9F}pohQsqY zY~-+=!_6FC&f!%YUdQ2f4)5UbUJmc)@DUF8ariukuW|SX4i9tqA%|vr{bwAgmiYhs zICx2vM4DkfD8?=hJFwBYjz2M=VI2N~{A3FK=t;Y>tGa{h~;S)kGuVyipP&N|fpt_KltGrLB!^ zMItUKTRLKqmKyA^iaJ(clSGiXlVWO`>MtyA!|qFn5A@Pj)D6axi;k*gsiQ1XxA7>l zsBo0E)isnUd&rr%V&#xqu}bV~+oCPBPnE)9Z281d6>CO0S9G?@&09^~y5@)&Bx-S8 zJ6Rcu+t84BPt@fEt*ou>!p?S+8BHABB1AgH@Ro0N>!zkwwA0s|)sfihR%O#^2yU*A zw9`HgwM4Iodz{tHkx09E&{-3SwluZY#Uf^Bh)0|?%^hfhHFeFM5%IM1xI)B1CufSZ zWDI$t3YpPZf%xs_AFR-UHP^SbZj|v@B?Bj8R$Y60n2aw%tWy-2p3u&6H;&#H;kx>k zhUQkW1yD-|Y$TMeNQiK~g8nGNjr5i>mgAZfjYew0E1R%d)n6zU>R~SF>w37eRnorg zs9Oi)l(^r4K@W-$KXKGY==GgP97<-Nqp=V`cJ%vrCyNtv zoyvA3#0qCeEZU6BL@7b7^)2n9k|6xYuFSd7ECQ)7S_k}J_?#ZBS`{ptH+MF=oU+YC zp8sy2mX3|}(U@66D&_zDKfk~5n3b$$de^XX0*jgH{bP=u-s1ZY@Nd}yMLSi$m2h}& zm%sg;nV%qkIxI|z z-_#>1pUVGKfyv*?`X%#I`4^sS^6zB+J)g?|O{@&LJmU%_r+fkA7->}br>-&i3j>OO zCT-x4@u&FzagNE~KDkhGIgY_gB*ouzp2^?E{BM1F`(I%4w@)jSk`Epy10{dbmrefK z6BYk)*tt9hEdF-p|EbL7=r1LI;^n6N{F9XYr$4oQ=EK6E+F#64{L}TLWfMiok8L;k z+vh0$3y;nIAL?gpffsYF`LC^9wK`B7m_K{r?72dlJ$sJzAG-o|2sI1qqB;DDY>wax z$DDPYP0bDJyJ1d}aqjH=*##WAdC|h~!ufQFHA^zgn>z>VR~s`V!h)?j_MJ=>QayCd zRllJwDs+z<`-Am3Cy!vOEp?t&1W>1Yp3`y)Cn)E9Zb56!IS1cb-q^pH0Q zZ@9Q(RZVbhjp%pkUvXW8^0_JtLT%U`>v5My<^;-IMY)P89#`c&MM*Hl@2Z@yC|_kt zwySc1qVzB&;Hq4xC|5Hj&&69_ZiZ`Is)6!d<(rE;Ffw|XFyB=jSznAAUhBG1HsK;7 zlz?y@6P6Gm2*UMDIE4r+K)8VkrxIZ$2sbjJkOnkI2>n(@D}l}x`gTUw0-Y!H+Ze3{x=`p}V{`-1lZF0uM%!Igb(@9$4MsP+s_KE> zE>TBLm*%Q!0KS9quK-^M{F{vT0`F)S`W=klLh-=wWPAt3Hwpb)jNc8s0r*{v?*zU` z=-*~^7tqB*{|=*lKnqaqyBXg{IO=^5EiMBNheIKXZ;dPZn z)^)D8BA(=kyS*+lA1%k-g8B_LZ8FQJIBussZUydP$k?Yjc9)8^rY|RchNJt2MO*2g zWrlrTk$Pt7s^t|GWx^RD4U@Y3teT*3ezA<;Gf7D}qol4h?xJDNWr_dX98iYFWjqmEp>oDq$4-oTRQ!66W4zWwUU;Ft$sy za!o~P35Ek{snp_7QI*htOzKby68cYkD2>yTi|LO-R70-*#3_V?idL1B1%>`LC3H|G z^bz_=8fEK{*(%CRshypkE08QrlSjqefKd-(PZ`pY2jghR3GUvvp@d&6tX%fr=0Yl7jTs$kK)xk#jUxE{gUMk+20!!z5W z4S2Jj6^L-b@)+yvP}EMQ>aLo)^@_C7MIEc>I9*k^XcFBRX~4AF#6-g-Eu9tZ_3~-4 znUlMi+z5ja9*J96HR0JncF}6sWNF3-{UYX1vt-W|`j?nE!c~HMMingM%Phk$sYwwR zGk2yX0<-!OCXP0h@}-iT`On|n==^d^)lIFc_|@S5$|{pe`exku+%C3a40!`$Psc=3h)aEF8nTOW*1`6(UCM(DWa< zPKO?GgaA{cY=VneUJ%Immr{} zb}<3^5d_rbAtpc}f&dNpFcY8wLBP}DznB2c2LhfCKV?F%BtS?1j0rm=0b2SIChU|1 z($ha@N}r;jtbI)BR}>WXQKlSF6qNQcrW{rj6n8gMx*Sv((%5^L0>5#xGe}L##@FBp zPuG7Sm2=jL=2&&zM$GG-F6s^77yyd$LrEF!@}dK!gs+M z`H0CdLO70ES?P zd{@+6wRulD6U@7b(?hj(aE)}4F40O8*V5}G({g+p;nMP=mBBDvfQCcC zB3zskg?g_4x9Mns2=2<^KB&;A`qk2nNcHQQ@%*306rCu*r!(#(Jlc#jc}#Ihj=JcE z2Gnc@6Fnf(iH0nAcbg{XC#nR*ga(?IQjE}F^s2*Q!&EXMu7>pMDIgg%=oBSE1> z${fZsC5O=S86OS2xv@?bvw&&YptWsmZ4>%jri=vzcki(Fm#v}aj3<^zOB0?N^O+}? zNm!|4>CePzDj{a>LjSvHM?EJG6lB;M!4vFcf4+QTogy-*QHeoLOH5PQ$Ril{3dd1B zqc8HWN1r(=j}@~3DV-jQH~Vx&X<5+h)J*+)|7agNwY&~@V_PwHZ{Xqz-i=f=^06SQ zd?Ux<`G?asOq>YDHx4QEoBV2-?{x8Kt!b;?(z33tSsjV#H*>rvDO5&7<}DnR=Bmaa zT}5MsJnO1!Hud_goTuMajBR0EJ*EOCUQ<1iZs(|xW}Db+rr+jYimIEHE-9)h3YU~( zKUY&xbrxK^KI^}T>dmKM)@JNEE)M21iX-%2m^Cx=7$!*X_vb^7nN5Y*igV)Q-9CD z8+=aB&Bq@xSkWKW-5ERarX1#^95WuJ0dj;IGhVq!(sOvsq%g{3CN+a+q8c-4jPjUC zXOzdx2u69#_!!Mpqr;z}7S-8mbYyTWkB*Uy^5_`Fh2+tZ$taJGEJk^BjAoQa#|ez` z=*VW2N5>e>h)2g*MtO9MW0Xh7ct&}2OkhzwIwms8qhk_RkVi*=(MmNsCNsKLjgBdd z)~eBw!x?Q*qa&BmW;HsdX3(V9bJ|UElPm-T5GPlD$-qeU_N6{EoEAvP~RkMXQl zkK<}^cr<-k#yPOGLs#ML1G;b^^i#Pc!bP_tOf7m^25EWPrVQ7wg>tOvIoVcGhUB3a zWo$wYSUI6AW?_>YLa&r1Fk@=Us>8)aWo65YiciNTGV{kW?L+t;q0u#DAFZ-{G(;r? zxxWT=j7AT?-%~uT=fv1h>8k3QqE*Gga9B8<{i#{Fbl=&EivbP7*)O-AIka~*xj-Bb z7N>_qI4Wx@D#K;LHNi65vIvg`tQm#dX;3j7WuMAq7*in52%`*DHLEL2SFNZh5*ysx zT}MWvvFq0f_iem460YWUbE_lVUvn)-J!sw6++GstxG>h%F5F*dq94SXrWkh1?r$(D z+tq+qcHOtLumI4rgnI|0xfCm(Lhf%eDUUc5=?*5%BrbU)g`STc!hI)4RLRG=))nzqe3?XDj8cRTR(TZSERaMbhVjQ8x3La1J z>gr%sNpMB!s$hwjKm=tanyA1tsm_xKW`lSx!PtgL*;5HwZDP|1qm@`qX?ale$);ak zRDnUpJ7L|*~7^$ejHbd;TMFmU370bVXb(+{?@g!-FOB%^Dxt@@e;uT`A0?Mjk z2-_!NymeF!D?UsSR*_q+=bB(q?C~CE+7+~ zp6lMhARULDfV|1%x!%%oc)w2Gd~2e;gy)7Az&7b5tVeLzQH<9uCWLXRiSApeJ8lh< zV&OOj!YEf4vP=eD1Sq}db_bF>!Wh1=6?%WfE+aC#_9)TNa6&2-}{(oo#if|n&D*u3Lb-TH{Nr|va0Y53fM6jPwGV|1TR zo~-m5k`~+ywTcutxiIM2HH9QaV1UMUPf>F4irGe-W5{Uq%eNtF8nF&7!BJV?$XWlL zvaZ49Icm=vRj%s(9x#$4riW=)yna&{IZ-We1&*!+hH(xQmUo{P<%dzA@CMjEVJOh< z)iiC%cr;#PX=O-g-_^bV1P|HoK^TEP0#H)oncmRZ-i*tiu}HYR9rw(TPlwRDA>oIJ zol;j%2#v-mbsGsJYEIq8W}$75LN_vEUKf z*A=?<#Ae#hYTwYvj;x(^V)8ky-L8>YS-&ccBCYG*`m%Hluccrp4D0Q_x68 zGFUgXH;MEpky2mRB?C|=IVlrK)(ZN z7Y>iik0a(a#NhAb84&za7T5=Z_Pbe=gjhhYlnsJqK^p)n)1q?#%%)dS@~;DQGU|nw z%kBes>c~QZMTkR9XlqHt?-ADpwnZ-j5Q}LVUcxNjG+9%$Ua&44PS2l-S@12H#r#Tu zQ%4n24&rtWwG*`kt)TA*%fjK2`CAb)27@@i7r+GsYzJ^PfCXCsyaZrjB}?k!F#j&Z zOoHWG{y9CX&_qi#EXvAp@zy?KZk8ivCy$h0a9Dzrs{-gbQrgaY>7q}ckSta zEYtUMI`eRUADFMU(*K0gXTmNlmZEh;N*UprwiK{%4NO+Z73dUC3&-Su=4oZ*eheee zMp7h5(@bn%A{7DTDvJ5$!2luC=<&8Rof6*hk)$|1+GM<(xAa>`qD|HD3_+4&B++K7 zJeToBU~P`dDPu35mM0_4sbX0;ytye{C$vQ~foqz=FA~~fg=f$rah=6lPpnJMv{>uI zU|p*4rSnlu?bK^zr2l3-xRx%}Kq>sDq&Ph!YUx}mWRW5*rOQWJF;~Btk_Tx^gW~s7 z%nC!+Z|S!PSxK8CO`D4c0(5UFCGt9)U4=-6X$>mWa0RuO*Wod#xNHq&QK_hYlL}th z-PKA)u1TjZmk~88B0Cu&AK&uny;{YMH{@3Pr9@v@>ZL<8=f$ zYH26cXzdDB*FO=mff8%lX>=VzJ5>%gU@xO?+G!^CV`{rX6N4obEy>u?15P{1HsG|m zO8nCQjR7}gtQ}*J89q~dmkr0Kp!Q^%HnpE4U z@;Yu|>X4o(;?+exEgXdwp=qO`7k4PRR&;y2VrZlh4h9c1Ed4xsRy=|#=%O5b@A)h@ zo5H+k{ygtCnU^HZ@F^WdGcyvJ`(YFn_0Q*F?ofA;u)(1kT>M#Uun8Bk>g%En|H>MS zLZS39cJQ2+&;mbGl_(rmiO2Bx(Z%;ZYbEe=ULBq7|B5Pf@D0&(sS5u`7tC~Z!R)_% zq3nP65}6@yO$f&cWQj23oe@XV5j3}+=XTD$ ziv+5a#$A-s;JX~g+l1M!ZW!w7hJL*38ZOU2kie}S(}-uBlz9S%zsoZL-yUrqzP;ZA zyZ2oBB1ojLagvOG))5Q#Yk9`3Obxx3Di@=C#8S~%Rkul=Mi{d*_aQmXPE&)e4M#`M z;b>2)6<6BY5ZNq@e2(!aV~TM+xEu$t9k?*VvDvBWMCt5Ew2katc#k)e3XK!iRI-)X z&ytLJ9F;5hd~JATjQN>V_hZEhW2LO8p?3J%gufw|H0-4twzP&ZF?i>2u2u=U_6@X1 z`d{&-olDNT)A6D*Kq^@Jeo2i29MLXcn$pfE?h)<%<(lv271IPW>K-9_4vvp3Hh9I4TsvfS;I-ADTNyb-_exnGyo@%uoFo1 z36v53veAsO=4fQSs_2c{5fIy1rl}gRQG5!88>8CnMrtArCa*tGII|cP)3mW46EcUa z96cA4$&fz+u9`8ja+59cyo9?YcFjmU0w{f6eemUjYdmUlu;%R9kCEbl~M%ew-V<(**D@=ma6YoAI;((+E2 z&GJqtTiyw@Ebj_2E$_*wq?LV-?6zuLl}OSam$adlcSK}#+K2Jr}%L?jS92TKu|9*-%DR#-g|sMHfdq@H95 z^+X}5CmBLLQAp~ELZzMvQtC<4EcHYft0&1K)e}LMdLqP9PlQ-~>PZqvJt+#QCxVoEBFIutgh=&7fK5FSYN{uKho~nauzFIUQcnb%>WN@W zJrR;rPlVaj6QQi02(;9bLQM6Pj7qAaJ+j+|t0z-l@?elCQawq4)f2(TP){Pd2%>WL7$dLrDWo@}V4o`_~wPcALofUBwvIDz4-p4upFAykz)BX8gt38hqq zA?qgI2D~#Rv{A%{r7lE7T8D}lBSq{OHmM=vDiR@6kKxoFrBf_N4BDhWD>c_{E~kD9 zTo?4hz-L-cZH{e@$sdsa9N#?{KzCC$>rgs~=;EK(B_WNBhTEKN*^ zrHKh4O)NP`6Dt6kSOL()k_DPr5uk}Bfi$tAkR~QbX<~vbO-zW?#01zhF`=d=CU}S@ zCIV|>1u9KUu&Id&wlpyzNli?cO%oH!nwUUK6D!2j#K|bTCN_DJw8v#v4qYe`m(;`( zU` zG1_Ep4XEbyJ)5U*C#)7f#OO^?wui~YGd&G9FO^I>{1sXbv9u@2@X;%@Tq1slh&YYG zYf?g+N~vE51p}O>gjd74Jh{8k7RfnP%bA+GV>-@84kt5TL}}=E6GhroKw36splNAi zC>W!VbXkkB(1#-^Gm$orBF9e$LBneTDF}VG#9qhUd}83UN%1;%GIdCDOnp+b^Kn@C znI03kav{%vot7StU)D<)Sv`e8k7)AgA!tCP(nz9N)FPX3V;Sx05qs% zfd*9sXi!NY4XP-lK?zbClpsrk5+XGy0X7XvsHs5-9-={sz#3G6N`n$?YEXhL4N6E- zgA!)bpoFppCD78K3NbZkGAgMp_sDJ=zLquRCD*b*Pw*kG^h==G$_&R8q_GFap?H^ate;Rn+D3zyJ>a;E|loPMd=;4(`a^w z!*myGBVOxK*I_86ODpLc5sRJlF4jSC*Lf^%y38W95qB!)K4$iM?g1esDI9*S=s=wA zy>-w9qtq8vf?VFmdp?4eOtNpRuWyD|FN-~m*#pcj9v?|M@Oz(C2i8Ypri-=$Qw=&g@P-TdS?JOpLeyt)+VC$nMmjz8MvI}5xyJP&727E-k8az2Zl0p# zm?1;Q^Tv8Dub3S(+)U4+99x9tm_fxjy*Htw;h2GP!IkZ#1nXU(gXmEI%bHXe4eCZhL5Dn~0mW;tx4INs2^0^p?ToGk zI*%MPsMuPd(lLWVHvpB685G*?VaE&#-Rxn<41|(n1`j)CQ21AXE5{59?**gTi+LmyQ_}x(ldu%%IRdpvp0W!uJu5df&s+`w2(I z?`8aD!cp`47(YNbUMBf2;{$|C#|%o|Vc^O!gTjw!X%FKlj~p|2j&{uOwu-`TO1^<^ z`Cr(_(sy`0!yPjyv3Gkt$8gM`;&$5OEXN8@v&da4)|$SSV+NJDZ&6U?*tYud^`(xPnFvfz@b1A;lEgua;`?TW_m9JcQ z7;{O3syuM;ZETmQ>63vJRJwAa@DmN$4{@{bDXVk zQd0?!>Hi={;&%TBVNgfLyj4HM|G_NKl}@nxKUk)y4l#nd zjCg!BK->zaSc&_@2x_--6F;{9gRet`e+T(LxEIsaW4___V~NreFX{ilR?2+xe?Ym* z(vdR&0sjYz02KuS+V(*vKr4ZOmfFPxs38!bXC7h#^bQEp|ACSLMFWELf1n6ZFd#_( z2a3=u3DW<8BJ7X^>Hk0xc1nWsf1oIRih{ECnI%ya6!uZGD2js8KE{;8ih|JGma!GBqPj3cI#*zHG zwtNLnzgE&vMD^Z#HD2Q(pIz*)AW!ef*bZBYXBE6@3H|DfnGj6#qr9mDjtH*Hpp0qZ zH~baw>!nydC(Wbo51IFs^cy$=D==lK$HR*6GU+#RT&69~`URd2EPOZ~Yc(@1UD?O4 zXyJA};&0~o@x0c=H7R@YTQZa$3s})ZQs2taQ#`{jHtE}0FfKN+e}G}_q~DgY3(e&8 zP{TVtdjMx?^xnw}fLzl+M9NQjrPAdz9s%d4zf$Qk3=%imvRHUhcH)K96R>?`iv@wo zVnGmDEMy3a1%+g>kRdD<6q3b)LS?ZaNLef-&9Yb!#uf|7A}tmKSr!XIEQzu}}n9EF^&}7K%a^3xbrzf}jw#*YdSILZrol0Gq{vP}5>T z@DPgy5!hm(KxMHY*tA#>Y*{P_Nm?ujvso+%Ws3!Ymc>FLro|!|Ww%(EJW1N)vMYz$ ze2Gh1EF{1d3xbbfu^_VD=BwD)VnK*yv5=gm#exvK#e#5~#lnVK77L=;Ef(qFaC;bj zxWbLNt0&xZ=(<=o#ss{5m7pnCRKS)w=0ZPim$7e{qSgkrmDI+nRgM?~AL{stJgJnl zaf+yok+0rXG%CeSyHZ@@8?PeuF)PT$pSf~?L|(^e6BL7EjCJMFS{Yk!N=>A#BUW5k z_}WUTP1=JAH5S+9l-asE7z#&dJ!P5|aLG`k&9rF|&7M#Q3{MFdjEgdGLyVNUb}ns) zx8vQ4@j;kd)-^YE;FU62TA`gs3)%M(H;xp&c0N7fs*vgUlBSOKx)|O8jPfQE*AH%)hAu|F6VD>Fo?<@%YO4a-ioy}RekXt0P%Dtd4{)(_ zCKiGjR(050o=byp!VhzTIgzZbyvQ9#<^&O~Sn=*e(|@Ng;p z{+jgLqb>X%TDAypbWkDIw|4T2b|`+b5&Q6J9Bwyq?xtPkDkLgJNye*J^C(3F`4!Uo zh}t#Uto375>pZ-@VKvKc5_c~ssvY)F*{{sTm(xR!*b%f=2t$T^L{1WuA}yWab|rgO z1?XN!AJ=mPjnb=zv2IqZvoDgYg_jpXvJiobsm*sCK_h6|WE+CF30RtV5arTE7|-(0 zWXzW@5q!?RMolNaW=LxX(~9-)W47YcBh7g#TF&Vy!MCBg3J}mqi~BpW)AwxY42){2H`_7#nhd~At4{oF8Ay-WVUihkZ(P&L>Bxmx9x=zNO84#;ZA7T9iZcyb9M+@7uYPSM^% z{0)Fo=?hev9`sg(TAxJgnmWj@oBEv>y+Jdz#ifBlu)|_D1~1k^k)@;TIL9GrXM>b3 z%dU-}vR_MhT>)aLX!|5Km$5^@MnpTBad_^N1-~}n!@DC|1{FiUwov%3qQDC$Zq8f3 zIiojfU0jB*a)@hFjZ~CIp-rSJju?y5WN69a|5(%v&eee1gpr0J@{*G#xYR<_Q43JnQz{NQ~AA0MUTS{k!wh>m|n#e0$JNcGt~LyX$6M z9!K!805z9hU3zvfTqBGdvvgoeoa-(U2UjJg%jBURl)d5dU^yHWhL;yrmln%?XjQrN z=_&GE=ZqK)9hO3S7SlfFI(Ni;5}qScipYDWbYdbmHLmkG#$$^yfAq_B{s?-54@y6U zHluB=au4eYkC-NfWv7t!KO$VU%oa$oQr0mkH>HMtyvwzY@jPK1x9G0=5obeiDz)-T zR3VL;2ftnFbX}7{ug#7aZuWEaW>EP?*v)>fYbDKci8jofmFMcoxC^Q?MVkFwS7)3I z!PG9&?B}{JgEGcLFJ+k7&vm^N3$tI!P_v)w29EHjSf)GE?B}|X<1%e=HoKkcCXUZe z#@h{duA4c2e2O|^9%}Y;-IDQ5**yU(dPwS9IeJRUaI>FlI}6UmJEF%lkGgKl*o|g# zd#K@kmR-)BaxShe__3tmRV;zZE=LgAgDNZI8i&9ci8 z#&$W$BJFYnS#~)>EV~>bmR*hzvdc*hvdbv|b~y#WE+<)Fms14THSU%Dctj^va!@Gy-&$L zy@Za5q+ev@SZ0cs1hAEx;y1E?X>HY~XRr~8D%^C?^d2T@w)UNSNPb&$1AIWK-)q$F zF*E6i)T=8}@cgt}steCZxa-&;wEIXALb;1flA?XL9zwFhVfnL!Vf+$d8-9UO`=_S8 z1NvyRa}*domPU6(VI%wJy9Cnj5o-S&fT9*BG_(zAVxi^081{9T8M0w3#Bag?r{vkP zzZhOe9Jztzdfn}zp@cVm;Xn&NC8G?ZcyU5AmrQR?E|iH1 z;g#k?$QzGennXN--vnvGM2tC<`r22(rC$r5jUItj-y~WyWwq2rFT`q5nmJ|L%AWz% zexzw-;Nf=t(OW20V4cwJr)PHno%0jwoB-TsJ@5r8@Z|eZ+QVFovvUeTf-fNC{W}Pm z@(d!Mf;XipF9VncuRBxd)$Pjx(eo52vVA7#F zyh3%L>b)wfhk;7tRA~EUXW)l9+apc$@UueZOqEjiLWHn* zJ&|m>%IC;q8s&f&p1T$6NiDGBq6~W^eePtul}@AhUY0~FH?3bA2_e%0SaRg$qbFB` zE3XK^x+wt80PuYR8Ufss1E3SYGXQdP0OX!PUtWC8(sEUv3pvc|0`(m*PHQL831CZd zWd+1k>MfIR2V%8Xv}ygsor8(@{G9;Y6kEZ7w8cmuu``d)%Gx7&Q z3KTLCdu3{VRQvmJ)C_M>cdL@QJ)|Ed;?-re3Ypu%@&naiwaoJ0%tJh!fe|iF#i77w z+Gn=ozC(TN^W4p}Pg8X}>qHg)1qTo2Hq*SisCQ}iqtX6-Y{1w6nLiWbh`fiQ8FDw` z_~I-KNJH*M9MLz3Zn^@=Muc@A$xyoy$HuEbb$Kc%k>wqP%*tp0`^H1JZ#)dTVkB2D z&VuJCi{wVcIhUGA<*7JseoD%w-+D2A@-anP-a{xK+l?f64^eGwZdHc;*o&J=S%e|( zAvU+QF1P=5fRXF}sRL_rGWd{BYh$XPE+5dc9Pan%rvr>>Owow~d^+P!!pSGUk;fF5 z|xRK-Z)X^}A z88`XqeK8zjCig}59}F;V=6Fw16#rm=aSKP8`?O&Wt&LkbCx7Z}%4s{J$NZ51<2HX5 zs$f8`$aa&2T6|=m_^iB+ z_6UC1aA!OPHI4?AbHtNj&XMxE3)-UC`CS-^nmecl=wxL4*82NR_YU&Az!6F znjxDR=BB`ng@$EGQ&iqq-hwAf zMkOZOr@G!Zre)BCG?m`bGZ74_Sk$>ZpTY($p7AHl*0f`L<~NpQ+yD`%uj!fJIF*Ym z0(Sc-+&n{E}mMVqsLsvK^fi zwxWz5AYr=GxF%x>RH&db#YZG?&np(3q*D1SZoXY^s`P_TB#@PTA7T-*NV32Cb${I zC7lg;;Yk>0a}1ubbR1}$!+09TXENJ!nd&zmb4O=voF{8wj;CWVoS%6P3g+@q@iMHR zZJ-}_aP(gZ+DQI!2S-1xnNfBuN39=saP;3I6VtC#8KLrulGSBF;rJz`8>NMzFq>dP zh$J5@TDDe*M%296!(^U{iLPZ|3_Q#3gM93JSQU-VrO0uA!idjm$L!-Nsg2J7MV#>&VS-^bTDO4r5w+d0&-Ws(_FVOkg- zHpG3Q~bo{wpZ|R>Y|MS5p4h5-Rf#QT_*kVw}Vw zBA48=p(uP_yfPBwcEC91r3Y@2$s+Y~QTB0|o+rfLWs$(q3$Z@~K^3QgiZfNVO@!LU zHRCwB$m@GTYu9K*_OoD-R|rgq8Aw%v%WX<#lw_*G)In7|ssV$W>CV~ZvaF_v4i?o3 zQGF1V6Ilgo*5!90`9YAB5jGyVtE^lB9Bq>9X*sWRujrfbn;CL~i`bJIHdB|N+f z+Cn!d`!pI}Vn!jp;FFreGmw5V3>V~$zK=TW!C7YBk5S&Lb9Pe`PE~T@>mOaRX9=bo z+=g>m9;dRb0?JGsSpP(0Rcnfb_5|tWFCxk|Bw>YC{`bvSH-&ak`vxTTaQH0QDIqGq5XxbI(`lnM`-U*wN3*9Taw$rd>u&} zJ6PcCh#;q~x~N9CekSV;c`$5jFUbEq?KkEx*Vms|NQD*&j1XNzHrN7_`QEDy=b$6? zC8(M%zWiA$u)e;Y-s1f{%iqrBo_Ufg|3O*)&;A4F$rEsWr`Cst_!qxDYZ;S1%~o{W z`)v4qUyMoITeMCD9Vz4Rv~c5ihED_uR40N2(TSi8aUw_|oe0VhCxR5xi6DjQM35kL zA}DFri6CKoA}Cqpi6BANi69}?i69}?i69|#A}BfNL{I@Z5mW$91SJbj1Qh`%f|5Wd zf{H>Xf&{4(L4vFkK|z2oix$1Qn=G1PL}z1PQiI1PMu=2oh#H z5hRpP1PQcG1QlYQ2qvTKCxRwVlJ>al%Aq&)iA$acN`OxU2|mV&Ad#sDRgnfKDK?AR+b>LBee(f;QAT5hR-ZM9@PnR>IPARcaS0POJ@ZBDKD`ZCzb+nEb=y z`H-oZ^Y$*Dzn##Ttr)>6IKLT9033H0sws{87c{nq3L+=>5ERgMvH(9TfJY(dF|en$ zq72}eG9HEK$Oi%HIfsyYfT$~Ow7}LDXl7DVhd{%nQ;u)rGeY?4NROwz2}IL;ZG@yN zB*k)*5P_qZx&MGzucND5mHPO}L=_$wx>x~C^_kTF`i?N1chlqc^HiYu+-@JuROOzE zE9j;H|KG=AZ_|X%w6yi6OG1dCT9K0-cGKaz3D9Yk^AV0}9;$R5~9}XuHAA2Nb&5VCMsblJfzBoewDd zE5McW0fqMhSI!3%ehbA*=K~7gLGjZ0fWq$vuAC1jd?#?}d_bYQfJ)~B3he``oDV2` zAK|F?J+fwwoPNSl@p~D6nQ+wnKE@9aE}ajk^aF%T=K~5q3|u)MQ1}teD-WCDe84!` z`M|mq*&=YNDNT7c=L0JB4zDrX`GAVJ+iM)d`GAVsX^*p<2RzLc*rj5v>1#P3P>K77 zMO*2g<@9hqkizGCbekcC&-Y${x=u0A_tFvZX)Cc5>$&gDzlRdqPwkQfSp1x~N>mCa zbh||DP6krg$-rMBCzW7@pQP<3f)uPMGc`(^=Ft~xXX8yz15N~>UvN8giKZrma9vFE zZ>csYr=gR0muXiF;XQRI?`alqdbq5pYGsg?H^G(o(M^xONc%aGj+l)vU#HLuWv;$6 zI_nx#wnbVhqEO}`>Gb6?N2kr@f#FuA6?&U%Jd%)-HC-N%2-p!tYI(ujMMXmYqU+b7 zc#iGz;Cc@P@fbT({?=WL6^bzE(qm_bqINP>H*78s_ys(JE#nQCGn-tBXc*FoK}CDL z^h2|mle?H~xjazK>`~;Tzk-XHKh2Vj`S&Fzjxfm9opgDiWcVdDDdJ-0&a^~e%3i|6 z(Wb_|)TL5qD}v?nKvBmVN4q?r7Q-XOz>D;iq=nZQ@~(y0*L=>+Cf_EF^W%Gzg^L{U)KN6n%r z3QGGJQw}Q%io2UBT@EUYa(Td|;m#l(EE``Fqp%tM!T)OSUEu4gs{HYD?@80srVY1G zQYdf>1tOO8QbH-vmZV8bQ__+)X-UiDCQWW0Hjis^(+5@>X;D#Vc(T5GSh z_S*aGbIv~blzC4IEO|iQz;R&71Hu&k2tV3=J;Gs@Q&4dgT6uk)6aB9G6l6h706{N^ z=H*@j;kV?->?II%@L|{#S^`01^TvgjK+ssU_L`h)AYlCCdbdGH>~X}`SvXWxE_4c( z*H_4*_ks*JnmH0Igzu@1~?NJTX@2!4-uwlvXV#tW&Bh~mv0lEn||wf43& zws+8nts|I#;|mG7pt$Qo$N4a3<7cVclohN`EAi*po;L!Th_bJ>Rfbh&B@SJ-S2iH9TdawC-SzgX3ES?q*IOA z@qA#6YD{9ep`Ai{7F|)B^v4<;8j-Upws3KGi?$un@L*Xe&Y|Xp7jyaYFT{nPNXOM^ z@kCtv;e8>#v^|xga`p$IMPwf75{b-yfOhBWgVO?MFagPhP79DgCB{03;8VO#iV4i) zx~jw%NjjTO>?NghzP6I=FP#R>{O_+!;?bA^YhfeHrn%jg7v^Q+B=a3wsOgw$4{w6 zcO^y{@8+5Dt-IiJ#83@M^S=6Pg83n|yjO|MxMX!zE#?K+)UDfyr9;0Mc@4v~Sj?nq%FVlzz8R6lg_Yn|!fx>xTiV!MrtslO`AD3KLSB*HTs;k1+>yvT^yK?!m z^;bBFyt`)3!(4m5deJ5C(=*G76$Dpc%}7iZ(PyXX@HHviEosIZhIxO@1W^#+!_3IA zasw~#?wQYn5&D6Ayhqc7Z`xL4k;>j`dNC{SGc$j$_{Q>8e$n@z^7hSKt+4TYl@;)u zdv_O~8st-RVUk9CwKs2w5yiPRQ{&{kdsw@9`L$_$OIW`kbuS}JVDns-aEkK|DAn`T zC7AlEY~Gh=(j5pg1l59-`pV3GN?$J@>8r1YKHAG?{+7>7%D-wG9xH0CYokw1J9!V! z`~ugT*wm&v8`Eug;MmFgDxWBVruax{Hy-kL^1e3nW7;0@GC9So$)ztQhskq!_sw)L zxi;QAGYZOFgihYqm2dO1eeaC>c0P(?fl~FlDiT3*OKJyRV~fnL1zx`H!FW8Of5sg^ zPXvt?Az<-iJ=IqlvgVQyvCVl1(Qk&3{B!Rf;}f>hn1H z)J3>^p5QZA@qX%0a3*gdahQ%iIJs?Msi{7m-S@R{BJa{KMRLL4@cvSi{VYVxPi!hkL!}`R_iM*SrZvzT-r)t|`d+?e9)_?`In&PDogHlR*jV0b% zQidaZFBm*%%{wi*j3f_T0!g^rv{j2*Muz$Y;SiS^RY9mLE=6&YtKUn;ci+%r`BPXs zFuK9*JeDC@`}-*IbCT7DXQ=eDEKXzxMe)YVfR&YGZy+Upq%nBCcq>iizK{HK-C~S7 z$U_I1aRPxHx%um0S=0b<7C8t{6DTKgPcen}kxxu>vQSJ;uQ&LyO3#STIty$tBKU9_ zamzZ*kJX=Y9{NUn>XT_ElW9*CTkAJQBj=EnCb(@(gZG{hzs@prUB@*X2)^}tKD~>2 zLg$*wTB8vKd0NSZAn`!i;cMOIg>x#DU}%;18cx>{$+B;G4s ziF~gD8`d!;9CbIVKM>ev}Q!kokSu|8V7Q8OXsNF zlt`p%8lk7o!SQ@>pEfO0;Pak-a^PTwQ4X1!q#{>>z}LQL8nj;wVY5h>=6i}?!2%L< zD)WGjr1I=MslGaUS}_>Ro{ZXb$73CK*Llb52R*@=4mRBr&cEoH@?7 zB6=R&{PyiWw*>OYaEAEo5+}?7&w^Z}>UORn)_jW#kY3+qu;k^kiBzrgjKnCa_3jca zv*6rGiUyG|kBb3SHBBR_;Q6OTE||71vOd4QU?YrQQUK6#=9fAb;ADb!Q5<6?U#X2M z)8T@^A*5YMJcuRnAf}}O1p4rc#xa|P1qjipsKdoUsZ?SSkvPsJ!GeUp)HiRI-uTkG zIN|b1C1p`#PoTR;>LxuNWNr|@j;JyrcH7Kgv1HiD!dcf zNZ(|4%l(K%s6GCk08!5TltptYMyLNDdG52>HPtVZ6~wN0q0u`2-1@ ziIk~E6U+w8>a3-a=j-Z>4>xiz+{p2av$6+xP@A8qJMV&U=RHX}@5w=z6-uvslJv^4 zV6QwS*eg#pQqg(qUYWXWzgM1N+%Pk2&y&TTMSew8|1pbMawmPtaPe?zI04NLhX=KH z>T9{vqSnsgLD6zX;4G{YH)nP5%n2giNvH(v7Y=z0tHhq;#h&l11qNDF*m5Qk!XkXwFi>y1HZt*P{_*o-wNQsH&Bz9u-60fXQU2>xVLix~i_+qzc5X zlf0u>IjyS_8LK!-4 z0-A~i5;C1VGY1znNH{A{40LmK<~!Tei%OppI0Wx=b<`o)q`tZn$QcyD6r`0OCIO8U zJ(P*Y>0wZQI5Uiw%-{tRSZGXS!hd489@!(JT&hl%_$;JrqtJ+mM$tK|9H@z;$2>pK z)CI;klj~@(LH$r5s8v$MurnOn7@+XbBv@0KMNr8Jt-%Z=&=!Jo6-cjS#gmL=v;(Q! z6lr`@g9Ddo!GVhmQdC2cxdmii%q;|C%NYCQfUyxnMS(+9Ie2-3v#01$->EwM=u#w< zZmf%uoOU-7^ic9RM&RTpbap|@jxyIHo|U*$4lub(nMpc8?w|@}KsreeASUZd7nP< zGE#~;AwDqr%IXcYMp~E|Y+f%rc6?J-H-ALp=&^oXH6JUpqOG@VZe`<17 zO|xP`bv{k1jyyZtoZ8&p*fl@XnV#R*+cQ7MG;MoVQ%7HO%JD@22ul%)6C`PVy0>`? zZc{Wl4)oV6ilds_+Pk_kC2cT*qi=U;80h9yi-u{*sZ4LPKIqLfL7!!z!uZ}b*_ z(|sY58FGJhqgUciIpX$a+{p*s-o@_Zmb|F@(!>_@7Z3Ce0RHlXRe+Cf-9P`DrI+G( z|AYY?Keu(&U*X_yCS-8%{jCSDb_+^gd1>gEz}=w=yt;MYqlY$nOWn^!>b)yBx-Z>0 zu<7sIL%TBW6Hdue+_;bCm*l$zHvx*ceXDMEC%%4V)rU6p^=;UyPPXK?yFYeXytAtM zUU>Sq-g&>=>wbDyCi%nE5--uycH5&5xm&zd?uyqNuluAsai4dlH{acS%$@oC{~dI{ zrMJeeQ(F#!U;{2`$0H=s3jfa@aBITu#Aze39%Var=-zD^9ULc1GK9 zzoH4RMB}~-F?vI3^ws0n=mbSPqOhYEFJfqQ-cfW1S_3X*qDNI1q`{xU&Yl zd7Ipi?b`32*0OhKlUrEtZa>oZ*zWW0aC;BJSMJG?s0-`=0wto(ckp|ho;X4EHZ6Vh zZce{HD_JObC7 zt3p(T0ja{YNMz}=k)_cH6d!xYZ_jMc1lkTg_!z}2t$!(N{6)GGJhX#HG1}<{G%6nK zAi@!3XMg$nw>u|NUw&xiro`Z*y&E?@wQ19ar5msA!`~*iZ@?`$_{xtPILeED0Wg5|m8qJu@Lt_m2$cv7PKx%!bsn`rIXpuHG zw4h;%Nm3YSsI+uy83B&_&-kd0JOB0T9<5r^>6R^a4?Fc2^tmUMxL@A2&-;P<4^BOx zgVD2Q52fRt9u7`Uw!RQce>j$OD26=V=|jEMSGF#_va0!VciSrN^WE5yO>WnIcS`+l z?{7Vi_>A^pnE@#Chi9Z@0i>2`cI#B*LjQGY2LButUoJ}1->(bFmxyu zqt2^<{>MZle~tweqsK$60V&5)S-cFDMl78asebI5{^r$fS8rUhW!ly$e|3+0YP~lz zdg%=JdavF+$&2@4nECtP_qhcFeIM;p`KcZSvDhPikJD<7`K|z2AN`c9kMB;4OjjLk znaUC8;Pi3wK0%|3|AHJ5e1u6SiLF?%s->5Gqxy3V4|_Qh%qn(Xm{Uf^bkL+C?&U3R zdA)nN7vJQ);_Y#dIo_(nXpNt8XO*~rz00fjezw=U3G$4)XIH&9_kC`kH`PnL;oaf>ljH4kCmwvvo#EZ&PC8ia&UxM4 zyszAyP~vX8>0-BVF;YsUd&-e7?si-1-T3oM+*ro_#;#-Ttmm)X>(0z9aVKQlt=`ln zmtV5_Hn+u_x^%A_TfD@blyNtBi?3{TPt7d3%{_?Ap`N}f_d}6`QM$IhOSS61*|=cgFl5*O&k9nX6lWf7PSsuipCT`|2yOC(_;{ z?&QU8Z@oL^VB045hE*%wg8KR1^{XHKnOD>aG0Xn_qfc+#wEKG$3)@N-{%-3JS3h_y zlJXMJ(gk3CCV$(N9dFNnQ6=>)#|XE;oA&e%v8nUVt6#TwpF4Hc-pl&-s@%N^kvg^u zxWIBFoIPYI5L_-!U!aD#iO~(H*>BB5ik`+w$2tgJxaHmIB|7`x}SHJhV-?wff zC+xsa^bq}QxUMhdZXI|-xdzwrCp|yyjeBCzDD0)5(0uSOXFDgfq5x_eNPEMkMrtnd zDv`S&a^HX6w#kj}bDNKR>H6Kf+cqRNyOZnP%)TXM6_K^SJ>ocXi8?5N5kEJaU!=o;|=w-ZTzIWeHGHi4?p03byv&Ht><0i##XsK z`+s`bk_+ZnKeMf;cXgYa+3&_~x_0vd_mov``?0^@y2&l@rnDY;9wsK| zT&XzHJ7dwZadc`@iXg@y->lQ^?Td$lyfBqc& z&u^W-1ix3dp2#`H5CrQXJdS%B^FN#ngCsx>yktBvO;8STs#G~>zGv{e?C zMJozDXP!QE8u!lDnl z<%RK^^U4d0_lzqqOzh6TqVO;#7^4#l6Tm%=lTU!^$@0S3Q_BjyXIJ9>h1x{V1JldY z@fjKoJrkRtreBYv!<-+^E_1=B2z8Q~vH6DYI@D`b!5ZQYdoZ2D(=F{x2SxW#y>`2> zSj)u1A|Ox;?}=pv-E{PLVXXWKG85C29waX<(>4M8aDJm#lVqlf?oiM+Tzv@t3g~58 zC{IyqdcqH}+#o)e+)|WFV1zC+8ed>OsNU`<1;@uHqGpBOAe^R}@5#_+T|?sl0st)#dWT#$9D$ z&DFyMT@{?w!TjVyuE>dM3;Mez+8A*76$RTuM;im~UtSPh6F5YpDGwbEZx@RDN6?1k zGLGiMX{#)3xIyem=lkPj3O`BxIu6-`@bbyIml!{SJ<`z)!x&^$!LWWKf7TN_pgilt*r+JhCUhyl~O(@s))G z5j5LHz@QNpBbCIFN{Wz5V$UL-d}mcb^gAP*#`1m?hoql;aw3oO7xepJv|@68&F=g? z<8IEo)m=65@$x6ipIr8AIkN0iq4u4tJ&`^7$H7kLlmWs+D(YAJo$#_~XAR@Ye}tFS zG-{deb4OT2MnVH_A#IED&)Pp&Me0^)HbpC`~zp42U~6lIB@EQPs9 zar4_(qM4i5ih>ooUGsU0KPo3HT+#|ww4pt3Ak220kXgUK40wr*{)1$%o5@~# zC|-7tL(`9TO)M-121YA_(PD@a@2M3qTrmt6hvAA~xLEm9+IZkK5C6npmTr97@K^P$ zVf&$}sBO6TC;TmVr^>&eVLrprlieNxy$tx(bECk)ZfR1E{7UC#F|r06(-yLu>WR2t zqU45+AB zY}vDcev;yfzE`8~kSVEG*JaJ?N4sszOq@kukE zT_f{Bmtut#vi((r&I&A@GRS|#U*1=|+wfO$g>0s}*_8#+72Me=50ZVToV*6MpEp!i$FIi}5~)w zR|Vvo2ebx;S&3gW<)t~)Hv-I(#QGf8@$o+q(5bGzs45+JbOY+PboW4zCREGn<@g9j z5)0*K+VOTU)auFfrIV=k7XR@8Hcw+Zom3y&O(ykizs>m4WtYPX?S;Nx5mo{puwpI5 z5csSWKIEJBZxpe5*`Lu6an(3Fxi=Yp4vLs8Y+*Dax~ztm;EZPKAuMpo~Mb7Q6DB-+e7<_fDq z-D%#oF4frE-Q_48RV`Refpw&FHFWTUE_YO@Rhh9mbDu+B8Ek9pYVJt&IN_yeBv`F> zknM$$-kx5*hTgm$iGt3CEZB<$G}M|CX<11li-1-~qP39FwD57k^qM+eBCG-ri!?Uj zIWN3!-i~+T)5=ej;+(9{zqT9Bw3e-YNt_g^3>?u48fwA1z*L|fF^<_UbYM&WU`ZHFB>sAnV*GU)Fb7;5G{(FpvS!6gKy z*?8KBPT+cMrqoVD4-fYLPPcUD#@*LiQzV0Jl$ zG-Wh2KUc|YqJAd2iT6}#fp;5ROyE5RS0wPw1{W8Y*4L&D{E7wsn877{I8W1&HzQFw z;5}K}WjN2^iUl5LaB+cYJrmkcwn$*l;9>&D49*ky3yf3BXg20oH2wz9p+ud;;9-U* z@%44YsS)rDM&Wy810OC^Y$h=KQ+OXZC8&FStrCMqw1z|h5gJtBUs;ievrfQcj2h=` zcP==0P!2^eP-g1`)H~7RA$H@peRtZr9^!M~@M+SXz$<)X)rtl^TsK}xxfml%|CCXRs2E=lvCw23(o zGa6xjrGmnoJe|#(aHfQY#3QtV6m4MrpA1g)1EfZbaE@kd$mebg z&Xty%DD&aj(P>nvln(1trM=?v@x5e*iTa!(3*i zZ>!UGiLY0UfRbS%&IVi923^ejO5G(gCmQVsvx^7M84eoS$cnV`-gVLuD;N&2d)4|n zC`XxH;P3kJzbzr~_YBVJLZ#dhra`p7JtzlKFo&~`GW~M_-U9#H;1UA=#^5X+q}(e^ zqjZo1DVReCF&-CFb`W?bpQMgP;JCqg0+$$ELSVVaLU!fT)^09ikXfyBj4&it*Dpm3 zi41e(jFVvK0^XA{0xvMQn7|7Su1H{-9HLDPsN~=}jU#In34Fc5#RP6JI8WeDFitU) zg8@TWB=BB?iwXQmgYyKwE69*xeuu*?TjQsf&a?jJb@nw7M6q08^V~ta?6gi;nUXcB*wtc0;YUat%$tGpt3nk zXGF12QX`;|zqcW~SS=%@(IEQ>C_V@~03`%(a%AjoCR+_STZ?t)Dw0Uo|d2bY6 zvX@w@WJJ`tU{K%{J}xmRun0zL5isMET`(x{4U7YsfZqv_2`oC(s8HaTA2JsV3M>^N zI)N(#bOIaa*9a&V;8ZbzKjarp3<|v0$6YWeutaLELF@Tk9jwf#Hq=zW3LmxhYYa+e z0F{8x8miwh=&}x=67VD+wN`4h(MQ#6Wl*L?P*CbKV5pe8zZ0LI!WgQaz~W~lNb#@8 zB{G3UFvtWP$yh_I%)Pv)%qH-C1{V|feuFC#__GEV7x;4qS1j-s3@#z?HyMYNbJUT8 zZv_Yie%#=S1%ATd;sQTua76;k)gk3SfsYzGPvHCb;!P>zJB0z!_%Xj=V(*sSfh#veAv)=0?*^lPbtIa{he594`X0Vddi^26(xT;>-hv6f&pB+^GPsz)Lk8yw+{unp3d%tjBS}GlyA3WOaN6LC1%9u=#RaCNW@rPy zB7yr1E+(*Cp@Gg5_(i5u3TigyS6u!%Mj=oH6ul8B0`6c|pt^xU;XXn*J>v6TE1=XB z!)^f$@3l5>$#=fuqW4F9-t_{C^U-|?C}JZ{y@28YPzh)>sJAt!^F=f8ChyPkZBip( zgOA!EjQ+-;9%4`~Q83&Q&=_+=wzwfii2l?Q{|n=O$@_?Nt;i7}xjO8ZS%H7yJq3%v z#|$neu#8jm;|Wk~j~e#wmj{)$mlQf`LLWj#?+z+zwZ_c|9bOkcvF4P*jd6(GBo;XXqq z;En*y%1rZN-iu(@xPFN>?`GY};4;J|5SSR-0 zXi#F?-3BFg6r&*pNu7VfIbI5@> zDo0Mt;n!+$h8Puotrl&hj)e17W1gzyK^+z~IRSB~;n_ z<16(J7$;c5#ly>%Q!@JsjkDFNV1$swoSx~oN4>;cFL8E{bLLq^gEH{A(U)UIi^!3i zhq;nxKNtT1?&D z49*jH7UPrv5l!Dope;vp711wh3UxKjpudZA@i_ro2z<7| z#RQgnJFsIyV3`*t+X`G`%KGfqcnSPhrd&+m2&X`@vkw~_y`--; z8PX8HZ2d*%AoGW<1eD@A4D%>czu=d$0``e45<6gj%M^d~nON2pIX`BST=`0_A*Y*~ zdjc;sxP-tL8=Pg0GCo%xpb>bP!Nmk#VQ@tPH!@D8AUW6^AQZUC;9>$d8=NQbhl32| z;3I~xNZ^keTuk6w4Q|-lu45YbUO>?Y$x74^jydwzR%T#sELh<%z$7vhP_fOpPx2nP zn85NN8*oJe-)`vQ0^ezH#RBK^SO^|C>d3)(MuK6nz@EXy1)gAVMFLMWxR}5(gYyKQ z#W*Ec4o)$I#RAKOHI#`9Ec2RFV}VaIWn%)LZg7@I#me`wRp3zprOs&01W55|iL ze379`2)xkXVgi>LoG0)v3@(vfn^k=75btwb>B&=)%YBk{0t)9GMi)Um+Ef9IYu4KvD=w%V&)PaW{}vTs_+#nTj~K_(DznUC5i93J*jH3Ay> za<#103;c2+)yNI331CwhR62o%UnH@9hEN~0UL)aemZ`{bEp+qRKBqw4h za61!`x#jO=k3<4@!T%BJn20qXG$9zUL0*b{D zjy9v3Y(}p!;@@~r5i0QS3@#?Hq$AKJ1eQ4{;6|K}k|_)-E3iyBP+5Ux8UZ*@;9EH_ zQQ6_@aI&BL)(I#q(V}INL^$PWuK9^~PV;}(u z>QbNMIsupZs2Tx{D(gg*4xegWwkkPB|#~h|7PQ_dn*n+y(wOKK7e&7K1;x{1EeNXF2lt z!i#*ICC(9g$^HFIccSRe;|98j_iK4Cci804T=rc#x#OL!?}_HOm-YE9@3ZedX3HN< z??0DbCU6dL{5{NjnZ3#8FI|M>aLGZ^75usM+2#MMk4swGJ5msG5&r-5w&S!${Es7r zM9Wo3#ECoZFtPm+l!)P9(KuL{B~2^{laGJbY3ylLvoc-~(}V*x!=h>E=nnkH@$Z-F zNoDlPafap|oNvItmIc6}d5YQiH#A?z5w$Nv^E5EDX&PFDh*%f-7&`Y4_@_5|sgw>< z8oqu*VW?zD2Ua|3-sU{*W2h93*XbQxT?#a6U6p_GX>=*a`GvvY8&s&4+Mpz?`Wu{+ z#~d}jq!~*fX;A5s%km|gd*yOU*DF%YCCsj5yJ0jAXgAV^--(6*P)XX*KoQWa#P8HF zO^>0WhT=xf2%VRMKLH>w)4v;`U#ekvqmgwSsF7&oer5sa+{lY_;fF929G%XrCn=h0 zZogr&c}zpG=tim`k|H3yUCcCO6*rQ=FQ=#g*$SqaqG-zaC_n(PjgyIL2P%sLL5Y#-*di7+FQN9lJ_O zBKd+mpnYKziOy?4t#$5f+>%OeZENmGrhB?ONpotI#7yfBa+ZkxHYu_rCU?jGejw^X(eFYnv_lGl)s5JXzov2Bk(0MrjoiJ zouK3B#CedkvNvjR)XsE^`xXeOhT)C8Oz%NxFOxOxjamW4zHS9!UlFy`o%$7BcUb_- zj@}bh_cF-R(K~$I?><}V{v@b#*ZuwPpzhN^Gg{s6_UrC{rwtghZHEnY-Q$QugAYO< zB0N%-?st;O?aj$Xtgs8D%Bxs#3YZ&oU#T%v`co*C_Dk6@b{}ZM8PaZF#4W6p^h7mW z+Kt2jg*RzC)bo*b-3ax*;Z52O%?#zPggym#SBeUWREZ%0{Ar z>4hyxa3jU|4aW!b*+lg+vZR#WGfnxTk!T=m?xszfDnX-Vh3!Y2N{FVsyu55A8ddko za^K6U?o`@rTA#{I4L}X2Gf`7}Z#+k0{wX+p0ii=1wf6`8n7`Xr8r0OoQol+bcO< zwY^afn*e&G9+vXPwJ5FI&YPgN#Zm7`eWva`m)e4Wq281FOx=490h1NaJnsD(&T#MP ze+UpLf4dhv`njd#YJ<{tG!50AYKKCBP1+9GhQ<_bBphEvDs86$Flm~ThWnjcabCBb z9DH~bw;eQe){W%ocU1gTRZygx*a+*4Qz|yjJzrwuKClb7L8779sDd)OFW5;aYa_om z06UuB>mWh<{a2v2^&y`=f`9E(iX^h8*`!bT9#A~GP^*BNFCuDMx`rEIpGIvlis&%# zLqg+^Ky)dx>U1NPA@On?$J)yliSOk!PL1Z}0nlhKlaIoiWXL^0YcCf83P(7Vpw|7& z1>(W|!+P*Z--Fwzn6;4yNuSX?SPnkggHM9mHZ6JZ75r-tt^^HfZ#MDZkAc!2418ab z$)v>{P~IV5nDPQ0k1zUBXgFUGKeFN0g<`|Qz>rtM8?}PPU^3c>C?7Q1K2>1`IFh>m z5wNa%;JcCm>Z6dQ>yEK;j=E#nN_>kFEe=CCz8dAL0AsNyz>j=jw&SrFMS`}NDKC)p z?{@-0cFH*h;2cHcpV6XsA#P6Uv1lvUoh)MfJz2iPxBL+w9|Wjx>I0J)kZxp7IB75; zMfhRBqeb{tz6X;ifxoP+0jOE1l4< zz6~j}g*Ry_=Yvk$C;YKZp{BWDZJ*pNh3NhOnmCj(vptjHnFnx2MYv)$8<@i(%sIf6 z;os1ZKNE0hxWyUo(0uDDiktjMi%S53!nyMpduIsem8{4Rk%l&Daip_uadSiG=|K96 zhXGTpxe=lX_vUitTLTF+d~+jkQ;v-y;hu7dgr_k zM)<&)JHDE_;l^;Z4b6$n^wzvkMHlpIXRj#(=5Q17ISy#788atB3%_dP-fioO+ zw7j_fkUWz~t1LsMK$hF5Jm2z8{9Xn}Xulgh1kxk?icMrcYS((6P0s2))0ETE$TU@( zNS{$?%Bd|5M?*3wHr|8FHl4BQp>CoMZxkCzgr4pz<#p#U4P}Y%!RhSN@JSqrFE)ct z`+`4innig9{Hc90dOKS=+-@3=@|Tx)=k-TwAS4KWpwKpMywyq)Q(B zhVManQX;64z8;)BOIr7Z5J}pHH)`E+{EybUi=d2-goU8SU)H9s3m`$a+##IJ-Ewb0 zQ5`MjYqP>C*_*>!$Zpw7-I%=QHzzH&Huff91LgAdYmu@in1QB8Grz5X(Dg+Hidn zzIDpJP&E6AW*SF=!aN0x?=L?Rv~-FDx_>%PQOeKQBEfEL(k~A|L;OM3iz33`%NXEQ zV05&U`sW0YXrcQqI$Gx9RCo+Pv=l8LyH29zIrx(94Td+0mjCdhr2@9GH_C}+NLEOj z(E0s#M*uuUR6qVliYU70Qigvx5qu5K*wxo>VWAFVVZ$C5W;+bN+Ca+QuhHf5W+kLOd9_xNBJ?Y>qWkxd*ovu z)B2o8==I{TvySI_Wuf4Y#52X2j_2(-eR`0@k+#zh0w@ceVcr}Y#eCy?B<8J`pG67&B`yxyiK1TcMw4|`mYFj0>~^}UYu7lwp{$J};br`f6baD~%woo&PiVPh~K0j3OR6lXsUwayfWe-Ev*dJw)^_e-gJnxZLKVUsxYrAM|? zsD(Beq0#7D$6-8lo(?1qp92k5Pv092`-12w4o|;H^3Mji&GswB;R?it&Oem(?2Y2^ zjfBMEPhq=oy{H7mVHwb)#o^hQ2hure21?lCC=TE6$Kgs_8DJ<5%iu2^hX;TmE0|5< zuoU{}IK<7;PR#w8j>z{Zt)E9)bpZ6m7Jy?(vyaTf8RnD6rIMOTPG1UB1W zTLNb_DETLi!_i`OG=EWB9s-l$+Op{Lvc!*LN%zMRzAUGtorWNDFW!&Fid5vdg1IOI ze}yom9nc_zSvVDkjN!Y$W0O8)NvEfDLb6K9A0f=b*U(r`g!Ef2>7|x*%C=$YLnlZ& zjUhvvFQO$dLYUI&mh|^n(q9>q-*2&`&$Fb{>vti277kd_UmKJ3J1yz-d~ZlrX{9Co z8B6+`W0L-+C4CZ7MObe%a?j4rjo2|Ngmh_@ANx$EcPBWOHnwDN`N&ll2 zb@4GtKVV7UX-Usm(q~(BFCLThXD#XUPExq;`z`6$ThbF_l1}5pkgSW|vZTLZN&kW+ zebJbtzhp^&&XWGDCH*E#dfAwyzhz0M&l-fRQ98+LaYroaE5{`LIZHaN4;z+#$f|qV zl3p_==|?T;hb-w2Thd!B>GflhKFP{;rIzLCJ&cew7QSXlZy1yGSFF0fYSsOiRrgO@ z(%Z%){Z&i)8d_Sxfp8mh|nG^zCDke#DZ#-;#d6C4GY>y?;#7 zU$&&bWJ!O{lKv4(`YmIUe!C^T(vnVdx)5i^{0k3SecZs9q(5Rwztxhy$C93~>VD^# zq(5v)-(yMNX-O}(qz{cr`W{RATub_FOZrWgV9BM(j6<) z&bBfwEvgxgx*u559~qPMyREv{S#__r>i&{t`NLz9K43{-Y)LP*r0=(+9~qPMm}U9J zmgQ+?J8bzsT9!XLCh3Q*y5DWp{dTMFm6r4u#w6Xd>ORk^JFR3AuKUj{=`W8-`V&^& z@3-oHw^jFQOZqEgl77sRe$0~ok|q6ZS1ZP*c z?$;n%hO4{Gs{J?Ct8}r%YStZ0svg(tqDqPI;b|_OF6|;h&s&B!t6s-7cTsOgo#-qY zmeP!}@{V8@My*`;W_&C&Cv}!|S`juRtMoZb`Y}vzGmXsK%o&UHxt8>umUNoA4(YS- zW$~AP578Tw^kPf;9!vU8OZw}U^w^lBS6b2!S<)Z2q~B^;zGzI+J1pswO#adH*rj=q zY|C%5qAorr>1~$uJWKjpR^3-x(u>C=J#IC-Lg*ILr+Ea?N52Fxl zU$vy4Zqw?2liwJ~fZ72E~me{MF zdW36OqqBeYXY9jur>9YetGit5{WsRDbP{Z*>jmd#ZBmQrGJYQ68a6Gl5usMqwb^~Jz4ZM|H&ddfUsgx6Rns;PwkOq;7Dw>h~=TWGUx5L z1w*5lJ?v#oa|Bj zSEj{r%HmWi&U}6j8W{uVQhx$QuHQB06l7wV`@);89ou?8&Gk!*CFML2IPwx0O-I#c-uV1`09?F42~2y-(q^mHe7EbDG6h4=w0 zV3JLGb&FU$SoZ^J7Qs)2zQwK21fC*cp4j9Q}s0CT9*>P5)l(twBk22G`l9j+1JJa3W=R(qV0#g*S z*oO(@^8w)eH89PgQu~1k>vIU0H$pUYAG-{twe-$ZXH$9y;zvEV6K7xi18C&QG#wki z0%i!M$dnpG&$%`O#0g+J8#@qX0OLWco&lONzZOY)p=foT@;mX+d@clyj8Zh_a$sc4 zrZF@Mrp-vd9vGSP)HFMQ3AbFj3n62EP4lP4~&d1G|fK&b1Y=BUjXwgPU@N} zJz%`JUoXPU049yS(Qqy>^}vuw&3Pd(_lNkb1*SMeLvPH>lY6>U2AJFZQjMGOG6qWM zy906N{2|a7S;-{cdrl@n6^zw8KoiF72j*6vGo5<|7#Xi>>HiE&1J2Nq#=NEYlm%Kr z0Um^G2wCGadNeX*=L>+@;iXn8pvjFu~@6gCo|WvvHhdx&!vFbz0w?A#BGjDK{g zTY;H`Ok(_X7ceF^@P?X7tm$}A`qx1tb7)bgwj-4yf68pL=KOuokUx!2Uj}9X7&;$y zT6$9{%CrsfAm?9!=B-df{SlbMp?Z0k7@ilRnaxwhrWOlB9k z&F7n-sRn3dy#&m);HP!&ZEx*rL>4~~D)n>FJmS|2#Ll09q0Q7QHVNyuglJ9&MrMSf z4wUI?>P$N?#Dn@Q0!?Me&Q}8SYDmM)!0ZfRwgD6N*9U=_9g4BrfXReP(VNP&nSSRn zU>*+9{0JC%-VZ0Ry#h>Li1Y7&xieJLLJYy;pw-rB=}9#<Nx zp4YP00CS5fr9JI9*8roRUlk9w1M`UQW$<)%1M{$N!4op#8A}ZO^+1(6Z^n=Fa-q%4x7>XwP$NPtP0r8EH&U1k2_v=nH7XtH0TsRY^ z5}0R0Ijn4hR)Q9xB6PQW9 zEEILV2+Yn9=22kkaK`ZY0WgO`H2(}tS%~KU0kb$n^A<3)k+tX_nHUilkBc>AWnjwT zT2{-p9;`lu2={4l$~hgS=J~COF!O++&3L)e!mI}-p+stIfFt7Tuw({WSh|d|l1EL36-N(?;IK0Q1#-4aYos)4?(wy4d*P3kXY3yoE^~zy; zS4+3Rjhi?3q_)aYM>}2>;zBJw^jrcT&?taGx+Gwb+2Xx%wN__)*Ve|4_U0Oh>r7=* zJu4f#nmbZG4%Qb)Hl@=^T5=0rcwqm7%xLaamDIlznNZ zt+6-R)RgJ&ajtIfS{*(oi}i0)OOFQ%$?93OiER%%|7&KGBGTLGo zsqg4gmxRrvvpH1NNA)^-QmyJ#=Z<7YQ+L-^ZG&WUstM^hneN6w7FI*&6*|^7=4L4- zuU)<}iS@0zdy;KzY&k>Hk}1J%gAK6|R;py-1*N46om6LEQom41kbccR+1k~YOl@yU zr8Di_T^7Hd#`fNntfvJpuJ29ttj6kE%X_GfS~;x4)CV-bcL#J&irzEV8sbo8y(BJA zyL)!PVcTo5{0e0CI>~gZ{lY~HlRbT1nfA^U$|1_Igl3OJic?ic@k=gok{c+(uuNuE zCjw?!BZd;m742QkHOrY-*5R@pYbc6E!7EZ3rd!e7Q{LQ+g)bnSwKpd#x}irFr{&vI zO->RtHOm9Ct9sXTcTu$(H+Q6}x+?m5dQx2(Md0&Ib@g>7+dGvdI@&k)H1_OB(lb9s za%(D+?CjlYRzh?_M_9Vy;!@N-+1#CM?daazi1`QDhRPcZHIQD1Ow|q(-H>X=SuAhU z2i6o70w+htqgZFUBh`s&fg?M#wYR0Qy`!%u+X%D^-$4t1n4FmWnAl-_+~K>10QHFX@rowy@L? zG&VQ;48jGuX=Ty(AOg3htRl&}>RP&r-Q0+&wcxT<=aW>-dqVEI^=s;?RxeN1)Gl9N zc~x@V^6IN9lGRnUbr@$R$;%WXoVluyXUiF@ukn-6e={`4@0L_gSE}Q}1<6L}sAH5I zqrW|(m?bOgu38u7%_BA~NKXN3cwMGrLp!o%W5@cgZDXaq+@8$bYyya`?`}Y-91gz9+4H&y{ehBAXWq+4Yl;xL&2)!Z)}3z@IiZ1uTrQN z0iNt`Ar+gpP=w-jR_%c9&B>O&E~!?sv8l7UqYJ#lC1}B$9z+27th4bwNT0oZn|oCS zl3Pr7Xj$zrqMvw_Y4oU;eX+JLg+wQ8+Oyas8#{Yj zk#W%}8WMfQqMf3zr;IO1S=G_P!_-G6JJJ=Ma2xt;In&+Ij1->E1kyLhB&VjjHoCB^ zLOV@m7**5L-Gn>{TwO;m&`7a;DW?v39D$ih@o9*_!-LsXNLD0!)2XKRmiDHA$Prq} z@->yPEW))K*{CnQ0=}XyV0l+YSxVg0mTF9g{Hhz42{^V8jf4Cakc%aI0+q<1v*CEe zI3tB!|AMgRi_%a=5VmKewsV-oKsBsbw@#S^{bO=7I!JBqipF#X`I>Vz z2+%jEejc4gYZqmA74UF)JK6=>pb9X=N^dus52XY2?9I-wIYpa>EW-nJh^Q*B<129O zBA%CiCrK0mg6>(OqmFu4_FWnyNp^tBmts{iAYWD`lNEO6Otz-fz!D2ZqVqv~HRsC3 z)GStaH}`d<^x&1!H-){Hf|CKqhIw$0-KcC&@uX(XlIZD`MYlFJbs%A&1JxGgsAyu& zx$3KpmfQK{5TyCkc8FsMDo6FHNXDh5M0QgkvUOTjpBZ8;Q6Vb{XtC(20z*@k+HzzB zj#^3)W;B(<`aC13S?4fus5d}vXZ2M6tV#8t)4&x%6QUR6G8!5yefZ)|AMm{j$%B$1 zyK39Iw;@UT!NZ|L_jQxu(5Jdo`NJoxxrOb~8VIJ53K3Jz@VcML(d^~&j;n?GKnr|< z4ad}ir0>b_z!jDF-Alz1lnL9Gfc zB|_H)O-RkB%P6RwuBt-)QU?Zxsh(s@M`NoVdSN`ar8lz$*DDa4m3q|tM|KlztLj1s zqxDj5t<~4`dSq-I;Ezhe14A;SVmIsnP4}g?+RC0hA)~9B6{n`Z!oai{ql1u*`DT(X zsi)#c8uX!2SpDnp7Ycd^#Jtr+dw9@Gx*OA&;g_@n2{r#xLb@LRLPCX!x@|?Z=4(K{ H%=`ZUgl@-D&|ZA(Eyj#$na8-aX7wN9tsP5TYWE8j&>Q z(2gDbvGR-Rv_IV*_oSl*O0>+lZjweM4aaoiRI(yFZsS$}4c1D-#&yt^=lNzj(*=adkY>w@DE5hO@7wH;dXa+=FOWoZ{EE3W_It@SI-Xb{!0!2>#tw> z>u-JQziEM1Ory<8AHy^!HQ(=n?ryDw#>&MaMy z%cVi`_tGHe8U8aJv--08QbzD(=@)v;@SX25t0&7ZbO>Z)FiStz@l5$8J%hzKBwf-L zADh4`K#nFLd4wi83P{>wNbj8bUVLA!Pu)$=mddl3AB*!`349C?3>Dyfa9(U4;e|kk zM|dHS(I)9a%Qhgrv+!H)Ns1f=vb!}PJC}69C%9x>3tS4wwSe3c-t+---Ug)X+kga+ zbh$6rBFATfEr8sUW3>wz4RVZt9B>IB$6hD`a^31ec2CM22kr;tme4cTh5rQfp7&m7 z>De)(V+0VKz49kKko$5h05%})6_B(H(vKoJ(2;l9tht)t8Nr zti4%X*-^@fdGF(vMPJ(*83b{VXs8NLnvQS_WCVUQ)&{vR zG)Y;(Cwx2vd;oX~_%e{ybEe~SKz1*yUyeJ0QWvD2UXWzD{vNvUx4gkV)0g;FFtWd~kk})A5>B0}8U&fq_E9n;*Lvk%Vk)wc|Pjn$o zNz?ut@GKy=7LhS3_z@UrjL;(28T?8YBwc6_nneDyzPk^|#>3gh$}?Ta@(P}e zt}#IB%V^4u84YsG=#X<4xC0QBLdP^9N5L&=Ssmwdl)CQ%gdXX4k$tJ-Ot88O*?nol zEx;9k+!8wFTI8eNh2HZl?VDZ5?n(W-dthT1JU~w6mYiqsZ@VDZ!+;!r4G=!`LN9M5 z{cAvWU-)wn$gbrmV^Bcokv_UPmT`)LW^2SQ5*XOoLF^^w%y z3sRpzN>TcqrljBhu?upQ@k>}Nv}KU-y!R;l?*+Nnd)-TeoJ+qiMMIXhACUSo+C;Yg z2FPfTqgG>TMSr{l_%lFcP3B)YicDtkau?)UPP6pvC}V6dAo#L08MnP4_j*Cv-g})=bc!aS zTjJY*+$>XHr)Nj{u@CvTK=-GTN3pei3*G z5c!n*GCyT$lKvzhIEBYzlL%Z3T)qe-Ed#kFGzbVCVh;$NGIxBW3o`G>Jd=Uk%g*Ka z=UrHwCUgkAuM1c8KvsY6QRo-Q(u58f2bws(L}q)(MejIW>Rf^!F9Op483;W+WGs35 zXcvSI$sptl9!VDZg!jGmoi9xp4Vju3zGgOv=+6v9uL_8bCLrl@Epye)Kz|p06_D#c z2IM#n2rY6H_;Emv8GS;t*pC?LfaumB-Y=W zjv2@;ITsoPWS$TZdef9NE$chsm7HfsvCHKAcHqr`+`AEwv~12?56FBjAY)kU43UAe zK~`4yA#xzHB(g8_hRiPla(yn4Ia46ZCwN4cW$;@-rmy5E>DjoEqqIpt&aVdK_$EMP zML_6~ql{%aik^@(Im)$woJ(2;k|zBkAoNHZ#eNoFJcF!%vg_9a5);YNrQdD^Buzl( zFS!<-C3ducoc|P%UZvl?`d9i+>hFcDKA|atEKQD5kAR#DP11%x07R}bkn6?p^dk5Y z(3{jtgPe=(W%bKZ>JyN2(P1KAqFY7R2*|kqAAqD~AlK&t;ZZNhn3b`afz-DYd>fFl z*LzQF34x{3B>k&hkn`n0FTU5#U*o`Q9C(cb=gR@nf1*zp zO8JIoJbJIGi)7{XQ5hwZ@|+hE%K%A1ur7cDV~1>8r<8I=BUj1^B^f;SnM+-6ZW9da zDqB8SrZ(e;$eX-SLq$>t1;1bBt7;hy$zTNDKrVEi@%(Aeu?U{s1yaXQL`OliwJNSj28 zg-4}kPMBsG2P*O{h1(^I!cD(Hwy4}NpZonEkXtJP7bIvYgL}F;*SQbdbdX&4XvBkdxemi_DrCE@hK*-;mGzsysMK+ix~+Ud>V zj?Gk?W#~CRckr^FtMffwBotY(KU{)o+7`$%EaTWY_WzzE_i4>c6Excv7k%tMUC`iv{BxtZxQer1pQ7s2Sz02@J^79cnC#9_-34flQqEmWQ--|r);DLT%RYj0 zk(k`RjLMC|6zW!()p6OBvHEX4>y-f z88$E_HO5kTfo)B)^P<8iT^2NAm_}zVN#oDE%X3?)S>w@?aawN_*KZ~R@@N#wmDn`= ziWt=+`Fh$pHU)|vE(}h|8q3&_%p|%ciwoTFhM5H4Kq{h$yCkm8ga5ZKyNoYtA3&!0 z7sQJScHTL%DCImZA+pq!@a)(v_3B^dmfP<_+(52zxR|1V+Ftmg{r$a{=W`Bq^j6wj zY50ONogcn-!S#7v%(s`5Mf5%TrX^;zb0Hm|vGT8B5eL`*yrd!nA%c`TXI(KmcjBR9 zJ+HZ$Vs=C-5jdkOZ$@YPu?t6TyBQte(EfNY>c`&ngH6&ejBcZz7opdB?sU|hZ+xNj zrHxNSM{IlD$Qyl6zBg^Gzj9yYjn2kfUb%nwyUVk!TZ1G0_PQ_poQo0_ppmCR=bQiZw6yb1Sd6gq z6SL=CHp|$9Bc-x?qmb*|)5kX9si^vEwPFTkj+=QKEXItkCc z1cGy1sI8Ez(n$L{Vv_ga0w}sDmw9>ow=sv-hr|U8SP6}<8)s5-6d~aP~viV zcD73Xk9OwwG+|nZpYC7LwUQMRSfld~extEsPEGMIK0sG5Hnf**nV++O@#LSa7|q5C zj*LR?v77TN);Hf%%A|p+Kh4a&$i&X?d`mPBw!j5g_gKlP+FG*slfUu$i!#8^g8K5; zYr|Vx){*ClEq>MKu~DCh%AarD8~j?oeakB?@7?7u-Ss&PZ}MV=Kd^P5$mFC!r&6UQF z{_=T{f1X)hv%AleQS;g0m`sN&11qetS5C&Tl~<;Pf(4c>GmvwZy1z5P&F@{iTXS>8 z`uR1x`+L#u4iA6+?`7Qk0;29`jC;TFFIQ|385gp^c}5L)Cd2!T1yjV>QN-^}U8$TQ~-bH;mb)wfHmm7O=p^4;m1L`l5kx|R1- zmPOf_n(*|;m%YHRcakpI%Fb$;;a3Qd*%ce--&2$2%J6@sov0PFyu*`!w6Z(x{_aw? zQl@tySNzUTA{KwYY;VVSw0~vS30JD8!`z#HbwyW7R%XZwmhZw$zhr3nA`^*BL+nLb z@Jkl|?uOG}3wlextqd^3tk?wq-B=-9nO1%`M&x43&K*5pTtcop|Kf+2N?vA~m*#)k zT_QfeOjL$EWF+v=|6GpIot9bj-CfWi^*27U=+;GCu7GwuwKnq8%U)MGGvzBl*gSHv z{8nnFH17DVm7T)psl3>emFC#R(lcNFHNxguah@k|Y{lf&Ag;esX18Iy7V&<~i9b&v zp3jz!|0QkPi%k6Pn#MHXBI#SQxbx`8FL}-CUOB7Vx%~~V``gf#(Y!#P_epX4{VQ!O zG?p+V!zI$rMdPD4Eew-N>oPp2OwDs)$?o5J`AWAl!+ep)3$;B;OR@CP59cqEoKwYD zIvRNj^D@rgNXMC@3^IqBQ zCf`e2*Os(HFEa7FYkSM2agh=EC5ykd%lq%$F7Nb(RZGoCOQg-4uAQGg-gEl`YS&6_4cxEF0!%aC2(0tvdp(` zK4UAhEa!dvJK3QVuRH(#!Sin6IWwM#1?McdM23|V8t3UVY=hxNkIRS7=YM4B zLcQ;gTRO)Qsc*ey>9>Jh3~382(e7GIV+U=$h$k;QU;Ra)eo53=BNv1DhLfjZKI=o7 z3uriNPBzJ`Smb-;Z}BB3E4kVG&A+n9!s-g)@{Je@Zh!E*VlG_JeAjJ9dMLiNiWH`B zA%i+An;vhyx%b^<%hupM$asOrb3ebh1C+tf4ahcz)B2!f^^`rs>Aia{Gs<#LQJ%I& zU55oG7OV^5$!W?;Z-z_R5m#_Z!>;*9?muTsk@GMb!anh47yuQbU z(iktCbx!BEzM58`r6Q$|g!z-jwV&hq-d{+Al%XY(b_y0;oJu~&S!Za+f*coyrHi8T zLm%p%T@;!W$763u)ul#Nu(A%wM(hHr&*NhI-Q8^(p%p6m$RHINQR>26`tbR&?wc?d zO4@}ry)(P3D{@jk0wwYh$^Ut@ZHX-5$=|vnO-|bf`*`oSPzru7mJgldKiLhBg9x5E zn#7ce7epk__76dZHq?L4SFvq{yH)jIC4EmJG(xX`v2QS(e@{y1P1mPwhVYaHVsdK2 zFNht+?Z>){1>lK#Md*S|S);S@8%7!gl3t$&jeP#<{7;Q}~}KXLOppMJc{!)}v>E>0J)b3XIAPdc%FY6=@y_1e_Bf1^h3 z;ww-`|xw+TrNX2hq|1JmZbMNb7!|yvK zaCEGqE0%+(%goN&BMaCHmaRn#i|ZWnx1i9ei!k@iS593qcVm|$FcCkQDid!C%M-)S zUuP~|s6-DS)Y48^DELGG(f-SV&Odt3eEuGmfw2qABCzv~XR>nhN0`@dxs4osq@e+o z=M8WERys(!DgYF=tmo0njDhEkN;2N@YWg~>lwrDC9_>(#la8YdIWyd-Q7j)T4qVcBzFa=*%gg6Ye?h&}+s=*K z|EfDvs;X6REUejr!%rL8Dk??F8puT$xC3Q=SBbtjR7~IBeV**<-1%c^PNXEFE2>~8 zY*ms8L>($(=oY5=DJ4?$yU@=Qt7NV|%Oxx8|G zIaG(a7dOs}C4}>-CXB;^OkvmB&G=f|_REJPrXA){Mu7p#FubR@_wfDMms z?+HeU-@xnSrH}aE0fU9YfjCRiM`7N1LTCMdkeswszZLQ6ibcb-H<^RlmCg$fUxQQ_ zYo=Lrnn_a3u;)C(`A`2li5{f+;j?-dO#llMNEI8VYGrjFs30NBN8fqJf9-7nZ~vzU z>-p6AEr=C!5$}5pPk!L%U-K#cGVO9Sp9nS5!n@7&XKNWLsPl^v>4%H+hVbOW%lkEj z=xnGvpXzNp^Q?M5|z0e zc=BX-FhdZZP~=mnl6f%Ox3d_Z<~g-54V|C+zp@+BNCw*0oD03B2nCO_pw-G&hMnLj zfT>?P5TF4@oSsPvcXVmax`7J0cl)mN08}|O1Po3 zrC22h33dwfK*IU0|9C#ENCsgm5 z5mS8BwB_^2<>b|WacS6{NaVJFt_7rRqcG=4^ibI}4=hQsOCD9pSOO>__ZF~*WMy1;OmeBn*i&Bh{A zLYzh+Z*=~sYyB*^MHf+tAfG2}F-1~8HEYGPpezjdv#%^lNhL%$OS}3laJf4vDUD3I zfaGh0X*upA);$R%$Kd_?@14R+Ijs*g-_mAl>FVYXA!1l9!n&aMbk5EV|0cuP6&G6F zP3ek+rURBjEtTpkj(|R0NM$1FoqzHxauARqi0;t_3YVNg7A~h>O!#BarkHeIZV9ri z=cQzte(Kx#%TLZ{m9{YorHJlt0-l+we>}KcpPfb3sUN;QG1M+Ot zm_nubIW!sP_2Q(sDq>@1Al@_13#HPu5WR*}pq+amHp1us!@L;?;dH+8MH_(LHA-lf zXoItpfB8e93GewAokiYA#7r8jWky;pvse~FI#tngAMYxE2<(1Rvh*cw5UWamY&{`# z2TGb*qmf3;XF7$rkf#Ot!pS$;MgqU#@(*qDiCl-fRkX$mr;E**gf_>jnrGY)d9Dtr zcnoL7zg`wfMmZw~ZcAKM`B7EM-RKwvSxOmGQFxcaJBo~M237472jqZ*r&C_|i%_F& zh-l?YC+~bTB@HDnsP#dtb4cJLO9)l|;eckL*xa%PkbR^GoP`=Wkt3}Zx93!^8b%9F z^8bi7ekspz>~fS`4A=ROU`zkI_^|2)C!e%dM4@Vh&?A?SN9)AP;<5`g3+UYQ+eTBT zP!F}~4{ef)bhD&!%xe^s|BmByYthXCANII>=}Ixqsb8F~dFa;i{2!z#bg~poS!d|k zThrggW=D-&q)J7RW8r1mAijmHc|HlJwZk}Hi$0;M&cXd@8Wm`XGQ>Y^;6^cc8rLud zHp)8`J{!nOI~0n$mm{2~zJ*SuR?TDGvfi4co?1hlJgg@{lSC-+E!LSK!Yzt_YBM?hl)2M zuLED2D_R53M-h!w{74mk7o-g2-X)G#1Gz_1=2B^KsTse9o_w!v9ierEgGebuYmr|j zRsQ*3idmQ56Q<)OQC&_1Cy~x+-06@iYe`Z1yH{nOIl+72I@P{Ad@+-cZCaj zDf8&2%le=BCr?B#H1BkudCL>g?&kf`d--vv>-X;G-S{s@&Rd?HkRPYI)8W|ie%9%K z_WkmH{QhUJ)4xwO^>~iF@NY4SO0R=I~JkY74PRqu3p#zx-+ABp?NYb zy}OyBJB^wY&5`~y6Z3N9uTP1&Qr+b*pyr8a*WUg5jsN|+P4C_n|EB!p76<*#|Jhd_ ztZb7Xy?T+~uS$_rw!O6DWQlI+fl`coTp-->KYI5&oehb|!a3lP%P$d0K{2Kiu?!e~ zGLXp;BYehD1zCiUpq=VZy|--MB_DEVXe$^&5}`!8vf41oG$e2RgEY?1e9FA1HI9hC zOg@pNFI{6Nic*q7ON6QiBo(~+W>2zVtY6oANwf&X2gwAx$nG|Z5N&XQI#L>gp4G(? z5mXY1lvG+Ex4RIh$MBvT@gu@~Lf+A2v^IL5WED#xHd;aoBt{U-83vFp4jx;6bUjt* zNi4og#1IprQkE3*DL=T*V~oa)+@o)QJ$bsI#EMXPCBqU>DvGIwk;tWM1RET1m2wG6 zv4k@zwnV{?iCZjouQ;W0SSkyG(&e5lc;?Aga zjiV%QTo83GGeN1SnMr8YYH$kU zY<{!Va-^M%|h; zZcvm_MR{8px+esQTyJoqMs6xcFcG?CwI+(>mVnzY)QJeaxt-^R;7Y)yrxq2>Vc>H= zPC#0qgE*$3)1d}qbieMC2~m=wmZFL%?4u0;^`)#m<s0qdrQ&Ai1S7qWuv9n4G@$10 zj~bCQO@t+8$h!yJ#HQoo1ManGj9Cp-n8j6#<-DWCQB}y( z5M(COOM0Vf^yn87d|?+_t~tnZVSoNH7Z)f`AK9aIYLcHh9zA-0a-ae!jZYoi(U!*^ z@OUTMrISDU&%{&Jj@a>A)M&dk!IySkTY2#a6!bquj;cj=z1}ANY}HCVMe#`oisJG~ zPGfJ%(JAp#jDeFVrh(!(2oc2NbxRNnJLF$hspQh2%6#X}Z=RyUwOULBC=RJa zJGDluMsroib*s)aDnTwwSqfRaC4$Qdu_~0A_e1 z>%n9(jN=rg;(=W_w(dxTdz_G(&P;M2O?#)C?|h3`b(}=P@p(-aTDs5leoX46=_i!% zUs?`5NSyvp!x>aUjT#iQVorN0^UItFmu_Op^Z~isdC?zD=*5<6?ThlL))?a^S!2cN zX2KBLb6ho`5I>s+jpAt2oimAUaG!CbBVy#|Mx6nZ$wKdNY(sj-S*=-5jURNw!)5J# zukpcC&)ZaFPtgwpxy}cETDnuu1ua$vlGd+OM1p3fA~bdq6($l{*0lHSsErRaqqgKmy5Z+> zZy`W_(oT+DC;5&30*`&o6VaWUo}KtB9DiKxUzDGvzWy{Pc_}Q{XCC`oo~`l2&u`4a z2WNEHaj`Wim2Iil&-GWI$lWK}1fU1HfHb7GP?pf+en)kpSX}GD+`T`4o4Fs}vvy~6 z)^5xSr^jgF<)W)zY;voz@czuMnI=9aqcwDEx708me1sJmaZX}Z@^C%3Mtzvoh;O2* zZA^x!^g$&ukKbqK&P9eK1wd?JWk_ zmQ2`UJ=w-%pJ6ZoxQWW}#i*4loIRr-V|)(O2%;Sk_SqT90A>Q@TdQ8lXs84Dh}tuO z7Hl>t9%7eZ>tR-C%d3>Te`9EhdxbSt8?S|`PtFLJi`O_?Puva za@UH5TbO!ahl7$Nb<7&oT0X}3g9tb)wZmK3hT$q_F^OcC$bw-!P-fs8BRQj*uiNcn zVB*j@lND%2A9TL@Ef{7d(hW$7LaQbbT*NZQbvLCv20_8;E7Wl%#YNpItq`}8boRZl zhO4$l&g$``P*-fwQnj|Nd@Ly=yn8cFd7ZUbEV;fRwb=oii(0IkXeh_BpWBx!OB)qLb(eNC213a+d2VLrxwV$i@^^qEU`VVPr7rFEkl*4#N~7Y$Al z95^-VCv@a2{$fkHgau$A-vyN~m2q7u*?HzV7%dIvLXL2jL1P?P3x^?FdXxmI1P}ow zp%j@mgimpW<|TvS!#H?S2uyvMz;pzSjxgd!-h4@>8d5CNGOR=iC%U_1@-UI)4Xj(~ zRM-jdRj61YjTwaoH!mi>rMAl4M*(h9YwV>`U_5$F#0@BsKIax#xPS%?qZ)g9E|Wrf zCbB>QDF?#P$tQ`7P8QlDnw!=ka%=p;dYy@UN}4G76GO!!jX>CkGD&R#z2QmHWKo!c zxYU*b^-&a*a&(*Ah`j?rJd3@8Ayq51D}6eYWjy(nn%UGv6)i^u3Tm}P9cU+mSDg14 zMoZrSFptsStxbu?L0|&cZz>lBk?5I3m=j20CoMq)qwvf>l*TefEMt~iG`N6}aRpr> z$MfEz?lsU0`|yovvW=fCSM+XzL6->TsS1pCu}8SAq%JlHoV>&bEjX` z+D+gny^gL)>oMFYCR`9&bGpxIJ;5~`zbWE6R62)X#K^RiH(orxN|0(&s8?fTxY84` z;z|T3k$m&el>k-3>EagRLM~A+4Z7XMp^%V4JUhdHBx~nNw_y5`hYP|XAl3+^PQpB* zT{Iwwx`AM&D5@nyP&9$4|M*PsC^;WFs^)wMcFj)sjt&7v=8%JPr`hZhSnPUax_f@ zKlcY+Kz;N**Fm zLe|!zv-+7@ZXY(oEMbJz>c=(>)%vzZNpa3~ZNRo21i9wiP%Tpfo_LYFw_3_ma+!v+6j`QFjV!2z?Hx0C%W zy(Pc6nbm73IJ(7J-h6wsE)?P3xf9Bcb*6vet1q=H(3C#yhsWHUN$Bal(fHh< zB6-n?_K)A~PZk55A$xkSdcywkw&6bThDQ73YWI-Gmf)fl<9v^{LAbBDL#^ILTh(*r zJL|IM&8m3g=(XEta}Cxi^Z0O4=h=0mleevEP0$X>Nvw6WeY{UxGuR?+%a6`+P37T) z(nU3`?8jm>`1uDTMt|pR>bKH*b&08>mf7Lqb*;VT~NyX7u1H0nZ zJ-+{?_Du@+7*Fsxy5Ugqp(t01#_`lcYx};}`M33twdp0~4c$s9it7IArHk2IyyPh( zr3}Z79lz|0j%a1hfHFFs5P{{wm`IZ)UcV-4^h7CVT;Ym~osv|=z5oHNK2Dl3EPD!U z{&8_TAA2~wt7)RS6Jiz+VBmhsv=tkt`Z8Y-uC*k3BrM|qHbROi5*mg|Vj-GZZHb%c zV1fHU$}KhAgl}p0jj99g@je&37LR;%ifTsbAz?GUHh#z6obMyw3BD>rOS1HSpdV&Q z*f3Qa;+yli!ZDsBB*K6jg}(^HKu#pM-5~1WMy;Tk1C20Pc;Oj5CrIHS9Xq5ka$7Wzmq|L z6eL2hG5nIt;` zzG}fbxuwz_;UW-FBw|`3Y?nr!JQ3+D5RxJo4;7~**%cba3^4+N3C~A*7jr5fL}u4-GmpW)Q$@Q<)I8mz-DOhO+}3o>NcWg-66t9P5AV2?uOb zX1&5Vb=G0bGZhOb9v+a!i$Yf==*&oe)c?$S|04*WU2=p!i zB>|PW$e2T@8ab4IjCrCT7i|c0Aw$ec9fN>LNP>ihDS#hku%?#cX%QM}Io3>4s_0dh z@Z=l6?(4<c zkN)YFg*z8ssHDsMHwaDh!H2hQhZ zfDw$!##N2u(V8N7k!V{?x!65!h{Q7h5VV4tbHt^OW^gcfM*Tjq3B4e0++eeMq|_#C zW&V=TsXLbuwoqqRnbC1W%p zHP>?rH&19FgWd1tMvBZrs*kFuBNhvr1L4?921{v09>Lry-OtZ*pXK4MZs3~Ig9D3u71hi;*|e0C{*7CDoEBpmE~ z!=`7cI(+%B>xNIR0*DF{tI#FzWHqa_-=3x{@vVhn0r50d;9vgZQ@J&zsOrWkHl}2f zra`(yyfkS>3R7f--Z&tOGyzLYXf1s0!7dJNc1!y@XF_`|$;vMHT#7^U$tYQJB~+20 zHuXSOedmie^`u_p>EG4&#{F&l^4Nv3?lq1rmv1S@GOLAMlHK(r21*0r&lX3-@L6c! zoKMy(e{OyU_j2hvE&ocs`0($m0Cxj63wa~mcG{}B#t%J+;bOmnBKH$TZvJluhD zsc9uqqv_O%<5<;?_>s@nAm&H2OfYti5E3)bXf2U_f?#b_tXb08F~aHs6YvavFlY(N zW7>%=Qu5-;rhudkfe|z=30PmXxpdj&q>paXPx<&%wvk_)$jRgt2YQ{;yy>HA{vPV)yGf5m3{OHoz zLTwLwpK<0f#+a6|$Qzf?z9_U}YKH4@V`nqL*uj3=@36H+w#6k4)0-k*j@C&YbIos% zOX-=tV9ioUBGqB7U94^L5z|pIQ$yeGi}ggDVB*k1rhUqb<)~eFX(om)m2!V?g%z=U zQnK>~)liCCd(Hb_B@;Xb8|{)bU$FQJ^F|U0R+s57C3NfFH$sI~si-RksX#*u7#k?{ zI+lTHUoatRi`p$X1-^u3@ENOW^xDCg23Sv6}}g@CP_ zVg$#KD2N2~N=e0yzxZTdiH?CJT^`9{SzLj+6mC|W?h0Ac1t5|9Q>iu9AN9J!)x zR2;>P+>GOv%HAb#3uy~$wfs=NKfkxQC*HtzK6?WTwVhk|jndGRqV$-o(TM2}4xbdZ zZHa466rKbirj3%5N@X!HWvafz7tz*$l^r@w1PY!AU19#u--lqE$W(v|3B0u5$sYN} zE-=d8PmK|*5+smHC^sj4K_h6aRNXL#6weXZjdG6RpR$Q$AbDiqby7e&QZoh$DJMWd z&g4R97OrTC*XMAb60-&0gzn^kL#`6S!QN+XH?-&)k6f-1lAxE+KtjjH;iZ14@5{iL zvh`YwU=|QklXwpKu@Yg3Jj5_nWT!Ie8&ceeY8QU$3nf?HT)~DE6k#6imUPEX!9}G> zn~VZsemx}9GKrGE^jz18?w}SJ>q%{l;>|A0A@mq3C{KsrLw@NKtH??rs_?S9eNIw# zNeUhwgRm<;q5>gbd_6dZ76$b-j;&X|C?af5b~fdk77}{?*pF-=vf!*j_eA^5AR4MW zH5abX3nEE}%e!EUoU@|1x3YR7LH|2U3^=$_0jtV}N@O}vvKA|`3b#;uwpJWZ5MFfr z&InbV?{CMSNAJU3N)6a~kzWzv)}3FoSRXuIF%JYHrA!gChz|9kaLDU}oE&A#P*M%@T|2cM_g)aUB1!$DSqEjy?B^AP#uyqx%J>Kw}HtwsZ0uC+MjM zyyIgP`vGrXaoT&p`--EA?kBzB%KPhmYsTBvzS2Z{_|htibJekCIi4*QpXDLwi5opf zLXuujCj*XFtc3YGrb6DPv_vH%iKlgdsj##*#ZZJGSkhh(06ZKZZM>bv`RjK2u zTqg)(mO0|$bH&3&76`5zd3Q4W_{QIMBhKG<(EWPl*RQf$`MqWKQtdsg?1z5gGNm31 z#%j@Hfeog|gR%OMwQsDpy>i4$l5{nNz^zBHxZj+-t>4xQ8*$Z&k6SZAe8?j-%et`+ zm(#0It3MM68hLbJnb`M3F=1nt45q#7ULs~Z?LE|N=1LV7Eux9GgouUIo7(a4k!v3) zCc{U(ewT!eveaQ4_s9K5Rp+Xoz$!_qZ?8PptkkBVjm481mkdfBO=p4tdqLZ!r>%D5zw6#nil!B@>~kx{5U?7CA)EA>}P777Yv~ zp=Hb&;cESOTP!(g11n;(b5m9sMo$Kvt8ig7aRVF(&`xGvK1=I!jEW$}X8cAMh~xDCgpk7;qbz;S%F zsj5zejk5$_S$eD0SV>^bFgebJs}~;fqf;$;cohWl4>Cjr`jllfSjJ#Ap+s}Bny2*I zi1Borpnd*O5t(f~kBF0Jzbrm|@vci`H)hOL%-T=A+8S#|aIwy_g2!c>ZreD1%X^IK z#Fo+aY}MNDie&Jz$7GiKEG@*?|!6$j_ZH6mS;hboumAhbDe*-KV*q*c940Hoi;7is!Sjtv+HO%=~MUz6G@r= zXK~wN*JM#X{4YF^Or3N;>GwIG6QzLylW0o*5 z=H#=3Db>k9b^grbqx4x(EKJp6DLM%I_5lmJkjBtWUk>rq#q%p&@iOdGm_4Kc+zd1Wxr&)Ns*@$<*CH<>BMxG;(D%^ zcsz0bxx(%Pf!XTCd2CbcdB|}dOYiDM`mAKOoRTg%3_p-QpZHRclJj`FdXeqDyi%Qd zT(Y}u@=BF%1nq9&Jo;-Okan@Eavo18UiF71v7j5C*)R)}l}H7c5n>S0AsSR9hlZJ6 z>2C&vVs7Wdpsbf;{tmO(A@J0UZ+N6j2q2jMNSW~Dx7h%{7_g&DWKK;sEf!f05fLNx zS+b<=v1_Jxe(!Bh`x2PnTH$N2Im;{_@ljr43|Tmw_(+K{t7b8C`es>MbzSzzu~^V@ zCK9HS{#u)YiJJ4~o=$R1vzD}z#ka$t@o>b_U|M^OVwf{M8p; z2kG!6+2CsfJSuBL5o-s32#cFWX)6t)FvE%P8ZDoFb%p+lbz@O>zKGVN*@JmStXwP* zg9qUl5~$p%+;DC)+?Vx>FaDG7qkWSF8;;ja%t2qujm$b;Oe^cQNi*>|`sSpS_zC&= z##)TeVJH?;EHxFg+b>cz)fWF!?{_k=78`hb5=V#|bh;)SPd*mAm)6Ep@nmcNuEqCNXaCY5tTffNvE{R;B2~_?2Rn7&z#%4YwylukzJ3Q7|Z=_wutQGSNB>up37k)($!9*&(wW$Aiw7oA0R1zzyHHG4SRT<|H-GCLYFf zq{>kldZH?mkLEWk4D3^kl4#$mDSHz-zLsnV_S$oPBR6uS9I(+QK!S&efb`LH7_#r- z;P>nU!2vh4rgp33(a(Lq`Wbue*xKq??Gt0Q^3W}{=uJ&E{SB6Wrz+#YR`b1{Uoh7V zRn|03mM>hdd>|O9{83`BcC5MZV6gAYwWeRe_!}J>_4QUaXPcRn9`-|vKeiL`h|QkL zl<7s+-)HRihiaJUb3XA3%Zsk?OP5=XV}ZKSeZX$r?N8L)&qp6|A9IfdCqCrvy?l}d zv*()EsN}7mczt;gXJXt}Axhu)nALj5FFLAru>XKFxY-WBUMbf6hy8ctB9~ndROvVm z+oQ+A`^=fmv2nN_U7BFj?lqM%Y=sh?Tpxl6clSO|IY`J3r41mA7Ji6yzw!1#-(d)+iPIT z7py}(Op6bERe7w5j1zDv+YF63VH+zW0dI`QK_giU8s5Redc`bZNhy4PbPWz|RyG!H+$3 zAr(t_4Ca-I=rKVtFha{<(S{hBNH+flOI>|>1xva`=T=5D&Vj1L4AFP4$ct?CDOkvuG$=;falf839(nTnJcfmS zYCBf8Qa%rGNO0EQXCo(ICS%KKn{)%)pv)u|zBb^g$Rxw*fFFYi{t_=`rr23A`l%YL zC=AM7UJDP|MS1s=m-vt>@67edooJPhBnH%go0teIIb&akdL;_}fqgU8u-ggH*wL325l12^(p0(z`da#6% zIZn40Jmxm04Z>2?Bz~~dZ?aVk=@_ihvFv|jFKjYv_$`a&X2rBi=P+Wm)KHaYAYld* z6z2pWEz+qP5?~;OpZ|2Z8LkQ)*RNOwXLUZbRkvTs zj1b6|MvDhgtMR-AUBzx1?1{+QTG`WtMGbi)G=74R1CI%-)E=35{e8+T58fO^hx;oP z`yQ{dYP(k)-$PK|nlvWW;b5m1N6#C6R916}B6D%n+TDy3ERYZlZ2EHsib=siMuCCZ zqTnpC%p{rG-Q*Q#?c9)+*e=)owM`DYLvJYG=-PEJw%M0M_so^_1=_D!_|=;-9>q)b|9v7cr2%Oh*pYif*ohI?D{h^KzqJ5*Nh^-!RjywP_? zg>i4a@2T6&nE%j8JVF;t<5(dr$LBe$t!4s469nRxsY9L;UynVjI*&)Z0@s2MZ(EsY zulLzl(|&w&Icm#mOq}WR{Y`d8Zr<41#2qjlVb6$sHRRtTDyuMMqBm9_z555NWA}v< z)3hS9w_SO^$`5aOdo$X3bnxGMzwTA*ec{-#ax!=5s`bHt zac~QN=q|6aqush}cr3Vn?gnp-8aoo*kyM&ICwk(sprSa|OSvhYZ~eu(DzfuYo+*`I zs~{@zOU0u{k?xz0|T~XX0NG#T2O18ngSd$n)h2i-&Jt#7}K&BGJZRlD+RvSa9KrtbH9<`tW#Z?D*uS|0(8 znl(N6ON6d|>PXqRZ545hVVYXUA8ifTUv7_04L!&&be$sn%=H=(~_6OE}8DIinz z$NYxP&e!7-P9Vn9I8x*ZQo<~JKeqX%6HxzvXI%HuYmcwiJM(A;dk5`e6|?nrk3KJ$qY8FP+$N^Eb*xoF z7p;614y%-%qfm7fn{W?Z%Ok}QXbhV?#k!*nXAL0_>3S|EboG+sRwa_wzbAGo-?`R6 zTMn*D;>oK$@A%E{EDsdFj<%KOSwg$nH2v}@%tPnN_D~SRx_0$5*zH95s;dd=l-UA_ zqOZZLD$3tNujoEzs)1Ylgk8xbod-FuWdrf(Q-|nQ!jEjF%wKm2;hQLtU%3nOl}E4n z0d(V9tQU2}n;M&}T35Kf2p^UUGS%AXg;!h}I?TZmC!-IltAvzkFNBigmyNc4>P5jP ziH=aUT%KrVYa_i4P+z)Kr0IZE>CNIH?=kGo>1$(sVwG|Scm+xA#i1WSQ?zQgOp2IH z$~IF%mt{0wYvO2`89Iok%a}(bq#@0>d%_g@m5FY;Y?R9qUqlTuJy95GqTBQbVbZM~ zRYDWIA|w46N!-)eKD%Q|UOYv#rk#82qw?TseEb&w00R{9V)rXC86@Lb2?$*}+TKsJ z@|F)6bCOmgXoNoY2S4N`t%_|PsDxuj%Hgr5v_4TpYZ^JG;g(6b$*4ZF1q{T;+WHk% zdLJ?|L*@~-v%2yCH9;f0MGOqtA-dAKrOpQ499zvFD5}o?{%GhT9pDSp-GMi%%7tf! zabxmxHNuxT@7h*J^b?0u|iwZ86llWa$^8BvwKR4MDXavNRko(3C=&IFQ8|Atn zQLb54kPWm<@v|bh2VB&z5se38slE#VnvvO)IX!B;e9Jd>w#!TkjU3~4kmyrcUXwLx z%-k0k%mXzH6U-KZL5M9k&bVtN;8~ckFJQjbK_xHZ?O5tv{L3qgcScOuSZV6y$NuG6 z0!T}|-fBSrsk{I6jXt|YlNUFidZ*MI{WCr2+TCrsM8sy~N|kO~15kmB=?+-c-I05x>TZF3V(X%y*4eh?cHi7Jzx}o6+1sPv--PFe z$6!2UV-Bi^{Xs%V4SEB|!tg|0FhCCYo@6tyUV;dg3lMD@ugSJjY_CGwoRc{g<&a1@ z27WJWIr+`Eaa}?*mJi*UdkQ|X{jzq5;$vTc*$)+KRdr%_G{+;6YP3S-Z>mhHU1geh>5wyHeQD)0_erl+CDa&d}vd2$$mDEnu}W6SNi1|h zMVi4MPY~pY5579p7Y4;$l{HrU58S}t(*6NQjjVd}=EL4`>l2$2XWzq>QvAB=D|U5% zf-8Ob^Oa|t)`6nuSL$0Q+_j$dU~y_p9jG+N_dUF&aX5}U{nh%VpnSfDRtg2j}cT<2SdqZ@7Fk87Aw0O>u5{>R=dotG2t(H_^x=wGRes zzOPZMy^L?*MQXVC^1 zI{P3Wkw7s|e$n}Gj=O(;61M4@UBaV8i3o0oWugUt-dA#mgS_`c8ZksTzBRlhR_Suq5@0XGY%Oc%p*QT6y0_KUA_6DG5f* zvam#X=;B@CGyBJQbB{k(GiHOj6(l#R!nQh*~K5D?KTkjdG1q${tTL*KG zez3x5uhuHAJ+{rSn-SWPtqzZ`wrkF%*B|l90d?%Ie7?BRd5;+d!L%ZH>IVh8k`!xC zZRW+nV?o2KU>hHD8FEkFU)|b9t z|5jAK(ctNP{~&YSmH+GeN`dLeUYTi>m}$sXEI(S4yT77hddh$YeDN#=Rb%iHEUTM` zg%%j1MtR7#1;e9ciZMEt3~sZSwhO!_fYqQH|LhQ$GGp7Q)r`_HUz#6b|4oi}{?$$R zvnssHZ$>Zk$k$rm5AOFykBl~zK@_aah%F223W>>kI*37UC3a^FRd{$$K~QM%DeZ1v zMFiNwK*%%SG65T|R|(;lA}CYiWf)c0n(^Zefr91v_(1Is*AXE1?g&r`CVq9> zHo<3z&7gsKJ~ZQaZPWBf+7-c#bZ6&cth@^E0IBN(=5X!Da1Rz#)A{? zXb5i($B1XW!O`Ky=H-t$byb6QO43#o`7aNnGAg*qoJTEnO+%cMC75$jfwLO=5=pZcvzi| zk9Hnwcm%pJ!zd6WGqvzL>;Ge+f@Qds5ewNvW;yiD5C%+R`ym&3mQeKGvp9e)lw$k} z+wJkB0F_*bx+t^F>sZP=D2z(Q$(T3HQB*dQ$^I-@?HPalnVmu4)$Os`(Ab`E(i<`N znQv;A>tjQ4xb4Gk@Nv%%cO#VJm8)#q98`&C=L_35uN|#;)jiGXM}nbEluzP##GW|9 z3^iJd2hF)S+0R+vPuYE;b0SERtra)fU8&v!iE3?8)yL@RfarKVY5WM!!SVd~jhh2C zRC^||wyd5DhLjbAKgI)bMpA#ixk*+3>Yd*xjPG7Mw#QXln`1+3ANIYg#sdF-FZj*= zr;o)CJB8YAugb*Gs@&~Wc6%{_Lb|>16vi?$Wo_-lYrPG@pcOi`OQR{YUlIpN*f#eM z#r4XEgIP5>dx9ug(^l_c{TuZ-`(AHfInE_F1}Bccr@vm?(+bs|V;lS%-L123w7&Mc z*Qj{v;k8CGI~U&=>^sO{nmthK{PDV(Jjh$W^2>X)9taR-gSh?!9kx~d!hm2p#c%o^}#UFP^uJ!Wi2+Y#JOnD738Xx*<9#M?vg%1_GdDZ9>gYxYY)@Rjw9qq}Vfe}ZqpW9w} z+`GA5b&nK(DSEg$di1u>dXI1ZC;_1L!9%m3Qp8Wk+S{fHnpPv{fnt?l>2)J-Cn$XN zwFDvOh(2y?C&M2Yn`?dYoey|dIMq+SbKjrLKChv3Opu^oRxAB5ESV@JGUd*W?uyG3!cFjuqblM_Ssk!$EMdhMte_=871 zPohnpY^@ru*s!rVHdmcyKiT-?8roWYi%--GI@512ybS*MgH}wKS=jM-@RGB7I}J-( zN0mfXZ&8oAHz~rY8{@qY^S*%{b82`jAp%#uW$xX7YV#2K^gH+7bm9iJ?e6#SRCpz5 zz2aOkx#optW#Gf!(8Qd7b@2*!`nJ#5&rAI7x{=y{tC-W%Ys~4dT@8iA=_ck5F^G+a zniY#Ds#6IJXm5PT8$H@ErR_d<$LhxVV02RV(Ig?Y$+GNWqqXnhS#ZA`PJHuf@4Al` z4fyQdD0>j?_H^;On@-5Srl)v_UD|N%zz&Ikwh1D)rr&wp$hab!9kfoU&YhnNH{R#* z=D5MP(6?V396A;x{s1JuGUQ1E*cb`v*A0cWVKb>tdFG%H-XO?$N8k$Gx(f(>ngn&r zFcPB6?4zt&#%RiTd0zf_zuBtgz0rD^uo#BM%j^YFhtQLlvg3ZYkdvE%V?z{@x$+BtFJ`U>yhK=zK0*9n$xJGdEIHoa&J z%J{2pS%o3~gk8-0h1%Gp>{@)F=o7%!|L_P=R$Llz>Nu04>~O_53_|chUx4i$BEv}n zg%5ZVY0vMX`y{xZ9RIfOvpLXh=2`=1H|G2_^<*W` zZ!tL9z}Oz0WR{R=(8cg%mJD4_IF|fB%!6@KG5E0KgO^T@&QV;^lZ_X!o(6Ky#UCwJ zI-mJj2|>pQXi<)vf|dlw<8_tMqlZ~-_=H>-61Nn+e0D&9Y$AV~6;Kh8BHLIo#Z|1=Wv!ZZmf}LHe z)Kt8YAd%ekZT8LKBYSM zOzxERltDHJ@x9j^9b$6@oO~Jrn5S6IQy4KusA4#tU*nrJk-#tJw@YX7$}V;shVDdv zki3XR!Du1hN2Yibb~Ov9oSi$7ye!TJU=YFGoT8cEr3 z`WFNi?ax~`oW5G1`-;W?kG1!YZsWYqd}l^uhU=;+@M?n2qB;!b#S3T%QW6O|{2Up?*WyTCg1Fz2%7%g*uUZg=s0*xEBx;F zfB1qA@Zn$N2j5?%9X(!lM5OwuJ4>n_ze*mq$KA>SXwqf`t?*UK>g#k?7>}_1R+2#S zC)aWsFCw!4q%n4yPBCGYwwK6uKjhRz9P#a5VVE5<2{(^;Kl4}7KM;-9ZY4Xj>0rx~ z=KD#hDx`oC14}@?sO5I}X@*@I+UF?G)p)LwD^~eU9(ni1%lMS&_E^ztR%n5>Lpo8I zk0ObSL1T`Z*#R@B$qaVnA!EAVOzI9W(i8{*_La6W9(0!yx=sa2Zo!BFM2>|!w)sj% zuCkO~=)~3QI)rOFDpbdHL!Fpy0gm>*fsIBoHR>fO`9s@EcAgQgd)-$3`UPy-OWTUt zZhDT+rR17RsdU>}RGLy#&Jk>5LT^C(pvkw18>7e)ZP=re z*thD+>Hy^4Xat8H>c)f~CHk-zve)5S@tPq9WMsh@Twr7|_s;*c)^{ZRsCC1OhYMru zddsc2(l2ar$oXtO6F$-#Ei<>Ivc~6GXU z9{~=0T(E7k{l;t<$|;o=33hNBoWk-O&=0T+n*QA_IZb8gI(9lk-$j*YKbE&Y8iGFJ4c+ zYbGO~;y&MPCw4-?{fgRMrLwOVc`6t0+iQu3{9%uUqCXT%WZ0woEosU|zdg8psSkSx zGbbh~@XWl81hH4Vir>XRSx6V1x#fFd+dHk5)@>p4n;xpN>)1>>^O)Dg)^^)pRiA&# z^d9nNxsLjDoW!g=Q@ zQ~&G_)cBH>Tqn7c))4#7JpBsg$=j&ayl2%c_~Gol%GbkRCs(vy6;*UHeMIc0xoX8W zyHP}(VoiO5Wp?Jc#>tiWfy^x0Q&{t(>zUbGmYDWj;%!T8Z-|UYn)Bv!Eo(|r`4X(v zp0oHIu@YMRf^9{Ph_mIvr>VZ*Y6yQ*YAKdBQm^?ZjcHlZQTVysMHU(8?XxNMGl$%D z!%x$Q@g<`u7UUoNJC&I>!B#pB`?fOe<+>A7X{7To10F$_?x@o++p)}iO->O9lNG27 zvE85{_{8@E=YFpPLM^Xt-}Kc`=ZLC|0JKK5L}$*Lr)H&`^gQZ%kfqu}5l|nNRH^Kb zK+(_U?+$x*-CJYz+bfUGksW0_)DbT`Y^E%tp5|J0b?TJSDgTX`u;bh#kV~C{dS%{@ zY1y{j$JSuiPwQ)GUUxOi#z=2tx{j$BXPL5lgvwfI;3X^~h?DKKxD`o-ZfYVV?% zG{xv?DlFz=W3BsGj(};z+_>e@8YLKBu!gK_gaysqR}!7{F42&}&O)8#SlwM?-3?Wm*aXjI>f20n zR?YOWH1ee5S_q*$@D4Z>sx*cw!0Y6qKrR_w74$gpO|K3lh~dxn^WhVp+7Z z*uHnGA*QqXh4c(08dvaE^0;2Shc+;WhVkZD52K$_Xe6nF_vCfW4v3AJRsU=QQ|^=o zW75N?nPMgkL0ygd^bBXXwNVd{(#>wSEKCV?jVYFu)Ph(XZUWVSKPeTk%M@ajVFl)A zXGa-IVzsv~nT38k-?S9WK|bbWZ{gXdy_<#n4}@_MR5VC1 z%dS%!YF=9ODlTC$6>STv+q$PQ255r{QlU~*Vi5O^XiB%{ANEE>ub#whDWp$uv>`mu zZ3zvq7a9!;3R*qr!^W`#2Lx-9U}0mHv>dk81&ws8 zCW&gkovB0Vt_BI}xD=d2uhBj-a{-dE81bkYR~08%qdzKi!6Y3~yZZ?iySP~&_IoK6 zK=}iAoS23doYLR<4`>D?uVIC&v{01zyZ}R;7PGUMs!{Np)WTBwi=f=GZD@&<$AxrQ z)5;@pT=ORI8vQ1RJ4HAv7gO@D;Mh$Mox^2}vY=jyPSL?*q zZIENUA3>jXXDQYg!7VclV0EEIrJl)RC2QSit&xKi%PEYQftM&Z zL8X-(Dkmu27)r;tm2dwE%gvJnyFg}dAda@S-*VH(;f^^^yJ3iCo=c~vCioJIYFDmO z+kT85*Wx$m11wqd%;Z4&tE5Kf$aTsy6f0&)>;@*@rqx@q{G?bntkRMdpC`$JsYQNB zE8Z?=iyUOJ2PoSk57I+)D_<3vczd95N2W8bQ-vJ2vv`%|9_8mb z4V!Iy4zqPJ49`FST@Nc{JK3rn;NSYWU1FC-zCv^F5jsrW#5x_0H|RQMGV^4*8b>cm z+WV5ZQQJNf@1l*WWwLX0aO4gG_J2(yCwDeU`vo@Ym$WDyrF){_;gpuNB&*~iTNb@V zPnbS-W#gO;YNglgO)k78*8QB-U1{`KY5wLdam4Ae9tbRL92`BqSl)g0v6Ge)o%TYR{m4FiW4Q+djMqP1- z(xEpk6-k=W(duG)e>l;kLtu@m=8i7o=;xYgd~I5(8&3FA|NZ91spO?_bjL;Hy&@_! z6z6zyzrj*Xa7E-U68yA}BanlHpG-ExQ37OSc9{X^Jc%dSDRM`MgSFJ7{AiP< zD*Oq7SIdzWrOHS%E^|%eZZfdQIH{(Hszs`;vbz8YMB@dyQhERH&fKhwuD_6Z&x|An zkShDoM9+@1`@T??d&A+e(jFQR(FVHZ&QD0*&HpUmNU1F$k7$LY`(WM za`YuS4@@J6-Ze818k=Ev)CMwp)2aZCEvJ9r^1n;6Aqq`v%kCo2?`(zvEJ0%Tb?rQA zH0il$<(VHqqndx8gk2C#;xh#h;5j zBwon8YZ{4XannaogN+@T8q!*q?94DfdWoLh_uWW- zAdL*_hvZN*y|IT{fduq-&9I&UQoTgYsk`Lu)mx)U7?Cni?e}&PEB>x+ABZGgD*v86 zY7bX?KDf)s)1?76^p+I{s>|OV8QCi@kpo@%-xsa)lZ7-`VZN7bf{`41+0Ji&`1@`d z+EDxOY_3_2j`{)N3WSqJewywx__#alIwL2~{rs?1x#>ONSE#>rG)?c%w2rP2KGxn# zm+7Ofk2-OA)Z1JdZDM^7WvCs+C62b}?B=b}i8yGL9#kQNlGmKl@T0i_u==~^=<&t) zRA;^X_E99cyg+Z;=Bw5yLV#nn$}>C05I8e0(mpf)G;5KmXp>U*^^s%E^p(+rDK;vH zWdPeZT6f85=dqV;(mB#LZ-TT89hBh(9-&^;F+En6Y0#Qn1Eqb&!8#2V;fF=s6@B z1lm}H*f_*8Y52-Q85`FQlo&{%|$UFWu=4elE=qAQD{aofe=l*T)ljCdoz}5I6 zyv1D{8z^T>>`AO$!DDfuH|$P2Wp-(8G`RrCa-=Uk)Qxq+;cMOC;KySp&1a?uNcHtU3{Z2OcLlH+@`>PYK(`zU^2Y<5&Xsf1N)(db z9m8wF7uEUL=xq~Tno z)PJQD>e|aRdr`*WSKv@Tu)A>FYD4CkHnoyuNE6Loo90jMl-o1Iu3R#sayZjX*u{L!D%^2LiQhHZYao*9@Kl*VvC$xz;X1;nA|_ImTl* z9Pv%3>cPFNv5u|OIC^Akp7pX73Jnx?o-rR=;zeO2C_=HIX}aB0Ofl4XH!#=QLW=5*Da71zv}HG4)~>oezeo})bU zLwdos-S`D)a`#(@TgXjvk}Ij#J@u($K9jpFcjkMdlFND)G987MoM$&(Z;d6}>^mUC zM||I;rG6$Q=-iG@$&;OwBE1(o)E5~xZ~3_M!#26xQR~9y7E;jfIgSFyTS!AUl#? zAn8S7_5mZunj-r{vBvtOz2CaY#dZ>dE>*8@8yDO`QPMhRAJY-)5jpLh-#>kwdaoh0 zMYG!T@>pD?-DAncopu-NQNW|pWCDt%=Dw!jciWQO=sZr-JLfXc z8d1qpYLUnV>>rbzu^r4+X-b_`lrCnL?nwKy(?8FZE(=Xo^R3<+EG$9!XndJ;*yFrU zeD(9x?jbJ_VYC`DSrsNPmBn>Y^$I?9dE1mz>-HqYS_AOmpy8L3lP(`-kSq_9HEzKX&=olV6}0C@|)CO!l{~4+PxY|j8jqc;>(f3 z0*Te6px|F@#9K2?I&%X#q>o09dnw&^%usFJq0V)uza$C+|HmBSfL+*dA;W^wbVQkx zB$-Ccpp-UulVW3m#H*CBVYft*yd!sV;A!WSsSh3zNyadUa5J*yrfncA4D5OBKU%gs za)N%#)MUhe-((|Y1`_}*D7@9)L$u}|B<60T4-77yOx{^851EUG zCgsefvJ|DpZ`H9XtnRO#+V7n`ioE>_&eBHtt@S#*K&-H{A8OB=>ro|Id%{JPq}sCvX3 zrhP2=21~QjvyA3e9F1cOPfwaPSp?m_XvdI$FB{g1T#nMT-Mz`n{vL_d=0Zju@;?Il3t7GJ203PEfo&l)!evmj>p0OqX!5*W8qk-l+{qrP!kz<&@r17*aC4N`2xCB zsO$#{vCd*cQ$@ij}j%8qcN;&Wo-`nCmSdg>E-v zHXCng2#svCnec`7K#UoksU+{3tB*DUZ}EMt%zK{3EuA#D|`Gp_M*3OJ`(&*O9J(lRTn zrc^M?VLh*mi$K|CyTn3p7>yco2;IWq>H10xJcmm%sfa0U)wVH(#0U;h3j~!)A6DkU zpr;%YBgIUWXfqTDKqW)eEYvwJvE&1#B96iv7G_M*DHI?rRL(oU{b1edRD#ph zl~tDPP$C#Mn18q`kr1U3x31+u?!aifsX*>A3uz5s`Wgm`z;r}Y%$kcqMb75#Ri=Q^ ztU#^Ik>)|QB%X{JUXW?omNa`!_F;OWMQlTu#`(C9f{}pC_#9Jr_{A9J*}6*cKjfea z6oWdU6cgIGpb9Q&9u{aPS#!Yz*HQv&4+yF6MbRk?)4iqG2`PNeyok^c>mtTFv*zew zmP8z`c!7l$Faj&GuFpw<6$0Q?ooOgog}&4JChk(f28mcK8x$5=45|cDz6@Dq5IrOi zc~zK8uLxS9b_;wNby~HO8U+H)>WQ=s*?(BG&=DZKCwfh>AfChrJBsPfG-Dk~EC`y! zP}W)9M;i%siYFzqIo}yt#v6h60i7D0+6a8}uVUtsBsgISvUPZn@-x+}ejMvhQ|ZR2 zsl!Z#WB5rk8!JZ*7mRUV#rh;D2>ccmtBs3b@gsb#xDDUH>T}pjlr-qJapO+##Jcut zyLCpGQn!La$F3MJ2K`1U>=G=7ibIXgx|&_WLLq1?C~fLe)TbR9W9&F`EvXfH*g;hn z!G!T@L>00=0u}JkfJ#x$Bn%rKsS6C5Ay5YCGl7G>lJuEx1f5?0tarduEnsr+UrI0y zc`!}m5;A|Z@I|ePTEhxM z+F2jNN^px7-WIqTKcWX=K^MFITqf3uHm<}BFWiByZ7Ha~x>m==G^;^4=>;S`us78Z zZcwsXUCmx(csV*B{^nEk0ke*Ve;vgof?`9YO{et=+Hg?HMFd`EgdemZJr_g>LU;bA zcO30mVNkB(uVu&+bc*^$m-JU@%$tW66j5=02IXjTI*0htj2hFj!qFNP&pgcfj2Tjr zsd?sdBxazPk?WDrLJMfF6|m}e7hI*=czR5uT%LbDNrIhc%q#w zc@*I;n8g^=J1&dw?0DVjD9y_~P``7RQ_gc~^u|(}6_=S*3k#BmR@j~I{{~Aot+=a6 zHg3V8#nY1B$>e&fxF$=YY#$bgn&ET?&R$>_m_n!KQMT{*k`!BK2hyy)o6)1ui@ol5 z5cCf1AFbBxrNhWEOLl~LTkN&A_rgLg3K*9MIrNcabx=DZ*oAJ~QIXW@2D|agCEm`hv zn##dqFm=>@-lHdtu@ppSk+D62ZCdq=(Kd8>8#MuArYs!OY6NiI>v9mwDicqg&A0jvmh~lLsz;+sC)}fEb68soNK$ zQ}BN5KLo6ZH+;{Cr*TmF3tO8&3kscxmn z5eI-Se`G7ZoOz%GnJHAUYj?lx`;$93fNTZKdbn`xA$tQKIlbeXr8~7+Dm{Bvern5J zdsVioSd_O%^gN#X%=_ntfx^J!_OYWYX>d2I=c%Exd=z;=pRNMsZM-g<)v5BaPvV1` zWC>-l@4LqL2WV=Oj~3tx0GiGL&B~KUUpk4Ko=mm^+3k(wa+;e!)StnfTmj0(nM2wT z3h4U~fWFB`Yk{5Ot81eHCPiB)+_h2oUudM+zwt<|2j_hkoBKkinBNSuW0z?Dp_gN2 z79i;z8>eKe(kPdT>?L#5DYj%I{H@xhsv9VL!|to{j;vAltQ<*_r%Nq)SRRlg@cG1z zj=cZ&zq=X4D`*x?M2O~tLl3Y#j%VAAQVq9DTI;Bz`>n+t2clclK4ftiN#@67K&GA6 ziTgA8M{39uxA(Aa(5>Sl`oMGzNc8*?sJ*vY;b|Jh`CDMW{jV;Cwb?SnaPW30S1nXw zo&{|+x-Ab?DBg?p6jDUq4;8W;0JQeeOab-V2S4~W;%`CnTpf{4sYU%mKJJV92c48x z_WwwxI(SZ>>f8^4`JX;DZpFc?x8*P0y`3XNWv~PO6nlxnm=rFG4{uiB8gXwl_wZJI zvx1Tq&Q3jvwECW3y+6}Vw8H)dG6FPNYVN>^UII0QI1fF4YxIv7!xHslX3npvsGc%p zy=b@5j^IvSA}Z%Y+c*;X7olISJs*J%z6SE;7yPQ1zlc>y8%17o^FNj~$454ef2iGN z!5x5HO))*+mdec|t=h+b>!T5(5f*m^>ef)j?_yb%(!R~>R2XF0e3OIk zQ^~BeSTO{;c1nBtAq9n-#bv52p)KUgG~T2*#hmh^Aer#qI6Rrq57+Q{ZN+*5B4SFj zq2cxW-E+S6q#3mwk3IZ6lEL1rwO$M7BJUoXBI(eAD5cafuZ3_eQ$A|5O&z=)y;?EuP^o=W{2$)0z z#|t)Ro>`LJr|f_?H^ja0yXj6!1jA==ci#_oi>_jyO-J~zBP3I7$p6&2CY*73=m!7(-<~^!`+M*_d zC4w@CReFcA8^wn{g{Fo{GR1W}5c|pllq!!it%mUD?$dTw$EVP+mNO;Re}9&RyXTI5S$=5Y`EmJ~^iR$! z|8sEMe{zi3GW|!w-VbT;PplVU4f;=t}B{H=}6pVcahk-KIPz``G#z%CB5Pyf#! znFoIdTeGPdZ5s-367(@e;a3Gu>M6^jFS0e3HEKM|JPZ;w>7Whc>DbK9nX}Y`iHV&G zJNI^9u>F{dl`J;@5UXjRz*b$weujp&IF`UIMokC0r;^K7aFt0hNeLD8O~G_KrKeg< zaq3JznArQpf5;2J+g}tVYhhauJU;w;@MECL`QSn7Ld6FPwmHEAZQ;X5AS? zop~xRX~I6>B#%J*`BqJ$#hM0m$)q>Xvnac&NckRMHfX8X&YYTp6k6Ra&XGc8p6UT7S^prGHy*7nv;cpN1duB%X%8aF~jLJ6o%?e!L;H$ zV1TTvc5c)4#I(xum)R_JaX%^Dsc*}v7h>2)vcINM)Hs&#CI zO7rPeLj7?*3?3LsR$M2pO}&1sO&Y>?`^gN&E$38atl?e&Ha%#Y#oDb@kl37&4*?PN z8~HIdqf5AFB2Rx0Qr9LV#Koy8V*x=&J*kTv_U%fnCT2hc`dGo(e!#AV{AAeoH{}v@ zoH_Yxf3`hF!$MaqRuT@3G!6aHu)a%VUp8{w3(syt0tWO>#4gnYZ@efxuR)EBg9%3>flPj94Pas?vJ~I7XiL4VT;_$19fAX zSpz^UYEDb3M5!vXRIWIiJ_rg#u`9jCkG)+nK7b8Al30^@yd4D`;33i;u(Kx(s#=dX zENe%pMOFt)GxsM>wKjNB6qjrLq+2gma#n*P!C39#eyL+WKTF2CFo^KR4KcAq1z#j* z#S0^9pPc=KQJD00`K5@j<>)C!Psz)bY8#>eTDU{ltXBbbp+#@OmN9*gOwY>BE_-f( zyOWJ&XrS0z-s`@R!F}ldOtt-uXs79PQ^Z!}MJPmXT4EqN2GgV4CYw>uS|)w8pXAf* zthLK)Tur-A(u<_Wg5Yq_zU95Pho;$X*P1|u}H?(u6TgA+xhBz;SZV7RNRBC0C~vB5?HlD23-qupj# z8(c3{(a&hMMRH}qC{ljU)r#TCJn)we4@ zs@jxB_UzYa_9ojDWoi<+- zG3xnk!vTX4@iab6>41WSYXU`FMO(MBBwq8 zZgor=?oQ3D!+4Z%kY=G}!JeI%t4c^v6++n}Q(}5?9aEC7)csC@S&L#o47X)0u0n(< zW7-&WcwfG#*VWjX(L?I|GMUkaJu`z)oJ!HykSPqUb7#&4SF*?RZcG~ff*C7QpNFEI z&Lo4L?<@~Zi|u{1?rjU*mpqK6pIGn3G*w;2nA)_2DWF1LW2{DY%Q#1Yb)eh{1Q&W# zgP~8%)dei7nO3L1K;M1!_w|_FpNSL4Q$em)*&MYLB~J8lJPjIG6a=TD+Mt`RJiVNj z(|Sy5b>G!s<~(WlQ92nD8Z8;lj#yfx0ALA%)O^JGe8HVc@`5XQYvoz`YGK-d}ker$@3mQkoIg6F} zv!;U~uC8O*jRgXaY51TcYA@4!{f3 zei#CAxwT2SpR`%&&aZwZM4`{6QS+@q`gl9( zI{q2U?6q{1mm<2=!wzP`sR}a2uhp!auVy>Rs)R~MWr#Rh7i1lji8x&{WFRF)FUKra zm2<`-@u4an#LU41TIkWYC`fIdl;lxqP`xwjl?lx1* zT#z`(1gd2&@G)W>?I^R#>KcFNNB=&np>^S5&cS<9Q@FL?;=$=gSu}lx3zzRMLz-T; zLY~&p?5MAGdpgCGPY{!dlPb=jFk^Jy$Z4gfF)kFl4!?`+0!9l5ycBp>6hNt|uc6zZ zW)!@xRpt`i1e*5aKOYnvD)H`bf<}bGQIxcjq$8)8PfH9U9_)NX361!(aUFx=Un+r(=WhnYshedMQ0kMi{_7`*XJhIA1f(E}az>?+7RV0UtfMN4_ky4t&&^pQc6dh^UbBNEe9Z`gA) zyAl04Wy49LhQP{Nx_6DmwY?K3oF+M75AVt?i0&;~X%x!#esP}7I}KWGTwO~Iv$042 zwro4Dz00$^*(P;wQ1?x`z^r7Z9D3Lfv4;+g~|rC<03z1VeLe=1c$Fz>&|+9<284 zA-(AHOi^EbU++p%dDMZ zQv!fId5${g#K=jJHg~x*?aX;bx0b4`ubO(DwrQ_hZcQeu6gfM$Yh)sA9HfQnndj!y zpA;iIe!NGVueNap!N@wZlQl}ZE4zA+S|h(Zc&A_@8>fw8ZA`{Y+|hO z%hGhBE7CeMb-^H|=gJTH&s%l6B?fwP%WQ$wt4!cPPI zb!Da&l0&zaKm;K_MhX*4?K3c8N5DXaD*Pyj-=h!=KXZweUQ4!&p>2C<%ZQRU=%v9( z1~SH@?p}<~L)L2)U^qUSgr1WmK77%`bl%)8j{Tq^?j*&?Ew}7^vU)6TfyGDa*y?O@5~}krJ=_ zEda(ZfIqWWAKczW64B+%_v}&GLtPi<2WR^)ER*!IBHJ+CdR8@FltTW6y{4?^kO> zKd{tc(SyR5z^L9qvA6K=%MAGPB|BF>ee8W$K>S$BV=cOI1vgH=@I$%vv3uH|s=-!8Q1q3L%W=TlolIp8(Cuo)hf^ql?e*YK8){pH)8kutT;?rV(JhR8*;FMW2O zJ50N8xv);4%XBHcaf-DN8+aKEeg}}UiLX2iado^alE*I3H9y8>@@p2O<`ehI+Q_W8z%o%hLO?++Y^aT3Jg!D=B`hMqLuZ%*9+ z+7z912y)*)-X#DC&E~$fDWkdXfN?Yebe{iB@se1#^Uo9(#BA=*=?eM2JKB3}z6@uE z{d8zOTKOcUQ@0(_Bkey5FV=>(!AKxuzgoE^*}R=?hVRd?gEER6@|vGfz+8c)yPIkA zps;NAb>|pU7bn0P@#W? z*+k82=Lg08W=mN9)KjumjjDSf9o?*Lp}PFN{z^3o>GmI2hq%^5>7iRE3ayFR@@4Cp z-^-{Ytc6%X>ld;2i9*sO#Ij)Gi zH(@t`Fhd&_9CmaKbMkl1VZ-^+nR~j(3s^9~wt{J`L^_@Ed34Rp9~VR4n;u19^y2)F z8BCv%2xyo!8eJzbZ*#38Q+~OXUnWcYS|YA*9TX3DEK<@%cF9!B>WcQDsB-@nyY4QC z%mP-k3imcldV7$HBem)zXJypHP)o&2!@F=`$3zg)=6SsOm%`!r^<3sKnAFD zF*4zD3OanOgNF6?^aPYG=x8A!y|fh$99oIy-~PK)Sf6<4K1Oi zFi0Sfq@(@Bn*9oH^Pot1;>eYeOO#nyVcfCpMQNY$viek~q%Jb1%hTv0`x=%WGPg&0 z&~6^M=A>@_-kx!5k#^bV%$R`lN_sXoCdusR<>Vl_D@eY)@eo!SiKw>m@Mc`=RWWF6 z9Iy3=+47ZP>7W%1%WgT=#@CMgmZ1D(>AzA*rhe!%ul&kJZ$~H%qlz|!%J$R`SxYE~ zSW99L|0L5D6rf@g5l5_9fba?j`eBqKPJ+5m;^%e_DXdTw!*Kaql8sKE@rx}0d{kzC z)MCwkbPWH_e@LYbTEv%O?V1_9^L)PEYe7qUOTGM2YsB%8!11`>cvH@Wzm9(+HD!6KZ8} z%DAUG_0hm1WX1$^9-=64Ed4s|naYxIBF-Cz|5zjMJWJfEzYtLRI+Cd+L;)Z?(BL4w zE^HIC+L7re#S#P7t}1gA)zAV>&#ha8JmK`Pn``Q-`3i5b+3;`5mUY%zI|9M=ahX~( z*FGu4O!$WdEplzTe!^@?2;>}iAezq2>d&1XqgZL$X2^?cc{c}%HU!L7WI-T`w2IQe zz~WKyIzDB=9ypn~^Zv8sN?0UW0iAAiSegYBd)d19jo{J-cBe}rv0{k3X z0-Is!>mQ|hT{oeVQFgWlu&TuGq;0OYu{jgq-?6e2TY2VR-4#Ly#`Lcb2B`QSY0B)#qb@Tz3V&tPYsAaEVwa-!auwU{~y_G;MG6XLw{@IpVvcwcnTH( z_^V&Lcitp{Ai4yt6poC<9}cmnY7!-hO_RjIIYj_m>S+PI)?$rq_zjI=U*ONEIL`4b z+7!5#4UFrp0}772Bh-uI_0g)ByeqUev2UPvl|3;Zd#916sOxo=#+t!46u-jrH9M!} z#Hl~T(jQwfY$8Nfzx&I7_<~0Ck0145pMZT?@b!bA@x$FM3cd&LiN~Q<=iWy<6O*3r zC+sRMt!1WQP;dZ;XW%%{Tt6f4q{yBqyW;gDAoJ(FkLGEjMrU5Tq zgFbuLlxMB)-QjP{(a83kc9x_q9$B%&*Ct6x<+%N1jn}5ME*jBhJ@vaJDMhD((bSF( zu(QPOWfvT4YTb-&lf_Crba^0i*2qz8$D@W!8${ZR@QXLO6?>7j3p zx<}Mi1iHL_imdWD6KThioFOc5d`(^#9;x#4!qw2slw@-Lq%9L(S|*qZ8s}ppIGz*x zd8ozm8JU(j&h&?A!kXZz1yix21j%d4Twp?Xnv_R}r&nnMU-8e^2TQr}lGvT32gB ztrfe&xI6BFJ!Jjck9<0|&PdV+_4U(3^r}VIj9f#7fZoj5?l^C3x^Uz&LzC_LL}S(y z;tvgX9K~84d%|pQXp@q6_nW2ls+`%8W(lp31ki<0a-KR}Gz&u~q+7|;iEZ{7Dx3)fWfGc0YUod9AMrDFyr2-C zv^ywy8fO8=Ix;9+?U(;*Tma@Jr`5H!Ig+>!`Am+O_Aj*dn0cyRNAyrZRu0`1dP3jD zdn~Klc-)%($W?W!D))n_s!FK=g&=@hCb1Ai&Fk|HJ13nNdKqgNld|rrw9eEN{u>wL zQWct}#yx)_TX;9OPME<=DwF_T$!4H+J5X17LHrRf(TL@8)W zp_B4eL&kIi2k^u!U!8MOK#h9A*J8S_tjBy6z$kv~*&Sn7i1!5SmP`i)rNo01Ao ztJE5^$3?^Sl57I?1pg&1f*7Gv$9dB@t5LLt8IvBEI4CuT(Jo*b5mcGcu#}2HQK&^V zS@blgPNmMBk`8?aH7=Kn^ETv;6l}^=COU;9gz}XKl=_l|u7J%~UCZn< z>MH4W`&m3(g=2yY1-bhDrbUu^g5C0$cuwDgre;Cu-raH3Mqti|FK|{H(OwXsj3TZp zeKMa`oC88(R5|Q%*Fg~G8eh)U@&HA=jNhwI*Y z1Vi_Lk?6DpWYv8%F7>$U66q~C@&&xV9Kn1oU|$RINeUrRPjwxHXgCfvx-ihN!asiN zWK5N9R1wO>W#E-fE|vNk!x|(Dv>VddJIv(u3#=DuQ8u8ool|W{lc6Js5ua#vl7?}N zbSA9H5P>sTVp<=^JeSb2ItmMm;FcBB`pm@~FZ#OUh}atLkm^%9e&3n%SI(&r0HSe7 zs$si`@JvXn-vi?u&Qw441)$yiRs?F2hj1fdZM-#s>HyuSG5*dMYaxxH zp~kEwg2J#QK2%IoT!jU|HmQ?D=M0)>Sx6-o_SQtGvoR{NI{Z6Icb!n|Oty(eTIeVs z;DJ&BUUy?~n^MqRbNZ@OiWqLjz2KUPy~^rhQWoq$u6^gJ{}#h~N3E+tE=Rtz;i}mM zyNoCpLFf4+Nbmc4F=pXqRt$9nokUz4#x1is%BkYxf>}=uu8KE~5?`G zH3b=1U3#SE*7caBWfY}PLhunYbfG9^n@AGF9`fD4j$|1wht`KRF?c^B)6$Z$bOt_` zhzPkM2PfcBocasKzs*)^f>I{YOqD*Wzz(zAgc6!To1g_@hM31RKWmpMMAJ2iump{% zq;bUQt0@`4c`B4uywv52`_6y4@4CpfQ;jt?~KAD)XJg*6h9rayVOLByC6M zhdxPW;yaL^w(B->MGny=Yfm|Mt5#|6rmf_q?`8=7t`qg>5 zm&!ETwd)`gU!O>7$!hMobh@s^*9j7e5-%rd4f#r27Ps>BWyX1-ZJ*CCvn`%>x+eWx@^ybxy29=_*z5bw!%ax3`%lf*rjC5s zKR_F>C~nN#Sb5lAp)>miidMhTXU?LYKW|bW4$P%xid(kS-p#FBjQBUI{p``@u}#+h zNWRR9H%^ZxWsh~GVqMv>U?;rSeEm@CLT2!Pw~d#v0^9{Vv&jQ=qEMrtSH0ffjxf@l zrisFh-fg+tgW{DX(P#=k(U#va zew>l+AF)!K%`91tIM}2JSSTns0^2K}nbhc;1D;Y(>Ojsq0$ z?uD2*pxvK|axnCGpa3U(nU9SuKiaIBk=K(I>HTehorZ9(W6 zUTp2!12I8sa7e5$_WE?Ww7+_+@U#O-^2t@XKbhLmlE-M3^O5E5NBIFq;LY~SUy^_G zofizgOgG&Je28H^%u#Ufeej6vf+RZ(+3#)0y1=sgyUcd7weQe0#}ROE-g;M*z}`!v zFCTlW@t)E3X@u+d*avpXp8oqY4?bMzLaA(!mk4y97vbXz^9% z+pWFr6;yOYPrcRnjA1i`J1-&jlK+%|O27A$G=)>|GHmE8AKYwoN%l;b`@_RNe4YyBJjV}?IYsoY2#^2X!4?kr-E$=|T`_S~O?UmZ49sYUWPl`ugL4o9f z{Ghhqc|eLk_{6<6__!>aIX#d#`xa^$wg?JZFiv1YBk9Mfce!SKCTx4RcapzC7-=0z z428yPr4t31$812lJu_N@Qa?D;ubPGz%5ecu`8J{|=aiir;{>^=7EQA#xa}VbYZ;X~4Ig@@M;%8`}UHu$o@uiAtl z96G#@+9}j$H2fvjgA>NS#8Um{8tlv);ZC}dK8OYs(QWr?h1qARn@4XVPKP@seL8xr z)C4{MR1H;t<-r6TAHECh8~8pn%G0c;mPH*__t=4U|6~5f-yziW2^d_{=yRy=`c?D1 zuSefCcCy$e=Pyz1RaZR*&uv+1^``>Il;~?9)W=T$3BDeJBv1~Ev^(N=oad^Ode1Oo zryvkHz{PL>zpLb^9~g}XH#24*ZCNHV4S{JPgKvaqo5+%dt($V_u|>J;nDzH4j&dlUIp%`cl2|x7T3@Vt3%@U2pUqD*APlWyR4qp^2;Z`@8*Qx zh8PMlq#7m#7T2R!O@w1^E%7u()rJQ!H-`(Y!Wj?!2p^&r5ZG_k{9U6m*#ZWpscmQc z)akOEn)Y!k1$5o~D^eUvs?4I%9i8y1E6bF{aZ1#0QXG2ejtjiQ)Jf_KWW?A=cM0fz zs>9_p8=+cW&XdU4l^&`Ln7^-cFpOHJLFMlIvCI2JeV9@E!( zfYGVwZN^e3%z1GP9?;F~d81~{A z?u8sdG|kAi$YLCx*SDD-^aulU7=8rFvAju4K%h)}ok(O@T9vaE6VSkhVtFkwjF)@m zi$xl7w7a>os3;E4m0I8L=^!W^SvD@vrtll1R3J2*{U@rAk@!_{VZxV@pcl+@G=|K>p~72yVGR z!swL(wFd=C#_~Yluc8dhf(|DoKIV6RE>oEHSX2F&9eKxsMv}w*8bRj={9>ffhW?xX z%O8y|J)skR%(;{$6~d%j(DUCa>h-BNp3v*p8x)N1eT6hc@AKpV-TpJ?`ZSEp#Qqh6@vmFNwqmATSknrwPB}8 zKewA=Y;n^F8)&H>1Q(e1?#v` z_%oZ)?C#)nDOsq1wl$p2mF!L&`7YbSB?mLN62qO!o%A{__Z5F)*6R5)TWjRJN>o}@ zk!6LEeXz+P156wYW?pdI5g(l-of}Oud(jsu`ljEYdAi)4^sC8ybf23o^(IR-PHFu} z@4dT%($kqW_&OOnBcqvAb313Z{QNVFm9A1fgg49(7C_%q97&`JRG+RX&s>yhWSmK! zt5Sm^m0(X^uoY#mQB@_ab4Gg6R{4;^eU&^_QR5ZL)2Uu(7?`6vx{?Ik>trfCb;T_` z&SY}SoiD1WOzP-L%cC^R%d`4?R{!CD{V9O@x8-cUHd24YJ{BYPcjiyO-;ZZL|Ffoz zy#JjNb8!0h(2}>^;SWD^f~h4xcIKcVBdFuK&tLtO0m?0|KYV!=WF5r+vU{mFE>{01 zi_Gs{XGfen_$P*_eBf6G?+l^-iOD4&xSKcl#W-)k6l#{!zRY)vF;;(Jk(n%?{D)QP zpS%7r)$?DI1v%^O#DPP}YCKu{!sXztw=4TxEMEVzO>6-uZ?veJwk&>=P@T+XTQnr( zP*p-{;AB7BvPV7sQZ%))aUPJwDMCnH^JIIO!e~52lvBK%wQIdm#BT@(stHm7Tm`@j zT%M~HQcgwY4AzV_XXa*fhC_dV{*{&=AsqeqA4s`6Y}9@bY5dru%CAXV{n&5fABD5p z529)wa3TW_-+6p*Ys%O*v^7lTl(90f(HVSrG&8@^-4S*i?CzfqH!?WsDxE@jbem?j zT1T8;7DpF(ShkkGRl-lQwbzD=^p|K_Vaj?PBXvG<_nXp0Kl{NT@olak3NbTr#=jz{# zvh%@#qsR1p{#dkN`3DYqW0rcx^QoikP|J*tq14rW$fy1&iY~cto&HSj9@R%knylNk z8?HCsnSS?{i8&HuhI+MswDFA5zufoo{^e5U>8t8=cIKjO{qFS4rQSrJI?UAh^F7@O zV@$bkxRq|LsOKrjJLieiY31qGleOK^W~1|3e#Q?bdh6eB)CQRFQnl43dsv;IN{Z3jS+ahw z+l$svZ{x6?8gr*=JzvQ>eP`6%{bg{nnZ%g>@9eqB0MILVq})f@4Ul3!l0)U3eVb+$ ztfK$)Z)Zn3oTQV75f|NO5~D|yZ`<3Q&f3wT+J4LKtk@m3<$=B)+FQ=pbDy&x^@9GT z{m1u@)%sVtSUD)Wm|IP&}*}}9G*Lt2_ zZIu}Edw1#Or4GmQDbrf;Mwe`N%>IR8Z7wpN9L?CZY?pIoOK5lvV9lrFwDH@)fPst9JCmxZ8H)im*i-~`LCYx>aWjG?~!M5S1&P501k zvVF)c|ITnp>HbL7+RiYadDk%Cq?*l6en{`E%}nD}07$$}?{)H*zoZWh4sW)4B6mai z3~8$4K(Co;PWD+I-eiq!A2yycuk|L6g}F?*u`w6F!~+$+RBHmjs3Ikrp1{L z)&@8BURSRzx#io=z4RN-y#M<0->k3rJJqhPvG>|T_Rxo>D`UTnGu(Oei4~vGPdCOY-j-~6d2&~F zY{4F7-sieU%T6|XIh!2)g`i}d9e#9Tqu*2r!Cd$qZ`~gX$_&ryUk?|(!tG5D=4Q@} zbf0maSqXB+8;du>Zw9B$o+!N7b#vvk^D+zHAI&Vf9lr!_W)2R7&lSVJvToYprHw;} zHuXF-e{gWRZ$gc}5S%u~4jXSw@3*!XW6xNl-TS@4Y&THH7JuM7N`Gi5xH`6Mf1*;D z`Ca2&PwVmNr=y*nPhKoP82B?!Sfei;8athx9UW?JdTY33Z1j$MuUoatwqCsEy)d1a zs883%&P=;IkBxTN%YNV$?Wa}kGugSDzNP2x_q=A!n4f;wjB1bX7=6}$>_&n!<(#Nl zv2w=2kfVq|-1-?C+xs-52%qn_CY)ySp)Ys?L+A>!u@2=Aj8VyDYgxZi3tZHNz0Kx5 zYQm;9W5lRV94zZm$Gq`)H*g*Q2)PpP(I6Ny!`>$TH%jtT{gQksE9 zO!L5hIOAWj_b_XJWVH7E|M066_|hk-<@T#+blJ?^`%o*Z9OL;QSvoyjh4(+@wP*(T zXlKWo;f8Kc@|5{_!gzAOmCxF4uwv}1T`^EiPMFwa@5)kBo~Ux@+wTu=vq}D zU(wPj<~Ly+qkKOVq}#G)r;d+if7eSKi1ZH5GMou#u#8kx&MWVn{iyvYHL~2c()UGL z(NFn-eTBs8j0&w}$84jTe&qtC_nPOu`3HmNEas}1 zX8rRNhpFNBoq-AP#D>-J+gLYFB(; z!;s<|RP}Ppr#QT~VijuJeRpb1S;;HR+DLRL*Sl{#QUZK}7c*r?*Gw0ez#(`j4f)L7 z`TleNFs^FpgDPE1Y{UAzrtaNgZL}lbJ?Fv&DqmB=VOz3BkAARI_ojW{@UIxT)5ANg zQJ605-A=YBpY--cy~!&?VUfX55q{x&ZlA7Q3GDnaZ*9b^W>QNu!kKn)1D_9SoMheZ zInR}LHnI||(CJ7Vf3V7Ip#)n@4RYxjsu6Y>Wv^B{gUNNy+1^IwMWfLfWBGtiYUPz7 z!=al%qhF(*G;+Rpg4jGUdUCOsCYRUD_BJUM?aHWg&N8XoQ>b=u23YEC)O(?!#7blb)m z+sm)m+eUUoMtaH%^Lyy~Ycl((Jr0?$Us65&r2$I%V0|3B@ta<$EE_kiE?~ z*I|p(R23LUo66N9S69K9uLE;xV@Z{_?ZmHqo#!*`=?MX5IZnLKO9iDQ2`W1`lK`2Y zB4IU_FdPJ;N(DHF{mG1td@VUj(*#KnBL{1b=>Wj}OKy-n{*n3l2E>WEy9#si4 z5O}h#r#vsOt1til{p|tm;6*GCfSgj7ndX76DQUJgR51^sa7a6RK==ULVslGy_Ds_FI4XypilCyKT@! zw>;Fbq8{tH6c`^0I^Xu}^ov>F{)-BjvVMI3#KvF~S-{~EM^6k~jUFHU=+v&><`Gpq zrYf~f?oM;FwJGd95DxYlgIVLm@aWIeS{-eK)K{JKXo-o!;0` z#T(tN+~;~0Jr%rs(ZA%qm35v|PefBEJY&bw^a*?P?~Te-=l3hwlm3w7%neg{u27Op zQxB#6*bZy=5qee^JwI@Rv5Nn^J?#S%U3=!;m-bn7X3kwz8Rv*u>HfOf(fy&P58F4b z7Y1%vH@(Eztx47U6{Si?Mik0>NOfNk{$HND#gBEFm9;*AAVXr7G8_2zxE~v zKJqBy^y7rqgClPFp~hR-y47CK+@R|DqrIEE0q(E+mxh?%ym|WJKc2s_ zwC;Z~vvcD&T1ztJ!u^uB&gUokZ`M{iADg~B^tlIr=LcSqqWkTI@AkfM zzgNrLo&R+D zStwql0pSB3rAH0`J?#n(J!|c_QC}){-f%hXu{d`tyYZvNPp;P{p6q!x^GnX^pL+Ag zY#4r+9{BA+Z}jV?@uiB)w7DqN%tyM;6d4lVnef8noB#>bOcnRZnR|d?Cz(NFZ#wYF z`)8Sk+{^tw{&cbwMTgBF>?(EZ&li`b>#4^uT!ke{iaCnWFD+TC^bwTqEpnem=M5it zTs!A0fysmRtsY?35Vzld`B&bv(XhKOIhRb}dBL_XsXu0VP9dT!Js9O2zEyY!Wb|f{ zDeTrl@bI5M$w=>r98~WmbN`K9{^nvRbJLb69|xd6X4{8N^Poos*7-~E-Q5bP@y~p{ z1Kbqg+h%tjoJ*8C%r~Z&cF)$R?Vfm>kudAM&rY8V6OSroLSe?ApA4-f|4PRu-q5f1 z+Z@0{6Gi``V!q1X;zU(JLwELr*}S;uH~Z%2JE|Z}XPBwN zxYe2WK0?WN=2HhcR?LEIXh*7FH)rksXRXH;+@^ZX-)$c}VeahQPm0Red!QTke1Ll9 zc^lj}bIm9DXxe>A?c9S*MhA$psN6S8_KNeA|AKmUyS){TP81IHZq7)7cT{tGpY1+J zGQR#9&#E%hgYu@tp-IjtG&li$iSvH^fE3FJvtM+IEA+t0*|jz^z5U9Nq?Z4wj51G`FTXSBj`?p8x$9x<3yjgj*;RZJId=7fA zI)_W2Ub4R4)#_jBh8Zg451rkfoDXW0?ab5{wHf16Hcv&&nYr3h|L&nQu!p$daBW?Rx@<0F3KV=SWzzlv5#?gWC%EuA0MFO*8@ycN%}@S%KK1;_8B=RM9-gzHia+z6 z+U}O~@G=c&-XVAD;ApL~a3Zptot3b#|^u9N};zy!zxp6M@n0wK`T&X>i8J(|m z8XHPqaXR#&&e6&2$ioR{Z*b8=_mqaGRdvKyWN*BDszhLQ@cr)n9YhP`s+u5}egcra zSJys5{S4mP;8#2ozig_v>Q44n6RtKsWGbnVJ5}t*9_Qi_GK`Fgdg6iPr@T^f+$aIl z+xML+ny;23vhGg~=n#;PI7gW^F>>Aylc#J&20-&&t=vfZZqEBXIMmJlsqs&q4*CC4 z{r->7Qe^V?|8R=;KOf=$$$8=+_CL9j9Y0?B9@pW2fEC5FXnt}j!1C`*qG?~|ZkFKC zp*xKM|F{l6zKnDxY>dA5qY*Ntw=z%U7L4kGAn@AAP$`V8h3rALg0{g0$f}HfPzR@f z!BTq`Cps6Yf8f}A#-&hb&sY3!)z$&zBQS+hl7?4$_Yppo9?5c+Q;te4E!2t^Jo-{| z(Xy>P#;j64RsqyPae(62lDQgL;JXOvl7+2f9Ih05zD=7_sra|-E7NOdn&#g6xVCkMgMem^oI9@mxI8j zl(Xj40q=cYZ)@5e^`?vEA>V!P+rRYCIgWG(BQd0T>DCy@Kt?9)BJll9Abr=N}Vx$uTJ z?QZlp`sLA9wj;8b#jNGj`}_pRe8sEeBm3=Nyq&(f7$$mChGv`^8rkfQAGA&7@3K4e zb4G_AoU`mNVx0}$e~B>@+WtmgsBg=LC+rbr8r4yyK*gBN5+zlMJq?|inyW9He$gjV zRb=sK?@jd9Y7f~kTDM+RwJ0$b73~BAHgzDqXvrPQC7iL(*yUt3GhGb)H^1lP2wzpg z2bt-*&v5&~q|d?j)uhq}O=I+ct9;d%m z5Twcp?NC@tpnT3z;ihgD)YHkTu8gQS%yIM$E9r9Pl$P7>1Xa6Ms{w#j6M#Za@a8xF zXM)+3>b}RAV;sjTiKrSft^x3Za<^?1H}X0F6=yGLb99+qTUN#p(~_rl)EwXNa=Ym-hY(hz-2Oy=!XBLr z(w80jMAUgJXx7|dDk{~6DS=$rFSXFX4^NF4f1|?Iq?!dPaYpxtMaIJPHhy6scgA;3 z(;JJd8ubbHobpdG=yT3W9IP(7LtnP)I*?!ObNXIp=pb}51tn*%9f8MBNoJ26s#~pSbN1C*c+bd)SFSK!ffa>Z_Nb%p2n`&N#Aw)Za0Cr^mu+@lHance z0T}U|EmebC4_dZ*8Z0>9%r4cWIJ_}kvvJq)$A&88Nt5hOpjesJ&E3A zJ{gin?I2AOC35c5AG8f^H7#;-R@P1cxtpU2ieDL8;L$LZ^eUr0)3yGi zl?|dyw;hDj%yD3uY9h_K;D%ov%4!HAmmcS-vYSflfWQp|M8SNy47c^Dts0gV;UjdxAB-=Tq+qwH;&*8|u>w-E!BTy>P9)%)Ca51D@Z|&YIhvnK{4Q=|6FxO2J~dASPtT$!RHZyr(H0Keovlqc(0 zzaM^BK8)GT;;l3jN<^CKR{pjOkZj;KR@T&`D`r0BYtwQx9wiM|Y}S}=gpeZ4)eJaC z)~)#CzH>WD4#wj*n%1FLbx(VB_C4|c+JCj};E#SG@Bjbtc=H2)$E&$r0RitkEbE<% z$~|K1WlOxfPyavvjX#qek%zCnxo1+Yh?0xavN5*2b2JrNu%_%>BGRJMO4F_wJdqoU zG%E;V>Kj^=HZ7(Bg|32_+alh_JF+^%5sKs|nkarHrN?ZD_VU2fm!pGU{izG*5NwipAW0AJ1h{;c0o2 z6HNUfj|y#h(yKB=Ov|ZT1OG=p1=(OVVS+rXt0m?CKS4~_3iuWHD2Jm%%7nZC;#76$ zeML^slwZdWUL$07{Wtp_BsSryA(rZ}wZQ)8E5z|ak;ekIDXjAs=R5tQXRAqV^mZh@ z3-acDUTz`7J!al#I9kq)-_9xEynqjxYPh_=GroFwk7n4#OA;r_)f;f5eD<6D`yss+ z<)r+ky@_ms>`25KV-bMdnq_<3(mTICXSFx#?v}?lq~-3>pt7dre{55=H=o=w-hgj- zyA<$n2&B%><#$ow!yHek=OI`46%S#U5PZ+ex}A@ z!FMj^$Wy$BW{E5Dd%iK7h=gdO6|z5X5k+c)#BY3f`3)%QbIcRhg5LSps3GO{iJPGJ zmFTy)I}WSpwj@mi(^82+jvu;v4PAmnVnm-;}tGI!E`GPly+tN3Go^{?L}R1-0I zhY)^^|Iuuql@okY``0!Luz6uRm5bxqQ_%A#XvrIXmet3!bVj*Dwn=H|d*^rUf8zh~Y41FEd;1~V@MDiR=YF4RdtcYWP;OD^CWelb(kU+Py1quGzOW)x zQ>X_!uq=M&(ouwTSYY+Bs@HNlzjeow{GQ(+ifkkF4Hy%Y*NG@E?38QBQ~Z_VZITG$ zkP?aJCAy2BG({5F4I53wo8NilR8qJo;+wjR=)l} zdW-teTR!$ryd^b9sf6j8Yu1lGYF^)!R%?_Brozv)c}tTsBQnlumaZ5*LgY*E>&KWPisE`^b>I$!)7l7uRO zqWYzEd)l@%+qUQ*2tF6pgQ-UPdgG#b19&PtNrz>y#++u@)6nw1?`J1{7hY_gGRa8H zxo6E8k__f`SdDH{3ntFf$fo6kU@wy}vW*)q^~)R0kf)xD-o@k)bBYp8hDB&BajRm9 zZ;=d!snf8un~E3eWSz^X4+p9Ob5&H$v+*mb#GP z@?emhi01>Fx(F43Rxs(G$QmuiILuu%-Jr3Mkp&X#%gbENMXS~KmgV)Yv&ih~F*CK% z?705Jd)-1AB0!1T9JSS->_4I^a%`>;wY#Q_q}4N_dOG)fIxVCMK+48>F|C{4fSwx$ zuC${izpv%>MUxF~G!OlZj)NiD7c;6K3>ho|B9TFTjQcL*VG6#UFHZ%lG>&FBQs_Se zxW>JlFz3Sf0Zrwm+UuQsrI4MBqDM22g%`8C8z)1q^w{zD6gVe@j{^2vbIz%AYT$@k zfx0*Oswf<0)=TDx(X;p~DcSu3_!&N>nj}%0@)sR)1n}p0_xfK!N%{M2r$GphH9O4^pqW^!BgR0MC!Ml)7L z3y|=bV$(KB{``v9Jshz6>6BrTHEOV^Is%S*r3eK9*T?<*WTWM45CKYocRN;?NkK6& zZCb%+wJbS^>XQKnm=WL6 zgOjrQc;u!ho6ChRbIr`ZXl^&d8P~j!LD5u23ZQMCou%rY@OBjWW))=Ay;VL`siF*PJ10k7DMfM=+*B*GKgg5O&RQu(TK2=Z7Lso5FD!(7B4%?TLvhJdCg!y>!B?!ZSQqRQimb%Sth&3=dDu+NSUlKs5o0lM zzDv)D?ypYz;KWtY;~yVPj<>{56}`ZV;UQbI#hQ7@9*cs%BGgzM09oTO;G(Z>_InHn z7WO3JK`eoWrX}^dyRj`s&hdnCV=?+Ij7n4}qmJFeF%#3+fkfc%#-6P!R?bHPx`MJl zpMA-lY|QP)H4SHfYrHIS%cY@49`eLnLwi0fUg9G~dB(~Whrnjb#6Bc@NSJoplZ)pk zzEH9~%JB6e*PB&t0twlUa?=7FJIBo}Ww5$jknWhlG?&!>0^nv5lD z3@ZEf>V`UIBb9ET%*38*TlmXjx)+PnU?bU2mMa#@4*H^NYRP}zi!D<$?^(h5PO+kF z58H?Pjr&2GRdhS2Tw2hJhcB|Wn%zs4&W4Hw!lKSbXsAGDW zX0wKSd;O8L--X?jORzyKCq4`-Twq0!D6l9kIwCJ7-`4VwE7>!p&OcBOQrp-!Be%QJ zgte^%K8P#?g%7K^C`m1dBYb%vs zI=p+#8KHOmrouQYOZ2J@GbOP@LMB*^zgX!ujE)zO>h}6Bdu-jXw`mDiQ#=-&jf-Y@ z+MLj2t6_A~7~ld`aEqSIt`Rq=grfJ(?++B1yWdNdvJOcWtouZK5~ zU>=Gq@Qz zisvvv@tUmet7-ym+MOhr5phTCkUR0sg{k`1?K>{nv^=d&dBr2%)S^7;EM#yZg`)J$pNd+MOH&u~OA>R| zt+{$S$Zm+jJ7j}+eHAsZqWaIM{;Nu%3`AWl!1e4YT7)mzSrV>7!OeUXsc92E?=cW5 zjiyNC1J;HG4iQJ;aaP8LMmS4T{JGxPo^@ZA)g8|?4~s$+Ef?>*Xba2%Dgwl=EBh%k zaBhS*Za={9p^$U3COj7t(&4{795-fHH?Ae zbepI!*=iL`Vu-26DRb+lpK@Dn6jg81G#isn+zWfas9ja$7^dfKKi(Z~y%soS!c6g^2bkmPgNIKN`-`#3Hh?x@ky_1!yIoFY=*j z_JFKymxs0+_IeD=D%uDQVc`EaE!V*egoGb_sF-OTuN5JrX)-F9zh`z#`c*44f;JHq zjc|y5)?Eg>bL&B?tB#)}!B%iE{OsQ*FzhZL83F|DQx3BOl&mpnqxB~idy;q-SWe^; z=7eFB-8znVRbl~QyVB9p1NbEYvtnh#^0mHJm47uOToy3k?dv)LOK>I?pUCoS)l2|JZoY;JlJ!tn8@YEjtY9-Dr|}!*tw!=8ri2VmWQD(M`^N_KQDj5D{#K z`;@4Yq`k!aOPl}!D8)ZQC`8o-=X|@U{F`RvI^$Ji6nt>WOJmSc=T2ke>jS2?-+(ahNHCNN9x*3bR6 zxGvg{8QdD)H!_0vjmE1_eOfq>Z@O^f2P+0JN3*Qkv2q3(@r)I3Yjm_Ubs^HKEC;R) z9JY{87w1Hj23IJUlg;KWGrJM=Mm%G9;IJ4!{%wEDouDRN*NCzWJhqdV2O;v)F=@lWFJdwTi;zMWiLNOx@XX9PJW?oAS)3J zgb!pQEg=os*j{KPD-|)(p*0sN{DYb8c*Jb(ZeZ%%vtSaKH@P_;Y4mfwY=Vism_3|z zn5JwtUVH1OQ3veg@w=`|uBLGJj;KqDMW&PJ)jdK;u^{3laGk!pF4ZvSZ7E_vB-wIoZZV!aDv#&8A4>BN3JG{kQ+z?JI2D^HQ9^=%E`=U zPat@2gttEb8~Mp-Id3+Q<2y#gvK`CWhghS2G|lP}hZ(Dj=LZSJa7X$-- zQf^+fQHW!OBZumMW}3Dv>LtbJ5_qDm*nOV8i-QtUgMqARp?gKd0)pQD#Up4W7bmXT zcBsT3#@a3l*uY2RryThlmJ$k;qRSqU0|CQk--{jO5-TE@P7zv=dlyRH5rI76$c8xj zhZ!KXCJ{_q4G=anIQ>%mDmUg*J#*9(OI<6;L=)H^1fI zpc}sdZaEw88pad*h5-g$!+vSwK~&${ST$4hY%#0!FV|TP~chXV}j8QiJJ?VS#$|3ZMGvou>j(% z6TSE^pY9q*XNTN0yxQhFTmvy?dgPCn!@^p&Rk#55^!`Av$CzNqeCfFuSm>=_WUDLq zOX4-L$S?E|W(lexj3LS+2!M=ei(nJI+@t~k?lGsnz-K{2kV*F-w1Gr3hcUGhC&qHGPZ#f(SCkDUnSDF)~HU0o3JH#;`?1?HRv zXC1Vx5`P5UdPZ$lvFTUIJkh)ZjK$4@e-XE$)1XcFw7nH_A+(ImYI#=Ao_=U*1`TVO zx^%($c&&8Ki!zJ-@3NV~-8`G!;qJ_e-!iwIqn7VQVLy@n25cNX69@bMcm-~ z%YE;0C2t>6cQqj1oW)X-Ha65|&tg|eh=#VZtJxLL>eC4dapKtF^JWQc1u0WlZ!xq4 ztns$7nmhWOBW9(d>Mi;wZ5^#E zNO&}db--(EhT?YPJc=aXTk2Z4EV^x{`7#+Kmcwgew~5~&CU87C!bbRY^BeAd7der+ z>l@8)9KCnRW+r8TNSG$Pb%zDXP)?Qwgj>U}gW1Gd#d0DM14uw&vKg`ogtL!k zItlYdbU-Vhm zQAx!Vl^~gxr40th`II`DeHVuuW5eB78HbO}Vl6RZ;&Q?%a5p>H4Ds6Gez{p5;&($Q zcvQmG`n8C7Y#}pqntbN1-~UhPax5UA2+kP?o#J`5OQfl5Mp6_prhh`!CqB)t05EPaok!TMgmefp(6(Y#os%A#eh|F5pWQDQnhxbrtxNV@Tgokn5gS^2m)tJfx z`{KToX;blk&phegK!Puj>>w<^b@Jb*%V(6@WGXB6uF`Qoj=)fSTo@@uzokcF%prCmkz|r-4UE8sJhA|H z9z#W*ZCfs6m`FN+fM7w#F@NzkcVbv?4eb#aNtmar?e>q|i1c$y>oyh>P9>rlZ@`P3;E)T6tU}Zw zTg)=aZM9l3%TAdPnFRtiwc|k1 zyMYMiWSNv`M%erq|2Dz|w2CzqG$A=$(E9W~-ua5C^qivHRmpR4c`3ttfo1-f;{i-DF3r*hJY= zUzm?T87=1*uF?J?7svHP4dRIv_5jCV$o*mz{~$k86`;e6GdEoEO^;!g=58$hv}jU| z0xE|@?vWhfEO41xbZ$>*V(GYBbrlYKQt(88UaQ~kuF zTr>iOxkGK7#!9PF5=t)>H&+fVR<`y=e)5a0U@3M-sg_Bhehd!BFFqA}ecf z>)y51Z26cedMZ|!TppcE@pOsh29HAV9ZV|nF9&Z2esOQixP+Ui-r4Y%zkh!SO4Pul z@UA?ZLCykfwugYzMiIfPgtP725#G3|)Kx$PDW$;G|czE=Bs-8g;ZP$ohkdY!5srAZWcQL^ z8T2Y8JA1Wu)O*p(vMG&(}~CTe)PLVGlG(`Zm}YJCjg z*S@MQS1v321@%IOLIP{xnlpJpOc`t7m~V#OHn8=$>T&iVujf&sE%3=!egn+>)zCm5 zg$Dz%QOs5Fyird1g>y+Py?n7tGWVj^;DLX!1y}-ZYO?_$gJ?7shJ5irJuFHTfg|Eb z!)SaP5|#O}v!ef`U64Jo2v7wA}@hwDft*(d5FYk^DqMu#z zOau}?#f)fRP#lDpnTRoQ1-9_AuEPlk_((Md!w?naZFt)dm$ zoGY0LsROFRx8@^R>=jM|pA1o0^`r=wXyF}xu#2j!7C$1p`YKcy$s)kVsbl+(^DGzc zNt?%<>*C2fumFr;^~G3J8Wjwf;+#*4x`S&uL*ryk)B!wQ+2Zwmp8@{ght@BEG!A-p z-=z9toBz->0yuJMj!Fe-k~OD6ntV5HX1nnBc4l{GUk+bu;JHd#nHneI-B=+2fQ)AO z>rwgM!S+Y1e$X<%CTK0&cG~>SzfY_R5Gs;1Ba`4QzPgE!U|$C{g~c;qjyP(F;j4JT zlrmOU)aKsJ>JUSaZSs`K?rg;_e$uN%Gg(+da{FIB8GroRBoWv~GV4wl;_`f(5 zJF>hlsvmRUSyuRzN_J16Es`j-sApW~IS!4L*Zb1qXE@m%g zZ-h7Ebw2mL4FGUa#Kf$bTCKLi3h>IrhmcjK_bh?~aPMO0QZ$MxrM7sR8K3uE#Tk{} z7EHy!qzbN-&IA7vQV~KiMHgKufF&XOT}|P-#Kdu#8*0SeK~aqGNKOioy!cU^_P6;( zdm64Srot9&XeV998&D{k`1oUBZBi7JYcs5^y5n*(HGqtv)jU%mZY{)~#X&3C!Xa;9 z(dK(ldECk-+rsr8Da|g;=onuhz>XArl&DKUB4q}#F7qk02&T#|%om0}hGQ0Vm@=g~ zJn}l-ieekwa@6w2T7Hv%R?Cx3oC^O_U4ow&``#k4l}?><>T7^Wjx9bIl_Cx`EQUuF zUM$oSP-%qzLnON}v!pe>*VQM`x}Q*s75;lbp$Gb?IIxA_=%i?l=neR#BTkr$Wgz@4 zQ00Is60O_SRc0)}oMhDvj5E0A&y=w8wtbX*5&G-VyIxJ%^Ox&of`yYIIbtx|58l5j zg|7Jq8?S1$q-5!ZHF1Ci%R%!B(*xG?7vNp<2(>U`7;dWXE3fZn@8W?i74bK*8xDK4%7TDgQ8{~- za!Xkz8ZNeI)UlxfP+E`1tHftS70hBzg4NW^yIXFP^_?*P?VRRfsj(*-2MVxA84N98 zr@(5Wr}%2;7-I#?b4Reg)V$XCVX?Pgkvy@dBM?1F|BD+!;oUZIweKV!Vz3NgeGQGf zYL-c0AbkleT<7`8(p~=xN-`*A*e`z3FAWD_y-R;Nv6Bjd3z@+IL4zTZtT68(@ebzI z%6kEl2M44{=TwS)L$y_jMmSt`J1Z7&T>C$(#F-Jyt8p4EyeBm4>GLaSZ(&p;iHH4ka?=}hDjQb|>8iHX|9?#DiOaVqlt zxrF~x;tKG}iz|5@A1(g|nPZlV8nAG^^GR*Iwsc;gGm$2-3owATMM`8Yt8d~A#!R`n z!l_9;6BqJiPtTepQ3zDl1T_>eJ1*vEt0@U-KrW;bh7JI%7)2ol^=;fqY`#3t#f%C$ z`2%lyE@gHc@J4QkZTgr0RZDMZ*Xn3FL#+rj+6|3R!bvMU->&YBQ); zyNVCyc}m}8$3?oE0D(Z~BShZlJZ(O2N>X!wNS2n20U=Ec=mJ&gVx3G==Y|NqNW;W_ zLPQShoLgG@pzJ^2I=a;d6PpU$P;*-v8f`Xw|1ZA>+awS0Z%gYnaI+=yiWbhxM#*($ z+u^6VyQ+VS!V2`&K-{eSkXO1^oBZ^wJsXJ+W|9twU9l=gNml3ca9vkmR2Z|c?n?a; zC0=oC(m|yq#=LW3_nz|~d?zYzA@k^^z;8vZLf3{>zv)g!SkKS?$vx7kGncH^6gHI5 za4R{E7*|6(_QHNk<26VHr%F_Jmg)j=1XceEy0ib;O8;WzV-=LZQd~o5XK$C2i!zd_bDTBvsq@1GWlxh0s3GBvqODRNIdvP3a|s>`ewUx3gf1o7G3s_Q4mmy&2c}W7>yS4nwoMx6 zW-R$9h}FM}f0LbxW?UjNsmT1_hCyvLCu}o#8X<#_J(m>b>WGTd7NtEGBsj(9ol~_JXA1QL-&oNA``Mu3Zt zN$b+r(9{xs)9NJAc>KNRd{(^1ZIn*v>3JW$fh{1f;ZK3%(b{x#gy@0kO|9}30xLOgKg;Gp=@@|3N7PUzYh|SmxvAIE*L^cOhx7LHT#JlNC)Kln)426Or zW=?=Hln6tXP_kGd@-7>*b1qLVWT@I8s8~XK{K(3+-3Aoi+hvIC0TRrcRBp}UyG3(1 z9=}&$A66wA&lW6M{z%u5{7VWHVMiF{t4>+XT~VZS>#7oLj1|Kvu??(n)1Eh_Ec}A> zS)yO*9|9&b(QEkSC}{B{`Np+&BT_HTgs41-*T`JRM;2l0)_Qa~IO+rI za@xiy>K-YN-mHC+C}dfSnpnMlIQx=f!AcFl8A+>K>M}a1jYBs8qKXj=dpX6TN}kOL zHcxlYS2o+FMFspkq2gN1Un@m#t%mf zh$3|@@+tQ%@SNLKPD%WRFF|hzmQO$ifgtB`Bq$#DOW6Q_d}_^Y?sxH&2;n+j{I-rw zOcU@5f^dq^%wo={ZF85#9>x8{y~`n5VrCIuMH|y>R$>2f%r{pAkd|n|Un%uWIB_N* z0=b|Fg4!pk?*pzEk%NIrXikZ{9F6-OewT0yl?GzQL%8>@N*=|d7{>k$v)~<3)M6|5 zzB04B#mRTKP4k!Nkt*mo4{3tL96KreCwxmg1A&Dd;n{>zzt0y2`vj(B%R89qrry5A z-a*JaaI?22cM&H#dp=o0JF_7YvnI%~?UV8h6q|)`Ny{Fe=+pj_EeCu3)+utCJF}yq zypWVn4#@qy5Ev@&^8K-OzwKZy`2-Z@(QLWvI)ol?)`6;;w=Mz86H={7yE(zHK}r2p z@r__$*dj(n;(|@2Q><+xUVU3Ni=ObL>q@{J`D5Qy(?rDdSY5cLV!aGkAlxDBOtvsF zLx@ZsO32P1(s<TIGeORT{ty+a`8AMszwUcOt_@aVQq?dc!yid?IL7_hk>J z-pYb+@<;hYUJuzlYVkj9x8Wz^__*Ylz7q>p!D+(rpzjc560Qeanu>N(Z!wl2Jx+5X zcXn=f5Oe~;M3a6ncFn)$&-+aYrKsI+loL(z>4(kR&rPRw5ZE=CQlo(Fj8xH5>VO22 zdzo0YdLF>tXSJzti!&2f{~&kWD;{l>cmAj=Ue8sPC2dbQg{dT!`v&Oe%nb}T`4NiT zV$PPv94Oo(uBUm2_QzS*C*luLTezdSh25p|**2sz?fYKwD7;-fR!$YBqI8!7fRRV< zZ2S}0j1UZV7tV&TJxOXYl6iiBz8oKrieKc6PmdI!lZL z$`{^x?_tU}n6R>_ayauSW|Rg_QBt@9-dL7|&&8evB?7emDTHI_)|RO$aFVZI=J#MWp^!|U`|Ee-~b4l!p8q8SpOQh@`Rg9bxSlSRr~QLvfP;9Oy@|3vH{ak*lrr zB>^wIU=t~$R_Ti<(pm9HPyIMWEGP0EoFEH zJaQ*jTblM=mObs4T0xV=V~r+}D@w2Mn@^ZO`~g#D*x0$7wIo&=#!lLn!nYG9Vb#Le z4RQHV&-{%-bOydlH7IENRvQH4V_3yFRM}+bCwT3r+oBkv?K&{K9OfitN^!Fcj4hd~ zf)15^E@i%qsM5DUeMYL8!AFVl0RnAuG2rd+HT7aA{pnVk?hDGw5s&)qpZhI3QJYa% zRU8hW@^A&H5DJfP36CKgaOO;C=_eU}Yd}a^*J}A22MTQxG zU>F@Vb%<{i`xGL7=nH|^DX@v^`q%Ky$f`v9qytkxL(Sm5caq?!J6Y+;w&O{B>A%>O zAkhnrzx|EGGPVf4OAH8F-FF5Z2Qya`T~VDTGXWYBxu&o*;%&6;bw4duH+jh>)jfgR zXHhI_Z(7<_`olQl<{if=#K%)J=t3fz2KbR^n-()xOu4kXnrhWAWXO7NlZZrG8bk5r z?zs38MPWy5KZVsu`KPjCjL4ha`qxGJ)PUAPO{=o)SMZL}%J44GMo(!|s{LInJUGBKCi5orvMF9u9@%uSqeAFy7vz` z)kQ^Lkb`q9IU!1z#ZW|mn5{4Rc)++2>t7fJ{{G9yl!%vc8Iv{1psn;w z5+`1A?sj%i=HT^FlR@M`{2aj)UeBW6Jz1;&K=iCQ56#R$al0hh7R}%*;u-)?KwdZ% zQDy@IKPA%#>Tkq7Y&5D<2vzXzc)^&3BHw!bc2J&e0k#*iBVFSWa3U2pw_mXHv=Fc> z!Vk1lG9Qu10~ffP$*B17T8~Ma3rh!_z#9O5fg_y$XZ=CgfTY0Fmn!T?Hx6)|a$`@h zlIShL(pa#p7sZ4#(^drp{F*QEQawcukt_{qIZ?IjLJ$~Ls1N6k$tDClnN^I>uy?J{ z0(N04@~y*9(qP04K^ECyv+2q8YTgRW8^;-zRi`BoH6X@}fAP+=*f*{R7DL-YYG@GjVIEB2Rgv1 zBNU_g-VPuC?2%x`M)T9c!=+{t(VKtxZ|L6<5!&X2_`MR#i}bKk0n{-DM0B`Ve1mus z5=k2-RK%b0`Yu((^G$kAf5jeHxAjOMr3gk4fKtlc=YahLY{O3gBWdd`@z$kF2bHbQ zy%rqK4r7&Oafqmxt}eJ!o$VZ4H6pYJ`kW7%%ygJsTaL=xsbc2VFMtw#_B$I09HMA0 z$+WQ~P3@u|L;(P3PBqR;c0)QFQm@x4wKxYCr-%=z{!gfyj{oSL^SgcTjVSi4Lu6RM zC#o_yf^ozI*!;gqd;jP-uItXTx>RCdg|^YpjOw2&iFE z3AOqW?k;ym=UAdK8c#N}5f#SaX6D5ExdlpbGPC>7f)q)KE%fVG_uc!w-}}Ay$;PJY zJT{h`i;vHC=K7$6L=g{`kiWg)?f2Q*AaFpw(uX5u8>xx7fB5?!riFT;BoS%;eFuw~ zj;TEV_yM`tEreaM5`yt3<~|ydH}U=1 zy0k;tA9_QP7!Qfo)+Yl3aRt;1FjUEY#L-(s|D%_+h@Lhd2ER~qmmQS~@i599dUX?c z{eE8_JlUd%7qCM)SL~&%xVM%Y*qG2e(DnL#@*_Bk?d%1n%)vWPz@nTB3P@4ljKQP!&bF6V zc^KhYIg1D5(*k(nxN}$Mu*OR|_>NG#9ocA1E7*0arF|mn`}Bs8MwA|i5v*1a!mv)e zgb5j(DA*KIgz1qBsZoGf86Rzml5!6-!($az~S0_u`GDYH_ zEXjumIiqfpEbq>R2RUcV{3IKLS?R~|evlUf6rjM{gsG_Z=GAP^&KQQJ75(t{J_4WY zBn=XDF=SmQL=0+-SmAk7O5X1XpksvaKNb4-aKb`62G#a zm_m}tV+T01SS(iRURVhDOZGT~v%N~M*kblFSL{l04Cc6vPsTr>HmaGVYieCGq219U zvnP`H+UwDwWzzDrr1OK{Cz9i`&#_k4yCf-EQJS&&O@O%XCl>*(2vf@>Aao4&an>@>v%!o)K zc#^-@IzMM7k#NoP8@*-++IgvXEk2Eg@iV>1QDwL0L0v9YH>qi|uc-;c|6#TSc>!X; zFl5N<>Ji*7?3q^Pn1*!4(1!GxXj=kOEU^JHKO%Kx?XU-%6b4O}A!aKL2~;YGp1H-a zh!+$8EInsXXtRP(joM**PEJ@SzhiY09f7q38fA}7w~ zmq8otgD^iS=OGSlYq9W*QsQ^FYJY2eu!(l0x9L$2sMuI7(MBl#uqdZ2=TfgEkO{@k zLM2}y^@v;7ax^_GGZjS|FA#iM>w*Vi7s}&oCdCfs)F2oz<+B4Xg(zmQr{vG)n0Lh! zWw+{02?u@2po2jWI%iF0 z3-BJ6AnDiO8SuiKNPc28(iIm@AKD;;!3$37H$?g=0zswludh|U>7{&AO72)Dm!JYy9aS{ zsx#W80s=D|r~;;W?OzzeIxQJoM6N>gKEQ9YRaWff5n%a zkDVqS(5E*+ovJT0n@Mtq!UFRXRLd$rj~pxf{hhs z3cpKxPvJY#^vMQme{)@p6qf1;E1jqT{l)sFHw)4*0|Q5rBe1-|evB2wC&0K4*Us~I`TRy7`dV zd~f~hKkDTUN1kws)@@?3RAH1ASonIj49jI}IBIWTA;pmTJ0hr?_iz2;A-ItA0i9~Dh@uDg`-W23 zE_6CPgYQF(VHJdp9$Zn1UJJWA(lP~9Z0U=pz3^OTQy}QYqb+zzB^U~ou|Bh$B z0@=XGObG^3e-pm(96rJBWuCoLSY5vOdX5nt>~nS{BI;$HVY*6t=!|JWw+Sq$7yOz=cocM#PyOE zOTmI(p#g#Hm%UI!at%!7rI&DERjpmd}gCJl{fbCe3`Z(s?T>85k?T@BpG;ZZ8IRjpmz8k{m z4Jp(U!PYlgXimVdB)ki+c%di|IG}wr`jZ&#+aKH;!9$lZ2;re-xWz7-OGx~f^*R^! zQT|9C%ia0&F9_*Mk_xrUUQ;b(wMD5a`&Nl_PiWxNKqeH`JXILRD7~OxP{GpN(L#Zs z%=Qj?D^;-yF$yRh7Vty-=DavJjg#I&M-I%gNvCNHHWS{jO_2?!1U>yQzWee%GG z#zZ*0TLN%QrlM<)d)E^J93)!KZR7sp!w9)QdANMQ5J+!d3 z|M7EEH7J+jh|3N)oAwaCmdc3`y|P>=7ZEH1+=z7ip>1QhV#<%`(E{4v7wW+!bsi@- z7wpmP>kGFd=G;hDlqR3zD?loI0$DvKN&u8Y2xv56B5k#lkvXe(wcQXxYE zJnc?qGI1&s(5RG}p7M4N9Aq@j$@m}ro8FD95`P&7F}=XUF9La~zp>w=1h-ygyo61KBgQ34lYY=UaIU-hnMD#a0H9zWyH~yYDI7<*86lWk(5Xz9BF?!=SpyN?i z0y~1F5J$8&wqK9-@$mUbeSE?`TArj#;9uCst-n#;iE76U4}-a`SE)BAESnM%(LZf; zdHXr5%p8Q%#exW{RB_m~x2jP-z*f#-8jwW;BLSVK-%~o$9AV3`<&h3Myj2HBf28&4 zx{Ri*&OuV`(W$$~nX&k^_n@En^^`EdGUY(5gs~r}INP$6C$n97CTz2eR9nZQ{TDww z-3Xkp9Dt0=-P)cgo@9;`RSTvxrw_0{zV+mH*#c>*`M^m-{;>SP<_e3RQjBfIMGvMNz>k%rJs-dhoJV7*s9rj}gCpMcL0zoC|3N+Ax z1v=KfR5C+$ojP)flpQP^S4Z}79apW%pUWqraTa)h!n%-(KJM-}{~0GliuUR>E5&KZ zA!H65ydWBPJGkh&7^+}?ao1=C)jWYv@i1_A1>(wKB~D~pa9q1*^zWE&bc9h@!0VzO z<>5=%0L`Qp0^$@OZMw@q+S%GN5oc%oDse-w5g8F5&CSslx$gDS*uB$m!EQwBUXn1J z(3_OLctp`Z{@BKt>9jo{%Hon5Nn@bWP0`&^v!z5k5&+4uj|6BO(Y3vZeGFgH#rozs zjw1mP0&5#7$Q72X301VEvPNnp?J%8mViC&joUv{`5 z7iTwv-;m@f+>NaLWKup5!H6dQKC>IR5k@!K_mGXt86*9~Lyy`bwI0P0GY*0@^@0Q& zvgo8yZ=P%}%I+d)?92^5ppG1Upe`I2o%oIfZhD_MUIJr?DzdraR8!SVI;%sF9N{8G zMTjG=c7?{4vORju81-|8I#Fs9#skW0Tpm3xgg$TP8ic_N_60yh9KCi66br@kB)duU zuB+{87=Q#~e@`i?82UrvovCWFbp#gJ7g;t{=gsEGrT}}Ob{OdMl_;V~|F6-x=#vCO zbaT+T3mG)a+_yvyBI#0D2*Q~*Z-1@3{FE2F4`o3+DeVI5!pDl%SM2Pf{+3)volZgx z`re&0giC2$OFsQ`Kix7O4{=d8Fl~FId(SU|Hx%%a)8_}G5sX_*_>^Pn>c*Sg4mgg<<0RF=7H<6 zi&|Scpe}qIjjql+mVStW_e3=Bv>bY_VHcx`+@s(92pMV015>w zFo7NTk^iu9IV_7*Yogdjw=l9K9qwRt-0CI>9sy<~I_W#1%Wv4K!3_J$bw(FFujdNi zf_R`w0&Yi-qNisWvq_>74iMDhZx|a_ipCB*S7$MV&kgo4!E1oeY`5i&bHB#K& z2%o7G+^W7!a7|Yw(`1Cj6F5*H-+CV7lRtsFSX4S(O57!ucAE8WsUOyY5;qlIQ%hJ_ z1# z{s;H10$^|?NlfC}Y{J$Jt|*!&sEF}f+A%@-UitD)Qd@<9lob!%4890s$`F^efL4I< zIuOel9mnBdH-G!ZKo)dCl#OIw0S|?Fnc`zPRd53iQWd9k)`Wty8L`5cvBcm3`+zUN zb)dq_?6@qACz;6UdrdLwfzt{bLzBDMRr)0wmULCyNLvmUg5h@x57cF-c$&J9_XKAB zf!|#i>9z^UAq*|-(ExMeI0>SvWm{#t)&VIP4_tZ{(Vghla5_)%KwtKeoyWI+=2_95 zrz<-nEGGV$?K-W98PW~|i)rIRnxMt?abZ-#SnOsX$0$*IQ{hNuiH<}W=SeT(w#4bs zDZ>N;z{v+&hwC?Z!mCN|joQ;*`)LnsLJ81nII==r^PJZp158Q`MT`ONc_mkSTn5ZO z2E*{gr9|DUFYN1xggfc5Kl8jQ}@E5kkTeTkXJ1F5Qnp~ z`vV_Wyqz-=P0pBW&|$Rw%+^{rqJ3aF?g!Yn@Lcs?6pba4kz^4gT;g;9K1HQ3{2RVm z(h_(K%!kK>JK*U>-zjpyxzkfor8x>ws5hZbDvlmjdq@>YP4qTAX$iepapiCy@nw8QgV{lGo=As zv?c^@UilV^)w=B~%#?~%jGlMf!yxZ~isT7sqD zR=BR_f^X>=m3}^c0R>U`a1RofCBa_Lu*q4Odn#@_4w+@lPS6WMWNjqQc@tHPgVrG5 zC5nQHdX~%Qa##_sYMuC%`{Jp@N*1ZyvZP{RMHSvq&6}(g{9|>PD#y2?+z$vKk9cccu{;AZQjCHb$69paF%|+3v;|nqyw~IU2B?CJMf%J7DK-M=djJ+`X$GK% zFs6hshRsGAw{S4*zUaRV4Bdy?yO_yeFx8=ZBTl}V>{+EF`jc@Bxc6$ zsU!ELUPO?BxF9fPlM<2)db1%~{J{5z#N|pLIW2k)dC{*ow%(6oPnGrNky5-9AM0X zCmZ#qh$ieJEol$budv9&1tL9!5NoWS4AM?|8E*#KXaj0RUVC>lNhG^q)}*nIGu6!{ zoaMx7WMrg)*Y&$T8e${y54q36vCIYFg(4Iy?*V94++x6@aZ;RY%XDS za8fv>VF{mLa#m?40bm{NHAgAxIn@+uN-)P}jZGGkl{#IBoTCwNq8{z)Q^D~nFj)Ep zGAH@Qa{my0y*zBF9(mYl04M{pLvqSxFXTlD3C?8%-OGh}W(t^F-hbCyf zfP9aVJ&bH&Tj3ID_>1}`j6wT&^rr*>hamkKdF+R>G<`Y0r80q{Fio&5^7AjM%yvW(^;yyW8a zHiuO90P%-W(7i$th3r<+&1ItJli6O}tH?TKnf$C_y24?_36y&c3x3@IASBOU%>3bz zkJ2q5qAgq!>+H4tRPieyU05^;miR-WuvA3(Fn-a8*&LE6Hk6zF3V(-WL6i^@``YA* zLg=7`XmF}P>mFBXzX|WpcCv3~!Enx60u^)g3pj z+AKpfYp*A%R0$gOj-HUpU0TYf+#=$CIrTE9L|l|aX35M`wz{p?;2x+kmq>M{ zn|u@wet*~_M}!reORbWfl?8~(o2oTk@{VuH(wT1qZo%)i zinl(M#X^#GJva78N(DO_Tc#Cr`T9fyAs?ZaqIYi( zXOXzW*^OPgUGdwJ#R5IROBl3BvaSsPKxo@bwV93eF+V{NV0R%KoP_l2-$+8Iok7~N z@b)HW*{ntk7$6@b;@njBkWx(vI=y4md6I;mP*Zp!OmAd`I4OA>Mc}%oSFbLLoUP1z zqBXTZ)FIuTT^jmQ`szg=)8QGX{hHh*CY>JX29_Kyuc6ZiTZnF4&Gd)dd$NE+poQp= zcFmc)$A!97xECBv-W`nBT3@csUMokxHSmhpcTME4@#p_r#tbhbk69R5kA*=Bp@&yw zd>R|v0o=hH;Yy*(nVpB)^t^hvjuS0PA6{C{9uXMZ)q^A>?d#7#jLzemSr`&WOp}Tk z2@%K>Uz+yT@O*jln6S8xC$l@3UlN|PouVij#V!~uq~U}VtE8+ZZV9GN>T4kC+7D?v zWU3Mz<8toZ;(p1piS|or&jAt2FOBh!-D_LE>^QDTRxiNh{pMI{)YMhARzSCjWfUzP z$l#?GvuoHp#Fo;gNeGY=CH`N`5maidRSuNw6QP!^z9D1+8Kx_W0qH>&<1hjDAj~Wv zD%==`jVvD!!1uN9qBjmX+-(>14-d*L7ks+(?2CG35H#icEJ3C9Yrrnqpp1wmDsb}a zWC`?))y4Z?t{3>D9+dH-n>wxMt1>M{)LIZ~QX&zd-TJCz6jW-_pbVHKBVGQj8|@t& zC6QzCO2QY^DL!`gd??*39TV21H{mkdZBPyfaODn|5LAr|ehpRFozMLZbL@zydkPOqQQ8LeviYOkRvv z#;l=qBF&p!;DL&TKsKWCgJ6C#n_oYf0tibE54^j&ae37QGAomlBV~>6|JsL29`lUb zD@97JOI)gKgY^gmRv_bjnimnm5^;swVMK>`2+Xz#G`P+WQvLcCj@?kx_I)1^dvRJm zWYW%Ji6CFRJj=i$8&o3GD1gl_TgmFcMssZ+k&F)`1d<4jXQXkEatZhqH#}wN*Ccg) z(}4fbDV`LqJ*vb%YRQL2(hoZ2$y@O@1W5fWK6%^0xR^H3aJ{epX1YXIuBl z5ueEQL6_mYGHyamnsT)`uQI+1{|+?)Mv7@UDU!IbsR%<-#+HUZc9B*ua6q?A?^48t z+T199>c6u~juoG0ExpGSk576`3iP~SV1k;JL~ugDI^=ADN19@YZ;^ZAp;GOmI?8Jg zH@m>qO#w$&bSv_#X&z=73+c2;?;QR>au%UA8A%SUdEUrQ zPddaC4%>>uZ)YcRG=vIJT@S57 z&Wrnn>}Kaqh6Y`k6mZC5^B2l@2f(d~XrbCQyG@O{nouclMN!Ym*iC-@>b*qY*vc~- zLlQg%4&fJ{(*%Md7W8n4aD%n$SpTB&f?N|yq6WTgr zEV>F=9?y@n-DOj|)|G)tytusOLF9MqwxRPTa3)0rqIV{e=D(DzdS+mThO{z0mAN~= zvV~SWkVi7#RMcywhBs<6hg6DUsc3A8P8g6p)+vbxy*+?ZdEt?5oTBgPk%w`rLrq{6 zBco?j+oLreHW{ge)bBV(DQi7}t6|kVU9bozK?;3vRV@3I^u5256Gg*v+WFjQB^PA? zQO%*Rxh8#;*Spt~H33zq_q+~bK1lOV|5r@1%xxs8!}$oU$3O-J=InIHG1*e`6q!6x z0JWlgBbe~loGAi>bQYz-GPf8`@XrZ3ROv~^7mA^BRyf5hGBzx++huTcZc^H&;HISU zS%yti#e4BWIq&GW+btl@tZ6xu7|_Z1-GBezVD7NN+bM1+38PGOMXm<$q#O_c_AQnT z7bBQog4pBd@&A+ zFT5c;6`)nZ3E%@rN~&TYWX~cyV+Ijs}+zeEk2E(^F!IFGhEs z!>e6|n;J}m4eJZ0m`~orLl*~1-iyBOE@)h;pu0S}R(Kw^`6%A1GKgTb9$aWm06f?s zG{7Rc=V&J){vvqG$A>ma_)pgAECSoEv<3H3bLXZKBx)_5JU`h_a{ZnBfcjtS9yd;c zi$KnnBZej4f89pg!gfjCVaq`etjCn#YSr5Ri~uOUJ8+*`@lB><;qLWVeY;kJ!7|P#JbhBDv4fcR!N`t9q_q&Gv(3yvg;i*|-SJa#nYqV67g z@S||{C&RtVuVX9%QpK4u$CS3R7C1qs8SD}#%8%Oa=o<3dRmS8%67kV;?z7C-7f)I| z4fQ}8Zy$t7Ay$&=mtG-0W$!3Xr<@%pqH+;EgO<+@+7QK_;2y-dWW z#){+3^+A9@@Ug+^#^O+^JzQ-$alCtAmxwfACHh$>Ri^V<@-W%ifSZ!$j5PR4!dF3l zJ9~}NzKraGgN5AM`@m0eIC*cJx`aPvn=k4dnQ*8xqMKtF5%KWH_k7i4lK+QB3K zmb!l=;6XgEn88mc+z`cIv}}Swf>z*;DSXGhNzPEG|;nS2OT`ucND@5}Ksr zb1r0~h7(!Qt^`kd*1SRo^GI=Zg|KQiq4m;C%fb!yhv}J@8-LK6Ru!VKNW<59LA(zFR23AkrwX2ku9>l*=4Afzk9rNY7?Sw-OCf za)#aKes&{nklYw3n&z*dDiG?BO(HV8FmxZG6?{X@Vx->0yWzM{BFbTU0P)atYl4{K5z~jHNR(jk6Hw<;WB<)9o&Y)JBVJ|D)%A zI!%2=*9r1S2mdl;0f@yR^TiynR8)f!REhqCfRtO6!?#D%qjiR(wTEpb3T&c zpQ5A+xY=Y873?9pu*4*ApD6|inc?P?!2o;~j2D;DA7_h%HVD9s<^IH&PhGoBPdx{% z4eO6JLwJ#L(7XOh02|MY{BrHjxVa<#CWYk**8=wIg@;;6iW!;2{APF1DBYfd)G&Y$Svo z_8VE;cmu0;D&_Z{;#@y1(O-;|c$I=F_8Q;t0IW{t6g*WMN<$duxtKcn2d zoPyjFMV=xqD?RrTUD>$+p8r`0HIfuD+1C~{UX4P)8|sW6ewfW=kiT;f22CqT1rf4@fvwPYSD8r&zL{57S<(jqj^o~6mbvZz(zX=#1(qdoP( zvpncMbzSsF*H{-vy*d|2#7z$&FBVTEm;_APMjb}!nJ0d3pwEN#4dovyE-`E3^px2( zUWy-p3rbpNy;mqe6B4bjefmDYRRTDoERK&Cdjph;f(!-{M)xa%?F8IW$^){zrG&*N z5$IF~3tZ3%5yf$zElMJQPls8+Z~%MoXLxgg;wluQpi2o!8}?}IiwXL%zHcL$x3Mqup!4B zQEbDTh=@H<3S5~d*D=EN$XF<$edR@x$je%xKg=>6F4xMV;YLJGhvMgcv=JT%i!NHD z_NdaF1HfpJ`(2wCE=cDFKm@nmVz=kv_qIz6MTWsKl396DzH310ZR*6rpL6BC1V3t{ zP?Li1c;Gxn%PfvZa*AqS#`3Qx`xfMKvKX9-C+dXxA>xiCDsq!4Sqc|%*3NoUyl2=G z!`aiWCR&pi?8=hE%A~SZH-=k_IOmq ziYPFF70Ki!Ne`(2Kqrdh5zfY#f$vfTjmg3W)|M%i0+B?Y&$OTZPIeYyAnv9Y|LBxY zFeakC$~`wz5n44A_sRV)@u)eX$TS*Fwyq>32UGaKR#isgWB&x~o*2FuckezgTn!4U z;V;(fg%QA99UnZ!U^Cnd;H{ryAc9*rIS*+>Oq3jx!pCb1mm@?50AzYXAIg@aB2Rce zL*ks47J9E6r{UKl5GmF^(iU))i$H2-%!tWX^(v_{V2eiPX>~ z;K|KXsu&EOQ9~>0bUi47*oNnV;I7P>7lKa!uME?`tBUwmgsdDFsVG>K-N$R73s?p0 z6ygqPHpkflJ@+S$E{#)+ClSSxmwR(UHRa^3pL-+&Gg#_Td>c_iNuJg#T#cR3rJUgU z2yYl6({A!jrEV&&X}%3NTIY4?C+G<76wKpujHMH=_lW4=d-U=GF$=)#zNX33yT6j{%B?BxZ>M6_|BJ z_QKoywd^ zC!weXrN^}MGIcD?DMOAU86kqNRg@rD!lAIQ#`LRw3y%>bag1r5i4SE-8oAtZl5%9Y zJcJLn?b(l%9G)l!m&OshU=OpSqV)pc4pm+71c{HJiMX)Pv~h{2)zBM&_rG?HSl(&|YO>CPj6X@&4T3rb7!a2hghOae=)__BjiRZ4M^M5aCmP?qi>%FW~KGtuR4 zKt^*)Kt34=EyOD28lN7vlEzpzixN$Gss$8CnAsS;D35&g@&GgVNoP;W)Fb5IjWn}J z-6BCyCSe`u8fhSE1yFi!3sv1w&Rr_pD)giwMyhWlk3K2-(Cjn5IPJ7bl$0bd2D*V0 z>VxBWZ7j6PPykIcxQ-CNz&9jx7CtFc9it4iU#&;tMq`Y*Rz--njZS_@Yg+ z3Fag(WB4bLkcX`&smS2tStZ15)CzVGT>+b){!PgqxU&Kj#t|=Rg3GXgZE3VX%ED)t zf8qpi8KV;`AgC5~;E1bSbxa?_iPk$30I^w4LR#*Emmqgxt>lg3!o>rbp6I1yd71lT zVAOXr991y8i|U*pWN}SX;OJhb!Hi-aFta9~%01=*geK^RzVTNdSp~>(C2dg&o_LJ~ z!c`MQHjy$&F{1^`CbiCVH`&%i9{mU+BO>;2kf0RQqlO#bszdv!Yhu3gi22?wtCTKz z5QDf$3pBL|rjS_V3M&J@fDPl1P_S^w0X?BP$d7MDYbG#;iV_#{C2tY4{^K&?8#Gqx z$*)%>I55p)5~xYP2!YR%O{FkDp~dkj7zNA9k8A%it&*D@uuTC=9XisvKnRW)*~+>8 zVT{U}P{>}UbE@#>>uW4sjZSj>Vj?&J1}7vAh5^+eT8sSK>@sH=>|)N=s>f^2>cH$Z zF6kXT1eU(@#6RjqmnSu^_BsRy2!oOY7TCQ0F#x_K> zWN+b)>MD+k99pJcpjm(|TE?j~(rpCLvK2h7+D=*KBFYft806-@Ohpwsb3eHcL~<{C zH`Pu^CSF|5Ew_DcJO1&{+ye$8WhGuTL5oeXLpxxIE2ldW2bm@^ICD_`l8V{vQG1K_ z3ukoXlM=uWCO(fJWa3j#krZZ!ICI%9u|)hcDVGzU>T+OvTE8{GcstUCi5yuw)%Ek? z{>1kK*57cDDd|NL@^Vj?db51Xp7yQD{{tRtmN($-#{^f4wudbQ@=HaKRSM_My#o6= zG*~2YkN=az0r0JLFf1*%ss0DDl?ZfPbkMwjQZ{}C4TSK%=@@Sgt<1#+WwV=M>0D%9 z>XI;B?ea=O_r3*EUQXM3*}%s#VJ+pg6#iZU>MkU$%U(vRB8^*r@D#V!0Lz)_4l+w` za~0Bs*hmb&I6Xoy1no%@Bn#yHRJ`@5jrC4T3BzqV!8d0{e9i)U&O(t3lR=9=%Jb%F zWE4lq(>6Q1%Tp1<771b#oP8P6fb1jJFLF@YVh)<{tz<1huAeOK@KCKsJ&%6k-qHaU z)}o1EJ&wRxG*fsx%<2fOP$!8#Uo7HnU7kFm_TZJ7ytBMg5OC1T^Qy1W8?pQDyr028Y(Y}!E&O++Nekd7cs;rwMLI2np{#srnM|D z;_p9k|A$wpNhER6YS{Qh(Z?3CKwoAk!bkDEQdgK*Q2z6_MVRhtf2es~c}*$#lSB`l z(NgQ{;ZV(UJY<23B=hk)^DFxX?R$fUx7aFwYC!JcutbC+Tbg&YmG=U3N5+Z0=uwAD z+Zg3Gn0KGKU7G1iYRVidQd4|&owXsCO1b=@`+N+SZz&!&y&tp~L=`~x7F|&Zr-*B} z0&RVxb8#9WHYo;e@>hAFNYEnDbcwYCwFu5ma+;X3+GD6jWb&b4UYZ)xzn?O@QdhVD zUrydonypdtc}(Ki{H?D}Pt` z!LvG$K>;A)=5JGU6#zk=CtkQei^@tk1t4QujF5BDn7R5AE1kK9ZHc+`Cno#z1M3|#*9+`sw1SRg5%+>3^TLA04B(2NNrJLQP5+~DH$5_>4A z0c*e;-GqhWah=hdf&hT4EA|z11{DPPlAk8>(%v2}hdLDJcMvT^#|Nz_fmzUXm#{Ze zTjld$Ui~rA;sn98h$=Pp)>deM7?R214OchfduXw`^Dpj~n8$Zsl-YF_m|HebDM_qQ zV^x`8BW^>Ua?;k!u<3O<-Yd#KuL@i%$Za_KVwJa9@OeX#g-b6D2AD!C4w5AAo>`El zNWMoL{&BW^qfPP(Kj+3VSxY8YWqmp?{<>?X7WUNA+1d>6ugT;dI&MzJUput{)&w(C zsSuN1h9+k?-Ab@Sn$h5_0o`m6@51Mz5okq2i(EmZNpQZYz!7c}QO`3eTq{b=ffGpN z%TkynxocpLX^QHEuP}^>;5@|`kMeCVl?{rOK&eH zD~VrieI%w2j0_+JIrJylK38;EzQtgSCEP0ez;+2bk%4A7P6qQC!e3Od2Svi;53NLP zZyHHq+G`?c5x28Wc9DgObd0SKu)15A?Fa!%oSRBs1++olikF(_uDo@JIA_XoZ;UX0 zqz7K@x4d+v{h2s>YUC^{6cf_ibm>9| z*Bx`v7}8f1$SB-IfWT-7WtZMoa5gFIV6zGKMBfNfxsG5nfo3vl3sfL-SGZj9<8q2Z z3Zo0hYaSzVM0Qx7ZNo`Hz`{pDNICoOMXe7sbE;nAoI$O14mBYVz?kGYu!5o#9 z>PfElA|pCSzj6X8}Fl>&vi2I|B0qpdxOYZc+9#qs8GmuxOQ zx6#2~tWr7>YfW&tNDbZ>#EmFwVgl9VhqOc?)rHp5{fN)mNf|cLD#8!QZPeY5s-t|oDbjUt2z=Yr2iVU$*$=ZsWvWTfd{vu4(kH7K@$ftlL1u~ zqB~z*Nh>AAg3L#e{UjsDV7Cff!gl?jS1!4e5CBP(5*y-PF-(1CJ*N;lMsEtz-@Xy> z46a~)a^*VtF8h%N{B+qwOIf(dbqvk-2qE4y*`CwHGI;_*eu$AkU=cL9COqm=|6!pf zDNW>Zd%yIdkjq&bZ^-ERW)qBQkCH!9eUu5#!fAC{8n}URU<7;;%8mT8RSIM`3*Tc% z6%#$4pv8m^7@DHq)6vEEs#OqH0%1G4|I1IsSn4G2`|unoX(I)UGlwsqY4K z5f($f2Hf&9v-?{Y-=9IV>$17d26x%!>j^~S3~B%%SGbGBsdVSm|3K9gUG)3Ylb#0% zh#&$i0H#W7V;30}!U2=ASt}>1g!c_ZCM?moFJjLZ>OZQp=>a9aVWE|nSN#>iK~P69 zy-%e#&5-G0&%W462|1*3OtNcDbb2N4&6=O3hD#C`H}DBk?2(_$o0< z&9q+)cX+#)W(K2o>*HIgzs`vI5|(gLvH$G(D1Laf$?;12;eA0=Em6vF{*v^i383pO zq8h{E3g-DbR^evPKR^P0>ZuWKmI317x zbiehdPmcPz0%b~_r_V$V!MW(E2s)Qem*_hK+}a`o&(}4Cu2oI<IG! zMeiI{mtg&M#yL;E8Y;Bx4wFA#0I+(_VkCPmmNja}! z#S3Pl7Yzrt-Ey!llpS|kH_4lLz~{)y7a<6PKyr3cCR-BGj=VL|AApU&6n9}E(7CCk zkQexLKPh<-;x8Fn0Chs)c?Sybr|;ekdbdG~=N6h$8(T~$EUt1pT|V2>$mB6<20AjR z%`s&M$@qAUn*&?3*H&`}II6reKcDkI%=)axn5f+e=>&DTI|Qh2_1YH*k)$Z#&vv~j zDHXm&7I(N%Im2X!K~yBPL7WvWA%W7pkA|3o;wl(TJc0FzX-e7&l#>YAJgJ#J+nNP2nnO9u5>E#`3t84;EBKni<3NX2eqjQD0uQ_Am5 zpB6YIf8YuliloHD9@$dpVbbaMUrgTyQ>*D+e?_;D0LQ5};Nqg{7-=zj#cP0M-i8dSJE=;YL^9~Ci5Z|+F50BItH{OzFs51a!dQ5&u~*iI;S)psv#{XYw167fj|WTPwV>CEH3UGyo^jJdbE5GVj7H=c_68y zK+q*WQb#dpOW)430^T1+>0Uf1#d=y9qd#wJ^-nOTP=$9*rz=I9pm0!?582)6saey4}!!Sr{FccSx&B-5DAjUD4#AJ zG+eI|bLsNc+^a7$k9Qf8uZKu;9v7D)YH8?Yjgohz_=*Z)KcOD@Ey9KLg$4Nl>HQcI zWP*3pJHZ-1I+)P!nCFt?GSQt9#trG~JrYBQ(q$kBQRo5(KWoaY|AeWLU3*{lE_3r0 zUsBi+ofVIW5ru}FOJ*{o^S;j7uP3)7rdh5YK&#YUoeLkzLQKE={BMxf3xT_iQq)R% z8rWjhBn`7#lxd~JE$4vM$9Y?LtZf7pS*=lPD(OlOrT<)VyUM^QFg0}#=`+4xhV4S7 z6H-`NJ}rOnm`%9{X$TlKdMp?07+B2UCP^scM$Bh(t+$9GCLIPiC$UBDX^P6m90~i5 zd&Es)CB8rTQEZRJjM##+Ik`e{-NazTDz<`B>;R9*bvYvRl5svPeQQyWfV}wmIyYO% zp{?-au$IZU>p%8XPanM{Kx^5hD7p1p@OYy ziza0W<%mMBr~3NiweN`LAO_B^de=d1Epp;JH^xirw*mKzaNmzW6KU|nN2e}lg~gLz z+Ce;oo|R{U)q=DDhIGT?4mg{e0fpdL{sg!|<{EF8SE13XJuwLPF@|pAIpwURfI#^Tg0N(p*+&T*kmTK>OCjMICBQ55hk`~CF zlW9jvy4`im9Lru`GfA4XU(klvpLhmVvQIr`Wy^go13lldh@Pex z;tVCx&>Ylg`YY@C1x~*tY2Ew(15)$OoJ6mqOwN(uMc=!4Pg3-R5iIylvLIGPfGv4R?pbL5N>Tfp&~z!7=iGSeB#(Da4lGvj=iTkFNi|hY=(A^xrWjdAqoc zEkIedg&SuV?q+SWC|NT<$_s1aucxBit0BoJTs#@*Is+r0PQJ*L`9_Qq?9V&}>b&*O z|9M(czOlgMjwNb6s!1VAilT!+*`U*D(N!S$MrsHAe5!b|$@zsFqI3U&y3Zi62kO$* zpH4tbX`z(imK5yU_!D;?>t&nsDPp<1%rHsAk2&krvJQ?W&n+kSx77Mh*IM)*>`Lzpef`GEi`^rsjJHttll~A+g?k@1{-+k>W zq$=_!`B@{SVW&>Utvi*EF+|8msMgc#EDQfy|Ez{76YrDNCxX4~^X`iGT zp_0XwvC+WkRT-od%KcuTd#^@xf*sT~#9lT%N{O;`H4|<1l$A#YiXf@&afNWBnd$4X zp-|+jMCZ2Yu?{AWp1LQT zYuP+F62I*pVH4$JuifyoUSMwtEK3J*?|qib!LbyYqSM-nMuH7t_*h^U`7vh*kxX!l!OcU(x_T2rZEC~lj0x#Pai6A zYa8#*^I!jxcQ_c9d-9>YDU1Bcue|N@jd;uTukigp$b(^p&J`p7rMKtZf7y51E0b3) z6N*CETX95Vq-}f=5K)3x@HcaE?FnJ@LKZ`kPXFV0*-M6y2y#h0dVv+1c#Zig7KW z-S}!Q8i`eGpDyHsjvGb+{b*+tO2e&MAB|T=j^t`SCgnH38bE34V%5g@GG=T~z%$s} zG~HlV&>SzG9^D=sPR7TjTowKJpM2=bxD^BI?IOyz{0?uT&z=NcPa53K({6BXtYLId zsB2{>ZrF=EqM%=|`Ay}tIbc?wvaRIESU$c7<4jzKPS=L*=AW*xQTJ~3ENgTnV9Y2r znj#V!H)=Ra<(o1Ej<@$G{Wjh7)^uOa8}~+o%tLNix=-~t@k+53Ox_da?>!P+39Mms)XfLh#>{(Iwd@C(iq)0s6hhUHBQZJ;KXb;gfDV?sA2^J$=y6^?jts|He({hwIBY z0DH0dbgq4`wrYvpXnr!V!u*Em{H6;-M>daha&%Ojdp(;bZEF`s73* znAYD?@q5!j@}xKM#U}!1)7(gA|CrZy&j!2bZ2048cevy0=_4m6kAW<_hnvSIR!rY? zkxf54F_J0fCibfEm}$npF!`-w*3}6=@H`dgA-L?u*i3k$8n>KAT_545q-Ikmb~LFH zXL7@?+rRd&g5s!4FYwp>yc+W!!nf>F+2+^1Vs0cek=yDG{wuXSn%fjU2;YBDhuhVj zAW~bS7k_Gc;t_9n+}uC%(ontT&8?_iSugoyZt)UIP`!)6dftQMMHk9;vmULRT0+5BCFW*i4gp=qooehUZVw>pQ^L%O(s z%&6jn-QZh+S8Sd&pa1tCD&DVDtgJ&%sol&{n~cu7^DmB|(33Lf<{C$#wC0}KeQ(~JnEJP|v^ z;(6C9hP8sOcxUUnH}L|eVMkXI^_He$>=x&j^sXhH$53m9rjuvp>u>!Ymueyu$m`LJ zv1-J=^ZqV7?AodkN>M`SL5Zq413oFlAIG(wuqGYduy<*v zubFiQov{)=b;+~%fYu~`bQ&A1a*qX%r5n!6j&(k0IG=BQ$ST>5436+%Xo{sd{g!Da z8v-{e*#T%H9A5I>ZK|uMmbU9dL0Hl=h3!Ej(6-xp;tWuUFff>T(zBA&Ca9goOVFa} zh87Z2$MUs5Xj>K&xSgV5S$lvk)v!k^+*rayW@k^)(yCz`{pnxs3G%MTcB?_wq6tN) z9{lGCaVtL2vLnvnTKVag6iFID)&t`yk0lTS79_ zgCAb0#y}=7QQBafHqioL>x9KJ$(XNLB31~n+78b%XZ04tCtlQ*jp&9oAEi+btkN-K z8+k`GahE{9PCY6n(Yy{QV>tYep~VCG-!BA!0tKwZS~!H|fcvj2HI0 zM06`EhVia!bNWc{NBq(Tf4kZqH42G?=MYe8JlgEO=M6hk0aFt}dxFkrfSq*0$V8m$ z5-fbfK_+8AHq^s2C;|YBo3z}`;WvyuY4y_3Ztp_p%n0lF)egIh(*sg}iXzmE0b+ z=vD2K&Gv#AgQcKX>txx4$}mZ_P+SI*W7wQywcTCg?kru}(^KjRdXFU2e%_Wle6 zM&3Bqu1sG-#A*aitQr6d+bSha(l}$hC*QOzlkS3Ttb&cuj}y*QvrL0zhi@Ps!R}4$ zK|7(2Wmf`s9Qe|^;EZA^vw@qw5l4#gBg?87gi)gZ#3t3)N5}jOlrI^G_K6yjiYm_yDjcc^f#YZVe^(d68E`t{;rRosZF*XsBQ~h zKQh<7(AH0!b%(DXZGLaOc2oN=)U!J1Fd9j14o1Vny0R8_=k~ZN)CTLS)hpFA-Y);Y zHxC8T;j7WLo832}L&=M_IUj5fuGOE|H5N?jA2!#LHtyd!yg(p{^>H%+`|e9z>5sr&LVGf~t}Y74*+%q5G)sdS^4-=K8x?qBui z_o<@ln^FC^RW&hYexY8y;G17ooZ;fg&RK&0;~pj8+LG%I*(3fwRb6uDUss)>LheSP zGyb5yUC>oOyk5A}*LNaHmZtk|jDYWV#=onpcET@i57RP|*6oU(PFmLs0sR1vsvvQ1 zs7nvKx;Qe#Hw#8~cywF_BYyfXcYl4_>{puN*7%rtNLPnKX8A(UnQ*r6Ml_CwNGtPl zCs1ZrXRg2q!pq@%zwy1d{C!J<_WgZBW0<4ASv~lfp|?JMF>AI`a0|-MsLh{DzR*z* z-a6M`?KB_!3(vEj{N!Fge8!Bt=k+~gjyk*hDB>Uc#wS1fBV&GUU;k%m2YNGzJ03OsknVV(zVTp(X1@*H64vm;Ljefyx?B&|JT2% zRJMKGS$!nf{Kfm-P;K53JZd`i;=lN|?yShW?+rSYCqK5=e>=IXFMaZ%>_g_f+U-?4 z|FHivWmw*9XGgfV()rl^{j0}=%kI~+<>Nu1dbTDieARU37N<@5n}@d+SC5;{;FI6s zv#a4Hwf9hVNvYD3>JR&tKHI-?&>!y)r;BH|74gImaWJe{yYDc)_h{se<(P5>0|wGo8;1t z`}-c9>l}XY2jL-O@%CT3kSz-t+@IN5`O;s~?vkkfZ)8zDXcgwww0V^cR#Zxk@;-d) zqhI``4_oS8uP+#E+QH`R6hmavr&~H;9?a(6V}H1>CQ=WwSaMv#o2}G z<*|EAxc}brF+QWH7=r%4K=hP&h0iQ(SFe5Z)}Ba>{7LX_4$r8S>+ERVA%+!Ok+NTkUrmyw!O2@j zj~vS#33mpYF~{ll7cRRO{T9L+cWQyVqI)}3?flm(0Z%4eI{e_ixqocVf2{nThU4)L znGyT$b77Q5C;OUN3i`PsAW)~}GcTd zf9k^tf0YY3k=)}J_`TOFG)>MJb$Y?#H&Uj#VvavBs~2k-ifQ^E8Z#V#o=_XUr7o#> zcLc4zz_Ogu5f=LHlTVcT$w55o0-4k9h}JE@2Ze<#Mz^K|SfVGBhq%yogVjA`wcat# z;-TfxRV5&b& zkr}d;DbL$eN?F4Yv?G}n-fU)u>6-2<_AUg@X`K(3g4}C*GyqmP$reC$RBdL?6E({h#!E@THosWVvk?N8 zM3u|1P(~@tx_n zxgB~B@c*BzKZ0E0zqF$D@AL`te2{*tPnes{TkGq%yCA;R1LH7EwQq{|IvzT z*dw2;*kOa@gX!w?zm|ckS3D))6wF(gz;UW#ee#eF3+O|m{LRpHV83TcJNIBiww2$| z2sV)ZXloY97!q<&GYOgRd&!0Hbnu9`tFHM8v9@c;MP#I^={K-wDB>7u(bnXfc8Ltb zkPWHCQI*FZ{;*|bA-u&UkOjvLvV`?70pWk=E9H0Nzw@8|^MCn$H-7=*sP^-|8l77L zJ1Au!=k396Z^pmtR98{+0KYSMIYR&JS7}959%+<(Wddl<_zA!ZEb_Z(N zqC4&lHNToudvdj#VO`B`s!zBo_~N-=`oaIE*KUr_oic}-L(k}gL(xP2iQMFp+o$Fa z6-HMOA2*vTYUEIm58|K`Xr&s3rV~y7Kis{4bR5@p=UG)KLT$zI0L2!z+)?PNheE5^ zq$skked zgTA*G9M3N~C18qd5}#%_?tiGN&K~Fe#1(MhveYg`m9*I1NZo-3*B zWaC&ZzI`DZ+H&zOQU%tzl|*&tVr+$_8{#WolwT-H3w_b{#kd7#wk+VFtcb3<(SEZ%2D` zABOHPhU49$yMJMSTs{;yhkbV@s$>rpTi0^4e7QI|8mOqAJMlu!;V%o(itk(w{_=)B zldS>(8^hVzLnUit)DSMZ-x8_S^v^=et}q-}_e&k8Zi&(>A{e)veNH>NBj4jU@nJa{ zB&ms!PUI0e*73tqwXv$+pVx3_@cKu#oEg`+A~Nf+tPYE8A@a_~Wf54O)n>(#O+f8H zGMziX{oNqhaw;Q1Q7Ms&K&cyl@E2ExFNO~Vt+Onxl`lKvpAF1~DXTiM?rT9W2vNzR z@Tge1nqTc44ffw24h5f+(V{$F4Nw4QoaKD2cxN@ZTg+!uVxch}jNE3|Uz0oBdc%KV z*7{({TZqeFC@$n9=Yqzxbx(G^DC$oY#dL;~xD`)XGy9y`eXw;tzPGx#FLsSdd+O_Q zemolQ%#`A8;Jm1=oyw|&&5Zv}GQAa+@~7ezsdC|*n+=L8$v3k$?%wBCu4a}P z311Ntk9C~v_kuGEzd7WLsB4XdXUi9ZxMdyLTl$DdMxFXq--=|(s_vN|o@Z=Sim>~! zQ^F6jj*O;XTwwVp5_1#L_>-~o-W!4IOtk1UI?~N*!GpQC71V|5MvG7U%s5(ks8F#* zlf|7)7d*tf6lxr2CQlIzjlu7Y)FlTf?p)Q;afwE1?H7A|(5P$|Rt_L>gq}4tR-C0) zDyhV?+=_;8(#-NA3^W5JY~bB0YmR-Zz_kMCCGBP}{G%VPNoziJto`LIjI#(eU$gfg z+7+f*Ik&_;xiKmR%C;1qZy%{oiaZOV)@BUceQW5c*BaRlHz^IdjaY#QwFaFq3(RN+ z2yOz|o{O`S`-{7Gw1a4}E5pP2Y`oZx+Qp=@d5m_XO-o86jwR8t;EaFpk6H1}q1h_i zo}XEd1~Dy|n@=}gGOP_)2>whU{yS-?ddp1hRljV8L-zEJy2u7?ne9bQ&5VWt%#nsa zy(wd(WDVv0*hyrw5uin>6{nOB7F`R$?O8g@uo9=OWVLLI##e9rkW));HJIESW7B9# zR*45BIMHudQ!Fc5tZh3rwjiX<{;*=Nva&=nBQn1Y+lJ??=9r#E--{JXOkkh(_<=aJ z!^oW;w&k=#7_p4v?f(u3ab$!E+X6(>cITp|oy{%ND8MKd^&hF;;^_?E>PV1HN{o^kU$Cp{grRfexAt%K{`m3;ZoH2k;n}&ZMP*teOSl5cw7G!It`b$sVwV4spcj zv(DiNOjEC1JC?y@&DMzxW=eCJg~AstphrW2Uc}SpoI2uOKXtlhMMtmwN+Rr zJgde6gl`6c@<*)5&(gsqUy=^;L>7e(hcH)gx*RTP2NtWzgE-j13Gh6D(bysSsD-goi1fbXjlM zBzj;6OOshYtJ(HmOAG{Y*AZZxDR`%(lHMwNVu+d@8_BeN{UaZ&QEKeOi9K{IG*~v$ z(IIFCZ_V*pY)#GDM`U+IHdW?d3+98m|7?*)v1DWsJ2FY|j0l3Dyb#E}m-b05Sj+O) zWt^S4eK*b=BXWj=5xEE)l5ybUeCXGBO7yKjj zf!`{w$YNqmoA=5|=GgwdVj0WK^elwO6a6vkU&@FxL+Y+iP&k2=6d!rBZ^DX&lhq1C zIz|NE8A7DyUOo%McsaBu9&_9xOAJ>6WF~NiEU@n{$QcokEYgt!v6ZCcNU0Qa8-;!* zFq|MbBM~7i&X|Gcl) zM~(dZ#YUrC?-y<@e??r4oU@gEPIF#ncUJdC;%E}z>E0LKxwv|x690TBx-Yy72?$HC zhFhHJ{gUfE=P&MlHF&U#M)aRK7qaL&JX627vCm2F3qREO8z~-_`)+@3{=Ii6i_Jfh z|8!w|^U!R4^U(DBf<^g3=kSOa-<-LJ(Zog$RSjmQ*6_xra}^P`l|2>DMJvq%Nir(c znc4V@6UD7y`anFjmE3+~-=7?jYopytFv8Q%yknuK)Cc(J3j*ZXfNi6RTWf-q)#Ze@GFEFmhA8BVJ>!LDz zv|JLbCyrJ>RLFCITHroUY7 z{?gdsn+)FmXW#ePd4$5$B8(KE+3a-Uv>#m@?Ag)i=S?+!n#93s&AmtEPG)vUG z!sS0P{oX2|J89El|*K?C$<-usGJ0hl^jO%xpgnO>}pw71eco)^P zgVWvE9bb#@iz`0A^FXn?Pywy}k&(~*_B()fDi=mS=b8j{zOs0+4xU$dL|UzIxtzw{e}ugT{RJ`oMN7e>G451tpN#p%KO$cuhjEVDCf z&qq%mc#??4+ki@!|F=eC&qp6Gf$HuV-g`B^HhF&d{@quD?w^A0y)NUW&xezbB?*haed;OdPvnGG*U>wyihF_b1 zeKKjoZa~fRf+*LIJtqd2t_?mrH~|iI{6DN6od#n98P@3SGw-Z-x7ad44JS??EFIli zI)88iT>8YPzW5JzIc;(JAlvL|%S-QF*ux*$#CbUI(v5Pk=b%pILAO4!cJwhI!-w1w zV9kebKNhyDLo+~KVb#4;?g@DG^T5mpN3*>bXI^*1AibZ0>Z-(wme|sW64%1%x5x$@;){JB|=(-TmlTA0TKcy0~!ueWab4{&Ok7DC;2DYao3mz?pTEHQdbW z1M$7_(l;;dMDyz%8GdbcYvOK4b-`b+W`oHEhuxR#Tw7m0KB;^D*_L>tc)Nnf&ig+v zUdvz0IIk?8y*6@T208u)y9sZ&ZkOYbPJrr-U2^6lhfsLU+0Rdc#vkbQ%)xu+@#g>? zpU7t7^jPbqZv?0M)4Vg-UeLHZAR0|mo$CE`XB>w2N3X|mTWCNIhs7_uKKu zhVu^>r*CB()5rV5pWXffXKNo=`O$c({CaT+bXRm>J(%ExUOb=^ z1`S?*3D`9KoC_b7Raae6V}ZkpX;|s#vFo4w!LyuoZZn1GQ0Y^wkO??6MeyWs_71=OlO)RW!Kwp@fc>A4>=XsZ;c%f&)|n_=upL zdZ2YroB%a1)Ne5;@fR1)#Uai1Wj_P|S!HOAffzONaf*YL`rA8Z5w$lBr)lo50{T1~>~6_R=>$ z_thf{u~?m1ozUlvle2H#uO)<1u(lk)<0CDW31(ZOX6YR_t265(4#r%Ss0GL6L~bX0 zX<9D;Jlbs!erf)p8HB8JDl(n`J7C% z#*M5y{#dmJZrv7R{@@L5`UnJd6a9qYnk-|(0aV5F=i^D<;%d<1lsEZ zeV*7fufJ5PxgnY8N37Msx0fO}S#IRZTY>Qcn1f#q`W{zA;yhkdsed%_)fc}k)bEVG zcyyt(kY|%?hbpGreVhBL48HDPjgLu}rMED6viNg>0;**=`QuT}lJ0IbG8jK9ocN;b zdx1sWGx3Axs~bv`B+&ZSgBq}Ohl;A}e<)sCFb<2++C_1`+#KwdD^`77Vg%bNwcWaX z{~NcS(gD`)k+N%yXaJi~4_M{gsc=;-HG&-)x&!^rkt)$uWWAE!CXqpRo=W{5AN+*vfJuKmcJU?P=~WF+_mFdW-?w4v*M6<=n8g7c zp{3YUt5&RL-O?LD9@U7q5gz5g>3tyslU4P=AT=Cgc zmjv??-4i;a^4$KR0>6*_SM?99;A{U-Qr4Rp~xw;tTQ4Py6+Z!6nxn zHV+){6kUI>2t>IXY{+;nmQ!|UOsaFo4i_C_Wwr9R;t{ZvtnYv^6?tDJ4g%4(-vD&vE=P5lPN0INggFQu~Y_;XP<3_C! zU5SDmy&qg)dwVox&$4TwZi@G+L-a8bh}UBLzp}bP_GcjU8a>371%8!)+EZbjb^ z6RjQTDg4sPX3%gqs%aLm!YNY=NBdNMHjrtsV{ub~?T*`-Z2HykOfq?>$f8w2{oizt(|u9hZwBCO;}?UV8i*+whyy`#Sndx-@!S)mD$*D6 z78B{2UTzN9`F+L3B~#vY;vK1Pf^Q7jblRD)*2)DLRt7`sZV*X7?`u1$c&^wU+V2vv z<@0@-o3wcEDQk4bW8f4sg1009rSRbRK#*IhFD}I-Y7Q*I_bPr@O5(cC_@VdNq;p7e z7Z^mSBb=4JLb$GxT>ryIQelQG2S%OjLq*_N$@yiHd=nji!@j2f z>>;swKny)h6no2D@i|>+ZDc0Q;L*te*tTLnEK3sXDidq6?T2TIS7OVZ8dOo&aqF)| zx!);>4jK89y7u&Z1LR7lR#TwH7Qg@=K>Irzz0*N(8<=W%w!-rAYtwzDz+a03*9fOXKHRz8V|=JiFdB`P zEO(qwlNSRP@Y<1-k3G47{Ah}ng|$e2bHKgyP;sRq)RW<7K6$St+^VsvaW_t$$}BgV z8&9oai_l+CJH*Wg(E;TU7x=*ohKz^nn8ju${e(3C`P=egwt zBDc!1%0!k65rfrQ9yfpinV^P7$IHviqSf-7zy6b+6{?K{i=w&aD{~C^2`LVs+hB>2xKu2 ztkDoOX`rQoVc_A-1$T;7=~2jJoC#^nMLBxm{@?wfZ4IqzETCssG7uQ}!S13wV|KA+ zCKd3Au{$D;B0^!o1eAP00bDZmm43i0FjnCr&|}IrCa)VYq|*L$I7cDr3C2o!f9JKC zcYsv0+XQHj9B^#5G7OS877RF^J``Ge7gXS+{eIKhoA-x|gd|9vTL<#1s3~da8a&Ih zYeAp417NHNSA`giMkqZyE~YX-`!UEEaTbvIq#X{tK6;#JY!f()K@8YQZ)6P8-XEzI z5>{`*kSD{v;%eq3ml{LBi13_*FTx^NHS_&rRG^VX`o4f!%3!PYSj65h1ji^Qkr5j! z_GDp@`#dLz3lcqkefi&>(W&tPvF0>@&yozGuNfGz3fZt{g)3G9O1zE=30R`a7>$~- zzTttLAuT+*e-t$>JqtKI26>E(nrX1o#uhX{N_NnI+j&ruDgs{N?t8xS57JFwJFi;I z7#ye?5aWn|fID;uR(*d$}u{oD==p_iSN2ORGp$*Cz~77B`b z5nv-0<7nYFTAcWU)E3LSL*aSN1|KJCDBA!uOwG0rdox`oS2&l421X=6sjX_(qS|Zk zwPl4JR%<>$a{_3{&J-S>7|gaoX7k_gdVanh>m!=BO6HMrvUh!9WM+ z{oYVu)e&_qa9;nSmmgZJwIJ0pKJd>NwHuI`vdPCl6C*^r480H1Aw|%LGEUacCXUna zZWDp4|2`<2to?ms1#rG*-U5zsqF_8F>DEEH!XsF><-lBc=qDB z=&uh~gAEpiYqntL5!A#iAjAw21c)I?bg&LbFdi9wM{H!Z0u<<8rq&u8H!?Oq(p|=p zoNwSOJ1Z08B%L3KUQ6^KCgY`TOxt=Wq`CoISQDv2`J_Q$2_zSp@z`4@=M<4fg}eT? zZ={TxGO~eiutiU>4#MerER`rdx0-h}1%{53-IX73P7`6;WdqOf*~Q-oE`=X-s*Bj6 z_0NfgV83%mGbkN$#;yrGw92!^-FasQs@u-0@NZL_F}cF(%|20O7Y(z-f#6IK?iAAA zhbyYe=Ys~@7Mz86s>8-4rmQVOo};iX(Y&yNndM!bBe*fdYW3Bzq# z=wz1vb|&GaFcWtOhl5=oua;SsEs634jj-=yQQ&GfdxJT!-jQOLs2q^#yx1GH9?X~K zJNw+=^pJB$9*)9QW3r$aU6_{RYvW;ZA_&gL1dEI_b2#ckY&9sMQP~Q{t=j`lHn9P* z5T|9E6w3+WLY(ZCjGv2}!9vqBADP`z8np1_34*$}*gi03iVZS&jg52s>`qXhaIA;N zIzzMUz~1SkuQkbJ4g}lCSBMY&v3G~rUFGgi?9y-N-^a@8*d6>TZ-(^_Uqwxwc7PbW zfk+ub#F7#FoYZaEo*`nq3{Vz~nQcM*;aa(JvPf_!m?c<6MIH+3&-(G<6HEP%s;Q1_ z$3KDxn!Ic1ym$fhG3#x?7smc$S2*xsF57jx0r2$pv9C2B$Z8QV#c)?{W2_lKR9xz8;J6AGgfv-LrqNbnUhs*;4m`A$F|@O6$ab#F z`r3i?f_R2tzxv=Ty#@_qk3RL<0;dq zShr=lRCbuc)S0;b6D165=B$BMH-^|7QAA;rUGlC4AEA2ViC_HTpMU6-&4Ihc2|LT$ z;P#oJIc~It1G$x*92Y;cK;bdKe zJyG$+%Pkw!W2})G|Ktm-ot_??J{rFeS{}Iw1`49IlUtc#NRzW1TBP~LH8;b@NBIN@ zxGcIKE%l{Q@_c#hxj`=nSMB-N4nw1A%$r6<+I5ATGL-=brglVslPoX09$`fzHp`=M z6~L5KeYMxW+I)H8Xw1`7bh+UdYyo1)&oc4=>Pzi0RF&= ze!|bCb}K!;GNSQQ{aIUNk17#@Wxva@DYRvK>V`WyRJdNBKXT1bFTGu#JOp}LBs>Ky zOhW1gX}}YU3BmAzAdT8nLNS+XB=btP$!`UN$6X{MeS;554_)6!zAO!bXdk2g5#UJm5BlC z(i=kQh;pStxw19$w7qjbc=_JT=y|8`JnBkzUF z{>b-%m;YZVXsDTt-d(?PQWf%$2PW&()sYm~EOkCGOpBOI^(ZyPgHace!|P=??53 zFTW7jhiB>{Uz1oqp0Bz?iw#2`JfIp5XIt^*j!^C8=PFK#^C#|%R`d% z6>Y!uUTZd^olkm@edl`X&fYiIcil*z_c4J}K(W4GVGHs=tC4Sn<<_vD9{@@i{es~Q z9~ezmvW^5CY_x*lahVNYl(~&eo~^cv&Rv+kiz3hpHz*>bZfyNAjC){K#p(<;TXHFJM7p@rY$jb?x(K*;a+2?WgQn_ z3pzvtt#)QKOKD|T(V<$y3w~oJwaA4rChy2o$1-O2I7;l@3=`HXX7@>u0FO9k+@z9~ zT3~3V*Dp$TBYkFkk(#9wdqig0sZU_*F~xy;#N=al$~sjDVl?0QgO8&jH2XAP2nsqF zI{T~a)b{7IW^>s0eOzWdh%#|lD+Te4?L8ZT0HM8Syaids2kUB^QYiO9Zbf+*RE%Iz#{p(viD+`;s zLoPW(r?qq8wU7TrE*}VV)u{8D&Y*ROEEKst(;j!*%wWXSvDrL0==w8YiE>dGb-;j2 zMIQ2OZ__0NAjo_N1Sv7xMr622)JTkq-!D@bWrc`JinQV|XDTx*!8b3ztEPbj2OJ{p z8|7#AW(#H=vfx`pJreR}Fq7(3yeKAwN(3gbm(vOcUDm>Oi~_a{fz0z>#>Im^ zNzYngP^OXHmeay&W|xAte{wOd1bmT%-U0@KMv=;9ssrckSuhc@Z|u11!^jsrNJW#g zQVV3WO0CM8Mqk|B!^3M%l@SD69B(UW2cpy|rrl_`GsIc2YeiJcsB=fQWR45YJZQ)h zq$<7D5Q)P9pid@u+fEpXOt|eC5^jjHuS6b<d+ z+VyrA5^zK~y>YD-p>24|JSmWCKI9@Zv71hQyiYspsp!kxfp9*f!3Gs=3NNebd^f2z zmr?2{=IA|n)ACF};tkg~V#(@DiseH%vB^2+iAepA%8pd{Xj;R`dd&dSgd*t`t#t{( zB$m7dG1Pie2#;7T6m%%*PJ0HY-ZaX}f^UIRngVpS_0>Ol8=8X3nX73sfPzT_w0?q! zI!$3(Xb*X`hVL{h>8)~sqBFtln+cZx5`NI4&n1imZyL7bK|lRxEcU)LjQ9L=Q=cWZ zU8;s&Jj6~{>S=8VC4yVo@)`=s^I#TUPfzg!0NCXa>3X)9+Gt9sqFC@?z%g&cMmGU( zGAcnld*vJN`c-bztzjT5O$$oX6jW^TS%Xz50fX$q?Z}&4FDkk*(q=kYZZy|9Z2!CvNeOfW-%6#2*5MqeINABTGU$p`+)S*8kw_2f~@c0I9sTi^&ggCV#08JXMJCkSHe5r3|AqLf_zhbOj z{~!OHR%i&8ItL0=O}w)Si*%f0#bj8slAZc~AHok#=xrAzDiMjDZL&c*woyZFW7-8< zJls3(@N#-YYggT`x=7ejyZVVL#xV)RAIVsKI}D5b<|c1>MM?oB2} zL((Fbf)lhp)q@Y*uV%OX>3)#-)K0C95OGqrtgwRZH*LfVieT*Pk9-ND2JtH__e@CK zGfM`-9A!x84nqi8Jy|Yi&&c$Y>FQAgfF{Jlvx!z<*oJq90x)#l$*SdbsT!&lHZHj$ zm3AD)Wq2A>zX$=)VGKY-&CCkhMrE?Jj&8KEqpLbmM(sszfabWV7L zH1*@uR{9d|WrLU-SL0*z=%{-~kic zQ23_ohA%}SEdZ#}!9pK<_Q1#2C)o!NZ1772=(Rx6*fXu+uhQ$k&btm4d?M3#_n!Gg zxE(`2Q zTP#gl#J^3+WE%B}iz|#$x)SkI+kp5c(Ts^3(d4Y&cqHo$CZ940d zWLbQGX1q^>TpelL8-M|cD={=mHm`Pe>NvqzOxX4F2iub%HA^RFZG>hR@^L-eLg%CxJg}shFsT79+YleS#mfokE0bmt zLfMI4ASzK^BFHd(EtiG*HC~7xBOtSTvZnXbvT0k-Q8k;th}I%DF*JxO74T3b%IQ4>j6*7yL-nLwQifh@pC$0m*}YTx7{bTUOS?%|^; z(GWV=kFX`s;EU0Xe>n;ND-tZCJ;)np`D!H2>yWRTJaitZBRi0D5PP3h(y_kwgxfx$ zk&aeHJkX-6r30h_lm_8T?22wrQi!M(#ztgl*B%bK5q&|o3Dj`K8fW@x`w*rptF=nD~HID!pyH!n4deQ~) z4av8^4m1V!1ryrwie;P@#_^Bq^|y&`xn#m9h7L-wM&2E}7wiaey?fyVWcL0~tu{Al z32KYG;vY72aGmO*L~NwNwh}OAn>|ciF0;JX#}brQ{Wx@i2`+3cb9S0?;zN%$dQ(#og?$hl3g5K|X<`{GsHMV`z=Cr^IDIT;e+ib5I)KB)x z1B)?$DcMi&7*E{6RH&=aAP}^?An>x%;Z2p|HR)brn^{MP0> zdbMvi>pR4OKQV#fdkG%J+crU;Ft0bbnFrxN#=6k$Y4rAd_mHO~)J7=02_5|luv0&_ z!!%iqw53%1-8X;W{_Ot?o2tJrzHI&PwKMzs3JKYl%?53DivOS5-~Iii{AZ9NnV-LB zL-u|CxBm849d!oO>Gff;w6W>(j9mq|XxLrbaFe$~in>K+>Zr9ANunI0r(HRxR?OL< zF92k%T+KSNo@cKS1?Pt4r$eXrQhVB+dQCnVOg|Zv&js;RLxyQJxG$KB4+U`)N0Wzw z>5dEmqok2EFR{Otk6{IW)6$>XQl=L8<WGzorF>Re!2Mhk!s4eXu+8kv^(%%Q@zx!r-aC9A;bWa!gV`H$6+N zfLAE*j^>3Vk5K?hRpWb3Vfm0=(5%_%q0p;-#5)v>W67nj#d%U9r`pgJwLOKW7KwhA$b%B1;=p+4PR2Z$$Xgh zc~&^q9T(X^OAK3?E5`qe0%JnYVi;ZEArZY0UXcn*ZJ;|pYD9))IQh2WH6-VCup(^C zB=35oe>;ePNk^M%{1^JZrUNGVp~14Omp3wC4p@rmY0VMtdJbK*2)|b>Qkjtl*Z!cE z5W%wVCqlfVdN!%B&r!KPQx?RB^}LS>iZe#AGD~)r!edc-GP@54T5RFQ zn_v*rMbuQ?5JgXSx_}+L;X`U)jZ2&Enf_q3r4DLI^I_kje{|0Y#Fagwl;LIlIBmif zAN(Lq~(l-35O(`*uz0SlH2q@&N=c^#fj9cN~;=V)ko2TJLt#~tz%a8 z9z6kIxF~ts*}};((z3-9Sj^h$##b`Z8}Gc4=H!VK!i$p74DlwT0@H@T6c98a^ZJ~n zOuXV)2saQ#*!HPBV{P6Gvr zgx*>JbV}^c;=le^sX3Pc6$@FwaP>2t<=Ja?d^b|$`y{98Xq9fv1m3?fQ=Kf}6{W<~ zQP7%92gAItWX}OChO72ap;nmHezJ%J&7);Rss>$}NUqePlyF<3fM6YxvA}DAtn#4oFt3!0sM`s1Eq`&P7D+el z>$_f0$xg4wkmeI)RgrAL2T^NTUXb%;cmLQ?Z1Th-muc}6_55%8$NhKhE^3cx;mprhLN->o~x#-;YuxO zaB8@rR7!@v+M@D=#d#ra()$*Cm+C`$QPTo3$s>P#3l%V8DeJ9^4#g~`SC9^V!%hrr z@B-_t-!&PiE1R}?ESXZJZj6>BMsZ*@%co2#@ZxpHkV*Eb``@M?WN1?ILAADO2R=A{AJPu2J7Nrzl0opK0y1pCX$87X@A=S}05D{w#qO@OqLOD7uEq z`0}fzJ{U@m(9^nlU7G&HD+;yO9%KVD`1kFL2T>D5{p=zXkO*H^X|$z<6mn^xi8sE- zsC(}7`lJ4vFH^Mh_8(Zie8(d!2S9f3;-jI9{q}`E;xkYc2@sJht&CwB`jiegj4yqq zU(hmedp&*A9Byg*C|qhgqeri90@1c9jnp4?S-s1%wrf#FEkt+(xFxc-q0vKaGy>Lg zE5(^BsOZGIQG7(xj`F1Bw+f*eeWg~fqPCbS^(94zKe@PS4&gDR{q<*LbNJM7j))~%J;}x9 zjrg6qd)G&)9ws8V9j&A@K?N8_bXAk-O(@}`U-KZ}K_mH^uV`74^_r|@gr3Tzktw4& zaXHz)D2-JaI+qc;)y?o^^AJ-vA=tCtb3uJL7|BhvcGm~|?sKnCblMpq9NQ?%D9v5- znbQft@U_Q>K&R{oUl)(&#_@8_*DTR=540DS`eplM+6{zC=r|ob5N{6w#zRsYMbxvp zrB1WwECSIfHwpH6Eq4mCT&OEPtjm{MRz>vV%=T;ChDI6nyHR&ah^!m@i+7Z!H0I(H zRAK>J>@;_=tx9hS)Im$n5y}G;az(D=1?RYTPw*mf_{Mg!=M-0!qfG*1&p{A_^Wt|~ zKqic8{L2`@S~c5Zu!g@`vj%`6_5-NIpT@zgoZ>H>UXT$WkKr+AEgm|64?A|kC){aR z<1Ay$)*386~|DoqZPpH(Ak7b2PES>sCkG zvAb#tC`g-Nchug-r0Z6Jk*iKUxbg8nXd^8&k4B9>a{vp_k1B%Y(Nzrm<(X%b&?_r8+pNTR`casjH}<%X`gD^#o~b zbDBH8rFLe4?yVJe+qCVbCr_ywxTvii0J z4$yD@ru9tTXC%J?;2`w6+itd><+Pqy-|H<8Zfam{_y>9=1kD}=YU;5FvaXtl}BU7Y?6!rh?@ambMm>r=qWMX(E&2d&X zlLi7)hp&3v^j@`1%xA7dCK79f4wR{x)H{&}?5uz~EL>@hn7En=LNZWu{*HP+!n^rg z+WP*dI|K76ykF z2Q&i?V45%;Tuv+$%mMyiS-{`4LbOew`Wji*_Px6UL4+!h0;(htwy_!nodD_9wv;5| zq;W+7Q;3u(pp`D`OBH?=jbt`SL}hJWRQz0>64t28`63c7v}LmL#=}3IQgiOXA&m=p z*|5Mt2tBFzW-bp`gHx8)Dje8?8E1$DKqQ>DS%_Ms(o$eI0}vF5&{xR9fYt1;@N6wC zV>GgQ2+K*RbxSn_O=8nirkEjY5A;O5=lG7Zqxq;#kdKR>cxE`t1`|_wChZBuXjl$G zEetP@!hn@VSt?Y_kSH{-kqaWpjg3V^wNju0AkY9JCI1m%?^PF4J5@vg5#&IJU~w8C z?k4+bw4m&F-}Nm!j478lkuD|h<@7)NZ{ehuM@*GKZg#?>UouoBr8;5i4 zDP+_NZD=sY2S8XVhI6yo>iS0MEP&2X%lCcjy@hmsLbuy9hmxe_TiL*9&=i1T;YNa& zUe%kU(937Q-~^7mNW~?D8aZy}k^?)E9|z9}-IyVot(eZ)G!oxt zGw&0ku_)5X&~|eS4^P>MIa}XS zQ#QA3;N=lVq(xqM&^ zI!l+x1tGmJdT+=RG;d$7vFh_Im>BoZr0Nsfo0#V$6Ex%q9wcHXZrO(CBp?OKFfw)h z!}YXaq)!&N%LI&pB>wkkG&NEZ>_Xf3vr`z~m3S(G$F%c3pQZ4)R>*peFU?A5fHu9g z$nyXXqd4eQOB%)NFMT3)V^oFVMCh4ND}bm+btv2OV9GEEA%XlgQ3Cb zs;;j)qr_5<{>?!}k@hNac~n15c{T@-^q$kSXjMo3My>G4AJt_KDpSx=6kO9)@Wg)o zGZ)-kDX>k8Igx?SJ%;jh9XgoL!o-xC7z~#vZUP!xQ?wn1LE~9APXfeRnIH@;6%Gd- z8c*!)8vqa9E_wUa+iuMO6=?F(Kv*+II0KTyf84_9q>LmTm$CgAvzEMPaLdx*|z3WefKZv)uu{XkRvK947PHnk+&f%@L# z!jlES;_bVxH=an%h)!eRQ6iWS-`}jGcL$&0B}_t_={dZ%T>-J;bO-BayG}c1 z$1F?;WzZ0mF2Hl%{N>0?iYm_rRblFEK%DMi@*}qMMA}@ zg!Kfrv%1N&MzG-=7V4I}y1Z7@!bO!%d@O06x~7EOTA04H7bTyF73?pzgh>T(g7?Y+ z2T!A~SBh?-_^rwHJn1ZpT12|) z<6fzgU92_L#2S+0KNfQrEG-9T_f9RGN>v9CtRk!@l+v4^NbFJgk>EZ5^AC}PhUIac&c~P_;nvtrv)J?3 z0X^=Q7pk`y`&GO17Mj5OaOIU)`}4pV%itt(hENn*LUQMw?#xa1X=M}Z`Y;rBV;?~eUbLimv7bOF0W7a zFqh}W^(4`#%ZcSe`vdpyyrmSe-RQ513igsgY3!MUj}aU}bHNA*K`;zHeisU|{rRy1 zkP>^kln&(4s0bklCjc4 zH7lly<uR> ztu!AiTyM1=V_n_@hA7FRNy(nR1M!Z+`Nl?I+>Jhl@yi1dH^&Ju-Cd`Vp@K7{ccX#)k1Lt>tz|-$20z-GMGqQDTfBql#eXl%U>p2EMGwmJ&{^st{ukC!;)Q>G33Chzula zC%!e@Hxb(`A0DCqu?+~ps8~c%9pC{JA>Z^mh`0{E*S+)@v}towBVK4xQ})!&qnWm` z#vW*~nP;Y@<3ZqLI1vYDIW-C1koe6hz(*cI*})N%G2KGhCo<#8v;8$2ra}U2=R<|8 zKV((fzTg`&r~kEEM)sKYymhNn)GrbLbO#%Dpo0x-R9-pSifI{FwAAl)MfgG-yoPMX znwb=#w)r}zdd$p>>wm!^6me?BOerC1 z{lC>Z#VM<;a3e%rigc5}JP$F|dN)H$ATrvP%?yTxsK1sM*CmKK7elD$&D>^-heY(dLV6-@%*BpX3>= zoe~*tUL=EqYYhFoT(M63@tM6aqUj>j%Be-9j4^6szi2b9!WC8 z+0vj@>V(?b!RsY-VoqyzQ4WR*1K-H3GvOIRm^u77JQI3fdDTLX4cJ+R`?`g$U?pBh z$KxO4rL+bi3-uZ6A5bcty*$!6u<>6OX2M23j3JI z0Km9_rBiMX1=YGMJnWS5Aobkj&&B}0?DAjfprg-9A@)4C46IML(@A}** ziZ(exyCJm_ccSS+M5M;rMmR@*MYu1U?mu%---T8brJxPXOJSLH^18|C@~zAyK07l( zcj&FAY&}_ASsRH~Wb!cQ58$A+Wj641xH+C*3N}N~5ip5tsE}~V>||0XUmj&v2v<$z zhFMw5%7IXQ>Ore!Z-lP4*a+9PeLyb0TF&;DN-@_=4VzNP6pDypMJLYkQgJ>3X9~Mf7Zo`3mkL&FP@c z5z-8ni0}i?L~DioLOUrV^|kqaR{K(fE=irsC=!~} zjNkl;x_%shUrTq!KG|45$j50wIHLx{lqMvF@v2BbXw-dSZV)%uWOSi&GYY*YYi769 z3L<6x$4OQwlZXuNUTzx69789QL?3JiAn0NG$%Bjx4I1fDt4)vCDC?P9UmowUX8R99 zqP18F_NugyVXf(6R1&w;W)*@Qabz)fpwB^>6CHh^g90+xY`o{cyu~?7Pa(J>;(nV0 z;jNfrYehYBG@Og@QWd3zE4oK|RY9IiI1|W-l~w|pAyA+pW_`~pz#20IVIW*IeAO<# z@U22>(S({E8)2+p^+jnQ5Bxw&LXS7z^Mkz;q~}THXcsP;}GbkR-ZR z)1s%jx324-epl_7+U)(AT9GcdhOz$E&xGXgkp=-6YA|HGA>0$gXzBn#$wcpoa5=u& zl$0nrlV>#R0^4}x>08o1wGn7qQ%cii>-Q;3cP34ue8G3juG(1RPaS;+og3&@)Ia^I zcogwcz2`DsGc?zBBYOO}a`*Q5tJwfa3<$)Pi|z0MRaOI@*3H)A`8$_V5!{G0J0PW3 zvi_0o;k74s`cLEfpUrxOkhU7J5WSmwUw`k5HXhv7%^vA$E-%x!2#97GL^p+8%r%P~ zv@k$*PpmWpxS)Rd_2^IaN2YiE#?>SD=BFMtz0bXl)A5YdqEboHMAugOv;I|M?7bHu zdxLrViRTVqNv=jSDyv-#qF}IiE||`(NTFRpYe?;`)eyX*3q*wa1)F2`PA%ONmI&RU zq}Om3x-oqdhS1B2bQkj&<^xrr_CjmL39NYYi`7GOIcXv-U~alal5I{8MZ`BHAJd=w z(Ji%)gtjqmoe9u?AbrSL92?9}W!pFtL>a@7ZqvKcQcDXQQzT|FQF$0RI2#s|rce`Z zvB<=cDZvqsN_c1YY7$yj6nQcrIXjF{O3_iIHyP30srVw{gqb(D-n?EsH}Pq)Ob9*U zeG%aaRD?d@Waa>u3)8R~#w1>~B0P^6zmiNDs~{yHyZ{RVmy7S5<<0AIUd+a z;thk^?C(cnSs$9EmTeI&x9~iGVe}NCmfud)Ju#R1o3E zDR#ESDNclb^sot0Ik^f{q8(YI4b8^48vUAN8Z}{8auAT3K9UZM00$mt7IoM2qpehb z6caWG1#$lv7}j#D_tkPC1ebt#OW~@1h_e_yc7%{!cXc9wB;9E^&NHoyM<(`KwXSHs zvTDNPmhm`Z5qdDG{5nVs_>ATNFoPi>?1^XJ#tCb%zM`Men{f=@83t`SxaSiyc6C?M zy^JZorH^~AG9M8d?qN+qcQu@vo#w>_6rtd(Ei&FF0=@5ovm+Dj1?ryF<-Xja4h5!Fr=JHE*~V$$?(2U^Qd(unmo6E$kvo3C8S^fF8M$ODa}u zaX^K87S;39grcQ!%4+**{;aid^@Rb7)GLx3y<(ww{f^Z$#dx3)>uzOqYu!dY+^8GZ zqcY_OctiQRf1svUIgv3@L9>e5D@cK^`=>Da3RZ4py%yv=*f95fnVZ}Xlm0&D913A&>3ACMhgIaGEifW#wu?xII1 zjz4>B$2is9qwVcptOxzUl^Dho57<+Yoz()XMi#OOodKMG`bV0-tw(ilZ-30dGE}I4 zq!CZ#lsFp?%x>u$2G$vR#1-|%pnh4AZ`WD2(c>B|G9(Y_a%gD%AL|dP38lwE&0rnc zk-EGnZu&k@fZb98JB+9vlTN_N*W~T)=K<<6=!uG!DgXzh7Oz#Xxr2f>bV>T(UzYlZ z+*PNL=Ki29YMFqPJ7bhfitHL&S%?lDC23m1FCoy0jY3z`p@nUs0T9gTec_QJCPS#= zJrb>8wRF#EpaUbTV$uP<9V~=x$dt@$deUODC>VeF>pyhr?bP$_=1lU(TVzEb7T*Cm z^iz6fHd6Ae^)Mfg;^_XDlLB~esJTUk8vN=a^?r9GjAt9yKk}X*xO?TpZ=Ei9Gqdqq zhxz@0)W-kMVI150SN?SJ|K7-xzmqkk8$7b7@QHJ9Z$LR)0ohCAD2|qosd!4-218g| zQ2f)gxOQ9B%|B8kFHBji4z)C8qE=8kJ0cbcvPDODmYUXZMj)~?#8+Uu^SqHxAUWCp zLEHNP$8leGp53h$Gf^mKrqzNw2$r61_CP}jl0ceqSX$q@e~sUO4R9z9CKE1><~jft zP~;?g`m@?vRc&fLJ?N1J7HEMC>yEeat^ow}GCpsaQdApXYI6ptVN6%(Go@2)bQ|AA z;wf2OHWx!aZ{odd2d%xdL1}a{m$>ELP-pjXT z4BvlfUU|1s%lF^?;6*vLch&EMxAIqsJg@$Fdl1{O6^cUJgry`2;)_kWwj-277nU)A zI>M*6PfBkruRHB?Um+?W6{Xpf6%12QfI)IukQpj2(>fsk3s>l~T(+_*GXWlv8wv=J zN%4pGrjH3s;{J#C{)e{Wc7z|Su}nD2H6<>~V{~C;$Kr|NQk7kRWXd^QFoq8uXL;s*0v3#+>QkkoE_f^fdxw3QHxdRLu?&XMwbx=;?7s2TkE5iK4TYSG z2UCwglT0+-ke#;BNHQ#r_3`HEWuc~OK( zMy+}!RE9I#Y2T@~1FgxE7Gf|mP<0HeF>pSF;>1|F!WaRS>SEj!uCc8#u4St%#u$%yZ_jc_JbTK{y!f&#PSwo_8q@TUJ8;BJ;q|QI zK&o%H@n54a+%*z4>5!b*S;?p!puEhCp9~x)$Pgwy=|5Gqzs1+7=(DdTVi#qdIJAcC z`XOdFwXe_|<4i(M5~Rabi@`42EUH4`v1dBzShDloW5$5KaG3m^s|iVBBU?Hs%a06Nljf{`AlzhuFBKdOqVr*Szxj9XcrMV7jd>G8 z`it%*_`US|=yZA`?L3=W%hq$j^PRdi*=c6Mq{T*HNL}VV+Ot+P88P!ao=rQd=k)e~ zD8z-Od%ph3ySH4d{IX?4@n{?Z9~2ME`qxL=NQWi81~?PTXk>sH#NSjLS@wst9-g%c z?m@6f{aFK+1rHihj$yZN`scn(3?pe zH5HJ8Pur}UP`+c<=bAx^zTn%79-~!Vxg!;=W1x`nJ(wq_moW^-xd?75t1g)V$(Mmx zWmz_skSy$dGu?-bV?A1^iXMoAUefmd zJ66oFx;<>OnTIlb!x^_D=FT6!uw)vm2O&F)zJeKmIW$E=7XUG*%4m+N8Zn>_w|wHg zpC~KOu8CB0*Z4W0hb<2wLc8Qj+%YoWwKXXWqz8Q6*gDdtivv4Dey|l{?VzcR?i$W-ls3Fx1(v}76i9RpSz?HDRg^LNO## zYg@FeA)AES5kd~F7%|CANt2l!T*&$mrJ-vz6zBto8p{xN_-evgs4C%-9Ol><=?}j| z0}Pg5ZbV`#9w||({FzIlaJ!fZxqPp4hX@R9WQA1Y59J`0f1>ke#wP%7GMM7VZOOTI zetn8~eJ_rN9v+z4wH2pTB8w4wXUeyrGRVIz-3Mih@kz%*P+7Cf**Sk3ZV^Fn7%dT+ z%gM;tVym4ZD^W>9wX^f{UoLYwz6*jl&B;ZI^Ydz6%IW!=?`ed-P`d;!C?FB-FDn6v z0Uv<6AgpMqz!cTaVA|2XXj_$4s7O z%Nw}nX8o+IAB$(NV8(9{r;S#JlWSq1)p2kZ&B|2UH`I@tLQf80NGcakp}=Mz79>?UeO(trs*C1@gl3z7ia=z$)+1BvBn{306RFO7-C< zJ-~})UtQ8K(4unByT5#ajR#qWmYtPu=xObAXTDuqD0SJ0%iiZ4)hFU}@e1(EM(|v( zeJQxQcP$_}>J}WbwGpeN+{VhWpi%v1|5$LquCYN# z;Ff>O`?)j28W4qmx_N2*ZO+?RF~*Y~;M8u4esxA4dZE*KO9M?frrTx7iIHYC8#yGv z1_XR(*?e&G;otJqB~bk-kowR4p?N|v|3J|RGC9pYO}(qX8g7=(RAGI28qzJ6g3S|V z=q{7iOD--L!)#nk{w$^*kA8GnSQIvW-*a_&KTS5|_S||mY3Tq6t7`3DyITMY8M37V z1js_NaB}|VWie$*-C?xQ3a8n=KBrZdb$R&j3#;kPh+kM@)2UB={wF6PmJOSXt9xPd z^|D#xb!~5Z`no~8jPO-hD;x$10%5;K=G}WRH2PdJ3r1c`l$|Hv&j;Pp8dVRLnqV+l zjlIZtKVNgg##aQ~C?s;fKwH*vzKm&-+?^-LUi&!zOKHY#3pzD!{O3QeJ1jUs@&mqf z-Dq$|=c;X7t=s4|p7H~(bv?jwq_00|6^BAAs|MdHk*Sx7vy4=M2MmkQq_tlSGXSF3 zHTEU%n31~zZ+M;=IoQHfSQRsAf+TytfDI}Am*u|axH}L0o@6dmO@TKOUiU`59D8!XgZOQ3`Q3hwd6u3%ZX@)35}vePHD z@CUq#3&7wJDr&5F%@#cX5lGbwzkIi1RSnIz0U|)UxGbV1W1i7Ba~;kKC1w0i^mU@M zBiLBQoIYkU2{LN17KY#!LCU>Wx#7n39JPU&(sjeJ`S9=|T!R+?c^ko!DzL9vvXq)T z|7u>CP`8Wu!oT7+KK#%IECwI}d&0Bq$Xd%rEj%Z%&N6V`Ft{ldw#JKF|kPd?DtF02V5DW4tZs2vA{-rA6d-y>Qu; zHZ(|(dnpl4$oFK)4Kg+HqM0~O{MPQphKN4RGB5xE5Ob&MxMdzGOy zf}r2E8SP~=Hlh?HoU-$QaDuz7Q)Ct~->Mor-+6Slhb$4sagg-Eqz9PmE@UEHIBH{s zU_43joV(mOBYrZH&d(;3ip|Nit;q({Lj+u4!zQ}3;v`2#37L@07#qN-%W`HZA$M8Y zR)|R%pA77Q)uz7B}N)Z#bxCX(KtW6?kVXwpfNek+#fDt zWYF8TSuP-}x5LZ)rRXnq)Z&>Vc(jpgc~7MJLl1d7|7`cYPyNi@^&_s4YJ&|I*vEG- zQ!qYn>9QG8*)CL>7f5if6_uJ$X3A#tri@cE8YcKFRyTa^i{!G9iZ$`J36s*E~iRP7}RH?1xS^Q0{CsBv;_Vj4BNV9Z_9?o{kSx zR`h5yPT35`*s6Z%Z~uf-vq%JrGhw!!H99kfzpN}Ti?HEFFiX~{B+1Y~6V%UKm;A45 zpK*<>&-uq=+vsz7T9Y$&NTz0wVLY-D+x?)bjHs3H4Ae$KUbe^+f^78&Z91GRV*$Y6 zxBo4;kJ*T6ZLs|;a%~+Nk!AEFt8&c^yS6VaLc;}ZY!ie_5YGsOCjQh@SY>-S87<+6 zW;OFu6T{*X6U2|oUd0^)#4lsbo%|dPs3IfiD;LnA5+WbZQSqv80H?Jr28W@@H&u_kYo2D5^e{^lNzf56ylvkMGO`{?WUFQ}wyXEx z8DfY6OcPMoY)7Vc5ZbiO_`kVHj?Ey=DnGLNv!aHKS(-bGa2S*cMNsWINWzF2egb64 zcj*^#B3rA}aE7HJxNYiH44P3qpOLs9Vf^B)(G)?+BC22}vcrUz4ur>jfR{gd@@~E% zYCv+0P&AS;&^7KrbEwbQlvQFYHR%n3+%@cPP(BRC;guDfr`X#k#5e-Ln;&G2HU8kNM-) zFPaK;JHX~fRVS2ti|j2XQ=#g#%EWdG%OlZBZnRA+2};b3!7Kh|M&`S{@A46djVL@1 zpZ~gu$YFv6>u3|>LQf%;^!ky9DQjYM2c{t}Zu-=SrMn`m2P$I?Dv1WG|43*43Ld=`dm79`U~ zKX~kX@>KqZzI_E%iEaJC=b$3o3)H6VPJWZQjevF#bO}1S6K1D%Iflm)Gtq9{?d};~ z_&@K;Ulcpa7N*=jamc&UiLrZ>Xp7(?&?=1MPrxF_Q*__wo>&Mj^Ln}x;xU<4pAzTIWBrbX-;AF!R@OMDM zDUa5N`piFZHEXhuq|BPEPbU;XwrA5e8&W3Kv~!S!+F9B>V)Y?l)|^|}?AgC{h0B#` z)7}GSnqMo@aVsp^3t;9Y#f*^Y}vm@=0pb;ApR9&FmGR8Y3Hi zIZQ$Jy}GYlE%Ql1&c)wH)q@BTs*N)CtQj#rWqNNYm;iBDX7sASb zwNTlh2SARpi_@AWk!yKB2~8@1QctWD>X#rxX2%dHv6Z;f0}Ut*>$BDFJ8{qiLRke7 zIUbJuhL`nZkyW);nuPy?wCq%?OynVlmHw0it)7vejt&uSdC+uT_%*vm>87cT#)1Ko zv&$2R=I=$vQj0GK78yAISZ2N{+cak?npq*uEwHgUphZ)wDx0K?#532);~TwkE4v(a z$l~`JSHCKq8*3m!daX3TDc9IBMtZufkq(Lu ztRFdCzh*Vq`6U++Nv!$ceJVznF#{q{b3-U7-|RH6uR#R~Jy)%!SIPbpmXbhSrEvlN z;v2*($wAUOLvT^3<}|RXIp$QrcC}~Yd{w{M|c$W_;Su#9) zSq2AV64GcSz?>#or<rd*;G+BqDZ4y){D0l6 zB*cqea?G0Tqc^a`u|l34OD}!`86jtv8%ewD#4M>nw@_~O+W4*|kzJYCbnD7avcl4R zY}hp2t1`8vW?y#A_V$oLQ-sHR>}B1<324)c-c#%AC=-9y|ZvyBkptEUs@w1u<{aS-qu z-;~jXpFmbCv|hDjz1)n|VQTg&^U&YgHjQkpBpV3ve*VN|r7f68+uXVG1MFu}To)Vm z?V+a)%1j@Er9$9Sux_(Ts99c7{f-}|DC4dyC%-;_7o@VHGW*~n6u3t6gFU5Ygb z)f+MB9Wd2(knFzE@A8*N*bVfS)lvdlb}E|30Bi}c!MDrPJ@E)6st7yrf=u=SHQ~PV ziqk`ff9%=(x|EsZx~nnQya9&c8(D?F#jD@OCvM>u@T^T^O+K}zY+=nZ{E;9f4w30L zx5IrJk>DWo+{jJxLY&ji^M7^=&=|~j4G)K($u|+-1vFU3^cVAGO#ftp-P32@>ju)A zA~3>(Ouu2fZDzU1_TeAXf9-Ua|6jK9k;y+o&5xKf^C5uc7Nj9NqW>rED)b||Qoi@> z-e+y2jh72egGB2?KL%w+`RRuuw~VhamN+Ss{DBu2c$PpC3k70<_hR7NlB@Hen@N82 zl`PF7@3CADi`TsLOULtBHge2|9+|u@bE@6P8Y3wV_WcJcZ5YW1f7%~>`n?zL=&`_u zV?{`%Zy4*yZxj<$2y)QGsBu=wazb*iz1WQ82;qFj8!M&r^^`W>>L)OOL^>)XTn`Rq zN9y++2?uOvcKrIfpH^27D?Gn6aUUs@xGZ(d3_@8|#4$eg4}a2dmP{WPqAE~0n_s5T zwL*=@;ogOD$aEMn?}U&;?uh8&Fx*Hn@PxC}HVqP&NNYCtEeAyD1;A^*=IpBcYDW#LRzjCR$ch^?1iw);EFP9VPM|*bnP7-Doq!53rQ!IiL8-8Bbo*#( zjCVLoKhyyn36?wCM-+>QRGs7W)M)Psw=m3t0=UiNM>zDHtJ`No@0ELKpA5)^wpH~A zMM)zh(M{ar&IA4g?3?2i)<41CgW8AD#@Gi3cGW z3y)DiD16ndM%VT=o*kH)j}7N&CxT3G@6n}UTh|hR!Q;F8?*mBDA zHd9>#zhZhzcDfT9>Ga{F#tHf83HGhm~5#lqJ<_7NkkS+j^p5y{PTJ3p>xZk3`d;Z{h}UbOOK zAt-22Rrdi&6jp5uMRlnPqg+ZBr7`L$uSuUV0yc>R)vXlUk+N`J-Asce@GCn=JvGo{ z-oNqqi$G(@E0>esI^|O$FkBqHULY}X07ZlfsV0!+^WwEbWROU2wLGVecAO#+nqYC@ z0^&K_R%#S`@r6+x^pRK1nWY{cpbb>BotU5m`E<4&wpBTep80FYDz$qB4v2dkikEiCC>$SI0Ue;Pq zO#>XX`1IT!&I7Bskdhb;?c-i4C%F2&Tj!{d9GmG|#xm%jmvVI@z!o!78TV3^>*QBz zJ3=8qQxU1P$Ac>&8;Zi2GACAv~tJ3bP$aiHsdyain9BgLya5e2v%HbRr^Z{NX>9FY#F>z6;~Y zAASyCC=5p$-BoNQC^hQIRRx&P5p5QT`sm^kgdIkbmMAx?640H{b;KHfqb|8VGB zm_a2A=dUsz6v(X|Y=>oWF{>dr$t~s7kyeO2GmPy+ZvJJstw9!d{`v3nUGYF<_Y4GL z$X)OY9!^qz;ss{>_Gvgkn5KkNyTdzfaWUM2T${vMl@GGnC%i6~#0FG_8J_ZthmPFQ z2>7;KN=_oKbV2-s$b$UMplK(gdr2&fyc;Nicla<1xRxw18^|3nLXv{i^P>WYLLl(=!WQJ><49Bx=4f^4yGshwm-Q7PP61IFj$7IA>q#j|hGw#~9k-I%PJb($B)q6P zEA#P@$txiUG)VE8u=YkW9|uY!ooC!P)do9uE+_}-*$(Szu-_bDRyMtA-Tu(NkjmHD z&qh|d>ZS6?s9<|8))^PrPkF-m;eD9GO?iSpi$kY3G1auWFq83D4tm?fErVVaOi!n; zIG;S+f92fhNP1{=Jl6JbA@~+EyaJqCwYv0Dm%Czs|Fo61e{o;PWp_?^2N!_hPO)DF_41Q3D$F(HXoV{XM__?A^G zYtJz*nxv{rhni~-aL{auH&={dO4mdK9zNr_*?gz#W`DQCID0@eOuqs@IfnOzS(-dp zw>JW<9;Ug)W(VEOXTMt3qf_VE;|S1du+cBs!!zldrS#`|N8^WIapDKV`=kx=0SsB0@zS;obxNwu~9p@P@H+EvQdhf zkFuRfLLbrMNr7J))r(ftTo|#AvM5TkcU5nG{0v$`iakunh<=b9;_KnY$Dd23cV@_5 zBj3Nwen>Swyy|Y2(rqAvtIUwfw^zAJ1CK1h%ec@>AO~yvxBrQO)PYyfSwIU148uOy zMf**EIuNs^+fTYD=LG}uv#SLVs^WZ_sW;hTXVGq4@}mMk$^Aig+^uC+ZD_N!)Wo!B z(r3ji!b}gQY>8tXAL_7;vl3vjO)Whb17tZ!vjA?j}^KCR9A#y2c<%@7O1rVqfLZAcn?u6Oqq?P2k2pP%GuH92>_0~SF;l*@c*tmDl%y658wX31f!)iH9R!6XOPz6-_ z#>01qLJeMnZIp4zKvNnABk+^op4E$*DcW~K` z18hVSknkv_(MV=tC2UwdbDgb|n3)EMcm@(S4lXnGkF}yNd%&wAcQp}x5omm%OdbPg zDdV7M8)K7e<2%kzWN4kFJ!vhq7%Jliv>98SU34q4y`#$T!o@vN6UezaJe#h@jY}8r zie6)}pi31i2rJeLo!5G1TM3MUFKk=~W9fQf@M^ERanHaEEUTy}ou#A6t^q2pd-jxplJxpH8cVM3T3!CsfKfszX|HsuTHG_XK z{tGKFRdev_c1O;y-|EOY_A$K+7#;g7*wrl%>_@{+wA5tZ`;nVj?^5%jJ%NsXcs1Xf z@$PMn2sMADm*$c1hrf9zVk>K_Ff6GI&4(U;;jN&IAu^aKgsU{9XdB2&{wbcNjf6KX z>GH>~%pofH zSU;<{C)JxW14UqJk3y!C5cuf6oV_?``=p{?UE6I7K&Tu)8!)Tb?q=5bIT~nOw@!bz zGk$JV56i5Z@*Ogfn@B5Asm?$I@Lx2?UvWu7_f?Oqlt@KmW@Ffy+P?R_n4xg6CUI%FTml7hhsa%sTUDqagAh9<`=f#zTE!~M+fBl=>z1O0Bs9G7L!*_@ zGLClE9F1iIbD_BdVi*?6q$YiX`?pypec5W80Xdmj=m5DY@zVN{k$84N;A`lt(KOK#&rwNA1)8*gc& zI%$zH3%o!WZA{3rokhO*&3la?V#=HZ+}t@aT-juBeE##E3Q1uaA$J-f0P0W`93flv zKvIyHsHa#)AmGRxvXt9XMp^QiVY{4J89*|+&&Z`@NL{;Y0|eZ|LWzoWGkhK@5fLfM4< zuECmuvXfLxUU)}PHrpr!lb|vRjylCgk<(G397_Tt4cb(ptMO_WXOaaOWA3t<9ZHSw zJp2=Zjy_VhNT{58s_vp}R!riVVAvwls;d}8i7Kf+S26wGWaH*V_q1CL|4~g9z(8lc#lO595zdXKYbH^n@Qt%IvHG@ z88L!Ef^YFXqut5wfDb?c8TSrH5f&O+%3!K|OtNMFqy7^?Y;SV~mewfRKoC+{SC$W4 z1E>WD{i5y%=w}X{1ktqz$4!AeLi7ZM*i0GG0ZJqSdea4Sjq2{rP6>2`2WgUsEP{oo zP)?Uc6;fSY1)xZG^tv2kT=r-gG!60WzA_qtA?;X>g}dW^BTMU*0J9}9N0rzumwL+V zD&wo1O?bkyJm9>+AAn5sJdvO~(z+7->_2P^CnOm+xSO^a@mYu@ah zAuBSO+G7IfL7o|KK7QxTIUHfAvd@`JgGp}IY$u6jjwlMv{Q(4R_;g}$xaPY*bO_Ck zIDIZelFFMrd=UaJW{08l0x@N++=&ZoGVdiw%NQYhO(w|Eh{iQy8=A||59Wvd1%?2Q z#l5pi5F_@!8mr1pjfK^+{lo<*%OAI361m2$cm9)q?flYDfA~A)+z>(eUwEYX8+!LW zh|C{tVlvn*kK1o0LP^p7g@1WBw;p1ZiarboV-6XYl0(X&0bf7M*St|!Ym8-lmbQ^F z69DJ{;}`|E-mWIRPhP~SI7@lkiMh*QTvUty<#!MLzMRh?e<=FRQc(6)pf?zcu`E16 z!eCKlFci2cL^Ml8r(qmU*=@=wm$QN&77N>anYOX~Q&7P;#3qi(hnzn(RGBhLS_ zMe4cvwy;hcasDiyax1s%NNqb4sO`-ETqF}mep62Jq`!`2>-q404j#+CkTLY6liDb+ zA54ug|D){IWk$C@emsHOq!~~{Z~X4JsoLEB_(amPSAib>cE+y_q1}$Wa4QBfhUBkM3(DI>AWQ^7B z+Zb8Tw{}IMZr>iuubsP#Lm-6_8R9-Ew1%8;bPl~Uf;3Fd#Js0yXALV6k zNfd82%L`|AzmkQ_P*GxsVqgP9$#0BGlrhM72zat-H zaz&5R@+kqF@jxseZo!qF#gYy^!(e+3uK727gz7_|%2z=mcfUGasv5?P;N{q+^7~$v zL5x`7^q2nx>B!eRgF(27XdZ0W&>fK^7_GT$u`&y6-#)sJ{T$U7u*n|K8LT>Aq zSXOQ!_c{w@ZzsN$^jSntB+f7EvJ$55X1&$xqXKD3$N2hrMVMaJcFx{^D5F9 z$MUg4{PRjc>T_L;f<N0#EycriFX ze)}8$MfNL?g(vE71fl)@R|=FLzYgqs&Hqtf2_N~7d?k6S)Oo73zTb072j0KPhrXeo z$&w@4H+%IX5-9G{^}_A1Tn^61!!ONeL40%K+Owbg)jJ|Vq_5>u^K@iW#v zzV#PAV&*uOmU8chKeFTZzcrSB>!%r_I6vWsK9Wh+!J0zp?cu=wqu<;UPMn>;5gaCg zRS)Q_eq^Oypc^AwVm{7FdaiWHD-EYV=lo~EqiHX4nWq-FUQia=x}_ai0sO-c8PX-+F7i z^k*zpI8a#OnyJ6;4u+|nOtf?oqsx<_D;JzR>oN^+kOMfEGnl69Eeszah6W~I)f3RB zA!z5~pYaUOP`Y3&7@bGUE(cEqu|p4+GX)4V=7F{J0EC`l;$F83%MLoD(B_9))pToO z!LJQbzHRmCURr+AeVS@D$4P~1&`&RxrhHpM_DMHe(DlPwQ8w4dT?|ASemTaP@=meV z9}J5X-U0CxUVY%WYu>NvnM=S@S6lrvf+PYz(iP@m+TlWa(PhipB)*}a#`M(A>j|D;*Jc~uh;NG- zyIH(dVE&mY`l?H=(`He+8avBCO! z$=k00cj+VyD=isBXJST!xvAscRr{N%GpJ;=+bR6?yY`eFPuS(x5tS)>DwOd9lxCE|l z2!7a@5OOyEI2mYNyLuY5a&kI*E`0$ip7c--s;wDP9%eR7v6J|?J}Nw5=BPQzaM6Jx zdtb9*ErWDi$Arx}O%U=z|0i=EAx6VMkSwcmD4ToN|%f6!b~R7w~-UUSho z{{Vy;{z4E=YOIdOI79k|rUzCHAO>G%+1_d*IRdB&58i1k{s1A z1$w}l8=4|EYXnHtaIqA_up1h_h7_wffVX%4r$6Oc#40Gq&Y>WLY2kecnBTaBH_lDf zlK&)aOwXlDs*3ckm+mhCLmzbf5R(?23>TXdDms-F-RoZMu={)ocj7p}CTy)&+0@Oc za8pk#2uV{f>mO*A7(d4Uamsk-u~;0*2>5hvrt8z*l$a3FLaYM*8sBg1e3pPH*TU+J zz`7wO!Ke^y`(bJrXQVUv3|p=c8&!as;a1VA474WHLZwcRXfN$kd+jsTFJq-&h&N|q zcDEB=!I|u^P9`#H&&aq^And7cwi({?x@IG!_)SFb5j`26N5UrZsKPKlb_(^wBm|wH zGavW|ocIvZwGo8-V+c#TR)pDE#wtwr&UhlxGNqd?;2p==f7aPQ&1j-l&53aFi*a&HaD;mP?!O>bRSF6xyjMw>bC|92|KqI21g9 z6CbuJmhV@*Q&+~%}=qmdLAPR%&=DnxFi<&(eQ5v{8g$kX} zFEi{@hq)_xUb$1$-L(Z2`Iw%3TLKJ< zHJ&0>W@mboXz-$&YjPQHi#oSMIEz;l>D-VW$f~FedUG=foQ>eY;Gy6pUdyZfg!f%% zkY(yqN**xvECZXOn7nfKE2N|~jEil=dRsKfcupN3Qna}v0!)wLpQyK}>nvjTx<1Ua zU9+E{M}WyQ7(%kuwdtwNX*p=hg`G(}8H#z%WBu>-_6T*kc4JE(2<{8~{cNF8tq_Xf zLb@~6F8Z8i%O-KW$lRdlH|7rgzRy3P_)@5iT6{9BH9OtpRK1a@C)^*ncoA>OESE09 zAY6of3Rjzq+mm)Y*@uU9>hIJS#eWEmY|4!dh)>zL+f~e_ZM-Rite|b@(ogZ+-ngya zaeOnl5)5B~(&~KyDzf|UqT`|ED<#59&X>owyDTKO(1yYMkVlXkChnbeCsSmA6brgA zz^D9molNz0tY>rED6A2M!JCx~jMI9_nYuWQZRV*dKbSeG!*Nv19;Y~Uk$OHYXp!IFz#6K4JSd$*a@#(}V2DdRUB zSU!<nCO&#xyx9=GXTZJ0uSME_p#WM#NtHa#kkq;-j%6Lr{1{4;dBYyz&4xZ zG~6|RTGcVm*yfmcms&V|B*dIDGs-uUQ=7HHEJOTj{6`PmEE55X(1R}>-PKTQB>xFV z&IQ3}&^d$|ap=I^=oa{5io+6<;FId1bdn`RmaeqIg^)*Oko9R?cSw6K_wjsbN%jNs z))XEAfmy(6iC*#&!lcnpk&a_GkT9%VECzwU%rmgr~s zCR;pO5_eW+zJh|Hob)V;X8K}lfrB02M>q3+;m}vv#Zz&=Yj^eDeM8QG&4I`}FP2#!>yC*(Yv4y0_rQI(U-QJUGP*;iQzXHI2l#E}CD_L;cI z56NA~;zG0%TZNCPVJ%!RWuXrIWAI{YYS%+daZK(gj%i{o!Y*7g%>@wm!+RumV7)*5 z!$vS_RqqeN;g^EfFuGwx5(tUV=`nHSQfcWe1Ra?}$?!kKdBtWx0ewzaCP@65g`GU@ zdE%g-5Fcp5n+j1|n*aqP-zU&Z>I_z95_uBanecBgty~nJJQWgg#rQ3SFUwsnh7YX1>>=ah90|Z?s5e+{^q}fAkyRwiK4^< zRKxv&JS^b5yM$XklTB@(FFE`pk!PJDd}!`QEg!3};44BEX%o?s`GK`FrjkLeNsyaM zx$Yxt3kWxV!7hpGBmfm#n_j$k>Q0P*oAIoPRYUZ7?0kp)heXb9@d*KgPv7UyU0#X2 zNp_lMX}9NN`j;i2Du{|cfC|WeA7OJ_!WVrw!`*T2yW+4!N!VFrvqm0*=^;=(s;3sj z|0#Y^Ou+6LCw@n=vfEJ!{G}J;CgMlt$RDV1v%1+WfWl*^R_5|cOUO*xCfXBZ-@b3%uHz5wYEHP;T)7LF5t6VwAhZv$)gXv(@#C-UA z@nk^U?9UN8)mqmZD_3!-rIk`|j;u}yASTHqT?IhVR)Znr;Tgf)7QHCi(tH9jx4E6R-vX$;pT!ih)Gb` zm{?R9K3!KVB3pAr5HLf^PZ69E|A2U6!8 zIOqV*RtEH*3Ld!TPN2j!Z)j-fyi0B;(KFSuB$hOHjIqhnGch0<7HC++6>kN=Wa8ww zz=|ks42poxLe=AEa_n$7AtM{>bO2ZGBRU{TkDEa;nc^aaWpkegG`1xGBA$##MN$Z` zo_W6lhIkQug%sKW2TLx&{PW^TU~D@}g$E@4I8q6bFKcuIc4(zYzHua`cv}t$#gxFY zzLw;1A~%hYXMAq(eJK;=+z_t4gwK^9;T}LroSYhAXjW2RRbRza;B&>59JqxP`2K>b zIRmZX#go~^<~&R~-9HYZlN|+qbdWW43BAAq3tEsT6*Zw_0{fRtXd7cHqJhpzp1Y<_ zWnx<1)+84BK@)HrVI%4{c7EfZLGrFUu2x4Kv41RULYxp3EuTEAXJlMr1t zVJ28Dxwu87>Ra2?1YPdy z`YrXY>mDQFfKrl3viIF!M$ngJTvQkqGYmG65>)Q|UjnGLVPfv3vC^IQnF^Z&-yl4` z)aXUTo`dQ=)RIcT5szFgk7kg|A~+VA#ROSMTsiqwAioS;TX{#fPoxT-!d>>OksPTj zFwq)@xQ~~HX_>Isj?tHHTwFWp$*+F+% z&u@$$BZ^OLTyzqF+8KC40}s}cCIRW0`<(Eh9C%;At;7|sd^)I1%_LX%9{1{V>9LaB z4&9SPx=3Q|HDewC#*+U4bc8rQvDz=X2VKEya6KHxAozKhix}%zRNcTlD8~N5PYXM9 zz_fTJpi)7kkHKbWlR*{)1=GQgf#WVy8!_+m%O!Hk)Xw`U%sFuSr+%53U0W|MPuBR zgaNtKcBCb~dHi?t_=b{?cs}C*nVcV4@N)1}CuKIP?9c=w=}2TrsHemNRhmJqwXi^M zIL+*TJo8SiwUX7|$X?a&y58>thOg6``$9UGN(9W+FV+a9<$@Ak9oGOFnTNk!G%)9`9I7U5OnV+A8aw~u^;{H%i?3mOwgP0)@X0GpwymP^;XfoHro#E*M3QZLA|%tjPz zhqan;@qe&rQb=QvMNcq3J}KcA;k6of59=~2oWp86f4G#(Av~K6icf(~i{k@VKvfv* zEHiL@M9oVg(W%-f`FKA9N2-kztw$>#*-Qy*uD+q4^j>F@4T;UttAsXZ@(R-6`gEKJ z`4cu6KEVwp?`6H9X$EiU0n#aymmiO4oT^AgOwAL>0saQ3X(t?qP9cPs|Hr$8eN-Ne zsvqX%H1ax&J`=(smUmQDh%-k^SHutc6-)UQccA%fZKjjF{p;PEvk(bOA0KR zbT5hB&5b!xDGp?y71WxKN>KWlPUR#4UcG-keb*ftc!#v42kt@QlY)(%T30ZMq3V;J zAyzhV{RA(hR5htK1%pPc(8)5eAJIPzZJNQ-2!4z*63mDNKJjZ(Q7{5DvVzlvX`^5+ zgrzjXifGXx19ch5(j1|m1P*a5s<>xiabil75D|a&-Tpo}CKfolB;Z|gYTa!LKAc0} zNQ!7%Ojlm*Fg%m&ok8>lE9)*i!$REV8DzmXZ5U6SxC5f{;;hw{vBPZP@yI@nAFKEd9w>^|mWW&p=PH@;fQFLuN3QiRvkl<4~wE0A>d=DO+Hs z*2EFz)yAY|*99L9ZJZ`Q9B7<)CU1{G0fS*HH}JttqNV$CeibS+J^IR+c|pDnu9ESe z^)2RnAHlCowB{=(uFdqezwOFEeg~MN_oDX}Rkz%0VlJCAyL`jPNS3-= zF+r$B^lM;em_fICsDypZPS_=* zSO(J0h(4x!WYJ}_7+-Pr3v3a$Fd5-uGoE|9E3T75%6U(`AhjaK3x;#$!8A<8X9^!R zDQ(_0QOqPZH32T9QblKzO&ny)r}%WtTMlmTJSw0{?jtMn2>iKVKe+{cyhIfg*Eet? z5~A80LH7PhU>h}_0phxhrFK;furt@*{cl_LS~^smyXaDM2Ox74e&S^((2=&`Ro zR$-<&h(sY%Qu@Ck{KJq&=ZVqrB0kb5Kk*>pgOkKxfpQVCXtaA%TlyT^xK z!FsG4OUq%o_DL?JYINZ^w@r;p9S zINA;+seXW=1bC8KchL$%j6WTpU`l7eCrFn=XBIn4b_jl4lQf~TS!pF1S;7-w?u3s= zBwWX=m%N!%-JBIV0inal3M(*O=iQplh;C&ZQQGy=lynsdxiMHS;ahImux0;s@UvkvEZ_vWsoL88TshK|o!eR3fqDJU>9*09@ zB*Dz)y}JRU`#P+uBVZC%W435v5;#Yo1D*!cI|oCYc=S5PgTX7q%RC|cuVP5T>I

ouf+&-BUBS*YVG+{pAR0JNg7s2ST9((+YLrg7`iMt@TVvhkyMc@Hu0bJ|c zv;sB{DV=CZwI~MBqvU%#pFH#ddkl$H#X+*V7S7wk_P>ug zq>44C=$Y_+J?B#)9A2C{HB~!(eS3S%z5W&kOn~jdgPs@_uN`*z!8=NW5D~=*pu#*t zRy!_s)<*$lLv9Iy>_jtT20MXi!#oH{<1Y(IRq>7J+h|Ork6j3mmmrg1D1yUpZS(nul@HJqj zwnPw^B-(WFH8*}u%w-;9je$vaq^N6+z$4TwK+Jr!R) z-RC4nRqe=7_X6QVqlYaw2;7}1RA0IPH5pG`JT+s>Ty|_x?y5!f*OYULA+%v5;RF1k zrX^f5zQ!cN+YuH{MgnBPr(hMY*i8dL%_FQ)Uy+jI_q5dJCuks+7Z3 zCx=#OHt;D#c_4ENW$JwnSUp6=wMWD%ad5(XrEfd;8+4>-eQ_4=Jz{ zMz+k`gtUp_~BTP>s11N#6+{g|gi-G-weB z%T6HOGX}!W90;l0?PCbBg>w><(w=cpS_PoWi7}ju0|OJy%>_z7#n-RX3uH_6jgBD9 zqAj=)diOH-PaJw)Q<$}DB3+X#QiApv<#m-edI(N?8O3A5AK^Q(lnq_?{Y#;1x32uA zFzX>K!#P1jFz8WSNQshZTwv|FTSb6Z1F4Am2F9m3!Qv0CmCC6VT98`3ZT1$+=$obZ zjKIH-Y-HIK%3anl&#|4HimV z=%rmy8yw0yBe{h?mI}%E+ZtwqeCR` z{?XkCCPKO|T>~H^p~UeUVVX%d&p-h+eJf36*mj%YI!}tBi;<=|NjX0AAhrYZ2^!gP^gON)74&BJr;V>m@$7uy2n_3&F{Wxj$~+ z?C$NJ*57t(F9Wc$oT^8kAIb~7nx;~tnhM|6g44z0(ou#y9!475C0qirvtVjodvmvY zYb>t~)uat)g2YW2`n69B6p$B6rD^~}8R`ci_Ja;C!VD)q70|;V`6ZU)Ik~)4sE|yW zq_IH_pt=P`n_;E(cJ0(VeNC8icIfyJ8&FFGl&+WiJX|do(A_@GOadk)wi&J(Ebfl(h-6CN-UCuB9p1nW&IhC+P;t>A!DJy_`e=@jZkeC830B`hTB+cF$8&{dGpIctLS+y0)7a9uwR-Et1Rv( z9@of_c5>A+L7Pk!NFmaqtJ^&}u{d#(V4%rTA+7A{cayVT%|@g%c6Y%R4_=%;1+=pU z8mH}Xlvk?H6D^J8F~1WP!jXGZ-3t2w5*NHJVGCe5sVJ1?=K99Jk$&pkj<`VZvRMZE zJ}Mhei8(4ZJDX{-z<6X5B02!b|GP%4Xvn@(!Xb*+G^c^Qnxm28&s z`V=EJ^|TH*cPm(2lmPB+#hnsX;^{Dtw|bRuZ^w20ZAvm)n)o@Ap_a7iXQlCs#a`uS zm{5TBmU(Hv31ARqU7T z5GrY*gT#==^|volN;ut5)7p2F=`5X1mngujN^)n;004&eggqGwz#tuAjII>i*n*RY z7qMC+-0-E-2ZFPEr#ejO%#5zA;-8_*gwPT^ zNRcJ3p~F_?gZ1}+eE80{`uRj#o_Gm^qYeOKXzBueywCM6ss z+({yP;yg1(s9C}x5{l1C&LxVA(c5nwm=A{Obg+i8Y#2ZGZ(~jkB?~F>K@Y+t5wwpd z0bxVAf_^1FdF`s_QFt7fS;0t3<14M!49i8=X@`;{j3Y1bP{bw=?~W=WaOp7=KshvF zlt_J1I@hps+(T|tc0T$uIj`svWnKnNK`-So!{s0k!Wh7%136J*frE~;{*Imtb^=l{n!i90DiUaBw8*hD6$CQd03RWcR>iJK z)QsJk`2xkp+K~Htk9sjic=;`85~a#A zh{Vj2Mk7{l$~qxHRbncTrV77Co?{AlVD2*Sh9E| z-7x;>9x36Ff>lBJ=P8_w%DgD}p~sjX*U!U4qc7{UMSn zByI_$Hj@kawm~+PtkHpC61gv%WEamN!7OBLGM<7#_(;3koL}%4A8C$UJ-xCGk@Y&$ zqTT?B6cV2=p=E>Noj_4qWSkCh#8?15O*8C_VS`4m6@@iR5y%Jg&Dp_u?IJ01YJo3$rMeM<$RVm+?t#$*XOB zve|m>@Qwsp(3)g<5@qA92?kIUZ5>NmZJM@jO;Ce`is`kes^_RVKC!4UTAl2+ro2j4 zIh&39`Mv{4vg>UB=l~dkz+mokpZ9s6AK&N4Ye-rw{n6BHo@~yo>?3Of*!W~{<`I-S z0?*#B#)Zm2QPJq}n)pG4@G#LKTfx>ITY$!M*o8gly(a~|h z)vGg8ND=Zi$)3m6MMd=e#%l)2S0pVnDcc`|nGk5yS@IapieZlPzc%&E3^Jr_PjPow z1POpFN?~e<6LBjudYIn~7X<%FV>u_%;klD>yxu&PXG(?u=?8lYrxW}n%FF`_?K&<} zg`cV?+(xu$Al$zo<%tfRmtak}72obmUd4u`0j2gK9;GQ|24OA!Sft@rp%aq0XT^Z8 zQ4gL&jeUs4LF7z)VwiF@Z*EW399uCPPx_lTg*qba*O^g5Dnfi{S{@k}n#3d&B>kO! zjQwLD%FV?vSMU+qXp%{2gFiN7|LqB7nmFQIGKC)B`?+Wd-AQ{}J(9f7cEj~4Y4c%_ zHOyh)yb=}2x7XzvmtFaH6<69PvPmgabX8ft*X z*LIAnL>I*LjbXE}Y)rm6zx?w4;K*p>Z7dJaoSW5`26G<#eDYF#No5O=rT?{(FImELs zU?^#PgTDp)9OqyDbIU!4@~PQqUsPQpS_&~ccf>tyLL3^g3=;{rVr_up36IhOGdq^` z9$Gg2It&2Lp(|m(sx|q8bl!0Y%y1f##)}3ufm?b!QQU@`1*U}q&&o9|5kHJ0gaz!r;NTy22Vu#KXU*Se6IiQ<1WhIxb3x_GXuwdCV3?1==b)4IXXe zj}RPF#33q#C~-L!%a!{NtrpCG?(5pfJRpEt7YB>rK?+*%;Bg-sbnOnug$@c?8V%DyAv&sznK5$lwM`zL+lo|cC<|ON z8ge8W(iigjvI46^=?vrtcNItpLj{_td~_m?r&}gt;K3wsy8^-icqY7}IZ_R8@AMT7 z<`=|p3}V2DU^pNZHj*RuZnM=k6)e(Zj&2>usdMYSD+8WH(qM2U>|nj)9QO-e)JrQ_ z;qlA^*u&};?z$c&+S3G30IuG|$o$)R4=a9+@aMtg28tn2m;LL@N@!vV=e-KMq1m9W z?x1Pp=zHU~kYb3Jc7`y~ww{cj8wp984ZSV_*@a(X)3^WA!NS#?F^DQhJh5=g>`=nx z`DIUiUqtab=$&R(b`Z-(pD;1JcTe+2OG!3|Zp+jjobk3bz1D4Y0^DPo>< z!Z&>k=EGc>Aq6Pi3)~9D$z(sZe%w+(-BKqfSww28S)tsN}?h4xIdktr7#3}YELg!sq#&aUJ0ut@LKcN>>hs^f*u!|)2xx3 z8tLVs%UULlHd`p~v(XXoX@f#KXX|It&hkdcht5~3)Gt9iA>AZd+872KN&4geZhKX= zr&+SDOn4Y`+9ql^XJ=GUtr>i)7Wd9Xm<2jUXabj2IJOpUQcl_Uj?qw!Wx^y>;N!}0 zpl7`%Yg&H|7MO7^O0tTOgmO1lyHcoRuy%e#ysATY1C-B2*aq-~^NkAwp|3f2Ml2*U zy&HAxRMRP?@@1lA7i1Vv(X1vV(bd_pGG#RnEmr{?nsd!3N2mKL;C^K}vCAkAKE9n* z1h#3CgqDexYQ(XD*b3{Ht@=}8mb(+Ndzq?(HW@|~68wZoXNF-Ccrl;Tkqv5#6;)q^ zHpfC9Pu2JN$j~A3tJvnt-eqd>h(BmZZeU_!dKsD}R6BkAb`BQcPA1#PGT6eEj<4ug_geCkb}>s0Wh7b`zo?z@dMRZk7{u&c_s4hhVJWg(w)ny3CB6U&LyQ~gV zRW=(ZD74Ml+6K5qzxSQy(2D^eIz=0WGv`=fDNv-VjBhPq|5ys}J2~b)=0u zw~wqD0=jYKOAmvi3rHvE^N|QK@zn)OERGV7y98iZSks&RV%7S#gM7}){(uTDEH2es zcMt8x$P}G65BT>f6M=Nk{nynVE0`@GVlZt+`yY1p-$^KYU@#h;#F+N zvv8IfGYrgvr7BeTAXK3dg5P}THTthhcsI{J)1yNDrDz^Yk-&5cJRhJ;jyc`6N;VCr z=wb$e%o-rG2hx#a*BVWx84%-cQ1`!&R_5O(P(bg-t1}(9;_k!!V%-up<@nG+AInrJ zbV6``+e=321U(iVSHI?gMgLWWnR=*xi`C>iJU@_&9C4E;Xn%phJ6YXPp1qRyd$e+Z z4GXP5WU)PpMv`D2p>nihz^B}wq#g1pnxUi@Sd|Yln0d@cTRM%$D}QE7niUGLL@WTV zl>L`*XipVeD6@!Dp??&uDS#r=O0yH$;FBO>e>D4h6x~odx$(QngB$ORvL|pxpGTEZ zARv&W!>zH+8W=uYu!M~%yPeqfS>+K(vu1IxDyr~QRpf>HOpR}QYsFY9R_eiqFajPb zh+>V3G1@e&Hq$#emW!xC3r6(4^;-d(!*o*~jo0wj0+;iP&PjN3Po;M-B`%0Vl3j2T z0rKQF&as-xwV=SDXq!tohwzOJm<~i-%k_i*Y1?JDS`#_PZ5Ca5+?#3w%BgG4=G&BV zdH*#_<^%zB3|2Cool7>0@FUy{ARl)|iVRadO!j~$37<09apc%p505XQkY@s-V{lGL6S zlV6K(mUViW93JQ1$J7mI*HLy9xwA+Bj!rI{Jdl0#H+#U2X@Qkb(K&N?L+YJQIu(B5 zD{!q2pvn$G;;9r8V#Gt1QNgHMTqcZNLMY*~JZ>HQ&+NZQvG~D;w$ehAxb+5l{5j$- z8n$Gd{XoP;P71hW{vU-ID9Pq)S7%xeZagx23OO1^AJN?=xvVM84={mn=HQK;%20>p!1mBKt4iIlcx*}^6wKJtmmT(MM{YI0y7 zztJ!2#KsK%w87>UpID4FF(m6?uH?m0zII)RjBRy#M}uDO4M}n1i=i43t)pX_^OIzo z{-Ycda6h$`Si3BdWH7MuV><@d%ZGB+x3rm}G{f4>f zn`=r$eMt@wua_w!KwO_`N)t~GYt`85fLSImEuQ`T{g*Oa`URHA&r2i zTxZ$7@#|Kc@s-a;^(zr=TE%Ghfe0iacAP9YZT%}7jOv|kgwV>`0ji+Yj%xLiO=e30 zUXqX={tjoeoC%+&wu<=^gpgM$bTBKp4e$1+0|xr0&BiSH_6kBU^Mj93c<*u&=& z_QRqK+Hz~->76@f>4)F&H1Z-fQ zgbY!jE`l)P*V*sb9lP1|3fOj3P4NVcB)C7+05%>KWSBqHG9nczt zA8QxLHX@w^jaoscxy?6>d&?L;vEdb0Xdcq{2VWNNc!Yort6aOGX17F7L07Fj&V4g-{#w^BvYrvGy9+*NkVp z0oxVNikpNE`Blw?D)~M@jvyuH8=v3SW5QG^{zi{8m$9}kvj{dpKu_4L?urWdWqkM0 zT@+mM%Cb)tT>WUY{y=k{kb=%9E=ZgL#ztW#AJmss@+H$Mrfkp-9N<)%*Gwj3C}7Le z9727NYF`5$Agl#)(#xD%|NV+(5^z&Q0D({omJrK0`$??I0LU#2OrZo;5-UwwbgAlt z)Fw&K_fI7+qkhj)iz&$7Yf??!OlzNs_r>GGkIF{-(g!${m7yG6208RuDh|Q)*a}R1 z89spoa5u2b4{WhWj1ixTjh##OGzPRAwA2JmVqkl3yYPRuWZ1OT7TgVB;iyb?djjs#ox^h&&K5I5bEY z9cJ?Eq@AtGg)&q=-s*(LE8C-}Myt{sj zT>-t0%$b zs!ZE$^}g(Htjw&if#hp%t$8gyoJNNyOxjRSjfy3B%E{E|nggb|c>9eug=$(hS2-J& zqFv$7VBbX0xz8D^WmzMS3QDQ_{=hk<`CsjK?y0oZy^sB1FpBJNN+?Klzv%Mi1!C zEyC^uy0TVlboIF^^5w8He*Yp0;We|yO~QF1DsB2(f4wcjsT$~_brAVGPO9vTk z^(bnnuFkx1D8urh6E7yS^Z1_BUfncpoQ(#aCGHyu5y|PTQ-1_$dfZ8Q(Or~U(C1NM zM-=m3lcV0~sMyb<(+xQI2Y`+kNIoW|&?wP%A_!$}$y9e%N2DIET}#Y-zAJ$JT6fST zJm61KSk6w!m(rG?C}?I)8-20^`_#k0t@D<|q$BH}1c|yxVR?>o$DZPQAq>(PU;Cf8 zLOKWSNRlK}O*!8BY_~eQTrc65+qglg2KnFoAIAp&NE=9YE{^F+Ng($mBYoEz&7B+H z8vS;%-+$>5P2fUKbIbqvzz(K+&73#s!$yKyF>dEZf`n>6s?rA+d$l1U79qTc~~^ds;#L2ErwgbcP@j>Hwmd3_H@{*F0_=yVw59 zllF*x%CSTw@u3Y9jSCU7v`j1e3h1|+q7Gg(Z~ISvq>w%$4o`dT+;*>4%v6qApcgF9dPb=%a3 zw6IWk75oT;^sMp`@~~Jl0%ql$tEr1gse7}v>O*)lb63v{y`7x%ndr%asYk7{N&|tM zxQp>vKOX-jb5;U`Yt4lc%5G8DIN%p&7FKOdLW*H!O|@VyjT=(=_Z-}oAQnqe02?SL z-GRKS>OmRQJeS*tsIzCP#iTKu(#5L@6K1}j^!wxCIsfr2S0qY=qOBMJ>vHoK<0Ek+ zR`AQx!6gTHjKE5L50EtyW?OU! z(flqBF#s5zr4wm-tlQ2S&122Y_X7X0g*8sI*A8iLI+=rBCOz~3`)m&sjl1b_G`oDD zaaFKsuXjQSTJuM&aAO*+S3Y@=9iSyclD?g7DRy~)Hj=|9g1Q{XChrt-kX1_<FC5b`k`=anyRYedT(RZ5Ukn2%VqCSH)jZkxv*fO6mx1II!mok@5kD1xfXAhu4QjhRpp9U&BPuy$XDs7hB+2}Ry5 zvF=$ij$=gNrx=xjc{~t$*#DW8{)ozD8}zZRPJIf=&vFLntEfgjJ^X$&=EI&V*d}5T*A@b?e=O???sWPChwnX#XoY63vw5+_$5kE=rCE&D! zVuePRjwWv7xG^}yCdLx6&d$BR2q*0W7yLj}KTrILmMT`8cjU|ogFuZ0(HCjKbMjz@ zMwEKnUEp=@3FNc<&@*-uH%G4L;MM^fgB&89zBmI$(CqAJY~T7hAQ}=u z-mF8nDRvKCf@cZ%hEW*D7GR(xhW9=`a3E^%PQe+^Qm#FiF5NL0C=O{bZ-xGKt;fhY z{G4+*Qcd=kF$krt_mm-(mlSkNLf({gU~;?Q0a zzw|4IhIFq!lg2}9y(xJ%ts|q~@^_6kRC@Y+fags?peodFA0RMzzOZD{pmr6-;M{O7 z%Xo&HNEfuq74s^uM4f21D3EFg)l1e_`O5DZp)pxAIAOgwANw5u37ZueBuB97 z4c~yRNhzcKY!UBB&u)C$7Okn!Xc_j2EQRx>7k3QEtt;*lE}{A;R!<-a1fyi^MiDS6 zOCW*=DrXnaxa_@ITqH=od1CgN`mt92@&+0F#Y`~aA}W-nhphw3?VEuwpC97Hh>FHQ(VtARgvMIhAhk*FGWDk6RIvlKs zr3|lNoa%PLO-k^AaM=9QgZ~_n(*wH?RRS951D_g^U*zN&=_ouSjT_;|w6j!^bclPl z%DBXU6aodjIm50jRu1SpNO#GAzBLhDk*_8*iqZqvqO1iuQ`z$XHk?mw?l)~DF=bm#+@O9z?-JF5~nl#GLCFmP{a16pjC&B8sT9I2=8XNi;3 zySqpw1ZXJ*=)W?I;zB!Mp7v@`F-j$adf1; z1T17hQ8pR_lQ_XpjwF-OX{v{tG0Th3Ho&KnI=(I2@hi`6xg$1oLv-K}dQOdk8NNu# z)=9Cj#OF?1ney4RI&t)O))#6Uy}5q>TcgHMB1n-CK9U{D$Tq@h1Ga3PH@bZ#Ch$4f zAq+k=R1i2$r65t~Ljy>}#T3z#+&A<(xbsH11?I9Y5QI!y_YFju&BsJ%dJkAGv8`@Y zxP_euw|cvuu=g6ZWS&Aj2Jg$glSj{m-kNwJej&#HILxpP7y-tP7vxmXRuqa4KvY*n zBLHU>Tm~>`z#Zq-FY7=AJp^5Z+H|o*yf-yyjKb^ZD%81>v%sBg(2x{|YshwgBiktZ z%ptBjl}gqk20JI>4SG~t?HG*wMDFjH{oyPvRh zu}Ej5z3gz-3b1wlSy~K&rp|LwvK7$)0N_6x-f&m5apTy8i%I(g`1it+p)9Rb zQqjqb3d{iDw$viSMH;zef(@p8ikW2N^P#YvOsu0MNfQ_rQMTHMP5<|Qd7B;!H!!Qg2!fZdW3F#xkkzcA z4waBEV8@gOG?ZkU@&(@md}8@jCs{!Spfgq8h6r5d+#jNn0WP;OPN9@@tMqXd4@27kdkrI07@L#>t*} zg8}wPdcpF$!ivcg(}uH(+ipEJ*@PH{3&D1SrHIoOamXpx3O}GrB)M zhJ_ZF1_?&ozRPrk!6jwHJ0Mh7A&b&^$+#p+Xc$Sa zYSB~|ezQs^U~?{qE(6Cr=psG`nPHh=llLgWt5g!nHN#QeC`oxz`mJOMm4r7+$^-2v zEbG?cPi=`3YDaO7;z&7DoH{~bIUci)PrzBGf{LBQho>upCmz zY_-ittm1weMA|H=1LXpjsEW3IzY4-z`N$4d( zHS*xJ-)1jSlL8oF%YVTr<(MGT#pxyH9n8u-S%WBQH0RA`a4PYJF}1HSGo-@qm!-fB zddqaXu{CRWl`tS_xWjp7T}n{$nL#yLDm$XM-(nVGnk3wD{?&iAMHR9wZ=|k3EbJAr zp>pH&KGvO+yNM@92~m~$_jL9xEOOSE$BWCy7dL*FxuC#2xVsd-TNmimRCL~)#E9ye z+Er8u40A!uErHYr%_RJG+?pQj3g*hXZ=b!cOal)=5_r4P;5^5yoxmF5p{58JQRLl>ywc0i3s4~vkbbhJg6Qv+%ewwMkd z%NS&>ojthR)A4w>J;CK*k}6Up+Spucc4r60P42eit!O|BNv<7`%`Zci9;CRTX`7@4 zVURp>p<8^rMbHkVF{{IKmvS5=Ha)ZGgE{n~;DGn@Rv>!q2?&w1G2w0zL(&~pVk0L7 zBdp^G3>v6Og?pdr+pBUt84?*=znVr82c+Df(D-K3OPg!mi*dTuLTzBhc{ zQ+2ntNJtC_;Yp)4n_9wAZ8y2k0uxK9Ze0dFYEG>g&L85L0-_`Bshgzqbc~|D(!^;| z3{HRwt9j-6)+?DwuerZ3@=`{C=%2$PUuNUhA3X6x^uNjMjP50pmxFuZmc~$f=^ddI zjPRF19nvm>|My|W8_H&ZGtS_c!F@Ci;fK@>Hj6dr&Ed=bb^u!ZIJyvnu-<_Ax&dgX zwClkS$a(-T1DveI*bj`n46A*yz1y2c!Px^__pvp`m7Pyb5k~)u(u-=J9emysjlKH8 zEo>eBKq*Iwh)tsNyiE(~U#zdaD{gETP!*1od^xgRe5FT?_2o8!`(8>$Tev706DHVT z3{9{n@#!v3N<2Pv6BF#SBrp{`6wL^*`J4}4Ek&ZW8r*5wNJtpVPv!7zeeLfwPex`&7M-rTgBKOqlAlZ={HI7+3H z4TMO~?fb`CPfxsm6KiH%u2kYwGIVapt~OIzGsA+hrA7Ho^X}F}8^Sacp1{kGzGUka z-(Ld;AMdr@!u-U_Q>4hNTc?^qqA#>dVq_;S$PeXHHz5B$tnOGmf#LG!F0J*B_M!hf zD?@=%+Dd5QX+#_?vV8*&w5QIuq0JJ-Pqh(@IZMw27K6w`TW0WyeC1oDZ?Axi2cPVO zpZ$#=+6ga2OAP<`@PR8hOCbf$*z#A{%3{98-)jMMp4T@0TMIB75hJ6{XUA^#QckBd z$Cfv6hc|Ih@CAqoSb({$jr{b)IIhZoeC=l@aY+$bP*(T}a0V~_%h!NSGcd?sy6=Z2 zNE4cvIU)Jivb+#Qv`LJ}+6l}G(osGHWOv7h2dsgSENuy@`WpiQulXex_ zpT5uRxjFHpi_qc30@M&Iz;5DLwsTloAHZyMHJl>d53wfYfa7pdYgw z+7tt)`Fj&TY#cb#hD~udd;4y?Ee^0FsL_m&=^U}JGNpfz6sj6N5G=xcG?*JUJU2dJ z_xJpAk|j)I)@wP9UVSF0%B?MtPRcUN$ZZ?vVDb?n>yDOLhCxSE%?;LoHNyWG%nGyX z!l{F(B|=H(!C#S+{ee~36TK=)(yTqJobF~3>goKYo=22HqC-Yadsv>zCVll{Rsh%*!I zhT~9>GohVMh}u$3c6SeiPJeyVvlZHLcTsSmnV&W(1>U9N^+GB zH1NfBXt%rh>Go%0B*RM4z{fzYO&wsJbrSUyAJ}!-+ROccf2VtppO>Oo*#)li+*g0t zG9Wcq2E-4HGq)3l@fv68l!T0E0qjPWgY>>>5d9uDkm9uA*^_`>k7er*ftJj#Jm)WN zBtVA&{8uQT3WRMx6@G8|sh0gD7V)0T(IPie zou~DkmW|hzXId+q(TsnTG&%5wQ61Ylo*g`O#cpG{J-QLLDwG*>nWzzbmKq;LI}mI? z)sTr(i`3bJ+L6D52HU3GiF2#}t6TRW2U~h{x7sR}qTTwQA4K(H9*0Daa6MFU9(uGE zqK!f*w<|!#pV~7`7{;c7;yjcSQyL0^9`-*E2K6veG59RfYpIDpL&L(6HfVYt4L=?QS4nJL3)gq)RPzD4awt{4L0mjV6mcK3!gWgtqMBG?Zg!XP%2iA?@ z6>)?~rb-1XI)ai{he)zRGGF(GH>lGeG-y&z3Z}YLB@df|WHjei4kyENIg%gj1IM$= zMBwPt@u2|tNc%w(yHf3x=A+aB>xZeT057a$VOCxHNGEnHIX<_GvY}3e(i6D+$`xV0 z6jKmRMj<#RMUWB|jks|fQV9SQ!rph07my#2>1<~lMrAqa+@~3WQmdmU7l9GRs#8tU z?ekZ^iFa|DrqdgQVpKWVPO+`%Ho^ZVvjcxQ$9oO@&ea4sp$TE8bF!=JNi$8!0ZDEw zcY)TWSDagSYjYB=SBf%9ySt2DJ5T4ey7|NU!XD5RAfRm6R-Fyf@66I9<{dhqQ|5t1 z=r@?C&Yc8+?E#w2=No+{YU~>2FFMRFN12fKz&vt&)<15wjn&Olz7o}TZdIm$jC}~8 zo5elF^+fCm^4oF|gQ>p38AXf3)#qMPol#9v%9$h4l?a|bOxf<8k)m{B+&i57OsJJd zm93z?X$|H-LKlFpQ^kX_o@sbu{x>N!yf)n=wPv!%Gd?wbS|fDo`yC-{P|D>LFNefB)6*nEY8pb036P)Gqu zk~P&u_0+fwwlTcSK<5r;vN4SSD2^%FiCQg>zSUUxbc2Dg$F4rrUh&l0KD2~Fpw6B^gL8Qp z<-w$a6{g+w8>gt($iYuh2&;+C%Y=fd3-O-&+UO)k>}q$9qX_&sxj?@RsGO=;f{UDk z>>>r@?nML|kaGZrBdH(#8{6JgM}wkvb1H(=uX8zyz`D}Z&gaxtVxa&@6HO$*_iy zv#SUw=!RZ!J8cS?0L-zGo%o<3lD2y4|59TU1fpQ|6?tCQh7Z2bE@K{04UIVFvo0Q<06#74kWCa>69m8cetrJ#rk5 z_+gfah?CfNh&mg*5=Me)@O)S!i>F)*9MQ+~q>9qerEDPf(VbBzl{3WH?>m_mAce~4 zIkNF8p&=x&F*4qqwg4sC-`|3aKq{gH3>J5Y2`QA%T_wBD_@r;y{bvurV`hW4Rde31 z|J2xp7=EEtb8Q~H8xqzpGRZ}2W^0I4u?^OqQlgE`dJY@*D7H@8l~?j=1KHnwSqLba zfWr5^2cnRGfM|aVHXi^rrmI@ewWhsOv4(o}ILmElIShp{?p{<;M;lQ0#L+R5T~yS8 z8JC8SF?(G)gW;OgIj?=vZtt7szWCJmZ%GTV+1V}xyOTo<5+DVM`@6PR(80oX^RWdPhc8g6ExvRQmfb!r74?Bw%dg2jb_u*w;WWvB-Q+mS=5f+~S}GkC{-Q%}DP9XxW>nEo<~4B;_|)_C};lmq|Bvy9dko>e{3nL;+aTsUsaUpj@mheB}02{SPxy%|QKB?7N_9 zRvyqgN`b5A4?dDikdX97B0fhs^*#B#ea}09_y4q z+knYa9ob017Ozqvp?t&|9Z|;C?1+WM$B53j;cLC z&f@`7fm|0=1(ZK-n*pJ9X2JDj3h>LA-hvYkY$@mEYgg^+i%3zbb^jQ~R`fFMTJaGI z0?u_;EedYqo6C@l%^zOIt))VPBG&5XG@A&>34i9~iK8d0N8ehX{d8}x*=t=JeGtR@ zoqPjlc;ykA0amoB=slXEXk3hqilPZ?c8~@}>;X>sB&UBV#^Z$ruudE>$&VaG^cvG- z^g789Io-RJhnI@LQY=AyEZFa35rb2igNs-|)O?pgv!p*@u+*_SQLdA^(Fvn+Z+F4# zZTfB1SE{_vp4Ch}eNXxM5e-lg@~Xr1Py^yNBj+Fn+%G*fFt#a&(E`2y`*0n~;WVW?9o$6ZSYX#ZuobwaF zU@#_XvgCrMv~GB zAJ7v4AW;E_7d5=$kw(+G2joB)(=^y~!NRk;uN;`-Dx#yQtQ6V6Sm_YXN{r+DQd%1W zDxny+f>1io0h$sQgRSs;GJ@94wa+-Y=rnN^TK~?RXx(ygMXE)%P-QPfNX3@gy~LTS zdFJGm>&uC%*C-alf4VnJGzh{nwV`>QY`OHru|4ZYo4vVf{cD<0_H(e*cG{^vhB9|( zqTNeQL>s59+s$L<9>i8hfGQ#f04ikI(8ER~BLLWqTp_`^N@S z@VQ7_wwo9mS@~*kTG$&TclbJ;os&5j+H29bEg=@ak6L~|G~oBuexCt|eI55L zRx@2o<=m{kN1_iu`02Kz9rv8USpZfp(=CnBBLb%AsfiOD$8JY=GzrOUN*Mj6|I>!Q zRv*{IX)6p{8bVR_9T~LIIx{NvUym&_mwh2LY#SJbsd#FcdgN) zcKXQZ5lyV-uQYiKU5mE>#hte%#&%dniqZ13mA1?ZfD(A^dWC*z5Q~B4v$Em*;F|@$ z+46@6^bOR6ok%|5x(J@#L&P|e zibb|u;`RgWv?hx3TwG-260Ai9V-*XXDk>z#o3tVW1_8dn zExOz6w%pxAJqhQNE6uNCXV`zBrq?5i1LaOo74W{f`#^{-XCH*8E6MBRyK)?yrVe#q zGp9b&j!rE>i&X|?xf6Ik+h=VcqPS6xvPTARlGXT5&Ta~ z zkX%$7RszolubGxms+tBMkGR_;CPt7&r}Klu1GE+U7DXvZ6Cxv#jh6V3UR#K`oE^_` zS}6S)aBH;$qlnpV8_kupw8lp>enf53yv%^1nIp zCf=}tYeegqT0aKn0l=|F9(!z05+m5h3kDs5<}Gb3n!k777B+$pj3XozXSWxCdBeb{M?Sp zX)OE^qET=Ul7*`E;LU`1CmixoyfqtbY*YD-e_&GtxCz1+$5IwO?c(4R0qi*VBct{J zON)N87J=NI5=S;zrAuZv#j3omOG+@ehob5L$bf`BxT3YQW>#8#D(^mRDzZt8`4Dpw zA#@rK{tI)ZR~i zDXCoy!#rE3>a=8YM{Ely9h}X?59F@ePiDW=U380+H=2QqjFQ}i^wQwqXDltC{~+tK z*0!q*@uD5f15@e-IOXtKR$MLi_>=Ev_#@^BSJWUzjaa?wuv4-)^4U$uJSed6~ZGu+4vs0MpK986XA=pV@k zxl)wnVF*RcWBHZ8&UkWSvyfgShOuR z4AVlz6{pwMxWyz3UXsvAs!s2xf`AMGBLB%Pxp~W+oM_#gu;fd22#1L=*fsa7x*Mwu z=FXiiaCd90&Oq5IyDBI}ZYC&(WQHeFrb|D<_(;1{d>7|QT}b!QP~hOf49W+dw^dCj z7`t7!rM~dKie>~x;E(1cZZ85&WPpeC$!ynfi0gwKk>$KaR_&He#;N0_=>eJ7LVdt{ z6!!Lq?&dJ+%c>+8|D!VVV@NLwyUuWfwwV6m>Ichv)gQM>A-CfO_9cK8{6>b2%etH) zj8VnIAWPl;3|hHuv(#eaHt9IW1b7-7CqNSc+a^86yBKg?E5$m@K{==e3i4O}^nC>> znGt+#HKY}FenRa%FhEXR43Dkv#`6tS+6OXoH-i&?RGZgOkOYKi8#KCwO|}&cSN}1j zLpfd?Y{>BBgvU&g5w=nTHmD5g2Or3o6g;NGajppo_^_g+fNV?A=x(q?1SeAmvNy|6b(*YmPTe;)$|$9OR%3f;kh{T@p*Lq%=8&V@v6oBv0IOj*F7- zi=5$N(D7W`LH?w1#tZd!;&ePaf~ZhQTvMy;a4K%a58|*;uOURGGcVL~zjU^C2sWMZ zFVvj$bo~8m|KhUG)oBqq=wJ3xv5^|n*EM+F_kWWNKzW&&0(IP9$5}aF zGqtErtBpe8R%)V@3b|_YW?JZ63XxxDrHJC}6c`F;NVb&ndI>kQQy?UciYXmh1-bk# z*SXy66r)N8-W5f8g~N4$gCR`zrR&px43!S3*v3={o zTj+-rK?76>tH5XD{l!z>Tu(WTC`H^taZ`_GU)+OdfA-7e3!|I~xkCOTKTXvD0n?r^ zjf=JM17k_mXVPg@_u0h0j~5VJt)0FU9*7R@S@nWF8Qv^DSe1-(6!Q}1*rLeuJj+&O zPtXh*{tpT&mN#F?T`4isU=j0`rS7iUp(q%+6kZJBOH`XGPSj%mQ1j(EGJl41KzC-@ z+1gkB;dWPrsQv%up?m4x3-{&MNBxKg%-OrlI;y!>y_7>9skRj8IRtl*zyte=?hjT_#)}M;=PVsnF z3(Q368+-mL?Qh=8`}xx#>=Y(vQtvm?VjYcJb>kRE+KC~)m8G@lK+SkzIZxdX^Wb(C zS3BubaZ+9`ZosnhalN(7PW9^TF5*(UC#dMCrM1ptZ<3tNnQmg@Zo$c-W|EyQ4jY#Z z8`gsnoaAq^bTfGHMy$}vfev* zurst4Ualn`x5HH5y4$bJbn6F$N-=1Z>Tw~@%|?wKT6euON$aVY?c5p4lYm|hyT|)Z zKvQMW8UOyD->B~}PPV~9_F=r)Onoe<6Jr^s5mT_ zhT{}5=@lol|IW{&%5CP5=atR1_{sRW(c+ma?QG1gcq}kVA_HHTX~MakS=|r#+3-_- z#{bY@8)~)8hfCi$_E*qBJF-5~GSv5+tW&7FJwMg>C<3-PaH6FA`P!A*qM2@@Pm&~S zd3mw-OR4gcY#kUFX`BIO$;?%eBSK ztVFLi>6d0h^x|YLuMAxXOpmGzCaRVyN&HCM#6XXK|M~GaN!r8o^8_XcUTe;ziRq=o zzSrF8j9*U|GbyoTtXMzVe5IMp?QN98I7c>2KJ#qpu14%JIz&4Zul zyx?^Y9K3vRCCSh4eIh(tg9nLu^3n0xJZT-MonA^V*LKyi;inGfFA)|NPM@#US7w`& zr<364vd++J`2jzFuv@52E@sI}hO^I_W8V(s*A~0kXMa$_I+!G6rT6*uZemaTDtfU~ z-q|xnXR!wR&4s8Do%hVyARu_FtsQ4|iqKGxf6coOJ5=sNSFRS>T3-KzUmMGd`)cXf z=l$i|Fd#BJCYj&Iunlv#yOABhTS6=|PGO^1s)ieX&rhB8l9-;)>88o2Q~rQR%d6Lh zMh|g9f)mM3zw%h2A;n(yN?hJymb~Nq+Ny`x?fXPdJqg>z0Bd0zSd5y}$qMz-=_@D@ zCqXcB>gtetXQhy%=2-Q!bDsG@bi2t-T&Ihs2R&`4nI&c#1INq4FyY)mTA@lweV(5u z^-~<@aE*n%NQqaan7rC@)0&$uv~=4 zinA+)vP;zwp5^6Q{)2yc8!DF?M{X~SQCS&UjQV`3@E9jUKXhQA9+iS~Ij+n^NvCkA z?AAKx;_@gom!CoIBWH{&8|Zep4`;Z936g=--?2%v$~(XQ7xh}nNhq7bE^r~9>j90$ zB7K(33ooh{`5Q-r7UTF>hWT7JgMOZxOvSCmmt>c?Bxhl zKCm?!(TUmTPn_gyFBT0Bhf~+DoH*eZeZEiv)gpESQK_dp%}V0t32p{HP0@shGj?gr z9TVS^2-=55I9<#Tlru%Ao);5-#!Y!iy;evr2T5*76=ikP+?nL{(Vb5H-B0{&ZY%@} zNkJIs5G>+~@JP7lxb8v-T+C$U5R#(PDhw|pQFS*85*)PS-MkWJ#g&4VA0w6JjjMiL zTf1f%lu^^9TVs_?-Msgo|8>0$e{FP;`c8m>kniB5Jsz~|R*PInj*{+Tv0U^PC*|OE z3Y{T0aVjCP$V-KaXQ)0{2Tvd9=h2jq{DSellTD6vb8Cul9YF+ctT12RyBt&jm$iwNu1t zM>zEIaa?FGsT7>MhUQZ4q3$NI*h9Op$=1ROGF>a)H=2hq)8_(xZlabfCu|PgGk0#> z#4Eq|Q}-YRZMH!bZt%!Mxe%-z*Wk~bWD!d1O|+16*$d*hab<7p9O%*2m^hscyzUB_ zcKN!DKI2l4|i9R3!_i^^qA%tJ@oSMsT4y>BY;AJXu60yv|?qYxjrV_~(KPdwXrpflKntdwJ;8>Ad#x zBee^)S}WTRjmhMGf1~F@=}XDpp+ApG{?>Fai;e;`Fb&%j*fTPL(_4+=|7gtGcy1e&nxHq{c3T~;>L;Y z3$+``%vx>FVv^KeX%6LKaxe}?W}C_JEKA6nHItwbEMJQH8#O3ylsF#Dk8gB&0d@dO z+q)1)dC$)&ifSg)RPea{jWR9Y_0I>s``v&0R{%@H>G;Hb-Yad@1b^~#@vK*4*~5oh z!G*Lp;_oJvjr>@;*)|@sY`A&v(w~mEneT}*~=bUpGPO@1XdB^t}-j(3n#EeXvi$ikI zpe(&oL(Tp)kdK6k*S&so=H%Vc$oG9e2Sp&$XZ92~DaZNvZOO%w4oyit6@WwxhNe$5m| z3WkJVxfmpSy661H)6vKOP_$l(Oe0=BkT6($bI#Os@!H5g3kpZ#J>Lh`svRMmI0A#G zuO+u?wZ={k-D&38jA^VL2ry6%w@{j1!3kl$OyYj_r+(5LKEUC;UL4vrV!~U# z-ww;}#fTQ<5pluwdd(O{<(1oVL-k1VO!V;Re7{2f#1lh}rdwleAJzoX(?e?!HHM8C z{GC76i7DJS+@pES{q`UH1T80!bkgC7xMC7>4a^jxSY+ELp>zKbv;vcI>7mAOu^b?Q zwTna3=6D!7y}79Kjt+XQ6fQ=+(nWF2(PEAal@593wTLRwi;)%)>&M}uo!ONJwL$a7 zxfK&cP$xdk8nBF}#}~5~kC|J)_>Zv@%o|9!UEZyIVz|i7#y!5zotq7J-Y_DwM`c$f{k8>RD907&&)6jSjyQU0!x}5dsp$ z;TMsftFMOakxN4>g}bO+<$lkUa6IG>+|YZ*_2IKzKYgza=d5fxBjEYaErrEGKXn6z}Z+%c9)y4IbSBMW+jw zxtmfoOL0LjEaCBn8+j+38S5miVt~_5lp8pHWv1zHU{@M=CaJ%UyP7%uq%#z_E2w=Y zCHRLh6`dq_YJ!3m2D6mvqow*zf=vHYy*q|q`!8Nh-t0aSymsG<$x`?6?Rc4>I{^?2IZ!mbDZ+g2{ z`1|CNeV=!e_?}?!_wm?!gE#yc`#vuwi+Y>d(~vR$UN3^G553EPnva^nyS$iuKmO5o z`FjU{_@*B5Km0cL_`|P%{KZZFeC2z!n}fIE-@#4Q*5c1zDLsZ%F@BWizwDu?hDW8l z)U6#jL@;R26W)Ff5SjuK(?N3Z*!jmpaB#qP}T z+B|>b(oiYhh=zC6?!3}BLHS^OB&dxP4+Ce^YG;ZY<3pqIdB0UWaK`g@lDHiubyisAe%9 zz5t+p$h&JOXeT)CtYPX0MFaBUmg6D9g!~BMeyeb#HrC`vew-DP@u90ViFpogb2&~3 zj*^~B(mqRUc(+k^$4WTnfpesW3aIbIgE!65o#qQa_=%7XN6deC0;6#}#Ia|$Rgyc( z&0ut{+olgfvnYC292#KB^|&v&Ap3--YTtcYE@(beTPIn3M{p@h}GSNZrV6E)e zieog|#8P4T4p1tWyQ6Z=H+KMRC7F|L7VA5wV`og!9IIbDbEVetYRReY z@pQV0Gn}1CuEyEv=v<7?f)EASX`;~)cf!qj{pR5e=q)*ePt>?De>iJa`aZie2_{bU zR^I*HzX1D)&+RSyPwlPxK2%g`j{wO8SDubz0`fQuCua#sLKZ1s@5gzv?zjA7T_Uc- z-K^)&cGu#pQZOf)55-aKXNUY|Yd)<_c2hSwamSN!e&*F?`g-#~oc+f6Lp@S&;Cd#y zR`7!3Nq(U5Oq!W*as=_Y;ElY{8ecgdJf3W%Oy^qcLUz{N7jsO?=Yu$T@73R{8`p4Z zog0_^mEtOaBcW$GFvQdAZqg{4x<54>82^qC(Oz^8cax4cH39D9WO0p%Dl<+t839Wa zk;tf0#2u^@YP77?_?FOyZMEW>m7$%j^cfP{{mbnB)GJ>IX3IMhXC)l^^Z(`-JH;dj zL9>i7A&}8x-39nXG;#onRitLM?BFGm@GHr zMZ_?yWiN$Ava_d`l1?$IuZ1}Sv{I^9Dp|I_srRiFokPy)#CLB!@@*#%JH;}K4M1Ud zKAz@T=!B6)cerE?MQ)0jvq9ubLatJ98bRJA9g~4Gp-Y;{*&6Y1saM=nIE3BB{YU^j znpl8lo?wm9)tLg*QU!0T^X@-pGnfDCI4UNx<8kMF1e#RlXw@hM=4Kp!l8u3Q^jxDC z!fBiGaP~z+zeP?wovoR~v?C(w$I7LCTrcvnPRKb`R~Y)@Bu(!)a+aNKIi|zn0xEUL z?&X>DT=1^%U9Q!7OKA=xfe?w**|~r@XtE-E6+e!s6SS=eT*zHGPz{Plat*h~rSZ;5 zQ1edS^5QEsW3uDfWuMpOf$`}toEZ6r9Jij8rAvpJ`#btS+Ds+YWE z*gbN+Gbn`%+#W(pE6U0<2@%$>+k-PUvRPpH%9TUe+6*?9H8*q#V=!1 zCUD_MR5nF~A1N2~yM!x+{^HD1Zp45#=9u4 zc8VlXR?&m3FC*w#WR&h)3KWDM=KdXsaW}}_AZZ-{nhK)s7#jC&n+7fn#N@2Wa-O;4 z=1}vDdsfJ5=6va+cfgzGd^d`sS_s@ztC@_ybuQPY*O08b+n4NeI>1gEb5l1}f4P80CA5Yst@r#d@uq zxRoK-Sz&i7hnYFxNie13BB#Ml4g^Xn7lOzA?~VPWA!9Y2*Ws3AFUl@MxNI53L34(d z0R6K*8V*z*I|vd5Nl7gka}#t5n-=eaJS zC*Rq>`{DRN?SD95`&g~vnS;^ajV70(mDx*9edR!{Hdd;-VH{;=qS>irwK`!&zr6R? zW}DUKu`aE{8`Y6gQeD`~ADW$E+0b*gapL!L?-%y;<0ny;{eFug{bYLSNYsFvuiTS@ zW#z9%=i}-n@2k<7+ggkS^n=p*thcaC=>DpXcUoHa#j&S)}c*ZX@7 z%JFBCowF?wX!J+b`?&AEd;jl$@4eI8rIvQeB}MhCE$Jh2*?i1ZrJV;FyPL{cYRaXT zRrzb)@9r6@JQ!YHJrPzehnQXM3&;o(awYPkj)TfXVxP&OKi zzwh?bW&djbjphU7y8HN{_WIm3W}~YPwON0c!yp;%!m0dFDQS#FLFd4&Kx0oHYEQA9 z>~rOP4){{&cRs4Wu&=v*&-CQu=VrRyXnpRIQE#G&QeZEjtj^Sz#pBuC%Twx2&-scH zxA4~kwNrBVjZb^(;xMIQzoLxYJ7mhs|722Ln|UDKchy*z#o2DN3W#-%6S0LNhj)}^ z8={T5`Zr$N;*ba~M?1Qq59i2ISrwQS+kw&%#Z5#V#s|)ga#)xfo7ITg`j+52yWSlY zdV1+D*!{pWsys5srU>}RBMZ1%3Hag&NbT@pB-}~DUIXl2g%l2bIb=b6_Cq0pZiufjm-koQH>~y*6+C&CGBVHmnE0`Mj7;!kEI>lZ4A1EX4im?D zuhEk5;#h7UX zBr(&fx`e5yI#6G0bV@358STpkBkhBtWL!#Z|d z%K(962WMORRFH4x40W)EK~bE^>O20o=zFlS^$` z8yjs3O&X5~;7tuGR&92#Uiu1%GM*l2S78VuVrjLoD`Pu#8OLicJ{7x;waN{cfsKC) zj)ieoF18Z_QR>mEUvHLaP=ZWd)n{_F7s!tYaV!|4Nr@%e%`y;DXUy<3F~)XPRaU-D z#sKOu=pdes(~K{I(?aG>*Urz3-v$!#yIet3Y(ZIe+L zwmy(8<%UQh6j zVLm5XLaMftW=uuC3q)_n7nYG*%ImNv6E@v8g`ekb_Tb|j(rgQB?dRSV zkFYm%-1drteUV|H1?u=A!!KF)cY|caibpWhJD{Heq!4=_vR8-0P*bsG0b zkC>8CoSwWlZUmG^QOF|FkLjja>uOExVFV4ZzNOH9Asrw5R;j_p@CWZcDE>xcYIt|x zaN*4>8+hE!zpat9&x;2p{=)!}d%*c_?CKWh@31R?v{!>GVt~xu_75O(Kxw-M$lj~d z--D&Se}Kq=#Esp!&<#ZHJ@Pxy-uD88{{ryrM?rEw^MhA;F#LOgJ$*HB#+C2t6#(3z zEyt&wmf6AJcZWARAPg!8pr^W?(60{+Y6rbD_jAUwSZ--3dI|DF-eYg&U(= zT>;oMYKrATu9B-<9D!kY+OJGXIo(KSpM^NT*IVq>)RtOLu6e5Hc4yS0 zYe4rX=K_G4REAc~3_3t_=}9S_%4C?aaPldU%%)Lun~FF&A?e()xnAuZGV`)taF z)b~0ZZ13^SJYlVIs@~N#E4f8GT{{3|AQ#{Y{lZs`GOoLUvotUAlX&nL^MT2Uc~-^| zfzt8mNbg9Dkv0OfyU{W`Ctbw}u!*N^%{Tk7wY=Go+S0%%k^>xfQz7{ehX{Xl{JpX5i~O`(n*+Kgf1D)^QCDZG9*9#e2tj~D*}<)vV_*pG%0x`* zqdC>nFem@rpWssmm6_D3XaFNxv^dIj?5a087T1Pzw7v307wSNe?RGYStyl3RvrCD5 z7?dsSM{?0pkNMEt$wtGzy)@zNHft9+Pa@WQQM~zUUp-#b(&;e2 ztR8yAkc@zV{Oh$*g(Z=9MmUG04+kA%2@~pgkhhOH2oxF)H@E!(5v@&VWoIciX(*Fk zz`8mWwr+Biv)qf;c;?p&PCp$$Z~WcIR(GL?s;z8eIG!`yt| z7%Wgl3@(YfJ;@p0%|3U=|{Z%`7_t&&Ib5Z5%nY&5@3h&uSykFb-xd2vfn=ZFLkAdhk`l z=t+=sP1}on!v|NR=iElq%DD89QDNExq;79y#G7v%2eA^3Ge$l+)Q&l7lxrgybKRr! zRsAK#QMQELmr=f!z442`ubbW#XuJ-W5(0OlW5@i*FtGdSN0wW>6uj*N@7jnKWDTfKX6SF@-?5z;Sns>MdPiqY!E2zkJvGtyo&JoLVRi zk%!VsM@1OpDb!QCCpfVIbkR3wT*U^4!nxAG#H}T1uEPEtMxj_VL+{M?5nMvxpx9p=-6TZp*#Y?FSCK>^)!-dE4hqOTY8VHN zO6$2leKC!R(>@<5nQ>0>d4`2$#fWsx0JK;a`7yFzp85$;Ksqh^g9SxTU@~tqq>tci zqCI?*erYWU_u10&idf)jY)#t9w2f-ct+EpEs^%greZ`vMlL6eyx?-p>9*&R1wr+x8 zXs*4wl*hECB?vqx8Jog*#L9sD*v&zlheT}4fqZI!iP6*&jkp*s3dtc(Xh32pthm|p zebE~&U^TQCXOfBq@4GE>QQQ=&Wg7fr4mA(CWHL-G>)PFKGI|_eRnyc#0wB*piN=Tu z87vjsp@IsKqnRMcfMbX%8>1dv-Dy4xe5|*@K>xu9K#OgC1^yC7fF@`P{#YCF;y1>= z%6Bxr24>BA)LLJUp9)2p3+i=%e$kiY0*X=9lA>ZOwv2GCf)Y|6U|%lVozPV11*69r z>q%)~2Qi$^DV78~r&Cu46O@Q??PCuaXEIT45Che?pcK@z-37>EfG}{#iX()Zb97dj zOW6%5%S!1B5@c%4liJj_M$->*^e0nDqV;r%;s*XUsMNkuPs)jP#ea(Xsi(!|$~%d> z4b{>N$0f!$zT{RftL&XSJ$l&lDkB(7lgqvLEt?8OkA`0^K*HWFpxrM|j8wgsy>A`f zb1-@qKE9&#GA9VTg?CTt%iRTQ-Ri+JsUM{+FRdoigJUg;+s0@QDJEWPNX{>Fk;>C@ zsvWrx2RZ+RcJiq6a^lP#&7Zi{pO4ea7o3Nj;-_!*Zu4i;f96;coITGnO5Xr@#uS0jDoWyrB$~)oTR2QpUon@LXR^ z9L&xZ)qHj~QS-gC79_TX&E$=-9R=5p#6zwUjf*hdJdY=^-HKki>J&$YV8m5(e9+xl z__McuLKC&>U1G(X7-aIe_qF?zk<6K!jz3zH%C1_aTz70XJnLzQ2@DF@Yo@CyG}$Mj z1URN4`QXr~3%TkmT{ZUEpni$)`>Mh#PtH5QOiv3^ef|8eRQ5Sb$^PjGfb3Fu%c0Kx zFK>fb)%8|K&jssueo9l_ish4FX%CJJMUMsRP;VwDfBs`(vv5pPhlW4meMr^LPweaV zYb#ry?}~2p#>mKe?y=ixi@H8J`Fziee(uk$>YV12tq%e7TohE1TOSF}6q*a*&U!oS zDLIzx`xB#n)d!%oJB?aZ`}lxSnuxRx6f^ka^<;%^fc8YQ-FmQ9clvx_#h^mnTY`Yk zG82dIOEj@(>=r(Gb|N6R&&*LMZB;u^yJ3^@9k^`E$rrx-jFDoxKRVu>Q?PeqEWju$jBxw6uQ(Y z@DgAP&BkeNbWaCaC$j1?$ik9U9l9mZ_(!HloeR2Gu^&G(^CuPC>wGa-DO9JU6)0SR zt``+BHmm&5J@32)tB_0W0wYsU3Q0$DE*LJ%^-m9Ye8DhThJw$1)OvrRZESJo0n+wO zw`ML?i4m>ZgOs=)a#>X?!SKw7YML0>vF^D08)rsWZYN6d`p8J@)iz9ku~~K-G->CuTnWhDuyQ-~ zNlxEhoU3V0S8HWrSY+2fzqcOxbfUVc)95n{)qCz8rIGvY1^<9Bi1KaEK22j~h=lYR z-G&69?y`j-(MBFAX5<*m$Y?>c+dMkk?HhI3gc!MBvm-BJ23;ZpaT%=UaewCAsC5@6 zgYy=J5}EPTR@ET~(-0h428Bi~qSBmhBg1{Vu-lBFa~+V;H_!iAxByWT)|_kAA%iN- zB88Jz1U3f}1j+J)&i+5q6gaL*RX)Vg7%ZfrD}Nn z(Objj0S7MOq5hR@B=X^U8y*hb9`Z+6?H5VOa+s zt7rI8wf$`Mw%|n2(XAVsJ(t0Lb3DW`=**7k&n~P6w?^?lA?(We==nj}2SDm4{?T;sht_3TFw!;|!i+i_;k1q$9=LHp%&@mvvjH z2h4?Qet57uk7BSmO5^4lPUIMc%MaTxP=(Cf#EmfIamW|}42MPvY-S8dZd^d`C@tVP zqyAn4Upg)84Uzx#VJ zx5`HcRJe~!{D&JHxE}_&jcst(ZuuVWncKL_r6fwB*M50mb@5w7nL;C|ReHi&d@ z6X5=0`g^HsH`?+Y)Q%?*@__Gt6m0h%`M^%_y6-3U-DuAFP!s!-J8vLvciy-R(A)e^ zoghyVOs24uJ>ax`{gkDyA3h?9p@(AUvEe`QGzykA+{S+=228lAw#M2jY9f03b>4H- zMA+(u=+wY!u}49!i2}ar@JA4Rscpfds|D>>+dcntzoWyxf8ZhBeg!$(cw`&DzVpV0 zf%^8lgWqc@;`hK`hr_selV0G5nOqWMCV;5x6Fe|N&}dRkCL_G<1}A;ejxVdgIgn;A zv>pAItp@Cr=s2G+rVb_Q1MoO1T`Phc2JHt2D*RINho03_(AMWO7#eL(j>#(G;JHR3 zQx%!k+{qD{spFAXx#R`T?kN(-oN{AOi}(A-C%u~Uz&Gt}@YacgaQ9dt&ii(E_e^la znY(}`0LXQ69BY|9RXcbA=uQd1P%{(>lEfXykXDI2HIDnS)gnRz0=gkNNyrbyN3$Ja zmch1IbBvOLIOFw`?LY###X!92$;{c+#=Vc;*+@B5u^i$O{_NX7&S`H(h#i%F-OU+8 z4A2GmhwWblgV1=Oy~K$M7Hv$N7H)Vv3Cc$!mM;JnbWeD3*U8D6)hCd6DY-bpK800i z+?;@S5NZRNjBE34siaIm27o(pL9y)(vQWzH(Z0z1tc6>NH!-9-R!63nl{p`8hF(Za zgMS9=i2rd+z#ude30pLEbFzn4Q^t|V*%`{UaIt``FMzD_jq$9)-I&h|edS%c-Ca7A z;2i-Z*aH8DUqthnGBY4HQ^Z7cGplrlP57<9oMiU1{DYpf>9?ej#St#rDkOxPVYe_! z`Pr1~fSBRzD+&22RT?(|y+fVh5o?bsW;GZGg`%}+QERamI;HslM;iF5<+o>2+!DkP zPjIPiF19BkLg9Ok7yR*yn`va~NIVrecUbiD4|#Lry(V;n-u4mS_xnn_2a3pUg3}r) zFpN-rg~vlJZ>UJxkgP|?p;20Jir|T?1xf%*syw!ShSjZhc(o^@Wj_#oH^6Dr&RmVZ zh78rmfh&5;Tm2o;;zTrA@@G`bzrN}kQclerEzTY7H6KZ&n3wa#Tsacy&XHd1+RNsm zurta%37_z-M#>x&=TaDb%p1scO8vMA=V`KxEKhjV*Dv_9t1q>Ef$?~PRBh( z7^IM@mAvJ?6Z$A$VZSG+N~Q@xyQ$qXrXc*pIMa4NgP~iUMesEWXheXTkpo*0tl)Tv z!1_y;^7}%6ih*QonAy-Uw!4ejENFw&EU#?uhAKi9ID69A$TR1yd1I=ud4b9%vk1D? zGRegtW2>Lf>A?{^{0fX#L{edj00AIAL!FZj%>&c*x3+1##yH>fo9{5?g4k){AB@ry#Rps6<=dd+}+(C|!` z#Y`Bw3`gFMh(6E!C?5$9Ywawy3IFD^0g>U6Vf2YvQ3j}j*7VwMFIj=ij^I5z3~}x@ z@eYC>4+=CxPB>)LOn@Kqwj&MZldG@-JU18Hv;k$pa4S>^Dq90P7!uqjTC6dNvl?9H|FSljGF>ChQ2xj~=;nX$PGHy_*^ zBxWuppl{p~9oTAR??VAta6e=SA!(6VytZE-EfN?5@S?GoNOKIipv)XzeF?8p;tl7Z23v)D#XSm(Me zQiPxv@+urr#Lx1DM*G0szZ^!9AKSayx_W}qGPOGA_rxT;X|9k{&;PTZW|bmNw9DWk zo}MFZvKdm}h-ue<0yj#a9hU|u)Qpk?d`IY{Aap;`Hg&&}bfNxjbX60(Fa#ktXC61< zX>_gf3Ect7VH3a+v&Mt1D^5^esmr46*oehoSZPWROb6~Bp9)uFE4Ga=1d=wwUY^eRo+PE2=k$5U(EQP-M+xRo&ssFCi0rg=7HC zfj+C`e#-r`5C5cO-Uh?m53>-XnYa1HK&XM}v(eBQ*0){m%Y<>`d2TPKXD8VA+>fij@JKpadEB1Pq*aP5)?r@)-7x6I2 z*pex{${H{z5WQIcuNs&(4j> zXD5QPGcuP( z7X-F-lmGmC{|(N8=C2I48FvI|E~OUGTyTUe4WFisxjyhL&@z!Uj9rhWkyiz=BWk*1 z=idh(PvpmEQ&eqMIThr8Wo&0~g)%BHC$sI&L&0RFPZ-YB?4If@8q&Ex`O6cPUS-eA ziFi2`C%t?`Zfr)}gT#ER$HG|iyoyd2NHNfyS~MZqIsePzE26Qg!!bjRZ{0w=AfM^j zPOu-uuo0DQ)gz2Fr)~ghZ^LXGzeDgkhBgXhl>^-cE07wUo2zI}TE&V#9|8m&q68vm z-0Y@cT60fg!-YP`Kkj$O4oJTm1uAQCH{9C!tdm>vMfU=t{4@T)`&I3DYs~BbF8p4w zp<~|HJ{Ddryx5(ED>eRrri#4@I#;!)8r{(xSVX=d`RMwPCZd_dls**7UR34l=f2X{ zJT$H}_8>>5i432POj-c#IM?TML)3&Kxp6@lirhfd}qNoZ09r@~-4WlCAHX-rmi& zsrun;Y{j{2er9^id257Nv*0;b9QU4BD?GMi9eC)YX%18lG^y}B1)jQhd<*gvnVd`= z{0Mw8cKzO8*S*<7Z$>~(F5YNr=N_P|&H;GFz*d?ERPXixOg6x@^&tQiL7%EN+1d4r zG~b!)8l-B63P`<)SK0tSuG6>*^Q#L`-8lDQu(eu{2SBPvX9z?6Y_KTyy*hf{o2k*} zb*a<4lM${u1l*Gwb10@Ia(6I%R3jqfkPuO?^t&InIb(u8&Gq`41-70dAXlrKmS<`L ze2vwc`K)XP59~t2DIEmHsDfG1i2)c0;sz49TqQiXE}sDgth$L-sGa?xu?k}@NtdnF z>VfGv9k!~qr-NZeC>C4An+PAqF zvQ*fBG+s31Wl#o70w`UBe%a~`(2QV2Xnq=*)kBJECk>s{a83PEM&52cvazMs=R!U9 zvG-OG@>yfGx_>&}-!9Fn>eGR@#Vvm!NM6qbjng|t3l5(;JwXsJ14srf{RAQwsWHvg znSwiZ{mBo%Acw%!%AqDJoY-vFJ1 znO@dSW|@(!3z~LlqIUXr zkTEv->~!#ppZ`g(>936l>>5He8KTgKD6PR$_7{v>1C(@t!07FiznNC4!CL09uhR%v zKFr2hXm$5jIgn!FE;5>)wMsv#2QHrWffgs|GpjFdET7iZ*onO*f>q0r-c}Vb7Mlrp z9z*oG3%S1DqL#75Wi`7g^vUc6`%VWe=8UVpc4|CU=l~1DskW66!3*q!n0$O9q$Kvm zeA18$9nAMYqdfqLtf0$L4lq7C?I@p^=mIq@XHs2DD07GJ?q-Czj)oSy{JB6&0Ndu+ z_1CtsXE~>cJ|z`IVa}Z-RA09xZ?7pmDtL5=DDxF(%vZhpL4+sbEhFF%{a`z5p2n!E z5*Qk+N0w5f;Vj5^EcAa0jgC#>B31)YoQxm?g0=@6(_4iG$2zug45PDWFqV1r1)E8}F~R!_ zq<)$TC(`#KmZt^|ECk|1f!eS0|XbwS0_hNZshzG`~P!n=-Uuda3ePK`v_z| z^Is9t`2+m1fAAupW8X&~`wqDFcc9o0Ught@#5Tf0SAT$n_PPJ^)0l!nvN#Zi4Kq#o zgTJ(m%tOD0naYPE{ij~l`UgQAAPl%TtuubCe3OYJht-rxz_9*A$!bxb4olHjavtAzw*O=-}XQJ)b1Q0+w27)Ycnby$}o`19OjA+xJYF5 zn?1rRXK&R4MXKUlMqvlh+Z8Afn0oYr%94wbw;NXuqrNY3c-a8(F7)wUYA+tTu$_>$ z0x5-f9pUUpyDeB2SiU6;`dqdf!=GeIJj)h)(%U|=By#^G`sV*VgjuR1d0dkANn&j% z)g-~MeC<2+udvV=O}u7?L3HFMC0H_jfnCco@I%FB3)EAS1Pvnpija)RT1@PXk(tKK zwT%Q5KFdHGnh8cTjm-&fDTIxZaR&OCzlcF{;snlEzXquYYh0BGB+EZEZfW$y2wrpa z>AWra`C4s=a1`h=k?^9m$kF*|DnNRej2j*Uje^Sn2_k5lnSzkz*)1VYMk0S|oK9%7 zn_ke)gT#SibO}M+rf1yuzcKAmJ791tR z)slGGp-AA1YQ-;{+qMR_3|?)F6W$@0NQC2Bvh@BNXBew!G4dZre&MfA?>Q-?b4Nsf(@vB~h{ z(^ryre7rFBV9oY-ExXay(7l{KoJNSp1K_u*F!WNh=?ex%Z_0OVMF< zO1R^PBOv2^K!QpR8H=VhMgb%Vwo|YNw(BN$ZO6yeEc_`yLu;*OhWhaPqTjVnspq)ZJGHE1@Ffwn}jcHrq8kD!=?Ac$*^{?Doa!!_`uP<5yZ`Eu55?f-E7Hv%+HES*t@fgd^ovdF6HwIhkMJU>NLs!lVuvQ zS-L%%*d8sC=6}N566MFQpWhK*6;?$aC5)XX_XXO~ucxiTfkgH~rQQob70B|*uxy=$ zTs?2dpkps=hJ0i9WWStiqUMel7f*yfhgnIuI%U=2y{IOfNwt_jFMK%oIzzO0C|kUe z&8B-Njgt8ENb!r~Gm4a~yE6RYu|h*FB$s-JuyBShE*HI62{XUTS(i%2l~-ou?E zzj)ItQ0RdG&{br)=IjH{J(7r5X^NT2TC=a_bDs$WTb&HhTd_@gLur6bCL>MkrmPAt z-Xd#7R?Pux9RbALEz*eeVp~F#9dVw5vBznVY!ybJM8+S?y|&xpFQ(?>f3%sQImi^| zWr8+~Edd8jo277}Hif8vw4Jf&KuuIy?`=k~?St(pvuepmzb72fCfUuk9Bu?u_4>Sb*Y)20e}C3mcD%1JLDK7MnUa zogLf0afMe^e{jO65dD^^y)Omm9lbifr3`oL3D7`*ihYn7Sz=ZtZmb!_a)K=@(~M__vz44ILS+H^GVve+i`$hGA!#pB(Z zrp$8AH@wbuuTnCdvb*V7aY&EbTwBV{p~Pr8o@@EB<(G3cE0p@QAnau!V0D}voo~a$ z-OTKS`9priC3KpVE#pmL2Gmqvjaih;o?iY2{nE+hl#;dfg{Wjz4i|^d|HhALqu>Lk zcNHBqNZA=?nVE5d!gj6vGQ%yyus#NIOQ-vKqQ$)71(Ntvqg6OjSx(YMNN(@kgi%h? z#A4bUV~iDVKrscTcDqg&JC}gd97fb>XR>m5F$h^0y?AcQS{K-P3oiGbgZ=4GP*;-GV zM%6NkywMUv86%Ip5IRD_53G*TuW^LJ{Jr%Xzh%_snV0;~+6WmakQVYpSZR?2)$0B0de zxVidRi>s+ce@AqDa(jeoBSQqP_1``kh8@d5DSO560+a$rNZ$}4D#bUXua}!{dnFfz z_z8#?YeJuvwCCHgtvC~L2$Lo@uiTHwc%Ti^{N}PnJTMX8!?X}Kzpj?SB}!(AQavpz zFj$Vi^?p{j4#tX%uw;h3nH}_DkLE35lnCGGFIn-YLj#gHDgniipG};s!^xq{+pUR! zZL3+aHo$)TUY+X>?G$q?#jy5ugQ4A;gO(emwi&goYaiZS0zuB7%vux>|CQE2jJ7%+(ZPS& z`>79mos$#gPr9EG%gKTCesi1Cxe#tO@AG%h`;)t}-FHWw33n-JT*#Qph5hL-MZ^Z& z@6_%I$7e%Xo{iQyzTH_lOU%jMs27F3>ZvjEc&;v+iX zNO5cys-kO^-C9Fknn`ay!LL#MlOYwozY$|XkB&Q_%GiiQ|ZvSf5_kKblM+rzC70d#@#Rz!@GD1(AHai z5MEY#tnxx7`TC*6Zdsk_4;@-30pK^B%aQZ-!xt+3vvcFM*$5ux{_t3!n#Gq6ThaQ7 z@tfy^ZR4VPdF53<+0uxba(?SOe|0iRJojUjS*27)KulwGNqp5)+sKmCP+sVfQ}ehd zwui-sN!NTK%PNx|r{~#rFIZgk{lIdlQd#LH7u|_0c;*j=?h=i^Xgx3jx$$ys=3W98 zYYS~(%vE@n>TG=*Y)QL%;9qDwaRAcdvM>DIlU0rAo-Nwd#+VHHuW{ll7ak=bjVtQU zahdyo76;#O?PBAwzUWwMzIUay!J8ZbyWdxSi#pio7@($;sDz?HA9@tFaTai-4zhT>rF3Nc3l+tIaHro%hM) zCxXYbsqX5%e|*KP|3z@k8(sj7=`_gmw>WcYVW;DeI87s*nmBmozN8+WeLW!o-&cc7 zRNot9)wv4qUaYS2b2;>3a{gfuSnKaYRXr4vCGD>g9Y_7-1{Ms&Ry}a<>7W@BT&ww8 z`?w8Y-R_mZTmSgV#AAiCr-EVVlV`i_WcJIW?Yl2li6f6!cRV&hI=*9Gc6tKpU~cRq zRG}MNxgC&|A7V9Fg!uS$aL3)<tem-wcDTcXtKc z#~ohvePR7v2jur^`JV=P`Cc0FG(qGvg^py^TG3kne=54$7b`Xq%=f{I`nQ2qox4a~ zb87)OG4WRP>|R=M5sWTy*D@I$tpS+)^xp6erxA><_X8D{3;vnK+;_i&Upr3;^=m2;qx>-#IjI4>wmFwBtskhi4*`G0-6X>|4-0_z4LnY}eS0;7WoV+NwBndI~Y z__vPG-cvk3IlJ8S>reYylrC}OLbJN61^iKe_)jm*JbK!%TCZe(3f#@-t0c8#7KU^x zz==Ab>IM$IH3Ph7;>QDqELgg`n?`^3S-a{6*7NfPmf$4->X~l!^NugR5LyN@WXca% zDjTz^jiUjZG?>JC%J4!I>{h>6Vf4DFqJ)v)9-b3&FcXT?L2<4LqBu&DBlc%weW*3F zT(z^Zb;pb>+hgG_U!y|K2Z`mFD2=o;D5l+aw(^|Im2y4MN^x;d%{`g-$<7(36 zlz9uQ3v%W8N#Jbrm7r}2UiQvHOuoU?`~r$aAlYNH%`!z}A}zg-1+nAgZVjSL+{GFV z%TFSAq&6fa=}U4ZfmeFoEjTN;?;R;qFeI_J{_f-~ELj2p5p)qT%wcrLZx_n#m93s1 z-GTA)PjLseh`VZKf~<*|$uumPr?=`=8Z4oGkh6ZkX$z?~l0Bb4pIi0ENYy#k_Dw{} zjp7w(Sn`%b25m5E=kR@@WUJFbK0O~?fG`Ymvy5{&7Ff@On?nDV;Dv5a(N4}f#-lrW zUMV1#C(84kxjTLvJxT;bq?hY6!D`@@R)W@KFm_XEWukZ>2*%*iKuMj9SKoQZO)gAd z26(0LOz>m@&pzm>Xw1iMsM=(hd6T`ue&L+3mvE-CK1N~H&cB@4`qjf8gpVOe1==4V zp)hvCPJ&ttIc~3Za$a`qC_om@P_Q&R4ytCnSu374bD4Yg7X=b1^A-kxHWg}|NO$iXJMfhrR8CkX5~dwmMvne+2#%z>Ua29 z8LxmHuxhbc17MU*H8|}A*KQgwe2BLy(BKxZmcunqzf+&kNq19{(_;2+J8I;Aiim8m zKi(Y#6J+zyEPQiR`DUb#62>SY5D%^4Ed8(l{s;0I-aH7x zzL8$>A59AVUS{b(E(H6o|7w2f4~fA3x!UHBhf^2Aphn`B;6k`-Q9rp!o_2-Gf z`*86>C@xKe5=_aD;C}>$u{JjN9aZ2^z@p%>76!)Bp*B`EFSY`foBm}%hcLKmrij-* z9&y$W4=2b|_9W54hxiJMa74$lL+!`HThrvv=C$v^0|lc&q`?D4^j(h)H{tCUv}66F zAMbhKr?)AgZWc!(*lL~W5!c@4Q9wf49lNT@hcU(yg00$ z>UqWYO^VZg@YKBM2_WL}>ZzK_pr7Ff9Sh&@WMiakTqLhxTYQ?7KB?F%rqD=@?B_n0 z!hO1#XaI)(Q38+5t^lEdY0*V9TaZYJBKsRGeP z!FVRlT)j`QJ{id zM;9~Sch0$nlh(ON{MMb{G(shgk7fCEq#qKJ6u|^(q@-oA^I#oHg+;put4C(O&_(O~ z1ureu9MUhH#S!%2kgHz#keF8_LyD$$1l7jMmkJPVyjY%c6`Y%z9Y&-6O;MG+>cl3? zU2UL3V3_S;Pm$7Ws!g#8YdPzUFPT!x&ej6I7FZD<`-uaN92lXC&oda$Z0rz1W)ECT!|~XdTCy$RVofh zP$$j|G#aW8zB$K(WyA5Ihg0rMSyS!X!)Wb&*Y0`E*zP_eS}=}=;yESz!q^Vy7;|2` z@wknAze$q<&RGr-*UTPkX!j83vFL^cAQ9Sl=wJ^FQX^0O{%$kW`Z#m6pPRZ=`hZTz zfuViOg~$k~MqL65f@CpHx<)2u^3H@iB~~(nz8br-J_Jdn{Ws2xBvwX?j?)o~z8Uq5_ z(1!`l;>{GkA)AB4RLv<0e!Q5@re4LatU5t(E%em$@Bgtim)P+lWYK%4dcBN1>vCGP zt=(Ja@r%+iJ2d_>d7UE|B1!So&X7ya$Eg)yL?p=y#TAZX${u+4v7l;=TYX$(aUuc? z&AT7-<_`C(-GWN!!(57^4vZYh(Lyuud5Yw=)m!CiFAX&;V^of zo+E1oyMLdmeDQhPCsdo6mVzXSg`7c{JDG*_6lI`H8M*JIEoBx0BUy26k}HP7IOcG? zo{KHNKUz4fsnqO&cII#AwnUe^Hnlkvj582EiW%bP_mE3KnbH$XEJ-MGQ$o5;vD-W- zDsTPzpBix=Y{!<_B!>e;kShy{AmoXzMJiE>uYh2%mbZtTOK%41f}_Kc9WC4JsKA&6 z6M0ILS0O;8(g>W`W|0GJI@`Uez@JB|L@!h1CV+@uJDddqC18Q{crob%P!SNjZu=t} zxD~X}IKz5(rQ@9pOO`NF7SpY5Ko((40Uh#7NM2$;CgAqCUTtw=YeK_(BE+el-enj*##rM^JcP!3RhgF5_hA3$b4xQTdSl9S z3L@!iGt0nE!%)N)>dVL<&WzoeIRK}K1is`N`4LW0f#oR`_vXUi#z|Ya$y^GMWoPn? z(8rTS&OB|_5|}txvytDwCu3N}nS3LpE94T$!e*Y*c81~We|hV;N7jc{Aq9d4fl^4Q z<;15Tqtq3Enrt$y^c-QKL8@;Yxqs8B;B*HB5bZ&A8yLmZkz&^MF!K$4f<3^?XIC{| z30w|YdS3TEL#fi2CW8pc#WuoxLi{gtqIg$wbj24Lvlf&cqckxdwXP)D32%4dt$Tkq z)GC;v<83O~8b&EIOD1xO7G-pGPXIcZH(LXiT=8bksdHtin0rYMer5WIYrJVnM;(pt zaJM_2q)#0iG9|N$_T_cQ>u1ViziaIXjcbuxx?UiQwi3QW>oNb3AR3*q$_zuRZ!wru zsbJ$VREYd>S8>Aa*OM^6ITN840E_sqBup-eoRJlK{$ z_cu1}V(O&GXgII3^dw)_GmMF9R1r=?giYOsmWenS+a2VKdyy;BER$Le5p^9{-1*!G zM8err-hS5P4tk&3ASpA;s$`asiEAI+4{_*L*dlt5l^VHZXJ9chm`vA=U53@0^`y$` zklu|mXm2puMkv*8F3W42F&y_mfXQr4qqr2?h|O;;Y@D9qK^SZR!6c_5){&3=r1*>< z>XA%g5pWL{B?Je~MRc=~2;lCw7fW4DnM+7|sKU(XF|8r2rVH*tfglN^yeah1#6D>a zEJlD`NXsjkHYH0zk1L|jSPFaWcR!OGr%Xq&w_Dgf_NJFppU@2h`)JMmQf79fw0lH= zNw}qgZxYmPG(|65#aQxc`ywSD@yCTX(n!>6Nh8Q)$E_6hcw2tcDOb#!#Tf!_NZQ-H z()-N()C10*WPgMXFCRXW|Mz=#6t{W(c;sR4q+2Cqe5p`#M~3=Yzc!OTYc6LQ6s%+J z^3>~OIj=cydEu0E>V1#@xAw;!N{*8Anm&+Ncx37c@6QW+?#E8t>3SsMDN=V&$Hw54 zjHGUoG;Xc#2TXR|dy)kXx(Il`~$A zliv8ZfvuvQiX+RoPOf^j{ebtbRsTJWO)y38ea3rZWJ@_LTqbixr*UjoQiQp>48L)Z z37Ld{zudm>ohuoX_{M(y>X;VYvvE2Ft%&TBT2ns&BJ zl)x{yED+uLiNis;hudpGK&_ojGC(%x`KQEJl>_#2?iugJ=FF@9V} zph8$3{aSbCk{EvDq}QPY%1n3t>0puC2TDT~8tojr{;LE~akqIITOhn-YcL0_;@Q*}T-s-Sc>lW-1Pz^0W_Q(+}# zHRd=cBC+>O7i)=|4MVD<(hQKu9XFj09=rX2*R@H0`S*X)*_wk)tE1={Hu~OgnLO3q z)%gZ5A;;Vjt;c2g0GSSHWCL(AVszoz60NI)=7ZCPshQ9EPSqx|yv)enXsD%8Futsd zXlS^is++h@lzE<(aXlTdt(&OpoN)eJAg+1koq%X}%!_L0!T8YVdLd%3sn%VIb)L*9Yl?8Gl` z7vBPSPC6>y7$x@AuuKVQTBEP4tNuWRW$HfbQ};(-!s%x;psI*xL+>M+f)5|6vw($yUz<9n_2(KR-KbV!Rl8J$1#Mw;- zA=422V6w9L5q|Es*ioy$7BEQN?3b7f=zqspPQx>Sv1)WKZYfjSjrt|^owxYMyk>K2 z&pSR%Q{7E1#)85(2XGRwo{;lgHKX6vlL?!M@SLuI+JGq^NODRneCr7LmzL&z18|Qu zvvYKc=S3E)b4C96)tv5NTSykq@sA(Z3Jr` zX~Zn)0?eSHMx5U?{Atx!}t#ysBWQ5T5WkAiA z>;L)-@qr4K1ECq1Jiv`?;2*S|yuGH_#u=R0^0Lr~7b(5K-Y{zChiwPwPGf(h>jJvd zm9)rPITvaak#brsad{8=-`mWZrIAvsdD?&+#ETC;L3NbN+Dj=NqDTQ}c-NMS|Nnt| z-(P0rha-ePB&XpIC8h3a->99kf$qIWzFqU=hbC%#yXeXJaFD3+J@Py8=QmO;zA3)1 zl*``(6DE5GwNn84HsZ#UJ=cHlMOF+-MnB}nukSn`ygV?AZ@iIVlIt0?F+sIyi2p-z zTziVDKsXMN%k}3<$UTp1@BXCz+~C2KV;$=63?4Tw8E<^>#*5$g3+53k`NoSSi*Fm( z?t5@e!5^9uIVptf#Y0t(N*C0m18b85+YxgYztkl+;jp`93kBiA4k?;OPLAZg+T}LU zr&pn##S^aT0c;3y%#~-HY?W|EGuxH*mYx_v#y*ri^@PVeeP>(ITYA884`)Jj?Bdtc zp35<}j4u*AEtfUJE>qc3&y&65JEc=Aj5IpW-}_ULu5ngi0H`x$Btn6d1V1}PTNjv& zZPAfihMGNgochVEsd0d6F3eUvjBpk#Op$E40Itz@`{+e)KX8)vBs0*v1WgiE1CyIB zn!T2}j3)`f*glRUPDcIQB|;}CQg_J}fa=db`4eSZ^{E9U$$u)z9G`mqXL0f*fskAZ zsES!QDExXLU(?}FWxV{&bs&vSHYeC}DHEZFs_y6thZX0CZ#q4AIbFQsJP3jtne z?Dk#Y5oTA&CK^E|Ru627#Bd-L8T1?GA{ zY-w(gkv}Br7yQqNaH>Et&t7NnD*K+o-py1mWUFqYw`4y~n|LNnv2XHTsjvs9tSB{d zATmL_J$HnP4wMdct6j6ID+XuYUFUE5QbF!?Zx-@qQEu!3#li!awth*Id#KK%3mcMu z&89nkD4`MtWB`3R61C|A!4%efJ?))!QqSFNXkQ29l5kjlS^yBeo^hNMRHjB-y@Nh> zS0c$g^;IwLJ>((A&{{}y$JVxshUg5ajE=+Rpc|&dZPUWB^Oo#&m=uwhFOLD99Gag3 z1D*-Pcs4?203E9rih27!zlzTdo{$t}LVUF@AMS>1g_qoZKNQ5Gr6e)LU#wq{{HFW5K7lz_~=6=$X#oAn&vDEsGb4lEZP)brif}Sny@cMxQMV;7fR@~ZK&;3zs zAs+5#CTODy0-|jDhzxEfi!G*bsSHsPnL|cvqJg#g@OYiLWVRa#!j8`Zk*%tc{7g-J zsn9KSO+JJ7sidJXZam$hhLTzZ8=&TPm-4zw{qnyTU>+rnDqx56`D%{M3G_j)Y%_i- zHGS@i|0=1~2SjM1AF*!5K?qqm#K7e(?K10@>9&HE2(Ud3ufX0gSS3UYs^byz7dhA_ ze|+CNB;A2N8_q<=_Tl>23l*q?1&|)UoWm^;a$AUB5A)V$J=hF%oQ`0f89j&mu!6|V zJk~B$K2V6O+)h!Ej<&N}#tU;C{G~V(tPJ9yvwlnq6n93Cfa*N{=N4d044?2&FARZ8_y*Eq!8J*^nHrXGqijLl9W*%y#|-Fdni+vQLXMAk1q?AQ+9 z1^?A_D{vBTB-i0hLq_n%Zue@*AAUYp>K4AQ)pd!5jWyS))TY;e(xaey$A zFmJJptbWu8#a8@T*vRmx(ji}?40=5Dy$$q`elYsH=s=w+pf#i?1ZaUH7X>W z(0e~>oxk(P6)Lw4fWr;W#6^IMvZVoA5r$RA4z*k zFy;;6K6|szlMI;!tJ1z6uf=xNGLDaU`LO38v_hXJIE%piyL$s|N1#Ur zq;E&WnH%w&-B0lahs+R&Lw=`=`z}W_6ZB4B3Biy_fDq$Nd7C&nK&CjOz+==Ylo%Y{ z2K`U}EctK{!y>sfI2aL%hU}s#5ql#m znY#;i$%*g}S~DRH*U*}V)LDDTu3ZoET1^=7J}yc>@aPazGz)7F8+On&UPd~lXgag%@i%$e(VL3?)CANuUm+XK+@aK%@<$ z*;ia9q$$WAOGX=8+>i(I!N}-gL$ey_;+}4Ax@hJphBKAeFdg5x^sjU~jf~v_3^b9t z9<->_pR&yb5*zJ>%JcOW#^pi64W=H;3|oN@>8=d!gs>vpt6DY%Vg8a$k_&+&GDh?) zYMB$IWBVW`af z$k&r6+|J8~vL0-1$m_1W=%E#BnMo36O3*!_K`JN%DI(lkdNo_|E9&>c-sF3|X7b0s z^Ap9LZuw(w^04crd+u<@=Y?NAa0k@iEo{Elt-ewEQ1$lSiMUUm545x}%$ z!n-2F-dVV`^Yi8DJKf=AxG~<@R1X!qpl&UuOP&yR;4>y|uLIfM^PYZD6;8N&QB&D{ zeodTmJcgo}1I^EV%O z$$`0dwfspZ+y(zoI{T-OEbj+hTfgVCeikm+^{#ZXy_|sf386J24(w4o1aUe!)2*E= zJhz2-+3}f*Pb@3zrQ`i08Rhy-Q0e!3!~_ct(vQKyT;NczWrA} z4R_Ak0?`gMr%R1Okp!f-yA*C6(ADh6&j?mchoo!k#deSKutFFztURd_5=Gh#Zk42BwI+sK(RR?MVq=(4g2PhbDcz%_2htY>77=T6^O42zC znF!O^)uWBWTcP-AS|DV=*%lB2vETJ?RL?tRRi1EwWi+Hy9eTwt%yO9GS>)hz+da1F z%h5~#rXnG!!Dof`C)G@soqzvI+3w7K7W0rO)PyE+fQBZ9siw6Ho_g1KuE;2QRR?_p zVl-%*r0W`Hu?N_macSmKFx)l=ssF}S?lF#n&jWoeC{r{c+*NHt*zNG_eiYQ^S2D5L zar|ez`HasQ*BRe%%Ger= z6sn0{pf4ra8Sz7^%Tzg*Ym>;Gy!Nxlj6C3Ir$PCQZ}^@Ok{pp4Vwg0VcCPH&s|LVj z(=VC+!82uze&v84zah4o)sYDYP>O0UGM;T4)%~BPdN6>I#$R}V8tPxjG?@cOMi`$h zju=Q;Cx@rN7R6ewf{>Axlj^{^XWW@?a0lsM!<8Kj+_e|)2PnLZ-AK=3=Oxl6LZ|~A z0^aq8In{BPxGMVvC%+mc1ZzG{Hxf;(s`vGmLN8~x|H;**_A6Z8vh#hO>s*Bn0Pz!OhyP!ANt4}xPe$Z}R9JtIODuNFK}4NWA3FmJ;M4hm!V)y%y1(tArL;#zY^Bgam)bJSuu z;depQvpc7{M(3Wf7K zaT%x&rhc~US;yRR4peVDpmNKUqdUBwI|**u^y=MFbfwYKX)d(@3(4(l6?ZHl4DmsI z^!|W%QPGi^q&45;7!Zt7Cm507VtqoqDJX+ObrB!7gD@Nfs+#!P!EV?BYqK~Zb>u>} zRY!bhqiR0uY>H1ks@HLU!O|%j;k{MJcF0lHe9XZ_9d&;h-W%#(EnwH^LlWE2pc=Ul z<4rnF91E1M7#lz&zRrLRm+8@nJ+-1eJdKF`^Ur)2BKH2D33s)1;gR>q??tnIMCQS_ zVW_uj?|wfD^?C8VmwCH_?+*vXZh%?8aRY{;F_pKzs}AtFx6>fLeU%S=PwkS8wtN@) z?jMKGJ+@KXctF1UkL%IkD&GOb${T>#o;}xpX={n~jmhcMOblDWF&#s#HI-ha1EW-H zSh?{cuc^T^{iBp2dVcoye6X+$5C(_gk_#I^HF*AjY3bA(uAtRtI(_D-L+&(Coy zq0kqM2Z*JIn9EH z2cQy@nC{x8t%oy!mZH7pX0XUd&gWTYAk>bipw(>FaL(~Oj4@-CHNgMB)w zrP{};9J9rwu?!)ufbW{nFq$5{_g}uAzCvd}YX%cy;bS!8SpZzh7W$X}PRT(-xj@h8 zM7>a+nDha}!1;9Xt`$%i%#dO6k=SD&Ks?y(*xd#hTxI94HKI^EoqBXd;>5%FQlHjM&AmXK{ZO6^Cw#ImatuX1^3f%}jey~@MbrKx`{vJM;nTs(V04y@U9L2|0nx%r)c4#?Qon|lz zXp==!J|8o0yMFS-XJ?`*Qre?v*X-u}$#Ph|ZAQE_1ZLS@xS?GyI*?R519H6oiz#1B zAjo+KC)BEbIF@V#S}R5h``A@xS5gA5u;dRBl~#i8Riu7M%WX}5e-!RT`llk=crYHq z@8j;plq@ztAf$qtckAk0Vxl7y2XO1(x9Yohyze@bB_{{Kw$1sY?RIhQtJw_Z3=5+) zcM>a+b!M9PNAtC=4`Zr2_6gl5C01&TE+55!iOYNZn-da<6z7*ax*VU6%Xiyi6QCp> zPSk7og=eld21)BCKr(Q+$>D{_>36raJ7RSsp19i3>D-eE#I@ytcI@xj5W}L?*q2f)D6@G0Zm>v&uKoD2q=_p?Bm+=_u?L-1b$HhvDua zDwWHDpn<96oC{gS+=^eo#iL2!4))^hAAS!e@xu_cit!w$9>4|HF`4*Lc52i0v%u@K z9G@jN*@I=0)X0}A6PFd`>3wk8oXbLNZQ15)WF$gmWN5fym9Lt; zn4WB~iGpo_xfgIifJ_sMs@TlbkfYIo90|dR@uxk#5G5RfE&C7e;XhtutWmyq=10+~ z68?s8`_2V6$S@t|4=j!#YL_CkosMLU>ocPAi{O9E2}X|4PL>jntslicO0W}Lc3#4I zc`gf&Ju;8-r7JW~8j_7MldN`<*Fl9nMdO^1{YDV|j-R-pQ>cz`?vvzcD`LwbddTFll z3041{81j(`S~b&m8#lJII|!<6&fZjxk1azqF;Q~wxLK&}i&NIiLSv(MEJe@j)lRt0 zVVOBObeWV!D|6uWI%rq8a0WxO?&EqZL(w^{qqA{21iRUnJf;8R3r`p4_H>YKH9nCt zkhr*FbG%{rI-eFtvKo%1!R8Dq)~Ps};FngTpSsp#!)I$JRWC#l*PgeE8 z32^sA{$We9+*^}(eK~9{2pMcCa7JvMoqw#v)=4OUq^lA{D|iX*dijSO_VPf++$MEJ zUcP1r9^1LuE0Hm8_^hC3FCks8{Jw|~oq%Id$;J`{Cs3R&{da$qQ5los36tc?2KdlF zS&OHz-Bo(p!MbqO!Zt+uo89>HahWQ%zZvUY(bebl9-)WTA2^r%{`)6~r87TzsiS%~ zfn$-2@4WuQ+FHB4IS%0!%F$pKr4ufcmp&9FZ@zcWm%zq?dU@}Uf*ARpldIZh-AY@q8Bsu-DVikN9#maYLE`&Ut#w*1j+3{attt*koCMa52DS%Nz!wi{H zNDK-#O+$bE5GO+#?gre$}U$g zhecR8TOfZ`3f3ltZK|S-2QYZl}6d{MdS-@fNf^<#7# z0*}{GS$Tv#tAzu45+trPx;?S09s(SegQkXIciTwP8wG4i(GtiE*P|F?ISR-w54VZp zRB1K!dvhIRl-&YVS;}X9Lh3} zfO)*FT_b2hjARQ)4X`oi#|_DaII^99jmgwxpt~^P`cj zt$_883y^eo{nsNko9;t91GOs(3WzY?39^UF+~!~TVSJG23Y&=#{21_DUk1ec)JNWw zg)XOmwK~8w+Uq^SN(9Bex>f*qv?B2;yhoWv^oFS?C|0jL>7T_@5`_<`D^Kz+t-Ypn z^u@J}Qc755O8bYgAZ4xQ&Co_ToC;sjeq{inEN~|6*(hZj`^SBO==SzYXJ#+*$ctzx z9%|C|wO=oy4T7ScO)$V)hFDdU*u7!DK3W;9u{;)r-L_R?Rbv7u-TYsoN!aq(Fgy(a z?8@)3Ap`dv&_m@C3dfV{G&B;LkJSRv7&%n-*3M0vI z;Ia0yF#gx6pksna?Ud!+Bf+4r;Z^}eJ=lBK)OU~Ld=b@>(!PI1H0Y~J>EeC4`oo{y z%JUDtOc;AjiI8{x?LSBJ`b(Pft(VIBzJe|G7nJq=i|_K9Xwc2{t^amxMbuu=Jkgo> zA}_u3?ZvNbJUcHm!WisAB&bfJ?Bd2qQoUQlXdv<|ev0_KMmf1SVXY-` zHx!e|!lkficoa7AXTSYh-v`f%(CTHal45!8rVBAiYe-=N-@xQFgJPiD9{RuSgL{z_ zs2tCX2(zrU0;?#XCff1o=ImpauGEMKBZZ-L;?oeJVwNU_zUMlZ)6ygH&~T`s!yXY2 zq=V>TyZT~MUQ>7xNcywTs678mcVcM)ZWSY#pcoQn322E($YjnzEGuD&qm(byyy8rV zIf25@iPpNQNIZq**v$c_#z~7wqWex#n3uy<0t<>)9|O}OYty8kgCROfc*&uE1usv-osXC-6dQ#$ zi1Ei9v>a$`3*7U?8LM34ZSb4CBTwU$mM00)u&sW5=k6x8*bMAI#=)1^CSON zT0RBtAdh9TG{hX1$MgX$^1JOc!&5+WukJ-eeOv#K&%0Bl7Y=+r3zYHzNKVw?rBJOG zG%zmUWA?mueKY~wkXEgg(C$->%>XLohCm%%4X;gH{>FeR42xu*vZT7hCNt1%B?+K# z_8QD7$_o!&#UD!S8DJXOtDQlWH~V782Km}LOe!@gHh{=ZyeU1oIdSj5isE;xE8 z|5yQ;WqbUN2bM+iy)F($>}yV7V-6p_;t;HjP(_FnqT`A+_@UgI&AMQ3#Mwuh0n5HF zd$Ei?Fq#7?G@(2Sbe}}$oYp+9TRIqfKmL2{uKXe2UHL9A!&a?!HZ9mEhwEq+LNIEn@)Vy>b+I-fCuDy7 z6raqqC6N1qTlUGLpr-{2G_)k5brtJ_8&czpn+^H3WMsQvrF4gJhz8Q;5r6xaACMyt zgng9A=G~Fmno|f)!upSzopTSJZgrN?0k|s+9nmlj)5;?l zGxduXF(iQ=xpM|uU4&*%XC76?IhYVh)U8de%(^G;8#`O3KO;shNpfn~kp_ekRZ6Aw zmGJ~G(Hk2cPROGI{8w~bi%Ey8q$`pBm@lHlJgUr2i5en@l(R)h=AL?w)wq3zLmFWm zAgMPLWtCGBWdVk2xP8M!c2au-4?o|1lQD(YTYW9hG;WBH$5F(9fq-)jnIni!ohqB7 z5p_<=iBQ;0$ULg}YF|uvwsMkk!fI4rQYS#jb`F}lWWjF=93QP&O-U9C$e>Jcc#d&! z3t)lxwUvCXi?wLGbBnhxCPpD_(ji__QQEng zL6K*oFu^90OK}zw1KY^rF|C`kM@e%*QZ;< z(q+zQQQ*iOg0fQhoG*rj#^;LsQTtdop>vmAY0dhc?ppt&4*>ho3q}w5GYHtOAwL!d zG8gzjitp*;NW!yd&exdvf#Dv2wMZcU5G~`feZ)zlYXi|S<6`K(qLbsYqwy>rFolBt zz>mHOc&A1N1(u<}XiOSt&Q3nw<~k6YP!=SOm(S)e;llF+DzHC1qXGBu)gbwsg*SmG zEOn@x_!ckV=JL8YTG5q6KR4Td_9HASrf}-mb|AM%7&@IH;G{K~$?`|{Rvvg}ZUPkG zp?6eecG4?ejEuK;wkGSn+_=-C)8R%z`*%KmmtrW&ABrYewPrtp@Ql-2KY~tgh!s+$ zu<2v&+^0t>+Ix7yO15Q#*=JdiYzsUHOVF|X7;Y(fHzXD9 z5ufZ(WL*A7-{%doxdy^*V{^$PT8@F0C5WUs=J>Rb^{sS0%$<^WoOslQvKXc*0~c~v zNXP3w()BPda^5}}J$&mCXvD1ukJ}Ff>S-DT#%}@)374gXe5&s}0^5d?$&}VZt*IbrNP&~4Dd}^rcnx`oTIsIl4ZH-d`%8ANm|=K z6))^@u9F&jqZ$kpl!fN}N)L0Kybc9(*isB`RVR&$Nn~MCG&;WHLFPJ3pCGhyi|>x3f@{48HquQYs3 zNaFgHllR0^GEnlI9%BIC(<1s+OqJ@z2UXo zNtaXDb1)UiRnqmzefWUn+IquzppdNN&# zf?s_9M+_-9K@nLrJlVvmNnb{qi1jZpxs+$c<2kT+-&_pDbY@2xj|UooyNIL%HEL%G)!vU5G2qZmDDVrOto1@MXM z<;P0VQv6s6y;iwlo%AK7BcPN~6i7!zI1i3*CX=(%I52LF>(G5k;HVskQ9?vOgkOUY zBjOnbY}83{Y&(u2T$2)(jUvfXHEVPNQyMpcZ;F&2quiMUm*dik!%smyTPZFqBNE&w zNK*v4&_OWBai$*PMdPD!aBEZ_c`zYC7uDm)Pr7wt#^d^(((|}Z$4N7}Yl2i3w@L-M z!vk*B0MvoCzG4v}%@h9;5`=>??$^nKzALPTuEw(y4jQVXiYCgK^77S0Y9Cs3>Rt^!U6zoy@cbAVSy{3 zX!0T4t;-Pw@oI>ZNCA8#5s?$kdi*f15h4UCoIJSXaQM_k4Ws@TR@ks|WsP7sNJUb% zY@EP`A)Dzc&HupH$5Kwtxyh`M77I)04Pon|uv}!??ZVw;>d|D$l%oYGh{DF_1d(!g zWN;NqJ-(S^YZc$@WB3A`p5s0%k>_Fh>7ptPy7^$`3x zJiWo+KVKrD$u*4taVu9jaKh8XjC?lQC~bwf!I(QjKF8@LUby|ttc{Yv!$xieoN>x0 z+XlJw<;g{8>i8rLI#T#spQUA~>iXhsCb@vet_IH=4Rz{4r@pd5qF9m*LcC8eB-vvn zfRI)rW%Zs%F=psDZsz{I6HOKpK{LtLF`2p*J@>QYaPecZ>dxYpV;+&NxYWc2?BTSe zLH=db2|Rq_xbyasK4Y!xi+7x6aQfTDqb!*h(4sCc7rL`k zl|iE5s56~GddWCmUqvBgGCRgNwO5WNlZYTH7rKM8#x6=ylKPlW;ChV@NW{dKYVKUZ zIWOL>rq6!sm0{dbdZU6%-PlzhcIe(z`Cj?rO67{dNY&mMyye^P_~#k1Es4|@W8=bf za|Sov`I#N(+EJV!Ba-HUEuIoHZ2t!LTj-JKp|$K0nv+dj&lTt%k_Cce2j?BS&fXB+ zJ!)cWQ^PmR!Y&hv3=z!JD8F?h=kR+RBBTzE&GS#b{S~D3L-54^3v#r+#w+)+2i<$8 zzBjJ3_zp0mgV79Wz2o1%zM0Ie)B{5nOWk^4 zE2z#*!_r|35S<>~_Q?qQ${C{hqDpB7GyHP|lW&Hb^DBoagIt`_$I>SG-{57=Pht{2 zF#8yaxmngg3&n+_tB_(R^mM6Fdj!50b!A+ecEI0&f(^Zqj-e-#HLYv{+BmJDaE55$&RDZVY<{R&Y}#hck=~?k1o%KC*?<|g`sn>p z?Dmgi{s1tIc}wtQLWTJXdSn=n3JO0+lfhTdPMkETTAQ3X7o(3O|A|8Vg&+JO%)fMy zL9kkZ?pQW6^G+F%1d2X+aQ~KS5r(6eLc!9Cds%~`Z+7Ee+FhFO?;AJO@JQ)?$}}}X z<+YEfw%Bc^9CvIds*(i`W@F4wNRPZTsG}rsKs`V}P(zL;l$&4k!6nMyx_Wo2F#-o< z;x&be9)+PSG+bKA$yBP2gDYeShxl}H1bPl4;Sj4g#;RPKEKG@|i{Orwl12>=4O`Pl z*S9vcLym$#WhYX6dsHRX4id5<{hzgfA%mf9O3Ny^F^M;Agim~^9yMm*^);fHvQfMB zD3l3!XWDCHB9DViwlO%eu&bLGnvfP)+X7t~2@%C1@_ZlX3neJZM9c#Qm;_O-7u zfFhMadDYkD#+MvbG9Mt@A-Gk|kO+ZBVS{ujF-7jp0^}BUzdTO?rGh33F498+S)I|( zY~3EP1)FfdgczpDbZKIQL?=nO85&OOY0~Y^O}60m>FUhb5Dxtb%n*w_+ij;eieId$ z(g>0?LuxuTVE#^gI3fGz1&WE7srtf`#V4ntif!w*prqt>#naUUFEdSlV3~R7_GjaP zbMS>>%S(Jl2s}6Z)V1pf=l};q;;Og;&mtbD{8X6_iUCdzzmP>fL~;e~*mVF79F{mI zq`=3VHu&!jFcvtps z27}W#%A7qnfxZ4#`zF1coE}y|YKX?mQUVQiE(KXxAR&DAfWK4|b6&>`6nrMKMW^*Zzz%FNF2KrDb+AKtN186!`c%(GxTf#HA%vjtTGVETlgIettL3KhZ!MSHHa-rw2LLK;%AVEwXdRq%+ zK#4jsW5_C>rLY(}tG=XL_R=&Waqmf17J?4ip10eUMun7=B5I}wEszuT!I&8eZf2bb zo%?(wKT}iW?qs|ybceaA6qu|C5SWEBbW8wkbFde=aV$g2WtMaJYaC33ldGF|O_zAq4MKXTO2TKPXtIksdyH^Sx5 z#mLzQc*moq?;3402d3y@%9Msyg5d!E&90rM2#$4WsziI$UYxlW!=XlYbIww^9WORE z?v>C7DsMBpKJepXD;Wu?Ln}yaaeg|rDFaJtiXvs|07?Ppr7FE7F6{*a;!0SLJ$U0J zi3#~BC>MAzy=Y}QU3tB<)i%zS@}oxOJxAn}1AqoU_Ag z)jOtJds;UQ-O$=WefgT?{9H;-a7CjRj}3a}OHLn%&YUA+l@teIl|;!v?}N?qedW37 z-u#mswc~@EleV*VDS5Ko3;V6RT(xV%xTsUmW z3bo$WhxSk0%Al0LsO_z>O+QS>xYzFL5gRO}CjpzN;6|ts>^~D@B;Pus%_E7l_b|vdVj{%p+fVv0 zveQRs)gEm99N1d=t^k?9TJt0?=L@D$`z3sg17lPug_4)ywB&f;9&(W&WIH#K5>dP( zTzB%J@5xAa!L26vC*OAvG#)J|ne9TLIxBI->-TWgJ3cU)VY&8~_V~A!y##=44uGsv zFV}upGAtawX(>GX_~swh3Qu2qcKnv)*0SrKo2bJ&2A&~hz`31lr-kfZ6Q8eDiOOE`RcqCvPr2cyQ~Ejw0!U3HNpsMW4p+Szmbk zW=D;s&GE^$23MP!H4#BjWXt>?QUkHw+eJaCv$b9W5aD_9hFx@EC)oRBJZ-JrKG5m& zKl39b4Vqg^p(PjUBjttlD*dXHDUv1Kw@aav7XRG|xWSO&C((-F8@Eg%Ol-7d<5^&; z@xk~ejP@amPTFnr6b_Fs#SuhyK?BzSE&%ti=AXTzCfG^>!*=d51zJ$NB@rl0ln+T! zPz1vxS!YRF3zv`lPJkR90rlP!zg)mF!a3huK;88R5Pi8-6>ioKt@k{wuq zB+f;aGVi?x-0wyJFS|F&$kc!~PAgdb_u#jnnIr?>$#WnR5m|+;yW7(HDnQs4$u8*P z)`=8&D9JIG=E@)e$=u5ouw@sZ=hJpcQBe$JCLZ$H&w!ao9U21*`5p)*%fC^OSpiz( zCASa!?LRmT_|obuG1LU5!A*8p9<*<6MFjalwJ&DWI|{FGSR_O5?3x3xlePg*3g;R@ zmx6K45h5u?8!}r62zX10e7?0LJC<^!T}ViAiv0Qt&i(l072L=HlRwNP6|H9T1&GOi zllBAA&~HPC54+&@4L_F|piO{TXz;8*aT19}!IxeQye@^et~|2W=LjfJElGIRdSi5H zQK{~%L8s{O#)5&6E`^ma>VRrVKsvkjEVyY>APot^O%<6wm=#(;&mC|~)DVNuP*4)D zLSwuqVw`2Y#%OB|4PYV;hMvP_W5I@fLM|YX6R$BhBXFDNiJ%xxOMX9)yz9xJ5E;XP z0nFz0j)LEMZvh52`Yk|XfQ*AAWlapuF5aERRHnJ^>q z@UO0SeN-w@OF;JAf$`n5>onm@GXS9t$(Gw>9UIL`?eGf=Gs%Sm`gYNHXR)lp3+sT~ zGE~VsOWwEbbt0TGumZ-(9hf3GuR$rJ9$xm=)TIKUQ65>f>mll;TmuOgOpSBD@kou6 z+g?GRK=%P_i*RiA!lc;jP3nNeDwk_c`CyaWgS<4Nl7cQKY%ufj6cd%$8}^+f_=B%rM82%Yb@>G6B@l zm+km7uLR3(pxSWGW#1u=AN|`q;L^!ggG>LJwTNDQlV2kr`gd@yZ&6z7nttIIfb0I6 zO!!x(W_S$~{>aO@CU(%W*D&Gb(+e;3CTY{JKK(995&klteyX45O{pE-xe32N5sjdQ zqn?R1@ZDd`aa6AF`m(Qi|E-^RBRccT7t4)b`O>faMSlKsZ@l#D4tU0s-+OCtge-5H zMy$+n1Km8X5qsWn4qDAbO|q6ieK9k*j|~)(YJ)PODEauM;^uk@wWgXZtXQ{h{nWCQ zLazcLxMu9ok~xwPXHD@-`!T=Tc$j>3pCdCsNTLU_v%v=`NM=#IxLBwzGH1!=aCV}r z+O->QE2s`ImS&%``jo`a81@6BhFNrfG!YsN9s<}VYn&dk;PE z*_8y`(aqLAR|?Qjaj%$u(GXt%lF(c6yLP3`nl6x}?I|5V)N!cDX4oZ~K3gV0fXJKV zgZ3OmYzRO8ULUZaK^ieEN8IeVz9o4kv$f*Ooc*`AG1ah&qL4%fA*?YWQ1q~MQ=>!( z7(X3_?W#24>Esp7jo64|3&REcO$WJgw+cDTrUPKhMgTP;AOnqqTtR2qQg}c`5g;jx zqnM0!KLavnjxtBUPtE`VxY^VKX92ze%b`0TR;Em9K5FPF2X|m?mZ_$USnZ&0+%1`m z$_HVUWwm9^ADDxuA~2Lt&O9>6uKG8}ZaA%%6*-`$Nci@}zCQr0EhJsP;t!cFS$Kv- zyE`JVSdq8?)`&`hWWa#w-Vh~Xh{;9dgpgJ0L3Pv{RIJ|%cl%JUrh5T|2g)ot-;m`& zzdhbC*-DAzzU98{b%342!2k;oQpRb$N`yWw&qmNO$-NYZ*16*Om~~Y+QzCBRAnGC6 zbSI|KaR_*zm{xA+Vwq!CW85K@dLUy^km;D>@M5B~-i0{Q-hVv??}4?ho!6U z#uM3PkTpYF^=&PQ9={`xankc!U$xFG;}0NkOI0T_&@m8XyqtGKx0yGmYL27E=D(~`q{b`pVI zK=7XCpJmb`k~Lr6K#hdt$0z{>(Bn{sksaWMfA)rI3P(q2>5DuSqz2>wj2;xqrJ9ry zHL%3Ai02EVtO!^|3W82?WCwmb;fBJ(iL3*Jk^5uMM_y|=%i%~yP*PQ}EQV-Q0<{pN z4>*@>AODq>tCBmSoz+;JS&+>b!L@55HkFZ8pjv|&6s9a=m~ExwD~i%hDUc}*tOc$d zQbnUdTXFwQ4zm%2V(DuySQ6P%RD>rxwhTnS<_ma6o)$JAkR3qg(h4EC%59siz zhC1nz4(V6CouV~k2Y*Jim*goJTz$TGBqg8X_H$(ECw;2wr2H(jFl5{=~yD%Zb z1o-1~>_FbPAHMZoSA!Z=1OM0)f_+j>&ps8x0JWBQiZIN9VkmKG+{ z)=gh)J*nE}*^_#}tOFR*Lu2Y!-K_f@yslwy-nk)E;syolwAMr3G0*?Q&lYE}saR^7 z!zHMWv^{1_>j85uwW@FPwVw{k^Ly%nQJV+iL0egpBhZbcd|Z~9yS7oUkzHYR_9%gJ z%k_o3`n{9aI>S1L6A^geabGA~=k@#P)-CboOnj$aI*7PT^FBDyD0(ra>n3n6>0%Q) zByJctAZjr_(KvDs>7xJE>j15UkR=%p3i&tIha^iN@3VWBwMrBE1O zJz;anC4ylsO_D`_DMzgG5A0C6c5;n+y%Yb_&ZoZvQi)N+cGS@F13F_iF&6KNwE$WN zO7DG-508kX3NXn5P2PO(AwA>{m1}F{)OziUwL+?jS5sZsj>}7Li!KjK<&*Z! z{~-NYh*=oPQTg5mR4#xAcwbXDyC_-;;U$=Ovb|A_ql@F!4@J=|)qbwoxldwjpWaxV zH*cBU6+OEvcxNI&7{!79ogxk5Zxe|RzrZHYjFP>QZxp)C<4+q&?a(`6_Cfoiaye0C z^|9V>PWapJsB=0%H3F#>q+wDO=K&DV5f^S-%0ZvjloGrD(UN3wtY1Igwo;HJ>eL}N zt$VGD7}KOH+Mj5ZQ0Nw_S9=LarFX}k-Ac>*TX#s}1z;knPtx(qbC73-TO;Fo?#@%m zvPPtarY<-#DoA2Usi*_rNH+bg6OD}1925NsOvIFA2`4?W5J>t8$)+%@hyD6kHmX2% zymIg;Re0z^GVxdmHtl(+S;y|&tEBKtYg$^bgc}9tL&qz?SbHR_|7}pWl84EyF#e$k z@(4*5cSTDlBq$!b(d^eHZoM9jNO=SRAF9l(aj#3JBIRvb06Nrv8Eye-hY~Ws{pPQF zDAFwNyn$_NiOr0DlOB39=V5t>Z*B@$>Vw|24~|rif|j8oTB^>>Hkp7x zBCVljFC?vps9mJ6%*Nqut=G$B15KBr6&%QT@gFOJ#ng}eJAw>HB+o4;v?Q}MWQ733 zlWISLw5*{*u?(BuH-AffB9gX4TFLf}bVYYrxJk99HVgS=6P93hJ;W>%0e!*bT_ZIX zh5(*lFqU-D8m%CD@AfH>4lL9=n)*Y}E&*ruMwwcjM@t=50gfZd1cx1Y9uO~ci8BDX zT<`rpCmqu**D0OzIj7|yr=tJZUkg`j0@F1`nJg{Bf_-Eo0{7Ten zU^zt0xGZA3B7Ken6e+LkGiqOMU(cCL<_L~M5GKyHt1}4iC|M4c#b#XhzhX;4M#@8;*^GoC~TB;}g=B zpitAZjjkkKFmMAh8x^?pDjH)Wyx?})0{i|U9?qUSzelhn$sg*WF|bM0v{c1*8{Sa1 zdB|#Bx8_+;>09YF*iWH-+`g> zTnk{OG?V=w6bg7NeAfp?%3t~sNnmhKUQhc~C{*qL0Tk*#Ge2k!AN|DiP2UyDdMQ<@ zP|#k00S0&LyC*z-^<7?_Wb`|Xtq;GOaYLm-|N8DP@QBy`L1_K*5hnX9UZS}^^b@Z~ z+1k0CsM|TY{}tElsGP5Q<1hPV`{Dog@}z`gkurT#%meHkaj#dKsh^@>I8Sd7Cgcs@ zb5FSuZ1iH%Uyj$_9;Zni!cZZpA5ZsTH#Zsw$BUy0D5dYjVW>%q&}x+L(p}$fO;Vhg zTM)8VATGg@Icg9&Oc0PPqm6eVUWDJNKWF`x{``LQQDFj1iq4;=1GWSnbRb5(MNN%K zI$+Z7Al~aMCt1L3*-ZN0$9#22gIXAqJ%aTY?WM9UKrLpfAzVH&cvs2$i1ZWz4`4$C zdf{sp*(DrcXx^yl3EBC6;YgZ+ekc(y4@3}Q>q$?ihSx9?A`ND5F9wQIgGJkV3`nMx z5-tgr6%d_a>xGTtC_4v=C1eC~OE2_$AwG>!4SJ&4+1R=1u^C2o-AD67!S2v95y=mlb^V+4>LAvA2SsqZ|Hw_doYqjz1qUX1T-l$M%SO^|EW zd5zFYtio)hc%s2k!EW4IPT_NrxN?Qok1;~TtJu^q!JODHWR66fj3DtxA)uIinmHV5 zXB?j236k-3F{s9Y%RcBEL!Hf$j`d7=Jf3&xqFTnua2i;_g3CyoE5XW;qBkTIum36vW86&QZz00DiF`&Z6QVT;O? z7XAjVBq2a`18qHrWtJykupj+cBOn^BhJA>|z!T{wcmp|=&@xlcQ0&@g)v^V6iyQno z8`%dKR!!h#WoBA1AgkH_b;RK?O?aL429}odL>|M7+0EK#-y#GP8HQpsy!CyU?_{#g zSfd`IK0?1TfD|h+xngp2*_bo~;bQVPCJGAYj_eFvLrMhp3XzF?ftSa}z&rVsOtU?&typ@HA*+;g`+j9T`?ljXMHXJKdCSS($+k9cQ z@=^-!OExy(jp!N%HH)9XV^1psRFq3h?nyTs8Q`C92^q%_8C^9yy_0Q3P8f&@%r0iq?N7XpET03BU?cn*@Mr2Qboymz96XjW ztrdp(02z0t6dEf63KRomQ^uBGBk+FI;zgxXq|k$5n$k|5M$f^p=s6KnfH9SY{bxQw4(55sr+BrdXc%)8 ze@AHgJweN0B}Ks^nt4INI7`OP0&uY=2LK*LTH1$Yo8T}YQXG*WDy4U%f|4)chdYaf zmU-T%{^RQyPGa8DVz@zt8LROGgy@76nvx9%oQ!bGlwEp}^Qp&7NxQyCJ(Rz-R%mOn zd{TStG&%LIAXF{sp)k^{x9T%Nx|}8TWqYLLbfM?`k6wI3E9DdP3#=1~TJ}3mb%vT( z6lleRIi}RKFH@N`_be4aKOtfTX*OfRbWts`3jxzQ9rW0RkD7pEIGatAV}`p{~KvF zt4Fy+>!pPnSnO>z!l}n6lH|mbgDU7E4xtmU(^`9UR6Oy3q~9^Ac{i5(@}bh(CkT*_ zjHxZ7V-b{i%}7@qJmNY@I}Z?jtv2*e+Re^jUpzRiHUIa5YJn}dS)QNNv{L7q5es`T z7;yXoHa3%GTYqH2{oWuphuW4i*A8!w-|%wTnHPyo5rJ;eSxJ#bxlPP`yt~xv08V`91bXsI1f+5vy zzZgOI{a3y)mevEv7SZKT&dw!(s?n13*B z2!RcSSrl#V1nt3Zx>g^tEh8~|Bdy03*%!o?o`8okTAUx^x+`-c31h?nX5@S)+hc>q z&(Re{w!+d+yz)S)M2+3_Lggycw+PLmrfBGhqg3ftc5@=b! z4Iq^0FbX=M`a?YPTF+I>Uw?r$LflhhYdk%RG~QhkhJ# zfJnksa@B~0oftINJgy*Y5)etgFWDM8TAtE#VM^zOsI4HIkP>-2gsHa?V_DzfL*11Z zs|I_b)9m-y5uRl03?O;8#4n%i7^3Ru)vJ-ESz)-{hRK##Uk37bg}R z##@Hnu5@d%%sa=@)L0Z40;I~2l;XhPtVh9bLWzdA2S3s&ZNi}jK?;*$6^EM3KAdn^ zm<&&Qh?g1v;<_)2CX;x~BbLvULu0ziUnTz$r2MG3l^iNP|4X0qIzc{8`f57bqtr})Bwj4@r^-GX6)NUV57NgYw z+=rG8I`tqeV0JSypd~2={Fpu)djk~A0yQ!d0)j$JJ_s=&4IV2#7r(8E#3>r8PnXV; z2&m#e^mkz=P#MVJIl?Ye00R>gIjx2jUo1`li20O{MyTXA0~(Q^_F~nrTZzUkO+;LX znDOnxx;&Ez&Dfu&*Wvsd9YzV%d^CtY&h-MrhKBB3xF9>B-MYoI=Nx)jfBOF z4vHy?cohq+MiLt40GUKm&)eXsiBzG{O^l3$o{{y6a7;Y*)Si{#?HXc>NUVV22tMS~ zh+;U*pUe1Trspgg*mRkzOmqwYR`x>3}}9GE8L1w7^$?L$r2L1S~}W8mn8oBgxcyFyf5Y%`1~WN)Ul79bztaW6)H5I!xf4=M6a( ziG@WWX6$0Hv4pf*IEJmW-XRdb0xTs=?=Sq1NFAj<=e zTAH5AQKqwuRZ26M@boe(Y^M()0?_XPl9I8PCwd4{LW+#-vhVOIO=op}SFVCO$2)oR zAq#5^;s!O3p%luE3JkeCU!KL2h3F`0g7iD)f(i-HCD{zxlskr%|s1m(nXd zi`+O1VK;G`(UiNT9_s@tC(`6DuyywOEGR}i5LiU+T~Rzkdca5XdEl|bz;pr7AntDG z9Pz&KY>E}BxNB`9ph^@AfxWd@X1rm61|CRM6w+nWb7v zI5Ex7#?;-4!KHyY8jSoH2sl?@0cJ0J=HJUK1;=7t=2IGsp1vc*ScXf{Z2kb2Q*<)( zAkwaI;Z0^4$9CJ3W#sAz$WS@sljHYB`jY za%k%yH&_8w&f|Yf5`+dOnMA6KfF3QC=W+d`VgcXacaKS_V|20$BZL|mF)?l)!Al(7 z67rzAuPFNblyi%~lianJO0{s+SM2jitiS*H|LZ;3u|LK>e6ET+{p#aHQ!V`JjVH04 zj^C-$rwN6de|+f}U`+BP_~4k`74;RF@#?9*+9CB*@?+_frSUmaA??$rY3ZE#w3B)& z*m-MW|8r&#J2JcHYo(3-U=Nff?n9z6d2T3-SfY)Fd7+T#ve7^rb)xFVe{>yx+-Y-m zE{oI8d|2*A9aobRCB{x$Xb|B?FBK%dt+z0RS+owBXIX%pi`etno$0f?!q($n{e*-I znXlOPpk4;$siw-8M!3q`-+lDiCTUhsK`y%CUyb4fr>>3?34z!|)YUmDph|0U5)_+O$YXZ4#at4|PL8V_hNEr0hJl3w--~vjY>@Rj&VCsaf)5f6-(LAD3v!5!+ zQ84is7K4M0c^uIy(fnv9LWzhVJ?dl@TA%DmuCMl|lPhb!0#%e0RRjzQiEWHpzf2sCWP~!$!2~RU zR7f^PTXL)lA`nxCmS~0sQjI|_xvVrltj=Dn_ynd|F5tc#E5>a9%w5?6=V7qU;YxvD z&c*>eo`p~5l~2GHCITW(1^bJeAZ3pD&!pbi*iSA3z!;V`%0?c4Ru8kLEHCDfnl-SC zJWpVl@oRSAILp8@B$ty6AZxB}HumT9X?@o0CA1a+U36YOCdg0J-y42!l%QpfGUCgq zg>5s-IY)V8DQ;vhNjZf@3tQ_9HBeFmOf`QH(@O9f88K2v9YRW!G6kXR?vI()@f4~a zCE zIsY)s$_>KfqMpDsGk{4>Bw+^LkTZJwk2|jnNBbMj-L(3>=WhCI2BYmTcy7LFhX?dm zLNxycG@xI5*L5qxU~!^8znav;1boE{i!)dAinq{RLv?iUoJs#c)=+f;dkn)t8(ky=Pkl7oqj!bO9n|Y} zcs0?Yip*~7ixz|h&lX>44|qGVr!{J2#g|Mjgg(0D42o54K>bib5ETIB6 z?$&zypYO>6hi*o8T7uKy0l*a(59ftMPz3hSBp!8T)IaCtj}O@r;QP#qC7*?&Bvxz< z6Bse)RDQ`t&O=Z*i(#4F8R}2HP;V5lq(n&_93kiOnKydiOaibNEn5IOx^ePEN$V@Q zDm<;c-5O(wn_y?Nv57s#n!wzU1yR{gEyju(NXU%`%PGXRVd#j2!;tN23B^GS9{l+Z zOBV0%_MiPDen%s-D%Zu4anc}&4zu2HW6o0kjBPq3TQtg_|nd#{6hc< zNC-+Of6h%JEM20G+*uevY)-V*Zr}BrVt{Cip^te_^KxCCM`w8)%c7M>S(Y%aR7W4I zueBH~A~88ki80!_y?hXhjTbV~@?Bn-ySM*w2)&44xZ*O>5;fkTY{Gp4M+el`d|qR| zv30T0kW+ir#~E6niHCeF1r8>Qfk&q@QMD-;#ZAxf5$P3;$U+e)2%VG?C5<4hz%JeX z*hgqLR-Xw|fi1BInvH;Y2H`Y`R)rmvsPcMguCZ@oQMW7pDo_+{A&4!3U*&E=yi$xl_ynB4fFJ`EyPRd8QTr3_ja*#HEmcei`$+#_~h%+SUmQl&Ld4t0n38OnzzTrF|=z%JGcekq+_zUX*vIMOmh20Yo%fGLXrX!Fz1}Zs^+gO z%dTI1;hq10zv8gwsWRwTi~KGlO^ZM-a@}I*HxCJf>;6+R`Q!$Ioyh#bU6J2E?;+2T zp74KDuDjtIZz4@hEmSE0Of^))lz|(CX_4A#zi+Z(l+$>`UfyYGE;X8dNcmv9EK(!W zqmn<8HIAi5KSXBo0ba01qz&)*wd+GxsHI4wN*+ONc?9LhIssEmKzxH8co- z<*pT!A>jOE3Y=7TI9Ll0hhOa3f> zj+@6kCR242PtIbX7Q$3w`)Qv=1#$dT`Cj}5jVs63mfaWou( zrYu4&Igs~BLo=2Nosz?mwVUH_GEKSZ1rQYw9yCpa`p*B^OMCLHd^PbD`MDQ0#>jmq z(}P{!4UwwTbjeWS{}3c&GWv{Rc*P18_AgDbC2%u!wX-R z-Hymrwp6A!e`#@Dj%NxwfNgKsZao9u#RJ*X@)h4j>dbyHNv;*8A{QnNl3@~v3Sm)3 zm}>Qs7mXW!^L=lq2G!&J)}D@++WPpy9*)7G>zS})3_Y})BjuU9mASEfDhit=GiHs8 zjD(K^5X;G&KvplY+NdGI1RTV}p(|opJ(85k*El?4wX@c${68O*MIftzm3>|k=<|OR zp)j1q-X!|Ayhgv0?jU*ZJ7#LNg{k3YT%JkBk4<*!wfRZoB>Jmfu+K*GwYH)b@65f) z-1K2(DELNp!lXHIqTwRSsK?qZvaj8rbnF==4B3b{9kM~*lbokat<{NssuW*LPV4&B z#<|!Wd8vUklZC^7nw)rN6E+c#GYyU!8S5lSdDZ$!R9=R&c7Q}kw)ny`KMy_vnz0l( z%fB6(ODgb&BvJJ?Un+U~BIdF42cf^PB58(H<}8PxC|GU+e&o0a^p`IFY@)Boih(tf zt9)2;Kn2`}1B=0Qa<-D-oR1dRH!N;&eF4*;a?kw)rF>Pjo~s`a@MP8~OYz!c(NsND z{ijK9ZRYm0x6eo9x1PH4$x?V`5H0N@0!LGi7Ih>qM{B>&>-`-0fI^2=cBs&tdY+^u zIWR)dN3Q^gp(l5h9-Qipk!vV?i}t*CCKnu=gUzU<>61gmOG=Xy&nE}5kpW>?4UWXy zl9R=@hWpUjZol?M0-MCRjqv`HEaSPQGFB$OaNSxXFat&j@g^Nb0>pqHv~WG}>_dle z)`u`+a#ObZ86M{0%m@2{VITo0lEoOQAsM9Y!+ zHNnR;TenQ9Toe+t!!}sK;tfwx{Pvrh9>j@bNQ3m6$l;EfY7L77wvi$3cuJtxns?gj zZd<`Rfx5H>%SOfm;m}Vu92xxj|J~jB$H;Y6cl^E0#923SvNIao$rdH=Ewkx5iAh}* zupvN+S!AY-%H#q9jUx2vtRX&v{GN?Y4FRhyFophXjadknZ zG9`jmu>%yST9VLTv?^qlf`U-0^z%LU-kI6;`bSLCir$@lKkkon&pr3td(S!d$HO|r zqYNzCz$BZI(Lotz9nqbIf5XC|CIiWlDhW5y1fuH>gYNF}p_$>P8UK9wBRbW_5M+vS z2-aeO09>+(fi5p7t6BmkiwF^=L$Q^sSO5~3Qx-)AHDw6kd^ZL?mnq}4W%}X?I#iXo zHKZk`%%rhxinSrzH^Z)v>=-Be$U<>)b_!Ds3+}N{O#RJ~YJ)wF!UD5`=4dE6)CG&J#iJbIRB0(xi%<|p zCFnIoidyTD4dOwLtEM%P17iz2tDxEO8&O7(7w2`b{IIMf<-sCKlJh1z(eX4{8bVd=P_&nWOJ~dh2$gu+${?;{RhT>oV_AE1Z zgFc9k;K5rB4s%>Dkiajx`qot^=t?`|*nD(n6$*#2$^0Or^vS#J-07`Dn4;;(=`eL{ zHB&6VBCfY{x&8VQ0x1EKqmHDGk_BWUSQl=9-dc)-U^l!DKGIGuvgKE@{_JCG`dgb= zZem-T!g(~Wt2K zEVgl!F!aZ|aC3&+1ItJZlUWn8!!Af@!OEM;oc@1pg_! z7HF1hInv^mtdbNPm_;hk&Y9Ce~e4#2~EqAq}lTr|@ zGUZUBvhGJqBMZPD}~NlmFKe0 z)>HaaB4Ow=DOWvM%A`K{vh?0EG(tJ*Frf!qN977$0;JC<%0+#OaWgf-6N@Y;4q732C}Rp_r9q%nf`r&CMJPFUiNlXtLj}5wesLwJM-wz>VEdrE--* z`)X?7GnS;hmVnZ>6Tlj^b>o;jt&1TG3D$Tg)rk~VmMs1BpCDEi+9)>Q-YynW9c>DGl?ieAjkgr(~iSGYRr}sYNkm!8cwp zkQBwqk5xL^iIIw_@zmB()C97@r*eYBTjY%)yK7gfNjb3qeH~8#bYaxYtV#lqy;#Gj z3i?nO0D55%v{aqQ3Ip-&b*+X_>5DF7Qy@6+8$Pn&$Pc_&OdJU1*!sb)caS&7nVarH z#8#z=K4=v31+dhK$C#ubYXu`W6%s6>xgp_>lUYTfyuR@9%R9&v)1B$@*Ke)YR+Z_( z$SSnCq149n)=-wh+OV@ZD>V>9)vAaHP~cAC4gyt@DV{R=@I7X>3TlWTq$p2*`BLFi zG~sNNA`zg)bX|+J4onJbTYI^_lA4Dw%39?0`^<=%anLBymBt7O=h5I-?~us1;dc zsTaAjxbJ51O-aU3hf>fjsXQ1=5@xD7@z&yTp(k>W?&b?5HvJiPa4I}-Y?*_C;@&sL zji!c?A~V&$HME-?wBE!!7cVHn^2}*w6C7WoBbmG|40_fY1fOThoTQ7pIU4Y;Av4tBT6Fb8my4U| zYn$qC(by{@Psc5*)60PKpbb?DfGvs|b`uFka1?l$2zWlzw=+jX!v!3fv(Kw3j>JNq z5-Ft*t2l-O)5PeistvA?Drs#19~q403Jl6Zw;&-Ee8ZMYI-D-dmWiGBoEU#wdwg?! zSNkKkm(ATxcH~^cY4r7H#PD{1qAarXcT2@ za-!IP*8ddGbH#K4Q!pXWnB2%b6BAGGEcQA~1m#3@W}i zWZHm!PNGtGS*kLI6^fo=|^Yo zU~dF9r`-dbwDMs-ZG*nFn~mPnD6=TB^%A`yjTxNzK^$2_B8aA%6YZFjVpNJ#Ss4@S-d4_u0_zy0wJ3z1iCe`*i*hYs7Apw6cHs#==XGBir;LuQ09 z97yL-NLE0BGV^IGnipgPwfh^7SLv3)i#84^Ko$j-%_%Y=u<$_JiVr`1Ie8R(hYRI* zLXRsK)0haI-RCbvzbh>e{O6FZq6V+@XhM#`4}q5iO4gUhce(x35_14+>AeS z+S8+@0*p}F;A3NZ65mxs-J=_{rh(H=Yzx5lxp68Z+cSi`rX!87&xY83G#0&!O(BS~ z)C^=Mds>VdO}LsCu2;(z4qzbwdC()X-2-poRcdch72%pr?cct_Udh&uCIa@V)@E|t zL{Cq==h8Suc}LG)dpnmJz0iGCYo1SpDSXzg87Dw3iSz{UUIOFhtBN)eSObL^9qM2E@6F`WN>z& z7HxLXYpV;|y-Fd?9lq8qry!s;(=E9?bMl1X-g^#GEHEW0XwVXb@J^}KXQ>aPB zUNfeSCx`F<>?%sUhrLDghb&Lv3sUIv2Yaf#P9@nRVV^mzgpX*Ezb%w-HVZAdCyU5R z%Vri#I2@U4ih8L74KcAdz)IgEB40@WwHK_L4DH%Bl8@Q$F<% z_MX}Gyf2e0$GrMUPAgOcM(8QHMYIiT`km$RbKxuO#Kd$^LRftz^W_P?`t)r`qC!Z8 zi=N#j=yH;=h(v>kZQFq|vH*9140=t-AR%pIv{D-*0wq`BgY-ulTFMBT9Zl*54t@mg z0!_8x0i=R!(YS&`e)T|t4+4_KS2{kr;SvLg=`ZC~T)lw>-6{&Pnjw*?Nqx9|+<8J2 zR6=mmudte9N`u0vI0m&96QTQO?-ESWVMS*^`;Y~*?-D^UFIP@Ic0W3*Spi3#0aOXf zdMN{#T!i&}Mg7Qv1jzwLxs_?|D%a3^c5=9ip}7#Um?a9!ctXhQpjR#eN+OXdr;I)i zEdPS!!b}@)nCgd6XfX;I0|0sSVb3WVDg2|MK;lFIh+P<*-o?E2W)BkN^pY#GYbxFA z|A?`uj71PUGipV~7PHbXg;gsOBL%S#!@ctb(pw@P0|nAjcV+bCn!3vJdh&|-b{IJ76)TdxQ!maXDrL`^dYkyB*o$p( zZu;KEi2xc}Xc!$P(V_TOoA$FR5dE=uSTpWH>^~@!H>*0|o?H&~?qBRBK)r+`tZ2_N zoJx*}OA^)-fUQ9f&9OxU;Md4rqil}$gm`ecY%bNhNBOp%#3hi z#4_L^6YkUzEGR>ZDb$g1NI&!LXTDA(H4&?8vwZR0orEp|gVEhA z2YleKEN~eMWS(rxA-Q+Z6f{#5p#b3NA6)Yz0#v$s)8&pO5j!{qB# zPlK(86-wJSx3+u9yNyXaTH@!8N zX-PsPv$9O{V-UfLD!^K2rGKnt^^zob+0SKzDBN@OD7_zG2j0XP)Cl_J@oQO@R3uZg zbMZ(cZ7;A#x`NWmycW5kjm|R9hh_aTW^Ze(&#jGCQ%;XXl}l5t-M6`A07wR>B+*FP zE-;O@5v%i0+RFb?4Akf(CV?XiSI5>C7bQx4-IOHr+pe51`Q|KNktPx_7I(c&H_bVh zvtTEU0+B%dUjxH^Rsru3DFwM}a4G@L>45&(s|@&=qG~FO6ad6}(*d5;oz#@=UcsW2(73}~B6NadKpsK|7n&FE%m6BPo7%?PGV>GN_N=2ImDRWIjaZy4 z^$gw4vTCu!y#uRh0+OQ~t14Os!zGs0Ko%iaz<8C{v9O32S)pJV2&l&+)q3~N&uici z`7}9f6U4?jjp$^DQr*I|E&HcBn?y!Ih!Y;1OZsJ0sbDLR!bt@qs*2)rjnQTCKlxuV z<2pI0S}#@%1WzCuyvDH$415w*U&87pA} z#gEAWrwj4gD#p~P)@g3Usb{XA4NBXQ>b#gsLa%aW)>$EFRU+u<0%6kp&AM~r-!i(H z{L?CGJW1u7FTt?P)Tj*&N~ZbK6|?e@N#Ns3ne9it{}Y!97_w~17l6xxs$u=P70C4= zwu=I5Sk1~5vqC=Pe>zCWi?VCvQ*0GT-F~1z{rCf`HFL|iL^zZ(%-r7mQ?LD}Q3mHr zPdhK*JZEmdVnCkYW}gwBGEHsc6P&O)_%Y&#eQ_T4#~*xfr7yjBAQS&GvsB&NaqD+C zf7%a)Q1`5kYVa-*t1(a;pPSI-R6Tryy`X-4=8AnjdK%JQ$X#`dK6ce*&OqcuA_s^8 zl=Z`zd*Pb<2JDiUxB7mXrIYCy!1SJ*z60k-b!dz%KKY_W1&*XG=iqZTp;zEw#e?nb z7D98Ek#3I(&5}!+&^&N}=7YUD-H+^^MkWwK;J3wR-$FNJnqyEOiO>`D00#jmlZUFD zR3>?dtbL~tIblKQ3lG!BEq5-yrM0FOX3l71;fqmk5vW8)Vu4O#j&fJ(76B)qwt$khI#&B6q+2)d1PuA*i*Fp07hFj{{;B;9z>P^r9wY-ii4L=W!4ZQ-ZKP1bfQhzu2`p{e6Z;s1mvaG`WFk%anI z6%xT!dt>z+{ecTCm5-B&JX-}1?@i9jek38CPiD;MqS|$2aVr)okz-JciliVVF$cJ4 zDq%2CD|<(!V+}_vonS^lfvo&R-W<)wOuf={A_^1(nGML&-GX*za3j8DDT7t*>2m3o zwp^t{jFps(Gs#*d7C~(xrDH85X&SM`F+pDOypEt`C=mb>j7D_-dsdm(;DxH~*QsWT@`O~%P$}g}3L)r<4(y)bVze75hR@*-QX$-TWD5xU z;puY_nF}Flwi~fqLO}%4kQJ)@8^*r2GyxfPKmAf4uzMm-z({B&Ko#OvlLo+OV^OFc zV7SWnpdHTO5k-f8aH)m}^4I)OP(4VK4NM#1O#~@5c&pDt1@qCNQnFBzgW8oc3L2D~ z_QI~p{-Q6$WkD$Oh`mg5Ccm7muAjB|QmV*2_ka;6?w~kne$JFJ9w}w(kyJdht_hKu zCld-*U&l|ae(!QLNJ%1A1k#L!-bMiV`8s(~Oa*Y!yctI~l~f7^g6_()j~vhFkcoM> z7C-+_1JhzU?f%_%i2r%-awUna2|fRhKi;FyHlF{HX#cyIv~P8K(qsLz`^&#y+Lj^a z1v=QG{`5;ro9+dIvSi&~n##5EjhV18642>JVq!TlpL1e1b8ak2yi{W5M(6KD!-PTJ zq9oPDore^n#sJ650k!auorifX^9doasuy!;(F}iL!>G~y<5OV%@^9&B#1ep}3>7LrA=;~aYqY)cQHt2ga4VRTTC7?`Fk-(uWb>@Hp z3ownEKE0QEDSp596xo4-IQFQpT$tvPKODwUw{|7ols~}bZ7C2{SfHaQYoen)P!i2} zq*Qc~GK9J^Di68m*0bUr=V)t>$~HJ5D^frismA&vr9mVAe$Bb~9;QQW+t-jl4PTZ% zI&LRPh@yJY{|Zi?E}C6k94ADroqkjaut2~NrW_<96;ZhNV6OmknU`3bbcsmZy>F93 zncm`}?uK#!lHwBRNonP_xgu$qACG3D8--rL@ECO+p}&+qz5Mc ze4p^8Usa~$$|4WtEbJ4ZV-;(4ON|;w(kjT*@rSAb%!s8NeFD1^?ne-zVH5kc!-rPO zoW!h_mcW%(8Nkv{iG4wN@}4dz?FEpJDAE5>qJCV3A$AMc$l{m&Q?mukYq7U)=8pYn zMQrBdxG7AHUZX-Q(wr8SNv{R{S!5Hw6&sg$J;u}!{7h=^{)Wq{^!ZpdI(^JiIkps?rL2&I_9BHy%>W{+7V*qI zXxFI;L&dOs^TLNk-4{Q@jFuMIh4p=glmjYAqytu>LUNZ52n5no2=}Z~5Rn=q+)@-` zH(u~kn44RxcV~Y~Z+>;7=9*j(Oh-0~%D=Q7@u*Ux%8-Kr(Q`3~f-46xMHN!0tje5> zi5f@8f4U<0HdDv)K|KrYpjr_bg89_SRzK6jpdT=JC$5;3YM3CW(%tg&@~0#^ zj@lgP8);M`NC*0Yp%ekE;N}h_u!MFms?SH{NJQW6_a0UEMuMJ7)t{&_-;IC|nvC=> zkk8d_bP`g-)FxB1@&yrw5I2XVBw-mObAOMlDGPFOM|U$_W)OQ5Lgd3#ndyZ*&X-&~ zQqsX(Hh#9rX38A0oU_;lrZl`Hlge~BTO++}p2FHOPXPz@0i{DOZWV8!Ds4WBrIgSu z=xnSubr?_xLR8Arl{Tu=u+yn7QTFqzf zwYUFp+v98YF-p)x`2Uez{mz#vKQfR2z-ea%dsFn07NjV65n|*Tpyf0r^-7MGl)L^egpvn7mR0wZ6o3nJ+45xFkA7mg*M-0Deci+k>nO#8;gtY46u@j{st`Fh05lzsOoqXz23zGl2oe18q=n%i})4c{1Sr}sz zX!8>x!b*3?P-m!Zt69Ke;yt>K>|A)X&fZlf@!mH%?l>2q^9gtD>wIFKN1WG+X6MYh zbB-9@pWJbd7_T6Bpp+w$JI?A>SPQu%eiFa+KbCm>NH0Py6@+ya*vxeYwm{Q*&VG{eg98>6Gbu^DkV#+GxpAxrLE3+(v7|$$ld8} zlOb;b@FCU#GfPINdEifnjX>3)))user_io( + .clk_sys (clock_24 ), + .conf_str (CONF_STR ), + .SPI_CLK (SPI_SCK ), + .SPI_SS_IO (CONF_DATA0 ), + .SPI_MISO (SPI_DO ), + .SPI_MOSI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable (scandoublerD ), + .ypbpr (ypbpr ), + .key_strobe (key_strobe ), + .key_pressed (key_pressed ), + .key_code (key_code ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) + ); + +dac #(.C_bits(16))dac( + .clk_i(clock_24), + .res_n_i(1), + .dac_i({audio,audio[4:0]}), + .dac_o(AUDIO_L) + ); + +wire m_up1 = btn_up | joystick_0[3]; +wire m_down1 = btn_down | joystick_0[2]; +wire m_left1 = btn_left | joystick_0[1]; +wire m_right1 = btn_right | joystick_0[0]; +wire m_fire1 = btn_fire1 | joystick_0[4]; + +wire m_up2 = btn_up | joystick_1[3]; +wire m_down2 = btn_down | joystick_1[2]; +wire m_left2 = btn_left | joystick_1[1]; +wire m_right2 = btn_right | joystick_1[0]; +wire m_fire2 = btn_fire1 | joystick_1[4]; + + +reg btn_one_player = 0; +reg btn_two_players = 0; +reg btn_left = 0; +reg btn_right = 0; +reg btn_down = 0; +reg btn_up = 0; +reg btn_fire1 = 0; +//reg btn_fire2 = 0; +//reg btn_fire3 = 0; +reg btn_coin = 0; + +always @(posedge clock_24) begin + reg old_state; + old_state <= key_strobe; + if(old_state != key_strobe) begin + case(key_code) + 'h75: btn_up <= key_pressed; // up + 'h72: btn_down <= key_pressed; // down + 'h6B: btn_left <= key_pressed; // left + 'h74: btn_right <= key_pressed; // right + 'h76: btn_coin <= key_pressed; // ESC + 'h05: btn_one_player <= key_pressed; // F1 + 'h06: btn_two_players <= key_pressed; // F2 + // 'h14: btn_fire3 <= key_pressed; // ctrl + // 'h11: btn_fire2 <= key_pressed; // alt + 'h29: btn_fire1 <= key_pressed; // Space + endcase + end +end + + +endmodule diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T65/T65.vhd b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T65/T65.vhd new file mode 100644 index 00000000..09253fe0 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T65/T65.vhd @@ -0,0 +1,564 @@ +-- **** +-- T65(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 more merging +-- Ver 300 Bugfixes by ehenciak added, started tidyup *bust* +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- 65xx compatible microprocessor core +-- +-- Version : 0246 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t65/ +-- +-- Limitations : +-- +-- 65C02 and 65C816 modes are incomplete +-- Undocumented instructions are not supported +-- Some interface signals behaves incorrect +-- +-- File history : +-- +-- 0246 : First release +-- + +library IEEE; + use IEEE.std_logic_1164.all; + use IEEE.numeric_std.all; + use work.T65_Pack.all; + +-- ehenciak 2-23-2005 : Added the enable signal so that one doesn't have to use +-- the ready signal to limit the CPU. +entity T65 is + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816 + Res_n : in std_logic; + Enable : in std_logic; + Clk : in std_logic; + Rdy : in std_logic; + Abort_n : in std_logic; + IRQ_n : in std_logic; + NMI_n : in std_logic; + SO_n : in std_logic; + R_W_n : out std_logic; + Sync : out std_logic; + EF : out std_logic; + MF : out std_logic; + XF : out std_logic; + ML_n : out std_logic; + VP_n : out std_logic; + VDA : out std_logic; + VPA : out std_logic; + A : out std_logic_vector(23 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T65; + +architecture rtl of T65 is + + -- Registers + signal ABC, X, Y, D : std_logic_vector(15 downto 0); + signal P, AD, DL : std_logic_vector(7 downto 0) := x"00"; + signal BAH : std_logic_vector(7 downto 0); + signal BAL : std_logic_vector(8 downto 0); + signal PBR : std_logic_vector(7 downto 0); + signal DBR : std_logic_vector(7 downto 0); + signal PC : unsigned(15 downto 0); + signal S : unsigned(15 downto 0); + signal EF_i : std_logic; + signal MF_i : std_logic; + signal XF_i : std_logic; + + signal IR : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + + signal Mode_r : std_logic_vector(1 downto 0); + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Write_Data_r : std_logic_vector(2 downto 0); + signal Set_Addr_To_r : std_logic_vector(1 downto 0); + signal PCAdder : unsigned(8 downto 0); + + signal RstCycle : std_logic; + signal IRQCycle : std_logic; + signal NMICycle : std_logic; + + signal B_o : std_logic; + signal SO_n_o : std_logic; + signal IRQ_n_o : std_logic; + signal NMI_n_o : std_logic; + signal NMIAct : std_logic; + + signal Break : std_logic; + + -- ALU signals + signal BusA : std_logic_vector(7 downto 0); + signal BusA_r : std_logic_vector(7 downto 0); + signal BusB : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal P_Out : std_logic_vector(7 downto 0); + + -- Micro code outputs + signal LCycle : std_logic_vector(2 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(2 downto 0); + signal Set_Addr_To : std_logic_vector(1 downto 0); + signal Write_Data : std_logic_vector(2 downto 0); + signal Jump : std_logic_vector(1 downto 0); + signal BAAdd : std_logic_vector(1 downto 0); + signal BreakAtNA : std_logic; + signal ADAdd : std_logic; + signal AddY : std_logic; + signal PCAdd : std_logic; + signal Inc_S : std_logic; + signal Dec_S : std_logic; + signal LDA : std_logic; + signal LDP : std_logic; + signal LDX : std_logic; + signal LDY : std_logic; + signal LDS : std_logic; + signal LDDI : std_logic; + signal LDALU : std_logic; + signal LDAD : std_logic; + signal LDBAL : std_logic; + signal LDBAH : std_logic; + signal SaveP : std_logic; + signal Write : std_logic; + + signal really_rdy : std_logic; + signal R_W_n_i : std_logic; + +begin + -- ehenciak : gate Rdy with read/write to make an "OK, it's + -- really OK to stop the processor now if Rdy is + -- deasserted" signal + really_rdy <= Rdy or not(R_W_n_i); + + -- ehenciak : Drive R_W_n_i off chip. + R_W_n <= R_W_n_i; + + Sync <= '1' when MCycle = "000" else '0'; + EF <= EF_i; + MF <= MF_i; + XF <= XF_i; + ML_n <= '0' when IR(7 downto 6) /= "10" and IR(2 downto 1) = "11" and MCycle(2 downto 1) /= "00" else '1'; + VP_n <= '0' when IRQCycle = '1' and (MCycle = "101" or MCycle = "110") else '1'; + VDA <= '1' when Set_Addr_To_r /= "00" else '0'; -- Incorrect !!!!!!!!!!!! + VPA <= '1' when Jump(1) = '0' else '0'; -- Incorrect !!!!!!!!!!!! + + mcode : T65_MCode + port map( + Mode => Mode_r, + IR => IR, + MCycle => MCycle, + P => P, + LCycle => LCycle, + ALU_Op => ALU_Op, + Set_BusA_To => Set_BusA_To, + Set_Addr_To => Set_Addr_To, + Write_Data => Write_Data, + Jump => Jump, + BAAdd => BAAdd, + BreakAtNA => BreakAtNA, + ADAdd => ADAdd, + AddY => AddY, + PCAdd => PCAdd, + Inc_S => Inc_S, + Dec_S => Dec_S, + LDA => LDA, + LDP => LDP, + LDX => LDX, + LDY => LDY, + LDS => LDS, + LDDI => LDDI, + LDALU => LDALU, + LDAD => LDAD, + LDBAL => LDBAL, + LDBAH => LDBAH, + SaveP => SaveP, + Write => Write + ); + + alu : T65_ALU + port map( + Mode => Mode_r, + Op => ALU_Op_r, + BusA => BusA_r, + BusB => BusB, + P_In => P, + P_Out => P_Out, + Q => ALU_Q + ); + + process (Res_n, Clk) + begin + if Res_n = '0' then + PC <= (others => '0'); -- Program Counter + IR <= "00000000"; + S <= (others => '0'); -- Dummy !!!!!!!!!!!!!!!!!!!!! + D <= (others => '0'); + PBR <= (others => '0'); + DBR <= (others => '0'); + + Mode_r <= (others => '0'); + ALU_Op_r <= "1100"; + Write_Data_r <= "000"; + Set_Addr_To_r <= "00"; + + R_W_n_i <= '1'; + EF_i <= '1'; + MF_i <= '1'; + XF_i <= '1'; + + elsif Clk'event and Clk = '1' then + if (Enable = '1') then + if (really_rdy = '1') then + R_W_n_i <= not Write or RstCycle; + + D <= (others => '1'); -- Dummy + PBR <= (others => '1'); -- Dummy + DBR <= (others => '1'); -- Dummy + EF_i <= '0'; -- Dummy + MF_i <= '0'; -- Dummy + XF_i <= '0'; -- Dummy + + if MCycle = "000" then + Mode_r <= Mode; + + if IRQCycle = '0' and NMICycle = '0' then + PC <= PC + 1; + end if; + + if IRQCycle = '1' or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DI; + end if; + end if; + + ALU_Op_r <= ALU_Op; + Write_Data_r <= Write_Data; + if Break = '1' then + Set_Addr_To_r <= "00"; + else + Set_Addr_To_r <= Set_Addr_To; + end if; + + if Inc_S = '1' then + S <= S + 1; + end if; + if Dec_S = '1' and RstCycle = '0' then + S <= S - 1; + end if; + if LDS = '1' then + S(7 downto 0) <= unsigned(ALU_Q); + end if; + + if IR = "00000000" and MCycle = "001" and IRQCycle = '0' and NMICycle = '0' then + PC <= PC + 1; + end if; + -- + -- jump control logic + -- + case Jump is + when "01" => + PC <= PC + 1; + + when "10" => + PC <= unsigned(DI & DL); + + when "11" => + if PCAdder(8) = '1' then + if DL(7) = '0' then + PC(15 downto 8) <= PC(15 downto 8) + 1; + else + PC(15 downto 8) <= PC(15 downto 8) - 1; + end if; + end if; + PC(7 downto 0) <= PCAdder(7 downto 0); + + when others => null; + end case; + end if; + end if; + end if; + end process; + + PCAdder <= resize(PC(7 downto 0),9) + resize(unsigned(DL(7) & DL),9) when PCAdd = '1' + else "0" & PC(7 downto 0); + + process (Clk) + begin + if Clk'event and Clk = '1' then + if (Enable = '1') then + if (really_rdy = '1') then + if MCycle = "000" then + if LDA = '1' then + ABC(7 downto 0) <= ALU_Q; + end if; + if LDX = '1' then + X(7 downto 0) <= ALU_Q; + end if; + if LDY = '1' then + Y(7 downto 0) <= ALU_Q; + end if; + if (LDA or LDX or LDY) = '1' then + P <= P_Out; + end if; + end if; + if SaveP = '1' then + P <= P_Out; + end if; + if LDP = '1' then + P <= ALU_Q; + end if; + if IR(4 downto 0) = "11000" then + case IR(7 downto 5) is + when "000" => + P(Flag_C) <= '0'; + when "001" => + P(Flag_C) <= '1'; + when "010" => + P(Flag_I) <= '0'; + when "011" => + P(Flag_I) <= '1'; + when "101" => + P(Flag_V) <= '0'; + when "110" => + P(Flag_D) <= '0'; + when "111" => + P(Flag_D) <= '1'; + when others => + end case; + end if; + + --if IR = "00000000" and MCycle = "011" and RstCycle = '0' and NMICycle = '0' and IRQCycle = '0' then + -- P(Flag_B) <= '1'; + --end if; + --if IR = "00000000" and MCycle = "100" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1') then + -- P(Flag_I) <= '1'; + -- P(Flag_B) <= B_o; + --end if; + + -- B=1 always on the 6502 + P(Flag_B) <= '1'; + if IR = "00000000" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1') then + if MCycle = "011" then + -- B=0 in *copy* of P pushed onto the stack + P(Flag_B) <= '0'; + elsif MCycle = "100" then + P(Flag_I) <= '1'; + end if; + end if; + + if SO_n_o = '1' and SO_n = '0' then + P(Flag_V) <= '1'; + end if; + if RstCycle = '1' and Mode_r /= "00" then + P(Flag_1) <= '1'; + P(Flag_D) <= '0'; + P(Flag_I) <= '1'; + end if; + P(Flag_1) <= '1'; + + B_o <= P(Flag_B); + SO_n_o <= SO_n; + IRQ_n_o <= IRQ_n; + NMI_n_o <= NMI_n; + end if; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + + process (Res_n, Clk) + begin + if Res_n = '0' then + BusA_r <= (others => '0'); + BusB <= (others => '0'); + AD <= (others => '0'); + BAL <= (others => '0'); + BAH <= (others => '0'); + DL <= (others => '0'); + elsif Clk'event and Clk = '1' then + if (Enable = '1') then + if (Rdy = '1') then + BusA_r <= BusA; + BusB <= DI; + + case BAAdd is + when "01" => + -- BA Inc + AD <= std_logic_vector(unsigned(AD) + 1); + BAL <= std_logic_vector(unsigned(BAL) + 1); + when "10" => + -- BA Add + BAL <= std_logic_vector(resize(unsigned(BAL(7 downto 0)),9) + resize(unsigned(BusA),9)); + when "11" => + -- BA Adj + if BAL(8) = '1' then + BAH <= std_logic_vector(unsigned(BAH) + 1); + end if; + when others => + end case; + + -- ehenciak : modified to use Y register as well (bugfix) + if ADAdd = '1' then + if (AddY = '1') then + AD <= std_logic_vector(unsigned(AD) + unsigned(Y(7 downto 0))); + else + AD <= std_logic_vector(unsigned(AD) + unsigned(X(7 downto 0))); + end if; + end if; + + if IR = "00000000" then + BAL <= (others => '1'); + BAH <= (others => '1'); + if RstCycle = '1' then + BAL(2 downto 0) <= "100"; + elsif NMICycle = '1' then + BAL(2 downto 0) <= "010"; + else + BAL(2 downto 0) <= "110"; + end if; + if Set_addr_To_r = "11" then + BAL(0) <= '1'; + end if; + end if; + + + if LDDI = '1' then + DL <= DI; + end if; + if LDALU = '1' then + DL <= ALU_Q; + end if; + if LDAD = '1' then + AD <= DI; + end if; + if LDBAL = '1' then + BAL(7 downto 0) <= DI; + end if; + if LDBAH = '1' then + BAH <= DI; + end if; + end if; + end if; + end if; + end process; + + Break <= (BreakAtNA and not BAL(8)) or (PCAdd and not PCAdder(8)); + + + with Set_BusA_To select + BusA <= DI when "000", + ABC(7 downto 0) when "001", + X(7 downto 0) when "010", + Y(7 downto 0) when "011", + std_logic_vector(S(7 downto 0)) when "100", + P when "101", + (others => '-') when others; + + with Set_Addr_To_r select + A <= "0000000000000001" & std_logic_vector(S(7 downto 0)) when "01", + DBR & "00000000" & AD when "10", + "00000000" & BAH & BAL(7 downto 0) when "11", + PBR & std_logic_vector(PC(15 downto 8)) & std_logic_vector(PCAdder(7 downto 0)) when others; + + with Write_Data_r select + DO <= DL when "000", + ABC(7 downto 0) when "001", + X(7 downto 0) when "010", + Y(7 downto 0) when "011", + std_logic_vector(S(7 downto 0)) when "100", + P when "101", + std_logic_vector(PC(7 downto 0)) when "110", + std_logic_vector(PC(15 downto 8)) when others; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + + process (Res_n, Clk) + begin + if Res_n = '0' then + MCycle <= "001"; + RstCycle <= '1'; + IRQCycle <= '0'; + NMICycle <= '0'; + NMIAct <= '0'; + elsif Clk'event and Clk = '1' then + if (Enable = '1') then + if (really_rdy = '1') then + if MCycle = LCycle or Break = '1' then + MCycle <= "000"; + RstCycle <= '0'; + IRQCycle <= '0'; + NMICycle <= '0'; + if NMIAct = '1' then + NMICycle <= '1'; + elsif IRQ_n_o = '0' and P(Flag_I) = '0' then + IRQCycle <= '1'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + + if NMICycle = '1' then + NMIAct <= '0'; + end if; + if NMI_n_o = '1' and NMI_n = '0' then + NMIAct <= '1'; + end if; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T65/T65_ALU.vhd b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T65/T65_ALU.vhd new file mode 100644 index 00000000..b1f6d632 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T65/T65_ALU.vhd @@ -0,0 +1,260 @@ +-- **** +-- T65(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 Bugfixes by ehenciak added +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- 6502 compatible microprocessor core +-- +-- Version : 0245 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t65/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0245 : First version +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T65_Pack.all; + +entity T65_ALU is + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816 + Op : in std_logic_vector(3 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + P_In : in std_logic_vector(7 downto 0); + P_Out : out std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0) + ); +end T65_ALU; + +architecture rtl of T65_ALU is + + -- AddSub variables (temporary signals) + signal ADC_Z : std_logic; + signal ADC_C : std_logic; + signal ADC_V : std_logic; + signal ADC_N : std_logic; + signal ADC_Q : std_logic_vector(7 downto 0); + signal SBC_Z : std_logic; + signal SBC_C : std_logic; + signal SBC_V : std_logic; + signal SBC_N : std_logic; + signal SBC_Q : std_logic_vector(7 downto 0); + +begin + + process (P_In, BusA, BusB) + variable AL : unsigned(6 downto 0); + variable AH : unsigned(6 downto 0); + variable C : std_logic; + begin + AL := resize(unsigned(BusA(3 downto 0) & P_In(Flag_C)), 7) + resize(unsigned(BusB(3 downto 0) & "1"), 7); + AH := resize(unsigned(BusA(7 downto 4) & AL(5)), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7); + +-- pragma translate_off + if is_x(std_logic_vector(AL)) then AL := "0000000"; end if; + if is_x(std_logic_vector(AH)) then AH := "0000000"; end if; +-- pragma translate_on + + if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then + ADC_Z <= '1'; + else + ADC_Z <= '0'; + end if; + + if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' then + AL(6 downto 1) := AL(6 downto 1) + 6; + end if; + + C := AL(6) or AL(5); + AH := resize(unsigned(BusA(7 downto 4) & C), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7); + + ADC_N <= AH(4); + ADC_V <= (AH(4) xor BusA(7)) and not (BusA(7) xor BusB(7)); + +-- pragma translate_off + if is_x(std_logic_vector(AH)) then AH := "0000000"; end if; +-- pragma translate_on + + if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' then + AH(6 downto 1) := AH(6 downto 1) + 6; + end if; + + ADC_C <= AH(6) or AH(5); + + ADC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1)); + end process; + + process (Op, P_In, BusA, BusB) + variable AL : unsigned(6 downto 0); + variable AH : unsigned(5 downto 0); + variable C : std_logic; + begin + C := P_In(Flag_C) or not Op(0); + AL := resize(unsigned(BusA(3 downto 0) & C), 7) - resize(unsigned(BusB(3 downto 0) & "1"), 6); + AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(5)), 6); + +-- pragma translate_off + if is_x(std_logic_vector(AL)) then AL := "0000000"; end if; + if is_x(std_logic_vector(AH)) then AH := "000000"; end if; +-- pragma translate_on + + if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then + SBC_Z <= '1'; + else + SBC_Z <= '0'; + end if; + + SBC_C <= not AH(5); + SBC_V <= (AH(4) xor BusA(7)) and (BusA(7) xor BusB(7)); + SBC_N <= AH(4); + + if P_In(Flag_D) = '1' then + if AL(5) = '1' then + AL(5 downto 1) := AL(5 downto 1) - 6; + end if; + AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(6)), 6); + if AH(5) = '1' then + AH(5 downto 1) := AH(5 downto 1) - 6; + end if; + end if; + + SBC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1)); + end process; + + process (Op, P_In, BusA, BusB, + ADC_Z, ADC_C, ADC_V, ADC_N, ADC_Q, + SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q) + variable Q_t : std_logic_vector(7 downto 0); + begin + -- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC + -- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC + P_Out <= P_In; + Q_t := BusA; + case Op(3 downto 0) is + when "0000" => + -- ORA + Q_t := BusA or BusB; + when "0001" => + -- AND + Q_t := BusA and BusB; + when "0010" => + -- EOR + Q_t := BusA xor BusB; + when "0011" => + -- ADC + P_Out(Flag_V) <= ADC_V; + P_Out(Flag_C) <= ADC_C; + Q_t := ADC_Q; + when "0101" | "1101" => + -- LDA + when "0110" => + -- CMP + P_Out(Flag_C) <= SBC_C; + when "0111" => + -- SBC + P_Out(Flag_V) <= SBC_V; + P_Out(Flag_C) <= SBC_C; + Q_t := SBC_Q; + when "1000" => + -- ASL + Q_t := BusA(6 downto 0) & "0"; + P_Out(Flag_C) <= BusA(7); + when "1001" => + -- ROL + Q_t := BusA(6 downto 0) & P_In(Flag_C); + P_Out(Flag_C) <= BusA(7); + when "1010" => + -- LSR + Q_t := "0" & BusA(7 downto 1); + P_Out(Flag_C) <= BusA(0); + when "1011" => + -- ROR + Q_t := P_In(Flag_C) & BusA(7 downto 1); + P_Out(Flag_C) <= BusA(0); + when "1100" => + -- BIT + P_Out(Flag_V) <= BusB(6); + when "1110" => + -- DEC + Q_t := std_logic_vector(unsigned(BusA) - 1); + when "1111" => + -- INC + Q_t := std_logic_vector(unsigned(BusA) + 1); + when others => + end case; + + case Op(3 downto 0) is + when "0011" => + P_Out(Flag_N) <= ADC_N; + P_Out(Flag_Z) <= ADC_Z; + when "0110" | "0111" => + P_Out(Flag_N) <= SBC_N; + P_Out(Flag_Z) <= SBC_Z; + when "0100" => + when "1100" => + P_Out(Flag_N) <= BusB(7); + if (BusA and BusB) = "00000000" then + P_Out(Flag_Z) <= '1'; + else + P_Out(Flag_Z) <= '0'; + end if; + when others => + P_Out(Flag_N) <= Q_t(7); + if Q_t = "00000000" then + P_Out(Flag_Z) <= '1'; + else + P_Out(Flag_Z) <= '0'; + end if; + end case; + + Q <= Q_t; + end process; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T65/T65_MCode.vhd b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T65/T65_MCode.vhd new file mode 100644 index 00000000..6c6c864a --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T65/T65_MCode.vhd @@ -0,0 +1,1052 @@ +-- **** +-- T65(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 302 minor timing fixes +-- Ver 301 Jump timing fixed +-- Ver 300 Bugfixes by ehenciak added +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- 65xx compatible microprocessor core +-- +-- Version : 0246 + fix +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t65/ +-- +-- Limitations : +-- +-- 65C02 +-- supported : inc, dec, phx, plx, phy, ply +-- missing : bra, ora, lda, cmp, sbc, tsb*2, trb*2, stz*2, bit*2, wai, stp, jmp, bbr*8, bbs*8 +-- +-- File history : +-- +-- 0246 : First release +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T65_Pack.all; + +entity T65_MCode is + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816 + IR : in std_logic_vector(7 downto 0); + MCycle : in std_logic_vector(2 downto 0); + P : in std_logic_vector(7 downto 0); + LCycle : out std_logic_vector(2 downto 0); + ALU_Op : out std_logic_vector(3 downto 0); + Set_BusA_To : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P + Set_Addr_To : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA + Write_Data : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH + Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel + BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj + BreakAtNA : out std_logic; + ADAdd : out std_logic; + AddY : out std_logic; + PCAdd : out std_logic; + Inc_S : out std_logic; + Dec_S : out std_logic; + LDA : out std_logic; + LDP : out std_logic; + LDX : out std_logic; + LDY : out std_logic; + LDS : out std_logic; + LDDI : out std_logic; + LDALU : out std_logic; + LDAD : out std_logic; + LDBAL : out std_logic; + LDBAH : out std_logic; + SaveP : out std_logic; + Write : out std_logic + ); +end T65_MCode; + +architecture rtl of T65_MCode is + + signal Branch : std_logic; + +begin + + with IR(7 downto 5) select + Branch <= not P(Flag_N) when "000", + P(Flag_N) when "001", + not P(Flag_V) when "010", + P(Flag_V) when "011", + not P(Flag_C) when "100", + P(Flag_C) when "101", + not P(Flag_Z) when "110", + P(Flag_Z) when others; + + process (IR, MCycle, P, Branch, Mode) + begin + LCycle <= "001"; + Set_BusA_To <= "001"; -- A + Set_Addr_To <= (others => '0'); + Write_Data <= (others => '0'); + Jump <= (others => '0'); + BAAdd <= "00"; + BreakAtNA <= '0'; + ADAdd <= '0'; + PCAdd <= '0'; + Inc_S <= '0'; + Dec_S <= '0'; + LDA <= '0'; + LDP <= '0'; + LDX <= '0'; + LDY <= '0'; + LDS <= '0'; + LDDI <= '0'; + LDALU <= '0'; + LDAD <= '0'; + LDBAL <= '0'; + LDBAH <= '0'; + SaveP <= '0'; + Write <= '0'; + AddY <= '0'; + + case IR(7 downto 5) is + when "100" => + --{{{ + case IR(1 downto 0) is + when "00" => + Set_BusA_To <= "011"; -- Y + Write_Data <= "011"; -- Y + when "10" => + Set_BusA_To <= "010"; -- X + Write_Data <= "010"; -- X + when others => + Write_Data <= "001"; -- A + end case; + --}}} + when "101" => + --{{{ + case IR(1 downto 0) is + when "00" => + if IR(4) /= '1' or IR(2) /= '0' then + LDY <= '1'; + end if; + when "10" => + LDX <= '1'; + when others => + LDA <= '1'; + end case; + Set_BusA_To <= "000"; -- DI + --}}} + when "110" => + --{{{ + case IR(1 downto 0) is + when "00" => + if IR(4) = '0' then + LDY <= '1'; + end if; + Set_BusA_To <= "011"; -- Y + when others => + Set_BusA_To <= "001"; -- A + end case; + --}}} + when "111" => + --{{{ + case IR(1 downto 0) is + when "00" => + if IR(4) = '0' then + LDX <= '1'; + end if; + Set_BusA_To <= "010"; -- X + when others => + Set_BusA_To <= "001"; -- A + end case; + --}}} + when others => + end case; + + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + Set_BusA_To <= "000"; -- DI + end if; + + case IR(4 downto 0) is + when "00000" | "01000" | "01010" | "11000" | "11010" => + --{{{ + -- Implied + case IR is + when "00000000" => + -- BRK + LCycle <= "110"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= "01"; -- S + Write_Data <= "111"; -- PCH + Write <= '1'; + when 2 => + Dec_S <= '1'; + Set_Addr_To <= "01"; -- S + Write_Data <= "110"; -- PCL + Write <= '1'; + when 3 => + Dec_S <= '1'; + Set_Addr_To <= "01"; -- S + Write_Data <= "101"; -- P + Write <= '1'; + when 4 => + Dec_S <= '1'; + Set_Addr_To <= "11"; -- BA + when 5 => + LDDI <= '1'; + Set_Addr_To <= "11"; -- BA + when 6 => + Jump <= "10"; -- DIDL + when others => + end case; + when "00100000" => + -- JSR + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDDI <= '1'; + Set_Addr_To <= "01"; -- S + when 2 => + Set_Addr_To <= "01"; -- S + Write_Data <= "111"; -- PCH + Write <= '1'; + when 3 => + Dec_S <= '1'; + Set_Addr_To <= "01"; -- S + Write_Data <= "110"; -- PCL + Write <= '1'; + when 4 => + Dec_S <= '1'; + when 5 => + Jump <= "10"; -- DIDL + when others => + end case; + when "01000000" => + -- RTI + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= "01"; -- S + when 2 => + Inc_S <= '1'; + Set_Addr_To <= "01"; -- S + when 3 => + Inc_S <= '1'; + Set_Addr_To <= "01"; -- S + Set_BusA_To <= "000"; -- DI + when 4 => + LDP <= '1'; + Inc_S <= '1'; + LDDI <= '1'; + Set_Addr_To <= "01"; -- S + when 5 => + Jump <= "10"; -- DIDL + when others => + end case; + when "01100000" => + -- RTS + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= "01"; -- S + when 2 => + Inc_S <= '1'; + Set_Addr_To <= "01"; -- S + when 3 => + Inc_S <= '1'; + LDDI <= '1'; + Set_Addr_To <= "01"; -- S + when 4 => + Jump <= "10"; -- DIDL + when 5 => + Jump <= "01"; + when others => + end case; + when "00001000" | "01001000" | "01011010" | "11011010" => + -- PHP, PHA, PHY*, PHX* + LCycle <= "010"; + if Mode = "00" and IR(1) = '1' then + LCycle <= "001"; + end if; + case to_integer(unsigned(MCycle)) is + when 1 => + case IR(7 downto 4) is + when "0000" => + Write_Data <= "101"; -- P + when "0100" => + Write_Data <= "001"; -- A + when "0101" => + Write_Data <= "011"; -- Y + when "1101" => + Write_Data <= "010"; -- X + when others => + end case; + Write <= '1'; + Set_Addr_To <= "01"; -- S + when 2 => + Dec_S <= '1'; + when others => + end case; + when "00101000" | "01101000" | "01111010" | "11111010" => + -- PLP, PLA, PLY*, PLX* + LCycle <= "011"; + if Mode = "00" and IR(1) = '1' then + LCycle <= "001"; + end if; + case IR(7 downto 4) is + when "0010" => + LDP <= '1'; + when "0110" => + LDA <= '1'; + when "0111" => + if Mode /= "00" then + LDY <= '1'; + end if; + when "1111" => + if Mode /= "00" then + LDX <= '1'; + end if; + when others => + end case; + case to_integer(unsigned(MCycle)) is + when 0 => + SaveP <= '1'; + when 1 => + Set_Addr_To <= "01"; -- S + when 2 => + Inc_S <= '1'; + Set_Addr_To <= "01"; -- S + when 3 => + Set_BusA_To <= "000"; -- DI + when others => + end case; + when "10100000" | "11000000" | "11100000" => + -- LDY, CPY, CPX + -- Immediate + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + when others => + end case; + when "10001000" => + -- DEY + LDY <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "011"; -- Y + when others => + end case; + when "11001010" => + -- DEX + LDX <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "010"; -- X + when others => + end case; + when "00011010" | "00111010" => + -- INC*, DEC* + if Mode /= "00" then + LDA <= '1'; -- A + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "100"; -- S + when others => + end case; + when "00001010" | "00101010" | "01001010" | "01101010" => + -- ASL, ROL, LSR, ROR + LDA <= '1'; -- A + Set_BusA_To <= "001"; -- A + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + when others => + end case; + when "10001010" | "10011000" => + -- TYA, TXA + LDA <= '1'; -- A + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + when others => + end case; + when "10101010" | "10101000" => + -- TAX, TAY + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "001"; -- A + when others => + end case; + when "10011010" => + -- TXS + case to_integer(unsigned(MCycle)) is + when 0 => + LDS <= '1'; + when 1 => + when others => + end case; + when "10111010" => + -- TSX + LDX <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "100"; -- S + when others => + end case; + + -- when "00011000" | "00111000" | "01011000" | "01111000" | "10111000" | "11011000" | "11111000" | "11001000" | "11101000" => + -- -- CLC, SEC, CLI, SEI, CLV, CLD, SED, INY, INX + -- case to_integer(unsigned(MCycle)) is + -- when 1 => + -- when others => + -- end case; + when others => + case to_integer(unsigned(MCycle)) is + when 0 => + when others => + end case; + end case; + --}}} + + when "00001" | "00011" => + --{{{ + -- Zero Page Indexed Indirect (d,x) + LCycle <= "101"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + ADAdd <= '1'; + Set_Addr_To <= "10"; -- AD + when 3 => + BAAdd <= "01"; -- DB Inc + LDBAL <= '1'; + Set_Addr_To <= "10"; -- AD + when 4 => + LDBAH <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 5 => + when others => + end case; + --}}} + + when "01001" | "01011" => + --{{{ + -- Immediate + LDA <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + when others => + end case; + + --}}} + + when "00010" | "10010" => + --{{{ + -- Immediate, KIL + LDX <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + if IR = "10100010" then + -- LDX + Jump <= "01"; + else + -- KIL !!!!!!!!!!!!!!!!!!!!!!!!!!!!! + end if; + when others => + end case; + --}}} + + when "00100" => + --{{{ + -- Zero Page + LCycle <= "010"; + case to_integer(unsigned(MCycle)) is + when 0 => + if IR(7 downto 5) = "001" then + SaveP <= '1'; + end if; + when 1 => + Jump <= "01"; + LDAD <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "10"; -- AD + when 2 => + when others => + end case; + --}}} + + when "00101" | "00110" | "00111" => + --{{{ + -- Zero Page + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + -- Read-Modify-Write + LCycle <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + LDDI <= '1'; + Write <= '1'; + Set_Addr_To <= "10"; -- AD + when 3 => + LDALU <= '1'; + SaveP <= '1'; + Write <= '1'; + Set_Addr_To <= "10"; -- AD + when 4 => + when others => + end case; + else + LCycle <= "010"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDAD <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "10"; -- AD + when 2 => + when others => + end case; + end if; + --}}} + + when "01100" => + --{{{ + -- Absolute + if IR(7 downto 6) = "01" and IR(4 downto 0) = "01100" then + -- JMP + if IR(5) = '0' then + --LCycle <= "011"; + LCycle <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDDI <= '1'; + when 2 => + Jump <= "10"; -- DIDL + when others => + end case; + else + --LCycle <= "101"; + LCycle <= "100"; -- mikej + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDDI <= '1'; + LDBAL <= '1'; + when 2 => + LDBAH <= '1'; + if Mode /= "00" then + Jump <= "10"; -- DIDL + end if; + if Mode = "00" then + Set_Addr_To <= "11"; -- BA + end if; + when 3 => + LDDI <= '1'; + if Mode = "00" then + Set_Addr_To <= "11"; -- BA + BAAdd <= "01"; -- DB Inc + else + Jump <= "01"; + end if; + when 4 => + Jump <= "10"; -- DIDL + when others => + end case; + end if; + else + LCycle <= "011"; + case to_integer(unsigned(MCycle)) is + when 0 => + if IR(7 downto 5) = "001" then + SaveP <= '1'; + end if; + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + LDBAH <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 3 => + when others => + end case; + end if; + --}}} + + when "01101" | "01110" | "01111" => + --{{{ + -- Absolute + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + -- Read-Modify-Write + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 3 => + LDDI <= '1'; + Write <= '1'; + Set_Addr_To <= "11"; -- BA + when 4 => + Write <= '1'; + LDALU <= '1'; + SaveP <= '1'; + Set_Addr_To <= "11"; -- BA + when 5 => + SaveP <= '0'; -- MIKEJ was 1 + when others => + end case; + else + LCycle <= "011"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + LDBAH <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 3 => + when others => + end case; + end if; + --}}} + + when "10000" => + --{{{ + -- Relative + + -- This circuit dictates when the last + -- microcycle occurs for the branch depending on + -- whether or not the branch is taken and if a page + -- is crossed... + if (Branch = '1') then + + LCycle <= "011"; -- We're done @ T3 if branching...upper + -- level logic will stop at T2 if no page cross + -- (See the Break signal) + else + + LCycle <= "001"; + + end if; + + -- This decodes the current microcycle and takes the + -- proper course of action... + case to_integer(unsigned(MCycle)) is + + -- On the T1 microcycle, increment the program counter + -- and instruct the upper level logic to fetch the offset + -- from the Din bus and store it in the data latches. This + -- will be the last microcycle if the branch isn't taken. + when 1 => + + Jump <= "01"; -- Increments the PC by one (PC will now be PC+2) + -- from microcycle T0. + + LDDI <= '1'; -- Tells logic in top level (T65.vhd) to route + -- the Din bus to the memory data latch (DL) + -- so that the branch offset is fetched. + + -- In microcycle T2, tell the logic in the top level to + -- add the offset. If the most significant byte of the + -- program counter (i.e. the current "page") does not need + -- updating, we are done here...the Break signal at the + -- T65.vhd level takes care of that... + when 2 => + + Jump <= "11"; -- Tell the PC Jump logic to use relative mode. + + PCAdd <= '1'; -- This tells the PC adder to update itself with + -- the current offset recently fetched from + -- memory. + + -- The following is microcycle T3 : + -- The program counter should be completely updated + -- on this cycle after the page cross is detected. + -- We don't need to do anything here... + when 3 => + + + when others => null; -- Do nothing. + + end case; + --}}} + + when "10001" | "10011" => + --{{{ + -- Zero Page Indirect Indexed (d),y + LCycle <= "101"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + LDBAL <= '1'; + BAAdd <= "01"; -- DB Inc + Set_Addr_To <= "10"; -- AD + when 3 => + Set_BusA_To <= "011"; -- Y + BAAdd <= "10"; -- BA Add + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 4 => + BAAdd <= "11"; -- BA Adj + if IR(7 downto 5) = "100" then + Write <= '1'; + else + BreakAtNA <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 5 => + when others => + end case; + --}}} + + when "10100" | "10101" | "10110" | "10111" => + --{{{ + -- Zero Page, X + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + -- Read-Modify-Write + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + ADAdd <= '1'; + Set_Addr_To <= "10"; -- AD + when 3 => + LDDI <= '1'; + Write <= '1'; + Set_Addr_To <= "10"; -- AD + when 4 => + LDALU <= '1'; + SaveP <= '1'; + Write <= '1'; + Set_Addr_To <= "10"; -- AD + when 5 => + when others => + end case; + else + LCycle <= "011"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + ADAdd <= '1'; + -- Added this check for Y reg. use... + if (IR(3 downto 0) = "0110") then + AddY <= '1'; + end if; + + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "10"; -- AD + when 3 => null; + when others => + end case; + end if; + --}}} + + when "11001" | "11011" => + --{{{ + -- Absolute Y + LCycle <= "100"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + Set_BusA_To <= "011"; -- Y + BAAdd <= "10"; -- BA Add + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 3 => + BAAdd <= "11"; -- BA adj + if IR(7 downto 5) = "100" then + Write <= '1'; + else + BreakAtNA <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 4 => + when others => + end case; + --}}} + + when "11100" | "11101" | "11110" | "11111" => + --{{{ + -- Absolute X + + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + -- Read-Modify-Write + LCycle <= "110"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + Set_BusA_To <= "010"; -- X + BAAdd <= "10"; -- BA Add + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 3 => + BAAdd <= "11"; -- BA adj + Set_Addr_To <= "11"; -- BA + when 4 => + LDDI <= '1'; + Write <= '1'; + Set_Addr_To <= "11"; -- BA + when 5 => + LDALU <= '1'; + SaveP <= '1'; + Write <= '1'; + Set_Addr_To <= "11"; -- BA + when 6 => + when others => + end case; + else + LCycle <= "100"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + -- mikej + -- special case 0xBE which uses Y reg as index!! + if (IR = "10111110") then + Set_BusA_To <= "011"; -- Y + else + Set_BusA_To <= "010"; -- X + end if; + BAAdd <= "10"; -- BA Add + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 3 => + BAAdd <= "11"; -- BA adj + if IR(7 downto 5) = "100" then + Write <= '1'; + else + BreakAtNA <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 4 => + when others => + end case; + end if; + --}}} + when others => + end case; + end process; + + process (IR, MCycle) + begin + -- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC + -- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC + case IR(1 downto 0) is + when "00" => + --{{{ + case IR(4 downto 2) is + when "000" | "001" | "011" => + case IR(7 downto 5) is + when "110" | "111" => + -- CP + ALU_Op <= "0110"; + when "101" => + -- LD + ALU_Op <= "0101"; + when "001" => + -- BIT + ALU_Op <= "1100"; + when others => + -- NOP/ST + ALU_Op <= "0100"; + end case; + when "010" => + case IR(7 downto 5) is + when "111" | "110" => + -- IN + ALU_Op <= "1111"; + when "100" => + -- DEY + ALU_Op <= "1110"; + when others => + -- LD + ALU_Op <= "1101"; + end case; + when "110" => + case IR(7 downto 5) is + when "100" => + -- TYA + ALU_Op <= "1101"; + when others => + ALU_Op <= "----"; + end case; + when others => + case IR(7 downto 5) is + when "101" => + -- LD + ALU_Op <= "1101"; + when others => + ALU_Op <= "0100"; + end case; + end case; + --}}} + when "01" => -- OR + --{{{ + ALU_Op(3) <= '0'; + ALU_Op(2 downto 0) <= IR(7 downto 5); + --}}} + when "10" => + --{{{ + ALU_Op(3) <= '1'; + ALU_Op(2 downto 0) <= IR(7 downto 5); + case IR(7 downto 5) is + when "000" => + if IR(4 downto 2) = "110" then + -- INC + ALU_Op <= "1111"; + end if; + when "001" => + if IR(4 downto 2) = "110" then + -- DEC + ALU_Op <= "1110"; + end if; + when "100" => + if IR(4 downto 2) = "010" then + -- TXA + ALU_Op <= "0101"; + else + ALU_Op <= "0100"; + end if; + when others => + end case; + --}}} + when others => + --{{{ + case IR(7 downto 5) is + when "100" => + ALU_Op <= "0100"; + when others => + if MCycle = "000" then + ALU_Op(3) <= '0'; + ALU_Op(2 downto 0) <= IR(7 downto 5); + else + ALU_Op(3) <= '1'; + ALU_Op(2 downto 0) <= IR(7 downto 5); + end if; + end case; + --}}} + end case; + end process; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T65/T65_Pack.vhd b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T65/T65_Pack.vhd new file mode 100644 index 00000000..e025e1bf --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T65/T65_Pack.vhd @@ -0,0 +1,117 @@ +-- **** +-- T65(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 Bugfixes by ehenciak added +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- 65xx compatible microprocessor core +-- +-- Version : 0246 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t65/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T65_Pack is + + constant Flag_C : integer := 0; + constant Flag_Z : integer := 1; + constant Flag_I : integer := 2; + constant Flag_D : integer := 3; + constant Flag_B : integer := 4; + constant Flag_1 : integer := 5; + constant Flag_V : integer := 6; + constant Flag_N : integer := 7; + + component T65_MCode + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816 + IR : in std_logic_vector(7 downto 0); + MCycle : in std_logic_vector(2 downto 0); + P : in std_logic_vector(7 downto 0); + LCycle : out std_logic_vector(2 downto 0); + ALU_Op : out std_logic_vector(3 downto 0); + Set_BusA_To : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P + Set_Addr_To : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA + Write_Data : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH + Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel + BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj + BreakAtNA : out std_logic; + ADAdd : out std_logic; + AddY : out std_logic; + PCAdd : out std_logic; + Inc_S : out std_logic; + Dec_S : out std_logic; + LDA : out std_logic; + LDP : out std_logic; + LDX : out std_logic; + LDY : out std_logic; + LDS : out std_logic; + LDDI : out std_logic; + LDALU : out std_logic; + LDAD : out std_logic; + LDBAL : out std_logic; + LDBAH : out std_logic; + SaveP : out std_logic; + Write : out std_logic + ); + end component; + + component T65_ALU + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816 + Op : in std_logic_vector(3 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + P_In : in std_logic_vector(7 downto 0); + P_Out : out std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T80/T80.vhd new file mode 100644 index 00000000..398fa0df --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T80/T80.vhd @@ -0,0 +1,1073 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 and Auto_Wait_t1 = '0' then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if T_Res = '1' then + Auto_Wait_t1 <= '0'; + else + Auto_Wait_t1 <= Auto_Wait or IORQ_i; + end if; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if (Auto_Wait = '1' and Auto_Wait_t2 = '0') nor + (IOWait = 1 and IORQ_i = '1' and Auto_Wait_t1 = '0') then + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T80/T80_ALU.vhd new file mode 100644 index 00000000..86fddce7 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T80/T80_ALU.vhd @@ -0,0 +1,351 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + OverFlow_v <= Carry_v xor Carry7_v; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T80/T80_MCode.vhd new file mode 100644 index 00000000..4cc30f35 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T80/T80_MCode.vhd @@ -0,0 +1,1934 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; +-- constant aNone : std_logic_vector(2 downto 0) := "000"; +-- constant aXY : std_logic_vector(2 downto 0) := "001"; +-- constant aIOA : std_logic_vector(2 downto 0) := "010"; +-- constant aSP : std_logic_vector(2 downto 0) := "011"; +-- constant aBC : std_logic_vector(2 downto 0) := "100"; +-- constant aDE : std_logic_vector(2 downto 0) := "101"; +-- constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0010"; + else + IncDec_16 <= "1010"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0010"; + else + IncDec_16 <= "1010"; + end if; + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T80/T80_Pack.vhd new file mode 100644 index 00000000..ac7d34da --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T80/T80_Pack.vhd @@ -0,0 +1,208 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T80/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T80/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T80/T80s.vhd b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T80/T80s.vhd new file mode 100644 index 00000000..5b612110 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/T80/T80s.vhd @@ -0,0 +1,190 @@ +-- +-- Z80 compatible microprocessor core, synchronous top level +-- Different timing than the original z80 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed read with wait +-- +-- 0211 : Fixed interrupt cycle +-- +-- 0235 : Updated for T80 interface change +-- +-- 0236 : Added T2Write generic +-- +-- 0237 : Fixed T2Write with wait state +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80s is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2 + IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80s; + +architecture rtl of T80s is + + signal CEN : std_logic; + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + CEN <= '1'; + + u0 : T80 + generic map( + Mode => Mode, + IOWait => IOWait) + port map( + CEN => CEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if T2Write = 0 then + if TState = "010" and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + else + if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end process; + +end; diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/YM2149_linmix_sep.vhd b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/YM2149_linmix_sep.vhd new file mode 100644 index 00000000..6ed2498a --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/YM2149_linmix_sep.vhd @@ -0,0 +1,574 @@ +-- changes for seperate audio outputs and enable now enables cpu access as well +-- +-- A simulation model of YM2149 (AY-3-8910 with bells on) + +-- Copyright (c) MikeJ - Jan 2005 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- +-- Clues from MAME sound driver and Kazuhiro TSUJIKAWA +-- +-- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V) +-- vol 15 .. 0 +-- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132 +-- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order +-- to produced all the required values. +-- (The first part of the curve is a bit steeper and the last bit is more linear than expected) +-- +-- NOTE, this component uses LINEAR mixing of the three analogue channels, and is only +-- accurate for designs where the outputs are buffered and not simply wired together. +-- The ouput level is more complex in that case and requires a larger table. + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity YM2149 is + port ( + -- data bus + I_DA : in std_logic_vector(7 downto 0); + O_DA : out std_logic_vector(7 downto 0); + O_DA_OE_L : out std_logic; + -- control + I_A9_L : in std_logic; + I_A8 : in std_logic; + I_BDIR : in std_logic; + I_BC2 : in std_logic; + I_BC1 : in std_logic; + I_SEL_L : in std_logic; + + O_AUDIO : out std_logic_vector(7 downto 0); + O_CHAN : out std_logic_vector(1 downto 0); + -- port a + I_IOA : in std_logic_vector(7 downto 0); + O_IOA : out std_logic_vector(7 downto 0); + O_IOA_OE_L : out std_logic; + -- port b + I_IOB : in std_logic_vector(7 downto 0); + O_IOB : out std_logic_vector(7 downto 0); + O_IOB_OE_L : out std_logic; + + ENA : in std_logic; -- clock enable for higher speed operation + RESET_L : in std_logic; + CLK : in std_logic -- note 6 Mhz + ); +end; + +architecture RTL of YM2149 is + type array_16x8 is array (0 to 15) of std_logic_vector( 7 downto 0); + type array_3x12 is array (1 to 3) of std_logic_vector(11 downto 0); + + signal cnt_div : std_logic_vector(3 downto 0) := (others => '0'); + signal cnt_div_t1 : std_logic_vector(3 downto 0); + signal noise_div : std_logic := '0'; + signal ena_div : std_logic; + signal ena_div_noise : std_logic; + signal poly17 : std_logic_vector(16 downto 0) := (others => '0'); + + -- registers + signal addr : std_logic_vector(7 downto 0); + signal busctrl_addr : std_logic; + signal busctrl_we : std_logic; + signal busctrl_re : std_logic; + + signal reg : array_16x8; + signal env_reset : std_logic; + signal ioa_inreg : std_logic_vector(7 downto 0); + signal iob_inreg : std_logic_vector(7 downto 0); + + signal noise_gen_cnt : std_logic_vector(4 downto 0); + signal noise_gen_op : std_logic; + signal tone_gen_cnt : array_3x12 := (others => (others => '0')); + signal tone_gen_op : std_logic_vector(3 downto 1) := "000"; + + signal env_gen_cnt : std_logic_vector(15 downto 0); + signal env_ena : std_logic; + signal env_hold : std_logic; + signal env_inc : std_logic; + signal env_vol : std_logic_vector(4 downto 0); + + signal tone_ena_l : std_logic; + signal tone_src : std_logic; + signal noise_ena_l : std_logic; + signal chan_vol : std_logic_vector(4 downto 0); + + signal dac_amp : std_logic_vector(7 downto 0); +begin + -- cpu i/f + p_busdecode : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8) + variable cs : std_logic; + variable sel : std_logic_vector(2 downto 0); + begin + -- BDIR BC2 BC1 MODE + -- 0 0 0 inactive + -- 0 0 1 address + -- 0 1 0 inactive + -- 0 1 1 read + -- 1 0 0 address + -- 1 0 1 inactive + -- 1 1 0 write + -- 1 1 1 read + busctrl_addr <= '0'; + busctrl_we <= '0'; + busctrl_re <= '0'; + + cs := '0'; + if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then + cs := '1'; + end if; + + sel := (I_BDIR & I_BC2 & I_BC1); + case sel is + when "000" => null; + when "001" => busctrl_addr <= '1'; + when "010" => null; + when "011" => busctrl_re <= cs; + when "100" => busctrl_addr <= '1'; + when "101" => null; + when "110" => busctrl_we <= cs; + when "111" => busctrl_addr <= '1'; + when others => null; + end case; + end process; + + p_oe : process(busctrl_re) + begin + -- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns + O_DA_OE_L <= not (busctrl_re); + end process; + + -- + -- CLOCKED + -- + p_waddr : process(RESET_L, CLK) + begin + -- looks like registers are latches in real chip, but the address is caught at the end of the address state. + if (RESET_L = '0') then + addr <= (others => '0'); + elsif rising_edge(CLK) then + if (ENA = '1') then + if (busctrl_addr = '1') then + addr <= I_DA; + end if; + end if; + end if; + end process; + + p_wdata : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + reg <= (others => (others => '0')); + env_reset <= '1'; + elsif rising_edge(CLK) then + if (ENA = '1') then + env_reset <= '0'; + if (busctrl_we = '1') then + case addr(3 downto 0) is + when x"0" => reg(0) <= I_DA; + when x"1" => reg(1) <= I_DA; + when x"2" => reg(2) <= I_DA; + when x"3" => reg(3) <= I_DA; + when x"4" => reg(4) <= I_DA; + when x"5" => reg(5) <= I_DA; + when x"6" => reg(6) <= I_DA; + when x"7" => reg(7) <= I_DA; + when x"8" => reg(8) <= I_DA; + when x"9" => reg(9) <= I_DA; + when x"A" => reg(10) <= I_DA; + when x"B" => reg(11) <= I_DA; + when x"C" => reg(12) <= I_DA; + when x"D" => reg(13) <= I_DA; env_reset <= '1'; + when x"E" => reg(14) <= I_DA; + when x"F" => reg(15) <= I_DA; + when others => null; + end case; + end if; + end if; + end if; + end process; + + p_rdata : process(busctrl_re, addr, reg, ioa_inreg, iob_inreg) + begin + O_DA <= (others => '0'); -- 'X' + if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator + case addr(3 downto 0) is + when x"0" => O_DA <= reg(0) ; + when x"1" => O_DA <= "0000" & reg(1)(3 downto 0) ; + when x"2" => O_DA <= reg(2) ; + when x"3" => O_DA <= "0000" & reg(3)(3 downto 0) ; + when x"4" => O_DA <= reg(4) ; + when x"5" => O_DA <= "0000" & reg(5)(3 downto 0) ; + when x"6" => O_DA <= "000" & reg(6)(4 downto 0) ; + when x"7" => O_DA <= reg(7) ; + when x"8" => O_DA <= "000" & reg(8)(4 downto 0) ; + when x"9" => O_DA <= "000" & reg(9)(4 downto 0) ; + when x"A" => O_DA <= "000" & reg(10)(4 downto 0) ; + when x"B" => O_DA <= reg(11); + when x"C" => O_DA <= reg(12); + when x"D" => O_DA <= "0000" & reg(13)(3 downto 0); + when x"E" => if (reg(7)(6) = '0') then -- input + O_DA <= ioa_inreg; + else + O_DA <= reg(14); -- read output reg + end if; + when x"F" => if (Reg(7)(7) = '0') then + O_DA <= iob_inreg; + else + O_DA <= reg(15); + end if; + when others => null; + end case; + end if; + end process; + -- + p_divider : process + begin + wait until rising_edge(CLK); + -- / 8 when SEL is high and /16 when SEL is low + if (ENA = '1') then + ena_div <= '0'; + ena_div_noise <= '0'; + if (cnt_div = "0000") then + cnt_div <= (not I_SEL_L) & "111"; + ena_div <= '1'; + + noise_div <= not noise_div; + if (noise_div = '1') then + ena_div_noise <= '1'; + end if; + else + cnt_div <= cnt_div - "1"; + end if; + end if; + end process; + + p_noise_gen : process + variable noise_gen_comp : std_logic_vector(4 downto 0); + variable poly17_zero : std_logic; + begin + wait until rising_edge(CLK); + if (reg(6)(4 downto 0) = "00000") then + noise_gen_comp := "00000"; + else + noise_gen_comp := (reg(6)(4 downto 0) - "1"); + end if; + + poly17_zero := '0'; + if (poly17 = "00000000000000000") then poly17_zero := '1'; end if; + + if (ENA = '1') then + if (ena_div_noise = '1') then -- divider ena + + if (noise_gen_cnt >= noise_gen_comp) then + noise_gen_cnt <= "00000"; + poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1); + else + noise_gen_cnt <= (noise_gen_cnt + "1"); + end if; + end if; + end if; + end process; + noise_gen_op <= poly17(0); + + p_tone_gens : process + variable tone_gen_freq : array_3x12; + variable tone_gen_comp : array_3x12; + begin + wait until rising_edge(CLK); + -- looks like real chips count up - we need to get the Exact behaviour .. + tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0); + tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2); + tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4); + -- period 0 = period 1 + for i in 1 to 3 loop + if (tone_gen_freq(i) = x"000") then + tone_gen_comp(i) := x"000"; + else + tone_gen_comp(i) := (tone_gen_freq(i) - "1"); + end if; + end loop; + + if (ENA = '1') then + for i in 1 to 3 loop + if (ena_div = '1') then -- divider ena + + if (tone_gen_cnt(i) >= tone_gen_comp(i)) then + tone_gen_cnt(i) <= x"000"; + tone_gen_op(i) <= not tone_gen_op(i); + else + tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1"); + end if; + end if; + end loop; + end if; + end process; + + p_envelope_freq : process + variable env_gen_freq : std_logic_vector(15 downto 0); + variable env_gen_comp : std_logic_vector(15 downto 0); + begin + wait until rising_edge(CLK); + env_gen_freq := reg(12) & reg(11); + -- envelope freqs 1 and 0 are the same. + if (env_gen_freq = x"0000") then + env_gen_comp := x"0000"; + else + env_gen_comp := (env_gen_freq - "1"); + end if; + + if (ENA = '1') then + env_ena <= '0'; + if (ena_div = '1') then -- divider ena + if (env_gen_cnt >= env_gen_comp) then + env_gen_cnt <= x"0000"; + env_ena <= '1'; + else + env_gen_cnt <= (env_gen_cnt + "1"); + end if; + end if; + end if; + end process; + + p_envelope_shape : process(env_reset, reg, CLK) + variable is_bot : boolean; + variable is_bot_p1 : boolean; + variable is_top_m1 : boolean; + variable is_top : boolean; + begin + -- envelope shapes + -- C AtAlH + -- 0 0 x x \___ + -- + -- 0 1 x x /___ + -- + -- 1 0 0 0 \\\\ + -- + -- 1 0 0 1 \___ + -- + -- 1 0 1 0 \/\/ + -- ___ + -- 1 0 1 1 \ + -- + -- 1 1 0 0 //// + -- ___ + -- 1 1 0 1 / + -- + -- 1 1 1 0 /\/\ + -- + -- 1 1 1 1 /___ + if (env_reset = '1') then + -- load initial state + if (reg(13)(2) = '0') then -- attack + env_vol <= "11111"; + env_inc <= '0'; -- -1 + else + env_vol <= "00000"; + env_inc <= '1'; -- +1 + end if; + env_hold <= '0'; + + elsif rising_edge(CLK) then + is_bot := (env_vol = "00000"); + is_bot_p1 := (env_vol = "00001"); + is_top_m1 := (env_vol = "11110"); + is_top := (env_vol = "11111"); + + if (ENA = '1') then + if (env_ena = '1') then + if (env_hold = '0') then + if (env_inc = '1') then + env_vol <= (env_vol + "00001"); + else + env_vol <= (env_vol + "11111"); + end if; + end if; + + -- envelope shape control. + if (reg(13)(3) = '0') then + if (env_inc = '0') then -- down + if is_bot_p1 then env_hold <= '1'; end if; + else + if is_top then env_hold <= '1'; end if; + end if; + else + if (reg(13)(0) = '1') then -- hold = 1 + if (env_inc = '0') then -- down + if (reg(13)(1) = '1') then -- alt + if is_bot then env_hold <= '1'; end if; + else + if is_bot_p1 then env_hold <= '1'; end if; + end if; + else + if (reg(13)(1) = '1') then -- alt + if is_top then env_hold <= '1'; end if; + else + if is_top_m1 then env_hold <= '1'; end if; + end if; + end if; + + elsif (reg(13)(1) = '1') then -- alternate + if (env_inc = '0') then -- down + if is_bot_p1 then env_hold <= '1'; end if; + if is_bot then env_hold <= '0'; env_inc <= '1'; end if; + else + if is_top_m1 then env_hold <= '1'; end if; + if is_top then env_hold <= '0'; env_inc <= '0'; end if; + end if; + end if; + + end if; + end if; + end if; + end if; + end process; + + p_chan_mixer : process(cnt_div, reg, tone_gen_op) + begin + tone_ena_l <= '1'; tone_src <= '1'; + noise_ena_l <= '1'; chan_vol <= "00000"; + case cnt_div(1 downto 0) is + when "00" => + tone_ena_l <= reg(7)(0); tone_src <= tone_gen_op(1); chan_vol <= reg(8)(4 downto 0); + noise_ena_l <= reg(7)(3); + when "01" => + tone_ena_l <= reg(7)(1); tone_src <= tone_gen_op(2); chan_vol <= reg(9)(4 downto 0); + noise_ena_l <= reg(7)(4); + when "10" => + tone_ena_l <= reg(7)(2); tone_src <= tone_gen_op(3); chan_vol <= reg(10)(4 downto 0); + noise_ena_l <= reg(7)(5); + when "11" => null; -- tone gen outputs become valid on this clock + when others => null; + end case; + end process; + + p_op_mixer : process + variable chan_mixed : std_logic; + variable chan_amp : std_logic_vector(4 downto 0); + begin + wait until rising_edge(CLK); + if (ENA = '1') then + + chan_mixed := (tone_ena_l or tone_src) and (noise_ena_l or noise_gen_op); + + chan_amp := (others => '0'); + if (chan_mixed = '1') then + if (chan_vol(4) = '0') then + if (chan_vol(3 downto 0) = "0000") then -- nothing is easy ! make sure quiet is quiet + chan_amp := "00000"; + else + chan_amp := chan_vol(3 downto 0) & '1'; -- make sure level 31 (env) = level 15 (tone) + end if; + else + chan_amp := env_vol(4 downto 0); + end if; + end if; + + dac_amp <= x"00"; + case chan_amp is + when "11111" => dac_amp <= x"FF"; + when "11110" => dac_amp <= x"D9"; + when "11101" => dac_amp <= x"BA"; + when "11100" => dac_amp <= x"9F"; + when "11011" => dac_amp <= x"88"; + when "11010" => dac_amp <= x"74"; + when "11001" => dac_amp <= x"63"; + when "11000" => dac_amp <= x"54"; + when "10111" => dac_amp <= x"48"; + when "10110" => dac_amp <= x"3D"; + when "10101" => dac_amp <= x"34"; + when "10100" => dac_amp <= x"2C"; + when "10011" => dac_amp <= x"25"; + when "10010" => dac_amp <= x"1F"; + when "10001" => dac_amp <= x"1A"; + when "10000" => dac_amp <= x"16"; + when "01111" => dac_amp <= x"13"; + when "01110" => dac_amp <= x"10"; + when "01101" => dac_amp <= x"0D"; + when "01100" => dac_amp <= x"0B"; + when "01011" => dac_amp <= x"09"; + when "01010" => dac_amp <= x"08"; + when "01001" => dac_amp <= x"07"; + when "01000" => dac_amp <= x"06"; + when "00111" => dac_amp <= x"05"; + when "00110" => dac_amp <= x"04"; + when "00101" => dac_amp <= x"03"; + when "00100" => dac_amp <= x"03"; + when "00011" => dac_amp <= x"02"; + when "00010" => dac_amp <= x"02"; + when "00001" => dac_amp <= x"01"; + when "00000" => dac_amp <= x"00"; + when others => null; + end case; + + cnt_div_t1 <= cnt_div; + end if; + end process; + + p_audio_output : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + O_AUDIO <= (others => '0'); + O_CHAN <= (others => '0'); + elsif rising_edge(CLK) then + + if (ENA = '1') then + O_AUDIO <= dac_amp(7 downto 0); + O_CHAN <= cnt_div_t1(1 downto 0); + end if; + end if; + end process; + + p_io_ports : process(reg) + begin + O_IOA <= reg(14); + O_IOA_OE_L <= not reg(7)(6); + O_IOB <= reg(15); + O_IOB_OE_L <= not reg(7)(7); + end process; + + p_io_ports_inreg : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then -- resync + ioa_inreg <= I_IOA; + iob_inreg <= I_IOB; + end if; + end process; +end architecture RTL; diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/build_id.tcl b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/dpram.vhd b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..cda0f3cd --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/dpram.vhd @@ -0,0 +1,123 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY dpram IS + GENERIC + ( + init_file : string := ""; + numwords_a : natural := 0; -- not used any more + widthad_a : natural; + width_a : natural := 8; + outdata_reg_a : string := "UNREGISTERED"; + outdata_reg_b : string := "UNREGISTERED" + ); + PORT + ( + address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + clock_a : IN STD_LOGIC ; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + wren_a : IN STD_LOGIC := '1'; + wren_b : IN STD_LOGIC := '1'; + q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); +END dpram; + + +ARCHITECTURE SYN OF dpram IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + + COMPONENT altsyncram + GENERIC ( + address_reg_b : STRING; + clock_enable_input_a : STRING; + clock_enable_input_b : STRING; + clock_enable_output_a : STRING; + clock_enable_output_b : STRING; + indata_reg_b : STRING; + init_file : STRING; + intended_device_family : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + numwords_b : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_aclr_b : STRING; + outdata_reg_a : STRING; + outdata_reg_b : STRING; + power_up_uninitialized : STRING; + widthad_a : NATURAL; + widthad_b : NATURAL; + width_a : NATURAL; + width_b : NATURAL; + width_byteena_a : NATURAL; + width_byteena_b : NATURAL; + wrcontrol_wraddress_reg_b : STRING + ); + PORT ( + wren_a : IN STD_LOGIC ; + clock0 : IN STD_LOGIC ; + wren_b : IN STD_LOGIC ; + clock1 : IN STD_LOGIC ; + address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q_a <= sub_wire0(width_a-1 DOWNTO 0); + q_b <= sub_wire1(width_a-1 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + address_reg_b => "CLOCK1", + clock_enable_input_a => "BYPASS", + clock_enable_input_b => "BYPASS", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", + init_file => init_file, + intended_device_family => "Cyclone III", + lpm_type => "altsyncram", + numwords_a => 2**widthad_a, + numwords_b => 2**widthad_a, + operation_mode => "BIDIR_DUAL_PORT", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => outdata_reg_a, + outdata_reg_b => outdata_reg_b, + power_up_uninitialized => "FALSE", + widthad_a => widthad_a, + widthad_b => widthad_a, + width_a => width_a, + width_b => width_a, + width_byteena_a => 1, + width_byteena_b => 1, + wrcontrol_wraddress_reg_b => "CLOCK1" + ) + PORT MAP ( + wren_a => wren_a, + clock0 => clock_a, + wren_b => wren_b, + clock1 => clock_b, + address_a => address_a, + address_b => address_b, + data_a => data_a, + data_b => data_b, + q_a => sub_wire0, + q_b => sub_wire1 + ); + +END SYN; diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/gen_ram.vhd b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/gen_ram.vhd new file mode 100644 index 00000000..f1a95608 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/gen_ram.vhd @@ -0,0 +1,84 @@ +-- ----------------------------------------------------------------------- +-- +-- Syntiac's generic VHDL support files. +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- +-- Modified April 2016 by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +-- Remove address register when writing +-- +-- ----------------------------------------------------------------------- +-- +-- gen_rwram.vhd +-- +-- ----------------------------------------------------------------------- +-- +-- generic ram. +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +entity gen_ram is + generic ( + dWidth : integer := 8; + aWidth : integer := 10 + ); + port ( + clk : in std_logic; + we : in std_logic; + addr : in std_logic_vector((aWidth-1) downto 0); + d : in std_logic_vector((dWidth-1) downto 0); + q : out std_logic_vector((dWidth-1) downto 0) + ); +end entity; + +-- ----------------------------------------------------------------------- + +architecture rtl of gen_ram is + subtype addressRange is integer range 0 to ((2**aWidth)-1); + type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0); + signal ram: ramDef; + + signal rAddrReg : std_logic_vector((aWidth-1) downto 0); + signal qReg : std_logic_vector((dWidth-1) downto 0); +begin +-- ----------------------------------------------------------------------- +-- Signals to entity interface +-- ----------------------------------------------------------------------- +-- q <= qReg; + +-- ----------------------------------------------------------------------- +-- Memory write +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if we = '1' then + ram(to_integer(unsigned(addr))) <= d; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Memory read +-- ----------------------------------------------------------------------- +process(clk) + begin + if rising_edge(clk) then +-- qReg <= ram(to_integer(unsigned(rAddrReg))); +-- rAddrReg <= addr; +---- qReg <= ram(to_integer(unsigned(addr))); + q <= ram(to_integer(unsigned(addr))); + end if; + end process; +--q <= ram(to_integer(unsigned(addr))); +end architecture; + diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/loc_hvgen.v b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/loc_hvgen.v new file mode 100644 index 00000000..348647b8 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/loc_hvgen.v @@ -0,0 +1,36 @@ +module loc_hvgen +( + output [8:0] HPOS, + output [8:0] VPOS, + input PCLK, + output reg HBLK = 1, + output reg VBLK = 1, + output reg HSYN = 1, + output reg VSYN = 1 +); + +reg [8:0] hcnt = 0; +reg [8:0] vcnt = 0; + +assign HPOS = hcnt; +assign VPOS = vcnt; + +always @(posedge PCLK) begin + case (hcnt) + 287: begin HBLK <= 1; HSYN <= 0; hcnt <= hcnt+1; end + 311: begin HSYN <= 1; hcnt <= hcnt+1; end + 383: begin + HBLK <= 0; HSYN <= 1; hcnt <= 0; + case (vcnt) + 223: begin VBLK <= 1; vcnt <= vcnt+1; end + 226: begin VSYN <= 0; vcnt <= vcnt+1; end + 233: begin VSYN <= 1; vcnt <= vcnt+1; end + 242: begin VBLK <= 0; vcnt <= 0; end + default: vcnt <= vcnt+1; + endcase + end + default: hcnt <= hcnt+1; + endcase +end + +endmodule \ No newline at end of file diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/loc_sound.vhd b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/loc_sound.vhd new file mode 100644 index 00000000..bdcf3db4 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/loc_sound.vhd @@ -0,0 +1,425 @@ +--------------------------------------------------------------------------------- +-- burnin rubber sound by Dar (darfpga@aol.fr) (05/12/2017) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- +-- gen_ram.vhd & io_ps2_keyboard +-------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +--------------------------------------------------------------------------------- +-- T65(b) core.Ver 301 by MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +--------------------------------------------------------------------------------- +-- YM2149 (AY-3-8910) +-- Copyright (c) MikeJ - Jan 2005 +--------------------------------------------------------------------------------- +-- Use burnin_rubber_de10_lite.sdc to compile (Timequest constraints) +-- /!\ +-- Don't forget to set device configuration mode with memory initialization +-- (Assignments/Device/Pin options/Configuration mode) +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity loc_sound is +port +( + clock_12 : in std_logic; + reset : in std_logic; + + sound_req : in std_logic; + sound_code_in : in std_logic_vector(7 downto 0); + sound_timing : in std_logic; + + audio_out : out std_logic_vector(10 downto 0); + + dbg_cpu_addr: out std_logic_vector(15 downto 0) + ); +end loc_sound; + +architecture syn of loc_sound is + + -- clocks, reset + signal clock_12n : std_logic; + signal clock_div1 : std_logic_vector(8 downto 0) := (others =>'0'); + signal clock_div2 : std_logic_vector(4 downto 0) := (others =>'0'); + signal clock_500K : std_logic; + signal ayx_clock : std_logic; + signal reset_n : std_logic; + + -- cpu signals + signal cpu_addr : std_logic_vector(23 downto 0); + signal cpu_di : std_logic_vector( 7 downto 0); + signal cpu_di_dec : std_logic_vector( 7 downto 0); + signal cpu_do : std_logic_vector( 7 downto 0); + signal cpu_rw_n : std_logic; + signal cpu_nmi_n : std_logic; + signal cpu_irq_n : std_logic; + signal cpu_sync : std_logic; + + -- program rom signals + signal prog_rom_cs : std_logic; + signal prog_rom_do : std_logic_vector(7 downto 0); + + -- working ram signals + signal wram_cs : std_logic; + signal wram_we : std_logic; + signal wram_do : std_logic_vector(7 downto 0); + + -- sound req management + signal nmi_reg : std_logic; + signal nmi_reg_cs : std_logic; + signal nmi_reg_we : std_logic; + signal sound_code : std_logic_vector(7 downto 0); + signal sound_code_cs : std_logic; + + -- ay-3-8910 signal + signal ay1_bc1 : std_logic; + signal ay1_bdir : std_logic; + signal ay1_audio_chan : std_logic_vector(1 downto 0); + signal ay1_audio_muxed: std_logic_vector(7 downto 0); + signal ay1_chan_a: std_logic_vector(7 downto 0); + signal ay1_chan_b: std_logic_vector(7 downto 0); + signal ay1_chan_c: std_logic_vector(7 downto 0); + + signal ay2_bc1 : std_logic; + signal ay2_bdir : std_logic; + signal ay2_audio_chan : std_logic_vector(1 downto 0); + signal ay2_audio_muxed: std_logic_vector(7 downto 0); + signal ay2_chan_a: std_logic_vector(7 downto 0); + signal ay2_chan_b: std_logic_vector(7 downto 0); + signal ay2_chan_c: std_logic_vector(7 downto 0); + + -- digital filtering AY2 channel A + signal uin : integer range -256 to 255; + signal u3 : integer range -32768 to 32767; + signal u4 : integer range -32768 to 32767; + signal du3 : integer range -32768*4096 to 32767*4096; + signal du4 : integer range -32768*4096 to 32767*4096; + signal uout : integer range -32768 to 32767; + signal uout_lim : integer range -128 to 127; + +begin + +process (clock_12, cpu_sync) +begin + if rising_edge(clock_12) then + if cpu_sync = '1' then + dbg_cpu_addr <= cpu_addr(15 downto 0); + end if; + end if; +end process; + +reset_n <= not reset; +clock_12n <= not clock_12; + +process (clock_12, reset) + begin + if reset='1' then + clock_div1 <= (others => '0'); + clock_div2 <= (others => '0'); + else + if rising_edge(clock_12) then + if clock_div1 = "111111111" then -- divide by 512 (23.437kHz) + clock_div1 <= "000000000"; + else + clock_div1 <= clock_div1 + '1'; + end if; + if clock_div2 = "10111" then -- divide by 24 + clock_div2 <= "00000"; + else + clock_div2 <= clock_div2 + '1'; + end if; + end if; + end if; +end process; + +clock_500K <= clock_div2(4); --12MHz/24 = 500kHz +ayx_clock <= clock_div1(2); --12MHz/8 = 1.5MHz + +--static ADDRESS_MAP_START( audio_map, AS_PROGRAM, 8, btime_state ) +-- AM_RANGE(0x0000, 0x03ff) AM_MIRROR(0x1c00) AM_RAM AM_SHARE("audio_rambase") +-- AM_RANGE(0x2000, 0x3fff) AM_DEVWRITE("ay1", ay8910_device, data_w) +-- AM_RANGE(0x4000, 0x5fff) AM_DEVWRITE("ay1", ay8910_device, address_w) +-- AM_RANGE(0x6000, 0x7fff) AM_DEVWRITE("ay2", ay8910_device, data_w) +-- AM_RANGE(0x8000, 0x9fff) AM_DEVWRITE("ay2", ay8910_device, address_w) +-- AM_RANGE(0xa000, 0xbfff) AM_READ(audio_command_r) +-- AM_RANGE(0xc000, 0xdfff) AM_WRITE(audio_nmi_enable_w) +-- AM_RANGE(0xe000, 0xefff) AM_MIRROR(0x1000) AM_ROM +--ADDRESS_MAP_END + +-- chip select +wram_cs <= '1' when cpu_addr(15 downto 13) = "000" else '0'; -- working ram 0000-07ff .. 1fff +ay1_bc1 <= '1' when cpu_addr(15 downto 13) = "010" else '0'; +ay1_bdir <= '1' when cpu_addr(15 downto 13) = "001" or ay1_bc1 = '1' else '0'; +ay2_bc1 <= '1' when cpu_addr(15 downto 13) = "100" else '0'; +ay2_bdir <= '1' when cpu_addr(15 downto 13) = "011" or ay2_bc1 = '1' else '0'; +sound_code_cs <= '1' when cpu_addr(15 downto 13) = "101" else '0'; +nmi_reg_cs <= '1' when cpu_addr(15 downto 13) = "110" else '0'; +prog_rom_cs <= '1' when cpu_addr(15 downto 13) = "111" else '0'; + +-- write enable +wram_we <= '1' when wram_cs = '1' and cpu_rw_n = '0' else '0'; +nmi_reg_we <= '1' when nmi_reg_cs = '1' and cpu_rw_n = '0' else '0'; + +-- cpu di mux +cpu_di <= wram_do when wram_cs = '1' else + prog_rom_do when prog_rom_cs = '1' else + sound_code when sound_code_cs = '1' else + X"FF"; + +-- regsiter sound code and irq management +process (clock_12) +begin + if rising_edge(clock_12) then + if sound_req = '1' then + sound_code <= sound_code_in; + cpu_irq_n <= '0'; + end if; + if sound_code_cs = '1' then + cpu_irq_n <= '1'; + end if; + end if; +end process; + +-- nmi autorisation management +process (reset, clock_12) +begin + if reset = '1' then + nmi_reg <= '0'; + else + if rising_edge(clock_12) then + if nmi_reg_we = '1' then + nmi_reg <= cpu_do(0); + end if; + end if; + end if; +end process; + +-- nmi +cpu_nmi_n <= '0' when nmi_reg = '1' and sound_timing = '1' else '1'; + +-- demux AY chips output +process (ayx_clock) +begin + if rising_edge(ayx_clock) then + if ay1_audio_chan = "00" then ay1_chan_a <= ay1_audio_muxed; end if; + if ay1_audio_chan = "01" then ay1_chan_b <= ay1_audio_muxed; end if; + if ay1_audio_chan = "10" then ay1_chan_c <= ay1_audio_muxed; end if; + if ay2_audio_chan = "00" then ay2_chan_a <= ay2_audio_muxed; end if; + if ay2_audio_chan = "01" then ay2_chan_b <= ay2_audio_muxed; end if; + if ay2_audio_chan = "10" then ay2_chan_c <= ay2_audio_muxed; end if; + end if; +end process; + +-- AOP Rauch passe bande filter +-- +-- ----------o------------ +-- u4^ | | | +-- | --- C4 | | R5 | +-- | --- | | | +-- | | C3 | | +-- --| R1 |----o----||---o------|\ | +-- ^ | ------> u3 | \__o--- +-- | | | / ^ +-- |uin | | R2 --|/ | +-- | | | | | uout +-- | | | | +-- ------------o--------------o---------- +-- +-- +-- i1 = (sin+u3)/R1 +-- i2 = -u3/R2 +-- i3 = (u4-u3)/R5 +-- i4 = i2-i1-i3 +-- +-- u3(t+dt) = u3(t) + i3(t)*dt/C3; +-- u4(t+dt) = u4(t) + i4(t)*dt/C4; + +-- uout = u4-u3 + +-- R1 = 5000; +-- R2 = 10000; +-- C3 = 0.068e-6; +-- C4 = 0.068e-6; +-- R5 = 47000; +-- +-- dt = 1/f_ech = 1/23437 +-- dt/C3 = dt/C4 = 627 +-- +-- (i3(t)*dt/C3)*8192 = du3*8192 = ((u4-u3)/47000*627)*8192 +-- = (u4-u3)*109 +-- +-- (i4(t)*dt/C4)*8192 = du4*8192 = (-u3/10000 -(uin+u3)/5000 -(u4-u3)/47000)*627*8192 +-- = -u3(514+1027-109) - uin*1027 - u4*109 +-- = -(u4*109 + u3*1432 + uin*1027) +-- + +-- down sample to 23.437kHz and filter AY2 channel A +uin <= to_integer(unsigned(ay2_chan_a)); + +process (clock_12) +begin + if rising_edge(clock_12) then + + if clock_div1 = "000000000" then + du3 <= u4*109 - u3*109; + du4 <= u4*109 + u3*1432 + uin*1027*16; -- add gain(16) to uin + end if; + + if clock_div1 = "000000001" then + u3 <= u3 + du3/8192; + u4 <= u4 - du4/8192; + end if; + + if clock_div1 = "000000010" then + uout <= (u4 - u3) / 8; -- adjust output gain + end if; + + -- limit signed dynamique before return to unsigned + if clock_div1 = "000000011" then + if uout > 127 then + uout_lim <= 127; + elsif uout < -127 then + uout_lim <= -127; + else + uout_lim <= uout; + end if; + end if; + + if clock_div1 = "000000100" then + + audio_out <= ("000"&ay1_chan_a(7 downto 0)) + + ("000"&ay1_chan_b(7 downto 0)) + + ("000"&ay1_chan_c(7 downto 0)) + + ("000"&std_logic_vector(to_unsigned(uout_lim+128,8)))+ + ("000"&ay2_chan_b(7 downto 0)) + + ("000"&ay2_chan_c(7 downto 0)); + end if; + + end if; +end process; + +--------------------------- +-- components +--------------------------- + +cpu_inst : entity work.T65 +port map +( + Mode => "00", -- 6502 + Res_n => reset_n, + Enable => '1', + Clk => clock_500K, + Rdy => '1', + Abort_n => '1', + IRQ_n => cpu_irq_n, + NMI_n => cpu_nmi_n, + SO_n => '1',--cpu_so_n, + R_W_n => cpu_rw_n, + Sync => cpu_sync, -- open + EF => open, + MF => open, + XF => open, + ML_n => open, + VP_n => open, + VDA => open, + VPA => open, + A => cpu_addr, + DI => cpu_di, + DO => cpu_do +); + +-- working ram +wram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 11) +port map( + clk => clock_12n, + we => wram_we, + addr => cpu_addr(10 downto 0), + d => cpu_do, + q => wram_do +); + +-- program rom +program_rom: entity work.loc_snd_rom +port map( + clk => clock_12n, + addr => cpu_addr(11 downto 0), + data => prog_rom_do +); + +-- AY-3-8910 #1 +ay_3_8910_1 : entity work.YM2149 +port map( + -- data bus + I_DA => cpu_do, -- in std_logic_vector(7 downto 0); + O_DA => open, -- out std_logic_vector(7 downto 0); + O_DA_OE_L => open, -- out std_logic; + -- control + I_A9_L => '0', -- in std_logic; + I_A8 => '1', -- in std_logic; + I_BDIR => ay1_bdir, -- in std_logic; + I_BC2 => '1', -- in std_logic; + I_BC1 => ay1_bc1, -- in std_logic; + I_SEL_L => '1', -- in std_logic; + + O_AUDIO => ay1_audio_muxed, -- out std_logic_vector(7 downto 0); + O_CHAN => ay1_audio_chan, -- out std_logic_vector(1 downto 0); + + -- port a + I_IOA => X"00", -- in std_logic_vector(7 downto 0); + O_IOA => open, -- out std_logic_vector(7 downto 0); + O_IOA_OE_L => open, -- out std_logic; + -- port b + I_IOB => X"00", -- in std_logic_vector(7 downto 0); + O_IOB => open, -- out std_logic_vector(7 downto 0); + O_IOB_OE_L => open, -- out std_logic; + + ENA => '1', -- in std_logic; -- clock enable for higher speed operation + RESET_L => reset_n, -- in std_logic; + CLK => ayx_clock -- in std_logic -- note 6 Mhz +); + +-- AY-3-8910 #2 +ay_3_8910_2 : entity work.YM2149 +port map( + -- data bus + I_DA => cpu_do, -- in std_logic_vector(7 downto 0); + O_DA => open, -- out std_logic_vector(7 downto 0); + O_DA_OE_L => open, -- out std_logic; + -- control + I_A9_L => '0', -- in std_logic; + I_A8 => '1', -- in std_logic; + I_BDIR => ay2_bdir, -- in std_logic; + I_BC2 => '1', -- in std_logic; + I_BC1 => ay2_bc1, -- in std_logic; + I_SEL_L => '1', -- in std_logic; + + O_AUDIO => ay2_audio_muxed, -- out std_logic_vector(7 downto 0); + O_CHAN => ay2_audio_chan, -- out std_logic_vector(1 downto 0); + + -- port a + I_IOA => (others => '0'), -- in std_logic_vector(7 downto 0); + O_IOA => open, -- out std_logic_vector(7 downto 0); + O_IOA_OE_L => open, -- out std_logic; + -- port b + I_IOB => (others => '0'), -- in std_logic_vector(7 downto 0); + O_IOB => open, -- out std_logic_vector(7 downto 0); + O_IOB_OE_L => open, -- out std_logic; + + ENA => '1', --cpu_ena, -- in std_logic; -- clock enable for higher speed operation + RESET_L => reset_n, -- in std_logic; + CLK => ayx_clock -- in std_logic -- note 6 Mhz +); + + +end SYN; diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/loc_sprite.v b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/loc_sprite.v new file mode 100644 index 00000000..3a880175 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/loc_sprite.v @@ -0,0 +1,154 @@ + +module loc_sprite +( + input VCLKx4, + input HBLK, + + input [8:0] HPOS, + input [8:0] VPOS, + + output reg [10:0] SPRAADRS, + input [15:0] SPRADATA, + + output [3:0] ARAMADRS, + input [7:0] ARAMDATA, + + output [12:0] SPCHRADR, + input [7:0] SPCHRDAT, + + output [7:0] DROMAD, + input [7:0] DROMDT, + + output reg [8:0] SPCOL +); + +reg [1:0] clkcnt; +always @( posedge VCLKx4 ) clkcnt<=clkcnt+1; +wire VCLKx2 = clkcnt[0]; +wire VCLK = clkcnt[1]; + +wire SIDE = VPOS[0]; + + +reg [19:0] SPATR0; +reg [36:0] SPATRS[0:31]; +reg [3:0] WWADR; +reg bHit; + +assign ARAMADRS = SPRAADRS[3:0]; + + +reg [7:0] WRADR; +reg [8:0] HPOSW; +reg [8:0] SPWCL; + +wire [36:0] SPA = SPATRS[{~SIDE,WRADR[7:4]}]; + +wire [3:0] SH = WRADR[3:0]+4'h4; +wire [3:0] SV = SPA[35:32]; + +wire [2:0] SPFY = { 3{SPA[1]} }; +wire [1:0] SPFX = { 1'b0, SPA[0] }; +wire [5:0] SPPL = SPA[29:24]; + +assign SPCHRADR = { SPA[7:2], ( SV[3] ^ SPA[1] ), ( SH[3:2] ^ SPFX ), ( SV[2:0] ^ SPFY ) };//Todo +wire [7:0] CHRO = SPCHRDAT; + + +wire [8:0] YM = ( SPRADATA[15:8] + 8'h10 ) + VPOS[7:0]; + +assign DROMAD = { 1'b0, (~SPA[19:17]), SPA[33:32], WRADR[3:2] }; + +always @ ( posedge VCLKx2 ) begin + + // in H-BLANK + if ( HBLK ) begin + + // Sprite V-hit check & list-up + if ( SPRAADRS < 10'h20 ) begin + if ( SPRAADRS[0] ) begin + if ( bHit ) begin + SPATRS[{SIDE,WWADR}] <= { 1'b1, SPATR0[3:0], SPRADATA, SPATR0[19:4] }; + WWADR <= WWADR+1; + end + end + else begin + if ( YM[7:4] == 4'b1111 ) begin + bHit <= 1; + SPATR0 <= { SPRADATA, YM[3:0] }; + end + else bHit <= 0; + end + SPRAADRS <= ( SPRAADRS == 10'h1F ) ? 10'h34 : (SPRAADRS+1); + end + // Rader-dot V-hit check & list-up + else begin + if ( SPRAADRS < 10'h40 ) begin + if ( YM[7:2] == 6'b111111 ) begin + SPATRS[{SIDE,WWADR}] <= { 1'b0, 2'b00, YM[1:0], 8'h0, ARAMDATA, SPRADATA }; + WWADR <= WWADR+1; + end + SPRAADRS <= SPRAADRS+1; + end + else SPATRS[{SIDE,WWADR}] <= 0; + end + + if ( SPA ) begin + // Rend Sprite + if ( SPA[36] ) begin + HPOSW <= ( WRADR[3:0] ) ? (HPOSW+1) : { SPA[31], SPA[23:16] }; + case ( SH[1:0] ^ {2{SPFX[0]}} ) + 2'b00: SPWCL <= { 1'b0, SPPL, CHRO[7], CHRO[3] }; + 2'b01: SPWCL <= { 1'b0, SPPL, CHRO[6], CHRO[2] }; + 2'b10: SPWCL <= { 1'b0, SPPL, CHRO[5], CHRO[1] }; + 2'b11: SPWCL <= { 1'b0, SPPL, CHRO[4], CHRO[0] }; + endcase + WRADR <= WRADR+1; + end + // Rend Rader-dot + else begin + HPOSW <= ( WRADR[3:0] ) ? (HPOSW+1) : ({ (~SPA[16]), SPA[7:0] }); + SPWCL <= ( DROMDT[1:0] != 2'b11 ) ? { 1'b1, 6'b000100, DROMDT[1:0] } : 0; + WRADR <= WRADR+4; + end + end + else SPWCL <= 0; + + end + + // in H-DISP + else begin + SPRAADRS <= 10'h14; + WWADR <= 0; + WRADR <= 0; + SPWCL <= 0; + end + +end + + +reg [9:0] radr0=0,radr1=1; +wire [8:0] SPCOLi; +dpram #( + .widthad_a(10), + .width_a(9)) +linebuffer( + .address_a({SIDE,HPOS}), + .address_b({~SIDE,HPOSW}), + .clock_a(VCLKx2), + .clock_b(VCLKx2), + .data_a(9'h0), + .data_b(SPWCL), + .wren_a(radr0==radr1), + .wren_b((SPWCL[0]|SPWCL[1])), + .q_a(SPCOLi), + .q_b() + ); + +always @(posedge VCLK) radr0 <= {SIDE,HPOS}; +always @(negedge VCLK) begin + if (radr0!=radr1) SPCOL <= SPCOLi; + radr1 <= radr0; +end + +endmodule diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/loc_top.v b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/loc_top.v new file mode 100644 index 00000000..6dffa672 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/loc_top.v @@ -0,0 +1,195 @@ +/************************************************************** + FPGA Locomotion (Main part) +***************************************************************/ +module loc_top +( + input RESET, // RESET + input CLK24M, // Clock 24.576MHz + output hsync, + output vsync, + output hblank, + output vblank, + output [2:0] r, + output [2:0] g, + output [1:0] b, + output [10:0] SND, // Sound (unsigned PCM) + input [7:0] DSW1, // DipSW + input [7:0] DSW2, // DipSW + input [7:0] CTR1, // Controler (Negative logic) + input [7:0] CTR2 +); + + +//-------------------------------------------------- +// Clock Generators +//-------------------------------------------------- +reg [2:0] _CCLK; +always @( posedge CLK24M ) _CCLK <= _CCLK+1; + +wire CLK = CLK24M; // 24MHz +wire CCLKx4 = _CCLK[0]; // CPU CLOCKx4 : 12.0MHz +wire CCLK = _CCLK[2]; // CPU CLOCK : 3.0MHz + + +//-------------------------------------------------- +// CPU +//-------------------------------------------------- +// memory access signals +wire rd, wr, me, ie, rf, m1; +wire [15:0] ad; +wire [7:0] odt, viddata; + +wire mx = rf & (~me); +wire mr = mx & (~rd); +wire mw = mx & (~wr); + +// interrupt signal/vector generator & other latches +reg inte = 1'b0; +reg intl = 1'b0; +reg [7:0] intv = 8'h0; + + +reg out1r = 1'b0; +reg out2r = 1'b0; +reg out3r = 1'b0; +reg sonr = 1'b0;//sound On + +wire vblk = (VP==224)&(HP<=8); + +wire lat_Wce = ( ad[15:4] == 12'hA18 ) & mw; + +wire sndw = ( lat_Wce & ( ad[3:0] == 4'h0 ) ); +wire iewr = ( lat_Wce & ( ad[3:0] == 4'h1 ) ); +wire mute = ( lat_Wce & ( ad[3:0] == 4'h1 ) );//mute +wire flip = ( lat_Wce & ( ad[3:0] == 4'h3 ) );//flip +wire out1w = ( lat_Wce & ( ad[3:0] == 4'h4 ) ); +//wire out2w = ( lat_Wce & ( ad[3:0] == 4'h5 ) );//NOP +wire out3w = ( lat_Wce & ( ad[3:0] == 4'h6 ) ); +//wire starw = ( lat_Wce & ( ad[3:0] == 4'h7 ) );//not used +wire iowr = ( (~wr) & (~ie) & m1 ); + + +always @( posedge CCLK ) begin + if ( iowr ) intv <= odt; + if ( vblk ) intl <= 1'b1; + if ( iewr ) begin + inte <= odt[0]; + intl <= 1'b0; + end + if ( sndw ) sonr <= odt[0]; + if ( out1w ) out1r <= odt[0]; +// if ( out2w ) out2r <= odt[0]; + if ( out3w ) out3r <= odt[0]; +end + +wire irq_n = ~( intl & inte ); + + +// address decoders +wire rom_Rce = ( ( ad[15] == 1'b0 ) & mr ); // $0000-$7FFF(R) +wire ram_Rce = ( ( ad[15:11] == 5'b1001_1 ) & mr ); // $9800-$9FFF(R) +wire ram_Wce = ( ( ad[15:11] == 5'b1001_1 ) & mw ); // $9800-$9FFF(W) +wire inp_Rce = ( ( ad[15:12] == 4'b1010 ) & mr ); // $A000-$AFFF(R) +wire snd_Wce = ( ( ad[15:8] == 8'b1010_0001 ) & mw ); // $A100-$A1FF(W) +wire vid_Rce; + + +wire [7:0] romdata; +loc_prg_rom loc_prg_rom ( + .clk(CCLK), + .addr(ad[14:0]), + .data(romdata) + ); + +// Work RAM (2KB) +wire [7:0] ramdata; +GSPRAM #(11,8) workram( + .CL(CCLK), + .AD(ad[10:0]), + .WE(ram_Wce), + .DI(odt), + .DO(ramdata) + ); + + +// Controler/DipSW input +wire [7:0] in0data = CTR1; +wire [7:0] in1data = CTR2; +wire [7:0] in2data = DSW1; +wire [7:0] in3data = DSW2; +wire [7:0] inpdata = (ad[8:7] == 2'b11) ? in3data : (ad[8:7] == 2'b10) ? in2data : (ad[8:7] == 2'b01) ? in1data : in0data; +// databus selector +wire [7:0] romd = rom_Rce ? romdata : 8'h00; +wire [7:0] ramd = ram_Rce ? ramdata : 8'h00; +wire [7:0] vidd = vid_Rce ? viddata : 8'h00; +wire [7:0] inpd = inp_Rce ? inpdata : 8'h00; +wire [7:0] irqv = ( (~m1) & (~ie) ) ? intv : 8'h00; + +wire [7:0] idt = romd | ramd | irqv | vidd | inpd; + + +T80s z80( + .RESET_n(~RESET), + .CLK_n(CCLK), + .WAIT_n(1'b1), + .INT_n(1'b1), + .NMI_n(irq_n), + .BUSRQ_n(1'b1), + .DI(idt), + .M1_n(m1), + .MREQ_n(me), + .IORQ_n(ie), + .RD_n(rd), + .WR_n(wr), + .RFSH_n(rf), + .HALT_n(), + .BUSAK_n(), + .A(ad), + .DO(odt) + ); + +//-------------------------------------------------- +// VIDEO +//-------------------------------------------------- +wire [8:0] HP; +wire [8:0] VP; +wire PCLK; + +loc_video video( + .VCLKx4(CLK), + .HPOS(HP+3), + .VPOS(VP+1), + .PCLK(PCLK), + .POUT({b,g,r}), + .CPUCLK(CCLK), + .CPUADDR(ad), + .CPUDI(odt), + .CPUDO(viddata), + .CPUME(mx), + .CPUWE(mw), + .CPUDT(vid_Rce) + ); + +loc_hvgen hvgen( + .HPOS(HP), + .VPOS(VP), + .PCLK(PCLK), + .HBLK(hblank), + .VBLK(vblank), + .HSYN(hsync), + .VSYN(vsync) + ); + +//-------------------------------------------------- +// SOUND //ToDo +//-------------------------------------------------- +loc_sound sound( + .clock_12(CCLKx4), + .reset(RESET), + .sound_req(sonr), + .sound_code_in(odt), + .sound_timing(snd_Wce), + .audio_out(SND) + ); + +endmodule diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/loc_video.v b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/loc_video.v new file mode 100644 index 00000000..807719dd --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/loc_video.v @@ -0,0 +1,194 @@ +module loc_video +( + input VCLKx4, // 24.976MHz + + input [8:0] HPOS, + input [8:0] VPOS, + output PCLK, + output reg [7:0] POUT, + + input CPUCLK, + input [15:0] CPUADDR, + input [7:0] CPUDI, + output [7:0] CPUDO, + input CPUME, + input CPUWE, + output CPUDT +); + +//----------------------------------------- +// Clock generators +//----------------------------------------- +reg VCLKx2; +always @( posedge VCLKx4 ) begin + VCLKx2 <= ~VCLKx2; +end + +reg VCLK; +always @( posedge VCLKx2 ) begin + VCLK <= ~VCLK; +end + +//----------------------------------------- +// BG scroll registers +//----------------------------------------- +reg [7:0] BGHSCR; +reg [7:0] BGVSCR; + +always @ ( posedge CPUCLK ) begin + if ( ( CPUADDR == 16'hA130 ) & CPUME & CPUWE ) begin + BGHSCR <= CPUDI-3; + end + if ( ( CPUADDR == 16'hA140 ) & CPUME & CPUWE ) begin + BGVSCR <= CPUDI; + end +end + + +//----------------------------------------- +// HV +//----------------------------------------- +wire [8:0] BGHPOS = HPOS + { 1'b0, BGHSCR }; +wire [8:0] BGVPOS = VPOS + { 1'b0, BGVSCR }; + +wire oHB = ( HPOS > 288 ) ? 1 : 0; +wire oVB = ( VPOS > 224 ) ? 1 : 0; + + +//---------------------------------------- +// VideoRAM Scanner +//---------------------------------------- +wire BF = ( HPOS >= 224 ); +wire [8:0] HP = BF ? HPOS : BGHPOS; +wire [8:0] VP = ( BF ? VPOS : BGVPOS ) + 9'h0F; + +wire [10:0] SPRAADRS; +wire [3:0] ARAMADRS; + +reg [10:0] VRAMADRS; +always @ ( HPOS ) begin + VRAMADRS <= oHB ? + SPRAADRS : + BF ? { 1'b0, VP[7:3], 2'b00, HP[5:3] } : { 1'b1, VP[7:3], HP[7:3] }; +end + +wire [7:0] CHRC; +wire [7:0] ATTR; +wire [7:0] ARDT; + +wire [7:0] V0DO, V1DO; + +wire CEV0 = ( ( CPUADDR[15:12] == 4'b1000 ) & (~CPUADDR[11]) ) & CPUME; +wire CEV1 = ( ( CPUADDR[15:12] == 4'b1000 ) & CPUADDR[11] ) & CPUME; +wire CEAT = ( CPUADDR[15:4] == 12'b1010_0000_0000 ) & CPUME; + +wire [7:0] DTV0 = CEV0 ? V0DO : 8'h00; +wire [7:0] DTV1 = CEV1 ? V1DO : 8'h00; + +assign CPUDO = DTV0 | DTV1; +assign CPUDT = ( ~CPUWE ) & ( CEV0 | CEV1 ); + +GDPRAM #(11,8) vram0( VCLKx4, VRAMADRS, CHRC, CPUCLK, CPUADDR[10:0], ( CPUWE & CEV0 ), CPUDI, V0DO ); + +GDPRAM #(11,8) vram1( VCLKx4, VRAMADRS, ATTR, CPUCLK, CPUADDR[10:0], ( CPUWE & CEV1 ), CPUDI, V1DO ); + +GDPRAM #(4,8) aram0( VCLKx4, ARAMADRS, ARDT, CPUCLK, CPUADDR[3:0], ( CPUWE & CEAT ), CPUDI ); + +wire BGF = ATTR[5]; + + +//---------------------------------------- +// BG/Sprite chip data reader +//---------------------------------------- +wire BGFX = ATTR[6]; +wire [2:0] BGFY = { ATTR[7], ATTR[7], ATTR[7] }; + +wire [12:0] SPCHRADR;//Todo +wire [12:0] CHRA = oHB ? SPCHRADR : { CHRC, ( HP[2] ^ BGFX ), ( VP[2:0] ^ BGFY ) }; + +wire [7:0] CHRO; +loc_chr_rom chrrom( + .clk(VCLKx4), + .addr(CHRA), + .data(CHRO) +); + +//---------------------------------------- +// Rader-dot chip ROM +//---------------------------------------- +wire [7:0] DROMAD; +wire [7:0] DROMDT; +loc_dot_rom dotrom( + .clk(VCLKx4), + .addr(DROMAD), + .data(DROMDT) + ); + +//---------------------------------------- +// BG/FG scanline generator +//---------------------------------------- +wire [5:0] BGPL = ATTR[5:0]; +reg [7:0] BGCOL; + +always @ ( posedge VCLK ) begin + case ( HP[1:0]^{2{BGFX}} ) + 2'b00: BGCOL <= { BGPL, CHRO[4], CHRO[0] }; + 2'b01: BGCOL <= { BGPL, CHRO[5], CHRO[1] }; + 2'b10: BGCOL <= { BGPL, CHRO[6], CHRO[2] }; + 2'b11: BGCOL <= { BGPL, CHRO[7], CHRO[3] }; + endcase +end + + +//---------------------------------------- +// Sprite Engine +//---------------------------------------- +wire [8:0] SPCOL; +loc_sprite speng( + .VCLKx4(VCLKx4), + .HBLK(oHB), + .HPOS(HPOS), + .VPOS(VPOS), + .SPRAADRS(SPRAADRS), + .SPRADATA({ ATTR, CHRC }), + .ARAMADRS(ARAMADRS), + .ARAMDATA(ARDT), + .SPCHRADR(SPCHRADR), + .SPCHRDAT(CHRO), + .DROMAD(DROMAD), + .DROMDT(DROMDT), + .SPCOL(SPCOL) + ); + + +//---------------------------------------- +// Color mixer +//---------------------------------------- +wire bBGOPAQUE = ( ( BF | BGF ) & (~SPCOL[8]) ); +wire bSPTRANSP = ( SPCOL[1:0] == 2'b00 ); + +wire [7:0] OUTCOL = ( bBGOPAQUE | bSPTRANSP ) ? BGCOL : SPCOL[7:0]; +wire [3:0] CLUT; +loc_col_rom colrom( + .clk(~VCLKx4), + .addr(OUTCOL), + .data(CLUT) + ); + +wire [4:0] PALA = SPCOL[8] ? SPCOL[4:0] : { 1'b0, CLUT }; +wire [7:0] PALO; + +loc_pal_rom palrom( + .clk(VCLKx4), + .addr(PALA), + .data(PALO) + ); + +//---------------------------------------- +// Color output +//---------------------------------------- +always @ ( posedge PCLK ) POUT <= (oHB|oVB) ? 8'h0 : PALO; +assign PCLK = VCLK; + + +endmodule \ No newline at end of file diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/pll.qip b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/pll.qip new file mode 100644 index 00000000..afd958be --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/pll.v b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/pll.v new file mode 100644 index 00000000..70025276 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/pll.v @@ -0,0 +1,309 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.4 Build 182 03/12/2014 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2014 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + inclk0, + c0, + locked); + + input inclk0; + output c0; + output locked; + + wire [4:0] sub_wire0; + wire sub_wire2; + wire [0:0] sub_wire5 = 1'h0; + wire [0:0] sub_wire1 = sub_wire0[0:0]; + wire c0 = sub_wire1; + wire locked = sub_wire2; + wire sub_wire3 = inclk0; + wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; + + altpll altpll_component ( + .inclk (sub_wire4), + .clk (sub_wire0), + .locked (sub_wire2), + .activeclock (), + .areset (1'b0), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 78, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 71, + altpll_component.clk0_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_UNUSED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "78" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.576923" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "71" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.57600000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "78" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "71" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/rams.v b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/rams.v new file mode 100644 index 00000000..4d579578 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/rams.v @@ -0,0 +1,64 @@ + + + +module GSPRAM #(parameter AW,parameter DW) +( + input CL, + input [(AW-1):0] AD, + input WE, + input [(DW-1):0] DI, + output reg [(DW-1):0] DO +); + +reg [(DW-1):0] core[0:((2**AW)-1)]; + +always @(posedge CL) begin + DO <= core[AD]; + if (WE) core[AD] <= DI; +end + +endmodule + + +module GDPRAM #(parameter AW,parameter DW) +( + input CL0, + input [(AW-1):0] AD0, + output reg [(DW-1):0] DO0, + + input CL1, + input [(AW-1):0] AD1, + input WE1, + input [(DW-1):0] DI1, + output reg [(DW-1):0] DO1 +); + +reg [(DW-1):0] core[0:((2**AW)-1)]; + +always @(posedge CL0) DO0 <= core[AD0]; +always @(posedge CL1) begin DO1 <= core[AD1]; if (WE1) core[AD1] <= DI1; end + +endmodule + +/* +module GLINEBUF #(parameter AW,parameter DW) +( + input CL0, + input [(AW-1):0] AD0, + input WE0, + output reg [(DW-1):0] DO0, + + input CL1, + input [(AW-1):0] AD1, + input WE1, + input [(DW-1):0] DI1 +); + +reg [(DW-1):0] core[0:((2**AW)-1)]; + +always @(posedge CL0) begin DO0 <= core[AD0]; if (WE0) core[AD0] <= 0; end +always @(posedge CL1) if (WE1) core[AD1] <= DI1; + +endmodule*/ + + diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/gutangtn.zip b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/gutangtn.zip new file mode 100644 index 0000000000000000000000000000000000000000..2afbe5d95338230c40a6c66569f22b895597a2a4 GIT binary patch literal 20474 zcmZ6yQ?MvNlcl?D+qP}nwr$(CZQHhO+cwX(&z|#l_r&cx4;A&4Sq~La_2tTy3evzJ zC;&hZ5CGqyn`CJSVIAlI000F47Wlu#$Y4lkcSNWLBIMYRT_(tp8#F0RL~S`F~ESknsoM7hg5(g9f&!_V7`j;rD3UrN(-}l%1 zexC#iFwlkGkcCN^d{j({*p;i2AxXAd&BA5(nbJu|{JyUD$5#n;vbN@jFVeW4S54-| zJ2t>uy*x{A?M=>T>8>yJDs$I0q|Bu?+?hEJLj`5$h;213JKOPn2=xuK(bI%{YbY!Y zmZI9nj*xMy(qz4vP)5Dc5Q#hTQic5TxIp>kO0xh0;VWqbOaikCB}uD?vnhANZJGu; zt<>3Ek%a^yJhOVP0S!_3W0o`l0g4MSW`$%yQ+Wa;mpzm*fKUYkx=|X#76+rtVP(~C zW%a|qPSb$mf&~qP4rP~ zR#xsJS4?&{p20%6>ZA*?BFaxGPjt**VFHJN%bm)-1fH0*EL1PD7|ve2 zVLIp_L38ku?59{Q7|c~A&n$d9cGiY`dlc&?{05ySFL@jBD~$C|%TA`s0JC$x8I*O! zB>~j+f(g|1q6p|NZ2bWzv{A+W0xyMk1&;*;P!Y*H|Lsn}qI~aGg|-AjCAO}|1(E7B ziQPuV5UMk&4y8LSd%E#WWJWS`Mohmfn7^V}>Sh`eCRL*5A-k~$vOD?u)b23v0Ph&% z%)J=^w+&NYK2z09TgrrjCyftsn7h+<2kwsdj`+?wj<6py@I=CBUqK92Gc75TijtXK znm+A}t<&!mCWAw^W$%tij(8@9Jc3RwA5uvpOkkF^cmuQYjsq44B+@uGqYYA>zU zki$kta(}e`Z2j^5IsPI3dHz}cx&D#<;r_w?QTIEp4}E|1Z^r(#|D^w{|2X^uF;5u- zaV!t|&a2MtlzDZ-?d<4vE44l|x)K8=enOJ?iLcUQ!gr+$38g;;uGAExrMl7{B`dOL zyNE`oJds=Kb0%u2VkVb zV=t29q%}$0gu65y5xX>KNq1npc!V1tNfNhlQ0;ESR|cJKut!GZTcY$n?=o6^gm(si zVz}rn55y>(gCqWB)Oy2%6rB>&!R@Y{w8#F>Od7Vm$#J`bEbtdE$Df*%Yuh-_&SwAb zzAdy?Ub}0a*G41hFO=s*kSk`EYJj8Z507BkuoP5VdZ@Svvos=ZWsipj14+u3J4rV7 zLQ>SE62$AqNzn-UC?m;$L`=rxdyfnZZiW6{%K>c?BgF?SK0V9T)Z^d{2y}W>H4W`y zmSQLDWYByDQ3@nF6gosYbTbHb$aSc7Xm+TlP*I`Q1{n=2e8lY0#v`*r6%G^cAvG&w z8|@G6523#d>!Y=YQyt75{F}NrPd8MrVy{4MKws?5`J011BRm5;gEVGljH5G~Gn6u1 z$pqk&>n8A*q}vnLCd8J+@X6kiDLax`61df;ZZN|85dbgvpp6GI3^y@jVRDIcEa6 z+%0@$fHEaVW)eh7uE>Okl!)(L_n7694#p>dfbbi;|R z;2hV%s%uj;&}bGuFn9~aVm)d=A!+~})1W}%p;!TIZpcU!T%XeGOc%hH{Zd&#A}AI= zYYiQSvqpy+yoZ27`G6J-w~3Xi|w5x44G zH^_5z!MUT$_PbLpriJN~#q!KlSA8S6#!QUQ0C2anZ|OLtF?0t&ajF1;Y&Vb)*^X&} zZe+MCDUjj-(w{++AEyiGSJ2@pQ0;tF-F^`=Ws8yHC5V z7?!Iu7N*79i6=9l*3-^4XojuVjjz`N-GD8g9l@TJ#C>x%;(Yt%RU3A0rf?bz&Vv1b zUTy{4dp4=-^KvE(rdNL3$_xTdXW6qy4P6a5K;>4bEvV;!Y+sX7oVOV_-?n~}vJJXt zz{f;zF_Nstee>l<(mqD;K#g+Vg{oY|v_nhi28+-Zi-QSVe1|}qnjoJ-7OJGr(jGzs z;$dZ>zuR*xtA4dmEmjLufcu%FYW0{>u2&FM7K!Gmun`PqrbR-#=@x4I(k_+w=h@_i z>O%9z7@dv(j;~bBuvPh+Y38Tcy-C%osU1{G2WpF{)=iV@PdV!^S2Ue3OZZIMFdk|5 zIm^I`8dghkL?OKVxfMARiQ$JFynaO!GpYq^v=XEikMTkov$cr98WCvcg=@4DJ63@i zD)`qnL##mRHf^PP17OQ(VJHGo&XA@Y!#s`Dt-9;CYQzuqyZk)goK2ee0`}RuAdn53 zOv+T9DdK~5?C7-F4qn#!R;p5Z5Y$HeAtsOj;-gQctFIb3X7z|=HFEuOQLQA(X6P|% zrc9y(VPq3h&UEx)-j9bqI;mD27*^Rrj<+DY8 zsjP#~`BwIq)7Ssg;B)VH0pRjZ7M>xcA;n><6JeXGWKZy0x_DyY2OM90z=+DU>myyf z{qN$*M}fW7KINIB*RJRtnET34755#UBXyqAylh@NPdAUAd?)e6&O%RBtC64e=#hbz zz5GIJrRQxJde9|5Nv}@lhR=2FFaPkN@skHHY?Hmm)VIw}i{Ww^>^$$2%F;EQ(LHJw-u{Ba@8c=1wu0ia!g9l=h;V7? zxM$C|f${P1;h*dJqN2ja!bajt)9Ksn?Y5T1^5fMwT3lRQvmgU4S5xU}S!n8NwR*i> zESEan?zSSV^CeSOSHW?wdfykT`tC9=3w`s*)l@;pR#Lhe7${m5o8s+8_I3lXr$Ly5EZw7|=w=tXO z{}%%1szWMZo1*+>@7^RKN!Z1MQZ@K3plz$fCNhX+u?avxkT62(8Gpc{Z#lrMVhzg@ zFjoO{U6GA%^jO8VuPSD>1&QoHn_nZga+MG#wi35>EtB-g7Pwx-#NCJgec1cj|NXh| z_2t({?6l{2jWC)Y*n6U$lkmN+H-JNP>L0hRBDXr)v|-!fbPtC39l3QiwYo{Kt5 zAFqec(E#%^B(%#z8e5wegZSn$LS{yZ;h_?M(%E`a0^58(?@{Z23&q zFO-)lFE4F|xD)|OkF@FJc*+2UeR`5gA13MGw=!9Z1o4*=G2}u)i6Lb(^ zLh1lKvxdmU((Gy0y!bv91uUwvc_``w;(QGev=vH^uz6MBLOZCGecI=Rdx6u~h(Z;4 zTqN=GA&W^BL zX@4GqX$Q(^G=}|4HJc>HB;qR;x{7>NziP=^M6)w?H;Vlfn6o`<8>1aG99NP@j8ixM zEP!G8%2uD|eJ*n>gn0BaED5KXKr%iF11r&Fmb(#+_?WxCQkSn&kZkg7R5_`Ro{rV0Ktrf#;YJQ$CFJ|lVu$+BFckG2$9U%4J|K=SppFuMnFt}JOe!JdbS-# zI-}W&0SXCq3slIX5$vBY5n9TS3{%n)63mz0)d(AcmeD)!*q@8zuCa1-5h6+)=Y-xY zL5K*&hINU1V1W}qvSWhKuHY?h>9lx|6Sz4BtAmKi2bqHVHGK97;8Xuq^~zi zR0=YLc-PzUJg5|@L1)XW=;eh;he)1Hek58Z>i%)A-P!9Pu#bEFb=P6+;NUUE+DvWGZmc#t;L1}I+i&&F12Y8A*kB>xil`LYR7fQ}czMDe3mnF(vm_)vz%m`wbP z$2aN2FqB_{5O|TwPGZeGiX&+6Fsqod~sQK0Z)~qZ%U6i`u`f~Zw`EvRK?~3os@{9Bf z^$W%?CO>;W({Ty<3;Rp|O5B$xO2O8`Y)MiHx|Urrt-e$xSV_DTT(PE>dy@FcsR(^?H2dR`4)S%dc}UKy?E$LR~Lu+vuL>5m1oP>u}%+@ z7k+vPHn@K3oV#`S)Y6p`tgHjS=?pGjK5gc}4IVyz=rH6>^W!_UZ`PAK$~Cr+$PB-^tlWAG~bx@D&2a3}MdF!Pi4{ z=eP~-+Hr5+A?nP%Hh;Bouv8{Dr@7P&WNL?TA$6?~men%H3 z_slxzTJ1yoyQu*CJRf3J=uhRs^ei8uCh)6qfpYOBtV)K_7INs-^!9!|3`=KTp1$uY z0$;>H{~b&>ZI8I6eW+(2I%m_!4XPilJK?;0V2pncG2aO2Y|U*C@4m5h(=dMO6wFZ1 z6%DAfcGGyS3!T`)n!9%Sg1g6s_1FcHt^TJo#I0MNV|x`+4kR+!AJS#Mfs-&oPrDfx zsEOGI*uKGV(DsdG8=LR|K`DMJTy_;ax;*3ML_>350e^nq<3}_<3 zPWM#_U7L+%Tg((*HZ66ioSo@hO)8VNs3mJOsu3-d+PO6MLa%_r<`WA9OA7hNfIiC) z=sfxjJ%g2X%kI`!tCViyodm#v#O9+YC_pgjq>ZK`T0N}+AOa|TEz3Yt^^k{Vu?tl+ z`E6(4WL1Kk!6xE@pjBgL^wju2!E-j)MHEqE9B1-AzpAu*Ov?2#*hGVo#> z(p=1_BZIWwrhbypZnYrG1~ueb)B!!Y^&$l1rv9+CQo$hAn!}8UXQbph!9^F=!MdyQ zGc)tF0es_yQ+C%zOb1w!!Hldq+>J<&X2`BxtqcMkWz4p%Ye3wv~rDXZiKkt z9>NSDiL78pH{g*RlwVXKu7ISM#nSUt>@ILq3fqrlKn-**2>S8Es zm-4Gm7g8D_G(&E0;3d|s z)4*N?mt?vGmH6y))UndQ&Wv1mk9Qk9aleU$oxV<4ZKwbK8ix^<-rhrbORn_7nnr}; z(6A*4z5YFi)dIs+gQ(sresd1{Rh0-(mG96+jn*9tCafnp&e}g6Lxn@&(E8Lem!{<< zj9V#nq7=H)1NNMR#-2-g!%N@nH1b;}V@+qo27u*K#-SZ7K)(YbPmGjm7#*_KGjNLb zb^9Y&2Y2MBy(F{i!FDty{*2zsU_4vn!5u4XVE7kl@KaATd+AWt;Z^A`S9>Q{Ef&2{P`{QQ0=unOg%QI z?uRM2Q-A9|Rex+>_yOeIrZ+|LQA?kHdnY7Bogh{ZEUnjc`XK2zmM3h76sH2%aGefx zZVJ+O+0nOqCerBPI+q&C+tc3_dW1<;uV_yb7p1hW7J|J`P)ZquQcsrNqG8+?mk7+( zZo=s28zyz|DuL(EK5RfCOWE>$Aa_9SKq$a59LyiScfzyZZga{9$GP(tD2v=ZtROMs!`q}HhYm;EffJBb?N+lVW zQx;`OfucrypKpZvbQI>4j3ACkQIc)iz)|d^-%;zuPP2rbb@Xb&m{eqtc&`gyCqyX} z^6tbf`Bw^aqH>ZQKQJ!ea3(eyVZ5n`(>wV8NBaJcK>Z&$r^8)BJpSKsZmQ4pAALGi z-O>hI6eVwSw`M)k_?|62m*Y}yX-EjiDyBK4lm-mw3@$>OUE1Vc`L{YAm zvP|#@MLY^2Ls+0nU<3h83jtOP0|G(ZKnD0UY@|ms9h;Cb`(~!c^Zs_md*9nWN2ya` z<(&Glv{QvJQYO%qNA)%F2OrbhO!v@U(!345!zHi8M-{Jc>S=YR47N!;p$@C-HchSl zqzV6yWFtz+TcMFW>!5d{nl>uE-sKOf)`zur4Q9MjaQhxk8n7$;RM_-muXVj@OhRi# zA2%AL<|}5DZ)1@`rI5!0Bt7oSv&f|eh&Bsj>$&l1htnkCb|Eg1TXYf~iDM-+m~bdb zdxDVYei2LGAC5;s?F_9frBF%tMRtNB+-)X1HxRGs*mYgzl-ZpJ?f%KKdK-=Rhwb{Q z{Mk8_$NQX(7%6T6YW!oWar$kIyYkb;tKi^@6S~_%yTbd7px$7m&k~lGJm#%udK6IY zl2NXfR+l@ZDuOT)%MF}N=u#QOATBs>$OqvrbbM8MkNG@${k&YbY*ch&Z&~Gb|x-cHAFi< z8P&9QoEPDs1@>~}TO^#z?khtk$^+7byOR8-l!Q!Yd`J6oure_z-Q~-KCvkVW3?48= zE8&}WiA_|)I)}U6s_%^_0~+;Q5Z$xQ=$=sPsomj|(Q7DwRqmJ>x)v$Br2*E%e;o1Y zdqH662i1y;5O@Vb)L!69)!ez5Tm1Hs<9a?TlIJ(&<4-)W& zrg@sO2)D5rV5Y7M-=|JrQ>KwXI^%p3h8za`VclT7crs&%%S;`*nQ8g4E%r4p_H|A6 zRU>9CnK3gYZ|PE=8Ct~04Q$g&JQXNUVAa_iadXe@#RXDeYQb&MKNzVio)(wTJe`U; zY;(d|cce~3IBfc3y3oVW4N2U|THdOohvUwZOn(P?r%`Fg*}kH!#Q(%H!MuXN3@obu zZRoZZ_{cX+bI&x258(K9JoYF!U1R)aB?b;w{yDT!><;p5Afb=7ur2(!uIz1Dw1>LD zEj;E#eMc%~on03ekjTyMqIdC~@Qo}}IVdy9tc=DhACu6WJoXXpkT94GyiSOb!0td`5R{^hE#>>^~_MUr0v;p`JTeS3MQC-K1f&d|Rwy&Rg7 z9lHzNYgg4hE`pEKx$@HTDs3OBx9_8S@aYypXW7T$0QtNQUawrQ54WAEQUw>zHZp+h z!&+Aja55e3U6&Cv3R-sjXnXcZ>q(`Ub02G^?FAT~ugtw{G>Q~&EO+%f} zFH_Y}dyNFt88!5nnx@xn0O2Y16$(;Qv8m4U2)2A6!J%2%UgqO1YPc%pS8_DF3<9!%-=4l-c?L6MopAfN;i(j3zAPg%g}8o9Lf`$9kK{k|9? zl6+ut#7)UC4<3-G7lwM*Go0-CaKpb3`DZcx@7p_j#8&uyOLg|`+U@QB8;Cdh&%J&{ zRs}Y8J9lc(0rx?4bKCZ>TVr%>W!W4``JgO7y5s%X6~Hnhb8p%TF+vzLnPh9b82MbX zOV*5O8VVPzD|+p)SOM5yu%#=I9u0hVi~d@&_EqFy1`i&Q38b^ z@qvx00-jwOqTHdp-;u<3(y)G!Z&EXc5vM6Cq$-%~qdCL&4MJBm3BCkIrcdg-(r*)> zFD=Qvj8rRa@wHyUvoeauhQFM{G-$~m5(}ODolQ*|;Mo!H9S)8X69Z9`O&TzDPo7SX z%X0RqAx)VR()){R%BWy9hHp{Xd}d|IqGq=G+Vx(!7n#LA2g9n%VCS@YK3?R3YvlXy z>_hR0fa&~pd5~BBLd3?QI-rQ#!^59M0gqKYV(15woL(@U_GjYyK!Q69#au@W0&X_k zV-y5l?@`Xo(9LXU1^+xERrD%OFem5}1gbkjcO1LdGtN(`^5-+luGDChS5ROk_yaZ zI5If|vs0{bgVm__7n6*+I;~+qY8MSeOkG(|tabPrW;cC`HKVNuM@w}8Hdddk)6fYk z8pM`KMH{`}AvQTTc&SEc3^tOkFmh~eN{OOpe~KhKvsD*$2pp-;V;WjFibZGFneV}a zm`hSXgmnIx(b3b9R@Zq_8Q$2`US4a}>}TvV8o9cP)!3EdZKk&I;Gyq&HnO2kkPja7 zD>Sa9`~*=(3z}hA~>jgzN=kgCIqK|Ik}T7Q52`12Jw5%@Dia-!;;x@o0O zDW*+v9V@hg=Tf=Fc;3>U5*M`Gn6U1%X0UtJc;N9&Qw>`FD+4VoF~Z0I_u4gEerEu2Vb0sVuKUG^%XkTTE!AfBd>(bcC{ zU!5StS=*fONFrP)6t#UL^@^hOeez08wrWDCiVsC992$^Qz5omkvtJMwaVAReOqvct z>DP>M)?>+bGWAnH1d=4r5oG^M_)ZlHQv`K_&NR*7?*H|4o4wVGE5)mCSaw%o>^NMo zUR+;A_N1`F*C^Z>Xc}o&$%IH026pOMHLR&3_5rmyxMc0E#EB}NTMC_qG%I!LQsQXl zRa#74sZtW9JYP-tQO;ljSsS}j(zsO>p+GGp8PL7~1+brX8h4?P5NeG$U9D$LYC;~h zcyCKn6i7N=%`R9dK*nT5d$>lamqOJuQ7OglqETy%t7J`PcYSephYa*M?t;eVDVHAC z^&EewTTFQp<0|E}E1J+K76vAw;s1|D)2s2griL{4bT>OrQBbg+Q*Fr3|$y zN}qd~3m{%DWfThHc^ky?7PzaDH7@>XWh86Sk=zP}onv(3d0Np#NreV0-8`!@muQTm zewA457;G)l7*~`c;!4+d!H?pX$Z?Ro4R1S7zVs3PeeTEE-5dA$p7UG_$yVFUo9K|L zc=vz{jSk|O9@1OVzCxs`ucIH!HS&-~*Bu})Y(m-sup!APo;}0k}C|Q&@ip0j>ozt->M<}l)3qpqVzgSCBgOY`| zZ;#%}7Ucq_N&4!{M#5T76(EG@O0G?EY9=*)4s4xCJ<@)JCe=|7j+gSJ`BE6H6Si;{ zO`@&zp`65%(|oN&G!Ge-k1*P&h|0GCL}t}rDzQJHL8}4u8ZV{ANwT3I+9lWc2Z@za z+8b8UtyK0(#GqdmhOT>XlHsfUUiX^mHwyTf_s6w05!=}`O`&m_xU}z}%6IKM^{dL& zE}$IpHCImES{b?RA#jC45U>o*Lo~EZ1kzb1$QaG}NFlmx6|-wrE=emY#e|xIdaM&y zt(9%Dvg|1dq;-+ngCUD0LT_kG>SU!Alu`WGYSjN(qY9?=VstUPj(zbMt_H{j z-kVk5CUD=ZvItVffF^*3YkfbcB z@M3g|r0SeHd9Gs7#uyc5^uI`r5Ihr(*%O7d5u-4~3I(@DAq*e6wE^A+V^&XlOv%zu zqVr3N{Si3c#xq{#8_QBBFY+qjC{e*_<}0J;E+#!u{x%onvfF#JwAk+rdrgm60YRqVie5w-nu)(0_Olx>IzuzPU{BAysjT*QtS zeBc`l>V49PhBD825IGt~jM_bLB6WzJhrNW@`2fa{gKZa6D14mEC_;8DVTP1ihJaj` zZ+!C##LaJE2lA3k&;4X#EtP0AX?m<3k0Wh1a`rvNK2}@w5JGRFD`$^{{Wy1O%Kqlb zg)hn=H~!-NRI|J`!_vZOB5l=ST2;Hi->#*pPgEH47-i8pgf6m~aR5z$`nt7?WP|||X*i^s0AWJ_N*(JWOIa%P3sGYVo2#Yy+hN*Ick{(m!Jhnv+CXWTu%47!JnG(aP0*A zd%-%+vC4}FTL1dfdG=`=BMRF%*!UEA4TrOnoxM}!?-}Mforz!JdqMwv@3OBH=X&3s z0Pxt z*IJNJcXt={t9@B0XK9DorZ-5i`$FY6-}{BT#{rWjAFgDqUhBHLr3QzW-B$P+HoTXZ zF+y39y2AXy$3rh7+EXN+AyuYC7#lb{Rl16DFzI z9xF9eCdvdD>o@FY#IaqITM-9m;G>KbYXn~9$Uau@bJmwa$^5g72h9ERc~1c>_EuXc zZmg2X4`>{zs~C)^b7VxHnPp>By#$bPjPHSgjM)aK8sX_)bgnv49~BeggJ;yMH<5V> z%HKXoK+2$b)}P^GU*OoehuKg27_u!U7TDvkz+B$N>f`PDu=cDEdV|I(yz9>E^$cya zADSAEPK`$ij{56_@Wm`1dJ-m6e219b_l$feRx*4CnbrAAu=j`N8iQ0Vbi#sl=`=!& zKm7b_zYm-p@U7RyCuhv{(PEN&3W0Uj$p>B0v;?gv^H{oi31BL|^QFSH33gLdpwtkr zEw3aD6>@NHX@e30_|G|XmWH+#JnDS)J)o?IPm#%!Kh^(vG2`Kc8~pBo2va z8VwM8A0lkzU;@`Yze`Ksb)4lUAh(I}JS~y^a zdYxs1@#ZDX|K+xfw8;(OWY;keV~bd5o&NWJmYF!kgFS+M?&;oKB44A+HZL-eS7zmb zCETqQ6j^eyO1i1ZS!QY$SwS7_25^JF<);Hj&e;3`>{xzuqXojdB{dZ3lTJp;;wcU^ zI^k}eSPu1DD#X|=_%lQ#hI36nXV$+w%8-QAiJGmx+dMu0XbwGUwJ zBQmn~UStGoE-=2c7{}NdU_n?x9EF`jkalBm78ft&ZoPRDioN`v~X(* z;@!G_-n{xV4+B7aRifR}hMkS;kA8lkdjxZXR=#%Q`m0>CbUlPuP`3`k?ZDS8D$QNQ zr;l*G==hVpOY5a=YFzp;@x8hVx z(&<^D%$_W0$GCOtQmUC%`Ff~b5BpmjU30QrK13Krx!_zpl|u&U2tg4G$V-8tyY~To zX3ZyeD+L#1cBh~C?$A3K0gqC_%~}@y|8$j{%j+rZ%tBB3KYsehFhIvdfOfN$5A93z zQWBGykb@Sj$`EcN_wYMVrUXUgX_@)abocqUm|dOyt)ui43vNR+CEKF=t`R25N?UXh zYnk%+43?S~px<==tlre}=8Iq$A*5k1Lo+|DUzYoXqj>E9IwfNzZu;f}r}(I-R5{r$ zYs8HEM0v~9BRh3rT>ew7*-nbjdhPXB;HhRaXWvY34*cp-3ODnLHb}a&9v#Tb$7lft zaKWTKIozuNA)Xi(bM(yApTb^U*c1ND8L6B<*X1bw_%lV~J?}mT# zHv?bQaw`TZUdQbB@8g#{YDS(o5?JoW z=#e%W$oV}(>TXdeN=>!U2CXGS?2=rt#I|Ht6Hd*^3A~cbU2)qj!#PnQinTRSvgBrg zhb*cg57n8ay#!OFeIZOh5l=D)u&f0ddENUsBDDeBYtHY#|LMDb>-*Y!daH{`F|3Zu z_z*1!I*wRH#37dqsc;D)u)rdni8ExwmNgdXj6np!p@gbuNI;vPLZlisO6}C>aj&21 z>F8)MU`&^KyQinon2C-)ecbKFFnsk!1@lpr!)fQJg`kzA7K&buS~zMUYWXK`z3fKSi5gfVgrkph4r0> zzy{VrvSG2QUuJ~lEX3K#LjT^qN>C}o^G}-WCn8N7X8L@;k9(i`(J!sB zF{B?oY<%0z&tcozI)1z3?2nB=9{<#OvPd$1a42$^zVLM689p-JrQsnL1zQG6SccZx z$_NLKCx7$_)M&3SCVIv-7qheowGR@;VQPy==N8DQZWF<^F=|E?Ila4BULzCH^O2g# zLR;js(;hUzbM*AHRx=v0$qAIDK6vnWwv-~x;__ZUu&`Lv7NICH^}=C?uRZXEk~Hy@ zc5#G|lr}6;FHUi&3-_~S__7~1%bHrYKdG_BTsZXEqd6CBrDz~>g13>#Il=9qaHrIV z_|+4Ymk&YkdLW~6qh!VE85P4!H!aF*b>>+#b{&^a>2lm-e zId|`#DSxP%y{z=}q&R#UH0*tf>l0XpzBM!@;63F{q_~Nq5~q{Hp*=)qY*b!M%E|K` zjqW(t0Xd3Gmjp5+dJ^Tx#FXsF)%SHn$&0^99Evmk+0VXScm;3rTz`4oga_TZrJ2)w zz4+ZcClp^TBfVVPgB&>R=fv2~HinN=mEU+c_643Mr>XWvTpue?DGz$!0(4&m4g5YK znH_TD84rTj`S8T-nG6!4WdVsKZ?y(2DeY|BGbC?(k+sfgWl>yByt7!iM`m-7ep1yH zQdyJ7Dx^D>UW5pb@wZ(Il#xRs5WHIJ+M$h984VzErOf0r6gEuPk3<&k^$UwQ_J29H zz@)c%qrNQ?VyG=*B1o#zYt+QJik;hxb8%i*1X&CVLMksSC(+C8L+C;10sJyrz)X^h zONpQuC6=HrzcR6n8I~yW4W?2YE(h7ku~T)Otd?UcQcv}%!cdN#Oh8c<&9~}VD8;sS z_VKQ0)de*KhZ>r*C5RaEL~xR$anvJhzy#`+F*r?IK*i<~E=s3t*}((iDZ&CjfG@}L zhZyPwwCkX_9uL44ZAh~f5L*hOg_dm^fSrdOcZM zHhCr`SYCEINl#3i$ej3?NS(-yAl^dTMfBz5LQqZn6koiwAkI!*}mn^(=c* zI@c+e-J-Bf*Gmg4S#pgLp6Q=RK~eKV7AGr-D9Y|?0Fw)FjH(7@0z(2xaJ=OxYQ z+)lHTWFuhq5yr@?-(5kFP-s9K`aL@>bND^ET{=p&7oFK!Kig_uhJ}>|0l&S(>0@W@ zUj{Cn+*VwtTxPHW7X%4W6ylx@RJX(=!9XBGya)(hr?5=U9HyjB&F4X%>{4jSIbBUW z!0rRP0oUy2mF+I);QHO^s< zpiO-|Y$`U*Qxxi37|~p0k6F4$X)7LXD8u-0DaF4SJaBGrS5D%tGo0fR`=h1ZwA?G2?W8*U$7CZKy{&uhr z{a7W0<`A%vV`8*>=$GpHBNNkYU&VV6VC#&e*Qq)R(toS70^16$XVE#J0#8qgpObav z*h)Q{s-CKDU-ZHS!AUl-1DlTPc>i?!aC&N2IOi4HJk@g-NbmFIU(mZW>MRvu%q+I_zp4jpymSgvsMn@zCB{GbCT6K~!2Q5cw*#Yi0aSi_b2tP_U%1+9H zK1cQx?yZ5dtARLE5@Ms~w-~R|G^5B#W3)yKd>mA}lt8diwmA3ev+6;a!|seNxk}9?GrdHfa$Gb zQ3!O?kQe7sP6yzQ{5iC@gHd0N2LN3j5mV|sR@C{T?zrwM?9MtP1j;bQA&yzvU1Y8R z5N3g~z3dWcI*NmSEu@O*ovc93E|ITmvP+#yf`mhlz+oaUt@_B`)sJBXGvyEeEq^ck zzOj$J%;9o0iPg_K7ioBXpkWX*eX-+ z<3LjVPo?XArB!>yglR7WH&)|@rk=~1`pE5|9Z=MZoF&Woq%`Jz1b5I*MVRAVT4P6-e6f3cmFKI?zjt|aBnX;}ba%vAD{ z&=IMeD|9a$35a4ea@m{Eu}b)gvNsWL9OLpEKG)Ep@C=fI^4aQu^r8ofTH1&yiPbO+ z*WcXQfB&}Dtf&0V(Myq!Wb`0%XD9J^T*iyiM`?nGo!xvPWj2QDW8zXdlbO7^$s|7~ z-8U2TqgYeZlUeI~K`z8C(9K5N!ViEWVKystr>_^{77*S;6{o3N5FC-K0l)ClGjk$n zhek*|KH$9JK=siydzQ@F($R6T9OAsUJL8-~?#^8l>SHtV#fyFd_J}jkKJ5a)Q-F>( z{9-7h-&xx=Zh0&4D?1PVnXj4PuMN4oKH}UXlg?QOMhqk=ekk#mfENP;hNbxM>6QC$vXj`eePcaT!?0r%#3cyn%deq~k*= zsa0QFV6Qbc-rH7KG`~Ngf&VpJxbdo8yYSDz&whvBwD0YeZ0(O;46hx{YyD9^{~^3O zoxivH1ozk>0Ew)S~{9Rj)dg4Ho6lXKL5t{-nLK zq1xNnTISfaX_(|Y^!H2r*Bqy#cDvq$g0*8*eK82~Zy;)CQ_D z+MI$)%cW47Lq9Q4_r>+F0;x|Trt~_F87s`FWU2icw~)D%m6pR&dn_CY*?8~>7QFV0 zoRz?5!%!M;^#F-P09`_apna~mPv@Kn1tCTO!TVFiVPdJkA!Jwx5ldUKZ*K!vctP<; z1WJz-{ruV$|EsDn+}>V!UfmI~&OcFE)!Iv|kd;54oZJR}d>jq<=Xdmz7TBiw^+!=Z zL0{c^s(P`izmMTwBR9Jhyb51bd^z!%jVl9+aM+~~q&AvhsFFZQT!AZygp!cnVUXNu z5MM-WF-U$wxl1Ao#F<4lK|%b{URC|<_cvFtL=gW$k?Q9eSrkH`6&&p$a3kruR6yvPFjgiG zAb>cB59QYUEIpSIT6EUF_jm#MK{tf2e zsF})_2k$hIG+;q}*4J&8d@=|4#Z{XplDw?8JY`Lbn6TlkaJULK<9h@=4fmrzzLgbP z*w8fi7MKE1(+XfVAfTxNEsO$~sbK&UKuTSRE5OJq3_}(f{2KSqjNiix_$%f9rE1roVT2}Ycltp=AQi1 zTbg=v$GJzxEdKaaap8UcxxZgLx9LBg{de@-4T01x1I$c?#B2w=i;1+W3#`hGr2qWC z36Yg46OBlfg=iOjhnaP!8*Rp&W#;c*1))|YBThu6Mr0>GgQ+&7D=xyVCgRWU0kIb$ zGk<_;55RVS>e~;de*$1N20^n9Au$&LuOH$pCc~;OqbN6nraxpPMn$4dB_LM?o?Pc0 zWXGFqrx|sJmwjm!gh`W(DG`+kkDcobq|1t|s|dA=hP`bB#7%PKM5YZzKnKr0263l7Z!>X`85tlGR7J)1 z8yUekOw=?YW-c1dv#qZvsuXqAg~z6Xk$)yGt%3Lt)Fu{uYX*7|I|hUoTV0gIi8Wa6 zTX9p*{c|Br8Z=i-nbY*?E+!oc0Vn2UTiB;>W0EAOWN?fT`uP!k4*LTUGc$F)P z)Nv-@P<4MCpF)f!LMSmRTUoPb7(2CgaNi_D zvrTsq&pj|;Pj6I_R^@gYDtKm2gtF$rM4{gDs>E7N+fzZP%+k>XN~BXcD{`iOIl=Et z{MMFw=ff;#@5nS*gsqZHGvN;-fyYSeD-P;hq}wTAdhTE*d+Qd3v`q)u2_=ZRuhW8%FVY(EVF>D z_2Sr5Pm#0gs0BsEENsM#^9rf3e9ag|_Jc&k+I^4}yBRaTI&;oyyLCoejF*rdMJmt!6ZOhaQ8gtCa(9y`}3 zBuObAI^eV{<^y+ZF2znTJE~%0&7|C|`C1raU#5P^hghUTmQv(dEJ|o7AdBaPHI}I>PK9l=3K;MW-R2 zQCBA;<7=B$Iac2%XI}>h%6w2cl6mkYn&sP(y z8HB|-ye6rNPIOgL9Mr{r|2jN>R;+HfFte5@>gd*tG+A$@+Tef%nJrjnqG(8b-o<6& z2&FWf$4RL)Z4=BM5Uwo`Jd03f)OZmD&1l8O;>eq`QXWy(rKB`)M+nxNkZcaB9jpk?RQ;dP?Sc^ zNsg3qqYrv&OmEX*)bh^S=v=%qz4g~p@okEsh8fanfBSu|yym5_3jb!O+2@fWWFG^? z$Fr!Z7oCQ7&E*8QF?~p!d%X;#XyQR$FUAEkzFMz|Y{k5X%ZvtHFm;4k8lx!m*c3}H z*H{drP!pB+b|>L{2efNsE6LF-WTjWz>)EhP-)+{ptTeMNi0UUK==S(|i5Z48^~=0u zy#9NdfRk_4iTJaNgF|6I_Ko-G*A>#r(L=fli6q0X!QfAn9>KVW z(gqjq>CaGXkV9TPWuDC)&W%oDx2K?c;|L`A91x636eb#Nuw2x)H~$7kb;k?)Ur5z0 zu7I72Za{u&LI)05(oF4(8ptsXGoJ$}OIg>?ySsbyDra~eEd?lpK|+}hAH|`;>E7H3==XkBR4(C)+FczLo1@u8n7u?&ON=BYsQ!g+`OL90c! z75Civ=gMgjZMMDACSgTY-C~&Pa?LLi&x+f=Po-g)a#Toj3!z|_9Mf^M0_m6@wc^SQ zh8Q$>ICn`fdq9jAdg$vn7t!y=4lEjbtL&&+4h@pWFuH{JNvnXe@7Vx2oK2Xiw3uj_ zN;yYjAvLkdaD$l@)aB56rm%jC{8gx+7@lxN$^rr0 z4SBCtj0Mjy0!YBZN#_-#?TSXJe0DawfEz+qP8Zf_CaqrY4}AAritQD0lhGfdj^Pfy zKZ%eJHjaePx+a`$d;CP#>HgD1_CSs@_)h00n?_(llIDEYAedgL$HaOkD26N=mgGtL zQS6ixP7|5$qk5rasR|8##T=wzmK6FRC7=%u-Wo&TR^K7jJQck`aEey`Le{`5N3Qu;a>5 z{9v}`Mpa#dI(GUcHY~U=@J@Cg6X>(5)WZ*0Abbssox$B(i`*=SlR-IeaGY5lVm#2X z)EM`!uB&C@40L_%HN@!J>2~UU6PVP+wGCXvL7Op;#lgYpx4!?1K8{xZM`9uwJ#yEcX zTS%y(MO1?;x;`Y+4g~>G@L?A|Tj~YYc6MZNy{A;L7%q5%vJ4s77U@evUaFxWsnh+` zU2YSlY$A8JsdF%j+nN)pwRKqA)yl6n-P-lGpP5(RdiTx3HLBA$kB~b%=My6#3& z>`u>{ep0#3rSm)cusS2_g=q7*E4tRBEh&DNNupriop%^sI!jvRq0w;d%Y7MK?`E}Z zo?qiue?MZ=0V>q#l&N#QbQfd9(a~zISW^QXKOcKhHly1$+hE&9M?#u6p6W`MRs@td zeYhfbk6mLoyj-6-RmeXf5-b2fY5iX2s z1ui}g&vyzaEUG-4H&{sqMgU>!D|9~ks_qHgPOi61FKa~&U?ge zt(Hv~wLVMZFPTdeyy9ud&Z7G9^Vo|5y}U_QE|sl(QTgN^LF^%Ji0DJIO087n9`xMW zy#K?>3GiBWCC}N)CR?M^`tH6X(qG@RZoZgoZC`dk^%`5U zY|V#TUD75aIeK0o=58a!CmnO~iC^o3T@XI;o@J?V!lV%Nr3!_r}CGrkfj0 zD5Sc$6nbZ^Gif_~E6@*7>EWzYNaY4h++XwOZ|}U^q(S60u)ex$RTSd_>c;fjysK{v zm&x>8)gsUACT^a#UoISm<~-F2xW%vCidf(X%WBtI{3OmzJT*YWRE2{jy4cNz@yI#hYw%)pL9~ccRVu>3RG`tu_x_t1ILNwabn1kP^91>g@3-Ht9DJb##MoC$*w7ks> zk&nqOzv_QqEnCX~!X(wA$(61p(%&+`O~Rna^xAXlW?$XW$M3s?yi%S!qdwOB8pScjU#t3?0 zsSk=Bnf}QI0FZb@kPCyEKn0~I>qovezb2x6%JcR}_yE=G9enDTJyryRZP?~Q@hm}W zjL?DJG$XJDJte0UFO$iZ`1|;zt~IPyH;OjgVre4Z#Batg3mrFeD=xLK**mXJEtHfW z63}myu^XEE$UOK)oWs{OMPeI1p~&1v>peI9p9=tbUc2Bw9F?+u2obYZ^7{C)ABPuY zICYvI@b6-2gz^w7rR)VEJ(f-*K=cIYxa22Q(g=_KtVt<+dPDGsW*PyK!9)KhfJQ)m zLNWOCA33x?vHzzT@q_yD*Ano-YQGdDPEsd>*?v>vcxgD{3RufHkTt9a^o zA1s0TRU3p7o^*o$rfdZ8)UiwakhUZ_G{!kNq055immIAo%kC*G7IqKN|<9I^fu1elh=M5x-tl_QDp={Im}O^Q#64 iUv<(FelY+*4xagG7usqh1S0`Z;g9Om0055$;p#sfif;Y@ literal 0 HcmV?d00001 diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/loc_chr_rom.vhd b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/loc_chr_rom.vhd new file mode 100644 index 00000000..c2d9ac92 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/loc_chr_rom.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity loc_chr_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of loc_chr_rom is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"0E",X"01",X"01",X"01",X"0F",X"0F",X"0E",X"00",X"07",X"08",X"08",X"08",X"0F",X"0F",X"07", + X"00",X"00",X"00",X"0F",X"0F",X"0F",X"00",X"00",X"00",X"00",X"00",X"0F",X"0F",X"07",X"04",X"00", + X"00",X"01",X"09",X"0D",X"0F",X"07",X"03",X"01",X"00",X"07",X"0F",X"0F",X"08",X"08",X"08",X"06", + X"00",X"0E",X"0F",X"0F",X"01",X"01",X"01",X"06",X"00",X"06",X"0F",X"0F",X"09",X"08",X"08",X"04", + X"00",X"04",X"0F",X"0F",X"0F",X"04",X"04",X"0C",X"00",X"00",X"0F",X"0F",X"07",X"02",X"01",X"00", + X"00",X"0E",X"0F",X"0F",X"01",X"01",X"02",X"02",X"00",X"08",X"09",X"09",X"09",X"09",X"09",X"0F", + X"00",X"0E",X"01",X"01",X"01",X"0F",X"0F",X"0E",X"00",X"04",X"09",X"09",X"09",X"0F",X"0F",X"07", + X"00",X"00",X"00",X"08",X"0F",X"0F",X"03",X"01",X"00",X"0C",X"0E",X"0F",X"0B",X"08",X"08",X"08", + X"00",X"0E",X"0F",X"0D",X"09",X"01",X"01",X"0E",X"00",X"00",X"06",X"09",X"0B",X"0F",X"07",X"00", + X"00",X"0E",X"0F",X"0F",X"09",X"09",X"09",X"02",X"00",X"07",X"0F",X"0F",X"08",X"08",X"08",X"07", + X"0C",X"02",X"01",X"05",X"05",X"09",X"02",X"0C",X"03",X"04",X"08",X"0A",X"0A",X"09",X"04",X"03", + X"0F",X"01",X"01",X"01",X"01",X"01",X"01",X"0F",X"0F",X"08",X"08",X"08",X"08",X"08",X"08",X"0F", + X"00",X"00",X"00",X"0A",X"0A",X"00",X"00",X"00",X"00",X"00",X"00",X"07",X"07",X"00",X"00",X"00", + X"00",X"00",X"00",X"04",X"04",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"02",X"00",X"00",X"00", + X"00",X"00",X"06",X"06",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"08",X"0C",X"0E",X"0C",X"08",X"00",X"00",X"03",X"07",X"07",X"03",X"07",X"07",X"03", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"07",X"0F",X"0E",X"0A",X"02",X"0E",X"03",X"00",X"00",X"01",X"07",X"0F",X"03",X"00",X"00", + X"00",X"0E",X"01",X"01",X"01",X"0F",X"0F",X"0F",X"00",X"06",X"09",X"09",X"09",X"0F",X"0F",X"0F", + X"00",X"06",X"01",X"01",X"01",X"0F",X"0F",X"0E",X"00",X"04",X"08",X"08",X"08",X"0F",X"0F",X"07", + X"00",X"0C",X"02",X"01",X"01",X"0F",X"0F",X"0F",X"00",X"03",X"04",X"08",X"08",X"0F",X"0F",X"0F", + X"00",X"01",X"01",X"01",X"01",X"0F",X"0F",X"0F",X"00",X"09",X"09",X"09",X"09",X"0F",X"0F",X"0F", + X"00",X"00",X"00",X"00",X"00",X"0F",X"0F",X"0F",X"00",X"09",X"09",X"09",X"09",X"0F",X"0F",X"0F", + X"00",X"0E",X"01",X"01",X"01",X"0F",X"0F",X"0E",X"00",X"05",X"09",X"09",X"08",X"0F",X"0F",X"07", + X"00",X"0F",X"00",X"00",X"00",X"0F",X"0F",X"0F",X"00",X"0F",X"01",X"01",X"01",X"0F",X"0F",X"0F", + X"00",X"00",X"00",X"0F",X"0F",X"0F",X"00",X"00",X"00",X"00",X"00",X"0F",X"0F",X"0F",X"00",X"00", + X"00",X"0E",X"0F",X"0F",X"01",X"01",X"01",X"02",X"00",X"0F",X"0F",X"0F",X"00",X"00",X"00",X"00", + X"00",X"03",X"0C",X"00",X"00",X"0F",X"0F",X"0F",X"00",X"08",X"04",X"03",X"02",X"0F",X"0F",X"0F", + X"00",X"01",X"01",X"01",X"01",X"0F",X"0F",X"0F",X"00",X"00",X"00",X"00",X"00",X"0F",X"0F",X"0F", + X"00",X"0F",X"08",X"0C",X"0E",X"0C",X"08",X"0F",X"00",X"0F",X"07",X"03",X"01",X"03",X"07",X"0F", + X"00",X"0F",X"0F",X"0E",X"0C",X"08",X"00",X"0F",X"00",X"0F",X"00",X"01",X"03",X"07",X"0F",X"0F", + X"00",X"0E",X"01",X"01",X"01",X"0F",X"0F",X"0E",X"00",X"07",X"08",X"08",X"08",X"0F",X"0F",X"07", + X"00",X"08",X"04",X"04",X"04",X"0F",X"0F",X"0F",X"00",X"07",X"08",X"08",X"08",X"0F",X"0F",X"0F", + X"00",X"0F",X"03",X"0D",X"01",X"0F",X"0F",X"0E",X"00",X"07",X"08",X"08",X"08",X"0F",X"0F",X"07", + X"00",X"09",X"05",X"06",X"04",X"0F",X"0F",X"0F",X"00",X"07",X"08",X"08",X"08",X"0F",X"0F",X"0F", + X"00",X"06",X"0F",X"0F",X"0F",X"09",X"01",X"02",X"00",X"04",X"08",X"09",X"0F",X"0F",X"0F",X"06", + X"00",X"00",X"00",X"0F",X"0F",X"0F",X"00",X"00",X"00",X"08",X"08",X"0F",X"0F",X"0F",X"08",X"08", + X"00",X"0E",X"01",X"01",X"01",X"0F",X"0F",X"0E",X"00",X"0F",X"00",X"00",X"00",X"0F",X"0F",X"0F", + X"00",X"00",X"00",X"0C",X"0F",X"0E",X"08",X"00",X"00",X"0C",X"03",X"00",X"00",X"03",X"0F",X"0E", + X"00",X"0F",X"0E",X"0C",X"08",X"0C",X"0E",X"0F",X"00",X"0F",X"01",X"03",X"07",X"03",X"01",X"0F", + X"00",X"07",X"0E",X"0C",X"08",X"04",X"02",X"01",X"00",X"08",X"04",X"03",X"03",X"07",X"0E",X"0C", + X"00",X"00",X"00",X"00",X"08",X"0C",X"02",X"01",X"00",X"0C",X"02",X"01",X"03",X"07",X"0F",X"0E", + X"00",X"01",X"01",X"09",X"0F",X"0F",X"0F",X"03",X"00",X"08",X"0E",X"0F",X"0F",X"0B",X"08",X"08", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"03",X"03",X"03",X"03",X"00", + X"0C",X"06",X"02",X"02",X"02",X"02",X"06",X"0C",X"07",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"07", + X"08",X"08",X"08",X"08",X"08",X"08",X"08",X"08",X"01",X"07",X"03",X"03",X"03",X"03",X"03",X"03", + X"0C",X"0E",X"0E",X"0E",X"0C",X"08",X"00",X"0E",X"07",X"08",X"08",X"00",X"01",X"03",X"07",X"0F", + X"0C",X"0E",X"0E",X"0C",X"0E",X"0E",X"0E",X"0C",X"07",X"08",X"00",X"01",X"00",X"08",X"08",X"07", + X"0C",X"0C",X"0C",X"0C",X"0C",X"0E",X"0C",X"0C",X"00",X"01",X"03",X"05",X"09",X"0F",X"01",X"01", + X"0C",X"00",X"00",X"0C",X"0E",X"0E",X"0E",X"0C",X"0F",X"08",X"08",X"0F",X"00",X"00",X"0C",X"03", + X"0C",X"02",X"00",X"0C",X"02",X"02",X"02",X"0C",X"07",X"0E",X"0E",X"0F",X"0E",X"0E",X"0E",X"07", + X"0E",X"0E",X"0C",X"08",X"08",X"00",X"00",X"00",X"0F",X"00",X"01",X"01",X"03",X"03",X"07",X"0F", + X"08",X"04",X"04",X"08",X"0E",X"0E",X"06",X"0C",X"03",X"06",X"07",X"07",X"09",X"08",X"08",X"07", + X"0C",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0C",X"07",X"08",X"08",X"08",X"07",X"00",X"08",X"07", + X"08",X"0E",X"00",X"02",X"0A",X"0A",X"0E",X"00",X"00",X"01",X"00",X"02",X"02",X"02",X"03",X"00", + X"00",X"0C",X"02",X"02",X"0E",X"00",X"0E",X"04",X"00",X"00",X"01",X"01",X"01",X"00",X"01",X"00", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"74",X"BA",X"DD",X"EE",X"FF",X"33",X"CC",X"F3",X"BB",X"BB",X"D5",X"D5",X"E2",X"F1",X"F0",X"F0", + X"F0",X"F0",X"F8",X"74",X"BA",X"BA",X"DD",X"DD",X"FC",X"33",X"CC",X"FF",X"77",X"BB",X"D5",X"E2", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"34",X"1A",X"0D",X"0E",X"0F",X"03",X"0C",X"C3",X"0B",X"0B",X"85",X"85",X"C2",X"E1",X"F0",X"F0", + X"F0",X"F0",X"78",X"34",X"1A",X"1A",X"0D",X"0D",X"3C",X"03",X"0C",X"0F",X"07",X"0B",X"85",X"C2", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"00",X"D5",X"D5",X"D5",X"E2",X"E2",X"E2",X"F1",X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F8",X"F8",X"00",X"BA",X"BA",X"BA",X"DD",X"DD",X"EE",X"66", + X"66",X"77",X"BB",X"BB",X"D5",X"D5",X"D5",X"D5",X"F1",X"F1",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F8",X"74",X"74",X"74",X"BA",X"BA",X"BA",X"BA", + X"00",X"85",X"85",X"85",X"C2",X"C2",X"C2",X"E1",X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"78",X"78",X"00",X"1A",X"1A",X"1A",X"0D",X"0D",X"0E",X"06", + X"06",X"07",X"0B",X"0B",X"85",X"85",X"85",X"85",X"E1",X"E1",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"78",X"34",X"34",X"34",X"1A",X"1A",X"1A",X"1A", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"FE",X"11",X"F0",X"F0",X"F0",X"F0",X"F0",X"FF",X"00",X"FF", + X"E0",X"E0",X"E0",X"E0",X"E0",X"EE",X"00",X"EE",X"F0",X"F0",X"F0",X"FC",X"33",X"CC",X"FF",X"77", + X"EE",X"FF",X"33",X"CC",X"F3",X"F0",X"F0",X"F0",X"FF",X"00",X"FF",X"F0",X"F0",X"F0",X"F0",X"F0", + X"EE",X"00",X"EE",X"E0",X"E0",X"E0",X"E0",X"E0",X"88",X"F7",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"1E",X"01",X"F0",X"F0",X"F0",X"F0",X"F0",X"0F",X"00",X"0F", + X"E0",X"E0",X"E0",X"E0",X"E0",X"0E",X"00",X"0E",X"F0",X"F0",X"F0",X"3C",X"03",X"0C",X"0F",X"07", + X"0E",X"0F",X"03",X"0C",X"C3",X"F0",X"F0",X"F0",X"0F",X"00",X"0F",X"F0",X"F0",X"F0",X"F0",X"F0", + X"0E",X"00",X"0E",X"E0",X"E0",X"E0",X"E0",X"E0",X"08",X"87",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"DD",X"DD",X"BA",X"BA",X"74",X"F8",X"F0",X"F0",X"E2",X"D5",X"BB",X"77",X"FF",X"CC",X"33",X"FC", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F3",X"CC",X"33",X"FF",X"EE",X"DD",X"BA",X"74",X"F0",X"F0",X"F1",X"E2",X"D5",X"D5",X"BB",X"BB", + X"0D",X"0D",X"1A",X"1A",X"34",X"78",X"F0",X"F0",X"C2",X"85",X"0B",X"07",X"0F",X"0C",X"03",X"3C", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"C3",X"0C",X"03",X"0F",X"0E",X"0D",X"1A",X"34",X"F0",X"F0",X"E1",X"C2",X"85",X"85",X"0B",X"0B", + X"00",X"D5",X"D5",X"D5",X"BB",X"BB",X"77",X"66",X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F1",X"F1", + X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"00",X"BA",X"BA",X"BA",X"74",X"74",X"74",X"F8", + X"F1",X"E2",X"E2",X"E2",X"D5",X"D5",X"D5",X"D5",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F8",X"F8",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"66",X"EE",X"DD",X"DD",X"BA",X"BA",X"BA",X"BA", + X"00",X"85",X"85",X"85",X"0B",X"0B",X"07",X"06",X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"E1",X"E1", + X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"00",X"1A",X"1A",X"1A",X"34",X"34",X"34",X"78", + X"E1",X"C2",X"C2",X"C2",X"85",X"85",X"85",X"85",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"78",X"78",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"06",X"0E",X"0D",X"0D",X"1A",X"1A",X"1A",X"1A", + X"F0",X"F0",X"F0",X"F3",X"CC",X"33",X"FF",X"EE",X"F0",X"F0",X"F0",X"F0",X"F0",X"FF",X"00",X"FF", + X"E0",X"E0",X"E0",X"E0",X"E0",X"EE",X"00",X"EE",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F7",X"88", + X"11",X"FE",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"FF",X"00",X"FF",X"F0",X"F0",X"F0",X"F0",X"F0", + X"EE",X"00",X"EE",X"E0",X"E0",X"E0",X"E0",X"E0",X"77",X"FF",X"CC",X"33",X"FC",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"C3",X"0C",X"03",X"0F",X"0E",X"F0",X"F0",X"F0",X"F0",X"F0",X"0F",X"00",X"0F", + X"E0",X"E0",X"E0",X"E0",X"E0",X"0E",X"00",X"0E",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"87",X"08", + X"01",X"1E",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"0F",X"00",X"0F",X"F0",X"F0",X"F0",X"F0",X"F0", + X"0E",X"00",X"0E",X"E0",X"E0",X"E0",X"E0",X"E0",X"07",X"0F",X"0C",X"03",X"3C",X"F0",X"F0",X"F0", + X"D5",X"D5",X"D5",X"D5",X"D5",X"DD",X"00",X"DD",X"F0",X"F0",X"F0",X"F0",X"F0",X"FF",X"00",X"FF", + X"F0",X"F0",X"F0",X"F0",X"F0",X"FF",X"00",X"FF",X"BA",X"BA",X"BA",X"BA",X"BA",X"BB",X"00",X"BB", + X"DD",X"00",X"DD",X"D5",X"D5",X"D5",X"D5",X"D5",X"FF",X"00",X"FF",X"F0",X"F0",X"F0",X"F0",X"F0", + X"FF",X"00",X"FF",X"F0",X"F0",X"F0",X"F0",X"F0",X"BB",X"00",X"BB",X"BA",X"BA",X"BA",X"BA",X"BA", + X"85",X"85",X"85",X"85",X"85",X"8D",X"00",X"8D",X"F0",X"F0",X"F0",X"F0",X"F0",X"FF",X"00",X"FF", + X"F0",X"F0",X"F0",X"F0",X"F0",X"FF",X"00",X"FF",X"1A",X"1A",X"1A",X"1A",X"1A",X"1B",X"00",X"1B", + X"8D",X"00",X"8D",X"85",X"85",X"85",X"85",X"85",X"FF",X"00",X"FF",X"F0",X"F0",X"F0",X"F0",X"F0", + X"FF",X"00",X"FF",X"F0",X"F0",X"F0",X"F0",X"F0",X"1B",X"00",X"1B",X"1A",X"1A",X"1A",X"1A",X"1A", + X"D5",X"D5",X"D5",X"D5",X"D5",X"0D",X"00",X"0D",X"F0",X"F0",X"F0",X"F0",X"F0",X"0F",X"00",X"0F", + X"F0",X"F0",X"F0",X"F0",X"F0",X"0F",X"00",X"0F",X"BA",X"BA",X"BA",X"BA",X"BA",X"0B",X"00",X"0B", + X"0D",X"00",X"0D",X"D5",X"D5",X"D5",X"D5",X"D5",X"0F",X"00",X"0F",X"F0",X"F0",X"F0",X"F0",X"F0", + X"0F",X"00",X"0F",X"F0",X"F0",X"F0",X"F0",X"F0",X"0B",X"00",X"0B",X"BA",X"BA",X"BA",X"BA",X"BA", + X"85",X"85",X"85",X"85",X"85",X"0D",X"00",X"0D",X"F0",X"F0",X"F0",X"F0",X"F0",X"0F",X"00",X"0F", + X"F0",X"F0",X"F0",X"F0",X"F0",X"0F",X"00",X"0F",X"1A",X"1A",X"1A",X"1A",X"1A",X"0B",X"00",X"0B", + X"0D",X"00",X"0D",X"85",X"85",X"85",X"85",X"85",X"0F",X"00",X"0F",X"F0",X"F0",X"F0",X"F0",X"F0", + X"0F",X"00",X"0F",X"F0",X"F0",X"F0",X"F0",X"F0",X"0B",X"00",X"0B",X"1A",X"1A",X"1A",X"1A",X"1A", + X"F0",X"F0",X"F0",X"F0",X"F0",X"FF",X"00",X"FF",X"F0",X"F0",X"F0",X"F0",X"F0",X"FF",X"00",X"FF", + X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"00",X"BA",X"BA",X"BA",X"BA",X"BA",X"BA",X"BA", + X"FF",X"00",X"FF",X"F0",X"F0",X"F0",X"F0",X"F0",X"FF",X"00",X"FF",X"F0",X"F0",X"F0",X"F0",X"F0", + X"00",X"D5",X"D5",X"D5",X"D5",X"D5",X"D5",X"D5",X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"0F",X"00",X"0F",X"F0",X"F0",X"F0",X"F0",X"F0",X"0F",X"00",X"0F", + X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"00",X"1A",X"1A",X"1A",X"1A",X"1A",X"1A",X"1A", + X"0F",X"00",X"0F",X"F0",X"F0",X"F0",X"F0",X"F0",X"0F",X"00",X"0F",X"F0",X"F0",X"F0",X"F0",X"F0", + X"00",X"85",X"85",X"85",X"85",X"85",X"85",X"85",X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"95",X"4A",X"2D",X"1E",X"0F",X"C3",X"3C",X"8B",X"4B",X"4B",X"A5",X"A5",X"D6",X"A3",X"D5",X"A2", + X"10",X"BA",X"54",X"BA",X"54",X"1E",X"F0",X"1E",X"00",X"AA",X"55",X"2E",X"C3",X"3C",X"0F",X"87", + X"55",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"AA",X"D5",X"A2",X"D5",X"A2",X"D5",X"A2",X"D5",X"A2", + X"1E",X"F0",X"1E",X"BA",X"54",X"BA",X"54",X"BA",X"78",X"8F",X"55",X"AA",X"55",X"AA",X"55",X"AA", + X"55",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"AA",X"D5",X"A2",X"D5",X"A2",X"D5",X"A2",X"D5",X"A2", + X"54",X"BA",X"54",X"BA",X"54",X"1E",X"F0",X"1E",X"55",X"AA",X"55",X"AA",X"55",X"AA",X"07",X"78", + X"47",X"3C",X"C3",X"0F",X"1E",X"2D",X"5B",X"A6",X"D5",X"A2",X"C5",X"92",X"A5",X"A5",X"4B",X"4B", + X"1E",X"F0",X"1E",X"BA",X"54",X"BA",X"54",X"1C",X"87",X"0F",X"3C",X"C3",X"1D",X"AA",X"55",X"8B", + X"11",X"AA",X"55",X"8B",X"3C",X"C3",X"0F",X"1E",X"80",X"A2",X"D5",X"A2",X"D5",X"0F",X"F0",X"0F", + X"2D",X"2D",X"5A",X"5A",X"94",X"3A",X"54",X"BA",X"56",X"AD",X"4B",X"87",X"0F",X"3C",X"C3",X"2E", + X"E1",X"0E",X"55",X"AA",X"55",X"AA",X"55",X"AA",X"0F",X"F0",X"0F",X"A2",X"D5",X"A2",X"D5",X"A2", + X"54",X"BA",X"54",X"BA",X"54",X"BA",X"54",X"BA",X"55",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"AA", + X"55",X"AA",X"55",X"AA",X"55",X"AA",X"0F",X"E1",X"D5",X"A2",X"D5",X"A2",X"D5",X"0F",X"F0",X"0F", + X"54",X"BA",X"54",X"BA",X"54",X"BA",X"54",X"BA",X"55",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"AA", + X"1E",X"0F",X"C3",X"3C",X"47",X"AA",X"55",X"0C",X"0F",X"F0",X"0F",X"A2",X"D5",X"A2",X"D5",X"83", + X"54",X"BA",X"5C",X"B6",X"5A",X"5A",X"2D",X"2D",X"1D",X"C3",X"3C",X"0F",X"87",X"4B",X"25",X"9A", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"F0",X"AA",X"45",X"AB",X"45",X"AB",X"4C",X"2A",X"5A",X"4A",X"5B",X"4A",X"2D",X"2D",X"1E",X"96", + X"55",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"F0",X"55",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"F0", + X"95",X"4A",X"2D",X"1E",X"0F",X"C3",X"3C",X"C3",X"4B",X"4B",X"25",X"AD",X"56",X"AB",X"55",X"F0", + X"F0",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"AA",X"F0",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"AA", + X"C3",X"3C",X"C3",X"0F",X"1E",X"2D",X"5B",X"A6",X"F0",X"AA",X"45",X"9A",X"25",X"AD",X"4B",X"4B", + X"45",X"9A",X"56",X"9A",X"25",X"AD",X"25",X"A5",X"55",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"F0", + X"5D",X"2A",X"45",X"AB",X"45",X"AB",X"44",X"F0",X"96",X"1E",X"2D",X"2D",X"5B",X"4A",X"5B",X"5A", + X"F0",X"AD",X"25",X"AD",X"4B",X"4B",X"87",X"96",X"F0",X"22",X"55",X"22",X"55",X"22",X"45",X"AB", + X"F0",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"AA",X"F0",X"4A",X"5B",X"4A",X"95",X"A6",X"95",X"2A", + X"2D",X"2D",X"5B",X"4A",X"95",X"2A",X"55",X"F0",X"56",X"AD",X"4B",X"87",X"0F",X"3C",X"C3",X"3C", + X"55",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"F0",X"55",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"F0", + X"F0",X"AA",X"5D",X"A6",X"5B",X"4A",X"2D",X"2D",X"3C",X"C3",X"3C",X"0F",X"87",X"4B",X"25",X"9A", + X"F0",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"AA",X"F0",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"AA", + X"96",X"87",X"4B",X"4B",X"25",X"AD",X"25",X"A5",X"45",X"23",X"55",X"22",X"55",X"22",X"55",X"F0", + X"55",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"F0",X"5D",X"A6",X"95",X"A6",X"5B",X"4A",X"5B",X"5A", + X"C4",X"EA",X"FD",X"FE",X"FF",X"F3",X"FC",X"33",X"FB",X"FB",X"F5",X"F5",X"B2",X"91",X"80",X"80", + X"10",X"10",X"10",X"10",X"10",X"FE",X"F0",X"FE",X"00",X"00",X"00",X"CC",X"F3",X"FC",X"FF",X"F7", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80", + X"FE",X"F0",X"FE",X"10",X"10",X"10",X"10",X"10",X"F8",X"77",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80", + X"10",X"10",X"10",X"10",X"10",X"FE",X"F0",X"FE",X"00",X"00",X"00",X"00",X"00",X"00",X"77",X"F8", + X"33",X"FC",X"F3",X"FF",X"FE",X"FD",X"EA",X"C4",X"80",X"80",X"91",X"B2",X"F5",X"F5",X"FB",X"FB", + X"FE",X"F0",X"FE",X"10",X"10",X"10",X"10",X"DC",X"F7",X"FF",X"FC",X"F3",X"CC",X"00",X"00",X"33", + X"00",X"00",X"00",X"33",X"FC",X"F3",X"FF",X"FE",X"80",X"80",X"80",X"80",X"80",X"FF",X"F0",X"FF", + X"FD",X"FD",X"FA",X"FA",X"D4",X"98",X"10",X"10",X"32",X"75",X"FB",X"F7",X"FF",X"FC",X"F3",X"CC", + X"F1",X"EE",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"F0",X"FF",X"80",X"80",X"80",X"80",X"80", + X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"F1",X"80",X"80",X"80",X"80",X"80",X"FF",X"F0",X"FF", + X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80", + X"FE",X"FF",X"F3",X"FC",X"33",X"00",X"00",X"CC",X"FF",X"F0",X"FF",X"80",X"80",X"80",X"80",X"B3", + X"10",X"10",X"98",X"D4",X"FA",X"FA",X"FD",X"FD",X"CC",X"F3",X"FC",X"FF",X"F7",X"FB",X"75",X"32", + X"F0",X"75",X"75",X"75",X"32",X"32",X"32",X"11",X"F0",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"F0",X"00",X"11",X"11",X"11",X"11",X"88",X"88",X"F0",X"EA",X"EA",X"EA",X"FD",X"FD",X"FE",X"F6", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"F0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"F0", + X"C4",X"EA",X"FD",X"FE",X"FF",X"F3",X"FC",X"F3",X"FB",X"FB",X"75",X"75",X"32",X"11",X"00",X"F0", + X"F0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"F0",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"F3",X"FC",X"F3",X"FF",X"FE",X"FD",X"EA",X"C4",X"F0",X"00",X"11",X"32",X"75",X"75",X"FB",X"FB", + X"11",X"32",X"32",X"32",X"75",X"75",X"75",X"F5",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"F0", + X"88",X"88",X"11",X"11",X"11",X"11",X"00",X"F0",X"F6",X"FE",X"FD",X"FD",X"EA",X"EA",X"EA",X"FA", + X"F0",X"75",X"75",X"75",X"FB",X"FB",X"F7",X"F6",X"F0",X"00",X"00",X"00",X"00",X"00",X"11",X"11", + X"F0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"F0",X"EA",X"EA",X"EA",X"C4",X"C4",X"C4",X"88", + X"FD",X"FD",X"EA",X"EA",X"C4",X"88",X"00",X"F0",X"32",X"75",X"FB",X"F7",X"FF",X"FC",X"F3",X"FC", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"F0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"F0", + X"F0",X"00",X"88",X"C4",X"EA",X"EA",X"FD",X"FD",X"FC",X"F3",X"FC",X"FF",X"F7",X"FB",X"75",X"32", + X"F0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"F0",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"F6",X"F7",X"FB",X"FB",X"75",X"75",X"75",X"F5",X"11",X"11",X"00",X"00",X"00",X"00",X"00",X"F0", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"F0",X"88",X"C4",X"C4",X"C4",X"EA",X"EA",X"EA",X"FA", + X"81",X"40",X"20",X"10",X"00",X"C0",X"30",X"08",X"40",X"40",X"A0",X"A0",X"94",X"82",X"85",X"82", + X"14",X"1A",X"14",X"1A",X"14",X"10",X"F0",X"10",X"05",X"0A",X"05",X"02",X"C0",X"30",X"00",X"80", + X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"85",X"82",X"85",X"82",X"85",X"82",X"85",X"82", + X"10",X"F0",X"10",X"1A",X"14",X"1A",X"14",X"1A",X"70",X"08",X"05",X"0A",X"05",X"0A",X"05",X"0A", + X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"85",X"82",X"85",X"82",X"85",X"82",X"85",X"82", + X"14",X"1A",X"14",X"1A",X"14",X"10",X"F0",X"10",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"00",X"70", + X"04",X"30",X"C0",X"00",X"10",X"20",X"41",X"82",X"85",X"82",X"84",X"90",X"A0",X"A0",X"40",X"40", + X"10",X"F0",X"10",X"1A",X"14",X"1A",X"14",X"1A",X"80",X"00",X"30",X"C0",X"01",X"0A",X"05",X"0A", + X"05",X"0A",X"05",X"08",X"30",X"C0",X"00",X"10",X"85",X"82",X"85",X"82",X"85",X"00",X"F0",X"00", + X"20",X"20",X"50",X"50",X"90",X"12",X"14",X"1A",X"20",X"40",X"80",X"00",X"00",X"30",X"C0",X"02", + X"E0",X"00",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"00",X"F0",X"00",X"82",X"85",X"82",X"85",X"82", + X"14",X"1A",X"14",X"1A",X"14",X"1A",X"14",X"1A",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A", + X"05",X"0A",X"05",X"0A",X"05",X"0A",X"00",X"E0",X"85",X"82",X"85",X"82",X"85",X"00",X"F0",X"00", + X"14",X"1A",X"14",X"1A",X"14",X"1A",X"14",X"1A",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A", + X"10",X"00",X"C0",X"30",X"04",X"0A",X"05",X"0A",X"00",X"F0",X"00",X"82",X"85",X"82",X"85",X"82", + X"14",X"1A",X"14",X"92",X"50",X"50",X"20",X"20",X"01",X"C0",X"30",X"00",X"80",X"40",X"20",X"18", + X"F0",X"28",X"20",X"28",X"14",X"18",X"14",X"0A",X"F0",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A", + X"F0",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"02",X"F0",X"40",X"41",X"40",X"20",X"20",X"10",X"90", + X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"F0",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"F0", + X"81",X"40",X"20",X"10",X"00",X"C0",X"30",X"C0",X"40",X"40",X"20",X"28",X"14",X"0A",X"05",X"F0", + X"F0",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"F0",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A", + X"C0",X"30",X"C0",X"00",X"10",X"20",X"41",X"82",X"F0",X"0A",X"04",X"18",X"20",X"28",X"40",X"40", + X"04",X"18",X"14",X"18",X"20",X"28",X"20",X"A0",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"F0", + X"05",X"02",X"05",X"0A",X"05",X"0A",X"05",X"F0",X"90",X"10",X"20",X"20",X"41",X"40",X"41",X"50", + X"F0",X"28",X"20",X"28",X"40",X"40",X"80",X"90",X"F0",X"0A",X"05",X"0A",X"05",X"0A",X"04",X"0A", + X"F0",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"F0",X"40",X"41",X"40",X"81",X"82",X"81",X"02", + X"20",X"20",X"41",X"40",X"81",X"02",X"05",X"F0",X"14",X"28",X"40",X"80",X"00",X"30",X"C0",X"30", + X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"F0",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"F0", + X"F0",X"0A",X"05",X"82",X"41",X"40",X"20",X"20",X"30",X"C0",X"30",X"00",X"80",X"40",X"20",X"18", + X"F0",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"F0",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A", + X"90",X"80",X"40",X"40",X"20",X"28",X"20",X"A0",X"04",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"F0", + X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"F0",X"05",X"82",X"81",X"82",X"41",X"40",X"41",X"50", + X"84",X"A6",X"84",X"A6",X"84",X"A6",X"84",X"A6",X"4B",X"4B",X"4B",X"4B",X"4B",X"4B",X"4B",X"4B", + X"00",X"AA",X"0F",X"F0",X"0F",X"0F",X"F0",X"0F",X"00",X"AA",X"0F",X"F0",X"0F",X"0F",X"F0",X"0F", + X"81",X"82",X"81",X"82",X"81",X"82",X"81",X"82",X"40",X"40",X"40",X"40",X"40",X"40",X"40",X"40", + X"05",X"0A",X"00",X"F0",X"00",X"00",X"F0",X"00",X"05",X"0A",X"00",X"F0",X"00",X"00",X"F0",X"00", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"0A", + X"C4",X"C4",X"C4",X"C4",X"C4",X"C4",X"C4",X"C4",X"FB",X"FB",X"FB",X"FB",X"FB",X"FB",X"FB",X"FB", + X"00",X"00",X"FF",X"F0",X"FF",X"FF",X"F0",X"FF",X"00",X"00",X"FF",X"F0",X"FF",X"FF",X"F0",X"FF", + X"08",X"0C",X"86",X"C2",X"C2",X"86",X"0C",X"08",X"07",X"1E",X"4B",X"0F",X"0F",X"4B",X"1E",X"07", + X"0C",X"86",X"4B",X"69",X"69",X"4B",X"86",X"0C",X"03",X"07",X"2D",X"0F",X"0F",X"2D",X"07",X"03", + X"88",X"CC",X"AE",X"2E",X"2E",X"AE",X"CC",X"88",X"77",X"FF",X"9F",X"FF",X"FF",X"9F",X"FF",X"77", + X"CC",X"EE",X"DF",X"9F",X"9F",X"DF",X"EE",X"CC",X"33",X"77",X"CF",X"FF",X"FF",X"CF",X"77",X"33", + X"2D",X"2D",X"2D",X"2D",X"2D",X"2D",X"2D",X"2D",X"56",X"12",X"56",X"12",X"56",X"12",X"56",X"12", + X"0F",X"F0",X"0F",X"0F",X"F0",X"0F",X"55",X"00",X"0F",X"F0",X"0F",X"0F",X"F0",X"0F",X"55",X"00", + X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"14",X"18",X"14",X"18",X"14",X"18",X"14",X"18", + X"00",X"F0",X"00",X"00",X"F0",X"00",X"05",X"0A",X"00",X"F0",X"00",X"00",X"F0",X"00",X"05",X"0A", + X"F0",X"AD",X"25",X"AD",X"16",X"9A",X"56",X"AB",X"F0",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"AA", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FD",X"FD",X"FD",X"FD",X"FD",X"FD",X"FD",X"FD",X"32",X"32",X"32",X"32",X"32",X"32",X"32",X"32", + X"FF",X"F0",X"FF",X"FF",X"F0",X"FF",X"00",X"00",X"FF",X"F0",X"FF",X"FF",X"F0",X"FF",X"00",X"00", + X"EE",X"DF",X"9F",X"9F",X"DF",X"EE",X"CC",X"00",X"77",X"CF",X"FF",X"FF",X"CF",X"77",X"33",X"00", + X"86",X"4B",X"69",X"69",X"4B",X"86",X"0C",X"00",X"07",X"2D",X"0F",X"0F",X"2D",X"07",X"03",X"00", + X"CC",X"EE",X"DF",X"9F",X"9F",X"DF",X"EE",X"CC",X"33",X"77",X"CF",X"FF",X"FF",X"CF",X"77",X"33", + X"0C",X"86",X"4B",X"69",X"69",X"4B",X"86",X"0C",X"03",X"07",X"2D",X"0F",X"0F",X"2D",X"07",X"03", + X"F0",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"F0",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"F0",X"FE",X"FE",X"FE",X"FE",X"FE",X"FE",X"FE",X"F0",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FE",X"FE",X"FE",X"FE",X"FE",X"FE",X"FE",X"FE",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + X"55",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"AA", + X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"F0",X"05",X"0A",X"05",X"0A",X"05",X"0A",X"05",X"F0", + X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"00",X"E0",X"E0",X"E0",X"E0",X"E0",X"E0",X"E0",X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"E0",X"E0",X"E0",X"E0",X"E0",X"E0",X"E0",X"E0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"0F",X"00",X"00",X"00",X"00",X"01",X"03",X"07",X"0F", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"08",X"0C",X"0E",X"0F",X"0C",X"0C",X"0C",X"0C", + X"0F",X"0F",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"07",X"03",X"01",X"00",X"00",X"00",X"00", + X"01",X"03",X"07",X"0F",X"03",X"03",X"03",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"DD",X"DD",X"99",X"99",X"55",X"DD",X"00",X"DD",X"E2",X"D5",X"BB",X"77",X"FF",X"CC",X"00",X"FF", + X"74",X"BA",X"DD",X"EE",X"FF",X"33",X"00",X"FF",X"BB",X"BB",X"99",X"99",X"AA",X"BB",X"00",X"BB", + X"DD",X"00",X"DD",X"55",X"99",X"99",X"DD",X"DD",X"FF",X"00",X"CC",X"FF",X"77",X"BB",X"D5",X"E2", + X"FF",X"00",X"33",X"FF",X"EE",X"DD",X"BA",X"74",X"BB",X"00",X"BB",X"AA",X"99",X"99",X"BB",X"BB", + X"F0",X"F1",X"F1",X"F3",X"F3",X"F3",X"F7",X"F7",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F1",X"F7",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"F0",X"F0",X"F0",X"F1",X"F1",X"F3",X"F7",X"FF", + X"F7",X"F7",X"F3",X"F3",X"F3",X"F1",X"F1",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"F7",X"F1",X"FF",X"F7",X"F3",X"F1",X"F1",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F7",X"FF",X"FF",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F3",X"F7", + X"F0",X"F0",X"F0",X"F7",X"FF",X"FF",X"FF",X"FF",X"F0",X"F0",X"F0",X"F0",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"F7",X"F0",X"F0",X"F0",X"F0",X"F0",X"F7",X"F3",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"FF",X"FF",X"FF",X"FF",X"F7",X"F0",X"F0",X"F0",X"FF",X"FF",X"FF",X"FF",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"0F",X"0D",X"0B",X"07",X"F0",X"F0",X"F0",X"F0",X"0F",X"0B",X"0D",X"0E", + X"E0",X"E0",X"E0",X"E0",X"0E",X"0C",X"0A",X"06",X"F0",X"F0",X"F0",X"F0",X"0F",X"0B",X"0D",X"0E", + X"07",X"0B",X"0D",X"0F",X"F0",X"F0",X"F0",X"F0",X"0E",X"0D",X"0B",X"0F",X"F0",X"F0",X"F0",X"F0", + X"06",X"0A",X"0C",X"0E",X"E0",X"E0",X"E0",X"E0",X"0E",X"0D",X"0B",X"0F",X"F0",X"F0",X"F0",X"F0", + X"00",X"0B",X"0D",X"0E",X"0E",X"0D",X"0B",X"0F",X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"00",X"0D",X"0B",X"07",X"07",X"0B",X"0D",X"0F", + X"0F",X"0B",X"0D",X"0E",X"0E",X"0D",X"0B",X"0F",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"0F",X"0D",X"0B",X"07",X"07",X"0B",X"0D",X"0F", + X"00",X"01",X"03",X"0E",X"0C",X"00",X"00",X"00",X"00",X"08",X"0C",X"07",X"03",X"00",X"00",X"00", + X"00",X"00",X"00",X"0C",X"0E",X"03",X"01",X"00",X"00",X"00",X"00",X"03",X"07",X"0C",X"08",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"01",X"0F",X"0F",X"F0",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"0F", + X"00",X"00",X"07",X"0F",X"0F",X"0F",X"0F",X"F0",X"00",X"00",X"00",X"03",X"0F",X"0F",X"0F",X"F0", + X"0F",X"0F",X"01",X"00",X"00",X"00",X"00",X"00",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"0F",X"0F",X"0F",X"0F",X"07",X"00",X"00",X"00",X"0F",X"0F",X"0F",X"03",X"00",X"00",X"00",X"00", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"F0",X"F0",X"01",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"F0", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"F0",X"F0",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"03",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"01",X"00", + X"F0",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"F0",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"E0",X"E0",X"E0",X"E0",X"E0",X"EE",X"00",X"EE",X"F0",X"F0",X"F0",X"F0",X"F0",X"FF",X"00",X"FF", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"BA",X"BA",X"BA",X"BA",X"BA",X"BA",X"BA",X"BA", + X"EE",X"00",X"EE",X"E0",X"E0",X"E0",X"E0",X"E0",X"FF",X"00",X"FF",X"F0",X"F0",X"F0",X"F0",X"F0", + X"D5",X"D5",X"D5",X"D5",X"D5",X"D5",X"D5",X"D5",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"E0",X"E0",X"E0",X"E0",X"E0",X"0E",X"00",X"0E",X"F0",X"F0",X"F0",X"F0",X"F0",X"0F",X"00",X"0F", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"1A",X"1A",X"1A",X"1A",X"1A",X"1A",X"1A",X"1A", + X"0E",X"00",X"0E",X"E0",X"E0",X"E0",X"E0",X"E0",X"0F",X"00",X"0F",X"F0",X"F0",X"F0",X"F0",X"F0", + X"85",X"85",X"85",X"85",X"85",X"85",X"85",X"85",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F3",X"CC",X"33",X"00",X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"FF",X"00",X"FF", + X"E0",X"E0",X"E0",X"E0",X"E0",X"EE",X"00",X"EE",X"F0",X"F0",X"F0",X"FC",X"33",X"CC",X"00",X"00", + X"00",X"00",X"33",X"CC",X"F3",X"F0",X"F0",X"F0",X"FF",X"00",X"FF",X"F0",X"F0",X"F0",X"F0",X"F0", + X"EE",X"00",X"EE",X"E0",X"E0",X"E0",X"E0",X"E0",X"00",X"00",X"CC",X"33",X"FC",X"F0",X"F0",X"F0", + X"00",X"D5",X"D5",X"D5",X"88",X"88",X"44",X"44",X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F1",X"F1", + X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F8",X"F8",X"00",X"BA",X"BA",X"BA",X"11",X"11",X"22",X"22", + X"44",X"44",X"88",X"88",X"D5",X"D5",X"D5",X"D5",X"F1",X"F1",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F8",X"F8",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"22",X"22",X"11",X"11",X"BA",X"BA",X"BA",X"BA", + X"00",X"04",X"E2",X"F3",X"FF",X"BB",X"EE",X"00",X"00",X"02",X"70",X"78",X"78",X"70",X"04",X"04", + X"88",X"89",X"C1",X"E1",X"E1",X"E1",X"E1",X"C1",X"33",X"22",X"70",X"70",X"70",X"70",X"70",X"70", + X"0F",X"0F",X"0F",X"0F",X"0F",X"F0",X"F0",X"F0",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"F0",X"F0", + X"0F",X"0F",X"0F",X"0F",X"0F",X"F0",X"F0",X"F0",X"0F",X"0F",X"0F",X"0F",X"0F",X"F0",X"F0",X"F0", + X"0F",X"0F",X"0F",X"0F",X"78",X"F0",X"F0",X"F0",X"0F",X"0F",X"0F",X"0F",X"0F",X"F0",X"F0",X"F0", + X"0F",X"0F",X"0F",X"0F",X"F0",X"F0",X"F0",X"F0",X"0F",X"0F",X"0F",X"0F",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"78",X"0F",X"0F",X"0F",X"0F",X"0F",X"F0",X"F0",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + X"F0",X"F0",X"F0",X"0F",X"0F",X"0F",X"0F",X"0F",X"F0",X"F0",X"F0",X"0F",X"0F",X"0F",X"0F",X"0F", + X"00",X"00",X"11",X"11",X"30",X"70",X"F0",X"E1",X"00",X"00",X"00",X"00",X"00",X"00",X"CC",X"FF", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"CC",X"CC",X"CC",X"88",X"88",X"C0",X"E0",X"F0",X"78", + X"E1",X"F0",X"70",X"30",X"11",X"11",X"33",X"33",X"33",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"FF",X"33",X"00",X"00",X"00",X"00",X"00",X"00",X"78",X"F0",X"E0",X"C0",X"88",X"88",X"00",X"00", + X"22",X"66",X"66",X"66",X"74",X"70",X"F0",X"E1",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"EE",X"FF",X"00",X"00",X"00",X"00",X"00",X"C0",X"F1",X"F0",X"78", + X"E1",X"F0",X"F8",X"30",X"00",X"00",X"00",X"00",X"00",X"FF",X"77",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"78",X"F0",X"E0",X"E2",X"66",X"66",X"66",X"44", + X"00",X"00",X"00",X"00",X"30",X"70",X"F0",X"E1",X"00",X"00",X"00",X"66",X"66",X"33",X"33",X"00", + X"00",X"88",X"88",X"00",X"00",X"00",X"00",X"00",X"00",X"11",X"77",X"66",X"C0",X"E0",X"F0",X"78", + X"E1",X"F0",X"70",X"30",X"66",X"EE",X"88",X"00",X"00",X"00",X"00",X"00",X"00",X"11",X"11",X"00", + X"00",X"CC",X"CC",X"66",X"66",X"00",X"00",X"00",X"78",X"F0",X"E0",X"C0",X"00",X"00",X"00",X"00", + X"F0",X"F0",X"F0",X"C3",X"0C",X"03",X"00",X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"0F",X"00",X"0F", + X"E0",X"E0",X"E0",X"E0",X"E0",X"0E",X"00",X"0E",X"F0",X"F0",X"F0",X"3C",X"03",X"0C",X"00",X"00", + X"00",X"00",X"03",X"0C",X"C3",X"F0",X"F0",X"F0",X"0F",X"00",X"0F",X"F0",X"F0",X"F0",X"F0",X"F0", + X"0E",X"00",X"0E",X"E0",X"E0",X"E0",X"E0",X"E0",X"00",X"00",X"0C",X"03",X"3C",X"F0",X"F0",X"F0", + X"00",X"85",X"85",X"85",X"08",X"08",X"04",X"04",X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"E1",X"E1", + X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"78",X"78",X"00",X"1A",X"1A",X"1A",X"01",X"01",X"02",X"02", + X"04",X"04",X"08",X"08",X"85",X"85",X"85",X"85",X"E1",X"E1",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"78",X"78",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"02",X"02",X"01",X"01",X"1A",X"1A",X"1A",X"1A", + X"00",X"EE",X"EE",X"EE",X"EE",X"EE",X"EE",X"EE",X"00",X"11",X"33",X"77",X"77",X"77",X"77",X"77", + X"00",X"EE",X"EE",X"EE",X"EE",X"EE",X"EE",X"EE",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"33", + X"EE",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"77",X"77",X"77",X"77",X"77",X"33",X"11",X"00", + X"EE",X"EE",X"EE",X"EE",X"EE",X"CC",X"88",X"00",X"77",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00", + X"33",X"33",X"33",X"33",X"33",X"33",X"00",X"33",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"EE",X"EE",X"EE",X"00",X"00",X"00",X"00",X"CC",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"FF", + X"33",X"33",X"00",X"33",X"33",X"33",X"33",X"33",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"EE",X"EE",X"EE",X"EE",X"EE",X"EE",X"EE",X"CC",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"33",X"11",X"00",X"33",X"33",X"33",X"33",X"33",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"EE",X"EE",X"00",X"00",X"00",X"EE",X"EE",X"EE",X"FF",X"FF",X"00",X"FF",X"FF",X"FF",X"FF",X"FF", + X"33",X"33",X"33",X"33",X"00",X"33",X"33",X"33",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"EE",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"00",X"FF",X"FF",X"FF", + X"33",X"33",X"00",X"11",X"33",X"33",X"33",X"33",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"EE",X"EE",X"EE",X"CC",X"88",X"EE",X"EE",X"EE",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"00",X"11",X"33",X"33",X"33",X"33",X"33",X"33",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"EE",X"EE",X"EE",X"EE",X"CC",X"EE",X"EE",X"00",X"FF",X"FF",X"FF",X"FF",X"99",X"FF",X"FF", + X"00",X"00",X"00",X"00",X"00",X"11",X"33",X"33",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"CC",X"EE",X"EE",X"00",X"00",X"00",X"00",X"00",X"BB",X"BB",X"BB", + X"33",X"33",X"33",X"33",X"33",X"11",X"00",X"33",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"EE",X"EE",X"EE",X"EE",X"EE",X"CC",X"00",X"EE",X"BB",X"88",X"FF",X"FF",X"FF",X"FF",X"00",X"FF", + X"33",X"33",X"33",X"33",X"33",X"33",X"00",X"11",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"EE",X"EE",X"EE",X"00",X"00",X"00",X"00",X"CC",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"FF", + X"33",X"33",X"33",X"33",X"33",X"33",X"33",X"11",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"EE",X"EE",X"EE",X"EE",X"EE",X"EE",X"EE",X"CC",X"FF",X"FF",X"99",X"FF",X"FF",X"FF",X"FF",X"FF", + X"00",X"11",X"33",X"33",X"33",X"33",X"33",X"33",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"CC",X"EE",X"EE",X"EE",X"EE",X"EE",X"EE",X"00",X"FF",X"FF",X"FF",X"99",X"FF",X"FF",X"FF", + X"33",X"11",X"00",X"33",X"33",X"33",X"33",X"33",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"EE",X"CC",X"00",X"00",X"00",X"00",X"EE",X"EE",X"FF",X"FF",X"00",X"FF",X"FF",X"FF",X"FF",X"FF", + X"F0",X"F0",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"F0",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + X"F0",X"F0",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"F0",X"F0",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"44",X"CF",X"C4",X"C6",X"CC",X"DD",X"FF",X"00",X"00",X"11",X"32",X"76",X"76",X"FF",X"FF", + X"00",X"00",X"00",X"00",X"C0",X"C0",X"00",X"00",X"00",X"00",X"06",X"22",X"6E",X"66",X"EE",X"EE", + X"FF",X"FF",X"DD",X"CC",X"C6",X"C4",X"CF",X"44",X"FF",X"FF",X"FF",X"76",X"76",X"32",X"11",X"00", + X"00",X"00",X"00",X"C0",X"C0",X"00",X"00",X"00",X"EE",X"EE",X"EE",X"66",X"6E",X"22",X"06",X"00", + X"00",X"01",X"02",X"19",X"13",X"19",X"BB",X"BB",X"00",X"00",X"00",X"23",X"77",X"75",X"FD",X"FD", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"30",X"B8",X"88",X"CC",X"CC",X"EE", + X"FF",X"FF",X"EE",X"EE",X"FF",X"F9",X"F8",X"77",X"FF",X"FF",X"FF",X"77",X"77",X"33",X"11",X"00", + X"60",X"60",X"00",X"88",X"0C",X"00",X"00",X"00",X"EE",X"FF",X"FF",X"02",X"08",X"02",X"8C",X"88", + X"00",X"00",X"0C",X"22",X"33",X"15",X"19",X"33",X"00",X"00",X"00",X"00",X"01",X"46",X"EE",X"F9", + X"00",X"00",X"00",X"00",X"00",X"00",X"60",X"60",X"00",X"00",X"C0",X"C0",X"00",X"88",X"CC",X"EE", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FC",X"FE",X"77",X"F9",X"FD",X"FF",X"77",X"77",X"33",X"11",X"00", + X"00",X"88",X"04",X"04",X"00",X"00",X"00",X"00",X"FF",X"FF",X"89",X"00",X"8C",X"C5",X"E6",X"CC", + X"00",X"30",X"30",X"CC",X"77",X"7F",X"33",X"33",X"00",X"00",X"00",X"01",X"00",X"02",X"04",X"CD", + X"00",X"00",X"00",X"00",X"C0",X"C0",X"00",X"CC",X"00",X"00",X"00",X"00",X"00",X"CC",X"FF",X"FF", + X"33",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"77",X"FF",X"F9",X"F8",X"77",X"77",X"33",X"11",X"00", + X"02",X"04",X"00",X"08",X"88",X"88",X"00",X"00",X"FF",X"CD",X"00",X"CE",X"FF",X"F1",X"FF",X"CC", + X"00",X"00",X"80",X"80",X"00",X"FF",X"FF",X"77",X"00",X"00",X"10",X"10",X"00",X"37",X"15",X"01", + X"00",X"00",X"00",X"00",X"00",X"8C",X"04",X"00",X"00",X"00",X"30",X"30",X"00",X"FF",X"FF",X"CD", + X"77",X"33",X"FF",X"FF",X"F7",X"FF",X"FF",X"77",X"04",X"05",X"FF",X"74",X"74",X"33",X"11",X"00", + X"04",X"04",X"EE",X"C4",X"C4",X"88",X"00",X"00",X"CC",X"89",X"FF",X"FE",X"FC",X"FF",X"FF",X"CC", + X"00",X"77",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"11",X"33",X"77",X"77",X"F9",X"F9", + X"00",X"00",X"00",X"88",X"08",X"08",X"00",X"04",X"00",X"CC",X"FF",X"F1",X"FF",X"CE",X"00",X"CD", + X"33",X"77",X"77",X"7F",X"66",X"88",X"30",X"30",X"FB",X"CD",X"04",X"02",X"00",X"01",X"01",X"00", + X"8A",X"88",X"00",X"C0",X"C0",X"00",X"00",X"00",X"FF",X"FF",X"EE",X"88",X"00",X"00",X"00",X"00", + X"00",X"77",X"FE",X"FC",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"11",X"33",X"77",X"77",X"FF",X"FD", + X"00",X"00",X"00",X"00",X"00",X"04",X"04",X"88",X"00",X"CC",X"E6",X"C6",X"89",X"04",X"02",X"99", + X"FF",X"77",X"33",X"33",X"37",X"22",X"0C",X"00",X"F9",X"F9",X"EF",X"44",X"02",X"00",X"00",X"00", + X"00",X"60",X"60",X"00",X"00",X"00",X"00",X"00",X"FF",X"EE",X"CC",X"88",X"00",X"00",X"C0",X"C0", + X"00",X"77",X"F9",X"F9",X"FB",X"EE",X"EE",X"FF",X"00",X"00",X"11",X"33",X"77",X"77",X"FF",X"FF", + X"00",X"00",X"00",X"00",X"08",X"88",X"88",X"60",X"00",X"88",X"8C",X"02",X"08",X"02",X"33",X"FF", + X"FF",X"BB",X"BB",X"19",X"13",X"08",X"02",X"01",X"FF",X"FD",X"FD",X"75",X"77",X"33",X"00",X"00", + X"60",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"EE",X"EE",X"CC",X"CC",X"B8",X"B8",X"00", + X"00",X"00",X"00",X"00",X"01",X"0F",X"0F",X"0F",X"00",X"00",X"00",X"00",X"00",X"00",X"07",X"0F", + X"00",X"00",X"07",X"0F",X"0F",X"0F",X"0F",X"0F",X"00",X"00",X"00",X"03",X"0F",X"0F",X"0F",X"0F", + X"0F",X"0F",X"01",X"00",X"00",X"00",X"00",X"00",X"07",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"0F",X"0F",X"0F",X"0F",X"07",X"00",X"00",X"00",X"0F",X"0F",X"0F",X"03",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"EE",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"03",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"01",X"00", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"01",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + X"FF",X"FF",X"CC",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"EE",X"CC",X"CC",X"CC", + X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"CC",X"FF",X"FF",X"FF",X"CC",X"CC",X"EE",X"FF",X"FF",X"FF",X"FF",X"FF", + X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"FF", + X"EE",X"CC",X"88",X"88",X"88",X"88",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"EE",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"EE",X"88",X"00",X"00", + X"00",X"88",X"88",X"88",X"88",X"CC",X"EE",X"EE",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"00",X"00",X"00",X"00",X"EE",X"FF",X"FF",X"FF",X"00",X"88",X"EE",X"FF",X"FF",X"FF",X"FF",X"FF", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"CC",X"88",X"88",X"88",X"88",X"00",X"00",X"00", + X"88",X"88",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"EE",X"EE",X"CC",X"CC", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"88",X"88",X"88",X"88",X"CC", + X"00",X"00",X"00",X"00",X"00",X"00",X"88",X"88",X"CC",X"CC",X"EE",X"EE",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"EE",X"CC",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"EE",X"88",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"EE",X"CC",X"00",X"00",X"00", + X"CC",X"EE",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"00",X"00",X"00",X"00",X"00",X"88",X"EE",X"FF",X"00",X"00",X"00",X"CC",X"EE",X"FF",X"FF",X"FF", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"EE",X"EE",X"EE",X"EE",X"EE",X"EE", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"EE",X"EE",X"EE",X"EE",X"EE",X"EE",X"FF",X"FF", + X"EE",X"CC",X"CC",X"88",X"88",X"88",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"88",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"EE",X"CC",X"88",X"88",X"00",X"00", + X"00",X"00",X"88",X"88",X"88",X"CC",X"CC",X"EE",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"88",X"00",X"00",X"88",X"88",X"CC",X"EE",X"FF",X"FF", + X"00",X"03",X"78",X"78",X"70",X"70",X"70",X"FF",X"00",X"00",X"03",X"03",X"00",X"00",X"00",X"33", + X"00",X"00",X"00",X"00",X"0C",X"0C",X"00",X"00",X"00",X"0E",X"F0",X"F0",X"F0",X"F0",X"F0",X"F8", + X"11",X"11",X"11",X"11",X"FF",X"FF",X"FF",X"00",X"33",X"33",X"33",X"33",X"33",X"11",X"00",X"00", + X"0C",X"0C",X"00",X"00",X"04",X"00",X"00",X"00",X"F8",X"F8",X"F8",X"FF",X"FF",X"EE",X"CC",X"00", + X"00",X"34",X"78",X"F0",X"F0",X"F0",X"F0",X"F1",X"00",X"00",X"00",X"01",X"12",X"1E",X"0C",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"0C",X"0C",X"00",X"80",X"C3",X"C3",X"E0",X"E0",X"F0",X"F8", + X"77",X"88",X"88",X"88",X"CC",X"FF",X"FF",X"33",X"00",X"11",X"11",X"11",X"11",X"00",X"00",X"00", + X"80",X"8A",X"CC",X"88",X"88",X"88",X"00",X"00",X"F8",X"FC",X"FF",X"77",X"FF",X"FF",X"EE",X"CC", + X"00",X"24",X"78",X"F0",X"F0",X"F0",X"F0",X"F1",X"00",X"00",X"00",X"01",X"12",X"30",X"34",X"1E", + X"00",X"00",X"00",X"00",X"08",X"08",X"08",X"82",X"00",X"04",X"0C",X"84",X"C0",X"E1",X"F0",X"F8", + X"F3",X"E6",X"CC",X"CC",X"EE",X"77",X"33",X"11",X"1C",X"00",X"00",X"11",X"00",X"00",X"00",X"00", + X"CC",X"CC",X"CC",X"CC",X"88",X"00",X"00",X"00",X"FC",X"FF",X"77",X"33",X"77",X"FF",X"EE",X"CC", + X"00",X"03",X"C3",X"F0",X"F0",X"F0",X"F0",X"F1",X"00",X"00",X"01",X"12",X"12",X"34",X"70",X"70", + X"00",X"00",X"00",X"00",X"02",X"00",X"CC",X"CC",X"00",X"00",X"00",X"03",X"C3",X"F0",X"F0",X"F9", + X"F3",X"E2",X"44",X"44",X"FF",X"77",X"11",X"00",X"34",X"0E",X"0C",X"00",X"00",X"00",X"00",X"00", + X"CC",X"EE",X"CC",X"CC",X"88",X"88",X"00",X"00",X"FF",X"FF",X"33",X"33",X"33",X"FF",X"FF",X"00", + X"00",X"00",X"00",X"33",X"33",X"22",X"E2",X"E2",X"00",X"00",X"00",X"06",X"06",X"06",X"70",X"78", + X"00",X"00",X"00",X"00",X"88",X"CC",X"CC",X"CC",X"00",X"00",X"00",X"FF",X"FF",X"11",X"11",X"11", + X"F3",X"F3",X"F0",X"F0",X"F0",X"09",X"09",X"00",X"78",X"78",X"78",X"78",X"70",X"01",X"01",X"00", + X"CC",X"CC",X"CC",X"88",X"00",X"00",X"00",X"00",X"FF",X"FF",X"F3",X"F3",X"F3",X"08",X"09",X"00", + X"00",X"00",X"11",X"77",X"FF",X"44",X"44",X"E2",X"00",X"00",X"00",X"00",X"00",X"00",X"0C",X"0E", + X"00",X"00",X"00",X"88",X"88",X"CC",X"CC",X"EE",X"00",X"00",X"FF",X"FF",X"33",X"33",X"33",X"FF", + X"F3",X"F1",X"F0",X"F0",X"F0",X"F0",X"4B",X"03",X"34",X"70",X"70",X"70",X"12",X"03",X"01",X"00", + X"CC",X"CC",X"CC",X"00",X"02",X"00",X"00",X"00",X"FF",X"F9",X"F0",X"F0",X"C3",X"03",X"00",X"00", + X"00",X"11",X"33",X"77",X"EE",X"CC",X"CC",X"66",X"00",X"00",X"00",X"00",X"00",X"11",X"00",X"00", + X"00",X"00",X"00",X"00",X"88",X"CC",X"CC",X"CC",X"00",X"CC",X"EE",X"FF",X"77",X"33",X"77",X"FF", + X"F3",X"F1",X"F0",X"F0",X"F0",X"F0",X"78",X"24",X"0C",X"1E",X"34",X"30",X"12",X"01",X"00",X"00", + X"CC",X"82",X"08",X"08",X"08",X"00",X"00",X"00",X"FC",X"F8",X"F0",X"E1",X"C0",X"84",X"0C",X"04", + X"00",X"33",X"FF",X"FF",X"CC",X"88",X"88",X"88",X"00",X"00",X"00",X"00",X"11",X"11",X"11",X"11", + X"00",X"00",X"00",X"88",X"88",X"88",X"CC",X"8A",X"00",X"CC",X"EE",X"FF",X"FF",X"77",X"FF",X"FC", + X"77",X"F1",X"F0",X"F0",X"F0",X"F0",X"78",X"07",X"00",X"00",X"0C",X"1E",X"12",X"10",X"00",X"00", + X"80",X"0C",X"0C",X"00",X"00",X"00",X"00",X"00",X"F8",X"F8",X"F0",X"E0",X"E0",X"C3",X"C3",X"80", + X"00",X"00",X"FF",X"FF",X"FF",X"11",X"11",X"11",X"00",X"00",X"00",X"11",X"33",X"33",X"33",X"33", + X"00",X"00",X"00",X"00",X"04",X"00",X"00",X"0C",X"00",X"00",X"CC",X"EE",X"FF",X"FF",X"F8",X"F8", + X"11",X"FF",X"70",X"70",X"70",X"78",X"78",X"03",X"33",X"33",X"00",X"00",X"00",X"03",X"03",X"00", + X"0C",X"00",X"00",X"0C",X"0C",X"00",X"00",X"00",X"F8",X"F8",X"F0",X"F0",X"F0",X"F0",X"F0",X"0E", + X"00",X"22",X"FF",X"FF",X"FF",X"FF",X"33",X"33",X"00",X"00",X"00",X"33",X"77",X"77",X"66",X"66", + X"00",X"00",X"00",X"00",X"08",X"08",X"00",X"00",X"00",X"01",X"CC",X"CC",X"E9",X"E1",X"F0",X"F8", + X"11",X"33",X"FC",X"30",X"10",X"12",X"07",X"06",X"77",X"33",X"33",X"11",X"00",X"00",X"00",X"00", + X"86",X"86",X"C0",X"C0",X"84",X"08",X"00",X"00",X"F8",X"F0",X"F0",X"F0",X"F0",X"E1",X"C2",X"00", + X"00",X"00",X"FF",X"FF",X"FE",X"FE",X"77",X"33",X"00",X"00",X"00",X"11",X"33",X"77",X"FF",X"EE", + X"00",X"00",X"00",X"00",X"00",X"00",X"0E",X"84",X"00",X"08",X"00",X"87",X"C2",X"E0",X"F0",X"F8", + X"11",X"33",X"FE",X"DC",X"88",X"00",X"01",X"01",X"EE",X"77",X"33",X"11",X"00",X"00",X"00",X"00", + X"C0",X"E0",X"C2",X"84",X"08",X"00",X"00",X"00",X"F8",X"F0",X"F0",X"F0",X"F0",X"69",X"0C",X"08", + X"00",X"02",X"44",X"FE",X"FC",X"FC",X"FE",X"77",X"00",X"00",X"00",X"33",X"33",X"77",X"FF",X"FF", + X"00",X"00",X"00",X"00",X"0C",X"0C",X"C0",X"C2",X"00",X"00",X"0C",X"0C",X"C0",X"F0",X"F0",X"F8", + X"11",X"11",X"11",X"EE",X"EE",X"00",X"00",X"00",X"EE",X"EE",X"77",X"77",X"11",X"00",X"00",X"00", + X"C2",X"C2",X"C2",X"84",X"80",X"00",X"00",X"00",X"F8",X"F0",X"F0",X"F0",X"34",X"07",X"0E",X"0C", + X"00",X"00",X"00",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"11",X"33",X"77",X"77",X"77", + X"00",X"00",X"00",X"0C",X"0C",X"0C",X"C0",X"C2",X"00",X"00",X"00",X"88",X"88",X"88",X"F8",X"F8", + X"FF",X"FF",X"F8",X"F8",X"F8",X"03",X"03",X"00",X"77",X"77",X"77",X"33",X"11",X"00",X"01",X"00", + X"C2",X"C2",X"C2",X"C2",X"C0",X"00",X"00",X"00",X"F8",X"F8",X"F0",X"F0",X"F0",X"03",X"03",X"00", + X"00",X"00",X"00",X"00",X"EE",X"EE",X"11",X"11",X"00",X"00",X"00",X"00",X"11",X"77",X"77",X"EE", + X"00",X"00",X"00",X"00",X"08",X"84",X"C2",X"E0",X"00",X"06",X"06",X"03",X"30",X"F0",X"F0",X"F0", + X"11",X"77",X"FE",X"FC",X"FC",X"FE",X"44",X"04",X"EE",X"FF",X"FF",X"77",X"33",X"33",X"00",X"00", + X"E0",X"E0",X"C0",X"0C",X"0C",X"00",X"00",X"00",X"F8",X"F8",X"F0",X"F0",X"C0",X"0C",X"0C",X"00", + X"00",X"01",X"01",X"00",X"88",X"DC",X"FE",X"33",X"00",X"00",X"00",X"00",X"00",X"11",X"33",X"77", + X"00",X"00",X"00",X"00",X"08",X"84",X"C2",X"E0",X"00",X"08",X"0C",X"69",X"F0",X"F0",X"F0",X"F0", + X"11",X"33",X"77",X"FE",X"FE",X"FF",X"FF",X"00",X"EE",X"EE",X"FF",X"77",X"33",X"11",X"00",X"00", + X"C0",X"84",X"0E",X"00",X"00",X"00",X"00",X"00",X"F8",X"F8",X"F0",X"E0",X"C2",X"87",X"00",X"08", + X"00",X"06",X"07",X"12",X"10",X"30",X"FC",X"33",X"00",X"00",X"00",X"00",X"00",X"11",X"33",X"33", + X"00",X"00",X"00",X"08",X"84",X"C0",X"C0",X"86",X"00",X"00",X"C2",X"E1",X"F0",X"F0",X"F0",X"F0", + X"11",X"33",X"33",X"FF",X"FF",X"FF",X"FF",X"22",X"77",X"66",X"66",X"77",X"77",X"33",X"00",X"00", + X"86",X"00",X"00",X"08",X"08",X"00",X"00",X"00",X"F8",X"F8",X"F0",X"E1",X"E9",X"CC",X"CC",X"01"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/loc_col_rom.vhd b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/loc_col_rom.vhd new file mode 100644 index 00000000..e5727bd6 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/loc_col_rom.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity loc_col_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of loc_col_rom is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"09",X"05",X"0C",X"00",X"01",X"08",X"06",X"00",X"06",X"0F",X"01",X"00",X"01",X"02",X"03", + X"00",X"04",X"05",X"07",X"00",X"07",X"08",X"09",X"00",X"0A",X"0B",X"0C",X"00",X"08",X"05",X"0F", + X"00",X"08",X"0F",X"01",X"00",X"05",X"04",X"0E",X"00",X"01",X"07",X"08",X"00",X"0B",X"0C",X"0D", + X"00",X"01",X"01",X"01",X"00",X"02",X"02",X"02",X"00",X"03",X"03",X"03",X"00",X"04",X"04",X"04", + X"00",X"05",X"05",X"05",X"00",X"06",X"06",X"06",X"00",X"07",X"07",X"07",X"00",X"08",X"08",X"08", + X"00",X"09",X"09",X"09",X"00",X"0A",X"0A",X"0A",X"00",X"0B",X"0B",X"0B",X"00",X"0C",X"0C",X"0C", + X"00",X"0D",X"0D",X"0D",X"00",X"0E",X"0E",X"0E",X"00",X"0F",X"0F",X"0F",X"00",X"00",X"00",X"00", + X"00",X"02",X"05",X"0C",X"00",X"09",X"05",X"0C",X"00",X"0B",X"05",X"0C",X"00",X"0E",X"05",X"0C", + X"00",X"09",X"05",X"0C",X"00",X"01",X"08",X"06",X"00",X"06",X"0F",X"01",X"00",X"01",X"02",X"03", + X"00",X"04",X"05",X"07",X"00",X"07",X"08",X"09",X"00",X"0A",X"0B",X"0C",X"00",X"08",X"05",X"0F", + X"00",X"08",X"00",X"01",X"00",X"05",X"04",X"0E",X"00",X"01",X"07",X"08",X"00",X"0B",X"0C",X"0D", + X"00",X"01",X"01",X"01",X"00",X"02",X"02",X"02",X"00",X"03",X"03",X"03",X"00",X"04",X"04",X"04", + X"00",X"05",X"05",X"05",X"00",X"06",X"06",X"06",X"00",X"07",X"07",X"07",X"00",X"08",X"08",X"08", + X"00",X"09",X"09",X"09",X"00",X"0A",X"0A",X"0A",X"00",X"0B",X"0B",X"0B",X"00",X"0C",X"0C",X"0C", + X"00",X"0D",X"0D",X"0D",X"00",X"0E",X"0E",X"0E",X"00",X"0F",X"0F",X"0F",X"00",X"03",X"06",X"0D", + X"00",X"04",X"05",X"0C",X"00",X"03",X"05",X"0C",X"00",X"0B",X"08",X"09",X"00",X"09",X"04",X"0D"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/loc_dot_rom.vhd b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/loc_dot_rom.vhd new file mode 100644 index 00000000..2a1b624f --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/loc_dot_rom.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity loc_dot_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of loc_dot_rom is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"02",X"02",X"02",X"02",X"01",X"02",X"03", + X"03",X"03",X"02",X"01",X"03",X"01",X"02",X"01",X"03",X"01",X"01",X"01",X"03",X"01",X"01",X"01", + X"01",X"01",X"01",X"01",X"01",X"01",X"02",X"01",X"01",X"02",X"01",X"01",X"01",X"01",X"01",X"01", + X"01",X"01",X"01",X"01",X"01",X"02",X"02",X"02",X"02",X"02",X"03",X"03",X"03",X"03",X"03",X"03", + X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"02",X"02",X"01",X"01",X"02",X"03",X"03", + X"02",X"02",X"03",X"03",X"01",X"01",X"01",X"03",X"01",X"01",X"01",X"02",X"02",X"01",X"01",X"02", + X"02",X"01",X"01",X"01",X"02",X"01",X"01",X"01",X"03",X"02",X"01",X"01",X"03",X"03",X"01",X"01", + X"01",X"01",X"01",X"02",X"01",X"01",X"01",X"02",X"01",X"01",X"02",X"03",X"01",X"01",X"03",X"03", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"08",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"08",X"00",X"00",X"00",X"08",X"00", + X"00",X"00",X"08",X"00",X"00",X"00",X"08",X"00",X"00",X"00",X"08",X"00",X"00",X"00",X"08",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/loc_pal_rom.vhd b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/loc_pal_rom.vhd new file mode 100644 index 00000000..62d63c29 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/loc_pal_rom.vhd @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity loc_pal_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of loc_pal_rom is + type rom is array(0 to 31) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"07",X"A0",X"97",X"67",X"3F",X"7D",X"38",X"F0",X"A8",X"C0",X"18",X"5E",X"A8",X"1B",X"FF", + X"00",X"FF",X"B7",X"00",X"00",X"FF",X"B7",X"00",X"00",X"FF",X"B7",X"00",X"00",X"FF",X"B7",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/loc_prg_rom.vhd b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/loc_prg_rom.vhd new file mode 100644 index 00000000..48d5172a --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/loc_prg_rom.vhd @@ -0,0 +1,1302 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity loc_prg_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(14 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of loc_prg_rom is + type rom is array(0 to 20479) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"3E",X"00",X"32",X"81",X"A1",X"C3",X"A5",X"02",X"E1",X"87",X"E7",X"5E",X"23",X"56",X"EB",X"E9", + X"77",X"23",X"10",X"FC",X"0D",X"20",X"F9",X"C9",X"35",X"34",X"C8",X"35",X"C9",X"FF",X"FF",X"FF", + X"85",X"6F",X"D0",X"24",X"C9",X"FF",X"FF",X"FF",X"19",X"7C",X"E6",X"03",X"F6",X"80",X"67",X"C9", + X"EB",X"4E",X"23",X"46",X"EB",X"09",X"C9",X"FF",X"3A",X"C0",X"98",X"26",X"98",X"6F",X"7E",X"B7", + X"C0",X"72",X"2C",X"73",X"2C",X"7D",X"20",X"02",X"3E",X"C2",X"32",X"C0",X"98",X"C9",X"FF",X"FF", + X"FF",X"FF",X"FD",X"E1",X"DD",X"E1",X"E1",X"D1",X"C1",X"F1",X"D9",X"08",X"E1",X"D1",X"C1",X"3E", + X"01",X"32",X"81",X"A1",X"F1",X"C9",X"F5",X"AF",X"32",X"81",X"A1",X"C5",X"D5",X"E5",X"08",X"D9", + X"F5",X"C5",X"D5",X"E5",X"DD",X"E5",X"FD",X"E5",X"CD",X"58",X"01",X"CD",X"2E",X"01",X"21",X"1E", + X"98",X"11",X"1F",X"98",X"ED",X"A8",X"3A",X"00",X"A1",X"2F",X"12",X"1D",X"2D",X"ED",X"A8",X"3A", + X"80",X"A0",X"2F",X"12",X"1D",X"2D",X"ED",X"A8",X"ED",X"A8",X"ED",X"A8",X"3A",X"00",X"A0",X"2F", + X"12",X"32",X"80",X"A0",X"21",X"07",X"98",X"35",X"CD",X"C0",X"1F",X"CD",X"BE",X"00",X"21",X"52", + X"00",X"E5",X"3A",X"00",X"98",X"CF",X"18",X"02",X"4F",X"09",X"04",X"21",X"92",X"15",X"21",X"10", + X"98",X"7E",X"B7",X"28",X"05",X"35",X"07",X"32",X"84",X"A1",X"2E",X"14",X"7E",X"B7",X"28",X"05", + X"35",X"07",X"32",X"86",X"A1",X"21",X"18",X"98",X"7E",X"2C",X"B6",X"2C",X"2F",X"A6",X"E6",X"C4", + X"C8",X"47",X"E6",X"84",X"28",X"30",X"B8",X"28",X"04",X"01",X"16",X"01",X"C5",X"07",X"30",X"08", + X"3E",X"82",X"32",X"10",X"98",X"CD",X"8C",X"20",X"3A",X"15",X"98",X"47",X"21",X"11",X"98",X"7E", + X"C6",X"10",X"B8",X"77",X"D8",X"36",X"00",X"78",X"E6",X"0F",X"21",X"12",X"98",X"86",X"FE",X"63", + X"38",X"02",X"3E",X"63",X"77",X"C9",X"CD",X"8C",X"20",X"3E",X"86",X"32",X"14",X"98",X"3A",X"16", + X"98",X"47",X"21",X"13",X"98",X"7E",X"C6",X"10",X"B8",X"77",X"D8",X"C3",X"05",X"01",X"21",X"40", + X"98",X"11",X"14",X"80",X"AF",X"CD",X"3E",X"01",X"21",X"42",X"98",X"11",X"14",X"88",X"01",X"0C", + X"00",X"ED",X"A0",X"ED",X"A0",X"2C",X"2C",X"B9",X"38",X"F7",X"0E",X"04",X"1E",X"00",X"ED",X"A0", + X"ED",X"A0",X"2C",X"2C",X"B9",X"38",X"F7",X"C9",X"AF",X"21",X"20",X"88",X"01",X"01",X"04",X"D7", + X"21",X"60",X"98",X"11",X"34",X"80",X"CD",X"72",X"01",X"11",X"04",X"A0",X"CD",X"72",X"01",X"11", + X"34",X"88",X"ED",X"A0",X"ED",X"A0",X"ED",X"A0",X"ED",X"A0",X"ED",X"A0",X"ED",X"A0",X"ED",X"A0", + X"ED",X"A0",X"ED",X"A0",X"ED",X"A0",X"ED",X"A0",X"ED",X"A0",X"11",X"04",X"00",X"19",X"C9",X"21", + X"0E",X"99",X"34",X"5E",X"16",X"4E",X"1A",X"2C",X"86",X"77",X"C9",X"26",X"98",X"3A",X"C1",X"98", + X"6F",X"7E",X"87",X"20",X"0F",X"26",X"9C",X"3A",X"21",X"9C",X"6F",X"7E",X"87",X"20",X"22",X"CD", + X"C0",X"03",X"18",X"E7",X"4F",X"06",X"00",X"70",X"23",X"5E",X"2C",X"7D",X"20",X"02",X"3E",X"C2", + X"32",X"C1",X"98",X"7B",X"21",X"EF",X"01",X"09",X"5E",X"23",X"56",X"21",X"9B",X"01",X"E5",X"EB", + X"E9",X"4F",X"06",X"00",X"70",X"23",X"5E",X"2C",X"7D",X"FE",X"20",X"38",X"01",X"AF",X"32",X"21", + X"9C",X"7B",X"21",X"EF",X"01",X"09",X"5E",X"23",X"56",X"21",X"9B",X"01",X"E5",X"EB",X"E9",X"FF", + X"03",X"2C",X"03",X"84",X"04",X"DB",X"04",X"A6",X"08",X"E9",X"08",X"03",X"09",X"1E",X"09",X"00", + X"04",X"3A",X"20",X"9C",X"6F",X"26",X"9C",X"7E",X"B7",X"C0",X"72",X"2C",X"73",X"2C",X"7D",X"FE", + X"20",X"38",X"01",X"AF",X"32",X"20",X"9C",X"C9",X"3A",X"80",X"A1",X"47",X"E6",X"0F",X"20",X"01", + X"47",X"4F",X"A8",X"0F",X"0F",X"0F",X"0F",X"21",X"21",X"09",X"E7",X"46",X"79",X"21",X"21",X"09", + X"E7",X"4E",X"ED",X"43",X"15",X"98",X"3A",X"00",X"A1",X"EE",X"33",X"47",X"0F",X"0F",X"0F",X"0F", + X"E6",X"03",X"C6",X"03",X"FE",X"06",X"20",X"02",X"3E",X"FF",X"32",X"0C",X"98",X"78",X"21",X"00", + X"00",X"54",X"5C",X"44",X"4C",X"0F",X"CB",X"14",X"0F",X"CB",X"11",X"0F",X"CB",X"12",X"0F",X"CB", + X"10",X"3A",X"80",X"A1",X"E6",X"0F",X"20",X"01",X"2C",X"ED",X"53",X"BC",X"98",X"22",X"BE",X"98", + X"21",X"0B",X"98",X"70",X"2E",X"0F",X"71",X"3E",X"0A",X"06",X"00",X"21",X"31",X"09",X"11",X"00", + X"9F",X"0E",X"03",X"ED",X"B0",X"EB",X"01",X"3E",X"09",X"71",X"2C",X"10",X"FC",X"EB",X"3D",X"20", + X"F0",X"21",X"31",X"09",X"11",X"C6",X"99",X"0E",X"03",X"ED",X"B0",X"3E",X"01",X"32",X"0D",X"98", + X"21",X"00",X"98",X"34",X"C9",X"3A",X"00",X"50",X"FE",X"55",X"CA",X"01",X"50",X"21",X"00",X"98", + X"11",X"01",X"98",X"01",X"FF",X"07",X"36",X"00",X"ED",X"B0",X"32",X"80",X"A0",X"31",X"00",X"A0", + X"21",X"C2",X"C2",X"22",X"C0",X"98",X"21",X"D0",X"99",X"01",X"01",X"30",X"3E",X"FF",X"D7",X"21", + X"D0",X"D0",X"22",X"CD",X"99",X"32",X"80",X"A0",X"AF",X"32",X"84",X"A1",X"32",X"86",X"A1",X"32", + X"87",X"A1",X"3C",X"32",X"83",X"A1",X"CD",X"E5",X"1F",X"3E",X"0B",X"21",X"00",X"80",X"01",X"04", + X"00",X"D7",X"32",X"80",X"A0",X"01",X"04",X"00",X"D7",X"3E",X"80",X"32",X"80",X"A0",X"01",X"04", + X"00",X"D7",X"3E",X"80",X"32",X"80",X"A0",X"01",X"04",X"00",X"D7",X"CD",X"D1",X"1C",X"32",X"80", + X"A0",X"CD",X"22",X"03",X"CD",X"EB",X"1F",X"CD",X"22",X"03",X"3E",X"01",X"32",X"81",X"A1",X"C3", + X"9B",X"01",X"0B",X"32",X"80",X"A0",X"78",X"B1",X"20",X"F8",X"37",X"C9",X"47",X"3A",X"08",X"98", + X"B7",X"C8",X"3A",X"09",X"98",X"B7",X"20",X"63",X"11",X"00",X"02",X"CD",X"01",X"02",X"11",X"C0", + X"99",X"78",X"87",X"20",X"06",X"21",X"C9",X"99",X"C3",X"50",X"03",X"80",X"21",X"48",X"04",X"E7", + X"B7",X"06",X"03",X"1A",X"8E",X"27",X"12",X"1C",X"23",X"10",X"F8",X"47",X"30",X"04",X"AF",X"32", + X"3F",X"99",X"3A",X"01",X"99",X"B8",X"DC",X"A7",X"03",X"3A",X"3F",X"99",X"B7",X"20",X"1A",X"06", + X"03",X"21",X"C8",X"99",X"1D",X"1A",X"BE",X"D8",X"20",X"04",X"2D",X"10",X"F7",X"C9",X"3E",X"01", + X"32",X"3F",X"99",X"3E",X"04",X"90",X"EB",X"E7",X"EB",X"EB",X"2D",X"11",X"C8",X"99",X"ED",X"A8", + X"ED",X"A8",X"ED",X"A8",X"11",X"02",X"02",X"CD",X"01",X"02",X"C9",X"11",X"01",X"02",X"CD",X"01", + X"02",X"11",X"C3",X"99",X"C3",X"41",X"03",X"D5",X"C6",X"07",X"27",X"30",X"02",X"3E",X"99",X"21", + X"01",X"99",X"77",X"2D",X"34",X"11",X"00",X"05",X"CD",X"01",X"02",X"CD",X"73",X"20",X"D1",X"C9", + X"CD",X"59",X"2A",X"CD",X"87",X"2C",X"CD",X"2F",X"2E",X"CD",X"33",X"2B",X"21",X"19",X"98",X"CB", + X"46",X"C8",X"C9",X"0E",X"30",X"1A",X"91",X"77",X"13",X"3E",X"20",X"E7",X"10",X"F7",X"C9",X"81", + X"8C",X"9A",X"81",X"8C",X"8E",X"8E",X"8E",X"8E",X"90",X"90",X"90",X"90",X"90",X"90",X"91",X"91", + X"91",X"91",X"91",X"91",X"92",X"92",X"92",X"92",X"92",X"92",X"92",X"92",X"93",X"93",X"93",X"C9", + X"3C",X"28",X"06",X"21",X"DF",X"03",X"CD",X"C4",X"11",X"01",X"10",X"0B",X"79",X"C5",X"CD",X"DB", + X"04",X"C1",X"0C",X"10",X"F7",X"21",X"98",X"85",X"DD",X"21",X"02",X"9F",X"06",X"0A",X"C5",X"11", + X"20",X"00",X"CD",X"A2",X"04",X"11",X"60",X"00",X"19",X"DD",X"E5",X"D1",X"13",X"13",X"13",X"13", + X"06",X"03",X"CD",X"D3",X"03",X"11",X"0F",X"00",X"DD",X"19",X"11",X"7E",X"FE",X"19",X"C1",X"10", + X"DD",X"11",X"0F",X"03",X"CD",X"01",X"02",X"C9",X"00",X"00",X"00",X"10",X"00",X"00",X"20",X"00", + X"00",X"30",X"00",X"00",X"40",X"00",X"00",X"50",X"00",X"00",X"60",X"00",X"00",X"70",X"00",X"00", + X"80",X"00",X"00",X"90",X"00",X"00",X"00",X"01",X"00",X"10",X"01",X"00",X"20",X"01",X"00",X"30", + X"01",X"00",X"40",X"01",X"00",X"50",X"01",X"00",X"00",X"02",X"00",X"00",X"04",X"00",X"00",X"10", + X"00",X"00",X"50",X"00",X"DD",X"21",X"C2",X"99",X"21",X"85",X"80",X"A7",X"28",X"11",X"DD",X"21", + X"C5",X"99",X"21",X"C5",X"82",X"3D",X"28",X"07",X"DD",X"21",X"C8",X"99",X"21",X"A5",X"81",X"11", + X"20",X"00",X"06",X"03",X"DD",X"7E",X"00",X"4F",X"0F",X"0F",X"0F",X"0F",X"E6",X"0F",X"20",X"1F", + X"36",X"10",X"19",X"79",X"E6",X"0F",X"20",X"1C",X"36",X"10",X"19",X"DD",X"2B",X"10",X"E5",X"AF", + X"ED",X"52",X"77",X"19",X"C9",X"DD",X"7E",X"00",X"4F",X"0F",X"0F",X"0F",X"0F",X"E6",X"0F",X"77", + X"19",X"79",X"E6",X"0F",X"77",X"19",X"DD",X"2B",X"10",X"EB",X"C9",X"47",X"E6",X"3F",X"FE",X"03", + X"20",X"0A",X"78",X"E6",X"C0",X"F6",X"31",X"C5",X"CD",X"ED",X"04",X"C1",X"78",X"87",X"F5",X"21", + X"2B",X"05",X"E6",X"7F",X"85",X"6F",X"30",X"01",X"24",X"F1",X"5E",X"23",X"56",X"EB",X"5E",X"23", + X"56",X"23",X"EB",X"01",X"20",X"00",X"38",X"15",X"1A",X"FE",X"2E",X"28",X"0B",X"FE",X"2F",X"C8", + X"D6",X"30",X"77",X"13",X"09",X"18",X"F1",X"37",X"EB",X"23",X"C3",X"FE",X"04",X"1A",X"FE",X"2E", + X"28",X"F5",X"FE",X"2F",X"C8",X"36",X"10",X"13",X"09",X"18",X"F2",X"9B",X"05",X"A2",X"05",X"A9", + X"05",X"B0",X"05",X"DC",X"05",X"F3",X"05",X"09",X"06",X"12",X"06",X"2A",X"06",X"3C",X"06",X"51", + X"06",X"5B",X"06",X"68",X"06",X"75",X"06",X"81",X"06",X"92",X"06",X"A3",X"06",X"B9",X"06",X"BF", + X"06",X"C5",X"06",X"CB",X"06",X"D1",X"06",X"D7",X"06",X"DD",X"06",X"E3",X"06",X"E9",X"06",X"EF", + X"06",X"F6",X"06",X"00",X"07",X"07",X"07",X"07",X"07",X"37",X"07",X"37",X"07",X"66",X"07",X"73", + X"07",X"81",X"07",X"90",X"07",X"98",X"07",X"A8",X"07",X"B4",X"07",X"CC",X"07",X"E6",X"07",X"F7", + X"07",X"FD",X"07",X"0F",X"08",X"19",X"08",X"26",X"08",X"33",X"08",X"43",X"08",X"51",X"08",X"66", + X"08",X"A3",X"08",X"A3",X"08",X"A3",X"08",X"A3",X"08",X"A3",X"08",X"C6",X"81",X"48",X"49",X"47", + X"48",X"2F",X"A6",X"80",X"31",X"5B",X"55",X"50",X"2F",X"E6",X"82",X"32",X"5B",X"55",X"50",X"2F", + X"D9",X"84",X"3F",X"3F",X"40",X"40",X"4C",X"4F",X"43",X"4F",X"5B",X"4D",X"4F",X"54",X"49",X"4F", + X"4E",X"40",X"40",X"3F",X"3F",X"2F",X"D9",X"84",X"5B",X"40",X"47",X"55",X"54",X"54",X"41",X"4E", + X"47",X"40",X"47",X"4F",X"54",X"54",X"4F",X"4E",X"47",X"40",X"5B",X"2F",X"B2",X"84",X"50",X"4C", + X"45",X"41",X"53",X"45",X"40",X"44",X"45",X"50",X"4F",X"53",X"49",X"54",X"40",X"43",X"4F",X"49", + X"4E",X"53",X"2F",X"CC",X"84",X"48",X"41",X"56",X"45",X"40",X"41",X"40",X"4E",X"49",X"43",X"45", + X"40",X"54",X"52",X"49",X"50",X"40",X"3C",X"3C",X"2F",X"95",X"85",X"50",X"4C",X"45",X"41",X"53", + X"45",X"2F",X"A4",X"84",X"50",X"55",X"53",X"48",X"40",X"53",X"54",X"41",X"52",X"54",X"40",X"42", + X"55",X"54",X"54",X"4F",X"4E",X"40",X"46",X"4F",X"52",X"2F",X"02",X"85",X"4F",X"4E",X"45",X"40", + X"50",X"4C",X"41",X"59",X"45",X"52",X"40",X"4F",X"4E",X"4C",X"59",X"2F",X"C2",X"84",X"4F",X"4E", + X"45",X"40",X"4F",X"52",X"40",X"54",X"57",X"4F",X"40",X"50",X"4C",X"41",X"59",X"45",X"52",X"53", + X"2F",X"84",X"82",X"43",X"52",X"45",X"44",X"49",X"54",X"40",X"2F",X"75",X"85",X"50",X"4C",X"41", + X"59",X"45",X"52",X"40",X"4F",X"4E",X"45",X"2F",X"75",X"85",X"50",X"4C",X"41",X"59",X"45",X"52", + X"40",X"54",X"57",X"4F",X"2F",X"71",X"85",X"47",X"41",X"4D",X"45",X"40",X"4F",X"56",X"45",X"52", + X"2F",X"22",X"85",X"3A",X"40",X"43",X"45",X"4E",X"54",X"55",X"52",X"49",X"40",X"31",X"39",X"38", + X"32",X"2F",X"20",X"85",X"3A",X"40",X"43",X"45",X"4E",X"54",X"55",X"52",X"49",X"40",X"31",X"39", + X"38",X"32",X"2F",X"DA",X"84",X"5B",X"40",X"40",X"53",X"43",X"4F",X"52",X"45",X"40",X"52",X"41", + X"4E",X"4B",X"49",X"4E",X"47",X"40",X"40",X"5B",X"2F",X"B8",X"84",X"31",X"53",X"54",X"2F",X"B6", + X"84",X"32",X"4E",X"44",X"2F",X"B4",X"84",X"33",X"52",X"44",X"2F",X"B2",X"84",X"34",X"54",X"48", + X"2F",X"B0",X"84",X"35",X"54",X"48",X"2F",X"AE",X"84",X"36",X"54",X"48",X"2F",X"AC",X"84",X"37", + X"54",X"48",X"2F",X"AA",X"84",X"38",X"54",X"48",X"2F",X"A8",X"84",X"39",X"54",X"48",X"2F",X"86", + X"84",X"31",X"30",X"54",X"48",X"2F",X"A7",X"85",X"53",X"54",X"41",X"54",X"49",X"4F",X"4E",X"2F", + X"A8",X"84",X"31",X"35",X"30",X"30",X"2F",X"D7",X"84",X"3F",X"3F",X"40",X"40",X"4C",X"4F",X"43", + X"4F",X"5B",X"4D",X"4F",X"54",X"49",X"4F",X"4E",X"40",X"40",X"3F",X"3F",X"2F",X"78",X"85",X"12", + X"10",X"16",X"14",X"1A",X"18",X"1E",X"1C",X"22",X"20",X"2F",X"77",X"85",X"13",X"11",X"17",X"15", + X"1B",X"19",X"1F",X"1D",X"23",X"21",X"2F",X"00",X"85",X"4C",X"49",X"43",X"45",X"4E",X"53",X"45", + X"44",X"40",X"42",X"59",X"40",X"4B",X"4F",X"4E",X"41",X"4D",X"49",X"2F",X"B6",X"85",X"12",X"10", + X"26",X"24",X"1A",X"2A",X"28",X"1C",X"22",X"20",X"2F",X"B5",X"85",X"13",X"11",X"27",X"25",X"1B", + X"2B",X"29",X"1D",X"23",X"21",X"2F",X"67",X"85",X"42",X"4F",X"4E",X"55",X"53",X"40",X"4C",X"49", + X"4E",X"45",X"2F",X"67",X"85",X"43",X"52",X"41",X"5A",X"59",X"40",X"54",X"52",X"41",X"49",X"4E", + X"2F",X"47",X"85",X"4C",X"4F",X"4F",X"50",X"40",X"53",X"57",X"45",X"45",X"50",X"45",X"52",X"2F", + X"74",X"85",X"42",X"4F",X"4E",X"55",X"53",X"2F",X"47",X"85",X"42",X"4F",X"4E",X"55",X"53",X"40", + X"53",X"54",X"41",X"54",X"49",X"4F",X"4E",X"2F",X"84",X"82",X"46",X"52",X"45",X"45",X"40",X"50", + X"4C",X"41",X"59",X"2F",X"D9",X"84",X"41",X"44",X"4A",X"55",X"53",X"54",X"40",X"52",X"41",X"49", + X"4C",X"40",X"57",X"41",X"59",X"40",X"4C",X"49",X"4E",X"45",X"53",X"2F",X"B7",X"84",X"53",X"4F", + X"40",X"41",X"53",X"40",X"54",X"4F",X"40",X"4C",X"45",X"54",X"40",X"59",X"4F",X"55",X"52",X"40", + X"54",X"52",X"41",X"49",X"4E",X"2F",X"B5",X"84",X"41",X"44",X"56",X"41",X"4E",X"43",X"45",X"40", + X"53",X"41",X"46",X"45",X"4C",X"59",X"2F",X"CF",X"85",X"41",X"4E",X"44",X"2F",X"11",X"85",X"40", + X"50",X"45",X"52",X"46",X"45",X"43",X"54",X"40",X"43",X"4C",X"45",X"41",X"52",X"40",X"2F",X"91", + X"85",X"40",X"43",X"4C",X"45",X"41",X"52",X"40",X"2F",X"6E",X"85",X"40",X"35",X"30",X"30",X"30", + X"40",X"50",X"54",X"53",X"40",X"2F",X"6E",X"85",X"40",X"31",X"30",X"30",X"30",X"40",X"50",X"54", + X"53",X"40",X"2F",X"31",X"8D",X"C3",X"C3",X"C3",X"C3",X"C3",X"C3",X"C3",X"C3",X"C3",X"C3",X"C3", + X"C3",X"C3",X"2F",X"8E",X"8D",X"C3",X"C3",X"C3",X"C3",X"C3",X"C3",X"C3",X"C3",X"2F",X"00",X"84", + X"2F",X"00",X"85",X"4C",X"49",X"43",X"45",X"4E",X"53",X"45",X"44",X"40",X"42",X"59",X"40",X"4B", + X"4F",X"4E",X"41",X"4D",X"49",X"2F",X"44",X"84",X"4D",X"4F",X"56",X"45",X"40",X"54",X"48",X"45", + X"40",X"4A",X"4F",X"59",X"53",X"54",X"49",X"43",X"4B",X"40",X"54",X"4F",X"40",X"53",X"45",X"4C", + X"45",X"43",X"54",X"2E",X"42",X"84",X"49",X"4E",X"49",X"54",X"49",X"41",X"4C",X"40",X"41",X"4E", + X"44",X"40",X"50",X"52",X"45",X"53",X"53",X"40",X"46",X"49",X"52",X"45",X"42",X"55",X"54",X"54", + X"4F",X"4E",X"2F",X"00",X"80",X"2F",X"3A",X"BE",X"98",X"B7",X"28",X"05",X"3E",X"26",X"C3",X"DB", + X"04",X"3E",X"0A",X"CD",X"DB",X"04",X"3A",X"12",X"98",X"FE",X"63",X"38",X"02",X"3E",X"63",X"CD", + X"CD",X"08",X"21",X"64",X"83",X"11",X"20",X"00",X"06",X"01",X"C3",X"A7",X"04",X"4F",X"0F",X"0F", + X"0F",X"0F",X"E6",X"0F",X"47",X"04",X"AF",X"81",X"27",X"0E",X"00",X"C6",X"06",X"27",X"30",X"01", + X"0C",X"10",X"F8",X"D6",X"06",X"27",X"D0",X"0D",X"C9",X"3A",X"00",X"99",X"01",X"C4",X"06",X"11", + X"E0",X"FF",X"21",X"04",X"81",X"B8",X"38",X"05",X"71",X"19",X"10",X"F9",X"C9",X"36",X"10",X"19", + X"10",X"F3",X"C9",X"3A",X"02",X"99",X"3C",X"01",X"C5",X"10",X"11",X"20",X"00",X"21",X"A4",X"81", + X"B8",X"38",X"05",X"71",X"19",X"10",X"F9",X"C9",X"36",X"10",X"19",X"10",X"F3",X"C9",X"C3",X"CD", + X"30",X"00",X"11",X"22",X"04",X"31",X"06",X"15",X"02",X"33",X"07",X"21",X"03",X"24",X"05",X"13", + X"01",X"00",X"00",X"01",X"30",X"85",X"00",X"90",X"76",X"00",X"30",X"70",X"00",X"80",X"62",X"00", + X"00",X"54",X"00",X"90",X"39",X"00",X"00",X"36",X"00",X"50",X"28",X"00",X"10",X"24",X"00",X"3A", + X"BE",X"98",X"B7",X"28",X"08",X"21",X"C0",X"21",X"E5",X"11",X"26",X"03",X"FF",X"21",X"7B",X"09", + X"E5",X"3A",X"01",X"98",X"CF",X"AF",X"15",X"8A",X"09",X"FB",X"09",X"29",X"0C",X"38",X"0D",X"43", + X"0E",X"41",X"10",X"75",X"22",X"49",X"10",X"72",X"10",X"A6",X"10",X"3A",X"12",X"98",X"B7",X"C8", + X"AF",X"21",X"00",X"98",X"34",X"2C",X"77",X"2C",X"77",X"C9",X"3A",X"03",X"98",X"CF",X"94",X"09", + X"34",X"0B",X"9D",X"10",X"3A",X"07",X"98",X"0F",X"D8",X"CD",X"91",X"11",X"3A",X"2C",X"98",X"FE", + X"20",X"D8",X"AF",X"32",X"2C",X"98",X"21",X"DB",X"09",X"CD",X"C4",X"11",X"21",X"40",X"98",X"01", + X"01",X"50",X"D7",X"3C",X"CD",X"61",X"11",X"1E",X"2A",X"FF",X"1E",X"04",X"FF",X"1C",X"FF",X"1E", + X"1D",X"FF",X"1C",X"FF",X"1C",X"FF",X"1C",X"FF",X"1E",X"4E",X"FF",X"3E",X"04",X"32",X"3E",X"98", + X"CD",X"6F",X"11",X"21",X"02",X"98",X"36",X"00",X"2C",X"34",X"C9",X"81",X"8C",X"9A",X"81",X"8C", + X"8C",X"8C",X"8C",X"95",X"95",X"95",X"95",X"90",X"90",X"91",X"91",X"91",X"91",X"91",X"91",X"91", + X"8E",X"8E",X"8E",X"8E",X"90",X"90",X"90",X"90",X"90",X"90",X"90",X"3A",X"03",X"98",X"CF",X"15", + X"0A",X"A7",X"0A",X"D3",X"0A",X"11",X"0B",X"47",X"0B",X"50",X"0B",X"79",X"0B",X"A1",X"0B",X"0F", + X"0C",X"18",X"0C",X"9D",X"10",X"3A",X"07",X"98",X"0F",X"D8",X"CD",X"91",X"11",X"3A",X"2C",X"98", + X"FE",X"20",X"D8",X"AF",X"32",X"2C",X"98",X"CD",X"61",X"11",X"CD",X"6F",X"11",X"21",X"83",X"0A", + X"CD",X"C4",X"11",X"11",X"03",X"03",X"FF",X"1E",X"0E",X"FF",X"21",X"A3",X"0A",X"11",X"40",X"98", + X"01",X"04",X"00",X"ED",X"B0",X"CD",X"7D",X"11",X"11",X"6E",X"85",X"21",X"1B",X"42",X"CD",X"31", + X"11",X"21",X"BB",X"44",X"CD",X"31",X"11",X"21",X"BB",X"43",X"3E",X"02",X"CD",X"1F",X"11",X"11", + X"6A",X"85",X"21",X"BB",X"44",X"CD",X"31",X"11",X"21",X"BB",X"44",X"CD",X"31",X"11",X"21",X"DB", + X"43",X"3E",X"02",X"CD",X"1F",X"11",X"3E",X"80",X"32",X"21",X"98",X"21",X"02",X"98",X"36",X"02", + X"2C",X"34",X"C9",X"81",X"8C",X"9A",X"81",X"8C",X"8C",X"8C",X"8C",X"8C",X"8C",X"8C",X"9A",X"8C", + X"9A",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"9A",X"9A",X"9A",X"9A",X"93", + X"93",X"93",X"93",X"C1",X"98",X"58",X"01",X"3A",X"07",X"98",X"0F",X"D0",X"21",X"42",X"98",X"34", + X"7E",X"FE",X"70",X"21",X"00",X"FF",X"28",X"06",X"FE",X"90",X"C0",X"21",X"80",X"FF",X"11",X"6A", + X"86",X"19",X"EB",X"21",X"DB",X"3C",X"CD",X"31",X"11",X"21",X"02",X"98",X"35",X"C0",X"36",X"40", + X"2C",X"34",X"C9",X"3A",X"07",X"98",X"0F",X"D0",X"3A",X"02",X"98",X"DD",X"21",X"40",X"98",X"01", + X"90",X"88",X"FD",X"21",X"02",X"98",X"21",X"FD",X"10",X"22",X"1B",X"99",X"CD",X"AB",X"10",X"FD", + X"35",X"00",X"C0",X"FD",X"34",X"01",X"11",X"6E",X"86",X"21",X"BB",X"42",X"3E",X"02",X"CD",X"1F", + X"11",X"11",X"6A",X"86",X"21",X"DB",X"42",X"3E",X"02",X"CD",X"1F",X"11",X"11",X"1B",X"03",X"FF", + X"C9",X"3A",X"02",X"98",X"C6",X"1F",X"E6",X"20",X"20",X"14",X"3E",X"20",X"21",X"48",X"04",X"E7", + X"E5",X"DD",X"E1",X"21",X"F4",X"85",X"CD",X"9F",X"04",X"CD",X"01",X"0C",X"18",X"06",X"21",X"F4", + X"85",X"CD",X"3C",X"0B",X"21",X"02",X"98",X"35",X"C0",X"2C",X"34",X"C9",X"11",X"20",X"00",X"01", + X"10",X"0A",X"71",X"19",X"10",X"FC",X"C9",X"11",X"9B",X"03",X"FF",X"21",X"03",X"98",X"34",X"C9", + X"3A",X"07",X"98",X"0F",X"D0",X"3A",X"02",X"98",X"DD",X"21",X"40",X"98",X"01",X"90",X"88",X"FD", + X"21",X"02",X"98",X"21",X"FD",X"10",X"22",X"1B",X"99",X"CD",X"AB",X"10",X"FD",X"35",X"00",X"FD", + X"7E",X"00",X"E6",X"3F",X"C0",X"FD",X"34",X"01",X"C9",X"3A",X"07",X"98",X"0F",X"D0",X"21",X"42", + X"98",X"35",X"7E",X"FE",X"70",X"28",X"11",X"FE",X"6C",X"C0",X"3E",X"03",X"32",X"17",X"98",X"11", + X"21",X"03",X"FF",X"21",X"03",X"98",X"34",X"C9",X"11",X"EE",X"85",X"21",X"DB",X"3C",X"C3",X"31", + X"11",X"3A",X"02",X"98",X"C6",X"1F",X"E6",X"20",X"20",X"43",X"3E",X"2F",X"21",X"48",X"04",X"E7", + X"E5",X"DD",X"E1",X"21",X"14",X"85",X"CD",X"9F",X"04",X"CD",X"01",X"0C",X"CD",X"34",X"0B",X"3A", + X"07",X"98",X"E6",X"0F",X"C0",X"21",X"17",X"98",X"35",X"7E",X"20",X"02",X"36",X"03",X"87",X"F5", + X"21",X"F5",X"0B",X"E7",X"5E",X"23",X"56",X"EB",X"11",X"6E",X"85",X"CD",X"43",X"11",X"F1",X"21", + X"FB",X"0B",X"E7",X"5E",X"23",X"56",X"EB",X"11",X"6A",X"85",X"C3",X"43",X"11",X"21",X"14",X"85", + X"CD",X"3C",X"0B",X"18",X"C7",X"FB",X"41",X"3B",X"42",X"5B",X"42",X"DB",X"3C",X"DB",X"40",X"DB", + X"3C",X"01",X"20",X"00",X"11",X"0B",X"0C",X"09",X"C3",X"08",X"05",X"50",X"54",X"53",X"2F",X"11", + X"A1",X"03",X"FF",X"21",X"03",X"98",X"34",X"C9",X"21",X"40",X"98",X"01",X"01",X"40",X"AF",X"D7", + X"21",X"03",X"98",X"34",X"AF",X"32",X"17",X"98",X"C9",X"3A",X"03",X"98",X"CF",X"9A",X"0C",X"D2", + X"0C",X"08",X"0D",X"3F",X"0C",X"45",X"0C",X"8B",X"0C",X"34",X"0B",X"18",X"0C",X"9D",X"10",X"CD", + X"4B",X"0C",X"C3",X"A7",X"0A",X"CD",X"4B",X"0C",X"C3",X"D3",X"0A",X"3A",X"07",X"98",X"E6",X"1F", + X"C0",X"DD",X"21",X"1F",X"99",X"DD",X"7E",X"FE",X"D6",X"10",X"27",X"DD",X"77",X"FE",X"DD",X"7E", + X"FF",X"DE",X"00",X"27",X"DD",X"77",X"FF",X"21",X"F4",X"85",X"CD",X"9F",X"04",X"CD",X"01",X"0C", + X"21",X"1E",X"99",X"11",X"6F",X"86",X"7E",X"CD",X"7C",X"0C",X"2D",X"7E",X"0F",X"0F",X"0F",X"0F", + X"CD",X"84",X"0C",X"7E",X"E6",X"0F",X"C6",X"2C",X"12",X"1D",X"C9",X"CD",X"7D",X"11",X"11",X"25", + X"03",X"FF",X"1E",X"24",X"FF",X"21",X"03",X"98",X"34",X"C9",X"3A",X"07",X"98",X"0F",X"D8",X"CD", + X"91",X"11",X"3A",X"2C",X"98",X"FE",X"20",X"D8",X"AF",X"32",X"2C",X"98",X"CD",X"61",X"11",X"CD", + X"6F",X"11",X"21",X"83",X"0A",X"CD",X"C4",X"11",X"11",X"03",X"03",X"FF",X"1E",X"0E",X"FF",X"21", + X"A3",X"0A",X"11",X"40",X"98",X"01",X"04",X"00",X"ED",X"B0",X"CD",X"7D",X"11",X"21",X"03",X"98", + X"34",X"C9",X"11",X"6E",X"85",X"21",X"BB",X"3C",X"CD",X"31",X"11",X"21",X"FB",X"40",X"CD",X"31", + X"11",X"21",X"BB",X"43",X"3E",X"02",X"CD",X"1F",X"11",X"11",X"6A",X"85",X"21",X"BB",X"44",X"CD", + X"31",X"11",X"21",X"7B",X"41",X"CD",X"31",X"11",X"21",X"DB",X"43",X"3E",X"02",X"CD",X"1F",X"11", + X"21",X"02",X"98",X"36",X"02",X"2C",X"34",X"C9",X"11",X"30",X"0D",X"21",X"00",X"15",X"22",X"1D", + X"99",X"21",X"9A",X"9A",X"22",X"6C",X"8E",X"22",X"6E",X"8E",X"EB",X"11",X"6C",X"86",X"01",X"04", + X"00",X"ED",X"B0",X"21",X"03",X"98",X"34",X"C9",X"11",X"34",X"0D",X"21",X"40",X"00",X"18",X"DE", + X"2C",X"2C",X"31",X"2D",X"2C",X"30",X"2C",X"2C",X"3A",X"03",X"98",X"CF",X"9A",X"0C",X"4E",X"0D", + X"28",X"0D",X"94",X"0D",X"A6",X"0D",X"BD",X"0D",X"E1",X"0F",X"18",X"0C",X"9D",X"10",X"FD",X"21", + X"00",X"9D",X"FD",X"36",X"00",X"00",X"FD",X"36",X"01",X"00",X"FD",X"36",X"1F",X"01",X"11",X"6E", + X"85",X"21",X"9B",X"44",X"CD",X"31",X"11",X"21",X"FB",X"44",X"CD",X"31",X"11",X"21",X"BB",X"43", + X"3E",X"02",X"CD",X"1F",X"11",X"11",X"6A",X"85",X"21",X"9B",X"40",X"CD",X"31",X"11",X"21",X"1B", + X"45",X"CD",X"31",X"11",X"21",X"DB",X"43",X"3E",X"02",X"CD",X"1F",X"11",X"21",X"02",X"98",X"36", + X"02",X"2C",X"34",X"C9",X"CD",X"4B",X"0C",X"CD",X"C6",X"0D",X"21",X"1D",X"99",X"7E",X"2C",X"B6", + X"C0",X"21",X"03",X"98",X"34",X"C9",X"21",X"18",X"02",X"22",X"20",X"9D",X"7C",X"32",X"47",X"98", + X"0F",X"32",X"3F",X"9D",X"11",X"22",X"03",X"FF",X"21",X"03",X"98",X"34",X"C9",X"CD",X"09",X"0F", + X"CD",X"C6",X"0D",X"C3",X"7A",X"0F",X"21",X"ED",X"0D",X"E5",X"DD",X"21",X"40",X"98",X"FD",X"21", + X"00",X"9D",X"21",X"FD",X"10",X"22",X"1B",X"99",X"FD",X"7E",X"01",X"FD",X"77",X"1E",X"CF",X"B9", + X"0F",X"C3",X"0F",X"C3",X"0F",X"A0",X"0F",X"C3",X"0F",X"C3",X"0F",X"C3",X"0F",X"FD",X"7E",X"1E", + X"FD",X"BE",X"01",X"C8",X"FE",X"05",X"C8",X"B7",X"20",X"08",X"FD",X"36",X"1F",X"FF",X"FD",X"36", + X"00",X"C0",X"FE",X"04",X"20",X"07",X"CD",X"0D",X"0E",X"FD",X"7E",X"1E",X"3C",X"87",X"87",X"21", + X"27",X"0E",X"E7",X"5E",X"23",X"56",X"23",X"7E",X"23",X"66",X"6F",X"FD",X"7E",X"1E",X"FE",X"04", + X"C2",X"31",X"11",X"0F",X"C3",X"1F",X"11",X"EE",X"85",X"9B",X"44",X"6E",X"85",X"BB",X"3C",X"6A", + X"85",X"9B",X"3C",X"EA",X"85",X"DB",X"40",X"6A",X"86",X"DB",X"42",X"6E",X"86",X"BB",X"42",X"EE", + X"85",X"BB",X"3C",X"3A",X"03",X"98",X"CF",X"51",X"0E",X"CD",X"0E",X"E1",X"0F",X"18",X"0C",X"9D", + X"10",X"3A",X"07",X"98",X"0F",X"D8",X"CD",X"91",X"11",X"3A",X"2C",X"98",X"FE",X"20",X"D8",X"AF", + X"32",X"2C",X"98",X"CD",X"61",X"11",X"CD",X"6F",X"11",X"21",X"83",X"0A",X"CD",X"C4",X"11",X"11", + X"03",X"03",X"FF",X"1E",X"0E",X"FF",X"21",X"C5",X"0E",X"11",X"40",X"98",X"01",X"08",X"00",X"ED", + X"B0",X"3E",X"FF",X"32",X"1F",X"9D",X"32",X"3F",X"9D",X"ED",X"43",X"20",X"9D",X"21",X"C0",X"04", + X"22",X"00",X"9D",X"11",X"6E",X"85",X"21",X"9B",X"44",X"CD",X"31",X"11",X"21",X"BB",X"44",X"CD", + X"31",X"11",X"21",X"7B",X"44",X"CD",X"31",X"11",X"11",X"6A",X"85",X"21",X"FB",X"40",X"CD",X"31", + X"11",X"21",X"BB",X"44",X"CD",X"31",X"11",X"21",X"BB",X"40",X"CD",X"31",X"11",X"21",X"02",X"98", + X"36",X"40",X"2C",X"34",X"C9",X"E1",X"78",X"78",X"01",X"D4",X"98",X"8C",X"07",X"CD",X"1E",X"0F", + X"3A",X"1F",X"99",X"B7",X"28",X"06",X"CD",X"43",X"0F",X"C3",X"7A",X"0F",X"3A",X"07",X"98",X"E6", + X"04",X"21",X"00",X"00",X"28",X"03",X"2A",X"CA",X"0E",X"22",X"45",X"98",X"3A",X"42",X"98",X"FE", + X"7C",X"D8",X"3E",X"03",X"32",X"22",X"9D",X"32",X"1F",X"99",X"3C",X"32",X"47",X"98",X"2A",X"CA", + X"0E",X"22",X"45",X"98",X"11",X"23",X"03",X"FF",X"C9",X"3A",X"07",X"98",X"0F",X"D8",X"DD",X"21", + X"44",X"98",X"FD",X"21",X"20",X"9D",X"21",X"ED",X"10",X"22",X"1B",X"99",X"18",X"13",X"3A",X"07", + X"98",X"0F",X"D0",X"21",X"FD",X"10",X"22",X"1B",X"99",X"DD",X"21",X"40",X"98",X"FD",X"21",X"00", + X"9D",X"FD",X"7E",X"01",X"CF",X"A0",X"0F",X"BE",X"0F",X"BE",X"0F",X"A9",X"0F",X"C3",X"0F",X"C3", + X"0F",X"DC",X"0F",X"DD",X"21",X"44",X"98",X"FD",X"21",X"20",X"9D",X"3A",X"07",X"98",X"0F",X"30", + X"14",X"FD",X"35",X"02",X"FD",X"7E",X"02",X"20",X"04",X"FD",X"36",X"02",X"03",X"21",X"74",X"0F", + X"E7",X"7E",X"DD",X"77",X"00",X"FD",X"7E",X"01",X"B7",X"28",X"C6",X"FE",X"03",X"28",X"C2",X"FD", + X"35",X"00",X"18",X"BD",X"CC",X"D0",X"D4",X"05",X"06",X"07",X"DD",X"21",X"40",X"98",X"DD",X"7E", + X"01",X"DD",X"96",X"05",X"30",X"02",X"ED",X"44",X"FE",X"0C",X"D0",X"DD",X"7E",X"02",X"DD",X"96", + X"06",X"30",X"02",X"ED",X"44",X"FE",X"0C",X"D0",X"21",X"02",X"98",X"36",X"80",X"2C",X"34",X"C9", + X"11",X"01",X"90",X"FD",X"36",X"00",X"40",X"18",X"03",X"11",X"FF",X"70",X"DD",X"7E",X"02",X"83", + X"DD",X"77",X"02",X"BA",X"C0",X"FD",X"34",X"01",X"C9",X"01",X"70",X"68",X"18",X"08",X"01",X"90", + X"88",X"18",X"03",X"01",X"70",X"88",X"FD",X"7E",X"00",X"CD",X"AB",X"10",X"FD",X"7E",X"1F",X"FD", + X"86",X"00",X"FD",X"77",X"00",X"E6",X"3F",X"C0",X"FD",X"34",X"01",X"C9",X"FD",X"36",X"01",X"00", + X"C9",X"DD",X"21",X"40",X"98",X"CD",X"EF",X"0F",X"DD",X"21",X"44",X"98",X"C3",X"12",X"10",X"11", + X"31",X"10",X"21",X"02",X"98",X"35",X"7E",X"20",X"02",X"2C",X"34",X"0F",X"0F",X"E6",X"03",X"EB", + X"E7",X"7E",X"DD",X"77",X"00",X"3E",X"04",X"E7",X"7E",X"DD",X"77",X"03",X"C9",X"11",X"39",X"10", + X"18",X"E0",X"3A",X"3F",X"9D",X"07",X"30",X"F5",X"21",X"22",X"9D",X"35",X"7E",X"20",X"02",X"36", + X"03",X"21",X"74",X"0F",X"E7",X"7E",X"DD",X"77",X"00",X"3E",X"03",X"E7",X"7E",X"DD",X"77",X"03", + X"C9",X"F1",X"E1",X"D1",X"C1",X"10",X"0C",X"04",X"08",X"83",X"81",X"93",X"91",X"1A",X"09",X"08", + X"07",X"CD",X"6D",X"22",X"21",X"01",X"98",X"34",X"C9",X"CD",X"55",X"11",X"CD",X"92",X"15",X"CD", + X"55",X"11",X"FE",X"03",X"20",X"17",X"11",X"0E",X"03",X"FF",X"1E",X"03",X"FF",X"C9",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FE",X"05",X"C0", + X"34",X"C9",X"3A",X"03",X"98",X"CF",X"7C",X"10",X"34",X"0B",X"9D",X"10",X"3A",X"07",X"98",X"0F", + X"D8",X"CD",X"91",X"11",X"3A",X"2C",X"98",X"FE",X"20",X"D8",X"AF",X"32",X"2C",X"98",X"CD",X"61", + X"11",X"CD",X"6F",X"11",X"11",X"01",X"08",X"FF",X"21",X"03",X"98",X"34",X"C9",X"21",X"03",X"98", + X"36",X"00",X"2D",X"2D",X"34",X"C9",X"AF",X"32",X"01",X"98",X"C9",X"6F",X"CB",X"3F",X"AD",X"ED", + X"47",X"11",X"7A",X"4D",X"26",X"00",X"29",X"19",X"CD",X"0D",X"11",X"80",X"DD",X"77",X"01",X"EB", + X"23",X"CD",X"0D",X"11",X"81",X"DD",X"77",X"02",X"FD",X"7E",X"00",X"E6",X"0F",X"FE",X"08",X"C0", + X"FD",X"AE",X"00",X"0F",X"0F",X"0F",X"0F",X"FD",X"CB",X"1F",X"7E",X"20",X"04",X"C6",X"09",X"E6", + X"0F",X"4F",X"06",X"00",X"2A",X"1B",X"99",X"09",X"7E",X"DD",X"77",X"00",X"C9",X"91",X"8D",X"89", + X"85",X"81",X"9D",X"99",X"95",X"91",X"8D",X"89",X"85",X"81",X"9D",X"99",X"95",X"D1",X"CD",X"C9", + X"C5",X"C1",X"FD",X"F9",X"F5",X"F1",X"ED",X"E9",X"E5",X"E1",X"DD",X"D9",X"D5",X"5E",X"16",X"00", + X"EB",X"29",X"29",X"29",X"29",X"ED",X"57",X"07",X"ED",X"47",X"7C",X"D0",X"ED",X"44",X"C9",X"ED", + X"A0",X"ED",X"A0",X"ED",X"A0",X"ED",X"A0",X"01",X"1C",X"00",X"EB",X"09",X"EB",X"3D",X"20",X"EF", + X"C9",X"D5",X"3E",X"04",X"CD",X"1F",X"11",X"EB",X"E3",X"EB",X"CB",X"DA",X"3E",X"04",X"CD",X"1F", + X"11",X"D1",X"C9",X"D5",X"3E",X"04",X"CD",X"1F",X"11",X"EB",X"E3",X"EB",X"CB",X"DA",X"3E",X"04", + X"CD",X"1F",X"11",X"D1",X"C9",X"11",X"01",X"98",X"21",X"17",X"98",X"4E",X"1A",X"EB",X"71",X"12", + X"C9",X"11",X"00",X"03",X"FF",X"1C",X"FF",X"1C",X"3A",X"0A",X"98",X"B7",X"20",X"FF",X"C9",X"11", + X"00",X"02",X"FF",X"1C",X"3A",X"0A",X"98",X"B7",X"20",X"FF",X"1C",X"FF",X"C9",X"21",X"6A",X"8E", + X"11",X"18",X"00",X"0E",X"02",X"06",X"08",X"36",X"C0",X"23",X"10",X"FB",X"0D",X"19",X"20",X"F5", + X"C9",X"21",X"B7",X"11",X"E5",X"3A",X"2C",X"98",X"3C",X"32",X"2C",X"98",X"6F",X"26",X"00",X"E6", + X"1E",X"BD",X"20",X"03",X"25",X"ED",X"44",X"6F",X"29",X"29",X"29",X"29",X"11",X"00",X"86",X"19", + X"3E",X"10",X"01",X"01",X"1C",X"D7",X"C9",X"7D",X"E6",X"E0",X"6F",X"CB",X"94",X"01",X"01",X"08", + X"3E",X"10",X"D7",X"C9",X"22",X"30",X"98",X"11",X"04",X"88",X"01",X"04",X"00",X"CD",X"DC",X"11", + X"2A",X"30",X"98",X"3E",X"04",X"E7",X"11",X"00",X"8C",X"01",X"1C",X"00",X"D9",X"06",X"20",X"D9", + X"C5",X"ED",X"B0",X"C1",X"B7",X"ED",X"42",X"EB",X"ED",X"42",X"3E",X"20",X"E7",X"EB",X"D9",X"10", + X"EE",X"C9",X"21",X"10",X"39",X"10",X"1C",X"01",X"0A",X"01",X"2B",X"01",X"09",X"20",X"0C",X"20", + X"40",X"02",X"30",X"20",X"36",X"01",X"25",X"10",X"08",X"10",X"50",X"02",X"20",X"20",X"20",X"02", + X"50",X"10",X"40",X"02",X"40",X"20",X"40",X"20",X"40",X"20",X"40",X"00",X"40",X"00",X"40",X"00", + X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"01",X"40",X"20",X"40",X"00",X"40",X"00", + X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"02",X"40",X"20",X"40",X"00", + X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"01",X"40",X"01", + X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"10",X"40",X"00",X"40",X"00",X"40",X"00", + X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00", + X"40",X"00",X"40",X"00",X"40",X"10",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00", + X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"20",X"40",X"00",X"40",X"00", + X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00", + X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00", + X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"40",X"00",X"3A",X"09",X"99",X"B7",X"C8",X"FD", + X"E5",X"E1",X"4F",X"06",X"03",X"2C",X"AF",X"86",X"86",X"2C",X"10",X"FB",X"06",X"06",X"86",X"2C", + X"10",X"FC",X"FE",X"1E",X"D8",X"41",X"3E",X"F0",X"A5",X"6F",X"D9",X"CD",X"8F",X"01",X"E6",X"1E", + X"21",X"FE",X"12",X"E7",X"7E",X"B7",X"28",X"F3",X"23",X"08",X"7E",X"D9",X"B5",X"6F",X"7E",X"B7", + X"28",X"E4",X"35",X"3E",X"F0",X"A5",X"6F",X"08",X"B5",X"6F",X"34",X"10",X"D9",X"C9",X"00",X"00", + X"04",X"01",X"06",X"02",X"08",X"03",X"0B",X"04",X"0B",X"05",X"0B",X"06",X"0B",X"07",X"0B",X"08", + X"0B",X"09",X"00",X"00",X"00",X"00",X"00",X"00",X"05",X"01",X"07",X"02",X"09",X"03",X"06",X"40", + X"1A",X"E6",X"3F",X"FE",X"10",X"30",X"06",X"B5",X"6F",X"34",X"E6",X"F0",X"6F",X"13",X"10",X"F0", + X"3E",X"0F",X"B5",X"6F",X"06",X"03",X"7E",X"36",X"00",X"2D",X"86",X"36",X"00",X"10",X"FA",X"77", + X"C9",X"21",X"02",X"99",X"3E",X"03",X"BE",X"38",X"01",X"7E",X"87",X"87",X"87",X"ED",X"44",X"C6", + X"80",X"2C",X"77",X"2E",X"07",X"36",X"04",X"3A",X"02",X"99",X"FE",X"08",X"38",X"02",X"3E",X"07", + X"87",X"21",X"9F",X"13",X"E7",X"4E",X"23",X"46",X"ED",X"43",X"0C",X"99",X"3A",X"02",X"99",X"47", + X"E6",X"0F",X"4F",X"A8",X"0F",X"47",X"0F",X"0F",X"80",X"81",X"E6",X"07",X"21",X"96",X"13",X"E7", + X"7E",X"32",X"06",X"99",X"47",X"E6",X"0E",X"4F",X"A8",X"0F",X"0F",X"0F",X"0F",X"E6",X"0E",X"81", + X"6F",X"67",X"22",X"09",X"99",X"C9",X"44",X"54",X"64",X"45",X"56",X"55",X"65",X"66",X"46",X"18", + X"00",X"10",X"01",X"0C",X"02",X"0A",X"03",X"08",X"04",X"06",X"05",X"05",X"06",X"04",X"07",X"11", + X"A0",X"99",X"21",X"C2",X"13",X"01",X"10",X"00",X"ED",X"B0",X"21",X"C2",X"13",X"0E",X"10",X"ED", + X"B0",X"C9",X"01",X"08",X"08",X"08",X"01",X"02",X"02",X"01",X"02",X"02",X"00",X"00",X"01",X"00", + X"00",X"00",X"3A",X"02",X"99",X"87",X"87",X"87",X"6F",X"67",X"22",X"0E",X"99",X"01",X"01",X"40", + X"3E",X"FF",X"DD",X"E5",X"E1",X"D7",X"CD",X"C4",X"14",X"CD",X"65",X"14",X"CD",X"53",X"15",X"CD", + X"3C",X"14",X"C9",X"3A",X"08",X"99",X"D6",X"04",X"2E",X"00",X"67",X"22",X"06",X"9D",X"E6",X"F0", + X"6F",X"AC",X"87",X"87",X"87",X"87",X"67",X"11",X"10",X"10",X"19",X"22",X"04",X"9D",X"3A",X"07", + X"9D",X"6F",X"26",X"9A",X"6E",X"26",X"00",X"29",X"29",X"29",X"3E",X"04",X"E7",X"11",X"3B",X"45", + X"19",X"5E",X"23",X"56",X"ED",X"53",X"08",X"9D",X"11",X"82",X"99",X"3A",X"09",X"98",X"B7",X"28", + X"02",X"1E",X"92",X"01",X"08",X"00",X"21",X"02",X"9D",X"ED",X"B0",X"C9",X"DD",X"E5",X"E1",X"FD", + X"E5",X"D1",X"01",X"00",X"10",X"1A",X"B7",X"28",X"17",X"7D",X"E6",X"C0",X"6F",X"D9",X"CD",X"8F", + X"01",X"D9",X"E6",X"3F",X"B5",X"6F",X"7E",X"3C",X"20",X"EF",X"71",X"EB",X"35",X"EB",X"20",X"E9", + X"0C",X"13",X"10",X"E1",X"C9",X"3A",X"06",X"99",X"4F",X"E6",X"0F",X"47",X"A9",X"0F",X"0F",X"0F", + X"0F",X"4F",X"ED",X"43",X"24",X"98",X"0E",X"24",X"11",X"18",X"19",X"DD",X"E5",X"E1",X"CD",X"B1", + X"14",X"ED",X"4B",X"24",X"98",X"58",X"41",X"16",X"00",X"4A",X"1C",X"CB",X"38",X"30",X"01",X"0C", + X"36",X"1E",X"19",X"36",X"1C",X"2C",X"36",X"1F",X"19",X"36",X"1D",X"2C",X"10",X"F2",X"CB",X"41", + X"28",X"06",X"36",X"23",X"19",X"36",X"22",X"2C",X"3A",X"25",X"98",X"47",X"0E",X"21",X"11",X"1A", + X"1B",X"36",X"20",X"2C",X"CB",X"38",X"30",X"02",X"71",X"2C",X"72",X"2C",X"73",X"2C",X"10",X"FA", + X"36",X"20",X"2C",X"C9",X"3A",X"06",X"99",X"47",X"E6",X"03",X"4F",X"A8",X"0F",X"0F",X"E6",X"0C", + X"B1",X"87",X"21",X"3D",X"15",X"E7",X"7E",X"32",X"08",X"99",X"23",X"7E",X"5F",X"AF",X"57",X"DD", + X"E5",X"E1",X"19",X"77",X"FD",X"35",X"00",X"CD",X"13",X"15",X"23",X"D9",X"FD",X"E5",X"C1",X"CD", + X"8F",X"01",X"E6",X"07",X"28",X"F9",X"21",X"0B",X"15",X"E7",X"7E",X"57",X"60",X"69",X"E7",X"35", + X"F2",X"07",X"15",X"34",X"C3",X"EF",X"14",X"7A",X"D9",X"77",X"C9",X"00",X"01",X"02",X"03",X"05", + X"07",X"09",X"0C",X"2B",X"2B",X"FD",X"7E",X"03",X"B7",X"28",X"06",X"36",X"03",X"FD",X"35",X"03", + X"C9",X"FD",X"7E",X"09",X"B7",X"28",X"06",X"36",X"09",X"FD",X"35",X"09",X"C9",X"36",X"09",X"AF", + X"06",X"0F",X"FD",X"E5",X"D1",X"EB",X"23",X"B6",X"28",X"FC",X"35",X"EB",X"C9",X"8A",X"16",X"89", + X"19",X"8A",X"1D",X"00",X"00",X"7A",X"16",X"79",X"19",X"7A",X"1D",X"00",X"00",X"8A",X"1C",X"89", + X"20",X"8A",X"25",X"3A",X"06",X"99",X"C6",X"11",X"47",X"E6",X"0F",X"4F",X"A8",X"0F",X"0F",X"0F", + X"0F",X"81",X"87",X"ED",X"44",X"C6",X"1C",X"C8",X"47",X"36",X"20",X"2C",X"10",X"FB",X"7D",X"E6", + X"3F",X"2F",X"C6",X"40",X"47",X"04",X"FD",X"E5",X"D1",X"EB",X"7D",X"6F",X"D9",X"CD",X"8F",X"01", + X"D9",X"E6",X"0F",X"12",X"B5",X"6F",X"E6",X"F0",X"35",X"34",X"28",X"EF",X"35",X"6F",X"13",X"10", + X"EA",X"C9",X"CD",X"01",X"17",X"3A",X"01",X"98",X"CF",X"AF",X"15",X"E3",X"15",X"BE",X"16",X"7D", + X"17",X"6C",X"18",X"DC",X"18",X"30",X"19",X"A8",X"19",X"F1",X"19",X"D9",X"1A",X"54",X"1D",X"AF", + X"21",X"40",X"98",X"01",X"01",X"50",X"D7",X"21",X"00",X"9D",X"01",X"02",X"00",X"D7",X"21",X"00", + X"9A",X"01",X"02",X"00",X"D7",X"21",X"00",X"99",X"01",X"01",X"80",X"D7",X"21",X"01",X"98",X"34", + X"AF",X"32",X"2C",X"98",X"32",X"03",X"98",X"3A",X"08",X"98",X"47",X"3A",X"BE",X"98",X"A0",X"32", + X"20",X"98",X"C9",X"CD",X"1E",X"16",X"3A",X"0A",X"98",X"B7",X"C4",X"4E",X"16",X"3A",X"08",X"98", + X"B7",X"28",X"1A",X"11",X"0B",X"03",X"ED",X"53",X"24",X"98",X"21",X"01",X"98",X"34",X"2C",X"36", + X"00",X"3A",X"08",X"98",X"B7",X"C4",X"91",X"20",X"AF",X"32",X"2C",X"98",X"C9",X"21",X"01",X"98", + X"34",X"2C",X"36",X"01",X"AF",X"32",X"2C",X"98",X"3E",X"25",X"32",X"20",X"99",X"C9",X"11",X"80", + X"99",X"21",X"6D",X"17",X"01",X"10",X"00",X"ED",X"B0",X"3A",X"0C",X"98",X"32",X"00",X"99",X"CD", + X"AF",X"13",X"CD",X"41",X"13",X"DD",X"21",X"00",X"9B",X"FD",X"21",X"A0",X"99",X"CD",X"D2",X"13", + X"DD",X"21",X"00",X"99",X"21",X"00",X"9B",X"CD",X"0D",X"1C",X"CD",X"F3",X"13",X"C9",X"21",X"00", + X"99",X"11",X"60",X"99",X"01",X"20",X"00",X"ED",X"B0",X"21",X"80",X"99",X"11",X"90",X"99",X"0E", + X"10",X"ED",X"B0",X"11",X"40",X"9B",X"21",X"00",X"9B",X"0E",X"40",X"ED",X"B0",X"C9",X"81",X"8C", + X"9A",X"81",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80", + X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"3A",X"08", + X"98",X"B7",X"28",X"0B",X"ED",X"5B",X"24",X"98",X"FF",X"3A",X"0A",X"98",X"B7",X"28",X"08",X"11", + X"01",X"02",X"FF",X"11",X"02",X"03",X"FF",X"11",X"00",X"02",X"FF",X"1E",X"02",X"FF",X"11",X"01", + X"03",X"FF",X"1D",X"FF",X"21",X"2C",X"98",X"34",X"21",X"6E",X"16",X"C3",X"C4",X"11",X"3A",X"2C", + X"98",X"FE",X"21",X"30",X"16",X"3A",X"07",X"98",X"0F",X"D8",X"3E",X"10",X"CD",X"91",X"11",X"3A", + X"2C",X"98",X"FE",X"20",X"D8",X"11",X"0E",X"03",X"FF",X"18",X"B3",X"21",X"02",X"98",X"35",X"28", + X"11",X"3E",X"07",X"A6",X"C0",X"3E",X"18",X"A6",X"ED",X"5B",X"24",X"98",X"20",X"02",X"CB",X"FB", + X"FF",X"C9",X"36",X"40",X"2D",X"34",X"11",X"CB",X"03",X"FF",X"1E",X"8E",X"FF",X"CD",X"20",X"17", + X"C9",X"3A",X"08",X"98",X"0F",X"D0",X"3A",X"07",X"98",X"47",X"E6",X"07",X"C0",X"11",X"01",X"03", + X"3A",X"09",X"98",X"0F",X"30",X"01",X"1C",X"3E",X"18",X"A0",X"20",X"02",X"CB",X"FB",X"FF",X"C9", + X"3A",X"06",X"99",X"ED",X"44",X"C6",X"66",X"32",X"38",X"98",X"C9",X"3A",X"06",X"99",X"47",X"3A", + X"38",X"98",X"ED",X"44",X"C6",X"66",X"B8",X"3A",X"38",X"98",X"CD",X"CD",X"30",X"3A",X"38",X"98", + X"CD",X"47",X"17",X"32",X"38",X"98",X"C9",X"4F",X"E6",X"F0",X"47",X"A9",X"4F",X"3A",X"06",X"99", + X"C6",X"88",X"5F",X"E6",X"F0",X"57",X"AB",X"5F",X"B9",X"20",X"0A",X"78",X"BA",X"30",X"0B",X"7B", + X"2F",X"C6",X"2F",X"80",X"C9",X"3E",X"02",X"80",X"81",X"C9",X"3E",X"FF",X"C9",X"01",X"00",X"90", + X"50",X"A0",X"30",X"F0",X"84",X"00",X"02",X"00",X"00",X"D1",X"01",X"01",X"C1",X"3A",X"38",X"98", + X"3C",X"28",X"3A",X"CD",X"2B",X"17",X"3A",X"38",X"98",X"3C",X"C0",X"11",X"00",X"9D",X"21",X"80", + X"99",X"01",X"10",X"00",X"3A",X"09",X"98",X"B7",X"28",X"02",X"2E",X"90",X"ED",X"B0",X"21",X"00", + X"99",X"35",X"CD",X"15",X"18",X"CD",X"EF",X"24",X"CD",X"E9",X"17",X"11",X"00",X"06",X"FF",X"11", + X"00",X"05",X"FF",X"3A",X"0C",X"99",X"32",X"9B",X"9C",X"C3",X"D1",X"1C",X"C9",X"21",X"02",X"98", + X"35",X"C0",X"3A",X"0A",X"99",X"B7",X"28",X"16",X"21",X"01",X"98",X"34",X"2C",X"2C",X"36",X"00", + X"3E",X"10",X"32",X"98",X"9C",X"CD",X"82",X"20",X"CD",X"7B",X"2E",X"C3",X"13",X"20",X"21",X"08", + X"C0",X"22",X"01",X"98",X"AF",X"32",X"2C",X"98",X"C9",X"3A",X"08",X"9D",X"21",X"F5",X"17",X"E7", + X"7E",X"32",X"0C",X"9D",X"C9",X"D1",X"F1",X"C1",X"E1",X"F1",X"C1",X"F1",X"E1",X"C1",X"D1",X"D1", + X"E1",X"F1",X"C1",X"D1",X"E1",X"F1",X"F1",X"C1",X"C1",X"F1",X"F1",X"E1",X"E1",X"C1",X"C1",X"D1", + X"D1",X"D1",X"D1",X"E1",X"E1",X"11",X"30",X"9D",X"21",X"2C",X"18",X"3E",X"04",X"01",X"10",X"00", + X"EB",X"09",X"EB",X"ED",X"B0",X"3D",X"20",X"F5",X"CD",X"58",X"24",X"C9",X"00",X"00",X"10",X"70", + X"A0",X"30",X"F0",X"06",X"00",X"02",X"00",X"00",X"81",X"03",X"01",X"81",X"00",X"00",X"10",X"B0", + X"A0",X"30",X"F0",X"0A",X"00",X"02",X"00",X"00",X"81",X"02",X"01",X"81",X"00",X"00",X"F0",X"30", + X"A0",X"30",X"F0",X"E2",X"00",X"02",X"00",X"00",X"81",X"02",X"01",X"81",X"00",X"00",X"F0",X"70", + X"A0",X"30",X"F0",X"E6",X"00",X"02",X"00",X"00",X"81",X"02",X"01",X"81",X"CD",X"AE",X"33",X"CD", + X"C1",X"3B",X"CD",X"D1",X"1C",X"CD",X"CE",X"26",X"CD",X"7E",X"2A",X"3A",X"07",X"98",X"E6",X"0F", + X"CC",X"22",X"20",X"3A",X"00",X"9D",X"B7",X"C0",X"CD",X"EF",X"1F",X"DD",X"21",X"00",X"9D",X"DD", + X"36",X"06",X"F0",X"CD",X"3F",X"35",X"CD",X"B3",X"32",X"CD",X"98",X"35",X"3E",X"01",X"32",X"0D", + X"9D",X"11",X"80",X"99",X"21",X"00",X"9D",X"36",X"01",X"01",X"10",X"00",X"3A",X"09",X"98",X"B7", + X"28",X"02",X"1E",X"90",X"ED",X"B0",X"AF",X"32",X"2C",X"98",X"21",X"40",X"98",X"01",X"01",X"50", + X"D7",X"21",X"A0",X"99",X"01",X"01",X"12",X"D7",X"21",X"98",X"9C",X"01",X"01",X"68",X"D7",X"21", + X"80",X"9B",X"01",X"01",X"08",X"D7",X"21",X"01",X"98",X"36",X"05",X"C9",X"CD",X"95",X"11",X"3A", + X"2C",X"98",X"FE",X"20",X"D8",X"21",X"6E",X"16",X"CD",X"C4",X"11",X"AF",X"21",X"20",X"99",X"01", + X"01",X"20",X"D7",X"21",X"00",X"9D",X"01",X"02",X"00",X"D7",X"3E",X"08",X"32",X"89",X"9B",X"3A", + X"00",X"99",X"B7",X"20",X"0A",X"3E",X"0A",X"32",X"01",X"98",X"AF",X"32",X"03",X"98",X"C9",X"CD", + X"20",X"17",X"CD",X"FF",X"1B",X"28",X"06",X"3E",X"06",X"32",X"01",X"98",X"C9",X"21",X"03",X"40", + X"22",X"01",X"98",X"11",X"00",X"9B",X"CD",X"44",X"1C",X"21",X"00",X"9B",X"CD",X"0D",X"1C",X"C9", + X"3A",X"09",X"98",X"EE",X"01",X"32",X"09",X"98",X"20",X"47",X"21",X"00",X"99",X"11",X"60",X"99", + X"01",X"20",X"00",X"ED",X"B0",X"11",X"40",X"9B",X"CD",X"44",X"1C",X"21",X"40",X"99",X"11",X"00", + X"99",X"01",X"20",X"00",X"ED",X"B0",X"21",X"00",X"9B",X"CD",X"0D",X"1C",X"11",X"0B",X"03",X"ED", + X"53",X"24",X"98",X"11",X"01",X"03",X"FF",X"1C",X"FF",X"21",X"0B",X"98",X"3A",X"09",X"98",X"A6", + X"32",X"0E",X"98",X"EE",X"01",X"32",X"83",X"A1",X"21",X"01",X"98",X"36",X"02",X"2C",X"36",X"80", + X"C9",X"21",X"00",X"99",X"11",X"40",X"99",X"01",X"20",X"00",X"ED",X"B0",X"11",X"00",X"9B",X"CD", + X"44",X"1C",X"21",X"60",X"99",X"11",X"00",X"99",X"01",X"20",X"00",X"ED",X"B0",X"21",X"40",X"9B", + X"CD",X"0D",X"1C",X"11",X"0C",X"03",X"18",X"B7",X"3A",X"06",X"99",X"47",X"E6",X"0F",X"4F",X"A8", + X"47",X"87",X"81",X"ED",X"44",X"16",X"FF",X"87",X"5F",X"38",X"01",X"15",X"21",X"0E",X"86",X"19", + X"79",X"87",X"87",X"4F",X"2F",X"C6",X"21",X"5F",X"16",X"00",X"78",X"0F",X"0F",X"D9",X"47",X"3E", + X"10",X"D9",X"41",X"77",X"2C",X"10",X"FC",X"19",X"D9",X"10",X"F6",X"C9",X"3A",X"09",X"99",X"B7", + X"11",X"13",X"01",X"28",X"01",X"1D",X"FF",X"3A",X"09",X"99",X"B7",X"CA",X"CD",X"20",X"C3",X"AA", + X"20",X"3A",X"00",X"9D",X"0F",X"D2",X"88",X"18",X"3A",X"07",X"98",X"0F",X"D8",X"AF",X"21",X"44", + X"98",X"01",X"01",X"60",X"D7",X"3A",X"02",X"98",X"FE",X"BF",X"CC",X"A8",X"19",X"3A",X"02",X"98", + X"FE",X"B0",X"CC",X"DC",X"19",X"3A",X"02",X"98",X"47",X"E6",X"07",X"20",X"17",X"11",X"2B",X"03", + X"3A",X"09",X"99",X"B7",X"28",X"01",X"1C",X"3E",X"18",X"A0",X"20",X"02",X"CB",X"FB",X"FF",X"1E", + X"2F",X"FF",X"1C",X"FF",X"3A",X"09",X"99",X"B7",X"11",X"2D",X"03",X"28",X"01",X"1C",X"FF",X"21", + X"02",X"98",X"35",X"C0",X"34",X"11",X"AD",X"03",X"FF",X"AF",X"21",X"40",X"98",X"01",X"01",X"60", + X"D7",X"3E",X"10",X"CD",X"95",X"11",X"3A",X"2C",X"98",X"FE",X"20",X"D8",X"21",X"6E",X"16",X"CD", + X"C4",X"11",X"CD",X"B3",X"32",X"11",X"00",X"9B",X"3A",X"09",X"98",X"0F",X"30",X"02",X"1E",X"40", + X"CD",X"44",X"1C",X"3A",X"09",X"98",X"0F",X"38",X"57",X"11",X"00",X"9B",X"21",X"A0",X"99",X"D5", + X"DD",X"E1",X"E5",X"FD",X"E1",X"CD",X"1E",X"13",X"CD",X"BA",X"12",X"21",X"02",X"99",X"34",X"CD", + X"41",X"13",X"CD",X"D2",X"13",X"DD",X"E5",X"E1",X"CD",X"0D",X"1C",X"CD",X"F3",X"13",X"CD",X"20", + X"17",X"AF",X"21",X"20",X"99",X"01",X"01",X"20",X"D7",X"21",X"80",X"9B",X"01",X"01",X"10",X"D7", + X"21",X"98",X"9C",X"01",X"01",X"70",X"D7",X"21",X"20",X"9D",X"06",X"0B",X"11",X"20",X"00",X"77", + X"19",X"10",X"FC",X"21",X"00",X"99",X"34",X"21",X"01",X"98",X"34",X"AF",X"32",X"03",X"98",X"C9", + X"11",X"40",X"9B",X"21",X"A0",X"99",X"C3",X"7F",X"1A",X"3A",X"00",X"A1",X"CB",X"4F",X"28",X"15", + X"3A",X"02",X"99",X"C6",X"02",X"E6",X"03",X"20",X"0C",X"3A",X"03",X"98",X"CF",X"FC",X"1A",X"1D", + X"1B",X"4A",X"1B",X"69",X"1B",X"21",X"03",X"40",X"22",X"01",X"98",X"C9",X"21",X"03",X"98",X"34", + X"11",X"13",X"00",X"21",X"4F",X"84",X"3E",X"64",X"CD",X"10",X"1B",X"3E",X"C0",X"21",X"4F",X"8C", + X"0E",X"1C",X"06",X"0D",X"77",X"2C",X"10",X"FC",X"19",X"0D",X"20",X"F6",X"C9",X"21",X"40",X"02", + X"22",X"02",X"98",X"AF",X"21",X"30",X"98",X"06",X"04",X"77",X"2C",X"10",X"FC",X"11",X"67",X"85", + X"21",X"43",X"47",X"CD",X"39",X"1B",X"11",X"67",X"8D",X"3E",X"0A",X"01",X"0D",X"00",X"ED",X"B0", + X"EB",X"01",X"13",X"00",X"09",X"EB",X"3D",X"20",X"F2",X"C9",X"21",X"02",X"98",X"2C",X"34",X"21", + X"30",X"98",X"34",X"7E",X"EB",X"FE",X"06",X"30",X"9C",X"87",X"21",X"F5",X"1B",X"E7",X"4E",X"23", + X"46",X"ED",X"43",X"32",X"98",X"1C",X"AF",X"12",X"C9",X"3A",X"07",X"98",X"0F",X"D8",X"21",X"31", + X"98",X"7E",X"34",X"FE",X"15",X"38",X"06",X"3E",X"02",X"32",X"03",X"98",X"C9",X"11",X"20",X"00", + X"47",X"04",X"21",X"47",X"84",X"E7",X"3A",X"30",X"98",X"FE",X"05",X"28",X"47",X"3E",X"07",X"B8", + X"DC",X"DD",X"1B",X"E5",X"21",X"F0",X"1B",X"3A",X"30",X"98",X"E7",X"46",X"E1",X"7D",X"E6",X"1F", + X"21",X"60",X"85",X"B5",X"6F",X"3A",X"31",X"98",X"90",X"38",X"23",X"FE",X"0D",X"D0",X"D9",X"2A", + X"32",X"98",X"23",X"22",X"32",X"98",X"2B",X"11",X"0D",X"00",X"CD",X"C3",X"1B",X"D9",X"01",X"C0", + X"06",X"09",X"D9",X"06",X"0A",X"7E",X"19",X"D9",X"77",X"19",X"D9",X"10",X"F8",X"C9",X"06",X"0A", + X"3E",X"10",X"18",X"04",X"3E",X"10",X"06",X"1C",X"77",X"19",X"10",X"FC",X"C9",X"3E",X"71",X"CD", + X"D6",X"1B",X"01",X"80",X"04",X"09",X"3E",X"C0",X"C3",X"D6",X"1B",X"08",X"07",X"05",X"01",X"00", + X"00",X"01",X"03",X"07",X"08",X"43",X"47",X"47",X"48",X"4B",X"49",X"4F",X"4A",X"53",X"4B",X"21", + X"40",X"99",X"3A",X"09",X"98",X"B7",X"20",X"02",X"2E",X"60",X"7E",X"B7",X"C9",X"3A",X"06",X"99", + X"C6",X"22",X"47",X"4F",X"E6",X"0F",X"5F",X"A8",X"0F",X"0F",X"0F",X"0F",X"57",X"3E",X"88",X"91", + X"ED",X"53",X"2C",X"98",X"32",X"2E",X"98",X"16",X"9A",X"5F",X"D9",X"3A",X"2D",X"98",X"47",X"D9", + X"3A",X"2C",X"98",X"01",X"10",X"00",X"ED",X"A0",X"1C",X"3D",X"20",X"FA",X"EB",X"09",X"09",X"EB", + X"D9",X"10",X"EC",X"C9",X"3A",X"06",X"99",X"C6",X"22",X"47",X"4F",X"E6",X"0F",X"6F",X"A8",X"0F", + X"0F",X"0F",X"0F",X"67",X"3E",X"88",X"91",X"22",X"2C",X"98",X"32",X"2E",X"98",X"26",X"9A",X"6F", + X"D9",X"3A",X"2D",X"98",X"47",X"D9",X"3A",X"2C",X"98",X"01",X"10",X"00",X"08",X"7E",X"E6",X"3F", + X"12",X"23",X"13",X"08",X"0D",X"2C",X"3D",X"20",X"F3",X"09",X"09",X"D9",X"10",X"E7",X"21",X"00", + X"9A",X"AF",X"01",X"01",X"00",X"D7",X"C9",X"21",X"60",X"98",X"3A",X"00",X"9E",X"B7",X"28",X"38", + X"EB",X"3A",X"0E",X"98",X"0F",X"30",X"1B",X"01",X"06",X"00",X"21",X"14",X"9E",X"ED",X"B0",X"CD", + X"BE",X"1C",X"21",X"0E",X"9E",X"11",X"80",X"98",X"06",X"06",X"7E",X"2F",X"12",X"23",X"13",X"10", + X"F9",X"C9",X"21",X"14",X"9E",X"CD",X"A8",X"1C",X"CD",X"BE",X"1C",X"21",X"0E",X"9E",X"0E",X"0A", + X"EB",X"09",X"EB",X"0E",X"06",X"ED",X"B0",X"C9",X"21",X"80",X"98",X"01",X"01",X"10",X"AF",X"D7", + X"C9",X"CD",X"87",X"1C",X"06",X"08",X"11",X"20",X"00",X"21",X"40",X"98",X"DD",X"21",X"00",X"9D", + X"3A",X"0E",X"98",X"0F",X"38",X"35",X"0E",X"07",X"DD",X"7E",X"00",X"B7",X"28",X"22",X"DD",X"7E", + X"0C",X"77",X"2C",X"2C",X"DD",X"7E",X"02",X"D6",X"08",X"77",X"2D",X"DD",X"7E",X"03",X"C6",X"27", + X"2F",X"C6",X"20",X"77",X"DD",X"7E",X"0D",X"2C",X"2C",X"77",X"2C",X"DD",X"19",X"10",X"D9",X"C9", + X"2C",X"77",X"2C",X"77",X"2C",X"2C",X"DD",X"19",X"10",X"CE",X"C9",X"DD",X"7E",X"00",X"B7",X"28", + X"28",X"0E",X"00",X"DD",X"7E",X"0C",X"EE",X"02",X"77",X"2C",X"DD",X"7E",X"03",X"D6",X"08",X"30", + X"02",X"0E",X"80",X"77",X"2C",X"DD",X"7E",X"02",X"ED",X"44",X"D6",X"07",X"77",X"2C",X"DD",X"7E", + X"0D",X"B1",X"77",X"2C",X"DD",X"19",X"10",X"D3",X"C9",X"2C",X"77",X"2C",X"77",X"2C",X"2C",X"DD", + X"19",X"10",X"C8",X"C9",X"CD",X"FF",X"1B",X"20",X"04",X"21",X"C0",X"21",X"E5",X"3A",X"03",X"98", + X"CF",X"69",X"1D",X"7F",X"1D",X"95",X"1D",X"D2",X"1D",X"11",X"0D",X"03",X"FF",X"3A",X"09",X"98", + X"B7",X"1E",X"0B",X"28",X"01",X"1C",X"FF",X"21",X"03",X"98",X"34",X"2D",X"36",X"60",X"C9",X"21", + X"02",X"98",X"35",X"C0",X"2C",X"34",X"CD",X"22",X"1E",X"11",X"8C",X"03",X"FF",X"1C",X"FF",X"16", + X"08",X"FF",X"C3",X"F0",X"20",X"3A",X"28",X"98",X"B7",X"C4",X"8F",X"1E",X"21",X"02",X"98",X"35", + X"C0",X"11",X"A0",X"03",X"FF",X"21",X"29",X"98",X"36",X"0A",X"2D",X"7E",X"B7",X"20",X"01",X"34", + X"3A",X"28",X"98",X"B7",X"C4",X"38",X"1F",X"21",X"28",X"98",X"7E",X"B7",X"36",X"00",X"28",X"02", + X"3E",X"80",X"3C",X"21",X"03",X"98",X"34",X"2D",X"77",X"11",X"FF",X"08",X"FF",X"AF",X"32",X"2C", + X"98",X"C9",X"21",X"02",X"98",X"35",X"C0",X"34",X"3E",X"10",X"CD",X"95",X"11",X"3A",X"2C",X"98", + X"FE",X"20",X"D8",X"CD",X"FF",X"1B",X"28",X"1B",X"21",X"05",X"80",X"01",X"20",X"1A",X"11",X"06", + X"00",X"3E",X"10",X"2C",X"77",X"10",X"FC",X"19",X"06",X"1A",X"0D",X"20",X"F6",X"3E",X"06",X"32", + X"01",X"98",X"C9",X"21",X"17",X"1E",X"11",X"00",X"98",X"01",X"0A",X"00",X"ED",X"B0",X"AF",X"32", + X"0E",X"98",X"3C",X"32",X"83",X"A1",X"C9",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"AF",X"32",X"28",X"98",X"DD",X"21",X"C0",X"99",X"3A",X"09",X"98",X"B7",X"28",X"04", + X"DD",X"21",X"C3",X"99",X"06",X"0A",X"21",X"02",X"9F",X"11",X"0E",X"00",X"7E",X"DD",X"BE",X"02", + X"20",X"11",X"2B",X"7E",X"DD",X"BE",X"01",X"20",X"0B",X"2B",X"7E",X"DD",X"BE",X"00",X"20",X"05", + X"C3",X"57",X"1E",X"2B",X"2B",X"38",X"04",X"19",X"10",X"E2",X"C9",X"E5",X"21",X"28",X"98",X"70", + X"23",X"36",X"00",X"23",X"36",X"00",X"23",X"36",X"00",X"05",X"28",X"11",X"21",X"6B",X"9F",X"11", + X"77",X"9F",X"78",X"87",X"87",X"4F",X"87",X"81",X"4F",X"06",X"00",X"ED",X"B8",X"DD",X"E5",X"E1", + X"D1",X"ED",X"A0",X"ED",X"A0",X"ED",X"A0",X"EB",X"01",X"01",X"09",X"3E",X"40",X"D7",X"C9",X"21", + X"02",X"98",X"34",X"EB",X"21",X"04",X"99",X"DF",X"20",X"04",X"36",X"08",X"EB",X"35",X"3A",X"02", + X"98",X"47",X"E6",X"03",X"20",X"0A",X"11",X"32",X"03",X"CB",X"50",X"28",X"02",X"CB",X"FB",X"FF", + X"21",X"2B",X"98",X"DF",X"CD",X"0D",X"3B",X"B7",X"C4",X"D8",X"1E",X"C3",X"38",X"1F",X"21",X"2A", + X"98",X"34",X"28",X"06",X"2D",X"34",X"3E",X"04",X"BE",X"C0",X"21",X"29",X"98",X"36",X"10",X"21", + X"02",X"98",X"36",X"01",X"E1",X"C3",X"38",X"1F",X"21",X"2B",X"98",X"DF",X"C0",X"36",X"10",X"2D", + X"47",X"E6",X"33",X"28",X"D9",X"E6",X"30",X"28",X"19",X"34",X"28",X"DE",X"2D",X"CB",X"68",X"3E", + X"01",X"28",X"02",X"ED",X"44",X"86",X"FE",X"FF",X"20",X"02",X"3E",X"03",X"FE",X"04",X"28",X"CA", + X"77",X"2C",X"78",X"E6",X"03",X"C8",X"4F",X"2D",X"7E",X"FE",X"03",X"D0",X"2D",X"46",X"21",X"7B", + X"9F",X"11",X"F4",X"FF",X"19",X"10",X"FD",X"E7",X"CB",X"49",X"28",X"0E",X"34",X"3E",X"5B",X"BE", + X"D0",X"36",X"3B",X"21",X"2A",X"98",X"34",X"28",X"A1",X"C9",X"35",X"7E",X"FE",X"3B",X"D0",X"36", + X"5B",X"21",X"2A",X"98",X"34",X"28",X"93",X"C9",X"CD",X"8D",X"1F",X"DD",X"21",X"7B",X"9F",X"21", + X"A4",X"86",X"11",X"02",X"00",X"01",X"F4",X"FF",X"3A",X"28",X"98",X"DD",X"09",X"19",X"3D",X"20", + X"FA",X"DD",X"E5",X"D1",X"06",X"03",X"CD",X"D3",X"03",X"2B",X"3A",X"29",X"98",X"D6",X"03",X"5F", + X"3E",X"8E",X"16",X"2B",X"01",X"10",X"04",X"20",X"0B",X"36",X"37",X"CD",X"B5",X"1F",X"16",X"36", + X"05",X"CD",X"83",X"1F",X"1D",X"71",X"1C",X"20",X"01",X"72",X"CD",X"B5",X"1F",X"CD",X"83",X"1F", + X"10",X"F3",X"C9",X"08",X"7D",X"D6",X"20",X"6F",X"30",X"01",X"25",X"08",X"C9",X"3A",X"07",X"98", + X"47",X"E6",X"07",X"C0",X"3E",X"18",X"A0",X"28",X"22",X"FE",X"08",X"C0",X"21",X"84",X"84",X"3A", + X"28",X"98",X"87",X"85",X"6F",X"3E",X"8E",X"01",X"10",X"18",X"11",X"20",X"00",X"71",X"CD",X"B5", + X"1F",X"19",X"10",X"F9",X"C9",X"CB",X"DC",X"77",X"CB",X"9C",X"C9",X"11",X"FF",X"08",X"FF",X"C9", + X"21",X"CE",X"99",X"5E",X"16",X"99",X"1A",X"3C",X"C8",X"3D",X"47",X"3E",X"FF",X"12",X"1C",X"20", + X"02",X"1E",X"D0",X"73",X"3E",X"10",X"B8",X"28",X"17",X"3A",X"BF",X"98",X"21",X"08",X"98",X"B6", + X"C8",X"78",X"C3",X"F0",X"1F",X"3E",X"01",X"32",X"82",X"A1",X"C9",X"AF",X"32",X"82",X"A1",X"AF", + X"32",X"00",X"A1",X"3E",X"00",X"32",X"80",X"A1",X"00",X"00",X"00",X"00",X"3E",X"01",X"32",X"80", + X"A1",X"C9",X"47",X"11",X"CD",X"99",X"1A",X"6F",X"26",X"99",X"70",X"2C",X"20",X"02",X"2E",X"D0", + X"EB",X"73",X"C9",X"3E",X"1E",X"CD",X"02",X"20",X"3E",X"04",X"C3",X"02",X"20",X"3E",X"84",X"C3", + X"02",X"20",X"2A",X"30",X"99",X"29",X"29",X"7C",X"E6",X"0F",X"C8",X"C6",X"1D",X"C3",X"02",X"20", + X"3E",X"01",X"CD",X"02",X"20",X"3E",X"02",X"CD",X"02",X"20",X"3E",X"03",X"C3",X"02",X"20",X"3E", + X"05",X"C3",X"02",X"20",X"3E",X"85",X"C3",X"02",X"20",X"3E",X"85",X"CD",X"02",X"20",X"3E",X"06", + X"C3",X"02",X"20",X"3E",X"85",X"3E",X"86",X"C3",X"02",X"20",X"3E",X"07",X"C3",X"02",X"20",X"3E", + X"08",X"C3",X"02",X"20",X"3E",X"87",X"C3",X"02",X"20",X"3E",X"09",X"CD",X"02",X"20",X"3E",X"0A", + X"C3",X"02",X"20",X"3E",X"0B",X"C3",X"02",X"20",X"3E",X"0C",X"C3",X"02",X"20",X"3E",X"0D",X"C3", + X"02",X"20",X"3E",X"0E",X"C3",X"02",X"20",X"3E",X"0F",X"C3",X"02",X"20",X"3E",X"10",X"C3",X"02", + X"20",X"3E",X"00",X"CD",X"02",X"20",X"3E",X"11",X"CD",X"02",X"20",X"3E",X"12",X"CD",X"02",X"20", + X"3E",X"13",X"CD",X"02",X"20",X"3E",X"14",X"C3",X"02",X"20",X"3E",X"84",X"CD",X"02",X"20",X"3E", + X"85",X"CD",X"02",X"20",X"3E",X"86",X"CD",X"02",X"20",X"3E",X"87",X"CD",X"02",X"20",X"3E",X"15", + X"CD",X"02",X"20",X"3E",X"16",X"CD",X"02",X"20",X"3E",X"17",X"C3",X"02",X"20",X"3E",X"84",X"CD", + X"02",X"20",X"3E",X"85",X"CD",X"02",X"20",X"3E",X"86",X"CD",X"02",X"20",X"3E",X"87",X"CD",X"02", + X"20",X"3E",X"18",X"CD",X"02",X"20",X"3E",X"19",X"CD",X"02",X"20",X"3E",X"1A",X"C3",X"02",X"20", + X"3E",X"00",X"CD",X"02",X"20",X"3E",X"1B",X"CD",X"02",X"20",X"3E",X"1C",X"CD",X"02",X"20",X"3E", + X"1D",X"C3",X"02",X"20",X"3A",X"BE",X"98",X"B7",X"28",X"0B",X"AF",X"32",X"12",X"98",X"21",X"00", + X"00",X"22",X"00",X"98",X"C9",X"21",X"C0",X"21",X"E5",X"3A",X"01",X"98",X"CF",X"25",X"21",X"38", + X"21",X"8E",X"21",X"BB",X"21",X"21",X"40",X"98",X"01",X"01",X"50",X"AF",X"D7",X"32",X"2C",X"98", + X"21",X"02",X"98",X"36",X"10",X"2D",X"34",X"C9",X"3A",X"07",X"98",X"0F",X"D8",X"3E",X"10",X"CD", + X"91",X"11",X"3A",X"2C",X"98",X"FE",X"20",X"D8",X"11",X"01",X"02",X"FF",X"11",X"02",X"03",X"FF", + X"11",X"00",X"02",X"FF",X"1E",X"02",X"FF",X"11",X"01",X"03",X"FF",X"1D",X"FF",X"CD",X"EF",X"1F", + X"21",X"01",X"98",X"34",X"2C",X"36",X"FF",X"2C",X"AF",X"77",X"32",X"09",X"98",X"32",X"2C",X"98", + X"3C",X"32",X"83",X"A1",X"11",X"00",X"04",X"FF",X"11",X"07",X"03",X"FF",X"16",X"08",X"FF",X"3A", + X"0D",X"98",X"47",X"E6",X"0F",X"78",X"E6",X"F0",X"C8",X"0F",X"0F",X"0F",X"0F",X"C9",X"21",X"02", + X"98",X"DF",X"CC",X"75",X"22",X"3A",X"12",X"98",X"A7",X"C8",X"3D",X"11",X"08",X"03",X"28",X"01", + X"1C",X"0E",X"07",X"3A",X"07",X"98",X"47",X"E6",X"0F",X"C0",X"78",X"E6",X"30",X"20",X"04",X"CB", + X"FB",X"CB",X"F9",X"FF",X"59",X"FF",X"11",X"00",X"04",X"FF",X"C9",X"AF",X"32",X"01",X"98",X"C9", + X"3A",X"1C",X"98",X"E6",X"C0",X"C8",X"07",X"38",X"3B",X"3A",X"BE",X"98",X"B7",X"20",X"0B",X"3A", + X"12",X"98",X"FE",X"02",X"D8",X"D6",X"02",X"32",X"12",X"98",X"AF",X"21",X"C3",X"99",X"01",X"01", + X"03",X"D7",X"21",X"00",X"01",X"22",X"09",X"98",X"AF",X"21",X"C0",X"99",X"01",X"01",X"03",X"D7", + X"AF",X"32",X"01",X"98",X"32",X"0E",X"98",X"3C",X"32",X"83",X"A1",X"32",X"08",X"98",X"21",X"00", + X"98",X"36",X"03",X"C9",X"3A",X"BE",X"98",X"B7",X"20",X"09",X"3A",X"12",X"98",X"A7",X"C8",X"3D", + X"32",X"12",X"98",X"21",X"00",X"00",X"C3",X"E5",X"21",X"81",X"8C",X"9A",X"81",X"8C",X"8C",X"8E", + X"8E",X"8E",X"90",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80", + X"80",X"92",X"92",X"92",X"92",X"92",X"93",X"93",X"93",X"24",X"01",X"30",X"10",X"3C",X"02",X"30", + X"20",X"24",X"01",X"60",X"02",X"48",X"10",X"24",X"01",X"3C",X"20",X"24",X"02",X"30",X"20",X"21", + X"01",X"2A",X"01",X"21",X"10",X"1E",X"02",X"1E",X"02",X"3C",X"20",X"24",X"01",X"24",X"01",X"2A", + X"10",X"24",X"10",X"24",X"02",X"30",X"20",X"24",X"20",X"54",X"01",X"A8",X"FF",X"AF",X"32",X"2C", + X"98",X"32",X"03",X"98",X"C9",X"3A",X"03",X"98",X"CF",X"81",X"22",X"97",X"22",X"E7",X"22",X"5A", + X"23",X"3E",X"10",X"CD",X"95",X"11",X"3A",X"2C",X"98",X"FE",X"20",X"D8",X"21",X"19",X"22",X"CD", + X"C4",X"11",X"21",X"03",X"98",X"34",X"C9",X"21",X"03",X"98",X"34",X"11",X"27",X"03",X"FF",X"1C", + X"FF",X"1C",X"FF",X"1E",X"0F",X"FF",X"AF",X"21",X"00",X"9D",X"01",X"01",X"20",X"D7",X"21",X"00", + X"99",X"01",X"01",X"40",X"D7",X"21",X"90",X"9C",X"01",X"01",X"70",X"D7",X"21",X"2E",X"23",X"11", + X"00",X"9D",X"01",X"10",X"00",X"ED",X"B0",X"11",X"00",X"99",X"0E",X"10",X"ED",X"B0",X"11",X"54", + X"9A",X"CD",X"D7",X"22",X"CD",X"D7",X"22",X"3E",X"04",X"01",X"20",X"00",X"ED",X"A0",X"1C",X"0D", + X"3D",X"20",X"F9",X"EB",X"09",X"EB",X"C9",X"3E",X"C0",X"21",X"52",X"8D",X"11",X"20",X"00",X"06", + X"0C",X"77",X"19",X"10",X"FC",X"21",X"53",X"8D",X"06",X"0C",X"77",X"19",X"10",X"FC",X"01",X"03", + X"04",X"21",X"54",X"9A",X"E5",X"C5",X"7D",X"CD",X"CD",X"30",X"C1",X"E1",X"23",X"23",X"10",X"F4", + X"06",X"04",X"11",X"18",X"00",X"19",X"0D",X"20",X"EB",X"AF",X"32",X"08",X"98",X"21",X"01",X"00", + X"22",X"28",X"98",X"21",X"39",X"22",X"22",X"2A",X"98",X"21",X"03",X"98",X"34",X"C9",X"01",X"00", + X"80",X"38",X"80",X"30",X"18",X"74",X"00",X"02",X"00",X"00",X"D1",X"01",X"01",X"C1",X"00",X"00", + X"00",X"90",X"00",X"00",X"34",X"04",X"78",X"00",X"02",X"00",X"08",X"FF",X"00",X"00",X"02",X"03", + X"01",X"1C",X"03",X"0B",X"00",X"1D",X"01",X"02",X"08",X"22",X"CD",X"71",X"23",X"3A",X"07",X"98", + X"0F",X"DC",X"6E",X"32",X"CD",X"A7",X"34",X"CD",X"63",X"2E",X"CD",X"D1",X"1C",X"CD",X"7E",X"2A", + X"C9",X"21",X"28",X"98",X"35",X"28",X"57",X"7E",X"FE",X"12",X"C0",X"2C",X"7E",X"3D",X"F8",X"3A", + X"08",X"99",X"CD",X"27",X"24",X"3A",X"29",X"98",X"FE",X"10",X"38",X"1F",X"21",X"4E",X"24",X"CB", + X"67",X"28",X"03",X"21",X"53",X"24",X"46",X"23",X"4E",X"23",X"EB",X"09",X"EB",X"ED",X"A0",X"ED", + X"A0",X"CB",X"DA",X"3E",X"80",X"AE",X"1D",X"12",X"1D",X"12",X"C9",X"21",X"44",X"24",X"0F",X"38", + X"03",X"21",X"49",X"24",X"46",X"23",X"4E",X"23",X"EB",X"09",X"01",X"20",X"00",X"1A",X"77",X"09", + X"13",X"1A",X"77",X"13",X"CB",X"DC",X"1A",X"EE",X"80",X"77",X"ED",X"42",X"77",X"C9",X"3A",X"29", + X"98",X"FE",X"FF",X"28",X"40",X"EB",X"2A",X"2A",X"98",X"ED",X"A0",X"ED",X"A0",X"22",X"2A",X"98", + X"B7",X"C8",X"47",X"3A",X"2A",X"99",X"F6",X"28",X"6F",X"26",X"99",X"70",X"3E",X"01",X"AD",X"32", + X"2A",X"99",X"3A",X"08",X"99",X"CD",X"27",X"24",X"21",X"21",X"00",X"19",X"01",X"1F",X"00",X"3E", + X"FF",X"77",X"2C",X"77",X"09",X"77",X"2C",X"77",X"CB",X"DC",X"3E",X"80",X"77",X"2D",X"77",X"ED", + X"42",X"77",X"2D",X"77",X"C9",X"CD",X"F2",X"23",X"AF",X"32",X"00",X"9D",X"32",X"03",X"98",X"32", + X"2C",X"98",X"21",X"01",X"98",X"34",X"C9",X"3D",X"4F",X"E6",X"0F",X"47",X"A9",X"16",X"00",X"87", + X"CB",X"12",X"87",X"CB",X"12",X"80",X"80",X"5F",X"47",X"FE",X"0F",X"20",X"02",X"CB",X"EB",X"3E", + X"84",X"B2",X"57",X"C9",X"00",X"21",X"86",X"84",X"00",X"00",X"22",X"84",X"86",X"80",X"00",X"41", + X"87",X"85",X"80",X"00",X"21",X"85",X"87",X"00",X"3A",X"02",X"99",X"FE",X"0E",X"38",X"02",X"3E", + X"0A",X"C6",X"02",X"0F",X"0F",X"E6",X"03",X"C8",X"4F",X"06",X"0C",X"11",X"20",X"00",X"21",X"A2", + X"24",X"DD",X"21",X"40",X"9D",X"7E",X"32",X"80",X"9B",X"D9",X"CD",X"72",X"29",X"3A",X"80",X"9B", + X"B7",X"28",X"13",X"DD",X"E5",X"E1",X"CD",X"2A",X"28",X"CD",X"31",X"2C",X"38",X"08",X"D9",X"AF", + X"0D",X"28",X"0B",X"DD",X"19",X"D9",X"D9",X"23",X"10",X"DB",X"AF",X"DD",X"77",X"00",X"32",X"80", + X"9B",X"C9",X"01",X"0A",X"1B",X"11",X"03",X"19",X"09",X"13",X"02",X"0B",X"1A",X"12",X"3A",X"07", + X"9D",X"5F",X"16",X"9A",X"1A",X"E6",X"3F",X"C6",X"F0",X"FE",X"FC",X"D8",X"21",X"38",X"99",X"7E", + X"BB",X"28",X"07",X"73",X"2C",X"36",X"00",X"C3",X"44",X"20",X"2C",X"34",X"7E",X"FE",X"03",X"CA", + X"3F",X"20",X"FE",X"04",X"D8",X"36",X"00",X"C3",X"B6",X"2D",X"3A",X"08",X"9D",X"21",X"E3",X"24", + X"E7",X"6E",X"C9",X"03",X"03",X"03",X"03",X"02",X"02",X"01",X"01",X"01",X"01",X"02",X"02",X"AF", + X"32",X"01",X"9D",X"3A",X"07",X"9D",X"6F",X"26",X"9A",X"7E",X"EB",X"E6",X"3F",X"6F",X"C6",X"F0", + X"FE",X"FC",X"D4",X"DA",X"24",X"26",X"00",X"29",X"29",X"29",X"01",X"3C",X"45",X"09",X"3A",X"09", + X"9D",X"FE",X"04",X"20",X"07",X"3A",X"08",X"9D",X"E6",X"03",X"EE",X"02",X"47",X"EE",X"02",X"87", + X"E7",X"7E",X"FE",X"04",X"20",X"01",X"78",X"EE",X"02",X"87",X"21",X"E0",X"25",X"E7",X"4E",X"23", + X"46",X"7B",X"E6",X"F0",X"6F",X"AB",X"87",X"87",X"87",X"87",X"67",X"09",X"22",X"02",X"9D",X"22", + X"04",X"9D",X"3A",X"07",X"9D",X"2A",X"08",X"9D",X"22",X"28",X"98",X"32",X"2A",X"98",X"7D",X"C6", + X"F0",X"FE",X"FC",X"30",X"04",X"CD",X"24",X"26",X"D8",X"AF",X"32",X"2C",X"98",X"3A",X"07",X"9D", + X"6F",X"26",X"9A",X"7E",X"B7",X"28",X"5F",X"FE",X"0B",X"28",X"5B",X"CB",X"6F",X"20",X"57",X"C6", + X"F0",X"FE",X"FC",X"30",X"51",X"7D",X"32",X"07",X"9D",X"7E",X"E6",X"3F",X"EB",X"6F",X"26",X"00", + X"29",X"29",X"29",X"01",X"3B",X"45",X"09",X"06",X"00",X"7E",X"C6",X"F0",X"FE",X"FC",X"38",X"06", + X"04",X"23",X"23",X"C3",X"89",X"25",X"78",X"FE",X"04",X"30",X"25",X"4E",X"23",X"46",X"ED",X"43", + X"08",X"9D",X"87",X"21",X"E0",X"25",X"E7",X"4E",X"23",X"46",X"7B",X"E6",X"F0",X"6F",X"AB",X"87", + X"87",X"87",X"87",X"67",X"09",X"22",X"02",X"9D",X"22",X"04",X"9D",X"AF",X"32",X"06",X"9D",X"C9", + X"3A",X"07",X"9D",X"6F",X"26",X"9A",X"D9",X"21",X"2C",X"98",X"7E",X"34",X"E6",X"07",X"21",X"D8", + X"25",X"E7",X"7E",X"D9",X"85",X"C3",X"60",X"25",X"02",X"DE",X"1E",X"22",X"C2",X"FC",X"40",X"24", + X"10",X"10",X"20",X"00",X"10",X"F0",X"00",X"00",X"3A",X"07",X"9D",X"2A",X"08",X"9D",X"22",X"28", + X"98",X"32",X"2A",X"98",X"7D",X"FE",X"0C",X"30",X"09",X"CD",X"24",X"26",X"30",X"04",X"CD",X"24", + X"26",X"D8",X"3A",X"07",X"9D",X"6F",X"26",X"9A",X"4E",X"EB",X"21",X"00",X"9A",X"3E",X"03",X"06", + X"00",X"BE",X"28",X"07",X"2C",X"10",X"FA",X"3D",X"20",X"F5",X"C9",X"71",X"12",X"CD",X"0E",X"14", + X"C9",X"C3",X"E8",X"25",X"ED",X"4B",X"29",X"98",X"79",X"21",X"83",X"35",X"E7",X"7E",X"80",X"32", + X"2A",X"98",X"6F",X"26",X"9A",X"7E",X"E6",X"3F",X"6F",X"C6",X"F0",X"FE",X"FC",X"30",X"25",X"26", + X"00",X"29",X"29",X"29",X"11",X"3B",X"45",X"19",X"79",X"FE",X"04",X"20",X"07",X"3A",X"28",X"98", + X"E6",X"03",X"EE",X"02",X"57",X"87",X"E7",X"4E",X"23",X"46",X"ED",X"43",X"28",X"98",X"3E",X"F0", + X"81",X"FE",X"FC",X"C9",X"37",X"C9",X"21",X"00",X"00",X"54",X"06",X"08",X"0F",X"30",X"01",X"19", + X"CB",X"23",X"CB",X"12",X"10",X"F6",X"C9",X"87",X"5F",X"16",X"00",X"30",X"01",X"14",X"21",X"7A", + X"4D",X"19",X"7E",X"C9",X"87",X"3C",X"5F",X"16",X"00",X"30",X"01",X"14",X"21",X"7A",X"4D",X"19", + X"7E",X"C9",X"DD",X"66",X"06",X"3A",X"03",X"99",X"57",X"AF",X"06",X"80",X"5F",X"6F",X"ED",X"52", + X"D0",X"19",X"CB",X"3A",X"CB",X"1B",X"ED",X"52",X"30",X"02",X"B0",X"19",X"CB",X"38",X"30",X"F2", + X"2F",X"37",X"C9",X"87",X"5F",X"16",X"00",X"30",X"01",X"14",X"21",X"7A",X"4D",X"19",X"5E",X"23", + X"56",X"63",X"7C",X"AA",X"E6",X"01",X"4F",X"CD",X"99",X"26",X"E6",X"FE",X"B1",X"C9",X"21",X"80", + X"9B",X"7E",X"B7",X"28",X"09",X"2C",X"7E",X"CF",X"4A",X"29",X"1F",X"27",X"6A",X"27",X"3A",X"07", + X"98",X"E6",X"0F",X"C0",X"21",X"89",X"9B",X"DF",X"C0",X"CD",X"8F",X"01",X"E6",X"1B",X"6F",X"26", + X"00",X"22",X"80",X"9B",X"C9",X"1E",X"F3",X"3A",X"02",X"99",X"FE",X"08",X"38",X"04",X"87",X"2F", + X"83",X"5F",X"3A",X"82",X"9B",X"B7",X"C8",X"CD",X"66",X"26",X"7C",X"32",X"82",X"9B",X"B7",X"CA", + X"99",X"27",X"FE",X"0A",X"CA",X"5F",X"20",X"C6",X"D8",X"FE",X"FC",X"D8",X"C3",X"5A",X"20",X"CD", + X"9A",X"28",X"3A",X"07",X"98",X"E6",X"1F",X"CC",X"F5",X"26",X"ED",X"4B",X"85",X"9B",X"ED",X"5B", + X"02",X"9D",X"78",X"92",X"C6",X"05",X"FE",X"0B",X"D0",X"79",X"93",X"C6",X"05",X"FE",X"0B",X"D0", + X"3A",X"82",X"9B",X"CD",X"31",X"29",X"78",X"87",X"87",X"87",X"87",X"81",X"47",X"7A",X"87",X"87", + X"87",X"87",X"4F",X"ED",X"43",X"C9",X"99",X"AF",X"32",X"CB",X"99",X"11",X"00",X"01",X"FF",X"21", + X"81",X"9B",X"34",X"2D",X"36",X"40",X"CD",X"64",X"20",X"C9",X"21",X"80",X"9B",X"35",X"C2",X"9A", + X"28",X"21",X"0D",X"99",X"7E",X"34",X"FE",X"07",X"38",X"02",X"3E",X"07",X"21",X"91",X"27",X"E7", + X"7E",X"32",X"89",X"9B",X"CD",X"64",X"28",X"21",X"00",X"00",X"22",X"80",X"9B",X"CD",X"64",X"20", + X"C9",X"30",X"20",X"18",X"14",X"10",X"0C",X"0A",X"08",X"E1",X"21",X"71",X"27",X"E5",X"CD",X"8F", + X"01",X"E6",X"03",X"28",X"0F",X"06",X"04",X"11",X"20",X"00",X"21",X"40",X"9D",X"7E",X"B7",X"28", + X"79",X"19",X"10",X"F9",X"CD",X"69",X"20",X"3A",X"88",X"9B",X"6F",X"26",X"9A",X"3E",X"01",X"32", + X"94",X"9C",X"7E",X"08",X"7E",X"0F",X"E6",X"03",X"20",X"02",X"3E",X"04",X"C6",X"20",X"77",X"08", + X"EB",X"21",X"09",X"99",X"34",X"E6",X"1F",X"FE",X"18",X"38",X"13",X"2C",X"35",X"20",X"0F",X"F5", + X"D9",X"AF",X"32",X"2C",X"98",X"01",X"08",X"C0",X"ED",X"43",X"01",X"98",X"D9",X"F1",X"E6",X"07", + X"87",X"21",X"D3",X"36",X"E7",X"7E",X"83",X"4F",X"42",X"08",X"02",X"16",X"07",X"FF",X"43",X"59", + X"FF",X"60",X"69",X"DD",X"21",X"00",X"9D",X"06",X"06",X"11",X"20",X"00",X"DD",X"7E",X"00",X"0F", + X"30",X"0B",X"DD",X"7E",X"07",X"BC",X"CC",X"22",X"28",X"BD",X"CC",X"22",X"28",X"DD",X"19",X"10", + X"EB",X"C9",X"DD",X"34",X"00",X"DD",X"36",X"01",X"04",X"C9",X"3E",X"01",X"77",X"2C",X"77",X"2C", + X"ED",X"4B",X"85",X"9B",X"71",X"2C",X"70",X"2C",X"71",X"2C",X"70",X"2C",X"36",X"F0",X"2C",X"3A", + X"87",X"9B",X"57",X"78",X"0F",X"0F",X"0F",X"0F",X"B1",X"CB",X"4A",X"20",X"02",X"D6",X"11",X"77", + X"2C",X"36",X"00",X"2C",X"7A",X"FE",X"02",X"3E",X"01",X"30",X"01",X"3C",X"77",X"CB",X"D5",X"36", + X"02",X"C3",X"7D",X"20",X"3A",X"87",X"9B",X"CF",X"70",X"28",X"70",X"28",X"87",X"28",X"87",X"28", + X"2A",X"85",X"9B",X"11",X"F0",X"EF",X"19",X"7C",X"0F",X"0F",X"0F",X"0F",X"85",X"F5",X"C6",X"02", + X"CD",X"CD",X"30",X"F1",X"C3",X"CD",X"30",X"2A",X"85",X"9B",X"7C",X"0F",X"0F",X"0F",X"0F",X"85", + X"F5",X"D6",X"20",X"CD",X"CD",X"30",X"F1",X"C3",X"CD",X"30",X"3A",X"81",X"9B",X"B7",X"C8",X"01", + X"18",X"00",X"FE",X"02",X"28",X"18",X"3A",X"82",X"9B",X"FE",X"28",X"30",X"02",X"0E",X"0C",X"FE", + X"0A",X"30",X"02",X"0E",X"04",X"3A",X"07",X"98",X"2F",X"A1",X"20",X"02",X"06",X"04",X"3A",X"87", + X"9B",X"80",X"CF",X"F7",X"28",X"F7",X"28",X"15",X"29",X"15",X"29",X"D3",X"28",X"D3",X"28",X"D9", + X"28",X"D9",X"28",X"11",X"FF",X"FF",X"C3",X"DC",X"28",X"11",X"20",X"00",X"2A",X"83",X"9B",X"3E", + X"10",X"CD",X"F0",X"28",X"7A",X"2F",X"57",X"7B",X"2F",X"5F",X"13",X"19",X"3E",X"88",X"CB",X"DC", + X"06",X"04",X"77",X"19",X"10",X"FC",X"C9",X"3A",X"82",X"9B",X"CD",X"31",X"29",X"2A",X"83",X"9B", + X"1E",X"2C",X"78",X"83",X"77",X"2D",X"79",X"83",X"77",X"2D",X"7A",X"83",X"77",X"2D",X"73",X"11", + X"01",X"00",X"C3",X"EC",X"28",X"3A",X"82",X"9B",X"CD",X"31",X"29",X"2A",X"83",X"9B",X"1E",X"20", + X"7B",X"70",X"E7",X"71",X"7B",X"E7",X"72",X"7B",X"E7",X"36",X"00",X"11",X"E0",X"FF",X"C3",X"EC", + X"28",X"01",X"00",X"00",X"D6",X"64",X"38",X"04",X"04",X"C3",X"34",X"29",X"C6",X"64",X"D6",X"0A", + X"38",X"04",X"0C",X"C3",X"3E",X"29",X"C6",X"0A",X"57",X"C9",X"CD",X"72",X"29",X"11",X"FF",X"80", + X"E6",X"08",X"20",X"0C",X"D9",X"CD",X"8F",X"01",X"D9",X"E6",X"07",X"20",X"4B",X"11",X"3F",X"30", + X"D9",X"CD",X"8F",X"01",X"D9",X"A3",X"B2",X"32",X"82",X"9B",X"21",X"81",X"9B",X"34",X"CD",X"7D", + X"20",X"C9",X"CD",X"DA",X"29",X"38",X"31",X"22",X"83",X"9B",X"3A",X"80",X"9B",X"E6",X"18",X"0F", + X"0F",X"0F",X"32",X"87",X"9B",X"CD",X"AD",X"29",X"3A",X"87",X"9B",X"ED",X"4B",X"85",X"9B",X"57", + X"78",X"0F",X"0F",X"0F",X"0F",X"B1",X"CB",X"4A",X"20",X"02",X"D6",X"11",X"6F",X"26",X"9A",X"32", + X"88",X"9B",X"7E",X"E6",X"18",X"28",X"01",X"C9",X"AF",X"32",X"80",X"9B",X"C9",X"3A",X"87",X"9B", + X"87",X"21",X"D2",X"29",X"E7",X"5E",X"23",X"56",X"2A",X"83",X"9B",X"19",X"7D",X"87",X"87",X"87", + X"E6",X"F8",X"57",X"7D",X"CB",X"1C",X"1F",X"CB",X"1C",X"1F",X"E6",X"F8",X"5F",X"ED",X"53",X"85", + X"9B",X"C9",X"DF",X"FF",X"3F",X"00",X"3F",X"00",X"42",X"00",X"3A",X"80",X"9B",X"CB",X"67",X"20", + X"38",X"0E",X"00",X"61",X"CB",X"5F",X"20",X"01",X"0C",X"E6",X"07",X"28",X"2A",X"87",X"47",X"3A", + X"06",X"99",X"57",X"E6",X"F0",X"6F",X"AA",X"B8",X"D8",X"87",X"C6",X"13",X"CB",X"20",X"CB",X"20", + X"90",X"47",X"29",X"29",X"CB",X"E5",X"EB",X"21",X"F0",X"85",X"CB",X"41",X"28",X"05",X"ED",X"52", + X"78",X"E7",X"C9",X"19",X"78",X"E7",X"C9",X"37",X"C9",X"0E",X"00",X"61",X"CB",X"5F",X"20",X"01", + X"0C",X"E6",X"07",X"28",X"F2",X"47",X"3A",X"06",X"99",X"57",X"E6",X"F0",X"6F",X"AA",X"87",X"CB", + X"41",X"28",X"01",X"2F",X"C6",X"0E",X"4F",X"29",X"29",X"54",X"5D",X"29",X"7C",X"B8",X"D8",X"21", + X"40",X"85",X"ED",X"52",X"78",X"84",X"67",X"06",X"00",X"09",X"C9",X"3E",X"C0",X"06",X"04",X"11", + X"20",X"00",X"CB",X"DC",X"77",X"19",X"10",X"FC",X"C9",X"21",X"94",X"9C",X"7E",X"B7",X"C8",X"34", + X"3D",X"CA",X"4D",X"2E",X"3D",X"28",X"0A",X"D6",X"04",X"C0",X"77",X"3E",X"10",X"32",X"98",X"9C", + X"C9",X"AF",X"32",X"98",X"9C",X"32",X"93",X"9C",X"3E",X"10",X"32",X"9C",X"9C",X"C9",X"3A",X"07", + X"98",X"E6",X"03",X"C0",X"3A",X"9D",X"9C",X"B7",X"C0",X"21",X"98",X"9C",X"7E",X"B7",X"C0",X"21", + X"93",X"9C",X"7E",X"B7",X"FA",X"D5",X"2A",X"C8",X"3A",X"34",X"99",X"B7",X"C0",X"36",X"A1",X"CD", + X"4D",X"2E",X"3A",X"90",X"9C",X"47",X"3A",X"07",X"9D",X"B8",X"20",X"6F",X"3A",X"92",X"9C",X"32", + X"99",X"9C",X"3A",X"A0",X"9C",X"6F",X"26",X"9A",X"3A",X"91",X"9C",X"47",X"AE",X"E6",X"3F",X"28", + X"0F",X"78",X"E6",X"3F",X"C6",X"F0",X"FE",X"FC",X"38",X"50",X"78",X"AE",X"E6",X"3C",X"20",X"4A", + X"70",X"7D",X"C3",X"CD",X"30",X"34",X"6F",X"7E",X"B7",X"28",X"3A",X"5F",X"16",X"9A",X"1A",X"E6", + X"3F",X"6F",X"C6",X"F0",X"FE",X"FC",X"30",X"23",X"26",X"00",X"29",X"29",X"E5",X"29",X"01",X"3C", + X"45",X"09",X"3A",X"99",X"9C",X"4F",X"87",X"E7",X"7E",X"32",X"99",X"9C",X"E1",X"06",X"00",X"09", + X"01",X"63",X"46",X"09",X"1A",X"B6",X"12",X"7B",X"C3",X"CD",X"30",X"3A",X"99",X"9C",X"C6",X"4C", + X"12",X"7B",X"CD",X"CD",X"30",X"AF",X"32",X"93",X"9C",X"C9",X"00",X"AF",X"32",X"93",X"9C",X"3E", + X"10",X"32",X"98",X"9C",X"C9",X"3A",X"09",X"9D",X"EE",X"02",X"C6",X"4C",X"77",X"32",X"91",X"9C", + X"C3",X"78",X"20",X"21",X"98",X"9C",X"7E",X"B7",X"C8",X"FA",X"9B",X"2B",X"3A",X"00",X"9D",X"0F", + X"D0",X"3A",X"34",X"99",X"B7",X"C0",X"3E",X"10",X"32",X"93",X"9C",X"36",X"A0",X"2C",X"3A",X"09", + X"9D",X"77",X"32",X"92",X"9C",X"2C",X"36",X"00",X"EE",X"02",X"47",X"3A",X"07",X"9D",X"32",X"A0", + X"9C",X"32",X"90",X"9C",X"6F",X"26",X"9A",X"7E",X"E6",X"3F",X"C6",X"F0",X"FE",X"FC",X"30",X"B5", + X"7E",X"EB",X"87",X"87",X"21",X"63",X"46",X"80",X"E7",X"7E",X"EB",X"B6",X"77",X"32",X"91",X"9C", + X"7D",X"C9",X"6F",X"26",X"9A",X"7E",X"22",X"96",X"9C",X"32",X"95",X"9C",X"7D",X"CD",X"CD",X"30", + X"2A",X"96",X"9C",X"3A",X"95",X"9C",X"BE",X"C8",X"C3",X"85",X"2B",X"5E",X"34",X"3A",X"99",X"9C", + X"21",X"83",X"35",X"E7",X"16",X"9C",X"1A",X"86",X"13",X"12",X"5F",X"16",X"9A",X"1A",X"E6",X"3F", + X"6F",X"C6",X"F0",X"FE",X"FC",X"30",X"4C",X"26",X"00",X"29",X"29",X"E5",X"29",X"01",X"3B",X"45", + X"09",X"3A",X"99",X"9C",X"4F",X"87",X"E7",X"7E",X"C6",X"F0",X"FE",X"FC",X"30",X"2A",X"23",X"7E", + X"32",X"99",X"9C",X"E1",X"06",X"00",X"09",X"01",X"63",X"46",X"09",X"1A",X"B6",X"EB",X"BE",X"20", + X"14",X"3A",X"A0",X"9C",X"BD",X"20",X"0F",X"21",X"98",X"9C",X"5E",X"16",X"9C",X"AF",X"12",X"77", + X"2C",X"2C",X"36",X"01",X"C9",X"77",X"7D",X"C9",X"E1",X"21",X"98",X"9C",X"5E",X"16",X"9C",X"AF", + X"12",X"77",X"C9",X"1A",X"FE",X"40",X"38",X"1E",X"21",X"38",X"99",X"7B",X"BE",X"20",X"13",X"2C", + X"34",X"7E",X"D6",X"03",X"38",X"10",X"01",X"3F",X"20",X"28",X"03",X"01",X"B6",X"2D",X"C5",X"28", + X"05",X"2D",X"73",X"2C",X"36",X"00",X"3A",X"99",X"9C",X"C6",X"4C",X"12",X"AF",X"32",X"98",X"9C", + X"C9",X"3A",X"07",X"9D",X"47",X"DD",X"7E",X"07",X"B8",X"28",X"4A",X"DD",X"66",X"09",X"32",X"30", + X"98",X"22",X"31",X"98",X"CD",X"56",X"2C",X"D8",X"C6",X"F0",X"FE",X"FC",X"D0",X"CD",X"56",X"2C", + X"D8",X"C6",X"F0",X"FE",X"FC",X"D0",X"3A",X"32",X"98",X"21",X"83",X"35",X"E7",X"3A",X"30",X"98", + X"86",X"32",X"30",X"98",X"B8",X"28",X"1E",X"6F",X"26",X"9A",X"7E",X"E6",X"3F",X"6F",X"26",X"00", + X"29",X"29",X"29",X"11",X"3B",X"45",X"19",X"3A",X"32",X"98",X"87",X"E7",X"7E",X"23",X"4E",X"ED", + X"43",X"32",X"98",X"B7",X"C9",X"37",X"C9",X"21",X"9D",X"9C",X"7E",X"B7",X"C8",X"3A",X"9A",X"9C", + X"B7",X"20",X"51",X"21",X"A0",X"9C",X"7E",X"B7",X"28",X"45",X"5F",X"16",X"9A",X"1A",X"87",X"87", + X"47",X"3A",X"9E",X"9C",X"EE",X"02",X"80",X"21",X"63",X"46",X"E7",X"7E",X"2F",X"EB",X"A6",X"77", + X"7D",X"CD",X"82",X"2B",X"21",X"98",X"9C",X"DF",X"2E",X"9C",X"DF",X"2E",X"93",X"DF",X"21",X"A0", + X"9C",X"11",X"9F",X"9C",X"01",X"60",X"00",X"ED",X"B0",X"EB",X"70",X"3A",X"9B",X"9C",X"FE",X"04", + X"30",X"02",X"3E",X"04",X"32",X"9B",X"9C",X"3A",X"39",X"99",X"FE",X"03",X"C4",X"44",X"20",X"21", + X"9D",X"9C",X"35",X"C9",X"21",X"98",X"9C",X"DF",X"2E",X"9C",X"DF",X"2E",X"93",X"DF",X"21",X"A0", + X"9C",X"11",X"9F",X"9C",X"ED",X"A0",X"1A",X"08",X"ED",X"A0",X"7E",X"B7",X"20",X"FA",X"08",X"12", + X"21",X"9D",X"9C",X"35",X"21",X"9B",X"9C",X"DF",X"CA",X"98",X"2D",X"7E",X"FE",X"03",X"C0",X"CD", + X"3F",X"20",X"3A",X"20",X"9D",X"B7",X"C0",X"ED",X"4B",X"A3",X"9C",X"78",X"B7",X"20",X"04",X"3A", + X"A0",X"9C",X"47",X"91",X"38",X"17",X"D6",X"02",X"20",X"08",X"0E",X"02",X"11",X"10",X"F0",X"C3", + X"51",X"2D",X"D6",X"1E",X"C0",X"0E",X"03",X"11",X"00",X"00",X"C3",X"51",X"2D",X"C6",X"02",X"20", + X"08",X"0E",X"00",X"11",X"10",X"10",X"C3",X"51",X"2D",X"C6",X"1E",X"C0",X"0E",X"01",X"11",X"20", + X"00",X"78",X"E6",X"F0",X"6F",X"A8",X"87",X"87",X"87",X"87",X"67",X"19",X"22",X"22",X"9D",X"22", + X"24",X"9D",X"ED",X"43",X"26",X"9D",X"68",X"26",X"9A",X"7E",X"E6",X"3F",X"6F",X"26",X"00",X"29", + X"29",X"29",X"11",X"3B",X"45",X"19",X"79",X"87",X"E7",X"5E",X"23",X"56",X"ED",X"53",X"28",X"9D", + X"21",X"8F",X"34",X"22",X"2A",X"9D",X"21",X"02",X"01",X"22",X"20",X"9D",X"21",X"D4",X"07",X"22", + X"2C",X"9D",X"3E",X"01",X"32",X"2E",X"9D",X"C9",X"3A",X"20",X"9D",X"0F",X"30",X"12",X"21",X"A0", + X"9C",X"06",X"60",X"3A",X"27",X"9D",X"4F",X"7E",X"B7",X"28",X"05",X"B9",X"C8",X"2C",X"10",X"F7", + X"3A",X"0C",X"99",X"32",X"9B",X"9C",X"ED",X"4B",X"A0",X"9C",X"78",X"91",X"38",X"17",X"D6",X"02", + X"20",X"08",X"0E",X"02",X"11",X"10",X"F0",X"C3",X"E9",X"2D",X"D6",X"1E",X"C0",X"0E",X"03",X"11", + X"00",X"00",X"C3",X"E9",X"2D",X"C6",X"02",X"20",X"08",X"0E",X"00",X"11",X"10",X"10",X"C3",X"E9", + X"2D",X"C6",X"1E",X"C0",X"0E",X"01",X"11",X"20",X"00",X"78",X"E6",X"F0",X"6F",X"A8",X"87",X"87", + X"87",X"87",X"67",X"19",X"22",X"22",X"9D",X"22",X"24",X"9D",X"ED",X"43",X"26",X"9D",X"68",X"26", + X"9A",X"7E",X"E6",X"3F",X"6F",X"26",X"00",X"29",X"29",X"29",X"11",X"3B",X"45",X"19",X"79",X"87", + X"E7",X"5E",X"23",X"56",X"ED",X"53",X"28",X"9D",X"21",X"8F",X"34",X"22",X"2A",X"9D",X"21",X"01", + X"03",X"22",X"20",X"9D",X"3E",X"01",X"32",X"2E",X"9D",X"CD",X"44",X"20",X"C3",X"49",X"20",X"21", + X"9C",X"9C",X"7E",X"B7",X"C8",X"FA",X"3A",X"2E",X"36",X"9F",X"34",X"6E",X"7E",X"B7",X"C8",X"36", + X"00",X"5F",X"16",X"9A",X"1A",X"B7",X"C8",X"7B",X"C3",X"82",X"2B",X"77",X"C9",X"AF",X"32",X"98", + X"9C",X"06",X"3F",X"26",X"9A",X"11",X"A0",X"9C",X"1A",X"B7",X"C8",X"6F",X"7E",X"A0",X"77",X"1C", + X"20",X"F6",X"C9",X"DD",X"21",X"00",X"9E",X"3A",X"00",X"9E",X"B7",X"28",X"08",X"3A",X"01",X"9E", + X"CF",X"75",X"2E",X"C2",X"2E",X"21",X"1F",X"9E",X"DF",X"C0",X"C9",X"DD",X"21",X"00",X"9E",X"DD", + X"36",X"00",X"01",X"DD",X"36",X"01",X"01",X"3A",X"0C",X"9D",X"D6",X"C0",X"0F",X"0F",X"E6",X"0F", + X"21",X"B4",X"30",X"E7",X"11",X"74",X"30",X"3A",X"0E",X"98",X"B7",X"28",X"03",X"11",X"94",X"30", + X"7E",X"DD",X"77",X"04",X"EB",X"E7",X"11",X"1A",X"9E",X"01",X"06",X"00",X"ED",X"B0",X"56",X"23", + X"5E",X"2A",X"02",X"9D",X"19",X"22",X"02",X"9E",X"AF",X"DD",X"77",X"05",X"3C",X"DD",X"77",X"06", + X"C9",X"C9",X"DD",X"35",X"06",X"C0",X"06",X"06",X"DD",X"70",X"06",X"D9",X"DD",X"34",X"05",X"DD", + X"7E",X"05",X"21",X"11",X"2F",X"E7",X"7E",X"B7",X"FA",X"0D",X"2F",X"87",X"87",X"4F",X"87",X"81", + X"4F",X"06",X"00",X"DD",X"7E",X"04",X"0F",X"0F",X"21",X"1C",X"2F",X"E7",X"5E",X"23",X"56",X"EB", + X"09",X"ED",X"4B",X"02",X"9E",X"11",X"0E",X"9E",X"CD",X"FF",X"2E",X"3A",X"03",X"9E",X"4F",X"06", + X"06",X"7E",X"FE",X"FF",X"28",X"01",X"81",X"12",X"23",X"1C",X"10",X"F5",X"C9",X"DD",X"36",X"00", + X"00",X"C9",X"00",X"01",X"02",X"03",X"02",X"03",X"04",X"05",X"06",X"FF",X"24",X"2F",X"78",X"2F", + X"CC",X"2F",X"20",X"30",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"FF",X"FF",X"FF",X"FF",X"FF", + X"00",X"02",X"FF",X"FF",X"00",X"02",X"00",X"00",X"FF",X"FF",X"FD",X"FD",X"00",X"03",X"00",X"03", + X"00",X"03",X"00",X"00",X"FD",X"FD",X"FA",X"FA",X"00",X"04",X"00",X"04",X"00",X"04",X"00",X"00", + X"FC",X"FC",X"F8",X"F8",X"01",X"04",X"01",X"04",X"01",X"04",X"FE",X"FE",X"FB",X"FB",X"F8",X"F8", + X"02",X"04",X"FF",X"FF",X"02",X"04",X"FC",X"FC",X"FF",X"FF",X"F9",X"F9",X"03",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FA",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"FF", + X"FF",X"FF",X"FF",X"FF",X"00",X"02",X"FF",X"FF",X"00",X"02",X"00",X"00",X"FF",X"FF",X"03",X"03", + X"00",X"03",X"00",X"03",X"00",X"03",X"00",X"00",X"03",X"03",X"06",X"06",X"00",X"04",X"00",X"04", + X"00",X"04",X"00",X"00",X"04",X"04",X"08",X"08",X"01",X"04",X"01",X"04",X"01",X"04",X"02",X"02", + X"05",X"05",X"08",X"08",X"02",X"04",X"FF",X"FF",X"02",X"04",X"04",X"04",X"FF",X"FF",X"07",X"07", + X"03",X"FF",X"FF",X"FF",X"FF",X"FF",X"06",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"FF",X"FF",X"FF", + X"FF",X"FF",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"FF",X"FF",X"FD",X"FD",X"00",X"02", + X"FF",X"FF",X"00",X"02",X"00",X"00",X"FD",X"FD",X"FA",X"FA",X"00",X"03",X"00",X"03",X"00",X"03", + X"00",X"00",X"FC",X"FC",X"F8",X"F8",X"00",X"04",X"00",X"04",X"00",X"04",X"FE",X"FE",X"FB",X"FB", + X"F8",X"F8",X"01",X"04",X"01",X"04",X"01",X"04",X"FC",X"FC",X"FF",X"FF",X"F9",X"F9",X"02",X"04", + X"02",X"04",X"02",X"04",X"FA",X"FF",X"FF",X"FF",X"FF",X"FF",X"03",X"FF",X"FF",X"FF",X"FF",X"FF", + X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"FF",X"FF", + X"03",X"03",X"00",X"02",X"FF",X"FF",X"00",X"02",X"00",X"00",X"03",X"03",X"06",X"06",X"00",X"03", + X"00",X"03",X"00",X"03",X"00",X"00",X"04",X"04",X"08",X"08",X"00",X"04",X"00",X"04",X"00",X"04", + X"02",X"02",X"05",X"05",X"08",X"08",X"01",X"04",X"01",X"04",X"01",X"04",X"04",X"04",X"FF",X"FF", + X"07",X"07",X"02",X"04",X"02",X"04",X"02",X"04",X"06",X"FF",X"FF",X"FF",X"FF",X"FF",X"03",X"FF", + X"FF",X"FF",X"FF",X"FF",X"0B",X"0E",X"0C",X"0D",X"0C",X"0A",X"07",X"06",X"09",X"0A",X"0C",X"0D", + X"0C",X"0E",X"FE",X"08",X"0F",X"0E",X"0F",X"0D",X"0C",X"0B",X"0B",X"03",X"0A",X"09",X"0F",X"0D", + X"0A",X"0E",X"0B",X"FA",X"0E",X"0C",X"0A",X"0D",X"0E",X"09",X"06",X"08",X"0A",X"09",X"0E",X"0F", + X"0A",X"0C",X"FC",X"07",X"0E",X"08",X"0F",X"0A",X"0E",X"0A",X"07",X"05",X"09",X"0A",X"0E",X"0A", + X"09",X"0B",X"08",X"FA",X"10",X"10",X"10",X"10",X"00",X"00",X"00",X"00",X"18",X"18",X"18",X"18", + X"08",X"08",X"08",X"08",X"11",X"FE",X"83",X"3A",X"00",X"9A",X"C3",X"F0",X"30",X"B7",X"28",X"F4", + X"6F",X"26",X"9A",X"3D",X"4F",X"E6",X"0F",X"47",X"A9",X"16",X"00",X"87",X"CB",X"12",X"87",X"CB", + X"12",X"80",X"80",X"5F",X"78",X"FE",X"0F",X"20",X"02",X"CB",X"EB",X"3E",X"84",X"B2",X"57",X"7E", + X"6F",X"26",X"00",X"29",X"29",X"7C",X"E5",X"87",X"21",X"73",X"3C",X"E7",X"4E",X"23",X"46",X"E1", + X"29",X"29",X"3E",X"03",X"A4",X"20",X"21",X"29",X"09",X"3E",X"04",X"CD",X"16",X"31",X"EB",X"01", + X"80",X"07",X"09",X"EB",X"3E",X"04",X"ED",X"A0",X"ED",X"A0",X"ED",X"A0",X"ED",X"A0",X"EB",X"01", + X"1C",X"00",X"09",X"EB",X"3D",X"20",X"EF",X"C9",X"3D",X"28",X"3A",X"7D",X"B7",X"28",X"06",X"2E", + X"00",X"87",X"C3",X"66",X"31",X"29",X"09",X"13",X"13",X"23",X"23",X"CB",X"63",X"28",X"04",X"1B", + X"1B",X"2B",X"2B",X"CB",X"4A",X"20",X"0A",X"01",X"08",X"00",X"09",X"EB",X"01",X"40",X"00",X"09", + X"EB",X"3E",X"02",X"CD",X"A8",X"31",X"01",X"08",X"00",X"09",X"EB",X"01",X"C0",X"07",X"09",X"EB", + X"3E",X"02",X"C3",X"A8",X"31",X"7D",X"29",X"09",X"D9",X"07",X"07",X"07",X"E6",X"03",X"CF",X"77", + X"31",X"96",X"31",X"9A",X"31",X"B8",X"31",X"D9",X"01",X"08",X"00",X"09",X"01",X"40",X"00",X"EB", + X"09",X"EB",X"3E",X"02",X"CD",X"16",X"31",X"01",X"08",X"00",X"09",X"EB",X"01",X"C0",X"07",X"09", + X"EB",X"3E",X"02",X"C3",X"16",X"31",X"D9",X"C3",X"82",X"31",X"D9",X"3E",X"04",X"CD",X"A8",X"31", + X"EB",X"01",X"80",X"07",X"09",X"EB",X"3E",X"04",X"ED",X"A0",X"ED",X"A0",X"23",X"23",X"EB",X"01", + X"1E",X"00",X"09",X"EB",X"3D",X"20",X"F1",X"C9",X"D9",X"23",X"23",X"13",X"13",X"C3",X"9B",X"31", + X"3A",X"35",X"99",X"CB",X"4F",X"0E",X"05",X"20",X"01",X"0D",X"21",X"2C",X"99",X"06",X"04",X"D9", + X"21",X"07",X"9D",X"11",X"20",X"00",X"06",X"06",X"3A",X"36",X"99",X"4F",X"3A",X"08",X"99",X"BE", + X"20",X"0B",X"08",X"71",X"7D",X"D9",X"91",X"77",X"2C",X"05",X"C8",X"D9",X"08",X"19",X"10",X"EF", + X"D9",X"36",X"00",X"C9",X"3A",X"08",X"99",X"5F",X"D6",X"02",X"0E",X"01",X"C3",X"41",X"32",X"3A", + X"08",X"99",X"5F",X"D6",X"20",X"0E",X"02",X"C3",X"41",X"32",X"3A",X"08",X"99",X"5F",X"C6",X"20", + X"0E",X"03",X"C3",X"41",X"32",X"3A",X"2B",X"99",X"F6",X"28",X"6F",X"26",X"99",X"7E",X"B7",X"C8", + X"36",X"00",X"08",X"7D",X"EE",X"01",X"32",X"2B",X"99",X"08",X"0F",X"38",X"C7",X"0F",X"38",X"09", + X"0F",X"0F",X"0F",X"38",X"CA",X"0F",X"38",X"D2",X"C9",X"3A",X"08",X"99",X"5F",X"C6",X"02",X"0E", + X"00",X"6F",X"26",X"9A",X"54",X"7E",X"E6",X"3F",X"FE",X"10",X"D0",X"32",X"37",X"99",X"3E",X"01", + X"32",X"94",X"9C",X"D9",X"CD",X"4D",X"2E",X"D9",X"36",X"00",X"43",X"ED",X"43",X"35",X"99",X"7D", + X"32",X"08",X"99",X"CD",X"87",X"20",X"CD",X"C0",X"31",X"3E",X"04",X"C3",X"74",X"32",X"3A",X"34", + X"99",X"B7",X"28",X"A1",X"3D",X"32",X"34",X"99",X"47",X"D9",X"CC",X"B3",X"32",X"CD",X"90",X"32", + X"D9",X"CD",X"32",X"33",X"3A",X"35",X"99",X"CF",X"CF",X"32",X"EF",X"32",X"FB",X"32",X"1F",X"33", + X"21",X"AF",X"32",X"3A",X"35",X"99",X"E7",X"4E",X"11",X"2C",X"99",X"06",X"04",X"26",X"9D",X"1A", + X"B7",X"C8",X"6F",X"7E",X"81",X"77",X"2C",X"2C",X"7E",X"81",X"77",X"1C",X"10",X"F1",X"C9",X"F8", + X"08",X"08",X"F8",X"2A",X"36",X"99",X"7C",X"B7",X"C8",X"26",X"9A",X"77",X"ED",X"4B",X"38",X"99", + X"78",X"BD",X"C0",X"79",X"FE",X"03",X"C0",X"3D",X"32",X"39",X"99",X"C3",X"44",X"20",X"C9",X"D9", + X"68",X"26",X"00",X"19",X"E5",X"11",X"04",X"00",X"19",X"3E",X"FF",X"06",X"04",X"11",X"20",X"00", + X"CB",X"DC",X"36",X"80",X"CB",X"9C",X"77",X"19",X"10",X"F6",X"D1",X"79",X"C3",X"F0",X"30",X"D9", + X"78",X"ED",X"44",X"83",X"6F",X"62",X"E5",X"2B",X"C3",X"D9",X"32",X"D9",X"EB",X"11",X"E0",X"FF", + X"AF",X"B0",X"28",X"03",X"19",X"10",X"FD",X"E5",X"19",X"3E",X"FF",X"06",X"04",X"11",X"01",X"00", + X"CB",X"DC",X"36",X"80",X"CB",X"9C",X"77",X"19",X"10",X"F6",X"D1",X"79",X"C3",X"F0",X"30",X"D9", + X"EB",X"11",X"20",X"00",X"AF",X"B0",X"28",X"03",X"19",X"10",X"FD",X"E5",X"1E",X"80",X"19",X"C3", + X"09",X"33",X"2A",X"36",X"99",X"4C",X"7D",X"3D",X"57",X"E6",X"0F",X"67",X"AA",X"16",X"00",X"87", + X"CB",X"12",X"87",X"CB",X"12",X"84",X"84",X"5F",X"7C",X"FE",X"0F",X"20",X"02",X"CB",X"EB",X"3E", + X"84",X"B2",X"57",X"D9",X"C9",X"26",X"00",X"11",X"96",X"33",X"3A",X"0D",X"9D",X"DD",X"BE",X"0D", + X"28",X"03",X"11",X"7E",X"33",X"DD",X"7E",X"1F",X"C6",X"08",X"0F",X"0F",X"0F",X"0F",X"84",X"E6", + X"0F",X"DD",X"AE",X"11",X"EB",X"E7",X"7E",X"DD",X"86",X"0F",X"DD",X"77",X"0C",X"C9",X"00",X"1E", + X"1A",X"16",X"12",X"0E",X"0A",X"06",X"02",X"1C",X"18",X"14",X"10",X"0C",X"08",X"04",X"00",X"1E", + X"1A",X"16",X"12",X"0E",X"0A",X"06",X"00",X"3C",X"38",X"34",X"30",X"2C",X"28",X"24",X"20",X"1C", + X"18",X"14",X"10",X"0C",X"08",X"04",X"00",X"3C",X"38",X"34",X"30",X"2C",X"28",X"24",X"3A",X"00", + X"9D",X"0F",X"30",X"06",X"CD",X"A5",X"3A",X"CD",X"6E",X"32",X"CD",X"A7",X"34",X"CD",X"63",X"2E", + X"C9",X"DD",X"7E",X"06",X"C6",X"04",X"DD",X"77",X"06",X"C9",X"3A",X"0D",X"9D",X"DD",X"BE",X"0D", + X"20",X"EF",X"3A",X"06",X"9D",X"32",X"33",X"99",X"3A",X"3B",X"99",X"CB",X"5F",X"28",X"24",X"ED", + X"4B",X"30",X"99",X"3E",X"04",X"81",X"4F",X"30",X"09",X"04",X"3E",X"03",X"B8",X"30",X"03",X"01", + X"FF",X"03",X"ED",X"43",X"30",X"99",X"2A",X"32",X"99",X"04",X"09",X"22",X"32",X"99",X"7C",X"32", + X"06",X"9D",X"C9",X"ED",X"4B",X"30",X"99",X"3E",X"F8",X"81",X"4F",X"38",X"E5",X"05",X"78",X"3C", + X"20",X"E0",X"01",X"00",X"00",X"C3",X"F2",X"33",X"3A",X"20",X"9D",X"B7",X"C8",X"3A",X"21",X"9D", + X"CF",X"2D",X"34",X"2D",X"34",X"52",X"34",X"52",X"34",X"6D",X"34",X"81",X"34",X"3A",X"9B",X"9C", + X"FE",X"04",X"38",X"07",X"21",X"00",X"00",X"22",X"20",X"9D",X"C9",X"06",X"0C",X"3D",X"20",X"02", + X"06",X"04",X"2A",X"24",X"9D",X"3A",X"07",X"98",X"A0",X"28",X"03",X"21",X"00",X"00",X"22",X"22", + X"9D",X"C9",X"3A",X"26",X"9D",X"C6",X"09",X"32",X"26",X"9D",X"3A",X"2C",X"9D",X"32",X"3D",X"9D", + X"CD",X"36",X"35",X"3A",X"3D",X"9D",X"32",X"2C",X"9D",X"CD",X"C4",X"3A",X"C9",X"CD",X"53",X"20", + X"21",X"9B",X"34",X"22",X"2A",X"9D",X"DD",X"36",X"0E",X"01",X"DD",X"36",X"10",X"40",X"DD",X"34", + X"01",X"CD",X"C4",X"3A",X"DD",X"35",X"10",X"C0",X"21",X"00",X"00",X"22",X"20",X"9D",X"C9",X"D4", + X"04",X"02",X"D0",X"04",X"02",X"CC",X"04",X"02",X"FF",X"8F",X"34",X"D4",X"05",X"01",X"D0",X"06", + X"01",X"CC",X"07",X"01",X"FF",X"9B",X"34",X"DD",X"21",X"00",X"9D",X"CD",X"D6",X"34",X"DD",X"21", + X"20",X"9D",X"CD",X"18",X"34",X"11",X"20",X"00",X"DD",X"19",X"3A",X"07",X"98",X"0F",X"30",X"02", + X"DD",X"19",X"06",X"02",X"1E",X"40",X"DD",X"7E",X"00",X"B7",X"28",X"05",X"D9",X"CD",X"D6",X"34", + X"D9",X"DD",X"19",X"10",X"F1",X"C9",X"DD",X"7E",X"01",X"CF",X"33",X"35",X"33",X"35",X"33",X"35", + X"33",X"35",X"E6",X"34",X"06",X"35",X"3A",X"0D",X"9D",X"DD",X"BE",X"0D",X"21",X"15",X"35",X"28", + X"03",X"21",X"24",X"35",X"11",X"40",X"01",X"DD",X"75",X"0A",X"DD",X"74",X"0B",X"DD",X"72",X"0E", + X"DD",X"73",X"10",X"DD",X"34",X"01",X"CD",X"C4",X"3A",X"DD",X"35",X"10",X"C0",X"AF",X"DD",X"77", + X"00",X"DD",X"77",X"01",X"C9",X"C1",X"08",X"04",X"D1",X"04",X"04",X"E1",X"0C",X"04",X"F1",X"10", + X"04",X"FF",X"15",X"35",X"91",X"07",X"03",X"81",X"08",X"03",X"93",X"09",X"03",X"83",X"1A",X"03", + X"FF",X"24",X"35",X"CD",X"CA",X"33",X"3A",X"03",X"99",X"3D",X"DD",X"BE",X"06",X"38",X"59",X"DD", + X"7E",X"08",X"CF",X"E2",X"36",X"EC",X"36",X"F8",X"36",X"02",X"37",X"0E",X"37",X"2A",X"37",X"48", + X"37",X"66",X"37",X"82",X"37",X"9E",X"37",X"BC",X"37",X"D8",X"37",X"F6",X"37",X"F6",X"37",X"F6", + X"37",X"F6",X"37",X"0E",X"38",X"2D",X"38",X"4C",X"38",X"6D",X"38",X"8E",X"38",X"AF",X"38",X"D0", + X"38",X"EF",X"38",X"0E",X"39",X"2D",X"39",X"4C",X"39",X"6D",X"39",X"8E",X"39",X"AD",X"39",X"CC", + X"39",X"ED",X"39",X"FE",X"E0",X"02",X"20",X"00",X"3A",X"34",X"99",X"B7",X"C8",X"3A",X"36",X"99", + X"95",X"3E",X"00",X"C0",X"3A",X"37",X"99",X"C9",X"3A",X"34",X"99",X"B7",X"28",X"14",X"3A",X"36", + X"99",X"DD",X"BE",X"07",X"20",X"0C",X"DD",X"7E",X"02",X"DD",X"77",X"04",X"DD",X"7E",X"03",X"C3", + X"C3",X"35",X"DD",X"7E",X"02",X"C6",X"06",X"E6",X"F0",X"DD",X"77",X"04",X"DD",X"7E",X"03",X"C6", + X"06",X"E6",X"F0",X"DD",X"77",X"05",X"DD",X"7E",X"09",X"21",X"83",X"35",X"E7",X"7E",X"DD",X"4E", + X"07",X"81",X"DD",X"77",X"07",X"6F",X"26",X"9A",X"7E",X"E6",X"3F",X"CC",X"88",X"35",X"6F",X"C6", + X"F0",X"FE",X"FC",X"D4",X"B5",X"36",X"26",X"00",X"29",X"29",X"29",X"11",X"3B",X"45",X"19",X"DD", + X"7E",X"09",X"FE",X"04",X"20",X"05",X"DD",X"7E",X"08",X"E6",X"03",X"57",X"87",X"E7",X"46",X"23", + X"DD",X"7E",X"08",X"C6",X"F0",X"38",X"11",X"A0",X"C6",X"F0",X"FE",X"FC",X"38",X"0A",X"DD",X"34", + X"00",X"DD",X"36",X"01",X"04",X"C3",X"69",X"20",X"DD",X"70",X"08",X"7E",X"DD",X"77",X"09",X"DD", + X"36",X"06",X"00",X"FE",X"04",X"20",X"03",X"DD",X"71",X"07",X"3A",X"2D",X"9D",X"DD",X"BE",X"0D", + X"C8",X"3A",X"0D",X"9D",X"DD",X"BE",X"0D",X"20",X"75",X"D9",X"11",X"01",X"01",X"FF",X"D9",X"21", + X"9D",X"9C",X"34",X"7A",X"2C",X"77",X"DD",X"7E",X"08",X"C6",X"F0",X"30",X"55",X"DD",X"6E",X"07", + X"26",X"9A",X"7E",X"E6",X"3F",X"FE",X"18",X"D8",X"E6",X"07",X"87",X"EB",X"21",X"D2",X"36",X"E7", + X"3A",X"08",X"9D",X"BE",X"C0",X"1A",X"D6",X"08",X"12",X"23",X"6E",X"26",X"00",X"CB",X"7D",X"28", + X"01",X"25",X"19",X"7E",X"D6",X"08",X"77",X"16",X"07",X"45",X"FF",X"58",X"FF",X"CD",X"82",X"20", + X"CD",X"7B",X"2E",X"11",X"0A",X"01",X"FF",X"21",X"09",X"99",X"35",X"2C",X"35",X"C0",X"AF",X"32", + X"2C",X"98",X"01",X"08",X"C0",X"ED",X"43",X"01",X"98",X"21",X"80",X"9B",X"7E",X"B7",X"C8",X"36", + X"01",X"C9",X"FE",X"FC",X"D8",X"21",X"02",X"04",X"22",X"00",X"9D",X"C3",X"30",X"20",X"CD",X"31", + X"2C",X"D0",X"C3",X"7D",X"20",X"3A",X"0D",X"9D",X"DD",X"BE",X"0D",X"20",X"0C",X"11",X"0F",X"01", + X"FF",X"CD",X"78",X"20",X"3E",X"01",X"32",X"94",X"9C",X"CD",X"8F",X"01",X"E6",X"03",X"28",X"F9", + X"6F",X"C9",X"1D",X"FE",X"15",X"02",X"1B",X"FE",X"11",X"02",X"1E",X"20",X"18",X"E0",X"16",X"20", + X"12",X"E0",X"CD",X"20",X"3A",X"DD",X"86",X"05",X"DD",X"77",X"03",X"C9",X"CD",X"20",X"3A",X"ED", + X"44",X"DD",X"86",X"05",X"DD",X"77",X"03",X"C9",X"CD",X"20",X"3A",X"DD",X"86",X"04",X"DD",X"77", + X"02",X"C9",X"CD",X"20",X"3A",X"ED",X"44",X"DD",X"86",X"04",X"DD",X"77",X"02",X"C9",X"CD",X"92", + X"26",X"01",X"00",X"40",X"CD",X"37",X"3A",X"CD",X"6D",X"3A",X"7C",X"D6",X"10",X"DD",X"77",X"02", + X"CD",X"96",X"3A",X"DD",X"74",X"03",X"CD",X"55",X"33",X"C9",X"CD",X"92",X"26",X"01",X"01",X"40", + X"CD",X"37",X"3A",X"CD",X"6D",X"3A",X"DD",X"74",X"02",X"CD",X"96",X"3A",X"7C",X"C6",X"10",X"DD", + X"77",X"03",X"26",X"08",X"CD",X"57",X"33",X"C9",X"CD",X"92",X"26",X"01",X"01",X"80",X"CD",X"37", + X"3A",X"CD",X"7A",X"3A",X"7C",X"C6",X"10",X"DD",X"77",X"02",X"CD",X"96",X"3A",X"DD",X"74",X"03", + X"26",X"08",X"CD",X"57",X"33",X"C9",X"CD",X"92",X"26",X"01",X"00",X"80",X"CD",X"37",X"3A",X"CD", + X"7A",X"3A",X"DD",X"74",X"02",X"CD",X"96",X"3A",X"7C",X"C6",X"10",X"DD",X"77",X"03",X"CD",X"55", + X"33",X"C9",X"CD",X"92",X"26",X"01",X"00",X"00",X"CD",X"37",X"3A",X"CD",X"6D",X"3A",X"DD",X"74", + X"02",X"CD",X"89",X"3A",X"7C",X"D6",X"10",X"DD",X"77",X"03",X"CD",X"55",X"33",X"C9",X"CD",X"92", + X"26",X"01",X"01",X"00",X"CD",X"37",X"3A",X"CD",X"6D",X"3A",X"7C",X"D6",X"10",X"DD",X"77",X"02", + X"CD",X"89",X"3A",X"DD",X"74",X"03",X"26",X"08",X"CD",X"57",X"33",X"C9",X"CD",X"92",X"26",X"01", + X"00",X"C0",X"CD",X"37",X"3A",X"CD",X"7A",X"3A",X"7C",X"C6",X"10",X"DD",X"77",X"02",X"CD",X"89", + X"3A",X"DD",X"74",X"03",X"CD",X"55",X"33",X"C9",X"CD",X"92",X"26",X"01",X"01",X"C0",X"CD",X"37", + X"3A",X"CD",X"7A",X"3A",X"DD",X"74",X"02",X"CD",X"89",X"3A",X"7C",X"D6",X"10",X"DD",X"77",X"03", + X"26",X"08",X"CD",X"57",X"33",X"C9",X"DD",X"34",X"06",X"DD",X"34",X"06",X"3A",X"03",X"99",X"D6", + X"02",X"DD",X"BE",X"06",X"D0",X"3E",X"08",X"DD",X"AE",X"11",X"DD",X"77",X"11",X"C9",X"CD",X"92", + X"26",X"01",X"00",X"40",X"CD",X"37",X"3A",X"CD",X"0E",X"3A",X"CD",X"6D",X"3A",X"7C",X"D6",X"10", + X"DD",X"77",X"02",X"CD",X"96",X"3A",X"DD",X"74",X"03",X"CD",X"55",X"33",X"C9",X"CD",X"92",X"26", + X"01",X"00",X"40",X"CD",X"37",X"3A",X"CD",X"17",X"3A",X"CD",X"6D",X"3A",X"7C",X"D6",X"10",X"DD", + X"77",X"02",X"CD",X"96",X"3A",X"DD",X"74",X"03",X"CD",X"55",X"33",X"C9",X"CD",X"92",X"26",X"01", + X"01",X"40",X"CD",X"37",X"3A",X"CD",X"0E",X"3A",X"CD",X"6D",X"3A",X"DD",X"74",X"02",X"CD",X"96", + X"3A",X"7C",X"C6",X"10",X"DD",X"77",X"03",X"26",X"08",X"CD",X"57",X"33",X"C9",X"CD",X"92",X"26", + X"01",X"01",X"40",X"CD",X"37",X"3A",X"CD",X"17",X"3A",X"CD",X"6D",X"3A",X"DD",X"74",X"02",X"CD", + X"96",X"3A",X"7C",X"C6",X"10",X"DD",X"77",X"03",X"26",X"08",X"CD",X"57",X"33",X"C9",X"CD",X"92", + X"26",X"01",X"01",X"80",X"CD",X"37",X"3A",X"CD",X"0E",X"3A",X"CD",X"7A",X"3A",X"7C",X"C6",X"10", + X"DD",X"77",X"02",X"CD",X"96",X"3A",X"DD",X"74",X"03",X"26",X"08",X"CD",X"57",X"33",X"C9",X"CD", + X"92",X"26",X"01",X"01",X"80",X"CD",X"37",X"3A",X"CD",X"17",X"3A",X"CD",X"7A",X"3A",X"7C",X"C6", + X"10",X"DD",X"77",X"02",X"CD",X"96",X"3A",X"DD",X"74",X"03",X"26",X"08",X"CD",X"57",X"33",X"C9", + X"CD",X"92",X"26",X"01",X"00",X"80",X"CD",X"37",X"3A",X"CD",X"0E",X"3A",X"CD",X"7A",X"3A",X"DD", + X"74",X"02",X"CD",X"96",X"3A",X"7C",X"C6",X"10",X"DD",X"77",X"03",X"CD",X"55",X"33",X"C9",X"CD", + X"92",X"26",X"01",X"00",X"80",X"CD",X"37",X"3A",X"CD",X"17",X"3A",X"CD",X"7A",X"3A",X"DD",X"74", + X"02",X"CD",X"96",X"3A",X"7C",X"C6",X"10",X"DD",X"77",X"03",X"CD",X"55",X"33",X"C9",X"CD",X"92", + X"26",X"01",X"00",X"00",X"CD",X"37",X"3A",X"CD",X"0E",X"3A",X"CD",X"6D",X"3A",X"DD",X"74",X"02", + X"CD",X"89",X"3A",X"7C",X"D6",X"10",X"DD",X"77",X"03",X"CD",X"55",X"33",X"C9",X"CD",X"92",X"26", + X"01",X"00",X"00",X"CD",X"37",X"3A",X"CD",X"17",X"3A",X"CD",X"6D",X"3A",X"DD",X"74",X"02",X"CD", + X"89",X"3A",X"7C",X"D6",X"10",X"DD",X"77",X"03",X"CD",X"55",X"33",X"C9",X"CD",X"92",X"26",X"01", + X"01",X"00",X"CD",X"37",X"3A",X"CD",X"0E",X"3A",X"CD",X"6D",X"3A",X"7C",X"D6",X"10",X"DD",X"77", + X"02",X"CD",X"89",X"3A",X"DD",X"74",X"03",X"26",X"08",X"CD",X"57",X"33",X"C9",X"CD",X"92",X"26", + X"01",X"01",X"00",X"CD",X"37",X"3A",X"CD",X"17",X"3A",X"CD",X"6D",X"3A",X"7C",X"D6",X"10",X"DD", + X"77",X"02",X"CD",X"89",X"3A",X"DD",X"74",X"03",X"26",X"08",X"CD",X"57",X"33",X"C9",X"CD",X"92", + X"26",X"01",X"00",X"C0",X"CD",X"37",X"3A",X"CD",X"0E",X"3A",X"CD",X"7A",X"3A",X"7C",X"C6",X"10", + X"DD",X"77",X"02",X"CD",X"89",X"3A",X"DD",X"74",X"03",X"CD",X"55",X"33",X"C9",X"CD",X"92",X"26", + X"01",X"00",X"C0",X"CD",X"37",X"3A",X"CD",X"17",X"3A",X"CD",X"7A",X"3A",X"7C",X"C6",X"10",X"DD", + X"77",X"02",X"CD",X"89",X"3A",X"DD",X"74",X"03",X"CD",X"55",X"33",X"C9",X"CD",X"92",X"26",X"01", + X"01",X"C0",X"CD",X"37",X"3A",X"CD",X"0E",X"3A",X"CD",X"7A",X"3A",X"DD",X"74",X"02",X"CD",X"89", + X"3A",X"7C",X"D6",X"10",X"DD",X"77",X"03",X"26",X"08",X"CD",X"57",X"33",X"C9",X"CD",X"92",X"26", + X"01",X"01",X"C0",X"CD",X"37",X"3A",X"CD",X"17",X"3A",X"CD",X"7A",X"3A",X"DD",X"74",X"02",X"CD", + X"89",X"3A",X"7C",X"D6",X"10",X"DD",X"77",X"03",X"26",X"08",X"CD",X"57",X"33",X"C9",X"21",X"00", + X"FD",X"19",X"D0",X"11",X"00",X"03",X"C9",X"21",X"00",X"FD",X"09",X"D0",X"01",X"00",X"03",X"C9", + X"CD",X"92",X"26",X"DD",X"77",X"1F",X"5F",X"3A",X"07",X"99",X"87",X"87",X"87",X"CD",X"66",X"26", + X"7C",X"CB",X"15",X"30",X"01",X"3C",X"C9",X"C6",X"02",X"30",X"02",X"3E",X"FF",X"CB",X"41",X"28", + X"02",X"ED",X"44",X"E6",X"FC",X"0F",X"0F",X"80",X"DD",X"77",X"1F",X"87",X"21",X"7A",X"4D",X"5F", + X"16",X"00",X"30",X"01",X"14",X"19",X"4E",X"23",X"5E",X"16",X"00",X"42",X"CB",X"21",X"CB",X"10", + X"CB",X"21",X"CB",X"10",X"CB",X"23",X"CB",X"12",X"CB",X"23",X"CB",X"12",X"C9",X"3A",X"07",X"99", + X"DD",X"66",X"04",X"2E",X"80",X"09",X"3D",X"20",X"FC",X"C9",X"3A",X"07",X"99",X"DD",X"66",X"04", + X"2E",X"80",X"B7",X"ED",X"42",X"3D",X"20",X"FB",X"C9",X"3A",X"07",X"99",X"47",X"DD",X"66",X"05", + X"2E",X"80",X"19",X"10",X"FD",X"C9",X"3A",X"07",X"99",X"47",X"DD",X"66",X"05",X"2E",X"80",X"B7", + X"ED",X"52",X"10",X"FC",X"C9",X"CD",X"0D",X"3B",X"3A",X"3B",X"99",X"E6",X"33",X"C8",X"47",X"21", + X"3A",X"99",X"AE",X"A0",X"C8",X"47",X"11",X"2A",X"99",X"1A",X"F6",X"28",X"6F",X"26",X"99",X"70", + X"EE",X"01",X"12",X"C9",X"DD",X"35",X"0E",X"C0",X"DD",X"E5",X"E1",X"11",X"0A",X"00",X"19",X"5E", + X"2C",X"56",X"2C",X"EB",X"7E",X"3C",X"28",X"0D",X"ED",X"A0",X"ED",X"A0",X"ED",X"A0",X"DD",X"75", + X"0A",X"DD",X"74",X"0B",X"C9",X"23",X"4E",X"23",X"46",X"60",X"69",X"C3",X"D8",X"3A",X"21",X"20", + X"99",X"35",X"20",X"0F",X"23",X"7E",X"34",X"2B",X"EB",X"21",X"F2",X"11",X"87",X"E7",X"ED",X"A0", + X"7E",X"18",X"4F",X"3A",X"A8",X"9C",X"B7",X"28",X"49",X"3E",X"08",X"18",X"45",X"3A",X"3B",X"99", + X"32",X"3A",X"99",X"3A",X"08",X"98",X"0F",X"30",X"D5",X"3A",X"0E",X"98",X"B7",X"28",X"10",X"3A", + X"18",X"98",X"E6",X"01",X"47",X"3A",X"1C",X"98",X"E6",X"3E",X"B0",X"32",X"3B",X"99",X"C9",X"3A", + X"1C",X"98",X"E6",X"01",X"4F",X"3A",X"18",X"98",X"87",X"E6",X"74",X"47",X"0F",X"E6",X"08",X"ED", + X"44",X"80",X"CB",X"77",X"28",X"02",X"D6",X"30",X"B1",X"47",X"3A",X"1E",X"98",X"07",X"07",X"E6", + X"02",X"B0",X"32",X"3B",X"99",X"C9",X"DD",X"6E",X"07",X"26",X"9A",X"7E",X"E6",X"3F",X"BE",X"28", + X"05",X"3E",X"01",X"32",X"94",X"9C",X"7E",X"E6",X"3F",X"FE",X"04",X"30",X"15",X"EB",X"47",X"87", + X"87",X"4F",X"DD",X"7E",X"09",X"EE",X"02",X"81",X"21",X"B1",X"3B",X"E7",X"7E",X"12",X"16",X"07", + X"FF",X"C9",X"FE",X"0C",X"30",X"07",X"36",X"0B",X"EB",X"16",X"07",X"FF",X"C9",X"CB",X"67",X"C8", + X"3A",X"80",X"9B",X"B7",X"CA",X"BD",X"27",X"EB",X"1A",X"E6",X"07",X"87",X"21",X"D3",X"36",X"E7", + X"7E",X"83",X"4F",X"EB",X"3A",X"88",X"9B",X"B9",X"28",X"04",X"BD",X"C2",X"BD",X"27",X"11",X"71", + X"27",X"D5",X"C3",X"BD",X"27",X"05",X"05",X"04",X"04",X"07",X"06",X"06",X"07",X"08",X"09",X"08", + X"09",X"CD",X"C8",X"3B",X"CD",X"F4",X"3B",X"C9",X"3A",X"00",X"9D",X"0F",X"D0",X"ED",X"5B",X"02", + X"9D",X"2A",X"07",X"9D",X"D9",X"06",X"05",X"11",X"20",X"00",X"DD",X"21",X"20",X"9D",X"D9",X"CD", + X"3E",X"3C",X"38",X"06",X"D9",X"DD",X"19",X"10",X"F5",X"C9",X"CD",X"33",X"3C",X"21",X"02",X"04", + X"22",X"00",X"9D",X"C9",X"0E",X"04",X"11",X"20",X"00",X"FD",X"21",X"20",X"9D",X"FD",X"7E",X"00", + X"0F",X"30",X"20",X"FD",X"E5",X"DD",X"E1",X"DD",X"19",X"41",X"D9",X"FD",X"56",X"03",X"FD",X"5E", + X"02",X"FD",X"66",X"08",X"FD",X"6E",X"07",X"D9",X"D9",X"CD",X"3E",X"3C",X"38",X"0B",X"D9",X"DD", + X"19",X"10",X"F5",X"FD",X"19",X"0D",X"20",X"D5",X"C9",X"CD",X"56",X"3B",X"FD",X"34",X"00",X"FD", + X"36",X"01",X"04",X"CD",X"69",X"20",X"DD",X"34",X"00",X"DD",X"36",X"01",X"04",X"C9",X"DD",X"7E", + X"00",X"0F",X"D0",X"DD",X"7E",X"02",X"93",X"C6",X"08",X"FE",X"11",X"D0",X"DD",X"7E",X"03",X"92", + X"C6",X"08",X"FE",X"11",X"D0",X"DD",X"7E",X"07",X"BD",X"20",X"14",X"7C",X"D6",X"08",X"FE",X"08", + X"30",X"0D",X"C6",X"08",X"E6",X"FE",X"67",X"DD",X"7E",X"08",X"E6",X"FE",X"BC",X"20",X"02",X"37", + X"C9",X"B7",X"C9",X"7B",X"3C",X"7B",X"38",X"5B",X"34",X"BB",X"2C",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"80",X"80",X"80",X"80",X"80", + X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"83",X"5B",X"5A",X"82",X"63", + X"53",X"52",X"62",X"61",X"51",X"50",X"60",X"81",X"59",X"58",X"80",X"9C",X"9C",X"9C",X"9C",X"9C", + X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"83",X"43",X"42",X"82",X"4B", + X"3B",X"3A",X"4A",X"49",X"39",X"38",X"48",X"81",X"41",X"40",X"80",X"9D",X"9D",X"9D",X"9D",X"9D", + X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"83",X"AD",X"AF",X"82",X"AE", + X"6B",X"6A",X"7A",X"AC",X"69",X"68",X"78",X"81",X"79",X"7B",X"80",X"9E",X"9E",X"9E",X"9E",X"9E", + X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"83",X"9B",X"9A",X"82",X"97", + X"82",X"38",X"62",X"95",X"38",X"50",X"60",X"81",X"59",X"58",X"80",X"9C",X"9C",X"9C",X"9C",X"9C", + X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"83",X"5B",X"5A",X"82",X"63", + X"53",X"38",X"96",X"61",X"38",X"82",X"94",X"81",X"99",X"98",X"80",X"9C",X"9C",X"9C",X"9C",X"9C", + X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"83",X"43",X"42",X"82",X"97", + X"38",X"3A",X"4A",X"95",X"82",X"38",X"48",X"81",X"99",X"98",X"80",X"9D",X"9D",X"9D",X"9D",X"9D", + X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"83",X"9B",X"9A",X"82",X"4B", + X"38",X"82",X"96",X"49",X"39",X"38",X"94",X"81",X"41",X"40",X"80",X"9D",X"9D",X"9D",X"9D",X"9D", + X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"83",X"AD",X"AF",X"82",X"97", + X"AD",X"AF",X"96",X"95",X"AD",X"AF",X"94",X"81",X"79",X"7B",X"80",X"9E",X"9E",X"9E",X"9E",X"9E", + X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"83",X"9B",X"9A",X"82",X"AE", + X"7A",X"7A",X"7A",X"AC",X"78",X"78",X"78",X"81",X"99",X"98",X"80",X"9E",X"9E",X"9E",X"9E",X"9E", + X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"83",X"9B",X"9A",X"82",X"97", + X"8F",X"8E",X"7A",X"95",X"8D",X"8C",X"78",X"81",X"79",X"7B",X"80",X"9E",X"9E",X"9E",X"9E",X"9E", + X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"83",X"9B",X"9A",X"82",X"97", + X"82",X"82",X"96",X"95",X"82",X"82",X"94",X"81",X"99",X"98",X"80",X"9E",X"9E",X"9E",X"9E",X"9E", + X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"83",X"C3",X"C2",X"82",X"BF", + X"8B",X"8A",X"BE",X"BD",X"89",X"88",X"BC",X"81",X"C1",X"C0",X"80",X"9E",X"9E",X"9E",X"9E",X"9E", + X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"83",X"C3",X"C2",X"82",X"BF", + X"8B",X"8A",X"BE",X"BD",X"89",X"88",X"BC",X"81",X"C1",X"C0",X"80",X"9E",X"9E",X"9E",X"9E",X"9E", + X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"83",X"C3",X"C2",X"82",X"BF", + X"8B",X"8A",X"BE",X"BD",X"89",X"88",X"BC",X"81",X"C1",X"C0",X"80",X"9E",X"9E",X"9E",X"9E",X"9E", + X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"83",X"C3",X"C2",X"82",X"BF", + X"8B",X"8A",X"BE",X"BD",X"89",X"88",X"BC",X"81",X"C1",X"C0",X"80",X"9E",X"9E",X"9E",X"9E",X"9E", + X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"65",X"65",X"65",X"65",X"65", + X"65",X"65",X"65",X"63",X"53",X"5B",X"5B",X"5D",X"51",X"50",X"5D",X"10",X"10",X"10",X"10",X"10", + X"10",X"10",X"10",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"65",X"65",X"65",X"65",X"65", + X"65",X"65",X"65",X"5B",X"5B",X"5A",X"63",X"5D",X"59",X"58",X"5D",X"10",X"10",X"10",X"10",X"10", + X"10",X"10",X"10",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"52",X"57",X"56",X"52",X"6F", + X"55",X"54",X"54",X"65",X"65",X"65",X"65",X"65",X"65",X"65",X"65",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"52",X"5F",X"5E",X"52",X"54", + X"54",X"5C",X"6F",X"65",X"65",X"65",X"65",X"65",X"65",X"65",X"65",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"4B",X"42",X"65",X"65",X"43", + X"42",X"65",X"65",X"41",X"40",X"65",X"65",X"4B",X"62",X"65",X"65",X"C0",X"C0",X"10",X"10",X"C0", + X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"4B",X"62",X"65",X"65",X"47", + X"46",X"65",X"65",X"45",X"42",X"65",X"65",X"4B",X"42",X"65",X"65",X"C0",X"C0",X"10",X"10",X"C0", + X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"65",X"65",X"4B",X"44",X"65", + X"65",X"4B",X"4A",X"65",X"65",X"49",X"48",X"65",X"65",X"6E",X"44",X"10",X"10",X"C0",X"C0",X"10", + X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"65",X"65",X"6E",X"44",X"65", + X"65",X"4F",X"4E",X"65",X"65",X"4B",X"4C",X"65",X"65",X"4B",X"44",X"10",X"10",X"C0",X"C0",X"10", + X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"64",X"64",X"64",X"64",X"64", + X"64",X"64",X"64",X"67",X"33",X"3B",X"3B",X"6A",X"31",X"30",X"3D",X"10",X"10",X"10",X"10",X"10", + X"10",X"10",X"10",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"64",X"64",X"64",X"64",X"64", + X"64",X"64",X"64",X"3B",X"3B",X"3A",X"67",X"3D",X"39",X"38",X"6B",X"10",X"10",X"10",X"10",X"10", + X"10",X"10",X"10",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"6A",X"37",X"36",X"32",X"73", + X"35",X"34",X"34",X"64",X"64",X"64",X"64",X"64",X"64",X"64",X"64",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"32",X"3F",X"3E",X"6B",X"34", + X"34",X"3C",X"73",X"64",X"64",X"64",X"64",X"64",X"64",X"64",X"64",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"2B",X"22",X"64",X"64",X"23", + X"22",X"64",X"64",X"21",X"20",X"64",X"64",X"76",X"66",X"64",X"64",X"C0",X"C0",X"10",X"10",X"C0", + X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"74",X"66",X"64",X"64",X"27", + X"26",X"64",X"64",X"25",X"22",X"64",X"64",X"2B",X"22",X"64",X"64",X"C0",X"C0",X"10",X"10",X"C0", + X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"64",X"64",X"2B",X"24",X"64", + X"64",X"2B",X"2A",X"64",X"64",X"29",X"28",X"64",X"64",X"72",X"76",X"10",X"10",X"C0",X"C0",X"10", + X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"64",X"64",X"72",X"74",X"64", + X"64",X"2F",X"2E",X"64",X"64",X"2B",X"2C",X"64",X"64",X"2B",X"24",X"10",X"10",X"C0",X"C0",X"10", + X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"7B",X"7A",X"7A",X"7A",X"7B", + X"7A",X"7A",X"7A",X"7B",X"7A",X"7A",X"7A",X"79",X"78",X"78",X"78",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"83",X"5B",X"5A",X"82",X"63", + X"53",X"B6",X"66",X"61",X"B5",X"54",X"64",X"81",X"5D",X"5C",X"80",X"9C",X"9C",X"9C",X"9C",X"9C", + X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"83",X"47",X"46",X"82",X"4B", + X"BB",X"3E",X"4E",X"49",X"39",X"B8",X"4C",X"81",X"41",X"40",X"80",X"9D",X"9D",X"9D",X"9D",X"9D", + X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"83",X"AD",X"AF",X"82",X"B2", + X"73",X"72",X"7E",X"B0",X"71",X"70",X"7C",X"81",X"79",X"7B",X"80",X"9E",X"9E",X"9E",X"9E",X"9E", + X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"83",X"9B",X"9A",X"82",X"97", + X"82",X"38",X"66",X"95",X"38",X"54",X"64",X"81",X"5D",X"5C",X"80",X"9C",X"9C",X"9C",X"9C",X"9C", + X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"83",X"5F",X"5E",X"82",X"67", + X"57",X"38",X"96",X"65",X"38",X"82",X"94",X"81",X"99",X"98",X"80",X"9C",X"9C",X"9C",X"9C",X"9C", + X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"83",X"47",X"46",X"82",X"97", + X"38",X"3E",X"4E",X"95",X"82",X"38",X"4C",X"81",X"99",X"98",X"80",X"9D",X"9D",X"9D",X"9D",X"9D", + X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"83",X"9B",X"9A",X"82",X"4F", + X"38",X"82",X"96",X"4D",X"3D",X"38",X"94",X"81",X"45",X"44",X"80",X"9D",X"9D",X"9D",X"9D",X"9D", + X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"83",X"B1",X"B3",X"82",X"97", + X"B1",X"B3",X"96",X"95",X"B1",X"B3",X"94",X"81",X"7D",X"7F",X"80",X"9E",X"9E",X"9E",X"9E",X"9E", + X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"83",X"9B",X"9A",X"82",X"B2", + X"7E",X"7E",X"7E",X"B0",X"7C",X"7C",X"7C",X"81",X"99",X"98",X"80",X"9E",X"9E",X"9E",X"9E",X"9E", + X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"83",X"9B",X"9A",X"82",X"97", + X"8F",X"8E",X"93",X"95",X"8D",X"8C",X"91",X"81",X"7D",X"7F",X"80",X"9E",X"9E",X"9E",X"9E",X"9E", + X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"83",X"9B",X"9A",X"82",X"97", + X"82",X"82",X"96",X"95",X"82",X"82",X"94",X"81",X"99",X"98",X"80",X"9E",X"9E",X"9E",X"9E",X"9E", + X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"83",X"C3",X"C2",X"82",X"BF", + X"8B",X"8A",X"DA",X"BD",X"89",X"88",X"D8",X"81",X"C1",X"C0",X"80",X"9E",X"9E",X"9E",X"9E",X"9E", + X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"83",X"C3",X"C2",X"82",X"BF", + X"8B",X"8A",X"BE",X"BD",X"89",X"88",X"BC",X"81",X"DD",X"DC",X"80",X"9E",X"9E",X"9E",X"9E",X"9E", + X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"83",X"C3",X"C2",X"82",X"DB", + X"8B",X"8A",X"BE",X"D9",X"89",X"88",X"BC",X"81",X"C1",X"C0",X"80",X"9E",X"9E",X"9E",X"9E",X"9E", + X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"83",X"DF",X"DE",X"82",X"BF", + X"8B",X"8A",X"BE",X"BD",X"89",X"88",X"BC",X"81",X"C1",X"C0",X"80",X"9E",X"9E",X"9E",X"9E",X"9E", + X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"65",X"65",X"65",X"65",X"65", + X"65",X"65",X"65",X"63",X"53",X"5B",X"5B",X"54",X"51",X"50",X"54",X"10",X"10",X"10",X"10",X"10", + X"10",X"10",X"10",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"65",X"65",X"65",X"65",X"65", + X"65",X"65",X"65",X"5B",X"5B",X"5A",X"63",X"54",X"59",X"58",X"54",X"10",X"10",X"10",X"10",X"10", + X"10",X"10",X"10",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"52",X"57",X"56",X"52",X"6F", + X"55",X"54",X"54",X"65",X"65",X"65",X"65",X"65",X"65",X"65",X"65",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"52",X"5F",X"5E",X"52",X"54", + X"54",X"5C",X"6F",X"65",X"65",X"65",X"65",X"65",X"65",X"65",X"65",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"4B",X"42",X"65",X"65",X"43", + X"42",X"65",X"65",X"41",X"40",X"65",X"65",X"4B",X"62",X"65",X"65",X"C0",X"C0",X"10",X"10",X"C0", + X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"4B",X"62",X"65",X"65",X"47", + X"46",X"65",X"65",X"45",X"42",X"65",X"65",X"4B",X"42",X"65",X"65",X"C0",X"C0",X"10",X"10",X"C0", + X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"65",X"65",X"4B",X"44",X"65", + X"65",X"4B",X"4A",X"65",X"65",X"49",X"48",X"65",X"65",X"6E",X"42",X"10",X"10",X"C0",X"C0",X"10", + X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"65",X"65",X"6E",X"42",X"65", + X"65",X"4F",X"4E",X"65",X"65",X"4B",X"4C",X"65",X"65",X"4B",X"44",X"10",X"10",X"C0",X"C0",X"10", + X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"64",X"64",X"64",X"64",X"64", + X"64",X"64",X"64",X"61",X"13",X"1B",X"1B",X"68",X"11",X"70",X"1D",X"10",X"10",X"10",X"10",X"10", + X"10",X"10",X"10",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"64",X"64",X"64",X"64",X"64", + X"64",X"64",X"64",X"1B",X"1B",X"1A",X"61",X"1D",X"19",X"18",X"69",X"10",X"10",X"10",X"10",X"10", + X"10",X"10",X"10",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"68",X"17",X"16",X"12",X"6D", + X"15",X"14",X"14",X"64",X"64",X"64",X"64",X"64",X"64",X"64",X"64",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"12",X"1F",X"1E",X"69",X"14", + X"14",X"1C",X"6D",X"64",X"64",X"64",X"64",X"64",X"64",X"64",X"64",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"0B",X"02",X"64",X"64",X"03", + X"02",X"64",X"64",X"01",X"00",X"64",X"64",X"77",X"60",X"64",X"64",X"C0",X"C0",X"10",X"10",X"C0", + X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"75",X"60",X"64",X"64",X"07", + X"06",X"64",X"64",X"05",X"02",X"64",X"64",X"0B",X"02",X"64",X"64",X"C0",X"C0",X"10",X"10",X"C0", + X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"64",X"64",X"0B",X"04",X"64", + X"64",X"0B",X"0A",X"64",X"64",X"09",X"08",X"64",X"64",X"6C",X"77",X"10",X"10",X"C0",X"C0",X"10", + X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"64",X"64",X"6C",X"75",X"64", + X"64",X"0F",X"0E",X"64",X"64",X"0B",X"0C",X"64",X"64",X"0B",X"04",X"10",X"10",X"C0",X"C0",X"10", + X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"10",X"10",X"C0",X"C0",X"83",X"5F",X"5E",X"82",X"67", + X"57",X"BA",X"62",X"65",X"B9",X"50",X"60",X"81",X"59",X"58",X"80",X"9C",X"9C",X"9C",X"9C",X"9C", + X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"83",X"43",X"42",X"82",X"4F", + X"B7",X"3A",X"4A",X"4D",X"3D",X"B4",X"48",X"81",X"45",X"44",X"80",X"9D",X"9D",X"9D",X"9D",X"9D", + X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"83",X"B1",X"B3",X"82",X"AE", + X"6F",X"6E",X"7A",X"AC",X"6D",X"6C",X"78",X"81",X"7D",X"7F",X"80",X"9E",X"9E",X"9E",X"9E",X"9E", + X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"83",X"5F",X"5E",X"82",X"67", + X"57",X"56",X"66",X"65",X"55",X"54",X"64",X"81",X"5D",X"5C",X"80",X"9C",X"9C",X"9C",X"9C",X"9C", + X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"9C",X"83",X"47",X"46",X"82",X"4F", + X"3F",X"3E",X"4E",X"4D",X"3D",X"3C",X"4C",X"81",X"45",X"44",X"80",X"9D",X"9D",X"9D",X"9D",X"9D", + X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"9D",X"83",X"B1",X"B3",X"82",X"B2", + X"77",X"76",X"7E",X"B0",X"75",X"74",X"7C",X"81",X"7D",X"7F",X"80",X"9E",X"9E",X"9E",X"9E",X"9E", + X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"0E",X"04",X"0F",X"04",X"0C", + X"04",X"0D",X"04",X"06",X"03",X"07",X"02",X"09",X"01",X"08",X"00",X"04",X"01",X"0B",X"00",X"0A", + X"03",X"05",X"02",X"01",X"00",X"03",X"01",X"00",X"02",X"02",X"03",X"06",X"03",X"07",X"02",X"0C", + X"04",X"0D",X"04",X"0E",X"04",X"0F",X"04",X"09",X"01",X"08",X"00",X"04",X"01",X"0F",X"04",X"0C", + X"04",X"05",X"02",X"0E",X"04",X"0B",X"00",X"0A",X"03",X"0D",X"04",X"0E",X"04",X"03",X"01",X"0C", + X"04",X"02",X"03",X"01",X"00",X"0F",X"04",X"00",X"02",X"0D",X"04",X"06",X"03",X"07",X"02",X"0C", + X"04",X"0D",X"04",X"0E",X"04",X"0F",X"04",X"0C",X"04",X"0D",X"04",X"06",X"03",X"07",X"02",X"09", + X"01",X"08",X"00",X"04",X"01",X"0B",X"00",X"0A",X"03",X"05",X"02",X"01",X"00",X"03",X"01",X"00", + X"02",X"02",X"03",X"0E",X"04",X"0F",X"04",X"0C",X"04",X"0D",X"04",X"0E",X"04",X"1F",X"00",X"1D", + X"03",X"0D",X"04",X"15",X"03",X"17",X"02",X"0C",X"04",X"0D",X"04",X"0E",X"04",X"0F",X"04",X"1B", + X"01",X"19",X"00",X"11",X"01",X"0F",X"04",X"0C",X"04",X"13",X"02",X"0E",X"04",X"1E",X"00",X"1C", + X"03",X"0D",X"04",X"0E",X"04",X"0F",X"04",X"1A",X"01",X"18",X"00",X"14",X"03",X"16",X"02",X"0C", + X"04",X"0D",X"04",X"10",X"01",X"0F",X"04",X"0C",X"04",X"12",X"02",X"0E",X"04",X"1F",X"00",X"1D", + X"03",X"0D",X"04",X"15",X"03",X"17",X"02",X"0C",X"04",X"0D",X"04",X"0E",X"04",X"0F",X"04",X"1B", + X"01",X"19",X"00",X"11",X"01",X"0F",X"04",X"0C",X"04",X"13",X"02",X"0E",X"04",X"1E",X"00",X"1C", + X"03",X"0D",X"04",X"0E",X"04",X"0F",X"04",X"1A",X"01",X"18",X"00",X"14",X"03",X"16",X"02",X"0C", + X"04",X"0D",X"04",X"10",X"01",X"0F",X"04",X"0C",X"04",X"12",X"02",X"0E",X"04",X"0F",X"04",X"0C", + X"04",X"0D",X"04",X"0E",X"04",X"0F",X"04",X"0C",X"04",X"0D",X"04",X"0E",X"04",X"0F",X"04",X"0C", + X"04",X"0D",X"04",X"0E",X"04",X"0F",X"04",X"0C",X"04",X"0D",X"04",X"0E",X"04",X"0F",X"04",X"0C", + X"04",X"0D",X"04",X"00",X"00",X"00",X"00",X"40",X"40",X"80",X"80",X"40",X"80",X"80",X"40",X"40", + X"80",X"40",X"80",X"40",X"40",X"00",X"00",X"00",X"00",X"40",X"40",X"40",X"00",X"00",X"40",X"00", + X"40",X"40",X"00",X"00",X"40",X"00",X"40",X"40",X"00",X"40",X"00",X"40",X"40",X"00",X"00",X"00", + X"00",X"00",X"00",X"40",X"40",X"40",X"40",X"40",X"40",X"40",X"40",X"40",X"40",X"40",X"40",X"40", + X"40",X"40",X"40",X"00",X"40",X"40",X"00",X"40",X"40",X"00",X"00",X"00",X"00",X"40",X"40",X"40", + X"00",X"00",X"40",X"00",X"40",X"40",X"00",X"00",X"00",X"40",X"40",X"40",X"40",X"00",X"00",X"40", + X"00",X"00",X"40",X"00",X"40",X"40",X"00",X"40",X"40",X"00",X"00",X"00",X"00",X"40",X"40",X"40", + X"00",X"00",X"40",X"00",X"40",X"40",X"00",X"00",X"00",X"40",X"40",X"40",X"40",X"00",X"00",X"40", + X"00",X"00",X"40",X"C1",X"01",X"00",X"C1",X"00",X"00",X"FD",X"01",X"00",X"FD",X"00",X"00",X"F9", + X"01",X"00",X"F9",X"00",X"00",X"F5",X"01",X"00",X"F5",X"00",X"00",X"F1",X"00",X"00",X"F1",X"01", + X"00",X"ED",X"00",X"00",X"ED",X"00",X"00",X"E9",X"00",X"00",X"E9",X"00",X"00",X"E5",X"00",X"00", + X"E5",X"00",X"00",X"E1",X"00",X"00",X"E1",X"00",X"00",X"DD",X"00",X"00",X"DD",X"00",X"00",X"D9", + X"00",X"00",X"D9",X"00",X"00",X"D5",X"00",X"00",X"D5",X"00",X"00",X"D1",X"00",X"00",X"D1",X"01", + X"00",X"CD",X"00",X"00",X"CD",X"00",X"00",X"C9",X"00",X"00",X"C9",X"00",X"00",X"C5",X"00",X"00", + X"C5",X"00",X"00",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"64",X"64",X"64",X"64",X"64", + X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"64",X"64",X"64",X"64",X"64",X"A3",X"A2",X"10", + X"10",X"10",X"10",X"10",X"10",X"93",X"92",X"64",X"64",X"64",X"FE",X"FE",X"A6",X"A3",X"A2",X"10", + X"10",X"10",X"71",X"71",X"8F",X"64",X"64",X"CB",X"CA",X"FD",X"FC",X"A9",X"A8",X"A3",X"A2",X"71", + X"71",X"71",X"8E",X"64",X"C9",X"C8",X"C7",X"C6",X"A5",X"A4",X"A1",X"A0",X"A5",X"71",X"71",X"8C", + X"64",X"FE",X"FE",X"A7",X"A1",X"A0",X"A4",X"10",X"10",X"71",X"71",X"8D",X"64",X"64",X"A1",X"A0", + X"A4",X"10",X"10",X"10",X"10",X"10",X"91",X"90",X"64",X"64",X"64",X"10",X"10",X"10",X"10",X"10", + X"10",X"10",X"10",X"64",X"64",X"64",X"64",X"64",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10", + X"64",X"64",X"64",X"64",X"64",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"C0",X"C0",X"C0", + X"C0",X"C0",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"C0",X"C0",X"C0",X"80",X"80",X"C0",X"C0", + X"C0",X"80",X"80",X"80",X"C0",X"C0",X"80",X"C0",X"C0",X"80",X"80",X"80",X"80",X"80",X"80",X"80", + X"80",X"C0",X"C0",X"C0",X"80",X"C0",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"C0",X"C0", + X"C0",X"80",X"C0",X"80",X"80",X"C0",X"C0",X"C0",X"C0",X"80",X"80",X"C0",X"C0",X"80",X"C0",X"C0", + X"C0",X"C0",X"C0",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"C0",X"C0",X"C0",X"80",X"80",X"80", + X"80",X"80",X"80",X"80",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"80",X"80",X"80",X"80",X"80",X"80", + X"80",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"71",X"71", + X"71",X"71",X"71",X"71",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"71",X"71",X"71",X"71",X"71", + X"71",X"A3",X"A2",X"10",X"10",X"10",X"10",X"10",X"71",X"71",X"71",X"71",X"71",X"71",X"FE",X"FE", + X"A6",X"A3",X"A2",X"10",X"10",X"71",X"71",X"71",X"71",X"71",X"71",X"CB",X"CA",X"FD",X"FC",X"A9", + X"A8",X"A3",X"AB",X"AA",X"71",X"71",X"71",X"71",X"C9",X"C8",X"C7",X"C6",X"A5",X"A4",X"A1",X"A9", + X"A8",X"71",X"71",X"71",X"71",X"FE",X"FE",X"A7",X"A1",X"A0",X"A4",X"10",X"71",X"71",X"71",X"71", + X"71",X"71",X"A1",X"A0",X"A4",X"10",X"10",X"10",X"10",X"71",X"71",X"71",X"71",X"71",X"71",X"10", + X"10",X"10",X"10",X"10",X"10",X"10",X"71",X"71",X"71",X"71",X"71",X"71",X"10",X"10",X"10",X"10", + X"10",X"10",X"10",X"71",X"71",X"71",X"71",X"71",X"71",X"80",X"80",X"80",X"80",X"80",X"80",X"80", + X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"C0",X"C0",X"80",X"80",X"80",X"80",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0", + X"80",X"80",X"C0",X"C0",X"C0",X"80",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"80",X"80",X"80", + X"80",X"80",X"80",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"80",X"80",X"80",X"80",X"80",X"80", + X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"80",X"80",X"C0",X"C0",X"C0",X"C0",X"80",X"C0",X"C0", + X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"80",X"80",X"80",X"80",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"80",X"80", + X"80",X"80",X"80",X"80",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"10",X"10",X"10",X"10",X"10", + X"71",X"71",X"71",X"71",X"71",X"71",X"71",X"71",X"10",X"10",X"10",X"10",X"10",X"71",X"71",X"71", + X"71",X"71",X"71",X"71",X"71",X"A3",X"A2",X"10",X"10",X"10",X"71",X"71",X"71",X"71",X"71",X"71", + X"71",X"71",X"FE",X"FE",X"A6",X"A3",X"A2",X"AB",X"AB",X"AF",X"71",X"71",X"71",X"71",X"71",X"CB", + X"CA",X"FD",X"FC",X"A9",X"10",X"10",X"10",X"AE",X"71",X"71",X"71",X"71",X"C9",X"C8",X"C7",X"C6", + X"A5",X"10",X"10",X"10",X"AC",X"71",X"71",X"71",X"71",X"FE",X"FE",X"A7",X"A1",X"A0",X"A9",X"A9", + X"AD",X"71",X"71",X"71",X"71",X"71",X"A1",X"A0",X"A4",X"10",X"10",X"71",X"71",X"71",X"71",X"71", + X"71",X"71",X"71",X"10",X"10",X"10",X"10",X"10",X"71",X"71",X"71",X"71",X"71",X"71",X"71",X"71", + X"10",X"10",X"10",X"10",X"10",X"71",X"71",X"71",X"71",X"71",X"71",X"71",X"71",X"80",X"80",X"80", + X"80",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"80",X"80",X"80",X"80",X"80",X"C0", + X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"80",X"80",X"80",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"C0",X"80",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"80",X"80",X"80",X"80",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"80",X"80", + X"80",X"80",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"80",X"80",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"80",X"80",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"C0",X"C0",X"80",X"80",X"80",X"80",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"80",X"80",X"80",X"80",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"10", + X"71",X"71",X"71",X"71",X"71",X"71",X"71",X"71",X"71",X"71",X"71",X"71",X"10",X"71",X"71",X"71", + X"71",X"71",X"71",X"71",X"71",X"71",X"71",X"71",X"71",X"A3",X"10",X"10",X"10",X"10",X"B7",X"B6", + X"71",X"71",X"71",X"71",X"71",X"71",X"FE",X"10",X"10",X"10",X"10",X"10",X"B3",X"71",X"71",X"71", + X"71",X"71",X"71",X"CB",X"10",X"10",X"10",X"10",X"10",X"B2",X"71",X"71",X"71",X"71",X"71",X"71", + X"C9",X"10",X"10",X"10",X"10",X"10",X"B0",X"71",X"71",X"71",X"71",X"71",X"71",X"FE",X"10",X"10", + X"10",X"10",X"10",X"B1",X"71",X"71",X"71",X"71",X"71",X"71",X"A1",X"10",X"10",X"10",X"10",X"B5", + X"B4",X"71",X"71",X"71",X"71",X"71",X"71",X"10",X"71",X"71",X"71",X"71",X"71",X"71",X"71",X"71", + X"71",X"71",X"71",X"71",X"10",X"71",X"71",X"71",X"71",X"71",X"71",X"71",X"71",X"71",X"71",X"71", + X"71",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"80",X"C0", + X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"C0",X"C0",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"80", + X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"B7",X"B6",X"71",X"71", + X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"BF",X"71",X"10",X"10",X"10", + X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"BE",X"10",X"10",X"10",X"10",X"10",X"10", + X"10",X"10",X"10",X"10",X"10",X"10",X"BB",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10", + X"10",X"10",X"10",X"BA",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10", + X"B8",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"B9",X"10",X"10", + X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"BC",X"10",X"10",X"10",X"10",X"10", + X"10",X"10",X"10",X"10",X"10",X"10",X"BD",X"71",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10", + X"10",X"B5",X"B4",X"71",X"71",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0", + X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"FF",X"06",X"FF",X"0D",X"FF", + X"13",X"FF",X"19",X"FF",X"1F",X"FE",X"26",X"FD",X"2C",X"FC",X"32",X"FB",X"38",X"FA",X"3E",X"F8", + X"44",X"F7",X"4A",X"F5",X"50",X"F3",X"56",X"F1",X"5C",X"EF",X"62",X"ED",X"68",X"EA",X"6D",X"E7", + X"73",X"E5",X"79",X"E2",X"7E",X"DF",X"84",X"DC",X"89",X"D8",X"8E",X"D5",X"93",X"D1",X"99",X"CE", + X"9E",X"CA",X"A2",X"C6",X"A7",X"C2",X"AC",X"BE",X"B1",X"B9",X"B5",X"B5",X"B9",X"B1",X"BE",X"AC", + X"C2",X"A7",X"C6",X"A2",X"CA",X"9E",X"CE",X"99",X"D1",X"93",X"D5",X"8E",X"D8",X"89",X"DC",X"84", + X"DF",X"7E",X"E2",X"79",X"E5",X"73",X"E7",X"6D",X"EA",X"68",X"ED",X"62",X"EF",X"5C",X"F1",X"56", + X"F3",X"50",X"F5",X"4A",X"F7",X"44",X"F8",X"3E",X"FA",X"38",X"FB",X"32",X"FC",X"2C",X"FD",X"26", + X"FE",X"1F",X"FF",X"19",X"FF",X"13",X"FF",X"0D",X"FF",X"06",X"FF",X"00",X"FF",X"06",X"FF",X"0D", + X"FF",X"13",X"FF",X"19",X"FE",X"1F",X"FD",X"26",X"FC",X"2C",X"FB",X"32",X"FA",X"38",X"F8",X"3E", + X"F7",X"44",X"F5",X"4A",X"F3",X"50",X"F1",X"56",X"EF",X"5C",X"ED",X"62",X"EA",X"68",X"E7",X"6D", + X"E5",X"73",X"E2",X"79",X"DF",X"7E",X"DC",X"84",X"D8",X"89",X"D5",X"8E",X"D1",X"93",X"CE",X"99", + X"CA",X"9E",X"C6",X"A2",X"C2",X"A7",X"BE",X"AC",X"B9",X"B1",X"B5",X"B5",X"B1",X"B9",X"AC",X"BE", + X"A7",X"C2",X"A2",X"C6",X"9E",X"CA",X"99",X"CE",X"93",X"D1",X"8E",X"D5",X"89",X"D8",X"84",X"DC", + X"7E",X"DF",X"79",X"E2",X"73",X"E5",X"6D",X"E7",X"68",X"EA",X"62",X"ED",X"5C",X"EF",X"56",X"F1", + X"50",X"F3",X"4A",X"F5",X"44",X"F7",X"3E",X"F8",X"38",X"FA",X"32",X"FB",X"2C",X"FC",X"26",X"FD", + X"1F",X"FE",X"19",X"FF",X"13",X"FF",X"0D",X"FF",X"06",X"FF",X"00",X"FF",X"06",X"FF",X"0D",X"FF", + X"13",X"FF",X"19",X"FF",X"1F",X"FE",X"26",X"FD",X"2C",X"FC",X"32",X"FB",X"38",X"FA",X"3E",X"F8", + X"44",X"F7",X"4A",X"F5",X"50",X"F3",X"56",X"F1",X"5C",X"EF",X"62",X"ED",X"68",X"EA",X"6D",X"E7", + X"73",X"E5",X"79",X"E2",X"7E",X"DF",X"84",X"DC",X"89",X"D8",X"8E",X"D5",X"93",X"D1",X"99",X"CE", + X"9E",X"CA",X"A2",X"C6",X"A7",X"C2",X"AC",X"BE",X"B1",X"B9",X"B5",X"B5",X"B9",X"B1",X"BE",X"AC", + X"C2",X"A7",X"C6",X"A2",X"CA",X"9E",X"CE",X"99",X"D1",X"93",X"D5",X"8E",X"D8",X"89",X"DC",X"84", + X"DF",X"7E",X"E2",X"79",X"E5",X"73",X"E7",X"6D",X"EA",X"68",X"ED",X"62",X"EF",X"5C",X"F1",X"56", + X"F3",X"50",X"F5",X"4A",X"F7",X"44",X"F8",X"3E",X"FA",X"38",X"FB",X"32",X"FC",X"2C",X"FD",X"26", + X"FE",X"1F",X"FF",X"19",X"FF",X"13",X"FF",X"0D",X"FF",X"06",X"FF",X"00",X"FF",X"06",X"FF",X"0D", + X"FF",X"13",X"FF",X"19",X"FE",X"1F",X"FD",X"26",X"FC",X"2C",X"FB",X"32",X"FA",X"38",X"F8",X"3E", + X"F7",X"44",X"F5",X"4A",X"F3",X"50",X"F1",X"56",X"EF",X"5C",X"ED",X"62",X"EA",X"68",X"E7",X"6D", + X"E5",X"73",X"E2",X"79",X"DF",X"7E",X"DC",X"84",X"D8",X"89",X"D5",X"8E",X"D1",X"93",X"CE",X"99", + X"CA",X"9E",X"C6",X"A2",X"C2",X"A7",X"BE",X"AC",X"B9",X"B1",X"B5",X"B5",X"B1",X"B9",X"AC",X"BE", + X"A7",X"C2",X"A2",X"C6",X"9E",X"CA",X"99",X"CE",X"93",X"D1",X"8E",X"D5",X"89",X"D8",X"84",X"DC", + X"7E",X"DF",X"79",X"E2",X"73",X"E5",X"6D",X"E7",X"68",X"EA",X"62",X"ED",X"5C",X"EF",X"56",X"F1", + X"50",X"F3",X"4A",X"F5",X"44",X"F7",X"3E",X"F8",X"38",X"FA",X"32",X"FB",X"2C",X"FC",X"26",X"FD", + X"1F",X"FE",X"19",X"FF",X"13",X"FF",X"0D",X"FF",X"06",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/loc_snd_rom.vhd b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/loc_snd_rom.vhd new file mode 100644 index 00000000..af226908 --- /dev/null +++ b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/loc_snd_rom.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity loc_snd_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of loc_snd_rom is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"21",X"00",X"20",X"06",X"00",X"C3",X"6A",X"01",X"32",X"00",X"50",X"3A",X"00",X"40",X"C9",X"FF", + X"32",X"00",X"70",X"3A",X"00",X"60",X"C9",X"FF",X"78",X"CF",X"79",X"32",X"00",X"40",X"C9",X"FF", + X"78",X"D7",X"79",X"32",X"00",X"60",X"C9",X"FF",X"87",X"85",X"6F",X"7C",X"CE",X"00",X"67",X"7E", + X"23",X"66",X"6F",X"E9",X"FF",X"FF",X"FF",X"FF",X"D9",X"08",X"CD",X"40",X"00",X"08",X"D9",X"C9", + X"3E",X"0E",X"CF",X"B7",X"28",X"0D",X"57",X"CB",X"BF",X"FE",X"2D",X"D0",X"CB",X"7A",X"28",X"29", + X"C3",X"70",X"00",X"21",X"00",X"20",X"06",X"0C",X"AF",X"77",X"23",X"10",X"FC",X"C9",X"21",X"00", + X"20",X"06",X"06",X"0E",X"07",X"BE",X"28",X"05",X"23",X"23",X"10",X"F9",X"41",X"79",X"90",X"C9", + X"CD",X"5E",X"00",X"C8",X"AF",X"77",X"23",X"77",X"C9",X"32",X"17",X"20",X"CD",X"5E",X"00",X"28", + X"04",X"23",X"36",X"00",X"C9",X"AF",X"CD",X"5E",X"00",X"28",X"08",X"3A",X"17",X"20",X"77",X"23", + X"36",X"00",X"C9",X"CD",X"EF",X"00",X"CD",X"1A",X"01",X"B7",X"28",X"2D",X"3A",X"15",X"20",X"B7", + X"28",X"1F",X"3A",X"16",X"20",X"21",X"06",X"20",X"CD",X"DE",X"00",X"CD",X"E6",X"00",X"57",X"3A", + X"15",X"20",X"21",X"00",X"20",X"CD",X"DE",X"00",X"CD",X"E6",X"00",X"BA",X"F2",X"C1",X"00",X"18", + X"08",X"3A",X"16",X"20",X"21",X"06",X"20",X"18",X"06",X"3A",X"15",X"20",X"21",X"00",X"20",X"B7", + X"C8",X"3D",X"87",X"4F",X"06",X"00",X"09",X"3A",X"17",X"20",X"77",X"23",X"70",X"C9",X"3D",X"87", + X"4F",X"06",X"00",X"09",X"7E",X"C9",X"21",X"F6",X"0C",X"06",X"00",X"4F",X"09",X"7E",X"C9",X"3A", + X"00",X"20",X"CD",X"E6",X"00",X"32",X"11",X"20",X"3A",X"02",X"20",X"CD",X"E6",X"00",X"32",X"12", + X"20",X"3A",X"04",X"20",X"CD",X"E6",X"00",X"32",X"13",X"20",X"3A",X"17",X"20",X"CD",X"E6",X"00", + X"32",X"14",X"20",X"CD",X"45",X"01",X"32",X"15",X"20",X"C9",X"3A",X"06",X"20",X"CD",X"E6",X"00", + X"32",X"11",X"20",X"3A",X"08",X"20",X"CD",X"E6",X"00",X"32",X"12",X"20",X"3A",X"0A",X"20",X"CD", + X"E6",X"00",X"32",X"13",X"20",X"3A",X"17",X"20",X"CD",X"E6",X"00",X"32",X"14",X"20",X"CD",X"45", + X"01",X"32",X"16",X"20",X"C9",X"21",X"11",X"20",X"3A",X"14",X"20",X"06",X"03",X"4F",X"7E",X"B9", + X"F2",X"54",X"01",X"4F",X"23",X"10",X"F7",X"79",X"06",X"03",X"0E",X"01",X"21",X"11",X"20",X"BE", + X"28",X"06",X"0C",X"23",X"10",X"F9",X"0E",X"00",X"79",X"C9",X"70",X"23",X"7C",X"FE",X"24",X"20", + X"F9",X"F9",X"ED",X"56",X"21",X"00",X"30",X"22",X"0C",X"20",X"77",X"01",X"3F",X"07",X"DF",X"E7", + X"32",X"0E",X"20",X"32",X"0F",X"20",X"CD",X"7C",X"02",X"CD",X"80",X"02",X"CD",X"84",X"02",X"CD", + X"8A",X"02",X"CD",X"8E",X"02",X"CD",X"92",X"02",X"FB",X"3E",X"0F",X"CF",X"E6",X"40",X"20",X"F9", + X"3E",X"0F",X"CF",X"E6",X"40",X"28",X"F9",X"F3",X"3E",X"01",X"32",X"10",X"20",X"3A",X"01",X"20", + X"B7",X"3A",X"00",X"20",X"CA",X"BC",X"01",X"CD",X"64",X"02",X"18",X"03",X"CD",X"4A",X"02",X"FB", + X"00",X"00",X"F3",X"3E",X"02",X"32",X"10",X"20",X"3A",X"03",X"20",X"B7",X"3A",X"02",X"20",X"CA", + X"D7",X"01",X"CD",X"64",X"02",X"18",X"03",X"CD",X"4A",X"02",X"FB",X"00",X"00",X"F3",X"3E",X"03", + X"32",X"10",X"20",X"3A",X"05",X"20",X"B7",X"3A",X"04",X"20",X"CA",X"F2",X"01",X"CD",X"64",X"02", + X"18",X"03",X"CD",X"4A",X"02",X"FB",X"00",X"00",X"F3",X"3E",X"04",X"32",X"10",X"20",X"3A",X"07", + X"20",X"B7",X"3A",X"06",X"20",X"CA",X"0D",X"02",X"CD",X"64",X"02",X"18",X"03",X"CD",X"4A",X"02", + X"FB",X"00",X"00",X"F3",X"3E",X"05",X"32",X"10",X"20",X"3A",X"09",X"20",X"B7",X"3A",X"08",X"20", + X"CA",X"28",X"02",X"CD",X"64",X"02",X"18",X"03",X"CD",X"4A",X"02",X"FB",X"00",X"00",X"F3",X"3E", + X"06",X"32",X"10",X"20",X"3A",X"0B",X"20",X"B7",X"3A",X"0A",X"20",X"CA",X"44",X"02",X"CD",X"64", + X"02",X"C3",X"98",X"01",X"CD",X"4A",X"02",X"C3",X"98",X"01",X"21",X"23",X"0D",X"EF",X"B7",X"20", + X"1B",X"E5",X"21",X"01",X"20",X"3A",X"10",X"20",X"3D",X"87",X"D5",X"5F",X"16",X"00",X"19",X"D1", + X"36",X"01",X"E1",X"C9",X"B7",X"C8",X"21",X"7D",X"0D",X"EF",X"B7",X"C8",X"21",X"00",X"20",X"3A", + X"10",X"20",X"3D",X"4F",X"06",X"00",X"09",X"09",X"70",X"23",X"70",X"C9",X"06",X"08",X"18",X"06", + X"06",X"09",X"18",X"02",X"06",X"0A",X"0E",X"00",X"DF",X"C9",X"06",X"08",X"18",X"06",X"06",X"09", + X"18",X"02",X"06",X"0A",X"0E",X"00",X"E7",X"C9",X"3A",X"10",X"20",X"3D",X"21",X"A2",X"02",X"EF", + X"AF",X"C9",X"AE",X"02",X"B7",X"02",X"C0",X"02",X"C9",X"02",X"D2",X"02",X"DB",X"02",X"CD",X"7C", + X"02",X"0E",X"09",X"CD",X"E4",X"02",X"C9",X"CD",X"80",X"02",X"0E",X"12",X"CD",X"E4",X"02",X"C9", + X"CD",X"84",X"02",X"0E",X"24",X"CD",X"E4",X"02",X"C9",X"CD",X"8A",X"02",X"0E",X"09",X"CD",X"F0", + X"02",X"C9",X"CD",X"8E",X"02",X"0E",X"12",X"CD",X"F0",X"02",X"C9",X"CD",X"92",X"02",X"0E",X"24", + X"CD",X"F0",X"02",X"C9",X"3A",X"0E",X"20",X"B1",X"32",X"0E",X"20",X"06",X"07",X"4F",X"DF",X"C9", + X"3A",X"0F",X"20",X"B1",X"32",X"0F",X"20",X"06",X"07",X"4F",X"E7",X"C9",X"06",X"06",X"3A",X"10", + X"20",X"FE",X"04",X"FA",X"08",X"03",X"E7",X"C9",X"DF",X"C9",X"3A",X"0E",X"20",X"A0",X"B1",X"32", + X"0E",X"20",X"4F",X"06",X"07",X"DF",X"C9",X"3A",X"0F",X"20",X"A0",X"B1",X"32",X"0F",X"20",X"4F", + X"06",X"07",X"E7",X"C9",X"3A",X"10",X"20",X"3D",X"21",X"2D",X"03",X"EF",X"C9",X"39",X"03",X"40", + X"03",X"47",X"03",X"4E",X"03",X"55",X"03",X"5C",X"03",X"01",X"08",X"FE",X"CD",X"0A",X"03",X"C9", + X"01",X"10",X"FD",X"CD",X"0A",X"03",X"C9",X"01",X"20",X"FB",X"CD",X"0A",X"03",X"C9",X"01",X"08", + X"FE",X"CD",X"17",X"03",X"C9",X"01",X"10",X"FD",X"CD",X"17",X"03",X"C9",X"01",X"20",X"FB",X"CD", + X"17",X"03",X"C9",X"3A",X"10",X"20",X"3D",X"21",X"6C",X"03",X"EF",X"C9",X"78",X"03",X"7F",X"03", + X"86",X"03",X"8D",X"03",X"94",X"03",X"9B",X"03",X"01",X"01",X"F7",X"CD",X"0A",X"03",X"C9",X"01", + X"02",X"EF",X"CD",X"0A",X"03",X"C9",X"01",X"04",X"DF",X"CD",X"0A",X"03",X"C9",X"01",X"01",X"F7", + X"CD",X"17",X"03",X"C9",X"01",X"02",X"EF",X"CD",X"17",X"03",X"C9",X"01",X"04",X"DF",X"CD",X"17", + X"03",X"C9",X"3A",X"10",X"20",X"3D",X"21",X"AB",X"03",X"EF",X"C9",X"B7",X"03",X"BE",X"03",X"C5", + X"03",X"CC",X"03",X"D3",X"03",X"DA",X"03",X"01",X"00",X"F6",X"CD",X"0A",X"03",X"C9",X"01",X"00", + X"ED",X"CD",X"0A",X"03",X"C9",X"01",X"00",X"DB",X"CD",X"0A",X"03",X"C9",X"01",X"00",X"F6",X"CD", + X"17",X"03",X"C9",X"01",X"00",X"ED",X"CD",X"17",X"03",X"C9",X"01",X"00",X"DB",X"CD",X"17",X"03", + X"C9",X"3A",X"10",X"20",X"FE",X"04",X"30",X"05",X"C6",X"07",X"47",X"DF",X"C9",X"C6",X"04",X"47", + X"E7",X"C9",X"3A",X"10",X"20",X"FE",X"04",X"30",X"09",X"3D",X"87",X"47",X"4D",X"DF",X"4C",X"04", + X"DF",X"C9",X"D6",X"04",X"87",X"47",X"4D",X"E7",X"4C",X"04",X"E7",X"C9",X"FE",X"04",X"D0",X"F5", + X"CD",X"5C",X"04",X"F1",X"B7",X"20",X"02",X"77",X"C9",X"21",X"2C",X"04",X"87",X"87",X"4F",X"87", + X"81",X"4F",X"06",X"00",X"09",X"3A",X"10",X"20",X"3D",X"EF",X"77",X"C9",X"7F",X"04",X"84",X"04", + X"89",X"04",X"8E",X"04",X"93",X"04",X"98",X"04",X"9D",X"04",X"A2",X"04",X"A7",X"04",X"AC",X"04", + X"B1",X"04",X"B6",X"04",X"BB",X"04",X"C0",X"04",X"C5",X"04",X"CA",X"04",X"CF",X"04",X"D4",X"04", + X"D9",X"04",X"DE",X"04",X"E3",X"04",X"E8",X"04",X"ED",X"04",X"F2",X"04",X"21",X"2C",X"04",X"3A", + X"10",X"20",X"3D",X"EF",X"C9",X"2A",X"0C",X"20",X"7B",X"A5",X"6F",X"7A",X"A4",X"67",X"22",X"0C", + X"20",X"C9",X"2A",X"0C",X"20",X"7B",X"B5",X"6F",X"7A",X"B4",X"67",X"22",X"0C",X"20",X"C9",X"11", + X"3F",X"FF",X"18",X"E1",X"11",X"FF",X"FC",X"18",X"DC",X"11",X"FF",X"F3",X"18",X"D7",X"11",X"FC", + X"FF",X"18",X"D2",X"11",X"F3",X"FF",X"18",X"CD",X"11",X"CF",X"FF",X"18",X"C8",X"11",X"80",X"00", + X"18",X"D0",X"11",X"00",X"02",X"18",X"CB",X"11",X"00",X"08",X"18",X"C6",X"11",X"02",X"00",X"18", + X"C1",X"11",X"08",X"00",X"18",X"BC",X"11",X"20",X"00",X"18",X"B7",X"11",X"40",X"00",X"18",X"B2", + X"11",X"00",X"01",X"18",X"AD",X"11",X"00",X"04",X"18",X"A8",X"11",X"01",X"00",X"18",X"A3",X"11", + X"04",X"00",X"18",X"9E",X"11",X"10",X"00",X"18",X"99",X"11",X"C0",X"00",X"18",X"94",X"11",X"00", + X"03",X"18",X"8F",X"11",X"00",X"0C",X"18",X"8A",X"11",X"03",X"00",X"18",X"85",X"11",X"0C",X"00", + X"18",X"80",X"11",X"30",X"00",X"C3",X"72",X"04",X"DD",X"7E",X"00",X"32",X"37",X"20",X"FE",X"FF", + X"C8",X"CD",X"06",X"05",X"AF",X"C9",X"DD",X"35",X"01",X"C0",X"3A",X"32",X"20",X"DD",X"77",X"01", + X"DD",X"CB",X"00",X"46",X"C2",X"29",X"05",X"DD",X"7E",X"07",X"D6",X"01",X"FA",X"29",X"05",X"DD", + X"77",X"07",X"32",X"34",X"20",X"4F",X"CD",X"E1",X"03",X"DD",X"35",X"00",X"C0",X"DD",X"6E",X"02", + X"DD",X"66",X"03",X"7E",X"47",X"E6",X"1F",X"CA",X"C1",X"05",X"FE",X"1F",X"C2",X"D8",X"05",X"23", + X"DD",X"75",X"02",X"DD",X"74",X"03",X"78",X"E6",X"E0",X"0F",X"0F",X"0F",X"0F",X"4F",X"06",X"00", + X"21",X"59",X"05",X"09",X"5E",X"23",X"56",X"EB",X"E9",X"69",X"05",X"87",X"05",X"9D",X"05",X"B7", + X"05",X"B7",X"05",X"B7",X"05",X"B7",X"05",X"B7",X"05",X"DD",X"6E",X"02",X"DD",X"66",X"03",X"4E", + X"CB",X"21",X"06",X"00",X"21",X"11",X"06",X"09",X"5E",X"23",X"56",X"ED",X"53",X"30",X"20",X"DD", + X"73",X"04",X"DD",X"72",X"05",X"18",X"20",X"DD",X"6E",X"02",X"DD",X"66",X"03",X"4E",X"06",X"00", + X"21",X"A9",X"06",X"09",X"7E",X"32",X"32",X"20",X"DD",X"77",X"01",X"18",X"0A",X"DD",X"6E",X"02", + X"DD",X"66",X"03",X"7E",X"DD",X"77",X"06",X"DD",X"6E",X"02",X"DD",X"66",X"03",X"23",X"DD",X"75", + X"02",X"DD",X"74",X"03",X"C3",X"2D",X"05",X"0E",X"00",X"CD",X"E1",X"03",X"DD",X"36",X"00",X"FF", + X"C9",X"CD",X"C6",X"05",X"18",X"3D",X"78",X"E6",X"E0",X"07",X"07",X"07",X"47",X"3E",X"01",X"18", + X"01",X"07",X"10",X"FD",X"DD",X"77",X"00",X"C9",X"C5",X"CD",X"C6",X"05",X"C1",X"78",X"E6",X"1F", + X"3D",X"07",X"4F",X"06",X"00",X"DD",X"6E",X"04",X"DD",X"66",X"05",X"09",X"5E",X"23",X"56",X"EB", + X"22",X"35",X"20",X"CD",X"F2",X"03",X"DD",X"4E",X"06",X"79",X"DD",X"77",X"07",X"32",X"34",X"20", + X"CD",X"E1",X"03",X"DD",X"6E",X"02",X"DD",X"66",X"03",X"23",X"DD",X"75",X"02",X"DD",X"74",X"03", + X"C9",X"31",X"06",X"35",X"06",X"39",X"06",X"3D",X"06",X"41",X"06",X"45",X"06",X"49",X"06",X"4D", + X"06",X"51",X"06",X"55",X"06",X"59",X"06",X"5D",X"06",X"61",X"06",X"65",X"06",X"69",X"06",X"6D", + X"06",X"6B",X"08",X"F2",X"07",X"80",X"07",X"14",X"07",X"AE",X"06",X"4E",X"06",X"F3",X"05",X"9E", + X"05",X"4E",X"05",X"01",X"05",X"B9",X"04",X"76",X"04",X"36",X"04",X"F9",X"03",X"C0",X"03",X"8A", + X"03",X"57",X"03",X"27",X"03",X"FA",X"02",X"CF",X"02",X"A7",X"02",X"81",X"02",X"5D",X"02",X"3B", + X"02",X"1B",X"02",X"FD",X"01",X"E0",X"01",X"C5",X"01",X"AC",X"01",X"94",X"01",X"7D",X"01",X"68", + X"01",X"53",X"01",X"40",X"01",X"2E",X"01",X"1D",X"01",X"0D",X"01",X"FE",X"00",X"F0",X"00",X"E3", + X"00",X"D6",X"00",X"CA",X"00",X"BE",X"00",X"B4",X"00",X"AA",X"00",X"A0",X"00",X"97",X"00",X"8F", + X"00",X"87",X"00",X"7F",X"00",X"78",X"00",X"71",X"00",X"6B",X"00",X"65",X"00",X"5F",X"00",X"5A", + X"00",X"55",X"00",X"50",X"00",X"4C",X"00",X"47",X"00",X"46",X"3F",X"38",X"31",X"2B",X"26",X"21", + X"1C",X"18",X"15",X"12",X"0F",X"0D",X"0C",X"0B",X"0A",X"AF",X"32",X"37",X"20",X"21",X"EF",X"06", + X"11",X"18",X"20",X"01",X"18",X"00",X"ED",X"B0",X"3A",X"33",X"20",X"07",X"4F",X"07",X"81",X"4F", + X"06",X"00",X"21",X"07",X"0E",X"09",X"11",X"1A",X"20",X"CD",X"E5",X"06",X"11",X"22",X"20",X"CD", + X"E5",X"06",X"11",X"2A",X"20",X"7E",X"12",X"CD",X"EC",X"06",X"7E",X"12",X"23",X"13",X"C9",X"01", + X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"01", + X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"3E",X"1E",X"C3",X"4F",X"07",X"3E",X"1D",X"C3",X"4F", + X"07",X"3E",X"1C",X"C3",X"4F",X"07",X"3E",X"1B",X"C3",X"4F",X"07",X"3E",X"1A",X"C3",X"4F",X"07", + X"3E",X"19",X"C3",X"4F",X"07",X"3E",X"18",X"C3",X"4F",X"07",X"3E",X"17",X"C3",X"4F",X"07",X"3E", + X"16",X"C3",X"4F",X"07",X"3E",X"15",X"C3",X"4F",X"07",X"3E",X"14",X"C3",X"4F",X"07",X"3E",X"13", + X"C3",X"4F",X"07",X"3E",X"12",X"C3",X"4F",X"07",X"3E",X"11",X"C3",X"4F",X"07",X"3E",X"10",X"32", + X"49",X"20",X"3E",X"FF",X"C9",X"3E",X"01",X"CD",X"0C",X"04",X"CD",X"24",X"03",X"21",X"00",X"05", + X"22",X"3B",X"20",X"CD",X"F2",X"03",X"3E",X"0A",X"32",X"3A",X"20",X"4F",X"CD",X"E1",X"03",X"3E", + X"40",X"32",X"38",X"20",X"3E",X"F0",X"32",X"39",X"20",X"AF",X"32",X"3D",X"20",X"C9",X"21",X"3D", + X"20",X"35",X"7E",X"E6",X"01",X"20",X"36",X"21",X"38",X"20",X"35",X"7E",X"57",X"20",X"0A",X"36", + X"40",X"21",X"3A",X"20",X"35",X"4E",X"CD",X"E1",X"03",X"2A",X"3B",X"20",X"CB",X"62",X"3A",X"39", + X"20",X"06",X"FF",X"20",X"05",X"04",X"ED",X"44",X"CB",X"3F",X"4F",X"09",X"22",X"3B",X"20",X"CD", + X"F2",X"03",X"7A",X"E6",X"1F",X"20",X"06",X"21",X"39",X"20",X"34",X"28",X"02",X"AF",X"C9",X"3D", + X"C9",X"3E",X"01",X"CD",X"0C",X"04",X"CD",X"24",X"03",X"21",X"60",X"00",X"22",X"40",X"20",X"CD", + X"F2",X"03",X"3E",X"0C",X"32",X"3F",X"20",X"4F",X"CD",X"E1",X"03",X"3E",X"20",X"32",X"3E",X"20", + X"AF",X"C9",X"3A",X"3D",X"20",X"E6",X"01",X"C8",X"21",X"3E",X"20",X"35",X"28",X"17",X"7E",X"2A", + X"40",X"20",X"FE",X"18",X"01",X"E8",X"FF",X"38",X"03",X"01",X"08",X"00",X"09",X"22",X"40",X"20", + X"CD",X"F2",X"03",X"AF",X"C9",X"36",X"20",X"21",X"60",X"00",X"22",X"40",X"20",X"CD",X"F2",X"03", + X"21",X"3F",X"20",X"35",X"28",X"06",X"4E",X"CD",X"E1",X"03",X"AF",X"C9",X"3D",X"C9",X"3E",X"01", + X"CD",X"0C",X"04",X"CD",X"24",X"03",X"21",X"00",X"01",X"22",X"45",X"20",X"CD",X"F2",X"03",X"0E", + X"0C",X"CD",X"E1",X"03",X"AF",X"32",X"42",X"20",X"32",X"43",X"20",X"C9",X"3A",X"3D",X"20",X"E6", + X"01",X"C8",X"21",X"43",X"20",X"35",X"7E",X"28",X"21",X"57",X"FE",X"DC",X"28",X"2A",X"38",X"30", + X"FE",X"E8",X"28",X"18",X"2A",X"45",X"20",X"3A",X"42",X"20",X"C6",X"9D",X"32",X"42",X"20",X"AA", + X"AD",X"6F",X"22",X"45",X"20",X"CD",X"F2",X"03",X"AF",X"C9",X"3D",X"C9",X"3E",X"0F",X"32",X"44", + X"20",X"4F",X"CD",X"E1",X"03",X"C3",X"54",X"08",X"3E",X"02",X"CD",X"0C",X"04",X"C3",X"54",X"08", + X"E6",X"0F",X"20",X"D0",X"23",X"35",X"4E",X"CD",X"E1",X"03",X"C3",X"54",X"08",X"3E",X"02",X"CD", + X"0C",X"04",X"CD",X"63",X"03",X"3E",X"01",X"32",X"47",X"20",X"3E",X"0B",X"32",X"4A",X"20",X"4F", + X"CD",X"E1",X"03",X"AF",X"32",X"48",X"20",X"32",X"4B",X"20",X"C9",X"21",X"4B",X"20",X"35",X"7E", + X"E6",X"01",X"C8",X"21",X"47",X"20",X"35",X"20",X"2D",X"3A",X"49",X"20",X"CB",X"3F",X"CB",X"3F", + X"77",X"21",X"48",X"20",X"35",X"7E",X"E6",X"1F",X"16",X"0B",X"28",X"12",X"16",X"F2",X"FE",X"18", + X"28",X"0C",X"3A",X"4A",X"20",X"57",X"CB",X"56",X"3E",X"FF",X"28",X"02",X"ED",X"44",X"82",X"32", + X"4A",X"20",X"4F",X"CD",X"E1",X"03",X"3A",X"49",X"20",X"4F",X"CD",X"FC",X"02",X"AF",X"C9",X"3E", + X"01",X"CD",X"0C",X"04",X"CD",X"24",X"03",X"0E",X"0A",X"CD",X"E1",X"03",X"21",X"00",X"00",X"CD", + X"F2",X"03",X"3E",X"0F",X"32",X"4C",X"20",X"32",X"4D",X"20",X"AF",X"C9",X"21",X"4C",X"20",X"35", + X"7E",X"E6",X"0F",X"21",X"4D",X"20",X"20",X"03",X"35",X"28",X"E1",X"BE",X"21",X"F0",X"00",X"38", + X"02",X"2E",X"00",X"CD",X"F2",X"03",X"AF",X"C9",X"3E",X"03",X"CD",X"0C",X"04",X"CD",X"24",X"03", + X"0E",X"0B",X"CD",X"E1",X"03",X"21",X"FF",X"02",X"7D",X"32",X"4E",X"20",X"32",X"4F",X"20",X"CD", + X"F2",X"03",X"3E",X"08",X"32",X"50",X"20",X"AF",X"32",X"51",X"20",X"C9",X"21",X"51",X"20",X"35", + X"7E",X"E6",X"03",X"20",X"19",X"21",X"50",X"20",X"3A",X"4F",X"20",X"57",X"B7",X"3A",X"4E",X"20", + X"28",X"0E",X"96",X"38",X"0F",X"32",X"4E",X"20",X"6F",X"26",X"02",X"CD",X"F2",X"03",X"AF",X"C9", + X"86",X"C3",X"63",X"09",X"7A",X"2F",X"32",X"4F",X"20",X"7E",X"3C",X"FE",X"3E",X"30",X"EF",X"77", + X"AF",X"C9",X"3E",X"01",X"CD",X"0C",X"04",X"CD",X"24",X"03",X"0E",X"00",X"CD",X"E1",X"03",X"3E", + X"03",X"21",X"56",X"20",X"77",X"2C",X"77",X"21",X"A0",X"00",X"22",X"54",X"20",X"3E",X"0A",X"32", + X"53",X"20",X"3E",X"58",X"32",X"52",X"20",X"AF",X"C9",X"21",X"56",X"20",X"35",X"7E",X"2C",X"A6", + X"20",X"28",X"21",X"52",X"20",X"35",X"28",X"DF",X"7E",X"57",X"E6",X"0F",X"20",X"09",X"21",X"53", + X"20",X"35",X"35",X"4E",X"CD",X"E1",X"03",X"2A",X"54",X"20",X"CB",X"42",X"3E",X"0C",X"28",X"02", + X"ED",X"44",X"85",X"6F",X"22",X"54",X"20",X"CD",X"F2",X"03",X"AF",X"C9",X"3E",X"01",X"32",X"57", + X"20",X"3E",X"FF",X"C9",X"3E",X"01",X"CD",X"0C",X"04",X"CD",X"24",X"03",X"21",X"00",X"00",X"22", + X"5C",X"20",X"CD",X"F2",X"03",X"3E",X"0F",X"32",X"5A",X"20",X"4F",X"CD",X"E1",X"03",X"3E",X"02", + X"32",X"59",X"20",X"AF",X"32",X"58",X"20",X"32",X"5B",X"20",X"32",X"5E",X"20",X"C9",X"21",X"5E", + X"20",X"35",X"7E",X"E6",X"01",X"C8",X"21",X"58",X"20",X"35",X"7E",X"57",X"20",X"04",X"2C",X"35", + X"28",X"28",X"E6",X"1F",X"20",X"08",X"21",X"5A",X"20",X"35",X"4E",X"CD",X"E1",X"03",X"2A",X"5C", + X"20",X"3A",X"5B",X"20",X"C6",X"C5",X"32",X"5B",X"20",X"AA",X"AD",X"6F",X"67",X"1F",X"38",X"02", + X"26",X"01",X"22",X"5C",X"20",X"CD",X"F2",X"03",X"AF",X"C9",X"3D",X"C9",X"AF",X"CD",X"0C",X"04", + X"CD",X"24",X"03",X"21",X"20",X"00",X"22",X"61",X"20",X"CD",X"F2",X"03",X"0E",X"09",X"CD",X"E1", + X"03",X"3E",X"20",X"32",X"5F",X"20",X"3E",X"1E",X"32",X"60",X"20",X"AF",X"C9",X"3A",X"5E",X"20", + X"E6",X"01",X"20",X"1C",X"21",X"5F",X"20",X"35",X"7E",X"28",X"17",X"2C",X"BE",X"38",X"11",X"0E", + X"00",X"28",X"18",X"2A",X"61",X"20",X"01",X"0C",X"00",X"09",X"22",X"61",X"20",X"CD",X"F2",X"03", + X"AF",X"C9",X"36",X"20",X"2C",X"35",X"35",X"28",X"07",X"0E",X"09",X"CD",X"E1",X"03",X"AF",X"C9", + X"3D",X"C9",X"3E",X"01",X"CD",X"0C",X"04",X"CD",X"24",X"03",X"21",X"20",X"00",X"CD",X"F2",X"03", + X"3E",X"08",X"32",X"64",X"20",X"4F",X"CD",X"E1",X"03",X"3E",X"01",X"32",X"65",X"20",X"AF",X"32", + X"63",X"20",X"C9",X"21",X"63",X"20",X"35",X"7E",X"E6",X"3F",X"4F",X"28",X"19",X"FE",X"0C",X"20", + X"18",X"21",X"65",X"20",X"3A",X"64",X"20",X"86",X"28",X"11",X"32",X"64",X"20",X"FE",X"0F",X"4F", + X"20",X"04",X"7E",X"ED",X"44",X"77",X"CD",X"E1",X"03",X"AF",X"C9",X"3D",X"C9",X"3E",X"01",X"CD", + X"0C",X"04",X"CD",X"24",X"03",X"21",X"00",X"01",X"CD",X"F2",X"03",X"3E",X"E0",X"32",X"67",X"20", + X"32",X"69",X"20",X"32",X"66",X"20",X"3E",X"0C",X"32",X"68",X"20",X"4F",X"CD",X"E1",X"03",X"AF", + X"C9",X"21",X"69",X"20",X"35",X"7E",X"E6",X"01",X"C8",X"21",X"67",X"20",X"35",X"7E",X"28",X"2B", + X"57",X"E6",X"07",X"20",X"13",X"7A",X"FE",X"60",X"28",X"DC",X"FE",X"80",X"28",X"D8",X"FE",X"C0", + X"28",X"D4",X"2C",X"35",X"4E",X"CD",X"E1",X"03",X"3A",X"66",X"20",X"C6",X"9B",X"32",X"66",X"20", + X"AA",X"6F",X"17",X"9F",X"3C",X"67",X"CD",X"F2",X"03",X"AF",X"C9",X"3D",X"C9",X"3E",X"01",X"CD", + X"0C",X"04",X"CD",X"24",X"03",X"21",X"50",X"01",X"CD",X"F2",X"03",X"3E",X"07",X"32",X"6C",X"20", + X"4F",X"CD",X"E1",X"03",X"3E",X"80",X"32",X"6A",X"20",X"AF",X"32",X"6B",X"20",X"32",X"6D",X"20", + X"C9",X"21",X"6D",X"20",X"35",X"7E",X"E6",X"01",X"C8",X"21",X"6B",X"20",X"35",X"7E",X"28",X"2F", + X"FE",X"C0",X"38",X"17",X"E6",X"07",X"20",X"13",X"3A",X"6A",X"20",X"D6",X"0A",X"32",X"6A",X"20", + X"3A",X"6C",X"20",X"3C",X"32",X"6C",X"20",X"4F",X"CD",X"E1",X"03",X"7E",X"E6",X"03",X"07",X"07", + X"07",X"07",X"57",X"3A",X"6A",X"20",X"92",X"6F",X"26",X"01",X"CD",X"F2",X"03",X"AF",X"C9",X"3D", + X"C9",X"3E",X"01",X"CD",X"0C",X"04",X"CD",X"24",X"03",X"21",X"38",X"01",X"CD",X"F2",X"03",X"3E", + X"04",X"32",X"70",X"20",X"4F",X"CD",X"E1",X"03",X"3E",X"68",X"32",X"6E",X"20",X"AF",X"32",X"6F", + X"20",X"32",X"71",X"20",X"C9",X"21",X"71",X"20",X"35",X"7E",X"E6",X"01",X"C8",X"21",X"6F",X"20", + X"35",X"7E",X"28",X"2F",X"FE",X"C0",X"38",X"17",X"E6",X"07",X"20",X"13",X"3A",X"6E",X"20",X"D6", + X"0A",X"32",X"6E",X"20",X"3A",X"70",X"20",X"3C",X"32",X"70",X"20",X"4F",X"CD",X"E1",X"03",X"7E", + X"E6",X"03",X"07",X"07",X"07",X"07",X"57",X"3A",X"6E",X"20",X"92",X"6F",X"26",X"01",X"CD",X"F2", + X"03",X"AF",X"C9",X"3D",X"C9",X"3E",X"00",X"CD",X"0C",X"04",X"CD",X"24",X"03",X"21",X"00",X"00", + X"22",X"75",X"20",X"CD",X"F2",X"03",X"AF",X"32",X"74",X"20",X"4F",X"CD",X"E1",X"03",X"AF",X"32", + X"72",X"20",X"32",X"73",X"20",X"32",X"77",X"20",X"C9",X"21",X"77",X"20",X"35",X"7E",X"E6",X"01", + X"C8",X"21",X"73",X"20",X"35",X"7E",X"28",X"29",X"57",X"FE",X"D0",X"28",X"3A",X"38",X"51",X"FE", + X"E0",X"28",X"20",X"38",X"25",X"2C",X"34",X"4E",X"CD",X"E1",X"03",X"2A",X"75",X"20",X"3A",X"72", + X"20",X"C6",X"9D",X"32",X"72",X"20",X"AA",X"AD",X"6F",X"22",X"75",X"20",X"CD",X"F2",X"03",X"AF", + X"C9",X"3D",X"C9",X"21",X"10",X"00",X"CD",X"F2",X"03",X"7A",X"E6",X"02",X"0E",X"00",X"28",X"02", + X"0E",X"0F",X"CD",X"E1",X"03",X"AF",X"C9",X"3E",X"01",X"CD",X"0C",X"04",X"21",X"70",X"00",X"22", + X"75",X"20",X"CD",X"F2",X"03",X"3E",X"05",X"32",X"74",X"20",X"4F",X"CD",X"E1",X"03",X"AF",X"C9", + X"E6",X"3F",X"20",X"06",X"2C",X"35",X"4E",X"CD",X"E1",X"03",X"2A",X"75",X"20",X"CB",X"52",X"3E", + X"01",X"28",X"02",X"ED",X"44",X"85",X"6F",X"CD",X"F2",X"03",X"AF",X"C9",X"3E",X"01",X"CD",X"0C", + X"04",X"CD",X"24",X"03",X"21",X"00",X"01",X"CD",X"F2",X"03",X"3E",X"0F",X"32",X"79",X"20",X"4F", + X"CD",X"E1",X"03",X"AF",X"32",X"78",X"20",X"C9",X"21",X"78",X"20",X"35",X"7E",X"E6",X"3F",X"FE", + X"0C",X"0E",X"00",X"28",X"0A",X"B7",X"20",X"0A",X"21",X"79",X"20",X"35",X"28",X"06",X"4E",X"CD", + X"E1",X"03",X"AF",X"C9",X"3D",X"C9",X"00",X"10",X"0F",X"0E",X"0D",X"0C",X"0B",X"0A",X"09",X"08", + X"07",X"06",X"05",X"04",X"03",X"02",X"01",X"2C",X"2B",X"2A",X"29",X"28",X"27",X"26",X"25",X"24", + X"23",X"22",X"21",X"20",X"1F",X"1E",X"1D",X"1C",X"1B",X"1A",X"19",X"18",X"17",X"16",X"15",X"14", + X"13",X"12",X"11",X"98",X"02",X"55",X"07",X"C1",X"07",X"1E",X"08",X"8D",X"08",X"EF",X"08",X"28", + X"09",X"82",X"09",X"DC",X"09",X"E4",X"09",X"4C",X"0A",X"A2",X"0A",X"ED",X"0A",X"4D",X"0B",X"B1", + X"0B",X"15",X"0C",X"BC",X"0C",X"B9",X"0D",X"D0",X"0D",X"D0",X"0D",X"D0",X"0D",X"BE",X"0D",X"D0", + X"0D",X"D0",X"0D",X"C3",X"0D",X"D0",X"0D",X"D0",X"0D",X"C8",X"0D",X"D0",X"0D",X"D0",X"0D",X"07", + X"07",X"0C",X"07",X"11",X"07",X"16",X"07",X"1B",X"07",X"20",X"07",X"25",X"07",X"2A",X"07",X"2F", + X"07",X"34",X"07",X"39",X"07",X"3E",X"07",X"43",X"07",X"48",X"07",X"4D",X"07",X"00",X"00",X"7E", + X"07",X"E2",X"07",X"3C",X"08",X"AB",X"08",X"0C",X"09",X"4C",X"09",X"A9",X"09",X"00",X"00",X"0E", + X"0A",X"6D",X"0A",X"C3",X"0A",X"11",X"0B",X"71",X"0B",X"D5",X"0B",X"39",X"0C",X"D8",X"0C",X"D9", + X"0D",X"EE",X"0D",X"E0",X"0D",X"E7",X"0D",X"D9",X"0D",X"E0",X"0D",X"E7",X"0D",X"D9",X"0D",X"E0", + X"0D",X"E7",X"0D",X"D9",X"0D",X"E0",X"0D",X"E7",X"0D",X"3E",X"00",X"C3",X"CA",X"0D",X"3E",X"01", + X"C3",X"CA",X"0D",X"3E",X"02",X"C3",X"CA",X"0D",X"3E",X"03",X"32",X"33",X"20",X"CD",X"B9",X"06", + X"AF",X"CD",X"0C",X"04",X"CD",X"24",X"03",X"AF",X"C9",X"DD",X"21",X"18",X"20",X"C3",X"F8",X"04", + X"DD",X"21",X"20",X"20",X"C3",X"F8",X"04",X"DD",X"21",X"28",X"20",X"C3",X"F8",X"04",X"3A",X"37", + X"20",X"FE",X"FF",X"C8",X"3A",X"34",X"20",X"4F",X"CD",X"E1",X"03",X"2A",X"35",X"20",X"CB",X"3C", + X"CB",X"1D",X"CD",X"F2",X"03",X"AF",X"C9",X"1F",X"0E",X"3D",X"0E",X"72",X"0E",X"87",X"0E",X"B3", + X"0E",X"DD",X"0E",X"F2",X"0E",X"21",X"0F",X"4E",X"0F",X"62",X"0F",X"AC",X"0F",X"CF",X"0F",X"1F", + X"0F",X"5F",X"09",X"3F",X"0A",X"A6",X"80",X"81",X"86",X"60",X"61",X"86",X"60",X"68",X"3F",X"0B", + X"CA",X"C6",X"3F",X"0C",X"AB",X"80",X"8B",X"A6",X"A8",X"3F",X"0D",X"EA",X"FF",X"1F",X"03",X"5F", + X"07",X"80",X"76",X"76",X"80",X"76",X"76",X"80",X"76",X"76",X"80",X"76",X"76",X"80",X"76",X"76", + X"80",X"76",X"76",X"80",X"76",X"76",X"80",X"76",X"76",X"80",X"77",X"77",X"80",X"77",X"77",X"80", + X"77",X"77",X"80",X"77",X"77",X"80",X"76",X"76",X"80",X"76",X"76",X"80",X"76",X"76",X"80",X"76", + X"76",X"FF",X"1F",X"03",X"5F",X"08",X"A6",X"A1",X"A6",X"A1",X"A6",X"A1",X"A6",X"AA",X"AB",X"A6", + X"AB",X"AB",X"A6",X"A5",X"A3",X"A1",X"FF",X"1F",X"0E",X"3F",X"03",X"5F",X"09",X"38",X"38",X"38", + X"38",X"78",X"3A",X"5A",X"38",X"3A",X"5A",X"3D",X"38",X"38",X"38",X"38",X"78",X"36",X"56",X"35", + X"36",X"56",X"38",X"35",X"35",X"35",X"35",X"75",X"33",X"53",X"31",X"33",X"53",X"35",X"71",X"71", + X"71",X"60",X"FF",X"1F",X"0E",X"5F",X"09",X"35",X"35",X"35",X"35",X"75",X"36",X"56",X"35",X"36", + X"56",X"3A",X"35",X"35",X"35",X"35",X"75",X"33",X"53",X"31",X"33",X"53",X"35",X"31",X"31",X"31", + X"31",X"71",X"30",X"50",X"2E",X"30",X"50",X"31",X"6E",X"6E",X"6E",X"60",X"FF",X"1F",X"08",X"5F", + X"09",X"69",X"69",X"6A",X"6A",X"69",X"69",X"67",X"67",X"65",X"65",X"67",X"67",X"65",X"65",X"65", + X"60",X"FF",X"1F",X"0E",X"3F",X"0B",X"5F",X"09",X"8E",X"6E",X"6E",X"8E",X"6E",X"6E",X"90",X"70", + X"70",X"90",X"70",X"70",X"8E",X"6E",X"6E",X"8E",X"6E",X"6E",X"90",X"70",X"70",X"90",X"70",X"70", + X"92",X"72",X"72",X"93",X"73",X"73",X"B2",X"B0",X"8E",X"6E",X"6E",X"6E",X"72",X"6E",X"72",X"AE", + X"FF",X"1F",X"0E",X"5F",X"09",X"92",X"72",X"72",X"92",X"72",X"72",X"93",X"73",X"73",X"93",X"73", + X"73",X"92",X"72",X"72",X"92",X"72",X"72",X"93",X"73",X"73",X"93",X"73",X"73",X"95",X"75",X"75", + X"97",X"77",X"77",X"B5",X"B3",X"92",X"72",X"72",X"72",X"75",X"72",X"75",X"B2",X"FF",X"1F",X"02", + X"5F",X"08",X"AE",X"A0",X"B0",X"A0",X"AE",X"A0",X"B0",X"A0",X"B2",X"B3",X"B2",X"B0",X"B2",X"B2", + X"B2",X"FF",X"1F",X"0E",X"5F",X"09",X"3F",X"0B",X"69",X"66",X"82",X"82",X"62",X"64",X"66",X"67", + X"89",X"89",X"89",X"86",X"3F",X"0A",X"8B",X"8B",X"8B",X"60",X"69",X"8B",X"60",X"69",X"6B",X"6D", + X"6E",X"70",X"3F",X"09",X"92",X"1F",X"08",X"89",X"89",X"1F",X"0E",X"6E",X"69",X"3F",X"08",X"8E", + X"1F",X"08",X"89",X"89",X"1F",X"0E",X"69",X"66",X"3F",X"07",X"89",X"1F",X"08",X"89",X"89",X"1F", + X"0E",X"64",X"66",X"3F",X"06",X"82",X"1F",X"08",X"89",X"89",X"A0",X"FF",X"1F",X"08",X"5F",X"08", + X"80",X"82",X"89",X"89",X"89",X"82",X"89",X"89",X"89",X"82",X"8B",X"8B",X"8B",X"82",X"8B",X"8B", + X"8B",X"80",X"86",X"86",X"A0",X"86",X"86",X"A0",X"87",X"87",X"A0",X"86",X"86",X"A0",X"FF",X"1F", + X"08",X"5F",X"08",X"A0",X"86",X"86",X"86",X"80",X"86",X"86",X"86",X"80",X"87",X"87",X"87",X"80", + X"87",X"87",X"87",X"80",X"82",X"82",X"A0",X"82",X"82",X"A0",X"81",X"81",X"A0",X"82",X"82",X"A0", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/locomotn.zip b/Arcade_MiST/Namco Rally X Hardware/Locomotion_MiST/rtl/roms/locomotn.zip new file mode 100644 index 0000000000000000000000000000000000000000..89fa19e5841d55834fd3356856911022f1c57fbe GIT binary patch literal 21193 zcmYg%Qb2=jjCsh?l0APkK1&)89>H+f47XZyM zf^dBT5J21xXFvK~R-EaV?IK1@K?vm`HqeV^*#|J(8}kcBF5R9L!jH}6tt7Z4?4Eur zozGXm3jehkZjguzpbR`%4fdB10RRB(uT5hnI%5ad|1n92{z&%^{$sLRy*mzB5~1de z)7!wDmsEaGLBiz!ahT^D?mSxTtJ4&<0Zn2kZ3UR z3Lw&CCKY&N;G(CZ=K5|nke~x@3~R8XKdRT)ko z`a~TFpLC8`aIJm{2Yh(y;)yE6JNGiu92)SLVni>in+lHm`ZHKD#DXZrLY!JlT75 z#o2ShBsA~*Phap>PJ@-Z8}*RvaIYrQ*Zqv0z)s2*?sBT#JCFDa;K`hOf3M{{nIUlX zPMmQ5lZ3^v`M_kRO7DOQx9LuB9wIe_3l46K8Ye{CjRH0ZnsuKD7sSLSS84pBSn4-} z@8Y+DN8w;BXa_#Z6}$+kF&rm2cvO1Vd=M4u@NYh=wLbOyfgXYS?OH8`l2VLieJwvD z^Pe;s5s+-QwsBTIw1j*JQ6nZTMdMchgn6Kk038y^qJFRuV>@$Zf$M=fHEWi{kXNQ* zrYuM8%22{P=xYa}MVvmn<_+2v*_jA9sR3zk~*e(p)maFP-i)!51^$pDCd7u!( zZdNP@H>mPO6^H~9P5&jl7_BFUm_iBa;%|%icg;kArOfGL#lV%s#ta*oSIwNjyAhNj zc*OO5`)i-*Li z?aq1o;q9lMHIraqz;+w9eVffR8*aL@MLxJNELpa8wi^u;y@ck03{jF%eE5EfGqe<@ zC=FU92p4w}kQiQ)vw;T9B)Uz7JLxN4Is}`49!LhLe237Wx+9AYF@Hn0UPg=THG>;A z8R~NqJbrT}0^`=4rMz@ON-U}b3a>uu3*?fS`A>MgetlU(|E&3+Y}@!l+U_1fP$3J0Te_3>e+Svoa(aI6kV z3-9)~=9hImeR&;!dYW+fawP)UpC9oNJ1e|D*%Owas8%%eewL@u!AxXcW`aZe6znKL(cSYn^{nRk%R9_baji0ugl)sCDO%_HW@0?MG2xR z;C#=2$K&95Rqq3@&hgrmv2>wdtAkAgtw%D2e?Jf|Bx44n$K>x36ZHCdz1hso6j$iY zihumzkJVBTcB>L%0=4p)c>-3uAC4`Os!!B=>XUiBb8jQ9r_UdmP!i6?g@Hz>*Q>Up zmVj>R{G;64mXsoP&~oEXJKRdwS@<1P{jqge;71Q4QqW%@E~HM9t`@Ecl>=qgV3`mm zGTivf$21;;tXYE_p5ujt#QNC+mQ5LF2Pz(}`btrgDbHw{%(MPoMy)1ct66i{E3(5N zxk5vKGD_SR&PRM!Yj|zsI|)_qRxgnR(a89R<@d8dSw!%PTV?3Mxopk(Tp7?2`aF$D z!f`gdruZ^r*0e`>__+|~!7o+b+h)&fS0~57A0#tI+IUk469`sv`qiB^AnQb!P0hg- zczB2_&uwOhuSFR8opEy)Jm?qpUFKAdd|N`ED99Tfi!Rk_ycR8%QLtfT%i|=&BEka% zxVMy;V(5OKJ-_rgiVE29)l{hxHSL5!9_dIr`O`a>1F$AVEsb6;PnG>2s2i|3QF`py zf^GL+(}No&moRf+Kwd^2Vd#mPmCN*!XvFWui)WNRH=m? zVV85?=0$>T=bf+a5==z~6l5d%zb~VXh|G9WtNazVgui`{0e2j~zK4e+CvZkkUnoXa zP9C$Tg(BlxH{uoyqF%XpAGzy*SbIt$M>*8wu@&I7gnas6L+1;7)M?XbOxGyS zQGMoAW$4mem=KXWJPMqk@OW;XA$vcQcl$F&V`krVgP6Y&zx(U4CqcL2sp8&0AHJ$8 z{W$%fl8EBQ1zIFC=QO-e&ccJ8YloE|g4|?97j1haXGQKW)>pg2;2W28s zezq-JH2d@32ePI3Xo(L517AMHn?!N6=;jBr7Xa1A<)}qJ zJ7yC~l-fJg^)Y;kcQxI@xN#ZuwgOmTWMydb&Ta|(Zbcz3^#4^kkiRO&8HfigR4!B<)&YAMb-O!Bp8Q9`-H}GSg=S}6(kt>v1VWNE?XXZl0JM~Y z8E^oGc_;@E$W{=9tLPS)P&k5cP(R;APEsU0BQ>yPmqA8hLMB)TTprFDVGyB6PK9CV zUO{yTY#(-o;)(6MKd{WbnaiWoQJcJ9OM<-yF}5sow{<{jx-f~=x2imA z$37)fM?ziWD(53aL03%SGV=o1IPLdqbJSzM!(1&UKXPmvh0!(%&1py;#Q7QI*`Q$6 z+1(v0eX8+3FTZY3s#gpcqpHNN5;_bR6r>qnWK<1QUY0*(d;WC1I|=DVdeQ0m!CXU2 zQ!t+3&eJL}JgmvWZ1x#B%vWr}Tdn+b3V%*6)!|NWf2@>rK??i&Wc^26%F5YM!Fh1^ z??Z~}RJrq;O12_l8eb)>pGwxuSHP$U)`cqFWv%rF0dz!bFWFk9N>fr~v#E^wm8J1n ze01$!NqesnHPWvw{lqy7l4{vt!Bs%kLuvViH?v5cZC!M7t)zvxc&dG?+~xMvekk}q ztRr1iGUqvfvQ4}(wqqQGbkG*NvWUD;+%wKf-?8_B2{v#0N^eH0nUqJNvo1tBBp!~m z*CTM{dQnV(ltJjwU3Iw$B$1l*A{oC;cu&3Izv-bKfO%doHD2SJAM)_^KICnGP84y@ zF6ZCQ%K74+;BQv<(0h(JUcYMgKMbn5J~}p<$jYrkYO4FoQD*#5Iqs_aV{gSuI+puk*@7NF3qC176hs>x6<4mSzdBr>*Po# z^S2xVqQVc@rc8!EO+WFRVz>=Q2+JANHlWTQ%^2aR$P7Izmpm8~Iw%bt2_rLJ7Si2Y z9JQUCKbE5dHh(8(fVV>f?O(K`SF9VbJm{KMAX`p2U8Qc@@xdw9w4B z;|=u`Nr&meWSNzhHy~*;J36)<&NjXGafDsuu18 z=8RljM@#tZ8?(9FIqRLI_W@R};8Qaxhm3xrhfiFVHBjZ-O4(%TLfqbyoC;5vUtLPc z%fl;3ubb3Q;@VwX^}mpLb@o=acsv~NzK6s$46Cl^KJV;2NwPuHo0-!+0mDY^ z*;3PKG@`+3RK(qo%bIN7HR$5Nh8rgz1gP^r1+!DDd!BJvB$o}}+Q{@@b1Ed={i{hQ z-@L}n!8?yT=LWgcIr-+qKzXCR>NGcp!lIQLh@1YEv>S!vSPn@hKomI+) zV*IVo6D;H zGBE=3dd8D?47>!XLo)Ir+RHz&ZyVnp6~d z(cn8!98o2$;h+tcgbXA-W0}iSOZ0Nb`ze#`h-4m*w5+c$XDH_4T(XzNXjVng}jkvFxGV>U&X#b zYDMg6PxlB`K|a;`dMoQ*Djsbz*xZs65!?H=%;E{!7(RT*oP zR6U^Twi(Xlz|-EfUlaOmd|c3!kWwIzfu|fhST7EI5D3RosNmddP|lk$vcbumP&4oL z16uN!Bkz=wWUU^*8Y2lQ)FgN(?-rfMfjA`B$s?rIRa(T22;n^@@QB1a8=heX1()f_ zb@a+*?zVySb(^!lh|2_FT+GQN)9Cuo^T$S>rGKlgje)F{m3|H?J3x1?ggl%E6VZ`}ME8%}b6V*B~i ztQtX)Wlbu>hX}b88XR-tDlBg5xkY$!=6r0=^|fA>_^U=DmmG+ zZD`QOy;3!X$>_=?3t)oXm2i=v z>GK$Pk0Qe$6D^4|FX6Hqhj=VWfDefLJnHVGXh^Qcoe-x!%vkQP&(_>KZ55i}3pW*+ zNX4}%SwH5z9W9gi=O+^C%lh2OvF?u{df9jeerCV+OPKN%d_FWy%WjiiJUKNryl5T! z>D)iDqxpJUo$;S;;bR1!C6IoU96Sgpp=XeBtlP$&DJAQUZb|QLo!HQ9<#hMP2L|EX zO2#~^^F71Vd)$Ul#(U5?J8n8r;I~G4{JyY(Ce-c&tu$*rxJz(+DC+p5LeK_Y&|@A1 zAS3c5BQNJm2V9=qzQNpE9p|U#=~i^NQZYBHx)lx*c4~Sn5VhT2E*GaZ;3x~=&x7KR zz#rkk7QInHH>k>55R0SLd?$2}Hg_BvqzbM@n4u3c*22p@Q#*HQb63Dg_O333?Wm75aJWLuFX2R(4tA7#u=`U zn+&kjan@Qm3zv?Qlu6S_dn}^hN#qY7keIX_aIq1FneGV}nkllEcRJK)qA2#~0r4Kf z>rE3s0R`cJ2eEm{j*y%1Bt%toFA%3n-1<;CQazMDiPJy+87&JVM%Z9^JoBRpzJKc* zEWt$ch&l)&Z_9a9f3eLX(<|5%&Q5^ai`3u=8SGvJxn;D)A?G_DSL~A4^k<3`)}7k` zWQ64b=W=*qs0D;6pu3dya5TUJ{zhj9@qPvFp_>Z#g)s_7xE+w8n-CzD(*cj>PMw@? zD6vEvg$0K*^aE)Fs5=oyvw`fp4D5C}L(?$wUlJM9x$splJh*MODGzZFOi z@@csk!6mlSgsdX>;E(_rYPLx`9VhA9#_EdavH)1t+2043Uflg9YE$I64GUFWY1X*a zbGj$#Uo_9b-%H&TR`nv}i8>m3 zpgJ41TM_0p5K@=$MIznh>zED<;2lDMhs2jzhnCy{+%^?lP+#2vu`?sckTAeL;d9&= z55GMN+k1>|Q`S+wYTF01Z>?5nzW4U3L6!Tw9edW93tOj#;bn1ZP}-!%d*i1vI3LK_ zC6RGXk``@>&{x*#lj^05BrpfKoQ|Gf}6lBXFq{H zdOC*>zu*teM{j;m+Rr}3qwmRV4GZYw%J&yv;?b_8tp-#!w-0>ca_M|^Y4C79Z_1u8 zWQ?2ZGmSZ&RJ=SoMBJssjhgkNK@r4QsCKAGVrnOR9IaIOw7E*!Ka&QZFMj;|9TaFL zK6|g{N*3kgr1WR|@WWIXvzRhxYioaQUvWQXnQeNg1^1P zz2O>0^!G#yS92lRK=&1(-9!~d_Q6M>xo`iBiXJrNV z!=Qwttx#3zjlPF;N@aK}N-uf)J39`5$`gnW_IVoRIF0^Toe6 zz#o^!oAlIN=sMYY@qO5)@v!&T5l8o9Kk$tI6sKO@d8zCq+R45R_}1Rg<`T0#V`TH* z5g$J;@*(iU&X}q6B=T{q99!C8C-$trs#7$t5o=Ah47r?jQU|Pi@s;T~L-${T>>bJF}+k$OM=^+uf0d2*F^1v*?J| zVxdOx$AUgZ5G4^LASAvS?D9LpaHjEgBk-D*@#5L6L_tY0nmL>Bu%-yflU$&iqm(p( zRgrD8!orkkqdL3o&6Fd#K8|}nuHApOecjE(2?>5(PsfO*o)@o5SQX2Wqlz`04Y|eE zWbqAQuFQ*D;lCo6M;)sD@yi&xXyR3qxh#tf_z)?})cf-jK6IJ%#l57tNp zZn@GtkVxPX83~)jltL))&%S%nXoO9xfo9#Wne9Rg2?Dr9^&CT5qOkiEX#zr%znv|T zOb{+>ri}atGG@TJ5GG{8mWX+>zyfIFif2aE6Zvwpz=He*5rj5{!?9B+vgEA0C$~Un zW(vLvD7ww|EF1Q7Cwz&ifN1n^b;@FbQBXrN3OE=`yEz^N?|@j=#`^HJRXetpwAd@- zURVz~7_>oAXC-<)2nH>%Qy79J4%X+k(cw0Axnct?~5!Xe?E zQ;&$UUlG3me9ta9#>5E0h1^b+M}>hx7Z99;c7&i@`KJlORK{iT&qB)cs9{bq6;QtN zd7@>$oe7<1PA^sQM5@qd!-*axa9lmOf^^Y9!l$6**fB9$v6y}r-UD$j*x?v)uhIQ6 z*fHietCzDAzhwT?XVuOudu;fJchJO5`ILvrn^Gjh7ez?SeGps2To48pqXXO%{wN$q zu#W=r8=ITm1V*8ntpW{6M7cWle2*w)(#CEmeHPW3REM%PQG1Z_S!8M)Q)a~d7-T0C z8LE-iu!VGJoTV3iI;$CoTJjn*&aj6Kb`{ZiAAAZjbS;%(11T;8U*tjVn!-K% zgZKsgx)w*chY5D9j@8#jRzJgyVyY!1)ia2`?kR#4SPWjDDH(|)s*qF~4DA7Ugc7g4 zVEFS_!mj)`c}v)jJ9(X<@c2p5yn;*F8;cFQf2Mz`f1rPcf2@D- z5ABb4Pc;9`%N_aa%iH27`DfWD`X>YbL=p7j!kBaatbWDTT^5y%xAUFbRb1;-D2mL) zN%0}+TTF5nfj@<=)WnS>dZLpIS3z zL`Z^u8U%eW5u=Eo;(p|3cCz51zND^*pAu2_XS#^ay9m)gjjGeN~E6*>pXd`!at|Rg0+Y>^j%aPos_W2kKG+NCk6O7r_3; zt4FYG7)sP?We{;;M)}x`N|%R5U7JeN^%@&{0VQf;G2%u2xG07`%5Wk8F|*N#`yB&g zT+ye-Vt%W{Q1L#iPuIc(^(c6~BAp(UO>2wTmd^D?I`M1Bn^1y7cb!C=s0I-YvKo{- zlsoiANUTtEo$9I)K5Eu*{VMY1l4zt! z6d4lZAW}?}2^8aVc7Xy55Dbjy_*wmwL#fWV)$V=eXJ+W2QLOwRGu96Uy3_;waYVPG zV3-stpJT~^jddFH{pwMfo-2Ysyzf2;i3SJZ=+EH7aFZ)>g7gp*KIvr*S7P%o^;8ma z^_Y_-pw$}rp!r*K(FVWHRDpJt8;L!KfBnj!PxSNgM+`TevqKs9sZJp{hhzzKoPkVg zj2N&(7j428=tLah*@-Bxl+xUf$vmN#@F|$^j27qx^vV@&2CiMv3M*xgZ<(8_@($(g zD>Tmr=XGFO*}P3>XvrPq??i$qwrtH@zgnNp-wGSi;&-XwQ)9 z*0i)T`(q)bru$y4@TZsRm&)2+C@m%WZ=5LI0k2rwu`7{sA&BZUac!7&q^jhG^p1N9 zX#kEquj}7Vxvy*15gEP#(wL=+gCrmMYEW8ZRjs<(QDyBg$U0(Ioat3Gpu8ZaIbM{% zul3(~e`|9mv3@nV)w*A{q0tgUBLxN}+?rC(i*xl+RuW|6tF24SK=rj~!Ub|SZCE;0 z&Ut?ODWq)Ng@6&6YH)@(;P|MuRt0=x1JQMyh+EAsOk~VYjI-uDNvnL(}{)!UQBjcXIy&||4Pg<=&S-B37u}UtHONnSFjja4W5uu~N-f4OWAEow8~0 znpUV#CjDI~si(_EF%W_q3H2mXsQE=PU(%CjuO?I*l50M9FJSvzi>?yO`kMYzQtGeR zxgyo9xe-%t2WU%e*2#M05B=nCTR52~D}0)@myEpp=xr!C0izA6e{O^+^kHSr#2>TA zZhWhigKC_l7R+cRSUHOERF2VnV7xSk!J5Bf7}IgbXf-lSu){7>pcY;B?!D>g)pS)(lEu(X)<}s&2eW?(Qr7Tw|AIAs z+jf>0F-Ql+mTR2xS@~dAu0Gx6BxV-}v`t+qpT%X`ke$P7xgR2PX6aVqA=5SR{o8k_ zhD!^_94C(xja%OVjytWmJArNdDegkzUGl+wsd$U*inW}gLqu{4sVs^>kMcNjCF)`5 z%}Ah2u}f2j2nh-Chm5Wczo`=^8n>1U!jZd`t20MQ%Xb~z@Tw)Bkq&J5A4r@5~jv-6TGZSm6DUG|LlHI@btv%a+yZ1lj@m4oi&g_VV;-d20m5M_yFi3NwLs9-Mfpe_4H)c8Po?{>q!Fu$O_ zpq}{5bn+^E9jG}u7P)l_0m$ZP7+Oduu-UgBbp!ot>@iAY!bNRRzJ~y3CCQ zi`6zQtu2S!bur6Z@P+@sk+R(1NIBDjuc_q!w5u8aZC5Y-4UzxBf5POHzwK(|QPl0l z9Qj02ZFex_Ec_2OvKHW=q)^+4^D**CAqou11QR4F@+7t#l0lQ#ad}g$!U+*38EH)9 z#Hq+U$Qk%wEy{~>NJ$F{fkrD(?SPs161XL%Tx`O;a#G4dOd?7juYo!WJ51~cA@YqyyM{V_c` zSkKC}`O0OFsvz6-wh{28c+9*uADi+Ua+*j?h|(u@B=p-Ho`;U&Sp{rSe)nc~FhOkH zh96|c*8<4Kn~$V?P?$1?TATE!<#O4G0vio?i84gsP{52Ci!#)Uz!@}e7Lr({96)@` zx1o-gRjTOG2Io}|W#iyk(O4>K7Xn9{qlNndw@JZeZL>szlW$|X%8Fo5i(_M2p|Mu6 zS=(sSW>;MzRHZaPKm08ib7OJsM0t_HvD_5&q(%-WC@VBNbHFeQdBW-ue<7o&LXo}n8o&j?fQ+EWSL zLjjM9z*|(=eQCIBi*dal84iX(oVK+kD0lr2xYP9$nlhYKKQ*elj4zxG-TtJLhvw_M*gP@cb$EYGpZLx;!Ra zq*l#C!ZSvkB2@k=(q*32x39u;Rz&Op>g*U%Vt!-uJ6(I!_lSu(IQ6+LB?|xR5W&_q z9v-q$6Dxk?WSY-U&j8I)UD=?B*UtEzoL)|jZeRQ$wChAw#67C)o-FaMIOp3zWXnKp zZ9hFK9F6tiH;7vDXlNs)=`@gOmLwuNwKUqk)!Wkjyh^+0bIlw~mIETp~kjytOzSKdIBTh7q)#0KCM_hR8_VRBzV7b?2y}H?jGlu(P=V^ka7N_N`f;?zn zFG6-cjw5*0GCPQnF{=m~*-{)CM*DhygYY%wOU-ATEVG{xJtKbeUXz5(rjlEpVn3a&%4_w> z^TG3#<(qQyCG};@WGhKBx&pzk3zj_pSDXYM@`__N@a^Dux-JKgBQ;r zLobEYmz6n*y7z6ka+Ig;AH^+fcW)Yk8a|}w7jRX-fCM}FDO_EUO&6SM^;L$u@X8J^ z8fqQiNo&ijV?CIpIP`i^x>mGxAR^|g;d&d9VriMy=B^{Da5E0fQIrQhuH0CD_kkS=?B*P$0wXMQHM6uU;;Zy~r&a zI68!Qku3mUu1%ZJ-L7v)3FQOIZW-f`n$st*t>g+s8>y1JV^$6=g8sr-H8Yyt%kCfe#O}7 zUc001hFffK-(16i0K&Paxzzf~>e&n6M1gfB@)Ce{E2S}0RNuLMM2l?)u&ZtGB3uXf zwj&F^b~0|y?s)Rl9#PmT zR?6G~6+{cF&Qa3YZ4D&YYD{{^w0jA(5zSp_7tej#;x4(HeE7f(3~1TDaYI9r7eQ3` z)CS|;Spju6V^*LxRk&>Sno^FKbz!=;Odt?z}%b@IaT^YX`#%$^k zK2+|m@mbmp<=dn4y4jZBOhqc}Ns4aQGKqQULoixW%xIHB z;oc6o=-W&)<<5yU+M!kY=BCax55Zyi-Jwm)Fc~$rM^&PBLV3HwM*%OqZO7wHha>tU za&SsXxYQ2)kt#B+r?QCtdEc3lfRbLo4`s9%Oa_eVEi}`5o*i#EQmX2bl{Md`)P!aQO zUL|MtR)k_r!t^t_1IcLZMP=@gv8_n6l$~UgR6aeuwd%NKkowOvOw}%oc{Z}T-?*uk z0@0$(-NnakeOzIQCjJ42EnIGQ83vw^bl6>;0NIGTXXS*3>~E-ghI$CH2~n{Kr9E z81!`%-H$llegVhp59M*PZIv!pB}j$Hyi#ro_?CW}X$3|N1?kJt75k7O;S^$PbB|04T^L@5RJ z)3|U+NRPghPq}Qdqb(2ajNcGzvGAG;#|veU;5AoR8`+HgDKxeAWAwmb6P2Q`#{h#- zMS2>MrVDrRpHFOw?>tEj0XU{R4L;%;$=0c%vdf)`p)-=hX;TbUtdrrpT;36JcdV70 z>_hykNoqO^Te?A{iuWZGD=ibIEE!M^9@ALU*%VwF@6OAhz`lfj3;$Bo0vT%1UahFt z26p?$_31Jr`|Wnl8SPgf2P$Gy4?P?{BcxCZmGYQ@@4p=co4Tf(lh|PbN-barGJl&s zWzz$agNQGo4$}b@G8N}{T4AJIV9!hzlL6L@gC&a=6BmiO0DsO~)&x_KW+gQ^Yuk;M zy)dUlde^;L@*po%_I`AU*`=Eu|&&3uK?`Y_6SDJ!l|N)O`6=lekfl)HT0(iZ`|b z@k^FfCo3NXQJN$KP5V{v0-gK#}ruwEX<1$$+Gn>dy zwsUTLc6eVlnVsEnL+E<|_Qq8pbZY_t_Bi5FWqg7^GviLyq-~|5E(cfK_fV?k*i`;ao^^XJIIb3rjQ-7f!e;itqlTZeOo) z?&R$3=vVuc*Nl#q$LXtQ=Sw-5jKXa5h4=YFI~6?3_x0r0Pp;cymWHzv^6K3(x~2EF zgYX0Ku>I%dldp9fTHZOefthjs)-Rhdfcg9D!N+L72W4=Z7tiPOI^^|H7Yw-e;Gm1{ zyYJg0n2=I8E`D8NF>7u$zvzsD_;^^KBF=V8XfZ1R%({dpO02M;?Cfg8;(bi)>?PKi z1s6M*WnSaLlV3v`4hmLQ+sh^P(T4{gtAol@c5FgeiO+WUUSP3d*FcY)S3lqDs$h3_ znT&H=9k2ii7D^!9bMC<}PoVyd4`D_atLmxir-zCKO|Z=YFeIFrch>zCB;?yqq7mb- zW$)f=jI)up;FfN0o|~1@SeeUe_ebtOJF8^w{xv1|zvGYKC;N`@Aisk+(EKo%L~0dVS7<|N|}IaT(b#>_kXW{x-W@Fr^}iyOQ<^E50%z% z0~5Lrx%}j`v_hQMv_vF22hX9NQZFXH2_=zMswi({RRhI z1HP=Tfq4c5cxFUwZtm1CQWo z+X4=;H1nL_@qVrY-&KkR*e=}p`a;K(&7J|$CPGGy9I&P&VJoB%3El0QbOA`&8TbJQ z@!Py#80b8N3H$|j*Zc&QzFbs5rRfmFY05e1M5a$))@eO})0+SUP*%u69pW0I-#buK_s>{iX zhF9YU)4MFNW$;Kr@m@$mo8p(oVVj!}GbSVIHC&cj5p3|>2%j^kOy!oL@?H`ma;D>z z#^G;25<3n<3d=c;Uw`b+Cr_uZ>s?O%@~v}2ZA`9DXj5xdWLjb4%9Rz>x0F|u6gGEN zS9RA7Zfnk^?AV@-Ur(PhKb65^fG33^g&l}J79|+3J5GxXnY^l`Yx7>!fB8Rt{=j`e z|KoiB>5BpYT;#5kCEt!o5d3}q2miiy&U|oiP=u7teQbPv}O*!W+sE@BEuYJ6)`VfL34;O}_hKg66S|5XWqy8+gJ@E^Bc zJ>3rlLI5E;Z*8ij`Sr6C*I#AM8bkp9#K3}Z^GGdG&cZqc?hIOkKC81KIHg&Sh$uz5 zl-XHbQ1Q6U$h?`uc<(0nM@t06+kS>~)7w*Z!TWfEZ|ALS_UCim{Tu%LVG+aD|Nn@N z;9t?f5q_TNfc$&B|1UZ${}r8zzk>4*{&Tu+HERdt71ZrCH}!^YYD@;S0+Z0+3AX(b zl`CGRlwdO10R54|1d-U;0x+I19F!)97}~^>Fi^fEvOsa@jhI}Ea+c(~#W`^cmX}nD zqfcU&yTy^<(=O)u%&Gprp-7UJFVp2w3J;Y?JM&o3XwjA3gWJ5rU@dOeok-PK|8JT z*VnhtBF+>JrraL7)vc_*PHQogtN+B0t3I>f5H(ryr*bM=SbC5a%YLL+Ce9ALh|<1# zQ6TM@*Dlj(8nKZ-Yt?mLSJcYe7`iY(KJJp;-V@(zdKX|T+Y;V2KKE$ZCK5!TcrhB_ zH{~_-+RIm93GnCOE4V%cPOxS4y&z0D6w12=(8=+T@y26pzI* zqf|6J4X~%yU=d>EI0&2UpfhOG|6+Mz&sLE_=Ag|0b;SIt! zlh2l$fUg3#V>4xI58+EiIfNh{z4W8;OFzmHTDq6Uzd+GSME~xa=ru@Ux&Ux)^GN8P z@SEMfVu-EF=Wg7}pD7j7LCiUYdIqmjyVWZHQRiPDFtJa!)6#eo!!G26WPbVR@isx`~7pAl-3U?>1Lh@-tjE6GMZ$=WZRaF z?YRidfJ#ZsrZpoz*f(hRrjr=4f79<}|`xq!#*)l}r}7f)J(HO6qdOD$qr zH4uaq1V`%e!U4%7jxReu;VJAz_8X@tMW7v|T1!z?^31`+^hwE=Gcx5}f%v3Jlh!&t zv1|2&Frj7dzSi@Nfcj^I@c@sQiX+#WmsY36%xke@CK$oHS{xo?F>;S2562wmoJQCt z;2A%1ejl!A#}LRMHRi&Qv=0oB(epnMJd7?QK^6PUg+nV52U;y+ht)(E$fm8)FOgNM z$v+d)_k%H(tL+_fDw`-(ZBMdM$Y4&xCGn`Xeqn@37*2q~PPLr;i+xEPK7j$wgL13rD8nBg1Y;-wB_R72!bzSX!*nS}dzOsbO>0&loAN|uL@v1eFyEXG(&=!s#9b7LSKEacw{Fm4cwKP5GxKqfHylc@zoAPuAt zVn=lY@JE$bpuT|06oa%D1E6gxuS9y02>LQW#P0{FYijPS*VbmgPu1wVwSwIn5h=_V z!A_GXUDQpE^_X`@Y8}IvD~QUJvw!V})xS2z+yh~%0BH@!3L5}abV=M^EaAwZw5~}@ z0>hjnlHD~mj$(~z*Yg(Qklg1sE~hDpkl4O2@eU^KYuF58p8LJj+}B%3`jk} zXX7hzVQluZ5oyNuo_@1z7u_J=$Ol4o@aW-Bp)#* z+7>F8ka4U)WFS~-bJKiV8P-RRm#9vy8)A$m`|YH3BQn)OvxOAd6h!?BUA*&{>rSSj zDSB9J(;n-PR-(#Q?;ivYE6$Ino23Uxr?9xQ#oQnGhvjGDHjifYRJ_OIky-vsqoK7lw@aDndg%LQsi8Mva5?kUUeb*P?OHKXi9hBT zfCoLq0-Kq=T1PPkJJFeYzI|(Klh5gzAYm$=W->mTS&bo2`d;oP8#xnrSrBZwK!IE! zC-hWO;ny|}c_Ua~zC8-2QL^Sbx2Tz<_Ap1r#I-uK+%quPorL0)|(| zdKD(mxCH_{&Cp>mXl)Q)|Etge8MMiO#DMh36nZCiZ~|m&j?zUH3)CQ3Ya&h>0wG&m ze16$xRCUGZ8nJ+$Zh{i|s~th}G5tJeD-7!}C*K9wK9N6Eb@0 zG#|Jzni(&H9;08PWRRrhYYzl5pgE6|vrerXcTqfyyMa_kP4gM|#*bWlk4TB7P@$hx z%9#_lkjT&b(%V0BYJNJ^dsMqiRah#kma_7%RJpH1Cd%iP!BMluq8=U)oPjV{e}A#B zu1S>?I=>>xS3*J*K>x^-iRgXb&#~b#Z?u0#27a2e(kO};r@>ufa16G}*Pg{U91#Bf zD1BEd+6UX=UJLT_`eaK4<_0>+y4{s=hy%0#2EO=_yCX1xHt73X8S%CNZdtMB~7)Na*=2Sg{NaK6;G zfX!EZ)KgZKVpHd|d)qGmGVzAuftQ+Nf{1p-M;s;elSHWmMJ{-BoOOc9X_LVl&T^e$ zKe=P_gpXSC?s3H2Iu>B<3NBnGd~K09W)ABjI#X4g1?nAfrZuwYrYuQrZ}L`7@HdYp zc3Sctlfe(a=B-P$Z!CHBCU}S4`W?YlBTrtrxM+PcLXOK5;H*EEc1`sOaH%xbqp^#n zq?dMVM@YxeG<$b}R{{Ql8YD@hB6GTFNi+s)kgQA+EoX+<3AAcA$J2Z{z~%e>Xvy(l zQz-E*8(WdBTU4BS9~I!cHe0B8ilN2Q6Y4=W)nUQtu^imT;nYS2YEhbTG~5ELq|1fR z%8jf)!0T*B30C5*b_=$L@-lsvQf-h*eBPNk1E(iP;2$>NHWV)9bg$pQYO4b-iZLY{HjQ@0$8Z^|l=n zwhDi^ff|aF+~VHicH%7Ks1-@5AwN(NGqBNXG8`7?qa+wQXo|MRL`oRloB6vQW0P|j zCl!(RQ}hCFr7(L+_JO*z7%Pki;w7?5^aOfhHRd^HsE6EV(m2vJ*O~}1shD;3Q2Dqw z_$=Z1PzO4q813K}4_QgJZ%ai|g-*AjG(rbWLysp(o~3*t5afkCUK@1lO`$uy!{Huh zNvwL<6X35Nerg)UfV5TA)r<0EdaoZ@bVJ2t^&~8o)+7l_9b!rc1g0r0buMXHE*bnTP|5f5SIG(aGFKP!IcE@# zy z*J;sRF5DRABOr4C=TZO0)~d}aT`IGl#Ins*F6g@xx_N!CumO9-&+Vl_a@D|qL~)?T z69od4h>0(7V7%|ueQ>459rnZISE7izJW4eLLggk!09ZtNZbN>B7PnN!#Ddrz#0DW6 zFRki<;U3iUprM_uZ30vbVc7c*f}p|G+b&GsrDQw&wqgqj;Zu-?C8bJ7%>=O)0-dMp zTrdO~X&#={W7i1dj(P zxjm-j=2Hk*Hw2WE`x{ey5}Kfa7vB-SL2c9dDo>;*DrII&7<&ehp>HO+FO2{jdz^}g`|cSSm+bn!Qk*k)sucA@ zQS3)Pk}(D1lQ4653k68#%0xZY4{D+Rsa=fD-n6^wGSm+~*_q!ipguXR&bXmV)S;JX zPrL^jdHU0A#TVD#4RlCVKuQd5T5jNv|1G&4stz*534~>jYt$ywzPR1e-ruGtr%^68S!i`o-@@$9rX5b8$&dqR59{QkJd(vpPqb;x_BMB7ori%8#4RH#jAp-TwHjNY(9>2w-(MnuUW;K?Pz|kf?4e7= z(CbXwFC&@$OaAz?HB}oyAB51wWc*j=w74Dc-ztZ%5LoM0vM{Dq;1IV zY)ySqJIU2=smbSAW(k1>E)bb4{vZ$kne2d*m}_f-E~XWE2WxCkDQg=h-F7KaZHKP6 zI0tj7ozC??p8$v*5qKGI-k(u{Sp$#VY!0J5Uw2f^FG9Y)Dp9^E^E-&dR#v8W7gURR zlGG5x7|Ggmv7I%*)1j5lXy|n$vUVyp9#|oe1lKI$nifp>zOGgBjqlC=!3(>G=B*hc zgpH7W7-Ov`Lki1Ur+NP-{C)mzS9K#fo3ogYf-{c>g;|a)bqY!-_a?*_8tsYO^8u|v$LZW1y58Er zwyvYEnfh*1%##`1-8Z*R-s!tJgc{>1H@hDLT(lSLVflF69E7?Yg@V#Bq`U#XDhJl> zX}5Uz!R-kF_u3S3|3W9KN&YKXw-bt5aeJW@nt~%WVekFzeN^&qX56K0(pI|C6MI$5 ze4^At!zWmfRVuHQDQF%0ZLaF0@j^Y8C&15)Z7*yS9N}DX#FVBvJ4zzrtEd8QsnTKN z2t?k8;|3oWb}5fV{{UIVwoRcb?*};>7VZ$RE@B+Cs#_=3uRh96N0t-f2M2fZ%mI-iv zex#B{f}dNo7zr6y)m@euEZehj1b`0OEcxE^Szaz8hc z)>JzjhD%iRy^`PMfR`nOhHAPF`l->s`u1q^j*Bwp=#2->8J9W@9lw;8MGDFkE zW#IF#$9A0#C)y=3!9E>?@vDPuwbBO^-#I8}4;RqwFASR>$-SSs`QDi#!f4wcp0fr- zD`>6BKTCr>2^)zqqyCWYq~JLrCQ~3kBkLvfmD%r|TtF&xs6D|pZo7T!vyT zPY;7ic3L4@BabR3YXK{K!rz908h1<-Q2mnaP__(cWKK>ao{B?yhrE$^fjy>F3LxAf zdVhJ5C^cjGHdU+3n3(%-=--PB1GS+jC6VE2As{diY((!Wj@9@gRpTZL4R(2cb29; z8`Z&Q^WPfbT_j!B(C+O1vr!%V3^V_wz1>C7Wj%xbN%<$p2xAKVO9!Egpv!#3=b#u; ztpDRGzR0@FLv_xYp}~BozdEWevM#GKJ!f5E$FTlfb9xbUnV@|RLI`60P2Ro;x=hGE z2Z;%t{RQVr$p6aP7fF{X*yp5|7}B5h?0<3oEXJI3@WinGCe2)Yq07XVbC4MZ^cN}S vBIq)iXXcqD3p0TP!#R;I3im94{WDd))P*nEKjw;3-)UlQLkgOB&vHgLsaCW=mlXa{` zB=P6lm;e@v{KDCr72jJL2<`Y#zVq?1{Yk!c9UVkEOl{aj(9wTgqPA~#laeRfnks`n z77K^+LSEnO;;I^=ZlJFn_)xxu_}KmmMPc9UShLJGMD(5b5Z`h_l7EHBcMg}ipW^%Q zq578KWBWt9ET2=bSW@2Gj-Vf(ui+zwOS1eb6#nIN<`qcz!BGg>(Kwk1-;yNjOY+TM zAn_-%5cGm?G{Pemiv%R!f|Dier}o$hzBGg*sL_*usPFPQC+ADToEq}F!Xz}UXelia|q(bTM{vTLqWVGH!yJ9BqINk@a{c}cH89T z74$V;w(Qz>1_#T}-fO%84jNW_C9i^ZTeK$`imi_u7XwZhPvd)AUo7+xP1u2D$R)J* z(LwwTya^SP$oenDhfto)GWazG31j=^D2#vL8ovPcVhLk79{;vBm#iXp*FN^sSHO7J8l7z;{oQO)Wz z*Hnitd%G7gC5Z{IwNko=(t(9~YH|a?ZTmyBhZ4)&ml5@l7bM@-g-H6)0H*ffOQHB-nQAvuAx-BS z1@9+}?*r*RqWQK?24ljw9q6_`-_|g&y~eLwRF5T$D^0f1h}iaiX9|_zN@FvLN*F(! zB_+nvf(3mKgFzHLIoLn&5&8g)vL_XpXI;<*ByLPcB?s<+h8svffnu{ZE+hJ*gINbJ z1%R4(k)-aQXrTUqhrv>k$l8rk1h+jOYe7zTLQKJvp@cY;w)Oc~{?;dBflzm!=6k^3 z^Yoff`le&x8LUS_@yF5WgQ3KNClGnb=>_{6lk+E$_WHmN zz*N#xtCiQkRTh79;1-#tc_ik-qGw6%oxb&G&J;tB&pU4zryMz=v zpF#a zgeDCQkZo_EQy#)36a%l0qu3Z?WyGHmLG!66>!Ac>_oUx}VBlw9+H0H+CK?b2_kk%C z|K(to_Yz=p2?0j`*Vkmjdop<$-?6+iU#jLgs40V{~BG z$CyaHa(3gJ;;%zI{SA~;{4KWl)uH(B!BZJ8_lM%Evj@_^(0#Grff1AlW``2~P>$^<-^f{*4q9 z4<3Nf10v=|(gRN@2}Qf8LmsBuk+9Xo$b!!R91p%mXwfcWu(;+BSC0``Ld>fNO5?vQ z+BJe0sK-dm>tiH?&(1K<&hRs0uqy6Bo1P$fgAlflB)oPE32wWDFDZui7u(8!Ig%{H z*IGS#SU@Kq&s$Lo-1i2r7ZQ>;i|>XFM1V4Na3F^EiU!!uLRM zzwd#4XvmAW5?s)!;OP#2tRZ86r<+R@>Iv@0I5{lG36;%i6c^Y-@_|zY9gp_AeG#=1 z_rQ<>B}f7G7$fZ^rnRmm>jK4a#4ce-50ol~emlbu33-ZPkDXyiE4vj#pPhjo!d4mn z04;(-4#|QxKo-N}is2!%9>lb1p&Zhk2KbSRO2kX8}T(D>;-f~N`=p|On* zc~JC$pJzd0B7Gk*+(!(F^gV#pLUlU`Wj!Uid2)RfioZhSyn*XwnzGzLD875(3Yn-3 zJaOZ4lF|u+lnufbA~X|w{AIL!{yDoLWH9Sgszw|z6O+%Yft4f^!c{U0;^ejRUg%6FJd>2CE9-9*54wr?B5Pd zw*)%+U_U6TLOUhb!JiXB7V&mP_&x~ceBt$Z_uGMiGtdg?;Dpg$Pj%nlISRcQu$E7% zd{|K*#Ny|@`LviR1|xOlz!gvirSU%5`sHAG0vdEVBFo}^56RVh&w?K}&|Yim+j513 zRr;^7<`2a`D4p@z4+8)T1`nM~{fmS>;C#aQiMJ%4`(dIoExuYfD)A(BeiG{5tA%E~ z91nWptDT|l$Fb-g48$gc;{O=P!upn0`+cEpgPkYJavVGrjo15d0Oc#inC(gb;W}EP ze<#NJ;owBX$3HyuTiPI6^HJ)HMWI9n=3qjPKYH1l;0j#!kK*E$0pHfEAxsYCjVpN| z7NGvVEB{Dz8jP_^)j*tMwlC)Y803qx`L^cM;KqE!{_&jip%LVGmNVikxd1h1#E}f} z$)^VyMo9NOq-H|@E))hcjneb@et)?WtJV!5tMOsykn(B##}4|g#QacWKlYj&_r7g) zNMw%vZB~{~gHM)rIil6LACj#a{I|%#@7p#($&jO~$dd6LQ^qIe&>I{gqu~96ek7FT zljHrTJl>xJ|G~wGO3shIgK2hLK5^6}_$78;+uoNI_HF$mQp$O7Ax46n2fqfTu~+fS z`Tb4sOYVaYBZ~F4ikIcT%!=QRc-CQ1$7|7t@2NhFofwMOKx-y$$n8QM-}PnGGAhNg6`zY8&CsA17AY&q1*VxV;d3Z97J z@%49t5F3iWS{gq*@MoX{hw;@b%{$5VD_U)}@LFghndeJo@h3V*Q-7$|DLOB?UPz=b zslzaO(s%VgkSlsR2WYV1t>pZL?pge+Xl7ZW&>u_`ddjrNfcq}*276KW9u1q4?4rfb zbiRn0JuneZ6igm$pnY3^2nKABD|&JpN*{g8Q6B$&nPb-DwWN)L{-V7>M57L`Aw^A=KnmC<$75 zU^ylM3NZ=^6RV+r)2~Iuszgb^GccXzhmueG&7vAI@pQjkTauXiT9`KGZ^cqWJ&^-w z?xJ(g+r8I#3{@~iDH1rpm zu_uJ#6Tr&kN|0dR!7~8r(S6C+@SW<9;bP7kNWe~a!*GRP|jQhb>)>Dq%=;~deMEQ=Agfn~ar9*eaB6M&LRpa^2sc4cn0n7d@Nu-k9 zW7||@RFWum2Jv9omJK9P?ZIl+w+&}ZXw%(kvfi7h4||q<@ao`T=})OK!ALET7=^T+ zBHsgjA?-snLiZ6^TT)_cH%;z7;_+?mr)KX-_ajsA^oRBai6RE(z|hcr1kb_Cfnj8I zzFIotmt_ubS-czrcXfZ!F1bA23^p!8^tyvPQHB!VgIduCeWDACsVSwG?W2N}&gd`K z_LaqhoK&YAmLch(-7@M?Dij3A4s5DLsXD)>a*)GlG_ifHBq4=jJr{en+PL>i!bn16tAheO<9TD1Q)=?1%0`rD9K^LcVRJ#}4M>E997veV%NFTW3*E6{CfU zJ&8)szzm2)>pTqdzy!dy)h_A3#>*C$pB;1m4a?OMB&z^okOE#>n zH}skDMTmd2pbt${m$)fH7?F&66-t5zR(z?oe%J$_o_9jAU*pikm z?%(8bgrJ$8il#yX<&`bo*ZEdK-`{qtnHVU5RrR?6H<1Zo$M;~R%lBX?69aY$vhMy942b7?vN21q3-x??cithNn(ye>ywKv0 zV$)S$hvM&&-fKlhSbhCgZ4PM7XxiJTAhcm%njk%asr)nwR7VAR2BQN7LPqIlP)Xvi zhGsk^`47HHT1KvZ1GM(vit$0!c^ey>^r@7#7Yqf@BlW0Iy-`7_d$Q6H_#Uj$U2*Kz zurajd_t%$@=3FyPB`o9PWE$gTM1-_`s6KT-Vdl0cV{_5|eccDq{566aAr2MvSRU+u z?=PPofc19U{+KV+eF$^^F*L_xodX5Whh&Z@>X7v$m$#GhJ^=MX%&-VME9TayFT=8bT#(IUpaI&%nXBB zD>ujj;VH8iMe}V_3m#H~i%+C|Lzv>@#&|>?454^D>-Ya|$o5^@Cs4hg(54m^RMc<+ z>;?(rTSVx=S^`UmP(15KLeZ(elY?~l{sRk4!vU)x_WkkQv6&cbBhg8Jbz!*^e|a$T z33Ni|`zYBp)J(Fu55^9w^)yCK&w{<+Jmi-8C%(IOSQ~(fRJ7`xC|mYiX{= zT%@21@tj=)oRsRJtyCpz^;8&2OqfHZ+%@-(H)h>>5}>_!3WE_=k=?NqLLdAp6rV7G zIJ);(%TCx&u&@}+%20XHsY0OJzt**o3O%Fb5Bom!ZW5vu-2uw!YH%qrR>hQQ0~v*q8{x#JJ$=h}vuX?HnPzPSLm5_%k4C zY*gc2favF^u_q73gM9$|6}WFOYl>{6^h-e)%vu0sFzd<)7R4k)j@As&1`az&0+xz# z<9k$u9tkc7cyKeCQjSn_{-f#z=aQV0AqQ12143GC9#%BZNYa932znE#bcFW!;ENcX zBSPE$3|)uEUMPN$M)5g*G7Dg>Vw6&np7htL4m{uGhSt(I3F8jL73`1yA`~ZCsiszf zVt6IOvNER3?~NsmzwpLL@Qg8sp*y@)*L0igal$bj7|6#zuK94==4O!;#Xrc zV5Y;e4b^?J^Djv9{@IkI21%0QwvsrM@C<(_Ug;nB64o!^d`5Df2+l(9)6CX8A@FavaAN~gyF?=`-FZ~7a| z+E5RPk6}GvERp=N=~B{OV>(bd!szKo@nco|O#^?0IzMy`WaWV}m~{zBcxqrjQLkrh z*4ukVWoQ}Q&!HKb9UT+8?4ZQDy&^PALNa#KA44;6#^)7l&l;-!=m~3*I*n4^B zUi18E*cg}O9{!E-7P{v*fL{6i8wXzL`$n|j<=?*2_sW~EP52ce-Z;?pRxsxK%`30` z<2UE#9)8#72j}kJy!^^vZRkbM{^k|@OUBDG4^CZ(di3@VPCb>wH5`sW9}xW$#z!-5 z#;+L0e+A=DaCj4k&vCes!$uBYHS1 z%JQCId==x5FmB5IOP$K+bq+TU3%||yaK078_*OAKdRTZW<7+rP|2W|#On*-V(M^tFBc5u@A`_ucXX>z=X7RZ zFB{R!hou?+EI*q}{6FFU-4+OUL}KBl){S+|O%37pI^5fg#3Iq~hPu{<=15eC>MgCY zy3K(lfvFvV#-`>7cvaZe8A}n-bpp3Mr^fU%?Cgk0cy>puA>7=yzNtQ3P_S_R?7HUWnZz@@wX-D>1r_l`T$++1BCWBe*cQsU z36k5}qOm|;ityGqUl>4vP>_HnjIxk_-nxc{=gy|x6}8qLyrV_VvB@f9@O zh^>o8>$c?O2as`KYQqd-vr2x9ypWN%qiKC>T{8&?Qwf(yQA?Hu@}(PQC?KKYDO}eird*-7o`r*t1exMIQdtxF%oTTZrc=y*0rvWn8_>F1gln* zRh&6PRMtgfO=zg*wvGF8{Z zQOCvF+5#Od7>?9+bdfpIj!0A|(h$g7y{g14#p>1zTQRUy@npHfEp=$}Xf$tzoI0ra z)Q-HV>t_b0uAdPIR3}tB+yvb)QkbQM74JjItpDMnA#rLP}dP?Z3{HD)UA)q>cFsUYHJmNz?!CLth289 zjLrzABPB-J8_@@t4C}VUA{d>q0Cl&LqFP-bomr>$j!0)i8>-&iR$oUlX{g8A>f4$F z=$j5AOl_F0O7rRI)-_>{HC+_3^S6i&u~F2EsDR=S&>Q&opTGZ$Er7MGh7aB8_9I-2 zj}ve$!b>x7{TOf;!h5l)%mlm>;Vf69X*93ekkm zmjSmU?7-(MfV&W0h0j+3_aeLjpI*Q_5Ppkrz&jD1Jx+*Q0M{an;j;s97sBibLfj2F zfG`Jk@|}S55iSnkJP&Xo!b|aahWHVF6`vOX_abbbEX2!z+Yxr)GeA5D-^Ax_z=si@ zorCMyfNK#pOhY?-5&Q^m!zTcE2g1Ynp8}Y|4tz=g zcOm=^K4pM+BK#Pi8sdSbx*DHaz`Y31IuUsSu0>dn&t|~w2=Bt@%Yb(x^uzG56)=S} z@#zJekMIaSHvkqhh4=`cZxIZOYzsd318zt74nBJTA4d4q*=QfYy$GknuKgPE|L5<2 zd<$r(q2|owa4MPPOG%#<8lbsay?(GRWfB+s66yBbYWC!`Bs@sJjEqa<|a#~k&JaL zgUWaZrzgIsjgMs7dDGk??G8`AyVliiR66_ge#ED{x1~GMf8@>g)VkYUeX^`(dE8Fn zp6kfhYqfS+wz_Z z7%p=-Zsx)Ak=1ekPU%fXwci5$bRG2kwMkm$t$6?G`Xp|L%5G3t1BYMcu$RMcbNEvZ zpW*NThwpOeyiv)S$l+`bzrf)-4x=1?mBTwYe1OA#4&UNX#|0$%OW|-Lhch`0ada7{8puUJiF~_+1Vk=I|*FU*qsFhaYn2xmigb$>Deo^Ek}sa0!Pc9F}pohQsqY zY~-+=!_6FC&f!%YUdQ2f4)5UbUJmc)@DUF8ariukuW|SX4i9tqA%|vr{bwAgmiYhs zICx2vM4DkfD8?=hJFwBYjz2M=VI2N~{A3FK=t;Y>tGa{h~;S)kGuVyipP&N|fpt_KltGrLB!^ zMItUKTRLKqmKyA^iaJ(clSGiXlVWO`>MtyA!|qFn5A@Pj)D6axi;k*gsiQ1XxA7>l zsBo0E)isnUd&rr%V&#xqu}bV~+oCPBPnE)9Z281d6>CO0S9G?@&09^~y5@)&Bx-S8 zJ6Rcu+t84BPt@fEt*ou>!p?S+8BHABB1AgH@Ro0N>!zkwwA0s|)sfihR%O#^2yU*A zw9`HgwM4Iodz{tHkx09E&{-3SwluZY#Uf^Bh)0|?%^hfhHFeFM5%IM1xI)B1CufSZ zWDI$t3YpPZf%xs_AFR-UHP^SbZj|v@B?Bj8R$Y60n2aw%tWy-2p3u&6H;&#H;kx>k zhUQkW1yD-|Y$TMeNQiK~g8nGNjr5i>mgAZfjYew0E1R%d)n6zU>R~SF>w37eRnorg zs9Oi)l(^r4K@W-$KXKGY==GgP97<-Nqp=V`cJ%vrCyNtv zoyvA3#0qCeEZU6BL@7b7^)2n9k|6xYuFSd7ECQ)7S_k}J_?#ZBS`{ptH+MF=oU+YC zp8sy2mX3|}(U@66D&_zDKfk~5n3b$$de^XX0*jgH{bP=u-s1ZY@Nd}yMLSi$m2h}& zm%sg;nV%qkIxI|z z-_#>1pUVGKfyv*?`X%#I`4^sS^6zB+J)g?|O{@&LJmU%_r+fkA7->}br>-&i3j>OO zCT-x4@u&FzagNE~KDkhGIgY_gB*ouzp2^?E{BM1F`(I%4w@)jSk`Epy10{dbmrefK z6BYk)*tt9hEdF-p|EbL7=r1LI;^n6N{F9XYr$4oQ=EK6E+F#64{L}TLWfMiok8L;k z+vh0$3y;nIAL?gpffsYF`LC^9wK`B7m_K{r?72dlJ$sJzAG-o|2sI1qqB;DDY>wax z$DDPYP0bDJyJ1d}aqjH=*##WAdC|h~!ufQFHA^zgn>z>VR~s`V!h)?j_MJ=>QayCd zRllJwDs+z<`-Am3Cy!vOEp?t&1W>1Yp3`y)Cn)E9Zb56!IS1cb-q^pH0Q zZ@9Q(RZVbhjp%pkUvXW8^0_JtLT%U`>v5My<^;-IMY)P89#`c&MM*Hl@2Z@yC|_kt zwySc1qVzB&;Hq4xC|5Hj&&69_ZiZ`Is)6!d<(rE;Ffw|XFyB=jSznAAUhBG1HsK;7 zlz?y@6P6Gm2*UMDIE4r+K)8VkrxIZ$2sbjJkOnkI2>n(@D}l}x`gTUw0-Y!H+Ze3{x=`p}V{`-1lZF0uM%!Igb(@9$4MsP+s_KE> zE>TBLm*%Q!0KS9quK-^M{F{vT0`F)S`W=klLh-=wWPAt3Hwpb)jNc8s0r*{v?*zU` z=-*~^7tqB*{|=*lKnqaqyBXg{IO=^5EiMBNheIKXZ;dPZn z)^)D8BA(=kyS*+lA1%k-g8B_LZ8FQJIBussZUydP$k?Yjc9)8^rY|RchNJt2MO*2g zWrlrTk$Pt7s^t|GWx^RD4U@Y3teT*3ezA<;Gf7D}qol4h?xJDNWr_dX98iYFWjqmEp>oDq$4-oTRQ!66W4zWwUU;Ft$sy za!o~P35Ek{snp_7QI*htOzKby68cYkD2>yTi|LO-R70-*#3_V?idL1B1%>`LC3H|G z^bz_=8fEK{*(%CRshypkE08QrlSjqefKd-(PZ`pY2jghR3GUvvp@d&6tX%fr=0Yl7jTs$kK)xk#jUxE{gUMk+20!!z5W z4S2Jj6^L-b@)+yvP}EMQ>aLo)^@_C7MIEc>I9*k^XcFBRX~4AF#6-g-Eu9tZ_3~-4 znUlMi+z5ja9*J96HR0JncF}6sWNF3-{UYX1vt-W|`j?nE!c~HMMingM%Phk$sYwwR zGk2yX0<-!OCXP0h@}-iT`On|n==^d^)lIFc_|@S5$|{pe`exku+%C3a40!`$Psc=3h)aEF8nTOW*1`6(UCM(DWa< zPKO?GgaA{cY=VneUJ%Immr{} zb}<3^5d_rbAtpc}f&dNpFcY8wLBP}DznB2c2LhfCKV?F%BtS?1j0rm=0b2SIChU|1 z($ha@N}r;jtbI)BR}>WXQKlSF6qNQcrW{rj6n8gMx*Sv((%5^L0>5#xGe}L##@FBp zPuG7Sm2=jL=2&&zM$GG-F6s^77yyd$LrEF!@}dK!gs+M z`H0CdLO70ES?P zd{@+6wRulD6U@7b(?hj(aE)}4F40O8*V5}G({g+p;nMP=mBBDvfQCcC zB3zskg?g_4x9Mns2=2<^KB&;A`qk2nNcHQQ@%*306rCu*r!(#(Jlc#jc}#Ihj=JcE z2Gnc@6Fnf(iH0nAcbg{XC#nR*ga(?IQjE}F^s2*Q!&EXMu7>pMDIgg%=oBSE1> z${fZsC5O=S86OS2xv@?bvw&&YptWsmZ4>%jri=vzcki(Fm#v}aj3<^zOB0?N^O+}? zNm!|4>CePzDj{a>LjSvHM?EJG6lB;M!4vFcf4+QTogy-*QHeoLOH5PQ$Ril{3dd1B zqc8HWN1r(=j}@~3DV-jQH~Vx&X<5+h)J*+)|7agNwY&~@V_PwHZ{Xqz-i=f=^06SQ zd?Ux<`G?asOq>YDHx4QEoBV2-?{x8Kt!b;?(z33tSsjV#H*>rvDO5&7<}DnR=Bmaa zT}5MsJnO1!Hud_goTuMajBR0EJ*EOCUQ<1iZs(|xW}Db+rr+jYimIEHE-9)h3YU~( zKUY&xbrxK^KI^}T>dmKM)@JNEE)M21iX-%2m^Cx=7$!*X_vb^7nN5Y*igV)Q-9CD z8+=aB&Bq@xSkWKW-5ERarX1#^95WuJ0dj;IGhVq!(sOvsq%g{3CN+a+q8c-4jPjUC zXOzdx2u69#_!!Mpqr;z}7S-8mbYyTWkB*Uy^5_`Fh2+tZ$taJGEJk^BjAoQa#|ez` z=*VW2N5>e>h)2g*MtO9MW0Xh7ct&}2OkhzwIwms8qhk_RkVi*=(MmNsCNsKLjgBdd z)~eBw!x?Q*qa&BmW;HsdX3(V9bJ|UElPm-T5GPlD$-qeU_N6{EoEAvP~RkMXQl zkK<}^cr<-k#yPOGLs#ML1G;b^^i#Pc!bP_tOf7m^25EWPrVQ7wg>tOvIoVcGhUB3a zWo$wYSUI6AW?_>YLa&r1Fk@=Us>8)aWo65YiciNTGV{kW?L+t;q0u#DAFZ-{G(;r? zxxWT=j7AT?-%~uT=fv1h>8k3QqE*Gga9B8<{i#{Fbl=&EivbP7*)O-AIka~*xj-Bb z7N>_qI4Wx@D#K;LHNi65vIvg`tQm#dX;3j7WuMAq7*in52%`*DHLEL2SFNZh5*ysx zT}MWvvFq0f_iem460YWUbE_lVUvn)-J!sw6++GstxG>h%F5F*dq94SXrWkh1?r$(D z+tq+qcHOtLumI4rgnI|0xfCm(Lhf%eDUUc5=?*5%BrbU)g`STc!hI)4RLRG=))nzqe3?XDj8cRTR(TZSERaMbhVjQ8x3La1J z>gr%sNpMB!s$hwjKm=tanyA1tsm_xKW`lSx!PtgL*;5HwZDP|1qm@`qX?ale$);ak zRDnUpJ7L|*~7^$ejHbd;TMFmU370bVXb(+{?@g!-FOB%^Dxt@@e;uT`A0?Mjk z2-_!NymeF!D?UsSR*_q+=bB(q?C~CE+7+~ zp6lMhARULDfV|1%x!%%oc)w2Gd~2e;gy)7Az&7b5tVeLzQH<9uCWLXRiSApeJ8lh< zV&OOj!YEf4vP=eD1Sq}db_bF>!Wh1=6?%WfE+aC#_9)TNa6&2-}{(oo#if|n&D*u3Lb-TH{Nr|va0Y53fM6jPwGV|1TR zo~-m5k`~+ywTcutxiIM2HH9QaV1UMUPf>F4irGe-W5{Uq%eNtF8nF&7!BJV?$XWlL zvaZ49Icm=vRj%s(9x#$4riW=)yna&{IZ-We1&*!+hH(xQmUo{P<%dzA@CMjEVJOh< z)iiC%cr;#PX=O-g-_^bV1P|HoK^TEP0#H)oncmRZ-i*tiu}HYR9rw(TPlwRDA>oIJ zol;j%2#v-mbsGsJYEIq8W}$75LN_vEUKf z*A=?<#Ae#hYTwYvj;x(^V)8ky-L8>YS-&ccBCYG*`m%Hluccrp4D0Q_x68 zGFUgXH;MEpky2mRB?C|=IVlrK)(ZN z7Y>iik0a(a#NhAb84&za7T5=Z_Pbe=gjhhYlnsJqK^p)n)1q?#%%)dS@~;DQGU|nw z%kBes>c~QZMTkR9XlqHt?-ADpwnZ-j5Q}LVUcxNjG+9%$Ua&44PS2l-S@12H#r#Tu zQ%4n24&rtWwG*`kt)TA*%fjK2`CAb)27@@i7r+GsYzJ^PfCXCsyaZrjB}?k!F#j&Z zOoHWG{y9CX&_qi#EXvAp@zy?KZk8ivCy$h0a9Dzrs{-gbQrgaY>7q}ckSta zEYtUMI`eRUADFMU(*K0gXTmNlmZEh;N*UprwiK{%4NO+Z73dUC3&-Su=4oZ*eheee zMp7h5(@bn%A{7DTDvJ5$!2luC=<&8Rof6*hk)$|1+GM<(xAa>`qD|HD3_+4&B++K7 zJeToBU~P`dDPu35mM0_4sbX0;ytye{C$vQ~foqz=FA~~fg=f$rah=6lPpnJMv{>uI zU|p*4rSnlu?bK^zr2l3-xRx%}Kq>sDq&Ph!YUx}mWRW5*rOQWJF;~Btk_Tx^gW~s7 z%nC!+Z|S!PSxK8CO`D4c0(5UFCGt9)U4=-6X$>mWa0RuO*Wod#xNHq&QK_hYlL}th z-PKA)u1TjZmk~88B0Cu&AK&uny;{YMH{@3Pr9@v@>ZL<8=f$ zYH26cXzdDB*FO=mff8%lX>=VzJ5>%gU@xO?+G!^CV`{rX6N4obEy>u?15P{1HsG|m zO8nCQjR7}gtQ}*J89q~dmkr0Kp!Q^%HnpE4U z@;Yu|>X4o(;?+exEgXdwp=qO`7k4PRR&;y2VrZlh4h9c1Ed4xsRy=|#=%O5b@A)h@ zo5H+k{ygtCnU^HZ@F^WdGcyvJ`(YFn_0Q*F?ofA;u)(1kT>M#Uun8Bk>g%En|H>MS zLZS39cJQ2+&;mbGl_(rmiO2Bx(Z%;ZYbEe=ULBq7|B5Pf@D0&(sS5u`7tC~Z!R)_% zq3nP65}6@yO$f&cWQj23oe@XV5j3}+=XTD$ ziv+5a#$A-s;JX~g+l1M!ZW!w7hJL*38ZOU2kie}S(}-uBlz9S%zsoZL-yUrqzP;ZA zyZ2oBB1ojLagvOG))5Q#Yk9`3Obxx3Di@=C#8S~%Rkul=Mi{d*_aQmXPE&)e4M#`M z;b>2)6<6BY5ZNq@e2(!aV~TM+xEu$t9k?*VvDvBWMCt5Ew2katc#k)e3XK!iRI-)X z&ytLJ9F;5hd~JATjQN>V_hZEhW2LO8p?3J%gufw|H0-4twzP&ZF?i>2u2u=U_6@X1 z`d{&-olDNT)A6D*Kq^@Jeo2i29MLXcn$pfE?h)<%<(lv271IPW>K-9_4vvp3Hh9I4TsvfS;I-ADTNyb-_exnGyo@%uoFo1 z36v53veAsO=4fQSs_2c{5fIy1rl}gRQG5!88>8CnMrtArCa*tGII|cP)3mW46EcUa z96cA4$&fz+u9`8ja+59cyo9?YcFjmU0w{f6eemUjYdmUlu;%R9kCEbl~M%ew-V<(**D@=ma6YoAI;((+E2 z&GJqtTiyw@Ebj_2E$_*wq?LV-?6zuLl}OSam$adlcSK}#+K2Jr}%L?jS92TKu|9*-%DR#-g|sMHfdq@H95 z^+X}5CmBLLQAp~ELZzMvQtC<4EcHYft0&1K)e}LMdLqP9PlQ-~>PZqvJt+#QCxVoEBFIutgh=&7fK5FSYN{uKho~nauzFIUQcnb%>WN@W zJrR;rPlVaj6QQi02(;9bLQM6Pj7qAaJ+j+|t0z-l@?elCQawq4)f2(TP){Pd2%>WL7$dLrDWo@}V4o`_~wPcALofUBwvIDz4-p4upFAykz)BX8gt38hqq zA?qgI2D~#Rv{A%{r7lE7T8D}lBSq{OHmM=vDiR@6kKxoFrBf_N4BDhWD>c_{E~kD9 zTo?4hz-L-cZH{e@$sdsa9N#?{KzCC$>rgs~=;EK(B_WNBhTEKN*^ zrHKh4O)NP`6Dt6kSOL()k_DPr5uk}Bfi$tAkR~QbX<~vbO-zW?#01zhF`=d=CU}S@ zCIV|>1u9KUu&Id&wlpyzNli?cO%oH!nwUUK6D!2j#K|bTCN_DJw8v#v4qYe`m(;`( zU` zG1_Ep4XEbyJ)5U*C#)7f#OO^?wui~YGd&G9FO^I>{1sXbv9u@2@X;%@Tq1slh&YYG zYf?g+N~vE51p}O>gjd74Jh{8k7RfnP%bA+GV>-@84kt5TL}}=E6GhroKw36splNAi zC>W!VbXkkB(1#-^Gm$orBF9e$LBneTDF}VG#9qhUd}83UN%1;%GIdCDOnp+b^Kn@C znI03kav{%vot7StU)D<)Sv`e8k7)AgA!tCP(nz9N)FPX3V;Sx05qs% zfd*9sXi!NY4XP-lK?zbClpsrk5+XGy0X7XvsHs5-9-={sz#3G6N`n$?YEXhL4N6E- zgA!)bpoFppCD78K3NbZkGAgMp_sDJ=zLquRCD*b*Pw*kG^h==G$_&R8q_GFap?H^ate;Rn+D3zyJ>a;E|loPMd=;4(`a^w z!*myGBVOxK*I_86ODpLc5sRJlF4jSC*Lf^%y38W95qB!)K4$iM?g1esDI9*S=s=wA zy>-w9qtq8vf?VFmdp?4eOtNpRuWyD|FN-~m*#pcj9v?|M@Oz(C2i8Ypri-=$Qw=&g@P-TdS?JOpLeyt)+VC$nMmjz8MvI}5xyJP&727E-k8az2Zl0p# zm?1;Q^Tv8Dub3S(+)U4+99x9tm_fxjy*Htw;h2GP!IkZ#1nXU(gXmEI%bHXe4eCZhL5Dn~0mW;tx4INs2^0^p?ToGk zI*%MPsMuPd(lLWVHvpB685G*?VaE&#-Rxn<41|(n1`j)CQ21AXE5{59?**gTi+LmyQ_}x(ldu%%IRdpvp0W!uJu5df&s+`w2(I z?`8aD!cp`47(YNbUMBf2;{$|C#|%o|Vc^O!gTjw!X%FKlj~p|2j&{uOwu-`TO1^<^ z`Cr(_(sy`0!yPjyv3Gkt$8gM`;&$5OEXN8@v&da4)|$SSV+NJDZ&6U?*tYud^`(xPnFvfz@b1A;lEgua;`?TW_m9JcQ z7;{O3syuM;ZETmQ>63vJRJwAa@DmN$4{@{bDXVk zQd0?!>Hi={;&%TBVNgfLyj4HM|G_NKl}@nxKUk)y4l#nd zjCg!BK->zaSc&_@2x_--6F;{9gRet`e+T(LxEIsaW4___V~NreFX{ilR?2+xe?Ym* z(vdR&0sjYz02KuS+V(*vKr4ZOmfFPxs38!bXC7h#^bQEp|ACSLMFWELf1n6ZFd#_( z2a3=u3DW<8BJ7X^>Hk0xc1nWsf1oIRih{ECnI%ya6!uZGD2js8KE{;8ih|JGma!GBqPj3cI#*zHG zwtNLnzgE&vMD^Z#HD2Q(pIz*)AW!ef*bZBYXBE6@3H|DfnGj6#qr9mDjtH*Hpp0qZ zH~baw>!nydC(Wbo51IFs^cy$=D==lK$HR*6GU+#RT&69~`URd2EPOZ~Yc(@1UD?O4 zXyJA};&0~o@x0c=H7R@YTQZa$3s})ZQs2taQ#`{jHtE}0FfKN+e}G}_q~DgY3(e&8 zP{TVtdjMx?^xnw}fLzl+M9NQjrPAdz9s%d4zf$Qk3=%imvRHUhcH)K96R>?`iv@wo zVnGmDEMy3a1%+g>kRdD<6q3b)LS?ZaNLef-&9Yb!#uf|7A}tmKSr!XIEQzu}}n9EF^&}7K%a^3xbrzf}jw#*YdSILZrol0Gq{vP}5>T z@DPgy5!hm(KxMHY*tA#>Y*{P_Nm?ujvso+%Ws3!Ymc>FLro|!|Ww%(EJW1N)vMYz$ ze2Gh1EF{1d3xbbfu^_VD=BwD)VnK*yv5=gm#exvK#e#5~#lnVK77L=;Ef(qFaC;bj zxWbLNt0&xZ=(<=o#ss{5m7pnCRKS)w=0ZPim$7e{qSgkrmDI+nRgM?~AL{stJgJnl zaf+yok+0rXG%CeSyHZ@@8?PeuF)PT$pSf~?L|(^e6BL7EjCJMFS{Yk!N=>A#BUW5k z_}WUTP1=JAH5S+9l-asE7z#&dJ!P5|aLG`k&9rF|&7M#Q3{MFdjEgdGLyVNUb}ns) zx8vQ4@j;kd)-^YE;FU62TA`gs3)%M(H;xp&c0N7fs*vgUlBSOKx)|O8jPfQE*AH%)hAu|F6VD>Fo?<@%YO4a-ioy}RekXt0P%Dtd4{)(_ zCKiGjR(050o=byp!VhzTIgzZbyvQ9#<^&O~Sn=*e(|@Ng;p z{+jgLqb>X%TDAypbWkDIw|4T2b|`+b5&Q6J9Bwyq?xtPkDkLgJNye*J^C(3F`4!Uo zh}t#Uto375>pZ-@VKvKc5_c~ssvY)F*{{sTm(xR!*b%f=2t$T^L{1WuA}yWab|rgO z1?XN!AJ=mPjnb=zv2IqZvoDgYg_jpXvJiobsm*sCK_h6|WE+CF30RtV5arTE7|-(0 zWXzW@5q!?RMolNaW=LxX(~9-)W47YcBh7g#TF&Vy!MCBg3J}mqi~BpW)AwxY42){2H`_7#nhd~At4{oF8Ay-WVUihkZ(P&L>Bxmx9x=zNO84#;ZA7T9iZcyb9M+@7uYPSM^% z{0)Fo=?hev9`sg(TAxJgnmWj@oBEv>y+Jdz#ifBlu)|_D1~1k^k)@;TIL9GrXM>b3 z%dU-}vR_MhT>)aLX!|5Km$5^@MnpTBad_^N1-~}n!@DC|1{FiUwov%3qQDC$Zq8f3 zIiojfU0jB*a)@hFjZ~CIp-rSJju?y5WN69a|5(%v&eee1gpr0J@{*G#xYR<_Q43JnQz{NQ~AA0MUTS{k!wh>m|n#e0$JNcGt~LyX$6M z9!K!805z9hU3zvfTqBGdvvgoeoa-(U2UjJg%jBURl)d5dU^yHWhL;yrmln%?XjQrN z=_&GE=ZqK)9hO3S7SlfFI(Ni;5}qScipYDWbYdbmHLmkG#$$^yfAq_B{s?-54@y6U zHluB=au4eYkC-NfWv7t!KO$VU%oa$oQr0mkH>HMtyvwzY@jPK1x9G0=5obeiDz)-T zR3VL;2ftnFbX}7{ug#7aZuWEaW>EP?*v)>fYbDKci8jofmFMcoxC^Q?MVkFwS7)3I z!PG9&?B}{JgEGcLFJ+k7&vm^N3$tI!P_v)w29EHjSf)GE?B}|X<1%e=HoKkcCXUZe z#@h{duA4c2e2O|^9%}Y;-IDQ5**yU(dPwS9IeJRUaI>FlI}6UmJEF%lkGgKl*o|g# zd#K@kmR-)BaxShe__3tmRV;zZE=LgAgDNZI8i&9ci8 z#&$W$BJFYnS#~)>EV~>bmR*hzvdc*hvdbv|b~y#WE+<)Fms14THSU%Dctj^va!@Gy-&$L zy@Za5q+ev@SZ0cs1hAEx;y1E?X>HY~XRr~8D%^C?^d2T@w)UNSNPb&$1AIWK-)q$F zF*E6i)T=8}@cgt}steCZxa-&;wEIXALb;1flA?XL9zwFhVfnL!Vf+$d8-9UO`=_S8 z1NvyRa}*domPU6(VI%wJy9Cnj5o-S&fT9*BG_(zAVxi^081{9T8M0w3#Bag?r{vkP zzZhOe9Jztzdfn}zp@cVm;Xn&NC8G?ZcyU5AmrQR?E|iH1 z;g#k?$QzGennXN--vnvGM2tC<`r22(rC$r5jUItj-y~WyWwq2rFT`q5nmJ|L%AWz% zexzw-;Nf=t(OW20V4cwJr)PHno%0jwoB-TsJ@5r8@Z|eZ+QVFovvUeTf-fNC{W}Pm z@(d!Mf;XipF9VncuRBxd)$Pjx(eo52vVA7#F zyh3%L>b)wfhk;7tRA~EUXW)l9+apc$@UueZOqEjiLWHn* zJ&|m>%IC;q8s&f&p1T$6NiDGBq6~W^eePtul}@AhUY0~FH?3bA2_e%0SaRg$qbFB` zE3XK^x+wt80PuYR8Ufss1E3SYGXQdP0OX!PUtWC8(sEUv3pvc|0`(m*PHQL831CZd zWd+1k>MfIR2V%8Xv}ygsor8(@{G9;Y6kEZ7w8cmuu``d)%Gx7&Q z3KTLCdu3{VRQvmJ)C_M>cdL@QJ)|Ed;?-re3Ypu%@&naiwaoJ0%tJh!fe|iF#i77w z+Gn=ozC(TN^W4p}Pg8X}>qHg)1qTo2Hq*SisCQ}iqtX6-Y{1w6nLiWbh`fiQ8FDw` z_~I-KNJH*M9MLz3Zn^@=Muc@A$xyoy$HuEbb$Kc%k>wqP%*tp0`^H1JZ#)dTVkB2D z&VuJCi{wVcIhUGA<*7JseoD%w-+D2A@-anP-a{xK+l?f64^eGwZdHc;*o&J=S%e|( zAvU+QF1P=5fRXF}sRL_rGWd{BYh$XPE+5dc9Pan%rvr>>Owow~d^+P!!pSGUk;fF5 z|xRK-Z)X^}A z88`XqeK8zjCig}59}F;V=6Fw16#rm=aSKP8`?O&Wt&LkbCx7Z}%4s{J$NZ51<2HX5 zs$f8`$aa&2T6|=m_^iB+ z_6UC1aA!OPHI4?AbHtNj&XMxE3)-UC`CS-^nmecl=wxL4*82NR_YU&Az!6F znjxDR=BB`ng@$EGQ&iqq-hwAf zMkOZOr@G!Zre)BCG?m`bGZ74_Sk$>ZpTY($p7AHl*0f`L<~NpQ+yD`%uj!fJIF*Ym z0(Sc-+&n{E}mMVqsLsvK^fi zwxWz5AYr=GxF%x>RH&db#YZG?&np(3q*D1SZoXY^s`P_TB#@PTA7T-*NV32Cb${I zC7lg;;Yk>0a}1ubbR1}$!+09TXENJ!nd&zmb4O=voF{8wj;CWVoS%6P3g+@q@iMHR zZJ-}_aP(gZ+DQI!2S-1xnNfBuN39=saP;3I6VtC#8KLrulGSBF;rJz`8>NMzFq>dP zh$J5@TDDe*M%296!(^U{iLPZ|3_Q#3gM93JSQU-VrO0uA!idjm$L!-Nsg2J7MV#>&VS-^bTDO4r5w+d0&-Ws(_FVOkg- zHpG3Q~bo{wpZ|R>Y|MS5p4h5-Rf#QT_*kVw}Vw zBA48=p(uP_yfPBwcEC91r3Y@2$s+Y~QTB0|o+rfLWs$(q3$Z@~K^3QgiZfNVO@!LU zHRCwB$m@GTYu9K*_OoD-R|rgq8Aw%v%WX<#lw_*G)In7|ssV$W>CV~ZvaF_v4i?o3 zQGF1V6Ilgo*5!90`9YAB5jGyVtE^lB9Bq>9X*sWRujrfbn;CL~i`bJIHdB|N+f z+Cn!d`!pI}Vn!jp;FFreGmw5V3>V~$zK=TW!C7YBk5S&Lb9Pe`PE~T@>mOaRX9=bo z+=g>m9;dRb0?JGsSpP(0Rcnfb_5|tWFCxk|Bw>YC{`bvSH-&ak`vxTTaQH0QDIqGq5XxbI(`lnM`-U*wN3*9Taw$rd>u&} zJ6PcCh#;q~x~N9CekSV;c`$5jFUbEq?KkEx*Vms|NQD*&j1XNzHrN7_`QEDy=b$6? zC8(M%zWiA$u)e;Y-s1f{%iqrBo_Ufg|3O*)&;A4F$rEsWr`Cst_!qxDYZ;S1%~o{W z`)v4qUyMoITeMCD9Vz4Rv~c5ihED_uR40N2(TSi8aUw_|oe0VhCxR5xi6DjQM35kL zA}DFri6CKoA}Cqpi6BANi69}?i69}?i69|#A}BfNL{I@Z5mW$91SJbj1Qh`%f|5Wd zf{H>Xf&{4(L4vFkK|z2oix$1Qn=G1PL}z1PQiI1PMu=2oh#H z5hRpP1PQcG1QlYQ2qvTKCxRwVlJ>al%Aq&)iA$acN`OxU2|mV&Ad#sDRgnfKDK?AR+b>LBee(f;QAT5hR-ZM9@PnR>IPARcaS0POJ@ZBDKD`ZCzb+nEb=y z`H-oZ^Y$*Dzn##Ttr)>6IKLT9033H0sws{87c{nq3L+=>5ERgMvH(9TfJY(dF|en$ zq72}eG9HEK$Oi%HIfsyYfT$~Ow7}LDXl7DVhd{%nQ;u)rGeY?4NROwz2}IL;ZG@yN zB*k)*5P_qZx&MGzucND5mHPO}L=_$wx>x~C^_kTF`i?N1chlqc^HiYu+-@JuROOzE zE9j;H|KG=AZ_|X%w6yi6OG1dCT9K0-cGKaz3D9Yk^AV0}9;$R5~9}XuHAA2Nb&5VCMsblJfzBoewDd zE5McW0fqMhSI!3%ehbA*=K~7gLGjZ0fWq$vuAC1jd?#?}d_bYQfJ)~B3he``oDV2` zAK|F?J+fwwoPNSl@p~D6nQ+wnKE@9aE}ajk^aF%T=K~5q3|u)MQ1}teD-WCDe84!` z`M|mq*&=YNDNT7c=L0JB4zDrX`GAVJ+iM)d`GAVsX^*p<2RzLc*rj5v>1#P3P>K77 zMO*2g<@9hqkizGCbekcC&-Y${x=u0A_tFvZX)Cc5>$&gDzlRdqPwkQfSp1x~N>mCa zbh||DP6krg$-rMBCzW7@pQP<3f)uPMGc`(^=Ft~xXX8yz15N~>UvN8giKZrma9vFE zZ>csYr=gR0muXiF;XQRI?`alqdbq5pYGsg?H^G(o(M^xONc%aGj+l)vU#HLuWv;$6 zI_nx#wnbVhqEO}`>Gb6?N2kr@f#FuA6?&U%Jd%)-HC-N%2-p!tYI(ujMMXmYqU+b7 zc#iGz;Cc@P@fbT({?=WL6^bzE(qm_bqINP>H*78s_ys(JE#nQCGn-tBXc*FoK}CDL z^h2|mle?H~xjazK>`~;Tzk-XHKh2Vj`S&Fzjxfm9opgDiWcVdDDdJ-0&a^~e%3i|6 z(Wb_|)TL5qD}v?nKvBmVN4q?r7Q-XOz>D;iq=nZQ@~(y0*L=>+Cf_EF^W%Gzg^L{U)KN6n%r z3QGGJQw}Q%io2UBT@EUYa(Td|;m#l(EE``Fqp%tM!T)OSUEu4gs{HYD?@80srVY1G zQYdf>1tOO8QbH-vmZV8bQ__+)X-UiDCQWW0Hjis^(+5@>X;D#Vc(T5GSh z_S*aGbIv~blzC4IEO|iQz;R&71Hu&k2tV3=J;Gs@Q&4dgT6uk)6aB9G6l6h706{N^ z=H*@j;kV?->?II%@L|{#S^`01^TvgjK+ssU_L`h)AYlCCdbdGH>~X}`SvXWxE_4c( z*H_4*_ks*JnmH0Igzu@1~?NJTX@2!4-uwlvXV#tW&Bh~mv0lEn||wf43& zws+8nts|I#;|mG7pt$Qo$N4a3<7cVclohN`EAi*po;L!Th_bJ>Rfbh&B@SJ-S2iH9TdawC-SzgX3ES?q*IOA z@qA#6YD{9ep`Ai{7F|)B^v4<;8j-Upws3KGi?$un@L*Xe&Y|Xp7jyaYFT{nPNXOM^ z@kCtv;e8>#v^|xga`p$IMPwf75{b-yfOhBWgVO?MFagPhP79DgCB{03;8VO#iV4i) zx~jw%NjjTO>?NghzP6I=FP#R>{O_+!;?bA^YhfeHrn%jg7v^Q+B=a3wsOgw$4{w6 zcO^y{@8+5Dt-IiJ#83@M^S=6Pg83n|yjO|MxMX!zE#?K+)UDfyr9;0Mc@4v~Sj?nq%FVlzz8R6lg_Yn|!fx>xTiV!MrtslO`AD3KLSB*HTs;k1+>yvT^yK?!m z^;bBFyt`)3!(4m5deJ5C(=*G76$Dpc%}7iZ(PyXX@HHviEosIZhIxO@1W^#+!_3IA zasw~#?wQYn5&D6Ayhqc7Z`xL4k;>j`dNC{SGc$j$_{Q>8e$n@z^7hSKt+4TYl@;)u zdv_O~8st-RVUk9CwKs2w5yiPRQ{&{kdsw@9`L$_$OIW`kbuS}JVDns-aEkK|DAn`T zC7AlEY~Gh=(j5pg1l59-`pV3GN?$J@>8r1YKHAG?{+7>7%D-wG9xH0CYokw1J9!V! z`~ugT*wm&v8`Eug;MmFgDxWBVruax{Hy-kL^1e3nW7;0@GC9So$)ztQhskq!_sw)L zxi;QAGYZOFgihYqm2dO1eeaC>c0P(?fl~FlDiT3*OKJyRV~fnL1zx`H!FW8Of5sg^ zPXvt?Az<-iJ=IqlvgVQyvCVl1(Qk&3{B!Rf;}f>hn1H z)J3>^p5QZA@qX%0a3*gdahQ%iIJs?Msi{7m-S@R{BJa{KMRLL4@cvSi{VYVxPi!hkL!}`R_iM*SrZvzT-r)t|`d+?e9)_?`In&PDogHlR*jV0b% zQidaZFBm*%%{wi*j3f_T0!g^rv{j2*Muz$Y;SiS^RY9mLE=6&YtKUn;ci+%r`BPXs zFuK9*JeDC@`}-*IbCT7DXQ=eDEKXzxMe)YVfR&YGZy+Upq%nBCcq>iizK{HK-C~S7 z$U_I1aRPxHx%um0S=0b<7C8t{6DTKgPcen}kxxu>vQSJ;uQ&LyO3#STIty$tBKU9_ zamzZ*kJX=Y9{NUn>XT_ElW9*CTkAJQBj=EnCb(@(gZG{hzs@prUB@*X2)^}tKD~>2 zLg$*wTB8vKd0NSZAn`!i;cMOIg>x#DU}%;18cx>{$+B;G4s ziF~gD8`d!;9CbIVKM>ev}Q!kokSu|8V7Q8OXsNF zlt`p%8lk7o!SQ@>pEfO0;Pak-a^PTwQ4X1!q#{>>z}LQL8nj;wVY5h>=6i}?!2%L< zD)WGjr1I=MslGaUS}_>Ro{ZXb$73CK*Llb52R*@=4mRBr&cEoH@?7 zB6=R&{PyiWw*>OYaEAEo5+}?7&w^Z}>UORn)_jW#kY3+qu;k^kiBzrgjKnCa_3jca zv*6rGiUyG|kBb3SHBBR_;Q6OTE||71vOd4QU?YrQQUK6#=9fAb;ADb!Q5<6?U#X2M z)8T@^A*5YMJcuRnAf}}O1p4rc#xa|P1qjipsKdoUsZ?SSkvPsJ!GeUp)HiRI-uTkG zIN|b1C1p`#PoTR;>LxuNWNr|@j;JyrcH7Kgv1HiD!dcf zNZ(|4%l(K%s6GCk08!5TltptYMyLNDdG52>HPtVZ6~wN0q0u`2-1@ ziIk~E6U+w8>a3-a=j-Z>4>xiz+{p2av$6+xP@A8qJMV&U=RHX}@5w=z6-uvslJv^4 zV6QwS*eg#pQqg(qUYWXWzgM1N+%Pk2&y&TTMSew8|1pbMawmPtaPe?zI04NLhX=KH z>T9{vqSnsgLD6zX;4G{YH)nP5%n2giNvH(v7Y=z0tHhq;#h&l11qNDF*m5Qk!XkXwFi>y1HZt*P{_*o-wNQsH&Bz9u-60fXQU2>xVLix~i_+qzc5X zlf0u>IjyS_8LK!-4 z0-A~i5;C1VGY1znNH{A{40LmK<~!Tei%OppI0Wx=b<`o)q`tZn$QcyD6r`0OCIO8U zJ(P*Y>0wZQI5Uiw%-{tRSZGXS!hd489@!(JT&hl%_$;JrqtJ+mM$tK|9H@z;$2>pK z)CI;klj~@(LH$r5s8v$MurnOn7@+XbBv@0KMNr8Jt-%Z=&=!Jo6-cjS#gmL=v;(Q! z6lr`@g9Ddo!GVhmQdC2cxdmii%q;|C%NYCQfUyxnMS(+9Ie2-3v#01$->EwM=u#w< zZmf%uoOU-7^ic9RM&RTpbap|@jxyIHo|U*$4lub(nMpc8?w|@}KsreeASUZd7nP< zGE#~;AwDqr%IXcYMp~E|Y+f%rc6?J-H-ALp=&^oXH6JUpqOG@VZe`<17 zO|xP`bv{k1jyyZtoZ8&p*fl@XnV#R*+cQ7MG;MoVQ%7HO%JD@22ul%)6C`PVy0>`? zZc{Wl4)oV6ilds_+Pk_kC2cT*qi=U;80h9yi-u{*sZ4LPKIqLfL7!!z!uZ}b*_ z(|sY58FGJhqgUciIpX$a+{p*s-o@_Zmb|F@(!>_@7Z3Ce0RHlXRe+Cf-9P`DrI+G( z|AYY?Keu(&U*X_yCS-8%{jCSDb_+^gd1>gEz}=w=yt;MYqlY$nOWn^!>b)yBx-Z>0 zu<7sIL%TBW6Hdue+_;bCm*l$zHvx*ceXDMEC%%4V)rU6p^=;UyPPXK?yFYeXytAtM zUU>Sq-g&>=>wbDyCi%nE5--uycH5&5xm&zd?uyqNuluAsai4dlH{acS%$@oC{~dI{ zrMJeeQ(F#!U;{2`$0H=s3jfa@aBITu#Aze39%Var=-zD^9ULc1GK9 zzoH4RMB}~-F?vI3^ws0n=mbSPqOhYEFJfqQ-cfW1S_3X*qDNI1q`{xU&Yl zd7Ipi?b`32*0OhKlUrEtZa>oZ*zWW0aC;BJSMJG?s0-`=0wto(ckp|ho;X4EHZ6Vh zZce{HD_JObC7 zt3p(T0ja{YNMz}=k)_cH6d!xYZ_jMc1lkTg_!z}2t$!(N{6)GGJhX#HG1}<{G%6nK zAi@!3XMg$nw>u|NUw&xiro`Z*y&E?@wQ19ar5msA!`~*iZ@?`$_{xtPILeED0Wg5|m8qJu@Lt_m2$cv7PKx%!bsn`rIXpuHG zw4h;%Nm3YSsI+uy83B&_&-kd0JOB0T9<5r^>6R^a4?Fc2^tmUMxL@A2&-;P<4^BOx zgVD2Q52fRt9u7`Uw!RQce>j$OD26=V=|jEMSGF#_va0!VciSrN^WE5yO>WnIcS`+l z?{7Vi_>A^pnE@#Chi9Z@0i>2`cI#B*LjQGY2LButUoJ}1->(bFmxyu zqt2^<{>MZle~tweqsK$60V&5)S-cFDMl78asebI5{^r$fS8rUhW!ly$e|3+0YP~lz zdg%=JdavF+$&2@4nECtP_qhcFeIM;p`KcZSvDhPikJD<7`K|z2AN`c9kMB;4OjjLk znaUC8;Pi3wK0%|3|AHJ5e1u6SiLF?%s->5Gqxy3V4|_Qh%qn(Xm{Uf^bkL+C?&U3R zdA)nN7vJQ);_Y#dIo_(nXpNt8XO*~rz00fjezw=U3G$4)XIH&9_kC`kH`PnL;oaf>ljH4kCmwvvo#EZ&PC8ia&UxM4 zyszAyP~vX8>0-BVF;YsUd&-e7?si-1-T3oM+*ro_#;#-Ttmm)X>(0z9aVKQlt=`ln zmtV5_Hn+u_x^%A_TfD@blyNtBi?3{TPt7d3%{_?Ap`N}f_d}6`QM$IhOSS61*|=cgFl5*O&k9nX6lWf7PSsuipCT`|2yOC(_;{ z?&QU8Z@oL^VB045hE*%wg8KR1^{XHKnOD>aG0Xn_qfc+#wEKG$3)@N-{%-3JS3h_y zlJXMJ(gk3CCV$(N9dFNnQ6=>)#|XE;oA&e%v8nUVt6#TwpF4Hc-pl&-s@%N^kvg^u zxWIBFoIPYI5L_-!U!aD#iO~(H*>BB5ik`+w$2tgJxaHmIB|7`x}SHJhV-?wff zC+xsa^bq}QxUMhdZXI|-xdzwrCp|yyjeBCzDD0)5(0uSOXFDgfq5x_eNPEMkMrtnd zDv`S&a^HX6w#kj}bDNKR>H6Kf+cqRNyOZnP%)TXM6_K^SJ>ocXi8?5N5kEJaU!=o;|=w-ZTzIWeHGHi4?p03byv&Ht><0i##XsK z`+s`bk_+ZnKeMf;cXgYa+3&_~x_0vd_mov``?0^@y2&l@rnDY;9wsK| zT&XzHJ7dwZadc`@iXg@y->lQ^?Td$lyfBqc& z&u^W-1ix3dp2#`H5CrQXJdS%B^FN#ngCsx>yktBvO;8STs#G~>zGv{e?C zMJozDXP!QE8u!lDnl z<%RK^^U4d0_lzqqOzh6TqVO;#7^4#l6Tm%=lTU!^$@0S3Q_BjyXIJ9>h1x{V1JldY z@fjKoJrkRtreBYv!<-+^E_1=B2z8Q~vH6DYI@D`b!5ZQYdoZ2D(=F{x2SxW#y>`2> zSj)u1A|Ox;?}=pv-E{PLVXXWKG85C29waX<(>4M8aDJm#lVqlf?oiM+Tzv@t3g~58 zC{IyqdcqH}+#o)e+)|WFV1zC+8ed>OsNU`<1;@uHqGpBOAe^R}@5#_+T|?sl0st)#dWT#$9D$ z&DFyMT@{?w!TjVyuE>dM3;Mez+8A*76$RTuM;im~UtSPh6F5YpDGwbEZx@RDN6?1k zGLGiMX{#)3xIyem=lkPj3O`BxIu6-`@bbyIml!{SJ<`z)!x&^$!LWWKf7TN_pgilt*r+JhCUhyl~O(@s))G z5j5LHz@QNpBbCIFN{Wz5V$UL-d}mcb^gAP*#`1m?hoql;aw3oO7xepJv|@68&F=g? z<8IEo)m=65@$x6ipIr8AIkN0iq4u4tJ&`^7$H7kLlmWs+D(YAJo$#_~XAR@Ye}tFS zG-{deb4OT2MnVH_A#IED&)Pp&Me0^)HbpC`~zp42U~6lIB@EQPs9 zar4_(qM4i5ih>ooUGsU0KPo3HT+#|ww4pt3Ak220kXgUK40wr*{)1$%o5@~# zC|-7tL(`9TO)M-121YA_(PD@a@2M3qTrmt6hvAA~xLEm9+IZkK5C6npmTr97@K^P$ zVf&$}sBO6TC;TmVr^>&eVLrprlieNxy$tx(bECk)ZfR1E{7UC#F|r06(-yLu>WR2t zqU45+AB zY}vDcev;yfzE`8~kSVEG*JaJ?N4sszOq@kukE zT_f{Bmtut#vi((r&I&A@GRS|#U*1=|+wfO$g>0s}*_8#+72Me=50ZVToV*6MpEp!i$FIi}5~)w zR|Vvo2ebx;S&3gW<)t~)Hv-I(#QGf8@$o+q(5bGzs45+JbOY+PboW4zCREGn<@g9j z5)0*K+VOTU)auFfrIV=k7XR@8Hcw+Zom3y&O(ykizs>m4WtYPX?S;Nx5mo{puwpI5 z5csSWKIEJBZxpe5*`Lu6an(3Fxi=Yp4vLs8Y+*Dax~ztm;EZPKAuMpo~Mb7Q6DB-+e7<_fDq z-D%#oF4frE-Q_48RV`Refpw&FHFWTUE_YO@Rhh9mbDu+B8Ek9pYVJt&IN_yeBv`F> zknM$$-kx5*hTgm$iGt3CEZB<$G}M|CX<11li-1-~qP39FwD57k^qM+eBCG-ri!?Uj zIWN3!-i~+T)5=ej;+(9{zqT9Bw3e-YNt_g^3>?u48fwA1z*L|fF^<_UbYM&WU`ZHFB>sAnV*GU)Fb7;5G{(FpvS!6gKy z*?8KBPT+cMrqoVD4-fYLPPcUD#@*LiQzV0Jl$ zG-Wh2KUc|YqJAd2iT6}#fp;5ROyE5RS0wPw1{W8Y*4L&D{E7wsn877{I8W1&HzQFw z;5}K}WjN2^iUl5LaB+cYJrmkcwn$*l;9>&D49*ky3yf3BXg20oH2wz9p+ud;;9-U* z@%44YsS)rDM&Wy810OC^Y$h=KQ+OXZC8&FStrCMqw1z|h5gJtBUs;ievrfQcj2h=` zcP==0P!2^eP-g1`)H~7RA$H@peRtZr9^!M~@M+SXz$<)X)rtl^TsK}xxfml%|CCXRs2E=lvCw23(o zGa6xjrGmnoJe|#(aHfQY#3QtV6m4MrpA1g)1EfZbaE@kd$mebg z&Xty%DD&aj(P>nvln(1trM=?v@x5e*iTa!(3*i zZ>!UGiLY0UfRbS%&IVi923^ejO5G(gCmQVsvx^7M84eoS$cnV`-gVLuD;N&2d)4|n zC`XxH;P3kJzbzr~_YBVJLZ#dhra`p7JtzlKFo&~`GW~M_-U9#H;1UA=#^5X+q}(e^ zqjZo1DVReCF&-CFb`W?bpQMgP;JCqg0+$$ELSVVaLU!fT)^09ikXfyBj4&it*Dpm3 zi41e(jFVvK0^XA{0xvMQn7|7Su1H{-9HLDPsN~=}jU#In34Fc5#RP6JI8WeDFitU) zg8@TWB=BB?iwXQmgYyKwE69*xeuu*?TjQsf&a?jJb@nw7M6q08^V~ta?6gi;nUXcB*wtc0;YUat%$tGpt3nk zXGF12QX`;|zqcW~SS=%@(IEQ>C_V@~03`%(a%AjoCR+_STZ?t)Dw0Uo|d2bY6 zvX@w@WJJ`tU{K%{J}xmRun0zL5isMET`(x{4U7YsfZqv_2`oC(s8HaTA2JsV3M>^N zI)N(#bOIaa*9a&V;8ZbzKjarp3<|v0$6YWeutaLELF@Tk9jwf#Hq=zW3LmxhYYa+e z0F{8x8miwh=&}x=67VD+wN`4h(MQ#6Wl*L?P*CbKV5pe8zZ0LI!WgQaz~W~lNb#@8 zB{G3UFvtWP$yh_I%)Pv)%qH-C1{V|feuFC#__GEV7x;4qS1j-s3@#z?HyMYNbJUT8 zZv_Yie%#=S1%ATd;sQTua76;k)gk3SfsYzGPvHCb;!P>zJB0z!_%Xj=V(*sSfh#veAv)=0?*^lPbtIa{he594`X0Vddi^26(xT;>-hv6f&pB+^GPsz)Lk8yw+{unp3d%tjBS}GlyA3WOaN6LC1%9u=#RaCNW@rPy zB7yr1E+(*Cp@Gg5_(i5u3TigyS6u!%Mj=oH6ul8B0`6c|pt^xU;XXn*J>v6TE1=XB z!)^f$@3l5>$#=fuqW4F9-t_{C^U-|?C}JZ{y@28YPzh)>sJAt!^F=f8ChyPkZBip( zgOA!EjQ+-;9%4`~Q83&Q&=_+=wzwfii2l?Q{|n=O$@_?Nt;i7}xjO8ZS%H7yJq3%v z#|$neu#8jm;|Wk~j~e#wmj{)$mlQf`LLWj#?+z+zwZ_c|9bOkcvF4P*jd6(GBo;XXqq z;En*y%1rZN-iu(@xPFN>?`GY};4;J|5SSR-0 zXi#F?-3BFg6r&*pNu7VfIbI5@> zDo0Mt;n!+$h8Puotrl&hj)e17W1gzyK^+z~IRSB~;n_ z<16(J7$;c5#ly>%Q!@JsjkDFNV1$swoSx~oN4>;cFL8E{bLLq^gEH{A(U)UIi^!3i zhq;nxKNtT1?&D z49*jH7UPrv5l!Dope;vp711wh3UxKjpudZA@i_ro2z<7| z#RQgnJFsIyV3`*t+X`G`%KGfqcnSPhrd&+m2&X`@vkw~_y`--; z8PX8HZ2d*%AoGW<1eD@A4D%>czu=d$0``e45<6gj%M^d~nON2pIX`BST=`0_A*Y*~ zdjc;sxP-tL8=Pg0GCo%xpb>bP!Nmk#VQ@tPH!@D8AUW6^AQZUC;9>$d8=NQbhl32| z;3I~xNZ^keTuk6w4Q|-lu45YbUO>?Y$x74^jydwzR%T#sELh<%z$7vhP_fOpPx2nP zn85NN8*oJe-)`vQ0^ezH#RBK^SO^|C>d3)(MuK6nz@EXy1)gAVMFLMWxR}5(gYyKQ z#W*Ec4o)$I#RAKOHI#`9Ec2RFV}VaIWn%)LZg7@I#me`wRp3zprOs&01W55|iL ze379`2)xkXVgi>LoG0)v3@(vfn^k=75btwb>B&=)%YBk{0t)9GMi)Um+Ef9IYu4KvD=w%V&)PaW{}vTs_+#nTj~K_(DznUC5i93J*jH3Ay> za<#103;c2+)yNI331CwhR62o%UnH@9hEN~0UL)aemZ`{bEp+qRKBqw4h za61!`x#jO=k3<4@!T%BJn20qXG$9zUL0*b{D zjy9v3Y(}p!;@@~r5i0QS3@#?Hq$AKJ1eQ4{;6|K}k|_)-E3iyBP+5Ux8UZ*@;9EH_ zQQ6_@aI&BL)(I#q(V}INL^$PWuK9^~PV;}(u z>QbNMIsupZs2Tx{D(gg*4xegWwkkPB|#~h|7PQ_dn*n+y(wOKK7e&7K1;x{1EeNXF2lt z!i#*ICC(9g$^HFIccSRe;|98j_iK4Cci804T=rc#x#OL!?}_HOm-YE9@3ZedX3HN< z??0DbCU6dL{5{NjnZ3#8FI|M>aLGZ^75usM+2#MMk4swGJ5msG5&r-5w&S!${Es7r zM9Wo3#ECoZFtPm+l!)P9(KuL{B~2^{laGJbY3ylLvoc-~(}V*x!=h>E=nnkH@$Z-F zNoDlPafap|oNvItmIc6}d5YQiH#A?z5w$Nv^E5EDX&PFDh*%f-7&`Y4_@_5|sgw>< z8oqu*VW?zD2Ua|3-sU{*W2h93*XbQxT?#a6U6p_GX>=*a`GvvY8&s&4+Mpz?`Wu{+ z#~d}jq!~*fX;A5s%km|gd*yOU*DF%YCCsj5yJ0jAXgAV^--(6*P)XX*KoQWa#P8HF zO^>0WhT=xf2%VRMKLH>w)4v;`U#ekvqmgwSsF7&oer5sa+{lY_;fF929G%XrCn=h0 zZogr&c}zpG=tim`k|H3yUCcCO6*rQ=FQ=#g*$SqaqG-zaC_n(PjgyIL2P%sLL5Y#-*di7+FQN9lJ_O zBKd+mpnYKziOy?4t#$5f+>%OeZENmGrhB?ONpotI#7yfBa+ZkxHYu_rCU?jGejw^X(eFYnv_lGl)s5JXzov2Bk(0MrjoiJ zouK3B#CedkvNvjR)XsE^`xXeOhT)C8Oz%NxFOxOxjamW4zHS9!UlFy`o%$7BcUb_- zj@}bh_cF-R(K~$I?><}V{v@b#*ZuwPpzhN^Gg{s6_UrC{rwtghZHEnY-Q$QugAYO< zB0N%-?st;O?aj$Xtgs8D%Bxs#3YZ&oU#T%v`co*C_Dk6@b{}ZM8PaZF#4W6p^h7mW z+Kt2jg*RzC)bo*b-3ax*;Z52O%?#zPggym#SBeUWREZ%0{Ar z>4hyxa3jU|4aW!b*+lg+vZR#WGfnxTk!T=m?xszfDnX-Vh3!Y2N{FVsyu55A8ddko za^K6U?o`@rTA#{I4L}X2Gf`7}Z#+k0{wX+p0ii=1wf6`8n7`Xr8r0OoQol+bcO< zwY^afn*e&G9+vXPwJ5FI&YPgN#Zm7`eWva`m)e4Wq281FOx=490h1NaJnsD(&T#MP ze+UpLf4dhv`njd#YJ<{tG!50AYKKCBP1+9GhQ<_bBphEvDs86$Flm~ThWnjcabCBb z9DH~bw;eQe){W%ocU1gTRZygx*a+*4Qz|yjJzrwuKClb7L8779sDd)OFW5;aYa_om z06UuB>mWh<{a2v2^&y`=f`9E(iX^h8*`!bT9#A~GP^*BNFCuDMx`rEIpGIvlis&%# zLqg+^Ky)dx>U1NPA@On?$J)yliSOk!PL1Z}0nlhKlaIoiWXL^0YcCf83P(7Vpw|7& z1>(W|!+P*Z--Fwzn6;4yNuSX?SPnkggHM9mHZ6JZ75r-tt^^HfZ#MDZkAc!2418ab z$)v>{P~IV5nDPQ0k1zUBXgFUGKeFN0g<`|Qz>rtM8?}PPU^3c>C?7Q1K2>1`IFh>m z5wNa%;JcCm>Z6dQ>yEK;j=E#nN_>kFEe=CCz8dAL0AsNyz>j=jw&SrFMS`}NDKC)p z?{@-0cFH*h;2cHcpV6XsA#P6Uv1lvUoh)MfJz2iPxBL+w9|Wjx>I0J)kZxp7IB75; zMfhRBqeb{tz6X;ifxoP+0jOE1l4< zz6~j}g*Ry_=Yvk$C;YKZp{BWDZJ*pNh3NhOnmCj(vptjHnFnx2MYv)$8<@i(%sIf6 z;os1ZKNE0hxWyUo(0uDDiktjMi%S53!nyMpduIsem8{4Rk%l&Daip_uadSiG=|K96 zhXGTpxe=lX_vUitTLTF+d~+jkQ;v-y;hu7dgr_k zM)<&)JHDE_;l^;Z4b6$n^wzvkMHlpIXRj#(=5Q17ISy#788atB3%_dP-fioO+ zw7j_fkUWz~t1LsMK$hF5Jm2z8{9Xn}Xulgh1kxk?icMrcYS((6P0s2))0ETE$TU@( zNS{$?%Bd|5M?*3wHr|8FHl4BQp>CoMZxkCzgr4pz<#p#U4P}Y%!RhSN@JSqrFE)ct z`+`4innig9{Hc90dOKS=+-@3=@|Tx)=k-TwAS4KWpwKpMywyq)Q(B zhVManQX;64z8;)BOIr7Z5J}pHH)`E+{EybUi=d2-goU8SU)H9s3m`$a+##IJ-Ewb0 zQ5`MjYqP>C*_*>!$Zpw7-I%=QHzzH&Huff91LgAdYmu@in1QB8Grz5X(Dg+Hidn zzIDpJP&E6AW*SF=!aN0x?=L?Rv~-FDx_>%PQOeKQBEfEL(k~A|L;OM3iz33`%NXEQ zV05&U`sW0YXrcQqI$Gx9RCo+Pv=l8LyH29zIrx(94Td+0mjCdhr2@9GH_C}+NLEOj z(E0s#M*uuUR6qVliYU70Qigvx5qu5K*wxo>VWAFVVZ$C5W;+bN+Ca+QuhHf5W+kLOd9_xNBJ?Y>qWkxd*ovu z)B2o8==I{TvySI_Wuf4Y#52X2j_2(-eR`0@k+#zh0w@ceVcr}Y#eCy?B<8J`pG67&B`yxyiK1TcMw4|`mYFj0>~^}UYu7lwp{$J};br`f6baD~%woo&PiVPh~K0j3OR6lXsUwayfWe-Ev*dJw)^_e-gJnxZLKVUsxYrAM|? zsD(Beq0#7D$6-8lo(?1qp92k5Pv092`-12w4o|;H^3Mji&GswB;R?it&Oem(?2Y2^ zjfBMEPhq=oy{H7mVHwb)#o^hQ2hure21?lCC=TE6$Kgs_8DJ<5%iu2^hX;TmE0|5< zuoU{}IK<7;PR#w8j>z{Zt)E9)bpZ6m7Jy?(vyaTf8RnD6rIMOTPG1UB1W zTLNb_DETLi!_i`OG=EWB9s-l$+Op{Lvc!*LN%zMRzAUGtorWNDFW!&Fid5vdg1IOI ze}yom9nc_zSvVDkjN!Y$W0O8)NvEfDLb6K9A0f=b*U(r`g!Ef2>7|x*%C=$YLnlZ& zjUhvvFQO$dLYUI&mh|^n(q9>q-*2&`&$Fb{>vti277kd_UmKJ3J1yz-d~ZlrX{9Co z8B6+`W0L-+C4CZ7MObe%a?j4rjo2|Ngmh_@ANx$EcPBWOHnwDN`N&ll2 zb@4GtKVV7UX-Usm(q~(BFCLThXD#XUPExq;`z`6$ThbF_l1}5pkgSW|vZTLZN&kW+ zebJbtzhp^&&XWGDCH*E#dfAwyzhz0M&l-fRQ98+LaYroaE5{`LIZHaN4;z+#$f|qV zl3p_==|?T;hb-w2Thd!B>GflhKFP{;rIzLCJ&cew7QSXlZy1yGSFF0fYSsOiRrgO@ z(%Z%){Z&i)8d_Sxfp8mh|nG^zCDke#DZ#-;#d6C4GY>y?;#7 zU$&&bWJ!O{lKv4(`YmIUe!C^T(vnVdx)5i^{0k3SecZs9q(5Rwztxhy$C93~>VD^# zq(5v)-(yMNX-O}(qz{cr`W{RATub_FOZrWgV9BM(j6<) z&bBfwEvgxgx*u559~qPMyREv{S#__r>i&{t`NLz9K43{-Y)LP*r0=(+9~qPMm}U9J zmgQ+?J8bzsT9!XLCh3Q*y5DWp{dTMFm6r4u#w6Xd>ORk^JFR3AuKUj{=`W8-`V&^& z@3-oHw^jFQOZqEgl77sRe$0~ok|q6ZS1ZP*c z?$;n%hO4{Gs{J?Ct8}r%YStZ0svg(tqDqPI;b|_OF6|;h&s&B!t6s-7cTsOgo#-qY zmeP!}@{V8@My*`;W_&C&Cv}!|S`juRtMoZb`Y}vzGmXsK%o&UHxt8>umUNoA4(YS- zW$~AP578Tw^kPf;9!vU8OZw}U^w^lBS6b2!S<)Z2q~B^;zGzI+J1pswO#adH*rj=q zY|C%5qAorr>1~$uJWKjpR^3-x(u>C=J#IC-Lg*ILr+Ea?N52Fxl zU$vy4Zqw?2liwJ~fZ72E~me{MF zdW36OqqBeYXY9jur>9YetGit5{WsRDbP{Z*>jmd#ZBmQrGJYQ68a6Gl5usMqwb^~Jz4ZM|H&ddfUsgx6Rns;PwkOq;7Dw>h~=TWGUx5L z1w*5lJ?v#oa|Bj zSEj{r%HmWi&U}6j8W{uVQhx$QuHQB06l7wV`@);89ou?8&Gk!*CFML2IPwx0O-I#c-uV1`09?F42~2y-(q^mHe7EbDG6h4=w0 zV3JLGb&FU$SoZ^J7Qs)2zQwK21fC*cp4j9Q}s0CT9*>P5)l(twBk22G`l9j+1JJa3W=R(qV0#g*S z*oO(@^8w)eH89PgQu~1k>vIU0H$pUYAG-{twe-$ZXH$9y;zvEV6K7xi18C&QG#wki z0%i!M$dnpG&$%`O#0g+J8#@qX0OLWco&lONzZOY)p=foT@;mX+d@clyj8Zh_a$sc4 zrZF@Mrp-vd9vGSP)HFMQ3AbFj3n62EP4lP4~&d1G|fK&b1Y=BUjXwgPU@N} zJz%`JUoXPU049yS(Qqy>^}vuw&3Pd(_lNkb1*SMeLvPH>lY6>U2AJFZQjMGOG6qWM zy906N{2|a7S;-{cdrl@n6^zw8KoiF72j*6vGo5<|7#Xi>>HiE&1J2Nq#=NEYlm%Kr z0Um^G2wCGadNeX*=L>+@;iXn8pvjFu~@6gCo|WvvHhdx&!vFbz0w?A#BGjDK{g zTY;H`Ok(_X7ceF^@P?X7tm$}A`qx1tb7)bgwj-4yf68pL=KOuokUx!2Uj}9X7&;$y zT6$9{%CrsfAm?9!=B-df{SlbMp?Z0k7@ilRnaxwhrWOlB9k z&F7n-sRn3dy#&m);HP!&ZEx*rL>4~~D)n>FJmS|2#Ll09q0Q7QHVNyuglJ9&MrMSf z4wUI?>P$N?#Dn@Q0!?Me&Q}8SYDmM)!0ZfRwgD6N*9U=_9g4BrfXReP(VNP&nSSRn zU>*+9{0JC%-VZ0Ry#h>Li1Y7&xieJLLJYy;pw-rB=}9#<Nx zp4YP00CS5fr9JI9*8roRUlk9w1M`UQW$<)%1M{$N!4op#8A}ZO^+1(6Z^n=Fa-q%4x7>XwP$NPtP0r8EH&U1k2_v=nH7XtH0TsRY^ z5}0R0Ijn4hR)Q9xB6PQW9 zEEILV2+Yn9=22kkaK`ZY0WgO`H2(}tS%~KU0kb$n^A<3)k+tX_nHUilkBc>AWnjwT zT2{-p9;`lu2={4l$~hgS=J~COF!O++&3L)e!mI}-p+stIfFt7Tuw({WSh|d|l1EL36-N(?;IK0Q1#-4aYos)4?(wy4d*P3kXY3yoE^~zy; zS4+3Rjhi?3q_)aYM>}2>;zBJw^jrcT&?taGx+Gwb+2Xx%wN__)*Ve|4_U0Oh>r7=* zJu4f#nmbZG4%Qb)Hl@=^T5=0rcwqm7%xLaamDIlznNZ zt+6-R)RgJ&ajtIfS{*(oi}i0)OOFQ%$?93OiER%%|7&KGBGTLGo zsqg4gmxRrvvpH1NNA)^-QmyJ#=Z<7YQ+L-^ZG&WUstM^hneN6w7FI*&6*|^7=4L4- zuU)<}iS@0zdy;KzY&k>Hk}1J%gAK6|R;py-1*N46om6LEQom41kbccR+1k~YOl@yU zr8Di_T^7Hd#`fNntfvJpuJ29ttj6kE%X_GfS~;x4)CV-bcL#J&irzEV8sbo8y(BJA zyL)!PVcTo5{0e0CI>~gZ{lY~HlRbT1nfA^U$|1_Igl3OJic?ic@k=gok{c+(uuNuE zCjw?!BZd;m742QkHOrY-*5R@pYbc6E!7EZ3rd!e7Q{LQ+g)bnSwKpd#x}irFr{&vI zO->RtHOm9Ct9sXTcTu$(H+Q6}x+?m5dQx2(Md0&Ib@g>7+dGvdI@&k)H1_OB(lb9s za%(D+?CjlYRzh?_M_9Vy;!@N-+1#CM?daazi1`QDhRPcZHIQD1Ow|q(-H>X=SuAhU z2i6o70w+htqgZFUBh`s&fg?M#wYR0Qy`!%u+X%D^-$4t1n4FmWnAl-_+~K>10QHFX@rowy@L? zG&VQ;48jGuX=Ty(AOg3htRl&}>RP&r-Q0+&wcxT<=aW>-dqVEI^=s;?RxeN1)Gl9N zc~x@V^6IN9lGRnUbr@$R$;%WXoVluyXUiF@ukn-6e={`4@0L_gSE}Q}1<6L}sAH5I zqrW|(m?bOgu38u7%_BA~NKXN3cwMGrLp!o%W5@cgZDXaq+@8$bYyya`?`}Y-91gz9+4H&y{ehBAXWq+4Yl;xL&2)!Z)}3z@IiZ1uTrQN z0iNt`Ar+gpP=w-jR_%c9&B>O&E~!?sv8l7UqYJ#lC1}B$9z+27th4bwNT0oZn|oCS zl3Pr7Xj$zrqMvw_Y4oU;eX+JLg+wQ8+Oyas8#{Yj zk#W%}8WMfQqMf3zr;IO1S=G_P!_-G6JJJ=Ma2xt;In&+Ij1->E1kyLhB&VjjHoCB^ zLOV@m7**5L-Gn>{TwO;m&`7a;DW?v39D$ih@o9*_!-LsXNLD0!)2XKRmiDHA$Prq} z@->yPEW))K*{CnQ0=}XyV0l+YSxVg0mTF9g{Hhz42{^V8jf4Cakc%aI0+q<1v*CEe zI3tB!|AMgRi_%a=5VmKewsV-oKsBsbw@#S^{bO=7I!JBqipF#X`I>Vz z2+%jEejc4gYZqmA74UF)JK6=>pb9X=N^dus52XY2?9I-wIYpa>EW-nJh^Q*B<129O zBA%CiCrK0mg6>(OqmFu4_FWnyNp^tBmts{iAYWD`lNEO6Otz-fz!D2ZqVqv~HRsC3 z)GStaH}`d<^x&1!H-){Hf|CKqhIw$0-KcC&@uX(XlIZD`MYlFJbs%A&1JxGgsAyu& zx$3KpmfQK{5TyCkc8FsMDo6FHNXDh5M0QgkvUOTjpBZ8;Q6Vb{XtC(20z*@k+HzzB zj#^3)W;B(<`aC13S?4fus5d}vXZ2M6tV#8t)4&x%6QUR6G8!5yefZ)|AMm{j$%B$1 zyK39Iw;@UT!NZ|L_jQxu(5Jdo`NJoxxrOb~8VIJ53K3Jz@VcML(d^~&j;n?GKnr|< z4ad}ir0>b_z!jDF-Alz1lnL9Gfc zB|_H)O-RkB%P6RwuBt-)QU?Zxsh(s@M`NoVdSN`ar8lz$*DDa4m3q|tM|KlztLj1s zqxDj5t<~4`dSq-I;Ezhe14A;SVmIsnP4}g?+RC0hA)~9B6{n`Z!oai{ql1u*`DT(X zsi)#c8uX!2SpDnp7Ycd^#Jtr+dw9@Gx*OA&;g_@n2{r#xLb@LRLPCX!x@|?Z=4(K{ H%=`ZUgl