From 4b4f4c957edbcfbc815dee730274a6d946b27fd2 Mon Sep 17 00:00:00 2001 From: Gyorgy Szombathelyi Date: Thu, 13 Oct 2022 00:44:54 +0200 Subject: [PATCH] SNK68 --- .../SNK M68000 Harware/SNK68/README.md | 95 ++ .../SNK M68000 Harware/SNK68/SNK68.qpf | 31 + .../SNK M68000 Harware/SNK68/SNK68.qsf | 222 ++++ .../SNK M68000 Harware/SNK68/SNK68.sdc | 138 +++ ...scue (World Version 1, 8-Way Joystick).mra | 88 ++ ...O.W. - Prisoners of War (US Version 1).mra | 81 ++ .../meta/SAR - Search And Rescue (World).mra | 68 ++ .../meta/Street Smart (US Version 2).mra | 65 + .../SNK M68000 Harware/SNK68/rtl/SNK68.sv | 1043 +++++++++++++++++ .../SNK68/rtl/SNK68_MiST.sv | 337 ++++++ .../SNK M68000 Harware/SNK68/rtl/build_id.tcl | 35 + .../SNK68/rtl/chip_select.v | 240 ++++ .../SNK M68000 Harware/SNK68/rtl/defs.v | 3 + .../SNK68/rtl/dual_port_ram.vhd | 117 ++ .../SNK M68000 Harware/SNK68/rtl/math.vhd | 72 ++ .../SNK M68000 Harware/SNK68/rtl/pll_mist.qip | 4 + .../SNK M68000 Harware/SNK68/rtl/pll_mist.v | 309 +++++ .../SNK M68000 Harware/SNK68/rtl/sdram.sv | 447 +++++++ .../SNK68/rtl/video_timing.v | 99 ++ 19 files changed, 3494 insertions(+) create mode 100644 Arcade_MiST/SNK M68000 Harware/SNK68/README.md create mode 100644 Arcade_MiST/SNK M68000 Harware/SNK68/SNK68.qpf create mode 100644 Arcade_MiST/SNK M68000 Harware/SNK68/SNK68.qsf create mode 100644 Arcade_MiST/SNK M68000 Harware/SNK68/SNK68.sdc create mode 100644 Arcade_MiST/SNK M68000 Harware/SNK68/meta/Ikari III - The Rescue (World Version 1, 8-Way Joystick).mra create mode 100644 Arcade_MiST/SNK M68000 Harware/SNK68/meta/P.O.W. - Prisoners of War (US Version 1).mra create mode 100644 Arcade_MiST/SNK M68000 Harware/SNK68/meta/SAR - Search And Rescue (World).mra create mode 100644 Arcade_MiST/SNK M68000 Harware/SNK68/meta/Street Smart (US Version 2).mra create mode 100644 Arcade_MiST/SNK M68000 Harware/SNK68/rtl/SNK68.sv create mode 100644 Arcade_MiST/SNK M68000 Harware/SNK68/rtl/SNK68_MiST.sv create mode 100644 Arcade_MiST/SNK M68000 Harware/SNK68/rtl/build_id.tcl create mode 100644 Arcade_MiST/SNK M68000 Harware/SNK68/rtl/chip_select.v create mode 100644 Arcade_MiST/SNK M68000 Harware/SNK68/rtl/defs.v create mode 100644 Arcade_MiST/SNK M68000 Harware/SNK68/rtl/dual_port_ram.vhd create mode 100644 Arcade_MiST/SNK M68000 Harware/SNK68/rtl/math.vhd create mode 100644 Arcade_MiST/SNK M68000 Harware/SNK68/rtl/pll_mist.qip create mode 100644 Arcade_MiST/SNK M68000 Harware/SNK68/rtl/pll_mist.v create mode 100644 Arcade_MiST/SNK M68000 Harware/SNK68/rtl/sdram.sv create mode 100644 Arcade_MiST/SNK M68000 Harware/SNK68/rtl/video_timing.v diff --git a/Arcade_MiST/SNK M68000 Harware/SNK68/README.md b/Arcade_MiST/SNK M68000 Harware/SNK68/README.md new file mode 100644 index 00000000..1757d8a1 --- /dev/null +++ b/Arcade_MiST/SNK M68000 Harware/SNK68/README.md @@ -0,0 +1,95 @@ + +# SNK M68000 (Ikari III) FPGA Implementation + +FPGA compatible core of SNK M68000 (Ikari III based) arcade hardware originally written by [**Darren Olafson**](https://twitter.com/Darren__O). FPGA implementation has been verified against schematics for Ikari III (A7007). PCB measurements taken from Datsugoku: Prisoners of War (A7008), Street Smart (A8007), and Ikari III: The Rescue (A7007). + +Ikari III PCB donated by [**atrac17**](https://github.com/atrac17) / [**DJ Hard Rich**](https://twitter.com/djhardrich) and verified by [**Darren Olafson**](https://twitter.com/Darren__O). Other SNK68K PCB verification done by [**atrac17**](https://github.com/atrac17). The intent is for this core to be a 1:1 playable implementation of SNK M68000 (Ikari III) arcade hardware. Currently in **beta state**, this core is in active development with assistance from [**atrac17**](https://github.com/atrac17). + +MiST port, new SDRAM controller, some fixes and enhancements by Gyorgy Szombathelyi. + +## Supported Games + +| Title | PCB
Number | Status | Released | ROM Set | +|-------|---------------|---------|----------|----------| +| [**脱獄: Prisoners of War**](https://en.wikipedia.org/wiki/P.O.W.:_Prisoners_of_War)
P.O.W.: Prisoners of War | A7008 | Implemented | Yes | .245 merged | +| [**怒III**](https://en.wikipedia.org/wiki/Ikari_III:_The_Rescue)
Ikari III: The Rescue | A7007 | Implemented | W.I.P | .245 merged | +| [**Street Smart**](https://en.wikipedia.org/wiki/Street_Smart_(video_game)) | A7008 / A8007 | Implemented | Yes | .245 merged | +| [**SAR: Search and Rescue**](http://snk.fandom.com/wiki/SAR:_Search_and_Rescue) | A8007 | Implemented | Yes | .245 merged | + +## External Modules + +|Name| Purpose | Author | +|----|---------|--------| +| [**fx68k**](https://github.com/ijor/fx68k) | [**Motorola 68000 CPU**](https://en.wikipedia.org/wiki/Motorola_68000) | Jorge Cwik | +| [**t80**](https://opencores.org/projects/t80) | [**Zilog Z80 CPU**](https://en.wikipedia.org/wiki/Zilog_Z80) | Daniel Wallner | +| [**jtopl2**](https://github.com/jotego/jtopl) | [**Yamaha OPL 2**](https://en.wikipedia.org/wiki/Yamaha_OPL#OPL2) | Jose Tejada | +| [**jt7759**](https://github.com/jotego/jt7759) | [**NEC uPD7759**](https://github.com/jotego/jt7759) | Jose Tejada | + +# PCB Check List + +
+ +FPGA implementation has been verified against schematics [**schematics**](https://github.com/va7deo/SNK68/blob/main/doc/A7007%20(Ikari%20III)/Schematic/A7007%20Schematics.pdf) for Ikari III. PCB measurements taken from Datsugoku: Prisoners of War (A7008), Street Smart (A8007), and Ikari III: The Resucue (A7007). + +### Clock Information + +H-Sync | V-Sync | Source | PCB
Number | +------------|-------------|----------|----------------| +15.625kHz | 59.185606Hz | [**DSLogic+**](https://github.com/va7deo/SNK68/blob/main/doc/A7008%20(P.O.W.)/PCB%20Measurements/POW_CSYNC_50MHz.png) | A7008 (P.O.W.) | +15.625kHz | 59.185606Hz | TBD | A7007 (IK3) | +15.625kHz | 59.185606Hz | DSLogic+ | A8007 (SS) | + +### Crystal Oscillators + +Location | PCB
Number | Freq (MHz) | Use | +-----------------------|-----------------------------|------------|---------------------------| +X-4 (4MHZ) | A7008 (P.O.W.) / A8007 (SS) | 4.000 | Z80 / YM3812 / uPD7759 | +X-2 (18MHZ) | A7008 (P.O.W.) / A8007 (SS) | 18.000 | M68000 | +X-1 (24MHz) | A7008 (P.O.W.) / A8007 (SS) | 24.000 | Video / Pixel Clock | + +
+ +Location | PCB
Number | Freq (MHz) | Use | +-----------------------|---------------------------|------------|---------------------------| +F-18 (4MHZ) | A7007 (IK3) / A8007 (SAR) | 4.000 | Z80 / YM3812 / uPD7759 | +H-17 (18MHZ) | A7007 (IK3) / A8007 (SAR) | 18.000 | M68000 | +E-9 (24MHz) | A7007 (IK3) / A8007 (SAR) | 24.000 | Video / Pixel Clock | + +**Pixel clock:** 6.00 MHz + +**Estimated geometry:** + + 383 pixels/line + + 263 pixels/line + +### Main Components + +Location | PCB
Number | Chip | Use | +---------|---------------|------|-----| +68000 | A7008 (P.O.W.) / A8007 (SS) | [**Motorola 68000 CPU**](https://en.wikipedia.org/wiki/Motorola_68000) | Main CPU | +Z-80A | A7008 (P.O.W.) / A8007 (SS) | [**Zilog Z80 CPU**](https://en.wikipedia.org/wiki/Zilog_Z80) | Sound CPU | +YM3812 | A7008 (P.O.W.) / A8007 (SS) | [**Yamaha YM3812**](https://en.wikipedia.org/wiki/Yamaha_OPL#OPL2) | OPL2 | +7759 | A7008 (P.O.W.) / A8007 (SS) | [**NEC uPD7759**](https://github.com/jotego/jt7759) | ADPCM Decoder | + +Location | PCB
Number | Chip | Use | +---------|---------------|------|-----| +H-11/12 | A7007 (IK3) / A8007 (SAR) | [**Motorola 68000 CPU**](https://en.wikipedia.org/wiki/Motorola_68000) | Main CPU | +Z80 | A7007 (IK3) / A8007 (SAR) | [**Zilog Z80 CPU**](https://en.wikipedia.org/wiki/Zilog_Z80) | Sound CPU | +YM3812 | A7007 (IK3) / A8007 (SAR) | [**Yamaha YM3812**](https://en.wikipedia.org/wiki/Yamaha_OPL#OPL2) | OPL2 | +C-18 | A7007 (IK3) / A8007 (SAR) | [**NEC uPD7759**](https://github.com/jotego/jt7759) | ADPCM Decoder | + +### Custom Components + +Location | PCB
Number | Chip | Use | +---------|---------------|------|-----| +SNKCLK | A7007 (IK3) / A8007 (SAR) | [**SNK CLK**](https://github.com/va7deo/SNK68/blob/main/doc/Custom%20Components/SNK_CLK.jpg) | Counter | +SNKI/O | A7007 (IK3) / A8007 (SAR) | [**SNK I/O**](https://github.com/va7deo/SNK68/blob/main/doc/Custom%20Components/SNK_IO.jpg) | Rotary | + +# Support + +Please consider showing support for this and future projects via [**Darren's Ko-fi**](https://ko-fi.com/darreno) and [**atrac17's Patreon**](https://www.patreon.com/atrac17). While it isn't necessary, it's greatly appreciated. + +# Licensing + +Contact the author for special licensing needs. Otherwise follow the GPLv2 license attached. diff --git a/Arcade_MiST/SNK M68000 Harware/SNK68/SNK68.qpf b/Arcade_MiST/SNK M68000 Harware/SNK68/SNK68.qpf new file mode 100644 index 00000000..1acd4768 --- /dev/null +++ b/Arcade_MiST/SNK M68000 Harware/SNK68/SNK68.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition +# Date created = 04:04:47 October 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.1" +DATE = "04:04:47 October 16, 2017" + +# Revisions + +PROJECT_REVISION = "SNK68" diff --git a/Arcade_MiST/SNK M68000 Harware/SNK68/SNK68.qsf b/Arcade_MiST/SNK M68000 Harware/SNK68/SNK68.qsf new file mode 100644 index 00000000..d34c6f5a --- /dev/null +++ b/Arcade_MiST/SNK M68000 Harware/SNK68/SNK68.qsf @@ -0,0 +1,222 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 05:08:48 November 15, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Arcade-Scramble_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_90 -to SPI_SS4 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PIN_49 -to SDRAM_A[0] +set_location_assignment PIN_44 -to SDRAM_A[1] +set_location_assignment PIN_42 -to SDRAM_A[2] +set_location_assignment PIN_39 -to SDRAM_A[3] +set_location_assignment PIN_4 -to SDRAM_A[4] +set_location_assignment PIN_6 -to SDRAM_A[5] +set_location_assignment PIN_8 -to SDRAM_A[6] +set_location_assignment PIN_10 -to SDRAM_A[7] +set_location_assignment PIN_11 -to SDRAM_A[8] +set_location_assignment PIN_28 -to SDRAM_A[9] +set_location_assignment PIN_50 -to SDRAM_A[10] +set_location_assignment PIN_30 -to SDRAM_A[11] +set_location_assignment PIN_32 -to SDRAM_A[12] +set_location_assignment PIN_83 -to SDRAM_DQ[0] +set_location_assignment PIN_79 -to SDRAM_DQ[1] +set_location_assignment PIN_77 -to SDRAM_DQ[2] +set_location_assignment PIN_76 -to SDRAM_DQ[3] +set_location_assignment PIN_72 -to SDRAM_DQ[4] +set_location_assignment PIN_71 -to SDRAM_DQ[5] +set_location_assignment PIN_69 -to SDRAM_DQ[6] +set_location_assignment PIN_68 -to SDRAM_DQ[7] +set_location_assignment PIN_86 -to SDRAM_DQ[8] +set_location_assignment PIN_87 -to SDRAM_DQ[9] +set_location_assignment PIN_98 -to SDRAM_DQ[10] +set_location_assignment PIN_99 -to SDRAM_DQ[11] +set_location_assignment PIN_100 -to SDRAM_DQ[12] +set_location_assignment PIN_101 -to SDRAM_DQ[13] +set_location_assignment PIN_103 -to SDRAM_DQ[14] +set_location_assignment PIN_104 -to SDRAM_DQ[15] +set_location_assignment PIN_58 -to SDRAM_BA[0] +set_location_assignment PIN_51 -to SDRAM_BA[1] +set_location_assignment PIN_85 -to SDRAM_DQMH +set_location_assignment PIN_67 -to SDRAM_DQML +set_location_assignment PIN_60 -to SDRAM_nRAS +set_location_assignment PIN_64 -to SDRAM_nCAS +set_location_assignment PIN_66 -to SDRAM_nWE +set_location_assignment PIN_59 -to SDRAM_nCS +set_location_assignment PIN_33 -to SDRAM_CKE +set_location_assignment PIN_43 -to SDRAM_CLK +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_* +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_* +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name TOP_LEVEL_ENTITY SNK68_MiST + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP3C25E144C8 + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# ---------------------- +# start ENTITY(SNK68) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(SNK68) +# -------------------- +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP +set_global_assignment -name ENABLE_SIGNALTAP OFF +set_global_assignment -name USE_SIGNALTAP_FILE output_files/joy.stp +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON +set_global_assignment -name FORCE_SYNCH_CLEAR ON +set_global_assignment -name SYSTEMVERILOG_FILE rtl/SNK68_MiST.sv +set_global_assignment -name QIP_FILE rtl/pll_mist.qip +set_global_assignment -name VERILOG_FILE rtl/video_timing.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/SNK68.sv +set_global_assignment -name VHDL_FILE rtl/math.vhd +set_global_assignment -name VHDL_FILE rtl/dual_port_ram.vhd +set_global_assignment -name VERILOG_FILE rtl/chip_select.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv +set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip +set_global_assignment -name QIP_FILE ../../../common/CPU/68000/FX68k/fx68k.qip +set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip +set_global_assignment -name QIP_FILE ../../../common/Sound/jtopl/jtopl2.qip +set_global_assignment -name QIP_FILE ../../../common/Sound/jt7759/jt7759.qip +set_global_assignment -name SIGNALTAP_FILE output_files/cpu.stp +set_global_assignment -name SIGNALTAP_FILE output_files/z80.stp +set_global_assignment -name SIGNALTAP_FILE output_files/spr.stp +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name SIGNALTAP_FILE output_files/joy.stp +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/SNK M68000 Harware/SNK68/SNK68.sdc b/Arcade_MiST/SNK M68000 Harware/SNK68/SNK68.sdc new file mode 100644 index 00000000..81f99561 --- /dev/null +++ b/Arcade_MiST/SNK M68000 Harware/SNK68/SNK68.sdc @@ -0,0 +1,138 @@ +## Generated SDC file "vectrex_MiST.out.sdc" + +## Copyright (C) 1991-2013 Altera Corporation +## Your use of Altera Corporation's design tools, logic functions +## and other software and tools, and its AMPP partner logic +## functions, and any output files from any of the foregoing +## (including device programming or simulation files), and any +## associated documentation or information are expressly subject +## to the terms and conditions of the Altera Program License +## Subscription Agreement, Altera MegaCore Function License +## Agreement, or other applicable license agreement, including, +## without limitation, that your use is for the sole purpose of +## programming logic devices manufactured by Altera and sold by +## Altera or its authorized distributors. Please refer to the +## applicable agreement for further details. + + +## VENDOR "Altera" +## PROGRAM "Quartus II" +## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" + +## DATE "Sun Jun 24 12:53:00 2018" + +## +## DEVICE "EP3C25E144C8" +## + +# Clock constraints + +# Automatically constrain PLL and other generated clocks +derive_pll_clocks -create_base_clocks + +# Automatically calculate clock uncertainty to jitter and other effects. +derive_clock_uncertainty + +# tsu/th constraints + +# tco constraints + +# tpd constraints + +#************************************************************** +# Time Information +#************************************************************** + +set_time_format -unit ns -decimal_places 3 + + + +#************************************************************** +# Create Clock +#************************************************************** + +create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}] + +set sys_clk "pll|altpll_component|auto_generated|pll1|clk[0]" +set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[0]" + +#************************************************************** +# Create Generated Clock +#************************************************************** + + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** + +#************************************************************** +# Set Input Delay +#************************************************************** + +set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}] + +set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]] +set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]] + +#************************************************************** +# Set Output Delay +#************************************************************** + +set_output_delay -add_delay -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}] +set_output_delay -add_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_L}] +set_output_delay -add_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_R}] +set_output_delay -add_delay -clock [get_clocks $sdram_clk] 1.000 [get_ports {LED}] +set_output_delay -add_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {VGA_*}] + +set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] +set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] + +#************************************************************** +# Set Clock Groups +#************************************************************** + +set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}] + +#************************************************************** +# Set False Path +#************************************************************** + + + +#************************************************************** +# Set Multicycle Path +#************************************************************** + +set_multicycle_path -from {SNK68:SNK68|T80pa:z80|T80:u0|*} -setup 2 +set_multicycle_path -from {SNK68:SNK68|T80pa:z80|T80:u0|*} -hold 1 + +set_multicycle_path -to {VGA_*[*]} -setup 2 +set_multicycle_path -to {VGA_*[*]} -hold 1 + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** + diff --git a/Arcade_MiST/SNK M68000 Harware/SNK68/meta/Ikari III - The Rescue (World Version 1, 8-Way Joystick).mra b/Arcade_MiST/SNK M68000 Harware/SNK68/meta/Ikari III - The Rescue (World Version 1, 8-Way Joystick).mra new file mode 100644 index 00000000..b2937e92 --- /dev/null +++ b/Arcade_MiST/SNK M68000 Harware/SNK68/meta/Ikari III - The Rescue (World Version 1, 8-Way Joystick).mra @@ -0,0 +1,88 @@ + + Ikari III - The Rescue (World Version 1, 8-Way Joystick) + ikari3 + SNK68 + 0245 + 1989 + SNK + World + 8-Way + + + + + + + + + + + + + + + + + + + + + 00 + + + + + + + + + + + + + FF + + + FF + + + + + + + + FF + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Arcade_MiST/SNK M68000 Harware/SNK68/meta/P.O.W. - Prisoners of War (US Version 1).mra b/Arcade_MiST/SNK M68000 Harware/SNK68/meta/P.O.W. - Prisoners of War (US Version 1).mra new file mode 100644 index 00000000..035c2b99 --- /dev/null +++ b/Arcade_MiST/SNK M68000 Harware/SNK68/meta/P.O.W. - Prisoners of War (US Version 1).mra @@ -0,0 +1,81 @@ + + P.O.W. - Prisoners of War (US Version 1) + pow + SNK68 + 0245 + 1988 + SNK + US + + + + + + + + + + + + + + + + + + + + + 01 + + + + + + + + + FF + + + FF + + + FF + + + + + + FF + + + + + + + + + + + + + + + + + + + + + + + + + + FF + + + + + diff --git a/Arcade_MiST/SNK M68000 Harware/SNK68/meta/SAR - Search And Rescue (World).mra b/Arcade_MiST/SNK M68000 Harware/SNK68/meta/SAR - Search And Rescue (World).mra new file mode 100644 index 00000000..eee9bb21 --- /dev/null +++ b/Arcade_MiST/SNK M68000 Harware/SNK68/meta/SAR - Search And Rescue (World).mra @@ -0,0 +1,68 @@ + + SAR - Search And Rescue (World) + searchar + SNK68 + 0245 + 1989 + SNK + World + + + + + + + + + + + + + + + + + + + + + 08 + + + + + + + + + + + + + + + FF + + + + + + + + FF + + + + + + + + + + + + + + + + diff --git a/Arcade_MiST/SNK M68000 Harware/SNK68/meta/Street Smart (US Version 2).mra b/Arcade_MiST/SNK M68000 Harware/SNK68/meta/Street Smart (US Version 2).mra new file mode 100644 index 00000000..99d65d7e --- /dev/null +++ b/Arcade_MiST/SNK M68000 Harware/SNK68/meta/Street Smart (US Version 2).mra @@ -0,0 +1,65 @@ + + Street Smart (US version 2) + streetsm + SNK68 + 0245 + 1989 + SNK + World + + + + + + + + + + + + + + + + + + + + + 02 + + + + + + + + + FF + + + FF + + + + + + + + FF + + + + + + + + + + + + + + + + diff --git a/Arcade_MiST/SNK M68000 Harware/SNK68/rtl/SNK68.sv b/Arcade_MiST/SNK M68000 Harware/SNK68/rtl/SNK68.sv new file mode 100644 index 00000000..8faf5a5c --- /dev/null +++ b/Arcade_MiST/SNK M68000 Harware/SNK68/rtl/SNK68.sv @@ -0,0 +1,1043 @@ +//============================================================================ +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +//============================================================================ + +`default_nettype none + +module SNK68 +( + input pll_locked, + input clk_sys, // 72 MHz + input reset, + input [3:0] pcb, + input pause_cpu, + + input refresh_sel, + + // debug + input test_flip, + output flip, + + input [7:0] p1, + input [7:0] p2, + input [7:0] dsw1, + input [7:0] dsw2, + input [15:0] coin, + input [11:0] rotary1, + input [11:0] rotary2, + + output hbl, + output vbl, + output hsync, + output vsync, + output [4:0] r, + output [4:0] g, + output [4:0] b, + + output [15:0] audio_l, + output [15:0] audio_r, + + input [3:0] hs_offset, + input [3:0] vs_offset, + input [3:0] hs_width, + input [3:0] vs_width, + + input rom_download, + input [23:0] ioctl_addr, + input ioctl_wr, + input [7:0] ioctl_dout, + + output [12:0] SDRAM_A, + output [1:0] SDRAM_BA, + inout [15:0] SDRAM_DQ, + output SDRAM_DQML, + output SDRAM_DQMH, + output SDRAM_nCS, + output SDRAM_nCAS, + output SDRAM_nRAS, + output SDRAM_nWE +); + +assign m68k_a[0] = 0; + +reg refresh_mod; +assign flip = test_flip ^ scr_flip; + +always @(posedge clk_sys) begin + if (refresh_mod != ~refresh_sel) begin + refresh_mod <= ~refresh_sel; + end +end + + +localparam CLKSYS=72; + +reg [5:0] clk18_count; +reg [5:0] clk9_count; +reg [5:0] clk6_count; +reg [5:0] clk4_count; +reg [15:0] clk_upd_count; + +reg clk4_en_p, clk4_en_n; +reg clk9_en_p, clk9_en_n; +reg clk6_en; +reg clk_upd_en; +reg real_pause; + +always @(posedge clk_sys) begin + if (reset) begin + clk4_count <= 0; + clk6_count <= 0; + clk_upd_count <= 0; + {clk4_en_p, clk4_en_n} <= 0; + {clk9_en_p, clk9_en_n} <= 0; + clk6_en <= 0; + clk_upd_en <= 0; + end else begin + clk4_count <= clk4_count + 1'd1; + if (clk4_count == 17) begin + clk4_count <= 0; + end + clk4_en_p <= clk4_count == 0; + clk4_en_n <= clk4_count == 9; + + clk9_count <= clk9_count + 1'd1; + if (clk9_count == 7) begin + clk9_count <= 0; + real_pause <= pause_cpu & m68k_as_n; + end + clk9_en_p <= clk9_count == 0 && !real_pause; + clk9_en_n <= clk9_count == 4 && !real_pause; + + clk6_count <= clk6_count + 1'd1; + if (clk6_count == 11) clk6_count <= 0; + clk6_en <= clk6_count == 0; + + clk_upd_count <= clk_upd_count + 1'd1; + // 72MHz / 113 == 637.168KHz. should be 640. + // todo : use fractional divider 112.5 alternate between 112 & 113 + if (clk_upd_count == 112) clk_upd_count <= 0; + clk_upd_en <= clk_upd_count == 0; + end +end + +wire [8:0] hc; +wire [8:0] vc; +wire [8:0] hcflip = !flip ? hc[8:0] : { hc[8], ~hc[7:0] }; +wire [8:0] vcflip = !flip ? vc : {vc[8], ~vc[7:0]}; + +video_timing video_timing ( + .clk(clk_sys), + .clk_pix(clk6_en), + .refresh_mod(refresh_mod), + .hc(hc), + .vc(vc), + .hs_offset(hs_offset), + .vs_offset(vs_offset), + .hs_width(hs_width), + .vs_width(vs_width), + .hbl(hbl), + .vbl(vbl), + .hsync(hsync), + .vsync(vsync) +); + +// foreground layer +wire [9:0] fg_tile = { hcflip[7:3], vcflip[7:3] }; +assign fg_ram_addr = { fg_tile, hc[0] }; +reg [6:0] fg_colour, fg_colour_d; +wire [8:0] fg_x = hcflip; +wire [8:0] fg_y = vcflip; +reg [15:0] fg_ram_dout0, fg_ram_dout1; +reg [15:0] fg_pix_data; +reg [10:0] fg; + +always @(posedge clk_sys) begin + if (clk6_en) begin + if (hc[0]) + fg_ram_dout1 <= fg_ram_dout; + else + fg_ram_dout0 <= fg_ram_dout; + + if (fg_x[1:0] == ({2{flip}} ^ 2'b11)) begin + if ( pcb == 0 ) begin + fg_rom_addr <= { fg_ram_dout0[10:0], ~fg_x[2], fg_y[2:0] }; + fg_colour <= fg_ram_dout0[15:12]; + end else begin + // POW only has 256 text tiles in each bank. offset selects bank + fg_rom_addr <= { tile_offset, fg_ram_dout0[7:0], ~fg_x[2], fg_y[2:0] } ; + fg_colour <= fg_ram_dout1[2:0] ; + end + fg_pix_data <= fg_rom_data; + fg_colour_d <= fg_colour; + end + case ( fg_x[1:0] ) + 0: fg <= { fg_colour_d, fg_pix_data[12], fg_pix_data[8], fg_pix_data[4], fg_pix_data[0] } ; + 1: fg <= { fg_colour_d, fg_pix_data[13], fg_pix_data[9], fg_pix_data[5], fg_pix_data[1] } ; + 2: fg <= { fg_colour_d, fg_pix_data[14], fg_pix_data[10], fg_pix_data[6], fg_pix_data[2] } ; + 3: fg <= { fg_colour_d, fg_pix_data[15], fg_pix_data[11], fg_pix_data[7], fg_pix_data[3] } ; + endcase + end +end + +// sprite rendering into dual line buffers +reg [4:0] sprite_state; +reg [31:0] spr_pix_data; + +wire [8:0] sp_y = vcflip + (flip ? -1'd1 : 1'd1); + +reg [6:0] sprite_colour; +reg [14:0] sprite_tile_num; +reg sprite_flip_x; +reg sprite_flip_y; +reg [1:0] sprite_group; +reg [4:0] sprite_col; +reg [15:0] sprite_col_x; +reg [15:0] sprite_col_y; +reg [8:0] sprite_col_idx; +reg [8:0] spr_x_pos; +reg [3:0] spr_x_ofs; +reg [1:0] sprite_layer; +reg sprite_overrun; + +wire [3:0] spr_pen = { spr_pix_data[ 8 + { 3 { sprite_flip_x } } ^ spr_x_ofs[2:0]], + spr_pix_data[ 0 + { 3 { sprite_flip_x } } ^ spr_x_ofs[2:0]], + spr_pix_data[24 + { 3 { sprite_flip_x } } ^ spr_x_ofs[2:0]], + spr_pix_data[16 + { 3 { sprite_flip_x } } ^ spr_x_ofs[2:0]] } ; + +always @ (posedge clk_sys) begin + if ( reset == 1 ) begin + sprite_state <= 0; + sprite_overrun <= 0; + end else begin + // sprites. -- need 3 sprite layers + spr_buf_w <= 0; + if ( sprite_state == 0 && hc == 0 ) begin + // init + sprite_state <= 22; + sprite_layer <= 0; + spr_x_pos <= 0; + end else if ( sprite_state == 22 ) begin + // start + sprite_col <= 0; + + case ( sprite_layer ) + 0: sprite_group <= 2; + 1: sprite_group <= 3; + 2: sprite_group <= 1; + endcase + sprite_state <= 1; + end else if ( sprite_state == 1 ) begin + // setup x read + sprite_ram_addr <= { sprite_col, 3'b0, sprite_group, 1'b0 } ; + sprite_state <= 2; + end else if ( sprite_state == 2 ) begin + // setup y read + sprite_ram_addr <= sprite_ram_addr + 1'd1; + sprite_state <= 3; + end else if ( sprite_state == 3 ) begin + // x valid + sprite_col_x <= sprite_ram_dout; + sprite_state <= 4; + end else if ( sprite_state == 4 ) begin + if ( sprite_col_x[7:0] > 16 ) begin + sprite_state <= 17; + end + // y valid + sprite_col_y <= sprite_ram_dout; + sprite_state <= 5; + end else if ( sprite_state == 5 ) begin + // tile ofset from the top of the column + sprite_col_idx <= sp_y + sprite_col_y[8:0] ; + sprite_state <= 6; + end else if ( sprite_state == 6 ) begin + // setup sprite tile colour read + sprite_ram_addr <= { sprite_group[1:0], sprite_col[4:0], sprite_col_idx[8:4], 1'b0 }; + sprite_state <= 7; + + end else if ( sprite_state == 7 ) begin + // setup sprite tile index read + sprite_ram_addr <= sprite_ram_addr + 1'd1; + sprite_state <= 8; + end else if ( sprite_state == 8 ) begin + // tile colour ready + sprite_colour <= sprite_ram_dout[6:0]; // 0x7f + sprite_state <= 9; + end else if ( sprite_state == 9 ) begin + // tile index ready + if (pcb == 0 || pcb == 2) begin + sprite_tile_num <= sprite_ram_dout[14:0] ; // 0x7fff + sprite_flip_x <= sprite_ram_dout[15] & ~spr_flip_orientation ; // 0x8000 + sprite_flip_y <= sprite_ram_dout[15] & spr_flip_orientation; // 0x8000 + end else begin + sprite_tile_num <= sprite_ram_dout[13:0] ; // 0x3fff + sprite_flip_x <= sprite_ram_dout[14] & ~spr_flip_orientation ; // 0x4000 + sprite_flip_y <= sprite_ram_dout[15] & spr_flip_orientation; // 0x8000 + end + spr_x_ofs <= 0; + spr_x_pos <= { sprite_col_x[7:0], sprite_col_y[15:12] } ; + sprite_state <= 10; + end else if ( sprite_state == 10 ) begin + + // sprite_rom_addr <= { tile[10:0], ~dx[3], dy[3:0] } ; + case ( { sprite_flip_y, sprite_flip_x } ) + 2'b00: sprite_rom_addr <= { sprite_tile_num, ~spr_x_ofs[3], sprite_col_idx[3:0] } ; + 2'b01: sprite_rom_addr <= { sprite_tile_num, spr_x_ofs[3], sprite_col_idx[3:0] } ; + 2'b10: sprite_rom_addr <= { sprite_tile_num, ~spr_x_ofs[3], ~sprite_col_idx[3:0] } ; + 2'b11: sprite_rom_addr <= { sprite_tile_num, spr_x_ofs[3], ~sprite_col_idx[3:0] } ; + endcase + + sprite_rom_req <= ~sprite_rom_req; + sprite_state <= 11; + end else if ( sprite_state == 11 ) begin + // wait for sprite bitmap data + if ( sprite_rom_req == sprite_rom_ack ) begin + spr_pix_data <= sprite_rom_data; + sprite_state <= 12 ; + end + end else if ( sprite_state == 12 ) begin + spr_buf_addr_w <= { vc[0], spr_x_pos }; + + spr_buf_w <= | spr_pen ; // don't write if 0 - transparent + + spr_buf_din <= { sprite_colour, spr_pen }; + + if ( spr_x_ofs < 15 ) begin + spr_x_ofs <= spr_x_ofs + 1'd1; + spr_x_pos <= spr_x_pos + 1'd1; + + // the second 8 pixel needs another rom read + if ( spr_x_ofs == 7 ) begin + sprite_state <= 10; + end + + end else begin + sprite_state <= 17; + end + + end else if ( sprite_state == 17) begin + if ( hc > 360 ) begin + sprite_state <= 0; + sprite_overrun <= 1; + end else if ( sprite_col < 31 ) begin + sprite_col <= sprite_col + 1'd1; + sprite_state <= 1; + end else begin + if ( sprite_layer < 2 ) begin + sprite_layer <= sprite_layer + 1'd1; + sprite_state <= 22; + end else begin + sprite_state <= 0; + end + end + end + end +end + +wire [8:0] spr_pos = (flip ? 8'd8 : -8'd8) + hcflip; +assign spr_buf_addr_r = { ~vc[0], spr_pos }; +reg [10:0] sp; +always @ (posedge clk_sys) if (clk6_en) sp <= spr_buf_dout[10:0]; + +// final color mix +wire [10:0] pen = ( fg[3:0] == 0 && ( pcb == 1 || pcb == 2 || fg[7] == 0 ) ) ? sp[10:0] : fg[6:0]; + +always @ (posedge clk_sys) begin + if (clk6_en) begin + if ( pen[3:0] == 0 ) begin + tile_pal_addr <= 11'h7ff ; // background pen + end else begin + tile_pal_addr <= pen[10:0] ; + end + r <= r_pal; + g <= g_pal; + b <= b_pal; + end +end + +/// 68k cpu + +reg spr_flip_orientation ; +reg scr_flip ; +reg [2:0] tile_offset; +reg invert_input; + +assign m68k_dtack_n = m68k_rom_cs ? !m68k_rom_valid : + m68k_rom_2_cs ? !m68k_rom_valid : + m68k_ram_cs ? !m68k_ram_dtack : + 1'b0; + +assign m68k_din = m68k_rom_cs ? m68k_rom_data : + m68k_rom_2_cs ? m68k_rom_data : + m68k_ram_cs ? m68k_ram_dout : + // high byte of even addressed sprite ram not connected. pull high. + m68k_spr_cs ? ( m68k_a[1] == 0 ) ? ( m68k_sprite_dout | 16'hff00 ) : m68k_sprite_dout : // 0xff000000 + m68k_fg_ram_cs ? m68k_fg_ram_dout : + m68k_pal_cs ? m68k_pal_dout : + (input_p1_cs & !input_p2_cs ) ? (invert_input ? ~{p1, p1} : {p1, p1}) : + (input_p2_cs & !input_p1_cs ) ? (invert_input ? ~{p2, p2} : {p2, p2}) : + (input_p2_cs & input_p1_cs ) ? (invert_input ? ~{ p2[7:0], p1[7:0] } : { p2[7:0], p1[7:0] }) : + input_dsw1_cs ? {dsw1, dsw1} : + input_dsw2_cs ? {dsw2, dsw2} : + input_coin_cs ? (invert_input ? ~coin : coin) : + m68k_rotary1_cs ? ~{ rotary1[11:4], 8'h0 } : + m68k_rotary2_cs ? ~{ rotary2[11:4], 8'h0 } : + m68k_rotary_lsb_cs ? ~{ rotary2[3:0], rotary1[3:0], 8'h0 } : + z80_latch_read_cs ? { z80_latch, z80_latch } : + 16'd0; + +always @ (posedge clk_sys) begin + + if ( reset == 1 ) begin + z80_nmi_n <= 1 ; + scr_flip <= 0; + end else begin + + if ( !m68k_rw) begin + + if ( m68k_latch_cs == 1 ) begin + m68k_latch <= m68k_dout[7:0]; + z80_nmi_n <= 0; + end + + if ( m68k_scr_flip_cs == 1 ) begin + scr_flip <= m68k_dout[3]; + spr_flip_orientation <= m68k_dout[2]; + if ( pcb > 0 ) begin + tile_offset <= m68k_dout[6:4]; + end + end + + if ( m_invert_ctrl_cs == 1 ) begin + invert_input <= ( m68k_dout[7:0] == 8'h07 ); + end + end + + if (!z80_nmi_n && z80_addr == 16'h0066 && !M1_n && !MREQ_n) begin + z80_nmi_n <= 1; + end + end +end + +wire m68k_rom_cs; +wire m68k_rom_2_cs; +wire m68k_ram_cs; +wire m68k_pal_cs; +wire m68k_spr_cs; +wire m68k_fg_ram_cs; +wire m68k_scr_flip_cs; +wire input_p1_cs; +wire input_p2_cs; +wire input_coin_cs; +wire input_dsw1_cs; +wire input_dsw2_cs; +wire irq_z80_cs; +wire m_invert_ctrl_cs; +wire m68k_latch_cs; +wire z80_latch_read_cs; +wire m68k_rotary1_cs; +wire m68k_rotary2_cs; +wire m68k_rotary_lsb_cs; + +wire z80_rom_cs; +wire z80_ram_cs; +wire z80_latch_cs; +wire z80_sound0_cs; +wire z80_sound1_cs; +wire z80_upd_cs; +wire z80_upd_r_cs; + +chip_select cs ( + // 68k bus + .pcb(pcb), + .m68k_a(m68k_a), + .m68k_as_n(m68k_as_n), + .m68k_rw(m68k_rw), + .m68k_uds_n(m68k_uds_n), + .m68k_lds_n(m68k_lds_n), + + .z80_addr(z80_addr), + .MREQ_n(MREQ_n), + .IORQ_n(IORQ_n), + .M1_n(M1_n), + .RFSH_n(RFSH_n), + + // 68k chip selects + .m68k_rom_cs(m68k_rom_cs), + .m68k_rom_2_cs(m68k_rom_2_cs), + .m68k_ram_cs(m68k_ram_cs), + .m68k_spr_cs(m68k_spr_cs), + .m68k_scr_flip_cs(m68k_scr_flip_cs), + .m68k_fg_ram_cs(m68k_fg_ram_cs), + .m68k_pal_cs(m68k_pal_cs), + + .input_p1_cs(input_p1_cs), + .input_p2_cs(input_p2_cs), + .input_dsw1_cs(input_dsw1_cs), + .input_dsw2_cs(input_dsw2_cs), + .input_coin_cs(input_coin_cs), + + .m68k_rotary1_cs(m68k_rotary1_cs), + .m68k_rotary2_cs(m68k_rotary2_cs), + .m68k_rotary_lsb_cs(m68k_rotary_lsb_cs), + .m_invert_ctrl_cs(m_invert_ctrl_cs), + + .m68k_latch_cs(m68k_latch_cs), // write commands to z80 from 68k + .z80_latch_read_cs(z80_latch_read_cs), // read commands from z80 + + // z80 + .z80_rom_cs(z80_rom_cs), + .z80_ram_cs(z80_ram_cs), + .z80_latch_cs(z80_latch_cs), + .z80_sound0_cs(z80_sound0_cs), + .z80_sound1_cs(z80_sound1_cs), + .z80_upd_cs(z80_upd_cs), + .z80_upd_r_cs(z80_upd_r_cs) +); + +reg [7:0] z80_latch; +reg [7:0] m68k_latch; + +// CPU outputs +wire m68k_rw ; // Read = 1, Write = 0 +wire m68k_as_n ; // Address strobe +wire m68k_lds_n ; // Lower byte strobe +wire m68k_uds_n ; // Upper byte strobe +wire m68k_E; +wire [2:0] m68k_fc ; // Processor state +wire m68k_reset_n_o ; // Reset output signal +wire m68k_halted_n ; // Halt output + +// CPU busses +wire [15:0] m68k_dout ; +wire [23:0] m68k_a /* synthesis keep */ ; +reg [15:0] m68k_din ; +//assign m68k_a[0] = 1'b0; + +// CPU inputs +reg m68k_dtack_n ; // Data transfer ack (always ready) +reg m68k_ipl0_n ; + +wire m68k_vpa_n = ~int_ack;//( m68k_lds_n == 0 && m68k_fc == 3'b111 ); // int ack + +wire int_ack = !m68k_as_n && m68k_fc == 3'b111; + +reg [1:0] vbl_sr; + +// vblank handling +// process interrupt and sprite buffering +always @ (posedge clk_sys ) begin + if ( reset == 1 ) begin + m68k_ipl0_n <= 1 ; + end else begin + vbl_sr <= { vbl_sr[0], vbl }; + + if ( vbl_sr == 2'b01 ) begin // rising edge + // trigger sprite buffer copy + // 68k vbl interrupt + m68k_ipl0_n <= 0; + end else if ( int_ack == 1/* || vbl_sr == 2'b10*/ ) begin + // deassert interrupt since 68k ack'ed. + m68k_ipl0_n <= 1 ; + end + end +end + +fx68k fx68k ( + // input + .clk(clk_sys), + .enPhi1(clk9_en_p), + .enPhi2(clk9_en_n), + + .extReset(reset), + .pwrUp(reset), + + // output + .eRWn(m68k_rw), + .ASn(m68k_as_n), + .LDSn(m68k_lds_n), + .UDSn(m68k_uds_n), + .E(), + .VMAn(), + .FC0(m68k_fc[0]), + .FC1(m68k_fc[1]), + .FC2(m68k_fc[2]), + .BGn(), + .oRESETn(m68k_reset_n_o), + .oHALTEDn(m68k_halted_n), + + // input + .VPAn( m68k_vpa_n ), + .DTACKn( m68k_dtack_n ), + .BERRn(1'b1), + .BRn(1'b1), + .BGACKn(1'b1), + + .IPL0n(m68k_ipl0_n), + .IPL1n(1'b1), + .IPL2n(1'b1), + + // busses + .iEdb(m68k_din), + .oEdb(m68k_dout), + .eab(m68k_a[23:1]) +); + +// z80 audio +wire [7:0] z80_rom_data; +wire [7:0] z80_ram_data; + +wire [15:0] z80_addr; +reg [7:0] z80_din; +wire [7:0] z80_dout; + +wire z80_wr_n; +wire z80_rd_n; +wire z80_wait_n; +reg z80_nmi_n; + +wire IORQ_n; +wire MREQ_n; +wire M1_n; +wire RFSH_n; + +T80pa z80 ( + .RESET_n ( ~reset ), + .CLK ( clk_sys ), + .CEN_p ( clk4_en_p ), + .CEN_n ( clk4_en_n ), + .WAIT_n ( z80_wait_n ), // z80_wait_n + .INT_n ( opl_irq_n ), // opl_irq_n + .NMI_n ( z80_nmi_n ), + .BUSRQ_n ( 1'b1 ), + .RD_n ( z80_rd_n ), + .WR_n ( z80_wr_n ), + .A ( z80_addr ), + .DI ( z80_din ), + .DO ( z80_dout ), + // unused + .DIRSET ( 1'b0 ), + .DIR ( 212'b0 ), + .OUT0 ( 1'b0 ), + .RFSH_n ( RFSH_n ), + .IORQ_n ( IORQ_n ), + .M1_n ( M1_n ), // for interrupt ack + .BUSAK_n (), + .HALT_n ( 1'b1 ), + .MREQ_n ( MREQ_n ), + .Stop (), + .REG () +); + +reg opl_wait ; + +assign z80_wait_n = z80_rom_cs ? z80_rom_valid : 1'b1; + +assign z80_din = z80_rom_cs ? z80_rom_data : + z80_ram_cs ? z80_ram_data : + z80_latch_cs ? m68k_latch : + z80_sound0_cs ? opl_dout : 8'hFF; + +always @ (posedge clk_sys) begin + + if ( reset == 1 ) begin + end else begin + + if ( z80_wr_n == 0 ) begin + + // 7759 + if ( z80_upd_cs == 1 ) begin + upd_din <= z80_dout ; + upd_start_n <= 1 ; + // need a pulse to trigger the 7759 start + upd_start_flag <= 1; + end + + if ( upd_start_flag == 1 ) begin + upd_start_n <= 0 ; + upd_start_flag <= 0; + end + + if ( z80_upd_r_cs == 1 ) begin + upd_reset <= 1; + end else begin + upd_reset <= 0; + end + + if ( z80_latch_cs == 1 ) begin + z80_latch <= z80_dout ; + end + end + + end +end + +wire [7:0] opl_dout; +wire opl_irq_n; + +reg signed [15:0] sample; + +wire signed [8:0] upd_sample_out; +wire signed [15:0] upd_sample = { upd_sample_out[8], upd_sample_out[8], upd_sample_out, 5'b0 }; + +wire opl_sample_clk; + +jtopl #(.OPL_TYPE(2)) opl +( + .rst(reset), + .clk(clk_sys), + .cen(clk4_en_p), + .din(z80_dout), + .addr(z80_addr[5]), + .cs_n(~( z80_sound0_cs | z80_sound1_cs )), + .wr_n(z80_wr_n), + .dout(opl_dout), + .irq_n(opl_irq_n), + .snd(sample), + .sample(opl_sample_clk) +); + +reg [7:0] upd_din; +reg upd_reset ; +reg upd_start_n ; +reg upd_start_flag ; + +jt7759 upd7759 +( + .rst( reset | upd_reset ), + .clk(clk_sys), // Use same clock as sound CPU + .cen(clk_upd_en), // 640kHz + .stn(upd_start_n), // STart (active low) + .cs(1'b1), + .mdn(1'b1), // MODE: 1 for stand alone mode, 0 for slave mode + // see chart in page 13 of PDF + .busyn(), + // CPU interface + .wrn(1'b1), // for slave mode only, 31.7us after drqn is set + .din(upd_din), + .drqn(), // data request. 50-70us delay after mdn goes low + + // ROM interface + .rom_cs(upd_rom_cs), // equivalent to DRQn in original chip + .rom_addr(upd_rom_addr), // output [16:0] + .rom_data(upd_rom_data), // input [ 7:0] + .rom_ok(upd_rom_valid), + + // Sound output + .sound(upd_sample_out) //output signed [ 8:0] +); + +always @(*) begin + // mix audio + audio_l = ( sample + upd_sample ) >>> 1; + audio_r = ( sample + upd_sample ) >>> 1; +end + +wire [15:0] m68k_sprite_dout; +wire [15:0] m68k_pal_dout; + +reg [13:0] sprite_ram_addr; +wire [15:0] sprite_ram_dout /* synthesis keep */; + +// main 68k sprite ram high +// 2kx16 +dual_port_ram #(.LEN(16384)) sprite_ram_H ( + .clock_a ( clk_sys ), + .address_a ( m68k_a[14:1] ), + .wren_a ( !m68k_rw & m68k_spr_cs & !m68k_uds_n ), + .data_a ( m68k_dout[15:8] ), + .q_a ( m68k_sprite_dout[15:8] ), + + .clock_b ( clk_sys ), + .address_b ( sprite_ram_addr ), + .wren_b ( 1'b0 ), + .data_b ( ), + .q_b( sprite_ram_dout[15:8] ) + ); + +// main 68k sprite ram low +dual_port_ram #(.LEN(16384)) sprite_ram_L ( + .clock_a ( clk_sys ), + .address_a ( m68k_a[14:1] ), + .wren_a ( !m68k_rw & m68k_spr_cs & !m68k_lds_n ), + .data_a ( m68k_dout[7:0] ), + .q_a ( m68k_sprite_dout[7:0] ), + + .clock_b ( clk_sys ), + .address_b ( sprite_ram_addr ), + .wren_b ( 1'b0 ), + .data_b ( ), + .q_b( sprite_ram_dout[7:0] ) + ); + + +wire [10:0] fg_ram_addr /* synthesis keep */; +wire [15:0] fg_ram_dout /* synthesis keep */; + +wire [15:0] m68k_fg_ram_dout; + +// foreground high +dual_port_ram #(.LEN(2048)) ram_fg_h ( + .clock_a ( clk_sys ), + .address_a ( m68k_a[11:1] ), + .wren_a ( !m68k_rw & m68k_fg_ram_cs & !m68k_uds_n ), // can write to m68k_fg_mirror_cs but not read + .data_a ( m68k_dout[15:8] ), + .q_a ( m68k_fg_ram_dout[15:8] ), + + .clock_b ( clk_sys ), + .address_b ( fg_ram_addr ), + .wren_b ( 1'b0 ), + .data_b ( ), + .q_b( fg_ram_dout[15:8] ) + + ); + +// foreground low +dual_port_ram #(.LEN(2048)) ram_fg_l ( + .clock_a ( clk_sys ), + .address_a ( m68k_a[11:1] ), + .wren_a ( !m68k_rw & m68k_fg_ram_cs & !m68k_lds_n ), + .data_a ( m68k_dout[7:0] ), + .q_a ( m68k_fg_ram_dout[7:0] ), + + .clock_b ( clk_sys ), + .address_b ( fg_ram_addr ), + .wren_b ( 1'b0 ), + .data_b ( ), + .q_b( fg_ram_dout[7:0] ) + ); + + +reg [10:0] tile_pal_addr; +wire [15:0] tile_pal_dout; + +// int dark = pal_data >> 15; +// int r = ((pal_data >> 7) & 0x1e) | ((pal_data >> 14) & 0x1) ; +// int g = ((pal_data >> 3) & 0x1e) | ((pal_data >> 13) & 0x1) ; +// int b = ((pal_data << 1) & 0x1e) | ((pal_data >> 12) & 0x1) ; + +// todo: shift for dark bit +wire [4:0] r_pal = { tile_pal_dout[11:8] , tile_pal_dout[14] }; +wire [4:0] g_pal = { tile_pal_dout[7:4] , tile_pal_dout[13] }; +wire [4:0] b_pal = { tile_pal_dout[3:0] , tile_pal_dout[12] }; + +// tile palette high +dual_port_ram #(.LEN(2048)) tile_pal_h ( + .clock_a ( clk_sys ), + .address_a ( m68k_a[11:1] ), + .wren_a ( !m68k_rw & m68k_pal_cs & !m68k_uds_n ), + .data_a ( m68k_dout[15:8] ), + .q_a ( m68k_pal_dout[15:8] ), + + .clock_b ( clk_sys ), + .address_b ( tile_pal_addr ), + .wren_b ( 1'b0 ), + .data_b ( ), + .q_b( tile_pal_dout[15:8] ) + ); + +// tile palette low +dual_port_ram #(.LEN(2048)) tile_pal_l ( + .clock_a ( clk_sys ), + .address_a ( m68k_a[11:1] ), + .wren_a ( !m68k_rw & m68k_pal_cs & !m68k_lds_n ), + .data_a ( m68k_dout[7:0] ), + .q_a ( m68k_pal_dout[7:0] ), + + .clock_b ( clk_sys ), + .address_b ( tile_pal_addr ), + .wren_b ( 1'b0 ), + .data_b ( ), + .q_b( tile_pal_dout[7:0] ) + ); + +// z80 ram +dual_port_ram #(.LEN(2048)) z80_ram ( + .clock_b ( clk_sys ), + .address_b ( z80_addr[10:0] ), + .wren_b ( z80_ram_cs & ~z80_wr_n ), + .data_b ( z80_dout ), + .q_b ( z80_ram_data ) + ); + +wire [15:0] spr_pal_dout ; +wire [15:0] m68k_spr_pal_dout ; + +wire [9:0] spr_buf_addr_r; +reg [9:0] spr_buf_addr_w; +reg spr_buf_w; +reg [15:0] spr_buf_din; +wire [15:0] spr_buf_dout; + +dual_port_ram #(.LEN(1024), .DATA_WIDTH(16)) spr_buffer_ram ( + .clock_a ( clk_sys ), + .address_a ( spr_buf_addr_w ), + .wren_a ( spr_buf_w ), + .data_a ( spr_buf_din ), + .q_a ( ), + + .clock_b ( clk_sys ), + .address_b ( spr_buf_addr_r ), + .data_b ( 16'd0 ), + .wren_b ( clk6_en ), + .q_b ( spr_buf_dout ) + ); + +// M68K RAM CONTROL +reg m68k_ram_req; +wire m68k_ram_ack; +reg [21:1] m68k_ram_a; +reg m68k_ram_we; +wire [15:0] m68k_ram_dout; +reg [15:0] m68k_ram_din; +reg [1:0] m68k_ram_ds; +reg m68k_ram_dtack; + +localparam M68K_RAM_IDLE = 0; +localparam M68K_RAM_M68K = 1; + +reg [1:0] m68k_ram_state; + +always @ (posedge clk_sys) begin + if ( reset == 1 ) begin + m68k_ram_dtack <= 0; + m68k_ram_state <= M68K_RAM_IDLE; + end else begin + if (!m68k_ram_cs) m68k_ram_dtack <= 0; + + case (m68k_ram_state) + M68K_RAM_IDLE: + if (m68k_ram_cs & !m68k_ram_dtack) begin + m68k_ram_a <= m68k_a[13:1]; + m68k_ram_din <= m68k_dout; + m68k_ram_we <= !m68k_rw; + m68k_ram_ds <= {!m68k_uds_n, !m68k_lds_n}; + m68k_ram_req <= !m68k_ram_req; + m68k_ram_state <= M68K_RAM_M68K; + end + + M68K_RAM_M68K: + if (m68k_ram_req == m68k_ram_ack) begin + m68k_ram_dtack <= 1; + m68k_ram_state <= M68K_RAM_IDLE; + end + endcase + end +end + +reg port1_req, port2_req; +always @(posedge clk_sys) begin + if (rom_download) begin + if (ioctl_wr) begin + port1_req <= ~port1_req; + port2_req <= ~port2_req; + end + end +end + +wire [15:0] m68k_rom_data; +wire m68k_rom_valid; + +wire [15:0] cpu2_do; +assign z80_rom_data = z80_addr[0] ? cpu2_do[7:0] : cpu2_do[15:8]; +wire z80_rom_valid; + +wire [15:0] cpu4_do; +wire [16:0] upd_rom_addr; +wire [7:0] upd_rom_data = upd_rom_addr[0] ? cpu4_do[7:0] : cpu4_do[15:8]; +wire upd_rom_cs; +wire upd_rom_valid; + +reg [19:0] sprite_rom_addr; +wire [31:0] sprite_rom_data; +reg sprite_rom_req; +wire sprite_rom_ack; + +reg [14:0] fg_rom_addr; +wire [15:0] fg_rom_data; +wire fg_rom_valid; + +sdram #(CLKSYS) sdram +( + .*, + .init_n ( pll_locked ), + .clk ( clk_sys ), + + // Bank 0-1 ops + .port1_a ( ioctl_addr[23:1] ), + .port1_req ( port1_req ), + .port1_ack (), + .port1_we ( rom_download ), + .port1_ds ( {~ioctl_addr[0], ioctl_addr[0]} ), + .port1_d ( {ioctl_dout, ioctl_dout} ), + .port1_q (), + + // M68K + .cpu1_rom_addr ( {m68k_rom_2_cs, m68k_a[17:1]} ), //ioctl_addr >= 24'h000000) & (ioctl_addr < 24'h040000 + .cpu1_rom_cs ( m68k_rom_cs | m68k_rom_2_cs ), + .cpu1_rom_q ( m68k_rom_data ), + .cpu1_rom_valid( m68k_rom_valid), + + .cpu1_ram_req ( m68k_ram_req ), + .cpu1_ram_ack ( m68k_ram_ack ), + .cpu1_ram_addr ( m68k_ram_a ), + .cpu1_ram_we ( m68k_ram_we ), + .cpu1_ram_d ( m68k_ram_din ), + .cpu1_ram_q ( m68k_ram_dout ), + .cpu1_ram_ds ( m68k_ram_ds ), + + // Audio Z80 + .cpu2_addr ( {4'h8, z80_addr[15:1]} ), // (ioctl_addr >= 24'h080000) & (ioctl_addr < 24'h090000) ; + .cpu2_rom_cs ( z80_rom_cs ), + .cpu2_q ( cpu2_do ), + .cpu2_valid ( z80_rom_valid ), + + .cpu3_addr ( {4'hC, fg_rom_addr} ), // (ioctl_addr >= 24'h0c0000) & (ioctl_addr < 24'h0d0000) ; + .cpu3_rom_cs ( 1'b1 ), + .cpu3_q ( fg_rom_data ), + .cpu3_valid ( fg_rom_valid ), + + .cpu4_addr ( {3'b101, upd_rom_addr[16:1]} ), // (ioctl_addr >= 24'hA0000) & (ioctl_addr < 24'hC0000) + .cpu4_rom_cs ( upd_rom_cs ), + .cpu4_q ( cpu4_do ), + .cpu4_valid ( upd_rom_valid ), + + // Bank 2-3 ops + .port2_a ( ioctl_addr[23:1] ), + .port2_req ( port2_req ), + .port2_ack ( ), + .port2_we ( rom_download ), + .port2_ds ( {~ioctl_addr[0], ioctl_addr[0]} ), + .port2_d ( {ioctl_dout, ioctl_dout} ), + .port2_q ( ), + + .gfx1_addr ( ), + .gfx1_q ( ), + + .gfx2_addr ( ), + .gfx2_q ( ), + + .gfx3_addr ( ), + .gfx3_q ( ), + + .sp_addr ( 20'h40000 + sprite_rom_addr ), // (ioctl_addr >= 24'h100000) & (ioctl_addr < 24'h400000) + .sp_req ( sprite_rom_req ), + .sp_ack ( sprite_rom_ack ), + .sp_q ( sprite_rom_data ) +); + +endmodule diff --git a/Arcade_MiST/SNK M68000 Harware/SNK68/rtl/SNK68_MiST.sv b/Arcade_MiST/SNK M68000 Harware/SNK68/rtl/SNK68_MiST.sv new file mode 100644 index 00000000..00e7d09b --- /dev/null +++ b/Arcade_MiST/SNK M68000 Harware/SNK68/rtl/SNK68_MiST.sv @@ -0,0 +1,337 @@ +//============================================================================ +// SNK M68000 HW top-level for MiST +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module SNK68_MiST +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + inout SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input SPI_SS4, + input CONF_DATA0, + input CLOCK_27, + + output [12:0] SDRAM_A, + inout [15:0] SDRAM_DQ, + output SDRAM_DQML, + output SDRAM_DQMH, + output SDRAM_nWE, + output SDRAM_nCAS, + output SDRAM_nRAS, + output SDRAM_nCS, + output [1:0] SDRAM_BA, + output SDRAM_CLK, + output SDRAM_CKE +); + +//`define DEBUG + +`include "build_id.v" + +`define CORE_NAME "IKARI3" +wire [6:0] core_mod; + +localparam CONF_STR = { + `CORE_NAME, ";;", + "O2,Rotate Controls,Off,On;", + "O34,Scanlines,Off,25%,50%,75%;", + "O5,Blending,Off,On;", + "O6,Joystick Swap,Off,On;", + "O7,Pause,Off,On;", + "O8,Service,Off,On;", + "O1,Video Timing,54.1Hz (PCB),59.2Hz (MAME);", +`ifdef DEBUG + "OD,Flip,Off,On;", +`endif + "DIP;", + "T0,Reset;", + "V,v1.20.",`BUILD_DATE +}; + +wire rotate = status[2]; +wire [1:0] scanlines = status[4:3]; +wire blend = status[5]; +wire joyswap = status[6]; +wire pause = status[7]; +wire service = status[8]; +wire vidmode = status[1]; + +reg [7:0] dsw1; +reg [7:0] dsw2; +reg [7:0] p1, p2; +reg [15:0] coin; +reg [1:0] orientation; +wire flipped; + +wire key_test = m_fire1[3]; + +always @(*) begin + orientation[0] = core_mod[3]; // bit3 - tate + orientation[1] = ~flipped; + + p1 = ~{ m_one_player, m_fire1[2:0], m_right1, m_left1, m_down1, m_up1 }; + p2 = ~{ m_two_players, m_fire2[2:0], m_right2, m_left2, m_down2, m_up2 }; + + dsw1 = status[23:16]; + dsw2 = status[31:24]; + coin = ~{ { 2 { 2'b0, m_coin2, m_coin1, 2'b0, service, key_test } } }; +end + +wire rot1_cw = m_fire1[7] | m_right1B | m_up1B; // R +wire rot1_ccw = m_fire1[6] | m_left1B | m_down1B; // L +wire rot2_cw = m_fire2[7] | m_right2B | m_up2B; // R +wire rot2_ccw = m_fire2[6] | m_left2B | m_down2B; // L + +wire [11:0] rotary1; +wire [11:0] rotary2; + +rotary_ctrl rot1(clk_72, reset, rot1_cw, rot1_ccw, rotary1); +rotary_ctrl rot2(clk_72, reset, rot2_cw, rot2_ccw, rotary2); + +assign LED = ~ioctl_downl; +assign SDRAM_CLK = clk_72; +assign SDRAM_CKE = 1; + +wire clk_72; +wire pll_locked; +pll_mist pll( + .inclk0(CLOCK_27), + .c0(clk_72), + .locked(pll_locked) + ); + +// reset generation +reg reset = 1; +reg rom_loaded = 0; +always @(posedge clk_72) begin + reg ioctl_downlD; + ioctl_downlD <= ioctl_downl; + + if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1; + reset <= status[0] | buttons[1] | ~rom_loaded | ioctl_downl; +end + +// ARM connection +wire [63:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [31:0] joystick_0; +wire [31:0] joystick_1; +wire scandoublerD; +wire ypbpr; +wire no_csync; +wire key_strobe; +wire key_pressed; +wire [7:0] key_code; + +user_io #( + .STRLEN($size(CONF_STR)>>3), + .ROM_DIRECT_UPLOAD(1)) +user_io( + .clk_sys (clk_72 ), + .conf_str (CONF_STR ), + .SPI_CLK (SPI_SCK ), + .SPI_SS_IO (CONF_DATA0 ), + .SPI_MISO (SPI_DO ), + .SPI_MOSI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable (scandoublerD ), + .ypbpr (ypbpr ), + .no_csync (no_csync ), + .core_mod (core_mod ), + .key_strobe (key_strobe ), + .key_pressed (key_pressed ), + .key_code (key_code ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) + ); + +wire ioctl_downl; +wire [7:0] ioctl_index; +wire ioctl_wr; +wire [24:0] ioctl_addr; +wire [7:0] ioctl_dout; + +data_io #(.ROM_DIRECT_UPLOAD(1)) data_io( + .clk_sys ( clk_72 ), + .SPI_SCK ( SPI_SCK ), + .SPI_SS2 ( SPI_SS2 ), + .SPI_SS4 ( SPI_SS4 ), + .SPI_DI ( SPI_DI ), + .SPI_DO ( SPI_DO ), + .ioctl_download( ioctl_downl ), + .ioctl_index ( ioctl_index ), + .ioctl_wr ( ioctl_wr ), + .ioctl_addr ( ioctl_addr ), + .ioctl_dout ( ioctl_dout ) +); + +wire [15:0] laudio, raudio; +wire hs, vs; +wire blankn = ~(hb | vb); +wire hb, vb; +wire [4:0] r,b,g; + +SNK68 SNK68 +( + .pll_locked ( pll_locked ), + .clk_sys ( clk_72 ), + .reset ( reset ), + .pcb ( core_mod[2:0] ), + .pause_cpu ( pause ), + .refresh_sel ( vidmode ), + +`ifdef DEBUG + .test_flip ( status[13] ), +`else + .test_flip ( 1'b0 ), +`endif + .flip ( flipped ), + .p1 ( p1 ), + .p2 ( p2 ), + .dsw1 ( dsw1 ), + .dsw2 ( dsw2 ), + .coin ( coin ), + .rotary1 ( rotary1 ), + .rotary2 ( rotary2 ), + + .hbl ( hb ), + .vbl ( vb ), + .hsync ( hs ), + .vsync ( vs ), + .r ( r ), + .g ( g ), + .b ( b ), + + .audio_l ( laudio ), + .audio_r ( raudio ), + + .rom_download ( ioctl_downl && ioctl_index == 0), + .ioctl_addr ( ioctl_addr ), + .ioctl_wr ( ioctl_wr ), + .ioctl_dout ( ioctl_dout ), + + .SDRAM_A ( SDRAM_A ), + .SDRAM_BA ( SDRAM_BA ), + .SDRAM_DQ ( SDRAM_DQ ), + .SDRAM_DQML ( SDRAM_DQML ), + .SDRAM_DQMH ( SDRAM_DQMH ), + .SDRAM_nCS ( SDRAM_nCS ), + .SDRAM_nCAS ( SDRAM_nCAS ), + .SDRAM_nRAS ( SDRAM_nRAS ), + .SDRAM_nWE ( SDRAM_nWE ) +); + +mist_video #(.COLOR_DEPTH(5),.SD_HCNT_WIDTH(10)) mist_video( + .clk_sys(clk_72), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R(blankn ? r : 5'd0), + .G(blankn ? g : 5'd0), + .B(blankn ? b : 5'd0), + .HSync(~hs), + .VSync(~vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .no_csync(no_csync), + .rotate({orientation[1],rotate}), + .ce_divider(3'd5), // pix clock = 72/6 + .blend(blend), + .scandoubler_disable(scandoublerD), + .scanlines(scanlines), + .ypbpr(ypbpr) + ); + +dac #(16) dacl( + .clk_i(clk_72), + .res_n_i(1), + .dac_i({~laudio[15], laudio[14:0]}), + .dac_o(AUDIO_L) + ); + +dac #(16) dacr( + .clk_i(clk_72), + .res_n_i(1), + .dac_i({~raudio[15], raudio[14:0]}), + .dac_o(AUDIO_R) + ); + +// Common inputs +wire m_up1, m_down1, m_left1, m_right1, m_up1B, m_down1B, m_left1B, m_right1B; +wire m_up2, m_down2, m_left2, m_right2, m_up2B, m_down2B, m_left2B, m_right2B; +wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players; +wire [11:0] m_fire1, m_fire2; + +arcade_inputs inputs ( + .clk ( clk_72 ), + .key_strobe ( key_strobe ), + .key_pressed ( key_pressed ), + .key_code ( key_code ), + .joystick_0 ( joystick_0 ), + .joystick_1 ( joystick_1 ), + .rotate ( rotate ), + .orientation ( orientation ), + .joyswap ( joyswap ), + .oneplayer ( 1'b0 ), + .controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ), + .player1 ( {m_up1B, m_down1B, m_left1B, m_right1B, m_fire1, m_up1, m_down1, m_left1, m_right1} ), + .player2 ( {m_up2B, m_down2B, m_left2B, m_right2B, m_fire2, m_up2, m_down2, m_left2, m_right2} ) +); + +endmodule + +module rotary_ctrl +( + input clk_sys, + input reset, + input cw, + input ccw, + output reg [11:0] rotary +); + +reg cw_last, ccw_last; +always @ (posedge clk_sys) begin + if (reset) begin + rotary <= 12'h1; + end else begin + cw_last <= cw; + ccw_last <= ccw; + if (cw & ~cw_last) + rotary <= { rotary[0], rotary[11:1] }; + + if (ccw & ~ccw_last) + rotary <= { rotary[10:0], rotary[11] }; + end +end + +endmodule diff --git a/Arcade_MiST/SNK M68000 Harware/SNK68/rtl/build_id.tcl b/Arcade_MiST/SNK M68000 Harware/SNK68/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade_MiST/SNK M68000 Harware/SNK68/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/SNK M68000 Harware/SNK68/rtl/chip_select.v b/Arcade_MiST/SNK M68000 Harware/SNK68/rtl/chip_select.v new file mode 100644 index 00000000..3ecdb1d0 --- /dev/null +++ b/Arcade_MiST/SNK M68000 Harware/SNK68/rtl/chip_select.v @@ -0,0 +1,240 @@ +// + +module chip_select +( + input [3:0] pcb, + + input [23:0] m68k_a, + input m68k_as_n, + input m68k_rw, + input m68k_uds_n, + input m68k_lds_n, + + input [15:0] z80_addr, + input MREQ_n, + input IORQ_n, + input M1_n, + input RFSH_n, + + // M68K selects + output reg m68k_rom_cs, + output reg m68k_rom_2_cs, + output reg m68k_ram_cs, + output reg m68k_spr_cs, + output reg m68k_pal_cs, + output reg m68k_fg_ram_cs, + output reg m68k_scr_flip_cs, + output reg input_p1_cs, + output reg input_p2_cs, + output reg input_dsw1_cs, + output reg input_dsw2_cs, + output reg input_coin_cs, + output reg m68k_rotary1_cs, + output reg m68k_rotary2_cs, + output reg m68k_rotary_lsb_cs, + output reg m_invert_ctrl_cs, + output reg m68k_latch_cs, + output reg z80_latch_read_cs, + + // Z80 selects + output reg z80_rom_cs, + output reg z80_ram_cs, + output reg z80_latch_cs, + + output reg z80_sound0_cs, + output reg z80_sound1_cs, + output reg z80_upd_cs, + output reg z80_upd_r_cs +); + +`include "defs.v" + +function m68k_cs; + input [23:0] start_address; + input [23:0] end_address; +begin + m68k_cs = ( m68k_a[23:0] >= start_address && m68k_a[23:0] <= end_address) & !m68k_as_n & !(m68k_uds_n & m68k_lds_n); +end +endfunction + +function z80_mem_cs; + input [15:0] base_address; + input [7:0] width; +begin + z80_mem_cs = ( z80_addr >> width == base_address >> width ) & !MREQ_n && RFSH_n; +end +endfunction + +function z80_io_cs; + input [7:0] address_lo; +begin + z80_io_cs = ( z80_addr[7:0] == address_lo ) && !IORQ_n && M1_n; +end +endfunction + +always @ (*) begin + // Memory mapping based on PCB type + z80_rom_cs = !MREQ_n && RFSH_n && z80_addr[15:0] < 16'hf000; + z80_ram_cs = !MREQ_n && RFSH_n && z80_addr[15:0] >= 16'hf000 && z80_addr[15:0] < 16'hf800; + z80_latch_cs = !MREQ_n && RFSH_n && z80_addr[15:0] == 16'hf800; + + case (pcb) + pcb_A7007_A8007: begin + m68k_rom_cs = m68k_cs( 24'h000000, 24'h03ffff ); + m68k_rom_2_cs = m68k_cs( 24'h300000, 24'h33ffff ); + + m68k_ram_cs = m68k_cs( 24'h040000, 24'h043fff ); + + // write only + m68k_latch_cs = m68k_cs( 24'h080000, 24'h080001 ) & !m68k_rw; + + // read only + input_p1_cs = m68k_cs( 24'h080000, 24'h080001 ) & m68k_rw; + + input_p2_cs = m68k_cs( 24'h080002, 24'h080003 ); + input_coin_cs = m68k_cs( 24'h080004, 24'h080005 ); + m_invert_ctrl_cs = m68k_cs( 24'h080006, 24'h080007 ); + + m68k_scr_flip_cs = m68k_cs( 24'h0c0000, 24'h0c0001 ); + + m68k_rotary1_cs = m68k_cs( 24'h0c0000, 24'h0c0001 ); + m68k_rotary2_cs = m68k_cs( 24'h0c8000, 24'h0c8001 ); + m68k_rotary_lsb_cs = m68k_cs( 24'h0d0000, 24'h0d0001 ); + + input_dsw1_cs = m68k_cs( 24'h0f0000, 24'h0f0001 ) ; + input_dsw2_cs = m68k_cs( 24'h0f0008, 24'h0f0009 ) ; + + z80_latch_read_cs = m68k_cs( 24'h0f8000, 24'h0f8001 ) ; + m68k_spr_cs = m68k_cs( 24'h100000, 24'h107fff ) ; + m68k_fg_ram_cs = m68k_cs( 24'h200000, 24'h200fff ) | m68k_cs( 24'h201000, 24'h201fff ) ; + m68k_pal_cs = m68k_cs( 24'h400000, 24'h400fff ) ; + + z80_sound0_cs = z80_io_cs(8'h00); // ym3812 address + z80_sound1_cs = z80_io_cs(8'h20); // ym3812 data + z80_upd_cs = z80_io_cs(8'h40); // 7759 write + z80_upd_r_cs = z80_io_cs(8'h80); // 7759 reset + + end + + pcb_A7008: begin + m68k_rom_cs = m68k_cs( 24'h000000, 24'h03ffff ) ; + m68k_rom_2_cs = 0; + m68k_ram_cs = m68k_cs( 24'h040000, 24'h043fff ) ; + + // read only + input_p2_cs = m68k_cs( 24'h080000, 24'h080001 ) & m68k_rw ; + + // write only + m68k_latch_cs = m68k_cs( 24'h080000, 24'h080001 ) & !m68k_rw ; + + // read only + input_coin_cs = m68k_cs( 24'h0c0000, 24'h0c0001 ) & m68k_rw ; + + m_invert_ctrl_cs = 0; + + // write only + m68k_scr_flip_cs = m68k_cs( 24'h0c0000, 24'h0c0001 ) & !m68k_rw; + + input_p1_cs = m68k_cs( 24'h080000, 24'h080001 ) ; + + m68k_rotary1_cs = 0; + m68k_rotary2_cs = 0; + m68k_rotary_lsb_cs = 0; + + input_dsw1_cs = m68k_cs( 24'h0f0000, 24'h0f0001 ) ; + input_dsw2_cs = m68k_cs( 24'h0f0008, 24'h0f0009 ) ; + m68k_spr_cs = m68k_cs( 24'h200000, 24'h207fff ) ; + m68k_fg_ram_cs = m68k_cs( 24'h100000, 24'h100fff ) | m68k_cs( 24'h101000, 24'h101fff ); + m68k_pal_cs = m68k_cs( 24'h400000, 24'h400fff ) ; + + z80_latch_read_cs = 0; + + + z80_sound0_cs = z80_io_cs(8'h00); // ym3812 address + z80_sound1_cs = z80_io_cs(8'h20); // ym3812 data + z80_upd_cs = z80_io_cs(8'h40); // 7759 write + z80_upd_r_cs = z80_io_cs(8'h80); // 7759 reset + + end + + pcb_A7008_SS: begin + m68k_rom_cs = m68k_cs( 24'h000000, 24'h03ffff ) ; + m68k_rom_2_cs = 0; + m68k_ram_cs = m68k_cs( 24'h040000, 24'h043fff ) ; + + // read only + input_p2_cs = m68k_cs( 24'h080000, 24'h080001 ) & m68k_rw ; + // write only + m68k_latch_cs = m68k_cs( 24'h080000, 24'h080001 ) & !m68k_rw ; + + // read only + input_coin_cs = m68k_cs( 24'h0c0000, 24'h0c0001 ) & m68k_rw ; + + m_invert_ctrl_cs = 0; + + // write only + m68k_scr_flip_cs = m68k_cs( 24'h0c0000, 24'h0c0001 ) & !m68k_rw; + + + input_p1_cs = m68k_cs( 24'h080000, 24'h080001 ) ; + + input_dsw1_cs = m68k_cs( 24'h0f0000, 24'h0f0001 ) ; + input_dsw2_cs = m68k_cs( 24'h0f0008, 24'h0f0009 ) ; + + m68k_rotary1_cs = 0; + m68k_rotary2_cs = 0; + m68k_rotary_lsb_cs = 0; + + m68k_spr_cs = m68k_cs( 24'h200000, 24'h207fff ) ; + m68k_fg_ram_cs = m68k_cs( 24'h100000, 24'h100fff ) | m68k_cs( 24'h101000, 24'h101fff ); + m68k_pal_cs = m68k_cs( 24'h400000, 24'h400fff ) ; + + z80_latch_read_cs = 0; + + z80_sound0_cs = z80_io_cs(8'h00); // ym3812 address + z80_sound1_cs = z80_io_cs(8'h20); // ym3812 data + z80_upd_cs = z80_io_cs(8'h40); // 7759 write + z80_upd_r_cs = z80_io_cs(8'h80); // 7759 reset + end + + default: begin + m68k_rom_cs = 0; + m68k_rom_2_cs = 0; + + m68k_ram_cs = 0; + + // write only + m68k_latch_cs = 0; + + // read only + input_p1_cs = 0; + + input_p2_cs = 0; + input_coin_cs = 0; + m_invert_ctrl_cs = 0; + + m68k_scr_flip_cs = 0; + + m68k_rotary1_cs = 0; + m68k_rotary2_cs = 0; + m68k_rotary_lsb_cs = 0; + + input_dsw1_cs = 0; + input_dsw2_cs = 0; + + z80_latch_read_cs = 0; + m68k_spr_cs = 0; + m68k_fg_ram_cs = 0; + m68k_pal_cs = 0; + + z80_sound0_cs = 0; + z80_sound1_cs = 0; + z80_upd_cs = 0; + z80_upd_r_cs = 0; + + end + endcase + +end + +endmodule diff --git a/Arcade_MiST/SNK M68000 Harware/SNK68/rtl/defs.v b/Arcade_MiST/SNK M68000 Harware/SNK68/rtl/defs.v new file mode 100644 index 00000000..ce16e5f9 --- /dev/null +++ b/Arcade_MiST/SNK M68000 Harware/SNK68/rtl/defs.v @@ -0,0 +1,3 @@ +localparam pcb_A7007_A8007 = 0; // [ikari3], [searchar], [streetsmj, streetsm1, streetsmw] - Ikari III, S.A.R., and Street Smart V1 (mame nomenclature, would be V2) +localparam pcb_A7008 = 1; // [pow] - P.O.W. +localparam pcb_A7008_SS = 2; // [streetsm] - Street Smart V2 (mame nomenclature, would be V1) diff --git a/Arcade_MiST/SNK M68000 Harware/SNK68/rtl/dual_port_ram.vhd b/Arcade_MiST/SNK M68000 Harware/SNK68/rtl/dual_port_ram.vhd new file mode 100644 index 00000000..e47fb4b2 --- /dev/null +++ b/Arcade_MiST/SNK M68000 Harware/SNK68/rtl/dual_port_ram.vhd @@ -0,0 +1,117 @@ +-- __ __ __ __ __ __ +-- /\ "-.\ \ /\ \/\ \ /\ \ /\ \ +-- \ \ \-. \ \ \ \_\ \ \ \ \____ \ \ \____ +-- \ \_\\"\_\ \ \_____\ \ \_____\ \ \_____\ +-- \/_/ \/_/ \/_____/ \/_____/ \/_____/ +-- ______ ______ __ ______ ______ ______ +-- /\ __ \ /\ == \ /\ \ /\ ___\ /\ ___\ /\__ _\ +-- \ \ \/\ \ \ \ __< _\_\ \ \ \ __\ \ \ \____ \/_/\ \/ +-- \ \_____\ \ \_____\ /\_____\ \ \_____\ \ \_____\ \ \_\ +-- \/_____/ \/_____/ \/_____/ \/_____/ \/_____/ \/_/ +-- +-- https://joshbassett.info +-- https://twitter.com/nullobject +-- https://github.com/nullobject +-- +-- Copyright (c) 2020 Josh Bassett +-- +-- Permission is hereby granted, free of charge, to any person obtaining a copy +-- of this software and associated documentation files (the "Software"), to deal +-- in the Software without restriction, including without limitation the rights +-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +-- copies of the Software, and to permit persons to whom the Software is +-- furnished to do so, subject to the following conditions: +-- +-- The above copyright notice and this permission notice shall be included in all +-- copies or substantial portions of the Software. +-- +-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +-- SOFTWARE. + +-- 2022-05-24 Changed to use word count instead of address width +-- and renamed ports to match quartus IP naming + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +--use work.common.all; +use work.math.all; + +library altera_mf; +use altera_mf.altera_mf_components.all; + +entity dual_port_ram is + generic ( + LEN : natural := 8192; + DATA_WIDTH : natural := 8 + ); + port ( + -- port A + clock_a : in std_logic; + address_a : in unsigned(ilog2(LEN)-1 downto 0); + data_a : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0'); + q_a : out std_logic_vector(DATA_WIDTH-1 downto 0); + wren_a : in std_logic := '0'; + + -- port B + clock_b : in std_logic; + address_b : in unsigned(ilog2(LEN)-1 downto 0); + data_b : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0'); + q_b : out std_logic_vector(DATA_WIDTH-1 downto 0); + wren_b : in std_logic := '0' + ); +end dual_port_ram; + +architecture arch of dual_port_ram is + +begin + altsyncram_component : altsyncram + generic map ( + address_reg_b => "CLOCK1", + clock_enable_input_a => "BYPASS", + clock_enable_input_b => "BYPASS", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", + intended_device_family => "Cyclone V", + lpm_type => "altsyncram", + numwords_a => LEN, + numwords_b => LEN, + operation_mode => "BIDIR_DUAL_PORT", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => "UNREGISTERED", + outdata_reg_b => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", + width_a => DATA_WIDTH, + width_b => DATA_WIDTH, + width_byteena_a => 1, + width_byteena_b => 1, + widthad_a => ilog2(LEN), + widthad_b => ilog2(LEN), + wrcontrol_wraddress_reg_b => "CLOCK1" + ) + port map ( + address_a => std_logic_vector(address_a), + address_b => std_logic_vector(address_b), + clock0 => clock_a, + clock1 => clock_b, + data_a => data_a, + data_b => data_b, + wren_a => wren_a, + wren_b => wren_b, + q_a => q_a, + q_b => q_b + ); + + +end architecture arch; diff --git a/Arcade_MiST/SNK M68000 Harware/SNK68/rtl/math.vhd b/Arcade_MiST/SNK M68000 Harware/SNK68/rtl/math.vhd new file mode 100644 index 00000000..5d64d8c7 --- /dev/null +++ b/Arcade_MiST/SNK M68000 Harware/SNK68/rtl/math.vhd @@ -0,0 +1,72 @@ +-- __ __ __ __ __ __ +-- /\ "-.\ \ /\ \/\ \ /\ \ /\ \ +-- \ \ \-. \ \ \ \_\ \ \ \ \____ \ \ \____ +-- \ \_\\"\_\ \ \_____\ \ \_____\ \ \_____\ +-- \/_/ \/_/ \/_____/ \/_____/ \/_____/ +-- ______ ______ __ ______ ______ ______ +-- /\ __ \ /\ == \ /\ \ /\ ___\ /\ ___\ /\__ _\ +-- \ \ \/\ \ \ \ __< _\_\ \ \ \ __\ \ \ \____ \/_/\ \/ +-- \ \_____\ \ \_____\ /\_____\ \ \_____\ \ \_____\ \ \_\ +-- \/_____/ \/_____/ \/_____/ \/_____/ \/_____/ \/_/ +-- +-- https://joshbassett.info +-- https://twitter.com/nullobject +-- https://github.com/nullobject +-- +-- Copyright (c) 2020 Josh Bassett +-- +-- Permission is hereby granted, free of charge, to any person obtaining a copy +-- of this software and associated documentation files (the "Software"), to deal +-- in the Software without restriction, including without limitation the rights +-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +-- copies of the Software, and to permit persons to whom the Software is +-- furnished to do so, subject to the following conditions: +-- +-- The above copyright notice and this permission notice shall be included in all +-- copies or substantial portions of the Software. +-- +-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +-- SOFTWARE. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +package math is + -- calculates the log2 of the given number + function ilog2(n : natural) return natural; + + -- Masks the given range of bits for a vector. + -- + -- Only the bits between the MSB and LSB (inclusive) will be kept, all other + -- bits will be masked out. + function mask_bits(data : std_logic_vector; msb : natural; lsb : natural) return std_logic_vector; + function mask_bits(data : std_logic_vector; msb : natural; lsb : natural; size : natural) return std_logic_vector; +end package math; + +package body math is + function ilog2(n : natural) return natural is + begin + return natural(ceil(log2(real(n)))); + end ilog2; + + function mask_bits(data : std_logic_vector; msb : natural; lsb : natural) return std_logic_vector is + variable n : natural; + variable mask : std_logic_vector(data'length-1 downto 0); + begin + n := (2**(msb-lsb+1))-1; + mask := std_logic_vector(shift_left(to_unsigned(n, mask'length), lsb)); + return std_logic_vector(shift_right(unsigned(data AND mask), lsb)); + end mask_bits; + + function mask_bits(data : std_logic_vector; msb : natural; lsb : natural; size : natural) return std_logic_vector is + begin + return std_logic_vector(resize(unsigned(mask_bits(data, msb, lsb)), size)); + end mask_bits; +end package body math; diff --git a/Arcade_MiST/SNK M68000 Harware/SNK68/rtl/pll_mist.qip b/Arcade_MiST/SNK M68000 Harware/SNK68/rtl/pll_mist.qip new file mode 100644 index 00000000..6182871f --- /dev/null +++ b/Arcade_MiST/SNK M68000 Harware/SNK68/rtl/pll_mist.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_mist.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_mist.ppf"] diff --git a/Arcade_MiST/SNK M68000 Harware/SNK68/rtl/pll_mist.v b/Arcade_MiST/SNK M68000 Harware/SNK68/rtl/pll_mist.v new file mode 100644 index 00000000..09a344d2 --- /dev/null +++ b/Arcade_MiST/SNK M68000 Harware/SNK68/rtl/pll_mist.v @@ -0,0 +1,309 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll_mist.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.4 Build 182 03/12/2014 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2014 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll_mist ( + inclk0, + c0, + locked); + + input inclk0; + output c0; + output locked; + + wire [4:0] sub_wire0; + wire sub_wire2; + wire [0:0] sub_wire5 = 1'h0; + wire [0:0] sub_wire1 = sub_wire0[0:0]; + wire c0 = sub_wire1; + wire locked = sub_wire2; + wire sub_wire3 = inclk0; + wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; + + altpll altpll_component ( + .inclk (sub_wire4), + .clk (sub_wire0), + .locked (sub_wire2), + .activeclock (), + .areset (1'b0), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 3, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 8, + altpll_component.clk0_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_mist", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_UNUSED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "72.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "16" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "72.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_mist.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/SNK M68000 Harware/SNK68/rtl/sdram.sv b/Arcade_MiST/SNK M68000 Harware/SNK68/rtl/sdram.sv new file mode 100644 index 00000000..f1f36e8c --- /dev/null +++ b/Arcade_MiST/SNK M68000 Harware/SNK68/rtl/sdram.sv @@ -0,0 +1,447 @@ +// +// sdram.v +// +// sdram controller implementation for the MiST board +// https://github.com/mist-devel/mist-board +// +// Copyright (c) 2013 Till Harbaum +// Copyright (c) 2019-2022 Gyorgy Szombathelyi +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +module sdram ( + + // interface to the MT48LC16M16 chip + inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus + output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus + output reg SDRAM_DQML, // two byte masks + output reg SDRAM_DQMH, // two byte masks + output reg [1:0] SDRAM_BA, // two banks + output SDRAM_nCS, // a single chip select + output SDRAM_nWE, // write enable + output SDRAM_nRAS, // row address select + output SDRAM_nCAS, // columns address select + + // cpu/chipset interface + input init_n, // init signal after FPGA config to initialize RAM + input clk, // sdram clock + + // 1st bank + input port1_req, + output reg port1_ack, + input port1_we, + input [23:1] port1_a, + input [1:0] port1_ds, + input [15:0] port1_d, + output reg [15:0] port1_q, + + // cpu1 rom/ram + input [21:1] cpu1_rom_addr, + input cpu1_rom_cs, + output reg [15:0] cpu1_rom_q, + output reg cpu1_rom_valid, + + input cpu1_ram_req, + output reg cpu1_ram_ack, + input [21:1] cpu1_ram_addr, + input cpu1_ram_we, + input [1:0] cpu1_ram_ds, + input [15:0] cpu1_ram_d, + output reg [15:0] cpu1_ram_q, + + // cpu2 rom + input [21:1] cpu2_addr, + input cpu2_rom_cs, + output reg [15:0] cpu2_q, + output reg cpu2_valid, + // cpu3 rom + input [21:1] cpu3_addr, + input cpu3_rom_cs, + output reg [15:0] cpu3_q, + output reg cpu3_valid, + // cpu4 rom + input [21:1] cpu4_addr, + input cpu4_rom_cs, + output reg [15:0] cpu4_q, + output reg cpu4_valid, + + // 2nd bank + input port2_req, + output reg port2_ack, + input port2_we, + input [23:1] port2_a, + input [1:0] port2_ds, + input [15:0] port2_d, + output reg [31:0] port2_q, + + input [21:2] gfx1_addr, + output reg [31:0] gfx1_q, + input [21:2] gfx2_addr, + output reg [31:0] gfx2_q, + input [21:2] gfx3_addr, + output reg [31:0] gfx3_q, + + input [21:2] sp_addr, + input sp_req, + output reg sp_ack, + output reg [31:0] sp_q +); + +parameter MHZ = 16'd80; // 80 MHz default clock, set it to proper value to calculate refresh rate + +localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz +localparam BURST_LENGTH = 3'b001; // 000=1, 001=2, 010=4, 011=8 +localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved +localparam CAS_LATENCY = 3'd2; // 2/3 allowed +localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed +localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write + +localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH}; + +// 64ms/8192 rows = 7.8us +localparam RFRSH_CYCLES = 16'd78*MHZ/4'd10; + +// --------------------------------------------------------------------- +// ------------------------ cycle state machine ------------------------ +// --------------------------------------------------------------------- + +/* + SDRAM state machine for 2 bank interleaved access + 2 words burst, CL2 +cmd issued registered + 0 RAS0 cas1 - data0 read burst terminated + 1 ras0 + 2 data1 returned + 3 CAS0 data1 returned + 4 RAS1 cas0 + 5 ras1 + 6 CAS1 data0 returned +*/ + +localparam STATE_RAS0 = 3'd0; // first state in cycle +localparam STATE_RAS1 = 3'd4; // Second ACTIVE command after RAS0 + tRRD (15ns) +localparam STATE_CAS0 = STATE_RAS0 + RASCAS_DELAY + 1'd1; // CAS phase - 3 +localparam STATE_CAS1 = STATE_RAS1 + RASCAS_DELAY; // CAS phase - 6 +localparam STATE_READ0 = 3'd0;// STATE_CAS0 + CAS_LATENCY + 2'd2; // 7 +localparam STATE_READ1 = 3'd3; +localparam STATE_DS1b = 3'd0; +localparam STATE_READ1b = 3'd4; +localparam STATE_LAST = 3'd6; + +reg [2:0] t; + +always @(posedge clk) begin + t <= t + 1'd1; + if (t == STATE_LAST) t <= STATE_RAS0; +end + +// --------------------------------------------------------------------- +// --------------------------- startup/reset --------------------------- +// --------------------------------------------------------------------- + +// wait 1ms (32 8Mhz cycles) after FPGA config is done before going +// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0) +reg [4:0] reset; +reg init = 1'b1; +always @(posedge clk, negedge init_n) begin + if(!init_n) begin + reset <= 5'h1f; + init <= 1'b1; + end else begin + if((t == STATE_LAST) && (reset != 0)) reset <= reset - 5'd1; + init <= !(reset == 0); + end +end + +// --------------------------------------------------------------------- +// ------------------ generate ram control signals --------------------- +// --------------------------------------------------------------------- + +// all possible commands +localparam CMD_INHIBIT = 4'b1111; +localparam CMD_NOP = 4'b0111; +localparam CMD_ACTIVE = 4'b0011; +localparam CMD_READ = 4'b0101; +localparam CMD_WRITE = 4'b0100; +localparam CMD_BURST_TERMINATE = 4'b0110; +localparam CMD_PRECHARGE = 4'b0010; +localparam CMD_AUTO_REFRESH = 4'b0001; +localparam CMD_LOAD_MODE = 4'b0000; + +reg [3:0] sd_cmd; // current command sent to sd ram +reg [15:0] sd_din; +// drive control signals according to current command +assign SDRAM_nCS = sd_cmd[3]; +assign SDRAM_nRAS = sd_cmd[2]; +assign SDRAM_nCAS = sd_cmd[1]; +assign SDRAM_nWE = sd_cmd[0]; + +reg [24:1] addr_latch[3]; +reg [24:1] addr_latch_next[2]; +reg [21:1] addr_last[1:5]; +reg [21:2] addr_last2[5]; +reg [15:0] din_next; +reg [15:0] din_latch[2]; +reg oe_next; +reg [1:0] oe_latch; +reg we_next; +reg [1:0] we_latch; +reg [1:0] ds_next; +reg [1:0] ds[2]; + +reg port1_state; +reg port2_state; +reg cpu1_ram_req_state; + +localparam PORT_NONE = 3'd0; +localparam PORT_CPU1_ROM = 3'd1; +localparam PORT_CPU1_RAM = 3'd2; +localparam PORT_CPU2 = 3'd3; +localparam PORT_CPU3 = 3'd4; +localparam PORT_CPU4 = 3'd5; +localparam PORT_GFX1 = 3'd1; +localparam PORT_GFX2 = 3'd2; +localparam PORT_GFX3 = 3'd3; +localparam PORT_SP = 3'd4; +localparam PORT_REQ = 3'd6; + +reg [2:0] next_port[2]; +reg [2:0] port[2]; + +reg refresh; +reg [10:0] refresh_cnt; +wire need_refresh = (refresh_cnt >= RFRSH_CYCLES); + +// PORT1: bank 0,1 +always @(*) begin + next_port[0] = PORT_NONE; + addr_latch_next[0] = addr_latch[0]; + ds_next = 2'b00; + { oe_next, we_next } = 2'b00; + din_next = 0; + + if (refresh) begin + // nothing + end else if (port1_req ^ port1_state) begin + next_port[0] = PORT_REQ; + addr_latch_next[0] = { 1'b0, port1_a }; + ds_next = port1_ds; + { oe_next, we_next } = { ~port1_we, port1_we }; + din_next = port1_d; + end else if (/*cpu1_rom_addr != addr_last[PORT_CPU1_ROM] &&*/ cpu1_rom_cs && !cpu1_rom_valid) begin + next_port[0] = PORT_CPU1_ROM; + addr_latch_next[0] = { 3'd0, cpu1_rom_addr }; + ds_next = 2'b11; + { oe_next, we_next } = 2'b10; + end else if (cpu1_ram_req ^ cpu1_ram_req_state) begin + next_port[0] = PORT_CPU1_RAM; + addr_latch_next[0] = { 2'b01, 1'b1, cpu1_ram_addr }; + ds_next = cpu1_ram_ds; + { oe_next, we_next } = { ~cpu1_ram_we, cpu1_ram_we }; + din_next = cpu1_ram_d; + end else if (cpu2_addr != addr_last[PORT_CPU2] && cpu2_rom_cs) begin + next_port[0] = PORT_CPU2; + addr_latch_next[0] = { 3'd0, cpu2_addr }; + ds_next = 2'b11; + { oe_next, we_next } = 2'b10; + end else if (cpu3_addr != addr_last[PORT_CPU3] && cpu3_rom_cs) begin + next_port[0] = PORT_CPU3; + addr_latch_next[0] = { 3'd0, cpu3_addr }; + ds_next = 2'b11; + { oe_next, we_next } = 2'b10; + end else if (cpu4_addr != addr_last[PORT_CPU4] && cpu4_rom_cs) begin + next_port[0] = PORT_CPU4; + addr_latch_next[0] = { 3'd0, cpu4_addr }; + ds_next = 2'b11; + { oe_next, we_next } = 2'b10; + end +end + +// PORT1: bank 2,3 +always @(*) begin + if (port2_req ^ port2_state) begin + next_port[1] = PORT_REQ; + addr_latch_next[1] = { 1'b1, port2_a }; + end else if (gfx1_addr != addr_last2[PORT_GFX1]) begin + next_port[1] = PORT_GFX1; + addr_latch_next[1] = { 1'b1, 2'd0, gfx1_addr, 1'b0 }; + end else if (gfx2_addr != addr_last2[PORT_GFX2]) begin + next_port[1] = PORT_GFX2; + addr_latch_next[1] = { 1'b1, 2'd0, gfx2_addr, 1'b0 }; + end else if (gfx3_addr != addr_last2[PORT_GFX3]) begin + next_port[1] = PORT_GFX3; + addr_latch_next[1] = { 1'b1, 2'd0, gfx3_addr, 1'b0 }; + end else if (sp_req ^ sp_ack) begin + next_port[1] = PORT_SP; + addr_latch_next[1] = { 1'b1, 2'd0, sp_addr, 1'b0 }; + end else begin + next_port[1] = PORT_NONE; + addr_latch_next[1] = addr_latch[1]; + end +end + +always @(posedge clk) begin + + // permanently latch ram data to reduce delays + sd_din <= SDRAM_DQ; + SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ; + { SDRAM_DQMH, SDRAM_DQML } <= 2'b11; + sd_cmd <= CMD_NOP; // default: idle + refresh_cnt <= refresh_cnt + 1'd1; + + if(init) begin + { cpu1_rom_valid, cpu2_valid, cpu3_valid, cpu4_valid } <= 0; + // initialization takes place at the end of the reset phase + if(t == STATE_RAS0) begin + + if(reset == 15) begin + sd_cmd <= CMD_PRECHARGE; + SDRAM_A[10] <= 1'b1; // precharge all banks + end + + if(reset == 10 || reset == 8) begin + sd_cmd <= CMD_AUTO_REFRESH; + end + + if(reset == 2) begin + sd_cmd <= CMD_LOAD_MODE; + SDRAM_A <= MODE; + SDRAM_BA <= 2'b00; + end + end + end else begin + if (!cpu1_rom_cs) cpu1_rom_valid <= 0; + if (cpu2_addr != addr_last[PORT_CPU2] && cpu2_rom_cs) cpu2_valid <= 0; + if (cpu3_addr != addr_last[PORT_CPU3] && cpu3_rom_cs) cpu3_valid <= 0; + if (cpu4_addr != addr_last[PORT_CPU4] && cpu4_rom_cs) cpu4_valid <= 0; + + // RAS phase + // bank 0,1 + if(t == STATE_RAS0) begin + addr_latch[0] <= addr_latch_next[0]; + port[0] <= next_port[0]; + { oe_latch[0], we_latch[0] } <= 2'b00; + + if (next_port[0] != PORT_NONE) begin + sd_cmd <= CMD_ACTIVE; + SDRAM_A <= addr_latch_next[0][22:10]; + SDRAM_BA <= addr_latch_next[0][24:23]; + end + addr_last[next_port[0]] <= addr_latch_next[0][21:1]; + ds[0] <= ds_next; + { oe_latch[0], we_latch[0] } <= { oe_next, we_next }; + din_latch[0] <= din_next; + + if (next_port[0] == PORT_REQ) port1_state <= port1_req; + if (next_port[0] == PORT_CPU1_RAM) cpu1_ram_req_state <= cpu1_ram_req; + end + + // bank 2,3 + if(t == STATE_RAS1) begin + refresh <= 1'b0; + addr_latch[1] <= addr_latch_next[1]; + { oe_latch[1], we_latch[1] } <= 2'b00; + port[1] <= next_port[1]; + + if (next_port[1] != PORT_NONE) begin + sd_cmd <= CMD_ACTIVE; + SDRAM_A <= addr_latch_next[1][22:10]; + SDRAM_BA <= addr_latch_next[1][24:23]; + addr_last2[next_port[1]] <= addr_latch_next[1][21:2]; + if (next_port[1] == PORT_REQ) begin + { oe_latch[1], we_latch[1] } <= { ~port1_we, port1_we }; + ds[1] <= port2_ds; + din_latch[1] <= port2_d; + port2_state <= port2_req; + end else begin + { oe_latch[1], we_latch[1] } <= 2'b10; + ds[1] <= 2'b11; + end + end + + if (next_port[1] == PORT_NONE && need_refresh && !we_latch[0] && !oe_latch[0]) begin + refresh <= 1'b1; + refresh_cnt <= 0; + sd_cmd <= CMD_AUTO_REFRESH; + end + end + + // CAS phase + if(t == STATE_CAS0 && (we_latch[0] || oe_latch[0])) begin + sd_cmd <= we_latch[0]?CMD_WRITE:CMD_READ; + { SDRAM_DQMH, SDRAM_DQML } <= ~ds[0]; + if (we_latch[0]) begin + SDRAM_DQ <= din_latch[0]; + case(port[0]) + PORT_REQ: port1_ack <= port1_req; + PORT_CPU1_RAM: cpu1_ram_ack <= cpu1_ram_req; + default: ; + endcase; + end + SDRAM_A <= { 4'b0010, addr_latch[0][9:1] }; // auto precharge + SDRAM_BA <= addr_latch[0][24:23]; + end + + if(t == STATE_CAS1 && (we_latch[1] || oe_latch[1])) begin + sd_cmd <= we_latch[1]?CMD_WRITE:CMD_READ; + { SDRAM_DQMH, SDRAM_DQML } <= ~ds[1]; + if (we_latch[1]) begin + SDRAM_DQ <= din_latch[1]; + port2_ack <= port2_req; + end + SDRAM_A <= { 4'b0010, addr_latch[1][9:1] }; // auto precharge + SDRAM_BA <= addr_latch[1][24:23]; + end + + // Data returned + if(t == STATE_READ0 && oe_latch[0]) begin + case(port[0]) + PORT_REQ: begin port1_q <= sd_din; port1_ack <= port1_req; end + PORT_CPU1_ROM: begin cpu1_rom_q <= sd_din; cpu1_rom_valid <= 1; end + PORT_CPU1_RAM: begin cpu1_ram_q <= sd_din; cpu1_ram_ack <= cpu1_ram_req; end + PORT_CPU2: begin cpu2_q <= sd_din; cpu2_valid <= 1; end + PORT_CPU3: begin cpu3_q <= sd_din; cpu3_valid <= 1; end + PORT_CPU4: begin cpu4_q <= sd_din; cpu4_valid <= 1; end + default: ; + endcase; + end + + if(t == STATE_READ1 && oe_latch[1]) begin + case(port[1]) + PORT_REQ : port2_q[15:0] <= sd_din; + PORT_GFX1 : gfx1_q[15:0] <= sd_din; + PORT_GFX2 : gfx2_q[15:0] <= sd_din; + PORT_GFX3 : gfx3_q[15:0] <= sd_din; + PORT_SP : sp_q[15:0] <= sd_din; + default: ; + endcase; + end + + if(t == STATE_DS1b && oe_latch[1]) { SDRAM_DQMH, SDRAM_DQML } <= ~ds[1]; + + if(t == STATE_READ1b && oe_latch[1]) begin + case(port[1]) + PORT_REQ : begin port2_q[31:16] <= sd_din; port2_ack <= port2_req; end + PORT_GFX1 : begin gfx1_q[31:16] <= sd_din; end + PORT_GFX2 : begin gfx2_q[31:16] <= sd_din; end + PORT_GFX3 : begin gfx3_q[31:16] <= sd_din; end + PORT_SP : begin sp_q[31:16] <= sd_din; sp_ack <= sp_req; end + default: ; + endcase; + end + end +end + +endmodule diff --git a/Arcade_MiST/SNK M68000 Harware/SNK68/rtl/video_timing.v b/Arcade_MiST/SNK M68000 Harware/SNK68/rtl/video_timing.v new file mode 100644 index 00000000..f565fbb9 --- /dev/null +++ b/Arcade_MiST/SNK M68000 Harware/SNK68/rtl/video_timing.v @@ -0,0 +1,99 @@ + +module video_timing +( + input clk, + input clk_pix, + input reset, + + input refresh_mod, + + input signed [3:0] hs_offset, + input signed [3:0] vs_offset, + + input signed [3:0] hs_width, + input signed [3:0] vs_width, + + output [8:0] hc, + output [8:0] vc, + + output reg hsync, + output reg vsync, + + output reg hbl, + output reg vbl +); + +wire [8:0] h_ofs = 0; +wire [8:0] HBL_START = 266; +wire [8:0] HBL_END = 10; +wire [8:0] HS_START = HBL_START + 16 + $signed(hs_offset); +wire [8:0] HS_END = HBL_START + 48 + $signed(hs_offset) + $signed(hs_width); +wire [8:0] HTOTAL = 383; + +wire [8:0] v_ofs = 0; +wire [8:0] VBL_START = 240; +wire [8:0] VBL_END = 16; +wire [8:0] VS_START = VBL_START + ( refresh_mod ? 20 : 10 ) + $signed(vs_offset); +wire [8:0] VS_END = VBL_START + ( refresh_mod ? 24 : 13 )+ $signed(vs_offset) + $signed(vs_width); +wire [8:0] VTOTAL = 288 - ( refresh_mod ? 0 : 25 ); + +reg [8:0] v; +reg [8:0] h; + +assign vc = v - v_ofs; +assign hc = h - h_ofs; + +always @ (posedge clk) begin + if (reset) begin + h <= 0; + v <= 0; + + hbl <= 0; + vbl <= 0; + + hsync <= 0; + vsync <= 0; + end else if ( clk_pix == 1 ) begin + // counter + if (h == HTOTAL) begin + h <= 0; + v <= v + 1'd1; + + if ( v == VTOTAL ) begin + v <= 0; + end + end else begin + h <= h + 1'd1; + end + + // h signals + if ( h == HBL_START ) begin + hbl <= 1; + end else if ( h == HBL_END ) begin + hbl <= 0; + end + + // v signals + if ( v == VBL_START ) begin + vbl <= 1; + end else if ( v == VBL_END ) begin + vbl <= 0; + end + + if ( v == (VS_START ) ) begin + vsync <= 1; + end else if ( v == (VS_END ) ) begin + vsync <= 0; + end + + if ( h == (HS_START ) ) begin + hsync <= 1; + end else if ( h == (HS_END ) ) begin + hsync <= 0; + end + end + +end + +endmodule +