diff --git a/Arcade_MiST/Capcom SonSon Hardware/Sonson_MiST.qsf b/Arcade_MiST/Capcom SonSon Hardware/Sonson_MiST.qsf index d4b6aaf3..4d629619 100644 --- a/Arcade_MiST/Capcom SonSon Hardware/Sonson_MiST.qsf +++ b/Arcade_MiST/Capcom SonSon Hardware/Sonson_MiST.qsf @@ -40,7 +40,7 @@ # Project-Wide Assignments # ======================== set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.2 -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26" set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:48:06 MAY 24,2017" set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files @@ -245,13 +245,14 @@ set_global_assignment -name VHDL_FILE rtl/bitmapctl_e.vhd set_global_assignment -name VHDL_FILE rtl/tilemapctl_e.vhd set_global_assignment -name VHDL_FILE rtl/tilemapctl.vhd set_global_assignment -name VHDL_FILE rtl/sonson_soundboard.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/YM2149.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv set_global_assignment -name VERILOG_FILE rtl/pll.v set_global_assignment -name VHDL_FILE rtl/dprom_2r.vhd set_global_assignment -name VHDL_FILE rtl/dpram.vhd set_global_assignment -name VHDL_FILE rtl/sprom.vhd set_global_assignment -name VHDL_FILE rtl/spram.vhd +set_global_assignment -name VHDL_FILE ../../common/Sound/ym2149/YM2149.vhd +set_global_assignment -name VHDL_FILE ../../common/Sound/ym2149/vol_table_array.vhd set_global_assignment -name VERILOG_FILE ../../common/CPU/MC6809/mc6809i.v set_global_assignment -name QIP_FILE ../../common/mist/mist.qip set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Capcom SonSon Hardware/rtl/YM2149.sv b/Arcade_MiST/Capcom SonSon Hardware/rtl/YM2149.sv deleted file mode 100644 index eae73bb3..00000000 --- a/Arcade_MiST/Capcom SonSon Hardware/rtl/YM2149.sv +++ /dev/null @@ -1,329 +0,0 @@ -// -// Copyright (c) MikeJ - Jan 2005 -// Copyright (c) 2016-2018 Sorgelig -// -// All rights reserved -// -// Redistribution and use in source and synthezised forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// Redistributions in synthesized form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// -// Neither the name of the author nor the names of other contributors may -// be used to endorse or promote products derived from this software without -// specific prior written permission. -// -// THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. -// - - -// BDIR BC MODE -// 0 0 inactive -// 0 1 read value -// 1 0 write value -// 1 1 set address -// - -module YM2149 -( - input CLK, // Global clock - input CE, // PSG Clock enable - input RESET, // Chip RESET (set all Registers to '0', active hi) - input BDIR, // Bus Direction (0 - read , 1 - write) - input BC, // Bus control - input A8, - input A9_L, - input [7:0] DI, // Data In - output [7:0] DO, // Data Out - output [7:0] CHANNEL_A, // PSG Output channel A - output [7:0] CHANNEL_B, // PSG Output channel B - output [7:0] CHANNEL_C, // PSG Output channel C - - input SEL, - input MODE, - - output [5:0] ACTIVE, - - input [7:0] IOA_in, - output [7:0] IOA_out, - - input [7:0] IOB_in, - output [7:0] IOB_out -); - -assign ACTIVE = ~ymreg[7][5:0]; -assign IOA_out = ymreg[7][6] ? ymreg[14] : 8'hff; -assign IOB_out = ymreg[7][7] ? ymreg[15] : 8'hff; - -reg [7:0] addr; -reg [7:0] ymreg[16]; -wire cs = !A9_L & A8; - -// Write to PSG -reg env_reset; -always @(posedge CLK) begin - if(RESET) begin - ymreg <= '{default:0}; - ymreg[7] <= '1; - addr <= '0; - env_reset <= 0; - end else begin - env_reset <= 0; - if(cs & BDIR) begin - if(BC) addr <= DI; - else if(!addr[7:4]) begin - ymreg[addr[3:0]] <= DI; - env_reset <= (addr == 13); - end - end - end -end - -// Read from PSG -assign DO = dout; -reg [7:0] dout; -always_comb begin - dout = 8'hFF; - if(cs & ~BDIR & BC & !addr[7:4]) begin - case(addr[3:0]) - 0: dout = ymreg[0]; - 1: dout = ymreg[1][3:0]; - 2: dout = ymreg[2]; - 3: dout = ymreg[3][3:0]; - 4: dout = ymreg[4]; - 5: dout = ymreg[5][3:0]; - 6: dout = ymreg[6][4:0]; - 7: dout = ymreg[7]; - 8: dout = ymreg[8][4:0]; - 9: dout = ymreg[9][4:0]; - 10: dout = ymreg[10][4:0]; - 11: dout = ymreg[11]; - 12: dout = ymreg[12]; - 13: dout = ymreg[13][3:0]; - 14: dout = ymreg[7][6] ? ymreg[14] : IOA_in; - 15: dout = ymreg[7][7] ? ymreg[15] : IOB_in; - endcase - end -end - -reg ena_div; -reg ena_div_noise; - -// p_divider -always @(posedge CLK) begin - reg [3:0] cnt_div; - reg noise_div; - - if(CE) begin - ena_div <= 0; - ena_div_noise <= 0; - if(!cnt_div) begin - cnt_div <= {SEL, 3'b111}; - ena_div <= 1; - - noise_div <= (~noise_div); - if (noise_div) ena_div_noise <= 1; - end else begin - cnt_div <= cnt_div - 1'b1; - end - end -end - - -reg [2:0] noise_gen_op; - -// p_noise_gen -always @(posedge CLK) begin - reg [16:0] poly17; - reg [4:0] noise_gen_cnt; - - if(CE) begin - if (ena_div_noise) begin - if (!ymreg[6][4:0] || noise_gen_cnt >= ymreg[6][4:0] - 1'd1) begin - noise_gen_cnt <= 0; - poly17 <= {(poly17[0] ^ poly17[2] ^ !poly17), poly17[16:1]}; - end else begin - noise_gen_cnt <= noise_gen_cnt + 1'd1; - end - noise_gen_op <= {3{poly17[0]}}; - end - end -end - -wire [11:0] tone_gen_freq[1:3]; -assign tone_gen_freq[1] = {ymreg[1][3:0], ymreg[0]}; -assign tone_gen_freq[2] = {ymreg[3][3:0], ymreg[2]}; -assign tone_gen_freq[3] = {ymreg[5][3:0], ymreg[4]}; - -reg [3:1] tone_gen_op; - -//p_tone_gens -always @(posedge CLK) begin - integer i; - reg [11:0] tone_gen_cnt[1:3]; - - if(CE) begin - // looks like real chips count up - we need to get the Exact behaviour .. - - for (i = 1; i <= 3; i = i + 1) begin - if(ena_div) begin - if (tone_gen_freq[i]) begin - if (tone_gen_cnt[i] >= (tone_gen_freq[i] - 1'd1)) begin - tone_gen_cnt[i] <= 0; - tone_gen_op[i] <= ~tone_gen_op[i]; - end else begin - tone_gen_cnt[i] <= tone_gen_cnt[i] + 1'd1; - end - end else begin - tone_gen_op[i] <= ymreg[7][i]; - tone_gen_cnt[i] <= 0; - end - end - end - end -end - -reg env_ena; -wire [15:0] env_gen_comp = {ymreg[12], ymreg[11]} ? {ymreg[12], ymreg[11]} - 1'd1 : 16'd0; - -//p_envelope_freq -always @(posedge CLK) begin - reg [15:0] env_gen_cnt; - - if(CE) begin - env_ena <= 0; - if(ena_div) begin - if (env_gen_cnt >= env_gen_comp) begin - env_gen_cnt <= 0; - env_ena <= 1; - end else begin - env_gen_cnt <= (env_gen_cnt + 1'd1); - end - end - end -end - -reg [4:0] env_vol; - -wire is_bot = (env_vol == 5'b00000); -wire is_bot_p1 = (env_vol == 5'b00001); -wire is_top_m1 = (env_vol == 5'b11110); -wire is_top = (env_vol == 5'b11111); - -always @(posedge CLK) begin - reg env_hold; - reg env_inc; - - // envelope shapes - // C AtAlH - // 0 0 x x \___ - // - // 0 1 x x /___ - // - // 1 0 0 0 \\\\ - // - // 1 0 0 1 \___ - // - // 1 0 1 0 \/\/ - // ___ - // 1 0 1 1 \ - // - // 1 1 0 0 //// - // ___ - // 1 1 0 1 / - // - // 1 1 1 0 /\/\ - // - // 1 1 1 1 /___ - - if(env_reset | RESET) begin - // load initial state - if(!ymreg[13][2]) begin // attack - env_vol <= 5'b11111; - env_inc <= 0; // -1 - end else begin - env_vol <= 5'b00000; - env_inc <= 1; // +1 - end - env_hold <= 0; - end - else if(CE) begin - if (env_ena) begin - if (!env_hold) begin - if (env_inc) env_vol <= (env_vol + 5'b00001); - else env_vol <= (env_vol + 5'b11111); - end - - // envelope shape control. - if(!ymreg[13][3]) begin - if(!env_inc) begin // down - if(is_bot_p1) env_hold <= 1; - end else if (is_top) env_hold <= 1; - end else if(ymreg[13][0]) begin // hold = 1 - if(!env_inc) begin // down - if(ymreg[13][1]) begin // alt - if(is_bot) env_hold <= 1; - end else if(is_bot_p1) env_hold <= 1; - end else if(ymreg[13][1]) begin // alt - if(is_top) env_hold <= 1; - end else if(is_top_m1) env_hold <= 1; - end else if(ymreg[13][1]) begin // alternate - if(env_inc == 1'b0) begin // down - if(is_bot_p1) env_hold <= 1; - if(is_bot) begin - env_hold <= 0; - env_inc <= 1; - end - end else begin - if(is_top_m1) env_hold <= 1; - if(is_top) begin - env_hold <= 0; - env_inc <= 0; - end - end - end - end - end -end - -reg [5:0] A,B,C; -always @(posedge CLK) begin - A <= {MODE, ~((ymreg[7][0] | tone_gen_op[1]) & (ymreg[7][3] | noise_gen_op[0])) ? 5'd0 : ymreg[8][4] ? env_vol[4:0] : { ymreg[8][3:0], ymreg[8][3]}}; - B <= {MODE, ~((ymreg[7][1] | tone_gen_op[2]) & (ymreg[7][4] | noise_gen_op[1])) ? 5'd0 : ymreg[9][4] ? env_vol[4:0] : { ymreg[9][3:0], ymreg[9][3]}}; - C <= {MODE, ~((ymreg[7][2] | tone_gen_op[3]) & (ymreg[7][5] | noise_gen_op[2])) ? 5'd0 : ymreg[10][4] ? env_vol[4:0] : {ymreg[10][3:0], ymreg[10][3]}}; -end - -wire [7:0] volTable[64] = '{ - //YM2149 - 8'h00, 8'h01, 8'h01, 8'h02, 8'h02, 8'h03, 8'h03, 8'h04, - 8'h06, 8'h07, 8'h09, 8'h0a, 8'h0c, 8'h0e, 8'h11, 8'h13, - 8'h17, 8'h1b, 8'h20, 8'h25, 8'h2c, 8'h35, 8'h3e, 8'h47, - 8'h54, 8'h66, 8'h77, 8'h88, 8'ha1, 8'hc0, 8'he0, 8'hff, - - //AY8910 - 8'h00, 8'h00, 8'h03, 8'h03, 8'h04, 8'h04, 8'h06, 8'h06, - 8'h0a, 8'h0a, 8'h0f, 8'h0f, 8'h15, 8'h15, 8'h22, 8'h22, - 8'h28, 8'h28, 8'h41, 8'h41, 8'h5b, 8'h5b, 8'h72, 8'h72, - 8'h90, 8'h90, 8'hb5, 8'hb5, 8'hd7, 8'hd7, 8'hff, 8'hff -}; - -assign CHANNEL_A = volTable[A]; -assign CHANNEL_B = volTable[B]; -assign CHANNEL_C = volTable[C]; - -endmodule diff --git a/Arcade_MiST/Capcom SonSon Hardware/rtl/sonson_soundboard.vhd b/Arcade_MiST/Capcom SonSon Hardware/rtl/sonson_soundboard.vhd index 7a3e017f..ccc7b654 100644 --- a/Arcade_MiST/Capcom SonSon Hardware/rtl/sonson_soundboard.vhd +++ b/Arcade_MiST/Capcom SonSon Hardware/rtl/sonson_soundboard.vhd @@ -23,34 +23,6 @@ end sonson_soundboard; architecture SYN of sonson_soundboard is - component YM2149 - port ( - CLK : in std_logic; - CE : in std_logic; - RESET : in std_logic; - A8 : in std_logic := '1'; - A9_L : in std_logic := '0'; - BDIR : in std_logic; -- Bus Direction (0 - read , 1 - write) - BC : in std_logic; -- Bus control - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - CHANNEL_A : out std_logic_vector(7 downto 0); - CHANNEL_B : out std_logic_vector(7 downto 0); - CHANNEL_C : out std_logic_vector(7 downto 0); - - SEL : in std_logic; - MODE : in std_logic; - - ACTIVE : out std_logic_vector(5 downto 0); - - IOA_in : in std_logic_vector(7 downto 0); - IOA_out : out std_logic_vector(7 downto 0); - - IOB_in : in std_logic_vector(7 downto 0); - IOB_out : out std_logic_vector(7 downto 0) - ); - end component; - COMPONENT mc6809i GENERIC ( ILLEGAL_INSTRUCTIONS : STRING := "GHOST" ); PORT @@ -201,62 +173,42 @@ begin q => wram_do ); - ay83910_inst1: YM2149 + ay83910_inst1: work.YM2149 port map ( CLK => clk, - CE => clk_en_snd, - RESET => reset, - A8 => '1', - A9_L => not ay1_cs, - BDIR => not cpu_rw, - BC => not cpu_addr(0) or cpu_rw, - DI => cpu_do, - DO => ay1_do, - CHANNEL_A => ay1_chan_a, - CHANNEL_B => ay1_chan_b, - CHANNEL_C => ay1_chan_c, + ENA => clk_en_snd, + RESET_L => not reset, + I_A8 => '1', + I_A9_L => not ay1_cs, + I_BDIR => not cpu_rw, + I_BC1 => not cpu_addr(0) or cpu_rw, + I_DA => cpu_do, + O_DA => ay1_do, - SEL => '0', - MODE => '1', + O_AUDIO_L => audio_out_l, - ACTIVE => open, + I_IOA => (others => '0'), - IOA_in => (others => '0'), - IOA_out => open, - - IOB_in => (others => '0'), - IOB_out => open + I_IOB => (others => '0') ); - audio_out_l <= "0000000000" + ay1_chan_a + ay1_chan_b + ay1_chan_c; - - ay83910_inst2: YM2149 + ay83910_inst2: work.YM2149 port map ( CLK => clk, - CE => clk_en_snd, - RESET => reset, - A8 => '1', - A9_L => not ay2_cs, - BDIR => not cpu_rw, - BC => not cpu_addr(0) or cpu_rw, - DI => cpu_do, - DO => ay2_do, - CHANNEL_A => ay2_chan_a, - CHANNEL_B => ay2_chan_b, - CHANNEL_C => ay2_chan_c, + ENA => clk_en_snd, + RESET_L => not reset, + I_A8 => '1', + I_A9_L => not ay2_cs, + I_BDIR => not cpu_rw, + I_BC1 => not cpu_addr(0) or cpu_rw, + I_DA => cpu_do, + O_DA => ay2_do, - SEL => '0', - MODE => '1', + O_AUDIO_L => audio_out_r, - ACTIVE => open, + I_IOA => (others => '0'), - IOA_in => (others => '0'), - IOA_out => open, - - IOB_in => (others => '0'), - IOB_out => open + I_IOB => (others => '0') ); - audio_out_r <= "0000000000" + ay2_chan_a + ay2_chan_b + ay2_chan_c; - end SYN; \ No newline at end of file