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Atari Tetris: use common Pokey

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This commit is contained in:
Gyorgy Szombathelyi 2021-04-05 22:09:44 +02:00
parent df2ed06631
commit 4f2b6f7595
29 changed files with 10 additions and 2178 deletions
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4
Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/Centipede.qsf
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@ -156,8 +156,8 @@ set_global_assignment -name VHDL_FILE rtl/spram.vhd
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
set_global_assignment -name VHDL_FILE rtl/pll.vhd
set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
set_global_assignment -name SYSTEMVERILOG_FILE ../../../common/Sound/Pokey/POKEY.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../../common/Sound/Pokey/matoro.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/POKEY.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/matoro.sv
set_global_assignment -name QIP_FILE ../../../common/CPU/T65/T65.qip
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/cent.stp

0
common/Sound/Pokey/POKEY.sv → Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/POKEY.sv
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0
common/Sound/Pokey/matoro.sv → Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/matoro.sv
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13
Arcade_MiST/Atari Tetris/Tetris.qsf
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@ -218,23 +218,12 @@ set_global_assignment -name USE_SIGNALTAP_FILE output_files/tet.stp
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Tetris_MiST.sv
set_global_assignment -name VERILOG_FILE rtl/FPGA_ATetris.v
set_global_assignment -name VERILOG_FILE rtl/ATARI_SLAPSTIK1.v
set_global_assignment -name VHDL_FILE rtl/Pokey/syncreset_enable_divider.vhd
set_global_assignment -name VHDL_FILE rtl/Pokey/synchronizer.vhdl
set_global_assignment -name VHDL_FILE rtl/Pokey/pokey_poly_17_9.vhdl
set_global_assignment -name VHDL_FILE rtl/Pokey/pokey_poly_5.vhdl
set_global_assignment -name VHDL_FILE rtl/Pokey/pokey_poly_4.vhdl
set_global_assignment -name VHDL_FILE rtl/Pokey/pokey_noise_filter.vhdl
set_global_assignment -name VHDL_FILE rtl/Pokey/pokey_keyboard_scanner.vhdl
set_global_assignment -name VHDL_FILE rtl/Pokey/pokey_countdown_timer.vhdl
set_global_assignment -name VHDL_FILE rtl/Pokey/pokey.vhdl
set_global_assignment -name VHDL_FILE rtl/Pokey/latch_delay_line.vhdl
set_global_assignment -name VHDL_FILE rtl/Pokey/delay_line.vhdl
set_global_assignment -name VHDL_FILE rtl/Pokey/complete_address_decoder.vhdl
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
set_global_assignment -name VERILOG_FILE rtl/hvgen.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name VHDL_FILE rtl/pll_mist.vhd
set_global_assignment -name VHDL_FILE rtl/spram.vhd
set_global_assignment -name QIP_FILE ../../common/Sound/Pokey/Pokey.qip
set_global_assignment -name QIP_FILE ../../common/CPU/T65/T65.qip
set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
set_global_assignment -name SIGNALTAP_FILE output_files/tet.stp

81
Arcade_MiST/Atari Tetris/rtl/Pokey/syncreset_enable_divider.vhd
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@ -1,81 +0,0 @@
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY syncreset_enable_divider IS
generic(COUNT : natural := 1; RESETCOUNT : natural := 0);
PORT
(
CLK : IN STD_LOGIC;
SYNCRESET : in std_logic;
RESET_N : IN STD_LOGIC;
ENABLE_IN : IN STD_LOGIC;
ENABLE_OUT : OUT STD_LOGIC
);
END syncreset_enable_divider;
ARCHITECTURE vhdl OF syncreset_enable_divider IS
function log2c(n : integer) return integer is
variable m,p : integer;
begin
m := 0;
p := 1;
while p<n loop
m:=m+1;
p:=p*2;
end loop;
return m;
end log2c;
constant WIDTH : natural := log2c(COUNT);
signal count_reg : std_logic_vector(WIDTH-1 downto 0); -- width should depend on count
signal count_next : std_logic_vector(WIDTH-1 downto 0);
signal enabled_out_next : std_logic;
signal enabled_out_reg : std_logic;
BEGIN
-- register
process(clk,reset_n)
begin
if (reset_n = '0') then
count_reg <= (others=>'0');
enabled_out_reg <= '0';
elsif (clk'event and clk='1') then
count_reg <= count_next;
enabled_out_reg <= enabled_out_next;
end if;
end process;
-- Maintain a count in order to calculate a clock circa 1.79 (in this case 25/14) -> 64KHz -> /28
process(count_reg,enable_in,enabled_out_reg,syncreset)
begin
count_next <= count_reg;
enabled_out_next <= enabled_out_reg;
if (enable_in = '1') then
count_next <= std_logic_vector(unsigned(count_reg) + 1);
enabled_out_next <= '0';
if (unsigned(count_reg) = to_unsigned(COUNT-1,WIDTH)) then
count_next <= std_logic_vector(to_unsigned(0,WIDTH));
enabled_out_next <= '1';
end if;
end if;
if (syncreset='1') then
count_next <= std_logic_vector(to_unsigned(resetcount,width));
end if;
end process;
-- output
enable_out <= enabled_out_reg and enable_in;
END vhdl;

52
common/Sound/Pokey MrX/complete_address_decoder.vhdl
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@ -1,52 +0,0 @@
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY complete_address_decoder IS
generic (width : natural := 1);
PORT
(
addr_in : in std_logic_vector(width-1 downto 0);
addr_decoded : out std_logic_vector((2**width)-1 downto 0)
);
END complete_address_decoder;
--ARCHITECTURE vhdl OF complete_address_decoder IS
--BEGIN
-- comp_gen:
-- for i in 0 to ((2**width)-1) generate
-- addr_decoded(i) <= '1' when i=to_integer(unsigned(addr_in)) else '0';
-- end generate;
--end vhdl;
architecture tree of complete_address_decoder is
constant STAGE : natural:=width;
type std_logic_2d is array (natural range <>,natural range <>) of std_logic;
signal p: std_logic_2d(stage downto 0,2**stage-1 downto 0);
signal a: std_logic_vector(width-1 downto 0) ;
begin
a<=addr_in;
process(a,p)
begin
p(stage,0) <= '1';
for s in stage downto 1 loop
for r in 0 to (2**(stage-s)-1) loop
p(s-1,2*r) <= (not a(s-1)) and p(s,r);
p(s-1,2*r+1) <= a(s-1) and p(s,r);
end loop;
end loop;
for i in 0 to (2**stage-1) loop
addr_decoded(i) <= p(0,i);
end loop;
end process;
end tree;

57
common/Sound/Pokey MrX/delay_line.vhdl
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@ -1,57 +0,0 @@
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY delay_line IS
generic(COUNT : natural := 1);
PORT
(
CLK : IN STD_LOGIC;
SYNC_RESET : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC;
ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
RESET_N : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC
);
END delay_line;
ARCHITECTURE vhdl OF delay_line IS
signal shift_reg : std_logic_vector(COUNT-1 downto 0);
signal shift_next : std_logic_vector(COUNT-1 downto 0);
BEGIN
-- register
process(clk,reset_n)
begin
if (reset_N = '0') then
shift_reg <= (others=>'0');
elsif (clk'event and clk='1') then
shift_reg <= shift_next;
end if;
end process;
-- shift on enable
process(shift_reg,enable,data_in,sync_reset)
begin
shift_next <= shift_reg;
if (enable = '1') then
shift_next <= data_in&shift_reg(COUNT-1 downto 1);
end if;
if (sync_reset = '1') then
shift_next <= (others=>'0');
end if;
end process;
-- output
data_out <= shift_reg(0) and enable;
END vhdl;

66
common/Sound/Pokey MrX/latch_delay_line.vhdl
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@ -1,66 +0,0 @@
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY latch_delay_line IS
generic(COUNT : natural := 1);
PORT
(
CLK : IN STD_LOGIC;
SYNC_RESET : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC;
ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
RESET_N : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC
);
END latch_delay_line;
ARCHITECTURE vhdl OF latch_delay_line IS
signal shift_reg : std_logic_vector(COUNT-1 downto 0);
signal shift_next : std_logic_vector(COUNT-1 downto 0);
signal data_in_reg : std_logic;
signal data_in_next : std_logic;
BEGIN
-- register
process(clk,reset_n)
begin
if (reset_N = '0') then
shift_reg <= (others=>'0');
data_in_reg <= '0';
elsif (clk'event and clk='1') then
shift_reg <= shift_next;
data_in_reg <= data_in_next;
end if;
end process;
-- shift on enable
process(shift_reg,enable,data_in,data_in_reg,sync_reset)
begin
shift_next <= shift_reg;
data_in_next <= data_in or data_in_reg;
if (enable = '1') then
shift_next <= (data_in or data_in_reg)&shift_reg(COUNT-1 downto 1);
data_in_next <= '0';
end if;
if (sync_reset = '1') then
shift_next <= (others=>'0');
data_in_next <= '0';
end if;
end process;
-- output
data_out <= shift_reg(0) and enable;
END vhdl;

1307
common/Sound/Pokey MrX/pokey.vhdl
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102
common/Sound/Pokey MrX/pokey_countdown_timer.vhdl
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@ -1,102 +0,0 @@
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY pokey_countdown_timer IS
generic(UNDERFLOW_DELAY : natural := 3);
PORT
(
CLK : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
ENABLE_UNDERFLOW : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
DATA_OUT : OUT STD_LOGIC
);
END pokey_countdown_timer;
ARCHITECTURE vhdl OF pokey_countdown_timer IS
component delay_line IS
generic(COUNT : natural := 1);
PORT
(
CLK : IN STD_LOGIC;
SYNC_RESET : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC
);
END component;
function To_Std_Logic(L: BOOLEAN) return std_ulogic is
begin
if L then
return('1');
else
return('0');
end if;
end function To_Std_Logic;
signal count_reg : std_logic_vector(7 downto 0);
signal count_next: std_logic_vector(7 downto 0);
signal underflow : std_logic;
signal count_command : std_logic_vector(1 downto 0);
signal underflow_command: std_logic_vector(1 downto 0);
BEGIN
-- Instantiate delay (provides output)
underflow0_delay : delay_line
generic map (COUNT=>UNDERFLOW_DELAY)
port map(clk=>clk,sync_reset=>wr_en,data_in=>underflow,enable=>ENABLE_UNDERFLOW,reset_n=>reset_n,data_out=>data_out);
-- register
process(clk,reset_n)
begin
if (reset_N = '0') then
count_reg <= (others=>'0');
elsif (clk'event and clk='1') then
count_reg <= count_next;
end if;
end process;
-- count down on enable
process(count_reg,enable,wr_en,count_command,data_in)
begin
count_command <= enable&wr_en;
case count_command is
when "10" =>
count_next <= std_logic_vector(unsigned(count_reg) -1);
when "01"|"11" =>
count_next <= data_in;
when others =>
count_next <= count_reg;
end case;
end process;
-- underflow
process(count_reg,enable,underflow_command)
begin
underflow_command <= enable & To_Std_Logic(count_reg = X"00");
case underflow_command is
when "11" =>
underflow <= '1';
when others =>
underflow <= '0';
end case;
end process;
END vhdl;

202
common/Sound/Pokey MrX/pokey_keyboard_scanner.vhdl
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@ -1,202 +0,0 @@
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pokey_keyboard_scanner is
port
(
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic; -- typically hsync or equiv timing
keyboard_response : in std_logic_vector(1 downto 0);
debounce_disable : in std_logic;
scan_enable : in std_logic;
keyboard_scan : out std_logic_vector(5 downto 0);
key_held : out std_logic;
shift_held : out std_logic;
keycode : out std_logic_vector(7 downto 0);
other_key_irq : out std_logic;
break_irq : out std_logic
);
end pokey_keyboard_scanner;
architecture vhdl of pokey_keyboard_scanner is
signal bincnt_next : std_logic_vector(5 downto 0);
signal bincnt_reg : std_logic_vector(5 downto 0);
signal break_pressed_next : std_logic;
signal break_pressed_reg : std_logic;
signal shift_pressed_next : std_logic;
signal shift_pressed_reg : std_logic;
signal control_pressed_next : std_logic;
signal control_pressed_reg : std_logic;
signal compare_latch_next : std_logic_vector(5 downto 0);
signal compare_latch_reg : std_logic_vector(5 downto 0);
signal keycode_latch_next : std_logic_vector(7 downto 0);
signal keycode_latch_reg : std_logic_vector(7 downto 0);
signal irq_next : std_logic;
signal irq_reg : std_logic;
signal break_irq_next : std_logic;
signal break_irq_reg : std_logic;
signal key_held_next : std_logic;
signal key_held_reg : std_logic;
signal my_key : std_logic;
signal state_next : std_logic_vector(1 downto 0);
signal state_reg : std_logic_vector(1 downto 0);
constant state_wait_key : std_logic_vector(1 downto 0) := "00";
constant state_key_bounce : std_logic_vector(1 downto 0) := "01";
constant state_valid_key : std_logic_vector(1 downto 0) := "10";
constant state_key_debounce : std_logic_vector(1 downto 0) := "11";
begin
-- register
process(clk,reset_n)
begin
if (reset_n = '0') then
bincnt_reg <= (others=>'0');
break_pressed_reg <= '0';
shift_pressed_reg <= '0';
control_pressed_reg <= '0';
compare_latch_reg <= (others=>'0');
keycode_latch_reg <= (others=>'1');
key_held_reg <= '0';
state_reg <= state_wait_key;
irq_reg <= '0';
break_irq_reg <= '0';
elsif (clk'event and clk = '1') then
bincnt_reg <= bincnt_next;
state_reg <= state_next;
break_pressed_reg <= break_pressed_next;
shift_pressed_reg <= shift_pressed_next;
control_pressed_reg <= control_pressed_next;
compare_latch_reg <= compare_latch_next;
keycode_latch_reg <= keycode_latch_next;
key_held_reg <= key_held_next;
state_reg <= state_next;
irq_reg <= irq_next;
break_irq_reg <= break_irq_next;
end if;
end process;
process (enable, keyboard_response, scan_enable, key_held_reg, my_key, state_reg,bincnt_reg, compare_latch_reg, break_pressed_next, break_pressed_reg, shift_pressed_reg, break_irq_reg, control_pressed_reg, keycode_latch_reg, debounce_disable)
begin
bincnt_next <= bincnt_reg;
state_next <= state_reg;
compare_latch_next <= compare_latch_reg;
irq_next <= '0';
break_irq_next <= '0';
break_pressed_next <= break_pressed_reg;
shift_pressed_next <= shift_pressed_reg;
control_pressed_next <= control_pressed_reg;
keycode_latch_next <= keycode_latch_reg;
key_held_next <= key_held_reg;
my_key <= '0';
if (bincnt_reg = compare_latch_reg or debounce_disable='1') then
my_key <= '1';
end if;
if (enable = '1' and scan_enable='1') then
bincnt_next <= std_logic_vector(unsigned(bincnt_reg) + 1); -- check another key
key_held_next<= '0';
case state_reg is
when state_wait_key =>
if (keyboard_response(0) = '0') then -- detected key press
if (debounce_disable = '1') then
keycode_latch_next <= control_pressed_reg&shift_pressed_reg&bincnt_reg;
irq_next <= '1';
key_held_next<= '1';
else
state_next <= state_key_bounce;
compare_latch_next <= bincnt_reg;
end if;
end if;
when state_key_bounce =>
if (keyboard_response(0) = '0') then -- detected key press
if (my_key = '1') then -- same key
keycode_latch_next <= control_pressed_reg&shift_pressed_reg&compare_latch_reg;
irq_next <= '1';
key_held_next<= '1';
state_next <= state_valid_key;
else -- different key (multiple keys pressed)
state_next <= state_wait_key;
end if;
else -- key not pressed
if (my_key = '1') then -- same key, no longer pressed
state_next <= state_wait_key;
end if;
end if;
when state_valid_key =>
key_held_next<= '1';
if (my_key = '1') then -- only response to my key
if (keyboard_response(0) = '1') then -- no longer pressed
state_next <= state_key_debounce;
end if;
end if;
when state_key_debounce =>
key_held_next<= '1';
if (my_key = '1') then
if (keyboard_response(0) = '1') then -- no longer pressed
key_held_next<= '0';
state_next <= state_wait_key;
else
state_next <= state_valid_key;
end if;
end if;
when others=>
state_next <= state_wait_key;
end case;
if (bincnt_reg(3 downto 0) = "0000") then
case bincnt_reg(5 downto 4) is
when "11" =>
break_pressed_next <= not(keyboard_response(1)); --0x30
when "01" =>
shift_pressed_next <= not(keyboard_response(1)); --0x10
when "00" =>
control_pressed_next <= not(keyboard_response(1)); -- 0x00
when others =>
--
end case;
end if;
end if;
if (break_pressed_next='1' and break_pressed_reg='0') then
break_irq_next <= '1';
end if;
end process;
-- outputs
keyboard_scan <= not(bincnt_reg);
key_held <= key_held_reg;
shift_held <= shift_pressed_reg;
keycode <= keycode_latch_reg;
other_key_irq <= irq_reg;
break_irq <= break_irq_reg;
end vhdl;

79
common/Sound/Pokey MrX/pokey_noise_filter.vhdl
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@ -1,79 +0,0 @@
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY pokey_noise_filter IS
PORT
(
CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
NOISE_SELECT : IN STD_LOGIC_VECTOR(2 downto 0);
PULSE_IN : IN STD_LOGIC;
NOISE_4 : IN STD_LOGIC;
NOISE_5 : IN STD_LOGIC;
NOISE_LARGE : IN STD_LOGIC;
SYNC_RESET : IN STD_LOGIC;
PULSE_OUT : OUT STD_LOGIC
);
END pokey_noise_filter;
ARCHITECTURE vhdl OF pokey_noise_filter IS
-- signal pulse_noise_a : std_logic;
-- signal pulse_noise_b : std_logic;
signal audclk : std_logic;
signal out_next : std_logic;
signal out_reg : std_logic;
BEGIN
process(clk,reset_n)
begin
if (reset_n='0') then
out_reg <= '0';
elsif (clk'event and clk='1') then
out_reg <= out_next;
end if;
end process;
pulse_out <= out_reg;
process(pulse_in, noise_4, noise_5, noise_large, noise_select, audclk, out_reg, sync_reset)
begin
audclk <= pulse_in;
out_next <= out_reg;
if (NOISE_SELECT(2) = '0') then
audclk <= pulse_in and noise_5;
end if;
if (audclk = '1') then
if (NOISE_SELECT(0) = '1') then
-- toggle
out_next <= not(out_reg);
else
-- sample
if (NOISE_SELECT(1) = '1') then
out_next <= noise_4;
else
out_next <= noise_large;
end if;
end if;
end if;
if (sync_reset = '1') then
out_next <= '0';
end if;
end process;
end vhdl;

77
common/Sound/Pokey MrX/pokey_poly_17_9.vhdl
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@ -1,77 +0,0 @@
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY pokey_poly_17_9 IS
PORT
(
CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
SELECT_9_17 : IN STD_LOGIC; -- 9 high, 17 low
INIT : IN STD_LOGIC;
BIT_OUT : OUT STD_LOGIC;
RAND_OUT : OUT std_logic_vector(7 downto 0)
);
END pokey_poly_17_9;
ARCHITECTURE vhdl OF pokey_poly_17_9 IS
signal shift_reg: std_logic_vector(16 downto 0);
signal shift_next: std_logic_vector(16 downto 0);
signal cycle_delay_reg : std_logic;
signal cycle_delay_next : std_logic;
signal select_9_17_del_reg : std_logic;
signal select_9_17_del_next : std_logic;
signal feedback : std_logic;
BEGIN
-- register
process(clk,reset_n)
begin
if (reset_n = '0') then
shift_reg <= "01010101010101010";
cycle_delay_reg <= '0';
select_9_17_del_reg <= '0';
elsif (clk'event and clk='1') then
shift_reg <= shift_next;
cycle_delay_reg <= cycle_delay_next;
select_9_17_del_reg <= select_9_17_del_next;
end if;
end process;
-- next state (as pokey decap)
feedback <= shift_reg(13) xnor shift_reg(8);
process(enable,shift_reg,feedback,select_9_17,select_9_17_del_reg,init,cycle_delay_reg)
begin
shift_next <= shift_reg;
cycle_delay_next <= cycle_delay_reg;
select_9_17_del_next <= select_9_17_del_reg;
if (enable = '1') then
select_9_17_del_next <= select_9_17;
shift_next(15 downto 8) <= shift_reg(16 downto 9);
shift_next(7) <= feedback;
shift_next(6 downto 0) <= shift_reg(7 downto 1);
shift_next(16) <= ((feedback and select_9_17_del_reg) or (shift_reg(0) and not(select_9_17))) and not(init);
cycle_delay_next <= shift_reg(9);
end if;
end process;
-- output
bit_out <= cycle_delay_reg; -- from pokey schematics
RAND_OUT(7 downto 0) <= not(shift_reg(15 downto 8));
END vhdl;

50
common/Sound/Pokey MrX/pokey_poly_4.vhdl
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@ -1,50 +0,0 @@
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY pokey_poly_4 IS
PORT
(
CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
INIT : IN STD_LOGIC;
BIT_OUT : OUT STD_LOGIC
);
END pokey_poly_4;
ARCHITECTURE vhdl OF pokey_poly_4 IS
signal shift_reg: std_logic_vector(3 downto 0);
signal shift_next: std_logic_vector(3 downto 0);
BEGIN
-- register
process(clk, reset_n)
begin
if (reset_n = '0') then
shift_reg <= "1010";
elsif (clk'event and clk='1') then
shift_reg <= shift_next;
end if;
end process;
-- next state
process(shift_reg,enable,init)
begin
shift_next <= shift_reg;
if (enable = '1') then
shift_next <= ((shift_reg(1) xnor shift_reg(0)) and not(init))&shift_reg(3 downto 1);
end if;
end process;
-- output
bit_out <= shift_reg(0);
END vhdl;

50
common/Sound/Pokey MrX/pokey_poly_5.vhdl
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@ -1,50 +0,0 @@
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY pokey_poly_5 IS
PORT
(
CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
INIT : IN STD_LOGIC;
BIT_OUT : OUT STD_LOGIC
);
END pokey_poly_5;
ARCHITECTURE vhdl OF pokey_poly_5 IS
signal shift_reg: std_logic_vector(4 downto 0);
signal shift_next: std_logic_vector(4 downto 0);
BEGIN
-- register
process(clk,reset_n)
begin
if (reset_n = '0') then
shift_reg <= "01010";
elsif (clk'event and clk='1') then
shift_reg <= shift_next;
end if;
end process;
-- next state
process(shift_reg,enable,init)
begin
shift_next <= shift_reg;
if (enable = '1') then
shift_next <= ((shift_reg(2) xnor shift_reg(0)) and not(init))&shift_reg(4 downto 1);
end if;
end process;
-- output
bit_out <= shift_reg(0);
END vhdl;

39
common/Sound/Pokey MrX/synchronizer.vhdl
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@ -1,39 +0,0 @@
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY synchronizer IS
PORT
(
CLK : IN STD_LOGIC;
RAW : IN STD_LOGIC;
SYNC : OUT STD_LOGIC
);
END synchronizer;
ARCHITECTURE vhdl OF synchronizer IS
signal ff_next : std_logic_vector(2 downto 0);
signal ff_reg : std_logic_vector(2 downto 0);
begin
-- register
process(clk)
begin
if (clk'event and clk='1') then
ff_reg <= ff_next;
end if;
end process;
ff_next <= RAW&ff_reg(2 downto 1);
SYNC <= ff_reg(0);
end vhdl;

0
common/Sound/Pokey MrX/Pokey.qip → common/Sound/Pokey/Pokey.qip
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0
Arcade_MiST/Atari Tetris/rtl/Pokey/complete_address_decoder.vhdl → common/Sound/Pokey/complete_address_decoder.vhdl
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0
Arcade_MiST/Atari Tetris/rtl/Pokey/delay_line.vhdl → common/Sound/Pokey/delay_line.vhdl
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0
Arcade_MiST/Atari Tetris/rtl/Pokey/latch_delay_line.vhdl → common/Sound/Pokey/latch_delay_line.vhdl
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9
Arcade_MiST/Atari Tetris/rtl/Pokey/pokey.vhdl → common/Sound/Pokey/pokey.vhdl
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@ -367,6 +367,7 @@ ARCHITECTURE vhdl OF pokey IS
signal serout_enable : std_logic;
signal serout_enable_delayed : std_logic;
signal serin_enable : std_logic;
signal serin_enable_delayed : std_logic;
signal async_serial_reset : std_logic;
signal waiting_for_start_bit : std_logic;
@ -1000,6 +1001,10 @@ BEGIN
serout_clock_delay : delay_line
generic map (count=>2)
port map (clk=>clk, sync_reset=>serout_sync_reset,data_in=>serout_enable, enable=>enable_179, reset_n=>reset_n, data_out=>serout_enable_delayed);
serin_clock_delay : delay_line
generic map (count=>5)
port map (clk=>clk, sync_reset=>serout_sync_reset,data_in=>serin_enable, enable=>enable_179, reset_n=>reset_n, data_out=>serin_enable_delayed);
process(serout_enable_delayed, skctl_reg, serout_active_reg, serout_clock_last_reg,serout_clock_reg, serout_holding_load, serout_holding_reg, serout_holding_full_reg, serout_shift_reg, serout_bitcount_reg, serial_out_reg, twotone_reg, audf0_pulse, audf1_pulse, serial_reset)
@ -1089,7 +1094,7 @@ BEGIN
sio_in_next <= sio_in1_reg and sio_in2_reg and sio_in3_reg;
waiting_for_start_bit <= '1' when serin_bitcount_reg = X"9" else '0';
process(serin_enable,serin_clock_last_reg,serin_clock_reg, sio_in_reg, serin_reg,serin_shift_reg, serin_bitcount_reg, serial_ip_overrun_reg, serial_ip_framing_reg, skrest_write, irqst_reg, skctl_reg, waiting_for_start_bit, serial_reset)
process(serin_enable_delayed,serin_clock_last_reg,serin_clock_reg, sio_in_reg, serin_reg,serin_shift_reg, serin_bitcount_reg, serial_ip_overrun_reg, serial_ip_framing_reg, skrest_write, irqst_reg, skctl_reg, waiting_for_start_bit, serial_reset)
begin
serin_clock_next <= serin_clock_reg;
serin_clock_last_next <= serin_clock_reg;
@ -1105,7 +1110,7 @@ BEGIN
async_serial_reset <= '0';
-- generate clock from enable signals
if (serin_enable = '1') then
if (serin_enable_delayed = '1') then
serin_clock_next <= not(serin_clock_reg);
end if;

0
Arcade_MiST/Atari Tetris/rtl/Pokey/pokey_countdown_timer.vhdl → common/Sound/Pokey/pokey_countdown_timer.vhdl
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0
Arcade_MiST/Atari Tetris/rtl/Pokey/pokey_keyboard_scanner.vhdl → common/Sound/Pokey/pokey_keyboard_scanner.vhdl
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0
Arcade_MiST/Atari Tetris/rtl/Pokey/pokey_noise_filter.vhdl → common/Sound/Pokey/pokey_noise_filter.vhdl
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0
Arcade_MiST/Atari Tetris/rtl/Pokey/pokey_poly_17_9.vhdl → common/Sound/Pokey/pokey_poly_17_9.vhdl
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0
Arcade_MiST/Atari Tetris/rtl/Pokey/pokey_poly_4.vhdl → common/Sound/Pokey/pokey_poly_4.vhdl
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0
Arcade_MiST/Atari Tetris/rtl/Pokey/pokey_poly_5.vhdl → common/Sound/Pokey/pokey_poly_5.vhdl
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0
Arcade_MiST/Atari Tetris/rtl/Pokey/synchronizer.vhdl → common/Sound/Pokey/synchronizer.vhdl
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0
common/Sound/Pokey MrX/syncreset_enable_divider.vhdl → common/Sound/Pokey/syncreset_enable_divider.vhdl
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