From 5335ad87a9b18b4e06ce83c3aea2aa57d5161ae5 Mon Sep 17 00:00:00 2001 From: Marcel Date: Sat, 2 Jul 2022 09:15:53 +0200 Subject: [PATCH] Emerson Arcadia 2001 --- .../Arcadia_MiST.qpf | 30 + .../Arcadia_MiST.qsf | 209 +++ .../Arcadia_MiST.sdc | 42 + .../Emerson Arcadia 2001_MiST/Readme.md | 12 + .../Emerson Arcadia 2001_MiST/clean.bat | 15 + .../rtl/arcadia_core.vhd | 429 +++++++ .../rtl/arcadia_mist.sv | 174 +++ .../rtl/base_pack.vhd | 631 +++++++++ .../rtl/build_id.tcl | 35 + .../Emerson Arcadia 2001_MiST/rtl/pll.qip | 4 + .../Emerson Arcadia 2001_MiST/rtl/pll.vhd | 365 ++++++ .../Emerson Arcadia 2001_MiST/rtl/sgs2637.vhd | 778 +++++++++++ .../Emerson Arcadia 2001_MiST/rtl/sgs2650.vhd | 1133 +++++++++++++++++ .../rtl/sgs2650_pack.vhd | 598 +++++++++ .../Interton VC4000_MiST/VC4000_MiST.qsf | 36 +- 15 files changed, 4473 insertions(+), 18 deletions(-) create mode 100644 Console_MiST/Emerson Arcadia 2001_MiST/Arcadia_MiST.qpf create mode 100644 Console_MiST/Emerson Arcadia 2001_MiST/Arcadia_MiST.qsf create mode 100644 Console_MiST/Emerson Arcadia 2001_MiST/Arcadia_MiST.sdc create mode 100644 Console_MiST/Emerson Arcadia 2001_MiST/Readme.md create mode 100644 Console_MiST/Emerson Arcadia 2001_MiST/clean.bat create mode 100644 Console_MiST/Emerson Arcadia 2001_MiST/rtl/arcadia_core.vhd create mode 100644 Console_MiST/Emerson Arcadia 2001_MiST/rtl/arcadia_mist.sv create mode 100644 Console_MiST/Emerson Arcadia 2001_MiST/rtl/base_pack.vhd create mode 100644 Console_MiST/Emerson Arcadia 2001_MiST/rtl/build_id.tcl create mode 100644 Console_MiST/Emerson Arcadia 2001_MiST/rtl/pll.qip create mode 100644 Console_MiST/Emerson Arcadia 2001_MiST/rtl/pll.vhd create mode 100644 Console_MiST/Emerson Arcadia 2001_MiST/rtl/sgs2637.vhd create mode 100644 Console_MiST/Emerson Arcadia 2001_MiST/rtl/sgs2650.vhd create mode 100644 Console_MiST/Emerson Arcadia 2001_MiST/rtl/sgs2650_pack.vhd diff --git a/Console_MiST/Emerson Arcadia 2001_MiST/Arcadia_MiST.qpf b/Console_MiST/Emerson Arcadia 2001_MiST/Arcadia_MiST.qpf new file mode 100644 index 00000000..65595e61 --- /dev/null +++ b/Console_MiST/Emerson Arcadia 2001_MiST/Arcadia_MiST.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2014 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition +# Date created = 17:44:51 March 04, 2019 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.1" +DATE = "17:44:51 March 04, 2019" + +# Revisions + +PROJECT_REVISION = "Arcadia_MiST" diff --git a/Console_MiST/Emerson Arcadia 2001_MiST/Arcadia_MiST.qsf b/Console_MiST/Emerson Arcadia 2001_MiST/Arcadia_MiST.qsf new file mode 100644 index 00000000..bd48156f --- /dev/null +++ b/Console_MiST/Emerson Arcadia 2001_MiST/Arcadia_MiST.qsf @@ -0,0 +1,209 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2014 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition +# Date created = 21:36:26 March 08, 2019 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Galaga_MiST_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:59:05 MARCH 16, 2017" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_90 -to SPI_SS4 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PIN_49 -to SDRAM_A[0] +set_location_assignment PIN_44 -to SDRAM_A[1] +set_location_assignment PIN_42 -to SDRAM_A[2] +set_location_assignment PIN_39 -to SDRAM_A[3] +set_location_assignment PIN_4 -to SDRAM_A[4] +set_location_assignment PIN_6 -to SDRAM_A[5] +set_location_assignment PIN_8 -to SDRAM_A[6] +set_location_assignment PIN_10 -to SDRAM_A[7] +set_location_assignment PIN_11 -to SDRAM_A[8] +set_location_assignment PIN_28 -to SDRAM_A[9] +set_location_assignment PIN_50 -to SDRAM_A[10] +set_location_assignment PIN_30 -to SDRAM_A[11] +set_location_assignment PIN_32 -to SDRAM_A[12] +set_location_assignment PIN_83 -to SDRAM_DQ[0] +set_location_assignment PIN_79 -to SDRAM_DQ[1] +set_location_assignment PIN_77 -to SDRAM_DQ[2] +set_location_assignment PIN_76 -to SDRAM_DQ[3] +set_location_assignment PIN_72 -to SDRAM_DQ[4] +set_location_assignment PIN_71 -to SDRAM_DQ[5] +set_location_assignment PIN_69 -to SDRAM_DQ[6] +set_location_assignment PIN_68 -to SDRAM_DQ[7] +set_location_assignment PIN_86 -to SDRAM_DQ[8] +set_location_assignment PIN_87 -to SDRAM_DQ[9] +set_location_assignment PIN_98 -to SDRAM_DQ[10] +set_location_assignment PIN_99 -to SDRAM_DQ[11] +set_location_assignment PIN_100 -to SDRAM_DQ[12] +set_location_assignment PIN_101 -to SDRAM_DQ[13] +set_location_assignment PIN_103 -to SDRAM_DQ[14] +set_location_assignment PIN_104 -to SDRAM_DQ[15] +set_location_assignment PIN_58 -to SDRAM_BA[0] +set_location_assignment PIN_51 -to SDRAM_BA[1] +set_location_assignment PIN_85 -to SDRAM_DQMH +set_location_assignment PIN_67 -to SDRAM_DQML +set_location_assignment PIN_60 -to SDRAM_nRAS +set_location_assignment PIN_64 -to SDRAM_nCAS +set_location_assignment PIN_66 -to SDRAM_nWE +set_location_assignment PIN_59 -to SDRAM_nCS +set_location_assignment PIN_33 -to SDRAM_CKE +set_location_assignment PIN_43 -to SDRAM_CLK +set_location_assignment PIN_31 -to UART_RX +set_location_assignment PIN_46 -to UART_TX + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 +set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name TOP_LEVEL_ENTITY arcadia_mist + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# EDA Netlist Writer Assignments +# ============================== +set_global_assignment -name EDA_SIMULATION_TOOL "" + +# Assembler Assignments +# ===================== +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name GENERATE_RBF_FILE ON + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# start EDA_TOOL_SETTINGS(eda_simulation) +# --------------------------------------- + + # EDA Netlist Writer Assignments + # ============================== +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation + +# end EDA_TOOL_SETTINGS(eda_simulation) +# ------------------------------------- + +# ------------------------- +# start ENTITY(galaga_mist) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(galaga_mist) +# ----------------------- +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON +set_global_assignment -name SYSTEMVERILOG_FILE rtl/arcadia_mist.sv +set_global_assignment -name VHDL_FILE rtl/arcadia_core.vhd +set_global_assignment -name VHDL_FILE rtl/sgs2650_pack.vhd +set_global_assignment -name VHDL_FILE rtl/sgs2650.vhd +set_global_assignment -name VHDL_FILE rtl/sgs2637.vhd +set_global_assignment -name VHDL_FILE rtl/base_pack.vhd +set_global_assignment -name VHDL_FILE rtl/pll.vhd +set_global_assignment -name QIP_FILE ../../common/mist/mist.qip +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Console_MiST/Emerson Arcadia 2001_MiST/Arcadia_MiST.sdc b/Console_MiST/Emerson Arcadia 2001_MiST/Arcadia_MiST.sdc new file mode 100644 index 00000000..ea8cd2c9 --- /dev/null +++ b/Console_MiST/Emerson Arcadia 2001_MiST/Arcadia_MiST.sdc @@ -0,0 +1,42 @@ +#************************************************************ +# THIS IS A WIZARD-GENERATED FILE. +# +# Version 13.1.4 Build 182 03/12/2014 SJ Full Version +# +#************************************************************ + +# Copyright (C) 1991-2014 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + + +# Clock constraints + +create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}] + +# Automatically constrain PLL and other generated clocks +derive_pll_clocks -create_base_clocks + +# Automatically calculate clock uncertainty to jitter and other effects. +derive_clock_uncertainty + +set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}] + +set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_L}] +set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_R}] +set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {LED}] +set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {VGA_*}] + +set_multicycle_path -to {VGA_*[*]} -setup 2 +set_multicycle_path -to {VGA_*[*]} -hold 1 diff --git a/Console_MiST/Emerson Arcadia 2001_MiST/Readme.md b/Console_MiST/Emerson Arcadia 2001_MiST/Readme.md new file mode 100644 index 00000000..daeb0dcc --- /dev/null +++ b/Console_MiST/Emerson Arcadia 2001_MiST/Readme.md @@ -0,0 +1,12 @@ +# Emerson Arcadia 2001 game console + +## General description +This core implements a game console with Signetics 2650 CPU and 2637 Video controller. +This chipset was used in many game consoles such as : + +- Emerson Arcadia 2001 +- MPT-03 + + + + diff --git a/Console_MiST/Emerson Arcadia 2001_MiST/clean.bat b/Console_MiST/Emerson Arcadia 2001_MiST/clean.bat new file mode 100644 index 00000000..83fb0c47 --- /dev/null +++ b/Console_MiST/Emerson Arcadia 2001_MiST/clean.bat @@ -0,0 +1,15 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +del PLLJ_PLLSPE_INFO.txt +del *.qws +del *.ppf +del *.qip +del *.ddb +pause diff --git a/Console_MiST/Emerson Arcadia 2001_MiST/rtl/arcadia_core.vhd b/Console_MiST/Emerson Arcadia 2001_MiST/rtl/arcadia_core.vhd new file mode 100644 index 00000000..8e458c9e --- /dev/null +++ b/Console_MiST/Emerson Arcadia 2001_MiST/rtl/arcadia_core.vhd @@ -0,0 +1,429 @@ +--------------------------------------------------------------------------------- +-- Games consoles with Signetics 2650 CPU and 2637 VIDEO + +-- Emerson Arcadia 2001 & clones + +--------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.std_logic_1164.all; +USE IEEE.numeric_std.all; + +USE std.textio.ALL; + +LIBRARY work; +USE work.base_pack.ALL; + +ENTITY arcadia_core IS + PORT ( + -- Master input clock + clk : IN std_logic; + + -- Async reset from top-level module. Can be used as initial reset. + reset : IN std_logic; + + -- Must be passed to hps_io module + ntsc_pal : IN std_logic; + swap : IN std_logic; + swapxy : IN std_logic; + + -- Base video clock. Usually equals to CLK_SYS. + clk_video : OUT std_logic; + + -- Multiple resolutions are supported using different CE_PIXEL rates. + -- Must be based on CLK_VIDEO + ce_pixel : OUT std_logic; + + -- VGA + vga_r : OUT std_logic_vector(7 DOWNTO 0); + vga_g : OUT std_logic_vector(7 DOWNTO 0); + vga_b : OUT std_logic_vector(7 DOWNTO 0); + vga_hs : OUT std_logic; -- positive pulse! + vga_vs : OUT std_logic; -- positive pulse! + vga_de : OUT std_logic; -- = not (VBlank or HBlank) + + -- AUDIO + sound : OUT std_logic_vector(7 DOWNTO 0); + + ps2_key : IN std_logic_vector(10 DOWNTO 0); + joystick_0 : IN std_logic_vector(31 DOWNTO 0); + joystick_1 : IN std_logic_vector(31 DOWNTO 0); + joystick_analog_0 : IN std_logic_vector(15 DOWNTO 0); + joystick_analog_1 : IN std_logic_vector(15 DOWNTO 0); + + ioctl_download : IN std_logic; + ioctl_index : IN std_logic_vector(7 DOWNTO 0); + ioctl_wr : IN std_logic; + ioctl_addr : IN std_logic_vector(24 DOWNTO 0); + ioctl_dout : IN std_logic_vector(7 DOWNTO 0); + ioctl_wait : OUT std_logic + ); +END arcadia_core; + +ARCHITECTURE struct OF arcadia_core IS + + CONSTANT CDIV : natural := 4 * 8; + + -------------------------------------- + SIGNAL keypad1_1, keypad1_2, keypad1_3 : unsigned(7 DOWNTO 0); + SIGNAL keypad2_1, keypad2_2, keypad2_3 : unsigned(7 DOWNTO 0); + SIGNAL keypanel, volnoise : unsigned(7 DOWNTO 0); + + -------------------------------------- + SIGNAL vol : unsigned(1 DOWNTO 0); + SIGNAL icol,explo,explo2,noise,snd : std_logic; + SIGNAL sound1 : unsigned(7 DOWNTO 0); + SIGNAL lfsr : uv15; + SIGNAL nexplo : natural RANGE 0 TO 1000000; + SIGNAL divlfsr : uint8; + + SIGNAL pot1,pot2 : unsigned(7 DOWNTO 0); + SIGNAL potl_a,potl_b,potr_a,potr_b : unsigned(7 DOWNTO 0); + SIGNAL potl_v,potl_h,potr_v,potr_h : unsigned(7 DOWNTO 0); + SIGNAL pot0_a,pot0_b,pot1_a,pot1_b : unsigned(7 DOWNTO 0); + SIGNAL dpad0,dpad1 : std_logic; + SIGNAL tick_cpu_cpt : natural RANGE 0 TO CDIV-1; + SIGNAL tick_cpu : std_logic; + + SIGNAL ad,ad_delay,ad_rom : unsigned(14 DOWNTO 0); + SIGNAL dr,dw,dr_uvi,dr_rom,dr_key : unsigned(7 DOWNTO 0); + SIGNAL req,req_uvi,req_mem : std_logic; + SIGNAL ack,ackp,ack_uvi,ack_mem : std_logic; + SIGNAL sel_uvi,sel_mem : std_logic; + SIGNAL ack_mem_p,ack_mem_p2 : std_logic :='0'; + SIGNAL int,intack,creset : std_logic; + SIGNAL sense,flag : std_logic; + SIGNAL mio,ene,dc,wr : std_logic; + SIGNAL ph : unsigned(1 DOWNTO 0); + SIGNAL ivec : unsigned(7 DOWNTO 0); + + SIGNAL reset_na : std_logic; + SIGNAL w_d : unsigned(7 DOWNTO 0); + SIGNAL w_a : unsigned(12 DOWNTO 0); + SIGNAL w_wr : std_logic; + TYPE arr_cart IS ARRAY(natural RANGE <>) OF unsigned(7 DOWNTO 0); + --SIGNAL cart : arr_cart(0 TO 4095); + --ATTRIBUTE ramstyle : string; + --ATTRIBUTE ramstyle OF cart : SIGNAL IS "no_rw_check"; + + SHARED VARIABLE cart : arr_cart(0 TO 16383) :=(OTHERS =>x"00"); + ATTRIBUTE ramstyle : string; + ATTRIBUTE ramstyle OF cart : VARIABLE IS "no_rw_check"; + + SIGNAL wcart : std_logic; + + SIGNAL vga_argb : unsigned(3 DOWNTO 0); + SIGNAL vga_dei : std_logic; + SIGNAL vga_hsyn : std_logic; + SIGNAL vga_vsyn : std_logic; + SIGNAL vga_ce : std_logic; + + SIGNAL vrst : std_logic; + + SIGNAL vga_r_i,vga_g_i,vga_b_i : uv8; + + FILE fil : text OPEN write_mode IS "trace_mem.log"; + +BEGIN + + ---------------------------------------------------------- + -- Emerson Arcadia & clones + -- x00 aaaa aaaa aaaa : Cardtrige 4kb + -- x01 1000 aaaa aaaa : Video UVI RAM : 1800 + -- x01 1001 0xxx aaaa : Key inputs : 1900 + -- x01 1001 1xxx xxxx : Video UVI regs : 1980 + -- x01 1010 aaaa aaaa : Video UVI RAM : 1A00 + -- x10 aaaa aaaa aaaa : Cardridge high : 2000 + + i_sgs2637: ENTITY work.sgs2637 + PORT MAP ( + ad => ad, + dw => dw, + dr => dr_uvi, + req => req_uvi, + ack => ack_uvi, + wr => wr, + tick => tick_cpu, + vid_argb => vga_argb, + vid_de => vga_de, + vid_hsyn => vga_hsyn, + vid_vsyn => vga_vsyn, + vid_ce => vga_ce, + vrst => vrst, + sound => sound1, + pot1 => potr_v, + pot2 => potl_v, + pot3 => potr_h, + pot4 => potl_h, + np => ntsc_pal, + reset => reset, + clk => clk, + reset_na => reset_na); + + -- 1 2 3 + -- 4 5 6 + -- 7 8 9 + -- ENT 0 CLR + -- start,a,b,enter,clr,0,1,2,3,4,5,6,7,8,9 + + keypad1_1<="0000" & joystick_0(10) & joystick_0(13) & joystick_0(16) & joystick_0(8) ; -- 1900 : 1 4 7 CLEAR + keypad1_2<="0000" & joystick_0(11) & joystick_0(14) & joystick_0(17) & joystick_0(9) ; -- 1901 : 2 5 8 0 + keypad1_3<="0000" & joystick_0(12) & joystick_0(15) & joystick_0(18) & joystick_0(7) ; -- 1902 : 3 6 9 ENTER + + keypad2_1<="0000" & joystick_1(10) & joystick_1(13) & joystick_1(16) & joystick_1(8) ; -- 1904 : 1 4 7 CLEAR + keypad2_2<="0000" & joystick_1(11) & joystick_1(14) & joystick_1(17) & joystick_1(9) ; -- 1905 : 2 5 8 0 + keypad2_3<="0000" & joystick_1(12) & joystick_1(15) & joystick_1(18) & joystick_1(7) ; -- 1906 : 3 6 9 ENTER + + keypanel <="00000" & (joystick_0(6) & joystick_0(5) & joystick_0(4)) OR + (joystick_1(6) & joystick_1(5) & joystick_1(4)); -- 1908 : B A START + + dr_key<=keypad1_1 WHEN ad_delay(3 DOWNTO 0)=x"0" ELSE -- 1900 + keypad1_2 WHEN ad_delay(3 DOWNTO 0)=x"1" ELSE -- 1901 + keypad1_3 WHEN ad_delay(3 DOWNTO 0)=x"2" ELSE -- 1902 + keypad2_1 WHEN ad_delay(3 DOWNTO 0)=x"4" ELSE -- 1904 + keypad2_2 WHEN ad_delay(3 DOWNTO 0)=x"5" ELSE -- 1905 + keypad2_3 WHEN ad_delay(3 DOWNTO 0)=x"6" ELSE -- 1906 + keypanel WHEN ad_delay(3 DOWNTO 0)=x"8" ELSE -- 1908 + x"00"; + + + -- flag : Joystick : 0=Horizontal 1=Vertical + pot2<=potr_v WHEN flag='1' ELSE potr_h; + pot1<=potl_v WHEN flag='1' ELSE potl_h; + + sound <= std_logic_vector(sound1); + + ---------------------------------------------------------- + sense <=vrst; + + Joysticks:PROCESS (clk) IS + BEGIN + IF rising_edge(clk) THEN + ------------------------------------------------------------------------------- + IF dpad0='0' THEN + pot0_a<=unsigned(joystick_analog_0(15 DOWNTO 8))+x"80"; + pot0_b<=unsigned(joystick_analog_0( 7 DOWNTO 0))+x"80"; + ELSE + pot0_a<=x"80"; + pot0_b<=x"80"; + IF joystick_0(0)='1' THEN pot0_b<=x"FF"; END IF; + IF joystick_0(1)='1' THEN pot0_b<=x"00"; END IF; + IF joystick_0(2)='1' THEN pot0_a<=x"FF"; END IF; + IF joystick_0(3)='1' THEN pot0_a<=x"00"; END IF; + END IF; + + IF joystick_0(3 DOWNTO 0)/="0000" THEN + dpad0<='1'; + END IF; + IF joystick_analog_0(7 DOWNTO 5)="100" OR joystick_analog_0(7 DOWNTO 5)="011" OR + joystick_analog_0(15 DOWNTO 13)="100" OR joystick_analog_0(15 DOWNTO 13)="011" THEN + dpad0<='0'; + END IF; + + ------------------------------------------------------------------------------- + IF dpad1='0' THEN + pot1_a<=unsigned(joystick_analog_1(15 DOWNTO 8))+x"80"; + pot1_b<=unsigned(joystick_analog_1( 7 DOWNTO 0))+x"80"; + ELSE + pot1_a<=x"80"; + pot1_b<=x"80"; + IF joystick_1(0)='1' THEN pot1_b<=x"FF"; END IF; + IF joystick_1(1)='1' THEN pot1_b<=x"00"; END IF; + IF joystick_1(2)='1' THEN pot1_a<=x"FF"; END IF; + IF joystick_1(3)='1' THEN pot1_a<=x"00"; END IF; + END IF; + + IF joystick_1(3 DOWNTO 0)/="0000" THEN + dpad1<='1'; + END IF; + IF joystick_analog_1(7 DOWNTO 5)="100" OR joystick_analog_1(7 DOWNTO 5)="011" OR + joystick_analog_1(15 DOWNTO 13)="100" OR joystick_analog_1(15 DOWNTO 13)="011" THEN + dpad1<='0'; + END IF; + + ------------------------------------------------------------------------------- + potl_a<=mux(swap,pot1_a,pot0_a); + potl_b<=mux(swap,pot1_b,pot0_b); + potr_a<=mux(swap,pot0_a,pot1_a); + potr_b<=mux(swap,pot0_b,pot1_b); + + ------------------------------------------------------------------------------- + IF reset_na='0' THEN + dpad0<='0'; + dpad1<='0'; + END IF; + + END IF; + END PROCESS Joysticks; + + potl_h<=mux(swapxy,potl_a,potl_b); + potl_v<=mux(swapxy,potl_b,potl_a); + potr_h<=mux(swapxy,potr_a,potr_b); + potr_v<=mux(swapxy,potr_b,potr_a); + + ---------------------------------------------------------- + dr<=dr_uvi WHEN ad_delay(12)='1' AND ad_delay(11 DOWNTO 8)="1000" ELSE -- UVI Arcadia + dr_uvi WHEN ad_delay(12)='1' AND ad_delay(11 DOWNTO 7)="10011" ELSE -- UVI Arcadia + dr_key WHEN ad_delay(12)='1' AND ad_delay(11 DOWNTO 7)="10010" ELSE -- Keyboard + dr_uvi WHEN ad_delay(12)='1' AND ad_delay(11 DOWNTO 8)="1010" ELSE -- UVI Arcadia + dr_rom -- Cardridge + ; + + sel_uvi<=to_std_logic( + (ad(12)='1' AND ad(11 DOWNTO 8)="1000") OR + (ad(12)='1' AND ad(11 DOWNTO 8)="1010") OR + (ad(12)='1' AND ad(11 DOWNTO 7)="10011")); + + sel_mem<=NOT sel_uvi; + + req_uvi<=sel_uvi AND req; + req_mem<=sel_mem AND req; + + ackp<=tick_cpu AND ack_uvi WHEN sel_uvi='1' ELSE + tick_cpu AND ack_mem; + + PROCESS (clk) IS + BEGIN + IF rising_edge(clk) THEN + IF tick_cpu='1' THEN + ack_mem_p<=req_mem AND NOT ack_mem; + ack_mem_p2<=ack_mem_p AND req_mem; + END IF; + END IF; + END PROCESS; + ack_mem<=ack_mem_p2 AND ack_mem_p; + + --ack<='0'; + + ack<=ackp WHEN rising_edge(clk); + + ad_rom <="000" & ad(11 DOWNTO 0) WHEN ad(14 DOWNTO 12)="000" ELSE + "001" & ad(11 DOWNTO 0) WHEN ad(14 DOWNTO 12)="010" ELSE + ad; + + -- CPU + i_sgs2650: ENTITY work.sgs2650 + PORT MAP ( + req => req, + ack => ack, + ad => ad, + wr => wr, + dw => dw, + dr => dr, + mio => mio, + ene => ene, + dc => dc, + ph => ph, + int => int, + intack => intack, + ivec => ivec, + sense => sense, + flag => flag, + reset => creset, + clk => clk, + reset_na => reset_na); + + int<='0'; + ad_delay<=ad WHEN rising_edge(clk); + + ---------------------------------------------------------- +--pragma synthesis_off + Dump:PROCESS IS + VARIABLE lout : line; + VARIABLE doread : boolean := false; + VARIABLE adr : uv15; + BEGIN + wure(clk); + IF doread THEN + write(lout,"RD(" & to_hstring('0' & adr) & ")=" & to_hstring(dr)); + writeline(fil,lout); + doread:=false; + END IF; + IF req='1' AND ack='1' AND reset='0' AND reset_na='1' THEN + IF wr='1' THEN + write(lout,"WR(" & to_hstring('0' & ad) & ")=" & to_hstring(dw)); + writeline(fil,lout); + ELSE + doread:=true; + adr:=ad; + END IF; + END IF; + END PROCESS Dump; + +--pragma synthesis_on + ---------------------------------------------------------- + -- MUX VIDEO + clk_video<=clk; + ce_pixel<=vga_ce WHEN rising_edge(clk); + + vga_de<=vga_dei WHEN rising_edge(clk); + vga_hs<=vga_hsyn WHEN rising_edge(clk); + vga_vs<=vga_vsyn WHEN rising_edge(clk); + + vga_argb<=vga_argb WHEN rising_edge(clk); + vga_r_i<=(7=>vga_argb(2) AND vga_argb(3),OTHERS => vga_argb(2)); + vga_g_i<=(7=>vga_argb(1) AND vga_argb(3),OTHERS => vga_argb(1)); + vga_b_i<=(7=>vga_argb(0) AND vga_argb(3),OTHERS => vga_argb(0)); + vga_r<=std_logic_vector(vga_r_i); + vga_g<=std_logic_vector(vga_g_i); + vga_b<=std_logic_vector(vga_b_i); + + ---------------------------------------------------------- + -- ROM / RAM + + wcart<=wr AND req AND ack; -- WHEN ad(12)='0' ELSE '0'; + + icart:PROCESS(clk) IS + BEGIN + IF rising_edge(clk) THEN + dr_rom<=cart(to_integer(ad_rom(13 DOWNTO 0))); -- 8kB + + IF wcart='1' THEN + -- RAM + cart(to_integer(ad_rom(13 DOWNTO 0))):=dw; + END IF; + END IF; + END PROCESS icart; + + icart2:PROCESS(clk) IS + BEGIN + IF rising_edge(clk) THEN + -- Download + IF w_wr='1' THEN + cart(to_integer(w_a)):=w_d; + END IF; + END IF; + END PROCESS icart2; + + PROCESS(clk) IS + BEGIN + IF rising_edge(clk) THEN + w_wr<=ioctl_download AND ioctl_wr; + w_d <=unsigned(ioctl_dout); + w_a <=unsigned(ioctl_addr(12 DOWNTO 0)); + END IF; + END PROCESS; + + ioctl_wait<='0'; + + ---------------------------------------------------------- + -- CPU CLK + DivCLK:PROCESS (clk,reset_na) IS + BEGIN + IF reset_na='0' THEN + tick_cpu<='0'; + ELSIF rising_edge(clk) THEN + IF tick_cpu_cpt=CDIV - 1 THEN + tick_cpu_cpt<=0; + tick_cpu<='1'; + ELSE + tick_cpu_cpt<=tick_cpu_cpt+1; + tick_cpu<='0'; + END IF; + END IF; + END PROCESS DivCLK; + + reset_na<=NOT reset OR NOT ioctl_download; + creset<=ioctl_download; + +END struct; diff --git a/Console_MiST/Emerson Arcadia 2001_MiST/rtl/arcadia_mist.sv b/Console_MiST/Emerson Arcadia 2001_MiST/rtl/arcadia_mist.sv new file mode 100644 index 00000000..b77e217c --- /dev/null +++ b/Console_MiST/Emerson Arcadia 2001_MiST/rtl/arcadia_mist.sv @@ -0,0 +1,174 @@ +module arcadia_mist ( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 + +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "ARCADIA;BIN;", + "O34,Scandoubler Fx,None,CRT 25%,CRT 50%,CRT 75%;", + "O5,Swap Joystick,Off,On;", + "O6,Swap Joystick XY,Off,On;", + "T0,Reset;", + "V,v1.00.",`BUILD_DATE +}; + +assign LED = ~ioctl_downl; +assign AUDIO_R = AUDIO_L; +wire clksys, pll_locked; +pll pll( + .inclk0(CLOCK_27), + .c0(clksys),//35.46895 + .locked(pll_locked) + ); + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [31:0] joystick_0,joystick_1; +wire [31:0] joystick_analog_0,joystick_analog_1; +wire scandoublerD; +wire ypbpr; +wire no_csync; +wire [7:0] audio; +wire hs, vs; +wire blankn; +wire [7:0] r, g, b; +wire key_strobe; +wire key_pressed; +wire [7:0] key_code; +wire [15:0] rom_addr; +wire [15:0] rom_do; +wire [12:0] bg_addr; +wire [31:0] bg_do; + +//wire rom_rd; +wire ioctl_downl; +wire [7:0] ioctl_index; +wire ioctl_wr; +wire [24:0] ioctl_addr; +wire [7:0] ioctl_dout; + +data_io data_io( + .clk_sys ( clksys ), + .SPI_SCK ( SPI_SCK ), + .SPI_SS2 ( SPI_SS2 ), + .SPI_DI ( SPI_DI ), + .ioctl_download( ioctl_downl ), + .ioctl_index ( ioctl_index ), + .ioctl_wr ( ioctl_wr ), + .ioctl_addr ( ioctl_addr ), + .ioctl_dout ( ioctl_dout ) +); + +arcadia_core arcadia_core( + .clk(clksys), + .reset(status[0] | buttons[1] | ~ioctl_downl), + .ntsc_pal(1'b1), + .swap(status[5]), + .swapxy(status[6]), + .vga_r(r), + .vga_g(g), + .vga_b(b), + .vga_hs(hs), + .vga_vs(vs), + .vga_de(blankn), + .sound(audio), +// .joystick_0({joystick_0[31:6], m_fireB, m_fireA, m_left, m_right, m_up, m_down}), +// .joystick_1({joystick_1[31:6], m_fire2B, m_fire2A, m_left2, m_right2, m_up2, m_down2}), + .joystick_0(joystick_0), + .joystick_1(joystick_1), + .joystick_analog_0(joystick_analog_0), + .joystick_analog_1(joystick_analog_1), + .ioctl_download(ioctl_downl), + .ioctl_index(ioctl_index), + .ioctl_wr(ioctl_wr), + .ioctl_addr(ioctl_addr), + .ioctl_dout(ioctl_dout) + +); + +mist_video #(.COLOR_DEPTH(6), .SD_HCNT_WIDTH(10)) mist_video( + .clk_sys ( clksys ), + .SPI_SCK ( SPI_SCK ), + .SPI_SS3 ( SPI_SS3 ), + .SPI_DI ( SPI_DI ), + .R ( blankn ? r[7:2] : 0 ), + .G ( blankn ? g[7:2] : 0 ), + .B ( blankn ? b[7:2] : 0 ), + .HSync ( hs ), + .VSync ( vs ), + .VGA_R ( VGA_R ), + .VGA_G ( VGA_G ), + .VGA_B ( VGA_B ), + .VGA_VS ( VGA_VS ), + .VGA_HS ( VGA_HS ), + .scandoubler_disable( scandoublerD ), + .scanlines ( status[4:3] ), + .ypbpr ( ypbpr ), + .no_csync ( no_csync ) + ); + +user_io #(.STRLEN(($size(CONF_STR)>>3)))user_io( + .clk_sys (clksys ), + .conf_str (CONF_STR ), + .SPI_CLK (SPI_SCK ), + .SPI_SS_IO (CONF_DATA0 ), + .SPI_MISO (SPI_DO ), + .SPI_MOSI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable (scandoublerD ), + .ypbpr (ypbpr ), + .no_csync (no_csync ), + .key_strobe (key_strobe ), + .key_pressed (key_pressed ), + .key_code (key_code ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .joystick_analog_0(joystick_analog_0), + .joystick_analog_1(joystick_analog_1), + .status (status ) + ); + +dac #(.C_bits(8))dac( + .clk_i(clksys), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF; +wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F; +wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players; + +arcade_inputs inputs ( + .clk ( clksys ), + .key_strobe ( key_strobe ), + .key_pressed ( key_pressed ), + .key_code ( key_code ), + .joystick_0 ( joystick_0 ), + .joystick_1 ( joystick_1 ), + .joyswap ( 1'b0 ), + .oneplayer ( 1'b0 ), + .controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ), + .player1 ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ), + .player2 ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} ) +); + +endmodule diff --git a/Console_MiST/Emerson Arcadia 2001_MiST/rtl/base_pack.vhd b/Console_MiST/Emerson Arcadia 2001_MiST/rtl/base_pack.vhd new file mode 100644 index 00000000..7eb371fd --- /dev/null +++ b/Console_MiST/Emerson Arcadia 2001_MiST/rtl/base_pack.vhd @@ -0,0 +1,631 @@ +-------------------------------------------------------------------------------- +-- BASE +-- Definitions +-------------------------------------------------------------------------------- +-- DO 3/2009 +-------------------------------------------------------------------------------- +-- Base +-------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +PACKAGE base_pack IS + -------------------------------------- + SUBTYPE uv IS unsigned; + SUBTYPE sv IS signed; + + SUBTYPE uv1_0 IS unsigned(1 DOWNTO 0); + SUBTYPE uv0_1 IS unsigned(0 TO 1); + SUBTYPE uv3_0 IS unsigned(3 DOWNTO 0); + SUBTYPE uv0_3 IS unsigned(0 TO 3); + SUBTYPE uv7_0 IS unsigned(7 DOWNTO 0); + SUBTYPE uv0_7 IS unsigned(0 TO 7); + + SUBTYPE uv2 IS unsigned(1 DOWNTO 0); + SUBTYPE uv3 IS unsigned(2 DOWNTO 0); + SUBTYPE uv4 IS unsigned(3 DOWNTO 0); + SUBTYPE uv5 IS unsigned(4 DOWNTO 0); + SUBTYPE uv6 IS unsigned(5 DOWNTO 0); + SUBTYPE uv7 IS unsigned(6 DOWNTO 0); + SUBTYPE uv8 IS unsigned(7 DOWNTO 0); + SUBTYPE uv9 IS unsigned(8 DOWNTO 0); + SUBTYPE uv10 IS unsigned(9 DOWNTO 0); + SUBTYPE uv11 IS unsigned(10 DOWNTO 0); + SUBTYPE uv12 IS unsigned(11 DOWNTO 0); + SUBTYPE uv13 IS unsigned(12 DOWNTO 0); + SUBTYPE uv14 IS unsigned(13 DOWNTO 0); + SUBTYPE uv15 IS unsigned(14 DOWNTO 0); + SUBTYPE uv16 IS unsigned(15 DOWNTO 0); + SUBTYPE uv17 IS unsigned(16 DOWNTO 0); + SUBTYPE uv18 IS unsigned(17 DOWNTO 0); + SUBTYPE uv19 IS unsigned(18 DOWNTO 0); + SUBTYPE uv20 IS unsigned(19 DOWNTO 0); + SUBTYPE uv21 IS unsigned(20 DOWNTO 0); + SUBTYPE uv22 IS unsigned(21 DOWNTO 0); + SUBTYPE uv23 IS unsigned(22 DOWNTO 0); + SUBTYPE uv24 IS unsigned(23 DOWNTO 0); + SUBTYPE uv25 IS unsigned(24 DOWNTO 0); + SUBTYPE uv26 IS unsigned(25 DOWNTO 0); + SUBTYPE uv27 IS unsigned(26 DOWNTO 0); + SUBTYPE uv28 IS unsigned(27 DOWNTO 0); + SUBTYPE uv29 IS unsigned(28 DOWNTO 0); + SUBTYPE uv30 IS unsigned(29 DOWNTO 0); + SUBTYPE uv31 IS unsigned(30 DOWNTO 0); + SUBTYPE uv32 IS unsigned(31 DOWNTO 0); + SUBTYPE uv64 IS unsigned(63 DOWNTO 0); + SUBTYPE uv128 IS unsigned(127 DOWNTO 0); + + SUBTYPE sv2 IS signed(1 DOWNTO 0); + SUBTYPE sv4 IS signed(3 DOWNTO 0); + SUBTYPE sv8 IS signed(7 DOWNTO 0); + SUBTYPE sv16 IS signed(15 DOWNTO 0); + SUBTYPE sv32 IS signed(31 DOWNTO 0); + SUBTYPE sv64 IS signed(63 DOWNTO 0); + SUBTYPE sv128 IS signed(127 DOWNTO 0); + + TYPE arr_uv0_3 IS ARRAY(natural RANGE <>) OF uv0_3; + TYPE arr_uv0_7 IS ARRAY(natural RANGE <>) OF uv0_7; + + TYPE arr_uv4 IS ARRAY(natural RANGE <>) OF uv4; + TYPE arr_uv8 IS ARRAY(natural RANGE <>) OF uv8; + TYPE arr_uv16 IS ARRAY(natural RANGE <>) OF uv16; + TYPE arr_uv32 IS ARRAY(natural RANGE <>) OF uv32; + TYPE arr_uv64 IS ARRAY(natural RANGE <>) OF uv64; + + SUBTYPE uint1 IS natural RANGE 0 TO 1; + SUBTYPE uint2 IS natural RANGE 0 TO 3; + SUBTYPE uint3 IS natural RANGE 0 TO 7; + SUBTYPE uint4 IS natural RANGE 0 TO 15; + SUBTYPE uint5 IS natural RANGE 0 TO 31; + SUBTYPE uint6 IS natural RANGE 0 TO 63; + SUBTYPE uint7 IS natural RANGE 0 TO 127; + SUBTYPE uint8 IS natural RANGE 0 TO 255; + SUBTYPE uint9 IS natural RANGE 0 TO 511; + SUBTYPE uint10 IS natural RANGE 0 TO 1023; + SUBTYPE uint11 IS natural RANGE 0 TO 2047; + SUBTYPE uint12 IS natural RANGE 0 TO 4095; + SUBTYPE uint13 IS natural RANGE 0 TO 8191; + SUBTYPE uint14 IS natural RANGE 0 TO 16383; + SUBTYPE uint15 IS natural RANGE 0 TO 32767; + SUBTYPE uint16 IS natural RANGE 0 TO 65535; + SUBTYPE uint24 IS natural RANGE 0 TO 16777215; + + SUBTYPE int2 IS integer RANGE -2 TO 1; + SUBTYPE int3 IS integer RANGE -4 TO 3; + SUBTYPE int4 IS integer RANGE -8 TO 7; + SUBTYPE int5 IS integer RANGE -16 TO 15; + SUBTYPE int6 IS integer RANGE -32 TO 31; + SUBTYPE int7 IS integer RANGE -64 TO 63; + SUBTYPE int8 IS integer RANGE -128 TO 127; + SUBTYPE int9 IS integer RANGE -256 TO 255; + SUBTYPE int10 IS integer RANGE -512 TO 511; + SUBTYPE int11 IS integer RANGE -1024 TO 1023; + SUBTYPE int12 IS integer RANGE -2048 TO 2047; + SUBTYPE int13 IS integer RANGE -4096 TO 4095; + SUBTYPE int14 IS integer RANGE -8192 TO 8191; + SUBTYPE int15 IS integer RANGE -16384 TO 16383; + SUBTYPE int16 IS integer RANGE -32768 TO 32767; + SUBTYPE int17 IS integer RANGE -65536 TO 65535; + + + ------------------------------------------------------------- + FUNCTION v_or (CONSTANT v : unsigned) RETURN std_logic; + FUNCTION v_and (CONSTANT v : unsigned) RETURN std_logic; + FUNCTION vv (CONSTANT s : std_logic; + CONSTANT N : natural) RETURN unsigned; + + -------------------------------------- + FUNCTION to_std_logic (a : boolean) RETURN std_logic; + -------------------------------------- + FUNCTION mux ( + s : std_logic; + a : unsigned; + b : unsigned) RETURN unsigned; + -------------------------------------- + FUNCTION mux ( + s : boolean; + a : unsigned; + b : unsigned) RETURN unsigned; + -------------------------------------- + FUNCTION mux ( + s : std_logic; + a : std_logic; + b : std_logic) RETURN std_logic; + -------------------------------------- + FUNCTION mux ( + s : boolean; + a : std_logic; + b : std_logic) RETURN std_logic; + -------------------------------------- + FUNCTION mux ( + s : boolean; + a : boolean; + b : boolean) RETURN boolean; + -------------------------------------- + FUNCTION mux ( + s : boolean; + a : integer; + b : integer) RETURN integer; + -------------------------------------- + FUNCTION mux ( + s : std_logic; + a : character; + b : character) RETURN character; + -------------------------------------- + FUNCTION mux ( + s : boolean; + a : character; + b : character) RETURN character; + -------------------------------------- + FUNCTION sext ( + e : unsigned; + l : natural) RETURN unsigned; + -------------------------------------- + FUNCTION sext ( + e : std_logic; + l : natural) RETURN unsigned; + -------------------------------------- + FUNCTION uext ( + e : unsigned; + l : natural) RETURN unsigned; + -------------------------------------- + FUNCTION uext ( + e : std_logic; + l : natural) RETURN unsigned; + -------------------------------------- + PROCEDURE wure ( + SIGNAL clk : IN std_logic; + CONSTANT n : IN natural:=1); + -------------------------------------- + PROCEDURE wufe ( + SIGNAL clk : IN std_logic; + CONSTANT n : IN natural:=1); + -------------------------------------- + FUNCTION To_HString (v : unsigned) RETURN string; + FUNCTION To_String (v : unsigned) RETURN string; + -------------------------------------- + FUNCTION To_Upper (c : character) RETURN character; + FUNCTION To_Upper (s : string) RETURN string; + FUNCTION To_String (i : natural; b : integer) RETURN string; + FUNCTION To_Natural (s : string; b : integer) RETURN natural; + + FUNCTION ilog2 (CONSTANT v : natural) RETURN natural; + +END PACKAGE base_pack; + +-------------------------------------------------------------------------------- + +PACKAGE BODY base_pack IS + + ------------------------------------------------------------- + FUNCTION vv (CONSTANT s : std_logic; + CONSTANT N : natural) RETURN unsigned IS + VARIABLE v : unsigned(N-1 DOWNTO 0); + BEGIN + v:=(OTHERS => s); + RETURN v; + END FUNCTION vv; + + ------------------------------------------------------------- + -- Vector OR (reduce) + FUNCTION v_or (CONSTANT v : unsigned) RETURN std_logic IS + VARIABLE r : std_logic := '0'; + VARIABLE Z : unsigned(v'range) := (OTHERS =>'0'); + BEGIN +--pragma synthesis_off + IF 1=1 THEN + FOR I IN v'range LOOP + r:=r OR v(I); + END LOOP; + RETURN r; + ELSE +--pragma synthesis_on + IF v/=Z THEN + RETURN '1'; + ELSE + RETURN '0'; + END IF; +--pragma synthesis_off + END IF; +--pragma synthesis_on + END FUNCTION v_or; + + ------------------------------------------------------------- + -- Vector AND (reduce) + FUNCTION v_and (CONSTANT v : unsigned) RETURN std_logic IS + VARIABLE r : std_logic := '1'; + VARIABLE U : unsigned(v'range) := (OTHERS =>'1'); + BEGIN +--pragma synthesis_off + IF 1=1 THEN + FOR I IN v'range LOOP + r:=r AND v(I); + END LOOP; + RETURN r; + ELSE +--pragma synthesis_on + IF v/=U THEN + RETURN '0'; + ELSE + RETURN '1'; + END IF; +--pragma synthesis_off + END IF; +--pragma synthesis_on + END FUNCTION v_and; + + -------------------------------------- + FUNCTION to_std_logic (a : boolean) RETURN std_logic IS + BEGIN + IF a THEN RETURN '1'; + ELSE RETURN '0'; + END IF; + END FUNCTION to_std_logic; + + -------------------------------------- + -- Sélection/Multiplexage s=1:a, s=0:b + FUNCTION mux ( + s : std_logic; + a : unsigned; + b : unsigned) RETURN unsigned IS + VARIABLE x : unsigned(a'range) :=(OTHERS => 'X'); + BEGIN + ASSERT a'length=b'length + REPORT "mux(): Different lengths" SEVERITY failure; + IF s='1' THEN + RETURN a; + ELSIF s='0' THEN + RETURN b; + ELSE + RETURN x; + END IF; + END FUNCTION mux; + + -------------------------------------- + -- Sélection/Multiplexage s=true:a, s=false:b + FUNCTION mux ( + s : boolean; + a : unsigned; + b : unsigned) RETURN unsigned IS + BEGIN + ASSERT a'length=b'length + REPORT "mux(): Different lengths" SEVERITY failure; + IF s THEN + RETURN a; + ELSE + RETURN b; + END IF; + END FUNCTION mux; + + -------------------------------------- + -- Sélection/Multiplexage s=1:a, s=0:b + FUNCTION mux ( + s : std_logic; + a : std_logic; + b : std_logic) + RETURN std_logic IS + BEGIN + RETURN (S AND A) OR (NOT S AND B); + END FUNCTION mux; + + -------------------------------------- + -- Sélection/Multiplexage s=true:a, s=false:b + FUNCTION mux ( + s : boolean; + a : std_logic; + b : std_logic) + RETURN std_logic IS + BEGIN + IF s THEN + RETURN a; + ELSE + RETURN b; + END IF; + END FUNCTION mux; + + -------------------------------------- + -- Sélection/Multiplexage s=true:a, s=false:b + FUNCTION mux ( + s : boolean; + a : boolean; + b : boolean) + RETURN boolean IS + BEGIN + IF s THEN + RETURN a; + ELSE + RETURN b; + END IF; + END FUNCTION mux; + + -------------------------------------- + -- Sélection/Multiplexage s=1:a, s=0:b + FUNCTION mux ( + s : boolean; + a : integer; + b : integer) + RETURN integer IS + BEGIN + IF s THEN + RETURN a; + ELSE + RETURN b; + END IF; + END FUNCTION mux; + + -------------------------------------- + -- Sélection/Multiplexage s=true:a, s=false:b + FUNCTION mux ( + s : std_logic; + a : character; + b : character) + RETURN character IS + BEGIN + IF s='1' THEN + RETURN a; + ELSE + RETURN b; + END IF; + END FUNCTION mux; + + -------------------------------------- + -- Sélection/Multiplexage s=true:a, s=false:b + FUNCTION mux ( + s : boolean; + a : character; + b : character) + RETURN character IS + BEGIN + IF s THEN + RETURN a; + ELSE + RETURN b; + END IF; + END FUNCTION mux; + + -------------------------------------- + -- Étend un vecteur avec extension de signe + FUNCTION sext ( + e : unsigned; + l : natural) RETURN unsigned IS + VARIABLE t : unsigned(l-1 DOWNTO 0); + BEGIN + -- Vérifier numeric_std.resize ... + t:=(OTHERS => e(e'left)); + t(e'length-1 DOWNTO 0):=e; + RETURN t; + END FUNCTION sext; + + -------------------------------------- + -- Étend un vecteur avec extension de signe + FUNCTION sext ( + e : std_logic; + l : natural) RETURN unsigned IS + VARIABLE t : unsigned(l-1 DOWNTO 0); + BEGIN + -- Vérifier numeric_std.resize ... + t:=(OTHERS => e); + RETURN t; + END FUNCTION sext; + + -------------------------------------- + -- Étend un vecteur sans extension de signe + FUNCTION uext ( + e : unsigned; + l : natural) RETURN unsigned IS + VARIABLE t : unsigned(l-1 DOWNTO 0); + BEGIN + -- Vérifier numeric_std.resize ... + t:=(OTHERS => '0'); + t(e'length-1 DOWNTO 0):=e; + RETURN t; + END FUNCTION uext; + + -------------------------------------- + -- Étend un vecteur sans extension de signe + FUNCTION uext ( + e : std_logic; + l : natural) RETURN unsigned IS + VARIABLE t : unsigned(l-1 DOWNTO 0); + BEGIN + -- Vérifier numeric_std.resize ... + t:=(OTHERS => '0'); + t(0):=e; + RETURN t; + END FUNCTION uext; + + -------------------------------------- + -- Wait Until Rising Edge + PROCEDURE wure( + SIGNAL clk : IN std_logic; + CONSTANT n : IN natural:=1) IS + BEGIN + FOR i IN 1 TO n LOOP + WAIT UNTIL rising_edge(clk); + END LOOP; + END PROCEDURE wure; + + -------------------------------------- + -- Wait Until Rising Edge + PROCEDURE wufe( + SIGNAL clk : IN std_logic; + CONSTANT n : IN natural:=1) IS + BEGIN + FOR i IN 1 TO n LOOP + WAIT UNTIL falling_edge(clk); + END LOOP; + END PROCEDURE wufe; + + -------------------------------------- + CONSTANT HexString : string(1 TO 16):="0123456789ABCDEF"; + + -- Conversion unsigned -> Chaîne hexadécimale + FUNCTION To_HString(v : unsigned) RETURN string IS + VARIABLE r : string(1 TO ((v'length)+3)/4); + VARIABLE x : unsigned(1 TO v'length); + VARIABLE i,j : integer; + BEGIN + x:=v; + i:=1; + j:=1; + r:=(OTHERS =>' '); + WHILE i Chaîne binaire + FUNCTION To_String(v : unsigned) RETURN string IS + VARIABLE r : string(1 TO v'length); + VARIABLE x : unsigned(1 TO v'length); + BEGIN + x:=v; + FOR i IN 1 TO v'length LOOP + CASE x(i) IS + WHEN '0' => r(i):='0'; + WHEN '1' => r(i):='1'; + WHEN 'X' => r(i):='X'; + WHEN 'Z' => r(i):='Z'; + WHEN 'U' => r(i):='U'; + WHEN 'H' => r(i):='H'; + WHEN 'L' => r(i):='L'; + WHEN '-' => r(i):='-'; + WHEN 'W' => r(i):='W'; + END CASE; + -- r(i):=std_logic'image(x(i))(1); + END LOOP; + RETURN r; + END FUNCTION To_String; + + -------------------------------------- + -- Conversion majuscules caractère + FUNCTION To_Upper(c : character) RETURN character IS + VARIABLE r : character; + BEGIN + CASE c IS + WHEN 'a' => r := 'A'; + WHEN 'b' => r := 'B'; + WHEN 'c' => r := 'C'; + WHEN 'd' => r := 'D'; + WHEN 'e' => r := 'E'; + WHEN 'f' => r := 'F'; + WHEN 'g' => r := 'G'; + WHEN 'h' => r := 'H'; + WHEN 'i' => r := 'I'; + WHEN 'j' => r := 'J'; + WHEN 'k' => r := 'K'; + WHEN 'l' => r := 'L'; + WHEN 'm' => r := 'M'; + WHEN 'n' => r := 'N'; + WHEN 'o' => r := 'O'; + WHEN 'p' => r := 'P'; + WHEN 'q' => r := 'Q'; + WHEN 'r' => r := 'R'; + WHEN 's' => r := 'S'; + WHEN 't' => r := 'T'; + WHEN 'u' => r := 'U'; + WHEN 'v' => r := 'V'; + WHEN 'w' => r := 'W'; + WHEN 'x' => r := 'X'; + WHEN 'y' => r := 'Y'; + WHEN 'z' => r := 'Z'; + WHEN OTHERS => r := c; + END CASE; + RETURN r; + END To_Upper; + + -------------------------------------- + -- Conversion majuscules chaîne + FUNCTION To_Upper(s: string) RETURN string IS + VARIABLE r: string (s'range); + BEGIN + FOR i IN s'range LOOP + r(i):= to_upper(s(i)); + END LOOP; + RETURN r; + END To_Upper; + + -------------------------------------- + -- Conversion entier -> chaîne + FUNCTION To_String(i: natural; b: integer) RETURN string IS + VARIABLE r : string(1 TO 10); + VARIABLE j,k : natural; + VARIABLE t : character; + BEGIN + j:=i; + k:=10; + WHILE j>=b LOOP + r(k):=HexString(j MOD b); + j:=j/b; + k:=k-1; + END LOOP; + + RETURN r(k TO 10); + END FUNCTION To_String; + + -------------------------------------- + -- Conversion chaîne -> entier + FUNCTION To_Natural (s : string; b : integer) RETURN natural IS + VARIABLE v,r : natural; + BEGIN + r:=0; + FOR i IN s'range LOOP + CASE s(i) IS + WHEN '0' => v:=0; + WHEN '1' => v:=1; + WHEN '2' => v:=2; + WHEN '3' => v:=3; + WHEN '4' => v:=4; + WHEN '5' => v:=5; + WHEN '6' => v:=6; + WHEN '7' => v:=7; + WHEN '8' => v:=8; + WHEN '9' => v:=9; + WHEN 'a' | 'A' => v:=10; + WHEN 'b' | 'B' => v:=11; + WHEN 'c' | 'C' => v:=12; + WHEN 'd' | 'D' => v:=13; + WHEN 'e' | 'E' => v:=14; + WHEN 'f' | 'F' => v:=15; + WHEN OTHERS => + v:=1000; + END CASE; + ASSERT vr LOOP + n:=n+1; + r:=r*2; + END LOOP; + RETURN n; + END FUNCTION ilog2; + +END PACKAGE BODY base_pack; diff --git a/Console_MiST/Emerson Arcadia 2001_MiST/rtl/build_id.tcl b/Console_MiST/Emerson Arcadia 2001_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Console_MiST/Emerson Arcadia 2001_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Console_MiST/Emerson Arcadia 2001_MiST/rtl/pll.qip b/Console_MiST/Emerson Arcadia 2001_MiST/rtl/pll.qip new file mode 100644 index 00000000..48665362 --- /dev/null +++ b/Console_MiST/Emerson Arcadia 2001_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Console_MiST/Emerson Arcadia 2001_MiST/rtl/pll.vhd b/Console_MiST/Emerson Arcadia 2001_MiST/rtl/pll.vhd new file mode 100644 index 00000000..c2e5d2d9 --- /dev/null +++ b/Console_MiST/Emerson Arcadia 2001_MiST/rtl/pll.vhd @@ -0,0 +1,365 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.4 Build 182 03/12/2014 SJ Full Version +-- ************************************************************ + + +--Copyright (C) 1991-2014 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END pll; + + +ARCHITECTURE SYN OF pll IS + + SIGNAL sub_wire0 : STD_LOGIC ; + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + self_reset_on_loss_lock : STRING; + width_clock : NATURAL + ); + PORT ( + areset : IN STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + locked : OUT STD_LOGIC + ); + END COMPONENT; + +BEGIN + sub_wire5_bv(0 DOWNTO 0) <= "0"; + sub_wire5 <= To_stdlogicvector(sub_wire5_bv); + locked <= sub_wire0; + sub_wire2 <= sub_wire1(0); + c0 <= sub_wire2; + sub_wire3 <= inclk0; + sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 51, + clk0_duty_cycle => 50, + clk0_multiply_by => 67, + clk0_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 37037, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=pll", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_USED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_UNUSED", + port_clk2 => "PORT_UNUSED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + self_reset_on_loss_lock => "OFF", + width_clock => 5 + ) + PORT MAP ( + areset => areset, + inclk => sub_wire4, + locked => sub_wire0, + clk => sub_wire1 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "51" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "35.470589" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "67" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "35.46895000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "51" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "67" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Console_MiST/Emerson Arcadia 2001_MiST/rtl/sgs2637.vhd b/Console_MiST/Emerson Arcadia 2001_MiST/rtl/sgs2637.vhd new file mode 100644 index 00000000..f1cb3c4e --- /dev/null +++ b/Console_MiST/Emerson Arcadia 2001_MiST/rtl/sgs2637.vhd @@ -0,0 +1,778 @@ +-------------------------------------------------------------------------------- +-- Signetics 2637 UVI Universal Video Interface +-------------------------------------------------------------------------------- +-- DO 10/2018 +-------------------------------------------------------------------------------- + +-- 00 .. CF : RAM screen +-- D0 .. EF : RAM user +-- F0 : /O1.VC +-- F1 : O1.HC +-- F2 : /O2.VC +-- F3 : O2.HC +-- F4 : /O3.VC +-- F5 : O3.HC +-- F6 : /O4.VC +-- F7 : O4.HC +-- F8 : ? +-- F9 : ? +-- FA : ? +-- FB : ? +-- FC : V offset +-- FD : Sound pitch / Color mode +-- FE : Delay chars / random noise / sound ena / loudness +-- FF : DMA row +-- 100 .. 17F : ? +-- 180 .. 187 : O1. font +-- 188 .. 18F : O2. font +-- 190 .. 197 : O3. font +-- 198 .. 19F : O4. font +-- 1A0 .. 1A7 : O5. font +-- 1A8 .. 1AF : O6. font +-- 1B0 .. 1B7 : O7. font +-- 1B8 .. 1BF : O8. font +-- 1C0 .. 1F7 : ? +-- 1F8 : Colour / refresh mode / graphic mode / +-- 1F9 : Colour characters / pot / charsize +-- 1FA : Obj 3-4 colour +-- 1FB : Obj 1-2 colour +-- 1FC : Collision detect : chars +-- 1FD : Collision detect : inter-objets +-- 1FE : POT 2/4 +-- 1FF : POT 1/2 + +-- A D +-- 0 : Text +-- 1 : Data +-- 2 : Charmap +-- 3 : Obj1map Charsymbol +-- 4 : Obj2map Charsymbol +-- 5 : Obj3map Charsymbol +-- 6 : Obj4map Charsymbol +-- 7 : Charsymbol + + +-- 1800 .. 18FF : RAM + +-- 1900 .. 197F : Buttons +-- 1980 .. 19FF : Regs +-- 1A00 .. 1AFF : RAM +-- 1B00 .. 1BFF : Mirror 1900 .. 19FF +-- +-- +-------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +USE std.textio.ALL; + +LIBRARY work; +USE work.base_pack.ALL; + +ENTITY sgs2637 IS + PORT ( + ad : IN uv15; -- Address bus + + dw : IN uv8; -- Data write + dr : OUT uv8; -- Data read + + req : IN std_logic; + ack : OUT std_logic; + wr : IN std_logic; + tick : IN std_logic; + + vid_argb : OUT uv4; -- I | R | G | B + vid_de : OUT std_logic; + vid_hsyn : OUT std_logic; + vid_vsyn : OUT std_logic; + vid_ce : OUT std_logic; + vrst : OUT std_logic; + + sound : OUT uv8; + + pot1 : IN uv8; + pot2 : IN uv8; + pot3 : IN uv8; + pot4 : IN uv8; + + np : IN std_logic; -- 0=NTSC 60Hz, 1=PAL 50Hz + + reset : IN std_logic; + clk : IN std_logic; -- 8x Pixel clock + reset_na : IN std_logic + ); +END ENTITY sgs2637; + +ARCHITECTURE rtl OF sgs2637 IS + SUBTYPE uint9 IS natural RANGE 0 TO 511; + + -- 64 chars * 8 lines = 512 + CONSTANT CHARS : arr_uv8(0 TO 511) := ( + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- ' ' + x"01",x"02",x"04",x"08",x"10",x"20",x"40",x"80", -- / + x"80",x"40",x"20",x"10",x"08",x"04",x"02",x"01", -- \ + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- # + x"FF",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- " + x"01",x"01",x"01",x"01",x"01",x"01",x"01",x"01", -- | + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"FF", -- _ + x"80",x"80",x"80",x"80",x"80",x"80",x"80",x"80", -- | + x"FF",x"01",x"01",x"01",x"01",x"01",x"01",x"01", -- "| + x"FF",x"80",x"80",x"80",x"80",x"80",x"80",x"80", -- |" + x"80",x"80",x"80",x"80",x"80",x"80",x"80",x"FF", -- |_ + x"01",x"01",x"01",x"01",x"01",x"01",x"01",x"FF", -- _| + x"01",x"03",x"07",x"0F",x"1F",x"3F",x"7F",x"FF", -- / + x"80",x"C0",x"E0",x"F0",x"F8",x"FC",x"FE",x"FF", -- \ + x"FF",x"FE",x"FC",x"F8",x"F0",x"E0",x"C0",x"80", -- / + x"FF",x"7F",x"3F",x"1F",x"0F",x"07",x"03",x"01", -- \ + x"00",x"1C",x"22",x"26",x"2A",x"32",x"22",x"1C", -- 0 + x"00",x"08",x"18",x"08",x"08",x"08",x"08",x"1C", -- 1 + x"00",x"1C",x"22",x"02",x"0C",x"10",x"20",x"3E", -- 2 + x"00",x"3E",x"02",x"04",x"0C",x"02",x"22",x"1C", -- 3 + x"00",x"04",x"0C",x"14",x"24",x"3E",x"04",x"04", -- 4 + x"00",x"3E",x"20",x"3C",x"02",x"02",x"22",x"1C", -- 5 + x"00",x"0C",x"10",x"20",x"3C",x"22",x"22",x"1C", -- 6 + x"00",x"7C",x"02",x"04",x"08",x"10",x"10",x"10", -- 7 + x"00",x"1C",x"22",x"22",x"1C",x"22",x"22",x"1C", -- 8 + x"00",x"1C",x"22",x"22",x"3E",x"02",x"04",x"18", -- 9 + x"00",x"08",x"14",x"22",x"22",x"3E",x"22",x"22", -- A + x"00",x"3C",x"22",x"22",x"3C",x"22",x"22",x"3C", -- B + x"00",x"1C",x"22",x"20",x"20",x"20",x"22",x"1C", -- C + x"00",x"3C",x"22",x"22",x"22",x"22",x"22",x"3C", -- D + x"00",x"3E",x"20",x"20",x"3C",x"20",x"20",x"3E", -- E + x"00",x"3E",x"20",x"20",x"38",x"20",x"20",x"20", -- F + x"00",x"1E",x"20",x"20",x"20",x"26",x"22",x"1E", -- G + x"00",x"22",x"22",x"22",x"3E",x"22",x"22",x"22", -- H + x"00",x"1C",x"08",x"08",x"08",x"08",x"08",x"1C", -- I + x"00",x"02",x"02",x"02",x"02",x"02",x"22",x"1C", -- J + x"00",x"22",x"24",x"28",x"30",x"28",x"24",x"22", -- K + x"00",x"20",x"20",x"20",x"20",x"20",x"20",x"3E", -- L + x"00",x"22",x"36",x"2A",x"2A",x"22",x"22",x"22", -- M + x"00",x"22",x"22",x"32",x"2A",x"26",x"22",x"22", -- N + x"00",x"1C",x"22",x"22",x"22",x"22",x"22",x"1C", -- O + x"00",x"3C",x"22",x"22",x"3C",x"20",x"20",x"20", -- P + x"00",x"1C",x"22",x"22",x"22",x"2A",x"24",x"1A", -- Q + x"00",x"3C",x"22",x"22",x"3C",x"28",x"24",x"22", -- R + x"00",x"1C",x"22",x"20",x"1C",x"02",x"22",x"1C", -- S + x"00",x"3E",x"08",x"08",x"08",x"08",x"08",x"08", -- T + x"00",x"22",x"22",x"22",x"22",x"22",x"22",x"1C", -- U + x"00",x"22",x"22",x"22",x"22",x"22",x"14",x"08", -- V + x"00",x"22",x"22",x"22",x"2A",x"2A",x"36",x"22", -- W + x"00",x"22",x"22",x"14",x"08",x"14",x"22",x"22", -- X + x"00",x"22",x"22",x"14",x"08",x"08",x"08",x"08", -- Y + x"00",x"3E",x"02",x"04",x"08",x"10",x"20",x"3E", -- Z + x"00",x"00",x"00",x"00",x"00",x"00",x"0C",x"0C", -- . + x"00",x"00",x"00",x"00",x"00",x"08",x"08",x"10", -- , + x"00",x"00",x"08",x"08",x"3E",x"08",x"08",x"00", -- + + x"00",x"08",x"1E",x"28",x"1C",x"0A",x"3C",x"08", -- $ + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- User char + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- User char + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- User char + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- User char + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- User char + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- User char + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- User char + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00"); -- User char + + SIGNAL wreq : std_logic; + SIGNAL ram : arr_uv8(0 TO 1023); + ATTRIBUTE ramstyle : string; + ATTRIBUTE ramstyle OF ram : SIGNAL IS "no_rw_check"; + + SIGNAL adi : uv12; + SIGNAL ram_ad,xxx_ad : uv10; + SIGNAL ram_dr,rom_dr,ch : uv8; + SIGNAL dr_reg,dr_mem : uv8; + SIGNAL drreg_sel : std_logic; + SIGNAL rom_ad : uv9; + + SIGNAL o1_hc,o1_vc,o2_hc,o2_vc : uv8; -- F0..F3 + SIGNAL o3_hc,o3_vc,o4_hc,o4_vc : uv8; -- F4..F7 + SIGNAL voffset : uv8; -- FC + SIGNAL r_0fd : uv8; -- FD + ALIAS r_freq : uv7 IS r_0fd(6 DOWNTO 0); -- Sound Frequency + ALIAS r_cm : std_logic IS r_0fd(7); -- Color mode + + SIGNAL r_0fe : uv8; -- FE + ALIAS hshift : uv3 IS r_0fe(7 DOWNTO 5); -- Character shift + ALIAS r_rng : std_logic IS r_0fe(4); -- Random noise + ALIAS r_sen : std_logic IS r_0fe(3); -- Sound enable + ALIAS r_loud : uv3 IS r_0fe(2 DOWNTO 0); -- Sound loudness + SIGNAL dmarow : uv4; -- FF -- DMA row + SIGNAL r_1f8 : uv8; + ALIAS r_gmode : std_logic IS r_1f8(7); -- Graphic mode + ALIAS r_ref : std_logic IS r_1f8(6); -- Resolution vert. + ALIAS r_acc : uv3 IS r_1f8(5 DOWNTO 3); -- Alternate Screen Colour + ALIAS r_asc : uv3 IS r_1f8(2 DOWNTO 0); -- Alternate Screen Colour + SIGNAL r_1f9 : uv8; + ALIAS r_cc : uv3 IS r_1f9(5 DOWNTO 3); -- Character Colour + ALIAS r_sc : uv3 IS r_1f9(2 DOWNTO 0); -- Screen Colour + ALIAS r_pmux : std_logic IS r_1f9(6); -- Pot mux + ALIAS r_csize : std_logic IS r_1f9(7); -- Character Size + SIGNAL r_1fa,r_1fb : uv8; + ALIAS o1_size : std_logic IS r_1fb(7); -- Object 1 size + ALIAS o2_size : std_logic IS r_1fb(6); -- Object 2 size + ALIAS o3_size : std_logic IS r_1fa(7); -- Object 3 size + ALIAS o4_size : std_logic IS r_1fa(6); -- Object 4 size + ALIAS o1_col : uv3 IS r_1fb(5 DOWNTO 3); -- Object 1 colour + ALIAS o2_col : uv3 IS r_1fb(2 DOWNTO 0); -- Object 2 colour + ALIAS o3_col : uv3 IS r_1fa(5 DOWNTO 3); -- Object 3 colour + ALIAS o4_col : uv3 IS r_1fa(2 DOWNTO 0); -- Object 4 colour + SIGNAL ccoll : uv4; -- Character collision + SIGNAL ocoll : uv6; -- Object collision + SIGNAL ocoll_clr,ocoll_pre,ccoll_clr,ccoll_pre : std_logic; + SIGNAL pot24, pot13 : uv8; + + SIGNAL o1_hit,o2_hit,o3_hit,o4_hit,bg_hit : std_logic; + SIGNAL o12_coll,o13_coll,o23_coll,o14_coll,o34_coll,o24_coll : std_logic; + SIGNAL o1c_coll,o2c_coll,o3c_coll,o4c_coll : std_logic; + + SIGNAL col_grb : uv3; + CONSTANT HOFFSET : natural := 32+11; -- ??? + + SIGNAL cyc : uint3; + SIGNAL vrle,vrle_pre,hrle,hrle_pre,hpulse : std_logic; + SIGNAL hpos,hlen,hsync,hdisp : uint9; + SIGNAL vpos,vlen,vsync,vdisp : uint9; + + SIGNAL gmode : std_logic; + + ------------------------------------------------ + SIGNAL lfsr : uv32; + SIGNAL stog : std_logic; + SIGNAL snd_cpt : uv7; + + ------------------------------------------------ + -- Read object/character + FUNCTION objadrs( + vpos : uint9; -- Spot vertical position + vc : uv8; -- Vertical coordinate object + size : std_logic; -- Object size + no : uint2) RETURN unsigned IS + VARIABLE ivc : natural := to_integer(vc); + BEGIN + IF size='0' THEN -- 16 lines + RETURN to_unsigned(384 + no*8 + (((vpos-ivc)/2) MOD 8), 10); + ELSE -- 8 lines + RETURN to_unsigned(384 + no*8 + (((vpos-ivc) ) MOD 8), 10); + END IF; + END FUNCTION objadrs; + + ------------------------------------------------ + FUNCTION objbit( + hpos : uint9; -- Spot horizontal position + hc : uv8 ) RETURN natural IS -- Horizontal coordinate object + VARIABLE a : uint3; + VARIABLE ihc : uint8 := to_integer(hc); + BEGIN + a:=(hpos-ihc) MOD 8; + RETURN 7-a; + END FUNCTION; + + ------------------------------------------------ + FUNCTION objhit( + hpos : uint9; -- Spot horizontal position + vpos : uint9; -- Spot vertical position + hc : uv8; -- Horizontal coordinate object + vc : uv8; -- Vertical coordinate object + size : std_logic) RETURN boolean IS -- Object size + VARIABLE ivc : uint8 := to_integer(vc); + VARIABLE ihc : uint8 := to_integer(hc); + BEGIN + + IF hc > 227 THEN + RETURN false; + ELSIF size='1' THEN -- Small + RETURN vpos>=ivc AND (vpos-ivc)<8 AND hpos>=ihc AND (hpos-ihc)<8; + ELSE -- High + RETURN vpos>=ivc AND (vpos-ivc)<16 AND hpos>=ihc AND (hpos-ihc)<8; + END IF; + END FUNCTION; + + ------------------------------------------------ + FUNCTION pix(g : std_logic; -- 0=Text 1=Graph + h : uint3; -- Horizontal offset + v : uint1; -- Vertical offset + d : uv8; -- Character font + c : uv8) RETURN boolean IS -- Character code (for graphics) + BEGIN + IF g='0' THEN + RETURN d(7-h)='1'; + ELSE + IF v=0 AND h<3 THEN RETURN c(2)='1'; + ELSIF v=1 AND h<3 THEN RETURN c(5)='1'; + ELSIF v=0 AND h<6 THEN RETURN c(1)='1'; + ELSIF v=1 AND h<6 THEN RETURN c(4)='1'; + ELSIF v=0 THEN RETURN c(0)='1'; + ELSE RETURN c(3)='1'; + END IF; + END IF; + END FUNCTION; + + ------------------------------------------------ + + SIGNAL xxx_bg : boolean; + +BEGIN + + ack<='1'; + + wreq<=wr AND req AND tick; + adi <="0" & ad(10 DOWNTO 0); + + dr<=dr_reg WHEN drreg_sel='1' ELSE dr_mem; + + Regs:PROCESS(clk,reset_na) IS + BEGIN + IF reset_na='0' THEN + ocoll_pre<='0'; + ccoll_pre<='0'; + + ELSIF rising_edge(clk) THEN + -------------------------------------------- + -- RAM + dr_mem<=ram(to_integer(adi(9 DOWNTO 0))); + + IF wreq='1' THEN + ram(to_integer(adi(9 DOWNTO 0)))<=dw; + END IF; + + -------------------------------------------- + -- Registers + drreg_sel<='0'; + dr_reg<=x"00"; + + CASE adi IS + WHEN x"0F0" => IF wreq='1' THEN o1_vc<=NOT dw; END IF; + WHEN x"0F1" => IF wreq='1' THEN o1_hc<=dw; END IF; + WHEN x"0F2" => IF wreq='1' THEN o2_vc<=NOT dw; END IF; + WHEN x"0F3" => IF wreq='1' THEN o2_hc<=dw; END IF; + WHEN x"0F4" => IF wreq='1' THEN o3_vc<=NOT dw; END IF; + WHEN x"0F5" => IF wreq='1' THEN o3_hc<=dw; END IF; + WHEN x"0F6" => IF wreq='1' THEN o4_vc<=NOT dw; END IF; + WHEN x"0F7" => IF wreq='1' THEN o4_hc<=dw; END IF; + WHEN x"0FC" => IF wreq='1' THEN voffset<=NOT dw - 1; END IF; + WHEN x"0FD" => IF wreq='1' THEN r_0fd<=dw; END IF; + WHEN x"0FE" => IF wreq='1' THEN r_0fe<=dw; END IF; + WHEN x"0FF" => dr_reg<="1111" & dmarow; drreg_sel<='1'; + WHEN x"1F8" => IF wreq='1' THEN r_1f8<=dw; END IF; + WHEN x"1F9" => IF wreq='1' THEN r_1f9<=dw; END IF; + WHEN x"1FA" => IF wreq='1' THEN r_1fa<=dw; END IF; + WHEN x"1FB" => IF wreq='1' THEN r_1fb<=dw; END IF; + WHEN x"1FC" => dr_reg<="1111" & ccoll; drreg_sel<='1'; -- Coll bg + WHEN x"1FD" => dr_reg<="11" & ocoll; drreg_sel<='1'; -- Coll obj + WHEN x"1FE" => dr_reg<=pot24; drreg_sel<='1'; -- POT24 + WHEN x"1FF" => dr_reg<=pot13; drreg_sel<='1'; -- POT13 + WHEN OTHERS => NULL; + END CASE; + + -------------------------------------------- + -- Collisions + IF (vrle_pre='1' AND vrle='0') OR ccoll_clr='1' THEN + ccoll<="1111"; + ELSE + ccoll<=ccoll AND NOT (o4c_coll & o3c_coll & o2c_coll & o1c_coll); + END IF; + + IF adi=x"1FC" AND req='1' AND tick='1' THEN + ccoll_pre<='1'; + END IF; + + ccoll_clr<='0'; + IF adi/=x"1FC" AND ccoll_pre='1' THEN + ccoll_clr<='1'; + ccoll_pre<='0'; + END IF; + + IF (vrle_pre='1' AND vrle='0') OR ocoll_clr='1' THEN + ocoll<="111111"; + ELSE + ocoll<=ocoll AND NOT (o34_coll & o24_coll & o23_coll & + o14_coll & o13_coll & o12_coll); + END IF; + + IF adi=x"1FD" AND req='1' AND tick='1' THEN + ocoll_pre<='1'; + END IF; + + ocoll_clr<='0'; + IF adi/=x"1FD" AND ocoll_pre='1' THEN + ocoll_clr<='1'; + ocoll_pre<='0'; + END IF; + + -------------------------------------------- + -- POT MUX + pot13<=mux(r_pmux,pot3,pot1); + pot24<=mux(r_pmux,pot4,pot2); + + -------------------------------------------- + END IF; + + END PROCESS Regs; + + ------------------------------------------------------------------------------ + -- Memory address mux + MadMux:PROCESS(ram_dr,vpos,voffset,hpos,hshift,r_csize, + o1_size,o2_size,o3_size,o4_size, + o1_vc,o2_vc,o3_vc,o4_vc,cyc) IS + BEGIN + + -- Character ROM + IF r_csize='1' THEN + rom_ad <= (ram_dr(5 DOWNTO 0) & "000") + ((vpos - voffset) MOD 8); + ELSE + rom_ad <= (ram_dr(5 DOWNTO 0) & "000") + ((vpos - voffset)/2 MOD 8); + END IF; + + IF (vpos) < 13*8 + to_integer(voffset) THEN + xxx_ad <=to_unsigned( + (hpos - HOFFSET - to_integer(hshift)) / 8 + + ((vpos - to_integer(voffset)) / 8) * 16,10); + ELSE + xxx_ad <=to_unsigned(512 + + (hpos - HOFFSET - to_integer(hshift)) / 8 + + ((vpos - to_integer(voffset)) / 8 - 13) * 16,10); + END IF; + + CASE cyc IS + WHEN 1 | 7 | 0 => -- Read text image + IF r_csize='1' THEN -- Small chars + IF vpos < 13*8 + to_integer(voffset) THEN + ram_ad <=to_unsigned( + (hpos - HOFFSET - to_integer(hshift)) / 8 + + ((vpos - to_integer(voffset)) / 8) * 16,10); + ELSE + ram_ad <=to_unsigned(512 + + (hpos - HOFFSET - to_integer(hshift)) / 8 + + ((vpos - to_integer(voffset)) / 8 - 13) * 16,10); + END IF; + + ELSE -- High chars + ram_ad <=to_unsigned( + (hpos - HOFFSET - to_integer(hshift)) / 8 + + ((vpos - to_integer(voffset)) / 16) * 16,10); + END IF; + + WHEN 2 => -- Read user character shape + IF r_csize='1' THEN + ram_ad <= to_unsigned(384 + to_integer(ram_dr(2 DOWNTO 0)) * 8 + + ((vpos - to_integer(voffset)) MOD 8),10); + ELSE + ram_ad <= to_unsigned(384 + to_integer(ram_dr(2 DOWNTO 0)) * 8 + + ((vpos - to_integer(voffset))/2 MOD 8),10); + END IF; + + WHEN 3 => -- Read object 1 shape + ram_ad <=objadrs(vpos,o1_vc,o1_size,0); + + WHEN 4 => + ram_ad <=objadrs(vpos,o2_vc,o2_size,1); + + WHEN 5 => + ram_ad <=objadrs(vpos,o3_vc,o3_size,2); + + WHEN 6 => + ram_ad <=objadrs(vpos,o4_vc,o4_size,3); + + END CASE; + + END PROCESS MadMux; + + ------------------------------------------------------------------------------ + + rom_dr<=CHARS(to_integer(rom_ad)) WHEN rising_edge (clk); + + Madar:PROCESS(clk) IS + BEGIN + IF rising_edge(clk) THEN + ram_dr<=ram(to_integer(ram_ad)); + END IF; + END PROCESS Madar; + + ------------------------------------------------------------------------------ + + Vid:PROCESS (clk,reset_na) IS + VARIABLE h,m : boolean; + VARIABLE i : natural RANGE 0 TO 7; + VARIABLE dm_v : uv8; + BEGIN + IF reset_na='0' THEN + NULL; + ELSIF rising_edge(clk) THEN + -------------------------------------------- + IF np='0' THEN + -- NTSC + hlen <=227; + hsync<=224; + hdisp<=222; + vlen <=262; + vsync<=253; + vdisp<=252; + ELSE + -- PAL + hlen <=284; + hsync<=280; + hdisp<=228; + vlen <=312; + vsync<=260; + vdisp<=252; + END IF; + + + hlen <=227; + hsync<=200; + hdisp<=184; + + vlen <=312; + vsync<=269; + vdisp<=268; + + vsync<=270; + + -------------------------------------------- + -- Collisions pulses + o12_coll<='0'; + o23_coll<='0'; + o34_coll<='0'; + o13_coll<='0'; + o14_coll<='0'; + o24_coll<='0'; + o1c_coll<='0'; + o2c_coll<='0'; + o3c_coll<='0'; + o4c_coll<='0'; + + hpulse<='0'; + + -------------------------------------------- + cyc<=(cyc+1) MOD 8; + + CASE cyc IS + WHEN 0 => -- Clear + IF hpos + -- Wait ! + NULL; + + WHEN 2 => + -- Character address + ch<=ram_dr; -- Current character + + WHEN 3 => + -- Read Char. map : ROM + user char + -- code charactère + -- image ROM + -- image user + -- position écran + -- paramètres : offset, hauteur, mode graphique + IF ch(5 DOWNTO 0)<"111000" THEN + dm_v:=rom_dr; + ELSE + dm_v:=ram_dr; -- User char. + END IF; + + m:=true; + + IF r_csize='0' OR r_ref='1' THEN -- Full scree + IF vpos=128 OR + vpos>=to_integer(voffset)+8*26 OR + hpos=16*8+HOFFSET+to_integer(hshift) THEN + m:=false; + END IF; + + ELSE -- Half, small chars + IF vpos=128 OR + vpos>=to_integer(voffset)+8*13 OR + hpos=16*8+HOFFSET+to_integer(hshift) THEN + m:=false; + END IF; + + END IF; + --IF r_csize='1' THEN -- 16x13 mode + -- IF vpos=128 OR + -- vpos>=to_integer(voffset)+16*13 OR + -- hpos=16*8+HOFFSET+to_integer(hshift) THEN + -- m:=false; + -- END IF; + --ELSE -- 16x26 mode + -- IF vpos=128 OR + -- (vpos>=8*13+to_integer(voffset) AND r_ref='0') OR + -- (vpos>=8*26+to_integer(voffset) AND r_ref='1') OR + -- hpos=16*8+HOFFSET+to_integer(hshift) THEN + -- m:=false; + -- END IF; + --END IF; + + xxx_bg<=m; + + IF ch=x"C0" AND m THEN -- Set GMODE special char + gmode<='1'; + h:=false; + + ELSIF ch=x"40" AND m THEN -- Clear GMODE special char + gmode<='0'; + h:=false; + + ELSIF r_csize='1' THEN -- 16x13 mode + h:=pix(gmode,(hpos-HOFFSET-to_integer(hshift)) MOD 8, + ((vpos-to_integer(voffset))/8) MOD 2,dm_v,ch); + ELSE -- 16x26 mode + h:=pix(gmode,(hpos-HOFFSET-to_integer(hshift)) MOD 8, + ((vpos-to_integer(voffset))/4) MOD 2,dm_v,ch); + END IF; + + bg_hit<=to_std_logic(h AND m); + + IF r_cm='0' THEN -- Character Color Mode = 0 + col_grb<=mux(h AND m,ch(7 DOWNTO 6) & r_cc(0),r_sc); + ELSE -- Character Color Mode = 1 + col_grb<=mux(h AND m,mux(ch(6),r_cc,r_acc),mux(ch(7),r_sc,r_asc)); + END IF; + + WHEN 4 => -- Object 1 + i:=7- ((hpos-to_integer(o1_hc)) MOD 8); + h:=objhit(hpos,vpos,o1_hc,o1_vc,o1_size); + + IF h AND ram_dr(i)='1' THEN + o1_hit<='1'; + col_grb<=o1_col; + END IF; + + WHEN 5 => -- Object 2 + i:=7- ((hpos-to_integer(o2_hc)) MOD 8); + h:=objhit(hpos,vpos,o2_hc,o2_vc,o2_size); + + IF h AND ram_dr(i)='1' THEN + o2_hit<='1'; + col_grb<=o2_col; + END IF; + + WHEN 6 => -- Object 3 + i:=7- ((hpos-to_integer(o3_hc)) MOD 8); + h:=objhit(hpos,vpos,o3_hc,o3_vc,o3_size); + + IF h AND ram_dr(i)='1' THEN + o3_hit<='1'; + col_grb<=o3_col; + END IF; + + WHEN 7 => -- Object 4 + i:=7- ((hpos-to_integer(o4_hc)) MOD 8); + h:=objhit(hpos,vpos,o4_hc,o4_vc,o4_size); + + IF h AND ram_dr(i)='1' THEN + o4_hit<='1'; + col_grb<=o4_col; + END IF; + + END CASE; + + vid_hsyn<=to_std_logic(hpos>hsync); + vid_vsyn<=to_std_logic(vpos>vsync); + vrle <=to_std_logic(vpos>vsync); + vrle_pre<=vrle; + hrle <=to_std_logic(hpos>hsync); + hrle_pre<=hrle; + vid_de <=to_std_logic(hpos Indirect indexé ++ / -- + +--INHERENT +-- FETCH EXE +-- A A+1 A+1 +-- OP OP2 OP2 + +--LOAD RELATIVE +-- FETCH IMM +-- A A+1 rDA A+2 A+3 +-- OP IMM DR OP + +--STORE RELATIVE +-- A A+1 wDA A+2 +-- OP IMM ___ OP + +-- A A+1 A+2 wDA +-- OP IMM IMM2 + + +-- LOAD ABSOLUTE +-- FETCH IMM IMM2 +-- A A+1 A+2 AD +-- OP IMM1 IMM2 DATA +-- WIDX WR + +-- STORE ABSOLUTE +-- A A+1 A+2 AD +-- OP IMM1 IMM2 +-- WIDX + +-- LOAD ABSOLUTE INDIRECT +-- A A+1 A+2 IX IX+1 AD +-- OP IMM1 IMM2 ABS1 ABS2 DATA +-- WIDX WR + +-- Si indexed (absolute indexed) +-- Base +-- Si indirect indexed, addition de l'index après indirection + +-------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +USE std.textio.ALL; + +LIBRARY work; +USE work.base_pack.ALL; +USE work.sgs2650_pack.ALL; + +ENTITY sgs2650 IS + GENERIC ( + VER_B : boolean :=false -- false=2650A, true=2650B + ); + PORT ( + req : OUT std_logic; + ack : IN std_logic; + ad : OUT uv15; -- Address bus + wr : OUT std_logic; + dw : OUT uv8; -- Data write + dr : IN uv8; -- Data read + mio : OUT std_logic; -- 1=Memory access 0=IO Port access + ene : OUT std_logic; -- 1=Extended / 0=Not Extended I/O + dc : OUT std_logic; -- 1=Data 0=Control I/O + + ph : OUT uv2; -- 00=CODE 01=DATA 10=INDIRECT 11=IO + + int : IN std_logic; + intack : OUT std_logic; + ivec : IN uv8; -- Interrupt vector + sense : IN std_logic; + flag : OUT std_logic; + + reset : IN std_logic; + + clk : IN std_logic; + reset_na : IN std_logic + ); +END ENTITY sgs2650; + +ARCHITECTURE rtl OF sgs2650 IS + + CONSTANT phCODE : uv2 :="00"; + CONSTANT phDATA : uv2 :="01"; + CONSTANT phINDIRECT : uv2 :="10"; + CONSTANT phIO : uv2 :="11"; + + ------------------------------------------------ + SIGNAL req_i,req_c : std_logic; + SIGNAL reqack : std_logic; + SIGNAL dw_i,dw_c : uv8; + SIGNAL ad_i,ad_c : uv15; + SIGNAL wr_i,wr_c : std_logic; + SIGNAL ph_i,ph_c : uv2; + SIGNAL rd_c : uv8; + SIGNAL nrd_c : uv2; + SIGNAL intp,intp_c : std_logic; + SIGNAL mio_c,ene_c,dc_c : std_logic; + SIGNAL rd_maj_c,pushsub_c,popsub_c : std_logic; + SIGNAL indexed_c,indexed : std_logic; + + TYPE enum_state IS (sOPCODE,sIMM,sIMM2,sINDIRECT,sINDIRECT2,sWAIT, + sDATA,sIO,sEXE,sINTER,sHALT); + SIGNAL state,state_c : enum_state; + + ------------------------------------------------ + SIGNAL iar,iar_c : uv15; -- Instruction Addres Register + SIGNAL r0,r1,r1b,r2,r2b,r3,r3b : uv8; -- Registers + TYPE arr_uv15 IS ARRAY (natural RANGE <>) OF uv15; + SIGNAL ras : arr_uv15(0 TO 7); -- Return Address Stack + SIGNAL rras : uv15; + SIGNAL psu,psl,psu_c,psl_c : uv8; -- Program Status Word + ALIAS psu_sp : uv3 IS psu(2 DOWNTO 0); -- Stack pointer + + ALIAS psu_ii : std_logic IS psu(5); -- Interrupt inhibit + ALIAS psu_ii_c : std_logic IS psu_c(5); -- Interrupt inhibit + + ALIAS psu_f : std_logic IS psu(6); -- Flag output + ALIAS psu_s : std_logic IS psu(7); -- Sense input + + ALIAS psl_rs : std_logic IS psl(4); -- Register Bank Select + ALIAS psl_idc : std_logic IS psl(5); -- Inter-Digit Carry + ALIAS psl_cc : uv2 IS psl(7 DOWNTO 6); -- Condition Code + + ------------------------------------------------ + SIGNAL ri : uv8; -- Instruction Register : Opcode + SIGNAL rh,rh_c : uv8; -- Holding Register : Second instruction byte + SIGNAL ru,ru_c : uv8; -- Holding Register : Second instruction byte + SIGNAL dec,dec_c : type_deco; -- Decoded opcode + + SIGNAL xxx_rs_v : uv8; + SIGNAL xxx_ph : string(1 TO 4); + SIGNAL xxx_indirect : std_logic; + SIGNAL ccnt : natural; + + ------------------------------------------------ + FILE fil : text OPEN write_mode IS "trace.log"; + +BEGIN + + Comb:PROCESS(dr,psl,psu,iar,state,req_i,ack, + r0,r1,r1b,r2,r2b,r3,r3b,ru,rras, + int,ivec,ph_i,intp,dec, + ad_i,wr_i,dw_i,ri,rh,indexed) IS + VARIABLE rs_v,rd_v,psl_v : uv8; + VARIABLE rd_mav : std_logic; + VARIABLE cond_v : boolean; + VARIABLE nrd_v : uv2; + VARIABLE dec_v : type_deco; + BEGIN + + rd_maj_c<='0'; + rd_c<=ri; + rd_v:=x"00"; + + pushsub_c<='0'; + popsub_c <='0'; + + psl_c<=psl; + psu_c<=psu; + iar_c<=iar; + state_c<=state; + dec_v:=dec; + + dec_c<=dec; + ad_c<=ad_i; + wr_c<=wr_i; + dw_c<=dw_i; + ph_c<=ph_i; + mio_c<='1'; -- Memory access as default + ene_c<=ri(2); -- Extended/non Extended IO access + dc_c <=ri(6); -- Data/Control IO access + rh_c<=rh; + ru_c<=ru; + indexed_c<=indexed; + req_c<='1'; + intp_c<=intp; + + --------------------------------------------- + -- Source register + IF state=sOPCODE THEN + CASE dr(1 DOWNTO 0) IS + WHEN "01" => rs_v:=mux(psl_rs,r1b,r1); + WHEN "10" => rs_v:=mux(psl_rs,r2b,r2); + WHEN "11" => rs_v:=mux(psl_rs,r3b,r3); + WHEN OTHERS => rs_v:=r0; + END CASE; + nrd_c<=dr(1 DOWNTO 0); + ELSE + CASE ri(1 DOWNTO 0) IS + WHEN "01" => rs_v:=mux(psl_rs,r1b,r1); + WHEN "10" => rs_v:=mux(psl_rs,r2b,r2); + WHEN "11" => rs_v:=mux(psl_rs,r3b,r3); + WHEN OTHERS => rs_v:=r0; + END CASE; + nrd_c<=ri(1 DOWNTO 0); + END IF; + + xxx_rs_v<=rs_v; + + cond_v:=(ri(1 DOWNTO 0)=psl_cc OR ri(1 DOWNTO 0)="11"); + psl_v:=psl; + + --------------------------------------------- + IF (req_i='1' AND ack='1') OR req_i='0' THEN + CASE state IS + -------------------------------------- + WHEN sOPCODE => + indexed_c<='0'; + iar_c<=iar+1; + ad_c<=iar+1; + wr_c<='0'; -- READ + dw_c<=x"00"; + ph_c<=phCODE; + intp_c<='0'; + + dec_v:=opcodes(to_integer(dr)); + dec_c<=dec_v; + IF int='1' AND psu_ii='0' THEN + state_c<=sINTER; + iar_c<=iar - 1; + -- Indirect ? + --iar_c<="00" & sext(ivec(6 DOWNTO 0),13); + ad_c <="00" & sext(ivec(6 DOWNTO 0),13); + + ELSIF dec_v.len>1 THEN + state_c<=sIMM; + ELSIF dec_v.ins=IO THEN + state_c<=sIO; + ad_c<="0000000" & x"00"; + dw_c<=rs_v; + IF dr(7)='1' THEN -- WRTC, WRTD, WRTE : Write IO + wr_c<='1'; + END IF; + mio_c<='0'; + ph_c<=phIO; + ELSE + state_c<=sEXE; + END IF; + + -------------------------------------- + WHEN sIMM => + -- Immediate, Relative or Absolute + iar_c<=iar+1; + ad_c<=iar+1; + wr_c<='0'; + dw_c<=rs_v; + ph_c<=phCODE; + rh_c<=dr; + ru_c<=dr; + + IF dec.len>2 THEN + state_c<=sIMM2; + ELSE + CASE dec.fmt IS + WHEN I | EI => -- IMMEDIATE + CASE dec.ins IS + WHEN ALU => -- rn = rn imm + state_c<=sOPCODE; + op_alu(ri,rs_v,dr,psl,rd_v,psl_v); + rd_maj_c<='1'; + rd_c<=rd_v; + psl_c<=psl_v; + + WHEN TMI => -- Test under Mask, Immediate (3cy) + state_c<=sWAIT; + op_tmi(rs_v,dr,psl,psl_v); + psl_c<=psl_v; + + WHEN IO => -- READ/WRITE EXTENDED IO + state_c <=sIO; + ad_c<="0000000" & dr; + dw_c<=rs_v; + IF ri(7)='1' THEN -- WRTC, WRTD, WRTE : Write IO + wr_c<='1'; + END IF; + mio_c<='0'; + ph_c<=phIO; + + WHEN CPPS => -- Clear/Preset Program Status Upper/Lower (3cy) + state_c<=sWAIT; + IF ri(1 DOWNTO 0)="00" THEN -- CPSU + psu_c<=psu AND NOT dr; + ELSIF ri(1 DOWNTO 0)="01" THEN -- CPSL + psl_c<=psl AND NOT dr; + ELSIF ri(1 DOWNTO 0)="10" THEN -- PPSU + psu_c<=psu OR dr; + ELSE -- PPSL + psl_c<=psl OR dr; + END IF; + + WHEN TPS => -- Test Program Status Upper / Lower (3cy) + state_c<=sWAIT; + IF (mux(ri(0),psl,psu) AND dr)=dr THEN + psl_c(7 DOWNTO 6)<="00"; + ELSE + psl_c(7 DOWNTO 6)<="10"; + END IF; + + WHEN OTHERS => -- IMPOSSIBLE + NULL; + + END CASE; + + WHEN R | ER => -- RELATIVE + dw_c<=rs_v; + ru_c(6 DOWNTO 5)<="00"; -- No indexed indirect + + CASE dec.ins IS + ------------------------------- + WHEN ALU => -- Add, Sub, And, Xor, Cmp, Load Relative + ad_c<=iar + sext(dr(6 DOWNTO 0),15) + 1; + IF dr(7)='1' THEN -- INDIRECT + state_c<=sINDIRECT; + ph_c<=phINDIRECT; + ELSE + state_c<=sDATA; + ph_c<=phDATA; + END IF; + + WHEN STR => -- Store Relative + ad_c<=iar + sext(dr(6 DOWNTO 0),15) + 1; + IF dr(7)='1' THEN -- INDIRECT + state_c<=sINDIRECT; + ph_c<=phINDIRECT; + ELSE + state_c<=sDATA; + ph_c<=phDATA; + wr_c<='1'; + END IF; + + -- Adresse relative = PC_instruction_suivante + Offset + + ------------------------------- + WHEN BCTF | -- Branch on condition True/False Relativ 18/98 + BRN | -- Branch on register non-zero, Relative 58 + BIDR => -- Branch on Inc / Dec Register, Relative D8/F8 + state_c<=sWAIT; + IF ri(7 DOWNTO 6)="11" THEN -- BIDR : Inc/Dec + IF ri(5)='0' THEN -- BRIR : INC + rd_v:=rs_v+1; + ELSE -- BDRR + rd_v:=rs_v-1; + END IF; + rd_maj_c<='1'; + END IF; + rd_c<=rd_v; + + IF (ri(7 DOWNTO 6)="00" AND cond_v) OR -- BCTR + (ri(7 DOWNTO 6)="10" AND NOT cond_v) OR -- BCFR + (ri(7 DOWNTO 6)="01" AND rs_v/=x"00") OR -- BRN + (ri(7 DOWNTO 6)="11" AND rd_v/=x"00") THEN -- BIDR + ad_c <=iar + sext(dr(6 DOWNTO 0),15) + 1; + iar_c<=iar + sext(dr(6 DOWNTO 0),15) + 1; + IF dr(7)='1' THEN -- INDIRECT + ph_c<=phINDIRECT; + state_c<=sINDIRECT; + ELSE + ph_c<=phCODE; + state_c<=sWAIT; + END IF; + ELSE + state_c<=sWAIT; + END IF; + + WHEN ZBRR => -- Zero Branch, Relative, unconditional + state_c<=sWAIT; + ad_c <="00" & sext(dr(6 DOWNTO 0),13); + iar_c<="00" & sext(dr(6 DOWNTO 0),13); + IF dr(7)='1' THEN -- INDIRECT + ph_c<=phINDIRECT; + state_c<=sINDIRECT; + ELSE + ph_c<=phCODE; + state_c<=sWAIT; + END IF; + + ------------------------------- + WHEN BSTF | -- Branch to sub on condition True/False Relative + BSN => -- Branch to sub on register non-zero, Relative + IF (ri(7 DOWNTO 6)="00" AND cond_v) OR -- BSTR + (ri(7 DOWNTO 6)="10" AND NOT cond_v) OR -- BSFR + (ri(7 DOWNTO 6)="01" AND rs_v/=x"00") THEN -- BSN + pushsub_c<='1'; + ad_c <=iar + sext(dr(6 DOWNTO 0),15) + 1; + iar_c<=iar + sext(dr(6 DOWNTO 0),15) + 1; + IF dr(7)='1' THEN -- INDIRECT + ph_c<=phINDIRECT; + state_c<=sINDIRECT; + ELSE + ph_c<=phCODE; + state_c<=sWAIT; + END IF; + ELSE + state_c<=sWAIT; + END IF; + + WHEN ZBSR => -- Zero Branch to Sub, Relative, unconditional + pushsub_c<='1'; + ad_c <="00" & sext(dr(6 DOWNTO 0),13); + iar_c<="00" & sext(dr(6 DOWNTO 0),13); + IF dr(7)='1' THEN -- INDIRECT + ph_c<=phINDIRECT; + state_c<=sINDIRECT; + ELSE + ph_c<=phCODE; + state_c<=sWAIT; + END IF; + + WHEN OTHERS => -- Impossible + NULL; + END CASE; + WHEN OTHERS => -- Impossible + NULL; + + END CASE; + END IF; + + -------------------------------------- + WHEN sIMM2 => + -- Absolute + iar_c<=iar+1; + ad_c<=iar+1; + wr_c<='0'; + dw_c<=rs_v; + + CASE dec.ins IS + ------------------------------- + WHEN ALU => + IF rh(7)='1' THEN + state_c<=sINDIRECT; + ad_c<=iar(14 DOWNTO 13) & rh(4 DOWNTO 0) & dr; + ph_c<=phINDIRECT; + ELSE + state_c<=sDATA; + ph_c<=phDATA; + CASE ru(6 DOWNTO 5) IS + WHEN "00" => -- No index + ad_c<=(iar(14 DOWNTO 13) & rh(4 DOWNTO 0) & dr); + indexed_c<='0'; + WHEN "01" => -- Pre increment indexed + rd_v:=rs_v+1; + rd_c<=rd_v; + rd_maj_c<='1'; + ad_c<=(iar(14 DOWNTO 13) & rh(4 DOWNTO 0) & dr) + rd_v; + indexed_c<='1'; + WHEN "10" => -- Pre decrement indexed + rd_v:=rs_v-1; + rd_c<=rd_v; + rd_maj_c<='1'; + ad_c<=(iar(14 DOWNTO 13) & rh(4 DOWNTO 0) & dr) + rd_v; + indexed_c<='1'; + WHEN OTHERS => -- Indexed + rd_v:=rs_v; + ad_c<=(iar(14 DOWNTO 13) & rh(4 DOWNTO 0) & dr) + rd_v; + indexed_c<='1'; + END CASE; + END IF; + + ------------------------------- + WHEN STR => + IF rh(7)='1' THEN + state_c<=sINDIRECT; + ad_c<=iar(14 DOWNTO 13) & rh(4 DOWNTO 0) & dr; + ph_c<=phINDIRECT; + ELSE + state_c<=sDATA; + ph_c<=phDATA; + -- Positionne bus data + wr_c<='1'; + CASE ru(6 DOWNTO 5) IS + WHEN "00" => -- No index + ad_c<=(iar(14 DOWNTO 13) & rh(4 DOWNTO 0) & dr); + dw_c<=rs_v; + indexed_c<='0'; + WHEN "01" => -- Auto increment indexed + rd_v:=rs_v+1; + rd_c<=rd_v; + rd_maj_c<='1'; + ad_c<=(iar(14 DOWNTO 13) & rh(4 DOWNTO 0) & dr) + rd_v; + dw_c<=r0; + IF ri(1 DOWNTO 0)="00" THEN + dw_c<=r0+1; + END IF; + indexed_c<='1'; + WHEN "10" => -- Auto decrement indexed + rd_v:=rs_v-1; + rd_c<=rd_v; + rd_maj_c<='1'; + ad_c<=(iar(14 DOWNTO 13) & rh(4 DOWNTO 0) & dr) + rd_v; + dw_c<=r0; + IF ri(1 DOWNTO 0)="00" THEN + dw_c<=r0-1; + END IF; + indexed_c<='1'; + WHEN OTHERS => -- Indexed + rd_v:=rs_v; + ad_c<=(iar(14 DOWNTO 13) & rh(4 DOWNTO 0) & dr) + rd_v; + dw_c<=r0; + indexed_c<='1'; + END CASE; + END IF; + + ------------------------------- + WHEN BCTF | -- Branch on condition True/False, Absolute + BRN | -- Branch on register non-zero, Absolute + BIDR => -- Branch on Inc / Dec Register, Absolute + IF ri(7 DOWNTO 6)="11" THEN + IF ri(5)='0' THEN -- BIRR + rd_v:=rs_v+1; + ELSE -- BDRR + rd_v:=rs_v-1; + END IF; + rd_maj_c<='1'; + END IF; + rd_c<=rd_v; + + IF (ri(7 DOWNTO 6)="00" AND cond_v) OR -- BCTA + (ri(7 DOWNTO 6)="10" AND NOT cond_v) OR -- BCFA + (ri(7 DOWNTO 6)="01" AND rs_v/=x"00") OR -- BRNA + (ri(7 DOWNTO 6)="11" AND rd_v/=x"00") THEN -- BIDA + iar_c<=rh(6 DOWNTO 0) & dr; + ad_c <=rh(6 DOWNTO 0) & dr; + IF rh(7)='1' THEN -- INDIRECT + ph_c <=phINDIRECT; + state_c<=sINDIRECT; + ELSE + ph_c <=phCODE; + state_c<=sOPCODE; + END IF; + ELSE + iar_c<=iar + 1; + state_c<=sOPCODE; + END IF; + + WHEN BXA => -- Branch indexed absolute, unconditional + IF rh(7)='1' THEN -- INDIRECT + state_c<=sINDIRECT; + ad_c <=rh(6 DOWNTO 0) & dr; + ph_c<=phINDIRECT; + ELSE + state_c<=sOPCODE; + iar_c<=(rh(6 DOWNTO 0) & dr) + rs_v; -- RS=R3 : Index + ad_c <=(rh(6 DOWNTO 0) & dr) + rs_v; + ph_c<=phCODE; + state_c<=sOPCODE; + END IF; + + ------------------------------- + WHEN BSTF | -- Branch to sub on condition True/False absolute + BSN => -- Branch to sub on register non-zero, absolute + IF (ri(7 DOWNTO 6)="00" AND cond_v) OR -- BSTA + (ri(7 DOWNTO 6)="10" AND NOT cond_v) OR -- BSFA + (ri(7 DOWNTO 6)="01" AND rs_v/=x"00") THEN -- BSN + pushsub_c<='1'; + IF rh(7)='1' THEN -- INDIRECT + state_c<=sINDIRECT; + ad_c<=rh(6 DOWNTO 0) & dr; + ph_c<=phINDIRECT; + ELSE + iar_c<=rh(6 DOWNTO 0) & dr; + ad_c <=rh(6 DOWNTO 0) & dr; + ph_c<=phCODE; + state_c<=sOPCODE; + END IF; + ELSE + iar_c<=iar + 1; + state_c<=sOPCODE; + END IF; + + WHEN BSXA => -- Branch to sub indexed absolute unconditional + pushsub_c<='1'; + IF rh(7)='1' THEN -- INDIRECT + state_c<=sINDIRECT; + ad_c<=rh(6 DOWNTO 0) & dr; + ph_c<=phINDIRECT; + ELSE + iar_c<=(rh(6 DOWNTO 0) & dr)+rs_v; + ad_c <=(rh(6 DOWNTO 0) & dr)+rs_v; + ph_c<=phCODE; + state_c<=sOPCODE; + END IF; + + WHEN OTHERS => -- Impossible + NULL; + END CASE; + + -------------------------------------- + -- DATA READ. Relative or absolute ALU op + WHEN sDATA => + state_c<=sOPCODE; + ph_c<=phCODE; + ad_c<=iar; + wr_c<='0'; + IF dec.ins=ALU THEN + IF indexed='1' THEN + -- Indexed: R0 = R0 [abs+Rn], No index: Rn = Rn [abs] + nrd_c<="00"; + rs_v:=r0; + END IF; + op_alu(ri,rs_v,dr,psl,rd_v,psl_v); + rd_maj_c<='1'; + rd_c<=rd_v; + psl_c<=psl_v; + + END IF; + -- STORE : Nothing to do, just default to fetch address + + -------------------------------------- + -- After I/O Access + WHEN sIO => + state_c<=sOPCODE; + IF ri(7)='0' THEN -- READ IO : REDE,REDD,REDC + rd_c<=dr; + rd_maj_c<='1'; + psl_c(7 DOWNTO 6)<=sign(dr); + END IF; + + -------------------------------------- + WHEN sINDIRECT => + state_c<=sINDIRECT2; + ad_c<=ad_i+1; + rh_c<=dr; + + WHEN sINDIRECT2 => + -- Indirect + ad_c<=iar; + dw_c<=rs_v; + + IF intp='1' THEN + state_c<=sOPCODE; + iar_c<=rh(6 DOWNTO 0) & dr; + ad_c <=rh(6 DOWNTO 0) & dr; + ph_c<=phCODE; + ELSE + + CASE dec.ins IS + ------------------------------- + WHEN ALU | STR => + state_c<=sDATA; + ph_c<=phDATA; + IF dec.ins=STR THEN + wr_c<='1'; + END IF; + + CASE ru(6 DOWNTO 5) IS + WHEN "00" => -- No index + ad_c<=(rh(6 DOWNTO 0) & dr); + dw_c<=rs_v; + indexed_c<='0'; + WHEN "01" => -- Pre increment indexed + rd_v:=rs_v+1; + rd_c<=rd_v; + rd_maj_c<='1'; + ad_c<=(rh(6 DOWNTO 0) & dr)+rd_v; + dw_c<=r0; + indexed_c<='1'; + WHEN "10" => -- Pre decrement indexed + rd_v:=rs_v-1; + rd_c<=rd_v; + rd_maj_c<='1'; + ad_c<=(rh(6 DOWNTO 0) & dr)+rd_v; + dw_c<=r0; + indexed_c<='1'; + WHEN OTHERS => -- Indexed + rd_v:=rs_v; + ad_c<=(rh(6 DOWNTO 0) & dr)+rd_v; + dw_c<=r0; + indexed_c<='1'; + END CASE; + + ------------------------------- + WHEN BCTF | -- Branch on condition True/False, Absolute + BRN | -- Branch on register non-zero, Absolute + BIDR | -- Branch on Inc / Dec Register, Absolute + BSTF | -- Branch to sub on condition True/False Relative + BSN => -- Branch to sub on register non-zero, Relative + state_c<=sOPCODE; + iar_c<=rh(6 DOWNTO 0) & dr; + ad_c <=rh(6 DOWNTO 0) & dr; + ph_c<=phCODE; + + WHEN BXA | -- Branch indexed absolute, unconditional + BSXA => -- Branch to sub indexed absolute unconditional + state_c<=sOPCODE; + iar_c<=(rh(6 DOWNTO 0) & dr)+rs_v; -- RS=R3 : Index + ad_c <=(rh(6 DOWNTO 0) & dr)+rs_v; + ph_c<=phCODE; + + WHEN OTHERS => + NULL; + + END CASE; + END IF; + -------------------------------------- + WHEN sEXE => -- Z & E + state_c<=sOPCODE; + + CASE dec.ins IS + WHEN ALU => -- R0=R0 Rn + nrd_c<="00"; + op_alu(ri,r0,rs_v,psl,rd_v,psl_v); + rd_maj_c<='1'; + rd_c<=rd_v; + psl_c<=psl_v; + + WHEN STR => -- Rn=R0 + rd_maj_c<='1'; + rd_c<=r0; + IF ri(1 DOWNTO 0)/="00" THEN -- NOP : No CC reg update + psl_c(7 DOWNTO 6)<=sign(r0); + END IF; + + WHEN ROT => -- Rn = Rotate(Rn) + op_rotate(ri,rs_v,rd_v,psl,psl_v); + rd_maj_c<='1'; + rd_c<=rd_v; + psl_c<=psl_v; + + WHEN DAR => + op_dar(rs_v,rd_v,psl,psl_v); + rd_maj_c<='1'; + rd_c<=rd_v; + psl_c<=psl_v; + state_c<=sWAIT; + + WHEN RET => -- Return from Subroutine, Conditional + IF cond_v THEN + iar_c<=rras; --ras(to_integer(psu_sp-1)); + ad_c <=rras; --ras(to_integer(psu_sp-1)); + popsub_c<='1'; + IF ri(5)='1' THEN -- RETE + psu_ii_c<='0'; + END IF; + END IF; + state_c<=sWAIT; + + WHEN SPS => -- Store Program Status Upper / Lower + nrd_c<="00"; + rd_maj_c<='1'; + rd_v:=mux(ri(0),psl,psu); + rd_c<=rd_v; + psl_c(7 DOWNTO 6)<=sign(rd_v); + + WHEN LPS => -- Load Program Status Upper / Lower + IF ri(0)='1' THEN + psl_c<=r0; + ELSE + psu_c<=r0; + END IF; + + WHEN HALT => + state_c<=sHALT; + + WHEN OTHERS => -- + NULL; + + END CASE; + + WHEN sWAIT => + state_c<=sOPCODE; + ph_c<=phCODE; + + -------------------------------------- + WHEN sINTER => + intp_c<='1'; + psu_ii_c<='1'; + pushsub_c<='1'; + ru_c<=x"00"; + iar_c<="00" & sext(ivec(6 DOWNTO 0),13); + ad_c <="00" & sext(ivec(6 DOWNTO 0),13); + IF ivec(7)='1' THEN -- INDIRECT + -- + iar_c<="00" & sext(dr(6 DOWNTO 0),13); + ad_c <="00" & sext(dr(6 DOWNTO 0),13); + state_c<=sINDIRECT; + ph_c<=phINDIRECT; + ELSE + ph_c<=phCODE; + state_c<=sOPCODE; + END IF; + -- ZBSR +03 + + -------------------------------------- + WHEN sHALT => + IF int='1' AND psu_ii='0' THEN + state_c<=sINTER; + END IF; + req_c<='0'; + + END CASE; + + --------------------------------------------- + END IF; + END PROCESS Comb; + + --############################################################################ + reqack<=req_c AND ack; + + Sync:PROCESS (clk,reset_na) IS + BEGIN + IF reset_na='0' THEN + iar<="000000000000000"; + psu_sp<="000"; + psu_ii<='0'; + +--pragma synthesis_off + r0<=x"00"; + r1<=x"00"; + r2<=x"00"; + r3<=x"00"; + r1b<=x"00"; + r2b<=x"00"; + r3b<=x"00"; +--pragma synthesis_on + + ELSIF rising_edge(clk) THEN + + -------------------------------------------- + state<=state_c; + + -------------------------------------------- + IF state=sOPCODE THEN + ri<=dr; + END IF; + + iar<=iar_c; + dec<=dec_c; + rh<=rh_c; + ru<=ru_c; + ph<=ph_c; + + indexed<=indexed_c; + intp<=intp_c; + intack<=to_std_logic(state=sINTER); + + ad_i<=ad_c; + wr_i<=wr_c; + dw_i<=dw_c; + ph_i<=ph_c; + req_i<=req_c; + + -------------------------------------------- + IF rd_maj_c='1' THEN + CASE nrd_c IS + WHEN "01" => + IF psl_rs='0' THEN r1<=rd_c; ELSE r1b<=rd_c; END IF; + WHEN "10" => + IF psl_rs='0' THEN r2<=rd_c; ELSE r2b<=rd_c; END IF; + WHEN "11" => + IF psl_rs='0' THEN r3<=rd_c; ELSE r3b<=rd_c; END IF; + WHEN OTHERS => + r0<=rd_c; + END CASE; + END IF; + + -------------------------------------------- + psl<=psl_c; + psu<=psu_c; + + --------------------------------------------- + IF pushsub_c='1' THEN + psu_sp<=psu(2 DOWNTO 0) + 1; + ras(to_integer(psu(2 DOWNTO 0)))<=iar + 1; + END IF; + + rras<=ras(to_integer(psu_sp-1)); + + IF popsub_c='1' THEN + psu_sp<=psu(2 DOWNTO 0) - 1; + END IF; + + -------------------------------------------- + psu(7)<=sense; + + -------------------------------------------- + IF reset='1' THEN + ad_i<=(OTHERS =>'0'); + iar<=(OTHERS =>'0'); + psu_ii<='0'; + psu_sp<="000"; + psl_rs<='0'; + psu(4 DOWNTO 3)<="00"; -- User Flags + state<=sOPCODE; + psu(6)<='0'; -- FLAG + END IF; + + IF NOT VER_B THEN -- User Flags fixed to 00 + psu(4 DOWNTO 3)<="00"; + END IF; + + END IF; + END PROCESS Sync; + + --############################################################################ + req<=req_c; + ad <=ad_c; + dw <=dw_c; + wr <=wr_c; + mio<=mio_c; + dc <=dc_c; + ene<=ene_c; + + flag<=psu(6); + + xxx_ph<="CODE" WHEN ph_c=phCODE ELSE + "DATA" WHEN ph_c=phDATA ELSE + "INDI" WHEN ph_c=phINDIRECT ELSE + "IO " WHEN ph_c=phIO ELSE + "XXXX"; + + xxx_indirect<=to_std_logic(ph_c=phINDIRECT) WHEN rising_edge(clk); + + + --pragma synthesis_off + --############################################################################ + -- Instruction trace + Trace:PROCESS IS + VARIABLE rd_v : std_logic :='0'; + VARIABLE csa ,csb ,csc,cst : string(1 TO 1000) :=(OTHERS =>NUL); + VARIABLE lout : line; + VARIABLE admem : uv15; + VARIABLE phmem : uv2; + VARIABLE ta,tb : uv8; + CONSTANT COND : string := "=><*"; + ----------------------------------------------- + PROCEDURE write(cs: INOUT string; s : IN string) IS + VARIABLE j,k : integer; + BEGIN + j:=-1; + FOR i IN 1 TO cs'length LOOP + IF cs(i)=nul THEN j:=i; EXIT; END IF; + END LOOP; + k:=s'length; + FOR i IN 1 TO s'length LOOP + IF s(i)=nul THEN k:=i; EXIT; END IF; + END LOOP; + + IF j>0 THEN + cs(j TO j+k-1):=s(1 TO k); + END IF; + END PROCEDURE write; + + FUNCTION strip(s : IN string) RETURN string IS + BEGIN + FOR i IN 1 TO s'length LOOP + IF s(i)=nul THEN RETURN s(1 TO i-1); END IF; + END LOOP; + RETURN s; + END FUNCTION; + + PROCEDURE pad(s : INOUT string; l : natural) IS + VARIABLE j : integer; + BEGIN + j:=-1; + FOR i IN 1 TO s'length LOOP + IF s(i)=nul THEN j:=i; EXIT; END IF; + END LOOP; + IF j>0 THEN + s(j TO l):=(OTHERS =>' '); + END IF; + END PROCEDURE; + ----------------------------------------------- + PROCEDURE waitdata IS + BEGIN + LOOP + wure(clk); + EXIT WHEN reqack='1'; + END LOOP; + write (csb,to_hstring(dr) & " "); + END PROCEDURE; + + TYPE arr_string4 IS ARRAY(natural RANGE <>) OF string(1 TO 4); + CONSTANT ph_txt : arr_string4(0 TO 3):=("CODE","DATA","INDI","IO "); + VARIABLE dec_v : type_deco; + ----------------------------------------------- + BEGIN + WAIT UNTIL reset_na='1'; + LOOP + wure(clk); + --IF rd_v='1' THEN + -- write(lout," RD("&to_hstring('0' & admem) &")=" & to_hstring(dr)); + -- write(lout," <" & ph_txt(to_integer(phmem)) & ">"); + -- write(lout," <" & time'image(now)); + -- writeline(fil,lout); + -- rd_v:='0'; + --END IF; + IF reqack='1' AND reset='0' THEN + IF state=sDATA THEN + IF wr_i='1' THEN + write(lout,";WR("&to_hstring('0' & ad_i) &")=" & to_hstring(dw_i)); + write(lout," <" & ph_txt(to_integer(ph_i)) & ">"); + write(lout," <" & time'image(now)); + writeline(fil,lout); + ELSE + rd_v:='1'; + admem:=ad_i; + phmem:=ph_i; + write(lout,";RD("&to_hstring('0' & admem) &")=" & to_hstring(dr)); + write(lout," <" & ph_txt(to_integer(phmem)) & ">"); + write(lout," <" & time'image(now)); + writeline(fil,lout); + rd_v:='0'; + END IF; + + ELSIF state=sINDIRECT OR state=sINDIRECT2 THEN + IF wr_i='1' THEN + write(lout,";WR("&to_hstring('0' & ad_i) &")=" & to_hstring(dw_i)); + write(lout," <" & ph_txt(to_integer(ph_i)) & ">"); + write(lout," <" & time'image(now)); + writeline(fil,lout); + ELSE + rd_v:='1'; + admem:=ad_i; + phmem:=ph_i; + write(lout,";RD("&to_hstring('0' & admem) &")=" & to_hstring(dr)); + write(lout," <" & ph_txt(to_integer(phmem)) & ">"); + write(lout," <" & time'image(now)); + writeline(fil,lout); + rd_v:='0'; + END IF; + + ELSIF state=sOPCODE AND int='1' AND psu_ii='0' THEN + write(lout,string'("### INT ###")); + writeline(fil,lout); + waitdata; + + ELSIF state=sOPCODE THEN + csa:=(OTHERS =>nul); + csb:=(OTHERS =>nul); + csc:=(OTHERS =>nul); + write (csa,to_hstring('0' & iar) & " : "); + write (csb,to_hstring(dr) & " "); + dec_v:=opcodes(to_integer(dr)); + write (csc,dec_v.dis); + -- New instruction; + CASE dec_v.fmt IS + WHEN Z | -- 1 Register Zero, register in [1:0] + E => -- 1 Misc, implicit + write(csc,string'(" ")); + + WHEN I | -- 2 Immediate, register in [1:0] + EI => -- 2 Immediate, no register + waitdata; + write(csc, " #" & to_hstring(dr)); + + WHEN R | -- 2 Relative, register in [1:0] + ER => -- 2 Relative, no register + waitdata; + write(csc, " #" & to_hstring(dr)); + IF dr(7)='1' THEN write (csc,string'(" ")); END IF; + + WHEN A => -- 3 Absolute, non branch, register in [1:0] + waitdata; + ta:=dr; + waitdata; + tb:=dr; + write(csc," >"); + IF ta(6 DOWNTO 5)="00" THEN -- Non indexed + write(csc,to_hstring((ta AND x"1F") & tb)); + ELSIF ta(6 DOWNTO 5)="01" THEN -- Auto increment + csc:=(OTHERS =>nul); + write(csc,dec_v.dis(1 TO 5) & "R0 " & " , " & + dec_v.dis(6 TO 7) & "+ + " & + to_hstring((ta AND x"1F") & tb)); + ELSIF ta(6 DOWNTO 5)="10" THEN -- Auto decrement + csc:=(OTHERS =>nul); + write(csc,dec_v.dis(1 TO 5) & "R0 " & " , " & + dec_v.dis(6 TO 7) & "- + " & + to_hstring((ta AND x"1F") & tb)); + ELSE -- Indexed + csc:=(OTHERS =>nul); + write(csc,dec_v.dis(1 TO 5) & "R0 " & " , " & + dec_v.dis(6 TO 7) & " + " & + to_hstring((ta AND x"1F") & tb)); + END IF; + IF ta(7)='1' THEN write (csc,string'(" ")); END IF; + + WHEN B | -- 3 Absolute, branch instruction + C | -- 3 (LDPL/STPL) + EB => -- 3 Absolute => branch, no register + waitdata; + ta:=dr; + write(csc," >" & to_hstring(dr)); + waitdata; + write(csc,to_hstring(dr) & ' '); + IF ta(7)='1' THEN write (csc,string'(" ")); END IF; + + END CASE; + + pad(csc,22); + write(csc," ; PSU=" & to_hstring(psu) & " PSL=" & to_hstring(psl) & + " " & COND(to_integer(psl(7 DOWNTO 6))+1) & + " | R0=" & to_hstring(r0) & " | " & to_hstring(r1) & + "," & to_hstring(r2) & "," & to_hstring(r3) & + " | " & to_hstring(r1b) & + "," & to_hstring(r2b) & "," & to_hstring(r3b)); + write(csc," " & integer'image(ccnt/8/12)); + write(csc," " & time'image(now)); + pad(csb,16); + + cst:=(OTHERS =>nul); + write(cst,csa); -- PC : + write(cst,csb); -- opcodes + write(cst,csc); -- Disas + write(lout,strip(cst)); + writeline(fil,lout); + END IF; + END IF; + END LOOP; + END PROCESS Trace; + + + ccnt<=0 WHEN reset_na='0' ELSE ccnt+1 WHEN rising_edge(clk); + +--pragma synthesis_on + + +END ARCHITECTURE rtl; + diff --git a/Console_MiST/Emerson Arcadia 2001_MiST/rtl/sgs2650_pack.vhd b/Console_MiST/Emerson Arcadia 2001_MiST/rtl/sgs2650_pack.vhd new file mode 100644 index 00000000..5b5cbd59 --- /dev/null +++ b/Console_MiST/Emerson Arcadia 2001_MiST/rtl/sgs2650_pack.vhd @@ -0,0 +1,598 @@ +-------------------------------------------------------------------------------- +-- +-- SGS2650 CPU +-------------------------------------------------------------------------------- + +-- Package : +-- - ALU operations +-- - Instruction decode + +-------------------------------------------------------------------------------- +-- DO 4/2018 +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- +-- This design can be used for any purpose. +-- Please send any bug report or remark to : dev@temlib.org +-------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY work; +USE work.base_pack.ALL; + +PACKAGE sgs2650_pack IS + TYPE enum_fmt IS ( + Z, -- 1 Register Zero, register in [1:0] + I, -- 2 Immediate, register in [1:0] + R, -- 2 Relative, register in [1:0] + A, -- 3 Absolute, non branch, register in [1:0] + B, -- 3 Absolute, branch instruction + C, -- 3 (LDPL/STPL) + E, -- 1 Misc, implicit + EI, -- 2 Immediate, no register + ER, -- 2 Relative, no register + EB); -- 3 Absolute, branch, no register + + TYPE enum_ins IS ( + STR, -- STR_ : Z.RA : Store + LDP, -- LDPL : C : Load program status lower from memory (2650-B) + STP, -- STPL : C : Store program status lower to memory (2650-B) + SPS, -- SPSU : E : Store program status upper + -- SPSL : E : Store program status lower + LPS, -- LPSU : E : Load program status, upper + -- LPSL : E : Load program status, lower + CPPS, -- CPSU : EI : Clear program status Upper, Masked + -- CPSL : EI : Clear program status Lower, Masked + -- PPSU : EI : Preset program status Upper, Masked + -- PPSL : EI : Preset program status Lower, Masked + TPS, -- TPSU : EI : Test Program Status Upper, Masked + -- TPSL : EI : Test Program Status Lower, Masked + + ALU, -- LOD_ : ZIRA : Load + -- EOR_ : ZIRA : Exclusive Or + -- IOR_ : ZIRA : Or + -- AND_ : ZIRA : And + -- ADD_ : ZIRA : Add + -- SUB_ : ZIRA : Sub + -- COM_ : ZIRA : Compare + ROT, -- RRR : Z : Rotate Register Right + -- RRL : Z : Rotate Register Left + TMI, -- TMI : I : Test Under Mask, Immediate + DAR, -- DAR : Z : Decimal Adjust Register + + BSTF, -- BST_ : RB : Branch to Sub on Condition True + -- BSF_ : RB : Branch to Sub on Condition false + HALT, -- HALT : E : Halt, enter wait state + + IO , -- REDE : I : Read Extended + -- REDD : Z : Read Data + -- REDC : Z : Read Control + -- WRTC : Z : Write Control + -- WRTE : I : Write Extended + -- WRTD : Z : Write Data + BCTF, -- BCT_ : RB : Branch on Condition True + -- BCF_ : RB : Branch on Condition False + BRN, -- BRN_ : RB : Branch on Register non-zero + BIDR, -- BIR_ : RB : Branch on Incrementing Register + -- BDR_ : RB : Branch on Decrementing Register + BXA, -- BXA : EB : Branch indexed absolute, unconditional + ZBRR, -- ZBRR : ER : Zero Branch, Relative, unconditional + + BSN, -- BSN_ : RB : Branch to sub on non-zero reg + BSXA, -- BSXA : EB : Branch to Sub indexed absolute unconditional + ZBSR, -- ZBSR : ER : Zero branch to sub relative unconditional + + RET -- RETC : Z : Return from Subroutine, Conditional + -- RETE : Z : Return from Sub and Enable Int, Conditional + ); + + TYPE type_deco IS RECORD + dis : string(1 TO 7); -- TRACE : Instruction + fmt : enum_fmt; -- Instruction format (addressing mode) + ins : enum_ins; -- Instruction type + len : natural RANGE 1 TO 3; -- Instruction lenght + cycles : natural RANGE 0 TO 4; -- Instruction time + END RECORD; + TYPE arr_deco IS ARRAY (natural RANGE <>) OF type_deco; + + CONSTANT opcodes:arr_deco(0 TO 255):=( + ("LODZ R0", Z,ALU ,1,2), -- 00 + ("LODZ R1", Z,ALU ,1,2), -- 01 Load, Register Zero (1 cycle -B) + ("LODZ R2", Z,ALU ,1,2), -- 02 Load, Register Zero (1 cycle -B) + ("LODZ R3", Z,ALU ,1,2), -- 03 Load, Register Zero (1 cycle -B) + ("LODI R0", I,ALU ,2,2), -- 04 Load, Immediate + ("LODI R1", I,ALU ,2,2), -- 05 Load, Immediate + ("LODI R2", I,ALU ,2,2), -- 06 Load, Immediate + ("LODI R3", I,ALU ,2,2), -- 07 Load, Immediate + ("LODR R0", R,ALU ,2,3), -- 08 Load, Relative + ("LODR R1", R,ALU ,2,3), -- 09 Load, Relative + ("LODR R2", R,ALU ,2,3), -- 0A Load, Relative + ("LODR R3", R,ALU ,2,3), -- 0B Load, Relative + ("LODA R0", A,ALU ,3,4), -- 0C Load, Absolute + ("LODA R1", A,ALU ,3,4), -- 0D Load, Absolute + ("LODA R2", A,ALU ,3,4), -- 0E Load, Absolute + ("LODA R3", A,ALU ,3,4), -- 0F Load, Absolute + ("LDPL ", C,LDP ,3,4), -- 10 Load program status lower from mem (-B) + ("STPL ", C,STP ,3,4), -- 11 Store program status lower to mem (-B) + ("SPSU ", E,SPS ,1,2), -- 12 Store program status upper + ("SPSL ", E,SPS ,1,2), -- 13 Store program status lower + ("RETC =", Z,RET ,1,3), -- 14 Return from Subroutine, Conditional + ("RETC >", Z,RET ,1,3), -- 15 Return from Subroutine, Conditional + ("RETC <", Z,RET ,1,3), -- 16 Return from Subroutine, Conditional + ("RETC *", Z,RET ,1,3), -- 17 Return from Subroutine, Conditional + ("BCTR =", R,BCTF,2,3), -- 18 Branch on Condition True, Relative + ("BCTR >", R,BCTF,2,3), -- 19 Branch on Condition True, Relative + ("BCTR <", R,BCTF,2,3), -- 1A Branch on Condition True, Relative + ("BCTR *", R,BCTF,2,3), -- 1B Branch on Condition True, Relative + ("BCTA =", B,BCTF,3,3), -- 1C Branch on Condition True, Absolute + ("BCTA >", B,BCTF,3,3), -- 1D Branch on Condition True, Absolute + ("BCTA <", B,BCTF,3,3), -- 1E Branch on Condition True, Absolute + ("BCTA *", B,BCTF,3,3), -- 1F Branch on Condition True, Absolute + ("EORZ R0", Z,ALU ,1,2), -- 20 Exclusive Or, Register Zero (1 cycle -B) + ("EORZ R1", Z,ALU ,1,2), -- 21 Exclusive Or, Register Zero (1 cycle -B) + ("EORZ R2", Z,ALU ,1,2), -- 22 Exclusive Or, Register Zero (1 cycle -B) + ("EORZ R3", Z,ALU ,1,2), -- 23 Exclusive Or, Register Zero (1 cycle -B) + ("EORI R0", I,ALU ,2,2), -- 24 Exclusive Or, Immediate + ("EORI R1", I,ALU ,2,2), -- 25 Exclusive Or, Immediate + ("EORI R2", I,ALU ,2,2), -- 26 Exclusive Or, Immediate + ("EORI R3", I,ALU ,2,2), -- 27 Exclusive Or, Immediate + ("EORR R0", R,ALU ,2,3), -- 28 Exclusive Or, Relative + ("EORR R1", R,ALU ,2,3), -- 29 Exclusive Or, Relative + ("EORR R2", R,ALU ,2,3), -- 2A Exclusive Or, Relative + ("EORR R3", R,ALU ,2,3), -- 2B Exclusive Or, Relative + ("EORA R0", A,ALU ,3,4), -- 2C Exclusive Or, Absolute + ("EORA R1", A,ALU ,3,4), -- 2D Exclusive Or, Absolute + ("EORA R2", A,ALU ,3,4), -- 2E Exclusive Or, Absolute + ("EORA R3", A,ALU ,3,4), -- 2F Exclusive Or, Absolute + ("REDC R0", Z,IO ,1,2), -- 30 Read Control + ("REDC R1", Z,IO ,1,2), -- 31 Read Control + ("REDC R2", Z,IO ,1,2), -- 32 Read Control + ("REDC R3", Z,IO ,1,2), -- 33 Read Control + ("RETE =", Z,RET ,1,3), -- 34 Return from Sub and Enable Int, Conditional + ("RETE >", Z,RET ,1,3), -- 35 Return from Sub and Enable Int, Conditional + ("RETE <", Z,RET ,1,3), -- 36 Return from Sub and Enable Int, Conditional + ("RETE *", Z,RET ,1,3), -- 37 Return from Sub and Enable Int, Conditional + ("BSTR =", R,BSTF,2,3), -- 38 Branch to Sub on Condition True, Relative + ("BSTR >", R,BSTF,2,3), -- 39 Branch to Sub on Condition True, Relative + ("BSTR <", R,BSTF,2,3), -- 3A Branch to Sub on Condition True, Relative + ("BSTR *", R,BSTF,2,3), -- 3B Branch to Sub on Condition True, Relative + ("BSTA =", B,BSTF,3,3), -- 3C Branch to Sub on Condition True, Absolute + ("BSTA >", B,BSTF,3,3), -- 3D Branch to Sub on Condition True, Absolute + ("BSTA <", B,BSTF,3,3), -- 3E Branch to Sub on Condition True, Absolute + ("BSTA *", B,BSTF,3,3), -- 3F Branch to Sub on Condition True, Absolute + ("HALT ", E,HALT,1,2), -- 40 Halt, enter wait state + ("ANDZ R1", Z,ALU ,1,2), -- 41 And, Register Zero (1 cycle -B) + ("ANDZ R2", Z,ALU ,1,2), -- 42 And, Register Zero (1 cycle -B) + ("ANDZ R3", Z,ALU ,1,2), -- 43 And, Register Zero (1 cycle -B) + ("ANDI R0", I,ALU ,2,2), -- 44 And, Immediate + ("ANDI R1", I,ALU ,2,2), -- 45 And, Immediate + ("ANDI R2", I,ALU ,2,2), -- 46 And, Immediate + ("ANDI R3", I,ALU ,2,2), -- 47 And, Immediate + ("ANDR R0", R,ALU ,2,3), -- 48 And, Relative + ("ANDR R1", R,ALU ,2,3), -- 49 And, Relative + ("ANDR R2", R,ALU ,2,3), -- 4A And, Relative + ("ANDR R3", R,ALU ,2,3), -- 4B And, Relative + ("ANDA R0", A,ALU ,3,4), -- 4C And, Absolute + ("ANDA R1", A,ALU ,3,4), -- 4D And, Absolute + ("ANDA R2", A,ALU ,3,4), -- 4E And, Absolute + ("ANDA R3", A,ALU ,3,4), -- 4F And, Absolute + ("RRR R0", Z,ROT ,1,2), -- 50 Rotate Register Right + ("RRR R1", Z,ROT ,1,2), -- 51 Rotate Register Right + ("RRR R2", Z,ROT ,1,2), -- 52 Rotate Register Right + ("RRR R3", Z,ROT ,1,2), -- 53 Rotate Register Right + ("REDE R0", I,IO ,2,3), -- 54 Read Extended + ("REDE R1", I,IO ,2,3), -- 55 Read Extended + ("REDE R2", I,IO ,2,3), -- 56 Read Extended + ("REDE R3", I,IO ,2,3), -- 57 Read Extended + ("BRNR R0", R,BRN ,2,3), -- 58 Branch on Register non-zero, Relative + ("BRNR R1", R,BRN ,2,3), -- 59 Branch on Register non-zero, Relative + ("BRNR R2", R,BRN ,2,3), -- 5A Branch on Register non-zero, Relative + ("BRNR R3", R,BRN ,2,3), -- 5B Branch on Register non-zero, Relative + ("BRNA R0", B,BRN ,3,3), -- 5C Branch on Register non-zero, Absolute + ("BRNA R1", B,BRN ,3,3), -- 5D Branch on Register non-zero, Absolute + ("BRNA R2", B,BRN ,3,3), -- 5E Branch on Register non-zero, Absolute + ("BRNA R3", B,BRN ,3,3), -- 5F Branch on Register non-zero, Absolute + ("IORZ R0", Z,ALU ,1,2), -- 60 Or, Register Zero (1 cycle -B) + ("IORZ R1", Z,ALU ,1,2), -- 61 Or, Register Zero (1 cycle -B) + ("IORZ R2", Z,ALU ,1,2), -- 62 Or, Register Zero (1 cycle -B) + ("IORZ R3", Z,ALU ,1,2), -- 63 Or, Register Zero (1 cycle -B) + ("IORI R0", I,ALU ,2,2), -- 64 Or, Immediate + ("IORI R1", I,ALU ,2,2), -- 65 Or, Immediate + ("IORI R2", I,ALU ,2,2), -- 66 Or, Immediate + ("IORI R3", I,ALU ,2,2), -- 67 Or, Immediate + ("IORR R0", R,ALU ,2,3), -- 68 Or, Relative + ("IORR R1", R,ALU ,2,3), -- 69 Or, Relative + ("IORR R2", R,ALU ,2,3), -- 6A Or, Relative + ("IORR R3", R,ALU ,2,3), -- 6B Or, Relative + ("IORA R0", A,ALU ,3,4), -- 6C Or, Absolute + ("IORA R1", A,ALU ,3,4), -- 6D Or, Absolute + ("IORA R2", A,ALU ,3,4), -- 6E Or, Absolute + ("IORA R3", A,ALU ,3,4), -- 6F Or, Absolute + ("REDD R0", Z,IO ,1,2), -- 70 Read Data + ("REDD R1", Z,IO ,1,2), -- 71 Read Data + ("REDD R2", Z,IO ,1,2), -- 72 Read Data + ("REDD R3", Z,IO ,1,2), -- 73 Read Data + ("CPSU ",EI,CPPS,2,3), -- 74 Clear program status Upper, Masked + ("CPSL ",EI,CPPS,2,3), -- 75 Clear program status Lower, Masked + ("PPSU ",EI,CPPS,2,3), -- 76 Preset program status Upper, Masked + ("PPSL ",EI,CPPS,2,3), -- 77 Preset program status Lower, Masked + ("BSNR R0", R,BSN ,2,3), -- 78 Branch to sub on non-zero reg, Relative + ("BSNR R1", R,BSN ,2,3), -- 79 Branch to sub on non-zero reg, Relative + ("BSNR R2", R,BSN ,2,3), -- 7A Branch to sub on non-zero reg, Relative + ("BSNR R3", R,BSN ,2,3), -- 7B Branch to sub on non-zero reg, Relative + ("BSNA R0", B,BSN ,3,3), -- 7C Branch to sub on non-zero reg, Absolute + ("BSNA R1", B,BSN ,3,3), -- 7D Branch to sub on non-zero reg, Absolute + ("BSNA R2", B,BSN ,3,3), -- 7E Branch to sub on non-zero reg, Absolute + ("BSNA R3", B,BSN ,3,3), -- 7F Branch to sub on non-zero reg, Absolute + ("ADDZ R0", Z,ALU ,1,2), -- 80 Add, Register Zero (1 cycle -B) + ("ADDZ R1", Z,ALU ,1,2), -- 81 Add, Register Zero (1 cycle -B) + ("ADDZ R2", Z,ALU ,1,2), -- 82 Add, Register Zero (1 cycle -B) + ("ADDZ R3", Z,ALU ,1,2), -- 83 Add, Register Zero (1 cycle -B) + ("ADDI R0", I,ALU ,2,2), -- 84 Add, Immediate + ("ADDI R1", I,ALU ,2,2), -- 85 Add, Immediate + ("ADDI R2", I,ALU ,2,2), -- 86 Add, Immediate + ("ADDI R3", I,ALU ,2,2), -- 87 Add, Immediate + ("ADDR R0", R,ALU ,2,3), -- 88 Add, Relative + ("ADDR R1", R,ALU ,2,3), -- 89 Add, Relative + ("ADDR R2", R,ALU ,2,3), -- 8A Add, Relative + ("ADDR R3", R,ALU ,2,3), -- 8B Add, Relative + ("ADDA R0", A,ALU ,3,4), -- 8C Add, Absolute + ("ADDA R1", A,ALU ,3,4), -- 8D Add, Absolute + ("ADDA R2", A,ALU ,3,4), -- 8E Add, Absolute + ("ADDA R3", A,ALU ,3,4), -- 8F Add, Absolute + ("INVALID", E,LPS ,1,2), -- 90 + ("INVALID", E,LPS ,1,2), -- 91 + ("LPSU ", E,LPS ,1,2), -- 92 Load program status, upper + ("LPSL ", E,LPS ,1,2), -- 93 Load program status, lower + ("DAR R0", Z,DAR ,1,3), -- 94 Decimal Adjust Register + ("DAR R1", Z,DAR ,1,3), -- 95 Decimal Adjust Register + ("DAR R2", Z,DAR ,1,3), -- 96 Decimal Adjust Register + ("DAR R3", Z,DAR ,1,3), -- 97 Decimal Adjust Register + ("BCFR =", R,BCTF,2,3), -- 98 Branch on Condition False, Relative + ("BCFR >", R,BCTF,2,3), -- 99 Branch on Condition False, Relative + ("BCFR <", R,BCTF,2,3), -- 9A Branch on Condition False, Relative + ("ZBRR ",ER,ZBRR,2,3), -- 9B Zero Branch, Relative, unconditional + ("BCFA =", B,BCTF,3,3), -- 9C Branch on Condition False, Absolute + ("BCFA >", B,BCTF,3,3), -- 9D Branch on Condition False, Absolute + ("BCFA <", B,BCTF,3,3), -- 9E Branch on Condition False, Absolute + ("BXA R3",EB,BXA ,3,3), -- 9F Branch indexed absolute, unconditional + ("SUBZ R0", Z,ALU ,1,2), -- A0 Subtract, Register Zero (1 cycle -B) + ("SUBZ R1", Z,ALU ,1,2), -- A1 Subtract, Register Zero (1 cycle -B) + ("SUBZ R2", Z,ALU ,1,2), -- A2 Subtract, Register Zero (1 cycle -B) + ("SUBZ R3", Z,ALU ,1,2), -- A3 Subtract, Register Zero (1 cycle -B) + ("SUBI R0", I,ALU ,2,2), -- A4 Subtract, Immediate + ("SUBI R1", I,ALU ,2,2), -- A5 Subtract, Immediate + ("SUBI R2", I,ALU ,2,2), -- A6 Subtract, Immediate + ("SUBI R3", I,ALU ,2,2), -- A7 Subtract, Immediate + ("SUBR R0", R,ALU ,2,3), -- A8 Subtract, Relative + ("SUBR R1", R,ALU ,2,3), -- A9 Subtract, Relative + ("SUBR R2", R,ALU ,2,3), -- AA Subtract, Relative + ("SUBR R3", R,ALU ,2,3), -- AB Subtract, Relative + ("SUBA R0", A,ALU ,3,4), -- AC Subtract, Absolute + ("SUBA R1", A,ALU ,3,4), -- AD Subtract, Absolute + ("SUBA R2", A,ALU ,3,4), -- AE Subtract, Absolute + ("SUBA R3", A,ALU ,3,4), -- AF Subtract, Absolute + ("WRTC R0", Z,IO ,1,2), -- B0 Write Control + ("WRTC R1", Z,IO ,1,2), -- B1 Write Control + ("WRTC R2", Z,IO ,1,2), -- B2 Write Control + ("WRTC R3", Z,IO ,1,2), -- B3 Write Control + ("TPSU ",EI,TPS ,2,3), -- B4 Test Program Status Upper, Masked + ("TPSL ",EI,TPS ,2,3), -- B5 Test Program Status Lower, Masked + ("INVALID",EI,TPS ,2,3), -- B6 + ("INVALID",EI,TPS ,2,3), -- B7 + ("BSFR 0", R,BSTF,2,3), -- B8 Branch to Sub on Condition false, Relative + ("BSFR 1", R,BSTF,2,3), -- B9 Branch to Sub on Condition false, Relative + ("BSFR 2", R,BSTF,2,3), -- BA Branch to Sub on Condition false, Relative + ("ZBSR ",ER,ZBSR,2,3), -- BB Zero branch to sub relative unconditional + ("BSFA 0", B,BSTF,3,3), -- BC Branch to Sub on Condition false, Absolute + ("BSFA 1", B,BSTF,3,3), -- BD Branch to Sub on Condition false, Absolute + ("BSFA 2", B,BSTF,3,3), -- BE Branch to Sub on Condition false, Absolute + ("BSXA ",EB,BSXA,3,3), -- BF Branch to Sub indexed absolute unconditional + ("NOP ", Z,STR ,1,2), -- C0 No Operation + ("STRZ R1", Z,STR ,1,2), -- C1 Store, Register Zero (1 cycle -B) + ("STRZ R2", Z,STR ,1,2), -- C2 Store, Register Zero (1 cycle -B) + ("STRZ R3", Z,STR ,1,2), -- C3 Store, Register Zero (1 cycle -B) + ("INVALID", I,STR ,2,2), -- C4 + ("INVALID", I,STR ,2,2), -- C5 + ("INVALID", I,STR ,2,2), -- C6 + ("INVALID", I,STR ,2,2), -- C7 + ("STRR R0", R,STR ,2,3), -- C8 Store, Relative + ("STRR R1", R,STR ,2,3), -- C9 Store, Relative + ("STRR R2", R,STR ,2,3), -- CA Store, Relative + ("STRR R3", R,STR ,2,3), -- CB Store, Relative + ("STRA R0", A,STR ,3,4), -- CC Store, Absolute + ("STRA R1", A,STR ,3,4), -- CD Store, Absolute + ("STRA R2", A,STR ,3,4), -- CE Store, Absolute + ("STRA R3", A,STR ,3,4), -- CF Store, Absolute + ("RRL R0", Z,ROT ,1,2), -- D0 Rotate Register Left + ("RRL R1", Z,ROT ,1,2), -- D1 Rotate Register Left + ("RRL R2", Z,ROT ,1,2), -- D2 Rotate Register Left + ("RRL R3", Z,ROT ,1,2), -- D3 Rotate Register Left + ("WRTE R0", I,IO ,2,3), -- D4 Write Extended + ("WRTE R1", I,IO ,2,3), -- D5 Write Extended + ("WRTE R2", I,IO ,2,3), -- D6 Write Extended + ("WRTE R3", I,IO ,2,3), -- D7 Write Extended + ("BIRR R0", R,BIDR,2,3), -- D8 Branch on Incrementing Register, Relative + ("BIRR R1", R,BIDR,2,3), -- D9 Branch on Incrementing Register, Relative + ("BIRR R2", R,BIDR,2,3), -- DA Branch on Incrementing Register, Relative + ("BIRR R3", R,BIDR,2,3), -- DB Branch on Incrementing Register, Relative + ("BIRA R0", B,BIDR,3,3), -- DC Branch on Incrementing Register, Absolute + ("BIRA R1", B,BIDR,3,3), -- DD Branch on Incrementing Register, Absolute + ("BIRA R2", B,BIDR,3,3), -- DE Branch on Incrementing Register, Absolute + ("BIRA R3", B,BIDR,3,3), -- DF Branch on Incrementing Register, Absolute + ("COMZ R0", Z,ALU ,1,2), -- E0 Compare, Register Zero (1 cycle -B) + ("COMZ R1", Z,ALU ,1,2), -- E1 Compare, Register Zero (1 cycle -B) + ("COMZ R2", Z,ALU ,1,2), -- E2 Compare, Register Zero (1 cycle -B) + ("COMZ R3", Z,ALU ,1,2), -- E3 Compare, Register Zero (1 cycle -B) + ("COMI R0", I,ALU ,2,2), -- E4 Compare, Immediate + ("COMI R1", I,ALU ,2,2), -- E5 Compare, Immediate + ("COMI R2", I,ALU ,2,2), -- E6 Compare, Immediate + ("COMI R3", I,ALU ,2,2), -- E7 Compare, Immediate + ("COMR R0", R,ALU ,2,3), -- E8 Compare, Relative + ("COMR R1", R,ALU ,2,3), -- E9 Compare, Relative + ("COMR R2", R,ALU ,2,3), -- EA Compare, Relative + ("COMR R3", R,ALU ,2,3), -- EB Compare, Relative + ("COMA R0", A,ALU ,3,4), -- EC Compare, Absolute + ("COMA R1", A,ALU ,3,4), -- ED Compare, Absolute + ("COMA R2", A,ALU ,3,4), -- EE Compare, Absolute + ("COMA R3", A,ALU ,3,4), -- EF Compare, Absolute + ("WRTD R0", Z,IO ,1,2), -- F0 Write Data + ("WRTD R1", Z,IO ,1,2), -- F1 Write Data + ("WRTD R2", Z,IO ,1,2), -- F2 Write Data + ("WRTD R3", Z,IO ,1,2), -- F3 Write Data + ("TMI R0", I,TMI ,2,3), -- F4 Test Under Mask, Immediate + ("TMI R1", I,TMI ,2,3), -- F5 Test Under Mask, Immediate + ("TMI R2", I,TMI ,2,3), -- F6 Test Under Mask, Immediate + ("TMI R3", I,TMI ,2,3), -- F7 Test Under Mask, Immediate + ("BDRR R0", R,BIDR,2,3), -- F8 Branch on Decrementing Register, Relative + ("BDRR R1", R,BIDR,2,3), -- F9 Branch on Decrementing Register, Relative + ("BDRR R2", R,BIDR,2,3), -- FA Branch on Decrementing Register, Relative + ("BDRR R3", R,BIDR,2,3), -- FB Branch on Decrementing Register, Relative + ("BDRA R0", B,BIDR,3,3), -- FC Branch on Decrementing Register, Absolute + ("BDRA R1", B,BIDR,3,3), -- FD Branch on Decrementing Register, Absolute + ("BDRA R2", B,BIDR,3,3), -- FE Branch on Decrementing Register, Absolute + ("BDRA R3", B,BIDR,3,3) -- FF Branch on Decrementing Register, Absolute + ); + + ------------------------------------------------ + + FUNCTION sign(v : uv8) RETURN unsigned; + + -- LOAD : 00 EOR : 20 AND : 40 OR : 60 + -- ADD : 80 SUB : A0 STORE: C0 CMP : EO + PROCEDURE op_alu( + op : IN uv8; -- opcode + vi1 : IN uv8; -- Register + vi2 : IN uv8; -- Parameter, reg. zero + psli : IN uv8; -- Program status In + vo : OUT uv8; -- Register out + pslo : OUT uv8); -- Program Status Out + + ------------------------------------------------ + PROCEDURE op_dar( + vi : IN uv8; + vo : OUT uv8; + psli : IN uv8; + pslo : OUT uv8); + + ------------------------------------------------ + -- RRR = 50 RRL=D0 + PROCEDURE op_rotate( + op : IN uv8; + vi : IN uv8; + vo : OUT uv8; + psli : IN uv8; + pslo : OUT uv8); + + ------------------------------------------------ + PROCEDURE op_tmi( + vi1 : IN uv8; + vi2 : IN uv8; + psli : IN uv8; + pslo : OUT uv8); + + ---------------------------- + +END PACKAGE; + +--############################################################################## +PACKAGE BODY sgs2650_pack IS + + FUNCTION sign(v : uv8) RETURN unsigned IS + BEGIN + IF v=x"00" THEN + RETURN "00"; + ELSIF v(7)='0' THEN + RETURN "01"; + ELSE + RETURN "10"; + END IF; + END FUNCTION; + + -- LOAD : 00 EOR : 20 AND : 40 OR : 60 + -- ADD : 80 SUB : A0 STORE: C0 CMP : EO + PROCEDURE op_alu( + op : IN uv8; -- opcode + vi1 : IN uv8; -- Register + vi2 : IN uv8; -- Parameter, reg. zero + psli : IN uv8; -- Program status In + vo : OUT uv8; -- Register out + pslo : OUT uv8) IS -- Program Status Out + VARIABLE vt : uv8; -- Temporary result + ALIAS psli_c : std_logic IS psli(0); -- Carry + ALIAS psli_com : std_logic IS psli(1); -- Compare logical / arithmetic + ALIAS psli_ovf : std_logic IS psli(2); -- Overflow + ALIAS psli_wc : std_logic IS psli(3); -- With Carry + ALIAS psli_idc : std_logic IS psli(5); -- Inter-Digit Carry + ALIAS psli_cc : uv2 IS psli(7 DOWNTO 6); -- Condition Code + ALIAS pslo_c : std_logic IS pslo(0); -- Carry + ALIAS pslo_com : std_logic IS pslo(1); -- Compare logical=1 / arithmetic=0 + ALIAS pslo_ovf : std_logic IS pslo(2); -- Overflow + ALIAS pslo_wc : std_logic IS pslo(3); -- With Carry + ALIAS pslo_idc : std_logic IS pslo(5); -- Inter-Digit Carry + ALIAS pslo_cc : uv2 IS pslo(7 DOWNTO 6); -- Condition Code + + BEGIN + pslo:=psli; + vt:=vi1; + vo:=vt; + + CASE op(7 DOWNTO 5) IS + WHEN "000" => -- LOAD + vt:=vi2; + vo:=vt; + + WHEN "001" => -- EOR + vt:=vi1 XOR vi2; + vo:=vt; + + WHEN "010" => -- AND + vt:=vi1 AND vi2; + vo:=vt; + + WHEN "011" => -- OR + vt:=vi1 OR vi2; + vo:=vt; + + WHEN "100" => -- ADD + vt:=vi1 + vi2 + ("0000000" & (psli_c AND psli_wc)); + vo:=vt; + pslo_c :=(vi1(7) AND vi2(7)) OR (NOT vt(7) AND (vi1(7) OR vi2(7))); + pslo_ovf:=(vi1(7) AND vi2(7) AND NOT vt(7)) OR + (NOT vi1(7) AND NOT vi2(7) AND vt(7)); + pslo_idc:=to_std_logic(vt(3 DOWNTO 0) -- SUB + vt:=vi1 - vi2 - ("0000000" & (NOT psli_c AND psli_wc)); + vo:=vt; + pslo_c :=NOT ((NOT vi1(7) AND vi2(7)) OR (vt(7) AND (NOT vi1(7) OR vi2(7)))); + pslo_ovf:=(vi1(7) AND NOT vi2(7) AND NOT vt(7)) OR + (NOT vi1(7) AND vi2(7) AND vt(7)); + pslo_idc:=to_std_logic(vt(3 DOWNTO 0)<=vi1(3 DOWNTO 0)); + + WHEN "110" => -- STORE + vt:=vi2; + vo:=vt; + + WHEN OTHERS => -- COM + vt:=vi1 - vi2; + vo:=vi1; + + IF vt=x"00" THEN -- = + pslo_cc:="00"; + ELSIF psli_com='1' AND -- Unsigned < + ((vi1(7)='0' AND vi2(7)='1') OR + (vt(7)='1' AND NOT (vi1(7)='1' AND vi2(7)='0'))) THEN + pslo_cc:="10"; + ELSIF psli_com='0' AND -- Signed < + ((vi1(7)='1' AND vi2(7)='0') OR + (vi1(7)='0' AND vi2(7)='0' AND vt(7)='1') OR + (vi1(7)='1' AND vi2(7)='1' AND vt(7)='0')) THEN -- Signed < + pslo_cc:="10"; + ELSE -- > + pslo_cc:="01"; + END IF; + + END CASE; + + IF op(7 DOWNTO 5)/="111" THEN + pslo_cc:=sign(vt); + END IF; + + END PROCEDURE op_alu; + + ------------------------------------------------ + PROCEDURE op_dar( + vi : IN uv8; + vo : OUT uv8; + psli : IN uv8; + pslo : OUT uv8) IS + VARIABLE vt : uv8; + ALIAS psli_c : std_logic IS psli(0); -- Carry + ALIAS psli_com : std_logic IS psli(1); -- Compare logical / arithmetic + ALIAS psli_ovf : std_logic IS psli(2); -- Overflow + ALIAS psli_wc : std_logic IS psli(3); -- With Carry + ALIAS psli_idc : std_logic IS psli(5); -- Inter-Digit Carry + ALIAS psli_cc : uv2 IS psli(7 DOWNTO 6); -- Condition Code + ALIAS pslo_c : std_logic IS pslo(0); -- Carry + ALIAS pslo_com : std_logic IS pslo(1); -- Compare logical=1 / arithmetic=0 + ALIAS pslo_ovf : std_logic IS pslo(2); -- Overflow + ALIAS pslo_wc : std_logic IS pslo(3); -- With Carry + ALIAS pslo_idc : std_logic IS pslo(5); -- Inter-Digit Carry + ALIAS pslo_cc : uv2 IS pslo(7 DOWNTO 6); -- Condition Code + BEGIN + pslo:=psli; + vt:=vi; + IF psli_c='0' THEN + vt:=vt+x"A0"; + END IF; + IF psli_idc='0' THEN + vt:=vt(7 DOWNTO 4) & (vt(3 DOWNTO 0)+x"A"); + END IF; + pslo_cc:=sign(vt); + vo:=vt; + + END PROCEDURE op_dar; + + ------------------------------------------------ + -- RRR = 50 RRL=D0 + PROCEDURE op_rotate( + op : IN uv8; + vi : IN uv8; + vo : OUT uv8; + psli : IN uv8; + pslo : OUT uv8) IS + VARIABLE vt : uv8; + ALIAS psli_c : std_logic IS psli(0); -- Carry + ALIAS psli_wc : std_logic IS psli(3); -- With Carry + ALIAS pslo_c : std_logic IS pslo(0); -- Carry + ALIAS pslo_idc : std_logic IS pslo(5); -- Inter-Digit Carry + ALIAS pslo_cc : uv2 IS pslo(7 DOWNTO 6); -- Condition Code + BEGIN + pslo:=psli; + IF op(7)='1' THEN + IF psli_wc='1' THEN + vt:=vi(6 DOWNTO 0) & psli_c; + pslo_c:=vi(7); + pslo_idc:=vi(4); + ELSE + vt:=vi(6 DOWNTO 0) & vi(7); + END IF; + ELSE + IF psli_wc='1' THEN + vt:=psli_c & vi(7 DOWNTO 1); + pslo_c:=vi(0); + pslo_idc:=vi(6); + ELSE + vt:=vi(0) & vi(7 DOWNTO 1); + END IF; + END IF; + pslo_cc:=sign(vt); + vo:=vt; + + END PROCEDURE op_rotate; + + ------------------------------------------------ + PROCEDURE op_tmi( + vi1 : IN uv8; + vi2 : IN uv8; + psli : IN uv8; + pslo : OUT uv8) IS + BEGIN + pslo:=psli; + IF (vi1 AND vi2)=vi2 THEN + pslo(7 DOWNTO 6):="00"; + ELSE + pslo(7 DOWNTO 6):="10"; + END IF; + END PROCEDURE op_tmi; + + ------------------------------------------------ + +END PACKAGE BODY sgs2650_pack; + + + diff --git a/Console_MiST/Interton VC4000_MiST/VC4000_MiST.qsf b/Console_MiST/Interton VC4000_MiST/VC4000_MiST.qsf index 12f683a7..73c854ab 100644 --- a/Console_MiST/Interton VC4000_MiST/VC4000_MiST.qsf +++ b/Console_MiST/Interton VC4000_MiST/VC4000_MiST.qsf @@ -17,15 +17,15 @@ # -------------------------------------------------------------------------- # # # Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 21:36:26 March 08, 2019 +# Version 13.1.4 Build 182 03/12/2014 SJ Full Version +# Date created = 08:53:10 July 02, 2022 # # -------------------------------------------------------------------------- # # # Notes: # # 1) The default values for assignments are stored in the file: -# Galaga_MiST_assignment_defaults.qdf +# VC4000_MiST_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # @@ -44,6 +44,14 @@ set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:59:05 MARCH 16, 2017 set_global_assignment -name LAST_QUARTUS_VERSION 13.1 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name SYSTEMVERILOG_FILE rtl/vc4000_mist.sv +set_global_assignment -name VHDL_FILE rtl/vc4000_core.vhd +set_global_assignment -name VHDL_FILE rtl/sgs2650_pack.vhd +set_global_assignment -name VHDL_FILE rtl/sgs2650.vhd +set_global_assignment -name VHDL_FILE rtl/sgs2636.vhd +set_global_assignment -name VHDL_FILE rtl/base_pack.vhd +set_global_assignment -name VHDL_FILE rtl/pll.vhd +set_global_assignment -name QIP_FILE ../../common/mist/mist.qip # Pin & Location Assignments # ========================== @@ -124,6 +132,7 @@ set_location_assignment PIN_46 -to UART_TX # ========================== set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON # Analysis & Synthesis Assignments # ================================ @@ -175,35 +184,26 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" - # EDA Netlist Writer Assignments # ============================== -set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation + set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation # end EDA_TOOL_SETTINGS(eda_simulation) # ------------------------------------- # ------------------------- -# start ENTITY(galaga_mist) +# start ENTITY(vc4000_mist) # start DESIGN_PARTITION(Top) # --------------------------- # Incremental Compilation Assignments # =================================== + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top # end DESIGN_PARTITION(Top) # ------------------------- -# end ENTITY(galaga_mist) +# end ENTITY(vc4000_mist) # ----------------------- -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_global_assignment -name SYSTEMVERILOG_FILE rtl/vc4000_mist.sv -set_global_assignment -name VHDL_FILE rtl/vc4000_core.vhd -set_global_assignment -name VHDL_FILE rtl/sgs2650_pack.vhd -set_global_assignment -name VHDL_FILE rtl/sgs2650.vhd -set_global_assignment -name VHDL_FILE rtl/sgs2636.vhd -set_global_assignment -name VHDL_FILE rtl/base_pack.vhd -set_global_assignment -name VHDL_FILE rtl/pll.vhd -set_global_assignment -name QIP_FILE ../../common/mist/mist.qip set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file