diff --git a/Console_MiST/GCE - Vectrex_MiST/README.txt b/Console_MiST/GCE - Vectrex_MiST/README.txt index 132b2781..10d49708 100644 --- a/Console_MiST/GCE - Vectrex_MiST/README.txt +++ b/Console_MiST/GCE - Vectrex_MiST/README.txt @@ -1,21 +1,18 @@ GCE(General Consumer Electronics) - Vectrex For Mist FPGA -Max 16kb Roms supported +Up to 32kb Roms supported Controls: - Movement: Joystick, Keyboard(Arrow Keys) + Movement: Joystick Buttons: 1-4 on Joystick Fire Buttons - (Player 1) 1-4 on Keyboard 1-4 and WASD - (Player 2) NUM, /, *, - on Numpad and Arrow Keys - -ToDo: Reset (hold Button longer for a Correct Reset) - - - - +CPU: It's possible to choose between two CPUs: + - MC6809 - Greg Miller's cycle exact 6809 + - CPU09 - John Kent's 6809 compatible CPU +Speech extension can clash with the controls in some games, +turn off Speech if it happens. diff --git a/Console_MiST/GCE - Vectrex_MiST/rtl/vectrex.vhd b/Console_MiST/GCE - Vectrex_MiST/rtl/vectrex.vhd index 9cc8ecac..8ae07ee9 100644 --- a/Console_MiST/GCE - Vectrex_MiST/rtl/vectrex.vhd +++ b/Console_MiST/GCE - Vectrex_MiST/rtl/vectrex.vhd @@ -138,8 +138,8 @@ port clock_24 : in std_logic; clock_12 : in std_logic; reset : in std_logic; + cpu : in std_logic; -- 1 - CPU by John Kent, 0 -- CPU by Greg Miller (Cycle exact) - video_r : out std_logic_vector(3 downto 0); video_g : out std_logic_vector(3 downto 0); video_b : out std_logic_vector(3 downto 0); @@ -205,7 +205,35 @@ architecture syn of vectrex is IOB_out : out std_logic_vector(7 downto 0) ); end component; - + +component mc6809 is port +( + CPU : in std_logic; + + CLK : in std_logic; + CLKEN : in std_logic; + + E : out std_logic; + riseE : out std_logic; + fallE : out std_logic; + + Q : out std_logic; + riseQ : out std_logic; + fallQ : out std_logic; + + Din : in std_logic_vector(7 downto 0); + Dout : out std_logic_vector(7 downto 0); + ADDR : out std_logic_vector(15 downto 0); + RnW : out std_logic; + + nIRQ : in std_logic := '1'; + nFIRQ : in std_logic := '1'; + nNMI : in std_logic := '1'; + nHALT : in std_logic := '1'; + nRESET : in std_logic := '1' +); +end component mc6809; + -------------------------------------------------------------- -- Configuration -------------------------------------------------------------- @@ -406,20 +434,13 @@ end process; reset_n <= not reset; clock_24n <= not clock_24; -process (clock_24, reset) - begin - if reset='1' then - clock_div <= "0000"; - else - if rising_edge(clock_24) then - clock_div <= clock_div + '1'; - end if; +process (clock_24) begin + if rising_edge(clock_24) then + clock_div <= clock_div + '1'; end if; end process; via_en_4 <= '1' when clock_div(1 downto 0) = "11" else '0'; -cpu_clock <= clock_div(3); -cpu_clock_en <= '1' when clock_div(3 downto 0) = "1111" else '0'; process (clock_24, reset) begin @@ -457,7 +478,7 @@ ram_we <= '1' when cpu_rw = '0' and ram_cs = '1' else '0'; -- misc cpu_irq <= not via_irq_n; -cpu_firq <= '0'; +cpu_firq <= btn14; cart_rd <= cart_cs; cpu_di <= cart_do when cart_cs = '1' else ram_do when ram_cs = '1' else @@ -833,29 +854,26 @@ frame <= frame_line; --------------------------- -- microprocessor 6809 -main_cpu : entity work.cpu09 -port map( - clk => clock_24,-- E clock input (falling edge) - ce => cpu_clock_en, - rst => reset, -- reset input (active high) - vma => open, -- valid memory address (active high) - lic_out => open, -- last instruction cycle (active high) - ifetch => open, -- instruction fetch cycle (active high) - opfetch => cpu_fetch,-- opcode fetch (active high) - ba => open, -- bus available (high on sync wait or DMA grant) - bs => open, -- bus status (high on interrupt or reset vector fetch or DMA grant) - addr => cpu_addr, -- address bus output - rw => cpu_rw, -- read not write output - data_out => cpu_do, -- data bus output - data_in => cpu_di, -- data bus input - irq => cpu_irq, -- interrupt request input (active high) - firq => cpu_firq, -- fast interrupt request input (active high) - nmi => '0', -- non maskable interrupt request input (active high) - halt => '0'--, -- halt input (active high) grants DMA --- hold_in => '0' -- hold input (active high) extend bus cycle +main_cpu : mc6809 +port map +( + CLK => clock_24, + CLKEN => via_en_4, + nRESET => not reset, + CPU => not cpu, + + E => cpu_clock, + riseQ => cpu_clock_en, + + Din => cpu_di, + Dout => cpu_do, + ADDR => cpu_addr, + RnW => cpu_rw, + + nIRQ => not cpu_irq, + nFIRQ => not cpu_firq ); - cpu_prog_rom : entity work.vectrex_exec_prom port map( clk => clock_24, @@ -941,7 +959,7 @@ port map( RESET_L => reset_n, CLK => clock_24, - I_P2_H => cpu_clock, -- high for phase 2 clock ____----__ + I_P2_H => not cpu_clock,-- high for phase 2 clock ____----__ ENA_4 => via_en_4 -- 4x system clock (4HZ) _-_-_-_-_- ); diff --git a/Console_MiST/GCE - Vectrex_MiST/rtl/vectrex_mist.sv b/Console_MiST/GCE - Vectrex_MiST/rtl/vectrex_mist.sv index 374a3556..3179fdf0 100644 --- a/Console_MiST/GCE - Vectrex_MiST/rtl/vectrex_mist.sv +++ b/Console_MiST/GCE - Vectrex_MiST/rtl/vectrex_mist.sv @@ -33,6 +33,7 @@ module vectrex_mist localparam CONF_STR = { "Vectrex;BINVECROM;", + "O1,CPU,MC6809,CPU09;", "O2,Show Frame,Yes,No;", "O3,Skip Logo,Yes,No;", "O4,Joystick swap,Off,On;", @@ -101,20 +102,28 @@ sdram cart .ready() ); - wire reset = (status[0] | status[6] | buttons[1] | ioctl_downl | second_reset); - +reg reset = 0; reg second_reset = 0; + always @(posedge clk_24) begin integer timeout = 0; + reg [15:0] reset_counter = 0; + reg reset_start; - if(ioctl_downl && status[3]) timeout <= 5000000; - else begin - if(!timeout) second_reset <= 0; - else begin - timeout <= timeout - 1; - if(timeout < 1000) second_reset <= 1; - end + reset <= 0; + reset_start <= status[0] | status[6] | buttons[1] | ioctl_downl | second_reset; + if (reset_counter) begin + reset <= 1'b1; + reset_counter <= reset_counter - 1'd1; end + if (reset_start) reset_counter <= 16'd1000; + + second_reset <= 0; + if (timeout) begin + timeout <= timeout - 1; + if(timeout == 1) second_reset <= 1'b1; + end + if(ioctl_downl && !status[3]) timeout <= 5000000; end assign pot_x_1 = status[4] ? joy_ana_1[15:8] : joy_ana_0[15:8]; @@ -126,6 +135,7 @@ vectrex vectrex ( .clock_24 ( clk_24 ), .clock_12 ( clk_12 ), .reset ( reset ), + .cpu ( status[1] ), .video_r ( rr ), .video_g ( gg ), .video_b ( bb ), @@ -173,8 +183,6 @@ assign r = status[2] & frame_line ? 4'h4 : blankn ? rr : 4'd0; assign g = status[2] & frame_line ? 4'h0 : blankn ? gg : 4'd0; assign b = status[2] & frame_line ? 4'h0 : blankn ? bb : 4'd0; -wire vsync_out; -wire hsync_out; wire csync_out = ~(hs ^ vs); assign VGA_HS = ypbpr ? csync_out : hs;