From 3a8257b565dd3cc380439119acd97c89831822fe Mon Sep 17 00:00:00 2001 From: Gyorgy Szombathelyi <8644936+gyurco@users.noreply.github.com> Date: Tue, 29 Nov 2022 15:51:59 +0100 Subject: [PATCH 1/4] Congo Bongo: new arcade --- Arcade_MiST/Sega Congo Bongo/CongoBongo.qpf | 31 + Arcade_MiST/Sega Congo Bongo/CongoBongo.qsf | 230 +++ Arcade_MiST/Sega Congo Bongo/CongoBongo.sdc | 134 ++ Arcade_MiST/Sega Congo Bongo/README.txt | 36 + .../Sega Congo Bongo/meta/Congo Bongo.mra | 67 + .../meta/Tip Top (3 board stack).mra | 65 + .../Sega Congo Bongo/rtl/CongoBongo_MiST.sv | 352 +++++ Arcade_MiST/Sega Congo Bongo/rtl/build_id.tcl | 35 + .../Sega Congo Bongo/rtl/congo_bongo.vhd | 1269 +++++++++++++++++ .../Sega Congo Bongo/rtl/congo_samples.bin | Bin 0 -> 11566 bytes .../Sega Congo Bongo/rtl/congo_samples.vhd | 751 ++++++++++ .../rtl/congo_sound_board.vhd | 323 +++++ Arcade_MiST/Sega Congo Bongo/rtl/dpram.vhd | 87 ++ Arcade_MiST/Sega Congo Bongo/rtl/gen_ram.vhd | 63 + Arcade_MiST/Sega Congo Bongo/rtl/pll_mist.qip | 4 + Arcade_MiST/Sega Congo Bongo/rtl/pll_mist.v | 337 +++++ .../Sega Congo Bongo/rtl/samples_player.vhd | 193 +++ Arcade_MiST/Sega Congo Bongo/rtl/sdram.sv | 360 +++++ 18 files changed, 4337 insertions(+) create mode 100644 Arcade_MiST/Sega Congo Bongo/CongoBongo.qpf create mode 100644 Arcade_MiST/Sega Congo Bongo/CongoBongo.qsf create mode 100644 Arcade_MiST/Sega Congo Bongo/CongoBongo.sdc create mode 100644 Arcade_MiST/Sega Congo Bongo/README.txt create mode 100644 Arcade_MiST/Sega Congo Bongo/meta/Congo Bongo.mra create mode 100644 Arcade_MiST/Sega Congo Bongo/meta/Tip Top (3 board stack).mra create mode 100644 Arcade_MiST/Sega Congo Bongo/rtl/CongoBongo_MiST.sv create mode 100644 Arcade_MiST/Sega Congo Bongo/rtl/build_id.tcl create mode 100644 Arcade_MiST/Sega Congo Bongo/rtl/congo_bongo.vhd create mode 100644 Arcade_MiST/Sega Congo Bongo/rtl/congo_samples.bin create mode 100644 Arcade_MiST/Sega Congo Bongo/rtl/congo_samples.vhd create mode 100644 Arcade_MiST/Sega Congo Bongo/rtl/congo_sound_board.vhd create mode 100644 Arcade_MiST/Sega Congo Bongo/rtl/dpram.vhd create mode 100644 Arcade_MiST/Sega Congo Bongo/rtl/gen_ram.vhd create mode 100644 Arcade_MiST/Sega Congo Bongo/rtl/pll_mist.qip create mode 100644 Arcade_MiST/Sega Congo Bongo/rtl/pll_mist.v create mode 100644 Arcade_MiST/Sega Congo Bongo/rtl/samples_player.vhd create mode 100644 Arcade_MiST/Sega Congo Bongo/rtl/sdram.sv diff --git a/Arcade_MiST/Sega Congo Bongo/CongoBongo.qpf b/Arcade_MiST/Sega Congo Bongo/CongoBongo.qpf new file mode 100644 index 00000000..62e365a7 --- /dev/null +++ b/Arcade_MiST/Sega Congo Bongo/CongoBongo.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 00:21:03 December 03, 2019 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.1" +DATE = "00:21:03 December 03, 2019" + +# Revisions + +PROJECT_REVISION = "CongoBongo" + diff --git a/Arcade_MiST/Sega Congo Bongo/CongoBongo.qsf b/Arcade_MiST/Sega Congo Bongo/CongoBongo.qsf new file mode 100644 index 00000000..e2b8b42c --- /dev/null +++ b/Arcade_MiST/Sega Congo Bongo/CongoBongo.qsf @@ -0,0 +1,230 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 13:14:18 November 17, 2019 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Timber_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PIN_49 -to SDRAM_A[0] +set_location_assignment PIN_44 -to SDRAM_A[1] +set_location_assignment PIN_42 -to SDRAM_A[2] +set_location_assignment PIN_39 -to SDRAM_A[3] +set_location_assignment PIN_4 -to SDRAM_A[4] +set_location_assignment PIN_6 -to SDRAM_A[5] +set_location_assignment PIN_8 -to SDRAM_A[6] +set_location_assignment PIN_10 -to SDRAM_A[7] +set_location_assignment PIN_11 -to SDRAM_A[8] +set_location_assignment PIN_28 -to SDRAM_A[9] +set_location_assignment PIN_50 -to SDRAM_A[10] +set_location_assignment PIN_30 -to SDRAM_A[11] +set_location_assignment PIN_32 -to SDRAM_A[12] +set_location_assignment PIN_83 -to SDRAM_DQ[0] +set_location_assignment PIN_79 -to SDRAM_DQ[1] +set_location_assignment PIN_77 -to SDRAM_DQ[2] +set_location_assignment PIN_76 -to SDRAM_DQ[3] +set_location_assignment PIN_72 -to SDRAM_DQ[4] +set_location_assignment PIN_71 -to SDRAM_DQ[5] +set_location_assignment PIN_69 -to SDRAM_DQ[6] +set_location_assignment PIN_68 -to SDRAM_DQ[7] +set_location_assignment PIN_86 -to SDRAM_DQ[8] +set_location_assignment PIN_87 -to SDRAM_DQ[9] +set_location_assignment PIN_98 -to SDRAM_DQ[10] +set_location_assignment PIN_99 -to SDRAM_DQ[11] +set_location_assignment PIN_100 -to SDRAM_DQ[12] +set_location_assignment PIN_101 -to SDRAM_DQ[13] +set_location_assignment PIN_103 -to SDRAM_DQ[14] +set_location_assignment PIN_104 -to SDRAM_DQ[15] +set_location_assignment PIN_58 -to SDRAM_BA[0] +set_location_assignment PIN_51 -to SDRAM_BA[1] +set_location_assignment PIN_85 -to SDRAM_DQMH +set_location_assignment PIN_67 -to SDRAM_DQML +set_location_assignment PIN_60 -to SDRAM_nRAS +set_location_assignment PIN_64 -to SDRAM_nCAS +set_location_assignment PIN_66 -to SDRAM_nWE +set_location_assignment PIN_59 -to SDRAM_nCS +set_location_assignment PIN_33 -to SDRAM_CKE +set_location_assignment PIN_43 -to SDRAM_CLK +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*] + +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY CongoBongo_MiST +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# ------------------------- +# start ENTITY(DoTron_MiST) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(DoTron_MiST) +# ----------------------- +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name ENABLE_SIGNALTAP OFF +set_global_assignment -name USE_SIGNALTAP_FILE output_files/zaxx.stp +set_global_assignment -name SYSTEMVERILOG_FILE rtl/CongoBongo_MiST.sv +set_global_assignment -name VHDL_FILE rtl/samples_player.vhd +set_global_assignment -name QIP_FILE rtl/pll_mist.qip +set_global_assignment -name VHDL_FILE rtl/congo_sound_board.vhd +set_global_assignment -name VHDL_FILE rtl/congo_samples.vhd +set_global_assignment -name VHDL_FILE rtl/congo_bongo.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv +set_global_assignment -name VHDL_FILE rtl/dpram.vhd +set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd +set_global_assignment -name QIP_FILE ../../common/Sound/sn76489/sn76489.qip +set_global_assignment -name QIP_FILE ../../common/mist/mist.qip +set_global_assignment -name QIP_FILE ../../common/CPU/T80/T80.qip +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Sega Congo Bongo/CongoBongo.sdc b/Arcade_MiST/Sega Congo Bongo/CongoBongo.sdc new file mode 100644 index 00000000..33ffd42f --- /dev/null +++ b/Arcade_MiST/Sega Congo Bongo/CongoBongo.sdc @@ -0,0 +1,134 @@ +## Generated SDC file "vectrex_MiST.out.sdc" + +## Copyright (C) 1991-2013 Altera Corporation +## Your use of Altera Corporation's design tools, logic functions +## and other software and tools, and its AMPP partner logic +## functions, and any output files from any of the foregoing +## (including device programming or simulation files), and any +## associated documentation or information are expressly subject +## to the terms and conditions of the Altera Program License +## Subscription Agreement, Altera MegaCore Function License +## Agreement, or other applicable license agreement, including, +## without limitation, that your use is for the sole purpose of +## programming logic devices manufactured by Altera and sold by +## Altera or its authorized distributors. Please refer to the +## applicable agreement for further details. + + +## VENDOR "Altera" +## PROGRAM "Quartus II" +## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" + +## DATE "Sun Jun 24 12:53:00 2018" + +## +## DEVICE "EP3C25E144C8" +## + +# Clock constraints + +# Automatically constrain PLL and other generated clocks +derive_pll_clocks -create_base_clocks + +# Automatically calculate clock uncertainty to jitter and other effects. +derive_clock_uncertainty + +# tsu/th constraints + +# tco constraints + +# tpd constraints + +#************************************************************** +# Time Information +#************************************************************** + +set_time_format -unit ns -decimal_places 3 + + + +#************************************************************** +# Create Clock +#************************************************************** + +create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}] + +set sys_clk "pll|altpll_component|auto_generated|pll1|clk[1]" +set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[0]" +#************************************************************** +# Create Generated Clock +#************************************************************** + + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** + +#************************************************************** +# Set Input Delay +#************************************************************** + +set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}] + +set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]] +set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]] + +#************************************************************** +# Set Output Delay +#************************************************************** + +set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}] +set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_L}] +set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_R}] +set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {LED}] +set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {VGA_*}] + +set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] +set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] + +#************************************************************** +# Set Clock Groups +#************************************************************** + +set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}] + +#************************************************************** +# Set False Path +#************************************************************** + + + +#************************************************************** +# Set Multicycle Path +#************************************************************** + +set_multicycle_path -to {VGA_*[*]} -setup 2 +set_multicycle_path -to {VGA_*[*]} -hold 1 + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** + diff --git a/Arcade_MiST/Sega Congo Bongo/README.txt b/Arcade_MiST/Sega Congo Bongo/README.txt new file mode 100644 index 00000000..36cef859 --- /dev/null +++ b/Arcade_MiST/Sega Congo Bongo/README.txt @@ -0,0 +1,36 @@ +-- Congo Bongo port to MiST +-- +-- Usage: +-- Create .ROM and ARC files from MAME ROM zip files using the mra utility and the meta/mra files. +-- Example: mra -A -z /path/to/mame/roms "Congo Bongo.mra" +-- Copy the resulting ROM and ARC files to the root of the SD Card, next to the Zaxxon.rbf. +-- +-- MRA utilty: https://github.com/mist-devel/mra-tools-c +-- +--------------------------------------------------------------------------------- +-- Congo Bongo by Dar (darfpga@aol.fr) (12/11/2022) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- +-- release rev 00 : initial release +-- (12/11/2022) +--------------------------------------------------------------------------------- +-- gen_ram.vhd & io_ps2_keyboard +-------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +--------------------------------------------------------------------------------- +-- T80/T80se - Version : 304 +----------------------------- +-- Z80 compatible microprocessor core +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +--------------------------------------------------------------------------------- +-- Synthesizable model of TI's SN76489AN +-- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net) +--------------------------------------------------------------------------------- +-- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- diff --git a/Arcade_MiST/Sega Congo Bongo/meta/Congo Bongo.mra b/Arcade_MiST/Sega Congo Bongo/meta/Congo Bongo.mra new file mode 100644 index 00000000..40c0987c --- /dev/null +++ b/Arcade_MiST/Sega Congo Bongo/meta/Congo Bongo.mra @@ -0,0 +1,67 @@ + + Congo Bongo + no + no + 0248 + 1983 + Sega/Gremlin + Isometric Platform + Jungle + congo + vertical (cw) + CongoBongo + 4-way diagonal + + + + + + + + + + 00 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 00 + + + 00 + + + diff --git a/Arcade_MiST/Sega Congo Bongo/meta/Tip Top (3 board stack).mra b/Arcade_MiST/Sega Congo Bongo/meta/Tip Top (3 board stack).mra new file mode 100644 index 00000000..f5f086e0 --- /dev/null +++ b/Arcade_MiST/Sega Congo Bongo/meta/Tip Top (3 board stack).mra @@ -0,0 +1,65 @@ + + Tip Top + tiptop + no + no + 0248 + 1983 + Sega/Gremlin + Isometric Platform + vertical (cw) + CongoBongo + 4-way diagonal + + + + + + + + + + 00 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 00 + + + 00 + + + \ No newline at end of file diff --git a/Arcade_MiST/Sega Congo Bongo/rtl/CongoBongo_MiST.sv b/Arcade_MiST/Sega Congo Bongo/rtl/CongoBongo_MiST.sv new file mode 100644 index 00000000..164b593f --- /dev/null +++ b/Arcade_MiST/Sega Congo Bongo/rtl/CongoBongo_MiST.sv @@ -0,0 +1,352 @@ + +module CongoBongo_MiST( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27, + + output [12:0] SDRAM_A, + inout [15:0] SDRAM_DQ, + output SDRAM_DQML, + output SDRAM_DQMH, + output SDRAM_nWE, + output SDRAM_nCAS, + output SDRAM_nRAS, + output SDRAM_nCS, + output [1:0] SDRAM_BA, + output SDRAM_CLK, + output SDRAM_CKE +); + +`include "rtl/build_id.v" + +localparam CONF_STR = { + "CONGO;;", + "O2,Rotate Controls,Off,On;", + "O1,Pause,Off,On;", + "O34,Scanlines,Off,25%,50%,75%;", + "O8,Diagonal joystick,Off,On;", + "O5,Blend,Off,On;", + "O6,Flip,Off,On;", + "O7,Service,Off,On;", + "DIP;", + "T0,Reset;", + "V,v2.0.",`BUILD_DATE +}; + +wire pause = status[1]; +wire rotate = status[2]; +wire [1:0] scanlines = status[4:3]; +wire blend = status[5]; +wire flip = status[6]; +wire service = status[7]; +wire diagonal = status[8]; + +wire [7:0] sw1 = status[23:16]; +wire [7:0] sw2 = status[31:24]; + + +assign LED = ~ioctl_downl; +assign SDRAM_CLK = clk_sd; +assign SDRAM_CKE = 1; + +wire clk_sys, clk_sd; +wire pll_locked; +pll_mist pll( + .inclk0(CLOCK_27), + .c0(clk_sd),//48 + .c1(clk_sys),//24 + .locked(pll_locked) + ); + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire key_pressed; +wire key_strobe; +wire [7:0] key_code; +wire scandoublerD; +wire ypbpr; +wire no_csync; +wire [6:0] core_mod; + +user_io #( + .STRLEN(($size(CONF_STR)>>3))) +user_io( + .clk_sys (clk_sys ), + .conf_str (CONF_STR ), + .SPI_CLK (SPI_SCK ), + .SPI_SS_IO (CONF_DATA0 ), + .SPI_MISO (SPI_DO ), + .SPI_MOSI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable (scandoublerD ), + .ypbpr (ypbpr ), + .no_csync (no_csync ), + .key_strobe (key_strobe ), + .key_pressed (key_pressed ), + .key_code (key_code ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ), + .core_mod (core_mod ) + ); + +wire [15:0] audio_l; +wire [15:0] audio_r; +wire hs, vs, cs, hb, vb; +wire blankn = ~(vb | hb); +wire [2:0] g, r; +wire [1:0] b; +wire [14:0] rom_addr; +wire [15:0] rom_do; +wire [12:0] bg_addr; +wire [31:0] bg_do; +wire [13:0] sp_addr; +wire [31:0] sp_do; +wire [19:0] wave_addr; +wire [15:0] wave_do; +wire ioctl_downl; +wire [7:0] ioctl_index; +wire ioctl_wr; +wire [24:0] ioctl_addr; +wire [7:0] ioctl_dout; + +// ROM structure +// 00000-06FFF CPU ROM 28k u27-u28-u29-(u29-u29) +// 07000-0EFFF Tiledata 32k u91-u90-u93-u92 +// 0F000-0F7FF char1 2k u68 +// 0F800-0FFFF char2 2k u69 +// 10000-17FFF bg 32k u113-u112-u111-(u111) +// 18000-27FFF spr 64k u77-u78-u79-(u79) +// 28000-280FF 256b u76 +// 28100-281FF 256b u72 + +data_io data_io( + .clk_sys ( clk_sys ), + .SPI_SCK ( SPI_SCK ), + .SPI_SS2 ( SPI_SS2 ), + .SPI_DI ( SPI_DI ), + .ioctl_download( ioctl_downl ), + .ioctl_index ( ioctl_index ), + .ioctl_wr ( ioctl_wr ), + .ioctl_addr ( ioctl_addr ), + .ioctl_dout ( ioctl_dout ) +); + +wire [24:0] gfx_ioctl_addr = ioctl_addr - 17'hE000; + +reg port1_req, port2_req; +sdram #(48) sdram( + .*, + .init_n ( pll_locked ), + .clk ( clk_sd ), + + // port1 used for main CPU + .port1_req ( port1_req ), + .port1_ack ( ), + .port1_a ( ioctl_addr[23:1] ), + .port1_ds ( {ioctl_addr[0], ~ioctl_addr[0]} ), + .port1_we ( ioctl_downl ), + .port1_d ( {ioctl_dout, ioctl_dout} ), + .port1_q ( ), + + .cpu1_addr ( ioctl_downl ? 19'h7ffff : {5'd0, rom_addr[14:1]}), + .cpu1_q ( rom_do ), + .cpu2_addr ( wave_addr[19:1] + 17'h13100 ), + .cpu2_q ( wave_do ), + + // port2 for gfx + .port2_req ( port2_req ), + .port2_ack ( ), + .port2_a ( gfx_ioctl_addr[23:1] ), + .port2_ds ( {gfx_ioctl_addr[0], ~gfx_ioctl_addr[0]} ), + .port2_we ( ioctl_downl ), + .port2_d ( {ioctl_dout, ioctl_dout} ), + .port2_q ( ), + + .bg_addr ( bg_addr ), + .bg_q ( bg_do ), + .sp_addr ( sp_addr + 16'h2000), + .sp_q ( sp_do ) +); + +always @(posedge clk_sys) begin + reg ioctl_wr_last = 0; + + ioctl_wr_last <= ioctl_wr; + if (ioctl_downl) begin + if (~ioctl_wr_last && ioctl_wr) begin + port1_req <= ~port1_req; + port2_req <= ~port2_req; + end + end +end + +reg reset = 1; +reg rom_loaded = 0; +always @(posedge clk_sd) begin + reg ioctl_downlD; + ioctl_downlD <= ioctl_downl; + + if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1; + reset <= status[0] | buttons[1] | ~rom_loaded; +end + +wire dl_wr = ioctl_wr && ioctl_index == 0; + +wire m_north, m_south, m_east, m_west; + +always @(*) begin + if (~diagonal) begin + m_north <= m_up; + m_south <= m_down; + m_east <= m_right; + m_west <= m_left; + end + else begin + m_north <= m_up & m_right; + m_south <= m_down & m_left; + m_east <= m_right & m_down; + m_west <= m_left & m_up; + end +end + +congo_bongo congo_bongo +( + .clock_24(clk_sys), + .reset(reset), + .pause(pause), + .video_r(r), + .video_g(g), + .video_b(b), + .video_vblank(vb), + .video_hblank(hb), + .video_hs(hs), + .video_vs(vs), + + .audio_out_l(audio_l), + .audio_out_r(audio_r), + + .cpu_rom_addr ( rom_addr ), + .cpu_rom_do ( rom_addr[0] ? rom_do[15:8] : rom_do[7:0] ), + .bg_graphics_addr( bg_addr ), + .bg_graphics_do ( bg_do ), + .sp_graphics_addr( sp_addr ), + .sp_graphics_do ( sp_do ), + + .dl_addr(ioctl_addr[17:0]), + .dl_wr(dl_wr), + .dl_data(ioctl_dout), + + .coin1(m_coin1), + .coin2(m_coin2), + .start1(m_one_player), + .start2(m_two_players), + + .right(m_east), + .left(m_west), + .up(m_north), + .down(m_south), + .fire(m_fireA), + + .right_c(m_east), + .left_c(m_west), + .up_c(m_north), + .down_c(m_south), + .fire_c(m_fireA), + + .sw1_input(sw1), // cocktail(1) / sound(1) / ships(2) / N.U.(2) / extra ship (2) + .sw2_input(8'h33), // coin b(4) / coin a(4) -- "3" => 1c_1c + + .service(service), + .flip_screen(flip) + +//Dar .wave_data(wave_data), +//Dar .wave_addr(wave_addr), +//Dar .wave_rd(wave_rd), + +//Dar .hs_address(hs_address), +//Dar .hs_data_out(hs_data_out), +//Dar .hs_data_in(hs_data_in), +//Dar .hs_write(hs_write_enable) +); + + +mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video( + .clk_sys ( clk_sys ), + .SPI_SCK ( SPI_SCK ), + .SPI_SS3 ( SPI_SS3 ), + .SPI_DI ( SPI_DI ), + .R ( blankn ? r : 0 ), + .G ( blankn ? g : 0 ), + .B ( blankn ? {b,b[1]} : 0 ), + .HSync ( hs ), + .VSync ( vs ), + .VGA_R ( VGA_R ), + .VGA_G ( VGA_G ), + .VGA_B ( VGA_B ), + .VGA_VS ( VGA_VS ), + .VGA_HS ( VGA_HS ), + .ce_divider ( 1'b1 ), + .blend ( blend ), + .rotate ( {flip, rotate} ), + .scandoubler_disable(scandoublerD ), + .scanlines ( scanlines ), + .ypbpr ( ypbpr ), + .no_csync ( no_csync ) + ); + +dac #( + .C_bits(16)) +dacl( + .clk_i(clk_sys), + .res_n_i(1), + .dac_i(audio_l), + .dac_o(AUDIO_L) + ); + +dac #( + .C_bits(16)) +dacr( + .clk_i(clk_sys), + .res_n_i(1), + .dac_i(audio_r), + .dac_o(AUDIO_R) + ); + +wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF; +wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F; +wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players; + +arcade_inputs inputs ( + .clk ( clk_sys ), + .key_strobe ( key_strobe ), + .key_pressed ( key_pressed ), + .key_code ( key_code ), + .joystick_0 ( joystick_0 ), + .joystick_1 ( joystick_1 ), + .rotate ( rotate ), + .orientation ( {flip, 1'b1} ), + .joyswap ( 1'b0 ), + .oneplayer ( 1'b1 ), + .controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ), + .player1 ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ), + .player2 ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} ) +); + +endmodule diff --git a/Arcade_MiST/Sega Congo Bongo/rtl/build_id.tcl b/Arcade_MiST/Sega Congo Bongo/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade_MiST/Sega Congo Bongo/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Sega Congo Bongo/rtl/congo_bongo.vhd b/Arcade_MiST/Sega Congo Bongo/rtl/congo_bongo.vhd new file mode 100644 index 00000000..fec759f7 --- /dev/null +++ b/Arcade_MiST/Sega Congo Bongo/rtl/congo_bongo.vhd @@ -0,0 +1,1269 @@ +--------------------------------------------------------------------------------- +-- Congo Bongo by Dar (darfpga@aol.fr) (12/11/2022) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- +-- release rev 00 : initial release +-- (12/11/2022) +--------------------------------------------------------------------------------- +-- gen_ram.vhd & io_ps2_keyboard +-------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +--------------------------------------------------------------------------------- +-- T80/T80se - Version : 304 +----------------------------- +-- Z80 compatible microprocessor core +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +--------------------------------------------------------------------------------- +-- Synthesizable model of TI's SN76489AN +-- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net) +--------------------------------------------------------------------------------- +-- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- + +-- Features : +-- Video : TV 15kHz +-- Coctail mode : Yes +-- Sound : OK + +-- Use with MAME roms from congo.zip +-- +-- Use make_congo_proms.bat to build vhd file from binaries +-- (CRC list included) + +-- Congo Bongo (Gremlin/SEGA) : Congo Bongo is mainly identical to Zaxxon except +-- those : +-- +-- Use a DMA to transfert sprite data from wram to sprite ram +-- Use a color ram instead of color rom +-- CPU has more rom +-- Map data is half size +-- Sprite graphics is twice size +-- Registers/Inputs use mostly different addresses +-- Sound board uses analog circuit + 2xSN76486 +-- +-- See Zaxxon.vhd for more details +-- +--------------------------------------------------------------------------------- +-- Global screen flip is fully managed at hardware level. This allow to +-- easily add an external flip screen feature. +--------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity congo_bongo is +port( + clock_24 : in std_logic; + reset : in std_logic; + pause : in std_logic; +-- tv15Khz_mode : in std_logic; + video_r : out std_logic_vector(2 downto 0); + video_g : out std_logic_vector(2 downto 0); + video_b : out std_logic_vector(1 downto 0); + video_clk : out std_logic; + video_csync : out std_logic; + video_hblank : out std_logic; + video_vblank : out std_logic; + video_hs : out std_logic; + video_vs : out std_logic; + video_ce : out std_logic; + + audio_out_l : out std_logic_vector(15 downto 0); + audio_out_r : out std_logic_vector(15 downto 0); + + coin1 : in std_logic; + coin2 : in std_logic; + start1 : in std_logic; + start2 : in std_logic; + + left : in std_logic; + right : in std_logic; + up : in std_logic; + down : in std_logic; + fire : in std_logic; + + left_c : in std_logic; + right_c : in std_logic; + up_c : in std_logic; + down_c : in std_logic; + fire_c : in std_logic; + + sw1_input : in std_logic_vector( 7 downto 0); + sw2_input : in std_logic_vector( 7 downto 0); + + service : in std_logic; + flip_screen : in std_logic; + + cpu_rom_addr : out std_logic_vector(14 downto 0); + cpu_rom_do : in std_logic_vector(7 downto 0); + bg_graphics_addr : out std_logic_vector(12 downto 0); + bg_graphics_do : in std_logic_vector(31 downto 0); + sp_graphics_addr : out std_logic_vector(13 downto 0); + sp_graphics_do : in std_logic_vector(31 downto 0); + + dl_addr : in std_logic_vector(17 downto 0); + dl_wr : in std_logic; + dl_data : in std_logic_vector( 7 downto 0); + + dbg_cpu_addr : out std_logic_vector(15 downto 0) + ); +end congo_bongo; + +architecture struct of congo_bongo is + + signal reset_n : std_logic; + signal clock_vid : std_logic; + signal clock_vidn: std_logic; + signal clock_cnt : std_logic_vector(3 downto 0) := "0000"; + + signal hcnt : std_logic_vector(8 downto 0) := (others=>'0'); -- horizontal counter + signal vcnt : std_logic_vector(8 downto 0) := (others=>'0'); -- vertical counter + signal hflip : std_logic_vector(8 downto 0) := (others=>'0'); -- horizontal counter flip + signal vflip : std_logic_vector(8 downto 0) := (others=>'0'); -- vertical counter flip + + signal hs_cnt, vs_cnt :std_logic_vector(9 downto 0) ; + signal hsync0, hsync1, hsync2, hsync3, hsync4 : std_logic; + signal top_frame : std_logic := '0'; + + signal pix_ena : std_logic; + signal cpu_ena : std_logic; + + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_di : std_logic_vector( 7 downto 0); + signal cpu_do : std_logic_vector( 7 downto 0); + signal cpu_wr_n : std_logic; +-- signal cpu_rd_n : std_logic; + signal cpu_mreq_n : std_logic; +-- signal cpu_ioreq_n : std_logic; + signal cpu_irq_n : std_logic; + signal cpu_m1_n : std_logic; + +-- signal cpu_rom_do : std_logic_vector(7 downto 0); + + signal wram_addr : std_logic_vector(11 downto 0); + signal wram_we : std_logic; + signal wram_do : std_logic_vector(7 downto 0); + signal wram_do_to_cpu: std_logic_vector(7 downto 0); -- registred ram data for cpu + + signal dma_src_addr : std_logic_vector(11 downto 0); + signal dma_dst_addr : std_logic_vector( 7 downto 0); + signal dma_started : std_logic; + signal dma_cnt : std_logic_vector( 7 downto 0); + signal dma_step : std_logic_vector( 3 downto 0); + + signal ch_ram_addr: std_logic_vector(9 downto 0); + signal ch_ram_we : std_logic; + signal ch_ram_do : std_logic_vector(7 downto 0); + signal ch_ram_do_to_cpu: std_logic_vector(7 downto 0); -- registred ram data for cpu + + signal color_ram_we : std_logic; + signal color_ram_do : std_logic_vector(7 downto 0); + + signal ch_code : std_logic_vector(7 downto 0); + signal ch_color : std_logic_vector(3 downto 0); + signal ch_color_r : std_logic_vector(3 downto 0); + + signal ch_code_line_1 : std_logic_vector(11 downto 0); + signal ch_code_line_2 : std_logic_vector(11 downto 0); + signal ch_bit_nb : integer range 0 to 7; + signal ch_graphx1_do : std_logic_vector( 7 downto 0); + signal ch_graphx1_do_r : std_logic_vector( 7 downto 0); + signal ch_graphx2_do : std_logic_vector( 7 downto 0); + signal ch_graphx2_do_r : std_logic_vector( 7 downto 0); + signal ch_vid : std_logic_vector( 1 downto 0); + + signal palette_addr : std_logic_vector(7 downto 0); + signal palette_do : std_logic_vector(7 downto 0); + + signal map_offset_h : std_logic_vector(11 downto 0); + signal map_offset_l1 : std_logic_vector( 7 downto 0); + signal map_offset_l2 : std_logic_vector( 7 downto 0); + + signal map_addr : std_logic_vector(12 downto 0); + signal map1_do : std_logic_vector( 7 downto 0); + signal map2_do : std_logic_vector( 7 downto 0); + +-- signal bg_graphics_addr : std_logic_vector(12 downto 0); + signal bg_graphics1_do : std_logic_vector( 7 downto 0); + signal bg_graphics2_do : std_logic_vector( 7 downto 0); + signal bg_graphics3_do : std_logic_vector( 7 downto 0); + signal bg_graphics1_do_r: std_logic_vector( 7 downto 0); + signal bg_graphics2_do_r: std_logic_vector( 7 downto 0); + signal bg_graphics3_do_r: std_logic_vector( 7 downto 0); + signal bg_bit_nb : integer range 0 to 7; + signal bg_color_a : std_logic_vector(3 downto 0); + signal bg_color_r : std_logic_vector(3 downto 0); + signal bg_color : std_logic_vector(3 downto 0); + signal bg_vid : std_logic_vector(2 downto 0); + signal bg_vid_r : std_logic_vector(2 downto 0); + signal bg_code_line : std_logic_vector(9 downto 0); + + signal dma_do : std_logic_vector(7 downto 0); + signal sp_ram_addr : std_logic_vector(7 downto 0); + signal sp_ram_we : std_logic; + signal sp_ram_do : std_logic_vector(7 downto 0); + signal sp_ram_do_to_sp_machine : std_logic_vector(7 downto 0); + + signal sp_vcnt : std_logic_vector(7 downto 0); + signal sp_on_line : std_logic; + + signal sp_online_ram_we : std_logic; + signal sp_online_ram_addr : std_logic_vector(4 downto 0); + signal sp_online_ram_di : std_logic_vector(8 downto 0); + signal sp_online_ram_do : std_logic_vector(8 downto 0); + + signal vflip_r : std_logic_vector(8 downto 0); + signal sp_online_vcnt : std_logic_vector(7 downto 0); + signal sp_line : std_logic_vector(7 downto 0); + signal sp_code : std_logic_vector(7 downto 0); + signal sp_color : std_logic_vector(7 downto 0); + signal sp_color_r : std_logic_vector(4 downto 0); + + signal sp_code_line : std_logic_vector(13 downto 0); + signal sp_hflip : std_logic; + signal sp_hflip_r : std_logic; + signal sp_vflip : std_logic; + +-- signal sp_graphics_addr : std_logic_vector(13 downto 0); + signal sp_graphics1_do : std_logic_vector( 7 downto 0); + signal sp_graphics2_do : std_logic_vector( 7 downto 0); + signal sp_graphics3_do : std_logic_vector( 7 downto 0); + + signal sp_ok : std_logic; + signal sp_ok_r : std_logic; + signal sp_bit_hpos : std_logic_vector(7 downto 0); + signal sp_bit_hpos_r : std_logic_vector(7 downto 0); + signal sp_bit_nb : integer range 0 to 7; + + signal sp_buffer_ram_addr : std_logic_vector(7 downto 0); + signal sp_buffer_ram_we : std_logic; + signal sp_buffer_ram_di : std_logic_vector(7 downto 0); + signal sp_buffer_ram_do : std_logic_vector(7 downto 0); + signal sp_buffer_ram_do_r : std_logic_vector(7 downto 0); + + signal sp_vid : std_logic_vector(7 downto 0); + signal sp_vid_r : std_logic_vector(7 downto 0); + + signal vblkn, vblkn_r : std_logic; + signal int_on : std_logic := '0'; + + signal flip_cpu : std_logic := '0'; + signal flip : std_logic := '0'; + signal ch_color_ref : std_logic := '0'; + signal bg_position : std_logic_vector(10 downto 0) := (others => '0'); + signal bg_color_ref : std_logic := '0'; + signal bg_enable : std_logic := '0'; + + signal p1_input : std_logic_vector(7 downto 0); + signal p2_input : std_logic_vector(7 downto 0); + + signal gen_input : std_logic_vector(7 downto 0); + + signal coin1_r, coin1_mem, coin1_ena : std_logic := '0'; + signal coin2_r, coin2_mem, coin2_ena : std_logic := '0'; + + signal sound_cmd : std_logic_vector( 7 downto 0); + signal audio_out : std_logic_vector(15 downto 0); + + signal cpu_rom_we : std_logic; + signal ch_1_rom_we : std_logic; + signal ch_2_rom_we : std_logic; + signal bg_1_rom_we : std_logic; + signal bg_2_rom_we : std_logic; + signal bg_3_rom_we : std_logic; + signal sp_1_rom_we : std_logic; + signal sp_2_rom_we : std_logic; + signal sp_3_rom_we : std_logic; + signal map_1_rom_we : std_logic; + signal map_2_rom_we : std_logic; + signal palette_rom_we : std_logic; + +begin + +clock_vid <= clock_24; +clock_vidn <= not clock_24; +reset_n <= not reset; + +-- debug +--process (reset, clock_vid) +--begin +---- if rising_edge(clock_vid) and cpu_ena ='1' and cpu_mreq_n ='0' then +---- dbg_cpu_addr <= cpu_addr; +---- if rising_edge(clock_vid) then +---- dbg_cpu_addr <= sp_buffer_ram_do & sp_graphics1_do; +---- end if; +--end process; + +-- make enables clock from clock_vid +process (clock_vid, reset) +begin + if reset='1' then + clock_cnt <= (others=>'0'); + else + if rising_edge(clock_vid) then + if clock_cnt = "1111" then -- divide by 16 + clock_cnt <= (others=>'0'); + else + clock_cnt <= clock_cnt + 1; + end if; + end if; + end if; +end process; +-- _ _ _ _ _ _ _ _ _ _ _ +-- |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| | clock_vid 24MHz +-- ___ ___ ___ ___ ___ +-- ___| |___| |___| |___| |___| |__ clock_cnt(0) 12MHz +-- _______ _______ __ +-- _______| |_______| |_______| clock_cnt(1) 6MHz +-- ___ ___ ___ +-- ___| |___________| |___________| |__ pix_ena 6MHz +-- +-- _______ _______________ _______________ __ +-- _______|_______________|_______________|__ video +-- ___ ___ +-- ___| |___________________________| |__ cpu_ena 3MHz +-- +-- + +pix_ena <= '1' when clock_cnt(1 downto 0) = "01" else '0'; -- (6MHz) +cpu_ena <= '1' when hcnt(0) = '0' and pix_ena = '1' else '0'; -- (3MHz) + +video_ce <= pix_ena; +video_clk <= clock_vid; + +--------------------------------------- +-- Video scanner 384x264 @6.083 MHz -- +-- display 256x224 -- +-- -- +-- line : 63.13us -> 15.84kHz -- +-- frame : 16.67ms -> 60.00Hz -- +--------------------------------------- + +process (reset, clock_vid) +begin + if reset='1' then + hcnt <= (others=>'0'); + vcnt <= (others=>'0'); + top_frame <= '0'; + else + if rising_edge(clock_vid) then + if pix_ena = '1' then + + -- main horizontal / vertical counters + hcnt <= hcnt + 1; + if hcnt = 511 then + hcnt <= std_logic_vector(to_unsigned(128,9)); + end if; + + if hcnt = 128+8+8 then + vcnt <= vcnt + 1; + if vcnt = 263 then + vcnt <= (others=>'0'); + top_frame <= not top_frame; + end if; + end if; + + -- set syncs position + if hcnt = 170 then -- tune screen H position here + hs_cnt <= (others => '0'); + if (vcnt = 248) then -- tune screen V position here + vs_cnt <= (others => '0'); + else + vs_cnt <= vs_cnt +1; + end if; + + else + hs_cnt <= hs_cnt + 1; + end if; + + if vs_cnt = 1 then video_vs <= '0'; + elsif vs_cnt = 3 then video_vs <= '1'; + end if; + + -- blanking +-- video_blankn <= '0'; + +-- if (hcnt >= 256+9-5 or hcnt < 128+9-5) and +-- vcnt >= 17 and vcnt < 240 then video_blankn <= '1';end if; +-- + if hcnt = 256+9+1 then + video_hblank <= '0'; + end if; + if hcnt = 128+9+1 then + video_hblank <= '1'; + end if; + + if hcnt = 256+9+1 then + video_vblank <= '1'; + if vcnt >= 16 and vcnt < 240 then + video_vblank <= '0'; + end if; + end if; + + -- build syncs pattern (composite) + if hs_cnt = 0 then hsync0 <= '0'; video_hs <= '0'; + elsif hs_cnt = 29 then hsync0 <= '1'; video_hs <= '1'; + end if; + + if hs_cnt = 0 then hsync1 <= '0'; + elsif hs_cnt = 14 then hsync1 <= '1'; + elsif hs_cnt = 192+ 0 then hsync1 <= '0'; + elsif hs_cnt = 192+14 then hsync1 <= '1'; + end if; + + if hs_cnt = 0 then hsync2 <= '0'; + elsif hs_cnt = 192-29 then hsync2 <= '1'; + elsif hs_cnt = 192 then hsync2 <= '0'; + elsif hs_cnt = 384-29 then hsync2 <= '1'; + end if; + + if hs_cnt = 0 then hsync3 <= '0'; + elsif hs_cnt = 14 then hsync3 <= '1'; + elsif hs_cnt = 192 then hsync3 <= '0'; + elsif hs_cnt = 384-29 then hsync3 <= '1'; + end if; + + if hs_cnt = 0 then hsync4 <= '0'; + elsif hs_cnt = 192-29 then hsync4 <= '1'; + elsif hs_cnt = 192 then hsync4 <= '0'; + elsif hs_cnt = 192+14 then hsync4 <= '1'; + end if; + + if vs_cnt = 1 then video_csync <= hsync1; + elsif vs_cnt = 2 then video_csync <= hsync1; + elsif vs_cnt = 3 then video_csync <= hsync1; + elsif vs_cnt = 4 and top_frame = '1' then video_csync <= hsync3; + elsif vs_cnt = 4 and top_frame = '0' then video_csync <= hsync1; + elsif vs_cnt = 5 then video_csync <= hsync2; + elsif vs_cnt = 6 then video_csync <= hsync2; + elsif vs_cnt = 7 and top_frame = '1' then video_csync <= hsync4; + elsif vs_cnt = 7 and top_frame = '0' then video_csync <= hsync2; + elsif vs_cnt = 8 then video_csync <= hsync1; + elsif vs_cnt = 9 then video_csync <= hsync1; + elsif vs_cnt = 10 then video_csync <= hsync1; + elsif vs_cnt = 11 then video_csync <= hsync0; + else video_csync <= hsync0; + end if; + + end if; + end if; + end if; +end process; + +--------------------------------- +-- players/dip switches inputs -- +--------------------------------- +p1_input <= "000" & fire & down & up & left & right ; +p2_input <= "000" & fire_c & down_c & up_c & left_c & right_c; +gen_input <= service & coin2_mem & coin1_mem & '0' & start2 & start1 & "00"; + +------------------------------------------ +-- cpu data input with address decoding -- +------------------------------------------ +cpu_di <= cpu_rom_do when cpu_mreq_n = '0' and cpu_addr(15 downto 12) < X"8" else -- 0000-7FFF + wram_do_to_cpu when cpu_mreq_n = '0' and cpu_addr(15 downto 12) = x"8" else -- 8000-8FFF + ch_ram_do_to_cpu when cpu_mreq_n = '0' and (cpu_addr and x"E000") = x"A000" else -- video/color ram A000-A7FF + mirroring 1800 + p1_input when cpu_mreq_n = '0' and (cpu_addr and x"E03B") = x"C000" else -- player 1 C000 + mirroring 1FC4 + p2_input when cpu_mreq_n = '0' and (cpu_addr and x"E03B") = x"C001" else -- player 2 C001 + mirroring 1FC4 + sw1_input when cpu_mreq_n = '0' and (cpu_addr and x"E03B") = x"C002" else -- switch 1 C002 + mirroring 1FC4 + sw2_input when cpu_mreq_n = '0' and (cpu_addr and x"E03B") = x"C003" else -- switch 2 C003 + mirroring 1FC4 + gen_input when cpu_mreq_n = '0' and (cpu_addr and x"E038") = x"C008" else -- general C008 + mirroring 1FC7 + X"FF"; + +------------------------------------------------------------------------ +-- Coin registers +------------------------------------------------------------------------ +process (clock_vid, coin1_ena, coin2_ena) +begin + if coin1_ena = '0' then + coin1_mem <= '0'; + else + if rising_edge(clock_vid) then + coin1_r <= coin1; + if coin1 = '1' and coin1_r = '0' then coin1_mem <= coin1_ena; end if; + end if; + end if; + if coin2_ena = '0' then + coin2_mem <= '0'; + else + if rising_edge(clock_vid) then + coin2_r <= coin2; + if coin2 = '1' and coin2_r = '0' then coin2_mem <= coin2_ena; end if; + end if; + end if; +end process; + +------------------------------------------------------------------------ +-- Misc registers - interrupt set/enable +------------------------------------------------------------------------ +vblkn <= '0' when vcnt < 256 else '1'; + +process (clock_vid) +begin + if rising_edge(clock_vid) then + + vblkn_r <= vblkn; + + if cpu_mreq_n = '0' and cpu_wr_n = '0' then + -- U55/U52 + if (cpu_addr and x"E03F") = x"C018" then coin1_ena <= cpu_do(0); end if; -- C018 + mirroring 1FC0 + if (cpu_addr and x"E03F") = x"C019" then coin2_ena <= cpu_do(0); end if; -- C019 + mirroring 1FC0 + if (cpu_addr and x"E03F") = x"C01D" then bg_enable <= cpu_do(0); end if; -- C01D + mirroring 1FC0 + if (cpu_addr and x"E03F") = x"C01E" then flip_cpu <= cpu_do(0); end if; -- C01E + mirroring 1FC0 + if (cpu_addr and x"E03F") = x"C01F" then int_on <= cpu_do(0); end if; -- C01F + mirroring 1FC0 + -- U55/U53 + if (cpu_addr and x"E03F") = x"C021" then ch_color_ref <= cpu_do(0); end if; -- C021 + mirroring 1FC0 + if (cpu_addr and x"E03F") = x"C023" then bg_color_ref <= cpu_do(0); end if; -- C023 + mirroring 1FC0 +-- if (cpu_addr and x"E03F") = x"C026" then ch_bank <= cpu_do(0); end if; -- C026 + mirroring 1FC0 N.U. rom5 dump is 4ko only +-- if (cpu_addr and x"E03F") = x"C027" then palette_bank <= cpu_do(0); end if; -- C027 + mirroring 1FC0 N.U. depend on J1 setting + + -- U55/U39 U27,28,30,29 + if (cpu_addr and x"E03B") = x"C028" then bg_position( 7 downto 0) <= not cpu_do ; end if; -- C028 + mirroring 1FC4 + if (cpu_addr and x"E03B") = x"C029" then bg_position(10 downto 8) <= not cpu_do(2 downto 0); end if; -- C029 + mirroring 1FC4 + -- U55 + if (cpu_addr and x"E038") = x"C038" then sound_cmd <= cpu_do; end if; -- C038 + mirroring 1FC0 + end if; + + -- U41 + if int_on = '0' then + cpu_irq_n <= '1'; + else + if vblkn_r = '1' and vblkn = '0' then cpu_irq_n <= '0'; end if; + end if; + + end if; +end process; + +------------------------------------------ +-- write enable / ram access from CPU -- +-- mux ch_ram and sp ram addresses -- +-- dmux ch_ram and sp_ram data out -- +------------------------------------------ +wram_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and cpu_addr(15 downto 12 ) = x"8" and hcnt(0) = '1' else '0'; -- 8000-8FFF +ch_ram_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and (cpu_addr and x"FC00") = x"A000" and hcnt(0) = '0' else '0'; -- A000-A3FF +color_ram_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and (cpu_addr and x"FC00") = x"A400" and hcnt(0) = '0' else '0'; -- A400-A7FF + +flip <= flip_cpu xor flip_screen; +hflip <= hcnt when flip = '0' else not hcnt; +vflip <= vcnt when flip = '0' else not vcnt; + +wram_addr <= cpu_addr(11 downto 0) when hcnt(0) = '1' else dma_src_addr; +ch_ram_addr <= cpu_addr(9 downto 0) when hcnt(0) = '0' else vflip(7 downto 3) & hflip(7 downto 3); +sp_ram_addr <= dma_dst_addr when hcnt(0) = '1' else '0'& hcnt(7 downto 1); + +process (clock_vid) +begin + if rising_edge(clock_vid) then + if hcnt(0) = '1' then + wram_do_to_cpu <= wram_do; + else + sp_ram_do_to_sp_machine <= sp_ram_do; + if cpu_addr(10) = '0' then + ch_ram_do_to_cpu <= ch_ram_do; + else + ch_ram_do_to_cpu <= color_ram_do; + end if; + end if; + end if; +end process; + +---------------------- +--- sprite machine --- +---------------------- +-- +------ DMA : transfert sprite data from wram to sp_ram +-- +sp_ram_we <= '1' when dma_started = '1' and dma_step > x"1" and hcnt(0) = '1' and pix_ena = '1' else '0'; + +process (clock_vid) +begin + if rising_edge(clock_vid) then + + if cpu_mreq_n = '0' and cpu_wr_n = '0' and cpu_ena = '1' then + -- U59 (DMA) + if (cpu_addr and x"E03B") = x"C030" then dma_src_addr( 7 downto 0) <= cpu_do; end if; -- C030 + mirroring 1FC4 + if (cpu_addr and x"E03B") = x"C031" then dma_src_addr(11 downto 8) <= cpu_do(3 downto 0); end if; -- C031 + mirroring 1FC4 + if (cpu_addr and x"E03B") = x"C032" then dma_cnt <= cpu_do; end if; -- C032 + mirroring 1FC4 + if (cpu_addr and x"E03B") = x"C033" and cpu_do = x"01" then -- C033 + mirroring 1FC4 + dma_started <= '1'; + dma_step <= x"0"; + end if; + end if; + + if dma_started = '1' and pix_ena = '1' then + + if hcnt(0) = '0' then + + dma_do <= wram_do; + + if dma_step = x"1" then + dma_dst_addr <= dma_do(5 downto 0) & "00"; + else + dma_dst_addr <= dma_dst_addr + 1; + end if; + + if dma_step = x"5" then + dma_step <= x"1"; + if dma_cnt = 0 then + dma_started <= '0'; + else + dma_cnt <= dma_cnt - 1; + end if; + else + dma_step <= dma_step + 1; + end if; + + dma_src_addr <= dma_src_addr + 1; + if dma_step = x"4" then + dma_src_addr <= dma_src_addr + 28; + end if; + end if; + + end if; + + end if; +end process; + +-- +-- transfert sprites data from sp_ram to sp_online_ram +-- + +sp_vcnt <= sp_ram_do_to_sp_machine + ("111" & not(flip) & flip & flip & flip & '1') + vflip(7 downto 0) + 1; + +sp_online_ram_we <= '1' when hcnt(8) = '1' and sp_on_line = '1' and hcnt(0) ='0' and sp_online_ram_addr < "11111" else + '1' when hcnt(8) = '0' and hcnt(3) = '1' else '0'; + +sp_online_ram_di <= '1' & sp_ram_do_to_sp_machine when hcnt(8) = '1' else '0'&x"00"; + +process (clock_vid) +begin + if rising_edge(clock_vid) then + + if hcnt(8) = '1' then + if hcnt(2 downto 0) = "000" then + if sp_vcnt(7 downto 5) = "111" then + sp_on_line <= '1'; + else + sp_on_line <= '0'; + end if; + end if; + else + sp_on_line <= '0'; + end if; + + if hcnt(8) = '1' then + + -- during line display seek for sprite on line and transfert them to sp_online_ram + if hcnt = 256 then sp_online_ram_addr <= (others => '0'); end if; + + if pix_ena = '1' and sp_on_line = '1' and hcnt(0) = '0' and sp_online_ram_addr < "11111" then + + sp_online_ram_addr <= sp_online_ram_addr + 1; + + end if; + + -- during line fly back read sp_online_ram + else + sp_online_ram_addr <= hcnt(6 downto 4) & hcnt(2 downto 1); + end if; + + end if; +end process; + +-- +-- read sprite data from sp_online_ram and feed sprite line buffer with sprite graphics data +-- + +sp_online_vcnt <= sp_online_ram_do(7 downto 0) + ("111" & not(flip) & flip & flip & flip & '1') + vflip_r(7 downto 0) + 1; + +sp_code_line <= (sp_code(6 downto 0)) & + (sp_line(4 downto 3) xor (sp_code(7) & sp_code(7))) & + ("00" xor (sp_color(7) & sp_color(7))) & + (sp_line(2 downto 0) xor (sp_code(7) & sp_code(7) & sp_code(7))); + +sp_buffer_ram_addr <= sp_bit_hpos_r when flip = '1' and hcnt(8) = '1' else not sp_bit_hpos_r; + +sp_buffer_ram_di <= x"00" when hcnt(8) = '1' else + sp_color_r & sp_graphics3_do(sp_bit_nb) & + sp_graphics2_do(sp_bit_nb) & sp_graphics1_do(sp_bit_nb); + +sp_buffer_ram_we <= pix_ena when hcnt(8) = '1' else + sp_ok and clock_cnt(0) when sp_buffer_ram_do(2 downto 0) = "000" else '0'; + +sp_hflip <= sp_color(7); + +process (clock_vid) +begin + if rising_edge(clock_vid) then + + sp_buffer_ram_do_r <= sp_buffer_ram_do; + if pix_ena = '1' then + sp_vid <= sp_buffer_ram_do_r; + end if; + + if hcnt = 128 then vflip_r <= vflip; end if; + + if hcnt(8)='0' then + + if clock_cnt(0) = '1' then + if sp_hflip_r = '1' then sp_bit_nb <= sp_bit_nb + 1; end if; + if sp_hflip_r = '0' then sp_bit_nb <= sp_bit_nb - 1; end if; + + sp_bit_hpos_r <= sp_bit_hpos_r + 1; + end if; + + if pix_ena = '1' then + + if hcnt(3 downto 0) = "0000" then sp_line <= sp_online_vcnt; end if; + if hcnt(3 downto 0) = "0010" then sp_code <= sp_online_ram_do(7 downto 0); end if; + if hcnt(3 downto 0) = "0100" then sp_color <= sp_online_ram_do(7 downto 0); end if; + if hcnt(3 downto 0) = "0110" then + sp_ok_r <= sp_online_ram_do(8); + sp_bit_hpos <= sp_online_ram_do(7 downto 0) + ("111" & not(flip) & flip & flip & flip & '1') +1; + end if; + + if hcnt(3 downto 0) = "1000" then + if sp_hflip = '1' then sp_bit_nb <= 0; else sp_bit_nb <= 7; end if; + sp_bit_hpos_r <= sp_bit_hpos; + sp_color_r <= sp_color(4 downto 0); + sp_hflip_r <= sp_hflip; + sp_vflip <= sp_code(7); + sp_ok <= sp_ok_r; + end if; + + -- sprite rom address setup + if hcnt(3 downto 0) = "0110" then + sp_graphics_addr <= sp_code_line; + end if; + if hcnt(3 downto 0) = "1010" then + sp_graphics_addr(4 downto 3) <= "01" xor (sp_hflip_r & sp_hflip_r); + end if; + if hcnt(3 downto 0) = "1110" then + sp_graphics_addr(4 downto 3) <= "10" xor (sp_hflip_r & sp_hflip_r); + end if; + if hcnt(3 downto 0) = "0010" then + sp_graphics_addr(4 downto 3) <= "11" xor (sp_hflip_r & sp_hflip_r); + end if; + -- sprite rom data latch + if hcnt(1 downto 0) = "00" then + sp_graphics1_do <= sp_graphics_do(7 downto 0); + sp_graphics2_do <= sp_graphics_do(15 downto 8); + sp_graphics3_do <= sp_graphics_do(23 downto 16); + end if; + + end if; + + else + + if flip = '1' then + sp_bit_hpos_r <= hcnt(7 downto 0) - 8; -- tune sprite position w.r.t. background + else + sp_bit_hpos_r <= hcnt(7 downto 0) - 6; -- tune sprite position w.r.t. background + end if; + + end if; + + end if; +end process; + +-------------------- +--- char machine --- +-------------------- +ch_code <= ch_ram_do; +ch_code_line_1 <= '0' & ch_code & vflip(2 downto 0); +ch_code_line_2 <= '1' & ch_code & vflip(2 downto 0); + +process (clock_vid) +begin + if rising_edge(clock_vid) then + + if pix_ena = '1' then + + if hcnt(2 downto 0) = "111" then + ch_color_r <= color_ram_do(3 downto 0); + ch_graphx1_do_r <= ch_graphx1_do; + ch_graphx2_do_r <= ch_graphx2_do; + if flip = '1' then ch_bit_nb <= 0; else ch_bit_nb <= 7; end if; + else + + if flip = '1' then + ch_bit_nb <= ch_bit_nb + 1; + else + ch_bit_nb <= ch_bit_nb - 1; + end if; + + end if; + + ch_vid <= ch_graphx2_do_r(ch_bit_nb) & ch_graphx1_do_r(ch_bit_nb); + ch_color <= ch_color_r; + + end if; + + end if; +end process; + +--ch_vid <= ch_graphx2_do_r(ch_bit_nb) & ch_graphx1_do_r(ch_bit_nb); + +-------------------------- +--- background machine --- +-------------------------- +map_offset_h <= (bg_position & '1') + (x"0" & vflip(7 downto 0)) + 1; + +map_offset_l1 <= not('0' & vflip(7 downto 1)) + (hflip(7 downto 3) & "111") + 1; +map_offset_l2 <= map_offset_l1 + ('0' & not(flip) & flip & flip & flip & "000"); + +map_addr <= map_offset_h(10 downto 3) & map_offset_l2(7 downto 3); + +process (clock_vid) +begin + if rising_edge(clock_vid) then + + if pix_ena = '1' then + + if hcnt(2 downto 0) = "011" then -- 4H^ + bg_color_a <= map2_do(7 downto 4); + + bg_graphics_addr(2 downto 0) <= map_offset_h(2 downto 0); + bg_graphics_addr(12 downto 3) <= map2_do(1 downto 0) & map1_do;--bg_code_line; + end if; + if hcnt(2 downto 0) = "111" then -- LD7 + bg_color_r <= bg_color_a; + bg_graphics1_do <= bg_graphics_do(7 downto 0); + bg_graphics2_do <= bg_graphics_do(15 downto 8); + bg_graphics3_do <= bg_graphics_do(23 downto 16); + end if; + + if (not(vflip(3 downto 1)) + hflip(2 downto 0)) = "111" then + bg_graphics1_do_r <= bg_graphics1_do; + bg_graphics2_do_r <= bg_graphics2_do; + bg_graphics3_do_r <= bg_graphics3_do; + + bg_color <= bg_color_r; + + if flip = '1' then bg_bit_nb <= 0; else bg_bit_nb <= 7; end if; + else + if flip = '1' then + bg_bit_nb <= bg_bit_nb + 1; + else + bg_bit_nb <= bg_bit_nb - 1; + end if; + end if; + + bg_vid_r <= bg_graphics3_do_r(bg_bit_nb) & bg_graphics2_do_r(bg_bit_nb) & bg_graphics1_do_r(bg_bit_nb); + + end if; + + end if; +end process; + +bg_vid <= "000" when bg_enable = '0' else + bg_graphics3_do_r(bg_bit_nb) & bg_graphics2_do_r(bg_bit_nb) & bg_graphics1_do_r(bg_bit_nb) when flip = '1' else -- hack + bg_vid_r; + +-------------------------------------- +-- mux char/background/sprite video -- +-------------------------------------- +process (clock_vid) +begin + if rising_edge(clock_vid) then + + if pix_ena = '1' then + + palette_addr <= bg_color_ref & bg_color & bg_vid; + + if sp_vid(2 downto 0) /= "000" then + palette_addr <= sp_vid; + end if; + + if ch_vid /= "00" then + palette_addr <= ch_color_ref & ch_color & '0' & ch_vid; + end if; + + video_r <= palette_do(2 downto 0); + video_g <= palette_do(5 downto 3); + video_b <= palette_do(7 downto 6); + + end if; + + end if; +end process; + +----------- +-- Audio -- +----------- + +audio_out_r <= audio_out; +audio_out_l <= audio_out; + +------------------------------ +-- components & sound board -- +------------------------------ + +-- microprocessor Z80 +cpu : entity work.T80se +generic map(Mode => 0, T2Write => 1, IOWait => 1) +port map( + RESET_n => reset_n, + CLK_n => clock_vid, + CLKEN => cpu_ena, + WAIT_n => not pause, + INT_n => cpu_irq_n, + NMI_n => '1', --cpu_nmi_n, + BUSRQ_n => '1', + M1_n => cpu_m1_n, + MREQ_n => cpu_mreq_n, + IORQ_n => open, + RD_n => open, + WR_n => cpu_wr_n, + RFSH_n => open, + HALT_n => open, + BUSAK_n => open, + A => cpu_addr, + DI => cpu_di, + DO => cpu_do +); + + +-- cpu program ROM 0x0000-0x7FFF +--rom_cpu : entity work.congo_cpu +--port map( +-- clk => clock_vidn, +-- addr => cpu_addr(14 downto 0), +-- data => cpu_rom_do +--); + +--cpu_rom_we <= '1' when dl_wr = '1' and dl_addr(17 downto 15) = "000" else '0'; -- 00000-07FFF +--rom_cpu : entity work.dpram +--generic map( dWidth => 8, aWidth => 15) +--port map( +-- clk_a => clock_vidn, +-- addr_a => cpu_addr(14 downto 0), +-- q_a => cpu_rom_do, +-- clk_b => clock_vid, +-- addr_b => dl_addr(14 downto 0), +-- we_b => cpu_rom_we, +-- d_b => dl_data +--); +cpu_rom_addr <= cpu_addr(14 downto 0); + +-- working RAM 0x8000-0x8FFF +wram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 12) +port map( + clk => clock_vidn, + we => wram_we, + addr => wram_addr, --cpu_addr(11 downto 0), + d => cpu_do, + q => wram_do +); + +-- video RAM 0xA000-0xA3FF + mirroring adresses +-- U59 low part +video_ram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 10) +port map( + clk => clock_vidn, + we => ch_ram_we, + addr => ch_ram_addr, + d => cpu_do, + q => ch_ram_do +); + +-- color RAM 0xA400-0xA7FF + mirroring adresses +-- U59 high part +color_ram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 10) +port map( + clk => clock_vidn, + we => color_ram_we, + addr => ch_ram_addr, -- video RAM / color RAM same low bits address + d => cpu_do, + q => color_ram_do +); + +-- sprite RAM - DMA access +-- U12 +sprite_ram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 8) +port map( + clk => clock_vidn, + we => sp_ram_we, + addr => sp_ram_addr, + d => dma_do, + q => sp_ram_do +); + +-- sprite online RAM +sprites_online_ram : entity work.gen_ram +generic map( dWidth => 9, aWidth => 5) +port map( + clk => clock_vidn, + we => sp_online_ram_we, + addr => sp_online_ram_addr, + d => sp_online_ram_di, + q => sp_online_ram_do +); + +-- sprite line buffer +sprlinebuf : entity work.gen_ram +generic map( dWidth => 8, aWidth => 8) +port map( + clk => clock_vidn, + we => sp_buffer_ram_we, + addr => sp_buffer_ram_addr, + d => sp_buffer_ram_di, + q => sp_buffer_ram_do +); + +-- char graphics ROM 1 +--ch_graphics_1 : entity work.congo_char_bits +--port map( +-- clk => clock_vidn, +-- addr => ch_code_line_1, +-- data => ch_graphx1_do +--); + +ch_1_rom_we <= '1' when dl_wr = '1' and dl_addr(17 downto 12) = "001000" else '0'; -- 08000-08FFF +ch_graphics_1 : entity work.dpram +generic map( dWidth => 8, aWidth => 12) +port map( + clk_a => clock_vidn, + addr_a => ch_code_line_1, + q_a => ch_graphx1_do, + clk_b => clock_vid, + addr_b => dl_addr(11 downto 0), + we_b => ch_1_rom_we, + d_b => dl_data +); + +-- char graphics ROM 2 +--ch_graphics_2 : entity work.congo_char_bits +--port map( +-- clk => clock_vidn, +-- addr => ch_code_line_2, +-- data => ch_graphx2_do +--); +ch_2_rom_we <= '1' when dl_wr = '1' and dl_addr(17 downto 12) = "001001" else '0'; -- 09000-09FFF +ch_graphics_2 : entity work.dpram +generic map( dWidth => 8, aWidth => 12) +port map( + clk_a => clock_vidn, + addr_a => ch_code_line_2, + q_a => ch_graphx2_do, + clk_b => clock_vid, + addr_b => dl_addr(11 downto 0), + we_b => ch_2_rom_we, + d_b => dl_data +); + +-- map tile ROM 1 +--map_tile_1 : entity work.congo_map_1 +--port map( +-- clk => clock_vidn, +-- addr => map_addr, +-- data => map1_do +--); + +map_1_rom_we <= '1' when dl_wr = '1' and dl_addr(17 downto 13) = "00101" else '0'; -- 0A000-0BFFF +map_tile_1 : entity work.dpram +generic map( dWidth => 8, aWidth => 13) +port map( + clk_a => clock_vidn, + addr_a => map_addr, + q_a => map1_do, + clk_b => clock_vid, + addr_b => dl_addr(12 downto 0), + we_b => map_1_rom_we, + d_b => dl_data +); + +-- map tile ROM 2 +--map_tile_2 : entity work.congo_map_2 +--port map( +-- clk => clock_vidn, +-- addr => map_addr, +-- data => map2_do +--); +map_2_rom_we <= '1' when dl_wr = '1' and dl_addr(17 downto 13) = "00110" else '0'; -- 0C000-0DFFF +map_tile_2 : entity work.dpram +generic map( dWidth => 8, aWidth => 13) +port map( + clk_a => clock_vidn, + addr_a => map_addr, + q_a => map2_do, + clk_b => clock_vid, + addr_b => dl_addr(12 downto 0), + we_b => map_2_rom_we, + d_b => dl_data +); + +-- background graphics ROM 1 +--bg_graphics_bits_1 : entity work.congo_bg_bits_1 +--port map( +-- clk => clock_vidn, +-- addr => bg_graphics_addr, +-- data => bg_graphics1_do +--); +--bg_1_rom_we <= '1' when dl_wr = '1' and dl_addr(17 downto 13) = "00111" else '0'; -- 0E000-0FFFF +--bg_graphics_bits_1 : entity work.dpram +--generic map( dWidth => 8, aWidth => 13) +--port map( +-- clk_a => clock_vidn, +-- addr_a => bg_graphics_addr, +-- q_a => bg_graphics1_do, +-- clk_b => clock_vid, +-- addr_b => dl_addr(12 downto 0), +-- we_b => bg_1_rom_we, +-- d_b => dl_data +--); + +-- background graphics ROM 2 +--bg_graphics_bits_2 : entity work.congo_bg_bits_2 +--port map( +-- clk => clock_vidn, +-- addr => bg_graphics_addr, +-- data => bg_graphics2_do +--); +--bg_2_rom_we <= '1' when dl_wr = '1' and dl_addr(17 downto 13) = "01000" else '0'; -- 10000-11FFF +--bg_graphics_bits_2 : entity work.dpram +--generic map( dWidth => 8, aWidth => 13) +--port map( +-- clk_a => clock_vidn, +-- addr_a => bg_graphics_addr, +-- q_a => bg_graphics2_do, +-- clk_b => clock_vid, +-- addr_b => dl_addr(12 downto 0), +-- we_b => bg_2_rom_we, +-- d_b => dl_data +--); + +-- background graphics ROM 3 +--bg_graphics_bits_3 : entity work.congo_bg_bits_3 +--port map( +-- clk => clock_vidn, +-- addr => bg_graphics_addr, +-- data => bg_graphics3_do +--); + +--bg_3_rom_we <= '1' when dl_wr = '1' and dl_addr(17 downto 13) = "01001" else '0'; -- 12000-13FFF +--bg_graphics_bits_3 : entity work.dpram +--generic map( dWidth => 8, aWidth => 13) +--port map( +-- clk_a => clock_vidn, +-- addr_a => bg_graphics_addr, +-- q_a => bg_graphics3_do, +-- clk_b => clock_vid, +-- addr_b => dl_addr(12 downto 0), +-- we_b => bg_3_rom_we, +-- d_b => dl_data +--); + +-- sprite graphics ROM 1 +--sp_graphics_bits_1 : entity work.congo_sp_bits_1 +--port map( +-- clk => clock_vidn, +-- addr => sp_graphics_addr, +-- data => sp_graphics1_do +--); + +--sp_1_rom_we <= '1' when dl_wr = '1' and dl_addr(17 downto 14) = "0110" else '0'; -- 18000-1BFFF +--sp_graphics_bits_1 : entity work.dpram +--generic map( dWidth => 8, aWidth => 14) +--port map( +-- clk_a => clock_vidn, +-- addr_a => sp_graphics_addr, +-- q_a => sp_graphics1_do, +-- clk_b => clock_vid, +-- addr_b => dl_addr(13 downto 0), +-- we_b => sp_1_rom_we, +-- d_b => dl_data +--); + +-- sprite graphics ROM 2 +--sp_graphics_bits_2 : entity work.congo_sp_bits_2 +--port map( +-- clk => clock_vidn, +-- addr => sp_graphics_addr, +-- data => sp_graphics2_do +--); + +--sp_2_rom_we <= '1' when dl_wr = '1' and dl_addr(17 downto 14) = "0101" else '0'; -- 14000-17FFF +--sp_graphics_bits_2 : entity work.dpram +--generic map( dWidth => 8, aWidth => 14) +--port map( +-- clk_a => clock_vidn, +-- addr_a => sp_graphics_addr, +-- q_a => sp_graphics2_do, +-- clk_b => clock_vid, +-- addr_b => dl_addr(13 downto 0), +-- we_b => sp_2_rom_we, +-- d_b => dl_data +--); + +-- sprite graphics ROM 3 +--sp_graphics_bits_3 : entity work.congo_sp_bits_3 +--port map( +-- clk => clock_vidn, +-- addr => sp_graphics_addr, +-- data => sp_graphics3_do +--); + +--sp_3_rom_we <= '1' when dl_wr = '1' and dl_addr(17 downto 14) = "0111" else '0'; -- 1C000-1FFFF +--sp_graphics_bits_3 : entity work.dpram +--generic map( dWidth => 8, aWidth => 14) +--port map( +-- clk_a => clock_vidn, +-- addr_a => sp_graphics_addr, +-- q_a => sp_graphics3_do, +-- clk_b => clock_vid, +-- addr_b => dl_addr(13 downto 0), +-- we_b => sp_3_rom_we, +-- d_b => dl_data +--); + +--congo_sound_board +sound_board : entity work.congo_sound_board +port map( + clock_24 => clock_24, + reset => reset, + sound_cmd => sound_cmd, + audio_out => audio_out, + + dl_addr => dl_addr, + dl_wr => dl_wr, + dl_data => dl_data, + + dbg_out => dbg_cpu_addr +); + +-- palette +--palette : entity work.congo_palette +--port map( +-- clk => clock_vidn, +-- addr => palette_addr, +-- data => palette_do +--); + +palette_rom_we <= '1' when dl_wr = '1' and dl_addr(17 downto 8) = "1010000000" else '0'; -- 28000-280FF +palette : entity work.dpram +generic map( dWidth => 8, aWidth => 8) +port map( + clk_a => clock_vidn, + addr_a => palette_addr, + q_a => palette_do, + clk_b => clock_vid, + addr_b => dl_addr(7 downto 0), + we_b => palette_rom_we, + d_b => dl_data +); + + +end struct; \ No newline at end of file diff --git a/Arcade_MiST/Sega Congo Bongo/rtl/congo_samples.bin b/Arcade_MiST/Sega Congo Bongo/rtl/congo_samples.bin new file mode 100644 index 0000000000000000000000000000000000000000..80d5f57dee75248f0e877f71d6d9396729f1758d GIT binary patch literal 11566 zcma)?2V9fa`o|UAx2>aEwN~5}uVSlp*M$hm5CqwKZ$d%>A%yG%5&|Ubkg)d_5CsIc z;j3ZndCr?4-roDU|C5g-zUMj5`Mu|Tljob?iIcUJ)vM9NhPj!$ zT8753W=|M4Y}jykOk6yS{2M-O%&_19R=`z=5%Prskw736@kIi@KqTY|ctVbB)vyWU zCVVhu(v;~lXV02DZ-ME;C1#&5TfS=bx-Ttkce;89M>Dx%Wwy4mp}qU?$qQF+efRy( zPk#UPmmj}>c>lXQ-`u=$?aJ4ezPfPk?CFzz$B!L3eDFZe{;sZldpq{Dx3;!4H#IiY z*VWckS5;M3l$Vv3mJ}E1w3>pv+-$WfL#arWNre35Bz8QLPK%BR3kmf1_4aUc+2y#? z-py)TPfSV{h$J$3T6(5BJ2zjWEh;H3uc)l9sjaJTXl!a~Zf?=H=H{lRMoJ*cD=jI~ z6>9R|N)riq+@!<=RvbMxCMq&KG$bf6z|Ysm+so6#-ObI_#l^+h&|F+xUESQ=Jv_a< zeSG}_0)s+A!y=-hX|aqrRsx&DK~W+nDVYa%fmk91Rf;radPb&7ot2#f z((>~Q3N)I+!a}W9tJ7(9@TAqke>Iu{5R;digL+h%8K5Xlo|*!h#3G@9&r9YeaX?o* z2xHJ=L0U|7R1~O-hzQ3P1`n#ik;tg1=;)XjS}Y0zMe#%uH<<^bghW+JD$xbPK$%Ld z&dSP$mV+%98+ipsva+(&Y8A>!SHco0KoOBdG@&R|1+o(2<5?^wGcJz7phJs=Ml&@0 zPb?l~pcp2L6(64ff)Y8LBrc^1M1d-aR4PkBVRD5cElsIRPX~1wnN(AO2z`Tt8PErM zP>?(o7D*vBC>G3P#H)=aYP=>juJrz3Ly=9 zh#n9`NdirJQA8EUg4F_D24y%e&Og}j05s5oYH)!-4+;WBuuLF{(gbS-tA!1xBHBRS zzc;E6{*p)>0(w9Yt`juK2U&5saKW&_bfn?be`$tJDpaotMWHH`g^Pt(ku);pTY-a8 z@P)pQ#NiMkiD<%XlqjOgplgUUg9?16lu+wKEfKX!m;^OJBeIAtGLc@~e}5uTgOYGG zl?PKoBkM)27%spNeFiOWSBLcL2T-F8qV%fX${L*Y-(OJj^?xZPOwF>i+}Rh!XeL&LJa*!BltB+|e9>tz4sh(Jgl za8nC}!<>KsUi?1@;AzXB%purMcjEG&X{I0V~)wZxu1TzXpz}^H%|G5Ti35c zVZV6c{Mpl|PM*NZe&|4N&;IVN&V5kY+gf)+ZPyp~nyT`m{7e~_9^&a>xo+8_xihCv z{b=gPCJUCV++^bt5W|tFbyZD!x_f)~cXxK|t}icCr}CJQ{_Z=iEjE6+X3d&)8!fDN zx(7tE_^DZi74^G2x_S;A=;_|u+EA&>NfRZ~!~EQxc34|&g_>{U;OrF`8J8qc=IAQw zTH5z^f}%aU8>>qS)N)}WJtENC&B zm$QeA#ldWwh}Pmc->^z-rZ^z`)h4G4*# zF%x+bc}8}=wz#aK5-6jrL|2fVsgUwHtk|fqVB`q^hQN^UXnK5-Kq}A3$}7|rmzH7u z*B0ce(^JKKPCPv(A~YDPJAg%KcvLKtoh+0oGSs;Rg}NeW+QR(YtPF)rn4HL>#{j7W z2L%NMLnMt6&*6z=iga}jAr39_O;)BdRSKc;jM(VN@USq1gJ>Fq#pd$GDT;JeHqc1{ z;f^d-xkbt0$L*b60$HgZm3m{YpfR&R6EjK4im64Vz74adI3A7X)1qD8a zhLK4;p@f7YTp&6C_sLTvLS7PtG7w+@1ZZ>yGa-@7hfujP9Z3YsIxvqSRVo%hC_or6 z1r2!tfC`cd#8SwLq0pfEr>DtNq#{8whB8ToN79K$^uka8FCZLfKnVaX6m}*i!~?28 zi;DvQ0d53HlTo1=z!Q*Dk(weEBcUd;5o@3^nSd%3&q-5K0h|y55Ii7K0>Fr&2~;gd zr~%9Z%94Np48@j)gd!CKgC_%+5Gq0303t(3#8BWKQoaex7=VwE6(IqN-2}*!5K2{h z%qfGUz=oKWPz4rf;1>icq&$Kxghf)M7zy)JWJHy6h(sWyLXjj$X&%aU1XrN!LQNx) zNNI>eq(S+H(v1{|7>N8pMH)g$ECxfVg<=Nt6Jn%jgH%Zh{eb;2lyHL{nMfo86IK7A zppsBRWEA{R^%1xMLs0?63-F{z60Bl|x(d$}^B6+)1=2t-q~hr-9F#ReY*@sgB9KUU zhW{Dh%TN_bB+idzSRYDi$Y3nVYp9d(K};eslxp}{4~IzEB~jELs3L>05P_9RA32CL zhC+j%?pR8&9~y~+XOeUXXHenq#*zUzmVnZbYG%l3NJ;|roPd3Xxydsg(3gFE903Y) z82-GCB}d3?hB$m4oPKDmelY2K=a0VQ-6ws-kgU{^cccDmPU`HTdvJ~Z8cNC3PxK%1 zz9W+S=RXADp}z*cJ@U?ww}*$m(ua`xf9?NK|Jxx(BoPYXEiQo56H5dVo|LQHI(*XD z564fQFzKUdGv>^lzj#Md=Z_B`-TUtLty}-Na^>=s3#ZSW?mK<@$l=3>4)%0+cXxH{ z>DbfOhTrT-^@rMDsFEgxd)Ta7GJDGVqemEz96ND_=_)JNuta%5b?g4ahY$94cQjSx zE0Spe&f7Px{Os?hri(vcZEoit!W3m{Yg)Sw9XoOS=z)FBl^Ugh8Rq3^ZN7f(nzb9Y zSUdTIvxMoIil&a9Lr0GuKG4-#Tb!N3jScp4vavMZw8`Akc9(Z3BUzqPT+`Cg-Fu+7 zd++YrlH4=_3+TepcAMo^D{FffpHO;|RHZ3Lu;}jY+|yE9R*)g#5UQ}ZwXv~7njQk@rRQi$DynON z94bl*^)wO!h~e($?&TX8PGfP!3U!{Yw4$n}rmCV;m#0=p5JN%&e7(KAeEfpKW0)L) zEIlhVX_c5blSp#yetgiu;|gi zB!C$h0+b_8RjP9eG-wxS@^e(m6cNG*07fWUA<@Vz03w-?2CapHyd1SM71G2rVxl6# zLV-aDtN?+eK@3_DV8p1Da*2S;X3`-B+=B=RVI@*LlbweldD-fWv=lKvDFI`^YCt?; zvbh3DN?HcEKZqt6l8R|q3>t6=hQ!7p7D?p@FlZ%Yt25K(GDyQ_#StQjiKR0WI6R>= zH7!GxMYsh*6e(f>U=w&%04)^VaQToX4Lu#;6?C+KY?3)>8PUN1003gKDF6ae(KAgN z%p{;<5NPNORssibiWpW%GpbBv83ZJ-#SnU8V;M|LL&cyQf)oQ}1h~TiE&(!PKm_m; zpcbaV5QqWL0nXuZk%$a29E!0phOiJ=N@6MmBEbJZWFl~tif}bFh5{>uC8VlkIPVk% zl_nF!;7oij2Y`x7GstKJywICLKBG_$pbJ5Y3V}3eih&$FCqoRJ6)`^uzX_4w(4qp+ zBJ2j31!{(*0X1N*=|iY21lrJx0t-dYc9j1HS%?^!L}cJP5<^H4(-2Yv<3^qWAwmLl z=*|$D1DGTs6w4vXVGPMb91_4dLXmn?jnE#ZAx0vc6qUvh17`)G2bhQKhPIv_@(2tf zj1o1-f(pP(OasgY%t&k)m`U#{5()&eL)(jl0D_`#!v^{s8iG!gff51zh{Hp$4^YYg zh-g(Io&m@WhUn3da^;Zr2<#EoG@u?b;h=E`^f(v;K#bU?_pJ=(-XPu)4kaEP1R)0M z$&$jwK~@B)ApnT%M4h{iKh|=R77I$EfL9ioO2Yv5QB@}Z*$Pl80$q@J;0|5m5cCQ`& zzy1Aqhyiww7-swO`9Gii(C9H~^r!`iC!asNTN`RNY3deU*X;*qHGa!XOr27@uU_j( z_grPV#!uCC{&b7PZQb&%k-7U$9IWKJZu-(8PSbI)qcGmpVyg#7*WTHb&2Zgr8z3xh zZLdzJx!XB~OG}!YN>igf96f0A(uO*%B+Ap-kEtxJtIQKddbme8Wyi;P9oXic~R=!%pN1;G309#7pA92eLE;zAVBWjvwDL@*&B^ zO#`^|;hjp}0gg6y z&H;3BUQI`5d%ae{4tBD#uyzh&r54sT)tBc=A;Q{rmp@&cThn>uNOyCQA|cRW{o+qP zoHBcvrFVQrbw;^8?7ahaoDKxbmz1?k9If7_+%XRC_clgALvI{ji za&EMjot3qdUo1@D*49{-C8Uu9{tQW8bz@z5u8bAvWWH?f^pEGSwD#v@)gQWi=ewKd zdu!B5!4B(}%r{-W#WhB%Ywx@9_@;)#9b=?VUJ zYZuL1xZJ`mMuxe6`194XN0$#&DH-054$i*ONeWe_oJS9EvaxmYr3tdDIu0M%zq>>U zD`&aY)-@zSQPi|=Z%akCAj;ip#r!E_M~s`c*usact~+$)(ewWP{->~**@?c}mYGbN zIDO$dN1Xh`wTF*?xqGp^^?&-gh_7c2{O3 z_}Q%dbne10EIndVirY`#_~99j*i$G9-?{G7$s>)7|7NmcN0>;v=ghZ{`(YWM-#gus zljyg@YMZ@h1Xroi6{y6_Ag3*B*P7e=(#1JNx_l*{=DTCV(%Dl#p1;D{KT%zG@bZH{ z1_lORJo;*{RuHmd)!fMwr!H7+7o40^*VWtAT9GA)_I7pmkLIQqw;Vis;bd=OW=Kbtja^vL&TF0&5eYg$j^D7S^_0tF-OQJKJl4o))HE}zfaLs^4;yqAR;_Klpp$lNPlReSJj5Z?d#@vUR^nJmvOi>Hk-GX7xpD*JG;ZqKP( zKR$o?WT@4y3-P_i}(#|7- zn_1f2+E|ezVffl@*|Oawl&vgo-qTiJq)ZBPwRdm}ij(Ho?LTw#hd&42ym>PK%lzX0 zsRm_?<0_M}#v_c4$1hm#8Y?gD=)3md_m^;+ycziIYEKc*-@l1Yu^A5^Yq~u= zrSibnkNycE@PIq_)q}p8lyIBRr^2mPaTa(V6M3veUc0Je)Z@j z_QC@`^ag%|JPemF=TCr{V7?JXqvve)6BKn{{^|9<-uw#}31@rp4J?D-RCan-DpI1H$Snk`1b5$zwQdQyZRZ}qLXu3>g8zJ~P9AB$YW92j zB^bZNIy|MK_sUPN@YMeG@?KvuJhveFX7x@_YXY3eWXf3 zbJ@5E-VLM~PhRFg%V_AkgENs89Dq-Xf#1$GrN=m~nfn111s84NvYoLRjeWPD4L}-P z=>FFOznyQ+q&u&hH=bNCoNxTn9ns4A&SR7-cv2!+f zaSHaFyZ8L<^1S)=TytjZE=YrmLu9|d*g8TEm;QHH9GDHI^}o7*q(VY&5WF2BY=rUH zdFBD4(jK^t$o1-f_3%_hY{uW<7BU_&39p zC+d{3u!>VhgA$|RsIr=wG5LA#cxPW->Q&;YaQ#GEr^%!rB*Zog#9I8x>A@|QPyrh4d zx6zB8+j8=o-}}ia;cP#gZp?u9)`E%nj>jM)<7um0SlKP7@8XG**#_P`y|Oo-Edonqt_-52kHAhMuPSnu~WWW;%F zG5dskHbB_u87p^2VI{irn0z|GiM_mk8XyhJ;&|iX!^ccF1AbNuV?et!1+_xqO))TlW@4jav8PaX%e4L5pk)=K*@ zp{C^+6k@!0-@JJ6RcA>`tmn2>3r%J%Tw&=RBg(7WfBO2ppMH68y>Cykoawh?{nEK6 zbC;~M^No`gHujvkcIVFZGy7`+6g{@DSv+Uff@PbXLOAIqyAPfJ$DMDl^zE(4ObTg%f4$P**H z94yT(tatgvB+2tDTDp#$JagheTUD+sKFrhJV%@4Wo2*@f;)I#Hn)dxiPXL%!VlZ_jAsH&p6_MW4C$9vmrGzxA^fQ#*x^&7U>x(3pDY5C<%9s7aUYIGSw zW|+6*cJqzq+nszO*%Fnmx@B+Af&J}u#cD}Hq_4BB#fJ6J=Zk%X71fm`V1RNNVZN>o zI~-hm!s2+~vR1cr?C;sPyGEyyu%iRq9kyFq**W`0u!PFI(%Rh}-CcVc%k$It%y3^< z`)ymTz?}_?MFEZsXP`KwJwf3 zojv>`7)jzZl{yo?3MMgQ!UAA#HH;RYELCQM<62W&RiaU+3fQsX0bU-SzCn=;jxaSd z8!STD=1qVdVLxwgzhFEnSAqRnRa;+IRjMBm=ZiQq#dq)#?htvrQFo6X;Q4 zLH=;Mq0q^LFT=1qtkLA__nPTZ;jn)k2piJG&4vBoe2pd#I|WH#!A5`q8yORqz!gg6 zWCJ)4yjT3*OkCcO&_A;Z8Tq})F=zrY#8{a$JhnGC=Y zXt3!=kUnYzW+S__IEegE3~U?NPDG=Hcx-yl&v0}|EM+=khkoaEu#ehoCT^pC$B&qP z_-if*$Mn=zt$xcHryvF<=``#k>a9W?q#p*RA5lfDzqi}T)M35g!TsyOnW!'0'); + clock_cnt2 <= (others=>'0'); + else + if rising_edge(clock_24) then + ck1_ena <= '0'; + ck4_ena <= '0'; + + if clock_cnt1 = "101" then -- divide by 6 + ck4_ena <= '1'; + if clock_cnt2(1 downto 0) = "01" then ck1_ena <= '1'; end if; + + clock_cnt1 <= (others=>'0'); + if clock_cnt2 = x"F" then -- divide by 16 + clock_cnt2 <= (others=>'0'); + else + clock_cnt2 <= clock_cnt2 + 1; + end if; + else + clock_cnt1 <= clock_cnt1 + 1; + end if; + end if; + end if; +end process; + +process (clock_24, reset) +begin + if reset='1' or cpu_ioreq_n = '0' then -- reset on INT acknowledge + clock_cnt3 <= (others=>'0'); + else + if rising_edge(clock_24) then + if clock_cnt2 = x"F" and clock_cnt1 = "101" then + clock_cnt3 <= clock_cnt3 + 1; + end if; + end if; + end if; +end process; + +------------------------------------------ +-- cpu data input with address decoding -- +------------------------------------------ +cpu_di <= cpu_rom_do when cpu_mreq_n = '0' and cpu_addr(15 downto 13) = "000" else -- 0000-1FFF + wram_do when cpu_mreq_n = '0' and cpu_addr(15 downto 13) = "010" else -- 4000-47FF + mirror 1800 + sound_cmd when cpu_mreq_n = '0' and cpu_addr(15 downto 13) = "100" and cpu_addr(1 downto 0) = "00" else -- 8000 + ppi_port_b when cpu_mreq_n = '0' and cpu_addr(15 downto 13) = "100" and cpu_addr(1 downto 0) = "01" else -- 8001 + ppi_port_c when cpu_mreq_n = '0' and cpu_addr(15 downto 13) = "100" and cpu_addr(1 downto 0) = "10" else -- 8002 + X"FF"; + +------------------------------------------ +-- write enable to working ram from CPU -- +------------------------------------------ +wram_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and cpu_addr(15 downto 13) = "010" else '0'; -- 4000-47FF + mirror 1800 + +psg1_ce_n <= '0' when cpu_mreq_n = '0' and (cpu_rd_n = '0' or cpu_wr_n = '0') and cpu_addr(15 downto 13) = "011" else '1'; -- 6000-7FFF +psg2_ce_n <= '0' when cpu_mreq_n = '0' and (cpu_rd_n = '0' or cpu_wr_n = '0') and cpu_addr(15 downto 13) = "101" else '1'; -- A000-BFFF + +------------------------------------------------------------------------ +-- Misc registers, interrupt +------------------------------------------------------------------------ +cpu_irq_n <= not clock_cnt3(10); +cpu_wait_n <= '1' when psg1_rdy = '1' and psg2_rdy = '1' else '0'; + +process (clock_24, reset) +begin + if reset='1' then + ppi_port_b <= (others=>'0'); + ppi_port_c <= (others=>'0'); + else + if rising_edge(clock_24) then + if cpu_mreq_n = '0' and cpu_wr_n = '0' then + if cpu_addr(15 downto 13) = "100" and cpu_addr(1 downto 0) = "01" then ppi_port_b <= cpu_do; end if; -- 8001 + if cpu_addr(15 downto 13) = "100" and cpu_addr(1 downto 0) = "10" then ppi_port_c <= cpu_do; end if; -- 8002 + end if; + end if; + end if; +end process; + +------------------------------- +-- sound -- +------------------------------- + +audio_out <= (('0'&psg1_audio) + ('0'&psg2_audio)) & "0000000" + ("00"&samples_audio(15 downto 2)); + +---------------- +-- components -- +---------------- + +-- microprocessor Z80 +cpu : entity work.T80se +generic map(Mode => 0, T2Write => 1, IOWait => 1) +port map( + RESET_n => reset_n, + CLK_n => clock_24, + CLKEN => ck4_ena, + WAIT_n => cpu_wait_n, + INT_n => cpu_irq_n, + NMI_n => '1', + BUSRQ_n => '1', + M1_n => cpu_m1_n, + MREQ_n => cpu_mreq_n, + IORQ_n => cpu_ioreq_n, + RD_n => cpu_rd_n, + WR_n => cpu_wr_n, + RFSH_n => open, + HALT_n => open, + BUSAK_n => open, + A => cpu_addr, + DI => cpu_di, + DO => cpu_do +); + +-- cpu program ROM 0x0000-0x1FFF +--rom_cpu : entity work.congo_sound_cpu +--port map( +-- clk => clock_24n, +-- addr => cpu_addr(12 downto 0), +-- data => cpu_rom_do +--); + +cpu_rom_we <= '1' when dl_wr = '1' and dl_addr(17 downto 13) = "10011" else '0'; -- 26000-27FFF +rom_cpu : entity work.dpram +generic map( dWidth => 8, aWidth => 13) +port map( + clk_a => clock_24n, + addr_a => cpu_addr(12 downto 0), + q_a => cpu_rom_do, + clk_b => clock_24, + addr_b => dl_addr(12 downto 0), + we_b => cpu_rom_we, + d_b => dl_data +); + +-- working RAM 0x4000-0x47FF +wram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 11) +port map( + clk => clock_24n, + we => wram_we, + addr => cpu_addr(10 downto 0), + d => cpu_do, + q => wram_do +); + +---- samples data -- +samples : entity work.congo_samples +port map( + clk => clock_24n, + addr => wave_addr(13 downto 0), + data => wave_data +); + +-- PSG1 +psg1 : entity work.sn76489_top +-- +-- generic ( +-- clock_div_16_g : integer := 1 +-- ); +port map( + clock_i => clock_24, + clock_en_i => ck4_ena, + res_n_i => reset_n, + ce_n_i => psg1_ce_n, + we_n_i => cpu_wr_n, + ready_o => psg1_rdy, + d_i => cpu_do, + aout_o => psg1_audio +); + +-- PSG2 +psg2 : entity work.sn76489_top +-- +-- generic ( +-- clock_div_16_g : integer := 1 +-- ); +port map( + clock_i => clock_24, + clock_en_i => ck1_ena, + res_n_i => reset_n, + ce_n_i => psg2_ce_n, + we_n_i => cpu_wr_n, + ready_o => psg2_rdy, + d_i => cpu_do, + aout_o => psg2_audio +); + + +samples_player : entity work.samples_player +port map( + clock_24 => clock_24, + reset => reset, + + port_b => ppi_port_b, + port_c => ppi_port_c, + + audio_out => samples_audio, + + wave_addr => wave_addr, + wave_rd => open, + wave_data => wave_data + ); + +end struct; \ No newline at end of file diff --git a/Arcade_MiST/Sega Congo Bongo/rtl/dpram.vhd b/Arcade_MiST/Sega Congo Bongo/rtl/dpram.vhd new file mode 100644 index 00000000..1495bb42 --- /dev/null +++ b/Arcade_MiST/Sega Congo Bongo/rtl/dpram.vhd @@ -0,0 +1,87 @@ +-- ----------------------------------------------------------------------- +-- +-- Syntiac's generic VHDL support files. +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- +-- Modified April 2016 by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +-- Remove address register when writing +-- +-- ----------------------------------------------------------------------- +-- +-- dpram.vhd +-- +-- ----------------------------------------------------------------------- +-- +-- generic ram. +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +entity dpram is + generic ( + dWidth : integer := 8; + aWidth : integer := 10 + ); + port ( + clk_a : in std_logic; + we_a : in std_logic := '0'; + addr_a : in std_logic_vector((aWidth-1) downto 0); + d_a : in std_logic_vector((dWidth-1) downto 0) := (others => '0'); + q_a : out std_logic_vector((dWidth-1) downto 0); + + clk_b : in std_logic; + we_b : in std_logic := '0'; + addr_b : in std_logic_vector((aWidth-1) downto 0); + d_b : in std_logic_vector((dWidth-1) downto 0) := (others => '0'); + q_b : out std_logic_vector((dWidth-1) downto 0) + ); +end entity; + +-- ----------------------------------------------------------------------- + +architecture rtl of dpram is + subtype addressRange is integer range 0 to ((2**aWidth)-1); + type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0); + signal ram: ramDef; + ATTRIBUTE ramstyle : string; + ATTRIBUTE ramstyle OF ram : SIGNAL IS "no_rw_check"; + signal addr_a_reg: std_logic_vector((aWidth-1) downto 0); + signal addr_b_reg: std_logic_vector((aWidth-1) downto 0); +begin + +-- ----------------------------------------------------------------------- + process(clk_a) + begin + if rising_edge(clk_a) then + if we_a = '1' then + ram(to_integer(unsigned(addr_a))) <= d_a; + q_a <= d_a; + else + q_a <= ram(to_integer(unsigned(addr_a))); + end if; + end if; + end process; + + process(clk_b) + begin + if rising_edge(clk_b) then + if we_b = '1' then + ram(to_integer(unsigned(addr_b))) <= d_b; + q_b <= d_b; + else + q_b <= ram(to_integer(unsigned(addr_b))); + end if; + end if; + end process; + +end architecture; + diff --git a/Arcade_MiST/Sega Congo Bongo/rtl/gen_ram.vhd b/Arcade_MiST/Sega Congo Bongo/rtl/gen_ram.vhd new file mode 100644 index 00000000..1f47e1f9 --- /dev/null +++ b/Arcade_MiST/Sega Congo Bongo/rtl/gen_ram.vhd @@ -0,0 +1,63 @@ +-- ----------------------------------------------------------------------- +-- +-- Syntiac's generic VHDL support files. +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- +-- Modified April 2016 by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +-- Remove address register when writing +-- +-- ----------------------------------------------------------------------- +-- +-- gen_rwram.vhd +-- +-- ----------------------------------------------------------------------- +-- +-- generic ram. +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +entity gen_ram is + generic ( + dWidth : integer := 8; + aWidth : integer := 10 + ); + port ( + clk : in std_logic; + we : in std_logic; + addr : in std_logic_vector((aWidth-1) downto 0); + d : in std_logic_vector((dWidth-1) downto 0); + q : out std_logic_vector((dWidth-1) downto 0) + ); +end entity; + +-- ----------------------------------------------------------------------- + +architecture rtl of gen_ram is + subtype addressRange is integer range 0 to ((2**aWidth)-1); + type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0); + signal ram: ramDef; +begin + + process(clk) + begin + if rising_edge(clk) then + if we = '1' then + ram(to_integer(unsigned(addr))) <= d; + q <= d; + else + q <= ram(to_integer(unsigned(addr))); + end if; + end if; + end process; + +end architecture; diff --git a/Arcade_MiST/Sega Congo Bongo/rtl/pll_mist.qip b/Arcade_MiST/Sega Congo Bongo/rtl/pll_mist.qip new file mode 100644 index 00000000..6182871f --- /dev/null +++ b/Arcade_MiST/Sega Congo Bongo/rtl/pll_mist.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_mist.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_mist.ppf"] diff --git a/Arcade_MiST/Sega Congo Bongo/rtl/pll_mist.v b/Arcade_MiST/Sega Congo Bongo/rtl/pll_mist.v new file mode 100644 index 00000000..f54914f7 --- /dev/null +++ b/Arcade_MiST/Sega Congo Bongo/rtl/pll_mist.v @@ -0,0 +1,337 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll_mist.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2014 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll_mist ( + inclk0, + c0, + c1, + locked); + + input inclk0; + output c0; + output c1; + output locked; + + wire [4:0] sub_wire0; + wire sub_wire2; + wire [0:0] sub_wire6 = 1'h0; + wire [0:0] sub_wire3 = sub_wire0[0:0]; + wire [1:1] sub_wire1 = sub_wire0[1:1]; + wire c1 = sub_wire1; + wire locked = sub_wire2; + wire c0 = sub_wire3; + wire sub_wire4 = inclk0; + wire [1:0] sub_wire5 = {sub_wire6, sub_wire4}; + + altpll altpll_component ( + .inclk (sub_wire5), + .clk (sub_wire0), + .locked (sub_wire2), + .activeclock (), + .areset (1'b0), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 9, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 16, + altpll_component.clk0_phase_shift = "0", + altpll_component.clk1_divide_by = 9, + altpll_component.clk1_duty_cycle = 50, + altpll_component.clk1_multiply_by = 8, + altpll_component.clk1_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_mist", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_UNUSED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_USED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "24.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "24.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_mist.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "16" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "8" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Sega Congo Bongo/rtl/samples_player.vhd b/Arcade_MiST/Sega Congo Bongo/rtl/samples_player.vhd new file mode 100644 index 00000000..af7d0189 --- /dev/null +++ b/Arcade_MiST/Sega Congo Bongo/rtl/samples_player.vhd @@ -0,0 +1,193 @@ +---------------- +-- Wave player -- +----------------- + +-- Congo samples - start/stop addresses as stored in memory + +-- bass.wav e:RIFF n:1 sr:11025 br:11025 al:1 bps:8 lg: 2005 start: 44(x 2C) stop: 2050(x 802) +-- congal.wav e:RIFF n:1 sr:11025 br:11025 al:1 bps:8 lg: 2003 start: 2094(x 82E) stop: 4098(x 1002) +-- congah.wav e:RIFF n:1 sr:11025 br:11025 al:1 bps:8 lg: 1970 start: 4142(x 102E) stop: 6112(x 17E0) +-- rim.wav e:RIFF n:1 sr:11025 br:11025 al:1 bps:8 lg: 373 start: 6156(x 180C) stop: 6530(x 1982) +-- gorilla.wav e:RIFF n:1 sr:11025 br:11025 al:1 bps:8 lg: 4991 start: 6574(x 19AE) stop: 11566(x 2D2E) + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity samples_player is +port( + clock_24 : in std_logic; + reset : in std_logic; + + port_b : in std_logic_vector(7 downto 0); + port_c : in std_logic_vector(7 downto 0); + + audio_out : out std_logic_vector(15 downto 0); + + wave_addr : buffer std_logic_vector(15 downto 0); + wave_rd : out std_logic; + wave_data : in std_logic_vector(7 downto 0) + ); +end samples_player; + +architecture struct of samples_player is + + signal wav_clk_cnt : std_logic_vector(11 downto 0); -- 11kHz divider / sound# counter + + subtype snd_id_t is integer range 0 to 4; + signal snd_id : snd_id_t; + + type snd_addr_t is array(snd_id_t) of std_logic_vector(15 downto 0); + + -- wave current addresses in memory + signal snd_addrs : snd_addr_t; + +-- bass.wav e:RIFF n:1 sr:11025 br:11025 al:1 bps:8 lg: 2005 start: 44(x 2C) stop: 2050(x 802) +-- congal.wav e:RIFF n:1 sr:11025 br:11025 al:1 bps:8 lg: 2003 start: 2094(x 82E) stop: 4098(x 1002) +-- congah.wav e:RIFF n:1 sr:11025 br:11025 al:1 bps:8 lg: 1970 start: 4142(x 102E) stop: 6112(x 17E0) +-- rim.wav e:RIFF n:1 sr:11025 br:11025 al:1 bps:8 lg: 373 start: 6156(x 180C) stop: 6530(x 1982) +-- gorilla.wav e:RIFF n:1 sr:11025 br:11025 al:1 bps:8 lg: 4991 start: 6574(x 19AE) stop: 11566(x 2D2E) + + -- wave start addresses in memory + signal snd_starts : snd_addr_t := (x"002C",x"082E",x"102E",x"180C",x"19AE"); + + -- wave end addresses in memory + signal snd_stops : snd_addr_t := (x"0800",x"1000",x"17DE",x"1980",x"2D2C"); + + type snd_flag_t is array(snd_id_t) of std_logic; + + -- sound playing (once) + signal snd_starteds : snd_flag_t := ('0','0','0','0','0'); + -- sound to be restarted + signal snd_restarts : snd_flag_t := ('0','0','0','0','0'); + -- sound playing (loop) + signal snd_continus : snd_flag_t := ('0','0','0','0','0'); + + signal port_b_r : std_logic_vector(7 downto 0); + signal port_c_r : std_logic_vector(7 downto 0); + + -- sum all sound + signal audio_r, audio_sum : signed(18 downto 0); + signal audio_vol : signed(15 downto 0); + +-- signal wave_addr : std_logic_vector(15 downto 0); +-- signal wave_data : std_logic_vector( 7 downto 0); + +begin + +-- scan sound# from 0-4 +snd_id <= to_integer(unsigned(wav_clk_cnt(7 downto 5))) when wav_clk_cnt(11 downto 5) <= 4 else 0; + +audio_vol <= (signed('0'&wave_data)-to_signed(128,9))&"0000000"; -- congo samples memory is uint8 + +-- wave player +process (clock_24, reset) +begin + if reset='1' then + wav_clk_cnt <= (others=>'0'); + else + if rising_edge(clock_24) then + + port_b_r <= port_b; + port_c_r <= port_c; + + -- sound triggers + + -- snd_continus : play loop as long as set + -- snd_starteds : edge trigger start playing when currently stopped + -- snd_restarts : edge trigger restart from beginning + + snd_starteds( 0) <= snd_starteds( 0) or (not(port_c(0)) and port_c_r(0)); -- bass +-- snd_restarts( 0) <= snd_restarts( 0) or (not(port_c(0)) and port_c_r(0)); + + snd_starteds( 1) <= snd_starteds( 1) or (not(port_c(1)) and port_c_r(1)); -- congal + + snd_starteds( 2) <= snd_starteds( 2) or (not(port_c(2)) and port_c_r(2)); -- congah + + snd_starteds( 3) <= snd_starteds( 3) or (not(port_c(3)) and port_c_r(3)); -- rim + + snd_starteds( 4) <= snd_starteds( 4) or (not(port_b(1)) and port_b_r(1)); -- gorilla + + -- 11.025kHz base tempo / high bits for scanning sound# + if wav_clk_cnt = x"880" then -- divide 24MHz by 2176 => 11.025kHz + wav_clk_cnt <= (others=>'0'); + + -- latch final audio / reset sum + audio_r <= audio_sum; + audio_sum <= (others => '0'); + else + wav_clk_cnt <= wav_clk_cnt + 1; + end if; + + -- clip audio + if audio_r(18 downto 1) > 32767 then + audio_out <= x"7FFF"; + elsif audio_r(18 downto 1) < -32767 then + audio_out <= x"8001"; + else + audio_out <= std_logic_vector(audio_r(16 downto 1)+to_signed(32767,16)); + end if; + + -- sdram read trigger (and auto refresh period) + if wav_clk_cnt(4 downto 0) = "00000" then wave_rd <= '1';end if; + if wav_clk_cnt(4 downto 0) = "00010" then wave_rd <= '0';end if; + + -- select only useful cycles (0-4) + -- remaing cycles unsued + if wav_clk_cnt(11 downto 5) <= 4 then + + -- set sdram addr at begining of cycle + if wav_clk_cnt(4 downto 0) = "00000" then + wave_addr <= snd_addrs(snd_id); + end if; + + -- sound# currently playing + if (snd_starteds(snd_id) = '1' or snd_continus(snd_id) = '1' ) then + + -- get sound# sample and update next sound# address + -- (next / restart) + if wav_clk_cnt(4 downto 0) = "10000" then + + audio_sum <= audio_sum + audio_vol; + + if snd_restarts(snd_id) = '1' then + snd_addrs(snd_id) <= snd_starts(snd_id); + snd_restarts(snd_id) <= '0'; + else + snd_addrs(snd_id) <= snd_addrs(snd_id) + 1; + end if; + end if; + + -- update next sound# address + -- (stop / loop) + if snd_addrs(snd_id) >= snd_stops(snd_id) then + if snd_continus(snd_id) = '1' then + snd_addrs(snd_id) <= snd_starts(snd_id); + else + snd_starteds(snd_id) <= '0'; + end if; + end if; + + else + -- sound# stopped set begin address + snd_addrs(snd_id) <= snd_starts(snd_id); + end if; + + end if; + + end if; + end if; +end process; + + +-- samples data -- +--samples : entity work.congo_samples +--port map( +-- clk => clock_24, +-- addr => wave_addr(13 downto 0), +-- data => wave_data +--); + + +end struct; \ No newline at end of file diff --git a/Arcade_MiST/Sega Congo Bongo/rtl/sdram.sv b/Arcade_MiST/Sega Congo Bongo/rtl/sdram.sv new file mode 100644 index 00000000..e561f665 --- /dev/null +++ b/Arcade_MiST/Sega Congo Bongo/rtl/sdram.sv @@ -0,0 +1,360 @@ +// +// sdram.v +// +// sdram controller implementation for the MiST board +// https://github.com/mist-devel/mist-board +// +// Copyright (c) 2013 Till Harbaum +// Copyright (c) 2019 Gyorgy Szombathelyi +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +module sdram ( + + // interface to the MT48LC16M16 chip + inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus + output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus + output reg SDRAM_DQML, // two byte masks + output reg SDRAM_DQMH, // two byte masks + output reg [1:0] SDRAM_BA, // two banks + output SDRAM_nCS, // a single chip select + output SDRAM_nWE, // write enable + output SDRAM_nRAS, // row address select + output SDRAM_nCAS, // columns address select + + // cpu/chipset interface + input init_n, // init signal after FPGA config to initialize RAM + input clk, // sdram clock + + input port1_req, + output reg port1_ack, + input port1_we, + input [23:1] port1_a, + input [1:0] port1_ds, + input [15:0] port1_d, + output reg [15:0] port1_q, + + input [19:1] cpu1_addr, + output reg [15:0] cpu1_q, + input [19:1] cpu2_addr, + output reg [15:0] cpu2_q, + + input port2_req, + output reg port2_ack, + input port2_we, + input [23:1] port2_a, + input [1:0] port2_ds, + input [15:0] port2_d, + output reg [31:0] port2_q, + + input [14:2] bg_addr, + output reg [31:0] bg_q, + input [17:2] sp_addr, + output reg [31:0] sp_q +); + +parameter MHZ = 16'd80; // 80 MHz default clock, set it to proper value to calculate refresh rate + +localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz +localparam BURST_LENGTH = 3'b001; // 000=1, 001=2, 010=4, 011=8 +localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved +localparam CAS_LATENCY = 3'd2; // 2/3 allowed +localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed +localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write + +localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH}; + +// 64ms/8192 rows = 7.8us +localparam RFRSH_CYCLES = 16'd78*MHZ/4'd10; + +// --------------------------------------------------------------------- +// ------------------------ cycle state machine ------------------------ +// --------------------------------------------------------------------- + +/* + SDRAM state machine for 2 bank interleaved access + 1 word burst, CL2 +cmd issued registered + 0 RAS0 + 1 ras0 - data1 returned + 2 data1 returned + 3 CAS0 + 4 RAS1 cas0 + 5 ras1 + 6 CAS1 data0 returned + 7 cas1 - data0 read masked by DQM +*/ + +localparam STATE_RAS0 = 3'd0; // first state in cycle +localparam STATE_RAS1 = 3'd4; // Second ACTIVE command after RAS0 + tRRD (15ns) +localparam STATE_CAS0 = STATE_RAS0 + RASCAS_DELAY + 1'd1; // CAS phase - 3 +localparam STATE_CAS1 = STATE_RAS1 + RASCAS_DELAY; // CAS phase - 6 +localparam STATE_READ0 = STATE_CAS0 + CAS_LATENCY + 2'd2; // 7 +localparam STATE_READ1 = 3'd2; +localparam STATE_DS1b = 3'd7; +localparam STATE_READ1b = 3'd3; +localparam STATE_LAST = 3'd7; + +reg [2:0] t; + +always @(posedge clk) begin + t <= t + 1'd1; + if (t == STATE_LAST) t <= STATE_RAS0; +end + +// --------------------------------------------------------------------- +// --------------------------- startup/reset --------------------------- +// --------------------------------------------------------------------- + +// wait 1ms (32 8Mhz cycles) after FPGA config is done before going +// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0) +reg [4:0] reset; +reg init = 1'b1; +always @(posedge clk, negedge init_n) begin + if(!init_n) begin + reset <= 5'h1f; + init <= 1'b1; + end else begin + if((t == STATE_LAST) && (reset != 0)) reset <= reset - 5'd1; + init <= !(reset == 0); + end +end + +// --------------------------------------------------------------------- +// ------------------ generate ram control signals --------------------- +// --------------------------------------------------------------------- + +// all possible commands +localparam CMD_INHIBIT = 4'b1111; +localparam CMD_NOP = 4'b0111; +localparam CMD_ACTIVE = 4'b0011; +localparam CMD_READ = 4'b0101; +localparam CMD_WRITE = 4'b0100; +localparam CMD_BURST_TERMINATE = 4'b0110; +localparam CMD_PRECHARGE = 4'b0010; +localparam CMD_AUTO_REFRESH = 4'b0001; +localparam CMD_LOAD_MODE = 4'b0000; + +reg [3:0] sd_cmd; // current command sent to sd ram +reg [15:0] sd_din; // Fast Input register latching incoming SDRAM data + +// drive control signals according to current command +assign SDRAM_nCS = sd_cmd[3]; +assign SDRAM_nRAS = sd_cmd[2]; +assign SDRAM_nCAS = sd_cmd[1]; +assign SDRAM_nWE = sd_cmd[0]; + +reg [24:1] addr_latch[2]; +reg [24:1] addr_latch_next[2]; +reg [19:1] addr_last[2]; +reg [17:2] addr_last2[2]; +reg [15:0] din_latch[2]; +reg [1:0] oe_latch; +reg [1:0] we_latch; +reg [1:0] ds[2]; + +reg port1_state; +reg port2_state; + +localparam PORT_NONE = 2'd0; +localparam PORT_CPU1 = 2'd1; +localparam PORT_CPU2 = 2'd2; +localparam PORT_BG = 2'd1; +localparam PORT_SP = 2'd2; +localparam PORT_REQ = 2'd3; + +reg [1:0] next_port[2]; +reg [1:0] port[2]; + +reg refresh; +reg [11:0] refresh_cnt; +reg need_refresh; + +// PORT1: bank 0,1 +always @(*) begin + if (refresh) begin + next_port[0] = PORT_NONE; + addr_latch_next[0] = addr_latch[1]; + end else if (port1_req ^ port1_state) begin + next_port[0] = PORT_REQ; + addr_latch_next[0] = { 1'b0, port1_a }; + end else if (cpu1_addr != addr_last[PORT_CPU1]) begin + next_port[0] = PORT_CPU1; + addr_latch_next[0] = { 5'd0, cpu1_addr }; + end else if (cpu2_addr != addr_last[PORT_CPU2]) begin + next_port[0] = PORT_CPU2; + addr_latch_next[0] = { 5'd0, cpu2_addr }; + end else begin + next_port[0] = PORT_NONE; + addr_latch_next[0] = addr_latch[0]; + end +end + +// PORT1: bank 2,3 +always @(*) begin + if (port2_req ^ port2_state) begin + next_port[1] = PORT_REQ; + addr_latch_next[1] = { 1'b1, port2_a }; + end else if (sp_addr != addr_last2[PORT_SP]) begin + next_port[1] = PORT_SP; + addr_latch_next[1] = { 1'b1, 6'd0, sp_addr, 1'b0 }; + end else if (bg_addr != addr_last2[PORT_BG]) begin + next_port[1] = PORT_BG; + addr_latch_next[1] = { 1'b1, 9'd0, bg_addr, 1'b0 }; + end else begin + next_port[1] = PORT_NONE; + addr_latch_next[1] = addr_latch[1]; + end +end + +always @(posedge clk) begin + + // permanently latch ram data to reduce delays + sd_din <= SDRAM_DQ; + SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ; + { SDRAM_DQMH, SDRAM_DQML } <= 2'b11; + sd_cmd <= CMD_NOP; // default: idle + refresh_cnt <= refresh_cnt + 1'd1; + need_refresh <= (refresh_cnt >= RFRSH_CYCLES); + + if(init) begin + // initialization takes place at the end of the reset phase + if(t == STATE_RAS0) begin + + if(reset == 15) begin + sd_cmd <= CMD_PRECHARGE; + SDRAM_A[10] <= 1'b1; // precharge all banks + end + + if(reset == 10 || reset == 8) begin + sd_cmd <= CMD_AUTO_REFRESH; + end + + if(reset == 2) begin + sd_cmd <= CMD_LOAD_MODE; + SDRAM_A <= MODE; + SDRAM_BA <= 2'b00; + end + end + end else begin + // RAS phase + // bank 0,1 + if(t == STATE_RAS0) begin + addr_latch[0] <= addr_latch_next[0]; + port[0] <= next_port[0]; + { oe_latch[0], we_latch[0] } <= 2'b00; + + if (next_port[0] != PORT_NONE) begin + sd_cmd <= CMD_ACTIVE; + SDRAM_A <= addr_latch_next[0][22:10]; + SDRAM_BA <= addr_latch_next[0][24:23]; + addr_last[next_port[0]] <= addr_latch_next[0][19:1]; + if (next_port[0] == PORT_REQ) begin + { oe_latch[0], we_latch[0] } <= { ~port1_we, port1_we }; + ds[0] <= port1_ds; + din_latch[0] <= port1_d; + port1_state <= port1_req; + end else begin + { oe_latch[0], we_latch[0] } <= 2'b10; + ds[0] <= 2'b11; + end + end + end + + // bank 2,3 + if(t == STATE_RAS1) begin + refresh <= 0; + addr_latch[1] <= addr_latch_next[1]; + { oe_latch[1], we_latch[1] } <= 2'b00; + port[1] <= next_port[1]; + + if (next_port[1] != PORT_NONE) begin + sd_cmd <= CMD_ACTIVE; + SDRAM_A <= addr_latch_next[1][22:10]; + SDRAM_BA <= addr_latch_next[1][24:23]; + addr_last2[next_port[1]] <= addr_latch_next[1][16:2]; + if (next_port[1] == PORT_REQ) begin + { oe_latch[1], we_latch[1] } <= { ~port1_we, port1_we }; + ds[1] <= port2_ds; + din_latch[1] <= port2_d; + port2_state <= port2_req; + end else begin + { oe_latch[1], we_latch[1] } <= 2'b10; + ds[1] <= 2'b11; + end + end else if (need_refresh && !oe_latch[0] & !we_latch[0]) begin + refresh <= 1; + refresh_cnt <= 0; + sd_cmd <= CMD_AUTO_REFRESH; + end + end + + // CAS phase + if(t == STATE_CAS0 && (we_latch[0] || oe_latch[0])) begin + sd_cmd <= we_latch[0]?CMD_WRITE:CMD_READ; + { SDRAM_DQMH, SDRAM_DQML } <= ~ds[0]; + if (we_latch[0]) begin + SDRAM_DQ <= din_latch[0]; + port1_ack <= port1_req; + end + SDRAM_A <= { 4'b0010, addr_latch[0][9:1] }; // auto precharge + SDRAM_BA <= addr_latch[0][24:23]; + end + + if(t == STATE_CAS1 && (we_latch[1] || oe_latch[1])) begin + sd_cmd <= we_latch[1]?CMD_WRITE:CMD_READ; + { SDRAM_DQMH, SDRAM_DQML } <= ~ds[1]; + if (we_latch[1]) begin + SDRAM_DQ <= din_latch[1]; + port2_ack <= port2_req; + end + SDRAM_A <= { 4'b0010, addr_latch[1][9:1] }; // auto precharge + SDRAM_BA <= addr_latch[1][24:23]; + end + + // Data returned + if(t == STATE_READ0 && oe_latch[0]) begin + case(port[0]) + PORT_REQ: begin port1_q <= sd_din; port1_ack <= port1_req; end + PORT_CPU1: begin cpu1_q <= sd_din; end + PORT_CPU2: begin cpu2_q <= sd_din; end + default: ; + endcase; + end + + if(t == STATE_READ1 && oe_latch[1]) begin + case(port[1]) + PORT_REQ: port2_q[15:0] <= sd_din; + PORT_SP : sp_q[15:0] <= sd_din; + PORT_BG : bg_q[15:0] <= sd_din; + default: ; + endcase; + end + + //set DQM two cycles before the 2nd word in the burst + if(t == STATE_DS1b && oe_latch[1]) { SDRAM_DQMH, SDRAM_DQML } <= ~ds[1]; + + if(t == STATE_READ1b && oe_latch[1]) begin + case(port[1]) + PORT_REQ: begin port2_q[31:16] <= sd_din; port2_ack <= port2_req; end + PORT_SP : begin sp_q[31:16] <= sd_din; end + PORT_BG : begin bg_q[31:16] <= sd_din; end + default: ; + endcase; + end + end +end + +endmodule From 28caaf629c87855464d6072263fcfaca91146519 Mon Sep 17 00:00:00 2001 From: Gyorgy Szombathelyi <8644936+gyurco@users.noreply.github.com> Date: Tue, 29 Nov 2022 17:43:13 +0100 Subject: [PATCH 2/4] TropicalAngel: fix sea color, add MRAs and DIPs --- ...opicalAngel_MiST.qpf => TropicalAngel.qpf} | 2 +- ...opicalAngel_MiST.qsf => TropicalAngel.qsf} | 8 +- ...opicalAngel_MiST.sdc => TropicalAngel.sdc} | 0 .../meta/New Tropical Angel.mra | 74 ++++++++++++++++++ .../meta/Tropical Angel.mra | 75 +++++++++++++++++++ .../TropicalAngel_MiST/rtl/TropicalAngel.vhd | 4 +- .../rtl/TropicalAngel_MiST.sv | 11 +-- 7 files changed, 160 insertions(+), 14 deletions(-) rename Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/{TropicalAngel_MiST.qpf => TropicalAngel.qpf} (96%) rename Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/{TropicalAngel_MiST.qsf => TropicalAngel.qsf} (98%) rename Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/{TropicalAngel_MiST.sdc => TropicalAngel.sdc} (100%) create mode 100644 Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/meta/New Tropical Angel.mra create mode 100644 Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/meta/Tropical Angel.mra diff --git a/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/TropicalAngel_MiST.qpf b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/TropicalAngel.qpf similarity index 96% rename from Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/TropicalAngel_MiST.qpf rename to Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/TropicalAngel.qpf index 920d74e2..bab8b51e 100644 --- a/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/TropicalAngel_MiST.qpf +++ b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/TropicalAngel.qpf @@ -27,4 +27,4 @@ DATE = "18:28:29 January 01, 2020" # Revisions -PROJECT_REVISION = "TropicalAngel_MiST" +PROJECT_REVISION = "TropicalAngel" diff --git a/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/TropicalAngel_MiST.qsf b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/TropicalAngel.qsf similarity index 98% rename from Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/TropicalAngel_MiST.qsf rename to Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/TropicalAngel.qsf index 2b3e783a..644cc94b 100644 --- a/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/TropicalAngel_MiST.qsf +++ b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/TropicalAngel.qsf @@ -25,7 +25,7 @@ # Notes: # # 1) The default values for assignments are stored in the file: -# TropicalAngel_MiST_assignment_defaults.qdf +# TropicalAngel_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # @@ -43,7 +43,7 @@ set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:22:13 JUNE 04, 2019" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 -set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 set_global_assignment -name SMART_RECOMPILE ON # Pin & Location Assignments @@ -167,7 +167,7 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" - set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall # -------------------------------- -# start ENTITY(TropicalAngel_MiST) +# start ENTITY(TropicalAngel) # Pin & Location Assignments # ========================== @@ -215,7 +215,7 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO # end DESIGN_PARTITION(Top) # ------------------------- -# end ENTITY(TropicalAngel_MiST) +# end ENTITY(TropicalAngel) # ------------------------------ set_global_assignment -name ENABLE_SIGNALTAP OFF set_global_assignment -name USE_SIGNALTAP_FILE output_files/trop.stp diff --git a/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/TropicalAngel_MiST.sdc b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/TropicalAngel.sdc similarity index 100% rename from Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/TropicalAngel_MiST.sdc rename to Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/TropicalAngel.sdc diff --git a/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/meta/New Tropical Angel.mra b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/meta/New Tropical Angel.mra new file mode 100644 index 00000000..e4e2e735 --- /dev/null +++ b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/meta/New Tropical Angel.mra @@ -0,0 +1,74 @@ + + New Tropical Angel + World + no + no + + + Irem M57 + + 1983 + Irem + Sports + + newtangl + troangel + 0222 + TropicalAngel + + + 15kHz + Horizontal + + + 2 + 2-way + + 2 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/meta/Tropical Angel.mra b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/meta/Tropical Angel.mra new file mode 100644 index 00000000..53d2c726 --- /dev/null +++ b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/meta/Tropical Angel.mra @@ -0,0 +1,75 @@ + + Tropical Angel + World + no + no + + + Irem M57 + + 1983 + Irem + Sports + + troangel + troangel + 0222 + TropicalAngel + + + 15kHz + Horizontal + + + 2 + 2-way + + 2 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/TropicalAngel.vhd b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/TropicalAngel.vhd index 850dcd70..c0456ce9 100644 --- a/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/TropicalAngel.vhd +++ b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/TropicalAngel.vhd @@ -612,11 +612,11 @@ begin if pix_ena = '1' then -- always give priority to sprite when not 0000 if spr_output_line_do /= "0000" then - video_r <= spr_rgb_lut_do(7 downto 6); + video_r <= spr_rgb_lut_do(6)&spr_rgb_lut_do(7); video_g <= spr_rgb_lut_do(5 downto 3); video_b <= spr_rgb_lut_do(2 downto 0); else - video_r <= chr_palette_do(7 downto 6); + video_r <= chr_palette_do(6)&chr_palette_do(7); video_g <= chr_palette_do(5 downto 3); video_b <= chr_palette_do(2 downto 0); end if; diff --git a/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/TropicalAngel_MiST.sv b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/TropicalAngel_MiST.sv index ca067111..a91b8ee9 100644 --- a/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/TropicalAngel_MiST.sv +++ b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/TropicalAngel_MiST.sv @@ -49,13 +49,12 @@ module TropicalAngel_MiST( `include "rtl/build_id.v" localparam CONF_STR = { - "TROPANG;ROM;", + "TROANGEL;;", "O2,Rotate Controls,Off,On;", "O1,Video Timing,Original,Pal 50Hz;", "O34,Scanlines,Off,25%,50%,75%;", "O5,Blending,Off,On;", - "O6,Flip,Off,On;", - "O7,Invulnerability,Off,On;", + "DIP;", "T0,Reset;", "V,v1.0.",`BUILD_DATE }; @@ -64,8 +63,6 @@ wire palmode = status[1]; wire rotate = status[2]; wire [1:0] scanlines = status[4:3]; wire blend = status[5]; -wire flip = status[6]; -wire invuln = status[7]; assign LED = ~ioctl_downl; assign SDRAM_CLK = clk_sd; @@ -210,8 +207,8 @@ always @(posedge clk_sys) begin end -wire [7:0] dip1 = ~8'b00000010; -wire [7:0] dip2 = ~{ 1'b0, invuln, 1'b0, 1'b0/*stop*/, 3'b010, flip }; +wire [7:0] dip1 = ~status[15:8]; +wire [7:0] dip2 = ~status[23:16]; TropicalAngel TropicalAngel( .clock_36 ( clk_sys ), From 6a730f910c630ccbfaadea542328104bc24db89e Mon Sep 17 00:00:00 2001 From: Gyorgy Szombathelyi <8644936+gyurco@users.noreply.github.com> Date: Tue, 29 Nov 2022 18:57:04 +0100 Subject: [PATCH 3/4] Zaxxon: update video hw, add pause Fix Future Spy in flipped mode --- Arcade_MiST/Sega Zaxxon Hardware/Zaxxon.qsf | 3 +- .../Sega Zaxxon Hardware/rtl/Zaxxon_MiST.sv | 10 +- .../Sega Zaxxon Hardware/rtl/zaxxon.vhd | 156 +++++++++++------- 3 files changed, 109 insertions(+), 60 deletions(-) diff --git a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon.qsf b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon.qsf index 9c1ea5be..cf4d8427 100644 --- a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon.qsf +++ b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon.qsf @@ -40,7 +40,6 @@ # Project-Wide Assignments # ======================== set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL set_global_assignment -name LAST_QUARTUS_VERSION 13.1 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" @@ -228,4 +227,6 @@ set_global_assignment -name VERILOG_FILE rtl/Sega_Crypt.v set_global_assignment -name QIP_FILE ../../common/mist/mist.qip set_global_assignment -name QIP_FILE ../../common/CPU/T80/T80.qip set_global_assignment -name SIGNALTAP_FILE output_files/zaxx.stp +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON +set_global_assignment -name SMART_RECOMPILE ON set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Sega Zaxxon Hardware/rtl/Zaxxon_MiST.sv b/Arcade_MiST/Sega Zaxxon Hardware/rtl/Zaxxon_MiST.sv index 43155369..ff945a71 100644 --- a/Arcade_MiST/Sega Zaxxon Hardware/rtl/Zaxxon_MiST.sv +++ b/Arcade_MiST/Sega Zaxxon Hardware/rtl/Zaxxon_MiST.sv @@ -34,6 +34,7 @@ module Zaxxon_MiST( localparam CONF_STR = { "ZAXXON;;", "O2,Rotate Controls,Off,On;", + "O1,Pause,Off,On;", "O34,Scanlines,Off,25%,50%,75%;", "O5,Blend,Off,On;", "O6,Flip,Off,On;", @@ -43,6 +44,7 @@ localparam CONF_STR = { "V,v2.0.",`BUILD_DATE }; +wire pause = status[1]; wire rotate = status[2]; wire [1:0] scanlines = status[4:3]; wire blend = status[5]; @@ -123,7 +125,7 @@ user_io( wire [15:0] audio_l; wire hs, vs, cs, hb, vb; -wire blankn; +wire blankn = ~(hb | vb); wire [2:0] g, r; wire [1:0] b; wire [14:0] rom_addr; @@ -226,11 +228,13 @@ wire dl_wr = ioctl_wr && ioctl_addr < 18'h28200; zaxxon zaxxon( .clock_24(clk_sys), .reset(reset), - + .pause(pause), + .video_r(r), .video_g(g), .video_b(b), - .video_blankn(blankn), + .video_hblank(hb), + .video_vblank(vb), .video_hs(hs), .video_vs(vs), .video_csync(cs), diff --git a/Arcade_MiST/Sega Zaxxon Hardware/rtl/zaxxon.vhd b/Arcade_MiST/Sega Zaxxon Hardware/rtl/zaxxon.vhd index 3e08208e..94e4719a 100644 --- a/Arcade_MiST/Sega Zaxxon Hardware/rtl/zaxxon.vhd +++ b/Arcade_MiST/Sega Zaxxon Hardware/rtl/zaxxon.vhd @@ -116,15 +116,18 @@ entity zaxxon is port( clock_24 : in std_logic; reset : in std_logic; + pause : in std_logic; -- tv15Khz_mode : in std_logic; video_r : out std_logic_vector(2 downto 0); video_g : out std_logic_vector(2 downto 0); video_b : out std_logic_vector(1 downto 0); video_clk : out std_logic; video_csync : out std_logic; - video_blankn : out std_logic; + video_hblank : out std_logic; + video_vblank : out std_logic; video_hs : out std_logic; video_vs : out std_logic; + video_ce : out std_logic; audio_out_l : out std_logic_vector(15 downto 0); audio_out_r : out std_logic_vector(15 downto 0); @@ -177,7 +180,7 @@ architecture struct of zaxxon is signal hflip : std_logic_vector(8 downto 0) := (others=>'0'); -- horizontal counter flip signal vflip : std_logic_vector(8 downto 0) := (others=>'0'); -- vertical counter flip signal hflip2 : std_logic_vector(8 downto 0) := (others=>'0'); -- horizontal counter flip - + signal hs_cnt, vs_cnt :std_logic_vector(9 downto 0) ; signal hsync0, hsync1, hsync2, hsync3, hsync4 : std_logic; signal top_frame : std_logic := '0'; @@ -208,11 +211,15 @@ architecture struct of zaxxon is signal ch_code : std_logic_vector(7 downto 0); signal ch_code_r : std_logic_vector(7 downto 0); signal ch_attr : std_logic_vector(7 downto 0); + signal ch_color : std_logic_vector(3 downto 0); + signal ch_color_r : std_logic_vector(3 downto 0); signal ch_code_line : std_logic_vector(10 downto 0); signal ch_bit_nb : integer range 0 to 7; signal ch_graphx1_do : std_logic_vector( 7 downto 0); + signal ch_graphx1_do_r : std_logic_vector( 7 downto 0); signal ch_graphx2_do : std_logic_vector( 7 downto 0); + signal ch_graphx2_do_r : std_logic_vector( 7 downto 0); signal ch_vid : std_logic_vector( 1 downto 0); signal ch_color_addr : std_logic_vector(7 downto 0); @@ -232,10 +239,16 @@ architecture struct of zaxxon is signal bg_graphics1_do : std_logic_vector( 7 downto 0); signal bg_graphics2_do : std_logic_vector( 7 downto 0); signal bg_graphics3_do : std_logic_vector( 7 downto 0); + signal bg_graphics1_do_r: std_logic_vector( 7 downto 0); + signal bg_graphics2_do_r: std_logic_vector( 7 downto 0); + signal bg_graphics3_do_r: std_logic_vector( 7 downto 0); signal bg_bit_nb : integer range 0 to 7; signal bg_color_a : std_logic_vector(3 downto 0); + signal bg_color_r : std_logic_vector(3 downto 0); signal bg_color : std_logic_vector(3 downto 0); - signal bg_vid : std_logic_vector(2 downto 0); + signal bg_vid : std_logic_vector(2 downto 0); + signal bg_vid_r : std_logic_vector(2 downto 0); + signal bg_code_line : std_logic_vector(9 downto 0); signal sp_ram_addr : std_logic_vector(7 downto 0); signal sp_ram_we : std_logic; @@ -278,6 +291,7 @@ architecture struct of zaxxon is signal sp_buffer_ram_we : std_logic; signal sp_buffer_ram_di : std_logic_vector(7 downto 0); signal sp_buffer_ram_do : std_logic_vector(7 downto 0); + signal sp_buffer_ram_do_r : std_logic_vector(7 downto 0); signal sp_vid : std_logic_vector(7 downto 0); @@ -377,6 +391,9 @@ end process; pix_ena <= '1' when clock_cnt(1 downto 0) = "01" else '0'; -- (6MHz) cpu_ena <= '1' when hcnt(0) = '0' and pix_ena = '1' else '0'; -- (3MHz) +video_ce <= pix_ena; +video_clk <= clock_vid; + --------------------------------------- -- Video scanner 384x264 @6.083 MHz -- -- display 256x224 -- @@ -384,8 +401,6 @@ cpu_ena <= '1' when hcnt(0) = '0' and pix_ena = '1' else '0'; -- (3MHz) -- line : 63.13us -> 15.84kHz -- -- frame : 16.67ms -> 60.00Hz -- --------------------------------------- -video_hs <= hsync0; - process (reset, clock_vid) begin if reset='1' then @@ -413,8 +428,6 @@ begin -- set syncs position if hcnt = 170 then -- tune screen H position here hs_cnt <= (others => '0'); - if vcnt = 0 then video_vs <= '0'; end if; - if vcnt = 3 then video_vs <= '1'; end if; if (vcnt = 248) then -- tune screen V position here vs_cnt <= (others => '0'); else @@ -424,15 +437,34 @@ begin else hs_cnt <= hs_cnt + 1; end if; - + + if vs_cnt = 1 then video_vs <= '0'; + elsif vs_cnt = 3 then video_vs <= '1'; + end if; + -- blanking - video_blankn <= '0'; - if (hcnt >= 256+9-5 or hcnt < 128+9-5) and - vcnt >= 17 and vcnt < 240 then video_blankn <= '1';end if; - +-- video_blankn <= '0'; + +-- if (hcnt >= 256+9-5 or hcnt < 128+9-5) and +-- vcnt >= 17 and vcnt < 240 then video_blankn <= '1';end if; +-- + if hcnt = 256+9+1 then + video_hblank <= '0'; + end if; + if hcnt = 128+9+1 then + video_hblank <= '1'; + end if; + + if hcnt = 256+9+1 then + video_vblank <= '1'; + if vcnt >= 16 and vcnt < 240 then + video_vblank <= '0'; + end if; + end if; + -- build syncs pattern (composite) - if hs_cnt = 0 then hsync0 <= '0'; - elsif hs_cnt = 29 then hsync0 <= '1'; + if hs_cnt = 0 then hsync0 <= '0'; video_hs <= '0'; + elsif hs_cnt = 29 then hsync0 <= '1'; video_hs <= '1'; end if; if hs_cnt = 0 then hsync1 <= '0'; @@ -473,8 +505,8 @@ begin elsif vs_cnt = 10 then video_csync <= hsync1; elsif vs_cnt = 11 then video_csync <= hsync0; else video_csync <= hsync0; - end if; - + end if; + end if; end if; end if; @@ -570,25 +602,27 @@ end process; -- dmux ch_ram and sp_ram data out -- ------------------------------------------ wram_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and cpu_addr(15 downto 12 ) = x"6" else '0'; -ch_ram_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and (cpu_addr and x"E000") = x"8000" and hcnt(0) = '1' else '0'; +ch_ram_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and (cpu_addr and x"E000") = x"8000" and hcnt(0) = '0' else '0'; sp_ram_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and (cpu_addr and x"E000") = x"A000" and hcnt(0) = '1' else '0'; flip <= flip_cpu xor flip_screen; hflip <= hcnt when flip = '0' else not hcnt; vflip <= vcnt when flip = '0' else not vcnt; -ch_ram_addr <= cpu_addr(9 downto 0) when hcnt(0) = '1' else vflip(7 downto 3) & hflip(7 downto 3); +ch_ram_addr <= cpu_addr(9 downto 0) when hcnt(0) = '0' else vflip(7 downto 3) & hflip(7 downto 3); sp_ram_addr <= cpu_addr(7 downto 0) when hcnt(0) = '1' else '0'& hcnt(7 downto 1); process (clock_vid) begin if rising_edge(clock_vid) then if hcnt(0) = '1' then - ch_ram_do_to_cpu <= ch_ram_do; sp_ram_do_to_cpu <= sp_ram_do; else sp_ram_do_to_sp_machine <= sp_ram_do; end if; + if hcnt(0) = '0' then + ch_ram_do_to_cpu <= ch_ram_do; + end if; end if; end process; @@ -666,9 +700,10 @@ sp_hflip <= sp_code(6) when hwsel = "00" else sp_code(7); process (clock_vid) begin if rising_edge(clock_vid) then - - if pix_ena = '0' then - sp_vid <= sp_buffer_ram_do; + + sp_buffer_ram_do_r <= sp_buffer_ram_do; + if pix_ena = '1' then + sp_vid <= sp_buffer_ram_do_r; end if; if hcnt = 128 then vflip_r <= vflip; end if; @@ -726,9 +761,9 @@ begin else if flip = '1' then - sp_bit_hpos_r <= hcnt(7 downto 0) - 5; -- tune sprite position w.r.t. background + sp_bit_hpos_r <= hcnt(7 downto 0) - 8; -- tune sprite position w.r.t. background else - sp_bit_hpos_r <= hcnt(7 downto 0) - 2; -- tune sprite position w.r.t. background + sp_bit_hpos_r <= hcnt(7 downto 0) - 6; -- tune sprite position w.r.t. background end if; end if; @@ -739,45 +774,45 @@ end process; -------------------- --- char machine --- -------------------- +ch_code <= ch_ram_do; ch_code_line <= ch_code & vflip(2 downto 0); +ch_color_addr <= vflip(7 downto 5) & hflip(7 downto 3); process (clock_vid) begin if rising_edge(clock_vid) then if pix_ena = '1' then - - if hcnt(2 downto 0) = "010" then - ch_code <= ch_ram_do; - ch_color_addr <= vflip(7 downto 5) & hflip(7 downto 3); - + + if hcnt(2 downto 0) = "111" then + ch_color_r <= ch_color_do(3 downto 0); + ch_graphx1_do_r <= ch_graphx1_do; + ch_graphx2_do_r <= ch_graphx2_do; if flip = '1' then ch_bit_nb <= 0; else ch_bit_nb <= 7; end if; else - + if flip = '1' then ch_bit_nb <= ch_bit_nb + 1; else ch_bit_nb <= ch_bit_nb - 1; end if; - + end if; - + + ch_color <= ch_color_r; + ch_vid <= ch_graphx2_do_r(ch_bit_nb) & ch_graphx1_do_r(ch_bit_nb); + end if; end if; end process; - -ch_vid <= ch_graphx2_do(ch_bit_nb) & ch_graphx1_do(ch_bit_nb); -------------------------- --- background machine --- -------------------------- map_offset_h <= (bg_position & '1') + (x"0" & vflip(7 downto 0)) + 1; --- count from "00"->"FF" and then continue with "00"->"7F" instead of "80"->"FF" -hflip2 <= hflip xor (not(hcnt(8)) & "0000000") when flip = '1' else hflip; - -map_offset_l1 <= not('0' & vflip(7 downto 1)) + (hflip2(7 downto 3) & "111"); +map_offset_l1 <= not('0' & vflip(7 downto 1)) + (hflip(7 downto 3) & "111") + 1; map_offset_l2 <= map_offset_l1 + ('0' & not(flip) & flip & flip & flip & "000"); map_addr <= map_offset_h(11 downto 3) & map_offset_l2(7 downto 3); @@ -785,38 +820,47 @@ map_addr <= map_offset_h(11 downto 3) & map_offset_l2(7 downto 3); process (clock_vid) begin if rising_edge(clock_vid) then - if pix_ena = '1' then - - if (not(vflip(3 downto 1)) + hflip(2 downto 0)) = "000" then - bg_graphics_addr(12 downto 3) <= map2_do(1 downto 0) & map1_do; -- bg_code_line - bg_graphics_addr(2 downto 0) <= map_offset_h(2 downto 0); - bg_color_a <= map2_do(7 downto 4); - end if; - if (not(vflip(3 downto 1)) + hflip(2 downto 0)) = "011" then + if hcnt(2 downto 0) = "011" then -- 4H^ + bg_color_a <= map2_do(7 downto 4); + + bg_graphics_addr(2 downto 0) <= map_offset_h(2 downto 0); + bg_graphics_addr(12 downto 3) <= map2_do(1 downto 0) & map1_do;--bg_code_line; + end if; + if hcnt(2 downto 0) = "111" then -- LD7 + bg_color_r <= bg_color_a; bg_graphics1_do <= bg_graphics_do(7 downto 0); bg_graphics2_do <= bg_graphics_do(15 downto 8); bg_graphics3_do <= bg_graphics_do(23 downto 16); + end if; + + if (not(vflip(3 downto 1)) + hflip(2 downto 0)) = "111" then + bg_graphics1_do_r <= bg_graphics1_do; + bg_graphics2_do_r <= bg_graphics2_do; + bg_graphics3_do_r <= bg_graphics3_do; + + bg_color <= bg_color_r; - bg_color <= bg_color_a; - if flip = '1' then bg_bit_nb <= 0; else bg_bit_nb <= 7; end if; else if flip = '1' then bg_bit_nb <= bg_bit_nb + 1; else - bg_bit_nb <= bg_bit_nb - 1; + bg_bit_nb <= bg_bit_nb - 1; end if; end if; - + + bg_vid_r <= bg_graphics3_do_r(bg_bit_nb) & bg_graphics2_do_r(bg_bit_nb) & bg_graphics1_do_r(bg_bit_nb); + end if; end if; end process; - -bg_vid <= bg_graphics3_do(bg_bit_nb) & bg_graphics2_do(bg_bit_nb) & bg_graphics1_do(bg_bit_nb) - when bg_enable = '1' else "000"; + +bg_vid <= "000" when bg_enable = '0' else + bg_graphics3_do_r(bg_bit_nb) & bg_graphics2_do_r(bg_bit_nb) & bg_graphics1_do_r(bg_bit_nb) when flip = '1' else -- hack + bg_vid_r; -------------------------------------- -- mux char/background/sprite video -- @@ -834,12 +878,12 @@ begin end if; if ch_vid /= "00" then - palette_addr <= ch_color_ref & ch_color_do(3 downto 0) & '0' & ch_vid; + palette_addr <= ch_color_ref & ch_color & '0' & ch_vid; end if; video_r <= palette_do(2 downto 0); video_g <= palette_do(5 downto 3); - video_b <= palette_do(7 downto 6); + video_b <= palette_do(7 downto 6); end if; @@ -857,7 +901,7 @@ port map( RESET_n => reset_n, CLK_n => clock_vid, CLKEN => cpu_ena, - WAIT_n => '1', + WAIT_n => not pause, INT_n => cpu_irq_n, NMI_n => '1', --cpu_nmi_n, BUSRQ_n => '1', From 880706c1e0c4404bba884ec4d27cf6bc4935e0af Mon Sep 17 00:00:00 2001 From: Gyorgy Szombathelyi <8644936+gyurco@users.noreply.github.com> Date: Wed, 30 Nov 2022 18:26:42 +0100 Subject: [PATCH 4/4] Zaxxon: activate DSW2 --- Arcade_MiST/Sega Zaxxon Hardware/rtl/Zaxxon_MiST.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Arcade_MiST/Sega Zaxxon Hardware/rtl/Zaxxon_MiST.sv b/Arcade_MiST/Sega Zaxxon Hardware/rtl/Zaxxon_MiST.sv index ff945a71..176c23fe 100644 --- a/Arcade_MiST/Sega Zaxxon Hardware/rtl/Zaxxon_MiST.sv +++ b/Arcade_MiST/Sega Zaxxon Hardware/rtl/Zaxxon_MiST.sv @@ -251,7 +251,7 @@ zaxxon zaxxon( .service(service), .sw1_input(sw1), // cocktail(1) / sound(1) / ships(2) / N.U.(2) / extra ship (2) - .sw2_input(8'h33), // coin b(4) / coin a(4) -- "3" => 1c_1c + .sw2_input(sw2), // coin b(4) / coin a(4) -- "3" => 1c_1c .flip_screen(flip),