From 58e23d2405dea8f0e7aaebb69f5bfcdd0146bd7f Mon Sep 17 00:00:00 2001
From: Gyorgy Szombathelyi <gyurco@freemail.hu>
Date: Sat, 1 Aug 2020 16:31:20 +0200
Subject: [PATCH] Ladybug HW: use common T80 and SN67489

---
 .../CosmicAvenger_MiST/CosmicAvenger.qsf      |   18 +-
 .../CosmicAvenger_MiST/rtl/CosmicAvenger.sv   |  154 +-
 .../CosmicAvenger_MiST/rtl/cpu/T80.vhd        | 1094 ---------
 .../CosmicAvenger_MiST/rtl/cpu/T80_ALU.vhd    |  370 ---
 .../CosmicAvenger_MiST/rtl/cpu/T80_MCode.vhd  | 2027 -----------------
 .../CosmicAvenger_MiST/rtl/cpu/T80_Pack.vhd   |  220 --
 .../CosmicAvenger_MiST/rtl/cpu/T80_Reg.vhd    |  114 -
 .../CosmicAvenger_MiST/rtl/cpu/T80a.vhd       |  280 ---
 .../CosmicAvenger_MiST/rtl/ladybug.vhd        |    6 +-
 .../rtl/ladybug_cpu_unit.vhd                  |    6 +-
 .../rtl/ladybug_machine.vhd                   |    6 +-
 .../rtl}/ladybug_sound_unit.vhd               |   22 +-
 .../rtl/sound/sn76489/COPYING                 |  340 ---
 .../rtl/sound/sn76489/README                  |  143 --
 .../rtl/sound/sn76489/sn76489_attenuator.vhd  |  114 -
 .../rtl/sound/sn76489/sn76489_clock_div.vhd   |  134 --
 .../rtl/sound/sn76489/sn76489_latch_ctrl.vhd  |  138 --
 .../rtl/sound/sn76489/sn76489_noise.vhd       |  278 ---
 .../rtl/sound/sn76489/sn76489_tone.vhd        |  188 --
 .../rtl/sound/sn76489/sn76489_top.vhd         |  200 --
 .../Ladybug Hardware/Dorodon_MiST/Dorodon.qsf |   18 +-
 .../Dorodon_MiST/rtl/Dorodon.sv               |  149 +-
 .../Dorodon_MiST/rtl/cpu/T80.vhd              | 1094 ---------
 .../Dorodon_MiST/rtl/cpu/T80_ALU.vhd          |  370 ---
 .../Dorodon_MiST/rtl/cpu/T80_MCode.vhd        | 2027 -----------------
 .../Dorodon_MiST/rtl/cpu/T80_Pack.vhd         |  220 --
 .../Dorodon_MiST/rtl/cpu/T80_Reg.vhd          |  114 -
 .../Dorodon_MiST/rtl/cpu/T80a.vhd             |  280 ---
 .../Dorodon_MiST/rtl/ladybug.vhd              |    6 +-
 .../Dorodon_MiST/rtl/ladybug_cpu_unit.vhd     |    6 +-
 .../Dorodon_MiST/rtl/ladybug_machine.vhd      |    6 +-
 .../rtl}/ladybug_sound_unit.vhd               |   22 +-
 .../Dorodon_MiST/rtl/sound/sn76489/COPYING    |  340 ---
 .../Dorodon_MiST/rtl/sound/sn76489/README     |  143 --
 .../rtl/sound/sn76489/sn76489_attenuator.vhd  |  114 -
 .../rtl/sound/sn76489/sn76489_clock_div.vhd   |  134 --
 .../rtl/sound/sn76489/sn76489_latch_ctrl.vhd  |  138 --
 .../rtl/sound/sn76489/sn76489_noise.vhd       |  278 ---
 .../rtl/sound/sn76489/sn76489_tone.vhd        |  188 --
 .../rtl/sound/sn76489/sn76489_top.vhd         |  200 --
 .../Ladybug Hardware/LadyBug_MiST/LadyBug.qsf |   26 +-
 .../LadyBug_MiST/rtl/LadyBug.sv               |  154 +-
 .../LadyBug_MiST/rtl/cpu/T80.vhd              | 1094 ---------
 .../LadyBug_MiST/rtl/cpu/T80_ALU.vhd          |  370 ---
 .../LadyBug_MiST/rtl/cpu/T80_MCode.vhd        | 2027 -----------------
 .../LadyBug_MiST/rtl/cpu/T80_Pack.vhd         |  220 --
 .../LadyBug_MiST/rtl/cpu/T80_Reg.vhd          |  114 -
 .../LadyBug_MiST/rtl/cpu/T80a.vhd             |  280 ---
 .../LadyBug_MiST/rtl/ladybug.vhd              |    6 +-
 .../LadyBug_MiST/rtl/ladybug_cpu_unit.vhd     |    6 +-
 .../LadyBug_MiST/rtl/ladybug_machine.vhd      |    6 +-
 .../rtl}/ladybug_sound_unit.vhd               |   22 +-
 .../LadyBug_MiST/rtl/sound/sn76489/COPYING    |  340 ---
 .../LadyBug_MiST/rtl/sound/sn76489/README     |  143 --
 .../rtl/sound/sn76489/sn76489_attenuator.vhd  |  114 -
 .../rtl/sound/sn76489/sn76489_clock_div.vhd   |  134 --
 .../rtl/sound/sn76489/sn76489_latch_ctrl.vhd  |  138 --
 .../rtl/sound/sn76489/sn76489_noise.vhd       |  278 ---
 .../rtl/sound/sn76489/sn76489_tone.vhd        |  188 --
 .../rtl/sound/sn76489/sn76489_top.vhd         |  200 --
 .../Snapjack_MiST/Snapjack.qsf                |   18 +-
 .../Snapjack_MiST/rtl/Snapjack.sv             |  158 +-
 .../Snapjack_MiST/rtl/cpu/T80.vhd             | 1094 ---------
 .../Snapjack_MiST/rtl/cpu/T80_ALU.vhd         |  370 ---
 .../Snapjack_MiST/rtl/cpu/T80_MCode.vhd       | 2027 -----------------
 .../Snapjack_MiST/rtl/cpu/T80_Pack.vhd        |  220 --
 .../Snapjack_MiST/rtl/cpu/T80_Reg.vhd         |  114 -
 .../Snapjack_MiST/rtl/cpu/T80a.vhd            |  280 ---
 .../Snapjack_MiST/rtl/ladybug.vhd             |    6 +-
 .../Snapjack_MiST/rtl/ladybug_cpu_unit.vhd    |    6 +-
 .../Snapjack_MiST/rtl/ladybug_machine.vhd     |    6 +-
 .../rtl}/ladybug_sound_unit.vhd               |   22 +-
 .../Snapjack_MiST/rtl/sound/sn76489/COPYING   |  340 ---
 .../Snapjack_MiST/rtl/sound/sn76489/README    |  143 --
 .../rtl/sound/sn76489/sn76489_attenuator.vhd  |  114 -
 .../rtl/sound/sn76489/sn76489_clock_div.vhd   |  134 --
 .../rtl/sound/sn76489/sn76489_latch_ctrl.vhd  |  138 --
 .../rtl/sound/sn76489/sn76489_noise.vhd       |  278 ---
 .../rtl/sound/sn76489/sn76489_tone.vhd        |  188 --
 .../rtl/sound/sn76489/sn76489_top.vhd         |  200 --
 common/Sound/sn76489/sn76489_attenuator.vhd   |   45 +-
 common/Sound/sn76489/sn76489_clock_div.vhd    |   10 +-
 common/Sound/sn76489/sn76489_latch_ctrl.vhd   |   15 +-
 common/Sound/sn76489/sn76489_noise.vhd        |   37 +-
 common/Sound/sn76489/sn76489_tone.vhd         |   36 +-
 common/Sound/sn76489/sn76489_top.vhd          |   16 +-
 86 files changed, 416 insertions(+), 23158 deletions(-)
 delete mode 100644 Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/cpu/T80.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/cpu/T80_ALU.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/cpu/T80_MCode.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/cpu/T80_Pack.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/cpu/T80_Reg.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/cpu/T80a.vhd
 rename Arcade_MiST/Ladybug Hardware/{LadyBug_MiST/rtl/sound => CosmicAvenger_MiST/rtl}/ladybug_sound_unit.vhd (88%)
 delete mode 100644 Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/COPYING
 delete mode 100644 Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/README
 delete mode 100644 Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/sn76489_attenuator.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/sn76489_clock_div.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/sn76489_latch_ctrl.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/sn76489_noise.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/sn76489_tone.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/sn76489_top.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/cpu/T80.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/cpu/T80_ALU.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/cpu/T80_MCode.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/cpu/T80_Pack.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/cpu/T80_Reg.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/cpu/T80a.vhd
 rename Arcade_MiST/Ladybug Hardware/{Snapjack_MiST/rtl/sound => Dorodon_MiST/rtl}/ladybug_sound_unit.vhd (88%)
 delete mode 100644 Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/COPYING
 delete mode 100644 Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/README
 delete mode 100644 Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/sn76489_attenuator.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/sn76489_clock_div.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/sn76489_latch_ctrl.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/sn76489_noise.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/sn76489_tone.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/sn76489_top.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/cpu/T80.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/cpu/T80_ALU.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/cpu/T80_MCode.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/cpu/T80_Pack.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/cpu/T80_Reg.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/cpu/T80a.vhd
 rename Arcade_MiST/Ladybug Hardware/{CosmicAvenger_MiST/rtl/sound => LadyBug_MiST/rtl}/ladybug_sound_unit.vhd (88%)
 delete mode 100644 Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/COPYING
 delete mode 100644 Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/README
 delete mode 100644 Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/sn76489_attenuator.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/sn76489_clock_div.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/sn76489_latch_ctrl.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/sn76489_noise.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/sn76489_tone.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/sn76489_top.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/cpu/T80.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/cpu/T80_ALU.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/cpu/T80_MCode.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/cpu/T80_Pack.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/cpu/T80_Reg.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/cpu/T80a.vhd
 rename Arcade_MiST/Ladybug Hardware/{Dorodon_MiST/rtl/sound => Snapjack_MiST/rtl}/ladybug_sound_unit.vhd (88%)
 delete mode 100644 Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/COPYING
 delete mode 100644 Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/README
 delete mode 100644 Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/sn76489_attenuator.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/sn76489_clock_div.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/sn76489_latch_ctrl.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/sn76489_noise.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/sn76489_tone.vhd
 delete mode 100644 Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/sn76489_top.vhd

diff --git a/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/CosmicAvenger.qsf b/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/CosmicAvenger.qsf
index aab0eacd..59e1ff64 100644
--- a/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/CosmicAvenger.qsf	
+++ b/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/CosmicAvenger.qsf	
@@ -160,7 +160,6 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 
 # end ENTITY(CosmicAvenger)
 # -------------------------
-set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/CosmicAvenger.sv
 set_global_assignment -name VHDL_FILE rtl/ladybug.vhd
 set_global_assignment -name VHDL_FILE rtl/ladybug_video_unit.vhd
@@ -180,13 +179,7 @@ set_global_assignment -name VHDL_FILE rtl/ladybug_chutes.vhd
 set_global_assignment -name VHDL_FILE rtl/ladybug_chute.vhd
 set_global_assignment -name VHDL_FILE rtl/ladybug_char.vhd
 set_global_assignment -name VHDL_FILE rtl/ladybug_addr_dec.vhd
-set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_top.vhd
-set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_tone.vhd
-set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_noise.vhd
-set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_latch_ctrl.vhd
-set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_clock_div.vhd
-set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_attenuator.vhd
-set_global_assignment -name VHDL_FILE rtl/sound/ladybug_sound_unit.vhd
+set_global_assignment -name VHDL_FILE rtl/ladybug_sound_unit.vhd
 set_global_assignment -name VHDL_FILE rtl/ROM/rom_sprite_u.vhd
 set_global_assignment -name VHDL_FILE rtl/ROM/rom_sprite_l.vhd
 set_global_assignment -name VHDL_FILE rtl/ROM/rom_cpu3.vhd
@@ -198,15 +191,12 @@ set_global_assignment -name VHDL_FILE rtl/ROM/prom_decrypt.vhd
 set_global_assignment -name VHDL_FILE rtl/ROM/prom_10_3.vhd
 set_global_assignment -name VHDL_FILE rtl/ROM/prom_10_2.vhd
 set_global_assignment -name VHDL_FILE rtl/ROM/prom_10_1.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80a.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
 set_global_assignment -name VHDL_FILE rtl/ttl_393.vhd
 set_global_assignment -name VHDL_FILE rtl/ttl_175.vhd
 set_global_assignment -name VHDL_FILE rtl/spram.vhd
 set_global_assignment -name VHDL_FILE rtl/dpram.vhd
 set_global_assignment -name QIP_FILE rtl/pll.qip
+set_global_assignment -name QIP_FILE ../../../common/Sound/sn76489/sn76489.qip
+set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
+set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/CosmicAvenger.sv b/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/CosmicAvenger.sv
index dcb7395f..ee5fea54 100644
--- a/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/CosmicAvenger.sv	
+++ b/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/CosmicAvenger.sv	
@@ -41,13 +41,16 @@ module CosmicAvenger
 `include "rtl\build_id.v" 
 
 localparam CONF_STR = {
-	"C.Avenger;;",
+	"CAVENGER;;",
+	"O2,Rotate Controls,Off,On;",
 	"O34,Scanlines,Off,25%,50%,75%;",
 	"O5,Blend,Off,On;",
-	"T6,Reset;",
+	"T0,Reset;",
 	"V,v1.10.",`BUILD_DATE
 };
 
+wire rotate = status[2];
+
 assign LED = 1;
 assign AUDIO_R = AUDIO_L;
 
@@ -67,17 +70,43 @@ wire  [7:0] joystick_0;
 wire  [7:0] joystick_1;
 wire        scandoublerD;
 wire        ypbpr;
-wire [10:0] ps2_key;
-reg	[7:0] audio;
-wire 			hb, vb;
-wire        blankn = ~(hb | vb);
-wire 			ce_vid;
-wire 			hs, vs;
-wire  [1:0] r, g, b;
+wire        no_csync;
+wire        key_pressed;
+wire  [7:0] key_code;
+wire        key_strobe;
 
-ladybugt ladybugt(
+user_io #(
+	.STRLEN(($size(CONF_STR)>>3)))
+user_io(
+	.clk_sys        (clk_sys        ),
+	.conf_str       (CONF_STR       ),
+	.SPI_CLK        (SPI_SCK        ),
+	.SPI_SS_IO      (CONF_DATA0     ),
+	.SPI_MISO       (SPI_DO         ),
+	.SPI_MOSI       (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches       (switches       ),
+	.scandoubler_disable (scandoublerD),
+	.ypbpr          (ypbpr          ),
+	.no_csync       (no_csync       ),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
+	.key_code       (key_code       ),
+	.joystick_0     (joystick_0     ),
+	.joystick_1     (joystick_1     ),
+	.status         (status         )
+);
+
+wire  [8:0] audio;
+wire        hb, vb;
+wire        blankn = ~(hb | vb);
+wire        ce_vid;
+wire        hs, vs;
+wire  [1:0] r,g,b;
+
+ladybugt ladybug(
 	.CLK_IN(clk_sys),
-	.I_RESET(status[0] | status[6] | buttons[1]),
+	.I_RESET(status[0] | buttons[1]),
 	.O_PIXCE(ce_vid),
 	.O_VIDEO_R(r),
 	.O_VIDEO_G(g),
@@ -87,15 +116,15 @@ ladybugt ladybugt(
 	.O_VBLANK(vb),
 	.O_HBLANK(hb),
 	.O_AUDIO(audio),
-	.but_coin_s(~{1'b0,btn_coin}),
-	.but_fire_s(~{1'b0,m_fire}),
-	.but_bomb_s(~{1'b0,m_bomb}),
-	.but_tilt_s(~{1'b0,1'b0}),
-	.but_select_s(~{btn_two_players, btn_one_player}),
-	.but_up_s(~{1'b0,m_up}),
-	.but_down_s(~{1'b0,m_down}),
-	.but_left_s(~{1'b0,m_left}),
-	.but_right_s(~{1'b0,m_right})
+	.but_coin_s(~{m_coin2,m_coin1}),
+	.but_fire_s(~{m_fire2A,m_fireA}),
+	.but_bomb_s(~{m_fire2B,m_fireB}),
+	.but_tilt_s(~{m_tilt,m_tilt}),
+	.but_select_s(~{m_two_players, m_one_player}),
+	.but_up_s(~{m_up2,m_up}),
+	.but_down_s(~{m_down2,m_down}),
+	.but_left_s(~{m_left2,m_left}),
+	.but_right_s(~{m_right2,m_right})
 	);
 
 mist_video #(.COLOR_DEPTH(2),.SD_HCNT_WIDTH(10)) mist_video(
@@ -113,79 +142,40 @@ mist_video #(.COLOR_DEPTH(2),.SD_HCNT_WIDTH(10)) mist_video(
 	.VGA_B(VGA_B),
 	.VGA_VS(VGA_VS),
 	.VGA_HS(VGA_HS),
-	.rotate({1'b0,status[2]}),
+	.rotate({1'b0,rotate}),
 	.ce_divider(1'b1),
 	.blend(status[5]),
 	.scandoubler_disable(scandoublerD),
 	.scanlines(status[4:3]),
-	.ypbpr(ypbpr)
+	.ypbpr(ypbpr),
+	.no_csync(no_csync)
 );
 
-user_io #(
-	.STRLEN(($size(CONF_STR)>>3)))
-user_io(
-	.clk_sys        (clk_sys        ),
-	.conf_str       (CONF_STR       ),
-	.SPI_CLK        (SPI_SCK        ),
-	.SPI_SS_IO      (CONF_DATA0     ),
-	.SPI_MISO       (SPI_DO         ),
-	.SPI_MOSI       (SPI_DI         ),
-	.buttons        (buttons        ),
-	.switches       (switches       ),
-	.scandoubler_disable (scandoublerD),
-	.ypbpr          (ypbpr          ),
-	.key_strobe     (key_strobe     ),
-	.key_pressed    (key_pressed    ),
-	.key_code       (key_code       ),
-	.joystick_0     (joystick_0     ),
-	.joystick_1     (joystick_1     ),
-	.status         (status         )
-);
-
-dac dac(
+dac #(9) dac(
 	.clk_i(clk_sys),
 	.res_n_i(1),
-	.dac_i({~audio[7], audio[6:0]}),
+	.dac_i(audio),
 	.dac_o(AUDIO_L)
 	);
 
-wire m_up     = btn_up | joystick_0[3] | joystick_1[3];
-wire m_down   = btn_down | joystick_0[2] | joystick_1[2];
-wire m_left   = btn_left | joystick_0[1] | joystick_1[1];
-wire m_right  = btn_right | joystick_0[0] | joystick_1[0];
+wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
+wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
+wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
 
-wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
-wire m_bomb   = btn_fire2 | joystick_0[5] | joystick_1[5];
-
-reg btn_one_player = 0;
-reg btn_two_players = 0;
-reg btn_left = 0;
-reg btn_right = 0;
-reg btn_down = 0;
-reg btn_up = 0;
-reg btn_fire1 = 0;
-reg btn_fire2 = 0;
-reg btn_fire3 = 0;
-reg btn_coin  = 0;
-wire       key_pressed;
-wire [7:0] key_code;
-wire       key_strobe;
-
-always @(posedge clk_sys) begin
-	if(key_strobe) begin
-		case(key_code)
-			'h75: btn_up         	<= key_pressed; // up
-			'h72: btn_down        	<= key_pressed; // down
-			'h6B: btn_left      		<= key_pressed; // left
-			'h74: btn_right       	<= key_pressed; // right
-			'h76: btn_coin				<= key_pressed; // ESC
-			'h05: btn_one_player   	<= key_pressed; // F1
-			'h06: btn_two_players  	<= key_pressed; // F2
-			'h14: btn_fire3 			<= key_pressed; // ctrl
-			'h11: btn_fire2 			<= key_pressed; // alt
-			'h29: btn_fire1   		<= key_pressed; // Space
-		endcase
-	end
-end
+arcade_inputs inputs (
+	.clk         ( clk_sys     ),
+	.key_strobe  ( key_strobe  ),
+	.key_pressed ( key_pressed ),
+	.key_code    ( key_code    ),
+	.joystick_0  ( joystick_0  ),
+	.joystick_1  ( joystick_1  ),
+	.rotate      ( rotate      ),
+	.orientation ( 2'b00       ),
+	.joyswap     ( 1'b0        ),
+	.oneplayer   ( 1'b1        ),
+	.controls    ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
+	.player1     ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
+	.player2     ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
+);
 
 endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/cpu/T80.vhd
deleted file mode 100644
index c3e13c5c..00000000
--- a/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/cpu/T80.vhd	
+++ /dev/null
@@ -1,1094 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
---
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0210 : Fixed wait and halt
---
---      0211 : Fixed Refresh addition and IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
---      0235 : Added clock enable and IM 2 fix by Mike Johnson
---
---      0237 : Changed 8080 I/O address output, added IntE output
---
---      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
---      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
---      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
---      0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
-  generic(
-    Mode   : integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-    IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-    Flag_C : integer := 0;
-    Flag_N : integer := 1;
-    Flag_P : integer := 2;
-    Flag_X : integer := 3;
-    Flag_H : integer := 4;
-    Flag_Y : integer := 5;
-    Flag_Z : integer := 6;
-    Flag_S : integer := 7
-    );
-  port(
-    RESET_n    : in  std_logic;
-    CLK_n      : in  std_logic;
-    CEN        : in  std_logic;
-    WAIT_n     : in  std_logic;
-    INT_n      : in  std_logic;
-    NMI_n      : in  std_logic;
-    BUSRQ_n    : in  std_logic;
-    M1_n       : out std_logic;
-    IORQ       : out std_logic;
-    NoRead     : out std_logic;
-    Write      : out std_logic;
-    RFSH_n     : out std_logic;
-    HALT_n     : out std_logic;
-    BUSAK_n    : out std_logic;
-    A          : out std_logic_vector(15 downto 0);
-    DInst      : in  std_logic_vector(7 downto 0);
-    DI         : in  std_logic_vector(7 downto 0);
-    DO         : out std_logic_vector(7 downto 0);
-    MC         : out std_logic_vector(2 downto 0);
-    TS         : out std_logic_vector(2 downto 0);
-    IntCycle_n : out std_logic;
-    IntE       : out std_logic;
-    Stop       : out std_logic
-    );
-end T80;
-
-architecture rtl of T80 is
-
-  constant aNone              : std_logic_vector(2 downto 0) := "111";
-  constant aBC                : std_logic_vector(2 downto 0) := "000";
-  constant aDE                : std_logic_vector(2 downto 0) := "001";
-  constant aXY                : std_logic_vector(2 downto 0) := "010";
-  constant aIOA               : std_logic_vector(2 downto 0) := "100";
-  constant aSP                : std_logic_vector(2 downto 0) := "101";
-  constant aZI                : std_logic_vector(2 downto 0) := "110";
-
-  -- Registers
-  signal ACC, F               : std_logic_vector(7 downto 0);
-  signal Ap, Fp               : std_logic_vector(7 downto 0);
-  signal I                    : std_logic_vector(7 downto 0);
-  signal R                    : unsigned(7 downto 0);
-  signal SP, PC               : unsigned(15 downto 0);
-
-  signal RegDIH               : std_logic_vector(7 downto 0);
-  signal RegDIL               : std_logic_vector(7 downto 0);
-  signal RegBusA              : std_logic_vector(15 downto 0);
-  signal RegBusB              : std_logic_vector(15 downto 0);
-  signal RegBusC              : std_logic_vector(15 downto 0);
-  signal RegAddrA_r           : std_logic_vector(2 downto 0);
-  signal RegAddrA             : std_logic_vector(2 downto 0);
-  signal RegAddrB_r           : std_logic_vector(2 downto 0);
-  signal RegAddrB             : std_logic_vector(2 downto 0);
-  signal RegAddrC             : std_logic_vector(2 downto 0);
-  signal RegWEH               : std_logic;
-  signal RegWEL               : std_logic;
-  signal Alternate            : std_logic;
-
-  -- Help Registers
-  signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
-  signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
-  signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
-  signal RegBusA_r            : std_logic_vector(15 downto 0);
-
-  signal ID16                 : signed(15 downto 0);
-  signal Save_Mux             : std_logic_vector(7 downto 0);
-
-  signal TState               : unsigned(2 downto 0);
-  signal MCycle               : std_logic_vector(2 downto 0);
-  signal IntE_FF1             : std_logic;
-  signal IntE_FF2             : std_logic;
-  signal Halt_FF              : std_logic;
-  signal BusReq_s             : std_logic;
-  signal BusAck               : std_logic;
-  signal ClkEn                : std_logic;
-  signal NMI_s                : std_logic;
-  signal INT_s                : std_logic;
-  signal IStatus              : std_logic_vector(1 downto 0);
-
-  signal DI_Reg               : std_logic_vector(7 downto 0);
-  signal T_Res                : std_logic;
-  signal XY_State             : std_logic_vector(1 downto 0);
-  signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
-  signal NextIs_XY_Fetch      : std_logic;
-  signal XY_Ind               : std_logic;
-  signal No_BTR               : std_logic;
-  signal BTR_r                : std_logic;
-  signal Auto_Wait            : std_logic;
-  signal Auto_Wait_t1         : std_logic;
-  signal Auto_Wait_t2         : std_logic;
-  signal IncDecZ              : std_logic;
-
-  -- ALU signals
-  signal BusB                 : std_logic_vector(7 downto 0);
-  signal BusA                 : std_logic_vector(7 downto 0);
-  signal ALU_Q                : std_logic_vector(7 downto 0);
-  signal F_Out                : std_logic_vector(7 downto 0);
-
-  -- Registered micro code outputs
-  signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
-  signal Arith16_r            : std_logic;
-  signal Z16_r                : std_logic;
-  signal ALU_Op_r             : std_logic_vector(3 downto 0);
-  signal Save_ALU_r           : std_logic;
-  signal PreserveC_r          : std_logic;
-  signal MCycles              : std_logic_vector(2 downto 0);
-
-  -- Micro code outputs
-  signal MCycles_d            : std_logic_vector(2 downto 0);
-  signal TStates              : std_logic_vector(2 downto 0);
-  signal IntCycle             : std_logic;
-  signal NMICycle             : std_logic;
-  signal Inc_PC               : std_logic;
-  signal Inc_WZ               : std_logic;
-  signal IncDec_16            : std_logic_vector(3 downto 0);
-  signal Prefix               : std_logic_vector(1 downto 0);
-  signal Read_To_Acc          : std_logic;
-  signal Read_To_Reg          : std_logic;
-  signal Set_BusB_To          : std_logic_vector(3 downto 0);
-  signal Set_BusA_To          : std_logic_vector(3 downto 0);
-  signal ALU_Op               : std_logic_vector(3 downto 0);
-  signal Save_ALU             : std_logic;
-  signal PreserveC            : std_logic;
-  signal Arith16              : std_logic;
-  signal Set_Addr_To          : std_logic_vector(2 downto 0);
-  signal Jump                 : std_logic;
-  signal JumpE                : std_logic;
-  signal JumpXY               : std_logic;
-  signal Call                 : std_logic;
-  signal RstP                 : std_logic;
-  signal LDZ                  : std_logic;
-  signal LDW                  : std_logic;
-  signal LDSPHL               : std_logic;
-  signal IORQ_i               : std_logic;
-  signal Special_LD           : std_logic_vector(2 downto 0);
-  signal ExchangeDH           : std_logic;
-  signal ExchangeRp           : std_logic;
-  signal ExchangeAF           : std_logic;
-  signal ExchangeRS           : std_logic;
-  signal I_DJNZ               : std_logic;
-  signal I_CPL                : std_logic;
-  signal I_CCF                : std_logic;
-  signal I_SCF                : std_logic;
-  signal I_RETN               : std_logic;
-  signal I_BT                 : std_logic;
-  signal I_BC                 : std_logic;
-  signal I_BTR                : std_logic;
-  signal I_RLD                : std_logic;
-  signal I_RRD                : std_logic;
-  signal I_INRC               : std_logic;
-  signal SetDI                : std_logic;
-	signal SetEI                : std_logic;
-	signal IMode                : std_logic_vector(1 downto 0);
-	signal Halt                 : std_logic;
-	signal XYbit_undoc          : std_logic;
-
-
-begin
-
-  mcode : T80_MCode
-    generic map(
-      Mode   => Mode,
-      Flag_C => Flag_C,
-      Flag_N => Flag_N,
-      Flag_P => Flag_P,
-      Flag_X => Flag_X,
-      Flag_H => Flag_H,
-      Flag_Y => Flag_Y,
-      Flag_Z => Flag_Z,
-      Flag_S => Flag_S)
-    port map(
-      IR          => IR,
-      ISet        => ISet,
-      MCycle      => MCycle,
-      F           => F,
-      NMICycle    => NMICycle,
-      IntCycle    => IntCycle,
-      XY_State    => XY_State,
-      MCycles     => MCycles_d,
-      TStates     => TStates,
-      Prefix      => Prefix,
-      Inc_PC      => Inc_PC,
-      Inc_WZ      => Inc_WZ,
-      IncDec_16   => IncDec_16,
-      Read_To_Acc => Read_To_Acc,
-      Read_To_Reg => Read_To_Reg,
-      Set_BusB_To => Set_BusB_To,
-      Set_BusA_To => Set_BusA_To,
-      ALU_Op      => ALU_Op,
-      Save_ALU    => Save_ALU,
-      PreserveC   => PreserveC,
-      Arith16     => Arith16,
-      Set_Addr_To => Set_Addr_To,
-      IORQ        => IORQ_i,
-      Jump        => Jump,
-      JumpE       => JumpE,
-      JumpXY      => JumpXY,
-      Call        => Call,
-      RstP        => RstP,
-      LDZ         => LDZ,
-      LDW         => LDW,
-      LDSPHL      => LDSPHL,
-      Special_LD  => Special_LD,
-      ExchangeDH  => ExchangeDH,
-      ExchangeRp  => ExchangeRp,
-      ExchangeAF  => ExchangeAF,
-      ExchangeRS  => ExchangeRS,
-      I_DJNZ      => I_DJNZ,
-      I_CPL       => I_CPL,
-      I_CCF       => I_CCF,
-      I_SCF       => I_SCF,
-      I_RETN      => I_RETN,
-      I_BT        => I_BT,
-      I_BC        => I_BC,
-      I_BTR       => I_BTR,
-      I_RLD       => I_RLD,
-      I_RRD       => I_RRD,
-      I_INRC      => I_INRC,
-      SetDI       => SetDI,
-      SetEI       => SetEI,
-      IMode       => IMode,
-      Halt        => Halt,
-      NoRead      => NoRead,
-      Write       => Write,
-      XYbit_undoc => XYbit_undoc);
-
-  alu : T80_ALU
-    generic map(
-      Mode   => Mode,
-      Flag_C => Flag_C,
-      Flag_N => Flag_N,
-      Flag_P => Flag_P,
-      Flag_X => Flag_X,
-      Flag_H => Flag_H,
-      Flag_Y => Flag_Y,
-      Flag_Z => Flag_Z,
-      Flag_S => Flag_S)
-    port map(
-      Arith16 => Arith16_r,
-      Z16     => Z16_r,
-      ALU_Op  => ALU_Op_r,
-      IR      => IR(5 downto 0),
-      ISet    => ISet,
-      BusA    => BusA,
-      BusB    => BusB,
-      F_In    => F,
-      Q       => ALU_Q,
-      F_Out   => F_Out);
-
-  ClkEn <= CEN and not BusAck;
-
-  T_Res <= '1' when TState = unsigned(TStates) else '0';
-
-  NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
-                              ((Set_Addr_To = aXY) or
-                               (MCycle = "001" and IR = "11001011") or
-                               (MCycle = "001" and IR = "00110110")) else '0';
-
-  Save_Mux <= BusB when ExchangeRp = '1' else
-              DI_Reg when Save_ALU_r = '0' else
-              ALU_Q;
-
-  process (RESET_n, CLK_n)
-  begin
-    if RESET_n = '0' then
-      PC <= (others => '0');  -- Program Counter
-      A <= (others => '0');
-      TmpAddr <= (others => '0');
-      IR <= "00000000";
-      ISet <= "00";
-      XY_State <= "00";
-      IStatus <= "00";
-      MCycles <= "000";
-      DO <= "00000000";
-
-      ACC <= (others => '1');
-      F <= (others => '1');
-      Ap <= (others => '1');
-      Fp <= (others => '1');
-      I <= (others => '0');
-      R <= (others => '0');
-      SP <= (others => '1');
-      Alternate <= '0';
-
-      Read_To_Reg_r <= "00000";
-      F <= (others => '1');
-      Arith16_r <= '0';
-      BTR_r <= '0';
-      Z16_r <= '0';
-      ALU_Op_r <= "0000";
-      Save_ALU_r <= '0';
-      PreserveC_r <= '0';
-      XY_Ind <= '0';
-
-    elsif CLK_n'event and CLK_n = '1' then
-
-      if ClkEn = '1' then
-
-        ALU_Op_r <= "0000";
-        Save_ALU_r <= '0';
-        Read_To_Reg_r <= "00000";
-
-        MCycles <= MCycles_d;
-
-        if IMode /= "11" then
-          IStatus <= IMode;
-        end if;
-
-        Arith16_r <= Arith16;
-        PreserveC_r <= PreserveC;
-        if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
-          Z16_r <= '1';
-        else
-          Z16_r <= '0';
-        end if;
-
-        if MCycle  = "001" and TState(2) = '0' then
-          -- MCycle = 1 and TState = 1, 2, or 3
-
-          if TState = 2 and Wait_n = '1' then
-            if Mode < 2 then
-              A(7 downto 0) <= std_logic_vector(R);
-              A(15 downto 8) <= I;
-              R(6 downto 0) <= R(6 downto 0) + 1;
-            end if;
-
-            if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
-              PC <= PC + 1;
-            end if;
-
-            if IntCycle = '1' and IStatus = "01" then
-              IR <= "11111111";
-            elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
-              IR <= "00000000";
-            else
-              IR <= DInst;
-            end if;
-
-            ISet <= "00";
-            if Prefix /= "00" then
-              if Prefix = "11" then
-                if IR(5) = '1' then
-                  XY_State <= "10";
-                else
-                  XY_State <= "01";
-                end if;
-              else
-                if Prefix = "10" then
-                  XY_State <= "00";
-                  XY_Ind <= '0';
-                end if;
-                ISet <= Prefix;
-              end if;
-            else
-              XY_State <= "00";
-              XY_Ind <= '0';
-            end if;
-          end if;
-
-        else
-          -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
-          if MCycle = "110" then
-            XY_Ind <= '1';
-            if Prefix = "01" then
-              ISet <= "01";
-            end if;
-          end if;
-
-          if T_Res = '1' then
-            BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
-            if Jump = '1' then
-              A(15 downto 8) <= DI_Reg;
-              A(7 downto 0) <= TmpAddr(7 downto 0);
-              PC(15 downto 8) <= unsigned(DI_Reg);
-              PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-            elsif JumpXY = '1' then
-              A <= RegBusC;
-              PC <= unsigned(RegBusC);
-            elsif Call = '1' or RstP = '1' then
-              A <= TmpAddr;
-              PC <= unsigned(TmpAddr);
-            elsif MCycle = MCycles and NMICycle = '1' then
-              A <= "0000000001100110";
-              PC <= "0000000001100110";
-            elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
-              A(15 downto 8) <= I;
-              A(7 downto 0) <= TmpAddr(7 downto 0);
-              PC(15 downto 8) <= unsigned(I);
-              PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-            else
-              case Set_Addr_To is
-                when aXY =>
-                  if XY_State = "00" then
-                    A <= RegBusC;
-                  else
-                    if NextIs_XY_Fetch = '1' then
-                      A <= std_logic_vector(PC);
-                    else
-                      A <= TmpAddr;
-                    end if;
-                  end if;
-                when aIOA =>
-                  if Mode = 3 then
-                    -- Memory map I/O on GBZ80
-                    A(15 downto 8) <= (others => '1');
-                  elsif Mode = 2 then
-                    -- Duplicate I/O address on 8080
-                    A(15 downto 8) <= DI_Reg;
-                  else
-                    A(15 downto 8) <= ACC;
-                  end if;
-                  A(7 downto 0) <= DI_Reg;
-                when aSP =>
-                  A <= std_logic_vector(SP);
-                when aBC =>
-                  if Mode = 3 and IORQ_i = '1' then
-                    -- Memory map I/O on GBZ80
-                    A(15 downto 8) <= (others => '1');
-                    A(7 downto 0) <= RegBusC(7 downto 0);
-                  else
-                    A <= RegBusC;
-                  end if;
-                when aDE =>
-                  A <= RegBusC;
-                when aZI =>
-                  if Inc_WZ = '1' then
-                    A <= std_logic_vector(unsigned(TmpAddr) + 1);
-                  else
-                    A(15 downto 8) <= DI_Reg;
-                    A(7 downto 0) <= TmpAddr(7 downto 0);
-                  end if;
-                when others =>
-                  A <= std_logic_vector(PC);
-              end case;
-            end if;
-
-            Save_ALU_r <= Save_ALU;
-            ALU_Op_r <= ALU_Op;
-
-            if I_CPL = '1' then
-              -- CPL
-              ACC <= not ACC;
-              F(Flag_Y) <= not ACC(5);
-              F(Flag_H) <= '1';
-              F(Flag_X) <= not ACC(3);
-              F(Flag_N) <= '1';
-            end if;
-            if I_CCF = '1' then
-              -- CCF
-              F(Flag_C) <= not F(Flag_C);
-              F(Flag_Y) <= ACC(5);
-              F(Flag_H) <= F(Flag_C);
-              F(Flag_X) <= ACC(3);
-              F(Flag_N) <= '0';
-            end if;
-            if I_SCF = '1' then
-              -- SCF
-              F(Flag_C) <= '1';
-              F(Flag_Y) <= ACC(5);
-              F(Flag_H) <= '0';
-              F(Flag_X) <= ACC(3);
-              F(Flag_N) <= '0';
-            end if;
-          end if;
-
-          if TState = 2 and Wait_n = '1' then
-            if ISet = "01" and MCycle = "111" then
-              IR <= DInst;
-            end if;
-            if JumpE = '1' then
-              PC <= unsigned(signed(PC) + signed(DI_Reg));
-            elsif Inc_PC = '1' then
-              PC <= PC + 1;
-            end if;
-            if BTR_r = '1' then
-              PC <= PC - 2;
-            end if;
-            if RstP = '1' then
-              TmpAddr <= (others =>'0');
-              TmpAddr(5 downto 3) <= IR(5 downto 3);
-            end if;
-          end if;
-          if TState = 3 and MCycle = "110" then
-            TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
-          end if;
-
-          if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
-            if IncDec_16(2 downto 0) = "111" then
-              if IncDec_16(3) = '1' then
-                SP <= SP - 1;
-              else
-                SP <= SP + 1;
-              end if;
-            end if;
-          end if;
-
-          if LDSPHL = '1' then
-            SP <= unsigned(RegBusC);
-          end if;
-          if ExchangeAF = '1' then
-            Ap <= ACC;
-            ACC <= Ap;
-            Fp <= F;
-            F <= Fp;
-          end if;
-          if ExchangeRS = '1' then
-            Alternate <= not Alternate;
-          end if;
-        end if;
-
-        if TState = 3 then
-          if LDZ = '1' then
-            TmpAddr(7 downto 0) <= DI_Reg;
-          end if;
-          if LDW = '1' then
-            TmpAddr(15 downto 8) <= DI_Reg;
-          end if;
-
-          if Special_LD(2) = '1' then
-            case Special_LD(1 downto 0) is
-              when "00" =>
-                ACC <= I;
-                F(Flag_P) <= IntE_FF2;
-              when "01" =>
-                ACC <= std_logic_vector(R);
-                F(Flag_P) <= IntE_FF2;
-              when "10" =>
-                I <= ACC;
-              when others =>
-                R <= unsigned(ACC);
-            end case;
-          end if;
-        end if;
-
-        if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
-          if Mode = 3 then
-            F(6) <= F_Out(6);
-            F(5) <= F_Out(5);
-            F(7) <= F_Out(7);
-            if PreserveC_r = '0' then
-              F(4) <= F_Out(4);
-            end if;
-          else
-            F(7 downto 1) <= F_Out(7 downto 1);
-            if PreserveC_r = '0' then
-              F(Flag_C) <= F_Out(0);
-            end if;
-          end if;
-        end if;
-        if T_Res = '1' and I_INRC = '1' then
-          F(Flag_H) <= '0';
-          F(Flag_N) <= '0';
-          if DI_Reg(7 downto 0) = "00000000" then
-            F(Flag_Z) <= '1';
-          else
-            F(Flag_Z) <= '0';
-          end if;
-          F(Flag_S) <= DI_Reg(7);
-          F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
-                            DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
-        end if;
-
-        if TState = 1 then
-          DO <= BusB;
-          if I_RLD = '1' then
-            DO(3 downto 0) <= BusA(3 downto 0);
-            DO(7 downto 4) <= BusB(3 downto 0);
-          end if;
-          if I_RRD = '1' then
-            DO(3 downto 0) <= BusB(7 downto 4);
-            DO(7 downto 4) <= BusA(3 downto 0);
-          end if;
-        end if;
-
-        if T_Res = '1' then
-          Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
-          Read_To_Reg_r(4) <= Read_To_Reg;
-          if Read_To_Acc = '1' then
-            Read_To_Reg_r(3 downto 0) <= "0111";
-            Read_To_Reg_r(4) <= '1';
-          end if;
-        end if;
-
-        if TState = 1 and I_BT = '1' then
-          F(Flag_X) <= ALU_Q(3);
-          F(Flag_Y) <= ALU_Q(1);
-          F(Flag_H) <= '0';
-          F(Flag_N) <= '0';
-        end if;
-        if I_BC = '1' or I_BT = '1' then
-          F(Flag_P) <= IncDecZ;
-        end if;
-
-        if (TState = 1 and Save_ALU_r = '0') or
-          (Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-          case Read_To_Reg_r is
-            when "10111" =>
-              ACC <= Save_Mux;
-            when "10110" =>
-              DO <= Save_Mux;
-            when "11000" =>
-              SP(7 downto 0) <= unsigned(Save_Mux);
-            when "11001" =>
-              SP(15 downto 8) <= unsigned(Save_Mux);
-            when "11011" =>
-              F <= Save_Mux;
-            when others =>
-          end case;
-          if XYbit_undoc='1' then
-            DO <= ALU_Q;
-          end if;
-        end if;
-
-      end if;
-
-    end if;
-
-  end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
-  process (CLK_n)
-  begin
-    if CLK_n'event and CLK_n = '1' then
-      if ClkEn = '1' then
-        -- Bus A / Write
-        RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
-        if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
-          RegAddrA_r <= XY_State(1) & "11";
-        end if;
-
-        -- Bus B
-        RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
-        if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
-          RegAddrB_r <= XY_State(1) & "11";
-        end if;
-
-        -- Address from register
-        RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-        -- Jump (HL), LD SP,HL
-        if (JumpXY = '1' or LDSPHL = '1') then
-          RegAddrC <= Alternate & "10";
-        end if;
-        if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
-          RegAddrC <= XY_State(1) & "11";
-        end if;
-
-        if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
-          IncDecZ <= F_Out(Flag_Z);
-        end if;
-        if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
-          if ID16 = 0 then
-            IncDecZ <= '0';
-          else
-            IncDecZ <= '1';
-          end if;
-        end if;
-
-        RegBusA_r <= RegBusA;
-      end if;
-    end if;
-  end process;
-
-  RegAddrA <=
-    -- 16 bit increment/decrement
-    Alternate & IncDec_16(1 downto 0) when (TState = 2 or
-                                            (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
-    XY_State(1) & "11" when (TState = 2 or
-                             (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-    -- EX HL,DL
-    Alternate & "10" when ExchangeDH = '1' and TState = 3 else
-    Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-    -- Bus A / Write
-    RegAddrA_r;
-
-  RegAddrB <=
-    -- EX HL,DL
-    Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-    -- Bus B
-    RegAddrB_r;
-
-  ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
-          signed(RegBusA) + 1;
-
-  process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
-           ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-  begin
-    RegWEH <= '0';
-    RegWEL <= '0';
-    if (TState = 1 and Save_ALU_r = '0') or
-      (Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-      case Read_To_Reg_r is
-        when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
-          RegWEH <= not Read_To_Reg_r(0);
-          RegWEL <= Read_To_Reg_r(0);
-        when others =>
-      end case;
-    end if;
-
-    if ExchangeDH = '1' and (TState = 3 or TState = 4) then
-      RegWEH <= '1';
-      RegWEL <= '1';
-    end if;
-
-    if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-      case IncDec_16(1 downto 0) is
-        when "00" | "01" | "10" =>
-          RegWEH <= '1';
-          RegWEL <= '1';
-        when others =>
-      end case;
-    end if;
-  end process;
-
-  process (Save_Mux, RegBusB, RegBusA_r, ID16,
-           ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-  begin
-    RegDIH <= Save_Mux;
-    RegDIL <= Save_Mux;
-
-    if ExchangeDH = '1' and TState = 3 then
-      RegDIH <= RegBusB(15 downto 8);
-      RegDIL <= RegBusB(7 downto 0);
-    end if;
-    if ExchangeDH = '1' and TState = 4 then
-      RegDIH <= RegBusA_r(15 downto 8);
-      RegDIL <= RegBusA_r(7 downto 0);
-    end if;
-
-    if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-      RegDIH <= std_logic_vector(ID16(15 downto 8));
-      RegDIL <= std_logic_vector(ID16(7 downto 0));
-    end if;
-  end process;
-
-  Regs : T80_Reg
-    port map(
-      Clk   => CLK_n,
-      CEN   => ClkEn,
-      WEH   => RegWEH,
-      WEL   => RegWEL,
-      AddrA => RegAddrA,
-      AddrB => RegAddrB,
-      AddrC => RegAddrC,
-      DIH   => RegDIH,
-      DIL   => RegDIL,
-      DOAH  => RegBusA(15 downto 8),
-      DOAL  => RegBusA(7 downto 0),
-      DOBH  => RegBusB(15 downto 8),
-      DOBL  => RegBusB(7 downto 0),
-      DOCH  => RegBusC(15 downto 8),
-      DOCL  => RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
-  process (CLK_n)
-  begin
-    if CLK_n'event and CLK_n = '1' then
-      if ClkEn = '1' then
-        case Set_BusB_To is
-          when "0111" =>
-            BusB <= ACC;
-          when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-            if Set_BusB_To(0) = '1' then
-              BusB <= RegBusB(7 downto 0);
-            else
-              BusB <= RegBusB(15 downto 8);
-            end if;
-          when "0110" =>
-            BusB <= DI_Reg;
-          when "1000" =>
-            BusB <= std_logic_vector(SP(7 downto 0));
-          when "1001" =>
-            BusB <= std_logic_vector(SP(15 downto 8));
-          when "1010" =>
-            BusB <= "00000001";
-          when "1011" =>
-            BusB <= F;
-          when "1100" =>
-            BusB <= std_logic_vector(PC(7 downto 0));
-          when "1101" =>
-            BusB <= std_logic_vector(PC(15 downto 8));
-          when "1110" =>
-            BusB <= "00000000";
-          when others =>
-            BusB <= "--------";
-        end case;
-
-        case Set_BusA_To is
-          when "0111" =>
-            BusA <= ACC;
-          when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-            if Set_BusA_To(0) = '1' then
-              BusA <= RegBusA(7 downto 0);
-            else
-              BusA <= RegBusA(15 downto 8);
-            end if;
-          when "0110" =>
-            BusA <= DI_Reg;
-          when "1000" =>
-            BusA <= std_logic_vector(SP(7 downto 0));
-          when "1001" =>
-            BusA <= std_logic_vector(SP(15 downto 8));
-          when "1010" =>
-            BusA <= "00000000";
-          when others =>
-            BusB <= "--------";
-        end case;
-        if XYbit_undoc='1' then
-          BusA <= DI_Reg;
-          BusB <= DI_Reg;
-        end if;
-      end if;
-    end if;
-  end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
-  process (RESET_n,CLK_n)
-  begin
-    if RESET_n = '0' then
-      RFSH_n <= '1';
-    elsif CLK_n'event and CLK_n = '1' then
-      if CEN = '1' then
-        if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
-          RFSH_n <= '0';
-        else
-          RFSH_n <= '1';
-        end if;
-      end if;
-    end if;
-  end process;
-
-  MC <= std_logic_vector(MCycle);
-  TS <= std_logic_vector(TState);
-  DI_Reg <= DI;
-  HALT_n <= not Halt_FF;
-  BUSAK_n <= not BusAck;
-  IntCycle_n <= not IntCycle;
-  IntE <= IntE_FF1;
-  IORQ <= IORQ_i;
-  Stop <= I_DJNZ;
-
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
-  process (RESET_n, CLK_n)
-    variable OldNMI_n : std_logic;
-  begin
-    if RESET_n = '0' then
-      BusReq_s <= '0';
-      INT_s <= '0';
-      NMI_s <= '0';
-      OldNMI_n := '0';
-    elsif CLK_n'event and CLK_n = '1' then
-      if CEN = '1' then
-        BusReq_s <= not BUSRQ_n;
-        INT_s <= not INT_n;
-        if NMICycle = '1' then
-          NMI_s <= '0';
-        elsif NMI_n = '0' and OldNMI_n = '1' then
-          NMI_s <= '1';
-        end if;
-        OldNMI_n := NMI_n;
-      end if;
-    end if;
-  end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
-  process (RESET_n, CLK_n)
-  begin
-    if RESET_n = '0' then
-      MCycle <= "001";
-      TState <= "000";
-      Pre_XY_F_M <= "000";
-      Halt_FF <= '0';
-      BusAck <= '0';
-      NMICycle <= '0';
-      IntCycle <= '0';
-      IntE_FF1 <= '0';
-      IntE_FF2 <= '0';
-      No_BTR <= '0';
-      Auto_Wait_t1 <= '0';
-      Auto_Wait_t2 <= '0';
-      M1_n <= '1';
-    elsif CLK_n'event and CLK_n = '1' then
-      if CEN = '1' then
-        Auto_Wait_t1 <= Auto_Wait;
-        Auto_Wait_t2 <= Auto_Wait_t1;
-        No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
-                  (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
-                  (I_BTR and (not IR(4) or F(Flag_Z)));
-        if TState = 2 then
-          if SetEI = '1' then
-            IntE_FF1 <= '1';
-            IntE_FF2 <= '1';
-          end if;
-          if I_RETN = '1' then
-            IntE_FF1 <= IntE_FF2;
-          end if;
-        end if;
-        if TState = 3 then
-          if SetDI = '1' then
-            IntE_FF1 <= '0';
-            IntE_FF2 <= '0';
-          end if;
-        end if;
-        if IntCycle = '1' or NMICycle = '1' then
-          Halt_FF <= '0';
-        end if;
-        if MCycle = "001" and TState = 2 and Wait_n = '1' then
-          M1_n <= '1';
-        end if;
-        if BusReq_s = '1' and BusAck = '1' then
-        else
-          BusAck <= '0';
-          if TState = 2 and Wait_n = '0' then
-          elsif T_Res = '1' then
-            if Halt = '1' then
-              Halt_FF <= '1';
-            end if;
-            if BusReq_s = '1' then
-              BusAck <= '1';
-            else
-              TState <= "001";
-              if NextIs_XY_Fetch = '1' then
-                MCycle <= "110";
-                Pre_XY_F_M <= MCycle;
-                if IR = "00110110" and Mode = 0 then
-                  Pre_XY_F_M <= "010";
-                end if;
-              elsif (MCycle = "111") or
-                (MCycle = "110" and Mode = 1 and ISet /= "01") then
-                MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
-              elsif (MCycle = MCycles) or
-                No_BTR = '1' or
-                (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
-                M1_n <= '0';
-                MCycle <= "001";
-                IntCycle <= '0';
-                NMICycle <= '0';
-                if NMI_s = '1' and Prefix = "00" then
-                  NMICycle <= '1';
-                  IntE_FF1 <= '0';
-                elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
-                  IntCycle <= '1';
-                  IntE_FF1 <= '0';
-                  IntE_FF2 <= '0';
-                end if;
-              else
-                MCycle <= std_logic_vector(unsigned(MCycle) + 1);
-              end if;
-            end if;
-          else
-            if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
-
-              TState <= TState + 1;
-            end if;
-          end if;
-        end if;
-        if TState = 0 then
-          M1_n <= '0';
-        end if;
-      end if;
-    end if;
-  end process;
-
-  process (IntCycle, NMICycle, MCycle)
-  begin
-    Auto_Wait <= '0';
-    if IntCycle = '1' or NMICycle = '1' then
-      if MCycle = "001" then
-        Auto_Wait <= '1';
-      end if;
-    end if;
-  end process;
-
-end;
diff --git a/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/cpu/T80_ALU.vhd
deleted file mode 100644
index 7e8a9995..00000000
--- a/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/cpu/T80_ALU.vhd	
+++ /dev/null
@@ -1,370 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0238 : Fixed zero flag for 16 bit SBC and ADC
---
---      0240 : Added GB operations
---
---      0242 : Cleanup
---
---      0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16         : in  std_logic;
-		Z16             : in  std_logic;
-		ALU_Op          : in  std_logic_vector(3 downto 0);
-		IR              : in  std_logic_vector(5 downto 0);
-		ISet            : in  std_logic_vector(1 downto 0);
-		BusA            : in  std_logic_vector(7 downto 0);
-		BusB            : in  std_logic_vector(7 downto 0);
-		F_In            : in  std_logic_vector(7 downto 0);
-		Q               : out std_logic_vector(7 downto 0);
-		F_Out           : out std_logic_vector(7 downto 0)
-	);
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
-	procedure AddSub(A        : std_logic_vector;
-					 B        : std_logic_vector;
-					 Sub      : std_logic;
-					 Carry_In : std_logic;
-			  signal Res      : out std_logic_vector;
-			  signal Carry    : out std_logic) is
-
-		variable B_i          : unsigned(A'length - 1 downto 0);
-		variable Res_i        : unsigned(A'length + 1 downto 0);
-	begin
-		if Sub = '1' then
-			B_i := not unsigned(B);
-		else
-			B_i :=     unsigned(B);
-		end if;
-
-		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
-		Carry <= Res_i(A'length + 1);
-		Res <= std_logic_vector(Res_i(A'length downto 1));
-	end;
-
-	-- AddSub variables (temporary signals)
-	signal UseCarry                : std_logic;
-	signal Carry7_v                : std_logic;
-	signal Overflow_v              : std_logic;
-	signal HalfCarry_v             : std_logic;
-	signal Carry_v                 : std_logic;
-	signal Q_v                     : std_logic_vector(7 downto 0);
-
-	signal BitMask                 : std_logic_vector(7 downto 0);
-
-begin
-
-	with IR(5 downto 3) select BitMask <= "00000001" when "000",
-										  "00000010" when "001",
-										  "00000100" when "010",
-										  "00001000" when "011",
-										  "00010000" when "100",
-										  "00100000" when "101",
-										  "01000000" when "110",
-										  "10000000" when others;
-
-	UseCarry <= not ALU_Op(2) and ALU_Op(0);
-	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
-	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
-	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-	-- bug fix - parity flag is just parity for 8080, also overflow for Z80
-	process (Carry_v, Carry7_v, Q_v)
-	begin
-		if(Mode=2) then
-			OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
-					   Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7));  else
-	OverFlow_v <= Carry_v xor Carry7_v;
-		end if;
-	end process;
-
-	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
-		variable Q_t : std_logic_vector(7 downto 0);
-		variable DAA_Q : unsigned(8 downto 0);
-	begin
-		Q_t := "--------";
-		F_Out <= F_In;
-		DAA_Q := "---------";
-		case ALU_Op is
-		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_C) <= '0';
-			case ALU_OP(2 downto 0) is
-			when "000" | "001" => -- ADD, ADC
-				Q_t := Q_v;
-				F_Out(Flag_C) <= Carry_v;
-				F_Out(Flag_H) <= HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "010" | "011" | "111" => -- SUB, SBC, CP
-				Q_t := Q_v;
-				F_Out(Flag_N) <= '1';
-				F_Out(Flag_C) <= not Carry_v;
-				F_Out(Flag_H) <= not HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "100" => -- AND
-				Q_t(7 downto 0) := BusA and BusB;
-				F_Out(Flag_H) <= '1';
-			when "101" => -- XOR
-				Q_t(7 downto 0) := BusA xor BusB;
-				F_Out(Flag_H) <= '0';
-			when others => -- OR "110"
-				Q_t(7 downto 0) := BusA or BusB;
-				F_Out(Flag_H) <= '0';
-			end case;
-			if ALU_Op(2 downto 0) = "111" then -- CP
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			else
-				F_Out(Flag_X) <= Q_t(3);
-				F_Out(Flag_Y) <= Q_t(5);
-			end if;
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				if Z16 = '1' then
-					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
-				end if;
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			case ALU_Op(2 downto 0) is
-			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
-			when others =>
-				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			end case;
-			if Arith16 = '1' then
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-				F_Out(Flag_P) <= F_In(Flag_P);
-			end if;
-		when "1100" =>
-			-- DAA
-			F_Out(Flag_H) <= F_In(Flag_H);
-			F_Out(Flag_C) <= F_In(Flag_C);
-			DAA_Q(7 downto 0) := unsigned(BusA);
-			DAA_Q(8) := '0';
-			if F_In(Flag_N) = '0' then
-				-- After addition
-				-- Alow > 9 or H = 1
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if (DAA_Q(3 downto 0) > 9) then
-						F_Out(Flag_H) <= '1';
-					else
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q := DAA_Q + 6;
-				end if;
-				-- new Ahigh > 9 or C = 1
-				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q + 96; -- 0x60
-				end if;
-			else
-				-- After subtraction
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if DAA_Q(3 downto 0) > 5 then
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
-				end if;
-				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q - 352; -- 0x160
-				end if;
-			end if;
-			F_Out(Flag_X) <= DAA_Q(3);
-			F_Out(Flag_Y) <= DAA_Q(5);
-			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
-			Q_t := std_logic_vector(DAA_Q(7 downto 0));
-			if DAA_Q(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= DAA_Q(7);
-			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
-				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
-		when "1101" | "1110" =>
-			-- RLD, RRD
-			Q_t(7 downto 4) := BusA(7 downto 4);
-			if ALU_Op(0) = '1' then
-				Q_t(3 downto 0) := BusB(7 downto 4);
-			else
-				Q_t(3 downto 0) := BusB(3 downto 0);
-			end if;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-		when "1001" =>
-			-- BIT
-			Q_t(7 downto 0) := BusB and BitMask;
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				F_Out(Flag_P) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-				F_Out(Flag_P) <= '0';
-			end if;
-			F_Out(Flag_H) <= '1';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= '0';
-			F_Out(Flag_Y) <= '0';
-			if IR(2 downto 0) /= "110" then
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			end if;
-		when "1010" =>
-			-- SET
-			Q_t(7 downto 0) := BusB or BitMask;
-		when "1011" =>
-			-- RES
-			Q_t(7 downto 0) := BusB and not BitMask;
-		when "1000" =>
-			-- ROT
-			case IR(5 downto 3) is
-			when "000" => -- RLC
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := BusA(7);
-				F_Out(Flag_C) <= BusA(7);
-			when "010" => -- RL
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(7);
-			when "001" => -- RRC
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(0);
-				F_Out(Flag_C) <= BusA(0);
-			when "011" => -- RR
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(0);
-			when "100" => -- SLA
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := '0';
-				F_Out(Flag_C) <= BusA(7);
-			when "110" => -- SLL (Undocumented) / SWAP
-				if Mode = 3 then
-					Q_t(7 downto 4) := BusA(3 downto 0);
-					Q_t(3 downto 0) := BusA(7 downto 4);
-					F_Out(Flag_C) <= '0';
-				else
-					Q_t(7 downto 1) := BusA(6 downto 0);
-					Q_t(0) := '1';
-					F_Out(Flag_C) <= BusA(7);
-				end if;
-			when "101" => -- SRA
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(7);
-				F_Out(Flag_C) <= BusA(0);
-			when others => -- SRL
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := '0';
-				F_Out(Flag_C) <= BusA(0);
-			end case;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			if ISet = "00" then
-				F_Out(Flag_P) <= F_In(Flag_P);
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-			end if;
-		when others =>
-			null;
-		end case;
-		Q <= Q_t;
-	end process;
-end;
diff --git a/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/cpu/T80_MCode.vhd
deleted file mode 100644
index 7d407fb8..00000000
--- a/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/cpu/T80_MCode.vhd	
+++ /dev/null
@@ -1,2027 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0211 : Fixed IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0235 : Added IM 2 fix by Mike Johnson
---
---      0238 : Added NoRead signal
---
---      0238b: Fixed instruction timing for POP and DJNZ
---
---      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
-
---      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
---
---      0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80_MCode is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR                              : in std_logic_vector(7 downto 0);
-		ISet                    : in std_logic_vector(1 downto 0);
-		MCycle                  : in std_logic_vector(2 downto 0);
-		F                               : in std_logic_vector(7 downto 0);
-		NMICycle                : in std_logic;
-		IntCycle                : in std_logic;
-		XY_State                : in std_logic_vector(1 downto 0);
-		MCycles                 : out std_logic_vector(2 downto 0);
-		TStates                 : out std_logic_vector(2 downto 0);
-		Prefix                  : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD
-		Inc_PC                  : out std_logic;
-		Inc_WZ                  : out std_logic;
-		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg             : out std_logic;
-		Read_To_Acc             : out std_logic;
-		Set_BusA_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op                  : out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU                : out std_logic;
-		PreserveC               : out std_logic;
-		Arith16                 : out std_logic;
-		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ                    : out std_logic;
-		Jump                    : out std_logic;
-		JumpE                   : out std_logic;
-		JumpXY                  : out std_logic;
-		Call                    : out std_logic;
-		RstP                    : out std_logic;
-		LDZ                             : out std_logic;
-		LDW                             : out std_logic;
-		LDSPHL                  : out std_logic;
-		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH              : out std_logic;
-		ExchangeRp              : out std_logic;
-		ExchangeAF              : out std_logic;
-		ExchangeRS              : out std_logic;
-		I_DJNZ                  : out std_logic;
-		I_CPL                   : out std_logic;
-		I_CCF                   : out std_logic;
-		I_SCF                   : out std_logic;
-		I_RETN                  : out std_logic;
-		I_BT                    : out std_logic;
-		I_BC                    : out std_logic;
-		I_BTR                   : out std_logic;
-		I_RLD                   : out std_logic;
-		I_RRD                   : out std_logic;
-		I_INRC                  : out std_logic;
-		SetDI                   : out std_logic;
-		SetEI                   : out std_logic;
-		IMode                   : out std_logic_vector(1 downto 0);
-		Halt                    : out std_logic;
-		NoRead                  : out std_logic;
-		Write                   : out std_logic;
-		XYbit_undoc             : out std_logic
-	);
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
-	constant aNone      : std_logic_vector(2 downto 0) := "111";
-	constant aBC        : std_logic_vector(2 downto 0) := "000";
-	constant aDE        : std_logic_vector(2 downto 0) := "001";
-	constant aXY        : std_logic_vector(2 downto 0) := "010";
-	constant aIOA       : std_logic_vector(2 downto 0) := "100";
-	constant aSP        : std_logic_vector(2 downto 0) := "101";
-	constant aZI        : std_logic_vector(2 downto 0) := "110";
-
-	function is_cc_true(
-		F : std_logic_vector(7 downto 0);
-		cc : bit_vector(2 downto 0)
-		) return boolean is
-	begin
-		if Mode = 3 then
-			case cc is
-			when "000" => return F(7) = '0'; -- NZ
-			when "001" => return F(7) = '1'; -- Z
-			when "010" => return F(4) = '0'; -- NC
-			when "011" => return F(4) = '1'; -- C
-			when "100" => return false;
-			when "101" => return false;
-			when "110" => return false;
-			when "111" => return false;
-			end case;
-		else
-			case cc is
-			when "000" => return F(6) = '0'; -- NZ
-			when "001" => return F(6) = '1'; -- Z
-			when "010" => return F(0) = '0'; -- NC
-			when "011" => return F(0) = '1'; -- C
-			when "100" => return F(2) = '0'; -- PO
-			when "101" => return F(2) = '1'; -- PE
-			when "110" => return F(7) = '0'; -- P
-			when "111" => return F(7) = '1'; -- M
-			end case;
-		end if;
-	end;
-
-begin
-
-	process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State)
-		variable DDD : std_logic_vector(2 downto 0);
-		variable SSS : std_logic_vector(2 downto 0);
-		variable DPair : std_logic_vector(1 downto 0);
-		variable IRB : bit_vector(7 downto 0);
-	begin
-		DDD := IR(5 downto 3);
-		SSS := IR(2 downto 0);
-		DPair := IR(5 downto 4);
-		IRB := to_bitvector(IR);
-
-		MCycles <= "001";
-		if MCycle = "001" then
-			TStates <= "100";
-		else
-			TStates <= "011";
-		end if;
-		Prefix <= "00";
-		Inc_PC <= '0';
-		Inc_WZ <= '0';
-		IncDec_16 <= "0000";
-		Read_To_Acc <= '0';
-		Read_To_Reg <= '0';
-		Set_BusB_To <= "0000";
-		Set_BusA_To <= "0000";
-		ALU_Op <= "0" & IR(5 downto 3);
-		Save_ALU <= '0';
-		PreserveC <= '0';
-		Arith16 <= '0';
-		IORQ <= '0';
-		Set_Addr_To <= aNone;
-		Jump <= '0';
-		JumpE <= '0';
-		JumpXY <= '0';
-		Call <= '0';
-		RstP <= '0';
-		LDZ <= '0';
-		LDW <= '0';
-		LDSPHL <= '0';
-		Special_LD <= "000";
-		ExchangeDH <= '0';
-		ExchangeRp <= '0';
-		ExchangeAF <= '0';
-		ExchangeRS <= '0';
-		I_DJNZ <= '0';
-		I_CPL <= '0';
-		I_CCF <= '0';
-		I_SCF <= '0';
-		I_RETN <= '0';
-		I_BT <= '0';
-		I_BC <= '0';
-		I_BTR <= '0';
-		I_RLD <= '0';
-		I_RRD <= '0';
-		I_INRC <= '0';
-		SetDI <= '0';
-		SetEI <= '0';
-		IMode <= "11";
-		Halt <= '0';
-		NoRead <= '0';
-		Write <= '0';
-		XYbit_undoc <= '0';
-
-		case ISet is
-		when "00" =>
-
-------------------------------------------------------------------------------
---
---      Unprefixed instructions
---
-------------------------------------------------------------------------------
-
-		case IRB is
--- 8 BIT LOAD GROUP
-		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-			-- LD r,r'
-			Set_BusB_To(2 downto 0) <= SSS;
-			ExchangeRp <= '1';
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-			-- LD r,n
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-			-- LD r,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-			-- LD (HL),r
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110110" =>
-			-- LD (HL),n
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00001010" =>
-			-- LD A,(BC)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00011010" =>
-			-- LD A,(DE)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00111010" =>
-			if Mode = 3 then
-				-- LDD A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD A,(nn)
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-				when 4 =>
-					Read_To_Acc <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00000010" =>
-			-- LD (BC),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00010010" =>
-			-- LD (DE),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110010" =>
-			if Mode = 3 then
-				-- LDD (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),A
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					Set_BusB_To <= "0111";
-				when 4 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 16 BIT LOAD GROUP
-		when "00000001"|"00010001"|"00100001"|"00110001" =>
-			-- LD dd,nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1000";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1001";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-		when "00101010" =>
-			if Mode = 3 then
-				-- LDI A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD HL,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Set_BusA_To(2 downto 0) <= "101"; -- L
-					Read_To_Reg <= '1';
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Set_BusA_To(2 downto 0) <= "100"; -- H
-					Read_To_Reg <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00100010" =>
-			if Mode = 3 then
-				-- LDI (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "0101"; -- L
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "0100"; -- H
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11111001" =>
-			-- LD SP,HL
-			TStates <= "110";
-			LDSPHL <= '1';
-		when "11000101"|"11010101"|"11100101"|"11110101" =>
-			-- PUSH qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_TO <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "0111";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '0';
-					Set_BusB_To(3) <= '0';
-				end if;
-			when 2 =>
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "1011";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '1';
-					Set_BusB_To(3) <= '0';
-				end if;
-				Write <= '1';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "11000001"|"11010001"|"11100001"|"11110001" =>
-			-- POP qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1011";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				IncDec_16 <= "0111";
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "0111";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
-		when "11101011" =>
-			if Mode /= 3 then
-				-- EX DE,HL
-				ExchangeDH <= '1';
-			end if;
-		when "00001000" =>
-			if Mode = 3 then
-				-- LD (nn),SP
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "1000";
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "1001";
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EX AF,AF'
-				ExchangeAF <= '1';
-			end if;
-		when "11011001" =>
-			if Mode = 3 then
-				-- RETI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-					SetEI <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EXX
-				ExchangeRS <= '1';
-			end if;
-		when "11100011" =>
-			if Mode /= 3 then
-				-- EX (SP),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aSP;
-				when 2 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0101";
-					Set_BusB_To <= "0101";
-					Set_Addr_To <= aSP;
-				when 3 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0100";
-					Set_BusB_To <= "0100";
-					Set_Addr_To <= aSP;
-				when 5 =>
-					IncDec_16 <= "1111";
-					TStates <= "101";
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
-		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-			-- ADD A,r
-			-- ADC A,r
-			-- SUB A,r
-			-- SBC A,r
-			-- AND A,r
-			-- OR A,r
-			-- XOR A,r
-			-- CP A,r
-			Set_BusB_To(2 downto 0) <= SSS;
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-			-- ADD A,(HL)
-			-- ADC A,(HL)
-			-- SUB A,(HL)
-			-- SBC A,(HL)
-			-- AND A,(HL)
-			-- OR A,(HL)
-			-- XOR A,(HL)
-			-- CP A,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			when others => null;
-			end case;
-		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-			-- ADD A,n
-			-- ADC A,n
-			-- SUB A,n
-			-- SBC A,n
-			-- AND A,n
-			-- OR A,n
-			-- XOR A,n
-			-- CP A,n
-			MCycles <= "010";
-			if MCycle = "010" then
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			end if;
-		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-			-- INC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0000";
-		when "00110100" =>
-			-- INC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				ALU_Op <= "0000";
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-			-- DEC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0010";
-		when "00110101" =>
-			-- DEC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				ALU_Op <= "0010";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
-		when "00100111" =>
-			-- DAA
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			ALU_Op <= "1100";
-			Save_ALU <= '1';
-		when "00101111" =>
-			-- CPL
-			I_CPL <= '1';
-		when "00111111" =>
-			-- CCF
-			I_CCF <= '1';
-		when "00110111" =>
-			-- SCF
-			I_SCF <= '1';
-		when "00000000" =>
-			if NMICycle = '1' then
-				-- NMI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif IntCycle = '1' then
-				-- INT (IM 2)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					LDZ <= '1';
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 5 =>
-					Jump <= '1';
-				when others => null;
-				end case;
-			else
-				-- NOP
-			end if;
-		when "01110110" =>
-			-- HALT
-			Halt <= '1';
-		when "11110011" =>
-			-- DI
-			SetDI <= '1';
-		when "11111011" =>
-			-- EI
-			SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
-		when "00001001"|"00011001"|"00101001"|"00111001" =>
-			-- ADD HL,ss
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				NoRead <= '1';
-				ALU_Op <= "0000";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusA_To(2 downto 0) <= "101";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-				when others =>
-					Set_BusB_To <= "1000";
-				end case;
-				TStates <= "100";
-				Arith16 <= '1';
-			when 3 =>
-				NoRead <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				ALU_Op <= "0001";
-				Set_BusA_To(2 downto 0) <= "100";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-				when others =>
-					Set_BusB_To <= "1001";
-				end case;
-				Arith16 <= '1';
-			when others =>
-			end case;
-		when "00000011"|"00010011"|"00100011"|"00110011" =>
-			-- INC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "01";
-			IncDec_16(1 downto 0) <= DPair;
-		when "00001011"|"00011011"|"00101011"|"00111011" =>
-			-- DEC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "11";
-			IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
-		when "00000111"
-			-- RLCA
-			|"00010111"
-			-- RLA
-			|"00001111"
-			-- RRCA
-			|"00011111" =>
-			-- RRA
-			Set_BusA_To(2 downto 0) <= "111";
-			ALU_Op <= "1000";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-
--- JUMP GROUP
-		when "11000011" =>
-			-- JP nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				Inc_PC <= '1';
-				Jump <= '1';
-			when others => null;
-			end case;
-		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+C),A
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-						Set_BusB_To     <= "0111";
-					when 2 =>
-						Write <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "01" =>
-					-- LD (nn),A
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						Set_BusB_To <= "0111";
-					when 4 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "10" =>
-					-- LD A,($FF00+C)
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-					when 2 =>
-						Read_To_Acc <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "11" =>
-					-- LD A,(nn)
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-					when 4 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- JP cc,nn
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Jump <= '1';
-					end if;
-				when others => null;
-				end case;
-			end if;
-		when "00011000" =>
-			if Mode /= 2 then
-				-- JR e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00111000" =>
-			if Mode /= 2 then
-				-- JR C,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00110000" =>
-			if Mode /= 2 then
-				-- JR NC,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00101000" =>
-			if Mode /= 2 then
-				-- JR Z,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00100000" =>
-			if Mode /= 2 then
-				-- JR NZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "11101001" =>
-			-- JP (HL)
-			JumpXY <= '1';
-		when "00010000" =>
-			if Mode = 3 then
-				I_DJNZ <= '1';
-			elsif Mode < 2 then
-				-- DJNZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					I_DJNZ <= '1';
-					Set_BusB_To <= "1010";
-					Set_BusA_To(2 downto 0) <= "000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					I_DJNZ <= '1';
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-
--- CALL AND RETURN GROUP
-		when "11001101" =>
-			-- CALL nn
-			MCycles <= "101";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				IncDec_16 <= "1111";
-				Inc_PC <= '1';
-				TStates <= "100";
-				Set_Addr_To <= aSP;
-				LDW <= '1';
-				Set_BusB_To <= "1101";
-			when 4 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 5 =>
-				Write <= '1';
-				Call <= '1';
-			when others => null;
-			end case;
-		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
-			if IR(5) = '0' or Mode /= 3 then
-				-- CALL cc,nn
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					LDW <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						IncDec_16 <= "1111";
-						Set_Addr_TO <= aSP;
-						TStates <= "100";
-						Set_BusB_To <= "1101";
-					else
-						MCycles <= "011";
-					end if;
-				when 4 =>
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 5 =>
-					Write <= '1';
-					Call <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11001001" =>
-			-- RET
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_TO <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				LDZ <= '1';
-			when 3 =>
-				Jump <= '1';
-				IncDec_16 <= "0111";
-			when others => null;
-			end case;
-		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+nn),A
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-						Set_BusB_To     <= "0111";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "01" =>
-					-- ADD SP,n
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						ALU_Op <= "0000";
-						Inc_PC <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_BusA_To <= "1000";
-						Set_BusB_To <= "0110";
-					when 3 =>
-						NoRead <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						ALU_Op <= "0001";
-						Set_BusA_To <= "1001";
-						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
-					when others =>
-					end case;
-				when "10" =>
-					-- LD A,($FF00+nn)
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-					when 3 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				when "11" =>
-					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
-					MCycles <= "101";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						LDW <= '1';
-					when 4 =>
-						Set_BusA_To(2 downto 0) <= "101"; -- L
-						Read_To_Reg <= '1';
-						Inc_WZ <= '1';
-						Set_Addr_To <= aZI;
-					when 5 =>
-						Set_BusA_To(2 downto 0) <= "100"; -- H
-						Read_To_Reg <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- RET cc
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Set_Addr_TO <= aSP;
-					else
-						MCycles <= "001";
-					end if;
-					TStates <= "101";
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-				when others => null;
-				end case;
-			end if;
-		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-			-- RST p
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1101";
-			when 2 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 3 =>
-				Write <= '1';
-				RstP <= '1';
-			when others => null;
-			end case;
-
--- INPUT AND OUTPUT GROUP
-		when "11011011" =>
-			if Mode /= 3 then
-				-- IN A,(n)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-				when 3 =>
-					Read_To_Acc <= '1';
-					IORQ <= '1';
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-				when others => null;
-				end case;
-			end if;
-		when "11010011" =>
-			if Mode /= 3 then
-				-- OUT (n),A
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-					Set_BusB_To <= "0111";
-				when 3 =>
-					Write <= '1';
-					IORQ <= '1';
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-				when others => null;
-				end case;
-			end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
-		when "11001011" =>
-			if Mode /= 2 then
-				Prefix <= "01";
-			end if;
-
-		when "11101101" =>
-			if Mode < 2 then
-				Prefix <= "10";
-			end if;
-
-		when "11011101"|"11111101" =>
-			if Mode < 2 then
-				Prefix <= "11";
-			end if;
-
-		end case;
-
-		when "01" =>
-
-------------------------------------------------------------------------------
---
---      CB prefixed instructions
---
-------------------------------------------------------------------------------
-
-			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
-			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-				-- RLC r
-				-- RL r
-				-- RRC r
-				-- RR r
-				-- SLA r
-				-- SRA r
-				-- SRL r
-				-- SLL r (Undocumented) / SWAP r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1000";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- R/S (IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1000";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-
-			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-				-- RLC (HL)
-				-- RL (HL)
-				-- RRC (HL)
-				-- RR (HL)
-				-- SRA (HL)
-				-- SRL (HL)
-				-- SLA (HL)
-				-- SLL (HL) (Undocumented) / SWAP (HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
-				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-				-- BIT b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-					  ALU_Op <= "1001";
-					end if;
-				else
-				-- BIT b,(IX+d), undocumented
-					MCycles <= "010";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1001";
-						TStates <= "100";
-					when others => null;
-					end case;
-				end if;
-			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-				-- BIT b,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1001";
-					TStates <= "100";
-				when others => null;
-				end case;
-			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-				-- SET b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1010";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- SET b,(IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1010";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-				-- SET b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-				-- RES b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1011";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- RES b,(IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1011";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-				
-			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-				-- RES b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end case;
-
-		when others =>
-
-------------------------------------------------------------------------------
---
---      ED prefixed instructions
---
-------------------------------------------------------------------------------
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
-				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
-				|                                            "10100100"|"10100101"|"10100110"|"10100111"
-				|                                            "10101100"|"10101101"|"10101110"|"10101111"
-				|                                            "10110100"|"10110101"|"10110110"|"10110111"
-				|                                            "10111100"|"10111101"|"10111110"|"10111111"
-				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
-				null; -- NOP, undocumented
-			when "01111110"|"01111111" =>
-				-- NOP, undocumented
-				null;
--- 8 BIT LOAD GROUP
-			when "01010111" =>
-				-- LD A,I
-				Special_LD <= "100";
-				TStates <= "101";
-			when "01011111" =>
-				-- LD A,R
-				Special_LD <= "101";
-				TStates <= "101";
-			when "01000111" =>
-				-- LD I,A
-				Special_LD <= "110";
-				TStates <= "101";
-			when "01001111" =>
-				-- LD R,A
-				Special_LD <= "111";
-				TStates <= "101";
--- 16 BIT LOAD GROUP
-			when "01001011"|"01011011"|"01101011"|"01111011" =>
-				-- LD dd,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1000";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '1';
-					end if;
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1001";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '0';
-					end if;
-				when others => null;
-				end case;
-			when "01000011"|"01010011"|"01100011"|"01110011" =>
-				-- LD (nn),dd
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1000";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1001";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10100000" | "10101000" | "10110000" | "10111000" =>
-				-- LDI, LDD, LDIR, LDDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0000";
-					Set_Addr_To <= aDE;
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- IX
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					I_BT <= '1';
-					TStates <= "101";
-					Write <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0101"; -- DE
-					else
-						IncDec_16 <= "1101";
-					end if;
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100001" | "10101001" | "10110001" | "10111001" =>
-				-- CPI, CPD, CPIR, CPDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0111";
-					Save_ALU <= '1';
-					PreserveC <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0110";
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					I_BC <= '1';
-					TStates <= "101";
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-				-- NEG
-				Alu_OP <= "0010";
-				Set_BusB_To <= "0111";
-				Set_BusA_To <= "1010";
-				Read_To_Acc <= '1';
-				Save_ALU <= '1';
-			when "01000110"|"01001110"|"01100110"|"01101110" =>
-				-- IM 0
-				IMode <= "00";
-			when "01010110"|"01110110" =>
-				-- IM 1
-				IMode <= "01";
-			when "01011110"|"01110111" =>
-				-- IM 2
-				IMode <= "10";
--- 16 bit arithmetic
-			when "01001010"|"01011010"|"01101010"|"01111010" =>
-				-- ADC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0001";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-						when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0001";
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-					when others =>
-						Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01000010"|"01010010"|"01100010"|"01110010" =>
-				-- SBC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-					when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					when others =>
-							Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01101111" =>
-				-- RLD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1101";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RLD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01100111" =>
-				-- RRD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1110";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RRD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-				-- RETI, RETN
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-				when others => null;
-				end case;
-			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-				-- IN r,(C)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					if IR(5 downto 3) /= "110" then
-						Read_To_Reg <= '1';
-						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
-					end if;
-					I_INRC <= '1';
-				when others =>
-				end case;
-			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-				-- OUT (C),r
-				-- OUT (C),0
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
-					if IR(5 downto 3) = "110" then
-						Set_BusB_To(3) <= '1';
-					end if;
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					Write <= '1';
-					IORQ <= '1';
-				when others =>
-				end case;
-			when "10100010" | "10101010" | "10110010" | "10111010" =>
-				-- INI, IND, INIR, INDR
-				-- note B is decremented AFTER being put on the bus
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aXY;
-				when 3 =>
-					if IR(3) = '0' then
-						--IncDec_16 <= "0010";
-						IncDec_16 <= "0110";
-					else
-						--IncDec_16 <= "1010";
-						IncDec_16 <= "1110";
-					end if;
-					TStates <= "100";
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100011" | "10101011" | "10110011" | "10111011" =>
-				-- OUTI, OUTD, OTIR, OTDR
-				-- note B is decremented BEFORE being put on the bus.
-				-- mikej fix for hl inc
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aBC;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- mikej
-					else
-						IncDec_16 <= "1110"; -- mikej
-					end if;
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end case;
-
-		end case;
-
-		if Mode = 1 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "011";
-			end if;
-		end if;
-
-		if Mode = 3 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "100";
-			end if;
-		end if;
-
-		if Mode < 2 then
-			if MCycle = "110" then
-				Inc_PC <= '1';
-				if Mode = 1 then
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-					Set_BusB_To(2 downto 0) <= SSS;
-					Set_BusB_To(3) <= '0';
-				end if;
-				if IRB = "00110110" or IRB = "11001011" then
-					Set_Addr_To <= aNone;
-				end if;
-			end if;
-			if MCycle = "111" then
-				if Mode = 0 then
-					TStates <= "101";
-				end if;
-				if ISet /= "01" then
-					Set_Addr_To <= aXY;
-				end if;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-				if IRB = "00110110" or ISet = "01" then
-					-- LD (HL),n
-					Inc_PC <= '1';
-				else
-					NoRead <= '1';
-				end if;
-			end if;
-		end if;
-
-	end process;
-
-end;
diff --git a/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/cpu/T80_Pack.vhd
deleted file mode 100644
index 6904b66b..00000000
--- a/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/cpu/T80_Pack.vhd	
+++ /dev/null
@@ -1,220 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
-	component T80
-	generic(
-		Mode : integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		RESET_n         : in std_logic;
-		CLK_n           : in std_logic;
-		CEN                     : in std_logic;
-		WAIT_n          : in std_logic;
-		INT_n           : in std_logic;
-		NMI_n           : in std_logic;
-		BUSRQ_n         : in std_logic;
-		M1_n            : out std_logic;
-		IORQ            : out std_logic;
-		NoRead          : out std_logic;
-		Write           : out std_logic;
-		RFSH_n          : out std_logic;
-		HALT_n          : out std_logic;
-		BUSAK_n         : out std_logic;
-		A                       : out std_logic_vector(15 downto 0);
-		DInst           : in std_logic_vector(7 downto 0);
-		DI                      : in std_logic_vector(7 downto 0);
-		DO                      : out std_logic_vector(7 downto 0);
-		MC                      : out std_logic_vector(2 downto 0);
-		TS                      : out std_logic_vector(2 downto 0);
-		IntCycle_n      : out std_logic;
-		IntE            : out std_logic;
-		Stop            : out std_logic
-	);
-	end component;
-
-	component T80_Reg
-	port(
-		Clk                     : in std_logic;
-		CEN                     : in std_logic;
-		WEH                     : in std_logic;
-		WEL                     : in std_logic;
-		AddrA           : in std_logic_vector(2 downto 0);
-		AddrB           : in std_logic_vector(2 downto 0);
-		AddrC           : in std_logic_vector(2 downto 0);
-		DIH                     : in std_logic_vector(7 downto 0);
-		DIL                     : in std_logic_vector(7 downto 0);
-		DOAH            : out std_logic_vector(7 downto 0);
-		DOAL            : out std_logic_vector(7 downto 0);
-		DOBH            : out std_logic_vector(7 downto 0);
-		DOBL            : out std_logic_vector(7 downto 0);
-		DOCH            : out std_logic_vector(7 downto 0);
-		DOCL            : out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-	component T80_MCode
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR                      : in  std_logic_vector(7 downto 0);
-		ISet                    : in  std_logic_vector(1 downto 0);
-		MCycle                  : in  std_logic_vector(2 downto 0);
-		F                       : in  std_logic_vector(7 downto 0);
-		NMICycle                : in  std_logic;
-		IntCycle                : in  std_logic;
-		XY_State                : in  std_logic_vector(1 downto 0);
-		MCycles                 : out std_logic_vector(2 downto 0);
-		TStates                 : out std_logic_vector(2 downto 0);
-		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC                  : out std_logic;
-		Inc_WZ                  : out std_logic;
-		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg             : out std_logic;
-		Read_To_Acc             : out std_logic;
-		Set_BusA_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op                  : out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU                : out std_logic;
-		PreserveC               : out std_logic;
-		Arith16                 : out std_logic;
-		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ                    : out std_logic;
-		Jump                    : out std_logic;
-		JumpE                   : out std_logic;
-		JumpXY                  : out std_logic;
-		Call                    : out std_logic;
-		RstP                    : out std_logic;
-		LDZ                     : out std_logic;
-		LDW                     : out std_logic;
-		LDSPHL                  : out std_logic;
-		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH              : out std_logic;
-		ExchangeRp              : out std_logic;
-		ExchangeAF              : out std_logic;
-		ExchangeRS              : out std_logic;
-		I_DJNZ                  : out std_logic;
-		I_CPL                   : out std_logic;
-		I_CCF                   : out std_logic;
-		I_SCF                   : out std_logic;
-		I_RETN                  : out std_logic;
-		I_BT                    : out std_logic;
-		I_BC                    : out std_logic;
-		I_BTR                   : out std_logic;
-		I_RLD                   : out std_logic;
-		I_RRD                   : out std_logic;
-		I_INRC                  : out std_logic;
-		SetDI                   : out std_logic;
-		SetEI                   : out std_logic;
-		IMode                   : out std_logic_vector(1 downto 0);
-		Halt                    : out std_logic;
-		NoRead                  : out std_logic;
-		Write                   : out std_logic;
-		XYbit_undoc             : out std_logic
-	);
-	end component;
-
-	component T80_ALU
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16         : in  std_logic;
-		Z16             : in  std_logic;
-		ALU_Op          : in  std_logic_vector(3 downto 0);
-		IR              : in  std_logic_vector(5 downto 0);
-		ISet            : in  std_logic_vector(1 downto 0);
-		BusA            : in  std_logic_vector(7 downto 0);
-		BusB            : in  std_logic_vector(7 downto 0);
-		F_In            : in  std_logic_vector(7 downto 0);
-		Q               : out std_logic_vector(7 downto 0);
-		F_Out           : out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-end;
diff --git a/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/cpu/T80_Reg.vhd
deleted file mode 100644
index 998033ef..00000000
--- a/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/cpu/T80_Reg.vhd	
+++ /dev/null
@@ -1,114 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
---      0242 : Initial release
---
---      0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
-  port(
-    Clk   : in  std_logic;
-    CEN   : in  std_logic;
-    WEH   : in  std_logic;
-    WEL   : in  std_logic;
-    AddrA : in  std_logic_vector(2 downto 0);
-    AddrB : in  std_logic_vector(2 downto 0);
-    AddrC : in  std_logic_vector(2 downto 0);
-    DIH   : in  std_logic_vector(7 downto 0);
-    DIL   : in  std_logic_vector(7 downto 0);
-    DOAH  : out std_logic_vector(7 downto 0);
-    DOAL  : out std_logic_vector(7 downto 0);
-    DOBH  : out std_logic_vector(7 downto 0);
-    DOBL  : out std_logic_vector(7 downto 0);
-    DOCH  : out std_logic_vector(7 downto 0);
-    DOCL  : out std_logic_vector(7 downto 0)
-    );
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
-  type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
-  signal      RegsH   : Register_Image(0 to 7);
-  signal      RegsL   : Register_Image(0 to 7);
-
-begin
-
-  process (Clk)
-  begin
-    if Clk'event and Clk = '1' then
-      if CEN = '1' then
-        if WEH = '1' then
-          RegsH(to_integer(unsigned(AddrA))) <= DIH;
-        end if;
-        if WEL = '1' then
-          RegsL(to_integer(unsigned(AddrA))) <= DIL;
-        end if;
-      end if;
-    end if;
-  end process;
-
-  DOAH <= RegsH(to_integer(unsigned(AddrA)));
-  DOAL <= RegsL(to_integer(unsigned(AddrA)));
-  DOBH <= RegsH(to_integer(unsigned(AddrB)));
-  DOBL <= RegsL(to_integer(unsigned(AddrB)));
-  DOCH <= RegsH(to_integer(unsigned(AddrC)));
-  DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
diff --git a/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/cpu/T80a.vhd b/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/cpu/T80a.vhd
deleted file mode 100644
index 33d61068..00000000
--- a/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/cpu/T80a.vhd	
+++ /dev/null
@@ -1,280 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core, asynchronous top level
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0211 : Fixed interrupt cycle
---
---      0235 : Updated for T80 interface change
---
---      0238 : Updated for T80 interface change
---
---      0240 : Updated for T80 interface change
---
---      0242 : Updated for T80 interface change
---
---      0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80a is
-  generic(
-    Mode : integer := 0     -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-    );
-  port(
-    RESET_n    : in  std_logic;
-    CLK_n      : in  std_logic;
-    CLK_EN_SYS : in  std_logic;
-    WAIT_n     : in  std_logic;
-    INT_n      : in  std_logic;
-    NMI_n      : in  std_logic;
-    BUSRQ_n    : in  std_logic;
-    M1_n       : out std_logic;
-    MREQ_n     : out std_logic;
-    IORQ_n     : out std_logic;
-    RD_n       : out std_logic;
-    WR_n       : out std_logic;
-    RFSH_n     : out std_logic;
-    HALT_n     : out std_logic;
-    BUSAK_n    : out std_logic;
-    A          : out std_logic_vector(15 downto 0);
-		DI						: in  std_logic_vector(7 downto 0);
-		DO						: out std_logic_vector(7 downto 0)
-    );
-end T80a;
-
-architecture rtl of T80a is
-
-  signal CEN          : std_logic;
-  signal Reset_s      : std_logic;
-  signal IntCycle_n   : std_logic;
-  signal IORQ         : std_logic;
-  signal NoRead       : std_logic;
-  signal Write        : std_logic;
-  signal MREQ         : std_logic;
-  signal MReq_Inhibit : std_logic;
-  signal Req_Inhibit  : std_logic;
-  signal RD           : std_logic;
-  signal MREQ_n_i     : std_logic;
-  signal IORQ_n_i     : std_logic;
-  signal RD_n_i       : std_logic;
-  signal WR_n_i       : std_logic;
-  signal RFSH_n_i     : std_logic;
-  signal BUSAK_n_i    : std_logic;
-  signal A_i          : std_logic_vector(15 downto 0);
-	signal DO_Reg			: std_logic_vector(7 downto 0);
-  signal DI_Reg       : std_logic_vector (7 downto 0);  -- Input synchroniser
-  signal Wait_s       : std_logic;
-  signal MCycle       : std_logic_vector(2 downto 0);
-  signal TState       : std_logic_vector(2 downto 0);
-
-begin
-
-  -- clock enable supplied from clocking system
-  CEN <= CLK_EN_SYS;
-
-  BUSAK_n <= BUSAK_n_i;
-  MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
-  RD_n_i <= not RD or Req_Inhibit;
-
-  MREQ_n <= MREQ_n_i;
-  IORQ_n <= IORQ_n_i;
-  RD_n <= RD_n_i;
-  WR_n <= WR_n_i;
-  RFSH_n <= RFSH_n_i;
-  A <= A_i;
-	DO <= DO_Reg;
-
---   process (RESET_n, CLK_n)
---   begin
---     if RESET_n = '0' then
---       Reset_s <= '0';
---     elsif CLK_n'event and CLK_n = '1' then
---       Reset_s <= '1';
---     end if;
---   end process;
-  -- T80 reset input has already proper characteristics:
-  --   * asynchronous assertion
-  --   * deassertion synchronous to CLK_n (main_clk)
-  Reset_s <= RESET_n;
-
-  u0 : T80
-    generic map(
-      Mode       => Mode,
-      IOWait     => 1)
-    port map(
-      CEN        => CEN,
-      M1_n       => M1_n,
-      IORQ       => IORQ,
-      NoRead     => NoRead,
-      Write      => Write,
-      RFSH_n     => RFSH_n_i,
-      HALT_n     => HALT_n,
-      WAIT_n     => Wait_s,
-      INT_n      => INT_n,
-      NMI_n      => NMI_n,
-      RESET_n    => Reset_s,
-      BUSRQ_n    => BUSRQ_n,
-      BUSAK_n    => BUSAK_n_i,
-      CLK_n      => CLK_n,
-      A          => A_i,
-			DInst => DI,
-      DI         => DI_Reg,
-			DO => DO_Reg,
-      MC         => MCycle,
-      TS         => TState,
-      IntCycle_n => IntCycle_n);
-
-  process (CLK_n)
-  begin
-    if CLK_n'event and CLK_n = '0' then
-      if CEN = '1' then
-        Wait_s <= WAIT_n;
-        if TState = "011" and BUSAK_n_i = '1' then
-					DI_Reg <= to_x01(DI);
-        end if;
-      end if;
-    end if;
-  end process;
-
-  process (Reset_s,CLK_n)
-  begin
-    if Reset_s = '0' then
-      WR_n_i <= '1';
-    elsif CLK_n'event and CLK_n = '1' then
-      if CEN = '1' then
-        WR_n_i <= '1';
-        if TState = "001" then      -- To short for IO writes !!!!!!!!!!!!!!!!!!!
-          WR_n_i <= not Write;
-        end if;
-      end if;
-    end if;
-  end process;
-
-  process (Reset_s,CLK_n)
-  begin
-    if Reset_s = '0' then
-      Req_Inhibit <= '0';
-    elsif CLK_n'event and CLK_n = '1' then
-      if CEN = '1' then
-        if MCycle = "001" and TState = "010" then
-          Req_Inhibit <= '1';
-        else
-          Req_Inhibit <= '0';
-        end if;
-      end if;
-    end if;
-  end process;
-
-  process (Reset_s,CLK_n)
-  begin
-    if Reset_s = '0' then
-      MReq_Inhibit <= '0';
-    elsif CLK_n'event and CLK_n = '0' then
-      if CEN = '1' then
-        if MCycle = "001" and TState = "010" then
-          MReq_Inhibit <= '1';
-        else
-          MReq_Inhibit <= '0';
-        end if;
-      end if;
-    end if;
-  end process;
-
-  process(Reset_s,CLK_n)
-  begin
-    if Reset_s = '0' then
-      RD <= '0';
-      IORQ_n_i <= '1';
-      MREQ <= '0';
-    elsif CLK_n'event and CLK_n = '0' then
-      if CEN = '1' then
-
-        if MCycle = "001" then
-          if TState = "001" then
-            RD <= IntCycle_n;
-            MREQ <= IntCycle_n;
-            IORQ_n_i <= IntCycle_n;
-          end if;
-          if TState = "011" then
-            RD <= '0';
-            IORQ_n_i <= '1';
-            MREQ <= '1';
-          end if;
-          if TState = "100" then
-            MREQ <= '0';
-          end if;
-        else
-          if TState = "001" and NoRead = '0' then
-            RD <= not Write;
-            IORQ_n_i <= not IORQ;
-            MREQ <= not IORQ;
-          end if;
-          if TState = "011" then
-            RD <= '0';
-            IORQ_n_i <= '1';
-            MREQ <= '0';
-          end if;
-        end if;
-
-      end if;
-    end if;
-  end process;
-
-end;
diff --git a/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug.vhd b/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug.vhd
index a1a186fe..fe4f652a 100644
--- a/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug.vhd	
+++ b/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug.vhd	
@@ -65,7 +65,7 @@ port (
 	O_PIXCE      : out std_logic;
 
 	-- Audio Interface --------------------------------------------------------
-	O_AUDIO      : out signed(7 downto 0);
+	O_AUDIO      : out std_logic_vector( 8 downto 0);
 	
 	but_coin_s   : in  std_logic_vector( 1 downto 0);
 	but_fire_s   : in  std_logic_vector( 1 downto 0);
@@ -160,8 +160,8 @@ begin
 		rgb_b_o           => O_VIDEO_B,
 		hsync_n_o         => O_HSYNC,
 		vsync_n_o         => O_VSYNC,
-	   vblank_o          => O_VBLANK,
-	   hblank_o          => O_HBLANK,
+		vblank_o          => O_VBLANK,
+		hblank_o          => O_HBLANK,
 		audio_o           => O_AUDIO,
 		rom_cpu_a_o       => rom_cpu_a_s,
 		rom_cpu_d_i       => rom_cpu_d_s,
diff --git a/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_cpu_unit.vhd b/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_cpu_unit.vhd
index 7d41074f..5646437b 100644
--- a/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_cpu_unit.vhd	
+++ b/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_cpu_unit.vhd	
@@ -119,14 +119,14 @@ begin
   -- "wait" has to be modelled with the clock enable because the T80 is not
   -- able to enlarge write accesses properly when they are delayed with "wait"
   t80_clk_en_s <= clk_en_4mhz_i and wait_n_s;
-  T80a_b : entity work.T80a
+  T80a_b : entity work.T80s
     generic map (
       Mode => 0
     )
     port map (
       RESET_n    => res_n_i,
-      CLK_n      => clk_20mhz_i,
-      CLK_EN_SYS => t80_clk_en_s,
+      CLK        => clk_20mhz_i,
+      CEN        => t80_clk_en_s,
       WAIT_n     => wait_n_s,
       INT_n      => int_n_s,
       NMI_n      => nmi_n_s,
diff --git a/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_machine.vhd b/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_machine.vhd
index 584b8391..dbe5d75b 100644
--- a/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_machine.vhd	
+++ b/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_machine.vhd	
@@ -77,10 +77,10 @@ entity ladybug_machine is
     hsync_n_o         : out std_logic;
     vsync_n_o         : out std_logic;
     comp_sync_n_o     : out std_logic;
-	 vblank_o          : out std_logic;
-	 hblank_o          : out std_logic;
+    vblank_o          : out std_logic;
+    hblank_o          : out std_logic;
     -- Audio Interface --------------------------------------------------------
-    audio_o           : out signed( 7 downto 0);
+    audio_o           : out std_logic_vector( 8 downto 0);
     -- CPU ROM Interface ------------------------------------------------------
     rom_cpu_a_o       : out std_logic_vector(14 downto 0);
     rom_cpu_d_i       : in  std_logic_vector( 7 downto 0);
diff --git a/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/sound/ladybug_sound_unit.vhd b/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_sound_unit.vhd
similarity index 88%
rename from Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/sound/ladybug_sound_unit.vhd
rename to Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_sound_unit.vhd
index 23ad2a6a..8fe04ba8 100644
--- a/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/sound/ladybug_sound_unit.vhd	
+++ b/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_sound_unit.vhd	
@@ -59,7 +59,7 @@ entity ladybug_sound_unit is
     wr_n_i         : in  std_logic;
     d_from_cpu_i   : in  std_logic_vector(7 downto 0);
     sound_wait_n_o : out std_logic;
-    audio_o        : out signed(7 downto 0)
+    audio_o        : out std_logic_vector(8 downto 0)
   );
 
 end ladybug_sound_unit;
@@ -70,7 +70,7 @@ architecture struct of ladybug_sound_unit is
          ready_c1_s  : std_logic;
 
   signal aout_b1_s,
-         aout_c1_s   : signed(7 downto 0);
+         aout_c1_s   : std_logic_vector(7 downto 0);
 
 begin
 
@@ -117,23 +117,7 @@ begin
   --
   -- Purpose:
   --   Mix the digital audio of the two SN76489 instances.
-  --   Additional care is taken to avoid audio overfow/clipping.
-  --
-  mix: process (aout_b1_s,
-                aout_c1_s)
-    variable sum_v : signed(8 downto 0);
-  begin
-    sum_v := RESIZE(aout_b1_s, 9) + RESIZE(aout_c1_s, 9);
-
-    if sum_v > 127 then
-      audio_o <= to_signed(127, 8);
-    elsif sum_v < -128 then
-      audio_o <= to_signed(-128, 8);
-    else
-      audio_o <= RESIZE(sum_v, 8);
-    end if;
-
-  end process mix;
+  audio_o <= std_logic_vector(unsigned('0'&aout_b1_s) + unsigned('0'&aout_c1_s));
   -- 
   -----------------------------------------------------------------------------
 
diff --git a/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/COPYING b/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/COPYING
deleted file mode 100644
index 60549be5..00000000
--- a/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/COPYING	
+++ /dev/null
@@ -1,340 +0,0 @@
-		    GNU GENERAL PUBLIC LICENSE
-		       Version 2, June 1991
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- Copyright (C) 1989, 1991 Free Software Foundation, Inc.
-                       59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- Everyone is permitted to copy and distribute verbatim copies
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diff --git a/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/README b/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/README
deleted file mode 100644
index 33630144..00000000
--- a/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/README	
+++ /dev/null
@@ -1,143 +0,0 @@
-
-An SN76489AN Compatible Implementation in VHDL
-==============================================
-Version: $Date: 2006/06/18 19:28:40 $
-
-Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
-See the file COPYING.
-
-
-Integration
------------
-
-The sn76489 design exhibits all interface signals as the original chip. It
-only differs in the audio data output which is provided as an 8 bit signed
-vector instead of an analog output pin.
-
-  generic (
-    clock_div_16_g : integer := 1
-    -- Set to '1' when operating the design in SN76489 mode. The primary clock
-    -- input is divided by 16 in this variant. The data sheet mentions the
-    -- SN76494 which contains a divide-by-2 clock input stage. Set the generic
-    -- to '0' to enable this mode.
-  );
-  port (
-    clock_i    : in  std_logic;
-    -- Primary clock input
-    -- Drive with the target frequency or any integer multiple of it.
-
-    clock_en_i : in  std_logic;
-    -- Clock enable
-    -- A '1' on this input qualifies a valid rising edge on clock_i. A '0'
-    -- disables the next rising clock edge, effectivley halting the design
-    -- until the next enabled rising clock edge.
-    -- Can be used to run the core at lower frequencies than applied on
-    -- clock_i.
-
-    res_n_i    : in  std_logic;
-    -- Asynchronous low active reset input.
-    -- Sets all sequential elements to a known state.
-
-    ce_n_i     : in  std_logic;
-    -- Chip enable, low active.
-
-    we_n_i     : in  std_logic;
-    -- Write enable, low active.
-
-    ready_o    : out std_logic;
-    -- Ready indication to microprocessor.
-
-    d_i        : in  std_logic_vector(0 to 7);
-    -- Data input
-    -- MSB 0 ... 7 LSB
-
-    aout_o     : out signed(0 to 7)
-    -- Audio output, signed vector
-    -- MSB/SIGN 0 ... 7 LSB
-  );
-
-
-Both 8 bit vector ports are defined (0 to 7) which declares bit 0 to be the
-MSB and bit 7 to be the LSB. This has been implemented according to TI's data
-sheet, thus all register/data format figures apply 1:1 for this design.
-Many systems will flip the system data bus bit wise before it is connected to
-this PSG. This is simply achieved with the following VHDL construct:
-
-  signal data_s : std_logic_vector(7 downto 0);
-
-  ...
-  d_i => data_s,
-  ...
-
-d_i and data_s will be assigned from left to right, resulting in the expected
-bit assignment:
-
-  d_i    data_s
-   0       7
-   1       6
-      ...
-   6       1
-   7       0
-
-
-As this design is fully synchronous, care has to be taken when the design
-replaces an SN76489 in asynchronous mode. No problems are expected when
-interfacing the code to other synchronous components.
-
-
-Design Hierarchy
-----------------
-
-  sn76489_top
-    |
-    +-- sn76489_latch_ctrl
-    |
-    +-- sn76489_clock_div
-    |
-    +-- sn76489_tone
-    |     |
-    |     \-- sn76489_attentuator
-    |
-    +-- sn76489_tone
-    |     |
-    |     \-- sn76489_attentuator
-    |
-    +-- sn76489_tone
-    |     |
-    |     \-- sn76489_attentuator
-    |
-    \-- sn76489_noise
-          |
-          \-- sn76489_attentuator
-
-Resulting compilation sequence:
-
-  sn76489_comp_pack-p.vhd
-  sn76489_top.vhd
-  sn76489_latch_ctrl.vhd
-  sn76489_latch_ctrl-c.vhd
-  sn76489_clock_div.vhd
-  sn76489_clock_div-c.vhd
-  sn76489_attenuator.vhd
-  sn76489_attenuator-c.vhd
-  sn76489_tone.vhd
-  sn76489_tone-c.vhd
-  sn76489_noise.vhd
-  sn76489_noise-c.vhd
-  sn76489_top-c.vhd
-
-Skip the files containing VHDL configurations when analyzing the code for
-synthesis.
-
-
-References
-----------
-
-* TI Data sheet SN76489.pdf
-  ftp://ftp.whtech.com/datasheets%20&%20manuals/SN76489.pdf
-
-* John Kortink's article on the SN76489:
-  http://web.inter.nl.net/users/J.Kortink/home/articles/sn76489/
-
-* Maxim's "SN76489 notes" in
-  http://www.smspower.org/maxim/docs/SN76489.txt
diff --git a/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/sn76489_attenuator.vhd b/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/sn76489_attenuator.vhd
deleted file mode 100644
index 444064e5..00000000
--- a/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/sn76489_attenuator.vhd	
+++ /dev/null
@@ -1,114 +0,0 @@
--------------------------------------------------------------------------------
---
--- Synthesizable model of TI's SN76489AN.
---
--- $Id: sn76489_attenuator.vhd,v 1.7 2006/02/27 20:30:10 arnim Exp $
---
--- Attenuator Module
---
--------------------------------------------------------------------------------
---
--- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity sn76489_attenuator is
-
-  port (
-    attenuation_i : in  std_logic_vector(0 to 3);
-    factor_i      : in  signed(0 to 1);
-    product_o     : out signed(0 to 7)
-  );
-
-end sn76489_attenuator;
-
-
-architecture rtl of sn76489_attenuator is
-
-begin
-
-  -----------------------------------------------------------------------------
-  -- Process attenuate
-  --
-  -- Purpose:
-  --   Determine the attenuation and generate the resulting product.
-  --
-  --   The maximum attenuation value is 31 which corresponds to volume off.
-  --   As described in the data sheet, the maximum "playing" attenuation is
-  --     28 = 16 + 8 + 4
-  --
-  --   The table for the volume constants is derived from the following
-  --   formula (each step is 2dB voltage):
-  --     v(0)   = 31
-  --     v(n+1) = v(n) * 0.79432823
-  --
-  attenuate: process (attenuation_i,
-                      factor_i)
-
-    type     volume_t is array (natural range 0 to 15) of natural;
-    constant volume_c : volume_t :=
-      (31, 25, 20, 16, 12, 10, 8, 6, 5, 4, 3, 2, 2, 2, 1, 0);
-
-    variable attenuation_v  : unsigned(attenuation_i'range);
-    variable volume_v       : signed(product_o'range);
-
-  begin
-
-    attenuation_v := unsigned(attenuation_i);
-
-    -- volume look-up table
-    volume_v := to_signed(volume_c(to_integer(attenuation_v)),
-                          product_o'length);
-
-    -- this replaces a multiplier and consumes a bit fewer
-    -- resources
-    case to_integer(factor_i) is
-      when +1 =>
-        product_o <= volume_v;
-      when -1 =>
-        product_o <= -volume_v;
-      when others =>
-        product_o <= (others => '0');
-    end case;
-
-  end process attenuate;
-  --
-  -----------------------------------------------------------------------------
-
-end rtl;
diff --git a/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/sn76489_clock_div.vhd b/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/sn76489_clock_div.vhd
deleted file mode 100644
index eab86beb..00000000
--- a/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/sn76489_clock_div.vhd	
+++ /dev/null
@@ -1,134 +0,0 @@
--------------------------------------------------------------------------------
---
--- Synthesizable model of TI's SN76489AN.
---
--- $Id: sn76489_clock_div.vhd,v 1.4 2005/10/10 21:51:27 arnim Exp $
---
--- Clock Divider Circuit
---
--------------------------------------------------------------------------------
---
--- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity sn76489_clock_div is
-
-  generic (
-    clock_div_16_g : integer := 1
-  );
-  port (
-    clock_i    : in  std_logic;
-    clock_en_i : in  std_logic;
-    res_n_i    : in  std_logic;
-    clk_en_o   : out boolean
-  );
-
-end sn76489_clock_div;
-
-
-library ieee;
-use ieee.numeric_std.all;
-
-architecture rtl of sn76489_clock_div is
-
-  signal cnt_s,
-         cnt_q  : unsigned(3 downto 0);
-
-begin
-
-  -----------------------------------------------------------------------------
-  -- Process seq
-  --
-  -- Purpose:
-  --   Implements the sequential counter element.
-  --
-  seq: process (clock_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      cnt_q <= (others => '0');
-    elsif clock_i'event and clock_i = '1' then
-      cnt_q <= cnt_s;
-    end if;
-  end process seq;
-  --
-  -----------------------------------------------------------------------------
-
-
-  -----------------------------------------------------------------------------
-  -- Process comb
-  --
-  -- Purpose:
-  --   Implements the combinational counter logic.
-  --
-  comb: process (clock_en_i,
-                 cnt_q)
-  begin
-    -- default assignments
-    cnt_s    <= cnt_q;
-    clk_en_o <= false;
-
-    if clock_en_i = '1' then
-
-      if cnt_q = 0 then
-        clk_en_o <= true;
-
-        if clock_div_16_g = 1 then
-          cnt_s  <= to_unsigned(15, cnt_q'length);
-        elsif clock_div_16_g = 0 then
-          cnt_s  <= to_unsigned( 1, cnt_q'length);
-        else
-          -- pragma translate_off
-          assert false
-            report "Generic clock_div_16_g must be either 0 or 1."
-            severity failure;
-          -- pragma translate_on
-        end if;
-
-      else
-        cnt_s    <= cnt_q - 1;
-
-      end if;
-
-    end if;
-
-  end process comb;
-  --
-  -----------------------------------------------------------------------------
-
-end rtl;
diff --git a/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/sn76489_latch_ctrl.vhd b/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/sn76489_latch_ctrl.vhd
deleted file mode 100644
index 789720c2..00000000
--- a/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/sn76489_latch_ctrl.vhd	
+++ /dev/null
@@ -1,138 +0,0 @@
--------------------------------------------------------------------------------
---
--- Synthesizable model of TI's SN76489AN.
---
--- $Id: sn76489_latch_ctrl.vhd,v 1.6 2006/02/27 20:30:10 arnim Exp $
---
--- Latch Control Unit
---
--------------------------------------------------------------------------------
---
--- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity sn76489_latch_ctrl is
-
-  port (
-    clock_i    : in  std_logic;
-    clk_en_i   : in  boolean;
-    res_n_i    : in  std_logic;
-    ce_n_i     : in  std_logic;
-    we_n_i     : in  std_logic;
-    d_i        : in  std_logic_vector(0 to 7);
-    ready_o    : out std_logic;
-    tone1_we_o : out boolean;
-    tone2_we_o : out boolean;
-    tone3_we_o : out boolean;
-    noise_we_o : out boolean;
-    r2_o       : out std_logic
-  );
-
-end sn76489_latch_ctrl;
-
-
-library ieee;
-use ieee.numeric_std.all;
-
-architecture rtl of sn76489_latch_ctrl is
-
-  signal reg_q   : std_logic_vector(0 to 2);
-  signal we_q    : boolean;
-  signal ready_q : std_logic;
-
-begin
-
-  -----------------------------------------------------------------------------
-  -- Process seq
-  --
-  -- Purpose:
-  --   Implements the sequential elements.
-  --
-  seq: process (clock_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      reg_q     <= (others => '0');
-      we_q      <= false;
-      ready_q   <= '0';
-
-    elsif clock_i'event and clock_i = '1' then
-      -- READY Flag Output ----------------------------------------------------
-      if ready_q = '0' and we_q then
-        if clk_en_i then
-          -- assert READY when write access happened
-          ready_q <= '1';
-        end if;
-      elsif ce_n_i = '1' then
-        -- deassert READY when access has finished
-        ready_q <= '0';
-      end if;
-
-      -- Register Selection ---------------------------------------------------
-      if ce_n_i = '0' and we_n_i = '0' then
-        if clk_en_i then
-          if d_i(0) = '1' then
-            reg_q <= d_i(1 to 3);
-          end if;
-          we_q  <= true;
-        end if;
-      else
-        we_q  <= false;
-      end if;
-
-    end if;
-  end process seq;
-  --
-  -----------------------------------------------------------------------------
-
-
-  -----------------------------------------------------------------------------
-  -- Output mapping
-  -----------------------------------------------------------------------------
-  tone1_we_o <= reg_q(0 to 1) = "00" and we_q;
-  tone2_we_o <= reg_q(0 to 1) = "01" and we_q;
-  tone3_we_o <= reg_q(0 to 1) = "10" and we_q;
-  noise_we_o <= reg_q(0 to 1) = "11" and we_q;
-
-  r2_o       <= reg_q(2);
-
-  ready_o    <=   ready_q
-                when ce_n_i = '0' else
-                  '1';
-
-end rtl;
diff --git a/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/sn76489_noise.vhd b/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/sn76489_noise.vhd
deleted file mode 100644
index 688bdd56..00000000
--- a/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/sn76489_noise.vhd	
+++ /dev/null
@@ -1,278 +0,0 @@
--------------------------------------------------------------------------------
---
--- Synthesizable model of TI's SN76489AN.
---
--- $Id: sn76489_noise.vhd,v 1.6 2006/02/27 20:30:10 arnim Exp $
---
--- Noise Generator
---
--------------------------------------------------------------------------------
---
--- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity sn76489_noise is
-
-  port (
-    clock_i    : in  std_logic;
-    clk_en_i   : in  boolean;
-    res_n_i    : in  std_logic;
-    we_i       : in  boolean;
-    d_i        : in  std_logic_vector(0 to 7);
-    r2_i       : in  std_logic;
-    tone3_ff_i : in  std_logic;
-    noise_o    : out signed(0 to 7)
-  );
-
-end sn76489_noise;
-
-architecture rtl of sn76489_noise is
-
-  signal nf_q       : std_logic_vector(0 to 1);
-  signal fb_q       : std_logic;
-  signal a_q        : std_logic_vector(0 to 3);
-  signal freq_cnt_q : unsigned(0 to 6);
-  signal freq_ff_q  : std_logic;
-
-  signal shift_source_s,
-         shift_source_q    : std_logic;
-  signal shift_rise_edge_s : boolean;
-
-  signal lfsr_q            : std_logic_vector(0 to 15);
-
-  signal freq_s      : signed(0 to 1);
-
-begin
-
-  -----------------------------------------------------------------------------
-  -- Process cpu_regs
-  --
-  -- Purpose:
-  --   Implements the registers writable by the CPU.
-  --
-  cpu_regs: process (clock_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      nf_q <= (others => '0');
-      fb_q <= '0';
-      a_q  <= (others => '1');
-
-    elsif clock_i'event and clock_i = '1' then
-      if clk_en_i and we_i then
-        if r2_i = '0' then
-          -- access to control register
-          -- both access types can write to the control register!
-          nf_q <= d_i(6 to 7);
-          fb_q <= d_i(5);
-
-        else
-          -- access to attenuator register
-          -- both access types can write to the attenuator register!
-          a_q <= d_i(4 to 7);
-
-        end if;
-      end if;
-    end if;
-  end process cpu_regs;
-  --
-  -----------------------------------------------------------------------------
-
-
-  -----------------------------------------------------------------------------
-  -- Process freq_gen
-  --
-  -- Purpose:
-  --   Implements the frequency generation components.
-  --
-  freq_gen: process (clock_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      freq_cnt_q <= (others => '0');
-      freq_ff_q  <= '0';
-
-    elsif clock_i'event and clock_i = '1' then
-      if clk_en_i then
-        if freq_cnt_q = 0 then
-          -- reload frequency counter according to NF setting
-          case nf_q is
-            when "00" =>
-              freq_cnt_q <= to_unsigned(16 * 2 - 1, freq_cnt_q'length);
-            when "01" =>
-              freq_cnt_q <= to_unsigned(16 * 4 - 1, freq_cnt_q'length);
-            when "10" =>
-              freq_cnt_q <= to_unsigned(16 * 8 - 1, freq_cnt_q'length);
-            when others =>
-              null;
-          end case;
-
-          freq_ff_q <= not freq_ff_q;
-
-        else
-          -- decrement frequency counter
-          freq_cnt_q <= freq_cnt_q - 1;
-
-        end if;
-
-      end if;
-    end if;
-  end process freq_gen;
-  --
-  -----------------------------------------------------------------------------
-
-
-  -----------------------------------------------------------------------------
-  -- Multiplex the source of the LFSR's shift enable
-  -----------------------------------------------------------------------------
-  shift_source_s <=   tone3_ff_i
-                    when nf_q = "11" else
-                      freq_ff_q;
-
-  -----------------------------------------------------------------------------
-  -- Process rise_edge
-  --
-  -- Purpose:
-  --   Detect the rising edge of the selected LFSR shift source.
-  --
-  rise_edge: process (clock_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      shift_source_q <= '0';
-
-    elsif clock_i'event and clock_i = '1' then
-      if clk_en_i then
-        shift_source_q <= shift_source_s;
-      end if;
-    end if;
-  end process rise_edge;
-  --
-  -----------------------------------------------------------------------------
-
-  -- detect rising edge on shift source
-  shift_rise_edge_s <= shift_source_q = '0' and shift_source_s = '1';
-
-
-  -----------------------------------------------------------------------------
-  -- Process lfsr
-  --
-  -- Purpose:
-  --   Implements the LFSR that generates noise.
-  --   Note: This implementation shifts the register right, i.e. from index
-  --         15 towards 0 => bit 15 is the input, bit 0 is the output
-  --
-  --   Tapped bits according to MAME's sn76496.c, implemented in function
-  --   lfsr_tapped_f.
-  --
-  lfsr: process (clock_i, res_n_i)
-
-    function lfsr_tapped_f(lfsr : in std_logic_vector) return std_logic is
-      constant tapped_bits_c : std_logic_vector(0 to 15)
-        -- tapped bits are 0, 2, 15
-        := "1010000000000001";
-      variable parity_v : std_logic;
-    begin
-      parity_v := '0';
-
-      for idx in lfsr'low to lfsr'high loop
-        parity_v := parity_v xor (lfsr(idx) and tapped_bits_c(idx));
-      end loop;
-
-      return parity_v;
-    end;
-
-  begin
-    if res_n_i = '0' then
-      -- reset LFSR to "0000000000000001"
-      lfsr_q               <= (others => '0');
-      lfsr_q(lfsr_q'right) <= '1';
-
-    elsif clock_i'event and clock_i = '1' then
-      if clk_en_i then
-        if we_i and r2_i = '0' then
-          -- write to noise register
-          -- -> reset LFSR
-          lfsr_q               <= (others => '0');
-          lfsr_q(lfsr_q'right) <= '1';
-
-        elsif shift_rise_edge_s then
-
-          -- shift LFSR left towards MSB
-          for idx in lfsr_q'right-1 downto lfsr_q'left loop
-            lfsr_q(idx) <= lfsr_q(idx+1);
-          end loop;
-
-          -- determine input bit
-          if fb_q = '0' then
-            -- "Periodic" Noise
-            -- -> input to LFSR is output
-            lfsr_q(lfsr_q'right) <= lfsr_q(lfsr_q'left);
-          else
-            -- "White" Noise
-            -- -> input to LFSR is parity of tapped bits
-            lfsr_q(lfsr_q'right) <= lfsr_tapped_f(lfsr_q);
-          end if;
-
-        end if;
-
-      end if;
-    end if;
-  end process lfsr;
-  --
-  -----------------------------------------------------------------------------
-
-
-  -----------------------------------------------------------------------------
-  -- Map output of LFSR to signed value for attenuator.
-  -----------------------------------------------------------------------------
-  freq_s <=   to_signed(+1, 2)
-            when lfsr_q(0) = '1' else
-              to_signed( 0, 2);
-
-
-  -----------------------------------------------------------------------------
-  -- The attenuator itself
-  -----------------------------------------------------------------------------
-  attenuator_b : entity work.sn76489_attenuator
-    port map (
-      attenuation_i => a_q,
-      factor_i      => freq_s,
-      product_o     => noise_o
-    );
-
-end rtl;
diff --git a/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/sn76489_tone.vhd b/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/sn76489_tone.vhd
deleted file mode 100644
index 3658efcc..00000000
--- a/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/sn76489_tone.vhd	
+++ /dev/null
@@ -1,188 +0,0 @@
--------------------------------------------------------------------------------
---
--- Synthesizable model of TI's SN76489AN.
---
--- $Id: sn76489_tone.vhd,v 1.5 2006/02/27 20:30:10 arnim Exp $
---
--- Tone Generator
---
--------------------------------------------------------------------------------
---
--- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity sn76489_tone is
-
-  port (
-    clock_i  : in  std_logic;
-    clk_en_i : in  boolean;
-    res_n_i  : in  std_logic;
-    we_i     : in  boolean;
-    d_i      : in  std_logic_vector(0 to 7);
-    r2_i     : in  std_logic;
-    ff_o     : out std_logic;
-    tone_o   : out signed(0 to 7)
-  );
-
-end sn76489_tone;
-
-architecture rtl of sn76489_tone is
-
-  signal f_q        : std_logic_vector(0 to 9);
-  signal a_q        : std_logic_vector(0 to 3);
-  signal freq_cnt_q : unsigned(0 to 9);
-  signal freq_ff_q  : std_logic;
-
-  signal freq_s     : signed(0 to 1);
-
-  function all_zero(a : in std_logic_vector) return boolean is
-    variable result_v : boolean;
-  begin
-    result_v := true;
-
-    for idx in a'low to a'high loop
-      if a(idx) /= '0' then
-        result_v := false;
-      end if;
-    end loop;
-
-    return result_v;
-  end;
-
-begin
-
-  -----------------------------------------------------------------------------
-  -- Process cpu_regs
-  --
-  -- Purpose:
-  --   Implements the registers writable by the CPU.
-  --
-  cpu_regs: process (clock_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      f_q <= (others => '0');
-      a_q <= (others => '1');
-
-    elsif clock_i'event and clock_i = '1' then
-      if clk_en_i and we_i then
-        if r2_i = '0' then
-          -- access to frequency register
-          if d_i(0) = '0' then
-            f_q(0 to 5) <= d_i(2 to 7);
-          else
-            f_q(6 to 9) <= d_i(4 to 7);
-          end if;
-
-        else
-          -- access to attenuator register
-          -- both access types can write to the attenuator register!
-          a_q <= d_i(4 to 7);
-
-        end if;
-      end if;
-    end if;
-  end process cpu_regs;
-  --
-  -----------------------------------------------------------------------------
-
-
-  -----------------------------------------------------------------------------
-  -- Process freq_gen
-  --
-  -- Purpose:
-  --   Implements the frequency generation components.
-  --
-  freq_gen: process (clock_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      freq_cnt_q <= (others => '0');
-      freq_ff_q  <= '0';
-
-    elsif clock_i'event and clock_i = '1' then
-      if clk_en_i then
-        if freq_cnt_q = 0 then
-          -- update counter from frequency register
-          freq_cnt_q <= unsigned(f_q);
-
-          -- and toggle the frequency flip-flop if enabled
-          if not all_zero(f_q) then
-            freq_ff_q <= not freq_ff_q;
-          else
-            -- if frequency setting is 0, then keep flip-flop at +1
-            freq_ff_q <= '1';
-          end if;
-
-        else
-          -- decrement frequency counter
-          freq_cnt_q <= freq_cnt_q - 1;
-
-        end if;
-      end if;
-    end if;
-  end process freq_gen;
-  --
-  -----------------------------------------------------------------------------
-
-
-  -----------------------------------------------------------------------------
-  -- Map frequency flip-flop to signed value for attenuator.
-  -----------------------------------------------------------------------------
-  freq_s <=   to_signed(+1, 2)
-            when freq_ff_q = '1' else
-              to_signed(-1, 2);
-
-
-  -----------------------------------------------------------------------------
-  -- The attenuator itself
-  -----------------------------------------------------------------------------
-  attenuator_b : entity work.sn76489_attenuator
-    port map (
-      attenuation_i => a_q,
-      factor_i      => freq_s,
-      product_o     => tone_o
-    );
-
-
-  -----------------------------------------------------------------------------
-  -- Output mapping
-  -----------------------------------------------------------------------------
-  ff_o <= freq_ff_q;
-
-end rtl;
diff --git a/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/sn76489_top.vhd b/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/sn76489_top.vhd
deleted file mode 100644
index c26d0e1a..00000000
--- a/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/sn76489_top.vhd	
+++ /dev/null
@@ -1,200 +0,0 @@
--------------------------------------------------------------------------------
---
--- Synthesizable model of TI's SN76489AN.
---
--- $Id: sn76489_top.vhd,v 1.9 2006/02/27 20:30:10 arnim Exp $
---
--- Chip Toplevel
---
--- References:
---
---   * TI Data sheet SN76489.pdf
---     ftp://ftp.whtech.com/datasheets%20&%20manuals/SN76489.pdf
---
---   * John Kortink's article on the SN76489:
---     http://web.inter.nl.net/users/J.Kortink/home/articles/sn76489/
---
---   * Maxim's "SN76489 notes" in
---     http://www.smspower.org/maxim/docs/SN76489.txt
---
--------------------------------------------------------------------------------
---
--- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library ieee;
-use ieee.numeric_std.all;
-
-entity sn76489_top is
-
-  generic (
-    clock_div_16_g : integer := 1
-  );
-  port (
-    clock_i    : in  std_logic;
-    clock_en_i : in  std_logic;
-    res_n_i    : in  std_logic;
-    ce_n_i     : in  std_logic;
-    we_n_i     : in  std_logic;
-    ready_o    : out std_logic;
-    d_i        : in  std_logic_vector(0 to 7);
-    aout_o     : out signed(0 to 7)
-  );
-
-end sn76489_top;
-
-architecture struct of sn76489_top is
-
-  signal clk_en_s    : boolean;
-
-  signal tone1_we_s,
-         tone2_we_s,
-         tone3_we_s,
-         noise_we_s  : boolean;
-  signal r2_s        : std_logic;
-
-  signal tone1_s,
-         tone2_s,
-         tone3_s,
-         noise_s     : signed(0 to 7);
-
-  signal tone3_ff_s  : std_logic;
-
-begin
-
-  -----------------------------------------------------------------------------
-  -- Clock Divider
-  -----------------------------------------------------------------------------
-  clock_div_b : entity work.sn76489_clock_div
-    generic map (
-      clock_div_16_g => clock_div_16_g
-    )
-    port map (
-      clock_i    => clock_i,
-      clock_en_i => clock_en_i,
-      res_n_i    => res_n_i,
-      clk_en_o   => clk_en_s
-    );
-
-
-  -----------------------------------------------------------------------------
-  -- Latch Control = CPU Interface
-  -----------------------------------------------------------------------------
-  latch_ctrl_b : entity work.sn76489_latch_ctrl
-    port map (
-      clock_i    => clock_i,
-      clk_en_i   => clk_en_s,
-      res_n_i    => res_n_i,
-      ce_n_i     => ce_n_i,
-      we_n_i     => we_n_i,
-      d_i        => d_i,
-      ready_o    => ready_o,
-      tone1_we_o => tone1_we_s,
-      tone2_we_o => tone2_we_s,
-      tone3_we_o => tone3_we_s,
-      noise_we_o => noise_we_s,
-      r2_o       => r2_s
-    );
-
-
-  -----------------------------------------------------------------------------
-  -- Tone Channel 1
-  -----------------------------------------------------------------------------
-  tone1_b : entity work.sn76489_tone
-    port map (
-      clock_i  => clock_i,
-      clk_en_i => clk_en_s,
-      res_n_i  => res_n_i,
-      we_i     => tone1_we_s,
-      d_i      => d_i,
-      r2_i     => r2_s,
-      ff_o     => open,
-      tone_o   => tone1_s
-    );
-
-  -----------------------------------------------------------------------------
-  -- Tone Channel 2
-  -----------------------------------------------------------------------------
-  tone2_b : entity work.sn76489_tone
-    port map (
-      clock_i  => clock_i,
-      clk_en_i => clk_en_s,
-      res_n_i  => res_n_i,
-      we_i     => tone2_we_s,
-      d_i      => d_i,
-      r2_i     => r2_s,
-      ff_o     => open,
-      tone_o   => tone2_s
-    );
-
-  -----------------------------------------------------------------------------
-  -- Tone Channel 3
-  -----------------------------------------------------------------------------
-  tone3_b : entity work.sn76489_tone
-    port map (
-      clock_i  => clock_i,
-      clk_en_i => clk_en_s,
-      res_n_i  => res_n_i,
-      we_i     => tone3_we_s,
-      d_i      => d_i,
-      r2_i     => r2_s,
-      ff_o     => tone3_ff_s,
-      tone_o   => tone3_s
-    );
-
-  -----------------------------------------------------------------------------
-  -- Noise Channel
-  -----------------------------------------------------------------------------
-  noise_b : entity work.sn76489_noise
-    port map (
-      clock_i    => clock_i,
-      clk_en_i   => clk_en_s,
-      res_n_i    => res_n_i,
-      we_i       => noise_we_s,
-      d_i        => d_i,
-      r2_i       => r2_s,
-      tone3_ff_i => tone3_ff_s,
-      noise_o    => noise_s
-    );
-
-
-  aout_o <= tone1_s + tone2_s + tone3_s + noise_s;
-
-end struct;
diff --git a/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/Dorodon.qsf b/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/Dorodon.qsf
index 62050bd1..2a15614d 100644
--- a/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/Dorodon.qsf	
+++ b/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/Dorodon.qsf	
@@ -160,7 +160,6 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 
 # end ENTITY(Dorodon)
 # -------------------
-set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/Dorodon.sv
 set_global_assignment -name VHDL_FILE rtl/ladybug.vhd
 set_global_assignment -name VHDL_FILE rtl/ladybug_video_unit.vhd
@@ -180,13 +179,7 @@ set_global_assignment -name VHDL_FILE rtl/ladybug_chutes.vhd
 set_global_assignment -name VHDL_FILE rtl/ladybug_chute.vhd
 set_global_assignment -name VHDL_FILE rtl/ladybug_char.vhd
 set_global_assignment -name VHDL_FILE rtl/ladybug_addr_dec.vhd
-set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_top.vhd
-set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_tone.vhd
-set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_noise.vhd
-set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_latch_ctrl.vhd
-set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_clock_div.vhd
-set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_attenuator.vhd
-set_global_assignment -name VHDL_FILE rtl/sound/ladybug_sound_unit.vhd
+set_global_assignment -name VHDL_FILE rtl/ladybug_sound_unit.vhd
 set_global_assignment -name VHDL_FILE rtl/ROM/rom_sprite_u.vhd
 set_global_assignment -name VHDL_FILE rtl/ROM/rom_sprite_l.vhd
 set_global_assignment -name VHDL_FILE rtl/ROM/rom_cpu3.vhd
@@ -198,15 +191,12 @@ set_global_assignment -name VHDL_FILE rtl/ROM/prom_decrypt.vhd
 set_global_assignment -name VHDL_FILE rtl/ROM/prom_10_3.vhd
 set_global_assignment -name VHDL_FILE rtl/ROM/prom_10_2.vhd
 set_global_assignment -name VHDL_FILE rtl/ROM/prom_10_1.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80a.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
 set_global_assignment -name VHDL_FILE rtl/ttl_393.vhd
 set_global_assignment -name VHDL_FILE rtl/ttl_175.vhd
 set_global_assignment -name VHDL_FILE rtl/spram.vhd
 set_global_assignment -name VHDL_FILE rtl/dpram.vhd
+set_global_assignment -name QIP_FILE ../../../common/Sound/sn76489/sn76489.qip
+set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
+set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
 set_global_assignment -name QIP_FILE rtl/pll.qip
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/Dorodon.sv b/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/Dorodon.sv
index c526e31c..7e038708 100644
--- a/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/Dorodon.sv	
+++ b/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/Dorodon.sv	
@@ -41,14 +41,16 @@ module Dorodon
 `include "rtl\build_id.v" 
 
 localparam CONF_STR = {
-	"Dorodon;;",
+	"Ladybug;;",
 	"O2,Rotate Controls,Off,On;",
 	"O34,Scanlines,Off,25%,50%,75%;",
 	"O5,Blend,Off,On;",
-	"T6,Reset;",
+	"T0,Reset;",
 	"V,v1.10.",`BUILD_DATE
 };
 
+wire rotate = status[2];
+
 assign LED = 1;
 assign AUDIO_R = AUDIO_L;
 
@@ -68,17 +70,43 @@ wire  [7:0] joystick_0;
 wire  [7:0] joystick_1;
 wire        scandoublerD;
 wire        ypbpr;
-wire [10:0] ps2_key;
-reg	[7:0] audio;
-wire 			hb, vb;
+wire        no_csync;
+wire        key_pressed;
+wire  [7:0] key_code;
+wire        key_strobe;
+
+user_io #(
+	.STRLEN(($size(CONF_STR)>>3)))
+user_io(
+	.clk_sys        (clk_sys        ),
+	.conf_str       (CONF_STR       ),
+	.SPI_CLK        (SPI_SCK        ),
+	.SPI_SS_IO      (CONF_DATA0     ),
+	.SPI_MISO       (SPI_DO         ),
+	.SPI_MOSI       (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches       (switches       ),
+	.scandoubler_disable (scandoublerD),
+	.ypbpr          (ypbpr          ),
+	.no_csync       (no_csync       ),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
+	.key_code       (key_code       ),
+	.joystick_0     (joystick_0     ),
+	.joystick_1     (joystick_1     ),
+	.status         (status         )
+);
+
+wire  [8:0] audio;
+wire        hb, vb;
 wire        blankn = ~(hb | vb);
-wire 			ce_vid;
-wire 			hs, vs;
+wire        ce_vid;
+wire        hs, vs;
 wire  [1:0] r,g,b;
 
-ladybugt dorodon(
+ladybugt ladybug(
 	.CLK_IN(clk_sys),
-	.I_RESET(status[0] | status[6] | buttons[1]),
+	.I_RESET(status[0] | buttons[1]),
 	.O_PIXCE(ce_vid),
 	.O_VIDEO_R(r),
 	.O_VIDEO_G(g),
@@ -88,15 +116,15 @@ ladybugt dorodon(
 	.O_VBLANK(vb),
 	.O_HBLANK(hb),
 	.O_AUDIO(audio),	
-	.but_coin_s(~{1'b0,btn_coin}),
-	.but_fire_s(~{1'b0,m_fire}),
-	.but_bomb_s(~{1'b0,m_bomb}),
-	.but_tilt_s(~{1'b0,1'b0}),
-	.but_select_s(~{btn_two_players, btn_one_player}),
-	.but_up_s(~{1'b0,m_up}),
-	.but_down_s(~{1'b0,m_down}),
-	.but_left_s(~{1'b0,m_left}),
-	.but_right_s(~{1'b0,m_right})
+	.but_coin_s(~{m_coin2,m_coin1}),
+	.but_fire_s(~{m_fire2A,m_fireA}),
+	.but_bomb_s(~{m_fire2B,m_fireB}),
+	.but_tilt_s(~{m_tilt,m_tilt}),
+	.but_select_s(~{m_two_players, m_one_player}),
+	.but_up_s(~{m_up2,m_up}),
+	.but_down_s(~{m_down2,m_down}),
+	.but_left_s(~{m_left2,m_left}),
+	.but_right_s(~{m_right2,m_right})
 	);
 
 mist_video #(.COLOR_DEPTH(2),.SD_HCNT_WIDTH(10)) mist_video(
@@ -114,79 +142,40 @@ mist_video #(.COLOR_DEPTH(2),.SD_HCNT_WIDTH(10)) mist_video(
 	.VGA_B(VGA_B),
 	.VGA_VS(VGA_VS),
 	.VGA_HS(VGA_HS),
-	.rotate({1'b0,status[2]}),
+	.rotate({1'b0,rotate}),
 	.ce_divider(1'b1),
 	.blend(status[5]),
 	.scandoubler_disable(scandoublerD),
 	.scanlines(status[4:3]),
-	.ypbpr(ypbpr)
+	.ypbpr(ypbpr),
+	.no_csync(no_csync)
 );
 
-user_io #(
-	.STRLEN(($size(CONF_STR)>>3)))
-user_io(
-	.clk_sys        (clk_sys        ),
-	.conf_str       (CONF_STR       ),
-	.SPI_CLK        (SPI_SCK        ),
-	.SPI_SS_IO      (CONF_DATA0     ),
-	.SPI_MISO       (SPI_DO         ),
-	.SPI_MOSI       (SPI_DI         ),
-	.buttons        (buttons        ),
-	.switches       (switches       ),
-	.scandoubler_disable (scandoublerD),
-	.ypbpr          (ypbpr          ),
-	.key_strobe     (key_strobe     ),
-	.key_pressed    (key_pressed    ),
-	.key_code       (key_code       ),
-	.joystick_0     (joystick_0     ),
-	.joystick_1     (joystick_1     ),
-	.status         (status         )
-);
-
-dac dac(
+dac #(9) dac(
 	.clk_i(clk_sys),
 	.res_n_i(1),
-	.dac_i({~audio[7], audio[6:0]}),
+	.dac_i(audio),
 	.dac_o(AUDIO_L)
 	);
 
-wire m_up     = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3];
-wire m_down   = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2];
-wire m_left   = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1];
-wire m_right  = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0];
+wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
+wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
+wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
 
-wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
-wire m_bomb   = btn_fire2 | joystick_0[5] | joystick_1[5];
-
-reg btn_one_player = 0;
-reg btn_two_players = 0;
-reg btn_left = 0;
-reg btn_right = 0;
-reg btn_down = 0;
-reg btn_up = 0;
-reg btn_fire1 = 0;
-reg btn_fire2 = 0;
-reg btn_fire3 = 0;
-reg btn_coin  = 0;
-wire       key_pressed;
-wire [7:0] key_code;
-wire       key_strobe;
-
-always @(posedge clk_sys) begin
-	if(key_strobe) begin
-		case(key_code)
-			'h75: btn_up         	<= key_pressed; // up
-			'h72: btn_down        	<= key_pressed; // down
-			'h6B: btn_left      		<= key_pressed; // left
-			'h74: btn_right       	<= key_pressed; // right
-			'h76: btn_coin				<= key_pressed; // ESC
-			'h05: btn_one_player   	<= key_pressed; // F1
-			'h06: btn_two_players  	<= key_pressed; // F2
-			'h14: btn_fire3 			<= key_pressed; // ctrl
-			'h11: btn_fire2 			<= key_pressed; // alt
-			'h29: btn_fire1   		<= key_pressed; // Space
-		endcase
-	end
-end
+arcade_inputs inputs (
+	.clk         ( clk_sys     ),
+	.key_strobe  ( key_strobe  ),
+	.key_pressed ( key_pressed ),
+	.key_code    ( key_code    ),
+	.joystick_0  ( joystick_0  ),
+	.joystick_1  ( joystick_1  ),
+	.rotate      ( rotate      ),
+	.orientation ( 2'b01       ),
+	.joyswap     ( 1'b0        ),
+	.oneplayer   ( 1'b1        ),
+	.controls    ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
+	.player1     ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
+	.player2     ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
+);
 
 endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/cpu/T80.vhd
deleted file mode 100644
index c3e13c5c..00000000
--- a/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/cpu/T80.vhd	
+++ /dev/null
@@ -1,1094 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
---
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0210 : Fixed wait and halt
---
---      0211 : Fixed Refresh addition and IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
---      0235 : Added clock enable and IM 2 fix by Mike Johnson
---
---      0237 : Changed 8080 I/O address output, added IntE output
---
---      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
---      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
---      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
---      0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
-  generic(
-    Mode   : integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-    IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-    Flag_C : integer := 0;
-    Flag_N : integer := 1;
-    Flag_P : integer := 2;
-    Flag_X : integer := 3;
-    Flag_H : integer := 4;
-    Flag_Y : integer := 5;
-    Flag_Z : integer := 6;
-    Flag_S : integer := 7
-    );
-  port(
-    RESET_n    : in  std_logic;
-    CLK_n      : in  std_logic;
-    CEN        : in  std_logic;
-    WAIT_n     : in  std_logic;
-    INT_n      : in  std_logic;
-    NMI_n      : in  std_logic;
-    BUSRQ_n    : in  std_logic;
-    M1_n       : out std_logic;
-    IORQ       : out std_logic;
-    NoRead     : out std_logic;
-    Write      : out std_logic;
-    RFSH_n     : out std_logic;
-    HALT_n     : out std_logic;
-    BUSAK_n    : out std_logic;
-    A          : out std_logic_vector(15 downto 0);
-    DInst      : in  std_logic_vector(7 downto 0);
-    DI         : in  std_logic_vector(7 downto 0);
-    DO         : out std_logic_vector(7 downto 0);
-    MC         : out std_logic_vector(2 downto 0);
-    TS         : out std_logic_vector(2 downto 0);
-    IntCycle_n : out std_logic;
-    IntE       : out std_logic;
-    Stop       : out std_logic
-    );
-end T80;
-
-architecture rtl of T80 is
-
-  constant aNone              : std_logic_vector(2 downto 0) := "111";
-  constant aBC                : std_logic_vector(2 downto 0) := "000";
-  constant aDE                : std_logic_vector(2 downto 0) := "001";
-  constant aXY                : std_logic_vector(2 downto 0) := "010";
-  constant aIOA               : std_logic_vector(2 downto 0) := "100";
-  constant aSP                : std_logic_vector(2 downto 0) := "101";
-  constant aZI                : std_logic_vector(2 downto 0) := "110";
-
-  -- Registers
-  signal ACC, F               : std_logic_vector(7 downto 0);
-  signal Ap, Fp               : std_logic_vector(7 downto 0);
-  signal I                    : std_logic_vector(7 downto 0);
-  signal R                    : unsigned(7 downto 0);
-  signal SP, PC               : unsigned(15 downto 0);
-
-  signal RegDIH               : std_logic_vector(7 downto 0);
-  signal RegDIL               : std_logic_vector(7 downto 0);
-  signal RegBusA              : std_logic_vector(15 downto 0);
-  signal RegBusB              : std_logic_vector(15 downto 0);
-  signal RegBusC              : std_logic_vector(15 downto 0);
-  signal RegAddrA_r           : std_logic_vector(2 downto 0);
-  signal RegAddrA             : std_logic_vector(2 downto 0);
-  signal RegAddrB_r           : std_logic_vector(2 downto 0);
-  signal RegAddrB             : std_logic_vector(2 downto 0);
-  signal RegAddrC             : std_logic_vector(2 downto 0);
-  signal RegWEH               : std_logic;
-  signal RegWEL               : std_logic;
-  signal Alternate            : std_logic;
-
-  -- Help Registers
-  signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
-  signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
-  signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
-  signal RegBusA_r            : std_logic_vector(15 downto 0);
-
-  signal ID16                 : signed(15 downto 0);
-  signal Save_Mux             : std_logic_vector(7 downto 0);
-
-  signal TState               : unsigned(2 downto 0);
-  signal MCycle               : std_logic_vector(2 downto 0);
-  signal IntE_FF1             : std_logic;
-  signal IntE_FF2             : std_logic;
-  signal Halt_FF              : std_logic;
-  signal BusReq_s             : std_logic;
-  signal BusAck               : std_logic;
-  signal ClkEn                : std_logic;
-  signal NMI_s                : std_logic;
-  signal INT_s                : std_logic;
-  signal IStatus              : std_logic_vector(1 downto 0);
-
-  signal DI_Reg               : std_logic_vector(7 downto 0);
-  signal T_Res                : std_logic;
-  signal XY_State             : std_logic_vector(1 downto 0);
-  signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
-  signal NextIs_XY_Fetch      : std_logic;
-  signal XY_Ind               : std_logic;
-  signal No_BTR               : std_logic;
-  signal BTR_r                : std_logic;
-  signal Auto_Wait            : std_logic;
-  signal Auto_Wait_t1         : std_logic;
-  signal Auto_Wait_t2         : std_logic;
-  signal IncDecZ              : std_logic;
-
-  -- ALU signals
-  signal BusB                 : std_logic_vector(7 downto 0);
-  signal BusA                 : std_logic_vector(7 downto 0);
-  signal ALU_Q                : std_logic_vector(7 downto 0);
-  signal F_Out                : std_logic_vector(7 downto 0);
-
-  -- Registered micro code outputs
-  signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
-  signal Arith16_r            : std_logic;
-  signal Z16_r                : std_logic;
-  signal ALU_Op_r             : std_logic_vector(3 downto 0);
-  signal Save_ALU_r           : std_logic;
-  signal PreserveC_r          : std_logic;
-  signal MCycles              : std_logic_vector(2 downto 0);
-
-  -- Micro code outputs
-  signal MCycles_d            : std_logic_vector(2 downto 0);
-  signal TStates              : std_logic_vector(2 downto 0);
-  signal IntCycle             : std_logic;
-  signal NMICycle             : std_logic;
-  signal Inc_PC               : std_logic;
-  signal Inc_WZ               : std_logic;
-  signal IncDec_16            : std_logic_vector(3 downto 0);
-  signal Prefix               : std_logic_vector(1 downto 0);
-  signal Read_To_Acc          : std_logic;
-  signal Read_To_Reg          : std_logic;
-  signal Set_BusB_To          : std_logic_vector(3 downto 0);
-  signal Set_BusA_To          : std_logic_vector(3 downto 0);
-  signal ALU_Op               : std_logic_vector(3 downto 0);
-  signal Save_ALU             : std_logic;
-  signal PreserveC            : std_logic;
-  signal Arith16              : std_logic;
-  signal Set_Addr_To          : std_logic_vector(2 downto 0);
-  signal Jump                 : std_logic;
-  signal JumpE                : std_logic;
-  signal JumpXY               : std_logic;
-  signal Call                 : std_logic;
-  signal RstP                 : std_logic;
-  signal LDZ                  : std_logic;
-  signal LDW                  : std_logic;
-  signal LDSPHL               : std_logic;
-  signal IORQ_i               : std_logic;
-  signal Special_LD           : std_logic_vector(2 downto 0);
-  signal ExchangeDH           : std_logic;
-  signal ExchangeRp           : std_logic;
-  signal ExchangeAF           : std_logic;
-  signal ExchangeRS           : std_logic;
-  signal I_DJNZ               : std_logic;
-  signal I_CPL                : std_logic;
-  signal I_CCF                : std_logic;
-  signal I_SCF                : std_logic;
-  signal I_RETN               : std_logic;
-  signal I_BT                 : std_logic;
-  signal I_BC                 : std_logic;
-  signal I_BTR                : std_logic;
-  signal I_RLD                : std_logic;
-  signal I_RRD                : std_logic;
-  signal I_INRC               : std_logic;
-  signal SetDI                : std_logic;
-	signal SetEI                : std_logic;
-	signal IMode                : std_logic_vector(1 downto 0);
-	signal Halt                 : std_logic;
-	signal XYbit_undoc          : std_logic;
-
-
-begin
-
-  mcode : T80_MCode
-    generic map(
-      Mode   => Mode,
-      Flag_C => Flag_C,
-      Flag_N => Flag_N,
-      Flag_P => Flag_P,
-      Flag_X => Flag_X,
-      Flag_H => Flag_H,
-      Flag_Y => Flag_Y,
-      Flag_Z => Flag_Z,
-      Flag_S => Flag_S)
-    port map(
-      IR          => IR,
-      ISet        => ISet,
-      MCycle      => MCycle,
-      F           => F,
-      NMICycle    => NMICycle,
-      IntCycle    => IntCycle,
-      XY_State    => XY_State,
-      MCycles     => MCycles_d,
-      TStates     => TStates,
-      Prefix      => Prefix,
-      Inc_PC      => Inc_PC,
-      Inc_WZ      => Inc_WZ,
-      IncDec_16   => IncDec_16,
-      Read_To_Acc => Read_To_Acc,
-      Read_To_Reg => Read_To_Reg,
-      Set_BusB_To => Set_BusB_To,
-      Set_BusA_To => Set_BusA_To,
-      ALU_Op      => ALU_Op,
-      Save_ALU    => Save_ALU,
-      PreserveC   => PreserveC,
-      Arith16     => Arith16,
-      Set_Addr_To => Set_Addr_To,
-      IORQ        => IORQ_i,
-      Jump        => Jump,
-      JumpE       => JumpE,
-      JumpXY      => JumpXY,
-      Call        => Call,
-      RstP        => RstP,
-      LDZ         => LDZ,
-      LDW         => LDW,
-      LDSPHL      => LDSPHL,
-      Special_LD  => Special_LD,
-      ExchangeDH  => ExchangeDH,
-      ExchangeRp  => ExchangeRp,
-      ExchangeAF  => ExchangeAF,
-      ExchangeRS  => ExchangeRS,
-      I_DJNZ      => I_DJNZ,
-      I_CPL       => I_CPL,
-      I_CCF       => I_CCF,
-      I_SCF       => I_SCF,
-      I_RETN      => I_RETN,
-      I_BT        => I_BT,
-      I_BC        => I_BC,
-      I_BTR       => I_BTR,
-      I_RLD       => I_RLD,
-      I_RRD       => I_RRD,
-      I_INRC      => I_INRC,
-      SetDI       => SetDI,
-      SetEI       => SetEI,
-      IMode       => IMode,
-      Halt        => Halt,
-      NoRead      => NoRead,
-      Write       => Write,
-      XYbit_undoc => XYbit_undoc);
-
-  alu : T80_ALU
-    generic map(
-      Mode   => Mode,
-      Flag_C => Flag_C,
-      Flag_N => Flag_N,
-      Flag_P => Flag_P,
-      Flag_X => Flag_X,
-      Flag_H => Flag_H,
-      Flag_Y => Flag_Y,
-      Flag_Z => Flag_Z,
-      Flag_S => Flag_S)
-    port map(
-      Arith16 => Arith16_r,
-      Z16     => Z16_r,
-      ALU_Op  => ALU_Op_r,
-      IR      => IR(5 downto 0),
-      ISet    => ISet,
-      BusA    => BusA,
-      BusB    => BusB,
-      F_In    => F,
-      Q       => ALU_Q,
-      F_Out   => F_Out);
-
-  ClkEn <= CEN and not BusAck;
-
-  T_Res <= '1' when TState = unsigned(TStates) else '0';
-
-  NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
-                              ((Set_Addr_To = aXY) or
-                               (MCycle = "001" and IR = "11001011") or
-                               (MCycle = "001" and IR = "00110110")) else '0';
-
-  Save_Mux <= BusB when ExchangeRp = '1' else
-              DI_Reg when Save_ALU_r = '0' else
-              ALU_Q;
-
-  process (RESET_n, CLK_n)
-  begin
-    if RESET_n = '0' then
-      PC <= (others => '0');  -- Program Counter
-      A <= (others => '0');
-      TmpAddr <= (others => '0');
-      IR <= "00000000";
-      ISet <= "00";
-      XY_State <= "00";
-      IStatus <= "00";
-      MCycles <= "000";
-      DO <= "00000000";
-
-      ACC <= (others => '1');
-      F <= (others => '1');
-      Ap <= (others => '1');
-      Fp <= (others => '1');
-      I <= (others => '0');
-      R <= (others => '0');
-      SP <= (others => '1');
-      Alternate <= '0';
-
-      Read_To_Reg_r <= "00000";
-      F <= (others => '1');
-      Arith16_r <= '0';
-      BTR_r <= '0';
-      Z16_r <= '0';
-      ALU_Op_r <= "0000";
-      Save_ALU_r <= '0';
-      PreserveC_r <= '0';
-      XY_Ind <= '0';
-
-    elsif CLK_n'event and CLK_n = '1' then
-
-      if ClkEn = '1' then
-
-        ALU_Op_r <= "0000";
-        Save_ALU_r <= '0';
-        Read_To_Reg_r <= "00000";
-
-        MCycles <= MCycles_d;
-
-        if IMode /= "11" then
-          IStatus <= IMode;
-        end if;
-
-        Arith16_r <= Arith16;
-        PreserveC_r <= PreserveC;
-        if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
-          Z16_r <= '1';
-        else
-          Z16_r <= '0';
-        end if;
-
-        if MCycle  = "001" and TState(2) = '0' then
-          -- MCycle = 1 and TState = 1, 2, or 3
-
-          if TState = 2 and Wait_n = '1' then
-            if Mode < 2 then
-              A(7 downto 0) <= std_logic_vector(R);
-              A(15 downto 8) <= I;
-              R(6 downto 0) <= R(6 downto 0) + 1;
-            end if;
-
-            if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
-              PC <= PC + 1;
-            end if;
-
-            if IntCycle = '1' and IStatus = "01" then
-              IR <= "11111111";
-            elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
-              IR <= "00000000";
-            else
-              IR <= DInst;
-            end if;
-
-            ISet <= "00";
-            if Prefix /= "00" then
-              if Prefix = "11" then
-                if IR(5) = '1' then
-                  XY_State <= "10";
-                else
-                  XY_State <= "01";
-                end if;
-              else
-                if Prefix = "10" then
-                  XY_State <= "00";
-                  XY_Ind <= '0';
-                end if;
-                ISet <= Prefix;
-              end if;
-            else
-              XY_State <= "00";
-              XY_Ind <= '0';
-            end if;
-          end if;
-
-        else
-          -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
-          if MCycle = "110" then
-            XY_Ind <= '1';
-            if Prefix = "01" then
-              ISet <= "01";
-            end if;
-          end if;
-
-          if T_Res = '1' then
-            BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
-            if Jump = '1' then
-              A(15 downto 8) <= DI_Reg;
-              A(7 downto 0) <= TmpAddr(7 downto 0);
-              PC(15 downto 8) <= unsigned(DI_Reg);
-              PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-            elsif JumpXY = '1' then
-              A <= RegBusC;
-              PC <= unsigned(RegBusC);
-            elsif Call = '1' or RstP = '1' then
-              A <= TmpAddr;
-              PC <= unsigned(TmpAddr);
-            elsif MCycle = MCycles and NMICycle = '1' then
-              A <= "0000000001100110";
-              PC <= "0000000001100110";
-            elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
-              A(15 downto 8) <= I;
-              A(7 downto 0) <= TmpAddr(7 downto 0);
-              PC(15 downto 8) <= unsigned(I);
-              PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-            else
-              case Set_Addr_To is
-                when aXY =>
-                  if XY_State = "00" then
-                    A <= RegBusC;
-                  else
-                    if NextIs_XY_Fetch = '1' then
-                      A <= std_logic_vector(PC);
-                    else
-                      A <= TmpAddr;
-                    end if;
-                  end if;
-                when aIOA =>
-                  if Mode = 3 then
-                    -- Memory map I/O on GBZ80
-                    A(15 downto 8) <= (others => '1');
-                  elsif Mode = 2 then
-                    -- Duplicate I/O address on 8080
-                    A(15 downto 8) <= DI_Reg;
-                  else
-                    A(15 downto 8) <= ACC;
-                  end if;
-                  A(7 downto 0) <= DI_Reg;
-                when aSP =>
-                  A <= std_logic_vector(SP);
-                when aBC =>
-                  if Mode = 3 and IORQ_i = '1' then
-                    -- Memory map I/O on GBZ80
-                    A(15 downto 8) <= (others => '1');
-                    A(7 downto 0) <= RegBusC(7 downto 0);
-                  else
-                    A <= RegBusC;
-                  end if;
-                when aDE =>
-                  A <= RegBusC;
-                when aZI =>
-                  if Inc_WZ = '1' then
-                    A <= std_logic_vector(unsigned(TmpAddr) + 1);
-                  else
-                    A(15 downto 8) <= DI_Reg;
-                    A(7 downto 0) <= TmpAddr(7 downto 0);
-                  end if;
-                when others =>
-                  A <= std_logic_vector(PC);
-              end case;
-            end if;
-
-            Save_ALU_r <= Save_ALU;
-            ALU_Op_r <= ALU_Op;
-
-            if I_CPL = '1' then
-              -- CPL
-              ACC <= not ACC;
-              F(Flag_Y) <= not ACC(5);
-              F(Flag_H) <= '1';
-              F(Flag_X) <= not ACC(3);
-              F(Flag_N) <= '1';
-            end if;
-            if I_CCF = '1' then
-              -- CCF
-              F(Flag_C) <= not F(Flag_C);
-              F(Flag_Y) <= ACC(5);
-              F(Flag_H) <= F(Flag_C);
-              F(Flag_X) <= ACC(3);
-              F(Flag_N) <= '0';
-            end if;
-            if I_SCF = '1' then
-              -- SCF
-              F(Flag_C) <= '1';
-              F(Flag_Y) <= ACC(5);
-              F(Flag_H) <= '0';
-              F(Flag_X) <= ACC(3);
-              F(Flag_N) <= '0';
-            end if;
-          end if;
-
-          if TState = 2 and Wait_n = '1' then
-            if ISet = "01" and MCycle = "111" then
-              IR <= DInst;
-            end if;
-            if JumpE = '1' then
-              PC <= unsigned(signed(PC) + signed(DI_Reg));
-            elsif Inc_PC = '1' then
-              PC <= PC + 1;
-            end if;
-            if BTR_r = '1' then
-              PC <= PC - 2;
-            end if;
-            if RstP = '1' then
-              TmpAddr <= (others =>'0');
-              TmpAddr(5 downto 3) <= IR(5 downto 3);
-            end if;
-          end if;
-          if TState = 3 and MCycle = "110" then
-            TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
-          end if;
-
-          if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
-            if IncDec_16(2 downto 0) = "111" then
-              if IncDec_16(3) = '1' then
-                SP <= SP - 1;
-              else
-                SP <= SP + 1;
-              end if;
-            end if;
-          end if;
-
-          if LDSPHL = '1' then
-            SP <= unsigned(RegBusC);
-          end if;
-          if ExchangeAF = '1' then
-            Ap <= ACC;
-            ACC <= Ap;
-            Fp <= F;
-            F <= Fp;
-          end if;
-          if ExchangeRS = '1' then
-            Alternate <= not Alternate;
-          end if;
-        end if;
-
-        if TState = 3 then
-          if LDZ = '1' then
-            TmpAddr(7 downto 0) <= DI_Reg;
-          end if;
-          if LDW = '1' then
-            TmpAddr(15 downto 8) <= DI_Reg;
-          end if;
-
-          if Special_LD(2) = '1' then
-            case Special_LD(1 downto 0) is
-              when "00" =>
-                ACC <= I;
-                F(Flag_P) <= IntE_FF2;
-              when "01" =>
-                ACC <= std_logic_vector(R);
-                F(Flag_P) <= IntE_FF2;
-              when "10" =>
-                I <= ACC;
-              when others =>
-                R <= unsigned(ACC);
-            end case;
-          end if;
-        end if;
-
-        if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
-          if Mode = 3 then
-            F(6) <= F_Out(6);
-            F(5) <= F_Out(5);
-            F(7) <= F_Out(7);
-            if PreserveC_r = '0' then
-              F(4) <= F_Out(4);
-            end if;
-          else
-            F(7 downto 1) <= F_Out(7 downto 1);
-            if PreserveC_r = '0' then
-              F(Flag_C) <= F_Out(0);
-            end if;
-          end if;
-        end if;
-        if T_Res = '1' and I_INRC = '1' then
-          F(Flag_H) <= '0';
-          F(Flag_N) <= '0';
-          if DI_Reg(7 downto 0) = "00000000" then
-            F(Flag_Z) <= '1';
-          else
-            F(Flag_Z) <= '0';
-          end if;
-          F(Flag_S) <= DI_Reg(7);
-          F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
-                            DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
-        end if;
-
-        if TState = 1 then
-          DO <= BusB;
-          if I_RLD = '1' then
-            DO(3 downto 0) <= BusA(3 downto 0);
-            DO(7 downto 4) <= BusB(3 downto 0);
-          end if;
-          if I_RRD = '1' then
-            DO(3 downto 0) <= BusB(7 downto 4);
-            DO(7 downto 4) <= BusA(3 downto 0);
-          end if;
-        end if;
-
-        if T_Res = '1' then
-          Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
-          Read_To_Reg_r(4) <= Read_To_Reg;
-          if Read_To_Acc = '1' then
-            Read_To_Reg_r(3 downto 0) <= "0111";
-            Read_To_Reg_r(4) <= '1';
-          end if;
-        end if;
-
-        if TState = 1 and I_BT = '1' then
-          F(Flag_X) <= ALU_Q(3);
-          F(Flag_Y) <= ALU_Q(1);
-          F(Flag_H) <= '0';
-          F(Flag_N) <= '0';
-        end if;
-        if I_BC = '1' or I_BT = '1' then
-          F(Flag_P) <= IncDecZ;
-        end if;
-
-        if (TState = 1 and Save_ALU_r = '0') or
-          (Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-          case Read_To_Reg_r is
-            when "10111" =>
-              ACC <= Save_Mux;
-            when "10110" =>
-              DO <= Save_Mux;
-            when "11000" =>
-              SP(7 downto 0) <= unsigned(Save_Mux);
-            when "11001" =>
-              SP(15 downto 8) <= unsigned(Save_Mux);
-            when "11011" =>
-              F <= Save_Mux;
-            when others =>
-          end case;
-          if XYbit_undoc='1' then
-            DO <= ALU_Q;
-          end if;
-        end if;
-
-      end if;
-
-    end if;
-
-  end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
-  process (CLK_n)
-  begin
-    if CLK_n'event and CLK_n = '1' then
-      if ClkEn = '1' then
-        -- Bus A / Write
-        RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
-        if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
-          RegAddrA_r <= XY_State(1) & "11";
-        end if;
-
-        -- Bus B
-        RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
-        if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
-          RegAddrB_r <= XY_State(1) & "11";
-        end if;
-
-        -- Address from register
-        RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-        -- Jump (HL), LD SP,HL
-        if (JumpXY = '1' or LDSPHL = '1') then
-          RegAddrC <= Alternate & "10";
-        end if;
-        if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
-          RegAddrC <= XY_State(1) & "11";
-        end if;
-
-        if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
-          IncDecZ <= F_Out(Flag_Z);
-        end if;
-        if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
-          if ID16 = 0 then
-            IncDecZ <= '0';
-          else
-            IncDecZ <= '1';
-          end if;
-        end if;
-
-        RegBusA_r <= RegBusA;
-      end if;
-    end if;
-  end process;
-
-  RegAddrA <=
-    -- 16 bit increment/decrement
-    Alternate & IncDec_16(1 downto 0) when (TState = 2 or
-                                            (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
-    XY_State(1) & "11" when (TState = 2 or
-                             (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-    -- EX HL,DL
-    Alternate & "10" when ExchangeDH = '1' and TState = 3 else
-    Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-    -- Bus A / Write
-    RegAddrA_r;
-
-  RegAddrB <=
-    -- EX HL,DL
-    Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-    -- Bus B
-    RegAddrB_r;
-
-  ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
-          signed(RegBusA) + 1;
-
-  process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
-           ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-  begin
-    RegWEH <= '0';
-    RegWEL <= '0';
-    if (TState = 1 and Save_ALU_r = '0') or
-      (Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-      case Read_To_Reg_r is
-        when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
-          RegWEH <= not Read_To_Reg_r(0);
-          RegWEL <= Read_To_Reg_r(0);
-        when others =>
-      end case;
-    end if;
-
-    if ExchangeDH = '1' and (TState = 3 or TState = 4) then
-      RegWEH <= '1';
-      RegWEL <= '1';
-    end if;
-
-    if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-      case IncDec_16(1 downto 0) is
-        when "00" | "01" | "10" =>
-          RegWEH <= '1';
-          RegWEL <= '1';
-        when others =>
-      end case;
-    end if;
-  end process;
-
-  process (Save_Mux, RegBusB, RegBusA_r, ID16,
-           ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-  begin
-    RegDIH <= Save_Mux;
-    RegDIL <= Save_Mux;
-
-    if ExchangeDH = '1' and TState = 3 then
-      RegDIH <= RegBusB(15 downto 8);
-      RegDIL <= RegBusB(7 downto 0);
-    end if;
-    if ExchangeDH = '1' and TState = 4 then
-      RegDIH <= RegBusA_r(15 downto 8);
-      RegDIL <= RegBusA_r(7 downto 0);
-    end if;
-
-    if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-      RegDIH <= std_logic_vector(ID16(15 downto 8));
-      RegDIL <= std_logic_vector(ID16(7 downto 0));
-    end if;
-  end process;
-
-  Regs : T80_Reg
-    port map(
-      Clk   => CLK_n,
-      CEN   => ClkEn,
-      WEH   => RegWEH,
-      WEL   => RegWEL,
-      AddrA => RegAddrA,
-      AddrB => RegAddrB,
-      AddrC => RegAddrC,
-      DIH   => RegDIH,
-      DIL   => RegDIL,
-      DOAH  => RegBusA(15 downto 8),
-      DOAL  => RegBusA(7 downto 0),
-      DOBH  => RegBusB(15 downto 8),
-      DOBL  => RegBusB(7 downto 0),
-      DOCH  => RegBusC(15 downto 8),
-      DOCL  => RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
-  process (CLK_n)
-  begin
-    if CLK_n'event and CLK_n = '1' then
-      if ClkEn = '1' then
-        case Set_BusB_To is
-          when "0111" =>
-            BusB <= ACC;
-          when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-            if Set_BusB_To(0) = '1' then
-              BusB <= RegBusB(7 downto 0);
-            else
-              BusB <= RegBusB(15 downto 8);
-            end if;
-          when "0110" =>
-            BusB <= DI_Reg;
-          when "1000" =>
-            BusB <= std_logic_vector(SP(7 downto 0));
-          when "1001" =>
-            BusB <= std_logic_vector(SP(15 downto 8));
-          when "1010" =>
-            BusB <= "00000001";
-          when "1011" =>
-            BusB <= F;
-          when "1100" =>
-            BusB <= std_logic_vector(PC(7 downto 0));
-          when "1101" =>
-            BusB <= std_logic_vector(PC(15 downto 8));
-          when "1110" =>
-            BusB <= "00000000";
-          when others =>
-            BusB <= "--------";
-        end case;
-
-        case Set_BusA_To is
-          when "0111" =>
-            BusA <= ACC;
-          when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-            if Set_BusA_To(0) = '1' then
-              BusA <= RegBusA(7 downto 0);
-            else
-              BusA <= RegBusA(15 downto 8);
-            end if;
-          when "0110" =>
-            BusA <= DI_Reg;
-          when "1000" =>
-            BusA <= std_logic_vector(SP(7 downto 0));
-          when "1001" =>
-            BusA <= std_logic_vector(SP(15 downto 8));
-          when "1010" =>
-            BusA <= "00000000";
-          when others =>
-            BusB <= "--------";
-        end case;
-        if XYbit_undoc='1' then
-          BusA <= DI_Reg;
-          BusB <= DI_Reg;
-        end if;
-      end if;
-    end if;
-  end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
-  process (RESET_n,CLK_n)
-  begin
-    if RESET_n = '0' then
-      RFSH_n <= '1';
-    elsif CLK_n'event and CLK_n = '1' then
-      if CEN = '1' then
-        if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
-          RFSH_n <= '0';
-        else
-          RFSH_n <= '1';
-        end if;
-      end if;
-    end if;
-  end process;
-
-  MC <= std_logic_vector(MCycle);
-  TS <= std_logic_vector(TState);
-  DI_Reg <= DI;
-  HALT_n <= not Halt_FF;
-  BUSAK_n <= not BusAck;
-  IntCycle_n <= not IntCycle;
-  IntE <= IntE_FF1;
-  IORQ <= IORQ_i;
-  Stop <= I_DJNZ;
-
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
-  process (RESET_n, CLK_n)
-    variable OldNMI_n : std_logic;
-  begin
-    if RESET_n = '0' then
-      BusReq_s <= '0';
-      INT_s <= '0';
-      NMI_s <= '0';
-      OldNMI_n := '0';
-    elsif CLK_n'event and CLK_n = '1' then
-      if CEN = '1' then
-        BusReq_s <= not BUSRQ_n;
-        INT_s <= not INT_n;
-        if NMICycle = '1' then
-          NMI_s <= '0';
-        elsif NMI_n = '0' and OldNMI_n = '1' then
-          NMI_s <= '1';
-        end if;
-        OldNMI_n := NMI_n;
-      end if;
-    end if;
-  end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
-  process (RESET_n, CLK_n)
-  begin
-    if RESET_n = '0' then
-      MCycle <= "001";
-      TState <= "000";
-      Pre_XY_F_M <= "000";
-      Halt_FF <= '0';
-      BusAck <= '0';
-      NMICycle <= '0';
-      IntCycle <= '0';
-      IntE_FF1 <= '0';
-      IntE_FF2 <= '0';
-      No_BTR <= '0';
-      Auto_Wait_t1 <= '0';
-      Auto_Wait_t2 <= '0';
-      M1_n <= '1';
-    elsif CLK_n'event and CLK_n = '1' then
-      if CEN = '1' then
-        Auto_Wait_t1 <= Auto_Wait;
-        Auto_Wait_t2 <= Auto_Wait_t1;
-        No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
-                  (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
-                  (I_BTR and (not IR(4) or F(Flag_Z)));
-        if TState = 2 then
-          if SetEI = '1' then
-            IntE_FF1 <= '1';
-            IntE_FF2 <= '1';
-          end if;
-          if I_RETN = '1' then
-            IntE_FF1 <= IntE_FF2;
-          end if;
-        end if;
-        if TState = 3 then
-          if SetDI = '1' then
-            IntE_FF1 <= '0';
-            IntE_FF2 <= '0';
-          end if;
-        end if;
-        if IntCycle = '1' or NMICycle = '1' then
-          Halt_FF <= '0';
-        end if;
-        if MCycle = "001" and TState = 2 and Wait_n = '1' then
-          M1_n <= '1';
-        end if;
-        if BusReq_s = '1' and BusAck = '1' then
-        else
-          BusAck <= '0';
-          if TState = 2 and Wait_n = '0' then
-          elsif T_Res = '1' then
-            if Halt = '1' then
-              Halt_FF <= '1';
-            end if;
-            if BusReq_s = '1' then
-              BusAck <= '1';
-            else
-              TState <= "001";
-              if NextIs_XY_Fetch = '1' then
-                MCycle <= "110";
-                Pre_XY_F_M <= MCycle;
-                if IR = "00110110" and Mode = 0 then
-                  Pre_XY_F_M <= "010";
-                end if;
-              elsif (MCycle = "111") or
-                (MCycle = "110" and Mode = 1 and ISet /= "01") then
-                MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
-              elsif (MCycle = MCycles) or
-                No_BTR = '1' or
-                (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
-                M1_n <= '0';
-                MCycle <= "001";
-                IntCycle <= '0';
-                NMICycle <= '0';
-                if NMI_s = '1' and Prefix = "00" then
-                  NMICycle <= '1';
-                  IntE_FF1 <= '0';
-                elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
-                  IntCycle <= '1';
-                  IntE_FF1 <= '0';
-                  IntE_FF2 <= '0';
-                end if;
-              else
-                MCycle <= std_logic_vector(unsigned(MCycle) + 1);
-              end if;
-            end if;
-          else
-            if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
-
-              TState <= TState + 1;
-            end if;
-          end if;
-        end if;
-        if TState = 0 then
-          M1_n <= '0';
-        end if;
-      end if;
-    end if;
-  end process;
-
-  process (IntCycle, NMICycle, MCycle)
-  begin
-    Auto_Wait <= '0';
-    if IntCycle = '1' or NMICycle = '1' then
-      if MCycle = "001" then
-        Auto_Wait <= '1';
-      end if;
-    end if;
-  end process;
-
-end;
diff --git a/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/cpu/T80_ALU.vhd
deleted file mode 100644
index 7e8a9995..00000000
--- a/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/cpu/T80_ALU.vhd	
+++ /dev/null
@@ -1,370 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0238 : Fixed zero flag for 16 bit SBC and ADC
---
---      0240 : Added GB operations
---
---      0242 : Cleanup
---
---      0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16         : in  std_logic;
-		Z16             : in  std_logic;
-		ALU_Op          : in  std_logic_vector(3 downto 0);
-		IR              : in  std_logic_vector(5 downto 0);
-		ISet            : in  std_logic_vector(1 downto 0);
-		BusA            : in  std_logic_vector(7 downto 0);
-		BusB            : in  std_logic_vector(7 downto 0);
-		F_In            : in  std_logic_vector(7 downto 0);
-		Q               : out std_logic_vector(7 downto 0);
-		F_Out           : out std_logic_vector(7 downto 0)
-	);
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
-	procedure AddSub(A        : std_logic_vector;
-					 B        : std_logic_vector;
-					 Sub      : std_logic;
-					 Carry_In : std_logic;
-			  signal Res      : out std_logic_vector;
-			  signal Carry    : out std_logic) is
-
-		variable B_i          : unsigned(A'length - 1 downto 0);
-		variable Res_i        : unsigned(A'length + 1 downto 0);
-	begin
-		if Sub = '1' then
-			B_i := not unsigned(B);
-		else
-			B_i :=     unsigned(B);
-		end if;
-
-		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
-		Carry <= Res_i(A'length + 1);
-		Res <= std_logic_vector(Res_i(A'length downto 1));
-	end;
-
-	-- AddSub variables (temporary signals)
-	signal UseCarry                : std_logic;
-	signal Carry7_v                : std_logic;
-	signal Overflow_v              : std_logic;
-	signal HalfCarry_v             : std_logic;
-	signal Carry_v                 : std_logic;
-	signal Q_v                     : std_logic_vector(7 downto 0);
-
-	signal BitMask                 : std_logic_vector(7 downto 0);
-
-begin
-
-	with IR(5 downto 3) select BitMask <= "00000001" when "000",
-										  "00000010" when "001",
-										  "00000100" when "010",
-										  "00001000" when "011",
-										  "00010000" when "100",
-										  "00100000" when "101",
-										  "01000000" when "110",
-										  "10000000" when others;
-
-	UseCarry <= not ALU_Op(2) and ALU_Op(0);
-	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
-	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
-	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-	-- bug fix - parity flag is just parity for 8080, also overflow for Z80
-	process (Carry_v, Carry7_v, Q_v)
-	begin
-		if(Mode=2) then
-			OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
-					   Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7));  else
-	OverFlow_v <= Carry_v xor Carry7_v;
-		end if;
-	end process;
-
-	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
-		variable Q_t : std_logic_vector(7 downto 0);
-		variable DAA_Q : unsigned(8 downto 0);
-	begin
-		Q_t := "--------";
-		F_Out <= F_In;
-		DAA_Q := "---------";
-		case ALU_Op is
-		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_C) <= '0';
-			case ALU_OP(2 downto 0) is
-			when "000" | "001" => -- ADD, ADC
-				Q_t := Q_v;
-				F_Out(Flag_C) <= Carry_v;
-				F_Out(Flag_H) <= HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "010" | "011" | "111" => -- SUB, SBC, CP
-				Q_t := Q_v;
-				F_Out(Flag_N) <= '1';
-				F_Out(Flag_C) <= not Carry_v;
-				F_Out(Flag_H) <= not HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "100" => -- AND
-				Q_t(7 downto 0) := BusA and BusB;
-				F_Out(Flag_H) <= '1';
-			when "101" => -- XOR
-				Q_t(7 downto 0) := BusA xor BusB;
-				F_Out(Flag_H) <= '0';
-			when others => -- OR "110"
-				Q_t(7 downto 0) := BusA or BusB;
-				F_Out(Flag_H) <= '0';
-			end case;
-			if ALU_Op(2 downto 0) = "111" then -- CP
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			else
-				F_Out(Flag_X) <= Q_t(3);
-				F_Out(Flag_Y) <= Q_t(5);
-			end if;
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				if Z16 = '1' then
-					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
-				end if;
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			case ALU_Op(2 downto 0) is
-			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
-			when others =>
-				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			end case;
-			if Arith16 = '1' then
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-				F_Out(Flag_P) <= F_In(Flag_P);
-			end if;
-		when "1100" =>
-			-- DAA
-			F_Out(Flag_H) <= F_In(Flag_H);
-			F_Out(Flag_C) <= F_In(Flag_C);
-			DAA_Q(7 downto 0) := unsigned(BusA);
-			DAA_Q(8) := '0';
-			if F_In(Flag_N) = '0' then
-				-- After addition
-				-- Alow > 9 or H = 1
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if (DAA_Q(3 downto 0) > 9) then
-						F_Out(Flag_H) <= '1';
-					else
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q := DAA_Q + 6;
-				end if;
-				-- new Ahigh > 9 or C = 1
-				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q + 96; -- 0x60
-				end if;
-			else
-				-- After subtraction
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if DAA_Q(3 downto 0) > 5 then
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
-				end if;
-				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q - 352; -- 0x160
-				end if;
-			end if;
-			F_Out(Flag_X) <= DAA_Q(3);
-			F_Out(Flag_Y) <= DAA_Q(5);
-			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
-			Q_t := std_logic_vector(DAA_Q(7 downto 0));
-			if DAA_Q(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= DAA_Q(7);
-			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
-				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
-		when "1101" | "1110" =>
-			-- RLD, RRD
-			Q_t(7 downto 4) := BusA(7 downto 4);
-			if ALU_Op(0) = '1' then
-				Q_t(3 downto 0) := BusB(7 downto 4);
-			else
-				Q_t(3 downto 0) := BusB(3 downto 0);
-			end if;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-		when "1001" =>
-			-- BIT
-			Q_t(7 downto 0) := BusB and BitMask;
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				F_Out(Flag_P) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-				F_Out(Flag_P) <= '0';
-			end if;
-			F_Out(Flag_H) <= '1';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= '0';
-			F_Out(Flag_Y) <= '0';
-			if IR(2 downto 0) /= "110" then
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			end if;
-		when "1010" =>
-			-- SET
-			Q_t(7 downto 0) := BusB or BitMask;
-		when "1011" =>
-			-- RES
-			Q_t(7 downto 0) := BusB and not BitMask;
-		when "1000" =>
-			-- ROT
-			case IR(5 downto 3) is
-			when "000" => -- RLC
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := BusA(7);
-				F_Out(Flag_C) <= BusA(7);
-			when "010" => -- RL
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(7);
-			when "001" => -- RRC
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(0);
-				F_Out(Flag_C) <= BusA(0);
-			when "011" => -- RR
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(0);
-			when "100" => -- SLA
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := '0';
-				F_Out(Flag_C) <= BusA(7);
-			when "110" => -- SLL (Undocumented) / SWAP
-				if Mode = 3 then
-					Q_t(7 downto 4) := BusA(3 downto 0);
-					Q_t(3 downto 0) := BusA(7 downto 4);
-					F_Out(Flag_C) <= '0';
-				else
-					Q_t(7 downto 1) := BusA(6 downto 0);
-					Q_t(0) := '1';
-					F_Out(Flag_C) <= BusA(7);
-				end if;
-			when "101" => -- SRA
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(7);
-				F_Out(Flag_C) <= BusA(0);
-			when others => -- SRL
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := '0';
-				F_Out(Flag_C) <= BusA(0);
-			end case;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			if ISet = "00" then
-				F_Out(Flag_P) <= F_In(Flag_P);
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-			end if;
-		when others =>
-			null;
-		end case;
-		Q <= Q_t;
-	end process;
-end;
diff --git a/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/cpu/T80_MCode.vhd
deleted file mode 100644
index 7d407fb8..00000000
--- a/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/cpu/T80_MCode.vhd	
+++ /dev/null
@@ -1,2027 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0211 : Fixed IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0235 : Added IM 2 fix by Mike Johnson
---
---      0238 : Added NoRead signal
---
---      0238b: Fixed instruction timing for POP and DJNZ
---
---      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
-
---      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
---
---      0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80_MCode is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR                              : in std_logic_vector(7 downto 0);
-		ISet                    : in std_logic_vector(1 downto 0);
-		MCycle                  : in std_logic_vector(2 downto 0);
-		F                               : in std_logic_vector(7 downto 0);
-		NMICycle                : in std_logic;
-		IntCycle                : in std_logic;
-		XY_State                : in std_logic_vector(1 downto 0);
-		MCycles                 : out std_logic_vector(2 downto 0);
-		TStates                 : out std_logic_vector(2 downto 0);
-		Prefix                  : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD
-		Inc_PC                  : out std_logic;
-		Inc_WZ                  : out std_logic;
-		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg             : out std_logic;
-		Read_To_Acc             : out std_logic;
-		Set_BusA_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op                  : out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU                : out std_logic;
-		PreserveC               : out std_logic;
-		Arith16                 : out std_logic;
-		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ                    : out std_logic;
-		Jump                    : out std_logic;
-		JumpE                   : out std_logic;
-		JumpXY                  : out std_logic;
-		Call                    : out std_logic;
-		RstP                    : out std_logic;
-		LDZ                             : out std_logic;
-		LDW                             : out std_logic;
-		LDSPHL                  : out std_logic;
-		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH              : out std_logic;
-		ExchangeRp              : out std_logic;
-		ExchangeAF              : out std_logic;
-		ExchangeRS              : out std_logic;
-		I_DJNZ                  : out std_logic;
-		I_CPL                   : out std_logic;
-		I_CCF                   : out std_logic;
-		I_SCF                   : out std_logic;
-		I_RETN                  : out std_logic;
-		I_BT                    : out std_logic;
-		I_BC                    : out std_logic;
-		I_BTR                   : out std_logic;
-		I_RLD                   : out std_logic;
-		I_RRD                   : out std_logic;
-		I_INRC                  : out std_logic;
-		SetDI                   : out std_logic;
-		SetEI                   : out std_logic;
-		IMode                   : out std_logic_vector(1 downto 0);
-		Halt                    : out std_logic;
-		NoRead                  : out std_logic;
-		Write                   : out std_logic;
-		XYbit_undoc             : out std_logic
-	);
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
-	constant aNone      : std_logic_vector(2 downto 0) := "111";
-	constant aBC        : std_logic_vector(2 downto 0) := "000";
-	constant aDE        : std_logic_vector(2 downto 0) := "001";
-	constant aXY        : std_logic_vector(2 downto 0) := "010";
-	constant aIOA       : std_logic_vector(2 downto 0) := "100";
-	constant aSP        : std_logic_vector(2 downto 0) := "101";
-	constant aZI        : std_logic_vector(2 downto 0) := "110";
-
-	function is_cc_true(
-		F : std_logic_vector(7 downto 0);
-		cc : bit_vector(2 downto 0)
-		) return boolean is
-	begin
-		if Mode = 3 then
-			case cc is
-			when "000" => return F(7) = '0'; -- NZ
-			when "001" => return F(7) = '1'; -- Z
-			when "010" => return F(4) = '0'; -- NC
-			when "011" => return F(4) = '1'; -- C
-			when "100" => return false;
-			when "101" => return false;
-			when "110" => return false;
-			when "111" => return false;
-			end case;
-		else
-			case cc is
-			when "000" => return F(6) = '0'; -- NZ
-			when "001" => return F(6) = '1'; -- Z
-			when "010" => return F(0) = '0'; -- NC
-			when "011" => return F(0) = '1'; -- C
-			when "100" => return F(2) = '0'; -- PO
-			when "101" => return F(2) = '1'; -- PE
-			when "110" => return F(7) = '0'; -- P
-			when "111" => return F(7) = '1'; -- M
-			end case;
-		end if;
-	end;
-
-begin
-
-	process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State)
-		variable DDD : std_logic_vector(2 downto 0);
-		variable SSS : std_logic_vector(2 downto 0);
-		variable DPair : std_logic_vector(1 downto 0);
-		variable IRB : bit_vector(7 downto 0);
-	begin
-		DDD := IR(5 downto 3);
-		SSS := IR(2 downto 0);
-		DPair := IR(5 downto 4);
-		IRB := to_bitvector(IR);
-
-		MCycles <= "001";
-		if MCycle = "001" then
-			TStates <= "100";
-		else
-			TStates <= "011";
-		end if;
-		Prefix <= "00";
-		Inc_PC <= '0';
-		Inc_WZ <= '0';
-		IncDec_16 <= "0000";
-		Read_To_Acc <= '0';
-		Read_To_Reg <= '0';
-		Set_BusB_To <= "0000";
-		Set_BusA_To <= "0000";
-		ALU_Op <= "0" & IR(5 downto 3);
-		Save_ALU <= '0';
-		PreserveC <= '0';
-		Arith16 <= '0';
-		IORQ <= '0';
-		Set_Addr_To <= aNone;
-		Jump <= '0';
-		JumpE <= '0';
-		JumpXY <= '0';
-		Call <= '0';
-		RstP <= '0';
-		LDZ <= '0';
-		LDW <= '0';
-		LDSPHL <= '0';
-		Special_LD <= "000";
-		ExchangeDH <= '0';
-		ExchangeRp <= '0';
-		ExchangeAF <= '0';
-		ExchangeRS <= '0';
-		I_DJNZ <= '0';
-		I_CPL <= '0';
-		I_CCF <= '0';
-		I_SCF <= '0';
-		I_RETN <= '0';
-		I_BT <= '0';
-		I_BC <= '0';
-		I_BTR <= '0';
-		I_RLD <= '0';
-		I_RRD <= '0';
-		I_INRC <= '0';
-		SetDI <= '0';
-		SetEI <= '0';
-		IMode <= "11";
-		Halt <= '0';
-		NoRead <= '0';
-		Write <= '0';
-		XYbit_undoc <= '0';
-
-		case ISet is
-		when "00" =>
-
-------------------------------------------------------------------------------
---
---      Unprefixed instructions
---
-------------------------------------------------------------------------------
-
-		case IRB is
--- 8 BIT LOAD GROUP
-		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-			-- LD r,r'
-			Set_BusB_To(2 downto 0) <= SSS;
-			ExchangeRp <= '1';
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-			-- LD r,n
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-			-- LD r,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-			-- LD (HL),r
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110110" =>
-			-- LD (HL),n
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00001010" =>
-			-- LD A,(BC)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00011010" =>
-			-- LD A,(DE)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00111010" =>
-			if Mode = 3 then
-				-- LDD A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD A,(nn)
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-				when 4 =>
-					Read_To_Acc <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00000010" =>
-			-- LD (BC),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00010010" =>
-			-- LD (DE),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110010" =>
-			if Mode = 3 then
-				-- LDD (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),A
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					Set_BusB_To <= "0111";
-				when 4 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 16 BIT LOAD GROUP
-		when "00000001"|"00010001"|"00100001"|"00110001" =>
-			-- LD dd,nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1000";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1001";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-		when "00101010" =>
-			if Mode = 3 then
-				-- LDI A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD HL,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Set_BusA_To(2 downto 0) <= "101"; -- L
-					Read_To_Reg <= '1';
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Set_BusA_To(2 downto 0) <= "100"; -- H
-					Read_To_Reg <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00100010" =>
-			if Mode = 3 then
-				-- LDI (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "0101"; -- L
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "0100"; -- H
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11111001" =>
-			-- LD SP,HL
-			TStates <= "110";
-			LDSPHL <= '1';
-		when "11000101"|"11010101"|"11100101"|"11110101" =>
-			-- PUSH qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_TO <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "0111";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '0';
-					Set_BusB_To(3) <= '0';
-				end if;
-			when 2 =>
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "1011";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '1';
-					Set_BusB_To(3) <= '0';
-				end if;
-				Write <= '1';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "11000001"|"11010001"|"11100001"|"11110001" =>
-			-- POP qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1011";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				IncDec_16 <= "0111";
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "0111";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
-		when "11101011" =>
-			if Mode /= 3 then
-				-- EX DE,HL
-				ExchangeDH <= '1';
-			end if;
-		when "00001000" =>
-			if Mode = 3 then
-				-- LD (nn),SP
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "1000";
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "1001";
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EX AF,AF'
-				ExchangeAF <= '1';
-			end if;
-		when "11011001" =>
-			if Mode = 3 then
-				-- RETI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-					SetEI <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EXX
-				ExchangeRS <= '1';
-			end if;
-		when "11100011" =>
-			if Mode /= 3 then
-				-- EX (SP),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aSP;
-				when 2 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0101";
-					Set_BusB_To <= "0101";
-					Set_Addr_To <= aSP;
-				when 3 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0100";
-					Set_BusB_To <= "0100";
-					Set_Addr_To <= aSP;
-				when 5 =>
-					IncDec_16 <= "1111";
-					TStates <= "101";
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
-		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-			-- ADD A,r
-			-- ADC A,r
-			-- SUB A,r
-			-- SBC A,r
-			-- AND A,r
-			-- OR A,r
-			-- XOR A,r
-			-- CP A,r
-			Set_BusB_To(2 downto 0) <= SSS;
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-			-- ADD A,(HL)
-			-- ADC A,(HL)
-			-- SUB A,(HL)
-			-- SBC A,(HL)
-			-- AND A,(HL)
-			-- OR A,(HL)
-			-- XOR A,(HL)
-			-- CP A,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			when others => null;
-			end case;
-		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-			-- ADD A,n
-			-- ADC A,n
-			-- SUB A,n
-			-- SBC A,n
-			-- AND A,n
-			-- OR A,n
-			-- XOR A,n
-			-- CP A,n
-			MCycles <= "010";
-			if MCycle = "010" then
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			end if;
-		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-			-- INC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0000";
-		when "00110100" =>
-			-- INC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				ALU_Op <= "0000";
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-			-- DEC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0010";
-		when "00110101" =>
-			-- DEC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				ALU_Op <= "0010";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
-		when "00100111" =>
-			-- DAA
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			ALU_Op <= "1100";
-			Save_ALU <= '1';
-		when "00101111" =>
-			-- CPL
-			I_CPL <= '1';
-		when "00111111" =>
-			-- CCF
-			I_CCF <= '1';
-		when "00110111" =>
-			-- SCF
-			I_SCF <= '1';
-		when "00000000" =>
-			if NMICycle = '1' then
-				-- NMI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif IntCycle = '1' then
-				-- INT (IM 2)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					LDZ <= '1';
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 5 =>
-					Jump <= '1';
-				when others => null;
-				end case;
-			else
-				-- NOP
-			end if;
-		when "01110110" =>
-			-- HALT
-			Halt <= '1';
-		when "11110011" =>
-			-- DI
-			SetDI <= '1';
-		when "11111011" =>
-			-- EI
-			SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
-		when "00001001"|"00011001"|"00101001"|"00111001" =>
-			-- ADD HL,ss
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				NoRead <= '1';
-				ALU_Op <= "0000";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusA_To(2 downto 0) <= "101";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-				when others =>
-					Set_BusB_To <= "1000";
-				end case;
-				TStates <= "100";
-				Arith16 <= '1';
-			when 3 =>
-				NoRead <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				ALU_Op <= "0001";
-				Set_BusA_To(2 downto 0) <= "100";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-				when others =>
-					Set_BusB_To <= "1001";
-				end case;
-				Arith16 <= '1';
-			when others =>
-			end case;
-		when "00000011"|"00010011"|"00100011"|"00110011" =>
-			-- INC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "01";
-			IncDec_16(1 downto 0) <= DPair;
-		when "00001011"|"00011011"|"00101011"|"00111011" =>
-			-- DEC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "11";
-			IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
-		when "00000111"
-			-- RLCA
-			|"00010111"
-			-- RLA
-			|"00001111"
-			-- RRCA
-			|"00011111" =>
-			-- RRA
-			Set_BusA_To(2 downto 0) <= "111";
-			ALU_Op <= "1000";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-
--- JUMP GROUP
-		when "11000011" =>
-			-- JP nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				Inc_PC <= '1';
-				Jump <= '1';
-			when others => null;
-			end case;
-		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+C),A
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-						Set_BusB_To     <= "0111";
-					when 2 =>
-						Write <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "01" =>
-					-- LD (nn),A
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						Set_BusB_To <= "0111";
-					when 4 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "10" =>
-					-- LD A,($FF00+C)
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-					when 2 =>
-						Read_To_Acc <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "11" =>
-					-- LD A,(nn)
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-					when 4 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- JP cc,nn
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Jump <= '1';
-					end if;
-				when others => null;
-				end case;
-			end if;
-		when "00011000" =>
-			if Mode /= 2 then
-				-- JR e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00111000" =>
-			if Mode /= 2 then
-				-- JR C,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00110000" =>
-			if Mode /= 2 then
-				-- JR NC,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00101000" =>
-			if Mode /= 2 then
-				-- JR Z,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00100000" =>
-			if Mode /= 2 then
-				-- JR NZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "11101001" =>
-			-- JP (HL)
-			JumpXY <= '1';
-		when "00010000" =>
-			if Mode = 3 then
-				I_DJNZ <= '1';
-			elsif Mode < 2 then
-				-- DJNZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					I_DJNZ <= '1';
-					Set_BusB_To <= "1010";
-					Set_BusA_To(2 downto 0) <= "000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					I_DJNZ <= '1';
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-
--- CALL AND RETURN GROUP
-		when "11001101" =>
-			-- CALL nn
-			MCycles <= "101";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				IncDec_16 <= "1111";
-				Inc_PC <= '1';
-				TStates <= "100";
-				Set_Addr_To <= aSP;
-				LDW <= '1';
-				Set_BusB_To <= "1101";
-			when 4 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 5 =>
-				Write <= '1';
-				Call <= '1';
-			when others => null;
-			end case;
-		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
-			if IR(5) = '0' or Mode /= 3 then
-				-- CALL cc,nn
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					LDW <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						IncDec_16 <= "1111";
-						Set_Addr_TO <= aSP;
-						TStates <= "100";
-						Set_BusB_To <= "1101";
-					else
-						MCycles <= "011";
-					end if;
-				when 4 =>
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 5 =>
-					Write <= '1';
-					Call <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11001001" =>
-			-- RET
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_TO <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				LDZ <= '1';
-			when 3 =>
-				Jump <= '1';
-				IncDec_16 <= "0111";
-			when others => null;
-			end case;
-		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+nn),A
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-						Set_BusB_To     <= "0111";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "01" =>
-					-- ADD SP,n
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						ALU_Op <= "0000";
-						Inc_PC <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_BusA_To <= "1000";
-						Set_BusB_To <= "0110";
-					when 3 =>
-						NoRead <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						ALU_Op <= "0001";
-						Set_BusA_To <= "1001";
-						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
-					when others =>
-					end case;
-				when "10" =>
-					-- LD A,($FF00+nn)
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-					when 3 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				when "11" =>
-					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
-					MCycles <= "101";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						LDW <= '1';
-					when 4 =>
-						Set_BusA_To(2 downto 0) <= "101"; -- L
-						Read_To_Reg <= '1';
-						Inc_WZ <= '1';
-						Set_Addr_To <= aZI;
-					when 5 =>
-						Set_BusA_To(2 downto 0) <= "100"; -- H
-						Read_To_Reg <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- RET cc
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Set_Addr_TO <= aSP;
-					else
-						MCycles <= "001";
-					end if;
-					TStates <= "101";
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-				when others => null;
-				end case;
-			end if;
-		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-			-- RST p
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1101";
-			when 2 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 3 =>
-				Write <= '1';
-				RstP <= '1';
-			when others => null;
-			end case;
-
--- INPUT AND OUTPUT GROUP
-		when "11011011" =>
-			if Mode /= 3 then
-				-- IN A,(n)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-				when 3 =>
-					Read_To_Acc <= '1';
-					IORQ <= '1';
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-				when others => null;
-				end case;
-			end if;
-		when "11010011" =>
-			if Mode /= 3 then
-				-- OUT (n),A
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-					Set_BusB_To <= "0111";
-				when 3 =>
-					Write <= '1';
-					IORQ <= '1';
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-				when others => null;
-				end case;
-			end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
-		when "11001011" =>
-			if Mode /= 2 then
-				Prefix <= "01";
-			end if;
-
-		when "11101101" =>
-			if Mode < 2 then
-				Prefix <= "10";
-			end if;
-
-		when "11011101"|"11111101" =>
-			if Mode < 2 then
-				Prefix <= "11";
-			end if;
-
-		end case;
-
-		when "01" =>
-
-------------------------------------------------------------------------------
---
---      CB prefixed instructions
---
-------------------------------------------------------------------------------
-
-			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
-			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-				-- RLC r
-				-- RL r
-				-- RRC r
-				-- RR r
-				-- SLA r
-				-- SRA r
-				-- SRL r
-				-- SLL r (Undocumented) / SWAP r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1000";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- R/S (IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1000";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-
-			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-				-- RLC (HL)
-				-- RL (HL)
-				-- RRC (HL)
-				-- RR (HL)
-				-- SRA (HL)
-				-- SRL (HL)
-				-- SLA (HL)
-				-- SLL (HL) (Undocumented) / SWAP (HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
-				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-				-- BIT b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-					  ALU_Op <= "1001";
-					end if;
-				else
-				-- BIT b,(IX+d), undocumented
-					MCycles <= "010";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1001";
-						TStates <= "100";
-					when others => null;
-					end case;
-				end if;
-			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-				-- BIT b,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1001";
-					TStates <= "100";
-				when others => null;
-				end case;
-			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-				-- SET b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1010";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- SET b,(IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1010";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-				-- SET b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-				-- RES b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1011";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- RES b,(IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1011";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-				
-			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-				-- RES b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end case;
-
-		when others =>
-
-------------------------------------------------------------------------------
---
---      ED prefixed instructions
---
-------------------------------------------------------------------------------
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
-				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
-				|                                            "10100100"|"10100101"|"10100110"|"10100111"
-				|                                            "10101100"|"10101101"|"10101110"|"10101111"
-				|                                            "10110100"|"10110101"|"10110110"|"10110111"
-				|                                            "10111100"|"10111101"|"10111110"|"10111111"
-				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
-				null; -- NOP, undocumented
-			when "01111110"|"01111111" =>
-				-- NOP, undocumented
-				null;
--- 8 BIT LOAD GROUP
-			when "01010111" =>
-				-- LD A,I
-				Special_LD <= "100";
-				TStates <= "101";
-			when "01011111" =>
-				-- LD A,R
-				Special_LD <= "101";
-				TStates <= "101";
-			when "01000111" =>
-				-- LD I,A
-				Special_LD <= "110";
-				TStates <= "101";
-			when "01001111" =>
-				-- LD R,A
-				Special_LD <= "111";
-				TStates <= "101";
--- 16 BIT LOAD GROUP
-			when "01001011"|"01011011"|"01101011"|"01111011" =>
-				-- LD dd,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1000";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '1';
-					end if;
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1001";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '0';
-					end if;
-				when others => null;
-				end case;
-			when "01000011"|"01010011"|"01100011"|"01110011" =>
-				-- LD (nn),dd
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1000";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1001";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10100000" | "10101000" | "10110000" | "10111000" =>
-				-- LDI, LDD, LDIR, LDDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0000";
-					Set_Addr_To <= aDE;
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- IX
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					I_BT <= '1';
-					TStates <= "101";
-					Write <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0101"; -- DE
-					else
-						IncDec_16 <= "1101";
-					end if;
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100001" | "10101001" | "10110001" | "10111001" =>
-				-- CPI, CPD, CPIR, CPDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0111";
-					Save_ALU <= '1';
-					PreserveC <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0110";
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					I_BC <= '1';
-					TStates <= "101";
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-				-- NEG
-				Alu_OP <= "0010";
-				Set_BusB_To <= "0111";
-				Set_BusA_To <= "1010";
-				Read_To_Acc <= '1';
-				Save_ALU <= '1';
-			when "01000110"|"01001110"|"01100110"|"01101110" =>
-				-- IM 0
-				IMode <= "00";
-			when "01010110"|"01110110" =>
-				-- IM 1
-				IMode <= "01";
-			when "01011110"|"01110111" =>
-				-- IM 2
-				IMode <= "10";
--- 16 bit arithmetic
-			when "01001010"|"01011010"|"01101010"|"01111010" =>
-				-- ADC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0001";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-						when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0001";
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-					when others =>
-						Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01000010"|"01010010"|"01100010"|"01110010" =>
-				-- SBC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-					when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					when others =>
-							Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01101111" =>
-				-- RLD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1101";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RLD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01100111" =>
-				-- RRD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1110";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RRD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-				-- RETI, RETN
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-				when others => null;
-				end case;
-			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-				-- IN r,(C)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					if IR(5 downto 3) /= "110" then
-						Read_To_Reg <= '1';
-						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
-					end if;
-					I_INRC <= '1';
-				when others =>
-				end case;
-			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-				-- OUT (C),r
-				-- OUT (C),0
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
-					if IR(5 downto 3) = "110" then
-						Set_BusB_To(3) <= '1';
-					end if;
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					Write <= '1';
-					IORQ <= '1';
-				when others =>
-				end case;
-			when "10100010" | "10101010" | "10110010" | "10111010" =>
-				-- INI, IND, INIR, INDR
-				-- note B is decremented AFTER being put on the bus
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aXY;
-				when 3 =>
-					if IR(3) = '0' then
-						--IncDec_16 <= "0010";
-						IncDec_16 <= "0110";
-					else
-						--IncDec_16 <= "1010";
-						IncDec_16 <= "1110";
-					end if;
-					TStates <= "100";
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100011" | "10101011" | "10110011" | "10111011" =>
-				-- OUTI, OUTD, OTIR, OTDR
-				-- note B is decremented BEFORE being put on the bus.
-				-- mikej fix for hl inc
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aBC;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- mikej
-					else
-						IncDec_16 <= "1110"; -- mikej
-					end if;
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end case;
-
-		end case;
-
-		if Mode = 1 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "011";
-			end if;
-		end if;
-
-		if Mode = 3 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "100";
-			end if;
-		end if;
-
-		if Mode < 2 then
-			if MCycle = "110" then
-				Inc_PC <= '1';
-				if Mode = 1 then
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-					Set_BusB_To(2 downto 0) <= SSS;
-					Set_BusB_To(3) <= '0';
-				end if;
-				if IRB = "00110110" or IRB = "11001011" then
-					Set_Addr_To <= aNone;
-				end if;
-			end if;
-			if MCycle = "111" then
-				if Mode = 0 then
-					TStates <= "101";
-				end if;
-				if ISet /= "01" then
-					Set_Addr_To <= aXY;
-				end if;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-				if IRB = "00110110" or ISet = "01" then
-					-- LD (HL),n
-					Inc_PC <= '1';
-				else
-					NoRead <= '1';
-				end if;
-			end if;
-		end if;
-
-	end process;
-
-end;
diff --git a/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/cpu/T80_Pack.vhd
deleted file mode 100644
index 6904b66b..00000000
--- a/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/cpu/T80_Pack.vhd	
+++ /dev/null
@@ -1,220 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
-	component T80
-	generic(
-		Mode : integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		RESET_n         : in std_logic;
-		CLK_n           : in std_logic;
-		CEN                     : in std_logic;
-		WAIT_n          : in std_logic;
-		INT_n           : in std_logic;
-		NMI_n           : in std_logic;
-		BUSRQ_n         : in std_logic;
-		M1_n            : out std_logic;
-		IORQ            : out std_logic;
-		NoRead          : out std_logic;
-		Write           : out std_logic;
-		RFSH_n          : out std_logic;
-		HALT_n          : out std_logic;
-		BUSAK_n         : out std_logic;
-		A                       : out std_logic_vector(15 downto 0);
-		DInst           : in std_logic_vector(7 downto 0);
-		DI                      : in std_logic_vector(7 downto 0);
-		DO                      : out std_logic_vector(7 downto 0);
-		MC                      : out std_logic_vector(2 downto 0);
-		TS                      : out std_logic_vector(2 downto 0);
-		IntCycle_n      : out std_logic;
-		IntE            : out std_logic;
-		Stop            : out std_logic
-	);
-	end component;
-
-	component T80_Reg
-	port(
-		Clk                     : in std_logic;
-		CEN                     : in std_logic;
-		WEH                     : in std_logic;
-		WEL                     : in std_logic;
-		AddrA           : in std_logic_vector(2 downto 0);
-		AddrB           : in std_logic_vector(2 downto 0);
-		AddrC           : in std_logic_vector(2 downto 0);
-		DIH                     : in std_logic_vector(7 downto 0);
-		DIL                     : in std_logic_vector(7 downto 0);
-		DOAH            : out std_logic_vector(7 downto 0);
-		DOAL            : out std_logic_vector(7 downto 0);
-		DOBH            : out std_logic_vector(7 downto 0);
-		DOBL            : out std_logic_vector(7 downto 0);
-		DOCH            : out std_logic_vector(7 downto 0);
-		DOCL            : out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-	component T80_MCode
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR                      : in  std_logic_vector(7 downto 0);
-		ISet                    : in  std_logic_vector(1 downto 0);
-		MCycle                  : in  std_logic_vector(2 downto 0);
-		F                       : in  std_logic_vector(7 downto 0);
-		NMICycle                : in  std_logic;
-		IntCycle                : in  std_logic;
-		XY_State                : in  std_logic_vector(1 downto 0);
-		MCycles                 : out std_logic_vector(2 downto 0);
-		TStates                 : out std_logic_vector(2 downto 0);
-		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC                  : out std_logic;
-		Inc_WZ                  : out std_logic;
-		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg             : out std_logic;
-		Read_To_Acc             : out std_logic;
-		Set_BusA_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op                  : out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU                : out std_logic;
-		PreserveC               : out std_logic;
-		Arith16                 : out std_logic;
-		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ                    : out std_logic;
-		Jump                    : out std_logic;
-		JumpE                   : out std_logic;
-		JumpXY                  : out std_logic;
-		Call                    : out std_logic;
-		RstP                    : out std_logic;
-		LDZ                     : out std_logic;
-		LDW                     : out std_logic;
-		LDSPHL                  : out std_logic;
-		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH              : out std_logic;
-		ExchangeRp              : out std_logic;
-		ExchangeAF              : out std_logic;
-		ExchangeRS              : out std_logic;
-		I_DJNZ                  : out std_logic;
-		I_CPL                   : out std_logic;
-		I_CCF                   : out std_logic;
-		I_SCF                   : out std_logic;
-		I_RETN                  : out std_logic;
-		I_BT                    : out std_logic;
-		I_BC                    : out std_logic;
-		I_BTR                   : out std_logic;
-		I_RLD                   : out std_logic;
-		I_RRD                   : out std_logic;
-		I_INRC                  : out std_logic;
-		SetDI                   : out std_logic;
-		SetEI                   : out std_logic;
-		IMode                   : out std_logic_vector(1 downto 0);
-		Halt                    : out std_logic;
-		NoRead                  : out std_logic;
-		Write                   : out std_logic;
-		XYbit_undoc             : out std_logic
-	);
-	end component;
-
-	component T80_ALU
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16         : in  std_logic;
-		Z16             : in  std_logic;
-		ALU_Op          : in  std_logic_vector(3 downto 0);
-		IR              : in  std_logic_vector(5 downto 0);
-		ISet            : in  std_logic_vector(1 downto 0);
-		BusA            : in  std_logic_vector(7 downto 0);
-		BusB            : in  std_logic_vector(7 downto 0);
-		F_In            : in  std_logic_vector(7 downto 0);
-		Q               : out std_logic_vector(7 downto 0);
-		F_Out           : out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-end;
diff --git a/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/cpu/T80_Reg.vhd
deleted file mode 100644
index 998033ef..00000000
--- a/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/cpu/T80_Reg.vhd	
+++ /dev/null
@@ -1,114 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
---      0242 : Initial release
---
---      0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
-  port(
-    Clk   : in  std_logic;
-    CEN   : in  std_logic;
-    WEH   : in  std_logic;
-    WEL   : in  std_logic;
-    AddrA : in  std_logic_vector(2 downto 0);
-    AddrB : in  std_logic_vector(2 downto 0);
-    AddrC : in  std_logic_vector(2 downto 0);
-    DIH   : in  std_logic_vector(7 downto 0);
-    DIL   : in  std_logic_vector(7 downto 0);
-    DOAH  : out std_logic_vector(7 downto 0);
-    DOAL  : out std_logic_vector(7 downto 0);
-    DOBH  : out std_logic_vector(7 downto 0);
-    DOBL  : out std_logic_vector(7 downto 0);
-    DOCH  : out std_logic_vector(7 downto 0);
-    DOCL  : out std_logic_vector(7 downto 0)
-    );
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
-  type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
-  signal      RegsH   : Register_Image(0 to 7);
-  signal      RegsL   : Register_Image(0 to 7);
-
-begin
-
-  process (Clk)
-  begin
-    if Clk'event and Clk = '1' then
-      if CEN = '1' then
-        if WEH = '1' then
-          RegsH(to_integer(unsigned(AddrA))) <= DIH;
-        end if;
-        if WEL = '1' then
-          RegsL(to_integer(unsigned(AddrA))) <= DIL;
-        end if;
-      end if;
-    end if;
-  end process;
-
-  DOAH <= RegsH(to_integer(unsigned(AddrA)));
-  DOAL <= RegsL(to_integer(unsigned(AddrA)));
-  DOBH <= RegsH(to_integer(unsigned(AddrB)));
-  DOBL <= RegsL(to_integer(unsigned(AddrB)));
-  DOCH <= RegsH(to_integer(unsigned(AddrC)));
-  DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
diff --git a/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/cpu/T80a.vhd b/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/cpu/T80a.vhd
deleted file mode 100644
index 33d61068..00000000
--- a/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/cpu/T80a.vhd	
+++ /dev/null
@@ -1,280 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core, asynchronous top level
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0211 : Fixed interrupt cycle
---
---      0235 : Updated for T80 interface change
---
---      0238 : Updated for T80 interface change
---
---      0240 : Updated for T80 interface change
---
---      0242 : Updated for T80 interface change
---
---      0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80a is
-  generic(
-    Mode : integer := 0     -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-    );
-  port(
-    RESET_n    : in  std_logic;
-    CLK_n      : in  std_logic;
-    CLK_EN_SYS : in  std_logic;
-    WAIT_n     : in  std_logic;
-    INT_n      : in  std_logic;
-    NMI_n      : in  std_logic;
-    BUSRQ_n    : in  std_logic;
-    M1_n       : out std_logic;
-    MREQ_n     : out std_logic;
-    IORQ_n     : out std_logic;
-    RD_n       : out std_logic;
-    WR_n       : out std_logic;
-    RFSH_n     : out std_logic;
-    HALT_n     : out std_logic;
-    BUSAK_n    : out std_logic;
-    A          : out std_logic_vector(15 downto 0);
-		DI						: in  std_logic_vector(7 downto 0);
-		DO						: out std_logic_vector(7 downto 0)
-    );
-end T80a;
-
-architecture rtl of T80a is
-
-  signal CEN          : std_logic;
-  signal Reset_s      : std_logic;
-  signal IntCycle_n   : std_logic;
-  signal IORQ         : std_logic;
-  signal NoRead       : std_logic;
-  signal Write        : std_logic;
-  signal MREQ         : std_logic;
-  signal MReq_Inhibit : std_logic;
-  signal Req_Inhibit  : std_logic;
-  signal RD           : std_logic;
-  signal MREQ_n_i     : std_logic;
-  signal IORQ_n_i     : std_logic;
-  signal RD_n_i       : std_logic;
-  signal WR_n_i       : std_logic;
-  signal RFSH_n_i     : std_logic;
-  signal BUSAK_n_i    : std_logic;
-  signal A_i          : std_logic_vector(15 downto 0);
-	signal DO_Reg			: std_logic_vector(7 downto 0);
-  signal DI_Reg       : std_logic_vector (7 downto 0);  -- Input synchroniser
-  signal Wait_s       : std_logic;
-  signal MCycle       : std_logic_vector(2 downto 0);
-  signal TState       : std_logic_vector(2 downto 0);
-
-begin
-
-  -- clock enable supplied from clocking system
-  CEN <= CLK_EN_SYS;
-
-  BUSAK_n <= BUSAK_n_i;
-  MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
-  RD_n_i <= not RD or Req_Inhibit;
-
-  MREQ_n <= MREQ_n_i;
-  IORQ_n <= IORQ_n_i;
-  RD_n <= RD_n_i;
-  WR_n <= WR_n_i;
-  RFSH_n <= RFSH_n_i;
-  A <= A_i;
-	DO <= DO_Reg;
-
---   process (RESET_n, CLK_n)
---   begin
---     if RESET_n = '0' then
---       Reset_s <= '0';
---     elsif CLK_n'event and CLK_n = '1' then
---       Reset_s <= '1';
---     end if;
---   end process;
-  -- T80 reset input has already proper characteristics:
-  --   * asynchronous assertion
-  --   * deassertion synchronous to CLK_n (main_clk)
-  Reset_s <= RESET_n;
-
-  u0 : T80
-    generic map(
-      Mode       => Mode,
-      IOWait     => 1)
-    port map(
-      CEN        => CEN,
-      M1_n       => M1_n,
-      IORQ       => IORQ,
-      NoRead     => NoRead,
-      Write      => Write,
-      RFSH_n     => RFSH_n_i,
-      HALT_n     => HALT_n,
-      WAIT_n     => Wait_s,
-      INT_n      => INT_n,
-      NMI_n      => NMI_n,
-      RESET_n    => Reset_s,
-      BUSRQ_n    => BUSRQ_n,
-      BUSAK_n    => BUSAK_n_i,
-      CLK_n      => CLK_n,
-      A          => A_i,
-			DInst => DI,
-      DI         => DI_Reg,
-			DO => DO_Reg,
-      MC         => MCycle,
-      TS         => TState,
-      IntCycle_n => IntCycle_n);
-
-  process (CLK_n)
-  begin
-    if CLK_n'event and CLK_n = '0' then
-      if CEN = '1' then
-        Wait_s <= WAIT_n;
-        if TState = "011" and BUSAK_n_i = '1' then
-					DI_Reg <= to_x01(DI);
-        end if;
-      end if;
-    end if;
-  end process;
-
-  process (Reset_s,CLK_n)
-  begin
-    if Reset_s = '0' then
-      WR_n_i <= '1';
-    elsif CLK_n'event and CLK_n = '1' then
-      if CEN = '1' then
-        WR_n_i <= '1';
-        if TState = "001" then      -- To short for IO writes !!!!!!!!!!!!!!!!!!!
-          WR_n_i <= not Write;
-        end if;
-      end if;
-    end if;
-  end process;
-
-  process (Reset_s,CLK_n)
-  begin
-    if Reset_s = '0' then
-      Req_Inhibit <= '0';
-    elsif CLK_n'event and CLK_n = '1' then
-      if CEN = '1' then
-        if MCycle = "001" and TState = "010" then
-          Req_Inhibit <= '1';
-        else
-          Req_Inhibit <= '0';
-        end if;
-      end if;
-    end if;
-  end process;
-
-  process (Reset_s,CLK_n)
-  begin
-    if Reset_s = '0' then
-      MReq_Inhibit <= '0';
-    elsif CLK_n'event and CLK_n = '0' then
-      if CEN = '1' then
-        if MCycle = "001" and TState = "010" then
-          MReq_Inhibit <= '1';
-        else
-          MReq_Inhibit <= '0';
-        end if;
-      end if;
-    end if;
-  end process;
-
-  process(Reset_s,CLK_n)
-  begin
-    if Reset_s = '0' then
-      RD <= '0';
-      IORQ_n_i <= '1';
-      MREQ <= '0';
-    elsif CLK_n'event and CLK_n = '0' then
-      if CEN = '1' then
-
-        if MCycle = "001" then
-          if TState = "001" then
-            RD <= IntCycle_n;
-            MREQ <= IntCycle_n;
-            IORQ_n_i <= IntCycle_n;
-          end if;
-          if TState = "011" then
-            RD <= '0';
-            IORQ_n_i <= '1';
-            MREQ <= '1';
-          end if;
-          if TState = "100" then
-            MREQ <= '0';
-          end if;
-        else
-          if TState = "001" and NoRead = '0' then
-            RD <= not Write;
-            IORQ_n_i <= not IORQ;
-            MREQ <= not IORQ;
-          end if;
-          if TState = "011" then
-            RD <= '0';
-            IORQ_n_i <= '1';
-            MREQ <= '0';
-          end if;
-        end if;
-
-      end if;
-    end if;
-  end process;
-
-end;
diff --git a/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/ladybug.vhd b/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/ladybug.vhd
index 92348ed0..cd241b9d 100644
--- a/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/ladybug.vhd	
+++ b/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/ladybug.vhd	
@@ -65,7 +65,7 @@ port (
 	O_PIXCE      : out std_logic;
 
 	-- Audio Interface --------------------------------------------------------
-	O_AUDIO      : out signed(7 downto 0);
+	O_AUDIO      : out std_logic_vector( 8 downto 0);
 	
 	but_coin_s   : in  std_logic_vector( 1 downto 0);
 	but_fire_s   : in  std_logic_vector( 1 downto 0);
@@ -160,8 +160,8 @@ begin
 		rgb_b_o           => O_VIDEO_B,
 		hsync_n_o         => O_HSYNC,
 		vsync_n_o         => O_VSYNC,
-	   vblank_o          => O_VBLANK,
-	   hblank_o          => O_HBLANK,
+		vblank_o          => O_VBLANK,
+		hblank_o          => O_HBLANK,
 		audio_o           => O_AUDIO,
 		rom_cpu_a_o       => rom_cpu_a_s,
 		rom_cpu_d_i       => rom_cpu_d_s,
diff --git a/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_cpu_unit.vhd b/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_cpu_unit.vhd
index 7d41074f..5646437b 100644
--- a/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_cpu_unit.vhd	
+++ b/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_cpu_unit.vhd	
@@ -119,14 +119,14 @@ begin
   -- "wait" has to be modelled with the clock enable because the T80 is not
   -- able to enlarge write accesses properly when they are delayed with "wait"
   t80_clk_en_s <= clk_en_4mhz_i and wait_n_s;
-  T80a_b : entity work.T80a
+  T80a_b : entity work.T80s
     generic map (
       Mode => 0
     )
     port map (
       RESET_n    => res_n_i,
-      CLK_n      => clk_20mhz_i,
-      CLK_EN_SYS => t80_clk_en_s,
+      CLK        => clk_20mhz_i,
+      CEN        => t80_clk_en_s,
       WAIT_n     => wait_n_s,
       INT_n      => int_n_s,
       NMI_n      => nmi_n_s,
diff --git a/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_machine.vhd b/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_machine.vhd
index 584b8391..dbe5d75b 100644
--- a/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_machine.vhd	
+++ b/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_machine.vhd	
@@ -77,10 +77,10 @@ entity ladybug_machine is
     hsync_n_o         : out std_logic;
     vsync_n_o         : out std_logic;
     comp_sync_n_o     : out std_logic;
-	 vblank_o          : out std_logic;
-	 hblank_o          : out std_logic;
+    vblank_o          : out std_logic;
+    hblank_o          : out std_logic;
     -- Audio Interface --------------------------------------------------------
-    audio_o           : out signed( 7 downto 0);
+    audio_o           : out std_logic_vector( 8 downto 0);
     -- CPU ROM Interface ------------------------------------------------------
     rom_cpu_a_o       : out std_logic_vector(14 downto 0);
     rom_cpu_d_i       : in  std_logic_vector( 7 downto 0);
diff --git a/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/sound/ladybug_sound_unit.vhd b/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_sound_unit.vhd
similarity index 88%
rename from Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/sound/ladybug_sound_unit.vhd
rename to Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_sound_unit.vhd
index 23ad2a6a..8fe04ba8 100644
--- a/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/sound/ladybug_sound_unit.vhd	
+++ b/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_sound_unit.vhd	
@@ -59,7 +59,7 @@ entity ladybug_sound_unit is
     wr_n_i         : in  std_logic;
     d_from_cpu_i   : in  std_logic_vector(7 downto 0);
     sound_wait_n_o : out std_logic;
-    audio_o        : out signed(7 downto 0)
+    audio_o        : out std_logic_vector(8 downto 0)
   );
 
 end ladybug_sound_unit;
@@ -70,7 +70,7 @@ architecture struct of ladybug_sound_unit is
          ready_c1_s  : std_logic;
 
   signal aout_b1_s,
-         aout_c1_s   : signed(7 downto 0);
+         aout_c1_s   : std_logic_vector(7 downto 0);
 
 begin
 
@@ -117,23 +117,7 @@ begin
   --
   -- Purpose:
   --   Mix the digital audio of the two SN76489 instances.
-  --   Additional care is taken to avoid audio overfow/clipping.
-  --
-  mix: process (aout_b1_s,
-                aout_c1_s)
-    variable sum_v : signed(8 downto 0);
-  begin
-    sum_v := RESIZE(aout_b1_s, 9) + RESIZE(aout_c1_s, 9);
-
-    if sum_v > 127 then
-      audio_o <= to_signed(127, 8);
-    elsif sum_v < -128 then
-      audio_o <= to_signed(-128, 8);
-    else
-      audio_o <= RESIZE(sum_v, 8);
-    end if;
-
-  end process mix;
+  audio_o <= std_logic_vector(unsigned('0'&aout_b1_s) + unsigned('0'&aout_c1_s));
   -- 
   -----------------------------------------------------------------------------
 
diff --git a/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/COPYING b/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/COPYING
deleted file mode 100644
index 60549be5..00000000
--- a/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/COPYING	
+++ /dev/null
@@ -1,340 +0,0 @@
-		    GNU GENERAL PUBLIC LICENSE
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-                       59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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diff --git a/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/README b/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/README
deleted file mode 100644
index 33630144..00000000
--- a/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/README	
+++ /dev/null
@@ -1,143 +0,0 @@
-
-An SN76489AN Compatible Implementation in VHDL
-==============================================
-Version: $Date: 2006/06/18 19:28:40 $
-
-Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
-See the file COPYING.
-
-
-Integration
------------
-
-The sn76489 design exhibits all interface signals as the original chip. It
-only differs in the audio data output which is provided as an 8 bit signed
-vector instead of an analog output pin.
-
-  generic (
-    clock_div_16_g : integer := 1
-    -- Set to '1' when operating the design in SN76489 mode. The primary clock
-    -- input is divided by 16 in this variant. The data sheet mentions the
-    -- SN76494 which contains a divide-by-2 clock input stage. Set the generic
-    -- to '0' to enable this mode.
-  );
-  port (
-    clock_i    : in  std_logic;
-    -- Primary clock input
-    -- Drive with the target frequency or any integer multiple of it.
-
-    clock_en_i : in  std_logic;
-    -- Clock enable
-    -- A '1' on this input qualifies a valid rising edge on clock_i. A '0'
-    -- disables the next rising clock edge, effectivley halting the design
-    -- until the next enabled rising clock edge.
-    -- Can be used to run the core at lower frequencies than applied on
-    -- clock_i.
-
-    res_n_i    : in  std_logic;
-    -- Asynchronous low active reset input.
-    -- Sets all sequential elements to a known state.
-
-    ce_n_i     : in  std_logic;
-    -- Chip enable, low active.
-
-    we_n_i     : in  std_logic;
-    -- Write enable, low active.
-
-    ready_o    : out std_logic;
-    -- Ready indication to microprocessor.
-
-    d_i        : in  std_logic_vector(0 to 7);
-    -- Data input
-    -- MSB 0 ... 7 LSB
-
-    aout_o     : out signed(0 to 7)
-    -- Audio output, signed vector
-    -- MSB/SIGN 0 ... 7 LSB
-  );
-
-
-Both 8 bit vector ports are defined (0 to 7) which declares bit 0 to be the
-MSB and bit 7 to be the LSB. This has been implemented according to TI's data
-sheet, thus all register/data format figures apply 1:1 for this design.
-Many systems will flip the system data bus bit wise before it is connected to
-this PSG. This is simply achieved with the following VHDL construct:
-
-  signal data_s : std_logic_vector(7 downto 0);
-
-  ...
-  d_i => data_s,
-  ...
-
-d_i and data_s will be assigned from left to right, resulting in the expected
-bit assignment:
-
-  d_i    data_s
-   0       7
-   1       6
-      ...
-   6       1
-   7       0
-
-
-As this design is fully synchronous, care has to be taken when the design
-replaces an SN76489 in asynchronous mode. No problems are expected when
-interfacing the code to other synchronous components.
-
-
-Design Hierarchy
-----------------
-
-  sn76489_top
-    |
-    +-- sn76489_latch_ctrl
-    |
-    +-- sn76489_clock_div
-    |
-    +-- sn76489_tone
-    |     |
-    |     \-- sn76489_attentuator
-    |
-    +-- sn76489_tone
-    |     |
-    |     \-- sn76489_attentuator
-    |
-    +-- sn76489_tone
-    |     |
-    |     \-- sn76489_attentuator
-    |
-    \-- sn76489_noise
-          |
-          \-- sn76489_attentuator
-
-Resulting compilation sequence:
-
-  sn76489_comp_pack-p.vhd
-  sn76489_top.vhd
-  sn76489_latch_ctrl.vhd
-  sn76489_latch_ctrl-c.vhd
-  sn76489_clock_div.vhd
-  sn76489_clock_div-c.vhd
-  sn76489_attenuator.vhd
-  sn76489_attenuator-c.vhd
-  sn76489_tone.vhd
-  sn76489_tone-c.vhd
-  sn76489_noise.vhd
-  sn76489_noise-c.vhd
-  sn76489_top-c.vhd
-
-Skip the files containing VHDL configurations when analyzing the code for
-synthesis.
-
-
-References
-----------
-
-* TI Data sheet SN76489.pdf
-  ftp://ftp.whtech.com/datasheets%20&%20manuals/SN76489.pdf
-
-* John Kortink's article on the SN76489:
-  http://web.inter.nl.net/users/J.Kortink/home/articles/sn76489/
-
-* Maxim's "SN76489 notes" in
-  http://www.smspower.org/maxim/docs/SN76489.txt
diff --git a/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/sn76489_attenuator.vhd b/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/sn76489_attenuator.vhd
deleted file mode 100644
index 444064e5..00000000
--- a/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/sn76489_attenuator.vhd	
+++ /dev/null
@@ -1,114 +0,0 @@
--------------------------------------------------------------------------------
---
--- Synthesizable model of TI's SN76489AN.
---
--- $Id: sn76489_attenuator.vhd,v 1.7 2006/02/27 20:30:10 arnim Exp $
---
--- Attenuator Module
---
--------------------------------------------------------------------------------
---
--- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity sn76489_attenuator is
-
-  port (
-    attenuation_i : in  std_logic_vector(0 to 3);
-    factor_i      : in  signed(0 to 1);
-    product_o     : out signed(0 to 7)
-  );
-
-end sn76489_attenuator;
-
-
-architecture rtl of sn76489_attenuator is
-
-begin
-
-  -----------------------------------------------------------------------------
-  -- Process attenuate
-  --
-  -- Purpose:
-  --   Determine the attenuation and generate the resulting product.
-  --
-  --   The maximum attenuation value is 31 which corresponds to volume off.
-  --   As described in the data sheet, the maximum "playing" attenuation is
-  --     28 = 16 + 8 + 4
-  --
-  --   The table for the volume constants is derived from the following
-  --   formula (each step is 2dB voltage):
-  --     v(0)   = 31
-  --     v(n+1) = v(n) * 0.79432823
-  --
-  attenuate: process (attenuation_i,
-                      factor_i)
-
-    type     volume_t is array (natural range 0 to 15) of natural;
-    constant volume_c : volume_t :=
-      (31, 25, 20, 16, 12, 10, 8, 6, 5, 4, 3, 2, 2, 2, 1, 0);
-
-    variable attenuation_v  : unsigned(attenuation_i'range);
-    variable volume_v       : signed(product_o'range);
-
-  begin
-
-    attenuation_v := unsigned(attenuation_i);
-
-    -- volume look-up table
-    volume_v := to_signed(volume_c(to_integer(attenuation_v)),
-                          product_o'length);
-
-    -- this replaces a multiplier and consumes a bit fewer
-    -- resources
-    case to_integer(factor_i) is
-      when +1 =>
-        product_o <= volume_v;
-      when -1 =>
-        product_o <= -volume_v;
-      when others =>
-        product_o <= (others => '0');
-    end case;
-
-  end process attenuate;
-  --
-  -----------------------------------------------------------------------------
-
-end rtl;
diff --git a/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/sn76489_clock_div.vhd b/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/sn76489_clock_div.vhd
deleted file mode 100644
index eab86beb..00000000
--- a/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/sn76489_clock_div.vhd	
+++ /dev/null
@@ -1,134 +0,0 @@
--------------------------------------------------------------------------------
---
--- Synthesizable model of TI's SN76489AN.
---
--- $Id: sn76489_clock_div.vhd,v 1.4 2005/10/10 21:51:27 arnim Exp $
---
--- Clock Divider Circuit
---
--------------------------------------------------------------------------------
---
--- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity sn76489_clock_div is
-
-  generic (
-    clock_div_16_g : integer := 1
-  );
-  port (
-    clock_i    : in  std_logic;
-    clock_en_i : in  std_logic;
-    res_n_i    : in  std_logic;
-    clk_en_o   : out boolean
-  );
-
-end sn76489_clock_div;
-
-
-library ieee;
-use ieee.numeric_std.all;
-
-architecture rtl of sn76489_clock_div is
-
-  signal cnt_s,
-         cnt_q  : unsigned(3 downto 0);
-
-begin
-
-  -----------------------------------------------------------------------------
-  -- Process seq
-  --
-  -- Purpose:
-  --   Implements the sequential counter element.
-  --
-  seq: process (clock_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      cnt_q <= (others => '0');
-    elsif clock_i'event and clock_i = '1' then
-      cnt_q <= cnt_s;
-    end if;
-  end process seq;
-  --
-  -----------------------------------------------------------------------------
-
-
-  -----------------------------------------------------------------------------
-  -- Process comb
-  --
-  -- Purpose:
-  --   Implements the combinational counter logic.
-  --
-  comb: process (clock_en_i,
-                 cnt_q)
-  begin
-    -- default assignments
-    cnt_s    <= cnt_q;
-    clk_en_o <= false;
-
-    if clock_en_i = '1' then
-
-      if cnt_q = 0 then
-        clk_en_o <= true;
-
-        if clock_div_16_g = 1 then
-          cnt_s  <= to_unsigned(15, cnt_q'length);
-        elsif clock_div_16_g = 0 then
-          cnt_s  <= to_unsigned( 1, cnt_q'length);
-        else
-          -- pragma translate_off
-          assert false
-            report "Generic clock_div_16_g must be either 0 or 1."
-            severity failure;
-          -- pragma translate_on
-        end if;
-
-      else
-        cnt_s    <= cnt_q - 1;
-
-      end if;
-
-    end if;
-
-  end process comb;
-  --
-  -----------------------------------------------------------------------------
-
-end rtl;
diff --git a/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/sn76489_latch_ctrl.vhd b/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/sn76489_latch_ctrl.vhd
deleted file mode 100644
index 789720c2..00000000
--- a/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/sn76489_latch_ctrl.vhd	
+++ /dev/null
@@ -1,138 +0,0 @@
--------------------------------------------------------------------------------
---
--- Synthesizable model of TI's SN76489AN.
---
--- $Id: sn76489_latch_ctrl.vhd,v 1.6 2006/02/27 20:30:10 arnim Exp $
---
--- Latch Control Unit
---
--------------------------------------------------------------------------------
---
--- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity sn76489_latch_ctrl is
-
-  port (
-    clock_i    : in  std_logic;
-    clk_en_i   : in  boolean;
-    res_n_i    : in  std_logic;
-    ce_n_i     : in  std_logic;
-    we_n_i     : in  std_logic;
-    d_i        : in  std_logic_vector(0 to 7);
-    ready_o    : out std_logic;
-    tone1_we_o : out boolean;
-    tone2_we_o : out boolean;
-    tone3_we_o : out boolean;
-    noise_we_o : out boolean;
-    r2_o       : out std_logic
-  );
-
-end sn76489_latch_ctrl;
-
-
-library ieee;
-use ieee.numeric_std.all;
-
-architecture rtl of sn76489_latch_ctrl is
-
-  signal reg_q   : std_logic_vector(0 to 2);
-  signal we_q    : boolean;
-  signal ready_q : std_logic;
-
-begin
-
-  -----------------------------------------------------------------------------
-  -- Process seq
-  --
-  -- Purpose:
-  --   Implements the sequential elements.
-  --
-  seq: process (clock_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      reg_q     <= (others => '0');
-      we_q      <= false;
-      ready_q   <= '0';
-
-    elsif clock_i'event and clock_i = '1' then
-      -- READY Flag Output ----------------------------------------------------
-      if ready_q = '0' and we_q then
-        if clk_en_i then
-          -- assert READY when write access happened
-          ready_q <= '1';
-        end if;
-      elsif ce_n_i = '1' then
-        -- deassert READY when access has finished
-        ready_q <= '0';
-      end if;
-
-      -- Register Selection ---------------------------------------------------
-      if ce_n_i = '0' and we_n_i = '0' then
-        if clk_en_i then
-          if d_i(0) = '1' then
-            reg_q <= d_i(1 to 3);
-          end if;
-          we_q  <= true;
-        end if;
-      else
-        we_q  <= false;
-      end if;
-
-    end if;
-  end process seq;
-  --
-  -----------------------------------------------------------------------------
-
-
-  -----------------------------------------------------------------------------
-  -- Output mapping
-  -----------------------------------------------------------------------------
-  tone1_we_o <= reg_q(0 to 1) = "00" and we_q;
-  tone2_we_o <= reg_q(0 to 1) = "01" and we_q;
-  tone3_we_o <= reg_q(0 to 1) = "10" and we_q;
-  noise_we_o <= reg_q(0 to 1) = "11" and we_q;
-
-  r2_o       <= reg_q(2);
-
-  ready_o    <=   ready_q
-                when ce_n_i = '0' else
-                  '1';
-
-end rtl;
diff --git a/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/sn76489_noise.vhd b/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/sn76489_noise.vhd
deleted file mode 100644
index 688bdd56..00000000
--- a/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/sn76489_noise.vhd	
+++ /dev/null
@@ -1,278 +0,0 @@
--------------------------------------------------------------------------------
---
--- Synthesizable model of TI's SN76489AN.
---
--- $Id: sn76489_noise.vhd,v 1.6 2006/02/27 20:30:10 arnim Exp $
---
--- Noise Generator
---
--------------------------------------------------------------------------------
---
--- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity sn76489_noise is
-
-  port (
-    clock_i    : in  std_logic;
-    clk_en_i   : in  boolean;
-    res_n_i    : in  std_logic;
-    we_i       : in  boolean;
-    d_i        : in  std_logic_vector(0 to 7);
-    r2_i       : in  std_logic;
-    tone3_ff_i : in  std_logic;
-    noise_o    : out signed(0 to 7)
-  );
-
-end sn76489_noise;
-
-architecture rtl of sn76489_noise is
-
-  signal nf_q       : std_logic_vector(0 to 1);
-  signal fb_q       : std_logic;
-  signal a_q        : std_logic_vector(0 to 3);
-  signal freq_cnt_q : unsigned(0 to 6);
-  signal freq_ff_q  : std_logic;
-
-  signal shift_source_s,
-         shift_source_q    : std_logic;
-  signal shift_rise_edge_s : boolean;
-
-  signal lfsr_q            : std_logic_vector(0 to 15);
-
-  signal freq_s      : signed(0 to 1);
-
-begin
-
-  -----------------------------------------------------------------------------
-  -- Process cpu_regs
-  --
-  -- Purpose:
-  --   Implements the registers writable by the CPU.
-  --
-  cpu_regs: process (clock_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      nf_q <= (others => '0');
-      fb_q <= '0';
-      a_q  <= (others => '1');
-
-    elsif clock_i'event and clock_i = '1' then
-      if clk_en_i and we_i then
-        if r2_i = '0' then
-          -- access to control register
-          -- both access types can write to the control register!
-          nf_q <= d_i(6 to 7);
-          fb_q <= d_i(5);
-
-        else
-          -- access to attenuator register
-          -- both access types can write to the attenuator register!
-          a_q <= d_i(4 to 7);
-
-        end if;
-      end if;
-    end if;
-  end process cpu_regs;
-  --
-  -----------------------------------------------------------------------------
-
-
-  -----------------------------------------------------------------------------
-  -- Process freq_gen
-  --
-  -- Purpose:
-  --   Implements the frequency generation components.
-  --
-  freq_gen: process (clock_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      freq_cnt_q <= (others => '0');
-      freq_ff_q  <= '0';
-
-    elsif clock_i'event and clock_i = '1' then
-      if clk_en_i then
-        if freq_cnt_q = 0 then
-          -- reload frequency counter according to NF setting
-          case nf_q is
-            when "00" =>
-              freq_cnt_q <= to_unsigned(16 * 2 - 1, freq_cnt_q'length);
-            when "01" =>
-              freq_cnt_q <= to_unsigned(16 * 4 - 1, freq_cnt_q'length);
-            when "10" =>
-              freq_cnt_q <= to_unsigned(16 * 8 - 1, freq_cnt_q'length);
-            when others =>
-              null;
-          end case;
-
-          freq_ff_q <= not freq_ff_q;
-
-        else
-          -- decrement frequency counter
-          freq_cnt_q <= freq_cnt_q - 1;
-
-        end if;
-
-      end if;
-    end if;
-  end process freq_gen;
-  --
-  -----------------------------------------------------------------------------
-
-
-  -----------------------------------------------------------------------------
-  -- Multiplex the source of the LFSR's shift enable
-  -----------------------------------------------------------------------------
-  shift_source_s <=   tone3_ff_i
-                    when nf_q = "11" else
-                      freq_ff_q;
-
-  -----------------------------------------------------------------------------
-  -- Process rise_edge
-  --
-  -- Purpose:
-  --   Detect the rising edge of the selected LFSR shift source.
-  --
-  rise_edge: process (clock_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      shift_source_q <= '0';
-
-    elsif clock_i'event and clock_i = '1' then
-      if clk_en_i then
-        shift_source_q <= shift_source_s;
-      end if;
-    end if;
-  end process rise_edge;
-  --
-  -----------------------------------------------------------------------------
-
-  -- detect rising edge on shift source
-  shift_rise_edge_s <= shift_source_q = '0' and shift_source_s = '1';
-
-
-  -----------------------------------------------------------------------------
-  -- Process lfsr
-  --
-  -- Purpose:
-  --   Implements the LFSR that generates noise.
-  --   Note: This implementation shifts the register right, i.e. from index
-  --         15 towards 0 => bit 15 is the input, bit 0 is the output
-  --
-  --   Tapped bits according to MAME's sn76496.c, implemented in function
-  --   lfsr_tapped_f.
-  --
-  lfsr: process (clock_i, res_n_i)
-
-    function lfsr_tapped_f(lfsr : in std_logic_vector) return std_logic is
-      constant tapped_bits_c : std_logic_vector(0 to 15)
-        -- tapped bits are 0, 2, 15
-        := "1010000000000001";
-      variable parity_v : std_logic;
-    begin
-      parity_v := '0';
-
-      for idx in lfsr'low to lfsr'high loop
-        parity_v := parity_v xor (lfsr(idx) and tapped_bits_c(idx));
-      end loop;
-
-      return parity_v;
-    end;
-
-  begin
-    if res_n_i = '0' then
-      -- reset LFSR to "0000000000000001"
-      lfsr_q               <= (others => '0');
-      lfsr_q(lfsr_q'right) <= '1';
-
-    elsif clock_i'event and clock_i = '1' then
-      if clk_en_i then
-        if we_i and r2_i = '0' then
-          -- write to noise register
-          -- -> reset LFSR
-          lfsr_q               <= (others => '0');
-          lfsr_q(lfsr_q'right) <= '1';
-
-        elsif shift_rise_edge_s then
-
-          -- shift LFSR left towards MSB
-          for idx in lfsr_q'right-1 downto lfsr_q'left loop
-            lfsr_q(idx) <= lfsr_q(idx+1);
-          end loop;
-
-          -- determine input bit
-          if fb_q = '0' then
-            -- "Periodic" Noise
-            -- -> input to LFSR is output
-            lfsr_q(lfsr_q'right) <= lfsr_q(lfsr_q'left);
-          else
-            -- "White" Noise
-            -- -> input to LFSR is parity of tapped bits
-            lfsr_q(lfsr_q'right) <= lfsr_tapped_f(lfsr_q);
-          end if;
-
-        end if;
-
-      end if;
-    end if;
-  end process lfsr;
-  --
-  -----------------------------------------------------------------------------
-
-
-  -----------------------------------------------------------------------------
-  -- Map output of LFSR to signed value for attenuator.
-  -----------------------------------------------------------------------------
-  freq_s <=   to_signed(+1, 2)
-            when lfsr_q(0) = '1' else
-              to_signed( 0, 2);
-
-
-  -----------------------------------------------------------------------------
-  -- The attenuator itself
-  -----------------------------------------------------------------------------
-  attenuator_b : entity work.sn76489_attenuator
-    port map (
-      attenuation_i => a_q,
-      factor_i      => freq_s,
-      product_o     => noise_o
-    );
-
-end rtl;
diff --git a/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/sn76489_tone.vhd b/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/sn76489_tone.vhd
deleted file mode 100644
index 3658efcc..00000000
--- a/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/sn76489_tone.vhd	
+++ /dev/null
@@ -1,188 +0,0 @@
--------------------------------------------------------------------------------
---
--- Synthesizable model of TI's SN76489AN.
---
--- $Id: sn76489_tone.vhd,v 1.5 2006/02/27 20:30:10 arnim Exp $
---
--- Tone Generator
---
--------------------------------------------------------------------------------
---
--- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity sn76489_tone is
-
-  port (
-    clock_i  : in  std_logic;
-    clk_en_i : in  boolean;
-    res_n_i  : in  std_logic;
-    we_i     : in  boolean;
-    d_i      : in  std_logic_vector(0 to 7);
-    r2_i     : in  std_logic;
-    ff_o     : out std_logic;
-    tone_o   : out signed(0 to 7)
-  );
-
-end sn76489_tone;
-
-architecture rtl of sn76489_tone is
-
-  signal f_q        : std_logic_vector(0 to 9);
-  signal a_q        : std_logic_vector(0 to 3);
-  signal freq_cnt_q : unsigned(0 to 9);
-  signal freq_ff_q  : std_logic;
-
-  signal freq_s     : signed(0 to 1);
-
-  function all_zero(a : in std_logic_vector) return boolean is
-    variable result_v : boolean;
-  begin
-    result_v := true;
-
-    for idx in a'low to a'high loop
-      if a(idx) /= '0' then
-        result_v := false;
-      end if;
-    end loop;
-
-    return result_v;
-  end;
-
-begin
-
-  -----------------------------------------------------------------------------
-  -- Process cpu_regs
-  --
-  -- Purpose:
-  --   Implements the registers writable by the CPU.
-  --
-  cpu_regs: process (clock_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      f_q <= (others => '0');
-      a_q <= (others => '1');
-
-    elsif clock_i'event and clock_i = '1' then
-      if clk_en_i and we_i then
-        if r2_i = '0' then
-          -- access to frequency register
-          if d_i(0) = '0' then
-            f_q(0 to 5) <= d_i(2 to 7);
-          else
-            f_q(6 to 9) <= d_i(4 to 7);
-          end if;
-
-        else
-          -- access to attenuator register
-          -- both access types can write to the attenuator register!
-          a_q <= d_i(4 to 7);
-
-        end if;
-      end if;
-    end if;
-  end process cpu_regs;
-  --
-  -----------------------------------------------------------------------------
-
-
-  -----------------------------------------------------------------------------
-  -- Process freq_gen
-  --
-  -- Purpose:
-  --   Implements the frequency generation components.
-  --
-  freq_gen: process (clock_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      freq_cnt_q <= (others => '0');
-      freq_ff_q  <= '0';
-
-    elsif clock_i'event and clock_i = '1' then
-      if clk_en_i then
-        if freq_cnt_q = 0 then
-          -- update counter from frequency register
-          freq_cnt_q <= unsigned(f_q);
-
-          -- and toggle the frequency flip-flop if enabled
-          if not all_zero(f_q) then
-            freq_ff_q <= not freq_ff_q;
-          else
-            -- if frequency setting is 0, then keep flip-flop at +1
-            freq_ff_q <= '1';
-          end if;
-
-        else
-          -- decrement frequency counter
-          freq_cnt_q <= freq_cnt_q - 1;
-
-        end if;
-      end if;
-    end if;
-  end process freq_gen;
-  --
-  -----------------------------------------------------------------------------
-
-
-  -----------------------------------------------------------------------------
-  -- Map frequency flip-flop to signed value for attenuator.
-  -----------------------------------------------------------------------------
-  freq_s <=   to_signed(+1, 2)
-            when freq_ff_q = '1' else
-              to_signed(-1, 2);
-
-
-  -----------------------------------------------------------------------------
-  -- The attenuator itself
-  -----------------------------------------------------------------------------
-  attenuator_b : entity work.sn76489_attenuator
-    port map (
-      attenuation_i => a_q,
-      factor_i      => freq_s,
-      product_o     => tone_o
-    );
-
-
-  -----------------------------------------------------------------------------
-  -- Output mapping
-  -----------------------------------------------------------------------------
-  ff_o <= freq_ff_q;
-
-end rtl;
diff --git a/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/sn76489_top.vhd b/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/sn76489_top.vhd
deleted file mode 100644
index c26d0e1a..00000000
--- a/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/sn76489_top.vhd	
+++ /dev/null
@@ -1,200 +0,0 @@
--------------------------------------------------------------------------------
---
--- Synthesizable model of TI's SN76489AN.
---
--- $Id: sn76489_top.vhd,v 1.9 2006/02/27 20:30:10 arnim Exp $
---
--- Chip Toplevel
---
--- References:
---
---   * TI Data sheet SN76489.pdf
---     ftp://ftp.whtech.com/datasheets%20&%20manuals/SN76489.pdf
---
---   * John Kortink's article on the SN76489:
---     http://web.inter.nl.net/users/J.Kortink/home/articles/sn76489/
---
---   * Maxim's "SN76489 notes" in
---     http://www.smspower.org/maxim/docs/SN76489.txt
---
--------------------------------------------------------------------------------
---
--- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library ieee;
-use ieee.numeric_std.all;
-
-entity sn76489_top is
-
-  generic (
-    clock_div_16_g : integer := 1
-  );
-  port (
-    clock_i    : in  std_logic;
-    clock_en_i : in  std_logic;
-    res_n_i    : in  std_logic;
-    ce_n_i     : in  std_logic;
-    we_n_i     : in  std_logic;
-    ready_o    : out std_logic;
-    d_i        : in  std_logic_vector(0 to 7);
-    aout_o     : out signed(0 to 7)
-  );
-
-end sn76489_top;
-
-architecture struct of sn76489_top is
-
-  signal clk_en_s    : boolean;
-
-  signal tone1_we_s,
-         tone2_we_s,
-         tone3_we_s,
-         noise_we_s  : boolean;
-  signal r2_s        : std_logic;
-
-  signal tone1_s,
-         tone2_s,
-         tone3_s,
-         noise_s     : signed(0 to 7);
-
-  signal tone3_ff_s  : std_logic;
-
-begin
-
-  -----------------------------------------------------------------------------
-  -- Clock Divider
-  -----------------------------------------------------------------------------
-  clock_div_b : entity work.sn76489_clock_div
-    generic map (
-      clock_div_16_g => clock_div_16_g
-    )
-    port map (
-      clock_i    => clock_i,
-      clock_en_i => clock_en_i,
-      res_n_i    => res_n_i,
-      clk_en_o   => clk_en_s
-    );
-
-
-  -----------------------------------------------------------------------------
-  -- Latch Control = CPU Interface
-  -----------------------------------------------------------------------------
-  latch_ctrl_b : entity work.sn76489_latch_ctrl
-    port map (
-      clock_i    => clock_i,
-      clk_en_i   => clk_en_s,
-      res_n_i    => res_n_i,
-      ce_n_i     => ce_n_i,
-      we_n_i     => we_n_i,
-      d_i        => d_i,
-      ready_o    => ready_o,
-      tone1_we_o => tone1_we_s,
-      tone2_we_o => tone2_we_s,
-      tone3_we_o => tone3_we_s,
-      noise_we_o => noise_we_s,
-      r2_o       => r2_s
-    );
-
-
-  -----------------------------------------------------------------------------
-  -- Tone Channel 1
-  -----------------------------------------------------------------------------
-  tone1_b : entity work.sn76489_tone
-    port map (
-      clock_i  => clock_i,
-      clk_en_i => clk_en_s,
-      res_n_i  => res_n_i,
-      we_i     => tone1_we_s,
-      d_i      => d_i,
-      r2_i     => r2_s,
-      ff_o     => open,
-      tone_o   => tone1_s
-    );
-
-  -----------------------------------------------------------------------------
-  -- Tone Channel 2
-  -----------------------------------------------------------------------------
-  tone2_b : entity work.sn76489_tone
-    port map (
-      clock_i  => clock_i,
-      clk_en_i => clk_en_s,
-      res_n_i  => res_n_i,
-      we_i     => tone2_we_s,
-      d_i      => d_i,
-      r2_i     => r2_s,
-      ff_o     => open,
-      tone_o   => tone2_s
-    );
-
-  -----------------------------------------------------------------------------
-  -- Tone Channel 3
-  -----------------------------------------------------------------------------
-  tone3_b : entity work.sn76489_tone
-    port map (
-      clock_i  => clock_i,
-      clk_en_i => clk_en_s,
-      res_n_i  => res_n_i,
-      we_i     => tone3_we_s,
-      d_i      => d_i,
-      r2_i     => r2_s,
-      ff_o     => tone3_ff_s,
-      tone_o   => tone3_s
-    );
-
-  -----------------------------------------------------------------------------
-  -- Noise Channel
-  -----------------------------------------------------------------------------
-  noise_b : entity work.sn76489_noise
-    port map (
-      clock_i    => clock_i,
-      clk_en_i   => clk_en_s,
-      res_n_i    => res_n_i,
-      we_i       => noise_we_s,
-      d_i        => d_i,
-      r2_i       => r2_s,
-      tone3_ff_i => tone3_ff_s,
-      noise_o    => noise_s
-    );
-
-
-  aout_o <= tone1_s + tone2_s + tone3_s + noise_s;
-
-end struct;
diff --git a/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/LadyBug.qsf b/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/LadyBug.qsf
index a68a7052..18c79691 100644
--- a/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/LadyBug.qsf	
+++ b/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/LadyBug.qsf	
@@ -137,16 +137,17 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 
 		# Incremental Compilation Assignments
 		# ===================================
-		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 
 	# end DESIGN_PARTITION(Top)
 	# -------------------------
 
 # end ENTITY(LadyBug)
 # -------------------
-set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
+set_global_assignment -name ENABLE_SIGNALTAP OFF
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/snd.stp
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/LadyBug.sv
 set_global_assignment -name VHDL_FILE rtl/ladybug.vhd
 set_global_assignment -name VHDL_FILE rtl/ladybug_video_unit.vhd
@@ -166,13 +167,7 @@ set_global_assignment -name VHDL_FILE rtl/ladybug_chutes.vhd
 set_global_assignment -name VHDL_FILE rtl/ladybug_chute.vhd
 set_global_assignment -name VHDL_FILE rtl/ladybug_char.vhd
 set_global_assignment -name VHDL_FILE rtl/ladybug_addr_dec.vhd
-set_global_assignment -name VHDL_FILE rtl/sound/ladybug_sound_unit.vhd
-set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_top.vhd
-set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_tone.vhd
-set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_noise.vhd
-set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_latch_ctrl.vhd
-set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_clock_div.vhd
-set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_attenuator.vhd
+set_global_assignment -name VHDL_FILE rtl/ladybug_sound_unit.vhd
 set_global_assignment -name VHDL_FILE rtl/ROM/rom_sprite_u.vhd
 set_global_assignment -name VHDL_FILE rtl/ROM/rom_sprite_l.vhd
 set_global_assignment -name VHDL_FILE rtl/ROM/rom_cpu3.vhd
@@ -184,15 +179,12 @@ set_global_assignment -name VHDL_FILE rtl/ROM/prom_decrypt.vhd
 set_global_assignment -name VHDL_FILE rtl/ROM/prom_10_3.vhd
 set_global_assignment -name VHDL_FILE rtl/ROM/prom_10_2.vhd
 set_global_assignment -name VHDL_FILE rtl/ROM/prom_10_1.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80a.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
 set_global_assignment -name VHDL_FILE rtl/ttl_393.vhd
 set_global_assignment -name VHDL_FILE rtl/ttl_175.vhd
 set_global_assignment -name VHDL_FILE rtl/spram.vhd
 set_global_assignment -name VHDL_FILE rtl/dpram.vhd
 set_global_assignment -name QIP_FILE rtl/pll.qip
+set_global_assignment -name QIP_FILE ../../../common/Sound/sn76489/sn76489.qip
+set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
+set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/LadyBug.sv b/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/LadyBug.sv
index 48249a4a..3a05391a 100644
--- a/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/LadyBug.sv	
+++ b/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/LadyBug.sv	
@@ -45,10 +45,12 @@ localparam CONF_STR = {
 	"O2,Rotate Controls,Off,On;",
 	"O34,Scanlines,Off,25%,50%,75%;",
 	"O5,Blend,Off,On;",
-	"T6,Reset;",
+	"T0,Reset;",
 	"V,v1.10.",`BUILD_DATE
 };
 
+wire rotate = status[2];
+
 assign LED = 1;
 assign AUDIO_R = AUDIO_L;
 
@@ -68,17 +70,43 @@ wire  [7:0] joystick_0;
 wire  [7:0] joystick_1;
 wire        scandoublerD;
 wire        ypbpr;
-wire [10:0] ps2_key;
-reg	[7:0] audio;
-wire 			hb, vb;
+wire        no_csync;
+wire        key_pressed;
+wire  [7:0] key_code;
+wire        key_strobe;
+
+user_io #(
+	.STRLEN(($size(CONF_STR)>>3)))
+user_io(
+	.clk_sys        (clk_sys        ),
+	.conf_str       (CONF_STR       ),
+	.SPI_CLK        (SPI_SCK        ),
+	.SPI_SS_IO      (CONF_DATA0     ),
+	.SPI_MISO       (SPI_DO         ),
+	.SPI_MOSI       (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches       (switches       ),
+	.scandoubler_disable (scandoublerD),
+	.ypbpr          (ypbpr          ),
+	.no_csync       (no_csync       ),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
+	.key_code       (key_code       ),
+	.joystick_0     (joystick_0     ),
+	.joystick_1     (joystick_1     ),
+	.status         (status         )
+);
+
+wire  [8:0] audio;
+wire        hb, vb;
 wire        blankn = ~(hb | vb);
-wire 			ce_vid;
-wire 			hs, vs;
+wire        ce_vid;
+wire        hs, vs;
 wire  [1:0] r,g,b;
 
 ladybugt ladybug(
 	.CLK_IN(clk_sys),
-	.I_RESET(status[0] | status[6] | buttons[1]),
+	.I_RESET(status[0] | buttons[1]),
 	.O_PIXCE(ce_vid),
 	.O_VIDEO_R(r),
 	.O_VIDEO_G(g),
@@ -88,17 +116,17 @@ ladybugt ladybug(
 	.O_VBLANK(vb),
 	.O_HBLANK(hb),
 	.O_AUDIO(audio),	
-	.but_coin_s(~{1'b0,btn_coin}),
-	.but_fire_s(~{1'b0,m_fire}),
-	.but_bomb_s(~{1'b0,m_bomb}),
-	.but_tilt_s(~{1'b0,1'b0}),
-	.but_select_s(~{btn_two_players, btn_one_player}),
-	.but_up_s(~{1'b0,m_up}),
-	.but_down_s(~{1'b0,m_down}),
-	.but_left_s(~{1'b0,m_left}),
-	.but_right_s(~{1'b0,m_right})
+	.but_coin_s(~{m_coin2,m_coin1}),
+	.but_fire_s(~{m_fire2A,m_fireA}),
+	.but_bomb_s(~{m_fire2B,m_fireB}),
+	.but_tilt_s(~{m_tilt,m_tilt}),
+	.but_select_s(~{m_two_players, m_one_player}),
+	.but_up_s(~{m_up2,m_up}),
+	.but_down_s(~{m_down2,m_down}),
+	.but_left_s(~{m_left2,m_left}),
+	.but_right_s(~{m_right2,m_right})
 	);
-	
+
 mist_video #(.COLOR_DEPTH(2),.SD_HCNT_WIDTH(10)) mist_video(
 	.clk_sys(clk_sys),
 	.SPI_SCK(SPI_SCK),
@@ -114,84 +142,40 @@ mist_video #(.COLOR_DEPTH(2),.SD_HCNT_WIDTH(10)) mist_video(
 	.VGA_B(VGA_B),
 	.VGA_VS(VGA_VS),
 	.VGA_HS(VGA_HS),
-	.rotate({1'b0,status[2]}),
+	.rotate({1'b0,rotate}),
 	.ce_divider(1'b1),
 	.blend(status[5]),
 	.scandoubler_disable(scandoublerD),
 	.scanlines(status[4:3]),
-	.ypbpr(ypbpr)
+	.ypbpr(ypbpr),
+	.no_csync(no_csync)
 );
 
-user_io #(
-	.STRLEN(($size(CONF_STR)>>3)))
-user_io(
-	.clk_sys        (clk_sys        ),
-	.conf_str       (CONF_STR       ),
-	.SPI_CLK        (SPI_SCK        ),
-	.SPI_SS_IO      (CONF_DATA0     ),
-	.SPI_MISO       (SPI_DO         ),
-	.SPI_MOSI       (SPI_DI         ),
-	.buttons        (buttons        ),
-	.switches       (switches       ),
-	.scandoubler_disable (scandoublerD),
-	.ypbpr          (ypbpr          ),
-	.key_strobe     (key_strobe     ),
-	.key_pressed    (key_pressed    ),
-	.key_code       (key_code       ),
-	.joystick_0     (joystick_0     ),
-	.joystick_1     (joystick_1     ),
-	.status         (status         )
-);
-
-dac dac(
+dac #(9) dac(
 	.clk_i(clk_sys),
 	.res_n_i(1),
-	.dac_i({~audio[7], audio[6:0]}),
+	.dac_i(audio),
 	.dac_o(AUDIO_L)
 	);
 
-//wire m_up     = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[4] | joystick_0[3] | joystick_1[3];
-//wire m_down   = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[5] | joystick_0[2] | joystick_1[2];
-//wire m_left   = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[6] | joystick_0[1] | joystick_1[1];
-//wire m_right  = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[7] | joystick_0[0] | joystick_1[0];
-
-wire m_up     = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3];
-wire m_down   = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2];
-wire m_left   = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1];
-wire m_right  = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0];
-
-wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
-wire m_bomb   = btn_fire2 | joystick_0[5] | joystick_1[5];
-
-reg btn_one_player = 0;
-reg btn_two_players = 0;
-reg btn_left = 0;
-reg btn_right = 0;
-reg btn_down = 0;
-reg btn_up = 0;
-reg btn_fire1 = 0;
-reg btn_fire2 = 0;
-reg btn_fire3 = 0;
-reg btn_coin  = 0;
-wire       key_pressed;
-wire [7:0] key_code;
-wire       key_strobe;
-
-always @(posedge clk_sys) begin
-	if(key_strobe) begin
-		case(key_code)
-			'h75: btn_up         	<= key_pressed; // up
-			'h72: btn_down        	<= key_pressed; // down
-			'h6B: btn_left      		<= key_pressed; // left
-			'h74: btn_right       	<= key_pressed; // right
-			'h76: btn_coin				<= key_pressed; // ESC
-			'h05: btn_one_player   	<= key_pressed; // F1
-			'h06: btn_two_players  	<= key_pressed; // F2
-			'h14: btn_fire3 			<= key_pressed; // ctrl
-			'h11: btn_fire2 			<= key_pressed; // alt
-			'h29: btn_fire1   		<= key_pressed; // Space
-		endcase
-	end
-end
+wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
+wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
+wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
+        
+arcade_inputs inputs (
+	.clk         ( clk_sys     ),
+	.key_strobe  ( key_strobe  ),
+	.key_pressed ( key_pressed ),
+	.key_code    ( key_code    ),
+	.joystick_0  ( joystick_0  ),
+	.joystick_1  ( joystick_1  ),
+	.rotate      ( rotate      ),
+	.orientation ( 2'b01       ),
+	.joyswap     ( 1'b0        ),
+	.oneplayer   ( 1'b1        ),
+	.controls    ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
+	.player1     ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
+	.player2     ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
+);
 
 endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/cpu/T80.vhd
deleted file mode 100644
index c3e13c5c..00000000
--- a/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/cpu/T80.vhd	
+++ /dev/null
@@ -1,1094 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
---
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0210 : Fixed wait and halt
---
---      0211 : Fixed Refresh addition and IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
---      0235 : Added clock enable and IM 2 fix by Mike Johnson
---
---      0237 : Changed 8080 I/O address output, added IntE output
---
---      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
---      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
---      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
---      0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
-  generic(
-    Mode   : integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-    IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-    Flag_C : integer := 0;
-    Flag_N : integer := 1;
-    Flag_P : integer := 2;
-    Flag_X : integer := 3;
-    Flag_H : integer := 4;
-    Flag_Y : integer := 5;
-    Flag_Z : integer := 6;
-    Flag_S : integer := 7
-    );
-  port(
-    RESET_n    : in  std_logic;
-    CLK_n      : in  std_logic;
-    CEN        : in  std_logic;
-    WAIT_n     : in  std_logic;
-    INT_n      : in  std_logic;
-    NMI_n      : in  std_logic;
-    BUSRQ_n    : in  std_logic;
-    M1_n       : out std_logic;
-    IORQ       : out std_logic;
-    NoRead     : out std_logic;
-    Write      : out std_logic;
-    RFSH_n     : out std_logic;
-    HALT_n     : out std_logic;
-    BUSAK_n    : out std_logic;
-    A          : out std_logic_vector(15 downto 0);
-    DInst      : in  std_logic_vector(7 downto 0);
-    DI         : in  std_logic_vector(7 downto 0);
-    DO         : out std_logic_vector(7 downto 0);
-    MC         : out std_logic_vector(2 downto 0);
-    TS         : out std_logic_vector(2 downto 0);
-    IntCycle_n : out std_logic;
-    IntE       : out std_logic;
-    Stop       : out std_logic
-    );
-end T80;
-
-architecture rtl of T80 is
-
-  constant aNone              : std_logic_vector(2 downto 0) := "111";
-  constant aBC                : std_logic_vector(2 downto 0) := "000";
-  constant aDE                : std_logic_vector(2 downto 0) := "001";
-  constant aXY                : std_logic_vector(2 downto 0) := "010";
-  constant aIOA               : std_logic_vector(2 downto 0) := "100";
-  constant aSP                : std_logic_vector(2 downto 0) := "101";
-  constant aZI                : std_logic_vector(2 downto 0) := "110";
-
-  -- Registers
-  signal ACC, F               : std_logic_vector(7 downto 0);
-  signal Ap, Fp               : std_logic_vector(7 downto 0);
-  signal I                    : std_logic_vector(7 downto 0);
-  signal R                    : unsigned(7 downto 0);
-  signal SP, PC               : unsigned(15 downto 0);
-
-  signal RegDIH               : std_logic_vector(7 downto 0);
-  signal RegDIL               : std_logic_vector(7 downto 0);
-  signal RegBusA              : std_logic_vector(15 downto 0);
-  signal RegBusB              : std_logic_vector(15 downto 0);
-  signal RegBusC              : std_logic_vector(15 downto 0);
-  signal RegAddrA_r           : std_logic_vector(2 downto 0);
-  signal RegAddrA             : std_logic_vector(2 downto 0);
-  signal RegAddrB_r           : std_logic_vector(2 downto 0);
-  signal RegAddrB             : std_logic_vector(2 downto 0);
-  signal RegAddrC             : std_logic_vector(2 downto 0);
-  signal RegWEH               : std_logic;
-  signal RegWEL               : std_logic;
-  signal Alternate            : std_logic;
-
-  -- Help Registers
-  signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
-  signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
-  signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
-  signal RegBusA_r            : std_logic_vector(15 downto 0);
-
-  signal ID16                 : signed(15 downto 0);
-  signal Save_Mux             : std_logic_vector(7 downto 0);
-
-  signal TState               : unsigned(2 downto 0);
-  signal MCycle               : std_logic_vector(2 downto 0);
-  signal IntE_FF1             : std_logic;
-  signal IntE_FF2             : std_logic;
-  signal Halt_FF              : std_logic;
-  signal BusReq_s             : std_logic;
-  signal BusAck               : std_logic;
-  signal ClkEn                : std_logic;
-  signal NMI_s                : std_logic;
-  signal INT_s                : std_logic;
-  signal IStatus              : std_logic_vector(1 downto 0);
-
-  signal DI_Reg               : std_logic_vector(7 downto 0);
-  signal T_Res                : std_logic;
-  signal XY_State             : std_logic_vector(1 downto 0);
-  signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
-  signal NextIs_XY_Fetch      : std_logic;
-  signal XY_Ind               : std_logic;
-  signal No_BTR               : std_logic;
-  signal BTR_r                : std_logic;
-  signal Auto_Wait            : std_logic;
-  signal Auto_Wait_t1         : std_logic;
-  signal Auto_Wait_t2         : std_logic;
-  signal IncDecZ              : std_logic;
-
-  -- ALU signals
-  signal BusB                 : std_logic_vector(7 downto 0);
-  signal BusA                 : std_logic_vector(7 downto 0);
-  signal ALU_Q                : std_logic_vector(7 downto 0);
-  signal F_Out                : std_logic_vector(7 downto 0);
-
-  -- Registered micro code outputs
-  signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
-  signal Arith16_r            : std_logic;
-  signal Z16_r                : std_logic;
-  signal ALU_Op_r             : std_logic_vector(3 downto 0);
-  signal Save_ALU_r           : std_logic;
-  signal PreserveC_r          : std_logic;
-  signal MCycles              : std_logic_vector(2 downto 0);
-
-  -- Micro code outputs
-  signal MCycles_d            : std_logic_vector(2 downto 0);
-  signal TStates              : std_logic_vector(2 downto 0);
-  signal IntCycle             : std_logic;
-  signal NMICycle             : std_logic;
-  signal Inc_PC               : std_logic;
-  signal Inc_WZ               : std_logic;
-  signal IncDec_16            : std_logic_vector(3 downto 0);
-  signal Prefix               : std_logic_vector(1 downto 0);
-  signal Read_To_Acc          : std_logic;
-  signal Read_To_Reg          : std_logic;
-  signal Set_BusB_To          : std_logic_vector(3 downto 0);
-  signal Set_BusA_To          : std_logic_vector(3 downto 0);
-  signal ALU_Op               : std_logic_vector(3 downto 0);
-  signal Save_ALU             : std_logic;
-  signal PreserveC            : std_logic;
-  signal Arith16              : std_logic;
-  signal Set_Addr_To          : std_logic_vector(2 downto 0);
-  signal Jump                 : std_logic;
-  signal JumpE                : std_logic;
-  signal JumpXY               : std_logic;
-  signal Call                 : std_logic;
-  signal RstP                 : std_logic;
-  signal LDZ                  : std_logic;
-  signal LDW                  : std_logic;
-  signal LDSPHL               : std_logic;
-  signal IORQ_i               : std_logic;
-  signal Special_LD           : std_logic_vector(2 downto 0);
-  signal ExchangeDH           : std_logic;
-  signal ExchangeRp           : std_logic;
-  signal ExchangeAF           : std_logic;
-  signal ExchangeRS           : std_logic;
-  signal I_DJNZ               : std_logic;
-  signal I_CPL                : std_logic;
-  signal I_CCF                : std_logic;
-  signal I_SCF                : std_logic;
-  signal I_RETN               : std_logic;
-  signal I_BT                 : std_logic;
-  signal I_BC                 : std_logic;
-  signal I_BTR                : std_logic;
-  signal I_RLD                : std_logic;
-  signal I_RRD                : std_logic;
-  signal I_INRC               : std_logic;
-  signal SetDI                : std_logic;
-	signal SetEI                : std_logic;
-	signal IMode                : std_logic_vector(1 downto 0);
-	signal Halt                 : std_logic;
-	signal XYbit_undoc          : std_logic;
-
-
-begin
-
-  mcode : T80_MCode
-    generic map(
-      Mode   => Mode,
-      Flag_C => Flag_C,
-      Flag_N => Flag_N,
-      Flag_P => Flag_P,
-      Flag_X => Flag_X,
-      Flag_H => Flag_H,
-      Flag_Y => Flag_Y,
-      Flag_Z => Flag_Z,
-      Flag_S => Flag_S)
-    port map(
-      IR          => IR,
-      ISet        => ISet,
-      MCycle      => MCycle,
-      F           => F,
-      NMICycle    => NMICycle,
-      IntCycle    => IntCycle,
-      XY_State    => XY_State,
-      MCycles     => MCycles_d,
-      TStates     => TStates,
-      Prefix      => Prefix,
-      Inc_PC      => Inc_PC,
-      Inc_WZ      => Inc_WZ,
-      IncDec_16   => IncDec_16,
-      Read_To_Acc => Read_To_Acc,
-      Read_To_Reg => Read_To_Reg,
-      Set_BusB_To => Set_BusB_To,
-      Set_BusA_To => Set_BusA_To,
-      ALU_Op      => ALU_Op,
-      Save_ALU    => Save_ALU,
-      PreserveC   => PreserveC,
-      Arith16     => Arith16,
-      Set_Addr_To => Set_Addr_To,
-      IORQ        => IORQ_i,
-      Jump        => Jump,
-      JumpE       => JumpE,
-      JumpXY      => JumpXY,
-      Call        => Call,
-      RstP        => RstP,
-      LDZ         => LDZ,
-      LDW         => LDW,
-      LDSPHL      => LDSPHL,
-      Special_LD  => Special_LD,
-      ExchangeDH  => ExchangeDH,
-      ExchangeRp  => ExchangeRp,
-      ExchangeAF  => ExchangeAF,
-      ExchangeRS  => ExchangeRS,
-      I_DJNZ      => I_DJNZ,
-      I_CPL       => I_CPL,
-      I_CCF       => I_CCF,
-      I_SCF       => I_SCF,
-      I_RETN      => I_RETN,
-      I_BT        => I_BT,
-      I_BC        => I_BC,
-      I_BTR       => I_BTR,
-      I_RLD       => I_RLD,
-      I_RRD       => I_RRD,
-      I_INRC      => I_INRC,
-      SetDI       => SetDI,
-      SetEI       => SetEI,
-      IMode       => IMode,
-      Halt        => Halt,
-      NoRead      => NoRead,
-      Write       => Write,
-      XYbit_undoc => XYbit_undoc);
-
-  alu : T80_ALU
-    generic map(
-      Mode   => Mode,
-      Flag_C => Flag_C,
-      Flag_N => Flag_N,
-      Flag_P => Flag_P,
-      Flag_X => Flag_X,
-      Flag_H => Flag_H,
-      Flag_Y => Flag_Y,
-      Flag_Z => Flag_Z,
-      Flag_S => Flag_S)
-    port map(
-      Arith16 => Arith16_r,
-      Z16     => Z16_r,
-      ALU_Op  => ALU_Op_r,
-      IR      => IR(5 downto 0),
-      ISet    => ISet,
-      BusA    => BusA,
-      BusB    => BusB,
-      F_In    => F,
-      Q       => ALU_Q,
-      F_Out   => F_Out);
-
-  ClkEn <= CEN and not BusAck;
-
-  T_Res <= '1' when TState = unsigned(TStates) else '0';
-
-  NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
-                              ((Set_Addr_To = aXY) or
-                               (MCycle = "001" and IR = "11001011") or
-                               (MCycle = "001" and IR = "00110110")) else '0';
-
-  Save_Mux <= BusB when ExchangeRp = '1' else
-              DI_Reg when Save_ALU_r = '0' else
-              ALU_Q;
-
-  process (RESET_n, CLK_n)
-  begin
-    if RESET_n = '0' then
-      PC <= (others => '0');  -- Program Counter
-      A <= (others => '0');
-      TmpAddr <= (others => '0');
-      IR <= "00000000";
-      ISet <= "00";
-      XY_State <= "00";
-      IStatus <= "00";
-      MCycles <= "000";
-      DO <= "00000000";
-
-      ACC <= (others => '1');
-      F <= (others => '1');
-      Ap <= (others => '1');
-      Fp <= (others => '1');
-      I <= (others => '0');
-      R <= (others => '0');
-      SP <= (others => '1');
-      Alternate <= '0';
-
-      Read_To_Reg_r <= "00000";
-      F <= (others => '1');
-      Arith16_r <= '0';
-      BTR_r <= '0';
-      Z16_r <= '0';
-      ALU_Op_r <= "0000";
-      Save_ALU_r <= '0';
-      PreserveC_r <= '0';
-      XY_Ind <= '0';
-
-    elsif CLK_n'event and CLK_n = '1' then
-
-      if ClkEn = '1' then
-
-        ALU_Op_r <= "0000";
-        Save_ALU_r <= '0';
-        Read_To_Reg_r <= "00000";
-
-        MCycles <= MCycles_d;
-
-        if IMode /= "11" then
-          IStatus <= IMode;
-        end if;
-
-        Arith16_r <= Arith16;
-        PreserveC_r <= PreserveC;
-        if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
-          Z16_r <= '1';
-        else
-          Z16_r <= '0';
-        end if;
-
-        if MCycle  = "001" and TState(2) = '0' then
-          -- MCycle = 1 and TState = 1, 2, or 3
-
-          if TState = 2 and Wait_n = '1' then
-            if Mode < 2 then
-              A(7 downto 0) <= std_logic_vector(R);
-              A(15 downto 8) <= I;
-              R(6 downto 0) <= R(6 downto 0) + 1;
-            end if;
-
-            if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
-              PC <= PC + 1;
-            end if;
-
-            if IntCycle = '1' and IStatus = "01" then
-              IR <= "11111111";
-            elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
-              IR <= "00000000";
-            else
-              IR <= DInst;
-            end if;
-
-            ISet <= "00";
-            if Prefix /= "00" then
-              if Prefix = "11" then
-                if IR(5) = '1' then
-                  XY_State <= "10";
-                else
-                  XY_State <= "01";
-                end if;
-              else
-                if Prefix = "10" then
-                  XY_State <= "00";
-                  XY_Ind <= '0';
-                end if;
-                ISet <= Prefix;
-              end if;
-            else
-              XY_State <= "00";
-              XY_Ind <= '0';
-            end if;
-          end if;
-
-        else
-          -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
-          if MCycle = "110" then
-            XY_Ind <= '1';
-            if Prefix = "01" then
-              ISet <= "01";
-            end if;
-          end if;
-
-          if T_Res = '1' then
-            BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
-            if Jump = '1' then
-              A(15 downto 8) <= DI_Reg;
-              A(7 downto 0) <= TmpAddr(7 downto 0);
-              PC(15 downto 8) <= unsigned(DI_Reg);
-              PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-            elsif JumpXY = '1' then
-              A <= RegBusC;
-              PC <= unsigned(RegBusC);
-            elsif Call = '1' or RstP = '1' then
-              A <= TmpAddr;
-              PC <= unsigned(TmpAddr);
-            elsif MCycle = MCycles and NMICycle = '1' then
-              A <= "0000000001100110";
-              PC <= "0000000001100110";
-            elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
-              A(15 downto 8) <= I;
-              A(7 downto 0) <= TmpAddr(7 downto 0);
-              PC(15 downto 8) <= unsigned(I);
-              PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-            else
-              case Set_Addr_To is
-                when aXY =>
-                  if XY_State = "00" then
-                    A <= RegBusC;
-                  else
-                    if NextIs_XY_Fetch = '1' then
-                      A <= std_logic_vector(PC);
-                    else
-                      A <= TmpAddr;
-                    end if;
-                  end if;
-                when aIOA =>
-                  if Mode = 3 then
-                    -- Memory map I/O on GBZ80
-                    A(15 downto 8) <= (others => '1');
-                  elsif Mode = 2 then
-                    -- Duplicate I/O address on 8080
-                    A(15 downto 8) <= DI_Reg;
-                  else
-                    A(15 downto 8) <= ACC;
-                  end if;
-                  A(7 downto 0) <= DI_Reg;
-                when aSP =>
-                  A <= std_logic_vector(SP);
-                when aBC =>
-                  if Mode = 3 and IORQ_i = '1' then
-                    -- Memory map I/O on GBZ80
-                    A(15 downto 8) <= (others => '1');
-                    A(7 downto 0) <= RegBusC(7 downto 0);
-                  else
-                    A <= RegBusC;
-                  end if;
-                when aDE =>
-                  A <= RegBusC;
-                when aZI =>
-                  if Inc_WZ = '1' then
-                    A <= std_logic_vector(unsigned(TmpAddr) + 1);
-                  else
-                    A(15 downto 8) <= DI_Reg;
-                    A(7 downto 0) <= TmpAddr(7 downto 0);
-                  end if;
-                when others =>
-                  A <= std_logic_vector(PC);
-              end case;
-            end if;
-
-            Save_ALU_r <= Save_ALU;
-            ALU_Op_r <= ALU_Op;
-
-            if I_CPL = '1' then
-              -- CPL
-              ACC <= not ACC;
-              F(Flag_Y) <= not ACC(5);
-              F(Flag_H) <= '1';
-              F(Flag_X) <= not ACC(3);
-              F(Flag_N) <= '1';
-            end if;
-            if I_CCF = '1' then
-              -- CCF
-              F(Flag_C) <= not F(Flag_C);
-              F(Flag_Y) <= ACC(5);
-              F(Flag_H) <= F(Flag_C);
-              F(Flag_X) <= ACC(3);
-              F(Flag_N) <= '0';
-            end if;
-            if I_SCF = '1' then
-              -- SCF
-              F(Flag_C) <= '1';
-              F(Flag_Y) <= ACC(5);
-              F(Flag_H) <= '0';
-              F(Flag_X) <= ACC(3);
-              F(Flag_N) <= '0';
-            end if;
-          end if;
-
-          if TState = 2 and Wait_n = '1' then
-            if ISet = "01" and MCycle = "111" then
-              IR <= DInst;
-            end if;
-            if JumpE = '1' then
-              PC <= unsigned(signed(PC) + signed(DI_Reg));
-            elsif Inc_PC = '1' then
-              PC <= PC + 1;
-            end if;
-            if BTR_r = '1' then
-              PC <= PC - 2;
-            end if;
-            if RstP = '1' then
-              TmpAddr <= (others =>'0');
-              TmpAddr(5 downto 3) <= IR(5 downto 3);
-            end if;
-          end if;
-          if TState = 3 and MCycle = "110" then
-            TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
-          end if;
-
-          if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
-            if IncDec_16(2 downto 0) = "111" then
-              if IncDec_16(3) = '1' then
-                SP <= SP - 1;
-              else
-                SP <= SP + 1;
-              end if;
-            end if;
-          end if;
-
-          if LDSPHL = '1' then
-            SP <= unsigned(RegBusC);
-          end if;
-          if ExchangeAF = '1' then
-            Ap <= ACC;
-            ACC <= Ap;
-            Fp <= F;
-            F <= Fp;
-          end if;
-          if ExchangeRS = '1' then
-            Alternate <= not Alternate;
-          end if;
-        end if;
-
-        if TState = 3 then
-          if LDZ = '1' then
-            TmpAddr(7 downto 0) <= DI_Reg;
-          end if;
-          if LDW = '1' then
-            TmpAddr(15 downto 8) <= DI_Reg;
-          end if;
-
-          if Special_LD(2) = '1' then
-            case Special_LD(1 downto 0) is
-              when "00" =>
-                ACC <= I;
-                F(Flag_P) <= IntE_FF2;
-              when "01" =>
-                ACC <= std_logic_vector(R);
-                F(Flag_P) <= IntE_FF2;
-              when "10" =>
-                I <= ACC;
-              when others =>
-                R <= unsigned(ACC);
-            end case;
-          end if;
-        end if;
-
-        if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
-          if Mode = 3 then
-            F(6) <= F_Out(6);
-            F(5) <= F_Out(5);
-            F(7) <= F_Out(7);
-            if PreserveC_r = '0' then
-              F(4) <= F_Out(4);
-            end if;
-          else
-            F(7 downto 1) <= F_Out(7 downto 1);
-            if PreserveC_r = '0' then
-              F(Flag_C) <= F_Out(0);
-            end if;
-          end if;
-        end if;
-        if T_Res = '1' and I_INRC = '1' then
-          F(Flag_H) <= '0';
-          F(Flag_N) <= '0';
-          if DI_Reg(7 downto 0) = "00000000" then
-            F(Flag_Z) <= '1';
-          else
-            F(Flag_Z) <= '0';
-          end if;
-          F(Flag_S) <= DI_Reg(7);
-          F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
-                            DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
-        end if;
-
-        if TState = 1 then
-          DO <= BusB;
-          if I_RLD = '1' then
-            DO(3 downto 0) <= BusA(3 downto 0);
-            DO(7 downto 4) <= BusB(3 downto 0);
-          end if;
-          if I_RRD = '1' then
-            DO(3 downto 0) <= BusB(7 downto 4);
-            DO(7 downto 4) <= BusA(3 downto 0);
-          end if;
-        end if;
-
-        if T_Res = '1' then
-          Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
-          Read_To_Reg_r(4) <= Read_To_Reg;
-          if Read_To_Acc = '1' then
-            Read_To_Reg_r(3 downto 0) <= "0111";
-            Read_To_Reg_r(4) <= '1';
-          end if;
-        end if;
-
-        if TState = 1 and I_BT = '1' then
-          F(Flag_X) <= ALU_Q(3);
-          F(Flag_Y) <= ALU_Q(1);
-          F(Flag_H) <= '0';
-          F(Flag_N) <= '0';
-        end if;
-        if I_BC = '1' or I_BT = '1' then
-          F(Flag_P) <= IncDecZ;
-        end if;
-
-        if (TState = 1 and Save_ALU_r = '0') or
-          (Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-          case Read_To_Reg_r is
-            when "10111" =>
-              ACC <= Save_Mux;
-            when "10110" =>
-              DO <= Save_Mux;
-            when "11000" =>
-              SP(7 downto 0) <= unsigned(Save_Mux);
-            when "11001" =>
-              SP(15 downto 8) <= unsigned(Save_Mux);
-            when "11011" =>
-              F <= Save_Mux;
-            when others =>
-          end case;
-          if XYbit_undoc='1' then
-            DO <= ALU_Q;
-          end if;
-        end if;
-
-      end if;
-
-    end if;
-
-  end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
-  process (CLK_n)
-  begin
-    if CLK_n'event and CLK_n = '1' then
-      if ClkEn = '1' then
-        -- Bus A / Write
-        RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
-        if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
-          RegAddrA_r <= XY_State(1) & "11";
-        end if;
-
-        -- Bus B
-        RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
-        if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
-          RegAddrB_r <= XY_State(1) & "11";
-        end if;
-
-        -- Address from register
-        RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-        -- Jump (HL), LD SP,HL
-        if (JumpXY = '1' or LDSPHL = '1') then
-          RegAddrC <= Alternate & "10";
-        end if;
-        if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
-          RegAddrC <= XY_State(1) & "11";
-        end if;
-
-        if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
-          IncDecZ <= F_Out(Flag_Z);
-        end if;
-        if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
-          if ID16 = 0 then
-            IncDecZ <= '0';
-          else
-            IncDecZ <= '1';
-          end if;
-        end if;
-
-        RegBusA_r <= RegBusA;
-      end if;
-    end if;
-  end process;
-
-  RegAddrA <=
-    -- 16 bit increment/decrement
-    Alternate & IncDec_16(1 downto 0) when (TState = 2 or
-                                            (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
-    XY_State(1) & "11" when (TState = 2 or
-                             (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-    -- EX HL,DL
-    Alternate & "10" when ExchangeDH = '1' and TState = 3 else
-    Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-    -- Bus A / Write
-    RegAddrA_r;
-
-  RegAddrB <=
-    -- EX HL,DL
-    Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-    -- Bus B
-    RegAddrB_r;
-
-  ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
-          signed(RegBusA) + 1;
-
-  process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
-           ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-  begin
-    RegWEH <= '0';
-    RegWEL <= '0';
-    if (TState = 1 and Save_ALU_r = '0') or
-      (Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-      case Read_To_Reg_r is
-        when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
-          RegWEH <= not Read_To_Reg_r(0);
-          RegWEL <= Read_To_Reg_r(0);
-        when others =>
-      end case;
-    end if;
-
-    if ExchangeDH = '1' and (TState = 3 or TState = 4) then
-      RegWEH <= '1';
-      RegWEL <= '1';
-    end if;
-
-    if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-      case IncDec_16(1 downto 0) is
-        when "00" | "01" | "10" =>
-          RegWEH <= '1';
-          RegWEL <= '1';
-        when others =>
-      end case;
-    end if;
-  end process;
-
-  process (Save_Mux, RegBusB, RegBusA_r, ID16,
-           ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-  begin
-    RegDIH <= Save_Mux;
-    RegDIL <= Save_Mux;
-
-    if ExchangeDH = '1' and TState = 3 then
-      RegDIH <= RegBusB(15 downto 8);
-      RegDIL <= RegBusB(7 downto 0);
-    end if;
-    if ExchangeDH = '1' and TState = 4 then
-      RegDIH <= RegBusA_r(15 downto 8);
-      RegDIL <= RegBusA_r(7 downto 0);
-    end if;
-
-    if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-      RegDIH <= std_logic_vector(ID16(15 downto 8));
-      RegDIL <= std_logic_vector(ID16(7 downto 0));
-    end if;
-  end process;
-
-  Regs : T80_Reg
-    port map(
-      Clk   => CLK_n,
-      CEN   => ClkEn,
-      WEH   => RegWEH,
-      WEL   => RegWEL,
-      AddrA => RegAddrA,
-      AddrB => RegAddrB,
-      AddrC => RegAddrC,
-      DIH   => RegDIH,
-      DIL   => RegDIL,
-      DOAH  => RegBusA(15 downto 8),
-      DOAL  => RegBusA(7 downto 0),
-      DOBH  => RegBusB(15 downto 8),
-      DOBL  => RegBusB(7 downto 0),
-      DOCH  => RegBusC(15 downto 8),
-      DOCL  => RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
-  process (CLK_n)
-  begin
-    if CLK_n'event and CLK_n = '1' then
-      if ClkEn = '1' then
-        case Set_BusB_To is
-          when "0111" =>
-            BusB <= ACC;
-          when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-            if Set_BusB_To(0) = '1' then
-              BusB <= RegBusB(7 downto 0);
-            else
-              BusB <= RegBusB(15 downto 8);
-            end if;
-          when "0110" =>
-            BusB <= DI_Reg;
-          when "1000" =>
-            BusB <= std_logic_vector(SP(7 downto 0));
-          when "1001" =>
-            BusB <= std_logic_vector(SP(15 downto 8));
-          when "1010" =>
-            BusB <= "00000001";
-          when "1011" =>
-            BusB <= F;
-          when "1100" =>
-            BusB <= std_logic_vector(PC(7 downto 0));
-          when "1101" =>
-            BusB <= std_logic_vector(PC(15 downto 8));
-          when "1110" =>
-            BusB <= "00000000";
-          when others =>
-            BusB <= "--------";
-        end case;
-
-        case Set_BusA_To is
-          when "0111" =>
-            BusA <= ACC;
-          when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-            if Set_BusA_To(0) = '1' then
-              BusA <= RegBusA(7 downto 0);
-            else
-              BusA <= RegBusA(15 downto 8);
-            end if;
-          when "0110" =>
-            BusA <= DI_Reg;
-          when "1000" =>
-            BusA <= std_logic_vector(SP(7 downto 0));
-          when "1001" =>
-            BusA <= std_logic_vector(SP(15 downto 8));
-          when "1010" =>
-            BusA <= "00000000";
-          when others =>
-            BusB <= "--------";
-        end case;
-        if XYbit_undoc='1' then
-          BusA <= DI_Reg;
-          BusB <= DI_Reg;
-        end if;
-      end if;
-    end if;
-  end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
-  process (RESET_n,CLK_n)
-  begin
-    if RESET_n = '0' then
-      RFSH_n <= '1';
-    elsif CLK_n'event and CLK_n = '1' then
-      if CEN = '1' then
-        if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
-          RFSH_n <= '0';
-        else
-          RFSH_n <= '1';
-        end if;
-      end if;
-    end if;
-  end process;
-
-  MC <= std_logic_vector(MCycle);
-  TS <= std_logic_vector(TState);
-  DI_Reg <= DI;
-  HALT_n <= not Halt_FF;
-  BUSAK_n <= not BusAck;
-  IntCycle_n <= not IntCycle;
-  IntE <= IntE_FF1;
-  IORQ <= IORQ_i;
-  Stop <= I_DJNZ;
-
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
-  process (RESET_n, CLK_n)
-    variable OldNMI_n : std_logic;
-  begin
-    if RESET_n = '0' then
-      BusReq_s <= '0';
-      INT_s <= '0';
-      NMI_s <= '0';
-      OldNMI_n := '0';
-    elsif CLK_n'event and CLK_n = '1' then
-      if CEN = '1' then
-        BusReq_s <= not BUSRQ_n;
-        INT_s <= not INT_n;
-        if NMICycle = '1' then
-          NMI_s <= '0';
-        elsif NMI_n = '0' and OldNMI_n = '1' then
-          NMI_s <= '1';
-        end if;
-        OldNMI_n := NMI_n;
-      end if;
-    end if;
-  end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
-  process (RESET_n, CLK_n)
-  begin
-    if RESET_n = '0' then
-      MCycle <= "001";
-      TState <= "000";
-      Pre_XY_F_M <= "000";
-      Halt_FF <= '0';
-      BusAck <= '0';
-      NMICycle <= '0';
-      IntCycle <= '0';
-      IntE_FF1 <= '0';
-      IntE_FF2 <= '0';
-      No_BTR <= '0';
-      Auto_Wait_t1 <= '0';
-      Auto_Wait_t2 <= '0';
-      M1_n <= '1';
-    elsif CLK_n'event and CLK_n = '1' then
-      if CEN = '1' then
-        Auto_Wait_t1 <= Auto_Wait;
-        Auto_Wait_t2 <= Auto_Wait_t1;
-        No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
-                  (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
-                  (I_BTR and (not IR(4) or F(Flag_Z)));
-        if TState = 2 then
-          if SetEI = '1' then
-            IntE_FF1 <= '1';
-            IntE_FF2 <= '1';
-          end if;
-          if I_RETN = '1' then
-            IntE_FF1 <= IntE_FF2;
-          end if;
-        end if;
-        if TState = 3 then
-          if SetDI = '1' then
-            IntE_FF1 <= '0';
-            IntE_FF2 <= '0';
-          end if;
-        end if;
-        if IntCycle = '1' or NMICycle = '1' then
-          Halt_FF <= '0';
-        end if;
-        if MCycle = "001" and TState = 2 and Wait_n = '1' then
-          M1_n <= '1';
-        end if;
-        if BusReq_s = '1' and BusAck = '1' then
-        else
-          BusAck <= '0';
-          if TState = 2 and Wait_n = '0' then
-          elsif T_Res = '1' then
-            if Halt = '1' then
-              Halt_FF <= '1';
-            end if;
-            if BusReq_s = '1' then
-              BusAck <= '1';
-            else
-              TState <= "001";
-              if NextIs_XY_Fetch = '1' then
-                MCycle <= "110";
-                Pre_XY_F_M <= MCycle;
-                if IR = "00110110" and Mode = 0 then
-                  Pre_XY_F_M <= "010";
-                end if;
-              elsif (MCycle = "111") or
-                (MCycle = "110" and Mode = 1 and ISet /= "01") then
-                MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
-              elsif (MCycle = MCycles) or
-                No_BTR = '1' or
-                (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
-                M1_n <= '0';
-                MCycle <= "001";
-                IntCycle <= '0';
-                NMICycle <= '0';
-                if NMI_s = '1' and Prefix = "00" then
-                  NMICycle <= '1';
-                  IntE_FF1 <= '0';
-                elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
-                  IntCycle <= '1';
-                  IntE_FF1 <= '0';
-                  IntE_FF2 <= '0';
-                end if;
-              else
-                MCycle <= std_logic_vector(unsigned(MCycle) + 1);
-              end if;
-            end if;
-          else
-            if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
-
-              TState <= TState + 1;
-            end if;
-          end if;
-        end if;
-        if TState = 0 then
-          M1_n <= '0';
-        end if;
-      end if;
-    end if;
-  end process;
-
-  process (IntCycle, NMICycle, MCycle)
-  begin
-    Auto_Wait <= '0';
-    if IntCycle = '1' or NMICycle = '1' then
-      if MCycle = "001" then
-        Auto_Wait <= '1';
-      end if;
-    end if;
-  end process;
-
-end;
diff --git a/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/cpu/T80_ALU.vhd
deleted file mode 100644
index 7e8a9995..00000000
--- a/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/cpu/T80_ALU.vhd	
+++ /dev/null
@@ -1,370 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0238 : Fixed zero flag for 16 bit SBC and ADC
---
---      0240 : Added GB operations
---
---      0242 : Cleanup
---
---      0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16         : in  std_logic;
-		Z16             : in  std_logic;
-		ALU_Op          : in  std_logic_vector(3 downto 0);
-		IR              : in  std_logic_vector(5 downto 0);
-		ISet            : in  std_logic_vector(1 downto 0);
-		BusA            : in  std_logic_vector(7 downto 0);
-		BusB            : in  std_logic_vector(7 downto 0);
-		F_In            : in  std_logic_vector(7 downto 0);
-		Q               : out std_logic_vector(7 downto 0);
-		F_Out           : out std_logic_vector(7 downto 0)
-	);
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
-	procedure AddSub(A        : std_logic_vector;
-					 B        : std_logic_vector;
-					 Sub      : std_logic;
-					 Carry_In : std_logic;
-			  signal Res      : out std_logic_vector;
-			  signal Carry    : out std_logic) is
-
-		variable B_i          : unsigned(A'length - 1 downto 0);
-		variable Res_i        : unsigned(A'length + 1 downto 0);
-	begin
-		if Sub = '1' then
-			B_i := not unsigned(B);
-		else
-			B_i :=     unsigned(B);
-		end if;
-
-		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
-		Carry <= Res_i(A'length + 1);
-		Res <= std_logic_vector(Res_i(A'length downto 1));
-	end;
-
-	-- AddSub variables (temporary signals)
-	signal UseCarry                : std_logic;
-	signal Carry7_v                : std_logic;
-	signal Overflow_v              : std_logic;
-	signal HalfCarry_v             : std_logic;
-	signal Carry_v                 : std_logic;
-	signal Q_v                     : std_logic_vector(7 downto 0);
-
-	signal BitMask                 : std_logic_vector(7 downto 0);
-
-begin
-
-	with IR(5 downto 3) select BitMask <= "00000001" when "000",
-										  "00000010" when "001",
-										  "00000100" when "010",
-										  "00001000" when "011",
-										  "00010000" when "100",
-										  "00100000" when "101",
-										  "01000000" when "110",
-										  "10000000" when others;
-
-	UseCarry <= not ALU_Op(2) and ALU_Op(0);
-	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
-	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
-	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-	-- bug fix - parity flag is just parity for 8080, also overflow for Z80
-	process (Carry_v, Carry7_v, Q_v)
-	begin
-		if(Mode=2) then
-			OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
-					   Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7));  else
-	OverFlow_v <= Carry_v xor Carry7_v;
-		end if;
-	end process;
-
-	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
-		variable Q_t : std_logic_vector(7 downto 0);
-		variable DAA_Q : unsigned(8 downto 0);
-	begin
-		Q_t := "--------";
-		F_Out <= F_In;
-		DAA_Q := "---------";
-		case ALU_Op is
-		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_C) <= '0';
-			case ALU_OP(2 downto 0) is
-			when "000" | "001" => -- ADD, ADC
-				Q_t := Q_v;
-				F_Out(Flag_C) <= Carry_v;
-				F_Out(Flag_H) <= HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "010" | "011" | "111" => -- SUB, SBC, CP
-				Q_t := Q_v;
-				F_Out(Flag_N) <= '1';
-				F_Out(Flag_C) <= not Carry_v;
-				F_Out(Flag_H) <= not HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "100" => -- AND
-				Q_t(7 downto 0) := BusA and BusB;
-				F_Out(Flag_H) <= '1';
-			when "101" => -- XOR
-				Q_t(7 downto 0) := BusA xor BusB;
-				F_Out(Flag_H) <= '0';
-			when others => -- OR "110"
-				Q_t(7 downto 0) := BusA or BusB;
-				F_Out(Flag_H) <= '0';
-			end case;
-			if ALU_Op(2 downto 0) = "111" then -- CP
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			else
-				F_Out(Flag_X) <= Q_t(3);
-				F_Out(Flag_Y) <= Q_t(5);
-			end if;
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				if Z16 = '1' then
-					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
-				end if;
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			case ALU_Op(2 downto 0) is
-			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
-			when others =>
-				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			end case;
-			if Arith16 = '1' then
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-				F_Out(Flag_P) <= F_In(Flag_P);
-			end if;
-		when "1100" =>
-			-- DAA
-			F_Out(Flag_H) <= F_In(Flag_H);
-			F_Out(Flag_C) <= F_In(Flag_C);
-			DAA_Q(7 downto 0) := unsigned(BusA);
-			DAA_Q(8) := '0';
-			if F_In(Flag_N) = '0' then
-				-- After addition
-				-- Alow > 9 or H = 1
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if (DAA_Q(3 downto 0) > 9) then
-						F_Out(Flag_H) <= '1';
-					else
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q := DAA_Q + 6;
-				end if;
-				-- new Ahigh > 9 or C = 1
-				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q + 96; -- 0x60
-				end if;
-			else
-				-- After subtraction
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if DAA_Q(3 downto 0) > 5 then
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
-				end if;
-				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q - 352; -- 0x160
-				end if;
-			end if;
-			F_Out(Flag_X) <= DAA_Q(3);
-			F_Out(Flag_Y) <= DAA_Q(5);
-			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
-			Q_t := std_logic_vector(DAA_Q(7 downto 0));
-			if DAA_Q(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= DAA_Q(7);
-			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
-				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
-		when "1101" | "1110" =>
-			-- RLD, RRD
-			Q_t(7 downto 4) := BusA(7 downto 4);
-			if ALU_Op(0) = '1' then
-				Q_t(3 downto 0) := BusB(7 downto 4);
-			else
-				Q_t(3 downto 0) := BusB(3 downto 0);
-			end if;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-		when "1001" =>
-			-- BIT
-			Q_t(7 downto 0) := BusB and BitMask;
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				F_Out(Flag_P) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-				F_Out(Flag_P) <= '0';
-			end if;
-			F_Out(Flag_H) <= '1';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= '0';
-			F_Out(Flag_Y) <= '0';
-			if IR(2 downto 0) /= "110" then
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			end if;
-		when "1010" =>
-			-- SET
-			Q_t(7 downto 0) := BusB or BitMask;
-		when "1011" =>
-			-- RES
-			Q_t(7 downto 0) := BusB and not BitMask;
-		when "1000" =>
-			-- ROT
-			case IR(5 downto 3) is
-			when "000" => -- RLC
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := BusA(7);
-				F_Out(Flag_C) <= BusA(7);
-			when "010" => -- RL
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(7);
-			when "001" => -- RRC
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(0);
-				F_Out(Flag_C) <= BusA(0);
-			when "011" => -- RR
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(0);
-			when "100" => -- SLA
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := '0';
-				F_Out(Flag_C) <= BusA(7);
-			when "110" => -- SLL (Undocumented) / SWAP
-				if Mode = 3 then
-					Q_t(7 downto 4) := BusA(3 downto 0);
-					Q_t(3 downto 0) := BusA(7 downto 4);
-					F_Out(Flag_C) <= '0';
-				else
-					Q_t(7 downto 1) := BusA(6 downto 0);
-					Q_t(0) := '1';
-					F_Out(Flag_C) <= BusA(7);
-				end if;
-			when "101" => -- SRA
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(7);
-				F_Out(Flag_C) <= BusA(0);
-			when others => -- SRL
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := '0';
-				F_Out(Flag_C) <= BusA(0);
-			end case;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			if ISet = "00" then
-				F_Out(Flag_P) <= F_In(Flag_P);
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-			end if;
-		when others =>
-			null;
-		end case;
-		Q <= Q_t;
-	end process;
-end;
diff --git a/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/cpu/T80_MCode.vhd
deleted file mode 100644
index 7d407fb8..00000000
--- a/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/cpu/T80_MCode.vhd	
+++ /dev/null
@@ -1,2027 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0211 : Fixed IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0235 : Added IM 2 fix by Mike Johnson
---
---      0238 : Added NoRead signal
---
---      0238b: Fixed instruction timing for POP and DJNZ
---
---      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
-
---      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
---
---      0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80_MCode is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR                              : in std_logic_vector(7 downto 0);
-		ISet                    : in std_logic_vector(1 downto 0);
-		MCycle                  : in std_logic_vector(2 downto 0);
-		F                               : in std_logic_vector(7 downto 0);
-		NMICycle                : in std_logic;
-		IntCycle                : in std_logic;
-		XY_State                : in std_logic_vector(1 downto 0);
-		MCycles                 : out std_logic_vector(2 downto 0);
-		TStates                 : out std_logic_vector(2 downto 0);
-		Prefix                  : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD
-		Inc_PC                  : out std_logic;
-		Inc_WZ                  : out std_logic;
-		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg             : out std_logic;
-		Read_To_Acc             : out std_logic;
-		Set_BusA_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op                  : out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU                : out std_logic;
-		PreserveC               : out std_logic;
-		Arith16                 : out std_logic;
-		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ                    : out std_logic;
-		Jump                    : out std_logic;
-		JumpE                   : out std_logic;
-		JumpXY                  : out std_logic;
-		Call                    : out std_logic;
-		RstP                    : out std_logic;
-		LDZ                             : out std_logic;
-		LDW                             : out std_logic;
-		LDSPHL                  : out std_logic;
-		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH              : out std_logic;
-		ExchangeRp              : out std_logic;
-		ExchangeAF              : out std_logic;
-		ExchangeRS              : out std_logic;
-		I_DJNZ                  : out std_logic;
-		I_CPL                   : out std_logic;
-		I_CCF                   : out std_logic;
-		I_SCF                   : out std_logic;
-		I_RETN                  : out std_logic;
-		I_BT                    : out std_logic;
-		I_BC                    : out std_logic;
-		I_BTR                   : out std_logic;
-		I_RLD                   : out std_logic;
-		I_RRD                   : out std_logic;
-		I_INRC                  : out std_logic;
-		SetDI                   : out std_logic;
-		SetEI                   : out std_logic;
-		IMode                   : out std_logic_vector(1 downto 0);
-		Halt                    : out std_logic;
-		NoRead                  : out std_logic;
-		Write                   : out std_logic;
-		XYbit_undoc             : out std_logic
-	);
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
-	constant aNone      : std_logic_vector(2 downto 0) := "111";
-	constant aBC        : std_logic_vector(2 downto 0) := "000";
-	constant aDE        : std_logic_vector(2 downto 0) := "001";
-	constant aXY        : std_logic_vector(2 downto 0) := "010";
-	constant aIOA       : std_logic_vector(2 downto 0) := "100";
-	constant aSP        : std_logic_vector(2 downto 0) := "101";
-	constant aZI        : std_logic_vector(2 downto 0) := "110";
-
-	function is_cc_true(
-		F : std_logic_vector(7 downto 0);
-		cc : bit_vector(2 downto 0)
-		) return boolean is
-	begin
-		if Mode = 3 then
-			case cc is
-			when "000" => return F(7) = '0'; -- NZ
-			when "001" => return F(7) = '1'; -- Z
-			when "010" => return F(4) = '0'; -- NC
-			when "011" => return F(4) = '1'; -- C
-			when "100" => return false;
-			when "101" => return false;
-			when "110" => return false;
-			when "111" => return false;
-			end case;
-		else
-			case cc is
-			when "000" => return F(6) = '0'; -- NZ
-			when "001" => return F(6) = '1'; -- Z
-			when "010" => return F(0) = '0'; -- NC
-			when "011" => return F(0) = '1'; -- C
-			when "100" => return F(2) = '0'; -- PO
-			when "101" => return F(2) = '1'; -- PE
-			when "110" => return F(7) = '0'; -- P
-			when "111" => return F(7) = '1'; -- M
-			end case;
-		end if;
-	end;
-
-begin
-
-	process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State)
-		variable DDD : std_logic_vector(2 downto 0);
-		variable SSS : std_logic_vector(2 downto 0);
-		variable DPair : std_logic_vector(1 downto 0);
-		variable IRB : bit_vector(7 downto 0);
-	begin
-		DDD := IR(5 downto 3);
-		SSS := IR(2 downto 0);
-		DPair := IR(5 downto 4);
-		IRB := to_bitvector(IR);
-
-		MCycles <= "001";
-		if MCycle = "001" then
-			TStates <= "100";
-		else
-			TStates <= "011";
-		end if;
-		Prefix <= "00";
-		Inc_PC <= '0';
-		Inc_WZ <= '0';
-		IncDec_16 <= "0000";
-		Read_To_Acc <= '0';
-		Read_To_Reg <= '0';
-		Set_BusB_To <= "0000";
-		Set_BusA_To <= "0000";
-		ALU_Op <= "0" & IR(5 downto 3);
-		Save_ALU <= '0';
-		PreserveC <= '0';
-		Arith16 <= '0';
-		IORQ <= '0';
-		Set_Addr_To <= aNone;
-		Jump <= '0';
-		JumpE <= '0';
-		JumpXY <= '0';
-		Call <= '0';
-		RstP <= '0';
-		LDZ <= '0';
-		LDW <= '0';
-		LDSPHL <= '0';
-		Special_LD <= "000";
-		ExchangeDH <= '0';
-		ExchangeRp <= '0';
-		ExchangeAF <= '0';
-		ExchangeRS <= '0';
-		I_DJNZ <= '0';
-		I_CPL <= '0';
-		I_CCF <= '0';
-		I_SCF <= '0';
-		I_RETN <= '0';
-		I_BT <= '0';
-		I_BC <= '0';
-		I_BTR <= '0';
-		I_RLD <= '0';
-		I_RRD <= '0';
-		I_INRC <= '0';
-		SetDI <= '0';
-		SetEI <= '0';
-		IMode <= "11";
-		Halt <= '0';
-		NoRead <= '0';
-		Write <= '0';
-		XYbit_undoc <= '0';
-
-		case ISet is
-		when "00" =>
-
-------------------------------------------------------------------------------
---
---      Unprefixed instructions
---
-------------------------------------------------------------------------------
-
-		case IRB is
--- 8 BIT LOAD GROUP
-		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-			-- LD r,r'
-			Set_BusB_To(2 downto 0) <= SSS;
-			ExchangeRp <= '1';
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-			-- LD r,n
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-			-- LD r,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-			-- LD (HL),r
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110110" =>
-			-- LD (HL),n
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00001010" =>
-			-- LD A,(BC)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00011010" =>
-			-- LD A,(DE)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00111010" =>
-			if Mode = 3 then
-				-- LDD A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD A,(nn)
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-				when 4 =>
-					Read_To_Acc <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00000010" =>
-			-- LD (BC),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00010010" =>
-			-- LD (DE),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110010" =>
-			if Mode = 3 then
-				-- LDD (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),A
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					Set_BusB_To <= "0111";
-				when 4 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 16 BIT LOAD GROUP
-		when "00000001"|"00010001"|"00100001"|"00110001" =>
-			-- LD dd,nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1000";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1001";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-		when "00101010" =>
-			if Mode = 3 then
-				-- LDI A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD HL,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Set_BusA_To(2 downto 0) <= "101"; -- L
-					Read_To_Reg <= '1';
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Set_BusA_To(2 downto 0) <= "100"; -- H
-					Read_To_Reg <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00100010" =>
-			if Mode = 3 then
-				-- LDI (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "0101"; -- L
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "0100"; -- H
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11111001" =>
-			-- LD SP,HL
-			TStates <= "110";
-			LDSPHL <= '1';
-		when "11000101"|"11010101"|"11100101"|"11110101" =>
-			-- PUSH qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_TO <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "0111";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '0';
-					Set_BusB_To(3) <= '0';
-				end if;
-			when 2 =>
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "1011";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '1';
-					Set_BusB_To(3) <= '0';
-				end if;
-				Write <= '1';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "11000001"|"11010001"|"11100001"|"11110001" =>
-			-- POP qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1011";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				IncDec_16 <= "0111";
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "0111";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
-		when "11101011" =>
-			if Mode /= 3 then
-				-- EX DE,HL
-				ExchangeDH <= '1';
-			end if;
-		when "00001000" =>
-			if Mode = 3 then
-				-- LD (nn),SP
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "1000";
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "1001";
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EX AF,AF'
-				ExchangeAF <= '1';
-			end if;
-		when "11011001" =>
-			if Mode = 3 then
-				-- RETI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-					SetEI <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EXX
-				ExchangeRS <= '1';
-			end if;
-		when "11100011" =>
-			if Mode /= 3 then
-				-- EX (SP),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aSP;
-				when 2 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0101";
-					Set_BusB_To <= "0101";
-					Set_Addr_To <= aSP;
-				when 3 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0100";
-					Set_BusB_To <= "0100";
-					Set_Addr_To <= aSP;
-				when 5 =>
-					IncDec_16 <= "1111";
-					TStates <= "101";
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
-		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-			-- ADD A,r
-			-- ADC A,r
-			-- SUB A,r
-			-- SBC A,r
-			-- AND A,r
-			-- OR A,r
-			-- XOR A,r
-			-- CP A,r
-			Set_BusB_To(2 downto 0) <= SSS;
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-			-- ADD A,(HL)
-			-- ADC A,(HL)
-			-- SUB A,(HL)
-			-- SBC A,(HL)
-			-- AND A,(HL)
-			-- OR A,(HL)
-			-- XOR A,(HL)
-			-- CP A,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			when others => null;
-			end case;
-		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-			-- ADD A,n
-			-- ADC A,n
-			-- SUB A,n
-			-- SBC A,n
-			-- AND A,n
-			-- OR A,n
-			-- XOR A,n
-			-- CP A,n
-			MCycles <= "010";
-			if MCycle = "010" then
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			end if;
-		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-			-- INC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0000";
-		when "00110100" =>
-			-- INC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				ALU_Op <= "0000";
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-			-- DEC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0010";
-		when "00110101" =>
-			-- DEC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				ALU_Op <= "0010";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
-		when "00100111" =>
-			-- DAA
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			ALU_Op <= "1100";
-			Save_ALU <= '1';
-		when "00101111" =>
-			-- CPL
-			I_CPL <= '1';
-		when "00111111" =>
-			-- CCF
-			I_CCF <= '1';
-		when "00110111" =>
-			-- SCF
-			I_SCF <= '1';
-		when "00000000" =>
-			if NMICycle = '1' then
-				-- NMI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif IntCycle = '1' then
-				-- INT (IM 2)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					LDZ <= '1';
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 5 =>
-					Jump <= '1';
-				when others => null;
-				end case;
-			else
-				-- NOP
-			end if;
-		when "01110110" =>
-			-- HALT
-			Halt <= '1';
-		when "11110011" =>
-			-- DI
-			SetDI <= '1';
-		when "11111011" =>
-			-- EI
-			SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
-		when "00001001"|"00011001"|"00101001"|"00111001" =>
-			-- ADD HL,ss
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				NoRead <= '1';
-				ALU_Op <= "0000";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusA_To(2 downto 0) <= "101";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-				when others =>
-					Set_BusB_To <= "1000";
-				end case;
-				TStates <= "100";
-				Arith16 <= '1';
-			when 3 =>
-				NoRead <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				ALU_Op <= "0001";
-				Set_BusA_To(2 downto 0) <= "100";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-				when others =>
-					Set_BusB_To <= "1001";
-				end case;
-				Arith16 <= '1';
-			when others =>
-			end case;
-		when "00000011"|"00010011"|"00100011"|"00110011" =>
-			-- INC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "01";
-			IncDec_16(1 downto 0) <= DPair;
-		when "00001011"|"00011011"|"00101011"|"00111011" =>
-			-- DEC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "11";
-			IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
-		when "00000111"
-			-- RLCA
-			|"00010111"
-			-- RLA
-			|"00001111"
-			-- RRCA
-			|"00011111" =>
-			-- RRA
-			Set_BusA_To(2 downto 0) <= "111";
-			ALU_Op <= "1000";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-
--- JUMP GROUP
-		when "11000011" =>
-			-- JP nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				Inc_PC <= '1';
-				Jump <= '1';
-			when others => null;
-			end case;
-		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+C),A
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-						Set_BusB_To     <= "0111";
-					when 2 =>
-						Write <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "01" =>
-					-- LD (nn),A
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						Set_BusB_To <= "0111";
-					when 4 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "10" =>
-					-- LD A,($FF00+C)
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-					when 2 =>
-						Read_To_Acc <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "11" =>
-					-- LD A,(nn)
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-					when 4 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- JP cc,nn
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Jump <= '1';
-					end if;
-				when others => null;
-				end case;
-			end if;
-		when "00011000" =>
-			if Mode /= 2 then
-				-- JR e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00111000" =>
-			if Mode /= 2 then
-				-- JR C,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00110000" =>
-			if Mode /= 2 then
-				-- JR NC,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00101000" =>
-			if Mode /= 2 then
-				-- JR Z,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00100000" =>
-			if Mode /= 2 then
-				-- JR NZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "11101001" =>
-			-- JP (HL)
-			JumpXY <= '1';
-		when "00010000" =>
-			if Mode = 3 then
-				I_DJNZ <= '1';
-			elsif Mode < 2 then
-				-- DJNZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					I_DJNZ <= '1';
-					Set_BusB_To <= "1010";
-					Set_BusA_To(2 downto 0) <= "000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					I_DJNZ <= '1';
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-
--- CALL AND RETURN GROUP
-		when "11001101" =>
-			-- CALL nn
-			MCycles <= "101";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				IncDec_16 <= "1111";
-				Inc_PC <= '1';
-				TStates <= "100";
-				Set_Addr_To <= aSP;
-				LDW <= '1';
-				Set_BusB_To <= "1101";
-			when 4 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 5 =>
-				Write <= '1';
-				Call <= '1';
-			when others => null;
-			end case;
-		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
-			if IR(5) = '0' or Mode /= 3 then
-				-- CALL cc,nn
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					LDW <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						IncDec_16 <= "1111";
-						Set_Addr_TO <= aSP;
-						TStates <= "100";
-						Set_BusB_To <= "1101";
-					else
-						MCycles <= "011";
-					end if;
-				when 4 =>
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 5 =>
-					Write <= '1';
-					Call <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11001001" =>
-			-- RET
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_TO <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				LDZ <= '1';
-			when 3 =>
-				Jump <= '1';
-				IncDec_16 <= "0111";
-			when others => null;
-			end case;
-		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+nn),A
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-						Set_BusB_To     <= "0111";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "01" =>
-					-- ADD SP,n
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						ALU_Op <= "0000";
-						Inc_PC <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_BusA_To <= "1000";
-						Set_BusB_To <= "0110";
-					when 3 =>
-						NoRead <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						ALU_Op <= "0001";
-						Set_BusA_To <= "1001";
-						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
-					when others =>
-					end case;
-				when "10" =>
-					-- LD A,($FF00+nn)
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-					when 3 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				when "11" =>
-					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
-					MCycles <= "101";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						LDW <= '1';
-					when 4 =>
-						Set_BusA_To(2 downto 0) <= "101"; -- L
-						Read_To_Reg <= '1';
-						Inc_WZ <= '1';
-						Set_Addr_To <= aZI;
-					when 5 =>
-						Set_BusA_To(2 downto 0) <= "100"; -- H
-						Read_To_Reg <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- RET cc
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Set_Addr_TO <= aSP;
-					else
-						MCycles <= "001";
-					end if;
-					TStates <= "101";
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-				when others => null;
-				end case;
-			end if;
-		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-			-- RST p
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1101";
-			when 2 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 3 =>
-				Write <= '1';
-				RstP <= '1';
-			when others => null;
-			end case;
-
--- INPUT AND OUTPUT GROUP
-		when "11011011" =>
-			if Mode /= 3 then
-				-- IN A,(n)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-				when 3 =>
-					Read_To_Acc <= '1';
-					IORQ <= '1';
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-				when others => null;
-				end case;
-			end if;
-		when "11010011" =>
-			if Mode /= 3 then
-				-- OUT (n),A
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-					Set_BusB_To <= "0111";
-				when 3 =>
-					Write <= '1';
-					IORQ <= '1';
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-				when others => null;
-				end case;
-			end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
-		when "11001011" =>
-			if Mode /= 2 then
-				Prefix <= "01";
-			end if;
-
-		when "11101101" =>
-			if Mode < 2 then
-				Prefix <= "10";
-			end if;
-
-		when "11011101"|"11111101" =>
-			if Mode < 2 then
-				Prefix <= "11";
-			end if;
-
-		end case;
-
-		when "01" =>
-
-------------------------------------------------------------------------------
---
---      CB prefixed instructions
---
-------------------------------------------------------------------------------
-
-			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
-			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-				-- RLC r
-				-- RL r
-				-- RRC r
-				-- RR r
-				-- SLA r
-				-- SRA r
-				-- SRL r
-				-- SLL r (Undocumented) / SWAP r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1000";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- R/S (IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1000";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-
-			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-				-- RLC (HL)
-				-- RL (HL)
-				-- RRC (HL)
-				-- RR (HL)
-				-- SRA (HL)
-				-- SRL (HL)
-				-- SLA (HL)
-				-- SLL (HL) (Undocumented) / SWAP (HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
-				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-				-- BIT b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-					  ALU_Op <= "1001";
-					end if;
-				else
-				-- BIT b,(IX+d), undocumented
-					MCycles <= "010";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1001";
-						TStates <= "100";
-					when others => null;
-					end case;
-				end if;
-			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-				-- BIT b,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1001";
-					TStates <= "100";
-				when others => null;
-				end case;
-			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-				-- SET b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1010";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- SET b,(IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1010";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-				-- SET b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-				-- RES b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1011";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- RES b,(IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1011";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-				
-			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-				-- RES b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end case;
-
-		when others =>
-
-------------------------------------------------------------------------------
---
---      ED prefixed instructions
---
-------------------------------------------------------------------------------
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
-				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
-				|                                            "10100100"|"10100101"|"10100110"|"10100111"
-				|                                            "10101100"|"10101101"|"10101110"|"10101111"
-				|                                            "10110100"|"10110101"|"10110110"|"10110111"
-				|                                            "10111100"|"10111101"|"10111110"|"10111111"
-				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
-				null; -- NOP, undocumented
-			when "01111110"|"01111111" =>
-				-- NOP, undocumented
-				null;
--- 8 BIT LOAD GROUP
-			when "01010111" =>
-				-- LD A,I
-				Special_LD <= "100";
-				TStates <= "101";
-			when "01011111" =>
-				-- LD A,R
-				Special_LD <= "101";
-				TStates <= "101";
-			when "01000111" =>
-				-- LD I,A
-				Special_LD <= "110";
-				TStates <= "101";
-			when "01001111" =>
-				-- LD R,A
-				Special_LD <= "111";
-				TStates <= "101";
--- 16 BIT LOAD GROUP
-			when "01001011"|"01011011"|"01101011"|"01111011" =>
-				-- LD dd,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1000";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '1';
-					end if;
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1001";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '0';
-					end if;
-				when others => null;
-				end case;
-			when "01000011"|"01010011"|"01100011"|"01110011" =>
-				-- LD (nn),dd
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1000";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1001";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10100000" | "10101000" | "10110000" | "10111000" =>
-				-- LDI, LDD, LDIR, LDDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0000";
-					Set_Addr_To <= aDE;
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- IX
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					I_BT <= '1';
-					TStates <= "101";
-					Write <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0101"; -- DE
-					else
-						IncDec_16 <= "1101";
-					end if;
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100001" | "10101001" | "10110001" | "10111001" =>
-				-- CPI, CPD, CPIR, CPDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0111";
-					Save_ALU <= '1';
-					PreserveC <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0110";
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					I_BC <= '1';
-					TStates <= "101";
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-				-- NEG
-				Alu_OP <= "0010";
-				Set_BusB_To <= "0111";
-				Set_BusA_To <= "1010";
-				Read_To_Acc <= '1';
-				Save_ALU <= '1';
-			when "01000110"|"01001110"|"01100110"|"01101110" =>
-				-- IM 0
-				IMode <= "00";
-			when "01010110"|"01110110" =>
-				-- IM 1
-				IMode <= "01";
-			when "01011110"|"01110111" =>
-				-- IM 2
-				IMode <= "10";
--- 16 bit arithmetic
-			when "01001010"|"01011010"|"01101010"|"01111010" =>
-				-- ADC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0001";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-						when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0001";
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-					when others =>
-						Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01000010"|"01010010"|"01100010"|"01110010" =>
-				-- SBC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-					when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					when others =>
-							Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01101111" =>
-				-- RLD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1101";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RLD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01100111" =>
-				-- RRD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1110";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RRD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-				-- RETI, RETN
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-				when others => null;
-				end case;
-			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-				-- IN r,(C)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					if IR(5 downto 3) /= "110" then
-						Read_To_Reg <= '1';
-						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
-					end if;
-					I_INRC <= '1';
-				when others =>
-				end case;
-			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-				-- OUT (C),r
-				-- OUT (C),0
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
-					if IR(5 downto 3) = "110" then
-						Set_BusB_To(3) <= '1';
-					end if;
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					Write <= '1';
-					IORQ <= '1';
-				when others =>
-				end case;
-			when "10100010" | "10101010" | "10110010" | "10111010" =>
-				-- INI, IND, INIR, INDR
-				-- note B is decremented AFTER being put on the bus
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aXY;
-				when 3 =>
-					if IR(3) = '0' then
-						--IncDec_16 <= "0010";
-						IncDec_16 <= "0110";
-					else
-						--IncDec_16 <= "1010";
-						IncDec_16 <= "1110";
-					end if;
-					TStates <= "100";
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100011" | "10101011" | "10110011" | "10111011" =>
-				-- OUTI, OUTD, OTIR, OTDR
-				-- note B is decremented BEFORE being put on the bus.
-				-- mikej fix for hl inc
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aBC;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- mikej
-					else
-						IncDec_16 <= "1110"; -- mikej
-					end if;
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end case;
-
-		end case;
-
-		if Mode = 1 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "011";
-			end if;
-		end if;
-
-		if Mode = 3 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "100";
-			end if;
-		end if;
-
-		if Mode < 2 then
-			if MCycle = "110" then
-				Inc_PC <= '1';
-				if Mode = 1 then
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-					Set_BusB_To(2 downto 0) <= SSS;
-					Set_BusB_To(3) <= '0';
-				end if;
-				if IRB = "00110110" or IRB = "11001011" then
-					Set_Addr_To <= aNone;
-				end if;
-			end if;
-			if MCycle = "111" then
-				if Mode = 0 then
-					TStates <= "101";
-				end if;
-				if ISet /= "01" then
-					Set_Addr_To <= aXY;
-				end if;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-				if IRB = "00110110" or ISet = "01" then
-					-- LD (HL),n
-					Inc_PC <= '1';
-				else
-					NoRead <= '1';
-				end if;
-			end if;
-		end if;
-
-	end process;
-
-end;
diff --git a/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/cpu/T80_Pack.vhd
deleted file mode 100644
index 6904b66b..00000000
--- a/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/cpu/T80_Pack.vhd	
+++ /dev/null
@@ -1,220 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
-	component T80
-	generic(
-		Mode : integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		RESET_n         : in std_logic;
-		CLK_n           : in std_logic;
-		CEN                     : in std_logic;
-		WAIT_n          : in std_logic;
-		INT_n           : in std_logic;
-		NMI_n           : in std_logic;
-		BUSRQ_n         : in std_logic;
-		M1_n            : out std_logic;
-		IORQ            : out std_logic;
-		NoRead          : out std_logic;
-		Write           : out std_logic;
-		RFSH_n          : out std_logic;
-		HALT_n          : out std_logic;
-		BUSAK_n         : out std_logic;
-		A                       : out std_logic_vector(15 downto 0);
-		DInst           : in std_logic_vector(7 downto 0);
-		DI                      : in std_logic_vector(7 downto 0);
-		DO                      : out std_logic_vector(7 downto 0);
-		MC                      : out std_logic_vector(2 downto 0);
-		TS                      : out std_logic_vector(2 downto 0);
-		IntCycle_n      : out std_logic;
-		IntE            : out std_logic;
-		Stop            : out std_logic
-	);
-	end component;
-
-	component T80_Reg
-	port(
-		Clk                     : in std_logic;
-		CEN                     : in std_logic;
-		WEH                     : in std_logic;
-		WEL                     : in std_logic;
-		AddrA           : in std_logic_vector(2 downto 0);
-		AddrB           : in std_logic_vector(2 downto 0);
-		AddrC           : in std_logic_vector(2 downto 0);
-		DIH                     : in std_logic_vector(7 downto 0);
-		DIL                     : in std_logic_vector(7 downto 0);
-		DOAH            : out std_logic_vector(7 downto 0);
-		DOAL            : out std_logic_vector(7 downto 0);
-		DOBH            : out std_logic_vector(7 downto 0);
-		DOBL            : out std_logic_vector(7 downto 0);
-		DOCH            : out std_logic_vector(7 downto 0);
-		DOCL            : out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-	component T80_MCode
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR                      : in  std_logic_vector(7 downto 0);
-		ISet                    : in  std_logic_vector(1 downto 0);
-		MCycle                  : in  std_logic_vector(2 downto 0);
-		F                       : in  std_logic_vector(7 downto 0);
-		NMICycle                : in  std_logic;
-		IntCycle                : in  std_logic;
-		XY_State                : in  std_logic_vector(1 downto 0);
-		MCycles                 : out std_logic_vector(2 downto 0);
-		TStates                 : out std_logic_vector(2 downto 0);
-		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC                  : out std_logic;
-		Inc_WZ                  : out std_logic;
-		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg             : out std_logic;
-		Read_To_Acc             : out std_logic;
-		Set_BusA_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op                  : out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU                : out std_logic;
-		PreserveC               : out std_logic;
-		Arith16                 : out std_logic;
-		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ                    : out std_logic;
-		Jump                    : out std_logic;
-		JumpE                   : out std_logic;
-		JumpXY                  : out std_logic;
-		Call                    : out std_logic;
-		RstP                    : out std_logic;
-		LDZ                     : out std_logic;
-		LDW                     : out std_logic;
-		LDSPHL                  : out std_logic;
-		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH              : out std_logic;
-		ExchangeRp              : out std_logic;
-		ExchangeAF              : out std_logic;
-		ExchangeRS              : out std_logic;
-		I_DJNZ                  : out std_logic;
-		I_CPL                   : out std_logic;
-		I_CCF                   : out std_logic;
-		I_SCF                   : out std_logic;
-		I_RETN                  : out std_logic;
-		I_BT                    : out std_logic;
-		I_BC                    : out std_logic;
-		I_BTR                   : out std_logic;
-		I_RLD                   : out std_logic;
-		I_RRD                   : out std_logic;
-		I_INRC                  : out std_logic;
-		SetDI                   : out std_logic;
-		SetEI                   : out std_logic;
-		IMode                   : out std_logic_vector(1 downto 0);
-		Halt                    : out std_logic;
-		NoRead                  : out std_logic;
-		Write                   : out std_logic;
-		XYbit_undoc             : out std_logic
-	);
-	end component;
-
-	component T80_ALU
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16         : in  std_logic;
-		Z16             : in  std_logic;
-		ALU_Op          : in  std_logic_vector(3 downto 0);
-		IR              : in  std_logic_vector(5 downto 0);
-		ISet            : in  std_logic_vector(1 downto 0);
-		BusA            : in  std_logic_vector(7 downto 0);
-		BusB            : in  std_logic_vector(7 downto 0);
-		F_In            : in  std_logic_vector(7 downto 0);
-		Q               : out std_logic_vector(7 downto 0);
-		F_Out           : out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-end;
diff --git a/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/cpu/T80_Reg.vhd
deleted file mode 100644
index 998033ef..00000000
--- a/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/cpu/T80_Reg.vhd	
+++ /dev/null
@@ -1,114 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
---      0242 : Initial release
---
---      0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
-  port(
-    Clk   : in  std_logic;
-    CEN   : in  std_logic;
-    WEH   : in  std_logic;
-    WEL   : in  std_logic;
-    AddrA : in  std_logic_vector(2 downto 0);
-    AddrB : in  std_logic_vector(2 downto 0);
-    AddrC : in  std_logic_vector(2 downto 0);
-    DIH   : in  std_logic_vector(7 downto 0);
-    DIL   : in  std_logic_vector(7 downto 0);
-    DOAH  : out std_logic_vector(7 downto 0);
-    DOAL  : out std_logic_vector(7 downto 0);
-    DOBH  : out std_logic_vector(7 downto 0);
-    DOBL  : out std_logic_vector(7 downto 0);
-    DOCH  : out std_logic_vector(7 downto 0);
-    DOCL  : out std_logic_vector(7 downto 0)
-    );
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
-  type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
-  signal      RegsH   : Register_Image(0 to 7);
-  signal      RegsL   : Register_Image(0 to 7);
-
-begin
-
-  process (Clk)
-  begin
-    if Clk'event and Clk = '1' then
-      if CEN = '1' then
-        if WEH = '1' then
-          RegsH(to_integer(unsigned(AddrA))) <= DIH;
-        end if;
-        if WEL = '1' then
-          RegsL(to_integer(unsigned(AddrA))) <= DIL;
-        end if;
-      end if;
-    end if;
-  end process;
-
-  DOAH <= RegsH(to_integer(unsigned(AddrA)));
-  DOAL <= RegsL(to_integer(unsigned(AddrA)));
-  DOBH <= RegsH(to_integer(unsigned(AddrB)));
-  DOBL <= RegsL(to_integer(unsigned(AddrB)));
-  DOCH <= RegsH(to_integer(unsigned(AddrC)));
-  DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
diff --git a/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/cpu/T80a.vhd b/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/cpu/T80a.vhd
deleted file mode 100644
index 33d61068..00000000
--- a/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/cpu/T80a.vhd	
+++ /dev/null
@@ -1,280 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core, asynchronous top level
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0211 : Fixed interrupt cycle
---
---      0235 : Updated for T80 interface change
---
---      0238 : Updated for T80 interface change
---
---      0240 : Updated for T80 interface change
---
---      0242 : Updated for T80 interface change
---
---      0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80a is
-  generic(
-    Mode : integer := 0     -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-    );
-  port(
-    RESET_n    : in  std_logic;
-    CLK_n      : in  std_logic;
-    CLK_EN_SYS : in  std_logic;
-    WAIT_n     : in  std_logic;
-    INT_n      : in  std_logic;
-    NMI_n      : in  std_logic;
-    BUSRQ_n    : in  std_logic;
-    M1_n       : out std_logic;
-    MREQ_n     : out std_logic;
-    IORQ_n     : out std_logic;
-    RD_n       : out std_logic;
-    WR_n       : out std_logic;
-    RFSH_n     : out std_logic;
-    HALT_n     : out std_logic;
-    BUSAK_n    : out std_logic;
-    A          : out std_logic_vector(15 downto 0);
-		DI						: in  std_logic_vector(7 downto 0);
-		DO						: out std_logic_vector(7 downto 0)
-    );
-end T80a;
-
-architecture rtl of T80a is
-
-  signal CEN          : std_logic;
-  signal Reset_s      : std_logic;
-  signal IntCycle_n   : std_logic;
-  signal IORQ         : std_logic;
-  signal NoRead       : std_logic;
-  signal Write        : std_logic;
-  signal MREQ         : std_logic;
-  signal MReq_Inhibit : std_logic;
-  signal Req_Inhibit  : std_logic;
-  signal RD           : std_logic;
-  signal MREQ_n_i     : std_logic;
-  signal IORQ_n_i     : std_logic;
-  signal RD_n_i       : std_logic;
-  signal WR_n_i       : std_logic;
-  signal RFSH_n_i     : std_logic;
-  signal BUSAK_n_i    : std_logic;
-  signal A_i          : std_logic_vector(15 downto 0);
-	signal DO_Reg			: std_logic_vector(7 downto 0);
-  signal DI_Reg       : std_logic_vector (7 downto 0);  -- Input synchroniser
-  signal Wait_s       : std_logic;
-  signal MCycle       : std_logic_vector(2 downto 0);
-  signal TState       : std_logic_vector(2 downto 0);
-
-begin
-
-  -- clock enable supplied from clocking system
-  CEN <= CLK_EN_SYS;
-
-  BUSAK_n <= BUSAK_n_i;
-  MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
-  RD_n_i <= not RD or Req_Inhibit;
-
-  MREQ_n <= MREQ_n_i;
-  IORQ_n <= IORQ_n_i;
-  RD_n <= RD_n_i;
-  WR_n <= WR_n_i;
-  RFSH_n <= RFSH_n_i;
-  A <= A_i;
-	DO <= DO_Reg;
-
---   process (RESET_n, CLK_n)
---   begin
---     if RESET_n = '0' then
---       Reset_s <= '0';
---     elsif CLK_n'event and CLK_n = '1' then
---       Reset_s <= '1';
---     end if;
---   end process;
-  -- T80 reset input has already proper characteristics:
-  --   * asynchronous assertion
-  --   * deassertion synchronous to CLK_n (main_clk)
-  Reset_s <= RESET_n;
-
-  u0 : T80
-    generic map(
-      Mode       => Mode,
-      IOWait     => 1)
-    port map(
-      CEN        => CEN,
-      M1_n       => M1_n,
-      IORQ       => IORQ,
-      NoRead     => NoRead,
-      Write      => Write,
-      RFSH_n     => RFSH_n_i,
-      HALT_n     => HALT_n,
-      WAIT_n     => Wait_s,
-      INT_n      => INT_n,
-      NMI_n      => NMI_n,
-      RESET_n    => Reset_s,
-      BUSRQ_n    => BUSRQ_n,
-      BUSAK_n    => BUSAK_n_i,
-      CLK_n      => CLK_n,
-      A          => A_i,
-			DInst => DI,
-      DI         => DI_Reg,
-			DO => DO_Reg,
-      MC         => MCycle,
-      TS         => TState,
-      IntCycle_n => IntCycle_n);
-
-  process (CLK_n)
-  begin
-    if CLK_n'event and CLK_n = '0' then
-      if CEN = '1' then
-        Wait_s <= WAIT_n;
-        if TState = "011" and BUSAK_n_i = '1' then
-					DI_Reg <= to_x01(DI);
-        end if;
-      end if;
-    end if;
-  end process;
-
-  process (Reset_s,CLK_n)
-  begin
-    if Reset_s = '0' then
-      WR_n_i <= '1';
-    elsif CLK_n'event and CLK_n = '1' then
-      if CEN = '1' then
-        WR_n_i <= '1';
-        if TState = "001" then      -- To short for IO writes !!!!!!!!!!!!!!!!!!!
-          WR_n_i <= not Write;
-        end if;
-      end if;
-    end if;
-  end process;
-
-  process (Reset_s,CLK_n)
-  begin
-    if Reset_s = '0' then
-      Req_Inhibit <= '0';
-    elsif CLK_n'event and CLK_n = '1' then
-      if CEN = '1' then
-        if MCycle = "001" and TState = "010" then
-          Req_Inhibit <= '1';
-        else
-          Req_Inhibit <= '0';
-        end if;
-      end if;
-    end if;
-  end process;
-
-  process (Reset_s,CLK_n)
-  begin
-    if Reset_s = '0' then
-      MReq_Inhibit <= '0';
-    elsif CLK_n'event and CLK_n = '0' then
-      if CEN = '1' then
-        if MCycle = "001" and TState = "010" then
-          MReq_Inhibit <= '1';
-        else
-          MReq_Inhibit <= '0';
-        end if;
-      end if;
-    end if;
-  end process;
-
-  process(Reset_s,CLK_n)
-  begin
-    if Reset_s = '0' then
-      RD <= '0';
-      IORQ_n_i <= '1';
-      MREQ <= '0';
-    elsif CLK_n'event and CLK_n = '0' then
-      if CEN = '1' then
-
-        if MCycle = "001" then
-          if TState = "001" then
-            RD <= IntCycle_n;
-            MREQ <= IntCycle_n;
-            IORQ_n_i <= IntCycle_n;
-          end if;
-          if TState = "011" then
-            RD <= '0';
-            IORQ_n_i <= '1';
-            MREQ <= '1';
-          end if;
-          if TState = "100" then
-            MREQ <= '0';
-          end if;
-        else
-          if TState = "001" and NoRead = '0' then
-            RD <= not Write;
-            IORQ_n_i <= not IORQ;
-            MREQ <= not IORQ;
-          end if;
-          if TState = "011" then
-            RD <= '0';
-            IORQ_n_i <= '1';
-            MREQ <= '0';
-          end if;
-        end if;
-
-      end if;
-    end if;
-  end process;
-
-end;
diff --git a/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/ladybug.vhd b/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/ladybug.vhd
index b19b5cf8..9bf14857 100644
--- a/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/ladybug.vhd	
+++ b/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/ladybug.vhd	
@@ -65,7 +65,7 @@ port (
 	O_PIXCE      : out std_logic;
 
 	-- Audio Interface --------------------------------------------------------
-	O_AUDIO      : out signed(7 downto 0);
+	O_AUDIO      : out std_logic_vector( 8 downto 0);
 	
 	but_coin_s   : in  std_logic_vector( 1 downto 0);
 	but_fire_s   : in  std_logic_vector( 1 downto 0);
@@ -160,8 +160,8 @@ begin
 		rgb_b_o           => O_VIDEO_B,
 		hsync_n_o         => O_HSYNC,
 		vsync_n_o         => O_VSYNC,
-	   vblank_o          => O_VBLANK,
-	   hblank_o          => O_HBLANK,
+		vblank_o          => O_VBLANK,
+		hblank_o          => O_HBLANK,
 		audio_o           => O_AUDIO,
 		rom_cpu_a_o       => rom_cpu_a_s,
 		rom_cpu_d_i       => rom_cpu_d_s,
diff --git a/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_cpu_unit.vhd b/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_cpu_unit.vhd
index 7d41074f..5646437b 100644
--- a/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_cpu_unit.vhd	
+++ b/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_cpu_unit.vhd	
@@ -119,14 +119,14 @@ begin
   -- "wait" has to be modelled with the clock enable because the T80 is not
   -- able to enlarge write accesses properly when they are delayed with "wait"
   t80_clk_en_s <= clk_en_4mhz_i and wait_n_s;
-  T80a_b : entity work.T80a
+  T80a_b : entity work.T80s
     generic map (
       Mode => 0
     )
     port map (
       RESET_n    => res_n_i,
-      CLK_n      => clk_20mhz_i,
-      CLK_EN_SYS => t80_clk_en_s,
+      CLK        => clk_20mhz_i,
+      CEN        => t80_clk_en_s,
       WAIT_n     => wait_n_s,
       INT_n      => int_n_s,
       NMI_n      => nmi_n_s,
diff --git a/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_machine.vhd b/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_machine.vhd
index 584b8391..dbe5d75b 100644
--- a/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_machine.vhd	
+++ b/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_machine.vhd	
@@ -77,10 +77,10 @@ entity ladybug_machine is
     hsync_n_o         : out std_logic;
     vsync_n_o         : out std_logic;
     comp_sync_n_o     : out std_logic;
-	 vblank_o          : out std_logic;
-	 hblank_o          : out std_logic;
+    vblank_o          : out std_logic;
+    hblank_o          : out std_logic;
     -- Audio Interface --------------------------------------------------------
-    audio_o           : out signed( 7 downto 0);
+    audio_o           : out std_logic_vector( 8 downto 0);
     -- CPU ROM Interface ------------------------------------------------------
     rom_cpu_a_o       : out std_logic_vector(14 downto 0);
     rom_cpu_d_i       : in  std_logic_vector( 7 downto 0);
diff --git a/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/ladybug_sound_unit.vhd b/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_sound_unit.vhd
similarity index 88%
rename from Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/ladybug_sound_unit.vhd
rename to Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_sound_unit.vhd
index 23ad2a6a..8fe04ba8 100644
--- a/Arcade_MiST/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/ladybug_sound_unit.vhd	
+++ b/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_sound_unit.vhd	
@@ -59,7 +59,7 @@ entity ladybug_sound_unit is
     wr_n_i         : in  std_logic;
     d_from_cpu_i   : in  std_logic_vector(7 downto 0);
     sound_wait_n_o : out std_logic;
-    audio_o        : out signed(7 downto 0)
+    audio_o        : out std_logic_vector(8 downto 0)
   );
 
 end ladybug_sound_unit;
@@ -70,7 +70,7 @@ architecture struct of ladybug_sound_unit is
          ready_c1_s  : std_logic;
 
   signal aout_b1_s,
-         aout_c1_s   : signed(7 downto 0);
+         aout_c1_s   : std_logic_vector(7 downto 0);
 
 begin
 
@@ -117,23 +117,7 @@ begin
   --
   -- Purpose:
   --   Mix the digital audio of the two SN76489 instances.
-  --   Additional care is taken to avoid audio overfow/clipping.
-  --
-  mix: process (aout_b1_s,
-                aout_c1_s)
-    variable sum_v : signed(8 downto 0);
-  begin
-    sum_v := RESIZE(aout_b1_s, 9) + RESIZE(aout_c1_s, 9);
-
-    if sum_v > 127 then
-      audio_o <= to_signed(127, 8);
-    elsif sum_v < -128 then
-      audio_o <= to_signed(-128, 8);
-    else
-      audio_o <= RESIZE(sum_v, 8);
-    end if;
-
-  end process mix;
+  audio_o <= std_logic_vector(unsigned('0'&aout_b1_s) + unsigned('0'&aout_c1_s));
   -- 
   -----------------------------------------------------------------------------
 
diff --git a/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/COPYING b/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/COPYING
deleted file mode 100644
index 60549be5..00000000
--- a/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/COPYING	
+++ /dev/null
@@ -1,340 +0,0 @@
-		    GNU GENERAL PUBLIC LICENSE
-		       Version 2, June 1991
-
- Copyright (C) 1989, 1991 Free Software Foundation, Inc.
-                       59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- Everyone is permitted to copy and distribute verbatim copies
- of this license document, but changing it is not allowed.
-
-			    Preamble
-
-  The licenses for most software are designed to take away your
-freedom to share and change it.  By contrast, the GNU General Public
-License is intended to guarantee your freedom to share and change free
-software--to make sure the software is free for all its users.  This
-General Public License applies to most of the Free Software
-Foundation's software and to any other program whose authors commit to
-using it.  (Some other Free Software Foundation software is covered by
-the GNU Library General Public License instead.)  You can apply it to
-your programs, too.
-
-  When we speak of free software, we are referring to freedom, not
-price.  Our General Public Licenses are designed to make sure that you
-have the freedom to distribute copies of free software (and charge for
-this service if you wish), that you receive source code or can get it
-if you want it, that you can change the software or use pieces of it
-in new free programs; and that you know you can do these things.
-
-  To protect your rights, we need to make restrictions that forbid
-anyone to deny you these rights or to ask you to surrender the rights.
-These restrictions translate to certain responsibilities for you if you
-distribute copies of the software, or if you modify it.
-
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diff --git a/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/README b/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/README
deleted file mode 100644
index 33630144..00000000
--- a/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/README	
+++ /dev/null
@@ -1,143 +0,0 @@
-
-An SN76489AN Compatible Implementation in VHDL
-==============================================
-Version: $Date: 2006/06/18 19:28:40 $
-
-Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
-See the file COPYING.
-
-
-Integration
------------
-
-The sn76489 design exhibits all interface signals as the original chip. It
-only differs in the audio data output which is provided as an 8 bit signed
-vector instead of an analog output pin.
-
-  generic (
-    clock_div_16_g : integer := 1
-    -- Set to '1' when operating the design in SN76489 mode. The primary clock
-    -- input is divided by 16 in this variant. The data sheet mentions the
-    -- SN76494 which contains a divide-by-2 clock input stage. Set the generic
-    -- to '0' to enable this mode.
-  );
-  port (
-    clock_i    : in  std_logic;
-    -- Primary clock input
-    -- Drive with the target frequency or any integer multiple of it.
-
-    clock_en_i : in  std_logic;
-    -- Clock enable
-    -- A '1' on this input qualifies a valid rising edge on clock_i. A '0'
-    -- disables the next rising clock edge, effectivley halting the design
-    -- until the next enabled rising clock edge.
-    -- Can be used to run the core at lower frequencies than applied on
-    -- clock_i.
-
-    res_n_i    : in  std_logic;
-    -- Asynchronous low active reset input.
-    -- Sets all sequential elements to a known state.
-
-    ce_n_i     : in  std_logic;
-    -- Chip enable, low active.
-
-    we_n_i     : in  std_logic;
-    -- Write enable, low active.
-
-    ready_o    : out std_logic;
-    -- Ready indication to microprocessor.
-
-    d_i        : in  std_logic_vector(0 to 7);
-    -- Data input
-    -- MSB 0 ... 7 LSB
-
-    aout_o     : out signed(0 to 7)
-    -- Audio output, signed vector
-    -- MSB/SIGN 0 ... 7 LSB
-  );
-
-
-Both 8 bit vector ports are defined (0 to 7) which declares bit 0 to be the
-MSB and bit 7 to be the LSB. This has been implemented according to TI's data
-sheet, thus all register/data format figures apply 1:1 for this design.
-Many systems will flip the system data bus bit wise before it is connected to
-this PSG. This is simply achieved with the following VHDL construct:
-
-  signal data_s : std_logic_vector(7 downto 0);
-
-  ...
-  d_i => data_s,
-  ...
-
-d_i and data_s will be assigned from left to right, resulting in the expected
-bit assignment:
-
-  d_i    data_s
-   0       7
-   1       6
-      ...
-   6       1
-   7       0
-
-
-As this design is fully synchronous, care has to be taken when the design
-replaces an SN76489 in asynchronous mode. No problems are expected when
-interfacing the code to other synchronous components.
-
-
-Design Hierarchy
-----------------
-
-  sn76489_top
-    |
-    +-- sn76489_latch_ctrl
-    |
-    +-- sn76489_clock_div
-    |
-    +-- sn76489_tone
-    |     |
-    |     \-- sn76489_attentuator
-    |
-    +-- sn76489_tone
-    |     |
-    |     \-- sn76489_attentuator
-    |
-    +-- sn76489_tone
-    |     |
-    |     \-- sn76489_attentuator
-    |
-    \-- sn76489_noise
-          |
-          \-- sn76489_attentuator
-
-Resulting compilation sequence:
-
-  sn76489_comp_pack-p.vhd
-  sn76489_top.vhd
-  sn76489_latch_ctrl.vhd
-  sn76489_latch_ctrl-c.vhd
-  sn76489_clock_div.vhd
-  sn76489_clock_div-c.vhd
-  sn76489_attenuator.vhd
-  sn76489_attenuator-c.vhd
-  sn76489_tone.vhd
-  sn76489_tone-c.vhd
-  sn76489_noise.vhd
-  sn76489_noise-c.vhd
-  sn76489_top-c.vhd
-
-Skip the files containing VHDL configurations when analyzing the code for
-synthesis.
-
-
-References
-----------
-
-* TI Data sheet SN76489.pdf
-  ftp://ftp.whtech.com/datasheets%20&%20manuals/SN76489.pdf
-
-* John Kortink's article on the SN76489:
-  http://web.inter.nl.net/users/J.Kortink/home/articles/sn76489/
-
-* Maxim's "SN76489 notes" in
-  http://www.smspower.org/maxim/docs/SN76489.txt
diff --git a/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/sn76489_attenuator.vhd b/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/sn76489_attenuator.vhd
deleted file mode 100644
index 444064e5..00000000
--- a/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/sn76489_attenuator.vhd	
+++ /dev/null
@@ -1,114 +0,0 @@
--------------------------------------------------------------------------------
---
--- Synthesizable model of TI's SN76489AN.
---
--- $Id: sn76489_attenuator.vhd,v 1.7 2006/02/27 20:30:10 arnim Exp $
---
--- Attenuator Module
---
--------------------------------------------------------------------------------
---
--- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity sn76489_attenuator is
-
-  port (
-    attenuation_i : in  std_logic_vector(0 to 3);
-    factor_i      : in  signed(0 to 1);
-    product_o     : out signed(0 to 7)
-  );
-
-end sn76489_attenuator;
-
-
-architecture rtl of sn76489_attenuator is
-
-begin
-
-  -----------------------------------------------------------------------------
-  -- Process attenuate
-  --
-  -- Purpose:
-  --   Determine the attenuation and generate the resulting product.
-  --
-  --   The maximum attenuation value is 31 which corresponds to volume off.
-  --   As described in the data sheet, the maximum "playing" attenuation is
-  --     28 = 16 + 8 + 4
-  --
-  --   The table for the volume constants is derived from the following
-  --   formula (each step is 2dB voltage):
-  --     v(0)   = 31
-  --     v(n+1) = v(n) * 0.79432823
-  --
-  attenuate: process (attenuation_i,
-                      factor_i)
-
-    type     volume_t is array (natural range 0 to 15) of natural;
-    constant volume_c : volume_t :=
-      (31, 25, 20, 16, 12, 10, 8, 6, 5, 4, 3, 2, 2, 2, 1, 0);
-
-    variable attenuation_v  : unsigned(attenuation_i'range);
-    variable volume_v       : signed(product_o'range);
-
-  begin
-
-    attenuation_v := unsigned(attenuation_i);
-
-    -- volume look-up table
-    volume_v := to_signed(volume_c(to_integer(attenuation_v)),
-                          product_o'length);
-
-    -- this replaces a multiplier and consumes a bit fewer
-    -- resources
-    case to_integer(factor_i) is
-      when +1 =>
-        product_o <= volume_v;
-      when -1 =>
-        product_o <= -volume_v;
-      when others =>
-        product_o <= (others => '0');
-    end case;
-
-  end process attenuate;
-  --
-  -----------------------------------------------------------------------------
-
-end rtl;
diff --git a/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/sn76489_clock_div.vhd b/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/sn76489_clock_div.vhd
deleted file mode 100644
index eab86beb..00000000
--- a/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/sn76489_clock_div.vhd	
+++ /dev/null
@@ -1,134 +0,0 @@
--------------------------------------------------------------------------------
---
--- Synthesizable model of TI's SN76489AN.
---
--- $Id: sn76489_clock_div.vhd,v 1.4 2005/10/10 21:51:27 arnim Exp $
---
--- Clock Divider Circuit
---
--------------------------------------------------------------------------------
---
--- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity sn76489_clock_div is
-
-  generic (
-    clock_div_16_g : integer := 1
-  );
-  port (
-    clock_i    : in  std_logic;
-    clock_en_i : in  std_logic;
-    res_n_i    : in  std_logic;
-    clk_en_o   : out boolean
-  );
-
-end sn76489_clock_div;
-
-
-library ieee;
-use ieee.numeric_std.all;
-
-architecture rtl of sn76489_clock_div is
-
-  signal cnt_s,
-         cnt_q  : unsigned(3 downto 0);
-
-begin
-
-  -----------------------------------------------------------------------------
-  -- Process seq
-  --
-  -- Purpose:
-  --   Implements the sequential counter element.
-  --
-  seq: process (clock_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      cnt_q <= (others => '0');
-    elsif clock_i'event and clock_i = '1' then
-      cnt_q <= cnt_s;
-    end if;
-  end process seq;
-  --
-  -----------------------------------------------------------------------------
-
-
-  -----------------------------------------------------------------------------
-  -- Process comb
-  --
-  -- Purpose:
-  --   Implements the combinational counter logic.
-  --
-  comb: process (clock_en_i,
-                 cnt_q)
-  begin
-    -- default assignments
-    cnt_s    <= cnt_q;
-    clk_en_o <= false;
-
-    if clock_en_i = '1' then
-
-      if cnt_q = 0 then
-        clk_en_o <= true;
-
-        if clock_div_16_g = 1 then
-          cnt_s  <= to_unsigned(15, cnt_q'length);
-        elsif clock_div_16_g = 0 then
-          cnt_s  <= to_unsigned( 1, cnt_q'length);
-        else
-          -- pragma translate_off
-          assert false
-            report "Generic clock_div_16_g must be either 0 or 1."
-            severity failure;
-          -- pragma translate_on
-        end if;
-
-      else
-        cnt_s    <= cnt_q - 1;
-
-      end if;
-
-    end if;
-
-  end process comb;
-  --
-  -----------------------------------------------------------------------------
-
-end rtl;
diff --git a/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/sn76489_latch_ctrl.vhd b/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/sn76489_latch_ctrl.vhd
deleted file mode 100644
index 789720c2..00000000
--- a/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/sn76489_latch_ctrl.vhd	
+++ /dev/null
@@ -1,138 +0,0 @@
--------------------------------------------------------------------------------
---
--- Synthesizable model of TI's SN76489AN.
---
--- $Id: sn76489_latch_ctrl.vhd,v 1.6 2006/02/27 20:30:10 arnim Exp $
---
--- Latch Control Unit
---
--------------------------------------------------------------------------------
---
--- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity sn76489_latch_ctrl is
-
-  port (
-    clock_i    : in  std_logic;
-    clk_en_i   : in  boolean;
-    res_n_i    : in  std_logic;
-    ce_n_i     : in  std_logic;
-    we_n_i     : in  std_logic;
-    d_i        : in  std_logic_vector(0 to 7);
-    ready_o    : out std_logic;
-    tone1_we_o : out boolean;
-    tone2_we_o : out boolean;
-    tone3_we_o : out boolean;
-    noise_we_o : out boolean;
-    r2_o       : out std_logic
-  );
-
-end sn76489_latch_ctrl;
-
-
-library ieee;
-use ieee.numeric_std.all;
-
-architecture rtl of sn76489_latch_ctrl is
-
-  signal reg_q   : std_logic_vector(0 to 2);
-  signal we_q    : boolean;
-  signal ready_q : std_logic;
-
-begin
-
-  -----------------------------------------------------------------------------
-  -- Process seq
-  --
-  -- Purpose:
-  --   Implements the sequential elements.
-  --
-  seq: process (clock_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      reg_q     <= (others => '0');
-      we_q      <= false;
-      ready_q   <= '0';
-
-    elsif clock_i'event and clock_i = '1' then
-      -- READY Flag Output ----------------------------------------------------
-      if ready_q = '0' and we_q then
-        if clk_en_i then
-          -- assert READY when write access happened
-          ready_q <= '1';
-        end if;
-      elsif ce_n_i = '1' then
-        -- deassert READY when access has finished
-        ready_q <= '0';
-      end if;
-
-      -- Register Selection ---------------------------------------------------
-      if ce_n_i = '0' and we_n_i = '0' then
-        if clk_en_i then
-          if d_i(0) = '1' then
-            reg_q <= d_i(1 to 3);
-          end if;
-          we_q  <= true;
-        end if;
-      else
-        we_q  <= false;
-      end if;
-
-    end if;
-  end process seq;
-  --
-  -----------------------------------------------------------------------------
-
-
-  -----------------------------------------------------------------------------
-  -- Output mapping
-  -----------------------------------------------------------------------------
-  tone1_we_o <= reg_q(0 to 1) = "00" and we_q;
-  tone2_we_o <= reg_q(0 to 1) = "01" and we_q;
-  tone3_we_o <= reg_q(0 to 1) = "10" and we_q;
-  noise_we_o <= reg_q(0 to 1) = "11" and we_q;
-
-  r2_o       <= reg_q(2);
-
-  ready_o    <=   ready_q
-                when ce_n_i = '0' else
-                  '1';
-
-end rtl;
diff --git a/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/sn76489_noise.vhd b/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/sn76489_noise.vhd
deleted file mode 100644
index 688bdd56..00000000
--- a/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/sn76489_noise.vhd	
+++ /dev/null
@@ -1,278 +0,0 @@
--------------------------------------------------------------------------------
---
--- Synthesizable model of TI's SN76489AN.
---
--- $Id: sn76489_noise.vhd,v 1.6 2006/02/27 20:30:10 arnim Exp $
---
--- Noise Generator
---
--------------------------------------------------------------------------------
---
--- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity sn76489_noise is
-
-  port (
-    clock_i    : in  std_logic;
-    clk_en_i   : in  boolean;
-    res_n_i    : in  std_logic;
-    we_i       : in  boolean;
-    d_i        : in  std_logic_vector(0 to 7);
-    r2_i       : in  std_logic;
-    tone3_ff_i : in  std_logic;
-    noise_o    : out signed(0 to 7)
-  );
-
-end sn76489_noise;
-
-architecture rtl of sn76489_noise is
-
-  signal nf_q       : std_logic_vector(0 to 1);
-  signal fb_q       : std_logic;
-  signal a_q        : std_logic_vector(0 to 3);
-  signal freq_cnt_q : unsigned(0 to 6);
-  signal freq_ff_q  : std_logic;
-
-  signal shift_source_s,
-         shift_source_q    : std_logic;
-  signal shift_rise_edge_s : boolean;
-
-  signal lfsr_q            : std_logic_vector(0 to 15);
-
-  signal freq_s      : signed(0 to 1);
-
-begin
-
-  -----------------------------------------------------------------------------
-  -- Process cpu_regs
-  --
-  -- Purpose:
-  --   Implements the registers writable by the CPU.
-  --
-  cpu_regs: process (clock_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      nf_q <= (others => '0');
-      fb_q <= '0';
-      a_q  <= (others => '1');
-
-    elsif clock_i'event and clock_i = '1' then
-      if clk_en_i and we_i then
-        if r2_i = '0' then
-          -- access to control register
-          -- both access types can write to the control register!
-          nf_q <= d_i(6 to 7);
-          fb_q <= d_i(5);
-
-        else
-          -- access to attenuator register
-          -- both access types can write to the attenuator register!
-          a_q <= d_i(4 to 7);
-
-        end if;
-      end if;
-    end if;
-  end process cpu_regs;
-  --
-  -----------------------------------------------------------------------------
-
-
-  -----------------------------------------------------------------------------
-  -- Process freq_gen
-  --
-  -- Purpose:
-  --   Implements the frequency generation components.
-  --
-  freq_gen: process (clock_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      freq_cnt_q <= (others => '0');
-      freq_ff_q  <= '0';
-
-    elsif clock_i'event and clock_i = '1' then
-      if clk_en_i then
-        if freq_cnt_q = 0 then
-          -- reload frequency counter according to NF setting
-          case nf_q is
-            when "00" =>
-              freq_cnt_q <= to_unsigned(16 * 2 - 1, freq_cnt_q'length);
-            when "01" =>
-              freq_cnt_q <= to_unsigned(16 * 4 - 1, freq_cnt_q'length);
-            when "10" =>
-              freq_cnt_q <= to_unsigned(16 * 8 - 1, freq_cnt_q'length);
-            when others =>
-              null;
-          end case;
-
-          freq_ff_q <= not freq_ff_q;
-
-        else
-          -- decrement frequency counter
-          freq_cnt_q <= freq_cnt_q - 1;
-
-        end if;
-
-      end if;
-    end if;
-  end process freq_gen;
-  --
-  -----------------------------------------------------------------------------
-
-
-  -----------------------------------------------------------------------------
-  -- Multiplex the source of the LFSR's shift enable
-  -----------------------------------------------------------------------------
-  shift_source_s <=   tone3_ff_i
-                    when nf_q = "11" else
-                      freq_ff_q;
-
-  -----------------------------------------------------------------------------
-  -- Process rise_edge
-  --
-  -- Purpose:
-  --   Detect the rising edge of the selected LFSR shift source.
-  --
-  rise_edge: process (clock_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      shift_source_q <= '0';
-
-    elsif clock_i'event and clock_i = '1' then
-      if clk_en_i then
-        shift_source_q <= shift_source_s;
-      end if;
-    end if;
-  end process rise_edge;
-  --
-  -----------------------------------------------------------------------------
-
-  -- detect rising edge on shift source
-  shift_rise_edge_s <= shift_source_q = '0' and shift_source_s = '1';
-
-
-  -----------------------------------------------------------------------------
-  -- Process lfsr
-  --
-  -- Purpose:
-  --   Implements the LFSR that generates noise.
-  --   Note: This implementation shifts the register right, i.e. from index
-  --         15 towards 0 => bit 15 is the input, bit 0 is the output
-  --
-  --   Tapped bits according to MAME's sn76496.c, implemented in function
-  --   lfsr_tapped_f.
-  --
-  lfsr: process (clock_i, res_n_i)
-
-    function lfsr_tapped_f(lfsr : in std_logic_vector) return std_logic is
-      constant tapped_bits_c : std_logic_vector(0 to 15)
-        -- tapped bits are 0, 2, 15
-        := "1010000000000001";
-      variable parity_v : std_logic;
-    begin
-      parity_v := '0';
-
-      for idx in lfsr'low to lfsr'high loop
-        parity_v := parity_v xor (lfsr(idx) and tapped_bits_c(idx));
-      end loop;
-
-      return parity_v;
-    end;
-
-  begin
-    if res_n_i = '0' then
-      -- reset LFSR to "0000000000000001"
-      lfsr_q               <= (others => '0');
-      lfsr_q(lfsr_q'right) <= '1';
-
-    elsif clock_i'event and clock_i = '1' then
-      if clk_en_i then
-        if we_i and r2_i = '0' then
-          -- write to noise register
-          -- -> reset LFSR
-          lfsr_q               <= (others => '0');
-          lfsr_q(lfsr_q'right) <= '1';
-
-        elsif shift_rise_edge_s then
-
-          -- shift LFSR left towards MSB
-          for idx in lfsr_q'right-1 downto lfsr_q'left loop
-            lfsr_q(idx) <= lfsr_q(idx+1);
-          end loop;
-
-          -- determine input bit
-          if fb_q = '0' then
-            -- "Periodic" Noise
-            -- -> input to LFSR is output
-            lfsr_q(lfsr_q'right) <= lfsr_q(lfsr_q'left);
-          else
-            -- "White" Noise
-            -- -> input to LFSR is parity of tapped bits
-            lfsr_q(lfsr_q'right) <= lfsr_tapped_f(lfsr_q);
-          end if;
-
-        end if;
-
-      end if;
-    end if;
-  end process lfsr;
-  --
-  -----------------------------------------------------------------------------
-
-
-  -----------------------------------------------------------------------------
-  -- Map output of LFSR to signed value for attenuator.
-  -----------------------------------------------------------------------------
-  freq_s <=   to_signed(+1, 2)
-            when lfsr_q(0) = '1' else
-              to_signed( 0, 2);
-
-
-  -----------------------------------------------------------------------------
-  -- The attenuator itself
-  -----------------------------------------------------------------------------
-  attenuator_b : entity work.sn76489_attenuator
-    port map (
-      attenuation_i => a_q,
-      factor_i      => freq_s,
-      product_o     => noise_o
-    );
-
-end rtl;
diff --git a/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/sn76489_tone.vhd b/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/sn76489_tone.vhd
deleted file mode 100644
index 3658efcc..00000000
--- a/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/sn76489_tone.vhd	
+++ /dev/null
@@ -1,188 +0,0 @@
--------------------------------------------------------------------------------
---
--- Synthesizable model of TI's SN76489AN.
---
--- $Id: sn76489_tone.vhd,v 1.5 2006/02/27 20:30:10 arnim Exp $
---
--- Tone Generator
---
--------------------------------------------------------------------------------
---
--- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity sn76489_tone is
-
-  port (
-    clock_i  : in  std_logic;
-    clk_en_i : in  boolean;
-    res_n_i  : in  std_logic;
-    we_i     : in  boolean;
-    d_i      : in  std_logic_vector(0 to 7);
-    r2_i     : in  std_logic;
-    ff_o     : out std_logic;
-    tone_o   : out signed(0 to 7)
-  );
-
-end sn76489_tone;
-
-architecture rtl of sn76489_tone is
-
-  signal f_q        : std_logic_vector(0 to 9);
-  signal a_q        : std_logic_vector(0 to 3);
-  signal freq_cnt_q : unsigned(0 to 9);
-  signal freq_ff_q  : std_logic;
-
-  signal freq_s     : signed(0 to 1);
-
-  function all_zero(a : in std_logic_vector) return boolean is
-    variable result_v : boolean;
-  begin
-    result_v := true;
-
-    for idx in a'low to a'high loop
-      if a(idx) /= '0' then
-        result_v := false;
-      end if;
-    end loop;
-
-    return result_v;
-  end;
-
-begin
-
-  -----------------------------------------------------------------------------
-  -- Process cpu_regs
-  --
-  -- Purpose:
-  --   Implements the registers writable by the CPU.
-  --
-  cpu_regs: process (clock_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      f_q <= (others => '0');
-      a_q <= (others => '1');
-
-    elsif clock_i'event and clock_i = '1' then
-      if clk_en_i and we_i then
-        if r2_i = '0' then
-          -- access to frequency register
-          if d_i(0) = '0' then
-            f_q(0 to 5) <= d_i(2 to 7);
-          else
-            f_q(6 to 9) <= d_i(4 to 7);
-          end if;
-
-        else
-          -- access to attenuator register
-          -- both access types can write to the attenuator register!
-          a_q <= d_i(4 to 7);
-
-        end if;
-      end if;
-    end if;
-  end process cpu_regs;
-  --
-  -----------------------------------------------------------------------------
-
-
-  -----------------------------------------------------------------------------
-  -- Process freq_gen
-  --
-  -- Purpose:
-  --   Implements the frequency generation components.
-  --
-  freq_gen: process (clock_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      freq_cnt_q <= (others => '0');
-      freq_ff_q  <= '0';
-
-    elsif clock_i'event and clock_i = '1' then
-      if clk_en_i then
-        if freq_cnt_q = 0 then
-          -- update counter from frequency register
-          freq_cnt_q <= unsigned(f_q);
-
-          -- and toggle the frequency flip-flop if enabled
-          if not all_zero(f_q) then
-            freq_ff_q <= not freq_ff_q;
-          else
-            -- if frequency setting is 0, then keep flip-flop at +1
-            freq_ff_q <= '1';
-          end if;
-
-        else
-          -- decrement frequency counter
-          freq_cnt_q <= freq_cnt_q - 1;
-
-        end if;
-      end if;
-    end if;
-  end process freq_gen;
-  --
-  -----------------------------------------------------------------------------
-
-
-  -----------------------------------------------------------------------------
-  -- Map frequency flip-flop to signed value for attenuator.
-  -----------------------------------------------------------------------------
-  freq_s <=   to_signed(+1, 2)
-            when freq_ff_q = '1' else
-              to_signed(-1, 2);
-
-
-  -----------------------------------------------------------------------------
-  -- The attenuator itself
-  -----------------------------------------------------------------------------
-  attenuator_b : entity work.sn76489_attenuator
-    port map (
-      attenuation_i => a_q,
-      factor_i      => freq_s,
-      product_o     => tone_o
-    );
-
-
-  -----------------------------------------------------------------------------
-  -- Output mapping
-  -----------------------------------------------------------------------------
-  ff_o <= freq_ff_q;
-
-end rtl;
diff --git a/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/sn76489_top.vhd b/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/sn76489_top.vhd
deleted file mode 100644
index c26d0e1a..00000000
--- a/Arcade_MiST/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/sn76489_top.vhd	
+++ /dev/null
@@ -1,200 +0,0 @@
--------------------------------------------------------------------------------
---
--- Synthesizable model of TI's SN76489AN.
---
--- $Id: sn76489_top.vhd,v 1.9 2006/02/27 20:30:10 arnim Exp $
---
--- Chip Toplevel
---
--- References:
---
---   * TI Data sheet SN76489.pdf
---     ftp://ftp.whtech.com/datasheets%20&%20manuals/SN76489.pdf
---
---   * John Kortink's article on the SN76489:
---     http://web.inter.nl.net/users/J.Kortink/home/articles/sn76489/
---
---   * Maxim's "SN76489 notes" in
---     http://www.smspower.org/maxim/docs/SN76489.txt
---
--------------------------------------------------------------------------------
---
--- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library ieee;
-use ieee.numeric_std.all;
-
-entity sn76489_top is
-
-  generic (
-    clock_div_16_g : integer := 1
-  );
-  port (
-    clock_i    : in  std_logic;
-    clock_en_i : in  std_logic;
-    res_n_i    : in  std_logic;
-    ce_n_i     : in  std_logic;
-    we_n_i     : in  std_logic;
-    ready_o    : out std_logic;
-    d_i        : in  std_logic_vector(0 to 7);
-    aout_o     : out signed(0 to 7)
-  );
-
-end sn76489_top;
-
-architecture struct of sn76489_top is
-
-  signal clk_en_s    : boolean;
-
-  signal tone1_we_s,
-         tone2_we_s,
-         tone3_we_s,
-         noise_we_s  : boolean;
-  signal r2_s        : std_logic;
-
-  signal tone1_s,
-         tone2_s,
-         tone3_s,
-         noise_s     : signed(0 to 7);
-
-  signal tone3_ff_s  : std_logic;
-
-begin
-
-  -----------------------------------------------------------------------------
-  -- Clock Divider
-  -----------------------------------------------------------------------------
-  clock_div_b : entity work.sn76489_clock_div
-    generic map (
-      clock_div_16_g => clock_div_16_g
-    )
-    port map (
-      clock_i    => clock_i,
-      clock_en_i => clock_en_i,
-      res_n_i    => res_n_i,
-      clk_en_o   => clk_en_s
-    );
-
-
-  -----------------------------------------------------------------------------
-  -- Latch Control = CPU Interface
-  -----------------------------------------------------------------------------
-  latch_ctrl_b : entity work.sn76489_latch_ctrl
-    port map (
-      clock_i    => clock_i,
-      clk_en_i   => clk_en_s,
-      res_n_i    => res_n_i,
-      ce_n_i     => ce_n_i,
-      we_n_i     => we_n_i,
-      d_i        => d_i,
-      ready_o    => ready_o,
-      tone1_we_o => tone1_we_s,
-      tone2_we_o => tone2_we_s,
-      tone3_we_o => tone3_we_s,
-      noise_we_o => noise_we_s,
-      r2_o       => r2_s
-    );
-
-
-  -----------------------------------------------------------------------------
-  -- Tone Channel 1
-  -----------------------------------------------------------------------------
-  tone1_b : entity work.sn76489_tone
-    port map (
-      clock_i  => clock_i,
-      clk_en_i => clk_en_s,
-      res_n_i  => res_n_i,
-      we_i     => tone1_we_s,
-      d_i      => d_i,
-      r2_i     => r2_s,
-      ff_o     => open,
-      tone_o   => tone1_s
-    );
-
-  -----------------------------------------------------------------------------
-  -- Tone Channel 2
-  -----------------------------------------------------------------------------
-  tone2_b : entity work.sn76489_tone
-    port map (
-      clock_i  => clock_i,
-      clk_en_i => clk_en_s,
-      res_n_i  => res_n_i,
-      we_i     => tone2_we_s,
-      d_i      => d_i,
-      r2_i     => r2_s,
-      ff_o     => open,
-      tone_o   => tone2_s
-    );
-
-  -----------------------------------------------------------------------------
-  -- Tone Channel 3
-  -----------------------------------------------------------------------------
-  tone3_b : entity work.sn76489_tone
-    port map (
-      clock_i  => clock_i,
-      clk_en_i => clk_en_s,
-      res_n_i  => res_n_i,
-      we_i     => tone3_we_s,
-      d_i      => d_i,
-      r2_i     => r2_s,
-      ff_o     => tone3_ff_s,
-      tone_o   => tone3_s
-    );
-
-  -----------------------------------------------------------------------------
-  -- Noise Channel
-  -----------------------------------------------------------------------------
-  noise_b : entity work.sn76489_noise
-    port map (
-      clock_i    => clock_i,
-      clk_en_i   => clk_en_s,
-      res_n_i    => res_n_i,
-      we_i       => noise_we_s,
-      d_i        => d_i,
-      r2_i       => r2_s,
-      tone3_ff_i => tone3_ff_s,
-      noise_o    => noise_s
-    );
-
-
-  aout_o <= tone1_s + tone2_s + tone3_s + noise_s;
-
-end struct;
diff --git a/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/Snapjack.qsf b/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/Snapjack.qsf
index 0f5000dc..3458844d 100644
--- a/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/Snapjack.qsf	
+++ b/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/Snapjack.qsf	
@@ -160,7 +160,6 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 
 # end ENTITY(Snapjack)
 # --------------------
-set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/Snapjack.sv
 set_global_assignment -name VHDL_FILE rtl/ladybug.vhd
 set_global_assignment -name VHDL_FILE rtl/ladybug_video_unit.vhd
@@ -180,13 +179,7 @@ set_global_assignment -name VHDL_FILE rtl/ladybug_chutes.vhd
 set_global_assignment -name VHDL_FILE rtl/ladybug_chute.vhd
 set_global_assignment -name VHDL_FILE rtl/ladybug_char.vhd
 set_global_assignment -name VHDL_FILE rtl/ladybug_addr_dec.vhd
-set_global_assignment -name VHDL_FILE rtl/sound/ladybug_sound_unit.vhd
-set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_top.vhd
-set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_tone.vhd
-set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_noise.vhd
-set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_latch_ctrl.vhd
-set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_clock_div.vhd
-set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_attenuator.vhd
+set_global_assignment -name VHDL_FILE rtl/ladybug_sound_unit.vhd
 set_global_assignment -name VHDL_FILE rtl/ROM/rom_sprite_u.vhd
 set_global_assignment -name VHDL_FILE rtl/ROM/rom_sprite_l.vhd
 set_global_assignment -name VHDL_FILE rtl/ROM/rom_cpu3.vhd
@@ -198,15 +191,12 @@ set_global_assignment -name VHDL_FILE rtl/ROM/prom_decrypt.vhd
 set_global_assignment -name VHDL_FILE rtl/ROM/prom_10_3.vhd
 set_global_assignment -name VHDL_FILE rtl/ROM/prom_10_2.vhd
 set_global_assignment -name VHDL_FILE rtl/ROM/prom_10_1.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80a.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
 set_global_assignment -name VHDL_FILE rtl/ttl_393.vhd
 set_global_assignment -name VHDL_FILE rtl/ttl_175.vhd
 set_global_assignment -name VHDL_FILE rtl/spram.vhd
 set_global_assignment -name VHDL_FILE rtl/dpram.vhd
 set_global_assignment -name QIP_FILE rtl/pll.qip
+set_global_assignment -name QIP_FILE ../../../common/Sound/sn76489/sn76489.qip
+set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
+set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/Snapjack.sv b/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/Snapjack.sv
index 219412e4..d22a2ce5 100644
--- a/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/Snapjack.sv	
+++ b/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/Snapjack.sv	
@@ -21,14 +21,14 @@
 
 module Snapjack
 (
-	output        LED,						
+	output        LED,
 	output  [5:0] VGA_R,
 	output  [5:0] VGA_G,
 	output  [5:0] VGA_B,
 	output        VGA_HS,
 	output        VGA_VS,
 	output        AUDIO_L,
-	output        AUDIO_R,	
+	output        AUDIO_R,
 	input         SPI_SCK,
 	output        SPI_DO,
 	input         SPI_DI,
@@ -41,13 +41,16 @@ module Snapjack
 `include "rtl\build_id.v" 
 
 localparam CONF_STR = {
-	"Snapjack;;",
+	"SNAPJACK;;",
+	"O2,Rotate Controls,Off,On;",
 	"O34,Scanlines,Off,25%,50%,75%;",
 	"O5,Blend,Off,On;",
-	"T6,Reset;",
+	"T0,Reset;",
 	"V,v1.10.",`BUILD_DATE
 };
 
+wire rotate = status[2];
+
 assign LED = 1;
 assign AUDIO_R = AUDIO_L;
 
@@ -67,17 +70,43 @@ wire  [7:0] joystick_0;
 wire  [7:0] joystick_1;
 wire        scandoublerD;
 wire        ypbpr;
-wire [10:0] ps2_key;
-reg	[7:0] audio;
-wire 			hb, vb;
-wire        blankn = ~(hb | vb);
-wire 			ce_vid;
-wire 			hs, vs;
-wire  [1:0] r, g, b;
+wire        no_csync;
+wire        key_pressed;
+wire  [7:0] key_code;
+wire        key_strobe;
 
-ladybugt snapjack(
+user_io #(
+	.STRLEN(($size(CONF_STR)>>3)))
+user_io(
+	.clk_sys        (clk_sys        ),
+	.conf_str       (CONF_STR       ),
+	.SPI_CLK        (SPI_SCK        ),
+	.SPI_SS_IO      (CONF_DATA0     ),
+	.SPI_MISO       (SPI_DO         ),
+	.SPI_MOSI       (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches       (switches       ),
+	.scandoubler_disable (scandoublerD),
+	.ypbpr          (ypbpr          ),
+	.no_csync       (no_csync       ),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
+	.key_code       (key_code       ),
+	.joystick_0     (joystick_0     ),
+	.joystick_1     (joystick_1     ),
+	.status         (status         )
+);
+
+wire  [8:0] audio;
+wire        hb, vb;
+wire        blankn = ~(hb | vb);
+wire        ce_vid;
+wire        hs, vs;
+wire  [1:0] r,g,b;
+
+ladybugt ladybug(
 	.CLK_IN(clk_sys),
-	.I_RESET(status[0] | status[6] | buttons[1]),
+	.I_RESET(status[0] | buttons[1]),
 	.O_PIXCE(ce_vid),
 	.O_VIDEO_R(r),
 	.O_VIDEO_G(g),
@@ -87,15 +116,15 @@ ladybugt snapjack(
 	.O_VBLANK(vb),
 	.O_HBLANK(hb),
 	.O_AUDIO(audio),
-	.but_coin_s(~{1'b0,btn_coin}),
-	.but_fire_s(~{m_fire,m_fire}),
-	.but_bomb_s(~{m_bomb,m_bomb}),
-	.but_tilt_s(~{1'b0,1'b0}),
-	.but_select_s(~{btn_two_players, btn_one_player}),
-	.but_up_s(~{m_up,m_up}),
-	.but_down_s(~{m_down,m_down}),
-	.but_left_s(~{m_left,m_left}),
-	.but_right_s(~{m_right,m_right})
+	.but_coin_s(~{m_coin2,m_coin1}),
+	.but_fire_s(~{m_fire2A,m_fireA}),
+	.but_bomb_s(~{m_fire2B,m_fireB}),
+	.but_tilt_s(~{m_tilt,m_tilt}),
+	.but_select_s(~{m_two_players, m_one_player}),
+	.but_up_s(~{m_up2,m_up}),
+	.but_down_s(~{m_down2,m_down}),
+	.but_left_s(~{m_left2,m_left}),
+	.but_right_s(~{m_right2,m_right})
 	);
 
 mist_video #(.COLOR_DEPTH(2),.SD_HCNT_WIDTH(10)) mist_video(
@@ -113,79 +142,40 @@ mist_video #(.COLOR_DEPTH(2),.SD_HCNT_WIDTH(10)) mist_video(
 	.VGA_B(VGA_B),
 	.VGA_VS(VGA_VS),
 	.VGA_HS(VGA_HS),
-	.rotate({1'b0,status[2]}),
+	.rotate({1'b0,rotate}),
 	.ce_divider(1'b1),
 	.blend(status[5]),
 	.scandoubler_disable(scandoublerD),
 	.scanlines(status[4:3]),
-	.ypbpr(ypbpr)
+	.ypbpr(ypbpr),
+	.no_csync(no_csync)
 );
 
-user_io #(
-	.STRLEN(($size(CONF_STR)>>3)))
-user_io(
-	.clk_sys        (clk_sys        ),
-	.conf_str       (CONF_STR       ),
-	.SPI_CLK        (SPI_SCK        ),
-	.SPI_SS_IO      (CONF_DATA0     ),
-	.SPI_MISO       (SPI_DO         ),
-	.SPI_MOSI       (SPI_DI         ),
-	.buttons        (buttons        ),
-	.switches       (switches       ),
-	.scandoubler_disable (scandoublerD),
-	.ypbpr          (ypbpr          ),
-	.key_strobe     (key_strobe     ),
-	.key_pressed    (key_pressed    ),
-	.key_code       (key_code       ),
-	.joystick_0     (joystick_0     ),
-	.joystick_1     (joystick_1     ),
-	.status         (status         )
-);
-
-dac dac(
+dac #(9) dac(
 	.clk_i(clk_sys),
 	.res_n_i(1),
-	.dac_i({~audio[7], audio[6:0]}),
+	.dac_i(audio),
 	.dac_o(AUDIO_L)
 	);
 
-wire m_up     = btn_up | joystick_0[3] | joystick_1[3];
-wire m_down   = btn_down | joystick_0[2] | joystick_1[2];
-wire m_left   = btn_left | joystick_0[1] | joystick_1[1];
-wire m_right  = btn_right | joystick_0[0] | joystick_1[0];
+wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
+wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
+wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
 
-wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
-wire m_bomb   = btn_fire2 | joystick_0[5] | joystick_1[5];
-
-reg btn_one_player = 0;
-reg btn_two_players = 0;
-reg btn_left = 0;
-reg btn_right = 0;
-reg btn_down = 0;
-reg btn_up = 0;
-reg btn_fire1 = 0;
-reg btn_fire2 = 0;
-reg btn_fire3 = 0;
-reg btn_coin  = 0;
-wire       key_pressed;
-wire [7:0] key_code;
-wire       key_strobe;
-
-always @(posedge clk_sys) begin
-	if(key_strobe) begin
-		case(key_code)
-			'h75: btn_up         	<= key_pressed; // up
-			'h72: btn_down        	<= key_pressed; // down
-			'h6B: btn_left      		<= key_pressed; // left
-			'h74: btn_right       	<= key_pressed; // right
-			'h76: btn_coin				<= key_pressed; // ESC
-			'h05: btn_one_player   	<= key_pressed; // F1
-			'h06: btn_two_players  	<= key_pressed; // F2
-			'h14: btn_fire3 			<= key_pressed; // ctrl
-			'h11: btn_fire2 			<= key_pressed; // alt
-			'h29: btn_fire1   		<= key_pressed; // Space
-		endcase
-	end
-end
+arcade_inputs inputs (
+	.clk         ( clk_sys     ),
+	.key_strobe  ( key_strobe  ),
+	.key_pressed ( key_pressed ),
+	.key_code    ( key_code    ),
+	.joystick_0  ( joystick_0  ),
+	.joystick_1  ( joystick_1  ),
+	.rotate      ( rotate      ),
+	.orientation ( 2'b00       ),
+	.joyswap     ( 1'b0        ),
+	.oneplayer   ( 1'b1        ),
+	.controls    ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
+	.player1     ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
+	.player2     ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
+);
 
 endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/cpu/T80.vhd
deleted file mode 100644
index c3e13c5c..00000000
--- a/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/cpu/T80.vhd	
+++ /dev/null
@@ -1,1094 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
---
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0210 : Fixed wait and halt
---
---      0211 : Fixed Refresh addition and IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
---      0235 : Added clock enable and IM 2 fix by Mike Johnson
---
---      0237 : Changed 8080 I/O address output, added IntE output
---
---      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
---      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
---      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
---      0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
-  generic(
-    Mode   : integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-    IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-    Flag_C : integer := 0;
-    Flag_N : integer := 1;
-    Flag_P : integer := 2;
-    Flag_X : integer := 3;
-    Flag_H : integer := 4;
-    Flag_Y : integer := 5;
-    Flag_Z : integer := 6;
-    Flag_S : integer := 7
-    );
-  port(
-    RESET_n    : in  std_logic;
-    CLK_n      : in  std_logic;
-    CEN        : in  std_logic;
-    WAIT_n     : in  std_logic;
-    INT_n      : in  std_logic;
-    NMI_n      : in  std_logic;
-    BUSRQ_n    : in  std_logic;
-    M1_n       : out std_logic;
-    IORQ       : out std_logic;
-    NoRead     : out std_logic;
-    Write      : out std_logic;
-    RFSH_n     : out std_logic;
-    HALT_n     : out std_logic;
-    BUSAK_n    : out std_logic;
-    A          : out std_logic_vector(15 downto 0);
-    DInst      : in  std_logic_vector(7 downto 0);
-    DI         : in  std_logic_vector(7 downto 0);
-    DO         : out std_logic_vector(7 downto 0);
-    MC         : out std_logic_vector(2 downto 0);
-    TS         : out std_logic_vector(2 downto 0);
-    IntCycle_n : out std_logic;
-    IntE       : out std_logic;
-    Stop       : out std_logic
-    );
-end T80;
-
-architecture rtl of T80 is
-
-  constant aNone              : std_logic_vector(2 downto 0) := "111";
-  constant aBC                : std_logic_vector(2 downto 0) := "000";
-  constant aDE                : std_logic_vector(2 downto 0) := "001";
-  constant aXY                : std_logic_vector(2 downto 0) := "010";
-  constant aIOA               : std_logic_vector(2 downto 0) := "100";
-  constant aSP                : std_logic_vector(2 downto 0) := "101";
-  constant aZI                : std_logic_vector(2 downto 0) := "110";
-
-  -- Registers
-  signal ACC, F               : std_logic_vector(7 downto 0);
-  signal Ap, Fp               : std_logic_vector(7 downto 0);
-  signal I                    : std_logic_vector(7 downto 0);
-  signal R                    : unsigned(7 downto 0);
-  signal SP, PC               : unsigned(15 downto 0);
-
-  signal RegDIH               : std_logic_vector(7 downto 0);
-  signal RegDIL               : std_logic_vector(7 downto 0);
-  signal RegBusA              : std_logic_vector(15 downto 0);
-  signal RegBusB              : std_logic_vector(15 downto 0);
-  signal RegBusC              : std_logic_vector(15 downto 0);
-  signal RegAddrA_r           : std_logic_vector(2 downto 0);
-  signal RegAddrA             : std_logic_vector(2 downto 0);
-  signal RegAddrB_r           : std_logic_vector(2 downto 0);
-  signal RegAddrB             : std_logic_vector(2 downto 0);
-  signal RegAddrC             : std_logic_vector(2 downto 0);
-  signal RegWEH               : std_logic;
-  signal RegWEL               : std_logic;
-  signal Alternate            : std_logic;
-
-  -- Help Registers
-  signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
-  signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
-  signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
-  signal RegBusA_r            : std_logic_vector(15 downto 0);
-
-  signal ID16                 : signed(15 downto 0);
-  signal Save_Mux             : std_logic_vector(7 downto 0);
-
-  signal TState               : unsigned(2 downto 0);
-  signal MCycle               : std_logic_vector(2 downto 0);
-  signal IntE_FF1             : std_logic;
-  signal IntE_FF2             : std_logic;
-  signal Halt_FF              : std_logic;
-  signal BusReq_s             : std_logic;
-  signal BusAck               : std_logic;
-  signal ClkEn                : std_logic;
-  signal NMI_s                : std_logic;
-  signal INT_s                : std_logic;
-  signal IStatus              : std_logic_vector(1 downto 0);
-
-  signal DI_Reg               : std_logic_vector(7 downto 0);
-  signal T_Res                : std_logic;
-  signal XY_State             : std_logic_vector(1 downto 0);
-  signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
-  signal NextIs_XY_Fetch      : std_logic;
-  signal XY_Ind               : std_logic;
-  signal No_BTR               : std_logic;
-  signal BTR_r                : std_logic;
-  signal Auto_Wait            : std_logic;
-  signal Auto_Wait_t1         : std_logic;
-  signal Auto_Wait_t2         : std_logic;
-  signal IncDecZ              : std_logic;
-
-  -- ALU signals
-  signal BusB                 : std_logic_vector(7 downto 0);
-  signal BusA                 : std_logic_vector(7 downto 0);
-  signal ALU_Q                : std_logic_vector(7 downto 0);
-  signal F_Out                : std_logic_vector(7 downto 0);
-
-  -- Registered micro code outputs
-  signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
-  signal Arith16_r            : std_logic;
-  signal Z16_r                : std_logic;
-  signal ALU_Op_r             : std_logic_vector(3 downto 0);
-  signal Save_ALU_r           : std_logic;
-  signal PreserveC_r          : std_logic;
-  signal MCycles              : std_logic_vector(2 downto 0);
-
-  -- Micro code outputs
-  signal MCycles_d            : std_logic_vector(2 downto 0);
-  signal TStates              : std_logic_vector(2 downto 0);
-  signal IntCycle             : std_logic;
-  signal NMICycle             : std_logic;
-  signal Inc_PC               : std_logic;
-  signal Inc_WZ               : std_logic;
-  signal IncDec_16            : std_logic_vector(3 downto 0);
-  signal Prefix               : std_logic_vector(1 downto 0);
-  signal Read_To_Acc          : std_logic;
-  signal Read_To_Reg          : std_logic;
-  signal Set_BusB_To          : std_logic_vector(3 downto 0);
-  signal Set_BusA_To          : std_logic_vector(3 downto 0);
-  signal ALU_Op               : std_logic_vector(3 downto 0);
-  signal Save_ALU             : std_logic;
-  signal PreserveC            : std_logic;
-  signal Arith16              : std_logic;
-  signal Set_Addr_To          : std_logic_vector(2 downto 0);
-  signal Jump                 : std_logic;
-  signal JumpE                : std_logic;
-  signal JumpXY               : std_logic;
-  signal Call                 : std_logic;
-  signal RstP                 : std_logic;
-  signal LDZ                  : std_logic;
-  signal LDW                  : std_logic;
-  signal LDSPHL               : std_logic;
-  signal IORQ_i               : std_logic;
-  signal Special_LD           : std_logic_vector(2 downto 0);
-  signal ExchangeDH           : std_logic;
-  signal ExchangeRp           : std_logic;
-  signal ExchangeAF           : std_logic;
-  signal ExchangeRS           : std_logic;
-  signal I_DJNZ               : std_logic;
-  signal I_CPL                : std_logic;
-  signal I_CCF                : std_logic;
-  signal I_SCF                : std_logic;
-  signal I_RETN               : std_logic;
-  signal I_BT                 : std_logic;
-  signal I_BC                 : std_logic;
-  signal I_BTR                : std_logic;
-  signal I_RLD                : std_logic;
-  signal I_RRD                : std_logic;
-  signal I_INRC               : std_logic;
-  signal SetDI                : std_logic;
-	signal SetEI                : std_logic;
-	signal IMode                : std_logic_vector(1 downto 0);
-	signal Halt                 : std_logic;
-	signal XYbit_undoc          : std_logic;
-
-
-begin
-
-  mcode : T80_MCode
-    generic map(
-      Mode   => Mode,
-      Flag_C => Flag_C,
-      Flag_N => Flag_N,
-      Flag_P => Flag_P,
-      Flag_X => Flag_X,
-      Flag_H => Flag_H,
-      Flag_Y => Flag_Y,
-      Flag_Z => Flag_Z,
-      Flag_S => Flag_S)
-    port map(
-      IR          => IR,
-      ISet        => ISet,
-      MCycle      => MCycle,
-      F           => F,
-      NMICycle    => NMICycle,
-      IntCycle    => IntCycle,
-      XY_State    => XY_State,
-      MCycles     => MCycles_d,
-      TStates     => TStates,
-      Prefix      => Prefix,
-      Inc_PC      => Inc_PC,
-      Inc_WZ      => Inc_WZ,
-      IncDec_16   => IncDec_16,
-      Read_To_Acc => Read_To_Acc,
-      Read_To_Reg => Read_To_Reg,
-      Set_BusB_To => Set_BusB_To,
-      Set_BusA_To => Set_BusA_To,
-      ALU_Op      => ALU_Op,
-      Save_ALU    => Save_ALU,
-      PreserveC   => PreserveC,
-      Arith16     => Arith16,
-      Set_Addr_To => Set_Addr_To,
-      IORQ        => IORQ_i,
-      Jump        => Jump,
-      JumpE       => JumpE,
-      JumpXY      => JumpXY,
-      Call        => Call,
-      RstP        => RstP,
-      LDZ         => LDZ,
-      LDW         => LDW,
-      LDSPHL      => LDSPHL,
-      Special_LD  => Special_LD,
-      ExchangeDH  => ExchangeDH,
-      ExchangeRp  => ExchangeRp,
-      ExchangeAF  => ExchangeAF,
-      ExchangeRS  => ExchangeRS,
-      I_DJNZ      => I_DJNZ,
-      I_CPL       => I_CPL,
-      I_CCF       => I_CCF,
-      I_SCF       => I_SCF,
-      I_RETN      => I_RETN,
-      I_BT        => I_BT,
-      I_BC        => I_BC,
-      I_BTR       => I_BTR,
-      I_RLD       => I_RLD,
-      I_RRD       => I_RRD,
-      I_INRC      => I_INRC,
-      SetDI       => SetDI,
-      SetEI       => SetEI,
-      IMode       => IMode,
-      Halt        => Halt,
-      NoRead      => NoRead,
-      Write       => Write,
-      XYbit_undoc => XYbit_undoc);
-
-  alu : T80_ALU
-    generic map(
-      Mode   => Mode,
-      Flag_C => Flag_C,
-      Flag_N => Flag_N,
-      Flag_P => Flag_P,
-      Flag_X => Flag_X,
-      Flag_H => Flag_H,
-      Flag_Y => Flag_Y,
-      Flag_Z => Flag_Z,
-      Flag_S => Flag_S)
-    port map(
-      Arith16 => Arith16_r,
-      Z16     => Z16_r,
-      ALU_Op  => ALU_Op_r,
-      IR      => IR(5 downto 0),
-      ISet    => ISet,
-      BusA    => BusA,
-      BusB    => BusB,
-      F_In    => F,
-      Q       => ALU_Q,
-      F_Out   => F_Out);
-
-  ClkEn <= CEN and not BusAck;
-
-  T_Res <= '1' when TState = unsigned(TStates) else '0';
-
-  NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
-                              ((Set_Addr_To = aXY) or
-                               (MCycle = "001" and IR = "11001011") or
-                               (MCycle = "001" and IR = "00110110")) else '0';
-
-  Save_Mux <= BusB when ExchangeRp = '1' else
-              DI_Reg when Save_ALU_r = '0' else
-              ALU_Q;
-
-  process (RESET_n, CLK_n)
-  begin
-    if RESET_n = '0' then
-      PC <= (others => '0');  -- Program Counter
-      A <= (others => '0');
-      TmpAddr <= (others => '0');
-      IR <= "00000000";
-      ISet <= "00";
-      XY_State <= "00";
-      IStatus <= "00";
-      MCycles <= "000";
-      DO <= "00000000";
-
-      ACC <= (others => '1');
-      F <= (others => '1');
-      Ap <= (others => '1');
-      Fp <= (others => '1');
-      I <= (others => '0');
-      R <= (others => '0');
-      SP <= (others => '1');
-      Alternate <= '0';
-
-      Read_To_Reg_r <= "00000";
-      F <= (others => '1');
-      Arith16_r <= '0';
-      BTR_r <= '0';
-      Z16_r <= '0';
-      ALU_Op_r <= "0000";
-      Save_ALU_r <= '0';
-      PreserveC_r <= '0';
-      XY_Ind <= '0';
-
-    elsif CLK_n'event and CLK_n = '1' then
-
-      if ClkEn = '1' then
-
-        ALU_Op_r <= "0000";
-        Save_ALU_r <= '0';
-        Read_To_Reg_r <= "00000";
-
-        MCycles <= MCycles_d;
-
-        if IMode /= "11" then
-          IStatus <= IMode;
-        end if;
-
-        Arith16_r <= Arith16;
-        PreserveC_r <= PreserveC;
-        if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
-          Z16_r <= '1';
-        else
-          Z16_r <= '0';
-        end if;
-
-        if MCycle  = "001" and TState(2) = '0' then
-          -- MCycle = 1 and TState = 1, 2, or 3
-
-          if TState = 2 and Wait_n = '1' then
-            if Mode < 2 then
-              A(7 downto 0) <= std_logic_vector(R);
-              A(15 downto 8) <= I;
-              R(6 downto 0) <= R(6 downto 0) + 1;
-            end if;
-
-            if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
-              PC <= PC + 1;
-            end if;
-
-            if IntCycle = '1' and IStatus = "01" then
-              IR <= "11111111";
-            elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
-              IR <= "00000000";
-            else
-              IR <= DInst;
-            end if;
-
-            ISet <= "00";
-            if Prefix /= "00" then
-              if Prefix = "11" then
-                if IR(5) = '1' then
-                  XY_State <= "10";
-                else
-                  XY_State <= "01";
-                end if;
-              else
-                if Prefix = "10" then
-                  XY_State <= "00";
-                  XY_Ind <= '0';
-                end if;
-                ISet <= Prefix;
-              end if;
-            else
-              XY_State <= "00";
-              XY_Ind <= '0';
-            end if;
-          end if;
-
-        else
-          -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
-          if MCycle = "110" then
-            XY_Ind <= '1';
-            if Prefix = "01" then
-              ISet <= "01";
-            end if;
-          end if;
-
-          if T_Res = '1' then
-            BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
-            if Jump = '1' then
-              A(15 downto 8) <= DI_Reg;
-              A(7 downto 0) <= TmpAddr(7 downto 0);
-              PC(15 downto 8) <= unsigned(DI_Reg);
-              PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-            elsif JumpXY = '1' then
-              A <= RegBusC;
-              PC <= unsigned(RegBusC);
-            elsif Call = '1' or RstP = '1' then
-              A <= TmpAddr;
-              PC <= unsigned(TmpAddr);
-            elsif MCycle = MCycles and NMICycle = '1' then
-              A <= "0000000001100110";
-              PC <= "0000000001100110";
-            elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
-              A(15 downto 8) <= I;
-              A(7 downto 0) <= TmpAddr(7 downto 0);
-              PC(15 downto 8) <= unsigned(I);
-              PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-            else
-              case Set_Addr_To is
-                when aXY =>
-                  if XY_State = "00" then
-                    A <= RegBusC;
-                  else
-                    if NextIs_XY_Fetch = '1' then
-                      A <= std_logic_vector(PC);
-                    else
-                      A <= TmpAddr;
-                    end if;
-                  end if;
-                when aIOA =>
-                  if Mode = 3 then
-                    -- Memory map I/O on GBZ80
-                    A(15 downto 8) <= (others => '1');
-                  elsif Mode = 2 then
-                    -- Duplicate I/O address on 8080
-                    A(15 downto 8) <= DI_Reg;
-                  else
-                    A(15 downto 8) <= ACC;
-                  end if;
-                  A(7 downto 0) <= DI_Reg;
-                when aSP =>
-                  A <= std_logic_vector(SP);
-                when aBC =>
-                  if Mode = 3 and IORQ_i = '1' then
-                    -- Memory map I/O on GBZ80
-                    A(15 downto 8) <= (others => '1');
-                    A(7 downto 0) <= RegBusC(7 downto 0);
-                  else
-                    A <= RegBusC;
-                  end if;
-                when aDE =>
-                  A <= RegBusC;
-                when aZI =>
-                  if Inc_WZ = '1' then
-                    A <= std_logic_vector(unsigned(TmpAddr) + 1);
-                  else
-                    A(15 downto 8) <= DI_Reg;
-                    A(7 downto 0) <= TmpAddr(7 downto 0);
-                  end if;
-                when others =>
-                  A <= std_logic_vector(PC);
-              end case;
-            end if;
-
-            Save_ALU_r <= Save_ALU;
-            ALU_Op_r <= ALU_Op;
-
-            if I_CPL = '1' then
-              -- CPL
-              ACC <= not ACC;
-              F(Flag_Y) <= not ACC(5);
-              F(Flag_H) <= '1';
-              F(Flag_X) <= not ACC(3);
-              F(Flag_N) <= '1';
-            end if;
-            if I_CCF = '1' then
-              -- CCF
-              F(Flag_C) <= not F(Flag_C);
-              F(Flag_Y) <= ACC(5);
-              F(Flag_H) <= F(Flag_C);
-              F(Flag_X) <= ACC(3);
-              F(Flag_N) <= '0';
-            end if;
-            if I_SCF = '1' then
-              -- SCF
-              F(Flag_C) <= '1';
-              F(Flag_Y) <= ACC(5);
-              F(Flag_H) <= '0';
-              F(Flag_X) <= ACC(3);
-              F(Flag_N) <= '0';
-            end if;
-          end if;
-
-          if TState = 2 and Wait_n = '1' then
-            if ISet = "01" and MCycle = "111" then
-              IR <= DInst;
-            end if;
-            if JumpE = '1' then
-              PC <= unsigned(signed(PC) + signed(DI_Reg));
-            elsif Inc_PC = '1' then
-              PC <= PC + 1;
-            end if;
-            if BTR_r = '1' then
-              PC <= PC - 2;
-            end if;
-            if RstP = '1' then
-              TmpAddr <= (others =>'0');
-              TmpAddr(5 downto 3) <= IR(5 downto 3);
-            end if;
-          end if;
-          if TState = 3 and MCycle = "110" then
-            TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
-          end if;
-
-          if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
-            if IncDec_16(2 downto 0) = "111" then
-              if IncDec_16(3) = '1' then
-                SP <= SP - 1;
-              else
-                SP <= SP + 1;
-              end if;
-            end if;
-          end if;
-
-          if LDSPHL = '1' then
-            SP <= unsigned(RegBusC);
-          end if;
-          if ExchangeAF = '1' then
-            Ap <= ACC;
-            ACC <= Ap;
-            Fp <= F;
-            F <= Fp;
-          end if;
-          if ExchangeRS = '1' then
-            Alternate <= not Alternate;
-          end if;
-        end if;
-
-        if TState = 3 then
-          if LDZ = '1' then
-            TmpAddr(7 downto 0) <= DI_Reg;
-          end if;
-          if LDW = '1' then
-            TmpAddr(15 downto 8) <= DI_Reg;
-          end if;
-
-          if Special_LD(2) = '1' then
-            case Special_LD(1 downto 0) is
-              when "00" =>
-                ACC <= I;
-                F(Flag_P) <= IntE_FF2;
-              when "01" =>
-                ACC <= std_logic_vector(R);
-                F(Flag_P) <= IntE_FF2;
-              when "10" =>
-                I <= ACC;
-              when others =>
-                R <= unsigned(ACC);
-            end case;
-          end if;
-        end if;
-
-        if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
-          if Mode = 3 then
-            F(6) <= F_Out(6);
-            F(5) <= F_Out(5);
-            F(7) <= F_Out(7);
-            if PreserveC_r = '0' then
-              F(4) <= F_Out(4);
-            end if;
-          else
-            F(7 downto 1) <= F_Out(7 downto 1);
-            if PreserveC_r = '0' then
-              F(Flag_C) <= F_Out(0);
-            end if;
-          end if;
-        end if;
-        if T_Res = '1' and I_INRC = '1' then
-          F(Flag_H) <= '0';
-          F(Flag_N) <= '0';
-          if DI_Reg(7 downto 0) = "00000000" then
-            F(Flag_Z) <= '1';
-          else
-            F(Flag_Z) <= '0';
-          end if;
-          F(Flag_S) <= DI_Reg(7);
-          F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
-                            DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
-        end if;
-
-        if TState = 1 then
-          DO <= BusB;
-          if I_RLD = '1' then
-            DO(3 downto 0) <= BusA(3 downto 0);
-            DO(7 downto 4) <= BusB(3 downto 0);
-          end if;
-          if I_RRD = '1' then
-            DO(3 downto 0) <= BusB(7 downto 4);
-            DO(7 downto 4) <= BusA(3 downto 0);
-          end if;
-        end if;
-
-        if T_Res = '1' then
-          Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
-          Read_To_Reg_r(4) <= Read_To_Reg;
-          if Read_To_Acc = '1' then
-            Read_To_Reg_r(3 downto 0) <= "0111";
-            Read_To_Reg_r(4) <= '1';
-          end if;
-        end if;
-
-        if TState = 1 and I_BT = '1' then
-          F(Flag_X) <= ALU_Q(3);
-          F(Flag_Y) <= ALU_Q(1);
-          F(Flag_H) <= '0';
-          F(Flag_N) <= '0';
-        end if;
-        if I_BC = '1' or I_BT = '1' then
-          F(Flag_P) <= IncDecZ;
-        end if;
-
-        if (TState = 1 and Save_ALU_r = '0') or
-          (Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-          case Read_To_Reg_r is
-            when "10111" =>
-              ACC <= Save_Mux;
-            when "10110" =>
-              DO <= Save_Mux;
-            when "11000" =>
-              SP(7 downto 0) <= unsigned(Save_Mux);
-            when "11001" =>
-              SP(15 downto 8) <= unsigned(Save_Mux);
-            when "11011" =>
-              F <= Save_Mux;
-            when others =>
-          end case;
-          if XYbit_undoc='1' then
-            DO <= ALU_Q;
-          end if;
-        end if;
-
-      end if;
-
-    end if;
-
-  end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
-  process (CLK_n)
-  begin
-    if CLK_n'event and CLK_n = '1' then
-      if ClkEn = '1' then
-        -- Bus A / Write
-        RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
-        if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
-          RegAddrA_r <= XY_State(1) & "11";
-        end if;
-
-        -- Bus B
-        RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
-        if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
-          RegAddrB_r <= XY_State(1) & "11";
-        end if;
-
-        -- Address from register
-        RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-        -- Jump (HL), LD SP,HL
-        if (JumpXY = '1' or LDSPHL = '1') then
-          RegAddrC <= Alternate & "10";
-        end if;
-        if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
-          RegAddrC <= XY_State(1) & "11";
-        end if;
-
-        if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
-          IncDecZ <= F_Out(Flag_Z);
-        end if;
-        if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
-          if ID16 = 0 then
-            IncDecZ <= '0';
-          else
-            IncDecZ <= '1';
-          end if;
-        end if;
-
-        RegBusA_r <= RegBusA;
-      end if;
-    end if;
-  end process;
-
-  RegAddrA <=
-    -- 16 bit increment/decrement
-    Alternate & IncDec_16(1 downto 0) when (TState = 2 or
-                                            (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
-    XY_State(1) & "11" when (TState = 2 or
-                             (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-    -- EX HL,DL
-    Alternate & "10" when ExchangeDH = '1' and TState = 3 else
-    Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-    -- Bus A / Write
-    RegAddrA_r;
-
-  RegAddrB <=
-    -- EX HL,DL
-    Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-    -- Bus B
-    RegAddrB_r;
-
-  ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
-          signed(RegBusA) + 1;
-
-  process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
-           ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-  begin
-    RegWEH <= '0';
-    RegWEL <= '0';
-    if (TState = 1 and Save_ALU_r = '0') or
-      (Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-      case Read_To_Reg_r is
-        when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
-          RegWEH <= not Read_To_Reg_r(0);
-          RegWEL <= Read_To_Reg_r(0);
-        when others =>
-      end case;
-    end if;
-
-    if ExchangeDH = '1' and (TState = 3 or TState = 4) then
-      RegWEH <= '1';
-      RegWEL <= '1';
-    end if;
-
-    if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-      case IncDec_16(1 downto 0) is
-        when "00" | "01" | "10" =>
-          RegWEH <= '1';
-          RegWEL <= '1';
-        when others =>
-      end case;
-    end if;
-  end process;
-
-  process (Save_Mux, RegBusB, RegBusA_r, ID16,
-           ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-  begin
-    RegDIH <= Save_Mux;
-    RegDIL <= Save_Mux;
-
-    if ExchangeDH = '1' and TState = 3 then
-      RegDIH <= RegBusB(15 downto 8);
-      RegDIL <= RegBusB(7 downto 0);
-    end if;
-    if ExchangeDH = '1' and TState = 4 then
-      RegDIH <= RegBusA_r(15 downto 8);
-      RegDIL <= RegBusA_r(7 downto 0);
-    end if;
-
-    if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-      RegDIH <= std_logic_vector(ID16(15 downto 8));
-      RegDIL <= std_logic_vector(ID16(7 downto 0));
-    end if;
-  end process;
-
-  Regs : T80_Reg
-    port map(
-      Clk   => CLK_n,
-      CEN   => ClkEn,
-      WEH   => RegWEH,
-      WEL   => RegWEL,
-      AddrA => RegAddrA,
-      AddrB => RegAddrB,
-      AddrC => RegAddrC,
-      DIH   => RegDIH,
-      DIL   => RegDIL,
-      DOAH  => RegBusA(15 downto 8),
-      DOAL  => RegBusA(7 downto 0),
-      DOBH  => RegBusB(15 downto 8),
-      DOBL  => RegBusB(7 downto 0),
-      DOCH  => RegBusC(15 downto 8),
-      DOCL  => RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
-  process (CLK_n)
-  begin
-    if CLK_n'event and CLK_n = '1' then
-      if ClkEn = '1' then
-        case Set_BusB_To is
-          when "0111" =>
-            BusB <= ACC;
-          when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-            if Set_BusB_To(0) = '1' then
-              BusB <= RegBusB(7 downto 0);
-            else
-              BusB <= RegBusB(15 downto 8);
-            end if;
-          when "0110" =>
-            BusB <= DI_Reg;
-          when "1000" =>
-            BusB <= std_logic_vector(SP(7 downto 0));
-          when "1001" =>
-            BusB <= std_logic_vector(SP(15 downto 8));
-          when "1010" =>
-            BusB <= "00000001";
-          when "1011" =>
-            BusB <= F;
-          when "1100" =>
-            BusB <= std_logic_vector(PC(7 downto 0));
-          when "1101" =>
-            BusB <= std_logic_vector(PC(15 downto 8));
-          when "1110" =>
-            BusB <= "00000000";
-          when others =>
-            BusB <= "--------";
-        end case;
-
-        case Set_BusA_To is
-          when "0111" =>
-            BusA <= ACC;
-          when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-            if Set_BusA_To(0) = '1' then
-              BusA <= RegBusA(7 downto 0);
-            else
-              BusA <= RegBusA(15 downto 8);
-            end if;
-          when "0110" =>
-            BusA <= DI_Reg;
-          when "1000" =>
-            BusA <= std_logic_vector(SP(7 downto 0));
-          when "1001" =>
-            BusA <= std_logic_vector(SP(15 downto 8));
-          when "1010" =>
-            BusA <= "00000000";
-          when others =>
-            BusB <= "--------";
-        end case;
-        if XYbit_undoc='1' then
-          BusA <= DI_Reg;
-          BusB <= DI_Reg;
-        end if;
-      end if;
-    end if;
-  end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
-  process (RESET_n,CLK_n)
-  begin
-    if RESET_n = '0' then
-      RFSH_n <= '1';
-    elsif CLK_n'event and CLK_n = '1' then
-      if CEN = '1' then
-        if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
-          RFSH_n <= '0';
-        else
-          RFSH_n <= '1';
-        end if;
-      end if;
-    end if;
-  end process;
-
-  MC <= std_logic_vector(MCycle);
-  TS <= std_logic_vector(TState);
-  DI_Reg <= DI;
-  HALT_n <= not Halt_FF;
-  BUSAK_n <= not BusAck;
-  IntCycle_n <= not IntCycle;
-  IntE <= IntE_FF1;
-  IORQ <= IORQ_i;
-  Stop <= I_DJNZ;
-
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
-  process (RESET_n, CLK_n)
-    variable OldNMI_n : std_logic;
-  begin
-    if RESET_n = '0' then
-      BusReq_s <= '0';
-      INT_s <= '0';
-      NMI_s <= '0';
-      OldNMI_n := '0';
-    elsif CLK_n'event and CLK_n = '1' then
-      if CEN = '1' then
-        BusReq_s <= not BUSRQ_n;
-        INT_s <= not INT_n;
-        if NMICycle = '1' then
-          NMI_s <= '0';
-        elsif NMI_n = '0' and OldNMI_n = '1' then
-          NMI_s <= '1';
-        end if;
-        OldNMI_n := NMI_n;
-      end if;
-    end if;
-  end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
-  process (RESET_n, CLK_n)
-  begin
-    if RESET_n = '0' then
-      MCycle <= "001";
-      TState <= "000";
-      Pre_XY_F_M <= "000";
-      Halt_FF <= '0';
-      BusAck <= '0';
-      NMICycle <= '0';
-      IntCycle <= '0';
-      IntE_FF1 <= '0';
-      IntE_FF2 <= '0';
-      No_BTR <= '0';
-      Auto_Wait_t1 <= '0';
-      Auto_Wait_t2 <= '0';
-      M1_n <= '1';
-    elsif CLK_n'event and CLK_n = '1' then
-      if CEN = '1' then
-        Auto_Wait_t1 <= Auto_Wait;
-        Auto_Wait_t2 <= Auto_Wait_t1;
-        No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
-                  (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
-                  (I_BTR and (not IR(4) or F(Flag_Z)));
-        if TState = 2 then
-          if SetEI = '1' then
-            IntE_FF1 <= '1';
-            IntE_FF2 <= '1';
-          end if;
-          if I_RETN = '1' then
-            IntE_FF1 <= IntE_FF2;
-          end if;
-        end if;
-        if TState = 3 then
-          if SetDI = '1' then
-            IntE_FF1 <= '0';
-            IntE_FF2 <= '0';
-          end if;
-        end if;
-        if IntCycle = '1' or NMICycle = '1' then
-          Halt_FF <= '0';
-        end if;
-        if MCycle = "001" and TState = 2 and Wait_n = '1' then
-          M1_n <= '1';
-        end if;
-        if BusReq_s = '1' and BusAck = '1' then
-        else
-          BusAck <= '0';
-          if TState = 2 and Wait_n = '0' then
-          elsif T_Res = '1' then
-            if Halt = '1' then
-              Halt_FF <= '1';
-            end if;
-            if BusReq_s = '1' then
-              BusAck <= '1';
-            else
-              TState <= "001";
-              if NextIs_XY_Fetch = '1' then
-                MCycle <= "110";
-                Pre_XY_F_M <= MCycle;
-                if IR = "00110110" and Mode = 0 then
-                  Pre_XY_F_M <= "010";
-                end if;
-              elsif (MCycle = "111") or
-                (MCycle = "110" and Mode = 1 and ISet /= "01") then
-                MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
-              elsif (MCycle = MCycles) or
-                No_BTR = '1' or
-                (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
-                M1_n <= '0';
-                MCycle <= "001";
-                IntCycle <= '0';
-                NMICycle <= '0';
-                if NMI_s = '1' and Prefix = "00" then
-                  NMICycle <= '1';
-                  IntE_FF1 <= '0';
-                elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
-                  IntCycle <= '1';
-                  IntE_FF1 <= '0';
-                  IntE_FF2 <= '0';
-                end if;
-              else
-                MCycle <= std_logic_vector(unsigned(MCycle) + 1);
-              end if;
-            end if;
-          else
-            if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
-
-              TState <= TState + 1;
-            end if;
-          end if;
-        end if;
-        if TState = 0 then
-          M1_n <= '0';
-        end if;
-      end if;
-    end if;
-  end process;
-
-  process (IntCycle, NMICycle, MCycle)
-  begin
-    Auto_Wait <= '0';
-    if IntCycle = '1' or NMICycle = '1' then
-      if MCycle = "001" then
-        Auto_Wait <= '1';
-      end if;
-    end if;
-  end process;
-
-end;
diff --git a/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/cpu/T80_ALU.vhd
deleted file mode 100644
index 7e8a9995..00000000
--- a/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/cpu/T80_ALU.vhd	
+++ /dev/null
@@ -1,370 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0238 : Fixed zero flag for 16 bit SBC and ADC
---
---      0240 : Added GB operations
---
---      0242 : Cleanup
---
---      0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16         : in  std_logic;
-		Z16             : in  std_logic;
-		ALU_Op          : in  std_logic_vector(3 downto 0);
-		IR              : in  std_logic_vector(5 downto 0);
-		ISet            : in  std_logic_vector(1 downto 0);
-		BusA            : in  std_logic_vector(7 downto 0);
-		BusB            : in  std_logic_vector(7 downto 0);
-		F_In            : in  std_logic_vector(7 downto 0);
-		Q               : out std_logic_vector(7 downto 0);
-		F_Out           : out std_logic_vector(7 downto 0)
-	);
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
-	procedure AddSub(A        : std_logic_vector;
-					 B        : std_logic_vector;
-					 Sub      : std_logic;
-					 Carry_In : std_logic;
-			  signal Res      : out std_logic_vector;
-			  signal Carry    : out std_logic) is
-
-		variable B_i          : unsigned(A'length - 1 downto 0);
-		variable Res_i        : unsigned(A'length + 1 downto 0);
-	begin
-		if Sub = '1' then
-			B_i := not unsigned(B);
-		else
-			B_i :=     unsigned(B);
-		end if;
-
-		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
-		Carry <= Res_i(A'length + 1);
-		Res <= std_logic_vector(Res_i(A'length downto 1));
-	end;
-
-	-- AddSub variables (temporary signals)
-	signal UseCarry                : std_logic;
-	signal Carry7_v                : std_logic;
-	signal Overflow_v              : std_logic;
-	signal HalfCarry_v             : std_logic;
-	signal Carry_v                 : std_logic;
-	signal Q_v                     : std_logic_vector(7 downto 0);
-
-	signal BitMask                 : std_logic_vector(7 downto 0);
-
-begin
-
-	with IR(5 downto 3) select BitMask <= "00000001" when "000",
-										  "00000010" when "001",
-										  "00000100" when "010",
-										  "00001000" when "011",
-										  "00010000" when "100",
-										  "00100000" when "101",
-										  "01000000" when "110",
-										  "10000000" when others;
-
-	UseCarry <= not ALU_Op(2) and ALU_Op(0);
-	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
-	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
-	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-	-- bug fix - parity flag is just parity for 8080, also overflow for Z80
-	process (Carry_v, Carry7_v, Q_v)
-	begin
-		if(Mode=2) then
-			OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
-					   Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7));  else
-	OverFlow_v <= Carry_v xor Carry7_v;
-		end if;
-	end process;
-
-	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
-		variable Q_t : std_logic_vector(7 downto 0);
-		variable DAA_Q : unsigned(8 downto 0);
-	begin
-		Q_t := "--------";
-		F_Out <= F_In;
-		DAA_Q := "---------";
-		case ALU_Op is
-		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_C) <= '0';
-			case ALU_OP(2 downto 0) is
-			when "000" | "001" => -- ADD, ADC
-				Q_t := Q_v;
-				F_Out(Flag_C) <= Carry_v;
-				F_Out(Flag_H) <= HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "010" | "011" | "111" => -- SUB, SBC, CP
-				Q_t := Q_v;
-				F_Out(Flag_N) <= '1';
-				F_Out(Flag_C) <= not Carry_v;
-				F_Out(Flag_H) <= not HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "100" => -- AND
-				Q_t(7 downto 0) := BusA and BusB;
-				F_Out(Flag_H) <= '1';
-			when "101" => -- XOR
-				Q_t(7 downto 0) := BusA xor BusB;
-				F_Out(Flag_H) <= '0';
-			when others => -- OR "110"
-				Q_t(7 downto 0) := BusA or BusB;
-				F_Out(Flag_H) <= '0';
-			end case;
-			if ALU_Op(2 downto 0) = "111" then -- CP
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			else
-				F_Out(Flag_X) <= Q_t(3);
-				F_Out(Flag_Y) <= Q_t(5);
-			end if;
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				if Z16 = '1' then
-					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
-				end if;
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			case ALU_Op(2 downto 0) is
-			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
-			when others =>
-				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			end case;
-			if Arith16 = '1' then
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-				F_Out(Flag_P) <= F_In(Flag_P);
-			end if;
-		when "1100" =>
-			-- DAA
-			F_Out(Flag_H) <= F_In(Flag_H);
-			F_Out(Flag_C) <= F_In(Flag_C);
-			DAA_Q(7 downto 0) := unsigned(BusA);
-			DAA_Q(8) := '0';
-			if F_In(Flag_N) = '0' then
-				-- After addition
-				-- Alow > 9 or H = 1
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if (DAA_Q(3 downto 0) > 9) then
-						F_Out(Flag_H) <= '1';
-					else
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q := DAA_Q + 6;
-				end if;
-				-- new Ahigh > 9 or C = 1
-				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q + 96; -- 0x60
-				end if;
-			else
-				-- After subtraction
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if DAA_Q(3 downto 0) > 5 then
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
-				end if;
-				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q - 352; -- 0x160
-				end if;
-			end if;
-			F_Out(Flag_X) <= DAA_Q(3);
-			F_Out(Flag_Y) <= DAA_Q(5);
-			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
-			Q_t := std_logic_vector(DAA_Q(7 downto 0));
-			if DAA_Q(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= DAA_Q(7);
-			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
-				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
-		when "1101" | "1110" =>
-			-- RLD, RRD
-			Q_t(7 downto 4) := BusA(7 downto 4);
-			if ALU_Op(0) = '1' then
-				Q_t(3 downto 0) := BusB(7 downto 4);
-			else
-				Q_t(3 downto 0) := BusB(3 downto 0);
-			end if;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-		when "1001" =>
-			-- BIT
-			Q_t(7 downto 0) := BusB and BitMask;
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				F_Out(Flag_P) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-				F_Out(Flag_P) <= '0';
-			end if;
-			F_Out(Flag_H) <= '1';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= '0';
-			F_Out(Flag_Y) <= '0';
-			if IR(2 downto 0) /= "110" then
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			end if;
-		when "1010" =>
-			-- SET
-			Q_t(7 downto 0) := BusB or BitMask;
-		when "1011" =>
-			-- RES
-			Q_t(7 downto 0) := BusB and not BitMask;
-		when "1000" =>
-			-- ROT
-			case IR(5 downto 3) is
-			when "000" => -- RLC
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := BusA(7);
-				F_Out(Flag_C) <= BusA(7);
-			when "010" => -- RL
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(7);
-			when "001" => -- RRC
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(0);
-				F_Out(Flag_C) <= BusA(0);
-			when "011" => -- RR
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(0);
-			when "100" => -- SLA
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := '0';
-				F_Out(Flag_C) <= BusA(7);
-			when "110" => -- SLL (Undocumented) / SWAP
-				if Mode = 3 then
-					Q_t(7 downto 4) := BusA(3 downto 0);
-					Q_t(3 downto 0) := BusA(7 downto 4);
-					F_Out(Flag_C) <= '0';
-				else
-					Q_t(7 downto 1) := BusA(6 downto 0);
-					Q_t(0) := '1';
-					F_Out(Flag_C) <= BusA(7);
-				end if;
-			when "101" => -- SRA
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(7);
-				F_Out(Flag_C) <= BusA(0);
-			when others => -- SRL
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := '0';
-				F_Out(Flag_C) <= BusA(0);
-			end case;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			if ISet = "00" then
-				F_Out(Flag_P) <= F_In(Flag_P);
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-			end if;
-		when others =>
-			null;
-		end case;
-		Q <= Q_t;
-	end process;
-end;
diff --git a/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/cpu/T80_MCode.vhd
deleted file mode 100644
index 7d407fb8..00000000
--- a/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/cpu/T80_MCode.vhd	
+++ /dev/null
@@ -1,2027 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0211 : Fixed IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0235 : Added IM 2 fix by Mike Johnson
---
---      0238 : Added NoRead signal
---
---      0238b: Fixed instruction timing for POP and DJNZ
---
---      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
-
---      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
---
---      0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80_MCode is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR                              : in std_logic_vector(7 downto 0);
-		ISet                    : in std_logic_vector(1 downto 0);
-		MCycle                  : in std_logic_vector(2 downto 0);
-		F                               : in std_logic_vector(7 downto 0);
-		NMICycle                : in std_logic;
-		IntCycle                : in std_logic;
-		XY_State                : in std_logic_vector(1 downto 0);
-		MCycles                 : out std_logic_vector(2 downto 0);
-		TStates                 : out std_logic_vector(2 downto 0);
-		Prefix                  : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD
-		Inc_PC                  : out std_logic;
-		Inc_WZ                  : out std_logic;
-		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg             : out std_logic;
-		Read_To_Acc             : out std_logic;
-		Set_BusA_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op                  : out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU                : out std_logic;
-		PreserveC               : out std_logic;
-		Arith16                 : out std_logic;
-		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ                    : out std_logic;
-		Jump                    : out std_logic;
-		JumpE                   : out std_logic;
-		JumpXY                  : out std_logic;
-		Call                    : out std_logic;
-		RstP                    : out std_logic;
-		LDZ                             : out std_logic;
-		LDW                             : out std_logic;
-		LDSPHL                  : out std_logic;
-		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH              : out std_logic;
-		ExchangeRp              : out std_logic;
-		ExchangeAF              : out std_logic;
-		ExchangeRS              : out std_logic;
-		I_DJNZ                  : out std_logic;
-		I_CPL                   : out std_logic;
-		I_CCF                   : out std_logic;
-		I_SCF                   : out std_logic;
-		I_RETN                  : out std_logic;
-		I_BT                    : out std_logic;
-		I_BC                    : out std_logic;
-		I_BTR                   : out std_logic;
-		I_RLD                   : out std_logic;
-		I_RRD                   : out std_logic;
-		I_INRC                  : out std_logic;
-		SetDI                   : out std_logic;
-		SetEI                   : out std_logic;
-		IMode                   : out std_logic_vector(1 downto 0);
-		Halt                    : out std_logic;
-		NoRead                  : out std_logic;
-		Write                   : out std_logic;
-		XYbit_undoc             : out std_logic
-	);
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
-	constant aNone      : std_logic_vector(2 downto 0) := "111";
-	constant aBC        : std_logic_vector(2 downto 0) := "000";
-	constant aDE        : std_logic_vector(2 downto 0) := "001";
-	constant aXY        : std_logic_vector(2 downto 0) := "010";
-	constant aIOA       : std_logic_vector(2 downto 0) := "100";
-	constant aSP        : std_logic_vector(2 downto 0) := "101";
-	constant aZI        : std_logic_vector(2 downto 0) := "110";
-
-	function is_cc_true(
-		F : std_logic_vector(7 downto 0);
-		cc : bit_vector(2 downto 0)
-		) return boolean is
-	begin
-		if Mode = 3 then
-			case cc is
-			when "000" => return F(7) = '0'; -- NZ
-			when "001" => return F(7) = '1'; -- Z
-			when "010" => return F(4) = '0'; -- NC
-			when "011" => return F(4) = '1'; -- C
-			when "100" => return false;
-			when "101" => return false;
-			when "110" => return false;
-			when "111" => return false;
-			end case;
-		else
-			case cc is
-			when "000" => return F(6) = '0'; -- NZ
-			when "001" => return F(6) = '1'; -- Z
-			when "010" => return F(0) = '0'; -- NC
-			when "011" => return F(0) = '1'; -- C
-			when "100" => return F(2) = '0'; -- PO
-			when "101" => return F(2) = '1'; -- PE
-			when "110" => return F(7) = '0'; -- P
-			when "111" => return F(7) = '1'; -- M
-			end case;
-		end if;
-	end;
-
-begin
-
-	process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State)
-		variable DDD : std_logic_vector(2 downto 0);
-		variable SSS : std_logic_vector(2 downto 0);
-		variable DPair : std_logic_vector(1 downto 0);
-		variable IRB : bit_vector(7 downto 0);
-	begin
-		DDD := IR(5 downto 3);
-		SSS := IR(2 downto 0);
-		DPair := IR(5 downto 4);
-		IRB := to_bitvector(IR);
-
-		MCycles <= "001";
-		if MCycle = "001" then
-			TStates <= "100";
-		else
-			TStates <= "011";
-		end if;
-		Prefix <= "00";
-		Inc_PC <= '0';
-		Inc_WZ <= '0';
-		IncDec_16 <= "0000";
-		Read_To_Acc <= '0';
-		Read_To_Reg <= '0';
-		Set_BusB_To <= "0000";
-		Set_BusA_To <= "0000";
-		ALU_Op <= "0" & IR(5 downto 3);
-		Save_ALU <= '0';
-		PreserveC <= '0';
-		Arith16 <= '0';
-		IORQ <= '0';
-		Set_Addr_To <= aNone;
-		Jump <= '0';
-		JumpE <= '0';
-		JumpXY <= '0';
-		Call <= '0';
-		RstP <= '0';
-		LDZ <= '0';
-		LDW <= '0';
-		LDSPHL <= '0';
-		Special_LD <= "000";
-		ExchangeDH <= '0';
-		ExchangeRp <= '0';
-		ExchangeAF <= '0';
-		ExchangeRS <= '0';
-		I_DJNZ <= '0';
-		I_CPL <= '0';
-		I_CCF <= '0';
-		I_SCF <= '0';
-		I_RETN <= '0';
-		I_BT <= '0';
-		I_BC <= '0';
-		I_BTR <= '0';
-		I_RLD <= '0';
-		I_RRD <= '0';
-		I_INRC <= '0';
-		SetDI <= '0';
-		SetEI <= '0';
-		IMode <= "11";
-		Halt <= '0';
-		NoRead <= '0';
-		Write <= '0';
-		XYbit_undoc <= '0';
-
-		case ISet is
-		when "00" =>
-
-------------------------------------------------------------------------------
---
---      Unprefixed instructions
---
-------------------------------------------------------------------------------
-
-		case IRB is
--- 8 BIT LOAD GROUP
-		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-			-- LD r,r'
-			Set_BusB_To(2 downto 0) <= SSS;
-			ExchangeRp <= '1';
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-			-- LD r,n
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-			-- LD r,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-			-- LD (HL),r
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110110" =>
-			-- LD (HL),n
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00001010" =>
-			-- LD A,(BC)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00011010" =>
-			-- LD A,(DE)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00111010" =>
-			if Mode = 3 then
-				-- LDD A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD A,(nn)
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-				when 4 =>
-					Read_To_Acc <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00000010" =>
-			-- LD (BC),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00010010" =>
-			-- LD (DE),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110010" =>
-			if Mode = 3 then
-				-- LDD (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),A
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					Set_BusB_To <= "0111";
-				when 4 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 16 BIT LOAD GROUP
-		when "00000001"|"00010001"|"00100001"|"00110001" =>
-			-- LD dd,nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1000";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1001";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-		when "00101010" =>
-			if Mode = 3 then
-				-- LDI A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD HL,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Set_BusA_To(2 downto 0) <= "101"; -- L
-					Read_To_Reg <= '1';
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Set_BusA_To(2 downto 0) <= "100"; -- H
-					Read_To_Reg <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00100010" =>
-			if Mode = 3 then
-				-- LDI (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "0101"; -- L
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "0100"; -- H
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11111001" =>
-			-- LD SP,HL
-			TStates <= "110";
-			LDSPHL <= '1';
-		when "11000101"|"11010101"|"11100101"|"11110101" =>
-			-- PUSH qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_TO <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "0111";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '0';
-					Set_BusB_To(3) <= '0';
-				end if;
-			when 2 =>
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "1011";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '1';
-					Set_BusB_To(3) <= '0';
-				end if;
-				Write <= '1';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "11000001"|"11010001"|"11100001"|"11110001" =>
-			-- POP qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1011";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				IncDec_16 <= "0111";
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "0111";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
-		when "11101011" =>
-			if Mode /= 3 then
-				-- EX DE,HL
-				ExchangeDH <= '1';
-			end if;
-		when "00001000" =>
-			if Mode = 3 then
-				-- LD (nn),SP
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "1000";
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "1001";
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EX AF,AF'
-				ExchangeAF <= '1';
-			end if;
-		when "11011001" =>
-			if Mode = 3 then
-				-- RETI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-					SetEI <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EXX
-				ExchangeRS <= '1';
-			end if;
-		when "11100011" =>
-			if Mode /= 3 then
-				-- EX (SP),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aSP;
-				when 2 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0101";
-					Set_BusB_To <= "0101";
-					Set_Addr_To <= aSP;
-				when 3 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0100";
-					Set_BusB_To <= "0100";
-					Set_Addr_To <= aSP;
-				when 5 =>
-					IncDec_16 <= "1111";
-					TStates <= "101";
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
-		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-			-- ADD A,r
-			-- ADC A,r
-			-- SUB A,r
-			-- SBC A,r
-			-- AND A,r
-			-- OR A,r
-			-- XOR A,r
-			-- CP A,r
-			Set_BusB_To(2 downto 0) <= SSS;
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-			-- ADD A,(HL)
-			-- ADC A,(HL)
-			-- SUB A,(HL)
-			-- SBC A,(HL)
-			-- AND A,(HL)
-			-- OR A,(HL)
-			-- XOR A,(HL)
-			-- CP A,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			when others => null;
-			end case;
-		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-			-- ADD A,n
-			-- ADC A,n
-			-- SUB A,n
-			-- SBC A,n
-			-- AND A,n
-			-- OR A,n
-			-- XOR A,n
-			-- CP A,n
-			MCycles <= "010";
-			if MCycle = "010" then
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			end if;
-		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-			-- INC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0000";
-		when "00110100" =>
-			-- INC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				ALU_Op <= "0000";
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-			-- DEC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0010";
-		when "00110101" =>
-			-- DEC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				ALU_Op <= "0010";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
-		when "00100111" =>
-			-- DAA
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			ALU_Op <= "1100";
-			Save_ALU <= '1';
-		when "00101111" =>
-			-- CPL
-			I_CPL <= '1';
-		when "00111111" =>
-			-- CCF
-			I_CCF <= '1';
-		when "00110111" =>
-			-- SCF
-			I_SCF <= '1';
-		when "00000000" =>
-			if NMICycle = '1' then
-				-- NMI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif IntCycle = '1' then
-				-- INT (IM 2)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					LDZ <= '1';
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 5 =>
-					Jump <= '1';
-				when others => null;
-				end case;
-			else
-				-- NOP
-			end if;
-		when "01110110" =>
-			-- HALT
-			Halt <= '1';
-		when "11110011" =>
-			-- DI
-			SetDI <= '1';
-		when "11111011" =>
-			-- EI
-			SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
-		when "00001001"|"00011001"|"00101001"|"00111001" =>
-			-- ADD HL,ss
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				NoRead <= '1';
-				ALU_Op <= "0000";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusA_To(2 downto 0) <= "101";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-				when others =>
-					Set_BusB_To <= "1000";
-				end case;
-				TStates <= "100";
-				Arith16 <= '1';
-			when 3 =>
-				NoRead <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				ALU_Op <= "0001";
-				Set_BusA_To(2 downto 0) <= "100";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-				when others =>
-					Set_BusB_To <= "1001";
-				end case;
-				Arith16 <= '1';
-			when others =>
-			end case;
-		when "00000011"|"00010011"|"00100011"|"00110011" =>
-			-- INC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "01";
-			IncDec_16(1 downto 0) <= DPair;
-		when "00001011"|"00011011"|"00101011"|"00111011" =>
-			-- DEC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "11";
-			IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
-		when "00000111"
-			-- RLCA
-			|"00010111"
-			-- RLA
-			|"00001111"
-			-- RRCA
-			|"00011111" =>
-			-- RRA
-			Set_BusA_To(2 downto 0) <= "111";
-			ALU_Op <= "1000";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-
--- JUMP GROUP
-		when "11000011" =>
-			-- JP nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				Inc_PC <= '1';
-				Jump <= '1';
-			when others => null;
-			end case;
-		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+C),A
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-						Set_BusB_To     <= "0111";
-					when 2 =>
-						Write <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "01" =>
-					-- LD (nn),A
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						Set_BusB_To <= "0111";
-					when 4 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "10" =>
-					-- LD A,($FF00+C)
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-					when 2 =>
-						Read_To_Acc <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "11" =>
-					-- LD A,(nn)
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-					when 4 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- JP cc,nn
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Jump <= '1';
-					end if;
-				when others => null;
-				end case;
-			end if;
-		when "00011000" =>
-			if Mode /= 2 then
-				-- JR e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00111000" =>
-			if Mode /= 2 then
-				-- JR C,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00110000" =>
-			if Mode /= 2 then
-				-- JR NC,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00101000" =>
-			if Mode /= 2 then
-				-- JR Z,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00100000" =>
-			if Mode /= 2 then
-				-- JR NZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "11101001" =>
-			-- JP (HL)
-			JumpXY <= '1';
-		when "00010000" =>
-			if Mode = 3 then
-				I_DJNZ <= '1';
-			elsif Mode < 2 then
-				-- DJNZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					I_DJNZ <= '1';
-					Set_BusB_To <= "1010";
-					Set_BusA_To(2 downto 0) <= "000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					I_DJNZ <= '1';
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-
--- CALL AND RETURN GROUP
-		when "11001101" =>
-			-- CALL nn
-			MCycles <= "101";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				IncDec_16 <= "1111";
-				Inc_PC <= '1';
-				TStates <= "100";
-				Set_Addr_To <= aSP;
-				LDW <= '1';
-				Set_BusB_To <= "1101";
-			when 4 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 5 =>
-				Write <= '1';
-				Call <= '1';
-			when others => null;
-			end case;
-		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
-			if IR(5) = '0' or Mode /= 3 then
-				-- CALL cc,nn
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					LDW <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						IncDec_16 <= "1111";
-						Set_Addr_TO <= aSP;
-						TStates <= "100";
-						Set_BusB_To <= "1101";
-					else
-						MCycles <= "011";
-					end if;
-				when 4 =>
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 5 =>
-					Write <= '1';
-					Call <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11001001" =>
-			-- RET
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_TO <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				LDZ <= '1';
-			when 3 =>
-				Jump <= '1';
-				IncDec_16 <= "0111";
-			when others => null;
-			end case;
-		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+nn),A
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-						Set_BusB_To     <= "0111";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "01" =>
-					-- ADD SP,n
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						ALU_Op <= "0000";
-						Inc_PC <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_BusA_To <= "1000";
-						Set_BusB_To <= "0110";
-					when 3 =>
-						NoRead <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						ALU_Op <= "0001";
-						Set_BusA_To <= "1001";
-						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
-					when others =>
-					end case;
-				when "10" =>
-					-- LD A,($FF00+nn)
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-					when 3 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				when "11" =>
-					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
-					MCycles <= "101";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						LDW <= '1';
-					when 4 =>
-						Set_BusA_To(2 downto 0) <= "101"; -- L
-						Read_To_Reg <= '1';
-						Inc_WZ <= '1';
-						Set_Addr_To <= aZI;
-					when 5 =>
-						Set_BusA_To(2 downto 0) <= "100"; -- H
-						Read_To_Reg <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- RET cc
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Set_Addr_TO <= aSP;
-					else
-						MCycles <= "001";
-					end if;
-					TStates <= "101";
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-				when others => null;
-				end case;
-			end if;
-		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-			-- RST p
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1101";
-			when 2 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 3 =>
-				Write <= '1';
-				RstP <= '1';
-			when others => null;
-			end case;
-
--- INPUT AND OUTPUT GROUP
-		when "11011011" =>
-			if Mode /= 3 then
-				-- IN A,(n)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-				when 3 =>
-					Read_To_Acc <= '1';
-					IORQ <= '1';
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-				when others => null;
-				end case;
-			end if;
-		when "11010011" =>
-			if Mode /= 3 then
-				-- OUT (n),A
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-					Set_BusB_To <= "0111";
-				when 3 =>
-					Write <= '1';
-					IORQ <= '1';
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-				when others => null;
-				end case;
-			end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
-		when "11001011" =>
-			if Mode /= 2 then
-				Prefix <= "01";
-			end if;
-
-		when "11101101" =>
-			if Mode < 2 then
-				Prefix <= "10";
-			end if;
-
-		when "11011101"|"11111101" =>
-			if Mode < 2 then
-				Prefix <= "11";
-			end if;
-
-		end case;
-
-		when "01" =>
-
-------------------------------------------------------------------------------
---
---      CB prefixed instructions
---
-------------------------------------------------------------------------------
-
-			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
-			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-				-- RLC r
-				-- RL r
-				-- RRC r
-				-- RR r
-				-- SLA r
-				-- SRA r
-				-- SRL r
-				-- SLL r (Undocumented) / SWAP r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1000";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- R/S (IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1000";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-
-			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-				-- RLC (HL)
-				-- RL (HL)
-				-- RRC (HL)
-				-- RR (HL)
-				-- SRA (HL)
-				-- SRL (HL)
-				-- SLA (HL)
-				-- SLL (HL) (Undocumented) / SWAP (HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
-				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-				-- BIT b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-					  ALU_Op <= "1001";
-					end if;
-				else
-				-- BIT b,(IX+d), undocumented
-					MCycles <= "010";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1001";
-						TStates <= "100";
-					when others => null;
-					end case;
-				end if;
-			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-				-- BIT b,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1001";
-					TStates <= "100";
-				when others => null;
-				end case;
-			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-				-- SET b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1010";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- SET b,(IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1010";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-				-- SET b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-				-- RES b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1011";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- RES b,(IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1011";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-				
-			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-				-- RES b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end case;
-
-		when others =>
-
-------------------------------------------------------------------------------
---
---      ED prefixed instructions
---
-------------------------------------------------------------------------------
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
-				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
-				|                                            "10100100"|"10100101"|"10100110"|"10100111"
-				|                                            "10101100"|"10101101"|"10101110"|"10101111"
-				|                                            "10110100"|"10110101"|"10110110"|"10110111"
-				|                                            "10111100"|"10111101"|"10111110"|"10111111"
-				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
-				null; -- NOP, undocumented
-			when "01111110"|"01111111" =>
-				-- NOP, undocumented
-				null;
--- 8 BIT LOAD GROUP
-			when "01010111" =>
-				-- LD A,I
-				Special_LD <= "100";
-				TStates <= "101";
-			when "01011111" =>
-				-- LD A,R
-				Special_LD <= "101";
-				TStates <= "101";
-			when "01000111" =>
-				-- LD I,A
-				Special_LD <= "110";
-				TStates <= "101";
-			when "01001111" =>
-				-- LD R,A
-				Special_LD <= "111";
-				TStates <= "101";
--- 16 BIT LOAD GROUP
-			when "01001011"|"01011011"|"01101011"|"01111011" =>
-				-- LD dd,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1000";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '1';
-					end if;
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1001";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '0';
-					end if;
-				when others => null;
-				end case;
-			when "01000011"|"01010011"|"01100011"|"01110011" =>
-				-- LD (nn),dd
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1000";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1001";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10100000" | "10101000" | "10110000" | "10111000" =>
-				-- LDI, LDD, LDIR, LDDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0000";
-					Set_Addr_To <= aDE;
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- IX
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					I_BT <= '1';
-					TStates <= "101";
-					Write <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0101"; -- DE
-					else
-						IncDec_16 <= "1101";
-					end if;
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100001" | "10101001" | "10110001" | "10111001" =>
-				-- CPI, CPD, CPIR, CPDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0111";
-					Save_ALU <= '1';
-					PreserveC <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0110";
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					I_BC <= '1';
-					TStates <= "101";
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-				-- NEG
-				Alu_OP <= "0010";
-				Set_BusB_To <= "0111";
-				Set_BusA_To <= "1010";
-				Read_To_Acc <= '1';
-				Save_ALU <= '1';
-			when "01000110"|"01001110"|"01100110"|"01101110" =>
-				-- IM 0
-				IMode <= "00";
-			when "01010110"|"01110110" =>
-				-- IM 1
-				IMode <= "01";
-			when "01011110"|"01110111" =>
-				-- IM 2
-				IMode <= "10";
--- 16 bit arithmetic
-			when "01001010"|"01011010"|"01101010"|"01111010" =>
-				-- ADC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0001";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-						when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0001";
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-					when others =>
-						Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01000010"|"01010010"|"01100010"|"01110010" =>
-				-- SBC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-					when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					when others =>
-							Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01101111" =>
-				-- RLD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1101";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RLD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01100111" =>
-				-- RRD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1110";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RRD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-				-- RETI, RETN
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-				when others => null;
-				end case;
-			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-				-- IN r,(C)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					if IR(5 downto 3) /= "110" then
-						Read_To_Reg <= '1';
-						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
-					end if;
-					I_INRC <= '1';
-				when others =>
-				end case;
-			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-				-- OUT (C),r
-				-- OUT (C),0
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
-					if IR(5 downto 3) = "110" then
-						Set_BusB_To(3) <= '1';
-					end if;
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					Write <= '1';
-					IORQ <= '1';
-				when others =>
-				end case;
-			when "10100010" | "10101010" | "10110010" | "10111010" =>
-				-- INI, IND, INIR, INDR
-				-- note B is decremented AFTER being put on the bus
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aXY;
-				when 3 =>
-					if IR(3) = '0' then
-						--IncDec_16 <= "0010";
-						IncDec_16 <= "0110";
-					else
-						--IncDec_16 <= "1010";
-						IncDec_16 <= "1110";
-					end if;
-					TStates <= "100";
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100011" | "10101011" | "10110011" | "10111011" =>
-				-- OUTI, OUTD, OTIR, OTDR
-				-- note B is decremented BEFORE being put on the bus.
-				-- mikej fix for hl inc
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aBC;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- mikej
-					else
-						IncDec_16 <= "1110"; -- mikej
-					end if;
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end case;
-
-		end case;
-
-		if Mode = 1 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "011";
-			end if;
-		end if;
-
-		if Mode = 3 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "100";
-			end if;
-		end if;
-
-		if Mode < 2 then
-			if MCycle = "110" then
-				Inc_PC <= '1';
-				if Mode = 1 then
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-					Set_BusB_To(2 downto 0) <= SSS;
-					Set_BusB_To(3) <= '0';
-				end if;
-				if IRB = "00110110" or IRB = "11001011" then
-					Set_Addr_To <= aNone;
-				end if;
-			end if;
-			if MCycle = "111" then
-				if Mode = 0 then
-					TStates <= "101";
-				end if;
-				if ISet /= "01" then
-					Set_Addr_To <= aXY;
-				end if;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-				if IRB = "00110110" or ISet = "01" then
-					-- LD (HL),n
-					Inc_PC <= '1';
-				else
-					NoRead <= '1';
-				end if;
-			end if;
-		end if;
-
-	end process;
-
-end;
diff --git a/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/cpu/T80_Pack.vhd
deleted file mode 100644
index 6904b66b..00000000
--- a/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/cpu/T80_Pack.vhd	
+++ /dev/null
@@ -1,220 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
-	component T80
-	generic(
-		Mode : integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		RESET_n         : in std_logic;
-		CLK_n           : in std_logic;
-		CEN                     : in std_logic;
-		WAIT_n          : in std_logic;
-		INT_n           : in std_logic;
-		NMI_n           : in std_logic;
-		BUSRQ_n         : in std_logic;
-		M1_n            : out std_logic;
-		IORQ            : out std_logic;
-		NoRead          : out std_logic;
-		Write           : out std_logic;
-		RFSH_n          : out std_logic;
-		HALT_n          : out std_logic;
-		BUSAK_n         : out std_logic;
-		A                       : out std_logic_vector(15 downto 0);
-		DInst           : in std_logic_vector(7 downto 0);
-		DI                      : in std_logic_vector(7 downto 0);
-		DO                      : out std_logic_vector(7 downto 0);
-		MC                      : out std_logic_vector(2 downto 0);
-		TS                      : out std_logic_vector(2 downto 0);
-		IntCycle_n      : out std_logic;
-		IntE            : out std_logic;
-		Stop            : out std_logic
-	);
-	end component;
-
-	component T80_Reg
-	port(
-		Clk                     : in std_logic;
-		CEN                     : in std_logic;
-		WEH                     : in std_logic;
-		WEL                     : in std_logic;
-		AddrA           : in std_logic_vector(2 downto 0);
-		AddrB           : in std_logic_vector(2 downto 0);
-		AddrC           : in std_logic_vector(2 downto 0);
-		DIH                     : in std_logic_vector(7 downto 0);
-		DIL                     : in std_logic_vector(7 downto 0);
-		DOAH            : out std_logic_vector(7 downto 0);
-		DOAL            : out std_logic_vector(7 downto 0);
-		DOBH            : out std_logic_vector(7 downto 0);
-		DOBL            : out std_logic_vector(7 downto 0);
-		DOCH            : out std_logic_vector(7 downto 0);
-		DOCL            : out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-	component T80_MCode
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR                      : in  std_logic_vector(7 downto 0);
-		ISet                    : in  std_logic_vector(1 downto 0);
-		MCycle                  : in  std_logic_vector(2 downto 0);
-		F                       : in  std_logic_vector(7 downto 0);
-		NMICycle                : in  std_logic;
-		IntCycle                : in  std_logic;
-		XY_State                : in  std_logic_vector(1 downto 0);
-		MCycles                 : out std_logic_vector(2 downto 0);
-		TStates                 : out std_logic_vector(2 downto 0);
-		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC                  : out std_logic;
-		Inc_WZ                  : out std_logic;
-		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg             : out std_logic;
-		Read_To_Acc             : out std_logic;
-		Set_BusA_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op                  : out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU                : out std_logic;
-		PreserveC               : out std_logic;
-		Arith16                 : out std_logic;
-		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ                    : out std_logic;
-		Jump                    : out std_logic;
-		JumpE                   : out std_logic;
-		JumpXY                  : out std_logic;
-		Call                    : out std_logic;
-		RstP                    : out std_logic;
-		LDZ                     : out std_logic;
-		LDW                     : out std_logic;
-		LDSPHL                  : out std_logic;
-		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH              : out std_logic;
-		ExchangeRp              : out std_logic;
-		ExchangeAF              : out std_logic;
-		ExchangeRS              : out std_logic;
-		I_DJNZ                  : out std_logic;
-		I_CPL                   : out std_logic;
-		I_CCF                   : out std_logic;
-		I_SCF                   : out std_logic;
-		I_RETN                  : out std_logic;
-		I_BT                    : out std_logic;
-		I_BC                    : out std_logic;
-		I_BTR                   : out std_logic;
-		I_RLD                   : out std_logic;
-		I_RRD                   : out std_logic;
-		I_INRC                  : out std_logic;
-		SetDI                   : out std_logic;
-		SetEI                   : out std_logic;
-		IMode                   : out std_logic_vector(1 downto 0);
-		Halt                    : out std_logic;
-		NoRead                  : out std_logic;
-		Write                   : out std_logic;
-		XYbit_undoc             : out std_logic
-	);
-	end component;
-
-	component T80_ALU
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16         : in  std_logic;
-		Z16             : in  std_logic;
-		ALU_Op          : in  std_logic_vector(3 downto 0);
-		IR              : in  std_logic_vector(5 downto 0);
-		ISet            : in  std_logic_vector(1 downto 0);
-		BusA            : in  std_logic_vector(7 downto 0);
-		BusB            : in  std_logic_vector(7 downto 0);
-		F_In            : in  std_logic_vector(7 downto 0);
-		Q               : out std_logic_vector(7 downto 0);
-		F_Out           : out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-end;
diff --git a/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/cpu/T80_Reg.vhd
deleted file mode 100644
index 998033ef..00000000
--- a/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/cpu/T80_Reg.vhd	
+++ /dev/null
@@ -1,114 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
---      0242 : Initial release
---
---      0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
-  port(
-    Clk   : in  std_logic;
-    CEN   : in  std_logic;
-    WEH   : in  std_logic;
-    WEL   : in  std_logic;
-    AddrA : in  std_logic_vector(2 downto 0);
-    AddrB : in  std_logic_vector(2 downto 0);
-    AddrC : in  std_logic_vector(2 downto 0);
-    DIH   : in  std_logic_vector(7 downto 0);
-    DIL   : in  std_logic_vector(7 downto 0);
-    DOAH  : out std_logic_vector(7 downto 0);
-    DOAL  : out std_logic_vector(7 downto 0);
-    DOBH  : out std_logic_vector(7 downto 0);
-    DOBL  : out std_logic_vector(7 downto 0);
-    DOCH  : out std_logic_vector(7 downto 0);
-    DOCL  : out std_logic_vector(7 downto 0)
-    );
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
-  type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
-  signal      RegsH   : Register_Image(0 to 7);
-  signal      RegsL   : Register_Image(0 to 7);
-
-begin
-
-  process (Clk)
-  begin
-    if Clk'event and Clk = '1' then
-      if CEN = '1' then
-        if WEH = '1' then
-          RegsH(to_integer(unsigned(AddrA))) <= DIH;
-        end if;
-        if WEL = '1' then
-          RegsL(to_integer(unsigned(AddrA))) <= DIL;
-        end if;
-      end if;
-    end if;
-  end process;
-
-  DOAH <= RegsH(to_integer(unsigned(AddrA)));
-  DOAL <= RegsL(to_integer(unsigned(AddrA)));
-  DOBH <= RegsH(to_integer(unsigned(AddrB)));
-  DOBL <= RegsL(to_integer(unsigned(AddrB)));
-  DOCH <= RegsH(to_integer(unsigned(AddrC)));
-  DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
diff --git a/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/cpu/T80a.vhd b/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/cpu/T80a.vhd
deleted file mode 100644
index 33d61068..00000000
--- a/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/cpu/T80a.vhd	
+++ /dev/null
@@ -1,280 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core, asynchronous top level
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0211 : Fixed interrupt cycle
---
---      0235 : Updated for T80 interface change
---
---      0238 : Updated for T80 interface change
---
---      0240 : Updated for T80 interface change
---
---      0242 : Updated for T80 interface change
---
---      0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80a is
-  generic(
-    Mode : integer := 0     -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-    );
-  port(
-    RESET_n    : in  std_logic;
-    CLK_n      : in  std_logic;
-    CLK_EN_SYS : in  std_logic;
-    WAIT_n     : in  std_logic;
-    INT_n      : in  std_logic;
-    NMI_n      : in  std_logic;
-    BUSRQ_n    : in  std_logic;
-    M1_n       : out std_logic;
-    MREQ_n     : out std_logic;
-    IORQ_n     : out std_logic;
-    RD_n       : out std_logic;
-    WR_n       : out std_logic;
-    RFSH_n     : out std_logic;
-    HALT_n     : out std_logic;
-    BUSAK_n    : out std_logic;
-    A          : out std_logic_vector(15 downto 0);
-		DI						: in  std_logic_vector(7 downto 0);
-		DO						: out std_logic_vector(7 downto 0)
-    );
-end T80a;
-
-architecture rtl of T80a is
-
-  signal CEN          : std_logic;
-  signal Reset_s      : std_logic;
-  signal IntCycle_n   : std_logic;
-  signal IORQ         : std_logic;
-  signal NoRead       : std_logic;
-  signal Write        : std_logic;
-  signal MREQ         : std_logic;
-  signal MReq_Inhibit : std_logic;
-  signal Req_Inhibit  : std_logic;
-  signal RD           : std_logic;
-  signal MREQ_n_i     : std_logic;
-  signal IORQ_n_i     : std_logic;
-  signal RD_n_i       : std_logic;
-  signal WR_n_i       : std_logic;
-  signal RFSH_n_i     : std_logic;
-  signal BUSAK_n_i    : std_logic;
-  signal A_i          : std_logic_vector(15 downto 0);
-	signal DO_Reg			: std_logic_vector(7 downto 0);
-  signal DI_Reg       : std_logic_vector (7 downto 0);  -- Input synchroniser
-  signal Wait_s       : std_logic;
-  signal MCycle       : std_logic_vector(2 downto 0);
-  signal TState       : std_logic_vector(2 downto 0);
-
-begin
-
-  -- clock enable supplied from clocking system
-  CEN <= CLK_EN_SYS;
-
-  BUSAK_n <= BUSAK_n_i;
-  MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
-  RD_n_i <= not RD or Req_Inhibit;
-
-  MREQ_n <= MREQ_n_i;
-  IORQ_n <= IORQ_n_i;
-  RD_n <= RD_n_i;
-  WR_n <= WR_n_i;
-  RFSH_n <= RFSH_n_i;
-  A <= A_i;
-	DO <= DO_Reg;
-
---   process (RESET_n, CLK_n)
---   begin
---     if RESET_n = '0' then
---       Reset_s <= '0';
---     elsif CLK_n'event and CLK_n = '1' then
---       Reset_s <= '1';
---     end if;
---   end process;
-  -- T80 reset input has already proper characteristics:
-  --   * asynchronous assertion
-  --   * deassertion synchronous to CLK_n (main_clk)
-  Reset_s <= RESET_n;
-
-  u0 : T80
-    generic map(
-      Mode       => Mode,
-      IOWait     => 1)
-    port map(
-      CEN        => CEN,
-      M1_n       => M1_n,
-      IORQ       => IORQ,
-      NoRead     => NoRead,
-      Write      => Write,
-      RFSH_n     => RFSH_n_i,
-      HALT_n     => HALT_n,
-      WAIT_n     => Wait_s,
-      INT_n      => INT_n,
-      NMI_n      => NMI_n,
-      RESET_n    => Reset_s,
-      BUSRQ_n    => BUSRQ_n,
-      BUSAK_n    => BUSAK_n_i,
-      CLK_n      => CLK_n,
-      A          => A_i,
-			DInst => DI,
-      DI         => DI_Reg,
-			DO => DO_Reg,
-      MC         => MCycle,
-      TS         => TState,
-      IntCycle_n => IntCycle_n);
-
-  process (CLK_n)
-  begin
-    if CLK_n'event and CLK_n = '0' then
-      if CEN = '1' then
-        Wait_s <= WAIT_n;
-        if TState = "011" and BUSAK_n_i = '1' then
-					DI_Reg <= to_x01(DI);
-        end if;
-      end if;
-    end if;
-  end process;
-
-  process (Reset_s,CLK_n)
-  begin
-    if Reset_s = '0' then
-      WR_n_i <= '1';
-    elsif CLK_n'event and CLK_n = '1' then
-      if CEN = '1' then
-        WR_n_i <= '1';
-        if TState = "001" then      -- To short for IO writes !!!!!!!!!!!!!!!!!!!
-          WR_n_i <= not Write;
-        end if;
-      end if;
-    end if;
-  end process;
-
-  process (Reset_s,CLK_n)
-  begin
-    if Reset_s = '0' then
-      Req_Inhibit <= '0';
-    elsif CLK_n'event and CLK_n = '1' then
-      if CEN = '1' then
-        if MCycle = "001" and TState = "010" then
-          Req_Inhibit <= '1';
-        else
-          Req_Inhibit <= '0';
-        end if;
-      end if;
-    end if;
-  end process;
-
-  process (Reset_s,CLK_n)
-  begin
-    if Reset_s = '0' then
-      MReq_Inhibit <= '0';
-    elsif CLK_n'event and CLK_n = '0' then
-      if CEN = '1' then
-        if MCycle = "001" and TState = "010" then
-          MReq_Inhibit <= '1';
-        else
-          MReq_Inhibit <= '0';
-        end if;
-      end if;
-    end if;
-  end process;
-
-  process(Reset_s,CLK_n)
-  begin
-    if Reset_s = '0' then
-      RD <= '0';
-      IORQ_n_i <= '1';
-      MREQ <= '0';
-    elsif CLK_n'event and CLK_n = '0' then
-      if CEN = '1' then
-
-        if MCycle = "001" then
-          if TState = "001" then
-            RD <= IntCycle_n;
-            MREQ <= IntCycle_n;
-            IORQ_n_i <= IntCycle_n;
-          end if;
-          if TState = "011" then
-            RD <= '0';
-            IORQ_n_i <= '1';
-            MREQ <= '1';
-          end if;
-          if TState = "100" then
-            MREQ <= '0';
-          end if;
-        else
-          if TState = "001" and NoRead = '0' then
-            RD <= not Write;
-            IORQ_n_i <= not IORQ;
-            MREQ <= not IORQ;
-          end if;
-          if TState = "011" then
-            RD <= '0';
-            IORQ_n_i <= '1';
-            MREQ <= '0';
-          end if;
-        end if;
-
-      end if;
-    end if;
-  end process;
-
-end;
diff --git a/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/ladybug.vhd b/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/ladybug.vhd
index a1a186fe..fe4f652a 100644
--- a/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/ladybug.vhd	
+++ b/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/ladybug.vhd	
@@ -65,7 +65,7 @@ port (
 	O_PIXCE      : out std_logic;
 
 	-- Audio Interface --------------------------------------------------------
-	O_AUDIO      : out signed(7 downto 0);
+	O_AUDIO      : out std_logic_vector( 8 downto 0);
 	
 	but_coin_s   : in  std_logic_vector( 1 downto 0);
 	but_fire_s   : in  std_logic_vector( 1 downto 0);
@@ -160,8 +160,8 @@ begin
 		rgb_b_o           => O_VIDEO_B,
 		hsync_n_o         => O_HSYNC,
 		vsync_n_o         => O_VSYNC,
-	   vblank_o          => O_VBLANK,
-	   hblank_o          => O_HBLANK,
+		vblank_o          => O_VBLANK,
+		hblank_o          => O_HBLANK,
 		audio_o           => O_AUDIO,
 		rom_cpu_a_o       => rom_cpu_a_s,
 		rom_cpu_d_i       => rom_cpu_d_s,
diff --git a/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_cpu_unit.vhd b/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_cpu_unit.vhd
index 7d41074f..5646437b 100644
--- a/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_cpu_unit.vhd	
+++ b/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_cpu_unit.vhd	
@@ -119,14 +119,14 @@ begin
   -- "wait" has to be modelled with the clock enable because the T80 is not
   -- able to enlarge write accesses properly when they are delayed with "wait"
   t80_clk_en_s <= clk_en_4mhz_i and wait_n_s;
-  T80a_b : entity work.T80a
+  T80a_b : entity work.T80s
     generic map (
       Mode => 0
     )
     port map (
       RESET_n    => res_n_i,
-      CLK_n      => clk_20mhz_i,
-      CLK_EN_SYS => t80_clk_en_s,
+      CLK        => clk_20mhz_i,
+      CEN        => t80_clk_en_s,
       WAIT_n     => wait_n_s,
       INT_n      => int_n_s,
       NMI_n      => nmi_n_s,
diff --git a/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_machine.vhd b/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_machine.vhd
index 584b8391..dbe5d75b 100644
--- a/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_machine.vhd	
+++ b/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_machine.vhd	
@@ -77,10 +77,10 @@ entity ladybug_machine is
     hsync_n_o         : out std_logic;
     vsync_n_o         : out std_logic;
     comp_sync_n_o     : out std_logic;
-	 vblank_o          : out std_logic;
-	 hblank_o          : out std_logic;
+    vblank_o          : out std_logic;
+    hblank_o          : out std_logic;
     -- Audio Interface --------------------------------------------------------
-    audio_o           : out signed( 7 downto 0);
+    audio_o           : out std_logic_vector( 8 downto 0);
     -- CPU ROM Interface ------------------------------------------------------
     rom_cpu_a_o       : out std_logic_vector(14 downto 0);
     rom_cpu_d_i       : in  std_logic_vector( 7 downto 0);
diff --git a/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/sound/ladybug_sound_unit.vhd b/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_sound_unit.vhd
similarity index 88%
rename from Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/sound/ladybug_sound_unit.vhd
rename to Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_sound_unit.vhd
index 23ad2a6a..8fe04ba8 100644
--- a/Arcade_MiST/Ladybug Hardware/Dorodon_MiST/rtl/sound/ladybug_sound_unit.vhd	
+++ b/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_sound_unit.vhd	
@@ -59,7 +59,7 @@ entity ladybug_sound_unit is
     wr_n_i         : in  std_logic;
     d_from_cpu_i   : in  std_logic_vector(7 downto 0);
     sound_wait_n_o : out std_logic;
-    audio_o        : out signed(7 downto 0)
+    audio_o        : out std_logic_vector(8 downto 0)
   );
 
 end ladybug_sound_unit;
@@ -70,7 +70,7 @@ architecture struct of ladybug_sound_unit is
          ready_c1_s  : std_logic;
 
   signal aout_b1_s,
-         aout_c1_s   : signed(7 downto 0);
+         aout_c1_s   : std_logic_vector(7 downto 0);
 
 begin
 
@@ -117,23 +117,7 @@ begin
   --
   -- Purpose:
   --   Mix the digital audio of the two SN76489 instances.
-  --   Additional care is taken to avoid audio overfow/clipping.
-  --
-  mix: process (aout_b1_s,
-                aout_c1_s)
-    variable sum_v : signed(8 downto 0);
-  begin
-    sum_v := RESIZE(aout_b1_s, 9) + RESIZE(aout_c1_s, 9);
-
-    if sum_v > 127 then
-      audio_o <= to_signed(127, 8);
-    elsif sum_v < -128 then
-      audio_o <= to_signed(-128, 8);
-    else
-      audio_o <= RESIZE(sum_v, 8);
-    end if;
-
-  end process mix;
+  audio_o <= std_logic_vector(unsigned('0'&aout_b1_s) + unsigned('0'&aout_c1_s));
   -- 
   -----------------------------------------------------------------------------
 
diff --git a/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/COPYING b/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/COPYING
deleted file mode 100644
index 60549be5..00000000
--- a/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/COPYING	
+++ /dev/null
@@ -1,340 +0,0 @@
-		    GNU GENERAL PUBLIC LICENSE
-		       Version 2, June 1991
-
- Copyright (C) 1989, 1991 Free Software Foundation, Inc.
-                       59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- Everyone is permitted to copy and distribute verbatim copies
- of this license document, but changing it is not allowed.
-
-			    Preamble
-
-  The licenses for most software are designed to take away your
-freedom to share and change it.  By contrast, the GNU General Public
-License is intended to guarantee your freedom to share and change free
-software--to make sure the software is free for all its users.  This
-General Public License applies to most of the Free Software
-Foundation's software and to any other program whose authors commit to
-using it.  (Some other Free Software Foundation software is covered by
-the GNU Library General Public License instead.)  You can apply it to
-your programs, too.
-
-  When we speak of free software, we are referring to freedom, not
-price.  Our General Public Licenses are designed to make sure that you
-have the freedom to distribute copies of free software (and charge for
-this service if you wish), that you receive source code or can get it
-if you want it, that you can change the software or use pieces of it
-in new free programs; and that you know you can do these things.
-
-  To protect your rights, we need to make restrictions that forbid
-anyone to deny you these rights or to ask you to surrender the rights.
-These restrictions translate to certain responsibilities for you if you
-distribute copies of the software, or if you modify it.
-
-  For example, if you distribute copies of such a program, whether
-gratis or for a fee, you must give the recipients all the rights that
-you have.  You must make sure that they, too, receive or can get the
-source code.  And you must show them these terms so they know their
-rights.
-
-  We protect your rights with two steps: (1) copyright the software, and
-(2) offer you this license which gives you legal permission to copy,
-distribute and/or modify the software.
-
-  Also, for each author's protection and ours, we want to make certain
-that everyone understands that there is no warranty for this free
-software.  If the software is modified by someone else and passed on, we
-want its recipients to know that what they have is not the original, so
-that any problems introduced by others will not reflect on the original
-authors' reputations.
-
-  Finally, any free program is threatened constantly by software
-patents.  We wish to avoid the danger that redistributors of a free
-program will individually obtain patent licenses, in effect making the
-program proprietary.  To prevent this, we have made it clear that any
-patent must be licensed for everyone's free use or not licensed at all.
-
-  The precise terms and conditions for copying, distribution and
-modification follow.
-
-		    GNU GENERAL PUBLIC LICENSE
-   TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
-
-  0. This License applies to any program or other work which contains
-a notice placed by the copyright holder saying it may be distributed
-under the terms of this General Public License.  The "Program", below,
-refers to any such program or work, and a "work based on the Program"
-means either the Program or any derivative work under copyright law:
-that is to say, a work containing the Program or a portion of it,
-either verbatim or with modifications and/or translated into another
-language.  (Hereinafter, translation is included without limitation in
-the term "modification".)  Each licensee is addressed as "you".
-
-Activities other than copying, distribution and modification are not
-covered by this License; they are outside its scope.  The act of
-running the Program is not restricted, and the output from the Program
-is covered only if its contents constitute a work based on the
-Program (independent of having been made by running the Program).
-Whether that is true depends on what the Program does.
-
-  1. You may copy and distribute verbatim copies of the Program's
-source code as you receive it, in any medium, provided that you
-conspicuously and appropriately publish on each copy an appropriate
-copyright notice and disclaimer of warranty; keep intact all the
-notices that refer to this License and to the absence of any warranty;
-and give any other recipients of the Program a copy of this License
-along with the Program.
-
-You may charge a fee for the physical act of transferring a copy, and
-you may at your option offer warranty protection in exchange for a fee.
-
-  2. You may modify your copy or copies of the Program or any portion
-of it, thus forming a work based on the Program, and copy and
-distribute such modifications or work under the terms of Section 1
-above, provided that you also meet all of these conditions:
-
-    a) You must cause the modified files to carry prominent notices
-    stating that you changed the files and the date of any change.
-
-    b) You must cause any work that you distribute or publish, that in
-    whole or in part contains or is derived from the Program or any
-    part thereof, to be licensed as a whole at no charge to all third
-    parties under the terms of this License.
-
-    c) If the modified program normally reads commands interactively
-    when run, you must cause it, when started running for such
-    interactive use in the most ordinary way, to print or display an
-    announcement including an appropriate copyright notice and a
-    notice that there is no warranty (or else, saying that you provide
-    a warranty) and that users may redistribute the program under
-    these conditions, and telling the user how to view a copy of this
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-
-These requirements apply to the modified work as a whole.  If
-identifiable sections of that work are not derived from the Program,
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-    <one line to give the program's name and a brief idea of what it does.>
-    Copyright (C) 19yy  <name of author>
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-    This program is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
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-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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-  `Gnomovision' (which makes passes at compilers) written by James Hacker.
-
-  <signature of Ty Coon>, 1 April 1989
-  Ty Coon, President of Vice
-
-This General Public License does not permit incorporating your program into
-proprietary programs.  If your program is a subroutine library, you may
-consider it more useful to permit linking proprietary applications with the
-library.  If this is what you want to do, use the GNU Library General
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diff --git a/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/README b/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/README
deleted file mode 100644
index 33630144..00000000
--- a/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/README	
+++ /dev/null
@@ -1,143 +0,0 @@
-
-An SN76489AN Compatible Implementation in VHDL
-==============================================
-Version: $Date: 2006/06/18 19:28:40 $
-
-Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
-See the file COPYING.
-
-
-Integration
------------
-
-The sn76489 design exhibits all interface signals as the original chip. It
-only differs in the audio data output which is provided as an 8 bit signed
-vector instead of an analog output pin.
-
-  generic (
-    clock_div_16_g : integer := 1
-    -- Set to '1' when operating the design in SN76489 mode. The primary clock
-    -- input is divided by 16 in this variant. The data sheet mentions the
-    -- SN76494 which contains a divide-by-2 clock input stage. Set the generic
-    -- to '0' to enable this mode.
-  );
-  port (
-    clock_i    : in  std_logic;
-    -- Primary clock input
-    -- Drive with the target frequency or any integer multiple of it.
-
-    clock_en_i : in  std_logic;
-    -- Clock enable
-    -- A '1' on this input qualifies a valid rising edge on clock_i. A '0'
-    -- disables the next rising clock edge, effectivley halting the design
-    -- until the next enabled rising clock edge.
-    -- Can be used to run the core at lower frequencies than applied on
-    -- clock_i.
-
-    res_n_i    : in  std_logic;
-    -- Asynchronous low active reset input.
-    -- Sets all sequential elements to a known state.
-
-    ce_n_i     : in  std_logic;
-    -- Chip enable, low active.
-
-    we_n_i     : in  std_logic;
-    -- Write enable, low active.
-
-    ready_o    : out std_logic;
-    -- Ready indication to microprocessor.
-
-    d_i        : in  std_logic_vector(0 to 7);
-    -- Data input
-    -- MSB 0 ... 7 LSB
-
-    aout_o     : out signed(0 to 7)
-    -- Audio output, signed vector
-    -- MSB/SIGN 0 ... 7 LSB
-  );
-
-
-Both 8 bit vector ports are defined (0 to 7) which declares bit 0 to be the
-MSB and bit 7 to be the LSB. This has been implemented according to TI's data
-sheet, thus all register/data format figures apply 1:1 for this design.
-Many systems will flip the system data bus bit wise before it is connected to
-this PSG. This is simply achieved with the following VHDL construct:
-
-  signal data_s : std_logic_vector(7 downto 0);
-
-  ...
-  d_i => data_s,
-  ...
-
-d_i and data_s will be assigned from left to right, resulting in the expected
-bit assignment:
-
-  d_i    data_s
-   0       7
-   1       6
-      ...
-   6       1
-   7       0
-
-
-As this design is fully synchronous, care has to be taken when the design
-replaces an SN76489 in asynchronous mode. No problems are expected when
-interfacing the code to other synchronous components.
-
-
-Design Hierarchy
-----------------
-
-  sn76489_top
-    |
-    +-- sn76489_latch_ctrl
-    |
-    +-- sn76489_clock_div
-    |
-    +-- sn76489_tone
-    |     |
-    |     \-- sn76489_attentuator
-    |
-    +-- sn76489_tone
-    |     |
-    |     \-- sn76489_attentuator
-    |
-    +-- sn76489_tone
-    |     |
-    |     \-- sn76489_attentuator
-    |
-    \-- sn76489_noise
-          |
-          \-- sn76489_attentuator
-
-Resulting compilation sequence:
-
-  sn76489_comp_pack-p.vhd
-  sn76489_top.vhd
-  sn76489_latch_ctrl.vhd
-  sn76489_latch_ctrl-c.vhd
-  sn76489_clock_div.vhd
-  sn76489_clock_div-c.vhd
-  sn76489_attenuator.vhd
-  sn76489_attenuator-c.vhd
-  sn76489_tone.vhd
-  sn76489_tone-c.vhd
-  sn76489_noise.vhd
-  sn76489_noise-c.vhd
-  sn76489_top-c.vhd
-
-Skip the files containing VHDL configurations when analyzing the code for
-synthesis.
-
-
-References
-----------
-
-* TI Data sheet SN76489.pdf
-  ftp://ftp.whtech.com/datasheets%20&%20manuals/SN76489.pdf
-
-* John Kortink's article on the SN76489:
-  http://web.inter.nl.net/users/J.Kortink/home/articles/sn76489/
-
-* Maxim's "SN76489 notes" in
-  http://www.smspower.org/maxim/docs/SN76489.txt
diff --git a/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/sn76489_attenuator.vhd b/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/sn76489_attenuator.vhd
deleted file mode 100644
index 444064e5..00000000
--- a/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/sn76489_attenuator.vhd	
+++ /dev/null
@@ -1,114 +0,0 @@
--------------------------------------------------------------------------------
---
--- Synthesizable model of TI's SN76489AN.
---
--- $Id: sn76489_attenuator.vhd,v 1.7 2006/02/27 20:30:10 arnim Exp $
---
--- Attenuator Module
---
--------------------------------------------------------------------------------
---
--- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity sn76489_attenuator is
-
-  port (
-    attenuation_i : in  std_logic_vector(0 to 3);
-    factor_i      : in  signed(0 to 1);
-    product_o     : out signed(0 to 7)
-  );
-
-end sn76489_attenuator;
-
-
-architecture rtl of sn76489_attenuator is
-
-begin
-
-  -----------------------------------------------------------------------------
-  -- Process attenuate
-  --
-  -- Purpose:
-  --   Determine the attenuation and generate the resulting product.
-  --
-  --   The maximum attenuation value is 31 which corresponds to volume off.
-  --   As described in the data sheet, the maximum "playing" attenuation is
-  --     28 = 16 + 8 + 4
-  --
-  --   The table for the volume constants is derived from the following
-  --   formula (each step is 2dB voltage):
-  --     v(0)   = 31
-  --     v(n+1) = v(n) * 0.79432823
-  --
-  attenuate: process (attenuation_i,
-                      factor_i)
-
-    type     volume_t is array (natural range 0 to 15) of natural;
-    constant volume_c : volume_t :=
-      (31, 25, 20, 16, 12, 10, 8, 6, 5, 4, 3, 2, 2, 2, 1, 0);
-
-    variable attenuation_v  : unsigned(attenuation_i'range);
-    variable volume_v       : signed(product_o'range);
-
-  begin
-
-    attenuation_v := unsigned(attenuation_i);
-
-    -- volume look-up table
-    volume_v := to_signed(volume_c(to_integer(attenuation_v)),
-                          product_o'length);
-
-    -- this replaces a multiplier and consumes a bit fewer
-    -- resources
-    case to_integer(factor_i) is
-      when +1 =>
-        product_o <= volume_v;
-      when -1 =>
-        product_o <= -volume_v;
-      when others =>
-        product_o <= (others => '0');
-    end case;
-
-  end process attenuate;
-  --
-  -----------------------------------------------------------------------------
-
-end rtl;
diff --git a/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/sn76489_clock_div.vhd b/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/sn76489_clock_div.vhd
deleted file mode 100644
index eab86beb..00000000
--- a/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/sn76489_clock_div.vhd	
+++ /dev/null
@@ -1,134 +0,0 @@
--------------------------------------------------------------------------------
---
--- Synthesizable model of TI's SN76489AN.
---
--- $Id: sn76489_clock_div.vhd,v 1.4 2005/10/10 21:51:27 arnim Exp $
---
--- Clock Divider Circuit
---
--------------------------------------------------------------------------------
---
--- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity sn76489_clock_div is
-
-  generic (
-    clock_div_16_g : integer := 1
-  );
-  port (
-    clock_i    : in  std_logic;
-    clock_en_i : in  std_logic;
-    res_n_i    : in  std_logic;
-    clk_en_o   : out boolean
-  );
-
-end sn76489_clock_div;
-
-
-library ieee;
-use ieee.numeric_std.all;
-
-architecture rtl of sn76489_clock_div is
-
-  signal cnt_s,
-         cnt_q  : unsigned(3 downto 0);
-
-begin
-
-  -----------------------------------------------------------------------------
-  -- Process seq
-  --
-  -- Purpose:
-  --   Implements the sequential counter element.
-  --
-  seq: process (clock_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      cnt_q <= (others => '0');
-    elsif clock_i'event and clock_i = '1' then
-      cnt_q <= cnt_s;
-    end if;
-  end process seq;
-  --
-  -----------------------------------------------------------------------------
-
-
-  -----------------------------------------------------------------------------
-  -- Process comb
-  --
-  -- Purpose:
-  --   Implements the combinational counter logic.
-  --
-  comb: process (clock_en_i,
-                 cnt_q)
-  begin
-    -- default assignments
-    cnt_s    <= cnt_q;
-    clk_en_o <= false;
-
-    if clock_en_i = '1' then
-
-      if cnt_q = 0 then
-        clk_en_o <= true;
-
-        if clock_div_16_g = 1 then
-          cnt_s  <= to_unsigned(15, cnt_q'length);
-        elsif clock_div_16_g = 0 then
-          cnt_s  <= to_unsigned( 1, cnt_q'length);
-        else
-          -- pragma translate_off
-          assert false
-            report "Generic clock_div_16_g must be either 0 or 1."
-            severity failure;
-          -- pragma translate_on
-        end if;
-
-      else
-        cnt_s    <= cnt_q - 1;
-
-      end if;
-
-    end if;
-
-  end process comb;
-  --
-  -----------------------------------------------------------------------------
-
-end rtl;
diff --git a/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/sn76489_latch_ctrl.vhd b/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/sn76489_latch_ctrl.vhd
deleted file mode 100644
index 789720c2..00000000
--- a/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/sn76489_latch_ctrl.vhd	
+++ /dev/null
@@ -1,138 +0,0 @@
--------------------------------------------------------------------------------
---
--- Synthesizable model of TI's SN76489AN.
---
--- $Id: sn76489_latch_ctrl.vhd,v 1.6 2006/02/27 20:30:10 arnim Exp $
---
--- Latch Control Unit
---
--------------------------------------------------------------------------------
---
--- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity sn76489_latch_ctrl is
-
-  port (
-    clock_i    : in  std_logic;
-    clk_en_i   : in  boolean;
-    res_n_i    : in  std_logic;
-    ce_n_i     : in  std_logic;
-    we_n_i     : in  std_logic;
-    d_i        : in  std_logic_vector(0 to 7);
-    ready_o    : out std_logic;
-    tone1_we_o : out boolean;
-    tone2_we_o : out boolean;
-    tone3_we_o : out boolean;
-    noise_we_o : out boolean;
-    r2_o       : out std_logic
-  );
-
-end sn76489_latch_ctrl;
-
-
-library ieee;
-use ieee.numeric_std.all;
-
-architecture rtl of sn76489_latch_ctrl is
-
-  signal reg_q   : std_logic_vector(0 to 2);
-  signal we_q    : boolean;
-  signal ready_q : std_logic;
-
-begin
-
-  -----------------------------------------------------------------------------
-  -- Process seq
-  --
-  -- Purpose:
-  --   Implements the sequential elements.
-  --
-  seq: process (clock_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      reg_q     <= (others => '0');
-      we_q      <= false;
-      ready_q   <= '0';
-
-    elsif clock_i'event and clock_i = '1' then
-      -- READY Flag Output ----------------------------------------------------
-      if ready_q = '0' and we_q then
-        if clk_en_i then
-          -- assert READY when write access happened
-          ready_q <= '1';
-        end if;
-      elsif ce_n_i = '1' then
-        -- deassert READY when access has finished
-        ready_q <= '0';
-      end if;
-
-      -- Register Selection ---------------------------------------------------
-      if ce_n_i = '0' and we_n_i = '0' then
-        if clk_en_i then
-          if d_i(0) = '1' then
-            reg_q <= d_i(1 to 3);
-          end if;
-          we_q  <= true;
-        end if;
-      else
-        we_q  <= false;
-      end if;
-
-    end if;
-  end process seq;
-  --
-  -----------------------------------------------------------------------------
-
-
-  -----------------------------------------------------------------------------
-  -- Output mapping
-  -----------------------------------------------------------------------------
-  tone1_we_o <= reg_q(0 to 1) = "00" and we_q;
-  tone2_we_o <= reg_q(0 to 1) = "01" and we_q;
-  tone3_we_o <= reg_q(0 to 1) = "10" and we_q;
-  noise_we_o <= reg_q(0 to 1) = "11" and we_q;
-
-  r2_o       <= reg_q(2);
-
-  ready_o    <=   ready_q
-                when ce_n_i = '0' else
-                  '1';
-
-end rtl;
diff --git a/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/sn76489_noise.vhd b/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/sn76489_noise.vhd
deleted file mode 100644
index 688bdd56..00000000
--- a/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/sn76489_noise.vhd	
+++ /dev/null
@@ -1,278 +0,0 @@
--------------------------------------------------------------------------------
---
--- Synthesizable model of TI's SN76489AN.
---
--- $Id: sn76489_noise.vhd,v 1.6 2006/02/27 20:30:10 arnim Exp $
---
--- Noise Generator
---
--------------------------------------------------------------------------------
---
--- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity sn76489_noise is
-
-  port (
-    clock_i    : in  std_logic;
-    clk_en_i   : in  boolean;
-    res_n_i    : in  std_logic;
-    we_i       : in  boolean;
-    d_i        : in  std_logic_vector(0 to 7);
-    r2_i       : in  std_logic;
-    tone3_ff_i : in  std_logic;
-    noise_o    : out signed(0 to 7)
-  );
-
-end sn76489_noise;
-
-architecture rtl of sn76489_noise is
-
-  signal nf_q       : std_logic_vector(0 to 1);
-  signal fb_q       : std_logic;
-  signal a_q        : std_logic_vector(0 to 3);
-  signal freq_cnt_q : unsigned(0 to 6);
-  signal freq_ff_q  : std_logic;
-
-  signal shift_source_s,
-         shift_source_q    : std_logic;
-  signal shift_rise_edge_s : boolean;
-
-  signal lfsr_q            : std_logic_vector(0 to 15);
-
-  signal freq_s      : signed(0 to 1);
-
-begin
-
-  -----------------------------------------------------------------------------
-  -- Process cpu_regs
-  --
-  -- Purpose:
-  --   Implements the registers writable by the CPU.
-  --
-  cpu_regs: process (clock_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      nf_q <= (others => '0');
-      fb_q <= '0';
-      a_q  <= (others => '1');
-
-    elsif clock_i'event and clock_i = '1' then
-      if clk_en_i and we_i then
-        if r2_i = '0' then
-          -- access to control register
-          -- both access types can write to the control register!
-          nf_q <= d_i(6 to 7);
-          fb_q <= d_i(5);
-
-        else
-          -- access to attenuator register
-          -- both access types can write to the attenuator register!
-          a_q <= d_i(4 to 7);
-
-        end if;
-      end if;
-    end if;
-  end process cpu_regs;
-  --
-  -----------------------------------------------------------------------------
-
-
-  -----------------------------------------------------------------------------
-  -- Process freq_gen
-  --
-  -- Purpose:
-  --   Implements the frequency generation components.
-  --
-  freq_gen: process (clock_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      freq_cnt_q <= (others => '0');
-      freq_ff_q  <= '0';
-
-    elsif clock_i'event and clock_i = '1' then
-      if clk_en_i then
-        if freq_cnt_q = 0 then
-          -- reload frequency counter according to NF setting
-          case nf_q is
-            when "00" =>
-              freq_cnt_q <= to_unsigned(16 * 2 - 1, freq_cnt_q'length);
-            when "01" =>
-              freq_cnt_q <= to_unsigned(16 * 4 - 1, freq_cnt_q'length);
-            when "10" =>
-              freq_cnt_q <= to_unsigned(16 * 8 - 1, freq_cnt_q'length);
-            when others =>
-              null;
-          end case;
-
-          freq_ff_q <= not freq_ff_q;
-
-        else
-          -- decrement frequency counter
-          freq_cnt_q <= freq_cnt_q - 1;
-
-        end if;
-
-      end if;
-    end if;
-  end process freq_gen;
-  --
-  -----------------------------------------------------------------------------
-
-
-  -----------------------------------------------------------------------------
-  -- Multiplex the source of the LFSR's shift enable
-  -----------------------------------------------------------------------------
-  shift_source_s <=   tone3_ff_i
-                    when nf_q = "11" else
-                      freq_ff_q;
-
-  -----------------------------------------------------------------------------
-  -- Process rise_edge
-  --
-  -- Purpose:
-  --   Detect the rising edge of the selected LFSR shift source.
-  --
-  rise_edge: process (clock_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      shift_source_q <= '0';
-
-    elsif clock_i'event and clock_i = '1' then
-      if clk_en_i then
-        shift_source_q <= shift_source_s;
-      end if;
-    end if;
-  end process rise_edge;
-  --
-  -----------------------------------------------------------------------------
-
-  -- detect rising edge on shift source
-  shift_rise_edge_s <= shift_source_q = '0' and shift_source_s = '1';
-
-
-  -----------------------------------------------------------------------------
-  -- Process lfsr
-  --
-  -- Purpose:
-  --   Implements the LFSR that generates noise.
-  --   Note: This implementation shifts the register right, i.e. from index
-  --         15 towards 0 => bit 15 is the input, bit 0 is the output
-  --
-  --   Tapped bits according to MAME's sn76496.c, implemented in function
-  --   lfsr_tapped_f.
-  --
-  lfsr: process (clock_i, res_n_i)
-
-    function lfsr_tapped_f(lfsr : in std_logic_vector) return std_logic is
-      constant tapped_bits_c : std_logic_vector(0 to 15)
-        -- tapped bits are 0, 2, 15
-        := "1010000000000001";
-      variable parity_v : std_logic;
-    begin
-      parity_v := '0';
-
-      for idx in lfsr'low to lfsr'high loop
-        parity_v := parity_v xor (lfsr(idx) and tapped_bits_c(idx));
-      end loop;
-
-      return parity_v;
-    end;
-
-  begin
-    if res_n_i = '0' then
-      -- reset LFSR to "0000000000000001"
-      lfsr_q               <= (others => '0');
-      lfsr_q(lfsr_q'right) <= '1';
-
-    elsif clock_i'event and clock_i = '1' then
-      if clk_en_i then
-        if we_i and r2_i = '0' then
-          -- write to noise register
-          -- -> reset LFSR
-          lfsr_q               <= (others => '0');
-          lfsr_q(lfsr_q'right) <= '1';
-
-        elsif shift_rise_edge_s then
-
-          -- shift LFSR left towards MSB
-          for idx in lfsr_q'right-1 downto lfsr_q'left loop
-            lfsr_q(idx) <= lfsr_q(idx+1);
-          end loop;
-
-          -- determine input bit
-          if fb_q = '0' then
-            -- "Periodic" Noise
-            -- -> input to LFSR is output
-            lfsr_q(lfsr_q'right) <= lfsr_q(lfsr_q'left);
-          else
-            -- "White" Noise
-            -- -> input to LFSR is parity of tapped bits
-            lfsr_q(lfsr_q'right) <= lfsr_tapped_f(lfsr_q);
-          end if;
-
-        end if;
-
-      end if;
-    end if;
-  end process lfsr;
-  --
-  -----------------------------------------------------------------------------
-
-
-  -----------------------------------------------------------------------------
-  -- Map output of LFSR to signed value for attenuator.
-  -----------------------------------------------------------------------------
-  freq_s <=   to_signed(+1, 2)
-            when lfsr_q(0) = '1' else
-              to_signed( 0, 2);
-
-
-  -----------------------------------------------------------------------------
-  -- The attenuator itself
-  -----------------------------------------------------------------------------
-  attenuator_b : entity work.sn76489_attenuator
-    port map (
-      attenuation_i => a_q,
-      factor_i      => freq_s,
-      product_o     => noise_o
-    );
-
-end rtl;
diff --git a/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/sn76489_tone.vhd b/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/sn76489_tone.vhd
deleted file mode 100644
index 3658efcc..00000000
--- a/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/sn76489_tone.vhd	
+++ /dev/null
@@ -1,188 +0,0 @@
--------------------------------------------------------------------------------
---
--- Synthesizable model of TI's SN76489AN.
---
--- $Id: sn76489_tone.vhd,v 1.5 2006/02/27 20:30:10 arnim Exp $
---
--- Tone Generator
---
--------------------------------------------------------------------------------
---
--- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity sn76489_tone is
-
-  port (
-    clock_i  : in  std_logic;
-    clk_en_i : in  boolean;
-    res_n_i  : in  std_logic;
-    we_i     : in  boolean;
-    d_i      : in  std_logic_vector(0 to 7);
-    r2_i     : in  std_logic;
-    ff_o     : out std_logic;
-    tone_o   : out signed(0 to 7)
-  );
-
-end sn76489_tone;
-
-architecture rtl of sn76489_tone is
-
-  signal f_q        : std_logic_vector(0 to 9);
-  signal a_q        : std_logic_vector(0 to 3);
-  signal freq_cnt_q : unsigned(0 to 9);
-  signal freq_ff_q  : std_logic;
-
-  signal freq_s     : signed(0 to 1);
-
-  function all_zero(a : in std_logic_vector) return boolean is
-    variable result_v : boolean;
-  begin
-    result_v := true;
-
-    for idx in a'low to a'high loop
-      if a(idx) /= '0' then
-        result_v := false;
-      end if;
-    end loop;
-
-    return result_v;
-  end;
-
-begin
-
-  -----------------------------------------------------------------------------
-  -- Process cpu_regs
-  --
-  -- Purpose:
-  --   Implements the registers writable by the CPU.
-  --
-  cpu_regs: process (clock_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      f_q <= (others => '0');
-      a_q <= (others => '1');
-
-    elsif clock_i'event and clock_i = '1' then
-      if clk_en_i and we_i then
-        if r2_i = '0' then
-          -- access to frequency register
-          if d_i(0) = '0' then
-            f_q(0 to 5) <= d_i(2 to 7);
-          else
-            f_q(6 to 9) <= d_i(4 to 7);
-          end if;
-
-        else
-          -- access to attenuator register
-          -- both access types can write to the attenuator register!
-          a_q <= d_i(4 to 7);
-
-        end if;
-      end if;
-    end if;
-  end process cpu_regs;
-  --
-  -----------------------------------------------------------------------------
-
-
-  -----------------------------------------------------------------------------
-  -- Process freq_gen
-  --
-  -- Purpose:
-  --   Implements the frequency generation components.
-  --
-  freq_gen: process (clock_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      freq_cnt_q <= (others => '0');
-      freq_ff_q  <= '0';
-
-    elsif clock_i'event and clock_i = '1' then
-      if clk_en_i then
-        if freq_cnt_q = 0 then
-          -- update counter from frequency register
-          freq_cnt_q <= unsigned(f_q);
-
-          -- and toggle the frequency flip-flop if enabled
-          if not all_zero(f_q) then
-            freq_ff_q <= not freq_ff_q;
-          else
-            -- if frequency setting is 0, then keep flip-flop at +1
-            freq_ff_q <= '1';
-          end if;
-
-        else
-          -- decrement frequency counter
-          freq_cnt_q <= freq_cnt_q - 1;
-
-        end if;
-      end if;
-    end if;
-  end process freq_gen;
-  --
-  -----------------------------------------------------------------------------
-
-
-  -----------------------------------------------------------------------------
-  -- Map frequency flip-flop to signed value for attenuator.
-  -----------------------------------------------------------------------------
-  freq_s <=   to_signed(+1, 2)
-            when freq_ff_q = '1' else
-              to_signed(-1, 2);
-
-
-  -----------------------------------------------------------------------------
-  -- The attenuator itself
-  -----------------------------------------------------------------------------
-  attenuator_b : entity work.sn76489_attenuator
-    port map (
-      attenuation_i => a_q,
-      factor_i      => freq_s,
-      product_o     => tone_o
-    );
-
-
-  -----------------------------------------------------------------------------
-  -- Output mapping
-  -----------------------------------------------------------------------------
-  ff_o <= freq_ff_q;
-
-end rtl;
diff --git a/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/sn76489_top.vhd b/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/sn76489_top.vhd
deleted file mode 100644
index c26d0e1a..00000000
--- a/Arcade_MiST/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/sn76489_top.vhd	
+++ /dev/null
@@ -1,200 +0,0 @@
--------------------------------------------------------------------------------
---
--- Synthesizable model of TI's SN76489AN.
---
--- $Id: sn76489_top.vhd,v 1.9 2006/02/27 20:30:10 arnim Exp $
---
--- Chip Toplevel
---
--- References:
---
---   * TI Data sheet SN76489.pdf
---     ftp://ftp.whtech.com/datasheets%20&%20manuals/SN76489.pdf
---
---   * John Kortink's article on the SN76489:
---     http://web.inter.nl.net/users/J.Kortink/home/articles/sn76489/
---
---   * Maxim's "SN76489 notes" in
---     http://www.smspower.org/maxim/docs/SN76489.txt
---
--------------------------------------------------------------------------------
---
--- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library ieee;
-use ieee.numeric_std.all;
-
-entity sn76489_top is
-
-  generic (
-    clock_div_16_g : integer := 1
-  );
-  port (
-    clock_i    : in  std_logic;
-    clock_en_i : in  std_logic;
-    res_n_i    : in  std_logic;
-    ce_n_i     : in  std_logic;
-    we_n_i     : in  std_logic;
-    ready_o    : out std_logic;
-    d_i        : in  std_logic_vector(0 to 7);
-    aout_o     : out signed(0 to 7)
-  );
-
-end sn76489_top;
-
-architecture struct of sn76489_top is
-
-  signal clk_en_s    : boolean;
-
-  signal tone1_we_s,
-         tone2_we_s,
-         tone3_we_s,
-         noise_we_s  : boolean;
-  signal r2_s        : std_logic;
-
-  signal tone1_s,
-         tone2_s,
-         tone3_s,
-         noise_s     : signed(0 to 7);
-
-  signal tone3_ff_s  : std_logic;
-
-begin
-
-  -----------------------------------------------------------------------------
-  -- Clock Divider
-  -----------------------------------------------------------------------------
-  clock_div_b : entity work.sn76489_clock_div
-    generic map (
-      clock_div_16_g => clock_div_16_g
-    )
-    port map (
-      clock_i    => clock_i,
-      clock_en_i => clock_en_i,
-      res_n_i    => res_n_i,
-      clk_en_o   => clk_en_s
-    );
-
-
-  -----------------------------------------------------------------------------
-  -- Latch Control = CPU Interface
-  -----------------------------------------------------------------------------
-  latch_ctrl_b : entity work.sn76489_latch_ctrl
-    port map (
-      clock_i    => clock_i,
-      clk_en_i   => clk_en_s,
-      res_n_i    => res_n_i,
-      ce_n_i     => ce_n_i,
-      we_n_i     => we_n_i,
-      d_i        => d_i,
-      ready_o    => ready_o,
-      tone1_we_o => tone1_we_s,
-      tone2_we_o => tone2_we_s,
-      tone3_we_o => tone3_we_s,
-      noise_we_o => noise_we_s,
-      r2_o       => r2_s
-    );
-
-
-  -----------------------------------------------------------------------------
-  -- Tone Channel 1
-  -----------------------------------------------------------------------------
-  tone1_b : entity work.sn76489_tone
-    port map (
-      clock_i  => clock_i,
-      clk_en_i => clk_en_s,
-      res_n_i  => res_n_i,
-      we_i     => tone1_we_s,
-      d_i      => d_i,
-      r2_i     => r2_s,
-      ff_o     => open,
-      tone_o   => tone1_s
-    );
-
-  -----------------------------------------------------------------------------
-  -- Tone Channel 2
-  -----------------------------------------------------------------------------
-  tone2_b : entity work.sn76489_tone
-    port map (
-      clock_i  => clock_i,
-      clk_en_i => clk_en_s,
-      res_n_i  => res_n_i,
-      we_i     => tone2_we_s,
-      d_i      => d_i,
-      r2_i     => r2_s,
-      ff_o     => open,
-      tone_o   => tone2_s
-    );
-
-  -----------------------------------------------------------------------------
-  -- Tone Channel 3
-  -----------------------------------------------------------------------------
-  tone3_b : entity work.sn76489_tone
-    port map (
-      clock_i  => clock_i,
-      clk_en_i => clk_en_s,
-      res_n_i  => res_n_i,
-      we_i     => tone3_we_s,
-      d_i      => d_i,
-      r2_i     => r2_s,
-      ff_o     => tone3_ff_s,
-      tone_o   => tone3_s
-    );
-
-  -----------------------------------------------------------------------------
-  -- Noise Channel
-  -----------------------------------------------------------------------------
-  noise_b : entity work.sn76489_noise
-    port map (
-      clock_i    => clock_i,
-      clk_en_i   => clk_en_s,
-      res_n_i    => res_n_i,
-      we_i       => noise_we_s,
-      d_i        => d_i,
-      r2_i       => r2_s,
-      tone3_ff_i => tone3_ff_s,
-      noise_o    => noise_s
-    );
-
-
-  aout_o <= tone1_s + tone2_s + tone3_s + noise_s;
-
-end struct;
diff --git a/common/Sound/sn76489/sn76489_attenuator.vhd b/common/Sound/sn76489/sn76489_attenuator.vhd
index 444064e5..a7013b2d 100644
--- a/common/Sound/sn76489/sn76489_attenuator.vhd
+++ b/common/Sound/sn76489/sn76489_attenuator.vhd
@@ -45,22 +45,24 @@
 -------------------------------------------------------------------------------
 
 library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL; 
 
 entity sn76489_attenuator is
 
   port (
     attenuation_i : in  std_logic_vector(0 to 3);
-    factor_i      : in  signed(0 to 1);
-    product_o     : out signed(0 to 7)
+    factor_i      : in  std_logic;
+    product_o     : out std_logic_vector(0 to 7)
   );
 
 end sn76489_attenuator;
 
 
 architecture rtl of sn76489_attenuator is
-
+    type     volume_t is array (natural range 0 to 15) of natural;
+    constant volume_c : volume_t := (31, 25, 20, 16, 12, 10, 8, 6, 5, 4, 3, 2, 2, 2, 1, 0);
 begin
 
   -----------------------------------------------------------------------------
@@ -78,37 +80,8 @@ begin
   --     v(0)   = 31
   --     v(n+1) = v(n) * 0.79432823
   --
-  attenuate: process (attenuation_i,
-                      factor_i)
 
-    type     volume_t is array (natural range 0 to 15) of natural;
-    constant volume_c : volume_t :=
-      (31, 25, 20, 16, 12, 10, 8, 6, 5, 4, 3, 2, 2, 2, 1, 0);
-
-    variable attenuation_v  : unsigned(attenuation_i'range);
-    variable volume_v       : signed(product_o'range);
-
-  begin
-
-    attenuation_v := unsigned(attenuation_i);
-
-    -- volume look-up table
-    volume_v := to_signed(volume_c(to_integer(attenuation_v)),
-                          product_o'length);
-
-    -- this replaces a multiplier and consumes a bit fewer
-    -- resources
-    case to_integer(factor_i) is
-      when +1 =>
-        product_o <= volume_v;
-      when -1 =>
-        product_o <= -volume_v;
-      when others =>
-        product_o <= (others => '0');
-    end case;
-
-  end process attenuate;
-  --
-  -----------------------------------------------------------------------------
+  product_o <= conv_std_logic_vector(volume_c(conv_integer(attenuation_i)), product_o'length) when factor_i = '1'
+          else (others => '0');
 
 end rtl;
diff --git a/common/Sound/sn76489/sn76489_clock_div.vhd b/common/Sound/sn76489/sn76489_clock_div.vhd
index eab86beb..65a01da2 100644
--- a/common/Sound/sn76489/sn76489_clock_div.vhd
+++ b/common/Sound/sn76489/sn76489_clock_div.vhd
@@ -45,7 +45,9 @@
 -------------------------------------------------------------------------------
 
 library ieee;
-use ieee.std_logic_1164.all;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL; 
 
 entity sn76489_clock_div is
 
@@ -68,7 +70,7 @@ use ieee.numeric_std.all;
 architecture rtl of sn76489_clock_div is
 
   signal cnt_s,
-         cnt_q  : unsigned(3 downto 0);
+         cnt_q  : std_logic_vector(3 downto 0);
 
 begin
 
@@ -109,9 +111,9 @@ begin
         clk_en_o <= true;
 
         if clock_div_16_g = 1 then
-          cnt_s  <= to_unsigned(15, cnt_q'length);
+          cnt_s  <= conv_std_logic_vector(15, cnt_q'length);
         elsif clock_div_16_g = 0 then
-          cnt_s  <= to_unsigned( 1, cnt_q'length);
+          cnt_s  <= conv_std_logic_vector( 1, cnt_q'length);
         else
           -- pragma translate_off
           assert false
diff --git a/common/Sound/sn76489/sn76489_latch_ctrl.vhd b/common/Sound/sn76489/sn76489_latch_ctrl.vhd
index 789720c2..4ebc8082 100644
--- a/common/Sound/sn76489/sn76489_latch_ctrl.vhd
+++ b/common/Sound/sn76489/sn76489_latch_ctrl.vhd
@@ -75,6 +75,7 @@ architecture rtl of sn76489_latch_ctrl is
   signal reg_q   : std_logic_vector(0 to 2);
   signal we_q    : boolean;
   signal ready_q : std_logic;
+  signal we_n_d  : std_logic;
 
 begin
 
@@ -92,6 +93,12 @@ begin
       ready_q   <= '0';
 
     elsif clock_i'event and clock_i = '1' then
+      if clk_en_i then
+        we_n_d <= we_n_i;
+      elsif we_n_i = '1' then
+        we_n_d <= '1';
+      end if;
+
       -- READY Flag Output ----------------------------------------------------
       if ready_q = '0' and we_q then
         if clk_en_i then
@@ -104,15 +111,15 @@ begin
       end if;
 
       -- Register Selection ---------------------------------------------------
-      if ce_n_i = '0' and we_n_i = '0' then
-        if clk_en_i then
+      if clk_en_i then
+        if ce_n_i = '0' and we_n_d = '1' and we_n_i = '0' then
           if d_i(0) = '1' then
             reg_q <= d_i(1 to 3);
           end if;
           we_q  <= true;
+        else
+          we_q  <= false;
         end if;
-      else
-        we_q  <= false;
       end if;
 
     end if;
diff --git a/common/Sound/sn76489/sn76489_noise.vhd b/common/Sound/sn76489/sn76489_noise.vhd
index 688bdd56..f3a75272 100644
--- a/common/Sound/sn76489/sn76489_noise.vhd
+++ b/common/Sound/sn76489/sn76489_noise.vhd
@@ -45,8 +45,9 @@
 -------------------------------------------------------------------------------
 
 library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL; 
 
 entity sn76489_noise is
 
@@ -58,26 +59,25 @@ entity sn76489_noise is
     d_i        : in  std_logic_vector(0 to 7);
     r2_i       : in  std_logic;
     tone3_ff_i : in  std_logic;
-    noise_o    : out signed(0 to 7)
+    noise_o    : out std_logic_vector(0 to 7)
   );
 
 end sn76489_noise;
 
+
 architecture rtl of sn76489_noise is
 
   signal nf_q       : std_logic_vector(0 to 1);
   signal fb_q       : std_logic;
   signal a_q        : std_logic_vector(0 to 3);
-  signal freq_cnt_q : unsigned(0 to 6);
+  signal freq_cnt_q : std_logic_vector(0 to 6);
   signal freq_ff_q  : std_logic;
 
   signal shift_source_s,
          shift_source_q    : std_logic;
   signal shift_rise_edge_s : boolean;
 
-  signal lfsr_q            : std_logic_vector(0 to 15);
-
-  signal freq_s      : signed(0 to 1);
+  signal lfsr_q            : std_logic_vector(0 to 14);
 
 begin
 
@@ -133,11 +133,11 @@ begin
           -- reload frequency counter according to NF setting
           case nf_q is
             when "00" =>
-              freq_cnt_q <= to_unsigned(16 * 2 - 1, freq_cnt_q'length);
+              freq_cnt_q <= conv_std_logic_vector(16 * 2 - 1, freq_cnt_q'length);
             when "01" =>
-              freq_cnt_q <= to_unsigned(16 * 4 - 1, freq_cnt_q'length);
+              freq_cnt_q <= conv_std_logic_vector(16 * 4 - 1, freq_cnt_q'length);
             when "10" =>
-              freq_cnt_q <= to_unsigned(16 * 8 - 1, freq_cnt_q'length);
+              freq_cnt_q <= conv_std_logic_vector(16 * 8 - 1, freq_cnt_q'length);
             when others =>
               null;
           end case;
@@ -202,9 +202,9 @@ begin
   lfsr: process (clock_i, res_n_i)
 
     function lfsr_tapped_f(lfsr : in std_logic_vector) return std_logic is
-      constant tapped_bits_c : std_logic_vector(0 to 15)
+      constant tapped_bits_c : std_logic_vector(0 to 14)
         -- tapped bits are 0, 2, 15
-        := "1010000000000001";
+        := "110000000000000";
       variable parity_v : std_logic;
     begin
       parity_v := '0';
@@ -253,17 +253,6 @@ begin
       end if;
     end if;
   end process lfsr;
-  --
-  -----------------------------------------------------------------------------
-
-
-  -----------------------------------------------------------------------------
-  -- Map output of LFSR to signed value for attenuator.
-  -----------------------------------------------------------------------------
-  freq_s <=   to_signed(+1, 2)
-            when lfsr_q(0) = '1' else
-              to_signed( 0, 2);
-
 
   -----------------------------------------------------------------------------
   -- The attenuator itself
@@ -271,7 +260,7 @@ begin
   attenuator_b : entity work.sn76489_attenuator
     port map (
       attenuation_i => a_q,
-      factor_i      => freq_s,
+      factor_i      => lfsr_q(0),
       product_o     => noise_o
     );
 
diff --git a/common/Sound/sn76489/sn76489_tone.vhd b/common/Sound/sn76489/sn76489_tone.vhd
index 3658efcc..5edc8a45 100644
--- a/common/Sound/sn76489/sn76489_tone.vhd
+++ b/common/Sound/sn76489/sn76489_tone.vhd
@@ -45,8 +45,9 @@
 -------------------------------------------------------------------------------
 
 library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL; 
 
 entity sn76489_tone is
 
@@ -58,7 +59,7 @@ entity sn76489_tone is
     d_i      : in  std_logic_vector(0 to 7);
     r2_i     : in  std_logic;
     ff_o     : out std_logic;
-    tone_o   : out signed(0 to 7)
+    tone_o   : out std_logic_vector(0 to 7)
   );
 
 end sn76489_tone;
@@ -67,10 +68,9 @@ architecture rtl of sn76489_tone is
 
   signal f_q        : std_logic_vector(0 to 9);
   signal a_q        : std_logic_vector(0 to 3);
-  signal freq_cnt_q : unsigned(0 to 9);
+  signal freq_cnt_q : std_logic_vector(0 to 9);
   signal freq_ff_q  : std_logic;
-
-  signal freq_s     : signed(0 to 1);
+  signal output_ff  : std_logic;
 
   function all_zero(a : in std_logic_vector) return boolean is
     variable result_v : boolean;
@@ -134,21 +134,25 @@ begin
     if res_n_i = '0' then
       freq_cnt_q <= (others => '0');
       freq_ff_q  <= '0';
+      output_ff <= '0';
 
     elsif clock_i'event and clock_i = '1' then
       if clk_en_i then
-        if freq_cnt_q = 0 then
+        if freq_cnt_q = 1 then
           -- update counter from frequency register
-          freq_cnt_q <= unsigned(f_q);
+          freq_cnt_q <= f_q;
 
           -- and toggle the frequency flip-flop if enabled
-          if not all_zero(f_q) then
+          if (f_q > 5) then
             freq_ff_q <= not freq_ff_q;
           else
             -- if frequency setting is 0, then keep flip-flop at +1
             freq_ff_q <= '1';
           end if;
 
+          -- either way toggle the output_ff - this is used to clock noise
+          output_ff <= not output_ff;
+
         else
           -- decrement frequency counter
           freq_cnt_q <= freq_cnt_q - 1;
@@ -157,16 +161,6 @@ begin
       end if;
     end if;
   end process freq_gen;
-  --
-  -----------------------------------------------------------------------------
-
-
-  -----------------------------------------------------------------------------
-  -- Map frequency flip-flop to signed value for attenuator.
-  -----------------------------------------------------------------------------
-  freq_s <=   to_signed(+1, 2)
-            when freq_ff_q = '1' else
-              to_signed(-1, 2);
 
 
   -----------------------------------------------------------------------------
@@ -175,7 +169,7 @@ begin
   attenuator_b : entity work.sn76489_attenuator
     port map (
       attenuation_i => a_q,
-      factor_i      => freq_s,
+      factor_i      => freq_ff_q,
       product_o     => tone_o
     );
 
@@ -183,6 +177,6 @@ begin
   -----------------------------------------------------------------------------
   -- Output mapping
   -----------------------------------------------------------------------------
-  ff_o <= freq_ff_q;
+  ff_o <= output_ff;
 
 end rtl;
diff --git a/common/Sound/sn76489/sn76489_top.vhd b/common/Sound/sn76489/sn76489_top.vhd
index c26d0e1a..de3f34a2 100644
--- a/common/Sound/sn76489/sn76489_top.vhd
+++ b/common/Sound/sn76489/sn76489_top.vhd
@@ -56,11 +56,9 @@
 -------------------------------------------------------------------------------
 
 library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library ieee;
-use ieee.numeric_std.all;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL; 
 
 entity sn76489_top is
 
@@ -75,11 +73,15 @@ entity sn76489_top is
     we_n_i     : in  std_logic;
     ready_o    : out std_logic;
     d_i        : in  std_logic_vector(0 to 7);
-    aout_o     : out signed(0 to 7)
+    aout_o     : out std_logic_vector(0 to 7)
   );
 
 end sn76489_top;
 
+
+library ieee;
+use ieee.numeric_std.all;
+
 architecture struct of sn76489_top is
 
   signal clk_en_s    : boolean;
@@ -93,7 +95,7 @@ architecture struct of sn76489_top is
   signal tone1_s,
          tone2_s,
          tone3_s,
-         noise_s     : signed(0 to 7);
+         noise_s     : std_logic_vector(0 to 7);
 
   signal tone3_ff_s  : std_logic;