diff --git a/Arcade_MiST/NinjaKun_MiST/NinjaKun_MiST.qpf b/Arcade_MiST/NinjaKun_MiST/NinjaKun_MiST.qpf
new file mode 100644
index 00000000..2c69d2f2
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/NinjaKun_MiST.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 20:17:38 December 19, 2019
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "20:17:38 December 19, 2019"
+
+# Revisions
+
+PROJECT_REVISION = "NinjaKun_MiST"
\ No newline at end of file
diff --git a/Arcade_MiST/NinjaKun_MiST/NinjaKun_MiST.qsf b/Arcade_MiST/NinjaKun_MiST/NinjaKun_MiST.qsf
new file mode 100644
index 00000000..e83daba9
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/NinjaKun_MiST.qsf
@@ -0,0 +1,265 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 19:13:36 October 04, 2019
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# NinjaKun_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.2
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:48:06 MAY 24,2017"
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_54 -to CLOCK_27
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_90 -to SPI_SS4
+set_location_assignment PIN_13 -to CONF_DATA0
+set_location_assignment PIN_49 -to SDRAM_A[0]
+set_location_assignment PIN_44 -to SDRAM_A[1]
+set_location_assignment PIN_42 -to SDRAM_A[2]
+set_location_assignment PIN_39 -to SDRAM_A[3]
+set_location_assignment PIN_4 -to SDRAM_A[4]
+set_location_assignment PIN_6 -to SDRAM_A[5]
+set_location_assignment PIN_8 -to SDRAM_A[6]
+set_location_assignment PIN_10 -to SDRAM_A[7]
+set_location_assignment PIN_11 -to SDRAM_A[8]
+set_location_assignment PIN_28 -to SDRAM_A[9]
+set_location_assignment PIN_50 -to SDRAM_A[10]
+set_location_assignment PIN_30 -to SDRAM_A[11]
+set_location_assignment PIN_32 -to SDRAM_A[12]
+set_location_assignment PIN_83 -to SDRAM_DQ[0]
+set_location_assignment PIN_79 -to SDRAM_DQ[1]
+set_location_assignment PIN_77 -to SDRAM_DQ[2]
+set_location_assignment PIN_76 -to SDRAM_DQ[3]
+set_location_assignment PIN_72 -to SDRAM_DQ[4]
+set_location_assignment PIN_71 -to SDRAM_DQ[5]
+set_location_assignment PIN_69 -to SDRAM_DQ[6]
+set_location_assignment PIN_68 -to SDRAM_DQ[7]
+set_location_assignment PIN_86 -to SDRAM_DQ[8]
+set_location_assignment PIN_87 -to SDRAM_DQ[9]
+set_location_assignment PIN_98 -to SDRAM_DQ[10]
+set_location_assignment PIN_99 -to SDRAM_DQ[11]
+set_location_assignment PIN_100 -to SDRAM_DQ[12]
+set_location_assignment PIN_101 -to SDRAM_DQ[13]
+set_location_assignment PIN_103 -to SDRAM_DQ[14]
+set_location_assignment PIN_104 -to SDRAM_DQ[15]
+set_location_assignment PIN_58 -to SDRAM_BA[0]
+set_location_assignment PIN_51 -to SDRAM_BA[1]
+set_location_assignment PIN_85 -to SDRAM_DQMH
+set_location_assignment PIN_67 -to SDRAM_DQML
+set_location_assignment PIN_60 -to SDRAM_nRAS
+set_location_assignment PIN_64 -to SDRAM_nCAS
+set_location_assignment PIN_66 -to SDRAM_nWE
+set_location_assignment PIN_59 -to SDRAM_nCS
+set_location_assignment PIN_33 -to SDRAM_CKE
+set_location_assignment PIN_43 -to SDRAM_CLK
+set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
+
+
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+set_global_assignment -name TOP_LEVEL_ENTITY NinjaKun_MiST
+set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
+set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+
+# SignalTap II Assignments
+# ========================
+set_global_assignment -name ENABLE_SIGNALTAP OFF
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/druaga.stp
+
+# Power Estimation Assignments
+# ============================
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# Advanced I/O Timing Assignments
+# ===============================
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+# -----------------------------------
+# start ENTITY(TheTowerofDruaga_mist)
+
+ # start DESIGN_PARTITION(Top)
+ # ---------------------------
+
+ # Incremental Compilation Assignments
+ # ===================================
+
+ # end DESIGN_PARTITION(Top)
+ # -------------------------
+
+# end ENTITY(TheTowerofDruaga_mist)
+# ---------------------------------
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/NinjaKun_MiST.sv
+set_global_assignment -name VERILOG_FILE rtl/ninjakun_top.v
+set_global_assignment -name VERILOG_FILE rtl/ninjakun_main.v
+set_global_assignment -name VERILOG_FILE rtl/ninjakun_io_video.v
+set_global_assignment -name VERILOG_FILE rtl/ninjakun_video.v
+set_global_assignment -name VERILOG_FILE rtl/hvgen.v
+set_global_assignment -name VERILOG_FILE rtl/ninjakun_bg.v
+set_global_assignment -name VERILOG_FILE rtl/ninjakun_fg.v
+set_global_assignment -name VERILOG_FILE rtl/ninjakun_sp.v
+set_global_assignment -name VERILOG_FILE rtl/ninjakun_psg.v
+set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd
+set_global_assignment -name VERILOG_FILE rtl/ninjakun_cpumux.v
+set_global_assignment -name VERILOG_FILE rtl/ninjakun_irqgen.v
+set_global_assignment -name VERILOG_FILE rtl/ninjakun_clkgen.v
+set_global_assignment -name VERILOG_FILE rtl/ninjakun_input.v
+set_global_assignment -name VERILOG_FILE rtl/ninjakun_sadec.v
+set_global_assignment -name VERILOG_FILE rtl/ninjakun_adec.v
+set_global_assignment -name VERILOG_FILE rtl/dataselector_3D_8B.v
+set_global_assignment -name VERILOG_FILE rtl/dataselector_4D_9B.v
+set_global_assignment -name VERILOG_FILE rtl/dataselector_5D_8B.v
+set_global_assignment -name VHDL_FILE rtl/rom/bg4_rom.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/bg3_rom.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/bg2_rom.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/bg1_rom.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/fg4_rom.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/fg3_rom.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/fg2_rom.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/fg1_rom.vhd
+set_global_assignment -name VERILOG_FILE rtl/z80ip.v
+set_global_assignment -name VHDL_FILE rtl/cpu/T80s.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
+set_global_assignment -name VERILOG_FILE rtl/pll.v
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
+set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
+set_global_assignment -name VERILOG_FILE rtl/mems.v
+set_global_assignment -name VHDL_FILE rtl/dpram_1r1w.vhd
+set_global_assignment -name VHDL_FILE rtl/dpram.vhd
+set_global_assignment -name VERILOG_FILE rtl/DPRAM1024.v
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/NinjaKun_MiST/Snapshot/NINJAKUN.ROM b/Arcade_MiST/NinjaKun_MiST/Snapshot/NINJAKUN.ROM
new file mode 100644
index 00000000..44fbd53c
Binary files /dev/null and b/Arcade_MiST/NinjaKun_MiST/Snapshot/NINJAKUN.ROM differ
diff --git a/Arcade_MiST/NinjaKun_MiST/Snapshot/NinjaKun_MiST.rbf b/Arcade_MiST/NinjaKun_MiST/Snapshot/NinjaKun_MiST.rbf
new file mode 100644
index 00000000..56878c70
Binary files /dev/null and b/Arcade_MiST/NinjaKun_MiST/Snapshot/NinjaKun_MiST.rbf differ
diff --git a/Arcade_MiST/NinjaKun_MiST/clean.bat b/Arcade_MiST/NinjaKun_MiST/clean.bat
new file mode 100644
index 00000000..b4ae3f11
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/clean.bat
@@ -0,0 +1,41 @@
+@echo off
+del /s *.bak
+del /s *.orig
+del /s *.rej
+del /s *~
+rmdir /s /q db
+rmdir /s /q incremental_db
+rmdir /s /q output_files
+rmdir /s /q simulation
+rmdir /s /q greybox_tmp
+rmdir /s /q hc_output
+rmdir /s /q .qsys_edit
+rmdir /s /q hps_isw_handoff
+rmdir /s /q sys\.qsys_edit
+rmdir /s /q sys\vip
+cd sys
+for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
+cd ..
+for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
+del build_id.v
+del c5_pin_model_dump.txt
+del PLLJ_PLLSPE_INFO.txt
+del /s *.qws
+del /s *.ppf
+del /s *.ddb
+del /s *.csv
+del /s *.cmp
+del /s *.sip
+del /s *.spd
+del /s *.bsf
+del /s *.f
+del /s *.sopcinfo
+del /s *.xml
+del *.cdf
+del /s new_rtl_netlist
+del /s old_rtl_netlist
+del sys\vip.qip
+del sys\sysmem.qip
+del sys\sdram.sv
+del sys\ddram.sv
+pause
diff --git a/Arcade_MiST/NinjaKun_MiST/mister/Arcade-NinjaKun.sv b/Arcade_MiST/NinjaKun_MiST/mister/Arcade-NinjaKun.sv
new file mode 100644
index 00000000..ac109fb1
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/mister/Arcade-NinjaKun.sv
@@ -0,0 +1,358 @@
+//============================================================================
+// Arcade: Ninja-Kun -- Majyo no Bouken --
+//
+// Original implimentation and port to MiSTer by MiSTer-X 2019
+//============================================================================
+
+module emu
+(
+ //Master input clock
+ input CLK_50M,
+
+ //Async reset from top-level module.
+ //Can be used as initial reset.
+ input RESET,
+
+ //Must be passed to hps_io module
+ inout [44:0] HPS_BUS,
+
+ //Base video clock. Usually equals to CLK_SYS.
+ output VGA_CLK,
+
+ //Multiple resolutions are supported using different VGA_CE rates.
+ //Must be based on CLK_VIDEO
+ output VGA_CE,
+
+ output [7:0] VGA_R,
+ output [7:0] VGA_G,
+ output [7:0] VGA_B,
+ output VGA_HS,
+ output VGA_VS,
+ output VGA_DE, // = ~(VBlank | HBlank)
+
+ //Base video clock. Usually equals to CLK_SYS.
+ output HDMI_CLK,
+
+ //Multiple resolutions are supported using different HDMI_CE rates.
+ //Must be based on CLK_VIDEO
+ output HDMI_CE,
+
+ output [7:0] HDMI_R,
+ output [7:0] HDMI_G,
+ output [7:0] HDMI_B,
+ output HDMI_HS,
+ output HDMI_VS,
+ output HDMI_DE, // = ~(VBlank | HBlank)
+ output [1:0] HDMI_SL, // scanlines fx
+
+ //Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
+ output [7:0] HDMI_ARX,
+ output [7:0] HDMI_ARY,
+
+ output LED_USER, // 1 - ON, 0 - OFF.
+
+ // b[1]: 0 - LED status is system status OR'd with b[0]
+ // 1 - LED status is controled solely by b[0]
+ // hint: supply 2'b00 to let the system control the LED.
+ output [1:0] LED_POWER,
+ output [1:0] LED_DISK,
+
+ output [15:0] AUDIO_L,
+ output [15:0] AUDIO_R,
+ output AUDIO_S // 1 - signed audio samples, 0 - unsigned
+);
+
+assign LED_USER = ioctl_download;
+assign LED_DISK = 0;
+assign LED_POWER = 0;
+
+assign HDMI_ARX = status[1] ? 8'd16 : 8'd4;
+assign HDMI_ARY = status[1] ? 8'd9 : 8'd3;
+
+`include "build_id.v"
+localparam CONF_STR = {
+ "A.NinjaKun;;",
+
+ "F,rom;", // allow loading of alternate ROMs
+ "-;",
+ "O1,Aspect Ratio,Original,Wide;",
+ "-;",
+ "O8,Difficulty,Normal,Hard;",
+ "O9A,Lives,4,3,2,5;",
+ "OB,1st Extra,30000,40000;",
+ "OCD,2nd Extra (Every),50000,70000,90000,None;",
+ "OF,Allow Continue,No,Yes;",
+ "OG,Free Play,No,Yes;",
+ "OH,Endless(If Free Play),No,Yes;",
+ "OE,Demo Sound,Off,On;",
+ "OI,Name Letters,8,3;",
+ "-;",
+ "R0,Reset;",
+ "J1,Shot,Jump,Start 1P,Start 2P,Coin;",
+ "V,v",`BUILD_DATE
+};
+
+
+`define CABINET 1'b0 // Upright=0,Table=1
+`define DIFFICULTY ~status[8] // Hard=0,Normal=1
+`define LIVES ~status[10:9] // 00=5,01=2,10=3,11=4
+`define EXTEND1ST ~status[11] // 40000=0,30000=1
+`define EXTEND2ND ~status[13:12] // None,30000,50000,70000
+`define DEMOSOUND ~status[14] // On=0,Off=1
+
+`define ALLOW_CONTINUE ~status[15] // Yes=0,NO=1
+`define FREEPLAY ~status[16] // Yes=0,No=1
+`define ENDLESS ~status[17] // Yes=0,No=1 (If FreePlay)
+`define NAMELETTERS ~status[18] // 3Letters=0,8Letters=1
+`define COINAGE 3'b111 // 1C/1C
+
+
+wire bCabinet = `CABINET; // (upright only)
+
+
+//////////////////// CLOCKS ///////////////////
+
+wire clk_hdmi;
+wire clk_49M;
+wire clk_sys = clk_49M;
+
+pll pll
+(
+ .rst(0),
+ .refclk(CLK_50M),
+ .outclk_0(clk_49M),
+ .outclk_1(clk_hdmi)
+);
+
+///////////////////////////////////////////////////
+
+wire [31:0] status;
+wire [1:0] buttons;
+wire forced_scandoubler;
+
+wire ioctl_download;
+wire ioctl_wr;
+wire [24:0] ioctl_addr;
+wire [7:0] ioctl_dout;
+
+wire [10:0] ps2_key;
+wire [15:0] joystk1, joystk2;
+
+hps_io #(.STRLEN($size(CONF_STR)>>3)) hps_io
+(
+ .clk_sys(clk_sys),
+ .HPS_BUS(HPS_BUS),
+
+ .conf_str(CONF_STR),
+
+ .buttons(buttons),
+ .status(status),
+ .forced_scandoubler(forced_scandoubler),
+
+ .ioctl_download(ioctl_download),
+ .ioctl_wr(ioctl_wr),
+ .ioctl_addr(ioctl_addr),
+ .ioctl_dout(ioctl_dout),
+
+ .joystick_0(joystk1),
+ .joystick_1(joystk2),
+ .ps2_key(ps2_key)
+);
+
+wire pressed = ps2_key[9];
+wire [8:0] code = ps2_key[8:0];
+always @(posedge clk_sys) begin
+ reg old_state;
+ old_state <= ps2_key[10];
+
+ if(old_state != ps2_key[10]) begin
+ casex(code)
+ 'hX75: btn_up <= pressed; // up
+ 'hX72: btn_down <= pressed; // down
+ 'hX6B: btn_left <= pressed; // left
+ 'hX74: btn_right <= pressed; // right
+ 'h029: btn_trig1 <= pressed; // space
+ 'h014: btn_trig2 <= pressed; // ctrl
+ 'h005: btn_one_player <= pressed; // F1
+ 'h006: btn_two_players <= pressed; // F2
+
+ // JPAC/IPAC/MAME Style Codes
+ 'h016: btn_start_1 <= pressed; // 1
+ 'h01E: btn_start_2 <= pressed; // 2
+ 'h02E: btn_coin_1 <= pressed; // 5
+ 'h036: btn_coin_2 <= pressed; // 6
+ 'h02D: btn_up_2 <= pressed; // R
+ 'h02B: btn_down_2 <= pressed; // F
+ 'h023: btn_left_2 <= pressed; // D
+ 'h034: btn_right_2 <= pressed; // G
+ 'h01C: btn_trig1_2 <= pressed; // A
+ 'h01B: btn_trig2_2 <= pressed; // S
+ endcase
+ end
+end
+
+reg btn_up = 0;
+reg btn_down = 0;
+reg btn_right = 0;
+reg btn_left = 0;
+reg btn_trig1 = 0;
+reg btn_trig2 = 0;
+reg btn_one_player = 0;
+reg btn_two_players = 0;
+
+reg btn_start_1 = 0;
+reg btn_start_2 = 0;
+reg btn_coin_1 = 0;
+reg btn_coin_2 = 0;
+reg btn_up_2 = 0;
+reg btn_down_2 = 0;
+reg btn_left_2 = 0;
+reg btn_right_2 = 0;
+reg btn_trig1_2 = 0;
+reg btn_trig2_2 = 0;
+
+
+wire m_up2 = btn_up_2 | joystk2[3];
+wire m_down2 = btn_down_2 | joystk2[2];
+wire m_left2 = btn_left_2 | joystk2[1];
+wire m_right2 = btn_right_2 | joystk2[0];
+wire m_trig21 = btn_trig1_2 | joystk2[4];
+wire m_trig22 = btn_trig2_2 | joystk2[5];
+
+wire m_start1 = btn_one_player | joystk1[6] | joystk2[6] | btn_start_1;
+wire m_start2 = btn_two_players | joystk1[7] | joystk2[7] | btn_start_2;
+
+wire m_up1 = btn_up | joystk1[3] | (bCabinet ? 1'b0 : m_up2);
+wire m_down1 = btn_down | joystk1[2] | (bCabinet ? 1'b0 : m_down2);
+wire m_left1 = btn_left | joystk1[1] | (bCabinet ? 1'b0 : m_left2);
+wire m_right1 = btn_right | joystk1[0] | (bCabinet ? 1'b0 : m_right2);
+wire m_trig11 = btn_trig1 | joystk1[4] | (bCabinet ? 1'b0 : m_trig21);
+wire m_trig12 = btn_trig2 | joystk1[5] | (bCabinet ? 1'b0 : m_trig22);
+
+wire m_coin1 = btn_one_player | btn_coin_1 | joystk1[8];
+wire m_coin2 = btn_two_players| btn_coin_2 | joystk2[8];
+wire m_coin = m_coin1|m_coin2;
+
+
+///////////////////////////////////////////////////
+
+wire hblank, vblank;
+wire ce_vid;
+wire hs, vs;
+wire [3:0] r,g,b;
+
+reg ce_pix;
+always @(posedge clk_hdmi) begin
+ reg old_clk;
+ old_clk <= ce_vid;
+ ce_pix <= old_clk & ~ce_vid;
+end
+
+arcade_rotate_fx #(256,192,12) arcade_video
+(
+ .*,
+
+ .clk_video(clk_hdmi),
+
+ .RGB_in({r,g,b}),
+ .HBlank(hblank),
+ .VBlank(vblank),
+ .HSync(~hs),
+ .VSync(~vs),
+
+ .fx(0),
+ .no_rotate(1'b1)
+);
+
+wire PCLK;
+wire [8:0] HPOS,VPOS;
+wire [11:0] POUT;
+HVGEN hvgen
+(
+ .HPOS(HPOS),.VPOS(VPOS),.PCLK(PCLK),.iRGB(POUT),
+ .oRGB({b,g,r}),.HBLK(hblank),.VBLK(vblank),.HSYN(hs),.VSYN(vs)
+);
+assign ce_vid = PCLK;
+
+
+wire [15:0] AOUT;
+assign AUDIO_L = AOUT;
+assign AUDIO_R = AOUT;
+assign AUDIO_S = 1'b0; // unsigned
+
+
+///////////////////////////////////////////////////
+
+wire [7:0] iDSW1 = {`DIFFICULTY,`DEMOSOUND,`EXTEND2ND,`EXTEND1ST,`LIVES, `CABINET}; // 8'b1_0_01_1_10_0;
+wire [7:0] iDSW2 = {`ENDLESS,`FREEPLAY,1'b0,`ALLOW_CONTINUE,`NAMELETTERS,`COINAGE}; // 8'b1_1_0_0_1_111;
+
+wire [7:0] iCTR1 = ~{ 2'b11, m_start1, 1'b0, m_trig11, m_trig12, m_right1, m_left1 };
+wire [7:0] iCTR2 = ~{ ~m_coin,1'b1, m_start2, 1'b0, m_trig21, m_trig22, m_right2, m_left2 };
+
+wire iRST = RESET | status[0] | buttons[1] | ioctl_download;
+
+wire [7:0] oPIX;
+assign POUT = {{oPIX[7:6],oPIX[1:0]},{oPIX[5:4],oPIX[1:0]},{oPIX[3:2],oPIX[1:0]}};
+
+
+FPGA_NINJAKUN GameCore
+(
+ .RESET(iRST),.MCLK(clk_49M),
+
+ .CTR1(iCTR1),.CTR2(iCTR2),
+ .DSW1(iDSW1),.DSW2(iDSW2),
+
+ .PH(HPOS),.PV(VPOS),
+ .PCLK(PCLK),.POUT(oPIX),
+ .SNDOUT(AOUT),
+
+ .ROMCL(clk_sys),.ROMAD(ioctl_addr),.ROMDT(ioctl_dout),.ROMEN(ioctl_wr)
+);
+
+endmodule
+
+
+module HVGEN
+(
+ output [8:0] HPOS,
+ output [8:0] VPOS,
+ input PCLK,
+ input [11:0] iRGB,
+
+ output reg [11:0] oRGB,
+ output reg HBLK = 1,
+ output reg VBLK = 1,
+ output reg HSYN = 1,
+ output reg VSYN = 1
+);
+
+reg [8:0] hcnt = 0;
+reg [8:0] vcnt = 0;
+
+assign HPOS = hcnt-16;
+assign VPOS = vcnt-16;
+
+always @(posedge PCLK) begin
+ case (hcnt)
+ 15: begin HBLK <= 0; hcnt <= hcnt+1; end
+ 272: begin HBLK <= 1; hcnt <= hcnt+1; end
+ 311: begin HSYN <= 0; hcnt <= hcnt+1; end
+ 342: begin HSYN <= 1; hcnt <= 471; end
+ 511: begin hcnt <= 0;
+ case (vcnt)
+ 15: begin VBLK <= 0; vcnt <= vcnt+1; end
+ 207: begin VBLK <= 1; vcnt <= vcnt+1; end
+ 226: begin VSYN <= 0; vcnt <= vcnt+1; end
+ 233: begin VSYN <= 1; vcnt <= 483; end
+ 511: begin vcnt <= 0; end
+ default: vcnt <= vcnt+1;
+ endcase
+ end
+ default: hcnt <= hcnt+1;
+ endcase
+ oRGB <= (HBLK|VBLK) ? 12'h0 : iRGB;
+end
+
+endmodule
+
+
diff --git a/Arcade_MiST/NinjaKun_MiST/mister/LICENSE b/Arcade_MiST/NinjaKun_MiST/mister/LICENSE
new file mode 100644
index 00000000..94a9ed02
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/mister/LICENSE
@@ -0,0 +1,674 @@
+ GNU GENERAL PUBLIC LICENSE
+ Version 3, 29 June 2007
+
+ Copyright (C) 2007 Free Software Foundation, Inc.
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+ of this license document, but changing it is not allowed.
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diff --git a/Arcade_MiST/NinjaKun_MiST/mister/README.txt b/Arcade_MiST/NinjaKun_MiST/mister/README.txt
new file mode 100644
index 00000000..1dca0244
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/mister/README.txt
@@ -0,0 +1,74 @@
+---------------------------------------------------------------------------------
+--
+-- Arcade: Ninja-Kun port to MiSTer by MiSTer-X
+-- 20 October 2019
+--
+---------------------------------------------------------------------------------
+-- FPGA Ninja-Kun for Spartan-6
+------------------------------------------------
+-- Copyright (c) 2011 MiSTer-X
+---------------------------------------------------------------------------------
+-- T80/T80s - Version : 0242
+-----------------------------
+-- Z80 compatible microprocessor core
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+---------------------------------------------------------------------------------
+-- YM2149 (AY-3-8910)
+-- Copyright (c) MikeJ - Jan 2005
+---------------------------------------------------------------------------------
+--
+--
+-- Keyboard inputs :
+--
+-- F2 : Coin + Start 2 players
+-- F1 : Coin + Start 1 player
+-- UP,DOWN,LEFT,RIGHT arrows : Movements
+-- SPACE : Shot
+-- CTRL : Jump
+--
+-- MAME/IPAC/JPAC Style Keyboard inputs:
+-- 5 : Coin 1
+-- 6 : Coin 2
+-- 1 : Start 1 Player
+-- 2 : Start 2 Players
+-- R,F,D,G : Player 2 Movements
+-- A : Player 2 Shot
+-- S : Player 2 Jump
+--
+-- Joystick support.
+--
+--
+-- known bug: Sometimes BG screen glitches.
+--
+---------------------------------------------------------------------------------
+-- 23 October 2019
+---------------------------------------------------------------------------------
+-- FIXED: Analog video is shifted to right.
+---------------------------------------------------------------------------------
+
+ *** Attention ***
+
+ROM is not included. In order to use this arcade, you need to provide a correct ROM file.
+
+Find this zip file somewhere. You need to find the file exactly as required.
+Do not rename other zip files even if they also represent the same game - they are not compatible!
+The name of zip is taken from M.A.M.E. project, so you can get more info about
+hashes and contained files there.
+
+To generate the ROM using Windows:
+1) Copy the zip into "releases" directory
+2) Execute bat file - it will show the name of zip file containing required files.
+3) Put required zip into the same directory and execute the bat again.
+4) If everything will go without errors or warnings, then you will get the a.*.rom file.
+5) Copy generated a.*.rom into root of SD card along with the Arcade-*.rbf file
+
+To generate the ROM using Linux/MacOS:
+1) Copy the zip into "releases" directory
+2) Execute build_rom.sh
+3) Copy generated a.*.rom into root of SD card along with the Arcade-*.rbf file
+
+To generate the ROM using MiSTer:
+1) scp "releases" directory along with the zip file onto MiSTer:/media/fat/
+2) Using OSD execute build_rom.sh
+3) Copy generated a.*.rom into root of SD card along with the Arcade-*.rbf file
+
diff --git a/Arcade_MiST/NinjaKun_MiST/mister/build_rom.bat b/Arcade_MiST/NinjaKun_MiST/mister/build_rom.bat
new file mode 100644
index 00000000..4237b880
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/mister/build_rom.bat
@@ -0,0 +1,45 @@
+@powershell -NoProfile -ExecutionPolicy Unrestricted "$s=[scriptblock]::create((gc \"%~f0\"|?{$_.readcount -gt 1})-join\"`n\");&$s" %*&goto:eof
+#==============================================================
+$zip="ninjakun.zip"
+
+$ifiles=`
+ "ninja-6.7n","ninja-7.7p","ninja-8.7s","ninja-9.7t",`
+ "ninja-10.2c","ninja-11.2d","ninja-12.4c","ninja-13.4d",`
+ "ninja-1.7a","ninja-2.7b","ninja-3.7d","ninja-4.7e",`
+ "ninja-5.7h","ninja-2.7b","ninja-3.7d","ninja-4.7e"
+
+$ofile="a.ninjakun.rom"
+$ofileMd5sumValid="99e80f22f7a77cf1d574ce89486b385f"
+
+if (!(Test-Path "./$zip")) {
+ echo "Error: Cannot find $zip file."
+ echo ""
+ echo "Put $zip into the same directory."
+}
+else {
+ Expand-Archive -Path "./$zip" -Destination ./tmp/ -Force
+
+ cd tmp
+ Get-Content $ifiles -Enc Byte -Read 512 | Set-Content "../$ofile" -Enc Byte
+ cd ..
+ Remove-Item ./tmp -Recurse -Force
+
+ $ofileMD5sumCurrent=(Get-FileHash -Algorithm md5 "./$ofile").Hash.toLower()
+ if ($ofileMD5sumCurrent -ne $ofileMd5sumValid) {
+ echo "Expected checksum: $ofileMd5sumValid"
+ echo " Actual checksum: $ofileMd5sumCurrent"
+ echo ""
+ echo "Error: Generated $ofile is invalid."
+ echo ""
+ echo "This is more likely due to incorrect $zip content."
+ }
+ else {
+ echo "Checksum verification passed."
+ echo ""
+ echo "Copy $ofile into root of SD card along with the rbf file."
+ }
+}
+echo ""
+echo ""
+pause
+
diff --git a/Arcade_MiST/NinjaKun_MiST/mister/build_rom.ini b/Arcade_MiST/NinjaKun_MiST/mister/build_rom.ini
new file mode 100644
index 00000000..b6428ae3
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/mister/build_rom.ini
@@ -0,0 +1,4 @@
+zip=ninjakun.zip
+ifiles=(ninja-6.7n ninja-7.7p ninja-8.7s ninja-9.7t ninja-10.2c ninja-11.2d ninja-12.4c ninja-13.4d ninja-1.7a ninja-2.7b ninja-3.7d ninja-4.7e ninja-5.7h ninja-2.7b ninja-3.7d ninja-4.7e)
+ofile=a.ninjakun.rom
+ofileMd5sumValid=99e80f22f7a77cf1d574ce89486b385f
diff --git a/Arcade_MiST/NinjaKun_MiST/mister/build_rom.sh b/Arcade_MiST/NinjaKun_MiST/mister/build_rom.sh
new file mode 100644
index 00000000..2b1f85f7
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/mister/build_rom.sh
@@ -0,0 +1,100 @@
+#!/bin/bash
+
+exit_with_error() {
+ echo -e "\nERROR:\n${1}\n"
+ exit 1
+}
+
+check_dependencies() {
+ if [[ $OSTYPE == darwin* ]]; then
+ for j in unzip md5 cat cut; do
+ command -v ${j} > /dev/null 2>&1 || exit_with_error "This script requires\n${j}"
+ done
+ else
+ for j in unzip md5sum cat cut; do
+ command -v ${j} > /dev/null 2>&1 || exit_with_error "This script requires\n${j}"
+ done
+ fi
+}
+
+check_permissions () {
+ if [ ! -w ${BASEDIR} ]; then
+ exit_with_error "Cannot write to\n${BASEDIR}"
+ fi
+}
+
+read_ini () {
+ if [ ! -f ${BASEDIR}/build_rom.ini ]; then
+ exit_with_error "Missing build_rom.ini"
+ else
+ source ${BASEDIR}/build_rom.ini
+ fi
+}
+
+uncompress_zip() {
+ if [ -f ${BASEDIR}/${zip} ]; then
+ tmpdir=tmp.`date +%Y%m%d%H%M%S%s`
+ unzip -qq -d ${BASEDIR}/${tmpdir}/ ${BASEDIR}/${zip}
+ if [ $? != 0 ] ; then
+ rm -rf ${BASEDIR}/$tmpdir
+ exit_with_error "Something went wrong\nwhen extracting\n${zip}"
+ fi
+ else
+ exit_with_error "Cannot find ${zip}"
+ fi
+}
+
+generate_rom() {
+ for i in "${ifiles[@]}"; do
+ # ensure provided zip contains required files
+ if [ ! -f "${BASEDIR}/${tmpdir}/${i}" ]; then
+ rm -rf ${BASEDIR}/$tmpdir
+ exit_with_error "Provided ${zip}\nis missing required file:\n\n${i}"
+ else
+ cat ${BASEDIR}/${tmpdir}/${i} >> ${BASEDIR}/${tmpdir}/${ofile}
+ fi
+ done
+}
+
+validate_rom() {
+
+ if [[ $OSTYPE == darwin* ]]; then
+ ofileMd5sumCurrent=$(md5 -r ${BASEDIR}/${tmpdir}/${ofile}|cut -f 1 -d " ")
+ else
+ ofileMd5sumCurrent=$(md5sum ${BASEDIR}/${tmpdir}/${ofile}|cut -f 1 -d " ")
+ fi
+
+ if [[ "${ofileMd5sumValid}" != "${ofileMd5sumCurrent}" ]]; then
+ echo -e "\nExpected checksum:\n${ofileMd5sumValid}"
+ echo -e "Actual checksum:\n${ofileMd5sumCurrent}"
+ mv ${BASEDIR}/${tmpdir}/${ofile} .
+ rm -rf ${BASEDIR}/$tmpdir
+ exit_with_error "Generated ${ofile}\nis invalid.\nThis is more likely\ndue to incorrect\n${zip} content."
+ else
+ mv ${BASEDIR}/${tmpdir}/${ofile} ${BASEDIR}/.
+ rm -rf ${BASEDIR}/$tmpdir
+ echo -e "\nChecksum verification passed\n\nCopy the ${ofile}\ninto root of SD card\nalong with the rbf file.\n"
+ fi
+}
+
+BASEDIR=$(dirname "$0")
+
+echo "Generating ROM ..."
+
+## verify dependencies
+check_dependencies
+
+## verify write permissions
+check_permissions
+
+## load ini
+read_ini
+
+## extract package
+uncompress_zip
+
+## build rom
+generate_rom
+
+## verify rom
+validate_rom
diff --git a/Arcade_MiST/NinjaKun_MiST/mister/ninjakun_romarb.v b/Arcade_MiST/NinjaKun_MiST/mister/ninjakun_romarb.v
new file mode 100644
index 00000000..d6e4cd78
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/mister/ninjakun_romarb.v
@@ -0,0 +1,80 @@
+// Copyright (c) 2011 MiSTer-X
+
+module NINJAKUN_ROMARB
+(
+ input CLK,
+
+ input [12:0] FGCAD,
+ output [31:0] FGCDT,
+
+ input [12:0] BGCAD,
+ output [31:0] BGCDT,
+
+ input [12:0] SPCAD,
+ output [31:0] SPCDT,
+
+ output reg [2:0] PHASE,
+
+ input [14:0] CP0AD,
+ output [7:0] CP0DT,
+
+ input [14:0] CP1AD,
+ output [7:0] CP1DT
+);
+
+wire CL = ~CLK;
+
+always @( posedge CL ) PHASE <= PHASE+1;
+
+NJFGROM sprom( CL, SPCAD, SPCDT );
+NJFGROM fgrom( CL, FGCAD, FGCDT );
+NJBGROM bgrom( CL, BGCAD, BGCDT );
+
+NJCPU0I cpu0i( CL, CP0AD, CP0DT );
+NJCPU1I cpu1i( CL, {(CP1AD[14]|CP1AD[13]),CP1AD[12:0]}, CP1DT );
+
+endmodule
+
+module NINJAKUN_CPUMUX
+(
+ input CLK24M,
+ input [2:0] PHASE,
+
+ input [15:0] CP0AD,
+ input [7:0] CP0OD,
+ output [7:0] CP0ID,
+ input CP0RD,
+ input CP0WR,
+
+ input [15:0] CP1AD,
+ input [7:0] CP1OD,
+ output [7:0] CP1ID,
+ input CP1RD,
+ input CP1WR,
+
+ output [15:0] CPADR,
+ output [7:0] CPODT,
+ input [7:0] CPIDT,
+ output CPRED,
+ output CPWRT
+);
+
+reg CSIDE;
+reg [7:0] CP0D, CP1D;
+always @( posedge CLK24M ) begin
+ case (PHASE)
+ 4: begin CP1D <= CPIDT; CSIDE <= 0; end
+ 0: begin CP0D <= CPIDT; CSIDE <= 1; end
+ default:;
+ endcase
+end
+
+assign CPADR = CSIDE ? CP1AD : CP0AD;
+assign CPODT = CSIDE ? CP1OD : CP0OD;
+assign CPRED = CSIDE ? CP1RD : CP0RD;
+assign CPWRT = CSIDE ? CP1WR : CP0WR;
+
+assign CP0ID = CSIDE ? CP0D : CPIDT;
+assign CP1ID = CSIDE ? CPIDT : CP1D;
+
+endmodule
diff --git a/Arcade_MiST/NinjaKun_MiST/mister/rommap.txt b/Arcade_MiST/NinjaKun_MiST/mister/rommap.txt
new file mode 100644
index 00000000..ea7c701c
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/mister/rommap.txt
@@ -0,0 +1,7 @@
+
+00000-07FFF GFX1-0,1,2,3
+08000-0FFFF GFX2-0,1,2,3
+10000-17FFF CPU0-0,1,2,3
+18000-1FFFF CPU1-0,CPU0-1,2,3
+
+[EOF]
diff --git a/Arcade_MiST/NinjaKun_MiST/mister/roms.v b/Arcade_MiST/NinjaKun_MiST/mister/roms.v
new file mode 100644
index 00000000..dcda9151
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/mister/roms.v
@@ -0,0 +1,103 @@
+// Copyright (c) 2019 MiSTer-X
+
+module DLROM #(parameter AW,parameter DW)
+(
+ input CL0,
+ input [(AW-1):0] AD0,
+ output reg [(DW-1):0] DO0,
+
+ input CL1,
+ input [(AW-1):0] AD1,
+ input [(DW-1):0] DI1,
+ input WE1
+);
+
+reg [(DW-1):0] core[0:((2**AW)-1)];
+
+always @(posedge CL0) DO0 <= core[AD0];
+always @(posedge CL1) if (WE1) core[AD1] <= DI1;
+
+endmodule
+
+
+module NJFGROM
+(
+ input CL,
+ input [12:0] AD,
+ output [31:0] DT,
+
+ input ROMCL,
+ input [16:0] ROMAD,
+ input [7:0] ROMDT,
+ input ROMEN
+);
+
+wire ROME = ROMEN & (ROMAD[16:15]==2'b00);
+wire ROME0 = ROME & ~ROMAD[13];
+wire ROME1 = ROME & ROMAD[13];
+
+DLROM #(13,8) R0(CL,AD,DT[ 7: 0], ROMCL,{ROMAD[14],ROMAD[12:1]},ROMDT,ROME0 & ~ROMAD[0]);
+DLROM #(13,8) R1(CL,AD,DT[15: 8], ROMCL,{ROMAD[14],ROMAD[12:1]},ROMDT,ROME1 & ~ROMAD[0]);
+DLROM #(13,8) R2(CL,AD,DT[23:16], ROMCL,{ROMAD[14],ROMAD[12:1]},ROMDT,ROME0 & ROMAD[0]);
+DLROM #(13,8) R3(CL,AD,DT[31:24], ROMCL,{ROMAD[14],ROMAD[12:1]},ROMDT,ROME1 & ROMAD[0]);
+
+endmodule
+
+
+module NJBGROM
+(
+ input CL,
+ input [12:0] AD,
+ output [31:0] DT,
+
+ input ROMCL,
+ input [16:0] ROMAD,
+ input [7:0] ROMDT,
+ input ROMEN
+);
+
+wire ROME = ROMEN & (ROMAD[16:15]==2'b01);
+wire ROME0 = ROME & ~ROMAD[13];
+wire ROME1 = ROME & ROMAD[13];
+
+DLROM #(13,8) R0(CL,AD,DT[ 7: 0], ROMCL,{ROMAD[14],ROMAD[12:1]},ROMDT,ROME0 & ~ROMAD[0]);
+DLROM #(13,8) R1(CL,AD,DT[15: 8], ROMCL,{ROMAD[14],ROMAD[12:1]},ROMDT,ROME1 & ~ROMAD[0]);
+DLROM #(13,8) R2(CL,AD,DT[23:16], ROMCL,{ROMAD[14],ROMAD[12:1]},ROMDT,ROME0 & ROMAD[0]);
+DLROM #(13,8) R3(CL,AD,DT[31:24], ROMCL,{ROMAD[14],ROMAD[12:1]},ROMDT,ROME1 & ROMAD[0]);
+
+endmodule
+
+
+module NJC0ROM
+(
+ input CL,
+ input [14:0] AD,
+ output [7:0] DT,
+
+ input ROMCL,
+ input [16:0] ROMAD,
+ input [7:0] ROMDT,
+ input ROMEN
+);
+
+DLROM #(15,8) r(CL,AD,DT,ROMCL,ROMAD,ROMDT,ROMEN & (ROMAD[16:15]==2'b10));
+
+endmodule
+
+
+module NJC1ROM
+(
+ input CL,
+ input [14:0] AD,
+ output [7:0] DT,
+
+ input ROMCL,
+ input [16:0] ROMAD,
+ input [7:0] ROMDT,
+ input ROMEN
+);
+
+DLROM #(15,8) r(CL,AD,DT,ROMCL,ROMAD,ROMDT,ROMEN & (ROMAD[16:15]==2'b11));
+
+endmodule
+
diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/DPRAM1024.v b/Arcade_MiST/NinjaKun_MiST/rtl/DPRAM1024.v
new file mode 100644
index 00000000..e5a0fec0
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/rtl/DPRAM1024.v
@@ -0,0 +1,246 @@
+// megafunction wizard: %RAM: 2-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram
+
+// ============================================================
+// File Name: DPRAM1024.v
+// Megafunction Name(s):
+// altsyncram
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 17.1.0 Build 590 10/25/2017 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2017 Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Intel Program License
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors. Please
+//refer to the applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module DPRAM1024 (
+ address_a,
+ address_b,
+ clock_a,
+ clock_b,
+ data_a,
+ data_b,
+ wren_a,
+ wren_b,
+ q_a,
+ q_b);
+
+ input [9:0] address_a;
+ input [9:0] address_b;
+ input clock_a;
+ input clock_b;
+ input [7:0] data_a;
+ input [7:0] data_b;
+ input wren_a;
+ input wren_b;
+ output [7:0] q_a;
+ output [7:0] q_b;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri1 clock_a;
+ tri0 wren_a;
+ tri0 wren_b;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+ wire [7:0] sub_wire0;
+ wire [7:0] sub_wire1;
+ wire [7:0] q_a = sub_wire0[7:0];
+ wire [7:0] q_b = sub_wire1[7:0];
+
+ altsyncram altsyncram_component (
+ .address_a (address_a),
+ .address_b (address_b),
+ .clock0 (clock_a),
+ .clock1 (clock_b),
+ .data_a (data_a),
+ .data_b (data_b),
+ .wren_a (wren_a),
+ .wren_b (wren_b),
+ .q_a (sub_wire0),
+ .q_b (sub_wire1),
+ .aclr0 (1'b0),
+ .aclr1 (1'b0),
+ .addressstall_a (1'b0),
+ .addressstall_b (1'b0),
+ .byteena_a (1'b1),
+ .byteena_b (1'b1),
+ .clocken0 (1'b1),
+ .clocken1 (1'b1),
+ .clocken2 (1'b1),
+ .clocken3 (1'b1),
+ .eccstatus (),
+ .rden_a (1'b1),
+ .rden_b (1'b1));
+ defparam
+ altsyncram_component.address_reg_b = "CLOCK1",
+ altsyncram_component.clock_enable_input_a = "BYPASS",
+ altsyncram_component.clock_enable_input_b = "BYPASS",
+ altsyncram_component.clock_enable_output_a = "BYPASS",
+ altsyncram_component.clock_enable_output_b = "BYPASS",
+ altsyncram_component.indata_reg_b = "CLOCK1",
+ altsyncram_component.intended_device_family = "Cyclone III",
+ altsyncram_component.lpm_type = "altsyncram",
+ altsyncram_component.numwords_a = 1024,
+ altsyncram_component.numwords_b = 1024,
+ altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
+ altsyncram_component.outdata_aclr_a = "NONE",
+ altsyncram_component.outdata_aclr_b = "NONE",
+ altsyncram_component.outdata_reg_a = "CLOCK0",
+ altsyncram_component.outdata_reg_b = "CLOCK1",
+ altsyncram_component.power_up_uninitialized = "FALSE",
+ altsyncram_component.ram_block_type = "M9K",
+ altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
+ altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
+ altsyncram_component.widthad_a = 10,
+ altsyncram_component.widthad_b = 10,
+ altsyncram_component.width_a = 8,
+ altsyncram_component.width_b = 8,
+ altsyncram_component.width_byteena_a = 1,
+ altsyncram_component.width_byteena_b = 1,
+ altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+// Retrieval info: PRIVATE: CLRq NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "5"
+// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
+// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING ""
+// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
+// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+// Retrieval info: PRIVATE: REGdata NUMERIC "1"
+// Retrieval info: PRIVATE: REGq NUMERIC "1"
+// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: REGrren NUMERIC "0"
+// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGwren NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
+// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
+// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
+// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
+// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: enable NUMERIC "0"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
+// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
+// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
+// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
+// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
+// Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL "address_a[9..0]"
+// Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL "address_b[9..0]"
+// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
+// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
+// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]"
+// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL "data_b[7..0]"
+// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]"
+// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL "q_b[7..0]"
+// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
+// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
+// Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0
+// Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
+// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
+// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
+// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
+// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
+// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
+// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM1024.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM1024.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM1024.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM1024.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM1024_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM1024_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/NinjaKun_MiST.sv b/Arcade_MiST/NinjaKun_MiST/rtl/NinjaKun_MiST.sv
new file mode 100644
index 00000000..7ab26955
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/rtl/NinjaKun_MiST.sv
@@ -0,0 +1,289 @@
+module NinjaKun_MiST (
+ output LED,
+ output [5:0] VGA_R,
+ output [5:0] VGA_G,
+ output [5:0] VGA_B,
+ output VGA_HS,
+ output VGA_VS,
+ output AUDIO_L,
+ output AUDIO_R,
+ input SPI_SCK,
+ output SPI_DO,
+ input SPI_DI,
+ input SPI_SS2,
+ input SPI_SS3,
+ input CONF_DATA0,
+ input CLOCK_27,
+ output [12:0] SDRAM_A,
+ inout [15:0] SDRAM_DQ,
+ output SDRAM_DQML,
+ output SDRAM_DQMH,
+ output SDRAM_nWE,
+ output SDRAM_nCAS,
+ output SDRAM_nRAS,
+ output SDRAM_nCS,
+ output [1:0] SDRAM_BA,
+ output SDRAM_CLK,
+ output SDRAM_CKE
+
+);
+
+`include "rtl\build_id.v"
+
+localparam CONF_STR = {
+ "NINJAKUN;ROM;",
+ "O2,Rotate Controls,Off,On;",
+ "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;",
+ "O8,Difficulty,Normal,Hard;",
+ "O9A,Lives,4,3,2,5;",
+ "OB,1st Extra,30000,40000;",
+ "OCD,2nd Extra (Every),50000,70000,90000,None;",
+ "OF,Allow Continue,No,Yes;",
+ "OG,Free Play,No,Yes;",
+ "OH,Endless(If Free Play),No,Yes;",
+ "OE,Demo Sound,Off,On;",
+ "OI,Name Letters,8,3;",
+ "T6,Reset;",
+ "V,v1.00.",`BUILD_DATE
+};
+
+assign LED = ~ioctl_downl;
+assign AUDIO_R = AUDIO_L;
+assign SDRAM_CLK = ~CLOCK_48;
+assign SDRAM_CKE = 1;
+
+wire CLOCK_48, pll_locked;
+pll pll(
+ .inclk0(CLOCK_27),
+ .c0(CLOCK_48),
+ .locked(pll_locked)
+ );
+
+wire [31:0] status;
+wire [1:0] buttons;
+wire [1:0] switches;
+wire [11:0] kbjoy;
+wire [7:0] joystick_0;
+wire [7:0] joystick_1;
+wire scandoublerD;
+wire ypbpr;
+wire [15:0] audio;
+wire hs, vs;
+wire hb, vb;
+wire blankn = ~(hb | vb);
+wire [3:0] r, g, b;
+wire [14:0] cpu1_rom_addr;
+wire [12:0] cpu2_rom_addr;
+wire [15:0] cpu1_rom_do, cpu2_rom_do;
+//wire [12:0] sp_rom_addr;
+//wire [31:0] sp_rom_do;
+//wire [12:0] fg_rom_addr;
+//wire [31:0] fg_rom_do;
+wire [12:0] bg_rom_addr;
+wire [31:0] bg_rom_do;
+wire ioctl_downl;
+wire [7:0] ioctl_index;
+wire ioctl_wr;
+wire [24:0] ioctl_addr;
+wire [7:0] ioctl_dout;
+wire key_strobe;
+wire key_pressed;
+wire [7:0] key_code;
+
+data_io data_io(
+ .clk_sys ( CLOCK_48 ),
+ .SPI_SCK ( SPI_SCK ),
+ .SPI_SS2 ( SPI_SS2 ),
+ .SPI_DI ( SPI_DI ),
+ .ioctl_download( ioctl_downl ),
+ .ioctl_index ( ioctl_index ),
+ .ioctl_wr ( ioctl_wr ),
+ .ioctl_addr ( ioctl_addr ),
+ .ioctl_dout ( ioctl_dout )
+);
+
+wire [24:0] sp_ioctl_addr = ioctl_addr - 16'ha000;
+
+reg port1_req, port2_req;
+sdram sdram(
+ .*,
+ .init_n ( pll_locked ),
+ .clk ( CLOCK_48 ),
+
+ // port1 used for main + sound CPU
+ .port1_req ( port1_req ),
+ .port1_ack ( ),
+ .port1_a ( ioctl_addr[23:1] ),
+ .port1_ds ( {ioctl_addr[0], ~ioctl_addr[0]} ),
+ .port1_we ( ioctl_downl ),
+ .port1_d ( {ioctl_dout, ioctl_dout} ),
+ .port1_q ( ),
+
+ .cpu1_addr ( ioctl_downl ? 16'hffff : {1'b0, cpu1_rom_addr[14:1]} ),
+ .cpu1_q ( cpu1_rom_do ),
+ .cpu2_addr ( ioctl_downl ? 16'hffff : (16'h4000 + cpu2_rom_addr[12:1]) ),
+ .cpu2_q ( cpu2_rom_do ),
+
+ // port2 for sprite graphics
+ .port2_req ( port2_req ),
+ .port2_ack ( ),
+ .port2_a ( {sp_ioctl_addr[12:0], sp_ioctl_addr[14]} ),
+ .port2_ds ( {sp_ioctl_addr[13], ~sp_ioctl_addr[13]} ),
+ .port2_we ( ioctl_downl ),
+ .port2_d ( {ioctl_dout, ioctl_dout} ),
+ .port2_q ( ),
+
+ .sp_addr ( ioctl_downl ? 15'h7fff : bg_rom_addr ),
+ .sp_q ( bg_rom_do )
+);
+
+
+// ROM download controller
+always @(posedge CLOCK_48) begin
+ reg ioctl_wr_last = 0;
+
+ ioctl_wr_last <= ioctl_wr;
+ if (ioctl_downl) begin
+ if (~ioctl_wr_last && ioctl_wr) begin
+ port1_req <= ~port1_req;
+ port2_req <= ~port2_req;
+ end
+ end
+end
+
+
+reg reset = 1;
+reg rom_loaded = 0;
+always @(posedge CLOCK_48) begin
+ reg ioctl_downlD;
+ ioctl_downlD <= ioctl_downl;
+ if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1;
+ reset <= status[0] | buttons[1] | status[6] | ~rom_loaded;
+end
+
+wire PCLK;
+wire [8:0] HPOS,VPOS;
+wire [7:0] POUT;
+ninjakun_top ninjakun_top(
+ .RESET(reset),
+ .MCLK(CLOCK_48),
+ .CTR1(~{2'b11, btn_one_player, 1'b0, m_fire, m_bomb, m_right, m_left }),
+ .CTR2(~{~btn_coin, 1'b1, btn_two_players, 1'b0, m_fire, m_bomb, m_right, m_left }),
+ .DSW1({~status[8], ~status[14], ~status[13:12], ~status[11], ~status[10:9], 1'b0}),
+ .DSW2({~status[17], ~status[16], 1'b0, ~status[15], ~status[18], 3'b111}),
+ .PH(HPOS),
+ .PV(VPOS),
+ .PCLK(PCLK),
+ .POUT(POUT),
+ .SNDOUT(audio),
+ .CPU1ADDR(cpu1_rom_addr),
+ .CPU1DT(cpu1_rom_addr[0] ? cpu1_rom_do[15:8] : cpu1_rom_do[7:0]),
+ .CPU2ADDR(cpu2_rom_addr),
+ .CPU2DT(cpu2_rom_addr[0] ? cpu2_rom_do[15:8] : cpu2_rom_do[7:0]),
+// .sp_rom_addr(sp_rom_addr),
+// .sp_rom_data(sp_rom_do),
+// .fg_rom_addr(fg_rom_addr),
+// .fg_rom_data(sp_rom_do),
+ .bg_rom_addr(bg_rom_addr),
+ .bg_rom_data(bg_rom_do)
+);
+
+hvgen hvgen(
+ .HPOS(HPOS),
+ .VPOS(VPOS),
+ .PCLK(PCLK),
+ .iRGB(POUT),
+ .oRGB({r,g,b}),
+ .HBLK(hb),
+ .VBLK(vb),
+ .HSYN(hs),
+ .VSYN(vs)
+);
+
+mist_video #(.COLOR_DEPTH(4), .SD_HCNT_WIDTH(11)) mist_video(
+ .clk_sys ( CLOCK_48 ),
+ .SPI_SCK ( SPI_SCK ),
+ .SPI_SS3 ( SPI_SS3 ),
+ .SPI_DI ( SPI_DI ),
+ .R ( blankn ? r : 0 ),
+ .G ( blankn ? g : 0 ),
+ .B ( blankn ? b : 0 ),
+ .HSync ( hs ),
+ .VSync ( vs ),
+ .VGA_R ( VGA_R ),
+ .VGA_G ( VGA_G ),
+ .VGA_B ( VGA_B ),
+ .VGA_VS ( VGA_VS ),
+ .VGA_HS ( VGA_HS ),
+ .rotate ( {1'b1,status[2]} ),
+ .ce_divider (1),
+ .scandoubler_disable( scandoublerD ),
+ .scanlines ( status[4:3] ),
+ .ypbpr ( ypbpr )
+ );
+
+user_io #(.STRLEN(($size(CONF_STR)>>3)))user_io(
+ .clk_sys (CLOCK_48 ),
+ .conf_str (CONF_STR ),
+ .SPI_CLK (SPI_SCK ),
+ .SPI_SS_IO (CONF_DATA0 ),
+ .SPI_MISO (SPI_DO ),
+ .SPI_MOSI (SPI_DI ),
+ .buttons (buttons ),
+ .switches (switches ),
+ .scandoubler_disable (scandoublerD ),
+ .ypbpr (ypbpr ),
+ .key_strobe (key_strobe ),
+ .key_pressed (key_pressed ),
+ .key_code (key_code ),
+ .joystick_0 (joystick_0 ),
+ .joystick_1 (joystick_1 ),
+ .status (status )
+ );
+
+dac #(.C_bits(16))dac(
+ .clk_i(CLOCK_48),
+ .res_n_i(1),
+ .dac_i(audio),
+ .dac_o(AUDIO_L)
+ );
+// Rotated Normal
+//wire m_up = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3];
+//wire m_down = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2];
+wire m_left = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1];
+wire m_right = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0];
+wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4];
+wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5];
+
+reg btn_one_player = 0;
+reg btn_two_players = 0;
+reg btn_left = 0;
+reg btn_right = 0;
+reg btn_down = 0;
+reg btn_up = 0;
+reg btn_fire1 = 0;
+reg btn_fire2 = 0;
+//reg btn_fire3 = 0;
+reg btn_coin = 0;
+
+always @(posedge CLOCK_48) begin
+ reg old_state;
+ old_state <= key_strobe;
+ if(old_state != key_strobe) begin
+ case(key_code)
+ 'h75: btn_up <= key_pressed; // up
+ 'h72: btn_down <= key_pressed; // down
+ 'h6B: btn_left <= key_pressed; // left
+ 'h74: btn_right <= key_pressed; // right
+ 'h76: btn_coin <= key_pressed; // ESC
+ 'h05: btn_one_player <= key_pressed; // F1
+ 'h06: btn_two_players <= key_pressed; // F2
+// 'h14: btn_fire3 <= key_pressed; // ctrl
+ 'h11: btn_fire2 <= key_pressed; // alt
+ 'h29: btn_fire1 <= key_pressed; // Space
+ endcase
+ end
+end
+
+
+endmodule
diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/YM2149_linmix_sep.vhd b/Arcade_MiST/NinjaKun_MiST/rtl/YM2149_linmix_sep.vhd
new file mode 100644
index 00000000..6ed2498a
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/rtl/YM2149_linmix_sep.vhd
@@ -0,0 +1,574 @@
+-- changes for seperate audio outputs and enable now enables cpu access as well
+--
+-- A simulation model of YM2149 (AY-3-8910 with bells on)
+
+-- Copyright (c) MikeJ - Jan 2005
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- You are responsible for any legal issues arising from your use of this code.
+--
+-- The latest version of this file can be found at: www.fpgaarcade.com
+--
+-- Email support@fpgaarcade.com
+--
+-- Revision list
+--
+-- version 001 initial release
+--
+-- Clues from MAME sound driver and Kazuhiro TSUJIKAWA
+--
+-- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V)
+-- vol 15 .. 0
+-- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132
+-- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order
+-- to produced all the required values.
+-- (The first part of the curve is a bit steeper and the last bit is more linear than expected)
+--
+-- NOTE, this component uses LINEAR mixing of the three analogue channels, and is only
+-- accurate for designs where the outputs are buffered and not simply wired together.
+-- The ouput level is more complex in that case and requires a larger table.
+
+library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
+
+entity YM2149 is
+ port (
+ -- data bus
+ I_DA : in std_logic_vector(7 downto 0);
+ O_DA : out std_logic_vector(7 downto 0);
+ O_DA_OE_L : out std_logic;
+ -- control
+ I_A9_L : in std_logic;
+ I_A8 : in std_logic;
+ I_BDIR : in std_logic;
+ I_BC2 : in std_logic;
+ I_BC1 : in std_logic;
+ I_SEL_L : in std_logic;
+
+ O_AUDIO : out std_logic_vector(7 downto 0);
+ O_CHAN : out std_logic_vector(1 downto 0);
+ -- port a
+ I_IOA : in std_logic_vector(7 downto 0);
+ O_IOA : out std_logic_vector(7 downto 0);
+ O_IOA_OE_L : out std_logic;
+ -- port b
+ I_IOB : in std_logic_vector(7 downto 0);
+ O_IOB : out std_logic_vector(7 downto 0);
+ O_IOB_OE_L : out std_logic;
+
+ ENA : in std_logic; -- clock enable for higher speed operation
+ RESET_L : in std_logic;
+ CLK : in std_logic -- note 6 Mhz
+ );
+end;
+
+architecture RTL of YM2149 is
+ type array_16x8 is array (0 to 15) of std_logic_vector( 7 downto 0);
+ type array_3x12 is array (1 to 3) of std_logic_vector(11 downto 0);
+
+ signal cnt_div : std_logic_vector(3 downto 0) := (others => '0');
+ signal cnt_div_t1 : std_logic_vector(3 downto 0);
+ signal noise_div : std_logic := '0';
+ signal ena_div : std_logic;
+ signal ena_div_noise : std_logic;
+ signal poly17 : std_logic_vector(16 downto 0) := (others => '0');
+
+ -- registers
+ signal addr : std_logic_vector(7 downto 0);
+ signal busctrl_addr : std_logic;
+ signal busctrl_we : std_logic;
+ signal busctrl_re : std_logic;
+
+ signal reg : array_16x8;
+ signal env_reset : std_logic;
+ signal ioa_inreg : std_logic_vector(7 downto 0);
+ signal iob_inreg : std_logic_vector(7 downto 0);
+
+ signal noise_gen_cnt : std_logic_vector(4 downto 0);
+ signal noise_gen_op : std_logic;
+ signal tone_gen_cnt : array_3x12 := (others => (others => '0'));
+ signal tone_gen_op : std_logic_vector(3 downto 1) := "000";
+
+ signal env_gen_cnt : std_logic_vector(15 downto 0);
+ signal env_ena : std_logic;
+ signal env_hold : std_logic;
+ signal env_inc : std_logic;
+ signal env_vol : std_logic_vector(4 downto 0);
+
+ signal tone_ena_l : std_logic;
+ signal tone_src : std_logic;
+ signal noise_ena_l : std_logic;
+ signal chan_vol : std_logic_vector(4 downto 0);
+
+ signal dac_amp : std_logic_vector(7 downto 0);
+begin
+ -- cpu i/f
+ p_busdecode : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8)
+ variable cs : std_logic;
+ variable sel : std_logic_vector(2 downto 0);
+ begin
+ -- BDIR BC2 BC1 MODE
+ -- 0 0 0 inactive
+ -- 0 0 1 address
+ -- 0 1 0 inactive
+ -- 0 1 1 read
+ -- 1 0 0 address
+ -- 1 0 1 inactive
+ -- 1 1 0 write
+ -- 1 1 1 read
+ busctrl_addr <= '0';
+ busctrl_we <= '0';
+ busctrl_re <= '0';
+
+ cs := '0';
+ if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then
+ cs := '1';
+ end if;
+
+ sel := (I_BDIR & I_BC2 & I_BC1);
+ case sel is
+ when "000" => null;
+ when "001" => busctrl_addr <= '1';
+ when "010" => null;
+ when "011" => busctrl_re <= cs;
+ when "100" => busctrl_addr <= '1';
+ when "101" => null;
+ when "110" => busctrl_we <= cs;
+ when "111" => busctrl_addr <= '1';
+ when others => null;
+ end case;
+ end process;
+
+ p_oe : process(busctrl_re)
+ begin
+ -- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns
+ O_DA_OE_L <= not (busctrl_re);
+ end process;
+
+ --
+ -- CLOCKED
+ --
+ p_waddr : process(RESET_L, CLK)
+ begin
+ -- looks like registers are latches in real chip, but the address is caught at the end of the address state.
+ if (RESET_L = '0') then
+ addr <= (others => '0');
+ elsif rising_edge(CLK) then
+ if (ENA = '1') then
+ if (busctrl_addr = '1') then
+ addr <= I_DA;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ p_wdata : process(RESET_L, CLK)
+ begin
+ if (RESET_L = '0') then
+ reg <= (others => (others => '0'));
+ env_reset <= '1';
+ elsif rising_edge(CLK) then
+ if (ENA = '1') then
+ env_reset <= '0';
+ if (busctrl_we = '1') then
+ case addr(3 downto 0) is
+ when x"0" => reg(0) <= I_DA;
+ when x"1" => reg(1) <= I_DA;
+ when x"2" => reg(2) <= I_DA;
+ when x"3" => reg(3) <= I_DA;
+ when x"4" => reg(4) <= I_DA;
+ when x"5" => reg(5) <= I_DA;
+ when x"6" => reg(6) <= I_DA;
+ when x"7" => reg(7) <= I_DA;
+ when x"8" => reg(8) <= I_DA;
+ when x"9" => reg(9) <= I_DA;
+ when x"A" => reg(10) <= I_DA;
+ when x"B" => reg(11) <= I_DA;
+ when x"C" => reg(12) <= I_DA;
+ when x"D" => reg(13) <= I_DA; env_reset <= '1';
+ when x"E" => reg(14) <= I_DA;
+ when x"F" => reg(15) <= I_DA;
+ when others => null;
+ end case;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ p_rdata : process(busctrl_re, addr, reg, ioa_inreg, iob_inreg)
+ begin
+ O_DA <= (others => '0'); -- 'X'
+ if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator
+ case addr(3 downto 0) is
+ when x"0" => O_DA <= reg(0) ;
+ when x"1" => O_DA <= "0000" & reg(1)(3 downto 0) ;
+ when x"2" => O_DA <= reg(2) ;
+ when x"3" => O_DA <= "0000" & reg(3)(3 downto 0) ;
+ when x"4" => O_DA <= reg(4) ;
+ when x"5" => O_DA <= "0000" & reg(5)(3 downto 0) ;
+ when x"6" => O_DA <= "000" & reg(6)(4 downto 0) ;
+ when x"7" => O_DA <= reg(7) ;
+ when x"8" => O_DA <= "000" & reg(8)(4 downto 0) ;
+ when x"9" => O_DA <= "000" & reg(9)(4 downto 0) ;
+ when x"A" => O_DA <= "000" & reg(10)(4 downto 0) ;
+ when x"B" => O_DA <= reg(11);
+ when x"C" => O_DA <= reg(12);
+ when x"D" => O_DA <= "0000" & reg(13)(3 downto 0);
+ when x"E" => if (reg(7)(6) = '0') then -- input
+ O_DA <= ioa_inreg;
+ else
+ O_DA <= reg(14); -- read output reg
+ end if;
+ when x"F" => if (Reg(7)(7) = '0') then
+ O_DA <= iob_inreg;
+ else
+ O_DA <= reg(15);
+ end if;
+ when others => null;
+ end case;
+ end if;
+ end process;
+ --
+ p_divider : process
+ begin
+ wait until rising_edge(CLK);
+ -- / 8 when SEL is high and /16 when SEL is low
+ if (ENA = '1') then
+ ena_div <= '0';
+ ena_div_noise <= '0';
+ if (cnt_div = "0000") then
+ cnt_div <= (not I_SEL_L) & "111";
+ ena_div <= '1';
+
+ noise_div <= not noise_div;
+ if (noise_div = '1') then
+ ena_div_noise <= '1';
+ end if;
+ else
+ cnt_div <= cnt_div - "1";
+ end if;
+ end if;
+ end process;
+
+ p_noise_gen : process
+ variable noise_gen_comp : std_logic_vector(4 downto 0);
+ variable poly17_zero : std_logic;
+ begin
+ wait until rising_edge(CLK);
+ if (reg(6)(4 downto 0) = "00000") then
+ noise_gen_comp := "00000";
+ else
+ noise_gen_comp := (reg(6)(4 downto 0) - "1");
+ end if;
+
+ poly17_zero := '0';
+ if (poly17 = "00000000000000000") then poly17_zero := '1'; end if;
+
+ if (ENA = '1') then
+ if (ena_div_noise = '1') then -- divider ena
+
+ if (noise_gen_cnt >= noise_gen_comp) then
+ noise_gen_cnt <= "00000";
+ poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1);
+ else
+ noise_gen_cnt <= (noise_gen_cnt + "1");
+ end if;
+ end if;
+ end if;
+ end process;
+ noise_gen_op <= poly17(0);
+
+ p_tone_gens : process
+ variable tone_gen_freq : array_3x12;
+ variable tone_gen_comp : array_3x12;
+ begin
+ wait until rising_edge(CLK);
+ -- looks like real chips count up - we need to get the Exact behaviour ..
+ tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0);
+ tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2);
+ tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4);
+ -- period 0 = period 1
+ for i in 1 to 3 loop
+ if (tone_gen_freq(i) = x"000") then
+ tone_gen_comp(i) := x"000";
+ else
+ tone_gen_comp(i) := (tone_gen_freq(i) - "1");
+ end if;
+ end loop;
+
+ if (ENA = '1') then
+ for i in 1 to 3 loop
+ if (ena_div = '1') then -- divider ena
+
+ if (tone_gen_cnt(i) >= tone_gen_comp(i)) then
+ tone_gen_cnt(i) <= x"000";
+ tone_gen_op(i) <= not tone_gen_op(i);
+ else
+ tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1");
+ end if;
+ end if;
+ end loop;
+ end if;
+ end process;
+
+ p_envelope_freq : process
+ variable env_gen_freq : std_logic_vector(15 downto 0);
+ variable env_gen_comp : std_logic_vector(15 downto 0);
+ begin
+ wait until rising_edge(CLK);
+ env_gen_freq := reg(12) & reg(11);
+ -- envelope freqs 1 and 0 are the same.
+ if (env_gen_freq = x"0000") then
+ env_gen_comp := x"0000";
+ else
+ env_gen_comp := (env_gen_freq - "1");
+ end if;
+
+ if (ENA = '1') then
+ env_ena <= '0';
+ if (ena_div = '1') then -- divider ena
+ if (env_gen_cnt >= env_gen_comp) then
+ env_gen_cnt <= x"0000";
+ env_ena <= '1';
+ else
+ env_gen_cnt <= (env_gen_cnt + "1");
+ end if;
+ end if;
+ end if;
+ end process;
+
+ p_envelope_shape : process(env_reset, reg, CLK)
+ variable is_bot : boolean;
+ variable is_bot_p1 : boolean;
+ variable is_top_m1 : boolean;
+ variable is_top : boolean;
+ begin
+ -- envelope shapes
+ -- C AtAlH
+ -- 0 0 x x \___
+ --
+ -- 0 1 x x /___
+ --
+ -- 1 0 0 0 \\\\
+ --
+ -- 1 0 0 1 \___
+ --
+ -- 1 0 1 0 \/\/
+ -- ___
+ -- 1 0 1 1 \
+ --
+ -- 1 1 0 0 ////
+ -- ___
+ -- 1 1 0 1 /
+ --
+ -- 1 1 1 0 /\/\
+ --
+ -- 1 1 1 1 /___
+ if (env_reset = '1') then
+ -- load initial state
+ if (reg(13)(2) = '0') then -- attack
+ env_vol <= "11111";
+ env_inc <= '0'; -- -1
+ else
+ env_vol <= "00000";
+ env_inc <= '1'; -- +1
+ end if;
+ env_hold <= '0';
+
+ elsif rising_edge(CLK) then
+ is_bot := (env_vol = "00000");
+ is_bot_p1 := (env_vol = "00001");
+ is_top_m1 := (env_vol = "11110");
+ is_top := (env_vol = "11111");
+
+ if (ENA = '1') then
+ if (env_ena = '1') then
+ if (env_hold = '0') then
+ if (env_inc = '1') then
+ env_vol <= (env_vol + "00001");
+ else
+ env_vol <= (env_vol + "11111");
+ end if;
+ end if;
+
+ -- envelope shape control.
+ if (reg(13)(3) = '0') then
+ if (env_inc = '0') then -- down
+ if is_bot_p1 then env_hold <= '1'; end if;
+ else
+ if is_top then env_hold <= '1'; end if;
+ end if;
+ else
+ if (reg(13)(0) = '1') then -- hold = 1
+ if (env_inc = '0') then -- down
+ if (reg(13)(1) = '1') then -- alt
+ if is_bot then env_hold <= '1'; end if;
+ else
+ if is_bot_p1 then env_hold <= '1'; end if;
+ end if;
+ else
+ if (reg(13)(1) = '1') then -- alt
+ if is_top then env_hold <= '1'; end if;
+ else
+ if is_top_m1 then env_hold <= '1'; end if;
+ end if;
+ end if;
+
+ elsif (reg(13)(1) = '1') then -- alternate
+ if (env_inc = '0') then -- down
+ if is_bot_p1 then env_hold <= '1'; end if;
+ if is_bot then env_hold <= '0'; env_inc <= '1'; end if;
+ else
+ if is_top_m1 then env_hold <= '1'; end if;
+ if is_top then env_hold <= '0'; env_inc <= '0'; end if;
+ end if;
+ end if;
+
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ p_chan_mixer : process(cnt_div, reg, tone_gen_op)
+ begin
+ tone_ena_l <= '1'; tone_src <= '1';
+ noise_ena_l <= '1'; chan_vol <= "00000";
+ case cnt_div(1 downto 0) is
+ when "00" =>
+ tone_ena_l <= reg(7)(0); tone_src <= tone_gen_op(1); chan_vol <= reg(8)(4 downto 0);
+ noise_ena_l <= reg(7)(3);
+ when "01" =>
+ tone_ena_l <= reg(7)(1); tone_src <= tone_gen_op(2); chan_vol <= reg(9)(4 downto 0);
+ noise_ena_l <= reg(7)(4);
+ when "10" =>
+ tone_ena_l <= reg(7)(2); tone_src <= tone_gen_op(3); chan_vol <= reg(10)(4 downto 0);
+ noise_ena_l <= reg(7)(5);
+ when "11" => null; -- tone gen outputs become valid on this clock
+ when others => null;
+ end case;
+ end process;
+
+ p_op_mixer : process
+ variable chan_mixed : std_logic;
+ variable chan_amp : std_logic_vector(4 downto 0);
+ begin
+ wait until rising_edge(CLK);
+ if (ENA = '1') then
+
+ chan_mixed := (tone_ena_l or tone_src) and (noise_ena_l or noise_gen_op);
+
+ chan_amp := (others => '0');
+ if (chan_mixed = '1') then
+ if (chan_vol(4) = '0') then
+ if (chan_vol(3 downto 0) = "0000") then -- nothing is easy ! make sure quiet is quiet
+ chan_amp := "00000";
+ else
+ chan_amp := chan_vol(3 downto 0) & '1'; -- make sure level 31 (env) = level 15 (tone)
+ end if;
+ else
+ chan_amp := env_vol(4 downto 0);
+ end if;
+ end if;
+
+ dac_amp <= x"00";
+ case chan_amp is
+ when "11111" => dac_amp <= x"FF";
+ when "11110" => dac_amp <= x"D9";
+ when "11101" => dac_amp <= x"BA";
+ when "11100" => dac_amp <= x"9F";
+ when "11011" => dac_amp <= x"88";
+ when "11010" => dac_amp <= x"74";
+ when "11001" => dac_amp <= x"63";
+ when "11000" => dac_amp <= x"54";
+ when "10111" => dac_amp <= x"48";
+ when "10110" => dac_amp <= x"3D";
+ when "10101" => dac_amp <= x"34";
+ when "10100" => dac_amp <= x"2C";
+ when "10011" => dac_amp <= x"25";
+ when "10010" => dac_amp <= x"1F";
+ when "10001" => dac_amp <= x"1A";
+ when "10000" => dac_amp <= x"16";
+ when "01111" => dac_amp <= x"13";
+ when "01110" => dac_amp <= x"10";
+ when "01101" => dac_amp <= x"0D";
+ when "01100" => dac_amp <= x"0B";
+ when "01011" => dac_amp <= x"09";
+ when "01010" => dac_amp <= x"08";
+ when "01001" => dac_amp <= x"07";
+ when "01000" => dac_amp <= x"06";
+ when "00111" => dac_amp <= x"05";
+ when "00110" => dac_amp <= x"04";
+ when "00101" => dac_amp <= x"03";
+ when "00100" => dac_amp <= x"03";
+ when "00011" => dac_amp <= x"02";
+ when "00010" => dac_amp <= x"02";
+ when "00001" => dac_amp <= x"01";
+ when "00000" => dac_amp <= x"00";
+ when others => null;
+ end case;
+
+ cnt_div_t1 <= cnt_div;
+ end if;
+ end process;
+
+ p_audio_output : process(RESET_L, CLK)
+ begin
+ if (RESET_L = '0') then
+ O_AUDIO <= (others => '0');
+ O_CHAN <= (others => '0');
+ elsif rising_edge(CLK) then
+
+ if (ENA = '1') then
+ O_AUDIO <= dac_amp(7 downto 0);
+ O_CHAN <= cnt_div_t1(1 downto 0);
+ end if;
+ end if;
+ end process;
+
+ p_io_ports : process(reg)
+ begin
+ O_IOA <= reg(14);
+ O_IOA_OE_L <= not reg(7)(6);
+ O_IOB <= reg(15);
+ O_IOB_OE_L <= not reg(7)(7);
+ end process;
+
+ p_io_ports_inreg : process
+ begin
+ wait until rising_edge(CLK);
+ if (ENA = '1') then -- resync
+ ioa_inreg <= I_IOA;
+ iob_inreg <= I_IOB;
+ end if;
+ end process;
+end architecture RTL;
diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/build_id.tcl b/Arcade_MiST/NinjaKun_MiST/rtl/build_id.tcl
new file mode 100644
index 00000000..938515d8
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/rtl/build_id.tcl
@@ -0,0 +1,35 @@
+# ================================================================================
+#
+# Build ID Verilog Module Script
+# Jeff Wiencrot - 8/1/2011
+#
+# Generates a Verilog module that contains a timestamp,
+# from the current build. These values are available from the build_date, build_time,
+# physical_address, and host_name output ports of the build_id module in the build_id.v
+# Verilog source file.
+#
+# ================================================================================
+
+proc generateBuildID_Verilog {} {
+
+ # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
+ set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
+ set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
+
+ # Create a Verilog file for output
+ set outputFileName "rtl/build_id.v"
+ set outputFile [open $outputFileName "w"]
+
+ # Output the Verilog source
+ puts $outputFile "`define BUILD_DATE \"$buildDate\""
+ puts $outputFile "`define BUILD_TIME \"$buildTime\""
+ close $outputFile
+
+ # Send confirmation message to the Messages window
+ post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
+ post_message "Date: $buildDate"
+ post_message "Time: $buildTime"
+}
+
+# Comment out this line to prevent the process from automatically executing when the file is sourced:
+generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/NinjaKun_MiST/rtl/cpu/T80.vhd
new file mode 100644
index 00000000..398fa0df
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/rtl/cpu/T80.vhd
@@ -0,0 +1,1073 @@
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+-- 0208 : First complete release
+--
+-- 0210 : Fixed wait and halt
+--
+-- 0211 : Fixed Refresh addition and IM 1
+--
+-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
+--
+-- 0235 : Added clock enable and IM 2 fix by Mike Johnson
+--
+-- 0237 : Changed 8080 I/O address output, added IntE output
+--
+-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
+--
+-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
+--
+-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
+--
+-- 0247 : Fixed bus req/ack cycle
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80 is
+ generic(
+ Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+ IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
+ Flag_C : integer := 0;
+ Flag_N : integer := 1;
+ Flag_P : integer := 2;
+ Flag_X : integer := 3;
+ Flag_H : integer := 4;
+ Flag_Y : integer := 5;
+ Flag_Z : integer := 6;
+ Flag_S : integer := 7
+ );
+ port(
+ RESET_n : in std_logic;
+ CLK_n : in std_logic;
+ CEN : in std_logic;
+ WAIT_n : in std_logic;
+ INT_n : in std_logic;
+ NMI_n : in std_logic;
+ BUSRQ_n : in std_logic;
+ M1_n : out std_logic;
+ IORQ : out std_logic;
+ NoRead : out std_logic;
+ Write : out std_logic;
+ RFSH_n : out std_logic;
+ HALT_n : out std_logic;
+ BUSAK_n : out std_logic;
+ A : out std_logic_vector(15 downto 0);
+ DInst : in std_logic_vector(7 downto 0);
+ DI : in std_logic_vector(7 downto 0);
+ DO : out std_logic_vector(7 downto 0);
+ MC : out std_logic_vector(2 downto 0);
+ TS : out std_logic_vector(2 downto 0);
+ IntCycle_n : out std_logic;
+ IntE : out std_logic;
+ Stop : out std_logic
+ );
+end T80;
+
+architecture rtl of T80 is
+
+ constant aNone : std_logic_vector(2 downto 0) := "111";
+ constant aBC : std_logic_vector(2 downto 0) := "000";
+ constant aDE : std_logic_vector(2 downto 0) := "001";
+ constant aXY : std_logic_vector(2 downto 0) := "010";
+ constant aIOA : std_logic_vector(2 downto 0) := "100";
+ constant aSP : std_logic_vector(2 downto 0) := "101";
+ constant aZI : std_logic_vector(2 downto 0) := "110";
+
+ -- Registers
+ signal ACC, F : std_logic_vector(7 downto 0);
+ signal Ap, Fp : std_logic_vector(7 downto 0);
+ signal I : std_logic_vector(7 downto 0);
+ signal R : unsigned(7 downto 0);
+ signal SP, PC : unsigned(15 downto 0);
+ signal RegDIH : std_logic_vector(7 downto 0);
+ signal RegDIL : std_logic_vector(7 downto 0);
+ signal RegBusA : std_logic_vector(15 downto 0);
+ signal RegBusB : std_logic_vector(15 downto 0);
+ signal RegBusC : std_logic_vector(15 downto 0);
+ signal RegAddrA_r : std_logic_vector(2 downto 0);
+ signal RegAddrA : std_logic_vector(2 downto 0);
+ signal RegAddrB_r : std_logic_vector(2 downto 0);
+ signal RegAddrB : std_logic_vector(2 downto 0);
+ signal RegAddrC : std_logic_vector(2 downto 0);
+ signal RegWEH : std_logic;
+ signal RegWEL : std_logic;
+ signal Alternate : std_logic;
+
+ -- Help Registers
+ signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register
+ signal IR : std_logic_vector(7 downto 0); -- Instruction register
+ signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector
+ signal RegBusA_r : std_logic_vector(15 downto 0);
+
+ signal ID16 : signed(15 downto 0);
+ signal Save_Mux : std_logic_vector(7 downto 0);
+
+ signal TState : unsigned(2 downto 0);
+ signal MCycle : std_logic_vector(2 downto 0);
+ signal IntE_FF1 : std_logic;
+ signal IntE_FF2 : std_logic;
+ signal Halt_FF : std_logic;
+ signal BusReq_s : std_logic;
+ signal BusAck : std_logic;
+ signal ClkEn : std_logic;
+ signal NMI_s : std_logic;
+ signal INT_s : std_logic;
+ signal IStatus : std_logic_vector(1 downto 0);
+
+ signal DI_Reg : std_logic_vector(7 downto 0);
+ signal T_Res : std_logic;
+ signal XY_State : std_logic_vector(1 downto 0);
+ signal Pre_XY_F_M : std_logic_vector(2 downto 0);
+ signal NextIs_XY_Fetch : std_logic;
+ signal XY_Ind : std_logic;
+ signal No_BTR : std_logic;
+ signal BTR_r : std_logic;
+ signal Auto_Wait : std_logic;
+ signal Auto_Wait_t1 : std_logic;
+ signal Auto_Wait_t2 : std_logic;
+ signal IncDecZ : std_logic;
+
+ -- ALU signals
+ signal BusB : std_logic_vector(7 downto 0);
+ signal BusA : std_logic_vector(7 downto 0);
+ signal ALU_Q : std_logic_vector(7 downto 0);
+ signal F_Out : std_logic_vector(7 downto 0);
+
+ -- Registered micro code outputs
+ signal Read_To_Reg_r : std_logic_vector(4 downto 0);
+ signal Arith16_r : std_logic;
+ signal Z16_r : std_logic;
+ signal ALU_Op_r : std_logic_vector(3 downto 0);
+ signal Save_ALU_r : std_logic;
+ signal PreserveC_r : std_logic;
+ signal MCycles : std_logic_vector(2 downto 0);
+
+ -- Micro code outputs
+ signal MCycles_d : std_logic_vector(2 downto 0);
+ signal TStates : std_logic_vector(2 downto 0);
+ signal IntCycle : std_logic;
+ signal NMICycle : std_logic;
+ signal Inc_PC : std_logic;
+ signal Inc_WZ : std_logic;
+ signal IncDec_16 : std_logic_vector(3 downto 0);
+ signal Prefix : std_logic_vector(1 downto 0);
+ signal Read_To_Acc : std_logic;
+ signal Read_To_Reg : std_logic;
+ signal Set_BusB_To : std_logic_vector(3 downto 0);
+ signal Set_BusA_To : std_logic_vector(3 downto 0);
+ signal ALU_Op : std_logic_vector(3 downto 0);
+ signal Save_ALU : std_logic;
+ signal PreserveC : std_logic;
+ signal Arith16 : std_logic;
+ signal Set_Addr_To : std_logic_vector(2 downto 0);
+ signal Jump : std_logic;
+ signal JumpE : std_logic;
+ signal JumpXY : std_logic;
+ signal Call : std_logic;
+ signal RstP : std_logic;
+ signal LDZ : std_logic;
+ signal LDW : std_logic;
+ signal LDSPHL : std_logic;
+ signal IORQ_i : std_logic;
+ signal Special_LD : std_logic_vector(2 downto 0);
+ signal ExchangeDH : std_logic;
+ signal ExchangeRp : std_logic;
+ signal ExchangeAF : std_logic;
+ signal ExchangeRS : std_logic;
+ signal I_DJNZ : std_logic;
+ signal I_CPL : std_logic;
+ signal I_CCF : std_logic;
+ signal I_SCF : std_logic;
+ signal I_RETN : std_logic;
+ signal I_BT : std_logic;
+ signal I_BC : std_logic;
+ signal I_BTR : std_logic;
+ signal I_RLD : std_logic;
+ signal I_RRD : std_logic;
+ signal I_INRC : std_logic;
+ signal SetDI : std_logic;
+ signal SetEI : std_logic;
+ signal IMode : std_logic_vector(1 downto 0);
+ signal Halt : std_logic;
+
+begin
+
+ mcode : T80_MCode
+ generic map(
+ Mode => Mode,
+ Flag_C => Flag_C,
+ Flag_N => Flag_N,
+ Flag_P => Flag_P,
+ Flag_X => Flag_X,
+ Flag_H => Flag_H,
+ Flag_Y => Flag_Y,
+ Flag_Z => Flag_Z,
+ Flag_S => Flag_S)
+ port map(
+ IR => IR,
+ ISet => ISet,
+ MCycle => MCycle,
+ F => F,
+ NMICycle => NMICycle,
+ IntCycle => IntCycle,
+ MCycles => MCycles_d,
+ TStates => TStates,
+ Prefix => Prefix,
+ Inc_PC => Inc_PC,
+ Inc_WZ => Inc_WZ,
+ IncDec_16 => IncDec_16,
+ Read_To_Acc => Read_To_Acc,
+ Read_To_Reg => Read_To_Reg,
+ Set_BusB_To => Set_BusB_To,
+ Set_BusA_To => Set_BusA_To,
+ ALU_Op => ALU_Op,
+ Save_ALU => Save_ALU,
+ PreserveC => PreserveC,
+ Arith16 => Arith16,
+ Set_Addr_To => Set_Addr_To,
+ IORQ => IORQ_i,
+ Jump => Jump,
+ JumpE => JumpE,
+ JumpXY => JumpXY,
+ Call => Call,
+ RstP => RstP,
+ LDZ => LDZ,
+ LDW => LDW,
+ LDSPHL => LDSPHL,
+ Special_LD => Special_LD,
+ ExchangeDH => ExchangeDH,
+ ExchangeRp => ExchangeRp,
+ ExchangeAF => ExchangeAF,
+ ExchangeRS => ExchangeRS,
+ I_DJNZ => I_DJNZ,
+ I_CPL => I_CPL,
+ I_CCF => I_CCF,
+ I_SCF => I_SCF,
+ I_RETN => I_RETN,
+ I_BT => I_BT,
+ I_BC => I_BC,
+ I_BTR => I_BTR,
+ I_RLD => I_RLD,
+ I_RRD => I_RRD,
+ I_INRC => I_INRC,
+ SetDI => SetDI,
+ SetEI => SetEI,
+ IMode => IMode,
+ Halt => Halt,
+ NoRead => NoRead,
+ Write => Write);
+
+ alu : T80_ALU
+ generic map(
+ Mode => Mode,
+ Flag_C => Flag_C,
+ Flag_N => Flag_N,
+ Flag_P => Flag_P,
+ Flag_X => Flag_X,
+ Flag_H => Flag_H,
+ Flag_Y => Flag_Y,
+ Flag_Z => Flag_Z,
+ Flag_S => Flag_S)
+ port map(
+ Arith16 => Arith16_r,
+ Z16 => Z16_r,
+ ALU_Op => ALU_Op_r,
+ IR => IR(5 downto 0),
+ ISet => ISet,
+ BusA => BusA,
+ BusB => BusB,
+ F_In => F,
+ Q => ALU_Q,
+ F_Out => F_Out);
+
+ ClkEn <= CEN and not BusAck;
+
+ T_Res <= '1' when TState = unsigned(TStates) else '0';
+
+ NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
+ ((Set_Addr_To = aXY) or
+ (MCycle = "001" and IR = "11001011") or
+ (MCycle = "001" and IR = "00110110")) else '0';
+
+ Save_Mux <= BusB when ExchangeRp = '1' else
+ DI_Reg when Save_ALU_r = '0' else
+ ALU_Q;
+
+ process (RESET_n, CLK_n)
+ begin
+ if RESET_n = '0' then
+ PC <= (others => '0'); -- Program Counter
+ A <= (others => '0');
+ TmpAddr <= (others => '0');
+ IR <= "00000000";
+ ISet <= "00";
+ XY_State <= "00";
+ IStatus <= "00";
+ MCycles <= "000";
+ DO <= "00000000";
+
+ ACC <= (others => '1');
+ F <= (others => '1');
+ Ap <= (others => '1');
+ Fp <= (others => '1');
+ I <= (others => '0');
+ R <= (others => '0');
+ SP <= (others => '1');
+ Alternate <= '0';
+
+ Read_To_Reg_r <= "00000";
+ F <= (others => '1');
+ Arith16_r <= '0';
+ BTR_r <= '0';
+ Z16_r <= '0';
+ ALU_Op_r <= "0000";
+ Save_ALU_r <= '0';
+ PreserveC_r <= '0';
+ XY_Ind <= '0';
+
+ elsif CLK_n'event and CLK_n = '1' then
+
+ if ClkEn = '1' then
+
+ ALU_Op_r <= "0000";
+ Save_ALU_r <= '0';
+ Read_To_Reg_r <= "00000";
+
+ MCycles <= MCycles_d;
+
+ if IMode /= "11" then
+ IStatus <= IMode;
+ end if;
+
+ Arith16_r <= Arith16;
+ PreserveC_r <= PreserveC;
+ if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
+ Z16_r <= '1';
+ else
+ Z16_r <= '0';
+ end if;
+
+ if MCycle = "001" and TState(2) = '0' then
+ -- MCycle = 1 and TState = 1, 2, or 3
+
+ if TState = 2 and Wait_n = '1' then
+ if Mode < 2 then
+ A(7 downto 0) <= std_logic_vector(R);
+ A(15 downto 8) <= I;
+ R(6 downto 0) <= R(6 downto 0) + 1;
+ end if;
+
+ if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
+ PC <= PC + 1;
+ end if;
+
+ if IntCycle = '1' and IStatus = "01" then
+ IR <= "11111111";
+ elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
+ IR <= "00000000";
+ else
+ IR <= DInst;
+ end if;
+
+ ISet <= "00";
+ if Prefix /= "00" then
+ if Prefix = "11" then
+ if IR(5) = '1' then
+ XY_State <= "10";
+ else
+ XY_State <= "01";
+ end if;
+ else
+ if Prefix = "10" then
+ XY_State <= "00";
+ XY_Ind <= '0';
+ end if;
+ ISet <= Prefix;
+ end if;
+ else
+ XY_State <= "00";
+ XY_Ind <= '0';
+ end if;
+ end if;
+
+ else
+ -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
+
+ if MCycle = "110" then
+ XY_Ind <= '1';
+ if Prefix = "01" then
+ ISet <= "01";
+ end if;
+ end if;
+
+ if T_Res = '1' then
+ BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
+ if Jump = '1' then
+ A(15 downto 8) <= DI_Reg;
+ A(7 downto 0) <= TmpAddr(7 downto 0);
+ PC(15 downto 8) <= unsigned(DI_Reg);
+ PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+ elsif JumpXY = '1' then
+ A <= RegBusC;
+ PC <= unsigned(RegBusC);
+ elsif Call = '1' or RstP = '1' then
+ A <= TmpAddr;
+ PC <= unsigned(TmpAddr);
+ elsif MCycle = MCycles and NMICycle = '1' then
+ A <= "0000000001100110";
+ PC <= "0000000001100110";
+ elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
+ A(15 downto 8) <= I;
+ A(7 downto 0) <= TmpAddr(7 downto 0);
+ PC(15 downto 8) <= unsigned(I);
+ PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+ else
+ case Set_Addr_To is
+ when aXY =>
+ if XY_State = "00" then
+ A <= RegBusC;
+ else
+ if NextIs_XY_Fetch = '1' then
+ A <= std_logic_vector(PC);
+ else
+ A <= TmpAddr;
+ end if;
+ end if;
+ when aIOA =>
+ if Mode = 3 then
+ -- Memory map I/O on GBZ80
+ A(15 downto 8) <= (others => '1');
+ elsif Mode = 2 then
+ -- Duplicate I/O address on 8080
+ A(15 downto 8) <= DI_Reg;
+ else
+ A(15 downto 8) <= ACC;
+ end if;
+ A(7 downto 0) <= DI_Reg;
+ when aSP =>
+ A <= std_logic_vector(SP);
+ when aBC =>
+ if Mode = 3 and IORQ_i = '1' then
+ -- Memory map I/O on GBZ80
+ A(15 downto 8) <= (others => '1');
+ A(7 downto 0) <= RegBusC(7 downto 0);
+ else
+ A <= RegBusC;
+ end if;
+ when aDE =>
+ A <= RegBusC;
+ when aZI =>
+ if Inc_WZ = '1' then
+ A <= std_logic_vector(unsigned(TmpAddr) + 1);
+ else
+ A(15 downto 8) <= DI_Reg;
+ A(7 downto 0) <= TmpAddr(7 downto 0);
+ end if;
+ when others =>
+ A <= std_logic_vector(PC);
+ end case;
+ end if;
+
+ Save_ALU_r <= Save_ALU;
+ ALU_Op_r <= ALU_Op;
+
+ if I_CPL = '1' then
+ -- CPL
+ ACC <= not ACC;
+ F(Flag_Y) <= not ACC(5);
+ F(Flag_H) <= '1';
+ F(Flag_X) <= not ACC(3);
+ F(Flag_N) <= '1';
+ end if;
+ if I_CCF = '1' then
+ -- CCF
+ F(Flag_C) <= not F(Flag_C);
+ F(Flag_Y) <= ACC(5);
+ F(Flag_H) <= F(Flag_C);
+ F(Flag_X) <= ACC(3);
+ F(Flag_N) <= '0';
+ end if;
+ if I_SCF = '1' then
+ -- SCF
+ F(Flag_C) <= '1';
+ F(Flag_Y) <= ACC(5);
+ F(Flag_H) <= '0';
+ F(Flag_X) <= ACC(3);
+ F(Flag_N) <= '0';
+ end if;
+ end if;
+
+ if TState = 2 and Wait_n = '1' then
+ if ISet = "01" and MCycle = "111" then
+ IR <= DInst;
+ end if;
+ if JumpE = '1' then
+ PC <= unsigned(signed(PC) + signed(DI_Reg));
+ elsif Inc_PC = '1' then
+ PC <= PC + 1;
+ end if;
+ if BTR_r = '1' then
+ PC <= PC - 2;
+ end if;
+ if RstP = '1' then
+ TmpAddr <= (others =>'0');
+ TmpAddr(5 downto 3) <= IR(5 downto 3);
+ end if;
+ end if;
+ if TState = 3 and MCycle = "110" then
+ TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
+ end if;
+
+ if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
+ if IncDec_16(2 downto 0) = "111" then
+ if IncDec_16(3) = '1' then
+ SP <= SP - 1;
+ else
+ SP <= SP + 1;
+ end if;
+ end if;
+ end if;
+
+ if LDSPHL = '1' then
+ SP <= unsigned(RegBusC);
+ end if;
+ if ExchangeAF = '1' then
+ Ap <= ACC;
+ ACC <= Ap;
+ Fp <= F;
+ F <= Fp;
+ end if;
+ if ExchangeRS = '1' then
+ Alternate <= not Alternate;
+ end if;
+ end if;
+
+ if TState = 3 then
+ if LDZ = '1' then
+ TmpAddr(7 downto 0) <= DI_Reg;
+ end if;
+ if LDW = '1' then
+ TmpAddr(15 downto 8) <= DI_Reg;
+ end if;
+
+ if Special_LD(2) = '1' then
+ case Special_LD(1 downto 0) is
+ when "00" =>
+ ACC <= I;
+ F(Flag_P) <= IntE_FF2;
+ when "01" =>
+ ACC <= std_logic_vector(R);
+ F(Flag_P) <= IntE_FF2;
+ when "10" =>
+ I <= ACC;
+ when others =>
+ R <= unsigned(ACC);
+ end case;
+ end if;
+ end if;
+
+ if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
+ if Mode = 3 then
+ F(6) <= F_Out(6);
+ F(5) <= F_Out(5);
+ F(7) <= F_Out(7);
+ if PreserveC_r = '0' then
+ F(4) <= F_Out(4);
+ end if;
+ else
+ F(7 downto 1) <= F_Out(7 downto 1);
+ if PreserveC_r = '0' then
+ F(Flag_C) <= F_Out(0);
+ end if;
+ end if;
+ end if;
+ if T_Res = '1' and I_INRC = '1' then
+ F(Flag_H) <= '0';
+ F(Flag_N) <= '0';
+ if DI_Reg(7 downto 0) = "00000000" then
+ F(Flag_Z) <= '1';
+ else
+ F(Flag_Z) <= '0';
+ end if;
+ F(Flag_S) <= DI_Reg(7);
+ F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
+ DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
+ end if;
+
+ if TState = 1 and Auto_Wait_t1 = '0' then
+ DO <= BusB;
+ if I_RLD = '1' then
+ DO(3 downto 0) <= BusA(3 downto 0);
+ DO(7 downto 4) <= BusB(3 downto 0);
+ end if;
+ if I_RRD = '1' then
+ DO(3 downto 0) <= BusB(7 downto 4);
+ DO(7 downto 4) <= BusA(3 downto 0);
+ end if;
+ end if;
+
+ if T_Res = '1' then
+ Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
+ Read_To_Reg_r(4) <= Read_To_Reg;
+ if Read_To_Acc = '1' then
+ Read_To_Reg_r(3 downto 0) <= "0111";
+ Read_To_Reg_r(4) <= '1';
+ end if;
+ end if;
+
+ if TState = 1 and I_BT = '1' then
+ F(Flag_X) <= ALU_Q(3);
+ F(Flag_Y) <= ALU_Q(1);
+ F(Flag_H) <= '0';
+ F(Flag_N) <= '0';
+ end if;
+ if I_BC = '1' or I_BT = '1' then
+ F(Flag_P) <= IncDecZ;
+ end if;
+
+ if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or
+ (Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+ case Read_To_Reg_r is
+ when "10111" =>
+ ACC <= Save_Mux;
+ when "10110" =>
+ DO <= Save_Mux;
+ when "11000" =>
+ SP(7 downto 0) <= unsigned(Save_Mux);
+ when "11001" =>
+ SP(15 downto 8) <= unsigned(Save_Mux);
+ when "11011" =>
+ F <= Save_Mux;
+ when others =>
+ end case;
+ end if;
+
+ end if;
+
+ end if;
+
+ end process;
+
+---------------------------------------------------------------------------
+--
+-- BC('), DE('), HL('), IX and IY
+--
+---------------------------------------------------------------------------
+ process (CLK_n)
+ begin
+ if CLK_n'event and CLK_n = '1' then
+ if ClkEn = '1' then
+ -- Bus A / Write
+ RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
+ if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
+ RegAddrA_r <= XY_State(1) & "11";
+ end if;
+
+ -- Bus B
+ RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
+ if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
+ RegAddrB_r <= XY_State(1) & "11";
+ end if;
+
+ -- Address from register
+ RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
+ -- Jump (HL), LD SP,HL
+ if (JumpXY = '1' or LDSPHL = '1') then
+ RegAddrC <= Alternate & "10";
+ end if;
+ if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
+ RegAddrC <= XY_State(1) & "11";
+ end if;
+
+ if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
+ IncDecZ <= F_Out(Flag_Z);
+ end if;
+ if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
+ if ID16 = 0 then
+ IncDecZ <= '0';
+ else
+ IncDecZ <= '1';
+ end if;
+ end if;
+
+ RegBusA_r <= RegBusA;
+ end if;
+ end if;
+ end process;
+
+ RegAddrA <=
+ -- 16 bit increment/decrement
+ Alternate & IncDec_16(1 downto 0) when (TState = 2 or
+ (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
+ XY_State(1) & "11" when (TState = 2 or
+ (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
+ -- EX HL,DL
+ Alternate & "10" when ExchangeDH = '1' and TState = 3 else
+ Alternate & "01" when ExchangeDH = '1' and TState = 4 else
+ -- Bus A / Write
+ RegAddrA_r;
+
+ RegAddrB <=
+ -- EX HL,DL
+ Alternate & "01" when ExchangeDH = '1' and TState = 3 else
+ -- Bus B
+ RegAddrB_r;
+
+ ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
+ signed(RegBusA) + 1;
+
+ process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
+ ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+ begin
+ RegWEH <= '0';
+ RegWEL <= '0';
+ if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or
+ (Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+ case Read_To_Reg_r is
+ when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
+ RegWEH <= not Read_To_Reg_r(0);
+ RegWEL <= Read_To_Reg_r(0);
+ when others =>
+ end case;
+ end if;
+
+ if ExchangeDH = '1' and (TState = 3 or TState = 4) then
+ RegWEH <= '1';
+ RegWEL <= '1';
+ end if;
+
+ if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+ case IncDec_16(1 downto 0) is
+ when "00" | "01" | "10" =>
+ RegWEH <= '1';
+ RegWEL <= '1';
+ when others =>
+ end case;
+ end if;
+ end process;
+
+ process (Save_Mux, RegBusB, RegBusA_r, ID16,
+ ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+ begin
+ RegDIH <= Save_Mux;
+ RegDIL <= Save_Mux;
+
+ if ExchangeDH = '1' and TState = 3 then
+ RegDIH <= RegBusB(15 downto 8);
+ RegDIL <= RegBusB(7 downto 0);
+ end if;
+ if ExchangeDH = '1' and TState = 4 then
+ RegDIH <= RegBusA_r(15 downto 8);
+ RegDIL <= RegBusA_r(7 downto 0);
+ end if;
+
+ if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+ RegDIH <= std_logic_vector(ID16(15 downto 8));
+ RegDIL <= std_logic_vector(ID16(7 downto 0));
+ end if;
+ end process;
+
+ Regs : T80_Reg
+ port map(
+ Clk => CLK_n,
+ CEN => ClkEn,
+ WEH => RegWEH,
+ WEL => RegWEL,
+ AddrA => RegAddrA,
+ AddrB => RegAddrB,
+ AddrC => RegAddrC,
+ DIH => RegDIH,
+ DIL => RegDIL,
+ DOAH => RegBusA(15 downto 8),
+ DOAL => RegBusA(7 downto 0),
+ DOBH => RegBusB(15 downto 8),
+ DOBL => RegBusB(7 downto 0),
+ DOCH => RegBusC(15 downto 8),
+ DOCL => RegBusC(7 downto 0));
+
+---------------------------------------------------------------------------
+--
+-- Buses
+--
+---------------------------------------------------------------------------
+ process (CLK_n)
+ begin
+ if CLK_n'event and CLK_n = '1' then
+ if ClkEn = '1' then
+ case Set_BusB_To is
+ when "0111" =>
+ BusB <= ACC;
+ when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+ if Set_BusB_To(0) = '1' then
+ BusB <= RegBusB(7 downto 0);
+ else
+ BusB <= RegBusB(15 downto 8);
+ end if;
+ when "0110" =>
+ BusB <= DI_Reg;
+ when "1000" =>
+ BusB <= std_logic_vector(SP(7 downto 0));
+ when "1001" =>
+ BusB <= std_logic_vector(SP(15 downto 8));
+ when "1010" =>
+ BusB <= "00000001";
+ when "1011" =>
+ BusB <= F;
+ when "1100" =>
+ BusB <= std_logic_vector(PC(7 downto 0));
+ when "1101" =>
+ BusB <= std_logic_vector(PC(15 downto 8));
+ when "1110" =>
+ BusB <= "00000000";
+ when others =>
+ BusB <= "--------";
+ end case;
+
+ case Set_BusA_To is
+ when "0111" =>
+ BusA <= ACC;
+ when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+ if Set_BusA_To(0) = '1' then
+ BusA <= RegBusA(7 downto 0);
+ else
+ BusA <= RegBusA(15 downto 8);
+ end if;
+ when "0110" =>
+ BusA <= DI_Reg;
+ when "1000" =>
+ BusA <= std_logic_vector(SP(7 downto 0));
+ when "1001" =>
+ BusA <= std_logic_vector(SP(15 downto 8));
+ when "1010" =>
+ BusA <= "00000000";
+ when others =>
+ BusB <= "--------";
+ end case;
+ end if;
+ end if;
+ end process;
+
+---------------------------------------------------------------------------
+--
+-- Generate external control signals
+--
+---------------------------------------------------------------------------
+ process (RESET_n,CLK_n)
+ begin
+ if RESET_n = '0' then
+ RFSH_n <= '1';
+ elsif CLK_n'event and CLK_n = '1' then
+ if CEN = '1' then
+ if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then
+ RFSH_n <= '0';
+ else
+ RFSH_n <= '1';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ MC <= std_logic_vector(MCycle);
+ TS <= std_logic_vector(TState);
+ DI_Reg <= DI;
+ HALT_n <= not Halt_FF;
+ BUSAK_n <= not BusAck;
+ IntCycle_n <= not IntCycle;
+ IntE <= IntE_FF1;
+ IORQ <= IORQ_i;
+ Stop <= I_DJNZ;
+
+-------------------------------------------------------------------------
+--
+-- Syncronise inputs
+--
+-------------------------------------------------------------------------
+ process (RESET_n, CLK_n)
+ variable OldNMI_n : std_logic;
+ begin
+ if RESET_n = '0' then
+ BusReq_s <= '0';
+ INT_s <= '0';
+ NMI_s <= '0';
+ OldNMI_n := '0';
+ elsif CLK_n'event and CLK_n = '1' then
+ if CEN = '1' then
+ BusReq_s <= not BUSRQ_n;
+ INT_s <= not INT_n;
+ if NMICycle = '1' then
+ NMI_s <= '0';
+ elsif NMI_n = '0' and OldNMI_n = '1' then
+ NMI_s <= '1';
+ end if;
+ OldNMI_n := NMI_n;
+ end if;
+ end if;
+ end process;
+
+-------------------------------------------------------------------------
+--
+-- Main state machine
+--
+-------------------------------------------------------------------------
+ process (RESET_n, CLK_n)
+ begin
+ if RESET_n = '0' then
+ MCycle <= "001";
+ TState <= "000";
+ Pre_XY_F_M <= "000";
+ Halt_FF <= '0';
+ BusAck <= '0';
+ NMICycle <= '0';
+ IntCycle <= '0';
+ IntE_FF1 <= '0';
+ IntE_FF2 <= '0';
+ No_BTR <= '0';
+ Auto_Wait_t1 <= '0';
+ Auto_Wait_t2 <= '0';
+ M1_n <= '1';
+ elsif CLK_n'event and CLK_n = '1' then
+ if CEN = '1' then
+ if T_Res = '1' then
+ Auto_Wait_t1 <= '0';
+ else
+ Auto_Wait_t1 <= Auto_Wait or IORQ_i;
+ end if;
+ Auto_Wait_t2 <= Auto_Wait_t1;
+ No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
+ (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
+ (I_BTR and (not IR(4) or F(Flag_Z)));
+ if TState = 2 then
+ if SetEI = '1' then
+ IntE_FF1 <= '1';
+ IntE_FF2 <= '1';
+ end if;
+ if I_RETN = '1' then
+ IntE_FF1 <= IntE_FF2;
+ end if;
+ end if;
+ if TState = 3 then
+ if SetDI = '1' then
+ IntE_FF1 <= '0';
+ IntE_FF2 <= '0';
+ end if;
+ end if;
+ if IntCycle = '1' or NMICycle = '1' then
+ Halt_FF <= '0';
+ end if;
+ if MCycle = "001" and TState = 2 and Wait_n = '1' then
+ M1_n <= '1';
+ end if;
+ if BusReq_s = '1' and BusAck = '1' then
+ else
+ BusAck <= '0';
+ if TState = 2 and Wait_n = '0' then
+ elsif T_Res = '1' then
+ if Halt = '1' then
+ Halt_FF <= '1';
+ end if;
+ if BusReq_s = '1' then
+ BusAck <= '1';
+ else
+ TState <= "001";
+ if NextIs_XY_Fetch = '1' then
+ MCycle <= "110";
+ Pre_XY_F_M <= MCycle;
+ if IR = "00110110" and Mode = 0 then
+ Pre_XY_F_M <= "010";
+ end if;
+ elsif (MCycle = "111") or
+ (MCycle = "110" and Mode = 1 and ISet /= "01") then
+ MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
+ elsif (MCycle = MCycles) or
+ No_BTR = '1' or
+ (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
+ M1_n <= '0';
+ MCycle <= "001";
+ IntCycle <= '0';
+ NMICycle <= '0';
+ if NMI_s = '1' and Prefix = "00" then
+ NMICycle <= '1';
+ IntE_FF1 <= '0';
+ elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
+ IntCycle <= '1';
+ IntE_FF1 <= '0';
+ IntE_FF2 <= '0';
+ end if;
+ else
+ MCycle <= std_logic_vector(unsigned(MCycle) + 1);
+ end if;
+ end if;
+ else
+ if (Auto_Wait = '1' and Auto_Wait_t2 = '0') nor
+ (IOWait = 1 and IORQ_i = '1' and Auto_Wait_t1 = '0') then
+ TState <= TState + 1;
+ end if;
+ end if;
+ end if;
+ if TState = 0 then
+ M1_n <= '0';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ process (IntCycle, NMICycle, MCycle)
+ begin
+ Auto_Wait <= '0';
+ if IntCycle = '1' or NMICycle = '1' then
+ if MCycle = "001" then
+ Auto_Wait <= '1';
+ end if;
+ end if;
+ end process;
+
+end;
diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/NinjaKun_MiST/rtl/cpu/T80_ALU.vhd
new file mode 100644
index 00000000..86fddce7
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/rtl/cpu/T80_ALU.vhd
@@ -0,0 +1,351 @@
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+-- 0238 : Fixed zero flag for 16 bit SBC and ADC
+--
+-- 0240 : Added GB operations
+--
+-- 0242 : Cleanup
+--
+-- 0247 : Cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_ALU is
+ generic(
+ Mode : integer := 0;
+ Flag_C : integer := 0;
+ Flag_N : integer := 1;
+ Flag_P : integer := 2;
+ Flag_X : integer := 3;
+ Flag_H : integer := 4;
+ Flag_Y : integer := 5;
+ Flag_Z : integer := 6;
+ Flag_S : integer := 7
+ );
+ port(
+ Arith16 : in std_logic;
+ Z16 : in std_logic;
+ ALU_Op : in std_logic_vector(3 downto 0);
+ IR : in std_logic_vector(5 downto 0);
+ ISet : in std_logic_vector(1 downto 0);
+ BusA : in std_logic_vector(7 downto 0);
+ BusB : in std_logic_vector(7 downto 0);
+ F_In : in std_logic_vector(7 downto 0);
+ Q : out std_logic_vector(7 downto 0);
+ F_Out : out std_logic_vector(7 downto 0)
+ );
+end T80_ALU;
+
+architecture rtl of T80_ALU is
+
+ procedure AddSub(A : std_logic_vector;
+ B : std_logic_vector;
+ Sub : std_logic;
+ Carry_In : std_logic;
+ signal Res : out std_logic_vector;
+ signal Carry : out std_logic) is
+ variable B_i : unsigned(A'length - 1 downto 0);
+ variable Res_i : unsigned(A'length + 1 downto 0);
+ begin
+ if Sub = '1' then
+ B_i := not unsigned(B);
+ else
+ B_i := unsigned(B);
+ end if;
+ Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
+ Carry <= Res_i(A'length + 1);
+ Res <= std_logic_vector(Res_i(A'length downto 1));
+ end;
+
+ -- AddSub variables (temporary signals)
+ signal UseCarry : std_logic;
+ signal Carry7_v : std_logic;
+ signal Overflow_v : std_logic;
+ signal HalfCarry_v : std_logic;
+ signal Carry_v : std_logic;
+ signal Q_v : std_logic_vector(7 downto 0);
+
+ signal BitMask : std_logic_vector(7 downto 0);
+
+begin
+
+ with IR(5 downto 3) select BitMask <= "00000001" when "000",
+ "00000010" when "001",
+ "00000100" when "010",
+ "00001000" when "011",
+ "00010000" when "100",
+ "00100000" when "101",
+ "01000000" when "110",
+ "10000000" when others;
+
+ UseCarry <= not ALU_Op(2) and ALU_Op(0);
+ AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
+ AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
+ AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
+ OverFlow_v <= Carry_v xor Carry7_v;
+
+ process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
+ variable Q_t : std_logic_vector(7 downto 0);
+ variable DAA_Q : unsigned(8 downto 0);
+ begin
+ Q_t := "--------";
+ F_Out <= F_In;
+ DAA_Q := "---------";
+ case ALU_Op is
+ when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
+ F_Out(Flag_N) <= '0';
+ F_Out(Flag_C) <= '0';
+ case ALU_OP(2 downto 0) is
+ when "000" | "001" => -- ADD, ADC
+ Q_t := Q_v;
+ F_Out(Flag_C) <= Carry_v;
+ F_Out(Flag_H) <= HalfCarry_v;
+ F_Out(Flag_P) <= OverFlow_v;
+ when "010" | "011" | "111" => -- SUB, SBC, CP
+ Q_t := Q_v;
+ F_Out(Flag_N) <= '1';
+ F_Out(Flag_C) <= not Carry_v;
+ F_Out(Flag_H) <= not HalfCarry_v;
+ F_Out(Flag_P) <= OverFlow_v;
+ when "100" => -- AND
+ Q_t(7 downto 0) := BusA and BusB;
+ F_Out(Flag_H) <= '1';
+ when "101" => -- XOR
+ Q_t(7 downto 0) := BusA xor BusB;
+ F_Out(Flag_H) <= '0';
+ when others => -- OR "110"
+ Q_t(7 downto 0) := BusA or BusB;
+ F_Out(Flag_H) <= '0';
+ end case;
+ if ALU_Op(2 downto 0) = "111" then -- CP
+ F_Out(Flag_X) <= BusB(3);
+ F_Out(Flag_Y) <= BusB(5);
+ else
+ F_Out(Flag_X) <= Q_t(3);
+ F_Out(Flag_Y) <= Q_t(5);
+ end if;
+ if Q_t(7 downto 0) = "00000000" then
+ F_Out(Flag_Z) <= '1';
+ if Z16 = '1' then
+ F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
+ end if;
+ else
+ F_Out(Flag_Z) <= '0';
+ end if;
+ F_Out(Flag_S) <= Q_t(7);
+ case ALU_Op(2 downto 0) is
+ when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
+ when others =>
+ F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+ Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+ end case;
+ if Arith16 = '1' then
+ F_Out(Flag_S) <= F_In(Flag_S);
+ F_Out(Flag_Z) <= F_In(Flag_Z);
+ F_Out(Flag_P) <= F_In(Flag_P);
+ end if;
+ when "1100" =>
+ -- DAA
+ F_Out(Flag_H) <= F_In(Flag_H);
+ F_Out(Flag_C) <= F_In(Flag_C);
+ DAA_Q(7 downto 0) := unsigned(BusA);
+ DAA_Q(8) := '0';
+ if F_In(Flag_N) = '0' then
+ -- After addition
+ -- Alow > 9 or H = 1
+ if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+ if (DAA_Q(3 downto 0) > 9) then
+ F_Out(Flag_H) <= '1';
+ else
+ F_Out(Flag_H) <= '0';
+ end if;
+ DAA_Q := DAA_Q + 6;
+ end if;
+ -- new Ahigh > 9 or C = 1
+ if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
+ DAA_Q := DAA_Q + 96; -- 0x60
+ end if;
+ else
+ -- After subtraction
+ if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+ if DAA_Q(3 downto 0) > 5 then
+ F_Out(Flag_H) <= '0';
+ end if;
+ DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
+ end if;
+ if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
+ DAA_Q := DAA_Q - 352; -- 0x160
+ end if;
+ end if;
+ F_Out(Flag_X) <= DAA_Q(3);
+ F_Out(Flag_Y) <= DAA_Q(5);
+ F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
+ Q_t := std_logic_vector(DAA_Q(7 downto 0));
+ if DAA_Q(7 downto 0) = "00000000" then
+ F_Out(Flag_Z) <= '1';
+ else
+ F_Out(Flag_Z) <= '0';
+ end if;
+ F_Out(Flag_S) <= DAA_Q(7);
+ F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
+ DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
+ when "1101" | "1110" =>
+ -- RLD, RRD
+ Q_t(7 downto 4) := BusA(7 downto 4);
+ if ALU_Op(0) = '1' then
+ Q_t(3 downto 0) := BusB(7 downto 4);
+ else
+ Q_t(3 downto 0) := BusB(3 downto 0);
+ end if;
+ F_Out(Flag_H) <= '0';
+ F_Out(Flag_N) <= '0';
+ F_Out(Flag_X) <= Q_t(3);
+ F_Out(Flag_Y) <= Q_t(5);
+ if Q_t(7 downto 0) = "00000000" then
+ F_Out(Flag_Z) <= '1';
+ else
+ F_Out(Flag_Z) <= '0';
+ end if;
+ F_Out(Flag_S) <= Q_t(7);
+ F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+ Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+ when "1001" =>
+ -- BIT
+ Q_t(7 downto 0) := BusB and BitMask;
+ F_Out(Flag_S) <= Q_t(7);
+ if Q_t(7 downto 0) = "00000000" then
+ F_Out(Flag_Z) <= '1';
+ F_Out(Flag_P) <= '1';
+ else
+ F_Out(Flag_Z) <= '0';
+ F_Out(Flag_P) <= '0';
+ end if;
+ F_Out(Flag_H) <= '1';
+ F_Out(Flag_N) <= '0';
+ F_Out(Flag_X) <= '0';
+ F_Out(Flag_Y) <= '0';
+ if IR(2 downto 0) /= "110" then
+ F_Out(Flag_X) <= BusB(3);
+ F_Out(Flag_Y) <= BusB(5);
+ end if;
+ when "1010" =>
+ -- SET
+ Q_t(7 downto 0) := BusB or BitMask;
+ when "1011" =>
+ -- RES
+ Q_t(7 downto 0) := BusB and not BitMask;
+ when "1000" =>
+ -- ROT
+ case IR(5 downto 3) is
+ when "000" => -- RLC
+ Q_t(7 downto 1) := BusA(6 downto 0);
+ Q_t(0) := BusA(7);
+ F_Out(Flag_C) <= BusA(7);
+ when "010" => -- RL
+ Q_t(7 downto 1) := BusA(6 downto 0);
+ Q_t(0) := F_In(Flag_C);
+ F_Out(Flag_C) <= BusA(7);
+ when "001" => -- RRC
+ Q_t(6 downto 0) := BusA(7 downto 1);
+ Q_t(7) := BusA(0);
+ F_Out(Flag_C) <= BusA(0);
+ when "011" => -- RR
+ Q_t(6 downto 0) := BusA(7 downto 1);
+ Q_t(7) := F_In(Flag_C);
+ F_Out(Flag_C) <= BusA(0);
+ when "100" => -- SLA
+ Q_t(7 downto 1) := BusA(6 downto 0);
+ Q_t(0) := '0';
+ F_Out(Flag_C) <= BusA(7);
+ when "110" => -- SLL (Undocumented) / SWAP
+ if Mode = 3 then
+ Q_t(7 downto 4) := BusA(3 downto 0);
+ Q_t(3 downto 0) := BusA(7 downto 4);
+ F_Out(Flag_C) <= '0';
+ else
+ Q_t(7 downto 1) := BusA(6 downto 0);
+ Q_t(0) := '1';
+ F_Out(Flag_C) <= BusA(7);
+ end if;
+ when "101" => -- SRA
+ Q_t(6 downto 0) := BusA(7 downto 1);
+ Q_t(7) := BusA(7);
+ F_Out(Flag_C) <= BusA(0);
+ when others => -- SRL
+ Q_t(6 downto 0) := BusA(7 downto 1);
+ Q_t(7) := '0';
+ F_Out(Flag_C) <= BusA(0);
+ end case;
+ F_Out(Flag_H) <= '0';
+ F_Out(Flag_N) <= '0';
+ F_Out(Flag_X) <= Q_t(3);
+ F_Out(Flag_Y) <= Q_t(5);
+ F_Out(Flag_S) <= Q_t(7);
+ if Q_t(7 downto 0) = "00000000" then
+ F_Out(Flag_Z) <= '1';
+ else
+ F_Out(Flag_Z) <= '0';
+ end if;
+ F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+ Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+ if ISet = "00" then
+ F_Out(Flag_P) <= F_In(Flag_P);
+ F_Out(Flag_S) <= F_In(Flag_S);
+ F_Out(Flag_Z) <= F_In(Flag_Z);
+ end if;
+ when others =>
+ null;
+ end case;
+ Q <= Q_t;
+ end process;
+
+end;
diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/NinjaKun_MiST/rtl/cpu/T80_MCode.vhd
new file mode 100644
index 00000000..4cc30f35
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/rtl/cpu/T80_MCode.vhd
@@ -0,0 +1,1934 @@
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+-- 0208 : First complete release
+--
+-- 0211 : Fixed IM 1
+--
+-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+-- 0235 : Added IM 2 fix by Mike Johnson
+--
+-- 0238 : Added NoRead signal
+--
+-- 0238b: Fixed instruction timing for POP and DJNZ
+--
+-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
+--
+-- 0242 : Fixed I/O instruction timing, cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_MCode is
+ generic(
+ Mode : integer := 0;
+ Flag_C : integer := 0;
+ Flag_N : integer := 1;
+ Flag_P : integer := 2;
+ Flag_X : integer := 3;
+ Flag_H : integer := 4;
+ Flag_Y : integer := 5;
+ Flag_Z : integer := 6;
+ Flag_S : integer := 7
+ );
+ port(
+ IR : in std_logic_vector(7 downto 0);
+ ISet : in std_logic_vector(1 downto 0);
+ MCycle : in std_logic_vector(2 downto 0);
+ F : in std_logic_vector(7 downto 0);
+ NMICycle : in std_logic;
+ IntCycle : in std_logic;
+ MCycles : out std_logic_vector(2 downto 0);
+ TStates : out std_logic_vector(2 downto 0);
+ Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+ Inc_PC : out std_logic;
+ Inc_WZ : out std_logic;
+ IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
+ Read_To_Reg : out std_logic;
+ Read_To_Acc : out std_logic;
+ Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+ Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+ ALU_Op : out std_logic_vector(3 downto 0);
+ -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+ Save_ALU : out std_logic;
+ PreserveC : out std_logic;
+ Arith16 : out std_logic;
+ Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+ IORQ : out std_logic;
+ Jump : out std_logic;
+ JumpE : out std_logic;
+ JumpXY : out std_logic;
+ Call : out std_logic;
+ RstP : out std_logic;
+ LDZ : out std_logic;
+ LDW : out std_logic;
+ LDSPHL : out std_logic;
+ Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+ ExchangeDH : out std_logic;
+ ExchangeRp : out std_logic;
+ ExchangeAF : out std_logic;
+ ExchangeRS : out std_logic;
+ I_DJNZ : out std_logic;
+ I_CPL : out std_logic;
+ I_CCF : out std_logic;
+ I_SCF : out std_logic;
+ I_RETN : out std_logic;
+ I_BT : out std_logic;
+ I_BC : out std_logic;
+ I_BTR : out std_logic;
+ I_RLD : out std_logic;
+ I_RRD : out std_logic;
+ I_INRC : out std_logic;
+ SetDI : out std_logic;
+ SetEI : out std_logic;
+ IMode : out std_logic_vector(1 downto 0);
+ Halt : out std_logic;
+ NoRead : out std_logic;
+ Write : out std_logic
+ );
+end T80_MCode;
+
+architecture rtl of T80_MCode is
+
+ constant aNone : std_logic_vector(2 downto 0) := "111";
+ constant aBC : std_logic_vector(2 downto 0) := "000";
+ constant aDE : std_logic_vector(2 downto 0) := "001";
+ constant aXY : std_logic_vector(2 downto 0) := "010";
+ constant aIOA : std_logic_vector(2 downto 0) := "100";
+ constant aSP : std_logic_vector(2 downto 0) := "101";
+ constant aZI : std_logic_vector(2 downto 0) := "110";
+-- constant aNone : std_logic_vector(2 downto 0) := "000";
+-- constant aXY : std_logic_vector(2 downto 0) := "001";
+-- constant aIOA : std_logic_vector(2 downto 0) := "010";
+-- constant aSP : std_logic_vector(2 downto 0) := "011";
+-- constant aBC : std_logic_vector(2 downto 0) := "100";
+-- constant aDE : std_logic_vector(2 downto 0) := "101";
+-- constant aZI : std_logic_vector(2 downto 0) := "110";
+
+ function is_cc_true(
+ F : std_logic_vector(7 downto 0);
+ cc : bit_vector(2 downto 0)
+ ) return boolean is
+ begin
+ if Mode = 3 then
+ case cc is
+ when "000" => return F(7) = '0'; -- NZ
+ when "001" => return F(7) = '1'; -- Z
+ when "010" => return F(4) = '0'; -- NC
+ when "011" => return F(4) = '1'; -- C
+ when "100" => return false;
+ when "101" => return false;
+ when "110" => return false;
+ when "111" => return false;
+ end case;
+ else
+ case cc is
+ when "000" => return F(6) = '0'; -- NZ
+ when "001" => return F(6) = '1'; -- Z
+ when "010" => return F(0) = '0'; -- NC
+ when "011" => return F(0) = '1'; -- C
+ when "100" => return F(2) = '0'; -- PO
+ when "101" => return F(2) = '1'; -- PE
+ when "110" => return F(7) = '0'; -- P
+ when "111" => return F(7) = '1'; -- M
+ end case;
+ end if;
+ end;
+
+begin
+
+ process (IR, ISet, MCycle, F, NMICycle, IntCycle)
+ variable DDD : std_logic_vector(2 downto 0);
+ variable SSS : std_logic_vector(2 downto 0);
+ variable DPair : std_logic_vector(1 downto 0);
+ variable IRB : bit_vector(7 downto 0);
+ begin
+ DDD := IR(5 downto 3);
+ SSS := IR(2 downto 0);
+ DPair := IR(5 downto 4);
+ IRB := to_bitvector(IR);
+
+ MCycles <= "001";
+ if MCycle = "001" then
+ TStates <= "100";
+ else
+ TStates <= "011";
+ end if;
+ Prefix <= "00";
+ Inc_PC <= '0';
+ Inc_WZ <= '0';
+ IncDec_16 <= "0000";
+ Read_To_Acc <= '0';
+ Read_To_Reg <= '0';
+ Set_BusB_To <= "0000";
+ Set_BusA_To <= "0000";
+ ALU_Op <= "0" & IR(5 downto 3);
+ Save_ALU <= '0';
+ PreserveC <= '0';
+ Arith16 <= '0';
+ IORQ <= '0';
+ Set_Addr_To <= aNone;
+ Jump <= '0';
+ JumpE <= '0';
+ JumpXY <= '0';
+ Call <= '0';
+ RstP <= '0';
+ LDZ <= '0';
+ LDW <= '0';
+ LDSPHL <= '0';
+ Special_LD <= "000";
+ ExchangeDH <= '0';
+ ExchangeRp <= '0';
+ ExchangeAF <= '0';
+ ExchangeRS <= '0';
+ I_DJNZ <= '0';
+ I_CPL <= '0';
+ I_CCF <= '0';
+ I_SCF <= '0';
+ I_RETN <= '0';
+ I_BT <= '0';
+ I_BC <= '0';
+ I_BTR <= '0';
+ I_RLD <= '0';
+ I_RRD <= '0';
+ I_INRC <= '0';
+ SetDI <= '0';
+ SetEI <= '0';
+ IMode <= "11";
+ Halt <= '0';
+ NoRead <= '0';
+ Write <= '0';
+
+ case ISet is
+ when "00" =>
+
+------------------------------------------------------------------------------
+--
+-- Unprefixed instructions
+--
+------------------------------------------------------------------------------
+
+ case IRB is
+-- 8 BIT LOAD GROUP
+ when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+ |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+ |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+ |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+ |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+ |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+ |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+ -- LD r,r'
+ Set_BusB_To(2 downto 0) <= SSS;
+ ExchangeRp <= '1';
+ Set_BusA_To(2 downto 0) <= DDD;
+ Read_To_Reg <= '1';
+ when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
+ -- LD r,n
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ Set_BusA_To(2 downto 0) <= DDD;
+ Read_To_Reg <= '1';
+ when others => null;
+ end case;
+ when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
+ -- LD r,(HL)
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aXY;
+ when 2 =>
+ Set_BusA_To(2 downto 0) <= DDD;
+ Read_To_Reg <= '1';
+ when others => null;
+ end case;
+ when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
+ -- LD (HL),r
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aXY;
+ Set_BusB_To(2 downto 0) <= SSS;
+ Set_BusB_To(3) <= '0';
+ when 2 =>
+ Write <= '1';
+ when others => null;
+ end case;
+ when "00110110" =>
+ -- LD (HL),n
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ Set_Addr_To <= aXY;
+ Set_BusB_To(2 downto 0) <= SSS;
+ Set_BusB_To(3) <= '0';
+ when 3 =>
+ Write <= '1';
+ when others => null;
+ end case;
+ when "00001010" =>
+ -- LD A,(BC)
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aBC;
+ when 2 =>
+ Read_To_Acc <= '1';
+ when others => null;
+ end case;
+ when "00011010" =>
+ -- LD A,(DE)
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aDE;
+ when 2 =>
+ Read_To_Acc <= '1';
+ when others => null;
+ end case;
+ when "00111010" =>
+ if Mode = 3 then
+ -- LDD A,(HL)
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aXY;
+ when 2 =>
+ Read_To_Acc <= '1';
+ IncDec_16 <= "1110";
+ when others => null;
+ end case;
+ else
+ -- LD A,(nn)
+ MCycles <= "100";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 3 =>
+ Set_Addr_To <= aZI;
+ Inc_PC <= '1';
+ when 4 =>
+ Read_To_Acc <= '1';
+ when others => null;
+ end case;
+ end if;
+ when "00000010" =>
+ -- LD (BC),A
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aBC;
+ Set_BusB_To <= "0111";
+ when 2 =>
+ Write <= '1';
+ when others => null;
+ end case;
+ when "00010010" =>
+ -- LD (DE),A
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aDE;
+ Set_BusB_To <= "0111";
+ when 2 =>
+ Write <= '1';
+ when others => null;
+ end case;
+ when "00110010" =>
+ if Mode = 3 then
+ -- LDD (HL),A
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aXY;
+ Set_BusB_To <= "0111";
+ when 2 =>
+ Write <= '1';
+ IncDec_16 <= "1110";
+ when others => null;
+ end case;
+ else
+ -- LD (nn),A
+ MCycles <= "100";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 3 =>
+ Set_Addr_To <= aZI;
+ Inc_PC <= '1';
+ Set_BusB_To <= "0111";
+ when 4 =>
+ Write <= '1';
+ when others => null;
+ end case;
+ end if;
+
+-- 16 BIT LOAD GROUP
+ when "00000001"|"00010001"|"00100001"|"00110001" =>
+ -- LD dd,nn
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ Read_To_Reg <= '1';
+ if DPAIR = "11" then
+ Set_BusA_To(3 downto 0) <= "1000";
+ else
+ Set_BusA_To(2 downto 1) <= DPAIR;
+ Set_BusA_To(0) <= '1';
+ end if;
+ when 3 =>
+ Inc_PC <= '1';
+ Read_To_Reg <= '1';
+ if DPAIR = "11" then
+ Set_BusA_To(3 downto 0) <= "1001";
+ else
+ Set_BusA_To(2 downto 1) <= DPAIR;
+ Set_BusA_To(0) <= '0';
+ end if;
+ when others => null;
+ end case;
+ when "00101010" =>
+ if Mode = 3 then
+ -- LDI A,(HL)
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aXY;
+ when 2 =>
+ Read_To_Acc <= '1';
+ IncDec_16 <= "0110";
+ when others => null;
+ end case;
+ else
+ -- LD HL,(nn)
+ MCycles <= "101";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 3 =>
+ Set_Addr_To <= aZI;
+ Inc_PC <= '1';
+ LDW <= '1';
+ when 4 =>
+ Set_BusA_To(2 downto 0) <= "101"; -- L
+ Read_To_Reg <= '1';
+ Inc_WZ <= '1';
+ Set_Addr_To <= aZI;
+ when 5 =>
+ Set_BusA_To(2 downto 0) <= "100"; -- H
+ Read_To_Reg <= '1';
+ when others => null;
+ end case;
+ end if;
+ when "00100010" =>
+ if Mode = 3 then
+ -- LDI (HL),A
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aXY;
+ Set_BusB_To <= "0111";
+ when 2 =>
+ Write <= '1';
+ IncDec_16 <= "0110";
+ when others => null;
+ end case;
+ else
+ -- LD (nn),HL
+ MCycles <= "101";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 3 =>
+ Set_Addr_To <= aZI;
+ Inc_PC <= '1';
+ LDW <= '1';
+ Set_BusB_To <= "0101"; -- L
+ when 4 =>
+ Inc_WZ <= '1';
+ Set_Addr_To <= aZI;
+ Write <= '1';
+ Set_BusB_To <= "0100"; -- H
+ when 5 =>
+ Write <= '1';
+ when others => null;
+ end case;
+ end if;
+ when "11111001" =>
+ -- LD SP,HL
+ TStates <= "110";
+ LDSPHL <= '1';
+ when "11000101"|"11010101"|"11100101"|"11110101" =>
+ -- PUSH qq
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ TStates <= "101";
+ IncDec_16 <= "1111";
+ Set_Addr_TO <= aSP;
+ if DPAIR = "11" then
+ Set_BusB_To <= "0111";
+ else
+ Set_BusB_To(2 downto 1) <= DPAIR;
+ Set_BusB_To(0) <= '0';
+ Set_BusB_To(3) <= '0';
+ end if;
+ when 2 =>
+ IncDec_16 <= "1111";
+ Set_Addr_To <= aSP;
+ if DPAIR = "11" then
+ Set_BusB_To <= "1011";
+ else
+ Set_BusB_To(2 downto 1) <= DPAIR;
+ Set_BusB_To(0) <= '1';
+ Set_BusB_To(3) <= '0';
+ end if;
+ Write <= '1';
+ when 3 =>
+ Write <= '1';
+ when others => null;
+ end case;
+ when "11000001"|"11010001"|"11100001"|"11110001" =>
+ -- POP qq
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aSP;
+ when 2 =>
+ IncDec_16 <= "0111";
+ Set_Addr_To <= aSP;
+ Read_To_Reg <= '1';
+ if DPAIR = "11" then
+ Set_BusA_To(3 downto 0) <= "1011";
+ else
+ Set_BusA_To(2 downto 1) <= DPAIR;
+ Set_BusA_To(0) <= '1';
+ end if;
+ when 3 =>
+ IncDec_16 <= "0111";
+ Read_To_Reg <= '1';
+ if DPAIR = "11" then
+ Set_BusA_To(3 downto 0) <= "0111";
+ else
+ Set_BusA_To(2 downto 1) <= DPAIR;
+ Set_BusA_To(0) <= '0';
+ end if;
+ when others => null;
+ end case;
+
+-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
+ when "11101011" =>
+ if Mode /= 3 then
+ -- EX DE,HL
+ ExchangeDH <= '1';
+ end if;
+ when "00001000" =>
+ if Mode = 3 then
+ -- LD (nn),SP
+ MCycles <= "101";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 3 =>
+ Set_Addr_To <= aZI;
+ Inc_PC <= '1';
+ LDW <= '1';
+ Set_BusB_To <= "1000";
+ when 4 =>
+ Inc_WZ <= '1';
+ Set_Addr_To <= aZI;
+ Write <= '1';
+ Set_BusB_To <= "1001";
+ when 5 =>
+ Write <= '1';
+ when others => null;
+ end case;
+ elsif Mode < 2 then
+ -- EX AF,AF'
+ ExchangeAF <= '1';
+ end if;
+ when "11011001" =>
+ if Mode = 3 then
+ -- RETI
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_TO <= aSP;
+ when 2 =>
+ IncDec_16 <= "0111";
+ Set_Addr_To <= aSP;
+ LDZ <= '1';
+ when 3 =>
+ Jump <= '1';
+ IncDec_16 <= "0111";
+ I_RETN <= '1';
+ SetEI <= '1';
+ when others => null;
+ end case;
+ elsif Mode < 2 then
+ -- EXX
+ ExchangeRS <= '1';
+ end if;
+ when "11100011" =>
+ if Mode /= 3 then
+ -- EX (SP),HL
+ MCycles <= "101";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aSP;
+ when 2 =>
+ Read_To_Reg <= '1';
+ Set_BusA_To <= "0101";
+ Set_BusB_To <= "0101";
+ Set_Addr_To <= aSP;
+ when 3 =>
+ IncDec_16 <= "0111";
+ Set_Addr_To <= aSP;
+ TStates <= "100";
+ Write <= '1';
+ when 4 =>
+ Read_To_Reg <= '1';
+ Set_BusA_To <= "0100";
+ Set_BusB_To <= "0100";
+ Set_Addr_To <= aSP;
+ when 5 =>
+ IncDec_16 <= "1111";
+ TStates <= "101";
+ Write <= '1';
+ when others => null;
+ end case;
+ end if;
+
+-- 8 BIT ARITHMETIC AND LOGICAL GROUP
+ when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+ |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+ |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+ |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+ |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+ |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+ |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+ |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+ -- ADD A,r
+ -- ADC A,r
+ -- SUB A,r
+ -- SBC A,r
+ -- AND A,r
+ -- OR A,r
+ -- XOR A,r
+ -- CP A,r
+ Set_BusB_To(2 downto 0) <= SSS;
+ Set_BusA_To(2 downto 0) <= "111";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+ -- ADD A,(HL)
+ -- ADC A,(HL)
+ -- SUB A,(HL)
+ -- SBC A,(HL)
+ -- AND A,(HL)
+ -- OR A,(HL)
+ -- XOR A,(HL)
+ -- CP A,(HL)
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aXY;
+ when 2 =>
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ Set_BusB_To(2 downto 0) <= SSS;
+ Set_BusA_To(2 downto 0) <= "111";
+ when others => null;
+ end case;
+ when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+ -- ADD A,n
+ -- ADC A,n
+ -- SUB A,n
+ -- SBC A,n
+ -- AND A,n
+ -- OR A,n
+ -- XOR A,n
+ -- CP A,n
+ MCycles <= "010";
+ if MCycle = "010" then
+ Inc_PC <= '1';
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ Set_BusB_To(2 downto 0) <= SSS;
+ Set_BusA_To(2 downto 0) <= "111";
+ end if;
+ when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
+ -- INC r
+ Set_BusB_To <= "1010";
+ Set_BusA_To(2 downto 0) <= DDD;
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ PreserveC <= '1';
+ ALU_Op <= "0000";
+ when "00110100" =>
+ -- INC (HL)
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aXY;
+ when 2 =>
+ TStates <= "100";
+ Set_Addr_To <= aXY;
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ PreserveC <= '1';
+ ALU_Op <= "0000";
+ Set_BusB_To <= "1010";
+ Set_BusA_To(2 downto 0) <= DDD;
+ when 3 =>
+ Write <= '1';
+ when others => null;
+ end case;
+ when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
+ -- DEC r
+ Set_BusB_To <= "1010";
+ Set_BusA_To(2 downto 0) <= DDD;
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ PreserveC <= '1';
+ ALU_Op <= "0010";
+ when "00110101" =>
+ -- DEC (HL)
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aXY;
+ when 2 =>
+ TStates <= "100";
+ Set_Addr_To <= aXY;
+ ALU_Op <= "0010";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ PreserveC <= '1';
+ Set_BusB_To <= "1010";
+ Set_BusA_To(2 downto 0) <= DDD;
+ when 3 =>
+ Write <= '1';
+ when others => null;
+ end case;
+
+-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
+ when "00100111" =>
+ -- DAA
+ Set_BusA_To(2 downto 0) <= "111";
+ Read_To_Reg <= '1';
+ ALU_Op <= "1100";
+ Save_ALU <= '1';
+ when "00101111" =>
+ -- CPL
+ I_CPL <= '1';
+ when "00111111" =>
+ -- CCF
+ I_CCF <= '1';
+ when "00110111" =>
+ -- SCF
+ I_SCF <= '1';
+ when "00000000" =>
+ if NMICycle = '1' then
+ -- NMI
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ TStates <= "101";
+ IncDec_16 <= "1111";
+ Set_Addr_To <= aSP;
+ Set_BusB_To <= "1101";
+ when 2 =>
+ TStates <= "100";
+ Write <= '1';
+ IncDec_16 <= "1111";
+ Set_Addr_To <= aSP;
+ Set_BusB_To <= "1100";
+ when 3 =>
+ TStates <= "100";
+ Write <= '1';
+ when others => null;
+ end case;
+ elsif IntCycle = '1' then
+ -- INT (IM 2)
+ MCycles <= "101";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ LDZ <= '1';
+ TStates <= "101";
+ IncDec_16 <= "1111";
+ Set_Addr_To <= aSP;
+ Set_BusB_To <= "1101";
+ when 2 =>
+ TStates <= "100";
+ Write <= '1';
+ IncDec_16 <= "1111";
+ Set_Addr_To <= aSP;
+ Set_BusB_To <= "1100";
+ when 3 =>
+ TStates <= "100";
+ Write <= '1';
+ when 4 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 5 =>
+ Jump <= '1';
+ when others => null;
+ end case;
+ else
+ -- NOP
+ end if;
+ when "01110110" =>
+ -- HALT
+ Halt <= '1';
+ when "11110011" =>
+ -- DI
+ SetDI <= '1';
+ when "11111011" =>
+ -- EI
+ SetEI <= '1';
+
+-- 16 BIT ARITHMETIC GROUP
+ when "00001001"|"00011001"|"00101001"|"00111001" =>
+ -- ADD HL,ss
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ NoRead <= '1';
+ ALU_Op <= "0000";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ Set_BusA_To(2 downto 0) <= "101";
+ case to_integer(unsigned(IR(5 downto 4))) is
+ when 0|1|2 =>
+ Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+ Set_BusB_To(0) <= '1';
+ when others =>
+ Set_BusB_To <= "1000";
+ end case;
+ TStates <= "100";
+ Arith16 <= '1';
+ when 3 =>
+ NoRead <= '1';
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ ALU_Op <= "0001";
+ Set_BusA_To(2 downto 0) <= "100";
+ case to_integer(unsigned(IR(5 downto 4))) is
+ when 0|1|2 =>
+ Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+ when others =>
+ Set_BusB_To <= "1001";
+ end case;
+ Arith16 <= '1';
+ when others =>
+ end case;
+ when "00000011"|"00010011"|"00100011"|"00110011" =>
+ -- INC ss
+ TStates <= "110";
+ IncDec_16(3 downto 2) <= "01";
+ IncDec_16(1 downto 0) <= DPair;
+ when "00001011"|"00011011"|"00101011"|"00111011" =>
+ -- DEC ss
+ TStates <= "110";
+ IncDec_16(3 downto 2) <= "11";
+ IncDec_16(1 downto 0) <= DPair;
+
+-- ROTATE AND SHIFT GROUP
+ when "00000111"
+ -- RLCA
+ |"00010111"
+ -- RLA
+ |"00001111"
+ -- RRCA
+ |"00011111" =>
+ -- RRA
+ Set_BusA_To(2 downto 0) <= "111";
+ ALU_Op <= "1000";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+
+-- JUMP GROUP
+ when "11000011" =>
+ -- JP nn
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 3 =>
+ Inc_PC <= '1';
+ Jump <= '1';
+ when others => null;
+ end case;
+ when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
+ if IR(5) = '1' and Mode = 3 then
+ case IRB(4 downto 3) is
+ when "00" =>
+ -- LD ($FF00+C),A
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aBC;
+ Set_BusB_To <= "0111";
+ when 2 =>
+ Write <= '1';
+ IORQ <= '1';
+ when others =>
+ end case;
+ when "01" =>
+ -- LD (nn),A
+ MCycles <= "100";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 3 =>
+ Set_Addr_To <= aZI;
+ Inc_PC <= '1';
+ Set_BusB_To <= "0111";
+ when 4 =>
+ Write <= '1';
+ when others => null;
+ end case;
+ when "10" =>
+ -- LD A,($FF00+C)
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aBC;
+ when 2 =>
+ Read_To_Acc <= '1';
+ IORQ <= '1';
+ when others =>
+ end case;
+ when "11" =>
+ -- LD A,(nn)
+ MCycles <= "100";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 3 =>
+ Set_Addr_To <= aZI;
+ Inc_PC <= '1';
+ when 4 =>
+ Read_To_Acc <= '1';
+ when others => null;
+ end case;
+ end case;
+ else
+ -- JP cc,nn
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 3 =>
+ Inc_PC <= '1';
+ if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+ Jump <= '1';
+ end if;
+ when others => null;
+ end case;
+ end if;
+ when "00011000" =>
+ if Mode /= 2 then
+ -- JR e
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ when 3 =>
+ NoRead <= '1';
+ JumpE <= '1';
+ TStates <= "101";
+ when others => null;
+ end case;
+ end if;
+ when "00111000" =>
+ if Mode /= 2 then
+ -- JR C,e
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ if F(Flag_C) = '0' then
+ MCycles <= "010";
+ end if;
+ when 3 =>
+ NoRead <= '1';
+ JumpE <= '1';
+ TStates <= "101";
+ when others => null;
+ end case;
+ end if;
+ when "00110000" =>
+ if Mode /= 2 then
+ -- JR NC,e
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ if F(Flag_C) = '1' then
+ MCycles <= "010";
+ end if;
+ when 3 =>
+ NoRead <= '1';
+ JumpE <= '1';
+ TStates <= "101";
+ when others => null;
+ end case;
+ end if;
+ when "00101000" =>
+ if Mode /= 2 then
+ -- JR Z,e
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ if F(Flag_Z) = '0' then
+ MCycles <= "010";
+ end if;
+ when 3 =>
+ NoRead <= '1';
+ JumpE <= '1';
+ TStates <= "101";
+ when others => null;
+ end case;
+ end if;
+ when "00100000" =>
+ if Mode /= 2 then
+ -- JR NZ,e
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ if F(Flag_Z) = '1' then
+ MCycles <= "010";
+ end if;
+ when 3 =>
+ NoRead <= '1';
+ JumpE <= '1';
+ TStates <= "101";
+ when others => null;
+ end case;
+ end if;
+ when "11101001" =>
+ -- JP (HL)
+ JumpXY <= '1';
+ when "00010000" =>
+ if Mode = 3 then
+ I_DJNZ <= '1';
+ elsif Mode < 2 then
+ -- DJNZ,e
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ TStates <= "101";
+ I_DJNZ <= '1';
+ Set_BusB_To <= "1010";
+ Set_BusA_To(2 downto 0) <= "000";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ ALU_Op <= "0010";
+ when 2 =>
+ I_DJNZ <= '1';
+ Inc_PC <= '1';
+ when 3 =>
+ NoRead <= '1';
+ JumpE <= '1';
+ TStates <= "101";
+ when others => null;
+ end case;
+ end if;
+
+-- CALL AND RETURN GROUP
+ when "11001101" =>
+ -- CALL nn
+ MCycles <= "101";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 3 =>
+ IncDec_16 <= "1111";
+ Inc_PC <= '1';
+ TStates <= "100";
+ Set_Addr_To <= aSP;
+ LDW <= '1';
+ Set_BusB_To <= "1101";
+ when 4 =>
+ Write <= '1';
+ IncDec_16 <= "1111";
+ Set_Addr_To <= aSP;
+ Set_BusB_To <= "1100";
+ when 5 =>
+ Write <= '1';
+ Call <= '1';
+ when others => null;
+ end case;
+ when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
+ if IR(5) = '0' or Mode /= 3 then
+ -- CALL cc,nn
+ MCycles <= "101";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 3 =>
+ Inc_PC <= '1';
+ LDW <= '1';
+ if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+ IncDec_16 <= "1111";
+ Set_Addr_TO <= aSP;
+ TStates <= "100";
+ Set_BusB_To <= "1101";
+ else
+ MCycles <= "011";
+ end if;
+ when 4 =>
+ Write <= '1';
+ IncDec_16 <= "1111";
+ Set_Addr_To <= aSP;
+ Set_BusB_To <= "1100";
+ when 5 =>
+ Write <= '1';
+ Call <= '1';
+ when others => null;
+ end case;
+ end if;
+ when "11001001" =>
+ -- RET
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ TStates <= "101";
+ Set_Addr_TO <= aSP;
+ when 2 =>
+ IncDec_16 <= "0111";
+ Set_Addr_To <= aSP;
+ LDZ <= '1';
+ when 3 =>
+ Jump <= '1';
+ IncDec_16 <= "0111";
+ when others => null;
+ end case;
+ when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
+ if IR(5) = '1' and Mode = 3 then
+ case IRB(4 downto 3) is
+ when "00" =>
+ -- LD ($FF00+nn),A
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ Set_Addr_To <= aIOA;
+ Set_BusB_To <= "0111";
+ when 3 =>
+ Write <= '1';
+ when others => null;
+ end case;
+ when "01" =>
+ -- ADD SP,n
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ ALU_Op <= "0000";
+ Inc_PC <= '1';
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ Set_BusA_To <= "1000";
+ Set_BusB_To <= "0110";
+ when 3 =>
+ NoRead <= '1';
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ ALU_Op <= "0001";
+ Set_BusA_To <= "1001";
+ Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
+ when others =>
+ end case;
+ when "10" =>
+ -- LD A,($FF00+nn)
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ Set_Addr_To <= aIOA;
+ when 3 =>
+ Read_To_Acc <= '1';
+ when others => null;
+ end case;
+ when "11" =>
+ -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!!
+ MCycles <= "101";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 3 =>
+ Set_Addr_To <= aZI;
+ Inc_PC <= '1';
+ LDW <= '1';
+ when 4 =>
+ Set_BusA_To(2 downto 0) <= "101"; -- L
+ Read_To_Reg <= '1';
+ Inc_WZ <= '1';
+ Set_Addr_To <= aZI;
+ when 5 =>
+ Set_BusA_To(2 downto 0) <= "100"; -- H
+ Read_To_Reg <= '1';
+ when others => null;
+ end case;
+ end case;
+ else
+ -- RET cc
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+ Set_Addr_TO <= aSP;
+ else
+ MCycles <= "001";
+ end if;
+ TStates <= "101";
+ when 2 =>
+ IncDec_16 <= "0111";
+ Set_Addr_To <= aSP;
+ LDZ <= '1';
+ when 3 =>
+ Jump <= '1';
+ IncDec_16 <= "0111";
+ when others => null;
+ end case;
+ end if;
+ when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
+ -- RST p
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ TStates <= "101";
+ IncDec_16 <= "1111";
+ Set_Addr_To <= aSP;
+ Set_BusB_To <= "1101";
+ when 2 =>
+ Write <= '1';
+ IncDec_16 <= "1111";
+ Set_Addr_To <= aSP;
+ Set_BusB_To <= "1100";
+ when 3 =>
+ Write <= '1';
+ RstP <= '1';
+ when others => null;
+ end case;
+
+-- INPUT AND OUTPUT GROUP
+ when "11011011" =>
+ if Mode /= 3 then
+ -- IN A,(n)
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ Set_Addr_To <= aIOA;
+ when 3 =>
+ Read_To_Acc <= '1';
+ IORQ <= '1';
+ when others => null;
+ end case;
+ end if;
+ when "11010011" =>
+ if Mode /= 3 then
+ -- OUT (n),A
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ Set_Addr_To <= aIOA;
+ Set_BusB_To <= "0111";
+ when 3 =>
+ Write <= '1';
+ IORQ <= '1';
+ when others => null;
+ end case;
+ end if;
+
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+-- MULTIBYTE INSTRUCTIONS
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+
+ when "11001011" =>
+ if Mode /= 2 then
+ Prefix <= "01";
+ end if;
+
+ when "11101101" =>
+ if Mode < 2 then
+ Prefix <= "10";
+ end if;
+
+ when "11011101"|"11111101" =>
+ if Mode < 2 then
+ Prefix <= "11";
+ end if;
+
+ end case;
+
+ when "01" =>
+
+------------------------------------------------------------------------------
+--
+-- CB prefixed instructions
+--
+------------------------------------------------------------------------------
+
+ Set_BusA_To(2 downto 0) <= IR(2 downto 0);
+ Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+
+ case IRB is
+ when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
+ |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
+ |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
+ |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
+ |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
+ |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
+ |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
+ |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
+ -- RLC r
+ -- RL r
+ -- RRC r
+ -- RR r
+ -- SLA r
+ -- SRA r
+ -- SRL r
+ -- SLL r (Undocumented) / SWAP r
+ if MCycle = "001" then
+ ALU_Op <= "1000";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ end if;
+ when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
+ -- RLC (HL)
+ -- RL (HL)
+ -- RRC (HL)
+ -- RR (HL)
+ -- SRA (HL)
+ -- SRL (HL)
+ -- SLA (HL)
+ -- SLL (HL) (Undocumented) / SWAP (HL)
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 1 | 7 =>
+ Set_Addr_To <= aXY;
+ when 2 =>
+ ALU_Op <= "1000";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ Set_Addr_To <= aXY;
+ TStates <= "100";
+ when 3 =>
+ Write <= '1';
+ when others =>
+ end case;
+ when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+ |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+ |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+ |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+ |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+ |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+ |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
+ |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+ -- BIT b,r
+ if MCycle = "001" then
+ Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+ ALU_Op <= "1001";
+ end if;
+ when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
+ -- BIT b,(HL)
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 | 7 =>
+ Set_Addr_To <= aXY;
+ when 2 =>
+ ALU_Op <= "1001";
+ TStates <= "100";
+ when others =>
+ end case;
+ when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
+ |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
+ |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
+ |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
+ |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
+ |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
+ |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
+ |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
+ -- SET b,r
+ if MCycle = "001" then
+ ALU_Op <= "1010";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ end if;
+ when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+ -- SET b,(HL)
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 1 | 7 =>
+ Set_Addr_To <= aXY;
+ when 2 =>
+ ALU_Op <= "1010";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ Set_Addr_To <= aXY;
+ TStates <= "100";
+ when 3 =>
+ Write <= '1';
+ when others =>
+ end case;
+ when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+ |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+ |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+ |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+ |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+ |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+ |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+ |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+ -- RES b,r
+ if MCycle = "001" then
+ ALU_Op <= "1011";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ end if;
+ when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+ -- RES b,(HL)
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 1 | 7 =>
+ Set_Addr_To <= aXY;
+ when 2 =>
+ ALU_Op <= "1011";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ Set_Addr_To <= aXY;
+ TStates <= "100";
+ when 3 =>
+ Write <= '1';
+ when others =>
+ end case;
+ end case;
+
+ when others =>
+
+------------------------------------------------------------------------------
+--
+-- ED prefixed instructions
+--
+------------------------------------------------------------------------------
+
+ case IRB is
+ when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
+ |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
+ |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
+ |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
+ |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
+ |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
+ |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
+ |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
+
+
+ |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
+ |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
+ |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
+ |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
+ | "10100100"|"10100101"|"10100110"|"10100111"
+ | "10101100"|"10101101"|"10101110"|"10101111"
+ | "10110100"|"10110101"|"10110110"|"10110111"
+ | "10111100"|"10111101"|"10111110"|"10111111"
+ |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
+ |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
+ |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
+ |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
+ |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
+ |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
+ |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
+ |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
+ null; -- NOP, undocumented
+ when "01111110"|"01111111" =>
+ -- NOP, undocumented
+ null;
+-- 8 BIT LOAD GROUP
+ when "01010111" =>
+ -- LD A,I
+ Special_LD <= "100";
+ TStates <= "101";
+ when "01011111" =>
+ -- LD A,R
+ Special_LD <= "101";
+ TStates <= "101";
+ when "01000111" =>
+ -- LD I,A
+ Special_LD <= "110";
+ TStates <= "101";
+ when "01001111" =>
+ -- LD R,A
+ Special_LD <= "111";
+ TStates <= "101";
+-- 16 BIT LOAD GROUP
+ when "01001011"|"01011011"|"01101011"|"01111011" =>
+ -- LD dd,(nn)
+ MCycles <= "101";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 3 =>
+ Set_Addr_To <= aZI;
+ Inc_PC <= '1';
+ LDW <= '1';
+ when 4 =>
+ Read_To_Reg <= '1';
+ if IR(5 downto 4) = "11" then
+ Set_BusA_To <= "1000";
+ else
+ Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+ Set_BusA_To(0) <= '1';
+ end if;
+ Inc_WZ <= '1';
+ Set_Addr_To <= aZI;
+ when 5 =>
+ Read_To_Reg <= '1';
+ if IR(5 downto 4) = "11" then
+ Set_BusA_To <= "1001";
+ else
+ Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+ Set_BusA_To(0) <= '0';
+ end if;
+ when others => null;
+ end case;
+ when "01000011"|"01010011"|"01100011"|"01110011" =>
+ -- LD (nn),dd
+ MCycles <= "101";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Inc_PC <= '1';
+ LDZ <= '1';
+ when 3 =>
+ Set_Addr_To <= aZI;
+ Inc_PC <= '1';
+ LDW <= '1';
+ if IR(5 downto 4) = "11" then
+ Set_BusB_To <= "1000";
+ else
+ Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+ Set_BusB_To(0) <= '1';
+ Set_BusB_To(3) <= '0';
+ end if;
+ when 4 =>
+ Inc_WZ <= '1';
+ Set_Addr_To <= aZI;
+ Write <= '1';
+ if IR(5 downto 4) = "11" then
+ Set_BusB_To <= "1001";
+ else
+ Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+ Set_BusB_To(0) <= '0';
+ Set_BusB_To(3) <= '0';
+ end if;
+ when 5 =>
+ Write <= '1';
+ when others => null;
+ end case;
+ when "10100000" | "10101000" | "10110000" | "10111000" =>
+ -- LDI, LDD, LDIR, LDDR
+ MCycles <= "100";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aXY;
+ IncDec_16 <= "1100"; -- BC
+ when 2 =>
+ Set_BusB_To <= "0110";
+ Set_BusA_To(2 downto 0) <= "111";
+ ALU_Op <= "0000";
+ Set_Addr_To <= aDE;
+ if IR(3) = '0' then
+ IncDec_16 <= "0110"; -- IX
+ else
+ IncDec_16 <= "1110";
+ end if;
+ when 3 =>
+ I_BT <= '1';
+ TStates <= "101";
+ Write <= '1';
+ if IR(3) = '0' then
+ IncDec_16 <= "0101"; -- DE
+ else
+ IncDec_16 <= "1101";
+ end if;
+ when 4 =>
+ NoRead <= '1';
+ TStates <= "101";
+ when others => null;
+ end case;
+ when "10100001" | "10101001" | "10110001" | "10111001" =>
+ -- CPI, CPD, CPIR, CPDR
+ MCycles <= "100";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aXY;
+ IncDec_16 <= "1100"; -- BC
+ when 2 =>
+ Set_BusB_To <= "0110";
+ Set_BusA_To(2 downto 0) <= "111";
+ ALU_Op <= "0111";
+ Save_ALU <= '1';
+ PreserveC <= '1';
+ if IR(3) = '0' then
+ IncDec_16 <= "0110";
+ else
+ IncDec_16 <= "1110";
+ end if;
+ when 3 =>
+ NoRead <= '1';
+ I_BC <= '1';
+ TStates <= "101";
+ when 4 =>
+ NoRead <= '1';
+ TStates <= "101";
+ when others => null;
+ end case;
+ when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
+ -- NEG
+ Alu_OP <= "0010";
+ Set_BusB_To <= "0111";
+ Set_BusA_To <= "1010";
+ Read_To_Acc <= '1';
+ Save_ALU <= '1';
+ when "01000110"|"01001110"|"01100110"|"01101110" =>
+ -- IM 0
+ IMode <= "00";
+ when "01010110"|"01110110" =>
+ -- IM 1
+ IMode <= "01";
+ when "01011110"|"01110111" =>
+ -- IM 2
+ IMode <= "10";
+-- 16 bit arithmetic
+ when "01001010"|"01011010"|"01101010"|"01111010" =>
+ -- ADC HL,ss
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ NoRead <= '1';
+ ALU_Op <= "0001";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ Set_BusA_To(2 downto 0) <= "101";
+ case to_integer(unsigned(IR(5 downto 4))) is
+ when 0|1|2 =>
+ Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+ Set_BusB_To(0) <= '1';
+ when others =>
+ Set_BusB_To <= "1000";
+ end case;
+ TStates <= "100";
+ when 3 =>
+ NoRead <= '1';
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ ALU_Op <= "0001";
+ Set_BusA_To(2 downto 0) <= "100";
+ case to_integer(unsigned(IR(5 downto 4))) is
+ when 0|1|2 =>
+ Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+ Set_BusB_To(0) <= '0';
+ when others =>
+ Set_BusB_To <= "1001";
+ end case;
+ when others =>
+ end case;
+ when "01000010"|"01010010"|"01100010"|"01110010" =>
+ -- SBC HL,ss
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ NoRead <= '1';
+ ALU_Op <= "0011";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ Set_BusA_To(2 downto 0) <= "101";
+ case to_integer(unsigned(IR(5 downto 4))) is
+ when 0|1|2 =>
+ Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+ Set_BusB_To(0) <= '1';
+ when others =>
+ Set_BusB_To <= "1000";
+ end case;
+ TStates <= "100";
+ when 3 =>
+ NoRead <= '1';
+ ALU_Op <= "0011";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ Set_BusA_To(2 downto 0) <= "100";
+ case to_integer(unsigned(IR(5 downto 4))) is
+ when 0|1|2 =>
+ Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+ when others =>
+ Set_BusB_To <= "1001";
+ end case;
+ when others =>
+ end case;
+ when "01101111" =>
+ -- RLD
+ MCycles <= "100";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ NoRead <= '1';
+ Set_Addr_To <= aXY;
+ when 3 =>
+ Read_To_Reg <= '1';
+ Set_BusB_To(2 downto 0) <= "110";
+ Set_BusA_To(2 downto 0) <= "111";
+ ALU_Op <= "1101";
+ TStates <= "100";
+ Set_Addr_To <= aXY;
+ Save_ALU <= '1';
+ when 4 =>
+ I_RLD <= '1';
+ Write <= '1';
+ when others =>
+ end case;
+ when "01100111" =>
+ -- RRD
+ MCycles <= "100";
+ case to_integer(unsigned(MCycle)) is
+ when 2 =>
+ Set_Addr_To <= aXY;
+ when 3 =>
+ Read_To_Reg <= '1';
+ Set_BusB_To(2 downto 0) <= "110";
+ Set_BusA_To(2 downto 0) <= "111";
+ ALU_Op <= "1110";
+ TStates <= "100";
+ Set_Addr_To <= aXY;
+ Save_ALU <= '1';
+ when 4 =>
+ I_RRD <= '1';
+ Write <= '1';
+ when others =>
+ end case;
+ when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
+ -- RETI, RETN
+ MCycles <= "011";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_TO <= aSP;
+ when 2 =>
+ IncDec_16 <= "0111";
+ Set_Addr_To <= aSP;
+ LDZ <= '1';
+ when 3 =>
+ Jump <= '1';
+ IncDec_16 <= "0111";
+ I_RETN <= '1';
+ when others => null;
+ end case;
+ when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
+ -- IN r,(C)
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aBC;
+ when 2 =>
+ IORQ <= '1';
+ if IR(5 downto 3) /= "110" then
+ Read_To_Reg <= '1';
+ Set_BusA_To(2 downto 0) <= IR(5 downto 3);
+ end if;
+ I_INRC <= '1';
+ when others =>
+ end case;
+ when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
+ -- OUT (C),r
+ -- OUT (C),0
+ MCycles <= "010";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aBC;
+ Set_BusB_To(2 downto 0) <= IR(5 downto 3);
+ if IR(5 downto 3) = "110" then
+ Set_BusB_To(3) <= '1';
+ end if;
+ when 2 =>
+ Write <= '1';
+ IORQ <= '1';
+ when others =>
+ end case;
+ when "10100010" | "10101010" | "10110010" | "10111010" =>
+ -- INI, IND, INIR, INDR
+ MCycles <= "100";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ Set_Addr_To <= aBC;
+ Set_BusB_To <= "1010";
+ Set_BusA_To <= "0000";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ ALU_Op <= "0010";
+ when 2 =>
+ IORQ <= '1';
+ Set_BusB_To <= "0110";
+ Set_Addr_To <= aXY;
+ when 3 =>
+ if IR(3) = '0' then
+ IncDec_16 <= "0010";
+ else
+ IncDec_16 <= "1010";
+ end if;
+ TStates <= "100";
+ Write <= '1';
+ I_BTR <= '1';
+ when 4 =>
+ NoRead <= '1';
+ TStates <= "101";
+ when others => null;
+ end case;
+ when "10100011" | "10101011" | "10110011" | "10111011" =>
+ -- OUTI, OUTD, OTIR, OTDR
+ MCycles <= "100";
+ case to_integer(unsigned(MCycle)) is
+ when 1 =>
+ TStates <= "101";
+ Set_Addr_To <= aXY;
+ Set_BusB_To <= "1010";
+ Set_BusA_To <= "0000";
+ Read_To_Reg <= '1';
+ Save_ALU <= '1';
+ ALU_Op <= "0010";
+ when 2 =>
+ Set_BusB_To <= "0110";
+ Set_Addr_To <= aBC;
+ when 3 =>
+ if IR(3) = '0' then
+ IncDec_16 <= "0010";
+ else
+ IncDec_16 <= "1010";
+ end if;
+ IORQ <= '1';
+ Write <= '1';
+ I_BTR <= '1';
+ when 4 =>
+ NoRead <= '1';
+ TStates <= "101";
+ when others => null;
+ end case;
+ end case;
+
+ end case;
+
+ if Mode = 1 then
+ if MCycle = "001" then
+-- TStates <= "100";
+ else
+ TStates <= "011";
+ end if;
+ end if;
+
+ if Mode = 3 then
+ if MCycle = "001" then
+-- TStates <= "100";
+ else
+ TStates <= "100";
+ end if;
+ end if;
+
+ if Mode < 2 then
+ if MCycle = "110" then
+ Inc_PC <= '1';
+ if Mode = 1 then
+ Set_Addr_To <= aXY;
+ TStates <= "100";
+ Set_BusB_To(2 downto 0) <= SSS;
+ Set_BusB_To(3) <= '0';
+ end if;
+ if IRB = "00110110" or IRB = "11001011" then
+ Set_Addr_To <= aNone;
+ end if;
+ end if;
+ if MCycle = "111" then
+ if Mode = 0 then
+ TStates <= "101";
+ end if;
+ if ISet /= "01" then
+ Set_Addr_To <= aXY;
+ end if;
+ Set_BusB_To(2 downto 0) <= SSS;
+ Set_BusB_To(3) <= '0';
+ if IRB = "00110110" or ISet = "01" then
+ -- LD (HL),n
+ Inc_PC <= '1';
+ else
+ NoRead <= '1';
+ end if;
+ end if;
+ end if;
+
+ end process;
+
+end;
diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/NinjaKun_MiST/rtl/cpu/T80_Pack.vhd
new file mode 100644
index 00000000..ac7d34da
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/rtl/cpu/T80_Pack.vhd
@@ -0,0 +1,208 @@
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package T80_Pack is
+
+ component T80
+ generic(
+ Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+ IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
+ Flag_C : integer := 0;
+ Flag_N : integer := 1;
+ Flag_P : integer := 2;
+ Flag_X : integer := 3;
+ Flag_H : integer := 4;
+ Flag_Y : integer := 5;
+ Flag_Z : integer := 6;
+ Flag_S : integer := 7
+ );
+ port(
+ RESET_n : in std_logic;
+ CLK_n : in std_logic;
+ CEN : in std_logic;
+ WAIT_n : in std_logic;
+ INT_n : in std_logic;
+ NMI_n : in std_logic;
+ BUSRQ_n : in std_logic;
+ M1_n : out std_logic;
+ IORQ : out std_logic;
+ NoRead : out std_logic;
+ Write : out std_logic;
+ RFSH_n : out std_logic;
+ HALT_n : out std_logic;
+ BUSAK_n : out std_logic;
+ A : out std_logic_vector(15 downto 0);
+ DInst : in std_logic_vector(7 downto 0);
+ DI : in std_logic_vector(7 downto 0);
+ DO : out std_logic_vector(7 downto 0);
+ MC : out std_logic_vector(2 downto 0);
+ TS : out std_logic_vector(2 downto 0);
+ IntCycle_n : out std_logic;
+ IntE : out std_logic;
+ Stop : out std_logic
+ );
+ end component;
+
+ component T80_Reg
+ port(
+ Clk : in std_logic;
+ CEN : in std_logic;
+ WEH : in std_logic;
+ WEL : in std_logic;
+ AddrA : in std_logic_vector(2 downto 0);
+ AddrB : in std_logic_vector(2 downto 0);
+ AddrC : in std_logic_vector(2 downto 0);
+ DIH : in std_logic_vector(7 downto 0);
+ DIL : in std_logic_vector(7 downto 0);
+ DOAH : out std_logic_vector(7 downto 0);
+ DOAL : out std_logic_vector(7 downto 0);
+ DOBH : out std_logic_vector(7 downto 0);
+ DOBL : out std_logic_vector(7 downto 0);
+ DOCH : out std_logic_vector(7 downto 0);
+ DOCL : out std_logic_vector(7 downto 0)
+ );
+ end component;
+
+ component T80_MCode
+ generic(
+ Mode : integer := 0;
+ Flag_C : integer := 0;
+ Flag_N : integer := 1;
+ Flag_P : integer := 2;
+ Flag_X : integer := 3;
+ Flag_H : integer := 4;
+ Flag_Y : integer := 5;
+ Flag_Z : integer := 6;
+ Flag_S : integer := 7
+ );
+ port(
+ IR : in std_logic_vector(7 downto 0);
+ ISet : in std_logic_vector(1 downto 0);
+ MCycle : in std_logic_vector(2 downto 0);
+ F : in std_logic_vector(7 downto 0);
+ NMICycle : in std_logic;
+ IntCycle : in std_logic;
+ MCycles : out std_logic_vector(2 downto 0);
+ TStates : out std_logic_vector(2 downto 0);
+ Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+ Inc_PC : out std_logic;
+ Inc_WZ : out std_logic;
+ IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
+ Read_To_Reg : out std_logic;
+ Read_To_Acc : out std_logic;
+ Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+ Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+ ALU_Op : out std_logic_vector(3 downto 0);
+ -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+ Save_ALU : out std_logic;
+ PreserveC : out std_logic;
+ Arith16 : out std_logic;
+ Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+ IORQ : out std_logic;
+ Jump : out std_logic;
+ JumpE : out std_logic;
+ JumpXY : out std_logic;
+ Call : out std_logic;
+ RstP : out std_logic;
+ LDZ : out std_logic;
+ LDW : out std_logic;
+ LDSPHL : out std_logic;
+ Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+ ExchangeDH : out std_logic;
+ ExchangeRp : out std_logic;
+ ExchangeAF : out std_logic;
+ ExchangeRS : out std_logic;
+ I_DJNZ : out std_logic;
+ I_CPL : out std_logic;
+ I_CCF : out std_logic;
+ I_SCF : out std_logic;
+ I_RETN : out std_logic;
+ I_BT : out std_logic;
+ I_BC : out std_logic;
+ I_BTR : out std_logic;
+ I_RLD : out std_logic;
+ I_RRD : out std_logic;
+ I_INRC : out std_logic;
+ SetDI : out std_logic;
+ SetEI : out std_logic;
+ IMode : out std_logic_vector(1 downto 0);
+ Halt : out std_logic;
+ NoRead : out std_logic;
+ Write : out std_logic
+ );
+ end component;
+
+ component T80_ALU
+ generic(
+ Mode : integer := 0;
+ Flag_C : integer := 0;
+ Flag_N : integer := 1;
+ Flag_P : integer := 2;
+ Flag_X : integer := 3;
+ Flag_H : integer := 4;
+ Flag_Y : integer := 5;
+ Flag_Z : integer := 6;
+ Flag_S : integer := 7
+ );
+ port(
+ Arith16 : in std_logic;
+ Z16 : in std_logic;
+ ALU_Op : in std_logic_vector(3 downto 0);
+ IR : in std_logic_vector(5 downto 0);
+ ISet : in std_logic_vector(1 downto 0);
+ BusA : in std_logic_vector(7 downto 0);
+ BusB : in std_logic_vector(7 downto 0);
+ F_In : in std_logic_vector(7 downto 0);
+ Q : out std_logic_vector(7 downto 0);
+ F_Out : out std_logic_vector(7 downto 0)
+ );
+ end component;
+
+end;
diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/NinjaKun_MiST/rtl/cpu/T80_Reg.vhd
new file mode 100644
index 00000000..828485fb
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/rtl/cpu/T80_Reg.vhd
@@ -0,0 +1,105 @@
+--
+-- T80 Registers, technology independent
+--
+-- Version : 0244
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+-- 0242 : Initial release
+--
+-- 0244 : Changed to single register file
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_Reg is
+ port(
+ Clk : in std_logic;
+ CEN : in std_logic;
+ WEH : in std_logic;
+ WEL : in std_logic;
+ AddrA : in std_logic_vector(2 downto 0);
+ AddrB : in std_logic_vector(2 downto 0);
+ AddrC : in std_logic_vector(2 downto 0);
+ DIH : in std_logic_vector(7 downto 0);
+ DIL : in std_logic_vector(7 downto 0);
+ DOAH : out std_logic_vector(7 downto 0);
+ DOAL : out std_logic_vector(7 downto 0);
+ DOBH : out std_logic_vector(7 downto 0);
+ DOBL : out std_logic_vector(7 downto 0);
+ DOCH : out std_logic_vector(7 downto 0);
+ DOCL : out std_logic_vector(7 downto 0)
+ );
+end T80_Reg;
+
+architecture rtl of T80_Reg is
+
+ type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
+ signal RegsH : Register_Image(0 to 7);
+ signal RegsL : Register_Image(0 to 7);
+
+begin
+
+ process (Clk)
+ begin
+ if Clk'event and Clk = '1' then
+ if CEN = '1' then
+ if WEH = '1' then
+ RegsH(to_integer(unsigned(AddrA))) <= DIH;
+ end if;
+ if WEL = '1' then
+ RegsL(to_integer(unsigned(AddrA))) <= DIL;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ DOAH <= RegsH(to_integer(unsigned(AddrA)));
+ DOAL <= RegsL(to_integer(unsigned(AddrA)));
+ DOBH <= RegsH(to_integer(unsigned(AddrB)));
+ DOBL <= RegsL(to_integer(unsigned(AddrB)));
+ DOCH <= RegsH(to_integer(unsigned(AddrC)));
+ DOCL <= RegsL(to_integer(unsigned(AddrC)));
+
+end;
diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/cpu/T80s.vhd b/Arcade_MiST/NinjaKun_MiST/rtl/cpu/T80s.vhd
new file mode 100644
index 00000000..5b612110
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/rtl/cpu/T80s.vhd
@@ -0,0 +1,190 @@
+--
+-- Z80 compatible microprocessor core, synchronous top level
+-- Different timing than the original z80
+-- Inputs needs to be synchronous and outputs may glitch
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+-- 0208 : First complete release
+--
+-- 0210 : Fixed read with wait
+--
+-- 0211 : Fixed interrupt cycle
+--
+-- 0235 : Updated for T80 interface change
+--
+-- 0236 : Added T2Write generic
+--
+-- 0237 : Fixed T2Write with wait state
+--
+-- 0238 : Updated for T80 interface change
+--
+-- 0240 : Updated for T80 interface change
+--
+-- 0242 : Updated for T80 interface change
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80s is
+ generic(
+ Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+ T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
+ IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
+ );
+ port(
+ RESET_n : in std_logic;
+ CLK_n : in std_logic;
+ WAIT_n : in std_logic;
+ INT_n : in std_logic;
+ NMI_n : in std_logic;
+ BUSRQ_n : in std_logic;
+ M1_n : out std_logic;
+ MREQ_n : out std_logic;
+ IORQ_n : out std_logic;
+ RD_n : out std_logic;
+ WR_n : out std_logic;
+ RFSH_n : out std_logic;
+ HALT_n : out std_logic;
+ BUSAK_n : out std_logic;
+ A : out std_logic_vector(15 downto 0);
+ DI : in std_logic_vector(7 downto 0);
+ DO : out std_logic_vector(7 downto 0)
+ );
+end T80s;
+
+architecture rtl of T80s is
+
+ signal CEN : std_logic;
+ signal IntCycle_n : std_logic;
+ signal NoRead : std_logic;
+ signal Write : std_logic;
+ signal IORQ : std_logic;
+ signal DI_Reg : std_logic_vector(7 downto 0);
+ signal MCycle : std_logic_vector(2 downto 0);
+ signal TState : std_logic_vector(2 downto 0);
+
+begin
+
+ CEN <= '1';
+
+ u0 : T80
+ generic map(
+ Mode => Mode,
+ IOWait => IOWait)
+ port map(
+ CEN => CEN,
+ M1_n => M1_n,
+ IORQ => IORQ,
+ NoRead => NoRead,
+ Write => Write,
+ RFSH_n => RFSH_n,
+ HALT_n => HALT_n,
+ WAIT_n => Wait_n,
+ INT_n => INT_n,
+ NMI_n => NMI_n,
+ RESET_n => RESET_n,
+ BUSRQ_n => BUSRQ_n,
+ BUSAK_n => BUSAK_n,
+ CLK_n => CLK_n,
+ A => A,
+ DInst => DI,
+ DI => DI_Reg,
+ DO => DO,
+ MC => MCycle,
+ TS => TState,
+ IntCycle_n => IntCycle_n);
+
+ process (RESET_n, CLK_n)
+ begin
+ if RESET_n = '0' then
+ RD_n <= '1';
+ WR_n <= '1';
+ IORQ_n <= '1';
+ MREQ_n <= '1';
+ DI_Reg <= "00000000";
+ elsif CLK_n'event and CLK_n = '1' then
+ RD_n <= '1';
+ WR_n <= '1';
+ IORQ_n <= '1';
+ MREQ_n <= '1';
+ if MCycle = "001" then
+ if TState = "001" or (TState = "010" and Wait_n = '0') then
+ RD_n <= not IntCycle_n;
+ MREQ_n <= not IntCycle_n;
+ IORQ_n <= IntCycle_n;
+ end if;
+ if TState = "011" then
+ MREQ_n <= '0';
+ end if;
+ else
+ if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
+ RD_n <= '0';
+ IORQ_n <= not IORQ;
+ MREQ_n <= IORQ;
+ end if;
+ if T2Write = 0 then
+ if TState = "010" and Write = '1' then
+ WR_n <= '0';
+ IORQ_n <= not IORQ;
+ MREQ_n <= IORQ;
+ end if;
+ else
+ if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
+ WR_n <= '0';
+ IORQ_n <= not IORQ;
+ MREQ_n <= IORQ;
+ end if;
+ end if;
+ end if;
+ if TState = "010" and Wait_n = '1' then
+ DI_Reg <= DI;
+ end if;
+ end if;
+ end process;
+
+end;
diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/dataselector_3D_8B.v b/Arcade_MiST/NinjaKun_MiST/rtl/dataselector_3D_8B.v
new file mode 100644
index 00000000..9b99b4a9
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/rtl/dataselector_3D_8B.v
@@ -0,0 +1,19 @@
+module dataselector_3D_8B
+(
+ output [7:0] out,
+ input [7:0] df,
+
+ input en0,
+ input [7:0] dt0,
+ input en1,
+ input [7:0] dt1,
+ input en2,
+ input [7:0] dt2
+);
+
+assign out = en0 ? dt0 :
+ en1 ? dt1 :
+ en2 ? dt2 :
+ df;
+
+endmodule
\ No newline at end of file
diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/dataselector_4D_9B.v b/Arcade_MiST/NinjaKun_MiST/rtl/dataselector_4D_9B.v
new file mode 100644
index 00000000..a4558148
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/rtl/dataselector_4D_9B.v
@@ -0,0 +1,26 @@
+module dataselector_4D_9B
+(
+ output [8:0] OUT,
+
+ input EN1,
+ input [8:0] IN1,
+
+ input EN2,
+ input [8:0] IN2,
+
+ input EN3,
+ input [8:0] IN3,
+
+ input EN4,
+ input [8:0] IN4,
+
+ input [8:0] IND
+);
+
+assign OUT = EN1 ? IN1:
+ EN2 ? IN2:
+ EN3 ? IN3:
+ EN4 ? IN4:
+ IND;
+
+endmodule
\ No newline at end of file
diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/dataselector_5D_8B.v b/Arcade_MiST/NinjaKun_MiST/rtl/dataselector_5D_8B.v
new file mode 100644
index 00000000..bfc04745
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/rtl/dataselector_5D_8B.v
@@ -0,0 +1,23 @@
+module dataselector_5D_8B
+(
+ output [7:0] out,
+ input en0,
+ input [7:0] dt0,
+ input en1,
+ input [7:0] dt1,
+ input en2,
+ input [7:0] dt2,
+ input en3,
+ input [7:0] dt3,
+ input en4,
+ input [7:0] dt4
+);
+
+assign out = en0 ? dt0 :
+ en1 ? dt1 :
+ en2 ? dt2 :
+ en3 ? dt3 :
+ en4 ? dt4 :
+ 8'hFF;
+
+endmodule
\ No newline at end of file
diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/dpram.vhd b/Arcade_MiST/NinjaKun_MiST/rtl/dpram.vhd
new file mode 100644
index 00000000..9ea85a26
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/rtl/dpram.vhd
@@ -0,0 +1,130 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY dpram IS
+ GENERIC
+ (
+ init_file : string := "";
+ widthad_a : natural;
+ width_a : natural := 8;
+ outdata_reg_a : string := "UNREGISTERED";
+ outdata_reg_b : string := "UNREGISTERED"
+ );
+ PORT
+ (
+ address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+ address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+ clock_a : IN STD_LOGIC ;
+ clock_b : IN STD_LOGIC ;
+ data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+ data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+ wren_a : IN STD_LOGIC := '1';
+ wren_b : IN STD_LOGIC := '1';
+ q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+ q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+ );
+END dpram;
+
+
+ARCHITECTURE SYN OF dpram IS
+
+ SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+ SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+
+
+ COMPONENT altsyncram
+ GENERIC (
+ address_reg_b : STRING;
+ clock_enable_input_a : STRING;
+ clock_enable_input_b : STRING;
+ clock_enable_output_a : STRING;
+ clock_enable_output_b : STRING;
+ indata_reg_b : STRING;
+ init_file : STRING;
+ intended_device_family : STRING;
+ lpm_type : STRING;
+ numwords_a : NATURAL;
+ numwords_b : NATURAL;
+ operation_mode : STRING;
+ outdata_aclr_a : STRING;
+ outdata_aclr_b : STRING;
+ outdata_reg_a : STRING;
+ outdata_reg_b : STRING;
+ power_up_uninitialized : STRING;
+ read_during_write_mode_port_a : STRING;
+ read_during_write_mode_port_b : STRING;
+ widthad_a : NATURAL;
+ widthad_b : NATURAL;
+ width_a : NATURAL;
+ width_b : NATURAL;
+ width_byteena_a : NATURAL;
+ width_byteena_b : NATURAL;
+ wrcontrol_wraddress_reg_b : STRING
+ );
+ PORT (
+ wren_a : IN STD_LOGIC ;
+ clock0 : IN STD_LOGIC ;
+ wren_b : IN STD_LOGIC ;
+ clock1 : IN STD_LOGIC ;
+ address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+ address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+ q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+ q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+ data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+ data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
+BEGIN
+ q_a <= sub_wire0(width_a-1 DOWNTO 0);
+ q_b <= sub_wire1(width_a-1 DOWNTO 0);
+
+ altsyncram_component : altsyncram
+ GENERIC MAP (
+ address_reg_b => "CLOCK1",
+ clock_enable_input_a => "BYPASS",
+ clock_enable_input_b => "BYPASS",
+ clock_enable_output_a => "BYPASS",
+ clock_enable_output_b => "BYPASS",
+ indata_reg_b => "CLOCK1",
+ init_file => init_file,
+ intended_device_family => "Cyclone III",
+ lpm_type => "altsyncram",
+ numwords_a => 2**widthad_a,
+ numwords_b => 2**widthad_a,
+ operation_mode => "BIDIR_DUAL_PORT",
+ outdata_aclr_a => "NONE",
+ outdata_aclr_b => "NONE",
+ outdata_reg_a => outdata_reg_a,
+ outdata_reg_b => outdata_reg_a,
+ power_up_uninitialized => "FALSE",
+ read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+ read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
+ widthad_a => widthad_a,
+ widthad_b => widthad_a,
+ width_a => width_a,
+ width_b => width_a,
+ width_byteena_a => 1,
+ width_byteena_b => 1,
+ wrcontrol_wraddress_reg_b => "CLOCK1"
+ )
+ PORT MAP (
+ wren_a => wren_a,
+ clock0 => clock_a,
+ wren_b => wren_b,
+ clock1 => clock_b,
+ address_a => address_a,
+ address_b => address_b,
+ data_a => data_a,
+ data_b => data_b,
+ q_a => sub_wire0,
+ q_b => sub_wire1
+ );
+
+
+
+END SYN;
diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/dpram_1r1w.vhd b/Arcade_MiST/NinjaKun_MiST/rtl/dpram_1r1w.vhd
new file mode 100644
index 00000000..73f3d5d1
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/rtl/dpram_1r1w.vhd
@@ -0,0 +1,101 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY dpram_1r1w IS
+ GENERIC
+ (
+ widthad_a : natural;
+ width_a : natural := 8;
+ outdata_reg_b : string := "UNREGISTERED"
+ );
+ PORT
+ (
+ data : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+ rdaddress : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+ rdclock : IN STD_LOGIC ;
+ rdclocken : IN STD_LOGIC := '1';
+ wraddress : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+ wrclock : IN STD_LOGIC ;
+ wrclocken : IN STD_LOGIC := '1';
+ wren : IN STD_LOGIC := '1';
+ q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+ );
+END dpram_1r1w;
+
+
+ARCHITECTURE SYN OF dpram_1r1w IS
+
+ SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+ COMPONENT altsyncram
+ GENERIC (
+ address_reg_b : STRING;
+ clock_enable_input_a : STRING;
+ clock_enable_input_b : STRING;
+ clock_enable_output_b : STRING;
+ intended_device_family : STRING;
+ lpm_type : STRING;
+ numwords_a : NATURAL;
+ numwords_b : NATURAL;
+ operation_mode : STRING;
+ outdata_aclr_b : STRING;
+ outdata_reg_b : STRING;
+ power_up_uninitialized : STRING;
+ widthad_a : NATURAL;
+ widthad_b : NATURAL;
+ width_a : NATURAL;
+ width_b : NATURAL;
+ width_byteena_a : NATURAL
+ );
+ PORT (
+ clocken0 : IN STD_LOGIC ;
+ clocken1 : IN STD_LOGIC ;
+ wren_a : IN STD_LOGIC ;
+ clock0 : IN STD_LOGIC ;
+ clock1 : IN STD_LOGIC ;
+ address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+ address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+ q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+ data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
+BEGIN
+ q <= sub_wire0(width_a-1 DOWNTO 0);
+
+ altsyncram_component : altsyncram
+ GENERIC MAP (
+ address_reg_b => "CLOCK1",
+ clock_enable_input_a => "BYPASS",
+ clock_enable_input_b => "BYPASS",
+ clock_enable_output_b => "BYPASS",
+ intended_device_family => "Cyclone III",
+ lpm_type => "altsyncram",
+ numwords_a => 2**widthad_a,
+ numwords_b => 2**widthad_a,
+ operation_mode => "DUAL_PORT",
+ outdata_aclr_b => "NONE",
+ outdata_reg_b => outdata_reg_b,
+ power_up_uninitialized => "FALSE",
+ widthad_a => widthad_a,
+ widthad_b => widthad_a,
+ width_a => width_a,
+ width_b => width_a,
+ width_byteena_a => 1
+ )
+ PORT MAP (
+ clocken0 => wrclocken,
+ clocken1 => rdclocken,
+ wren_a => wren,
+ clock0 => wrclock,
+ clock1 => rdclock,
+ address_a => wraddress,
+ address_b => rdaddress,
+ data_a => data,
+ q_b => sub_wire0
+ );
+
+END SYN;
diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/hvgen.v b/Arcade_MiST/NinjaKun_MiST/rtl/hvgen.v
new file mode 100644
index 00000000..ffe5eacd
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/rtl/hvgen.v
@@ -0,0 +1,42 @@
+module hvgen
+(
+ output [8:0] HPOS,
+ output [8:0] VPOS,
+ input PCLK,
+ input [11:0] iRGB,
+
+ output reg [11:0] oRGB,
+ output reg HBLK = 1,
+ output reg VBLK = 1,
+ output reg HSYN = 1,
+ output reg VSYN = 1
+);
+
+reg [8:0] hcnt = 0;
+reg [8:0] vcnt = 0;
+
+assign HPOS = hcnt-16;
+assign VPOS = vcnt-16;
+
+always @(posedge PCLK) begin
+ case (hcnt)
+ 15: begin HBLK <= 0; hcnt <= hcnt+1; end
+ 272: begin HBLK <= 1; hcnt <= hcnt+1; end
+ 311: begin HSYN <= 0; hcnt <= hcnt+1; end
+ 342: begin HSYN <= 1; hcnt <= 471; end
+ 511: begin hcnt <= 0;
+ case (vcnt)
+ 15: begin VBLK <= 0; vcnt <= vcnt+1; end
+ 207: begin VBLK <= 1; vcnt <= vcnt+1; end
+ 226: begin VSYN <= 0; vcnt <= vcnt+1; end
+ 233: begin VSYN <= 1; vcnt <= 483; end
+ 511: begin vcnt <= 0; end
+ default: vcnt <= vcnt+1;
+ endcase
+ end
+ default: hcnt <= hcnt+1;
+ endcase
+ oRGB <= (HBLK|VBLK) ? 12'h0 : iRGB;
+end
+
+endmodule
\ No newline at end of file
diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/mems.v b/Arcade_MiST/NinjaKun_MiST/rtl/mems.v
new file mode 100644
index 00000000..e943fd5b
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/rtl/mems.v
@@ -0,0 +1,116 @@
+// Copyright (c) 2011 MiSTer-X
+
+module VDPRAM400x2
+(
+ input CL0,
+ input [10:0] AD0,
+ input WR0,
+ input [7:0] WD0,
+ output [7:0] RD0,
+
+ input CL1,
+ input [9:0] AD1,
+ output [15:0] RD1
+);
+
+reg A10;
+always @( posedge CL0 ) A10 <= AD0[10];
+
+wire [7:0] RD00, RD01;
+DPRAM400 LS( CL0, AD0[9:0], WR0 & (~AD0[10]), WD0, RD00, CL1, AD1, 1'b0, 8'h0, RD1[ 7:0] );
+DPRAM400 HS( CL0, AD0[9:0], WR0 & ( AD0[10]), WD0, RD01, CL1, AD1, 1'b0, 8'h0, RD1[15:8] );
+
+assign RD0 = A10 ? RD01 : RD00;
+
+endmodule
+
+
+module DPRAM800
+(
+ input CL0,
+ input [10:0] AD0,
+ input WE0,
+ input [7:0] WD0,
+ output reg [7:0] RD0,
+
+ input CL1,
+ input [10:0] AD1,
+ input WE1,
+ input [7:0] WD1,
+ output reg [7:0] RD1
+);
+
+reg [7:0] core[0:2047];
+
+always @( posedge CL0 ) begin
+ if (WE0) core[AD0] <= WD0;
+ RD0 <= core[AD0];
+end
+
+always @( posedge CL1 ) begin
+ if (WE1) core[AD1] <= WD1;
+ RD1 <= core[AD1];
+end
+
+endmodule
+
+
+module DPRAM400
+(
+ input CL0,
+ input [9:0] AD0,
+ input WE0,
+ input [7:0] WD0,
+ output reg [7:0] RD0,
+
+ input CL1,
+ input [9:0] AD1,
+ input WE1,
+ input [7:0] WD1,
+ output reg [7:0] RD1
+);
+
+reg [7:0] core[0:1023];
+
+always @( posedge CL0 ) begin
+ if (WE0) core[AD0] <= WD0;
+ RD0 <= core[AD0];
+end
+
+always @( posedge CL1 ) begin
+ if (WE1) core[AD1] <= WD1;
+ RD1 <= core[AD1];
+end
+
+endmodule
+
+
+module DPRAM200
+(
+ input CL0,
+ input [8:0] AD0,
+ input WE0,
+ input [7:0] WD0,
+ output reg [7:0] RD0,
+
+ input CL1,
+ input [8:0] AD1,
+ input WE1,
+ input [7:0] WD1,
+ output reg [7:0] RD1
+);
+
+reg [7:0] core[0:511];
+
+always @( posedge CL0 ) begin
+ if (WE0) core[AD0] <= WD0;
+ RD0 <= core[AD0];
+end
+
+always @( posedge CL1 ) begin
+ if (WE1) core[AD1] <= WD1;
+ RD1 <= core[AD1];
+end
+
+endmodule
+
diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_adec.v b/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_adec.v
new file mode 100644
index 00000000..b5b9977e
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_adec.v
@@ -0,0 +1,28 @@
+module ninjakun_adec
+(
+ input [15:0] CP0AD,
+ input CP0WR,
+
+ input [15:0] CP1AD,
+ input CP1WR,
+
+ output CS_IN0,
+ output CS_IN1,
+
+ output CS_SH0,
+ output CS_SH1,
+
+ output SYNWR0,
+ output SYNWR1
+);
+
+assign CS_IN0 = (CP0AD[15:2] == 14'b1010_0000_0000_00);
+assign CS_IN1 = (CP1AD[15:2] == 14'b1010_0000_0000_00);
+
+assign CS_SH0 = (CP0AD[15:11] == 5'b1110_0);
+assign CS_SH1 = (CP1AD[15:11] == 5'b1110_0);
+
+assign SYNWR0 = CS_IN0 & (CP0AD[1:0]==2) & CP0WR;
+assign SYNWR1 = CS_IN1 & (CP1AD[1:0]==2) & CP1WR;
+
+endmodule
\ No newline at end of file
diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_bg.v b/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_bg.v
new file mode 100644
index 00000000..fa24729e
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_bg.v
@@ -0,0 +1,44 @@
+// BackGround Scanline Generator
+module ninjakun_bg
+(
+ input VCLK,
+
+ input [8:0] PH, // CRTC
+ input [8:0] PV,
+
+ input [7:0] BGSCX, // SCRREG
+ input [7:0] BGSCY,
+
+ output reg [9:0] BGVAD, // VRAM
+ input [15:0] BGVDT,
+
+ output reg [12:0] BGCAD,
+ input [31:0] BGCDT,
+
+ output [8:0] BGOUT // OUTPUT
+);
+
+wire [8:0] POSH = PH+BGSCX+2;
+wire [8:0] POSV = PV+BGSCY+32;
+
+wire [9:0] CHRNO = {BGVDT[15:14],BGVDT[7:0]};
+reg [31:0] CDT;
+
+reg [3:0] PAL;
+reg [3:0] OUT;
+always @( posedge VCLK ) begin
+ case(POSH[2:0])
+ 0: begin OUT <= CDT[7:4] ; PAL <= BGVDT[11:8]; end
+ 1: begin OUT <= CDT[3:0] ; BGVAD <= {POSV[7:3],POSH[7:3]}; end
+ 2: begin OUT <= CDT[15:12]; end
+ 3: begin OUT <= CDT[11:8] ; end
+ 4: begin OUT <= CDT[23:20]; BGCAD <= {CHRNO,POSV[2:0]}; end
+ 5: begin OUT <= CDT[19:16]; end
+ 6: begin OUT <= CDT[31:28]; end
+ 7: begin OUT <= CDT[27:24]; CDT <= BGCDT; end
+ endcase
+end
+
+assign BGOUT = { 1'b1, PAL, OUT };
+
+endmodule
\ No newline at end of file
diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_clkgen.v b/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_clkgen.v
new file mode 100644
index 00000000..e10d8edd
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_clkgen.v
@@ -0,0 +1,35 @@
+// Copyright (c) 2011 MiSTer-X
+
+module ninjakun_clkgen
+(
+ input MCLK, // 48MHz
+
+ output VCLKx4,
+ output VCLK,
+
+ output VRAMCL,
+ output PCLK,
+
+ output CLK24M,
+ output CLK12M,
+ output CLK6M,
+ output CLK3M
+);
+
+reg [3:0] CLKDIV;
+always @( posedge MCLK ) CLKDIV <= CLKDIV+1'b1;
+
+assign VCLKx4 = CLKDIV[0]; // 24MHz
+assign VCLK = CLKDIV[2]; // 6MHz
+
+assign CLK24M = CLKDIV[0];
+assign CLK12M = CLKDIV[1];
+assign CLK6M = CLKDIV[2];
+assign CLK3M = CLKDIV[3];
+
+assign VRAMCL = ~VCLKx4;
+assign PCLK = ~VCLK;
+
+endmodule
+
+
diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_cpumux.v b/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_cpumux.v
new file mode 100644
index 00000000..6541c67b
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_cpumux.v
@@ -0,0 +1,53 @@
+module ninjakun_cpumux
+(
+ input SHCLK,
+ output [15:0] CPADR,
+ output [7:0] CPODT,
+ input [7:0] CPIDT,
+ output CPRED,
+ output CPWRT,
+
+ output reg CP0CL,
+ input [15:0] CP0AD,
+ input [7:0] CP0OD,
+ output [7:0] CP0ID,
+ input CP0RD,
+ input CP0WR,
+
+ output reg CP1CL,
+ input [15:0] CP1AD,
+ input [7:0] CP1OD,
+ output [7:0] CP1ID,
+ input CP1RD,
+ input CP1WR
+);
+
+reg [7:0] CP0DT, CP1DT;
+reg [2:0] PHASE;
+reg CSIDE;
+always @( posedge SHCLK ) begin // 24MHz
+ case (PHASE)
+ 0: begin CP0DT <= CPIDT; CSIDE <= 1'b0; end
+ 4: begin CP1DT <= CPIDT; CSIDE <= 1'b1; end
+ default:;
+ endcase
+end
+always @( negedge SHCLK ) begin
+ case (PHASE)
+ 0: CP0CL <= 1'b1;
+ 2: CP0CL <= 1'b0;
+ 4: CP1CL <= 1'b1;
+ 6: CP1CL <= 1'b0;
+ default:;
+ endcase
+ PHASE <= PHASE+1;
+end
+
+assign CPADR = CSIDE ? CP1AD : CP0AD;
+assign CPODT = CSIDE ? CP1OD : CP0OD;
+assign CPRED = CSIDE ? CP1RD : CP0RD;
+assign CPWRT = CSIDE ? CP1WR : CP0WR;
+assign CP0ID = CSIDE ? CP0DT : CPIDT;
+assign CP1ID = CSIDE ? CPIDT : CP1DT;
+
+endmodule
\ No newline at end of file
diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_fg.v b/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_fg.v
new file mode 100644
index 00000000..086c9a5e
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_fg.v
@@ -0,0 +1,41 @@
+// ForeGround Scanline Generator
+module ninjakun_fg
+(
+ input VCLK,
+
+ input [8:0] PH, // CRTC
+ input [8:0] PV,
+
+ output reg [9:0] FGVAD, // VRAM
+ input [15:0] FGVDT,
+
+ output reg [12:0] FGCAD,
+ input [31:0] FGCDT,
+
+ output [9:0] FGOUT // PIXEL OUT : {PRIO,PALNO[8:0]}
+);
+
+wire [8:0] POSH = PH+8+1;
+wire [8:0] POSV = PV+32;
+
+wire [9:0] CHRNO = {1'b0,FGVDT[13],FGVDT[7:0]};
+reg [31:0] CDT;
+
+reg [4:0] PAL;
+reg [3:0] OUT;
+always @( posedge VCLK ) begin
+ case(POSH[2:0])
+ 0: begin OUT <= CDT[7:4] ; PAL <= FGVDT[12:8]; end
+ 1: begin OUT <= CDT[3:0] ; FGVAD <= {POSV[7:3],POSH[7:3]}; end
+ 2: begin OUT <= CDT[15:12]; end
+ 3: begin OUT <= CDT[11:8] ; end
+ 4: begin OUT <= CDT[23:20]; FGCAD <= {CHRNO,POSV[2:0]}; end
+ 5: begin OUT <= CDT[19:16]; end
+ 6: begin OUT <= CDT[31:28]; end
+ 7: begin OUT <= CDT[27:24]; CDT <= FGCDT; end
+ endcase
+end
+
+assign FGOUT = { PAL[4], 1'b0, PAL[3:0], OUT };
+
+endmodule
\ No newline at end of file
diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_input.v b/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_input.v
new file mode 100644
index 00000000..936322f5
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_input.v
@@ -0,0 +1,57 @@
+// Copyright (c) 2011 MiSTer-X
+
+module ninjakun_input
+(
+ input INPCL,
+ input RESET,
+
+ input [7:0] CTR1i, // Control Panel (Negative Logic)
+ input [7:0] CTR2i,
+
+ input VBLK,
+
+ input [1:0] AD0,
+ input [1:0] OD0,
+ input WR0,
+
+ input [1:0] AD1,
+ input [1:0] OD1,
+ input WR1,
+
+ output [7:0] INPD0,
+ output [7:0] INPD1
+);
+
+reg [1:0] SYNCFLG;
+reg [7:0] CTR1,CTR2;
+always @( posedge INPCL or posedge RESET ) begin
+ if (RESET) begin
+ SYNCFLG = 0;
+ end
+ else begin
+ CTR1 <= CTR1i;
+ CTR2 <= CTR2i;
+ if (WR0) begin
+ if (OD0[1]) SYNCFLG[0] = 1;
+ if (OD0[0]) SYNCFLG[1] = 0;
+ end
+ if (WR1) begin
+ if (OD1[1]) SYNCFLG[0] = 0;
+ if (OD1[0]) SYNCFLG[1] = 1;
+ end
+ end
+end
+
+wire [7:0] INPORT0 = CTR1;
+wire [7:0] INPORT1 = CTR2;
+wire [7:0] INPORT2 = { 4'b0000, SYNCFLG, ~VBLK,1'b0 };
+
+assign INPD0 = ( AD0 == 0 ) ? INPORT0 :
+ ( AD0 == 1 ) ? INPORT1 :
+ ( AD0 == 2 ) ? INPORT2 : 8'hFF;
+
+assign INPD1 = ( AD1 == 0 ) ? INPORT0 :
+ ( AD1 == 1 ) ? INPORT1 :
+ ( AD1 == 2 ) ? INPORT2 : 8'hFF;
+
+endmodule
\ No newline at end of file
diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_io_video.v b/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_io_video.v
new file mode 100644
index 00000000..ba510c6b
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_io_video.v
@@ -0,0 +1,115 @@
+// Copyright (c) 2011,19 MiSTer-X
+
+module ninjakun_io_video
+(
+ input SHCLK,
+ input CLK3M,
+ input RESET,
+ input VRCLK,
+ input VCLKx4,
+ input VCLK,
+ input [8:0] PH,
+ input [8:0] PV,
+ input [15:0] CPADR,
+ input [7:0] CPODT,
+ output [7:0] CPIDT,
+ input CPRED,
+ input CPWRT,
+ input [7:0] DSW1,
+ input [7:0] DSW2,
+ output VBLK,
+ output [7:0] POUT,
+ output [15:0] SNDOUT,
+// output [12:0] sp_rom_addr,
+// input [31:0] sp_rom_data,
+// output [12:0] fg_rom_addr,
+// input [31:0] fg_rom_data,
+ output [12:0] bg_rom_addr,
+ input [31:0] bg_rom_data
+);
+
+wire [9:0] FGVAD;
+wire [15:0] FGVDT;
+wire [9:0] BGVAD;
+wire [15:0] BGVDT;
+wire [10:0] SPAAD;
+wire [7:0] SPADT;
+wire [7:0] SCRPX, SCRPY;
+wire [8:0] PALET;
+ninjakun_video video (
+ .RESET(RESET),
+ .VCLKx4(VCLKx4),
+ .VCLK(VCLK),
+ .PH(PH),
+ .PV(PV),
+ .PALAD(PALET), // Pixel Output (Palet Index)
+ .FGVAD(FGVAD), // FG
+ .FGVDT(FGVDT),
+ .BGVAD(BGVAD), // BG
+ .BGVDT(BGVDT),
+ .BGSCX(SCRPX),
+ .BGSCY(SCRPY),
+ .SPAAD(SPAAD), // Sprite
+ .SPADT(SPADT),
+ .VBLK(VBLK),
+ .DBGPD(1'b0), // Palet Display (for Debug)
+// .sp_rom_addr(sp_rom_addr),
+// .sp_rom_data(sp_rom_data),
+// .fg_rom_addr(fg_rom_addr),
+// .fg_rom_data(fg_rom_data),
+ .bg_rom_addr(bg_rom_addr),
+ .bg_rom_data(bg_rom_data)
+);
+
+wire CS_PSG, CS_FGV, CS_BGV, CS_SPA, CS_PAL;
+ninjakun_sadec sadec(
+ .CPADR(CPADR),
+ .CS_PSG(CS_PSG),
+ .CS_FGV(CS_FGV),
+ .CS_BGV(CS_BGV),
+ .CS_SPA(CS_SPA),
+ .CS_PAL(CS_PAL)
+);
+
+wire [7:0] PSDAT, FGDAT, BGDAT, SPDAT, PLDAT;
+
+wire [9:0] BGOFS = CPADR[9:0]+{SCRPY[7:3],SCRPX[7:3]};
+wire [10:0] BGADR = {CPADR[10],BGOFS};
+
+VDPRAM400x2 fgv( SHCLK, CPADR[10:0], CS_FGV & CPWRT, CPODT, FGDAT, VRCLK, FGVAD, FGVDT );
+VDPRAM400x2 bgv( SHCLK, BGADR , CS_BGV & CPWRT, CPODT, BGDAT, VRCLK, BGVAD, BGVDT );
+DPRAM800 spa( SHCLK, CPADR[10:0], CS_SPA & CPWRT, CPODT, SPDAT, VRCLK, SPAAD, 1'b0, 8'h0, SPADT );
+DPRAM200 pal( SHCLK, CPADR[ 8:0], CS_PAL & CPWRT, CPODT, PLDAT, VCLK, PALET, 1'b0, 8'h0, POUT );
+
+dataselector_5D_8B cpxdsel(
+ .out(CPIDT),
+ .en0(CS_PSG),
+ .dt0(PSDAT),
+ .en1(CS_FGV),
+ .dt1(FGDAT),
+ .en2(CS_BGV),
+ .dt2(BGDAT),
+ .en3(CS_SPA),
+ .dt3(SPDAT),
+ .en4(CS_PAL),
+ .dt4(PLDAT)
+);
+
+ninjakun_psg psg(
+ .AXSCLK(SHCLK),
+ .CLK(CLK3M),
+ .ADR(CPADR[1:0]),
+ .CS(CS_PSG),
+ .WR(CPWRT),
+ .ID(CPODT),
+ .OD(PSDAT),
+ .RESET(RESET),
+ .RD(CPRED),
+ .DSW1(DSW1),
+ .DSW2(DSW2),
+ .SCRPX(SCRPX),
+ .SCRPY(SCRPY),
+ .SNDO(SNDOUT)
+);
+
+endmodule
\ No newline at end of file
diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_irqgen.v b/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_irqgen.v
new file mode 100644
index 00000000..3fc16e62
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_irqgen.v
@@ -0,0 +1,33 @@
+module ninjakun_irqgen
+(
+ input CLK,
+ input VBLK,
+
+ input IRQ0_ACK,
+ input IRQ1_ACK,
+
+ output reg IRQ0,
+ output reg IRQ1
+);
+
+`define CYCLES 12500 // 1/240sec.
+
+reg pVBLK;
+wire VBTG = VBLK & (pVBLK^VBLK);
+
+reg [13:0] cnt;
+wire IRQ1_ACT = (cnt == 1);
+wire CNTR_RST = (cnt == `CYCLES)|VBTG;
+
+always @( posedge CLK ) begin
+ if (VBTG) IRQ0 <= 1'b1;
+ if (IRQ1_ACT) IRQ1 <= 1'b1;
+
+ if (IRQ0_ACK) IRQ0 <= 1'b0;
+ if (IRQ1_ACK) IRQ1 <= 1'b0;
+
+ cnt <= CNTR_RST ? 0 : (cnt + 1'b1);
+ pVBLK <= VBLK;
+end
+
+endmodule
diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_main.v b/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_main.v
new file mode 100644
index 00000000..197d57a6
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_main.v
@@ -0,0 +1,155 @@
+module ninjakun_main
+(
+ input RESET,
+ input CLK24M,
+ input CLK3M,
+ input VBLK,
+
+ input [7:0] CTR1,
+ input [7:0] CTR2,
+
+ output [15:0] CPADR,
+ output [7:0] CPODT,
+ input [7:0] CPIDT,
+ output CPRED,
+ output CPWRT,
+ output [14:0] CPU1ADDR,
+ input [7:0] CPU1DT,
+ output [12:0] CPU2ADDR,
+ input [7:0] CPU2DT
+);
+
+wire SHCLK = CLK24M;
+wire INPCL = CLK24M;
+
+wire CP0IQ, CP0IQA;
+wire CP1IQ, CP1IQA;
+ninjakun_irqgen ninjakun_irqgen(
+ .CLK(CLK3M),
+ .VBLK(VBLK),
+ .IRQ0_ACK(CP0IQA),
+ .IRQ1_ACK(CP1IQA),
+ .IRQ0(CP0IQ),
+ .IRQ1(CP1IQ)
+);
+
+wire CP0CL, CP1CL;
+wire [15:0] CP0AD, CP1AD;
+wire [7:0] CP0OD, CP1OD;
+wire [7:0] CP0DT, CP1DT;
+wire [7:0] CP0ID, CP1ID;
+wire CP0RD, CP1RD;
+wire CP0WR, CP1WR;
+Z80IP cpu0(
+ .reset_in(RESET),
+ .clk(CP0CL),
+ .adr(CP0AD),
+ .data_in(CP0DT),
+ .data_out(CP0OD),
+ .rd(CP0RD),
+ .wr(CP0WR),
+ .intreq(CP0IQ),
+ .intack(CP0IQA)
+);
+
+Z80IP cpu1(
+ .reset_in(RESET),
+ .clk(CP1CL),
+ .adr(CP1AD),
+ .data_in(CP1DT),
+ .data_out(CP1OD),
+ .rd(CP1RD),
+ .wr(CP1WR),
+ .intreq(CP1IQ),
+ .intack(CP1IQA)
+);
+
+ninjakun_cpumux ioshare(
+ .SHCLK(SHCLK),
+ .CPADR(CPADR),
+ .CPODT(CPODT),
+ .CPIDT(CPIDT),
+ .CPRED(CPRED),
+ .CPWRT(CPWRT),
+ .CP0CL(CP0CL),
+ .CP0AD(CP0AD),
+ .CP0OD(CP0OD),
+ .CP0ID(CP0ID),
+ .CP0RD(CP0RD),
+ .CP0WR(CP0WR),
+ .CP1CL(CP1CL),
+ .CP1AD(CP1AD),
+ .CP1OD(CP1OD),
+ .CP1ID(CP1ID),
+ .CP1RD(CP1RD),
+ .CP1WR(CP1WR)
+);
+
+wire CS_SH0, CS_SH1, CS_IN0, CS_IN1;
+wire SYNWR0, SYNWR1;
+ninjakun_adec adec(
+ .CP0AD(CP0AD),
+ .CP0WR(CP0WR),
+ .CP1AD(CP1AD),
+ .CP1WR(CP1WR),
+ .CS_IN0(CS_IN0),
+ .CS_IN1(CS_IN1),
+ .CS_SH0(CS_SH0),
+ .CS_SH1(CS_SH1),
+ .SYNWR0(SYNWR0),
+ .SYNWR1(SYNWR1)
+);
+
+
+wire [7:0] ROM0D, ROM1D;
+assign CPU1ADDR = CP0AD[14:0];
+assign ROM0D = CPU1DT;
+assign CPU2ADDR = CP1AD[12:0];
+assign ROM1D = CPU2DT;
+
+wire [7:0] SHDT0, SHDT1;
+DPRAM800 shmem(
+ SHCLK, { CP0AD[10] ,CP0AD[9:0]}, CS_SH0 & CP0WR, CP0OD, SHDT0,
+ SHCLK, {(~CP1AD[10]),CP1AD[9:0]}, CS_SH1 & CP1WR, CP1OD, SHDT1
+);
+
+wire [7:0] INPD0, INPD1;
+ninjakun_input inps(
+ .INPCL(INPCL),
+ .RESET(RESET),
+ .CTR1i(CTR1), // Control Panel (Negative Logic)
+ .CTR2i(CTR2),
+ .VBLK(VBLK),
+ .AD0(CP0AD[1:0]),
+ .OD0(CP0OD[7:6]),
+ .WR0(SYNWR0),
+ .AD1(CP1AD[1:0]),
+ .OD1(CP1OD[7:6]),
+ .WR1(SYNWR1),
+ .INPD0(INPD0),
+ .INPD1(INPD1)
+);
+
+dataselector_3D_8B cdt0(
+ .out(CP0DT),
+ .df(CP0ID),
+ .en0(CS_IN0),
+ .dt0(INPD0),
+ .en1(CS_SH0),
+ .dt1(SHDT0),
+ .en2(~CP0AD[15]),
+ .dt2(ROM0D)
+);
+
+dataselector_3D_8B cdt1(
+ .out(CP1DT),
+ .df(CP1ID),
+ .en0(CS_IN1),
+ .dt0(INPD1),
+ .en1(CS_SH1),
+ .dt1(SHDT1),
+ .en2(~CP1AD[15]),
+ .dt2(ROM1D)
+);
+
+endmodule
\ No newline at end of file
diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_psg.v b/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_psg.v
new file mode 100644
index 00000000..8cc26257
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_psg.v
@@ -0,0 +1,94 @@
+module ninjakun_psg
+(
+ input AXSCLK,
+ input CLK,
+ input [1:0] ADR,
+ input CS,
+ input WR,
+ input [7:0] ID,
+ output [7:0] OD,
+ input RESET,
+ input RD,
+ input [7:0] DSW1,
+ input [7:0] DSW2,
+ output [7:0] SCRPX,
+ output [7:0] SCRPY,
+ output [15:0] SNDO
+);
+
+wire [7:0] OD0, OD1;
+assign OD = ADR[1] ? OD1 : OD0;
+
+reg [7:0] SA0, SB0, SC0; wire [7:0] S0x; wire [1:0] S0c;
+reg [7:0] SA1, SB1, SC1; wire [7:0] S1x; wire [1:0] S1c;
+
+reg [1:0] encnt;
+reg ENA;
+always @(posedge AXSCLK) begin
+ ENA <= (encnt==0);
+ encnt <= encnt+1;
+ case (S0c)
+ 2'd0: SA0 <= S0x;
+ 2'd1: SB0 <= S0x;
+ 2'd2: SC0 <= S0x;
+ default:;
+ endcase
+ case (S1c)
+ 2'd0: SA1 <= S1x;
+ 2'd1: SB1 <= S1x;
+ 2'd2: SC1 <= S1x;
+ default:;
+ endcase
+end
+
+wire psgxad = ~ADR[0];
+wire psg0cs = CS & (~ADR[1]);
+wire psg0bd = psg0cs & (WR|psgxad);
+wire psg0bc = psg0cs & ((~WR)|psgxad);
+
+wire psg1cs = CS & ADR[1];
+wire psg1bd = psg1cs & (WR|psgxad);
+wire psg1bc = psg1cs & ((~WR)|psgxad);
+
+YM2149 psg0(
+ .I_DA(ID),
+ .O_DA(OD0),
+ .I_A9_L(~psg0cs),
+ .I_BDIR(psg0bd),
+ .I_BC1(psg0bc),
+ .I_A8(1'b1),
+ .I_BC2(1'b1),
+ .I_SEL_L(1'b0),
+ .O_AUDIO(S0x),
+ .O_CHAN(S0c),
+ .I_IOA(DSW1),
+ .I_IOB(DSW2),
+ .ENA(ENA),
+ .RESET_L(~RESET),
+ .CLK(AXSCLK)
+);
+
+YM2149 psg1(
+ .I_DA(ID),
+ .O_DA(OD1),
+ .I_A9_L(~psg1cs),
+ .I_BDIR(psg1bd),
+ .I_BC1(psg1bc),
+ .I_A8(1'b1),
+ .I_BC2(1'b1),
+ .I_SEL_L(1'b0),
+ .O_AUDIO(S1x),
+ .O_CHAN(S1c),
+ .I_IOA(8'd0),
+ .I_IOB(8'd0),
+ .O_IOA(SCRPX),
+ .O_IOB(SCRPY),
+ .ENA(ENA),
+ .RESET_L(~RESET),
+ .CLK(AXSCLK)
+);
+
+wire [11:0] SND = SA0+SB0+SC0+SA1+SB1+SC1;
+assign SNDO = {SND,SND[3:0]};
+
+endmodule
\ No newline at end of file
diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_sadec.v b/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_sadec.v
new file mode 100644
index 00000000..89bd4b14
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_sadec.v
@@ -0,0 +1,19 @@
+// Copyright (c) 2011 MiSTer-X
+
+module ninjakun_sadec
+(
+ input [15:0] CPADR,
+ output CS_PSG,
+ output CS_FGV,
+ output CS_BGV,
+ output CS_SPA,
+ output CS_PAL
+);
+
+assign CS_PSG = ( CPADR[15: 2] == 14'b1000_0000_0000_00 );
+assign CS_FGV = ( CPADR[15:11] == 5'b1100_0 );
+assign CS_BGV = ( CPADR[15:11] == 5'b1100_1 );
+assign CS_SPA = ( CPADR[15:11] == 5'b1101_0 );
+assign CS_PAL = ( CPADR[15:11] == 5'b1101_1 );
+
+endmodule
\ No newline at end of file
diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_sp.v b/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_sp.v
new file mode 100644
index 00000000..479f7ded
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_sp.v
@@ -0,0 +1,216 @@
+// Copyright (c) 2011,19 MiSTer-X
+
+module ninjakun_sp
+(
+ input VCLKx4,
+ input VCLK,
+
+ input [8:0] PH,
+ input [8:0] PV,
+
+ output [10:0] SPAAD,
+ input [7:0] SPADT,
+
+ output [12:0] SPCAD,
+ input [31:0] SPCDT,
+ input SPCFT,
+
+ output [8:0] SPOUT
+);
+
+wire WPEN;
+wire [8:0] WPAD;
+wire [7:0] WPIX;
+
+reg [7:0] POUT;
+wire [3:0] OTHP = (POUT[3:0]==1) ? POUT[7:4] : POUT[3:0];
+
+reg [9:0] radr0=0,radr1=1;
+wire [7:0] POUTi;
+LineDBuf ldbuf(
+ VCLKx4, radr0, POUTi, (radr0==radr1),
+ ~VCLKx4, {PV[0],WPAD}, WPIX, WPEN
+);
+always @(posedge VCLK) radr0 <= {~PV[0],PH};
+always @(negedge VCLK) begin
+ if (radr0!=radr1) POUT <= POUTi;
+ radr1 <= radr0;
+end
+
+NINJAKUN_SPENG eng (
+ VCLKx4, PH, PV,
+ SPAAD, SPADT,
+ SPCAD, SPCDT, SPCFT,
+ WPAD, WPIX, WPEN
+);
+
+assign SPOUT = { 5'h0, OTHP };
+
+endmodule
+
+
+module NINJAKUN_SPENG
+(
+ input VCLKx4,
+
+ input [8:0] PH,
+ input [8:0] PV,
+
+ output [10:0] SPAAD,
+ input [7:0] SPADT,
+
+ output [12:0] SPCAD,
+ input [31:0] SPCDT,
+ input SPCFT,
+
+ output [8:0] WPAD,
+ output [7:0] WPIX,
+ output WPEN
+);
+
+reg [5:0] SPRNO;
+reg [1:0] SPRIX;
+assign SPAAD = {SPRNO, 3'h0, SPRIX};
+
+reg [7:0] ATTR;
+wire [3:0] PALNO = ATTR[3:0];
+wire FLIPH = ATTR[4];
+wire FLIPV = ATTR[5];
+wire XPOSH = ATTR[6];
+wire DSABL = ATTR[7];
+
+reg [7:0] YPOS;
+reg [7:0] NV;
+wire [7:0] HV = NV-YPOS;
+wire [3:0] LV = {4{FLIPV}}^(HV[3:0]);
+wire YHIT = (HV[7:4]==4'b1111) & (~DSABL);
+
+reg [7:0] XPOS;
+reg [4:0] WP;
+wire [3:0] WOFS = {4{FLIPH}}^(WP[3:0]);
+assign WPAD = {1'b0,XPOS}-{XPOSH,8'h0}+WOFS-1;
+assign WPEN = ~(WP[4]|(WPIX[3:0]==0));
+
+reg [7:0] PTNO;
+reg CRS;
+assign SPCAD = {PTNO, LV[3], CRS, LV[2:0]};
+
+function [3:0] XOUT;
+input [2:0] N;
+input [31:0] CDT;
+ case(N)
+ 0: XOUT = CDT[7:4];
+ 1: XOUT = CDT[3:0];
+ 2: XOUT = CDT[15:12];
+ 3: XOUT = CDT[11:8];
+ 4: XOUT = CDT[23:20];
+ 5: XOUT = CDT[19:16];
+ 6: XOUT = CDT[31:28];
+ 7: XOUT = CDT[27:24];
+ endcase
+endfunction
+reg [31:0] CDT0, CDT1;
+assign WPIX = {PALNO, XOUT(WP[2:0],WP[3] ? CDT1 : CDT0)};
+
+
+`define WAIT 0
+`define FETCH0 1
+`define FETCH1 2
+`define FETCH2 3
+`define FETCH3 4
+`define FETCH4 5
+`define DRAW 6
+`define NEXT 7
+
+reg [2:0] STATE;
+always @( posedge VCLKx4 ) begin
+ case (STATE)
+
+ `WAIT: begin
+ WP <= 16;
+ if (~PH[8]) begin
+ NV <= PV+17;
+ SPRNO <= 0;
+ SPRIX <= 2;
+ STATE <= `FETCH0;
+ end
+ end
+
+ `FETCH0: begin
+ YPOS <= SPADT;
+ SPRIX <= 3;
+ STATE <= `FETCH1;
+ end
+ `FETCH1: begin
+ ATTR = SPADT; /* ATTR must block assign */
+ SPRIX <= 0;
+ STATE <= YHIT ? `FETCH2 : `NEXT;
+ end
+
+ `FETCH2: begin
+ PTNO <= SPADT;
+ SPRIX <= 1;
+ STATE <= `FETCH3;
+ end
+ `FETCH3: begin
+ if (SPCFT) begin // Wait for CHRROM fetch cycle
+ XPOS <= SPADT;
+ CRS <= 0;
+ STATE <= `FETCH4;
+ end
+ end
+ `FETCH4: begin
+ if (SPCFT) begin // Fetch CHRROM data (16pixels)
+ if (~CRS) begin
+ CDT0 <= SPCDT;
+ CRS <= 1;
+ end
+ else begin
+ CDT1 <= SPCDT;
+ WP <= 0;
+ STATE <= `DRAW;
+ end
+ end
+ end
+
+ `DRAW: begin
+ WP <= WP+1;
+ if (WP[4]) STATE <= `NEXT;
+ end
+
+ `NEXT: begin
+ CDT0 <= 0; CDT1 <= 0;
+ SPRNO <= SPRNO+1;
+ SPRIX <= 2;
+ STATE <= (SPRNO==63) ? `WAIT : `FETCH0;
+ end
+
+ endcase
+end
+
+endmodule
+
+
+module LineDBuf
+(
+ input rC,
+ input [9:0] rA,
+ output [7:0] rD,
+ input rE,
+
+ input wC,
+ input [9:0] wA,
+ input [7:0] wD,
+ input wE
+);
+
+DPRAM1024 ram(
+ rA, wA,
+ rC, wC,
+ 8'h0, wD,
+ rE, wE,
+ rD
+);
+
+endmodule
+
diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_top.v b/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_top.v
new file mode 100644
index 00000000..0f3a70fa
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_top.v
@@ -0,0 +1,124 @@
+/***********************************************
+ "FPGA NinjaKun" for MiSTer
+
+ Copyright (c) 2011,19 MiSTer-X
+************************************************/
+/*
+ROM_START( ninjakun )
+ ROM_REGION( 0x8000, "maincpu", 0 )
+ ROM_LOAD( "ninja-1.7a", 0x0000, 0x02000, CRC(1c1dc141) SHA1(423d3ed35e73a8d5bfce075a889b0322b207bd0d) )
+ ROM_LOAD( "ninja-2.7b", 0x2000, 0x02000, CRC(39cc7d37) SHA1(7f0d0e1e92cb6a57f15eb7fc51a67112f1c5fc8e) )
+ ROM_LOAD( "ninja-3.7d", 0x4000, 0x02000, CRC(d542bfe3) SHA1(3814d8f5b1acda21438fff4f71670fa653dc7b30) )
+ ROM_LOAD( "ninja-4.7e", 0x6000, 0x02000, CRC(a57385c6) SHA1(77925a281e64889bfe967c3d42a388529aaf7eb6) )
+
+ ROM_REGION( 0x2000, "sub", 0 )
+ ROM_LOAD( "ninja-5.7h", 0x0000, 0x02000, CRC(164a42c4) SHA1(16b434b33b76b878514f67c23315d4c6da7bfc9e) )
+
+ ROM_REGION( 0x08000, "gfx1", 0 )
+ ROM_LOAD16_BYTE( "ninja-6.7n", 0x0000, 0x02000, CRC(a74c4297) SHA1(87184d14c67331f2c8a2412e28f31427eddae799) )
+ ROM_LOAD16_BYTE( "ninja-7.7p", 0x0001, 0x02000, CRC(53a72039) SHA1(d77d608ce9388a8956831369badd88a8eda8e102) )
+ ROM_LOAD16_BYTE( "ninja-8.7s", 0x4000, 0x02000, CRC(4a99d857) SHA1(6aadb6a5c721a161a5c1bef5569c1e323e380cff) )
+ ROM_LOAD16_BYTE( "ninja-9.7t", 0x4001, 0x02000, CRC(dede49e4) SHA1(8ce4bc02ec583b3885ca63fb5e2d5dad185fe192) )
+
+ ROM_REGION( 0x08000, "gfx2", 0 )
+ ROM_LOAD16_BYTE( "ninja-10.2c", 0x0000, 0x02000, CRC(0d55664a) SHA1(955a607b4401ce9f3f807d53833a766152b0ef9b) )
+ ROM_LOAD16_BYTE( "ninja-11.2d", 0x0001, 0x02000, CRC(12ff9597) SHA1(10b572844ab32e3ae54abe3600fecc1a811ac713) )
+ ROM_LOAD16_BYTE( "ninja-12.4c", 0x4000, 0x02000, CRC(e9b75807) SHA1(cf4c8ac962f785e9de5502df58eab9b3725aaa28) )
+ ROM_LOAD16_BYTE( "ninja-13.4d", 0x4001, 0x02000, CRC(1760ed2c) SHA1(ee4c8efcce483c8051873714856824a1a1e14b61) )
+ROM_END*/
+
+module ninjakun_top
+(
+ input RESET, // RESET
+ input MCLK, // Master Clock (48.0MHz)
+ input [7:0] CTR1, // Control Panel
+ input [7:0] CTR2,
+ input [7:0] DSW1, // DipSW
+ input [7:0] DSW2,
+ input [8:0] PH, // PIXEL H
+ input [8:0] PV, // PIXEL V
+ output PCLK, // PIXEL CLOCK
+ output [7:0] POUT, // PIXEL OUT
+ output [15:0] SNDOUT, // Sound Output (LPCM unsigned 16bits)
+ output [14:0] CPU1ADDR,
+ input [7:0] CPU1DT,
+ output [12:0] CPU2ADDR,
+ input [7:0] CPU2DT,
+// output [12:0] sp_rom_addr,
+// input [31:0] sp_rom_data,
+// output [12:0] fg_rom_addr,
+// input [31:0] fg_rom_data,
+ output [12:0] bg_rom_addr,
+ input [31:0] bg_rom_data
+);
+
+wire VCLKx4, VCLK;
+wire VRAMCL, CLK24M, CLK12M, CLK6M, CLK3M;
+ninjakun_clkgen ninjakun_clkgen(
+ .MCLK(MCLK), // 48MHz
+ .VCLKx4(VCLKx4),
+ .VCLK(VCLK),
+ .VRAMCL(VRAMCL),
+ .PCLK(PCLK),
+ .CLK24M(CLK24M),
+ .CLK12M(CLK12M),
+ .CLK6M(CLK6M),
+ .CLK3M(CLK3M)
+);
+
+wire [15:0] CPADR;
+wire [7:0] CPODT, CPIDT;
+wire CPRED, CPWRT, VBLK;
+ninjakun_main ninjakun_main(
+ .RESET(RESET),
+ .CLK24M(CLK24M),
+ .CLK3M(CLK3M),
+ .VBLK(VBLK),
+ .CTR1(CTR1),
+ .CTR2(CTR2),
+ .CPADR(CPADR),
+ .CPODT(CPODT),
+ .CPIDT(CPIDT),
+ .CPRED(CPRED),
+ .CPWRT(CPWRT),
+ .CPU1ADDR(CPU1ADDR),
+ .CPU1DT(CPU1DT),
+ .CPU2ADDR(CPU2ADDR),
+ .CPU2DT(CPU2DT)
+);
+
+
+wire [9:0] FGVAD, BGVAD;
+wire [15:0] FGVDT, BGVDT;
+wire [10:0] SPAAD;
+wire [7:0] SPADT;
+wire [8:0] PALET;
+wire [7:0] SCRPX, SCRPY;
+ninjakun_io_video ninjakun_io_video(
+ .SHCLK(CLK24M),
+ .CLK3M(CLK3M),
+ .RESET(RESET),
+ .VRCLK(VRAMCL),
+ .VCLKx4(VCLKx4),
+ .VCLK(VCLK),
+ .PH(PH),
+ .PV(PV),
+ .CPADR(CPADR),
+ .CPODT(CPODT),
+ .CPIDT(CPIDT),
+ .CPRED(CPRED),
+ .CPWRT(CPWRT),
+ .DSW1(DSW1),
+ .DSW2(DSW2),
+ .VBLK(VBLK),
+ .POUT(POUT),
+ .SNDOUT(SNDOUT),
+// .sp_rom_addr(sp_rom_addr),
+// .sp_rom_data(sp_rom_data),
+// .fg_rom_addr(fg_rom_addr),
+// .fg_rom_data(fg_rom_data),
+ .bg_rom_addr(bg_rom_addr),
+ .bg_rom_data(bg_rom_data)
+);
+
+endmodule
\ No newline at end of file
diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_video.v b/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_video.v
new file mode 100644
index 00000000..043f5d1a
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_video.v
@@ -0,0 +1,142 @@
+// Copyright (c) 2011,19 MiSTer-X
+
+module ninjakun_video
+(
+ input RESET,
+ input VCLKx4,
+ input VCLK,
+
+ input [8:0] PH,
+ input [8:0] PV,
+
+ output [8:0] PALAD, // Pixel Output (Palet Index)
+
+ output [9:0] FGVAD, // FG
+ input [15:0] FGVDT,
+
+ output [9:0] BGVAD, // BG
+ input [15:0] BGVDT,
+ input [7:0] BGSCX,
+ input [7:0] BGSCY,
+
+ output [10:0] SPAAD, // Sprite
+ input [7:0] SPADT,
+
+ output VBLK,
+ input DBGPD, // Palet Display (for Debug)
+// output [12:0] sp_rom_addr,
+// input [31:0] sp_rom_data,
+// output [12:0] fg_rom_addr,
+// input [31:0] fg_rom_data,
+ output [12:0] bg_rom_addr,
+ input [31:0] bg_rom_data
+);
+
+assign VBLK = (PV>=193);
+
+// ROMs
+wire SPCFT = 1'b1;
+wire [12:0] SPCAD;
+wire [31:0] SPCDT;
+
+wire [12:0] FGCAD;
+wire [31:0] FGCDT;
+
+wire [12:0] BGCAD;
+wire [31:0] BGCDT;
+wire sc_acc = 0;
+
+//NJFGROM sprom(~VCLKx4, SPCAD, SPCDT, ROMCL, ROMAD, ROMDT, ROMEN);
+//NJFGROM fgrom( ~VCLK, FGCAD, FGCDT, ROMCL, ROMAD, ROMDT, ROMEN);
+//NJBGROM bgrom( ~VCLK, BGCAD, BGCDT, ROMCL, ROMAD, ROMDT, ROMEN);
+//assign sp_rom_addr = SPCAD;
+//assign SPCDT = sp_rom_data;
+//assign fg_rom_addr = FGCAD;
+//assign FGCDT = fg_rom_data;
+/*
+static GFXDECODE_START( gfx_ninjakun )
+ GFXDECODE_ENTRY( "gfx1", 0, layout16x16, 0x200, 16 ) // sprites
+ GFXDECODE_ENTRY( "gfx1", 0, layout8x8, 0x000, 16 ) // fg tiles
+ GFXDECODE_ENTRY( "gfx2", 0, layout8x8, 0x100, 16 ) // bg tiles
+GFXDECODE_END*/
+
+assign bg_rom_addr = BGCAD;
+assign BGCDT = bg_rom_data;
+
+fg1_rom fg1_rom (
+ .clk(~VCLKx4),//if sprite ? ~VCLKx4 : ~VCLK
+ .addr(SPCAD),//if sprite ? SPCAD : FGCAD
+ .data(SPCDT[7:0])//if sprite ? SPCDT[7:0] : FGCDT[7:0]
+);
+
+fg2_rom fg2_rom (
+ .clk(~VCLKx4),
+ .addr(SPCAD),
+ .data(SPCDT[15:8])
+);
+
+fg3_rom fg3_rom (
+ .clk(~VCLKx4),
+ .addr(SPCAD),
+ .data(SPCDT[23:16])
+);
+
+fg4_rom fg4_rom (
+ .clk(~VCLKx4),
+ .addr(SPCAD),
+ .data(SPCDT[31:24])
+);
+
+// Fore-Ground Scanline Generator
+wire FGPRI;
+wire [8:0] FGOUT;
+ninjakun_fg fg(
+ VCLK,
+ PH, PV,
+ FGVAD, FGVDT,
+ FGCAD, FGCDT,
+ {FGPRI, FGOUT}
+);
+wire FGOPQ =(FGOUT[3:0]!=0);
+wire FGPPQ = FGOPQ & (~FGPRI);
+
+// Back-Ground Scanline Generator
+wire [8:0] BGOUT;
+ninjakun_bg bg(
+ VCLK,
+ PH, PV,
+ BGSCX, BGSCY,
+ BGVAD, BGVDT,
+ BGCAD, BGCDT,
+ BGOUT
+);
+
+// Sprite Scanline Generator
+wire [8:0] SPOUT;
+ninjakun_sp sp(
+ VCLKx4, VCLK,
+ PH, PV,
+ SPAAD, SPADT,
+ SPCAD, SPCDT, SPCFT,
+ SPOUT
+);
+wire SPOPQ = (SPOUT[3:0]!=0);
+
+// Palet Display (for Debug)
+wire [8:0] PDOUT = (PV[7]|PV[8]) ? 0 : {PV[6:2],PH[7:4]};
+
+// Color Mixer
+dataselector_4D_9B dataselector_4D_9B(
+ .OUT(PALAD),
+ .EN1(DBGPD),
+ .IN1(PDOUT),
+ .EN2(FGPPQ),
+ .IN2(FGOUT),
+ .EN3(SPOPQ),
+ .IN3(SPOUT),
+ .EN4(FGOPQ),
+ .IN4(FGOUT),
+ .IND(BGOUT)
+);
+
+endmodule
\ No newline at end of file
diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/pll.v b/Arcade_MiST/NinjaKun_MiST/rtl/pll.v
new file mode 100644
index 00000000..d8ab4161
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/rtl/pll.v
@@ -0,0 +1,337 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll
+
+// ============================================================
+// File Name: pll.v
+// Megafunction Name(s):
+// altpll
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2014 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module pll (
+ inclk0,
+ c0,
+ c1,
+ locked);
+
+ input inclk0;
+ output c0;
+ output c1;
+ output locked;
+
+ wire [4:0] sub_wire0;
+ wire sub_wire2;
+ wire [0:0] sub_wire6 = 1'h0;
+ wire [0:0] sub_wire3 = sub_wire0[0:0];
+ wire [1:1] sub_wire1 = sub_wire0[1:1];
+ wire c1 = sub_wire1;
+ wire locked = sub_wire2;
+ wire c0 = sub_wire3;
+ wire sub_wire4 = inclk0;
+ wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
+
+ altpll altpll_component (
+ .inclk (sub_wire5),
+ .clk (sub_wire0),
+ .locked (sub_wire2),
+ .activeclock (),
+ .areset (1'b0),
+ .clkbad (),
+ .clkena ({6{1'b1}}),
+ .clkloss (),
+ .clkswitch (1'b0),
+ .configupdate (1'b0),
+ .enable0 (),
+ .enable1 (),
+ .extclk (),
+ .extclkena ({4{1'b1}}),
+ .fbin (1'b1),
+ .fbmimicbidir (),
+ .fbout (),
+ .fref (),
+ .icdrclk (),
+ .pfdena (1'b1),
+ .phasecounterselect ({4{1'b1}}),
+ .phasedone (),
+ .phasestep (1'b1),
+ .phaseupdown (1'b1),
+ .pllena (1'b1),
+ .scanaclr (1'b0),
+ .scanclk (1'b0),
+ .scanclkena (1'b1),
+ .scandata (1'b0),
+ .scandataout (),
+ .scandone (),
+ .scanread (1'b0),
+ .scanwrite (1'b0),
+ .sclkout0 (),
+ .sclkout1 (),
+ .vcooverrange (),
+ .vcounderrange ());
+ defparam
+ altpll_component.bandwidth_type = "AUTO",
+ altpll_component.clk0_divide_by = 9,
+ altpll_component.clk0_duty_cycle = 50,
+ altpll_component.clk0_multiply_by = 16,
+ altpll_component.clk0_phase_shift = "0",
+ altpll_component.clk1_divide_by = 9,
+ altpll_component.clk1_duty_cycle = 50,
+ altpll_component.clk1_multiply_by = 2,
+ altpll_component.clk1_phase_shift = "0",
+ altpll_component.compensate_clock = "CLK0",
+ altpll_component.inclk0_input_frequency = 37037,
+ altpll_component.intended_device_family = "Cyclone III",
+ altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
+ altpll_component.lpm_type = "altpll",
+ altpll_component.operation_mode = "NORMAL",
+ altpll_component.pll_type = "AUTO",
+ altpll_component.port_activeclock = "PORT_UNUSED",
+ altpll_component.port_areset = "PORT_UNUSED",
+ altpll_component.port_clkbad0 = "PORT_UNUSED",
+ altpll_component.port_clkbad1 = "PORT_UNUSED",
+ altpll_component.port_clkloss = "PORT_UNUSED",
+ altpll_component.port_clkswitch = "PORT_UNUSED",
+ altpll_component.port_configupdate = "PORT_UNUSED",
+ altpll_component.port_fbin = "PORT_UNUSED",
+ altpll_component.port_inclk0 = "PORT_USED",
+ altpll_component.port_inclk1 = "PORT_UNUSED",
+ altpll_component.port_locked = "PORT_USED",
+ altpll_component.port_pfdena = "PORT_UNUSED",
+ altpll_component.port_phasecounterselect = "PORT_UNUSED",
+ altpll_component.port_phasedone = "PORT_UNUSED",
+ altpll_component.port_phasestep = "PORT_UNUSED",
+ altpll_component.port_phaseupdown = "PORT_UNUSED",
+ altpll_component.port_pllena = "PORT_UNUSED",
+ altpll_component.port_scanaclr = "PORT_UNUSED",
+ altpll_component.port_scanclk = "PORT_UNUSED",
+ altpll_component.port_scanclkena = "PORT_UNUSED",
+ altpll_component.port_scandata = "PORT_UNUSED",
+ altpll_component.port_scandataout = "PORT_UNUSED",
+ altpll_component.port_scandone = "PORT_UNUSED",
+ altpll_component.port_scanread = "PORT_UNUSED",
+ altpll_component.port_scanwrite = "PORT_UNUSED",
+ altpll_component.port_clk0 = "PORT_USED",
+ altpll_component.port_clk1 = "PORT_USED",
+ altpll_component.port_clk2 = "PORT_UNUSED",
+ altpll_component.port_clk3 = "PORT_UNUSED",
+ altpll_component.port_clk4 = "PORT_UNUSED",
+ altpll_component.port_clk5 = "PORT_UNUSED",
+ altpll_component.port_clkena0 = "PORT_UNUSED",
+ altpll_component.port_clkena1 = "PORT_UNUSED",
+ altpll_component.port_clkena2 = "PORT_UNUSED",
+ altpll_component.port_clkena3 = "PORT_UNUSED",
+ altpll_component.port_clkena4 = "PORT_UNUSED",
+ altpll_component.port_clkena5 = "PORT_UNUSED",
+ altpll_component.port_extclk0 = "PORT_UNUSED",
+ altpll_component.port_extclk1 = "PORT_UNUSED",
+ altpll_component.port_extclk2 = "PORT_UNUSED",
+ altpll_component.port_extclk3 = "PORT_UNUSED",
+ altpll_component.self_reset_on_loss_lock = "OFF",
+ altpll_component.width_clock = 5;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "6.000000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "6.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "16"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/rom/make_rom.bat b/Arcade_MiST/NinjaKun_MiST/rtl/rom/make_rom.bat
new file mode 100644
index 00000000..43216a17
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/rtl/rom/make_rom.bat
@@ -0,0 +1,13 @@
+copy /b ninja-1.7a + ninja-2.7b + ninja-3.7d + ninja-4.7e cpu1_rom.bin
+copy /b ninja-5.7h cpu2_rom.bin
+copy /b ninja-10.2c + ninja-11.2d + ninja-12.4c + ninja-13.4d bg.bin
+copy /b cpu1_rom.bin + cpu2_rom.bin + bg.bin NINJAKUN.ROM
+
+
+make_vhdl_prom.exe ninja-6.7n fg1_rom.vhd
+make_vhdl_prom.exe ninja-7.7p fg2_rom.vhd
+make_vhdl_prom.exe ninja-8.7s fg3_rom.vhd
+make_vhdl_prom.exe ninja-9.7t fg4_rom.vhd
+
+
+pause
\ No newline at end of file
diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/rom/make_vhdl_prom.exe b/Arcade_MiST/NinjaKun_MiST/rtl/rom/make_vhdl_prom.exe
new file mode 100644
index 00000000..1e5618bf
Binary files /dev/null and b/Arcade_MiST/NinjaKun_MiST/rtl/rom/make_vhdl_prom.exe differ
diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninjakun.zip b/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninjakun.zip
new file mode 100644
index 00000000..4fb804ba
Binary files /dev/null and b/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninjakun.zip differ
diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/sdram.sv b/Arcade_MiST/NinjaKun_MiST/rtl/sdram.sv
new file mode 100644
index 00000000..41f5b7a8
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/rtl/sdram.sv
@@ -0,0 +1,348 @@
+//
+// sdram.v
+//
+// sdram controller implementation for the MiST board
+// https://github.com/mist-devel/mist-board
+//
+// Copyright (c) 2013 Till Harbaum
+// Copyright (c) 2019 Gyorgy Szombathelyi
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see .
+//
+
+module sdram (
+
+ // interface to the MT48LC16M16 chip
+ inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus
+ output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus
+ output reg SDRAM_DQML, // two byte masks
+ output reg SDRAM_DQMH, // two byte masks
+ output reg [1:0] SDRAM_BA, // two banks
+ output SDRAM_nCS, // a single chip select
+ output SDRAM_nWE, // write enable
+ output SDRAM_nRAS, // row address select
+ output SDRAM_nCAS, // columns address select
+
+ // cpu/chipset interface
+ input init_n, // init signal after FPGA config to initialize RAM
+ input clk, // sdram clock
+
+ input port1_req,
+ output reg port1_ack,
+ input port1_we,
+ input [23:1] port1_a,
+ input [1:0] port1_ds,
+ input [15:0] port1_d,
+ output reg [15:0] port1_q,
+
+ input [16:1] cpu1_addr,
+ output reg [15:0] cpu1_q,
+ input [16:1] cpu2_addr,
+ output reg [15:0] cpu2_q,
+
+ input port2_req,
+ output reg port2_ack,
+ input port2_we,
+ input [23:1] port2_a,
+ input [1:0] port2_ds,
+ input [15:0] port2_d,
+ output reg [31:0] port2_q,
+
+ input [16:2] sp_addr,
+ output reg [31:0] sp_q
+);
+
+localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz
+localparam BURST_LENGTH = 3'b001; // 000=1, 001=2, 010=4, 011=8
+localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
+localparam CAS_LATENCY = 3'd2; // 2/3 allowed
+localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed
+localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write
+
+localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
+
+// 64ms/8192 rows = 7.8us -> 842 cycles@108MHz
+localparam RFRSH_CYCLES = 10'd842;
+
+// ---------------------------------------------------------------------
+// ------------------------ cycle state machine ------------------------
+// ---------------------------------------------------------------------
+
+/*
+ SDRAM state machine for 2 bank interleaved access
+ 1 word burst, CL2
+cmd issued registered
+ 0 RAS0 cas1 - data0 read burst terminated
+ 1 ras0
+ 2 data1 returned
+ 3 CAS0 data1 returned
+ 4 RAS1 cas0
+ 5 ras1
+ 6 CAS1 data0 returned
+*/
+
+localparam STATE_RAS0 = 3'd0; // first state in cycle
+localparam STATE_RAS1 = 3'd4; // Second ACTIVE command after RAS0 + tRRD (15ns)
+localparam STATE_CAS0 = STATE_RAS0 + RASCAS_DELAY + 1'd1; // CAS phase - 3
+localparam STATE_CAS1 = STATE_RAS1 + RASCAS_DELAY; // CAS phase - 6
+localparam STATE_READ0 = 3'd0;// STATE_CAS0 + CAS_LATENCY + 2'd2; // 7
+localparam STATE_READ1 = 3'd3;
+localparam STATE_DS1b = 3'd0;
+localparam STATE_READ1b = 3'd4;
+localparam STATE_LAST = 3'd6;
+
+reg [2:0] t;
+
+always @(posedge clk) begin
+ t <= t + 1'd1;
+ if (t == STATE_LAST) t <= STATE_RAS0;
+end
+
+// ---------------------------------------------------------------------
+// --------------------------- startup/reset ---------------------------
+// ---------------------------------------------------------------------
+
+// wait 1ms (32 8Mhz cycles) after FPGA config is done before going
+// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0)
+reg [4:0] reset;
+reg init = 1'b1;
+always @(posedge clk, negedge init_n) begin
+ if(!init_n) begin
+ reset <= 5'h1f;
+ init <= 1'b1;
+ end else begin
+ if((t == STATE_LAST) && (reset != 0)) reset <= reset - 5'd1;
+ init <= !(reset == 0);
+ end
+end
+
+// ---------------------------------------------------------------------
+// ------------------ generate ram control signals ---------------------
+// ---------------------------------------------------------------------
+
+// all possible commands
+localparam CMD_INHIBIT = 4'b1111;
+localparam CMD_NOP = 4'b0111;
+localparam CMD_ACTIVE = 4'b0011;
+localparam CMD_READ = 4'b0101;
+localparam CMD_WRITE = 4'b0100;
+localparam CMD_BURST_TERMINATE = 4'b0110;
+localparam CMD_PRECHARGE = 4'b0010;
+localparam CMD_AUTO_REFRESH = 4'b0001;
+localparam CMD_LOAD_MODE = 4'b0000;
+
+reg [3:0] sd_cmd; // current command sent to sd ram
+reg [15:0] sd_din;
+// drive control signals according to current command
+assign SDRAM_nCS = sd_cmd[3];
+assign SDRAM_nRAS = sd_cmd[2];
+assign SDRAM_nCAS = sd_cmd[1];
+assign SDRAM_nWE = sd_cmd[0];
+
+reg [24:1] addr_latch[2];
+reg [24:1] addr_latch_next[2];
+reg [16:1] addr_last[2];
+reg [16:2] addr_last2[2];
+reg [15:0] din_latch[2];
+reg [1:0] oe_latch;
+reg [1:0] we_latch;
+reg [1:0] ds[2];
+
+reg port1_state;
+reg port2_state;
+
+localparam PORT_NONE = 2'd0;
+localparam PORT_CPU1 = 2'd1;
+localparam PORT_CPU2 = 2'd2;
+localparam PORT_SP = 2'd1;
+localparam PORT_REQ = 2'd3;
+
+reg [1:0] next_port[2];
+reg [1:0] port[2];
+
+reg refresh;
+reg [10:0] refresh_cnt;
+wire need_refresh = (refresh_cnt >= RFRSH_CYCLES);
+
+// PORT1: bank 0,1
+always @(*) begin
+ if (refresh) begin
+ next_port[0] = PORT_NONE;
+ addr_latch_next[0] = addr_latch[0];
+ end else if (port1_req ^ port1_state) begin
+ next_port[0] = PORT_REQ;
+ addr_latch_next[0] = { 1'b0, port1_a };
+ end else if (cpu1_addr != addr_last[PORT_CPU1]) begin
+ next_port[0] = PORT_CPU1;
+ addr_latch_next[0] = { 8'd0, cpu1_addr };
+ end else if (cpu2_addr != addr_last[PORT_CPU2]) begin
+ next_port[0] = PORT_CPU2;
+ addr_latch_next[0] = { 8'd0, cpu2_addr };
+ end else begin
+ next_port[0] = PORT_NONE;
+ addr_latch_next[0] = addr_latch[0];
+ end
+end
+
+// PORT1: bank 2,3
+always @(*) begin
+ if (port2_req ^ port2_state) begin
+ next_port[1] = PORT_REQ;
+ addr_latch_next[1] = { 1'b1, port2_a };
+ end else if (sp_addr != addr_last2[PORT_SP]) begin
+ next_port[1] = PORT_SP;
+ addr_latch_next[1] = { 1'b1, 7'd0, sp_addr, 1'b0 };
+ end else begin
+ next_port[1] = PORT_NONE;
+ addr_latch_next[1] = addr_latch[1];
+ end
+end
+
+always @(posedge clk) begin
+
+ // permanently latch ram data to reduce delays
+ sd_din <= SDRAM_DQ;
+ SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
+ { SDRAM_DQMH, SDRAM_DQML } <= 2'b11;
+ sd_cmd <= CMD_NOP; // default: idle
+ refresh_cnt <= refresh_cnt + 1'd1;
+
+ if(init) begin
+ // initialization takes place at the end of the reset phase
+ if(t == STATE_RAS0) begin
+
+ if(reset == 15) begin
+ sd_cmd <= CMD_PRECHARGE;
+ SDRAM_A[10] <= 1'b1; // precharge all banks
+ end
+
+ if(reset == 10 || reset == 8) begin
+ sd_cmd <= CMD_AUTO_REFRESH;
+ end
+
+ if(reset == 2) begin
+ sd_cmd <= CMD_LOAD_MODE;
+ SDRAM_A <= MODE;
+ SDRAM_BA <= 2'b00;
+ end
+ end
+ end else begin
+ // RAS phase
+ // bank 0,1
+ if(t == STATE_RAS0) begin
+ addr_latch[0] <= addr_latch_next[0];
+ port[0] <= next_port[0];
+ { oe_latch[0], we_latch[0] } <= 2'b00;
+
+ if (next_port[0] != PORT_NONE) begin
+ sd_cmd <= CMD_ACTIVE;
+ SDRAM_A <= addr_latch_next[0][22:10];
+ SDRAM_BA <= addr_latch_next[0][24:23];
+ addr_last[next_port[0]] <= addr_latch_next[0][16:1];
+ if (next_port[0] == PORT_REQ) begin
+ { oe_latch[0], we_latch[0] } <= { ~port1_we, port1_we };
+ ds[0] <= port1_ds;
+ din_latch[0] <= port1_d;
+ port1_state <= port1_req;
+ end else begin
+ { oe_latch[0], we_latch[0] } <= 2'b10;
+ ds[0] <= 2'b11;
+ end
+ end
+ end
+
+ // bank 2,3
+ if(t == STATE_RAS1) begin
+ refresh <= 1'b0;
+ addr_latch[1] <= addr_latch_next[1];
+ { oe_latch[1], we_latch[1] } <= 2'b00;
+ port[1] <= next_port[1];
+
+ if (next_port[1] != PORT_NONE) begin
+ sd_cmd <= CMD_ACTIVE;
+ SDRAM_A <= addr_latch_next[1][22:10];
+ SDRAM_BA <= addr_latch_next[1][24:23];
+ addr_last2[next_port[1]] <= addr_latch_next[1][16:2];
+ if (next_port[1] == PORT_REQ) begin
+ { oe_latch[1], we_latch[1] } <= { ~port1_we, port1_we };
+ ds[1] <= port2_ds;
+ din_latch[1] <= port2_d;
+ port2_state <= port2_req;
+ end else begin
+ { oe_latch[1], we_latch[1] } <= 2'b10;
+ ds[1] <= 2'b11;
+ end
+ end
+
+ if (next_port[1] == PORT_NONE && need_refresh && !we_latch[0] && !oe_latch[0]) begin
+ refresh <= 1'b1;
+ refresh_cnt <= 0;
+ sd_cmd <= CMD_AUTO_REFRESH;
+ end
+ end
+
+ // CAS phase
+ if(t == STATE_CAS0 && (we_latch[0] || oe_latch[0])) begin
+ sd_cmd <= we_latch[0]?CMD_WRITE:CMD_READ;
+ { SDRAM_DQMH, SDRAM_DQML } <= ~ds[0];
+ if (we_latch[0]) begin
+ SDRAM_DQ <= din_latch[0];
+ port1_ack <= port1_req;
+ end
+ SDRAM_A <= { 4'b0010, addr_latch[0][9:1] }; // auto precharge
+ SDRAM_BA <= addr_latch[0][24:23];
+ end
+
+ if(t == STATE_CAS1 && (we_latch[1] || oe_latch[1])) begin
+ sd_cmd <= we_latch[1]?CMD_WRITE:CMD_READ;
+ { SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
+ if (we_latch[1]) begin
+ SDRAM_DQ <= din_latch[1];
+ port2_ack <= port2_req;
+ end
+ SDRAM_A <= { 4'b0010, addr_latch[1][9:1] }; // auto precharge
+ SDRAM_BA <= addr_latch[1][24:23];
+ end
+
+ // Data returned
+ if(t == STATE_READ0 && oe_latch[0]) begin
+ case(port[0])
+ PORT_REQ: begin port1_q <= sd_din; port1_ack <= port1_req; end
+ PORT_CPU1: begin cpu1_q <= sd_din; end
+ PORT_CPU2: begin cpu2_q <= sd_din; end
+ default: ;
+ endcase;
+ end
+
+ if(t == STATE_READ1 && oe_latch[1]) begin
+ case(port[1])
+ PORT_REQ: port2_q[15:0] <= sd_din;
+ PORT_SP : sp_q[15:0] <= sd_din;
+ default: ;
+ endcase;
+ end
+
+ if(t == STATE_DS1b && oe_latch[1]) { SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
+
+ if(t == STATE_READ1b && oe_latch[1]) begin
+ case(port[1])
+ PORT_REQ: begin port2_q[31:16] <= sd_din; port2_ack <= port2_req; end
+ PORT_SP : begin sp_q[31:16] <= sd_din; end
+ default: ;
+ endcase;
+ end
+ end
+end
+
+endmodule
diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/spram.vhd b/Arcade_MiST/NinjaKun_MiST/rtl/spram.vhd
new file mode 100644
index 00000000..d8043481
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/rtl/spram.vhd
@@ -0,0 +1,55 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY spram IS
+ generic (
+ addr_width_g : integer := 8;
+ data_width_g : integer := 8
+ );
+ PORT
+ (
+ address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
+ clken : IN STD_LOGIC := '1';
+ clock : IN STD_LOGIC := '1';
+ data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
+ wren : IN STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
+ );
+END spram;
+
+
+ARCHITECTURE SYN OF spram IS
+
+BEGIN
+ altsyncram_component : altsyncram
+ GENERIC MAP (
+ clock_enable_input_a => "NORMAL",
+ clock_enable_output_a => "BYPASS",
+ intended_device_family => "Cyclone III",
+ lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+ lpm_type => "altsyncram",
+ numwords_a => 2**addr_width_g,
+ operation_mode => "SINGLE_PORT",
+ outdata_aclr_a => "NONE",
+ outdata_reg_a => "UNREGISTERED",
+ power_up_uninitialized => "FALSE",
+ read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+ widthad_a => addr_width_g,
+ width_a => data_width_g,
+ width_byteena_a => 1
+ )
+ PORT MAP (
+ address_a => address,
+ clock0 => clock,
+ clocken0 => clken,
+ data_a => data,
+ wren_a => wren,
+ q_a => q
+ );
+
+
+
+END SYN;
diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/z80ip.v b/Arcade_MiST/NinjaKun_MiST/rtl/z80ip.v
new file mode 100644
index 00000000..8d55182f
--- /dev/null
+++ b/Arcade_MiST/NinjaKun_MiST/rtl/z80ip.v
@@ -0,0 +1,51 @@
+// Copyright (c) 2011 MiSTer-X
+
+module Z80IP
+(
+ input reset_in,
+ input clk,
+ output [15:0] adr,
+ input [7:0] data_in,
+ output [7:0] data_out,
+ output rd,
+ output wr,
+ input intreq,
+ output intack
+);
+
+assign intack = (adr==16'h38);
+
+wire nmireq = 0;
+
+wire i_mreq, i_iorq, i_rd, i_wr, i_rfsh;
+
+T80s cpu(
+ .CLK_n(~clk),
+ .RESET_n(~reset_in),
+ .INT_n(~intreq),
+ .NMI_n(~nmireq),
+ .MREQ_n(i_mreq),
+ .IORQ_n(i_iorq),
+ .RFSH_n(i_rfsh),
+ .RD_n(i_rd),
+ .WR_n(i_wr),
+ .A(adr),
+ .DI(data_in),
+ .DO(data_out),
+ .WAIT_n(1'b1),
+ .BUSRQ_n(1'b1),
+ .BUSAK_n(),
+ .HALT_n(),
+ .M1_n()
+);
+
+wire mreq = (~i_mreq) & (i_rfsh);
+wire iorq = ~i_iorq;
+wire rdr = ~i_rd;
+wire wrr = ~i_wr;
+
+assign rd = mreq & rdr;
+assign wr = mreq & wrr;
+
+endmodule
+