From 5d4e16e165d9c704cddc55c7d2d0ff73279d10d9 Mon Sep 17 00:00:00 2001 From: Jose Tejada Date: Mon, 8 Mar 2021 09:06:54 +0100 Subject: [PATCH] Text layer dispayed. Colours wrong --- .../rtl/druaga_video.v | 115 ++++++++++-------- .../rtl/fpga_druaga.v | 47 ++++--- 2 files changed, 92 insertions(+), 70 deletions(-) diff --git a/Arcade_MiST/Namco Super Pacman Hardware/rtl/druaga_video.v b/Arcade_MiST/Namco Super Pacman Hardware/rtl/druaga_video.v index a9a52b84..20c1de1a 100644 --- a/Arcade_MiST/Namco Super Pacman Hardware/rtl/druaga_video.v +++ b/Arcade_MiST/Namco Super Pacman Hardware/rtl/druaga_video.v @@ -1,34 +1,37 @@ /*********************************** - FPGA Druaga ( Video Part ) + FPGA Druaga ( Video Part ) - Copyright (c) 2007 MiSTer-X + Copyright (c) 2007 MiSTer-X ************************************/ module DRUAGA_VIDEO ( - input VCLKx8, - input VCLK, - input VCLK_EN, + input VCLKx8, + input VCLK, + input VCLK_EN, - input [8:0] PH, - input [8:0] PV, - output PCLK, - output PCLK_EN, - output [7:0] POUT, - output VB, + input [8:0] PH, + input [8:0] PV, + output PCLK, + output PCLK_EN, + output [7:0] POUT, + output VB, - output [10:0] VRAM_A, - input [15:0] VRAM_D, + output [10:0] VRAM_A, + input [15:0] VRAM_D, - output [6:0] SPRA_A, - input [23:0] SPRA_D, + output [6:0] SPRA_A, + input [23:0] SPRA_D, - input [8:0] SCROLL, + input [8:0] SCROLL, - input [16:0] ROMAD, - input [7:0] ROMDT, - input ROMEN + input [16:0] ROMAD, + input [ 7:0] ROMDT, + input ROMEN, + input [ 2:0] MODEL ); +parameter [2:0] SUPERPAC=3'd5; + wire [8:0] HPOS = PH-8'd16; wire [8:0] VPOS = PV; @@ -37,14 +40,14 @@ wire oHB = (PH>=290) & (PH<492); assign VB = (PV==224); -reg [4:0] PALT_A; -wire [7:0] PALT_D; +reg [4:0] PALT_A; +wire [7:0] PALT_D; -wire [7:0] CLT0_A; -wire [3:0] CLT0_D; +wire [7:0] CLT0_A; +wire [3:0] CLT0_D; -wire [11:0] BGCH_A; -wire [7:0] BGCH_D; +wire [11:0] BGCH_A; +wire [7:0] BGCH_D; // @@ -58,53 +61,53 @@ always @(posedge VCLKx8) if (PH == 290) BGVSCR <= SCROLL; //---------------------------------------- // BG scanline generator //---------------------------------------- -reg [7:0] BGPN; -reg BGH; +reg [7:0] BGPN; +reg BGH; -wire [5:0] COL = HPOS[8:3]; -wire [5:0] ROW = VPOS[8:3]; -wire [5:0] ROW2 = ROW + 6'h02; +wire [5:0] COL = HPOS[8:3]; +wire [5:0] ROW = VPOS[8:3]; +wire [5:0] ROW2 = ROW + 6'h02; -wire [7:0] CHRC = VRAM_D[7:0]; -wire [5:0] BGPL = VRAM_D[13:8]; +wire [7:0] CHRC = VRAM_D[7:0]; +wire [5:0] BGPL = VRAM_D[13:8]; -wire [8:0] HP = HPOS; -wire [8:0] VP = COL[5] ? VPOS : BGVPOS; -wire [11:0] CHRA = { CHRC, ~HP[2], VP[2:0] }; -wire [7:0] CHRO = BGCH_D; +wire [8:0] HP = HPOS; +wire [8:0] VP = COL[5] ? VPOS : BGVPOS; +wire [11:0] CHRA = { CHRC, ~HP[2], VP[2:0] }; +wire [7:0] CHRO = BGCH_D; always @ ( posedge VCLKx8 ) begin - if (VCLK_EN) - case ( HP[1:0] ) - 2'b00: begin BGPN <= { BGPL, CHRO[7], CHRO[3] }; BGH <= VRAM_D[14]; end - 2'b01: begin BGPN <= { BGPL, CHRO[6], CHRO[2] }; BGH <= VRAM_D[14]; end - 2'b10: begin BGPN <= { BGPL, CHRO[5], CHRO[1] }; BGH <= VRAM_D[14]; end - 2'b11: begin BGPN <= { BGPL, CHRO[4], CHRO[0] }; BGH <= VRAM_D[14]; end - endcase + if (VCLK_EN) + case ( HP[1:0] ) + 2'b00: begin BGPN <= { BGPL, CHRO[7], CHRO[3] }; BGH <= VRAM_D[14]; end + 2'b01: begin BGPN <= { BGPL, CHRO[6], CHRO[2] }; BGH <= VRAM_D[14]; end + 2'b10: begin BGPN <= { BGPL, CHRO[5], CHRO[1] }; BGH <= VRAM_D[14]; end + 2'b11: begin BGPN <= { BGPL, CHRO[4], CHRO[0] }; BGH <= VRAM_D[14]; end + endcase end -wire [10:0] VRAMADRS = COL[5] ? { 4'b1111, COL[1:0], ROW[4], ROW2[3:0] } : { VP[8:3], HP[7:3] }; +wire [10:0] VRAMADRS = COL[5] ? { 4'b1111, COL[1:0], ROW[4], ROW2[3:0] } : { VP[8:3], HP[7:3] }; assign CLT0_A = BGPN; assign BGCH_A = CHRA; -assign VRAM_A = VRAMADRS; +assign VRAM_A = VRAMADRS & ( MODEL==SUPERPAC ? 11'h3FF : 11'h7FF ); -wire BGHI = BGH & (CLT0_D!=4'd15); -wire [4:0] BGCOL = { 1'b1, CLT0_D }; +wire BGHI = BGH & (CLT0_D!=4'd15); +wire [4:0] BGCOL = { 1'b1, CLT0_D }; //---------------------------------------- // Sprite scanline generator //---------------------------------------- -wire [4:0] SPCOL; +wire [4:0] SPCOL; DRUAGA_SPRITE spr ( - VCLKx8, VCLK_EN, - HPOS, VPOS, oHB, - SPRA_A, SPRA_D, - SPCOL, - ROMAD,ROMDT,ROMEN + VCLKx8, VCLK_EN, + HPOS, VPOS, oHB, + SPRA_A, SPRA_D, + SPCOL, + ROMAD,ROMDT,ROMEN ); //---------------------------------------- @@ -118,8 +121,12 @@ assign PCLK_EN = VCLK_EN; //---------------------------------------- // ROMs //---------------------------------------- +wire [7:0] chr_data = MODEL==SUPERPAC ? ~ROMDT : ROMDT; dpram #(8,12) bgchr(.clk_a(VCLKx8), .addr_a(BGCH_A), .q_a(BGCH_D), - .clk_b(VCLKx8), .addr_b(ROMAD[11:0]), .we_b(ROMEN & (ROMAD[16:12]=={1'b1,4'h2})), .d_b(ROMDT)); + .clk_b(VCLKx8), .addr_b(ROMAD[11:0]), + .we_b(ROMEN & (ROMAD[16:12]=={1'b1,4'h2})), + .d_b(chr_data) + ); dpram #(4,8) clut0(.clk_a(VCLKx8), .addr_a(CLT0_A^8'h03), .q_a(CLT0_D), .clk_b(VCLKx8), .addr_b(ROMAD[7:0]), .we_b(ROMEN & (ROMAD[16:8]=={1'b1,8'h34})), .d_b(ROMDT[3:0])); dpram #(8,5) pelet(.clk_a(VCLKx8), .addr_a(PALT_A), .q_a(PALT_D), diff --git a/Arcade_MiST/Namco Super Pacman Hardware/rtl/fpga_druaga.v b/Arcade_MiST/Namco Super Pacman Hardware/rtl/fpga_druaga.v index 2ddbf960..b9bb4c15 100644 --- a/Arcade_MiST/Namco Super Pacman Hardware/rtl/fpga_druaga.v +++ b/Arcade_MiST/Namco Super Pacman Hardware/rtl/fpga_druaga.v @@ -96,7 +96,8 @@ wire MCPU_IRQ, MCPU_IRQEN; wire SCPU_IRQ, SCPU_IRQEN; wire SCPU_RESET, IO_RESET; wire PSG_ENABLE; -REGS regs + +REGS #(.SUPERPAC(SUPERPAC)) regs ( CLKCPUx2, RESET, oVB, MCPU_ADRS, MCPU_VMA, MCPU_WE, @@ -105,7 +106,8 @@ REGS regs MCPU_IRQ, MCPU_IRQEN, SCPU_IRQ, SCPU_IRQEN, SCPU_RESET, IO_RESET, - PSG_ENABLE + PSG_ENABLE, + MODEL ); @@ -133,7 +135,8 @@ DRUAGA_VIDEO video .VRAM_A(vram_a), .VRAM_D(vram_d), .SPRA_A(spra_a), .SPRA_D(spra_d), .SCROLL({1'b0,SCROLL}), - .ROMAD(ROMAD),.ROMDT(ROMDT),.ROMEN(ROMEN) + .ROMAD(ROMAD),.ROMDT(ROMDT),.ROMEN(ROMEN), + .MODEL(MODEL) ); assign POUT = (IsMOTOS & (PV==0)) ? 8'h0 : oPOUT; @@ -246,16 +249,21 @@ reg mram_cs0, mram_cs1, mram_cs2, mram_cs3, mram_cs4, mram_cs5; +reg [10:0] cram_ad; +wire [10:0] mram_ad = MCPU_ADRS[10:0]; + assign IO_CS = ( MCPU_ADRS[15:11] == 5'b01001 ) & MCPU_VMA; // $4800-$4FFF wire mrom_cs = ( MCPU_ADRS[15] ) & MCPU_VMA; // $8000-$FFFF always @(*) begin + cram_ad = mram_ad; if( MODEL == SUPERPAC ) begin mram_cs0 = ( MCPU_ADRS[15:10] == 6'b000000 ) && MCPU_VMA; // $0000-$03FF mram_cs1 = ( MCPU_ADRS[15:10] == 6'b000001 ) && MCPU_VMA; // $0400-$07FF mram_cs2 = ( MCPU_ADRS[15:11] == 5'b00001 ) && MCPU_VMA; // $1000-$17FF mram_cs3 = ( MCPU_ADRS[15:11] == 5'b00010 ) && MCPU_VMA; // $1800-$1FFF mram_cs4 = ( MCPU_ADRS[15:11] == 5'b00011 ) && MCPU_VMA; // $2000-$27FF + if( mram_cs0 | mram_cs1 ) cram_ad[10]=0; end else begin mram_cs0 = ( MCPU_ADRS[15:11] == 5'b00000 ) && MCPU_VMA; // $0000-$07FF mram_cs1 = ( MCPU_ADRS[15:11] == 5'b00001 ) && MCPU_VMA; // $0800-$0FFF @@ -285,10 +293,8 @@ assign MCPU_DI = mram_cs0 ? mram_o0 : IO_CS ? IO_O : 8'h0; -wire [10:0] mram_ad = MCPU_ADRS[10:0]; - -dpram #(8,11) main_ram0( .clk_a(CPUCLKx2), .addr_a(mram_ad), .d_a(MCPU_DO), .q_a(mram_o0), .we_a(mram_w0), .clk_b(MCLK), .addr_b(vram_a), .q_b(vram_d[ 7:0])); -dpram #(8,11) main_ram1( .clk_a(CPUCLKx2), .addr_a(mram_ad), .d_a(MCPU_DO), .q_a(mram_o1), .we_a(mram_w1), .clk_b(MCLK), .addr_b(vram_a), .q_b(vram_d[15:8])); +dpram #(8,11) main_ram0( .clk_a(CPUCLKx2), .addr_a(cram_ad), .d_a(MCPU_DO), .q_a(mram_o0), .we_a(mram_w0), .clk_b(MCLK), .addr_b(vram_a), .q_b(vram_d[ 7:0])); +dpram #(8,11) main_ram1( .clk_a(CPUCLKx2), .addr_a(cram_ad), .d_a(MCPU_DO), .q_a(mram_o1), .we_a(mram_w1), .clk_b(MCLK), .addr_b(vram_a), .q_b(vram_d[15:8])); dpram #(8,11) main_ram2( .clk_a(CPUCLKx2), .addr_a(mram_ad), .d_a(MCPU_DO), .q_a(mram_o2), .we_a(mram_w2), .clk_b(MCLK), .addr_b({ 4'b1111, spra_a }), .q_b(spra_d[ 7: 0])); dpram #(8,11) main_ram3( .clk_a(CPUCLKx2), .addr_a(mram_ad), .d_a(MCPU_DO), .q_a(mram_o3), .we_a(mram_w3), .clk_b(MCLK), .addr_b({ 4'b1111, spra_a }), .q_b(spra_d[15: 8])); @@ -314,17 +320,17 @@ endmodule module REGS ( - input MCPU_CLK, - input RESET, - input VBLANK, + input MCPU_CLK, + input RESET, + input VBLANK, input [15:0] MCPU_ADRS, - input MCPU_VMA, - input MCPU_WE, + input MCPU_VMA, + input MCPU_WE, input [15:0] SCPU_ADRS, - input SCPU_VMA, - input SCPU_WE, + input SCPU_VMA, + input SCPU_WE, output reg [7:0] SCROLL, output MCPU_IRQ, @@ -333,14 +339,23 @@ module REGS output reg SCPU_IRQEN, output SCPU_RESET, output IO_RESET, - output reg PSG_ENABLE + output reg PSG_ENABLE, + input [2:0] MODEL ); +parameter [2:0] SUPERPAC=3'd5; + // BG Scroll Register wire MCPU_SCRWE = ( ( MCPU_ADRS[15:11] == 5'b00111 ) & MCPU_VMA & MCPU_WE ); + always @ ( negedge MCPU_CLK or posedge RESET ) begin if ( RESET ) SCROLL <= 8'h0; - else if ( MCPU_SCRWE ) SCROLL <= MCPU_ADRS[10:3]; + else begin + if( MODEL==SUPERPAC ) + SCROLL <= 8'd0; + else if ( MCPU_SCRWE ) + SCROLL <= MCPU_ADRS[10:3]; + end end // MainCPU IRQ Generator