diff --git a/common/CPU/T80/T80.vhd b/common/CPU/T80/T80.vhd index 641ed7ab..c081f108 100644 --- a/common/CPU/T80/T80.vhd +++ b/common/CPU/T80/T80.vhd @@ -233,6 +233,8 @@ architecture rtl of T80 is signal LDHLSP : std_logic; signal ADDSPdd : std_logic; signal IORQ_i : std_logic; + signal Write_i : std_logic; + signal NoRead_i : std_logic; signal Special_LD : std_logic_vector(2 downto 0); signal ExchangeDH : std_logic; signal ExchangeRp : std_logic; @@ -262,6 +264,8 @@ architecture rtl of T80 is signal No_PC : std_logic; signal DOR : std_logic_vector(127 downto 0); + signal Really_Wait : std_logic; + begin REG <= IntE_FF2 & IntE_FF1 & IStatus & DOR & std_logic_vector(PC) & std_logic_vector(SP) & std_logic_vector(R) & I & Fp & Ap & F & ACC when Alternate = '0' @@ -338,8 +342,8 @@ begin SetEI => SetEI, IMode => IMode, Halt => Halt, - NoRead => NoRead, - Write => Write, + NoRead => NoRead_i, + Write => Write_i, R800_mode => R800_mode, No_PC => No_PC, XYbit_undoc => XYbit_undoc); @@ -370,6 +374,8 @@ begin Q => ALU_Q, F_Out => F_Out); + Really_Wait <= not Wait_n and (Write_i or not NoRead_i); + ClkEn <= CEN and not BusAck; T_Res <= '1' when TState = unsigned(TStates) else '0'; @@ -679,7 +685,7 @@ begin end if; end if; - if (TState = 2 and I_BTR = '1' and IR(0) = '1') or (TState = 1 and I_BTR = '1' and IR(0) = '0') then + if (TState = 2 and Really_Wait = '0' and I_BTR = '1' and IR(0) = '1') or (TState = 1 and I_BTR = '1' and IR(0) = '0') then ioq := ('0' & DI_Reg) + ('0' & std_logic_vector(ID16(7 downto 0))); F(Flag_N) <= DI_Reg(7); F(Flag_C) <= ioq(8); @@ -688,7 +694,7 @@ begin F(Flag_P) <= not (ioq(0) xor ioq(1) xor ioq(2) xor ioq(3) xor ioq(4) xor ioq(5) xor ioq(6) xor ioq(7)); end if; - if TState = 2 and Wait_n = '1' then + if TState = 2 and Really_Wait = '0' then if ISet = "01" and MCycle = "111" then IR <= DInst; end if; @@ -716,7 +722,7 @@ begin end if; end if; - if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if (TState = 2 and Really_Wait = '0') or (TState = 4 and MCycle = "001") then if IncDec_16(2 downto 0) = "111" then if IncDec_16(3) = '1' then SP <= SP - 1; @@ -1005,7 +1011,7 @@ begin signed(RegBusA) + 1; process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, I_MULU, T_Res, - ExchangeDH, ExchangeWH, IncDec_16, MCycle, TState, Wait_n, LDHLSP) + ExchangeDH, ExchangeWH, IncDec_16, MCycle, TState, Really_Wait, LDHLSP) begin RegWEH <= '0'; RegWEL <= '0'; @@ -1034,7 +1040,7 @@ begin RegWEL <= '1'; end if; - if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + if IncDec_16(2) = '1' and ((TState = 2 and Really_Wait = '0' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then case IncDec_16(1 downto 0) is when "00" | "01" | "10" => RegWEH <= '1'; @@ -1047,7 +1053,7 @@ begin TmpAddr2 <= std_logic_vector(unsigned(signed(SP) + signed(Save_Mux))); process (Save_Mux, RegBusB, RegBusA_r, ID16, I_MULU, MULU_Prod32, MULU_tmp, T_Res, - ExchangeDH, ExchangeWH, IncDec_16, MCycle, TState, Wait_n, LDHLSP, TmpAddr2, WZ) + ExchangeDH, ExchangeWH, IncDec_16, MCycle, TState, Really_Wait, LDHLSP, TmpAddr2, WZ) begin RegDIH <= Save_Mux; RegDIL <= Save_Mux; @@ -1204,6 +1210,8 @@ begin IntCycle_n <= not IntCycle; IntE <= IntE_FF1; IORQ <= IORQ_i; + NoRead <= NoRead_i; + Write <= Write_i; Stop <= I_DJNZ; ------------------------------------------------------------------------- -- @@ -1275,7 +1283,7 @@ begin if BusReq_s = '1' and BusAck = '1' then else BusAck <= '0'; - if TState = 2 and Wait_n = '0' then + if TState = 2 and Really_Wait = '1' then elsif T_Res = '1' then if Halt = '1' and ( not(Mode = 3 and INT_n = '0' and IntE_FF1 = '0')) then -- halt bug when Mode = 3 , INT_n = '0' and IME=0 Halt_FF <= '1'; diff --git a/common/CPU/T80/T80a.vhd b/common/CPU/T80/T80a.vhd index fdd84d11..468b6901 100644 --- a/common/CPU/T80/T80a.vhd +++ b/common/CPU/T80/T80a.vhd @@ -291,7 +291,7 @@ begin if TState = "001" then IORQ_int <= not IntCycle_n; end if; - if TState = "010" then + if TState = "010" and Wait_s = '1' then IORQ_int <= '0'; end if; end if; diff --git a/common/CPU/T80/T80pa.vhd b/common/CPU/T80/T80pa.vhd index 315623be..0703675c 100644 --- a/common/CPU/T80/T80pa.vhd +++ b/common/CPU/T80/T80pa.vhd @@ -52,6 +52,8 @@ -- -- v2.3: Output last used Address during non-bus MCycle seems more correct. -- +-- v2.4: Use the fixed WAIT_n in T80.vhd +-- library IEEE; use IEEE.std_logic_1164.all; @@ -103,6 +105,7 @@ architecture rtl of T80pa is signal TState : std_logic_vector(2 downto 0); signal CEN_pol : std_logic; signal CEN : std_logic; + signal Wait_s : std_logic; begin CEN <= CEN_p and not CEN_pol; @@ -121,7 +124,7 @@ begin Write => Write, RFSH_n => RFSH_n, HALT_n => HALT_n, - WAIT_n => '1', + WAIT_n => Wait_s, INT_n => INT_n, NMI_n => NMI_n, RESET_n => RESET_n, @@ -154,25 +157,24 @@ begin CEN_pol <= '0'; elsif CEN_p = '1' and CEN_pol = '0' then CEN_pol <= '1'; - if MCycle = "001" then - if TState = "010" then - IORQ_n <= '1'; - MREQ_n <= '1'; - RD_n <= '1'; - end if; - else - if TState = "001" and IORQ = '1' then - WR_n <= not Write; - RD_n <= Write; - IORQ_n <= '0'; + if WAIT_s = '1' or TState /= "010" then + if MCycle = "001" then + if TState = "010" then + IORQ_n <= '1'; + MREQ_n <= '1'; + RD_n <= '1'; + end if; + else + if TState = "001" and IORQ = '1' then + WR_n <= not Write; + RD_n <= Write; + IORQ_n <= '0'; + end if; end if; end if; elsif CEN_n = '1' and CEN_pol = '1' then - if TState = "010" then - CEN_pol <= not WAIT_n; - else - CEN_pol <= '0'; - end if; + Wait_s <= Wait_n; + CEN_pol <= '0'; if TState = "011" and BUSAK = '1' then DI_Reg <= DI; end if;