diff --git a/Arcade_MiST/Atari Vector/LunarLander_MiST/LunarLander.qpf b/Arcade_MiST/Atari Vector/LunarLander_MiST/LunarLander.qpf new file mode 100644 index 00000000..2a9f7422 --- /dev/null +++ b/Arcade_MiST/Atari Vector/LunarLander_MiST/LunarLander.qpf @@ -0,0 +1,6 @@ +DATE = "19:48:06 May 24, 2017" +QUARTUS_VERSION = "16.0.2" + +# Revisions + +PROJECT_REVISION = "LunarLander" diff --git a/Arcade_MiST/Atari Vector/LunarLander_MiST/LunarLander.qsf b/Arcade_MiST/Atari Vector/LunarLander_MiST/LunarLander.qsf new file mode 100644 index 00000000..52ac2de8 --- /dev/null +++ b/Arcade_MiST/Atari Vector/LunarLander_MiST/LunarLander.qsf @@ -0,0 +1,212 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2014 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition +# Date created = 16:03:28 October 01, 2019 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# DigDugII_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.2 +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:48:06 MAY 24,2017" +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_90 -to SPI_SS4 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PIN_49 -to SDRAM_A[0] +set_location_assignment PIN_44 -to SDRAM_A[1] +set_location_assignment PIN_42 -to SDRAM_A[2] +set_location_assignment PIN_39 -to SDRAM_A[3] +set_location_assignment PIN_4 -to SDRAM_A[4] +set_location_assignment PIN_6 -to SDRAM_A[5] +set_location_assignment PIN_8 -to SDRAM_A[6] +set_location_assignment PIN_10 -to SDRAM_A[7] +set_location_assignment PIN_11 -to SDRAM_A[8] +set_location_assignment PIN_28 -to SDRAM_A[9] +set_location_assignment PIN_50 -to SDRAM_A[10] +set_location_assignment PIN_30 -to SDRAM_A[11] +set_location_assignment PIN_32 -to SDRAM_A[12] +set_location_assignment PIN_83 -to SDRAM_DQ[0] +set_location_assignment PIN_79 -to SDRAM_DQ[1] +set_location_assignment PIN_77 -to SDRAM_DQ[2] +set_location_assignment PIN_76 -to SDRAM_DQ[3] +set_location_assignment PIN_72 -to SDRAM_DQ[4] +set_location_assignment PIN_71 -to SDRAM_DQ[5] +set_location_assignment PIN_69 -to SDRAM_DQ[6] +set_location_assignment PIN_68 -to SDRAM_DQ[7] +set_location_assignment PIN_86 -to SDRAM_DQ[8] +set_location_assignment PIN_87 -to SDRAM_DQ[9] +set_location_assignment PIN_98 -to SDRAM_DQ[10] +set_location_assignment PIN_99 -to SDRAM_DQ[11] +set_location_assignment PIN_100 -to SDRAM_DQ[12] +set_location_assignment PIN_101 -to SDRAM_DQ[13] +set_location_assignment PIN_103 -to SDRAM_DQ[14] +set_location_assignment PIN_104 -to SDRAM_DQ[15] +set_location_assignment PIN_58 -to SDRAM_BA[0] +set_location_assignment PIN_51 -to SDRAM_BA[1] +set_location_assignment PIN_85 -to SDRAM_DQMH +set_location_assignment PIN_67 -to SDRAM_DQML +set_location_assignment PIN_60 -to SDRAM_nRAS +set_location_assignment PIN_64 -to SDRAM_nCAS +set_location_assignment PIN_66 -to SDRAM_nWE +set_location_assignment PIN_59 -to SDRAM_nCS +set_location_assignment PIN_33 -to SDRAM_CKE +set_location_assignment PIN_43 -to SDRAM_CLK + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name TOP_LEVEL_ENTITY LunarLander_MiST +set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 +set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name GENERATE_RBF_FILE ON + +# SignalTap II Assignments +# ======================== +set_global_assignment -name ENABLE_SIGNALTAP OFF +set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# --------------------------- +# start ENTITY(DigDugII_mist) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(DigDugII_mist) +# ------------------------- +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name SYSTEMVERILOG_FILE rtl/LunarLander_MiST.sv +set_global_assignment -name VHDL_FILE rtl/llander_top.vhd +set_global_assignment -name VHDL_FILE rtl/llander.vhd +set_global_assignment -name VHDL_FILE rtl/llander_vg.vhd +set_global_assignment -name VHDL_FILE rtl/llander_ram.vhd +set_global_assignment -name VHDL_FILE rtl/llander_dw.vhd +set_global_assignment -name VHDL_FILE rtl/rom/LLANDER_VEC_ROM_2.vhd +set_global_assignment -name VHDL_FILE rtl/rom/LLANDER_VEC_ROM_1.vhd +set_global_assignment -name VHDL_FILE rtl/rom/LLANDER_VEC_ROM_0.vhd +set_global_assignment -name VHDL_FILE rtl/rom/LLANDER_PROG_ROM_3.vhd +set_global_assignment -name VHDL_FILE rtl/rom/LLANDER_PROG_ROM_2.vhd +set_global_assignment -name VHDL_FILE rtl/rom/LLANDER_PROG_ROM_1.vhd +set_global_assignment -name VHDL_FILE rtl/rom/LLANDER_PROG_ROM_0.vhd +set_global_assignment -name VHDL_FILE rtl/rom/LLANDER_DVG_ROM.vhd +set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd +set_global_assignment -name VHDL_FILE rtl/dpram.vhd +set_global_assignment -name VHDL_FILE rtl/ovo.vhd +set_global_assignment -name VHDL_FILE rtl/base_pack.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv +set_global_assignment -name VERILOG_FILE rtl/p2ram.v +set_global_assignment -name VERILOG_FILE rtl/pll.v +set_global_assignment -name QIP_FILE ../../../common/CPU/T65/T65.qip +set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Atari Vector/LunarLander_MiST/clean.bat b/Arcade_MiST/Atari Vector/LunarLander_MiST/clean.bat new file mode 100644 index 00000000..59a9a059 --- /dev/null +++ b/Arcade_MiST/Atari Vector/LunarLander_MiST/clean.bat @@ -0,0 +1,38 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist +del /s PLLJ_PLLSPE_INFO.txt + +pause diff --git a/Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/LunarLander_MiST.sv b/Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/LunarLander_MiST.sv new file mode 100644 index 00000000..ea39ecca --- /dev/null +++ b/Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/LunarLander_MiST.sv @@ -0,0 +1,297 @@ +module LunarLander_MiST( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27/*, + + output [12:0] SDRAM_A, + inout [15:0] SDRAM_DQ, + output SDRAM_DQML, + output SDRAM_DQMH, + output SDRAM_nWE, + output SDRAM_nCAS, + output SDRAM_nRAS, + output SDRAM_nCS, + output [1:0] SDRAM_BA, + output SDRAM_CLK, + output SDRAM_CKE +*/ +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "LunarLander;;", + "O12,Scanlines,None,CRT 25%,CRT 50%,CRT 75%;", + "O3,Test,Off,On;", + "O45,Language,English,Spanish,French,German;", + "O68,Fuel,450,600,750,900,1100,1300,1550,1800;", + "T0,Reset;", + "V,v1.00.",`BUILD_DATE +}; + +assign LED = 1; +assign AUDIO_R = AUDIO_L; + +wire clk_50, clk_25, clk_6, locked; +pll pll( + .inclk0(CLOCK_27), + .c0(clk_50), + .c1(clk_25), + .c2(clk_6), + .locked(locked) +); + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoublerD; +wire ypbpr; +wire hs, vs, hso, vso; +wire hb, vb; +wire blankn = ~(hb | vb); +wire [3:0] r, g, b; +wire [7:0] ro, go, bo; +wire vgade; +wire [7:0] audio; +wire key_strobe; +wire key_pressed; +wire [7:0] key_code; +//this must go to sdram +wire [18:0] vram_write_addr; +wire [3:0] vram_write_data; +wire [18:0] vram_read_addr; +wire [3:0] vram_read_data; +wire vram_wren; +/* +sdram sdram ( + .SDRAM_DQ(SDRAM_DQ), + .SDRAM_A(SDRAM_A), + .SDRAM_DQML(SDRAM_DQML), + .SDRAM_DQMH(SDRAM_DQMH), + .SDRAM_BA(SDRAM_BA), + .SDRAM_nCS(SDRAM_nCS), + .SDRAM_nWE(SDRAM_nWE), + .SDRAM_nRAS(SDRAM_nRAS), + .SDRAM_nCAS(SDRAM_nCAS), + .SDRAM_CKE(SDRAM_CKE), + .init(~locked), // init signal after FPGA config to initialize RAM + .clk(clk_50), // sdram is accessed at up to 128MHz + .clkref(clk_25), // reference clock to sync to + .din(vram_write_data), // data input from chipset/cpu + .dout(vram_read_data), // data output to chipset/cpu + .raddr(vram_read_addr), // 25 bit byte address + .waddr(vram_write_addr), // 25 bit byte address + .rd(~vram_wren), // cpu/chipset requests read + .we(vram_wren) +);*/ + +//reduced ram size + +p2ram p2ram ( + .clock(clk_25), + .data(vram_write_data), + .rdaddress(vram_read_addr[15:0]), + .wraddress(vram_write_addr[15:0]), + .wren(vram_wren), + .q(vram_read_data) + ); + +LLANDER_TOP LLANDER_TOP ( + .ROT_LEFT_L(~m_left), + .ROT_RIGHT_L(~m_right), + .ABORT_L(~m_fire2), + .GAME_SEL_L(~m_fire1), + .START_L(~btn_one_player), + .COIN1_L(~btn_coin), + .COIN2_L(1'b1), + .THRUST(thrust), + .DIAG_STEP_L(1'b1), + .SLAM_L(1'b1), + .SELF_TEST_L(~status[3]), + .START_SEL_L(1'b1), + .AUDIO_OUT(audio), + .VIDEO_R_OUT(r), + .VIDEO_G_OUT(g), + .VIDEO_B_OUT(b), + .LAMP2(lamp2), + .LAMP3(lamp3), + .LAMP4(lamp4), + .LAMP5(lamp5), + .HSYNC_OUT(hs), + .VSYNC_OUT(vs), + .VID_HBLANK(hb), + .VID_VBLANK(vb), + .VGA_DE(vgade), + .DIP({1'b0,1'b0,status[4],status[5],~status[6],1'b1,status[7],status[8]}),//todo dip full + .RESET_L(~(status[0] | buttons[1])), + .clk_6(clk_6), + .clk_25(clk_25), + .vram_write_addr(vram_write_addr), + .vram_write_data(vram_write_data), + .vram_read_addr(vram_read_addr), + .vram_read_data(vram_read_data), + .vram_wren(vram_wren) + ); + +ovo #( + .COLS(1), + .LINES(1), + .RGB(24'hFF00FF)) +diff ( + .i_r({r,r}), + .i_g({g,g}), + .i_b({b,b}), + .i_hs(~hs), + .i_vs(~vs), + .i_de(vgade), + .i_en(1), + .i_clk(clk_25), + + .o_r(ro), + .o_g(go), + .o_b(bo), + .o_hs(hso), + .o_vs(vso), + .o_de(), + .ena(diff_count > 0), + .in0(difficulty), + .in1() +); + +reg [7:0] thrust = 0; + +// 1 second = 50,000,000 cycles (duh) +// If we want to go from zero to full throttle in 1 second we tick every +// 196,850 cycles. +always @(posedge clk_50) begin :thrust_count + int thrust_count; + thrust_count <= thrust_count + 1'd1; + if (thrust_count == 'd196_850) begin + thrust_count <= 0; + if (m_down && thrust > 0) + thrust <= thrust - 1'd1; + + if (m_up && thrust < 'd254) + thrust <= thrust + 1'd1; + end +end + +int diff_count = 0; +always @(posedge clk_50) begin + if (diff_count > 0) + diff_count <= diff_count - 1; + if (~m_fire2) + diff_count <= 'd500_000_000; // 10 seconds +end + +wire lamp2, lamp3, lamp4, lamp5; +wire [1:0] difficulty; +always_comb begin + if(lamp5) + difficulty = 2'd3; + else if(lamp4) + difficulty = 2'd2; + else if(lamp3) + difficulty = 2'd1; + else + difficulty = 2'd0; +end + +mist_video #(.COLOR_DEPTH(6), .SD_HCNT_WIDTH(10)) mist_video( + .clk_sys ( clk_25 ), + .SPI_SCK ( SPI_SCK ), + .SPI_SS3 ( SPI_SS3 ), + .SPI_DI ( SPI_DI ), + .R ( blankn ? ro[7:2] : 0 ), + .G ( blankn ? go[7:2] : 0 ), + .B ( blankn ? bo[7:2] : 0 ), + .HSync ( hso ), + .VSync ( vso ), + .VGA_R ( VGA_R ), + .VGA_G ( VGA_G ), + .VGA_B ( VGA_B ), + .VGA_VS ( VGA_VS ), + .VGA_HS ( VGA_HS ), + .scandoubler_disable(1),//scandoublerD ), + .scanlines ( status[2:1] ), + .ypbpr ( ypbpr ) + ); + +user_io #(.STRLEN(($size(CONF_STR)>>3)))user_io( + .clk_sys (clk_25 ), + .conf_str (CONF_STR ), + .SPI_CLK (SPI_SCK ), + .SPI_SS_IO (CONF_DATA0 ), + .SPI_MISO (SPI_DO ), + .SPI_MOSI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable (scandoublerD ), + .ypbpr (ypbpr ), + .key_strobe (key_strobe ), + .key_pressed (key_pressed ), + .key_code (key_code ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) + ); + +dac #( + .C_bits(8)) +dac( + .clk_i(clk_25), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +wire m_up = btn_up | joystick_0[3] | joystick_1[3]; +wire m_down = btn_down | joystick_0[2] | joystick_1[2]; +wire m_left = btn_left | joystick_0[1] | joystick_1[1]; +wire m_right = btn_right | joystick_0[0] | joystick_1[0]; +wire m_fire1 = btn_fire1 | joystick_0[4] | joystick_1[4]; +wire m_fire2 = btn_fire2 | joystick_0[5] | joystick_1[5]; +//wire m_fire3 = btn_fire3 | joystick_0[6] | joystick_1[6]; +reg btn_one_player = 0; +reg btn_left = 0; +reg btn_right = 0; +reg btn_down = 0; +reg btn_up = 0; +reg btn_fire1 = 0; +reg btn_fire2 = 0; +//reg btn_fire3 = 0; +reg btn_coin = 0; + +always @(posedge clk_25) begin + reg old_state; + old_state <= key_strobe; + if(old_state != key_strobe) begin + case(key_code) + 'h75: btn_up <= key_pressed; // up + 'h72: btn_down <= key_pressed; // down + 'h6B: btn_left <= key_pressed; // left + 'h74: btn_right <= key_pressed; // right + 'h76: btn_coin <= key_pressed; // ESC + 'h05: btn_one_player <= key_pressed; // F1 +// 'h14: btn_fire3 <= key_pressed; // ctrl + 'h11: btn_fire2 <= key_pressed; // alt + 'h29: btn_fire1 <= key_pressed; // Space + endcase + end +end + +endmodule \ No newline at end of file diff --git a/Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/base_pack.vhd b/Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/base_pack.vhd new file mode 100644 index 00000000..6fcd2338 --- /dev/null +++ b/Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/base_pack.vhd @@ -0,0 +1,593 @@ +-------------------------------------------------------------------------------- +-- BASE +-- Definitions +-------------------------------------------------------------------------------- +-- DO 3/2009 +-------------------------------------------------------------------------------- +-- Base +-------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +PACKAGE base_pack IS + -------------------------------------- + SUBTYPE uv IS unsigned; + SUBTYPE sv IS signed; + + SUBTYPE uv1_0 IS unsigned(1 DOWNTO 0); + SUBTYPE uv0_1 IS unsigned(0 TO 1); + SUBTYPE uv3_0 IS unsigned(3 DOWNTO 0); + SUBTYPE uv0_3 IS unsigned(0 TO 3); + SUBTYPE uv7_0 IS unsigned(7 DOWNTO 0); + SUBTYPE uv0_7 IS unsigned(0 TO 7); + + SUBTYPE uv2 IS unsigned(1 DOWNTO 0); + SUBTYPE uv3 IS unsigned(2 DOWNTO 0); + SUBTYPE uv4 IS unsigned(3 DOWNTO 0); + SUBTYPE uv5 IS unsigned(4 DOWNTO 0); + SUBTYPE uv6 IS unsigned(5 DOWNTO 0); + SUBTYPE uv7 IS unsigned(6 DOWNTO 0); + SUBTYPE uv8 IS unsigned(7 DOWNTO 0); + SUBTYPE uv9 IS unsigned(8 DOWNTO 0); + SUBTYPE uv10 IS unsigned(9 DOWNTO 0); + SUBTYPE uv11 IS unsigned(10 DOWNTO 0); + SUBTYPE uv12 IS unsigned(11 DOWNTO 0); + SUBTYPE uv13 IS unsigned(12 DOWNTO 0); + SUBTYPE uv14 IS unsigned(13 DOWNTO 0); + SUBTYPE uv15 IS unsigned(14 DOWNTO 0); + SUBTYPE uv16 IS unsigned(15 DOWNTO 0); + SUBTYPE uv24 IS unsigned(23 DOWNTO 0); + SUBTYPE uv32 IS unsigned(31 DOWNTO 0); + SUBTYPE uv64 IS unsigned(63 DOWNTO 0); + SUBTYPE uv128 IS unsigned(127 DOWNTO 0); + + SUBTYPE sv2 IS signed(1 DOWNTO 0); + SUBTYPE sv4 IS signed(3 DOWNTO 0); + SUBTYPE sv8 IS signed(7 DOWNTO 0); + SUBTYPE sv16 IS signed(15 DOWNTO 0); + SUBTYPE sv32 IS signed(31 DOWNTO 0); + SUBTYPE sv64 IS signed(63 DOWNTO 0); + SUBTYPE sv128 IS signed(127 DOWNTO 0); + + TYPE arr_uv0_3 IS ARRAY(natural RANGE <>) OF uv0_3; + TYPE arr_uv0_7 IS ARRAY(natural RANGE <>) OF uv0_7; + + TYPE arr_uv4 IS ARRAY(natural RANGE <>) OF uv4; + TYPE arr_uv8 IS ARRAY(natural RANGE <>) OF uv8; + TYPE arr_uv16 IS ARRAY(natural RANGE <>) OF uv16; + TYPE arr_uv32 IS ARRAY(natural RANGE <>) OF uv32; + TYPE arr_uv64 IS ARRAY(natural RANGE <>) OF uv64; + + SUBTYPE uint1 IS natural RANGE 0 TO 1; + SUBTYPE uint2 IS natural RANGE 0 TO 3; + SUBTYPE uint3 IS natural RANGE 0 TO 7; + SUBTYPE uint4 IS natural RANGE 0 TO 15; + SUBTYPE uint5 IS natural RANGE 0 TO 31; + SUBTYPE uint6 IS natural RANGE 0 TO 63; + SUBTYPE uint7 IS natural RANGE 0 TO 127; + SUBTYPE uint8 IS natural RANGE 0 TO 255; + SUBTYPE uint12 IS natural RANGE 0 TO 4095; + SUBTYPE uint16 IS natural RANGE 0 TO 65535; + SUBTYPE uint24 IS natural RANGE 0 TO 16777215; + + ------------------------------------------------------------- + FUNCTION v_or (CONSTANT v : unsigned) RETURN std_logic; + FUNCTION v_and (CONSTANT v : unsigned) RETURN std_logic; + FUNCTION vv (CONSTANT s : std_logic; + CONSTANT N : natural) RETURN unsigned; + + -------------------------------------- + FUNCTION to_std_logic (a : boolean) RETURN std_logic; + -------------------------------------- + FUNCTION mux ( + s : std_logic; + a : unsigned; + b : unsigned) RETURN unsigned; + -------------------------------------- + FUNCTION mux ( + s : boolean; + a : unsigned; + b : unsigned) RETURN unsigned; + -------------------------------------- + FUNCTION mux ( + s : std_logic; + a : std_logic; + b : std_logic) RETURN std_logic; + -------------------------------------- + FUNCTION mux ( + s : boolean; + a : std_logic; + b : std_logic) RETURN std_logic; + -------------------------------------- + FUNCTION mux ( + s : boolean; + a : boolean; + b : boolean) RETURN boolean; + -------------------------------------- + FUNCTION mux ( + s : boolean; + a : natural; + b : natural) RETURN natural; + -------------------------------------- + FUNCTION mux ( + s : std_logic; + a : character; + b : character) RETURN character; + -------------------------------------- + FUNCTION mux ( + s : boolean; + a : character; + b : character) RETURN character; + -------------------------------------- + FUNCTION sext ( + e : unsigned; + l : natural) RETURN unsigned; + -------------------------------------- + FUNCTION sext ( + e : std_logic; + l : natural) RETURN unsigned; + -------------------------------------- + FUNCTION uext ( + e : unsigned; + l : natural) RETURN unsigned; + -------------------------------------- + FUNCTION uext ( + e : std_logic; + l : natural) RETURN unsigned; + -------------------------------------- + PROCEDURE wure ( + SIGNAL clk : IN std_logic; + CONSTANT n : IN natural:=1); + -------------------------------------- + PROCEDURE wufe ( + SIGNAL clk : IN std_logic; + CONSTANT n : IN natural:=1); + -------------------------------------- + FUNCTION To_HString (v : unsigned) RETURN string; + FUNCTION To_String (v : unsigned) RETURN string; + -------------------------------------- + FUNCTION To_Upper (c : character) RETURN character; + FUNCTION To_Upper (s : string) RETURN string; + FUNCTION To_String (i : natural; b : integer) RETURN string; + FUNCTION To_Natural (s : string; b : integer) RETURN natural; + + FUNCTION ilog2 (CONSTANT v : natural) RETURN natural; + +END PACKAGE base_pack; + +-------------------------------------------------------------------------------- + +PACKAGE BODY base_pack IS + + ------------------------------------------------------------- + FUNCTION vv (CONSTANT s : std_logic; + CONSTANT N : natural) RETURN unsigned IS + VARIABLE v : unsigned(N-1 DOWNTO 0); + BEGIN + v:=(OTHERS => s); + RETURN v; + END FUNCTION vv; + + ------------------------------------------------------------- + -- Vector OR (reduce) + FUNCTION v_or (CONSTANT v : unsigned) RETURN std_logic IS + VARIABLE r : std_logic := '0'; + VARIABLE Z : unsigned(v'range) := (OTHERS =>'0'); + BEGIN +--pragma synthesis_off + IF 1=1 THEN + FOR I IN v'range LOOP + r:=r OR v(I); + END LOOP; + RETURN r; + ELSE +--pragma synthesis_on + IF v/=Z THEN + RETURN '1'; + ELSE + RETURN '0'; + END IF; +--pragma synthesis_off + END IF; +--pragma synthesis_on + END FUNCTION v_or; + + ------------------------------------------------------------- + -- Vector AND (reduce) + FUNCTION v_and (CONSTANT v : unsigned) RETURN std_logic IS + VARIABLE r : std_logic := '1'; + VARIABLE U : unsigned(v'range) := (OTHERS =>'1'); + BEGIN +--pragma synthesis_off + IF 1=1 THEN + FOR I IN v'range LOOP + r:=r AND v(I); + END LOOP; + RETURN r; + ELSE +--pragma synthesis_on + IF v/=U THEN + RETURN '0'; + ELSE + RETURN '1'; + END IF; +--pragma synthesis_off + END IF; +--pragma synthesis_on + END FUNCTION v_and; + + -------------------------------------- + FUNCTION to_std_logic (a : boolean) RETURN std_logic IS + BEGIN + IF a THEN RETURN '1'; + ELSE RETURN '0'; + END IF; + END FUNCTION to_std_logic; + + -------------------------------------- + -- Sélection/Multiplexage s=1:a, s=0:b + FUNCTION mux ( + s : std_logic; + a : unsigned; + b : unsigned) RETURN unsigned IS + VARIABLE x : unsigned(a'range) :=(OTHERS => 'X'); + BEGIN + ASSERT a'length=b'length + REPORT "mux(): Different lengths" SEVERITY failure; + IF s='1' THEN + RETURN a; + ELSIF s='0' THEN + RETURN b; + ELSE + RETURN x; + END IF; + END FUNCTION mux; + + -------------------------------------- + -- Sélection/Multiplexage s=true:a, s=false:b + FUNCTION mux ( + s : boolean; + a : unsigned; + b : unsigned) RETURN unsigned IS + BEGIN + ASSERT a'length=b'length + REPORT "mux(): Different lengths" SEVERITY failure; + IF s THEN + RETURN a; + ELSE + RETURN b; + END IF; + END FUNCTION mux; + + -------------------------------------- + -- Sélection/Multiplexage s=1:a, s=0:b + FUNCTION mux ( + s : std_logic; + a : std_logic; + b : std_logic) + RETURN std_logic IS + BEGIN + RETURN (S AND A) OR (NOT S AND B); + END FUNCTION mux; + + -------------------------------------- + -- Sélection/Multiplexage s=true:a, s=false:b + FUNCTION mux ( + s : boolean; + a : std_logic; + b : std_logic) + RETURN std_logic IS + BEGIN + IF s THEN + RETURN a; + ELSE + RETURN b; + END IF; + END FUNCTION mux; + + -------------------------------------- + -- Sélection/Multiplexage s=true:a, s=false:b + FUNCTION mux ( + s : boolean; + a : boolean; + b : boolean) + RETURN boolean IS + BEGIN + IF s THEN + RETURN a; + ELSE + RETURN b; + END IF; + END FUNCTION mux; + + -------------------------------------- + -- Sélection/Multiplexage s=1:a, s=0:b + FUNCTION mux ( + s : boolean; + a : natural; + b : natural) + RETURN natural IS + BEGIN + IF s THEN + RETURN a; + ELSE + RETURN b; + END IF; + END FUNCTION mux; + + -------------------------------------- + -- Sélection/Multiplexage s=true:a, s=false:b + FUNCTION mux ( + s : std_logic; + a : character; + b : character) + RETURN character IS + BEGIN + IF s='1' THEN + RETURN a; + ELSE + RETURN b; + END IF; + END FUNCTION mux; + + -------------------------------------- + -- Sélection/Multiplexage s=true:a, s=false:b + FUNCTION mux ( + s : boolean; + a : character; + b : character) + RETURN character IS + BEGIN + IF s THEN + RETURN a; + ELSE + RETURN b; + END IF; + END FUNCTION mux; + + -------------------------------------- + -- Étend un vecteur avec extension de signe + FUNCTION sext ( + e : unsigned; + l : natural) RETURN unsigned IS + VARIABLE t : unsigned(l-1 DOWNTO 0); + BEGIN + -- Vérifier numeric_std.resize ... + t:=(OTHERS => e(e'left)); + t(e'length-1 DOWNTO 0):=e; + RETURN t; + END FUNCTION sext; + + -------------------------------------- + -- Étend un vecteur avec extension de signe + FUNCTION sext ( + e : std_logic; + l : natural) RETURN unsigned IS + VARIABLE t : unsigned(l-1 DOWNTO 0); + BEGIN + -- Vérifier numeric_std.resize ... + t:=(OTHERS => e); + RETURN t; + END FUNCTION sext; + + -------------------------------------- + -- Étend un vecteur sans extension de signe + FUNCTION uext ( + e : unsigned; + l : natural) RETURN unsigned IS + VARIABLE t : unsigned(l-1 DOWNTO 0); + BEGIN + -- Vérifier numeric_std.resize ... + t:=(OTHERS => '0'); + t(e'length-1 DOWNTO 0):=e; + RETURN t; + END FUNCTION uext; + + -------------------------------------- + -- Étend un vecteur sans extension de signe + FUNCTION uext ( + e : std_logic; + l : natural) RETURN unsigned IS + VARIABLE t : unsigned(l-1 DOWNTO 0); + BEGIN + -- Vérifier numeric_std.resize ... + t:=(OTHERS => '0'); + t(0):=e; + RETURN t; + END FUNCTION uext; + + -------------------------------------- + -- Wait Until Rising Edge + PROCEDURE wure( + SIGNAL clk : IN std_logic; + CONSTANT n : IN natural:=1) IS + BEGIN + FOR i IN 1 TO n LOOP + WAIT UNTIL rising_edge(clk); + END LOOP; + END PROCEDURE wure; + + -------------------------------------- + -- Wait Until Rising Edge + PROCEDURE wufe( + SIGNAL clk : IN std_logic; + CONSTANT n : IN natural:=1) IS + BEGIN + FOR i IN 1 TO n LOOP + WAIT UNTIL falling_edge(clk); + END LOOP; + END PROCEDURE wufe; + + -------------------------------------- + CONSTANT HexString : string(1 TO 16):="0123456789ABCDEF"; + + -- Conversion unsigned -> Chaîne hexadécimale + FUNCTION To_HString(v : unsigned) RETURN string IS + VARIABLE r : string(1 TO ((v'length)+3)/4); + VARIABLE x : unsigned(1 TO v'length); + VARIABLE i,j : integer; + BEGIN + x:=v; + i:=1; + j:=1; + r:=(OTHERS =>' '); + WHILE i Chaîne binaire + FUNCTION To_String(v : unsigned) RETURN string IS + VARIABLE r : string(1 TO v'length); + VARIABLE x : unsigned(1 TO v'length); + BEGIN + x:=v; + FOR i IN 1 TO v'length LOOP + CASE x(i) IS + WHEN '0' => r(i):='0'; + WHEN '1' => r(i):='1'; + WHEN 'X' => r(i):='X'; + WHEN 'Z' => r(i):='Z'; + WHEN 'U' => r(i):='U'; + WHEN 'H' => r(i):='H'; + WHEN 'L' => r(i):='L'; + WHEN '-' => r(i):='-'; + WHEN 'W' => r(i):='W'; + END CASE; + -- r(i):=std_logic'image(x(i))(1); + END LOOP; + RETURN r; + END FUNCTION To_String; + + -------------------------------------- + -- Conversion majuscules caractère + FUNCTION To_Upper(c : character) RETURN character IS + VARIABLE r : character; + BEGIN + CASE c IS + WHEN 'a' => r := 'A'; + WHEN 'b' => r := 'B'; + WHEN 'c' => r := 'C'; + WHEN 'd' => r := 'D'; + WHEN 'e' => r := 'E'; + WHEN 'f' => r := 'F'; + WHEN 'g' => r := 'G'; + WHEN 'h' => r := 'H'; + WHEN 'i' => r := 'I'; + WHEN 'j' => r := 'J'; + WHEN 'k' => r := 'K'; + WHEN 'l' => r := 'L'; + WHEN 'm' => r := 'M'; + WHEN 'n' => r := 'N'; + WHEN 'o' => r := 'O'; + WHEN 'p' => r := 'P'; + WHEN 'q' => r := 'Q'; + WHEN 'r' => r := 'R'; + WHEN 's' => r := 'S'; + WHEN 't' => r := 'T'; + WHEN 'u' => r := 'U'; + WHEN 'v' => r := 'V'; + WHEN 'w' => r := 'W'; + WHEN 'x' => r := 'X'; + WHEN 'y' => r := 'Y'; + WHEN 'z' => r := 'Z'; + WHEN OTHERS => r := c; + END CASE; + RETURN r; + END To_Upper; + + -------------------------------------- + -- Conversion majuscules chaîne + FUNCTION To_Upper(s: string) RETURN string IS + VARIABLE r: string (s'range); + BEGIN + FOR i IN s'range LOOP + r(i):= to_upper(s(i)); + END LOOP; + RETURN r; + END To_Upper; + + -------------------------------------- + -- Conversion entier -> chaîne + FUNCTION To_String(i: natural; b: integer) RETURN string IS + VARIABLE r : string(1 TO 10); + VARIABLE j,k : natural; + VARIABLE t : character; + BEGIN + j:=i; + k:=10; + WHILE j>=b LOOP + r(k):=HexString(j MOD b); + j:=j/b; + k:=k-1; + END LOOP; + + RETURN r(k TO 10); + END FUNCTION To_String; + + -------------------------------------- + -- Conversion chaîne -> entier + FUNCTION To_Natural (s : string; b : integer) RETURN natural IS + VARIABLE v,r : natural; + BEGIN + r:=0; + FOR i IN s'range LOOP + CASE s(i) IS + WHEN '0' => v:=0; + WHEN '1' => v:=1; + WHEN '2' => v:=2; + WHEN '3' => v:=3; + WHEN '4' => v:=4; + WHEN '5' => v:=5; + WHEN '6' => v:=6; + WHEN '7' => v:=7; + WHEN '8' => v:=8; + WHEN '9' => v:=9; + WHEN 'a' | 'A' => v:=10; + WHEN 'b' | 'B' => v:=11; + WHEN 'c' | 'C' => v:=12; + WHEN 'd' | 'D' => v:=13; + WHEN 'e' | 'E' => v:=14; + WHEN 'f' | 'F' => v:=15; + WHEN OTHERS => + v:=1000; + END CASE; + ASSERT vr LOOP + n:=n+1; + r:=r*2; + END LOOP; + RETURN n; + END FUNCTION ilog2; + +END PACKAGE BODY base_pack; diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/build_id.tcl b/Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/build_id.tcl similarity index 100% rename from Arcade_MiST/NinjaKun_MiST/rtl/build_id.tcl rename to Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/build_id.tcl diff --git a/Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/dpram.vhd b/Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..fb0bfc8b --- /dev/null +++ b/Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/dpram.vhd @@ -0,0 +1,75 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +entity dpram is + generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 + ); + PORT + ( + address_a : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + clock_a : IN STD_LOGIC := '1'; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) := (others => '0'); + enable_a : IN STD_LOGIC := '1'; + enable_b : IN STD_LOGIC := '1'; + wren_a : IN STD_LOGIC := '0'; + wren_b : IN STD_LOGIC := '0'; + q_a : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) + ); +END dpram; + + +ARCHITECTURE SYN OF dpram IS +BEGIN + altsyncram_component : altsyncram + GENERIC MAP ( + address_reg_b => "CLOCK1", + clock_enable_input_a => "NORMAL", + clock_enable_input_b => "NORMAL", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", + intended_device_family => "Cyclone III", + lpm_type => "altsyncram", + numwords_a => 2**addr_width_g, + numwords_b => 2**addr_width_g, + operation_mode => "BIDIR_DUAL_PORT", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => "UNREGISTERED", + outdata_reg_b => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", + widthad_a => addr_width_g, + widthad_b => addr_width_g, + width_a => data_width_g, + width_b => data_width_g, + width_byteena_a => 1, + width_byteena_b => 1, + wrcontrol_wraddress_reg_b => "CLOCK1" + ) + PORT MAP ( + address_a => address_a, + address_b => address_b, + clock0 => clock_a, + clock1 => clock_b, + clocken0 => enable_a, + clocken1 => enable_b, + data_a => data_a, + data_b => data_b, + wren_a => wren_a, + wren_b => wren_b, + q_a => q_a, + q_b => q_b + ); + +END SYN; diff --git a/Arcade_MiST/Sega Zaxxon Hardware/rtl/gen_ram.vhd b/Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/gen_ram.vhd similarity index 100% rename from Arcade_MiST/Sega Zaxxon Hardware/rtl/gen_ram.vhd rename to Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/gen_ram.vhd diff --git a/Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/llander.vhd b/Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/llander.vhd new file mode 100644 index 00000000..7ae44809 --- /dev/null +++ b/Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/llander.vhd @@ -0,0 +1,648 @@ +-- +-- A simulation model of Lunar Lander hardware +-- James Sweet 2019 +-- This is not endorsed by fpgaarcade, please do not bother MikeJ with support requests +-- +-- Built upon model of Asteroids Deluxe hardware +-- Copyright (c) MikeJ - May 2004 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity LLander is + port ( + CLK_6 : in std_logic; + CLK_25 : in std_logic; + RESET_6_L : in std_logic; + -- + DIP : in std_logic_vector(7 downto 0); + -- + ROT_LEFT_L : in std_logic; + ROT_RIGHT_L : in std_logic; + ABORT_L : in std_logic; + GAME_SEL_L : in std_logic; + START_L : in std_logic; + COIN1_L : in std_logic; + COIN2_L : in std_logic; + -- + THRUST : in std_logic_vector(7 downto 0); + -- + DIAG_STEP_L : in std_logic; + SLAM_L : in std_logic; + SELF_TEST_L : in std_logic; + -- + START_SEL_L : out std_logic; + LAMP2 : out std_logic; + LAMP3 : out std_logic; + LAMP4 : out std_logic; + LAMP5 : out std_logic; + COIN_CTR : out std_logic; + -- + AUDIO_OUT : out std_logic_vector(7 downto 0); + -- + X_VECTOR : out std_logic_vector(9 downto 0); + Y_VECTOR : out std_logic_vector(9 downto 0); + Z_VECTOR : out std_logic_vector(3 downto 0); + BEAM_ON : out std_logic; + BEAM_ENA : out std_logic + ); +end; + +architecture RTL of LLander is + + + signal ena_count : std_logic_vector(10 downto 0) := (others => '0'); + signal ena_3M : std_ulogic; + signal ena_1_5M : std_ulogic; + signal ena_1_5M_e : std_ulogic; + signal ena_3K : std_ulogic; + signal ena_12k : std_ulogic; + signal clk_3k : std_ulogic; + signal clk_6K : std_ulogic; + signal clk_12K : std_ulogic; + + -- cpu + signal c_addr : std_logic_vector(23 downto 0); + signal c_din : std_logic_vector(7 downto 0); + signal c_dout : std_logic_vector(7 downto 0); + signal c_rw_l : std_logic; + signal c_irq_l : std_logic; + signal c_nmi_l : std_logic; + signal reset_l : std_logic; + signal wd_cnt : std_logic_vector(7 downto 0); + -- + signal nmi_count : std_logic_vector(3 downto 0); + -- addr decode + signal zpage_l : std_logic; + signal io_l : std_logic; + signal vmem_l : std_logic; + signal pmem_l : std_logic; + -- + signal sinp0_l : std_logic; + signal sinp1_l : std_logic; + signal opts_l : std_logic; + signal pot_l : std_logic; + -- + signal dma_go_l : std_logic; + signal outck_l : std_logic; + signal wdclr_l : std_logic; + signal explode_l : std_logic; + signal dma_reset_l : std_logic; + signal audio_l : std_logic; + signal noiserst_l : std_logic; + -- + signal shipthrusten : std_logic; + -- + signal test_l : std_logic; + signal halt : std_logic; + + -- memory + signal rom0_dout : std_logic_vector(7 downto 0); + signal rom1_dout : std_logic_vector(7 downto 0); + signal rom2_dout : std_logic_vector(7 downto 0); + signal rom3_dout : std_logic_vector(7 downto 0); + signal rom_dout : std_logic_vector(7 downto 0); + signal ram_addr : std_logic_vector(9 downto 0); + signal ram_dout : std_logic_vector(7 downto 0); + signal vg_dout : std_logic_vector(7 downto 0); + signal ram_we : std_logic; + + -- io + signal dips_p6_l : std_logic_vector(7 downto 0); + signal dips_ip_sel : std_logic_vector(1 downto 0); + + signal control_ip0_l : std_logic_vector(7 downto 0); + signal control_ip0_sel : std_logic; + signal control_ip1_l : std_logic_vector(7 downto 0); + signal control_ip1_sel : std_logic; + + -- sound + signal aud : std_logic_vector(5 downto 0); + signal tone3khz : std_logic_vector(3 downto 0); + signal tone6khz : std_logic_vector(3 downto 0); + + signal t_e_vol : std_logic_vector(2 downto 0); + + signal noise_shift : std_logic_vector(15 downto 0); + signal noise : std_logic; + signal shpsnd : std_logic_vector(3 downto 0); + signal lifesnd : std_logic_vector(3 downto 0); + + + signal lifeen : std_logic; + signal shpsnd_prefilter : std_logic; + signal shpsnd_filter_t1 : std_logic_vector(3 downto 0); + signal shpsnd_filter_t2 : std_logic_vector(3 downto 0); + signal shpsnd_filter_t3 : std_logic_vector(3 downto 0); + signal shpsnd_filtered : std_logic_vector(5 downto 0); + signal expaud : std_logic_vector(2 downto 0); + signal expitch : std_logic_vector(1 downto 0); + signal noise_cnt : std_logic_vector(3 downto 0); + signal expld_snd : std_logic_vector(3 downto 0); + + + signal clkdiv2 : std_logic_vector(3 downto 0); + signal audio_out2 : std_logic_vector(7 downto 0); + +begin + + + + p_ena : process -- clock divider + begin + wait until rising_edge(CLK_6); + ena_count <= ena_count + "1"; + ena_3M <= not ena_count(0); -- 3 Mhz; + + ena_1_5M <= '0'; + ena_1_5M_e <= '0'; + if (ena_count(1 downto 0) = "00") then + ena_1_5M <= '1'; -- 1.5 Mhz + end if; + if (ena_count(1 downto 0) = "10") then + ena_1_5M_e <= '1'; -- 1.5 Mhz (early) + end if; + ena_12k <= '0'; + if (ena_count(8 downto 0) = "000000000") then + ena_12k <= '1'; + end if; + + ena_3k <= '0'; + if (ena_count(10 downto 0) = "00000000000") then + ena_3k <= '1'; + end if; + + clk_3k <= ena_count(10); + end process; + + + cpu : entity work.T65 -- main cpu + port map ( + Mode => "00", + Res_n => reset_l, + Enable => ena_1_5M, + Clk => CLK_6, + Rdy => '1', + Abort_n => '1', + IRQ_n => '1', + NMI_n => c_nmi_l, + SO_n => '1', + R_W_n => c_rw_l, + Sync => open, + EF => open, + MF => open, + XF => open, + ML_n => open, + VP_n => open, + VDA => open, + VPA => open, + A => c_addr, + DI => c_din, + DO => c_dout + ); + + + p_nmi : process(reset_l, CLK_6) + variable carry : boolean; + begin + if (reset_l = '0') then + c_nmi_l <= '1'; + nmi_count <= "0000"; + elsif rising_edge(CLK_6) then + -- divide 3k signal by 12 + carry := (nmi_count = "1111"); + + c_nmi_l <= '1'; + if (test_l = '1') and carry then + c_nmi_l <= '0'; + end if; + + if (ena_3K = '1') then + if carry then + nmi_count <= "0100"; + else + nmi_count <= nmi_count + "1"; + end if; + end if; + + end if; + end process; + + p_wd_reset : process(RESET_6_L, CLK_6) + begin + if (RESET_6_L = '0') then + wd_cnt <= "00000000"; + reset_l <= '0'; + elsif rising_edge(CLK_6) then + + if (wdclr_l = '0') then + wd_cnt <= "00000000"; + elsif (ena_3K = '1') then + wd_cnt <= wd_cnt + "1"; + end if; + + if (ena_3k = '1') and (wd_cnt = "01111111") then + reset_l <= not reset_l; + end if; + -- simulation + -- reset_l <= reset_6_l; + end if; + end process; + + p_addr_decode1 : process(c_addr, c_rw_l, ena_1_5M, reset_l) + variable deca : std_logic_vector(3 downto 0); + variable decb : std_logic_vector(3 downto 0); + variable decc : std_logic_vector(7 downto 0); + variable input_read : std_logic; + variable control_write : std_logic; + begin + -- cpu address bit 15 is tied to ground + -- as far as the rest of the system is concerned + deca := "1111"; + case c_addr(14 downto 13) is + when "00" => deca := "1110"; + when "01" => deca := "1101"; + when "10" => deca := "1011"; + when "11" => deca := "0111"; + when others => null; + end case; + zpage_l <= deca(0); + io_l <= deca(1); + vmem_l <= deca(2); + pmem_l <= deca(3); + + + input_read := (not deca(1)) and (not c_addr(12)) and c_rw_l; + decb := "1111"; + if (input_read = '1') then + case c_addr(11 downto 10) is + when "00" => decb := "1110"; + when "01" => decb := "1101"; + when "10" => decb := "1011"; + when "11" => decb := "0111"; + when others => null; + end case; + end if; + sinp0_l <= decb(0); + sinp1_l <= decb(1); + opts_l <= decb(2); + pot_l <= decb(3); + + control_write := (not deca(1)) and c_addr(12) and (not c_rw_l);-- and ena_1_5M; + decc := "11111111"; + if (control_write = '1') then + case c_addr(11 downto 9) is + when "000" => decc := "11111110"; + when "001" => decc := "11111101"; + when "010" => decc := "11111011"; + when "011" => decc := "11110111"; + when "100" => decc := "11101111"; + when "101" => decc := "11011111"; + when "110" => decc := "10111111"; + when "111" => decc := "01111111"; + when others => null; + end case; + end if; + dma_go_l <= decc(0); + outck_l <= decc(1); + wdclr_l <= decc(2); + dma_reset_l <= decc(4); + audio_l <= decc(6); + noiserst_l <= decc(7); + end process; + + + lamp_reg : process(reset_l, clk_6) + begin + if (reset_l = '0') then + lamp5 <= '0'; + lamp4 <= '0'; + lamp3 <= '0'; + lamp2 <= '0'; + start_sel_l <= '0'; + coin_ctr <= '0'; + elsif rising_edge(CLK_6) then + if (ena_1_5M = '1') then + if (outck_l = '0') then + lamp5 <= c_dout(0); + lamp4 <= c_dout(1); + lamp3 <= c_dout(2); + lamP2 <= c_dout(3); + start_sel_l <= c_dout(4); + coin_ctr <= c_dout(5); + end if; + end if; + end if; + end process; + + + p_input_registers : process + begin + wait until rising_edge(CLK_6); + dips_p6_l <= DIP; + + -- diag step, self test, slam, halt + control_ip0_l(7) <= DIAG_STEP_L; + control_ip0_l(6) <= clk_3k; + control_ip0_l(5) <= '1'; + control_ip0_l(4) <= '1'; + control_ip0_l(3) <= '1'; + control_ip0_l(2) <= SLAM_L; + control_ip0_l(1) <= test_l; + control_ip0_l(0) <= halt; + + test_l <= SELF_TEST_L; + + -- left, right, abort, game select, coin11, coin2, start + control_ip1_l(7) <= ROT_LEFT_L; + control_ip1_l(6) <= ROT_RIGHT_L; + control_ip1_l(5) <= ABORT_L; + control_ip1_l(4) <= GAME_SEL_L; + control_ip1_l(3) <= not COIN1_L; + control_ip1_l(2) <= '1'; + control_ip1_l(1) <= not COIN2_L; + control_ip1_l(0) <= START_L; + end process; + + + p_input_sel : process(c_addr, dips_p6_l, control_ip0_l, control_ip1_l, clk_3k, halt) + begin + control_ip1_sel <= '0'; + case c_addr(2 downto 0) is + when "000" => control_ip1_sel <= not control_ip1_l(0); + when "001" => control_ip1_sel <= not control_ip1_l(1); + when "010" => control_ip1_sel <= not control_ip1_l(2); + when "011" => control_ip1_sel <= not control_ip1_l(3); + when "100" => control_ip1_sel <= not control_ip1_l(4); + when "101" => control_ip1_sel <= not control_ip1_l(5); + when "110" => control_ip1_sel <= not control_ip1_l(6); + when "111" => control_ip1_sel <= not control_ip1_l(7); + when others => null; + end case; + + dips_ip_sel <= "00"; + case c_addr(1 downto 0) is + when "00" => dips_ip_sel <= dips_p6_l(1) & dips_p6_l(0); + when "01" => dips_ip_sel <= dips_p6_l(3) & dips_p6_l(2); + when "10" => dips_ip_sel <= dips_p6_l(5) & dips_p6_l(4); + when "11" => dips_ip_sel <= dips_p6_l(7) & dips_p6_l(6); + when others => null; + end case; + end process; + + rom0 : entity work.LLANDER_PROG_ROM_0 + port map ( + addr => c_addr(10 downto 0), + data => rom0_dout, + clk => CLK_6 + ); + + rom1 : entity work.LLANDER_PROG_ROM_1 + port map ( + addr => c_addr(10 downto 0), + data => rom1_dout, + clk => CLK_6 + ); + + rom2 : entity work.LLANDER_PROG_ROM_2 + port map ( + addr => c_addr(10 downto 0), + data => rom2_dout, + clk => CLK_6 + ); + + rom3 : entity work.LLANDER_PROG_ROM_3 + port map ( + addr => c_addr(10 downto 0), + data => rom3_dout, + clk => CLK_6 + ); + + p_rom_mux : process(c_addr, rom0_dout, rom1_dout, rom2_dout, rom3_dout) + begin + rom_dout <= (others => '0'); + case c_addr(12 downto 11) is + when "00" => rom_dout <= rom0_dout; + when "01" => rom_dout <= rom1_dout; + when "10" => rom_dout <= rom2_dout; + when "11" => rom_dout <= rom3_dout; + when others => null; + end case; + end process; + + +-- Zero-page RAM +--RAM: Entity work.RAM256 +--port map( +-- clock => clk_6, +-- address => c_addr(7 downto 0), +-- data => c_dout, +-- wren => ram_we, +-- q => ram_dout +-- ); + +RAM: Entity work.gen_ram + generic map( + dWidth => 8, + aWidth => 8) + port map( + clk => clk_6, + we => ram_we, + addr => c_addr(7 downto 0), + d => c_dout, + q => ram_dout + ); + +ram_we <= (not zpage_l) and (not c_rw_l) and ena_1_5M; + + +-- CPU Data in mux controlled by address decoder +p_cpu_data_mux : process(c_addr, ram_dout, rom_dout, vg_dout, zpage_l, pmem_l, vmem_l, + sinp0_l, control_ip0_l, sinp1_l, control_ip1_sel, + opts_l, dips_ip_sel, pot_l, thrust) +begin + c_din <= (others => '0'); + if (sinp0_l = '0') then + c_din <= control_ip0_l; + elsif (sinp1_l = '0') then + c_din <= control_ip1_sel & "1111111"; + elsif (opts_l = '0') then + c_din <= "111111" & dips_ip_sel; + elsif (pot_l = '0') then + c_din <= thrust ; + elsif (zpage_l = '0') then + c_din <= ram_dout; + elsif (pmem_l = '0') then + c_din <= rom_dout; + elsif (vmem_l = '0') then + c_din <= vg_dout; + end if; +end process; + + + -- + -- audio + -- + + -- Thrust Aud0 through Aud 2 - volume + -- Explosion - Aud 3, volume by Aud 0 through Aud 2 + -- 3k - Aud 4 + -- 6k - Aud 5 + + -- Output register for audio control + p_aud_reg : process(RESET_L, CLK_6) + begin + if (reset_l = '0') then + aud <= "000000"; + elsif rising_edge(CLK_6) then + if (ena_1_5M = '1') then + if (audio_l = '0') then + aud <= c_dout(5 downto 0); + end if; + end if; + end if; + end process; + + + tone3khz <= "1111" when clk_3k = '1' and aud(4) = '1' else "0000"; + tone6khz <= "1111" when clk_6k = '1' and aud(5) = '1' else "0000"; + t_e_vol <= aud(2 downto 0); + shipthrusten <= aud(0) or aud(1) or aud(2); + + + -- LFSR to generate noise used in the ship thrust and explosion sounds + p_noise_gen : process(RESET_L, CLK_6) + variable shift_in : std_logic; + begin + if (reset_l = '0') then + noise_shift <= (others => '0'); + noise <= '0'; + elsif rising_edge(CLK_6) then + if (ena_12k = '1') then + shift_in := not(noise_shift(6) xor noise_shift(14)); + noise_shift <= noise_shift(14 downto 0) & shift_in; + noise <= shift_in; -- one clock late + end if; + end if; + end process; + + -- Ship thrust sound, passes noise through a low pass filter + p_ship_snd : process + begin + wait until rising_edge(CLK_6); + shpsnd_prefilter <= noise and shipthrusten; + -- simple low pass filter + if (ena_3k = '1') then + if (shpsnd_prefilter = '1') then + shpsnd_filter_t1 <= t_e_vol & '0'; + else + shpsnd_filter_t1 <= "0000"; + end if; + shpsnd_filter_t2 <= shpsnd_filter_t1; + shpsnd_filter_t3 <= shpsnd_filter_t2; + end if; + shpsnd_filtered <= ("00" & shpsnd_filter_t1 ) + + ('0' & shpsnd_filter_t2 & '0') + + ("00" & shpsnd_filter_t3 ); + end process; + + + p_expld_gen : process(reset_l, clk_6, aud) + begin + if reset_l = '0' then + expaud <= "000"; + elsif (aud(3) = '1') and (noise = '1') then + expaud <= aud(2 downto 0); + else + expaud <= "000"; + end if; + end process; + + + p_audio_output_reg : process + variable sum : std_logic_vector(8 downto 0); + begin + wait until rising_edge(clk_6); + + sum := ('0' & tone6khz)+ ('0' & tone3khz)+ ("00" & expaud & "000") + ('0' & shpsnd_filtered & "00"); + + if (sum(8) = '0') then + AUDIO_OUT <= sum(7 downto 0); + else -- clip + AUDIO_OUT <= "11111111"; + end if; + end process; + + + -- + -- vector generator + -- + + vg : entity work.LLANDER_VG + port map ( + C_ADDR => c_addr(15 downto 0), + C_DIN => c_dout, + C_DOUT => vg_dout, + C_RW_L => c_rw_l, + VMEM_L => vmem_l, + + DMA_GO_L => dma_go_l, + DMA_RESET_L => dma_reset_l, + HALT_OP => halt, + + X_VECTOR => X_VECTOR, + Y_VECTOR => Y_VECTOR, + Z_VECTOR => Z_VECTOR, + BEAM_ON => BEAM_ON, + -- + ENA_1_5M => ena_1_5m, + ENA_1_5M_E => ena_1_5m_e, + RESET_L => reset_l, + CLK_6 => CLK_6, + CLK_25 => CLK_25 + ); + + BEAM_ENA <= ena_1_5m; + + +end RTL; diff --git a/Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/llander_dw.vhd b/Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/llander_dw.vhd new file mode 100644 index 00000000..7fb8a131 --- /dev/null +++ b/Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/llander_dw.vhd @@ -0,0 +1,450 @@ +-- +-- A simulation model of Asteroids Deluxe hardware +-- Copyright (c) MikeJ - May 2004 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- +-- This code is not part of the original game. + +-- Dave Wood (oldgit) Feb 2019 + +-- My smaller version (512 x 512 screen). This module takes the Vectors and beam intensisty and +-- produces a double buffered raster graphics screen. The intensity was used to give a 'blue hue' as per the original game +-- to the rocks and text but produces white for the ships. + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +--use work.pkg_asteroids.all; + +entity LLANDER_DW is + port ( + RESET : in std_logic; + clk_25 : in std_logic; + clk_6 : in std_logic; + + X_VECTOR : in std_logic_vector(9 downto 0); + Y_VECTOR : in std_logic_vector(9 downto 0); + Z_VECTOR : in std_logic_vector(3 downto 0); + BEAM_ON : in std_logic; + BEAM_ENA : in std_logic; + + VIDEO_R_OUT : out std_logic_vector(3 downto 0); + VIDEO_G_OUT : out std_logic_vector(3 downto 0); + VIDEO_B_OUT : out std_logic_vector(3 downto 0); + HSYNC_OUT : out std_logic; + VSYNC_OUT : out std_logic; + VID_DE : out std_logic; + VID_HBLANK : out std_logic; + VID_VBLANK : out std_logic; + + vram_write_addr : out std_logic_vector(18 downto 0); + vram_write_data : out std_logic_vector(3 downto 0); + vram_read_addr : out std_logic_vector(18 downto 0); + vram_read_data : in std_logic_vector(3 downto 0); + vram_wren : out std_logic + ); +end; + +architecture RTL of LLANDER_DW is + -- types & constants + subtype Bus12 is std_logic_vector (11 downto 0); + + constant V_FRONT_PORCH_START : Bus12 := x"1e0"; -- line 480 + constant V_SYNC_START : Bus12 := x"1ea"; -- line 490 + constant V_BACK_PORCH_START : Bus12 := x"1ec"; -- line 492 + constant LINE_PER_FRAME : Bus12 := x"20d"; -- 525 lines + + constant H_FRONT_PORCH_START : Bus12 := x"280"; -- pixel 640 + constant H_SYNC_START : Bus12 := x"290"; -- pixel 656 + constant H_BACK_PORCH_START : Bus12 := x"2f0"; -- pixel 752 + constant PIXEL_PER_LINE : Bus12 := x"320"; -- 800 pixels + + signal lcount : std_logic_vector(9 downto 0); + signal pcount : std_logic_vector(10 downto 0); + + signal hterm : boolean; + signal vterm : boolean; + signal v_sync : std_logic; + signal h_sync : std_logic; + signal v_blank : std_logic; + signal h_blank : std_logic; + signal raster_active : std_logic; + + -- + signal beam_ena_t : std_logic_vector(2 downto 0); + signal beam_load : std_logic; + signal video_r : std_logic_vector(3 downto 0); + signal video_g : std_logic_vector(3 downto 0); + signal video_b : std_logic_vector(3 downto 0); + + signal dw_addr : std_logic_vector(18 downto 0); + + signal up_addr : std_logic_vector(17 downto 0); + signal vid_out : std_logic_vector(3 downto 0); + signal Y_Vid : std_logic_vector(8 downto 0); + signal X_Vid : std_logic_vector(8 downto 0); + signal Vid_data : std_logic_vector(3 downto 0); + + signal dcount : std_logic_vector(2 downto 0); + signal screen : std_logic_vector(0 downto 0); + signal vcount : std_logic_vector(8 downto 0); + signal hcount : std_logic_vector(8 downto 0); + signal pxcount : std_logic_vector(8 downto 0); +-- signal vram_wren : std_logic; + + + + + +begin + + pixel_cnt : process(clk_25, RESET) + variable vcnt_front_porch_start : boolean; + variable hcnt_front_porch_start : boolean; + begin + if (RESET = '1') then + hcount <= (others => '0'); + vcount <= (others => '0'); + + elsif rising_edge(clk_25) then + + vcnt_front_porch_start := (vcount = 511); + hcnt_front_porch_start := (hcount = 511); + + if hcnt_front_porch_start then + hcount <= (others => '0'); + else + hcount <= hcount + "1"; + end if; + + if hcnt_front_porch_start then + if vcnt_front_porch_start then + vcount <= (others => '0'); + + else + vcount <= vcount + "1"; + end if; + end if; + + end if; + end process; + + -- basic raster gen + p_cnt_compare_comb : process(pcount,lcount) + begin + hterm <= (pcount = (PIXEL_PER_LINE(10 downto 0) - "1")); + vterm <= (lcount = (LINE_PER_FRAME( 9 downto 0) - "1")); + end process; + + p_display_cnt : process(clk_25, RESET) + begin + if (RESET = '1') then + pcount <= (others => '0'); + lcount <= (others => '0'); + dcount <= (others => '0'); + elsif rising_edge(clk_25) then + if hterm then + pcount <= (others => '0'); + else + pcount <= pcount + "1"; + end if; + + if pcount > 63 then + pxcount <= pxcount + "1"; + raster_active <= '1'; + end if; + if pcount > 575 then + raster_active <= '0'; + pxcount <= "111111111"; + end if; + + + if hterm then + if vterm then + lcount <= (others => '0'); + dcount <= dcount + "1" ; + else + lcount <= lcount + "1"; + end if; + end if; + + end if; + end process; + + p_vsync : process(clk_25, RESET) + variable vcnt_eq_front_porch_start : boolean; + variable vcnt_eq_sync_start : boolean; + variable vcnt_eq_back_porch_start : boolean; + begin + if (RESET = '1') then + v_sync <= '1'; + v_blank <= '0'; + elsif rising_edge(clk_25) then + + vcnt_eq_front_porch_start := (lcount = (V_FRONT_PORCH_START(9 downto 0) - "1")); + vcnt_eq_sync_start := (lcount = ( V_SYNC_START(9 downto 0) - "1")); + vcnt_eq_back_porch_start := (lcount = ( V_BACK_PORCH_START(9 downto 0) - "1")); + + if vcnt_eq_sync_start and hterm then + v_sync <= '0'; + elsif vcnt_eq_back_porch_start and hterm then + v_sync <= '1'; + end if; + + if vcnt_eq_front_porch_start and hterm then + v_blank <= '1'; + elsif vterm and hterm then + v_blank <= '0'; + end if; + + end if; + end process; + + p_hsync : process(clk_25, RESET) + variable hcnt_eq_front_porch_start : boolean; + variable hcnt_eq_sync_start : boolean; + variable hcnt_eq_back_porch_start : boolean; + begin + if (RESET = '1') then + h_sync <= '1'; + h_blank <= '1'; -- 0 + elsif rising_edge(clk_25) then + hcnt_eq_front_porch_start := (pcount = ( H_FRONT_PORCH_START(10 downto 0) - "1")); + hcnt_eq_sync_start := (pcount = ( H_SYNC_START(10 downto 0) - "1")); + hcnt_eq_back_porch_start := (pcount = ( H_BACK_PORCH_START(10 downto 0) - "1")); + + if hcnt_eq_sync_start then + h_sync <= '0'; + elsif hcnt_eq_back_porch_start then + h_sync <= '1'; + end if; + + if hcnt_eq_front_porch_start then + h_blank <= '1'; + elsif hterm then + h_blank <= '0'; + end if; + + end if; + end process; + + p_active_video : process(h_blank, v_blank, raster_active, lcount, pxcount) + begin +-- raster_active <= not(h_blank or v_blank); + if raster_active = '1' then + Y_Vid <= not (lcount(8 downto 0) and lcount(8 downto 0)) ; + else + Y_Vid <= "111111111"; + end if; + if raster_active = '1' then + X_Vid <= pxcount(8 downto 0); + else + X_Vid <= "111111111"; + end if; + + end process; + + p_video_out : process + begin + wait until rising_edge(clk_25); + if raster_active = '1' then + case vid_out is + when "0000" => video_r <= "0000";video_g <= "0000";video_b <= "0000"; + when "0001" => video_r <= "0001";video_g <= "0001";video_b <= "0001"; + when "0010" => video_r <= "0011";video_g <= "0011";video_b <= "0011"; + when "0011" => video_r <= "0011";video_g <= "0011";video_b <= "0011"; + when "0100" => video_r <= "0011";video_g <= "0011";video_b <= "0111"; + when "0101" => video_r <= "0011";video_g <= "0011";video_b <= "0111"; + when "0110" => video_r <= "0011";video_g <= "0011";video_b <= "0111"; + when "0111" => video_r <= "0011";video_g <= "0011";video_b <= "0111"; + -- when "1000" => video_r <= "0111";video_g <= "0111";video_b <= "0111"; + when "1000" => video_r <= "0011";video_g <= "0011";video_b <= "0111"; + --when "1001" => video_r <= "0111";video_g <= "0111";video_b <= "0111"; + when "1001" => video_r <= "0011";video_g <= "0011";video_b <= "0111"; + when "1010" => video_r <= "0111";video_g <= "0111";video_b <= "0111"; + when "1011" => video_r <= "0111";video_g <= "0111";video_b <= "0111"; + when "1100" => video_r <= "1111";video_g <= "1111";video_b <= "1111"; + when "1101" => video_r <= "1111";video_g <= "1111";video_b <= "1111"; + when "1110" => video_r <= "1111";video_g <= "1111";video_b <= "1111"; + when others => video_r <= "1111";video_g <= "1111";video_b <= "1111"; + end case; + VIDEO_R_OUT <= video_r; + VIDEO_G_OUT <= video_g; + VIDEO_B_OUT <= video_b; + else -- blank + VIDEO_R_OUT <= "0000"; + VIDEO_G_OUT <= "0000"; + VIDEO_B_OUT <= "0000"; + end if; + VID_DE <= not(v_blank or h_blank); + VSYNC_OUT <= v_sync; + HSYNC_OUT <= h_sync; + VID_HBLANK <= h_blank; + VID_VBLANK <= v_blank; + + end process; + + up_addr <= (Y_Vid(8 downto 0) & X_Vid(8 downto 0)); + + clear_ram : process(clk_25, RESET) + variable state : integer range 0 to 4; + variable beam_ena_r : std_logic := '0'; + + begin + if RESET = '1' then + beam_ena_r := '0'; + + elsif rising_edge(clk_25) then + vram_wren <= '0' after 2 ns; + + if dcount = "000" then + screen <= "0"; + dw_addr <= "0" & ((Y_VECTOR(9 downto 1) ) & X_VECTOR(9 downto 1)); + if BEAM_ON = '1' and beam_ena_r = '0' and BEAM_ENA = '1' then + if Z_VECTOR(3 downto 0) = "0000" then + vid_data <= "0000"; + vram_wren <= '0'; + else + vid_data <= Z_VECTOR(3 downto 0); + vram_wren <= '1'; + end if; + end if; + end if; + if dcount = "001" then + screen <= "0"; + dw_addr <= "1" & (vcount ) & hcount; + vid_data <= "0000"; + vram_wren <= '1'; + end if; + if dcount = "010" then + screen <= "0"; + dw_addr <= "0" & ((Y_VECTOR(9 downto 1) ) & X_VECTOR(9 downto 1)); + if BEAM_ON = '1' and beam_ena_r = '0' and BEAM_ENA = '1' then + if Z_VECTOR(3 downto 0) = "0000" then + vid_data <= "0000"; + vram_wren <= '0'; + else + vid_data <= Z_VECTOR(3 downto 0); + vram_wren <= '1'; + end if; + end if; + end if; + if dcount = "011" then + screen <= "0"; + dw_addr <= "1" & ((Y_VECTOR(9 downto 1) ) & X_VECTOR(9 downto 1)); + if BEAM_ON = '1' and beam_ena_r = '0' and BEAM_ENA = '1' then + if Z_VECTOR(3 downto 0) = "0000" then + vid_data <= "0000"; + vram_wren <= '0'; + else + vid_data <= Z_VECTOR(3 downto 0); + vram_wren <= '1'; + end if; + end if; + end if; + if dcount = "100" then + screen <= "1"; + dw_addr <= "1" & ((Y_VECTOR(9 downto 1) ) & X_VECTOR(9 downto 1)); + if BEAM_ON = '1' and beam_ena_r = '0' and BEAM_ENA = '1' then + if Z_VECTOR(3 downto 0) = "0000" then + vid_data <= "0000"; + vram_wren <= '0'; + else + vid_data <= Z_VECTOR(3 downto 0); + vram_wren <= '1'; + end if; + end if; + end if; + if dcount = "101" then + screen <= "1"; + dw_addr <= "0" & (vcount ) & hcount; + vid_data <= "0000"; + vram_wren <= '1'; + end if; + if dcount = "110" then + screen <= "1"; + dw_addr <= "1" & ((Y_VECTOR(9 downto 1) ) & X_VECTOR(9 downto 1)); + if BEAM_ON = '1' and beam_ena_r = '0' and BEAM_ENA = '1' then + if Z_VECTOR(3 downto 0) = "0000" then + vid_data <= "0000"; + vram_wren <= '0'; + else + vid_data <= Z_VECTOR(3 downto 0); + vram_wren <= '1'; + end if; + end if; + end if; + if dcount = "111" then + screen <= "1"; + dw_addr <= "0" & ((Y_VECTOR(9 downto 1) ) & X_VECTOR(9 downto 1)); + if BEAM_ON = '1' and beam_ena_r = '0' and BEAM_ENA = '1' then + if Z_VECTOR(3 downto 0) = "0000" then + vid_data <= "0000"; + vram_wren <= '0'; + else + vid_data <= Z_VECTOR(3 downto 0); + vram_wren <= '1'; + end if; + end if; + end if; + beam_ena_r := beam_ena; + end if; + end process; + + +--video_rgb : work.dpram generic map (19,4) +--port map( +-- clock_a => clk_25, +-- wren_a => vram_wren, +-- address_a => dw_addr(18 downto 0), +-- data_a => vid_data, + +-- clock_b => clk_25, +-- address_b => (screen & up_addr(17 downto 0)), +--); +vram_write_addr <= dw_addr(18 downto 0); +vram_write_data <= vid_data; +vram_read_addr <= screen & up_addr(17 downto 0); +vid_out <= vram_read_data; + + -- job done ! +end architecture RTL; diff --git a/Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/llander_ram.vhd b/Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/llander_ram.vhd new file mode 100644 index 00000000..a60adcb6 --- /dev/null +++ b/Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/llander_ram.vhd @@ -0,0 +1,99 @@ +-- +-- A simulation model of Lunar Lander hardware +-- James Sweet 2019 +-- This is not endorsed by fpgaarcade, please do not bother MikeJ with support requests +-- +-- Built upon model of Asteroids Deluxe hardware +-- Copyright (c) MikeJ - May 2004 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + + +entity LLANDER_RAM is + port ( + ADDR : in std_logic_vector(9 downto 0); + DIN : in std_logic_vector(7 downto 0); + DOUT : out std_logic_vector(7 downto 0); + RW_L : in std_logic; + CS_L : in std_logic; -- used for write enable gate only + ENA : in std_logic; -- ditto + CLK : in std_logic + ); +end; + +architecture RTL of LLANDER_RAM is + + signal we : std_logic; + +begin +r1 : Entity work.gen_ram + generic map( + dWidth => 4, + aWidth => 10) + port map( + clk => clk, + we => we, + addr => ADDR(9 downto 0), + d => DIN(7 downto 4), + q => DOUT(7 downto 4) + ); + +r0 : Entity work.gen_ram + generic map( + dWidth => 4, + aWidth => 10) + port map( + clk => clk, + we => we, + addr => ADDR(9 downto 0), + d => DIN(3 downto 0), + q => DOUT(3 downto 0) + ); + + p_we : process(RW_L, CS_L, ENA) + begin + we <= (not CS_L) and (not RW_L) and ENA; + end process; + +end architecture RTL; diff --git a/Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/llander_top.vhd b/Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/llander_top.vhd new file mode 100644 index 00000000..033c390c --- /dev/null +++ b/Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/llander_top.vhd @@ -0,0 +1,241 @@ +-- +-- A simulation model of Lunar Lander hardware +-- James Sweet 2019 +-- This is not endorsed by fpgaarcade, please do not bother MikeJ with support requests +-- +-- Built upon model of Asteroids Deluxe hardware +-- Copyright (c) MikeJ - May 2004 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- + + -- + -- Notes : + -- + -- Button shorts input to ground when pressed + -- + -- ToDo: + -- Model sound effects for thump-thump, ship and saucer fire and saucer warble + -- Add player control switching and screen flip for cocktail mode + -- General cleanup + + + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity LLANDER_TOP is + port ( + + ROT_LEFT_L : in std_logic; + ROT_RIGHT_L : in std_logic; + ABORT_L : in std_logic; + GAME_SEL_L : in std_logic; + START_L : in std_logic; + COIN1_L : in std_logic; + COIN2_L : in std_logic; + -- + THRUST : in std_logic_vector(7 downto 0); + -- + DIAG_STEP_L : in std_logic; + SLAM_L : in std_logic; + SELF_TEST_L : in std_logic; + -- + START_SEL_L : out std_logic; + LAMP2 : out std_logic; + LAMP3 : out std_logic; + LAMP4 : out std_logic; + LAMP5 : out std_logic; + + + AUDIO_OUT : out std_logic_vector(7 downto 0); + VIDEO_R_OUT : out std_logic_vector(3 downto 0); + VIDEO_G_OUT : out std_logic_vector(3 downto 0); + VIDEO_B_OUT : out std_logic_vector(3 downto 0); + + HSYNC_OUT : out std_logic; + VSYNC_OUT : out std_logic; + VGA_DE : out std_logic; + VID_HBLANK : out std_logic; + VID_VBLANK : out std_logic; + + DIP : in std_logic_vector(7 downto 0); + + RESET_L : in std_logic; + + -- ref clock in + clk_6 : in std_logic; + clk_25 : in std_logic; + vram_write_addr : out std_logic_vector(18 downto 0); + vram_write_data : out std_logic_vector(3 downto 0); + vram_read_addr : out std_logic_vector(18 downto 0); + vram_read_data : in std_logic_vector(3 downto 0); + vram_wren : out std_logic + ); +end; + +architecture RTL of LLANDER_TOP is + + signal RAM_ADDR_A : std_logic_vector(18 downto 0); + signal RAM_ADDR_B : std_logic_vector(15 downto 0); -- same as above + signal RAM_WE_L : std_logic; + signal RAM_ADV_L : std_logic; + signal RAM_OE_L : std_logic; + signal RAM_DO : std_logic_vector(31 downto 0); + signal RAM_DI : std_logic_vector(31 downto 0); + signal ram_we : std_logic; + + signal reset_dll_h : std_logic; + + signal delay_count : std_logic_vector(7 downto 0) := (others => '0'); + signal reset_6_l : std_logic; + signal reset_6 : std_logic; + + signal clk_cnt : std_logic_vector(2 downto 0) := "000"; + + signal x_vector : std_logic_vector(9 downto 0); + signal y_vector : std_logic_vector(9 downto 0); + signal y_vector_w_offset : std_logic_vector(9 downto 0); + signal z_vector : std_logic_vector(3 downto 0); + signal beam_on : std_logic; + signal beam_ena : std_logic; + + signal ram_addr_int : std_logic_vector(18 downto 0); + signal ram_we_l_int : std_logic; + signal ram_adv_l_int : std_logic; + signal ram_oe_l_int : std_logic; + signal ram_dout_oe_l : std_logic; + signal ram_dout_oe_l_reg : std_logic; + signal ram_dout : std_logic_vector(31 downto 0); + signal ram_dout_reg : std_logic_vector(31 downto 0); + signal ram_din : std_logic_vector(31 downto 0); + +begin + + -- + -- Note about clocks + -- + -- (the original uses a 6.048 MHz clock, so 40 / 6 - slightly slower) + -- + + reset_dll_h <= not RESET_L; + reset_6 <= reset_dll_h; + + p_delay : process(RESET_L, clk_6) + begin + if (RESET_L = '0') then + delay_count <= x"00"; -- longer delay for cpu + reset_6_l <= '0'; + elsif rising_edge(clk_6) then + if (delay_count(7 downto 0) = (x"FF")) then + delay_count <= (x"FF"); + reset_6_l <= '1'; + else + delay_count <= delay_count + "1"; + reset_6_l <= '0'; + end if; + end if; + end process; + + LLander: entity work.llander +port map( + clk_6 => clk_6, + clk_25 => clk_25, + reset_6_l => reset_6_l, + dip => DIP, + rot_left_l => rot_left_l, + rot_right_l => rot_right_l, + abort_l => abort_l, + game_sel_l => game_sel_l, + start_l => start_l, + coin1_l => coin1_l, + coin2_l => coin2_l, + thrust => thrust, + diag_step_l => diag_step_l, + slam_l => '1', --switches(15), + self_test_l =>self_test_l, + start_sel_l => start_sel_l, + lamp2 => lamp2, + lamp3 => lamp3, + lamp4 => lamp4, + lamp5 => lamp5, + coin_ctr => open, + audio_out => AUDIO_OUT, + x_vector => x_vector, + y_vector => y_vector, + z_vector => z_vector, + beam_on => beam_on, + BEAM_ENA => beam_ena + ); + + y_vector_w_offset<= y_vector+100; + + u_DW : entity work.LLANDER_DW + port map ( + RESET => reset_6, + clk_25 => clk_25, + clk_6 => clk_6, + + X_VECTOR => x_vector, + Y_VECTOR => y_vector_w_offset,-- AJS move up y_vector, + Z_VECTOR => z_vector, + + BEAM_ON => beam_on, + BEAM_ENA => beam_ena, + + VIDEO_R_OUT => VIDEO_R_OUT, + VIDEO_G_OUT => VIDEO_G_OUT, + VIDEO_B_OUT => VIDEO_B_OUT, + HSYNC_OUT => HSYNC_OUT, + VSYNC_OUT => VSYNC_OUT, + VID_DE => VGA_DE, + VID_HBLANK => VID_HBLANK, + VID_VBLANK => VID_VBLANK, + + vram_write_addr => vram_write_addr, + vram_write_data => vram_write_data, + vram_read_addr => vram_read_addr, + vram_read_data => vram_read_data, + vram_wren => vram_wren + ); + + +end RTL; diff --git a/Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/llander_vg.vhd b/Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/llander_vg.vhd new file mode 100644 index 00000000..7d7a85ad --- /dev/null +++ b/Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/llander_vg.vhd @@ -0,0 +1,741 @@ +-- +-- A simulation model of Lunar Lander hardware +-- James Sweet 2019 +-- This is not endorsed by fpgaarcade, please do not bother MikeJ with support requests +-- +-- Built upon model of Asteroids Deluxe hardware +-- Copyright (c) MikeJ - May 2004 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + + +entity LLANDER_VG is + port ( + C_ADDR : in std_logic_vector(15 downto 0); + C_DIN : in std_logic_vector( 7 downto 0); + C_DOUT : out std_logic_vector( 7 downto 0); + C_RW_L : in std_logic; + VMEM_L : in std_logic; + + DMA_GO_L : in std_logic; + DMA_RESET_L : in std_logic; + HALT_OP : out std_logic; + + X_VECTOR : out std_logic_vector(9 downto 0); + Y_VECTOR : out std_logic_vector(9 downto 0); + Z_VECTOR : out std_logic_vector(3 downto 0); + BEAM_ON : out std_logic; + + ENA_1_5M : in std_logic; + ENA_1_5M_E : in std_logic; + RESET_L : in std_logic; + CLK_6 : in std_logic; + Clk_25 : in std_logic + ); +end; + +architecture RTL of LLANDER_VG is + type slv_array12 is array (natural range <>) of std_logic_vector(11 downto 0); + + signal state : std_logic_vector(3 downto 0); + signal next_state : std_logic_vector(3 downto 0); + signal state_halt : std_logic; + -- + signal dma_ld_l : std_logic; + signal dma_ld_l_t1 : std_logic; + signal dma_push_l : std_logic; + signal blank_l : std_logic; + signal latch_l : std_logic_vector(3 downto 0); + signal halt_strobe_l : std_logic; + signal go_strobe_l : std_logic; + -- + signal stop : std_logic; + signal go : std_logic; + signal halt : std_logic; + + signal offset : std_logic_vector(3 downto 0); + signal timer : std_logic_vector(3 downto 0); + signal scale : std_logic_vector(3 downto 0); + signal scale_reg : std_logic_vector(3 downto 0); + signal reg_addr : std_logic_vector(3 downto 0); + signal new_reg_addr : std_logic_vector(3 downto 0); + signal alphanum_l : std_logic; + signal timer_load : std_logic_vector(9 downto 0); + signal timer_counter : std_logic_vector(11 downto 0); + + signal dvx_bus : std_logic_vector(11 downto 0); + signal dvy_bus : std_logic_vector(11 downto 0); + -- + signal xpos_bus : std_logic_vector(11 downto 0); + signal ypos_bus : std_logic_vector(11 downto 0); + + + signal adma_bus : std_logic_vector(12 downto 1); + signal adma0 : std_logic; + signal load_bus : std_logic_vector(12 downto 1); + + signal vram1_l : std_logic; + signal vram2_l : std_logic; + signal vrom1_l : std_logic; + signal vrom2_l : std_logic; + signal vrom3_l : std_logic; + signal vram1_t1_l : std_logic; + signal vram2_t1_l : std_logic; + signal vrom1_t1_l : std_logic; + signal vrom2_t1_l : std_logic; + signal vrom3_t1_l : std_logic; + signal am_bus : std_logic_vector(12 downto 0); + signal vw_l : std_logic; + + -- ratemul + signal ratemul_reg : std_logic_vector(9 downto 0); + signal ratemulx_op : std_logic; + signal ratemulx_reg_and : std_logic_vector(9 downto 0); + signal ratemulx_clock_g : std_logic; + signal ratemulx_rate_out : std_logic_vector(9 downto 0); + -- + signal ratemuly_op : std_logic; + signal ratemuly_reg_and : std_logic_vector(9 downto 0); + signal ratemuly_clock_g : std_logic; + signal ratemuly_rate_out : std_logic_vector(9 downto 0); + -- + signal stack_reg : slv_array12(3 downto 0) := (others => (others => '0')); + signal ram_din : std_logic_vector(7 downto 0); + signal ram_dout_1 : std_logic_vector(7 downto 0); + signal ram_dout_2 : std_logic_vector(7 downto 0); + signal rom_dout_1 : std_logic_vector(7 downto 0); + signal rom_dout_2 : std_logic_vector(7 downto 0); + signal rom_dout_3 : std_logic_vector(7 downto 0); + signal memory_dout : std_logic_vector(7 downto 0); + +begin + + p_halt_go : process(RESET_L, CLK_6) + begin + if (RESET_L = '0') then + halt <= '1'; + go <= '0'; + elsif rising_edge(CLK_6) then + -- slight rejig here from j-k of original + if (DMA_RESET_L = '0') then + halt <= '1'; + elsif (DMA_GO_L = '0') then + halt <= '0'; + elsif (halt_strobe_l = '0') then + halt <= timer(0); + end if; + + if (halt = '1') then + go <= '0'; + elsif (go_strobe_l = '0') then + go <= '1'; + elsif (stop = '1') then + go <= '0'; + end if; + end if; + end process; + HALT_OP <= halt; + -- + -- state machine + -- + p_next_state : process(state, timer, go, halt) + variable go_halt : std_logic; + begin + -- this lot used to be in a rom with + -- + --addr(7) := not( go or halt); + --addr(6) := timer(2) and timer(3); + --addr(5) := timer(1) and timer(3); + --addr(4) := timer(0) and timer(3); + --addr(3 downto 0) := state; + + go_halt := go or halt; + + next_state <= x"0"; + case state is + when x"0" => if (go_halt = '1') then + next_state <= x"0"; + else + next_state <= x"9"; + end if; + + when x"1" => if (go_halt = '1') then + next_state <= x"1"; + else + next_state <= x"2"; + end if; + + when x"2" => next_state <= x"D"; + when x"3" => next_state <= x"D"; + when x"4" => next_state <= x"5"; + when x"5" => next_state <= x"6"; + when x"6" => next_state <= x"7"; + when x"7" => next_state <= x"D"; + + when x"8" => if (timer = x"B") then + next_state <= x"B"; + else + next_state <= x"9"; + end if; + + when x"9" => next_state <= x"D"; + when x"A" => next_state <= x"1"; + + when x"B" => if (timer = x"A") then + next_state <= x"D"; + else + next_state <= x"0"; + end if; + + when x"C" => if (timer = x"B") or (timer = x"C") then + next_state <= x"8"; + elsif (timer = x"D") or (timer = x"E") then + next_state <= x"9"; + elsif (timer = x"F") then + next_state <= x"A"; + else + next_state <= x"F"; + end if; + + when x"D" => next_state <= x"C"; + + when x"E" => if (timer = x"A") then + next_state <= x"B"; + else + next_state <= x"A"; + end if; + + when x"F" => next_state <= x"E"; + when others => null; + end case; + end process; + + p_state_machine : process(RESET_L, CLK_6) + begin + if (RESET_L = '0') then + state <= "0000"; + state_halt <= '0'; + elsif rising_edge(CLK_6) then + + if (DMA_RESET_L = '0') then + state <= "0000"; + state_halt <= '0'; + elsif (ENA_1_5M = '1') then + if (vmem_l = '1') or (state(2) = '0') then + state <= next_state; + state_halt <= halt; + end if; + end if; + end if; + end process; + + p_state_decode : process(state, state_halt, vmem_l, ENA_1_5M_E) + variable dec : std_logic_vector(7 downto 0); + begin + dec := "11111111"; + -- if start(2) is low, ignore vmem_l + if (state(3) = '1') and ((vmem_l = '1') or (state(2) = '0')) and (ENA_1_5M_E = '1') then + case state(2 downto 0) is + when "000" => dec := "11111110"; + when "001" => dec := "11111101"; + when "010" => dec := "11111011"; + when "011" => dec := "11110111"; + when "100" => dec := "11101111"; + when "101" => dec := "11011111"; + when "110" => dec := "10111111"; + when "111" => dec := "01111111"; + when others => null; + end case; + end if; + adma0 <= state(0); + blank_l <= not (state(3) or state_halt); + + -- following stobes are used on ena_1_5 early, so must not be clock enables on ena_1_5. + latch_l(3) <= dec(7); + latch_l(2) <= dec(6); + latch_l(1) <= dec(5); + latch_l(0) <= dec(4); + halt_strobe_l <= dec(3); + go_strobe_l <= dec(2); + dma_ld_l <= dec(1); + dma_push_l <= dec(0); + end process; + -- + -- Program counter / stack + -- + p_dmald : process(timer, CLK_6) + begin + if (timer(0) = '0') then + dma_ld_l_t1 <= '0'; + elsif rising_edge(CLK_6) then + dma_ld_l_t1 <= dma_ld_l; + end if; + end process; + + p_regaddr_calc : process(timer, reg_addr, dma_ld_l, dma_ld_l_t1, dma_push_l) + variable offset : std_logic_vector(3 downto 0); + begin + -- we need the address early + + -- dma_push_l = '0' => store, then inc + -- dma_ld dec, then load pc from stack + if (timer(0) = '1') then -- down + offset := "1111"; + else + offset := "0001"; + end if; + + if ((dma_ld_l = '0') and (dma_ld_l_t1 = '1')) or (dma_push_l = '0') then + new_reg_addr <= reg_addr + offset; + else + new_reg_addr <= reg_addr; + end if; + end process; + + p_regaddr : process + begin + wait until rising_edge(CLK_6); + + if (DMA_GO_L = '0') then -- reset not in original + reg_addr <= "0000"; + else + reg_addr <= new_reg_addr ; + end if; + end process; + + p_reg_write : process + begin + wait until rising_edge(CLK_6); + if (dma_push_l = '0') then + case reg_addr(1 downto 0) is + when "00" => stack_reg(0) <= adma_bus; + when "01" => stack_reg(1) <= adma_bus; + when "10" => stack_reg(2) <= adma_bus; + when "11" => stack_reg(3) <= adma_bus; + when others => null; + end case; + end if; + end process; + + p_reg_read : process(timer(0), new_reg_addr, dvy_bus, stack_reg) + begin + if (timer(0) = '1') then -- load + load_bus <= stack_reg(0); -- default + case new_reg_addr(1 downto 0) is + when "00" => load_bus <= stack_reg(0); + when "01" => load_bus <= stack_reg(1); + when "10" => load_bus <= stack_reg(2); + when "11" => load_bus <= stack_reg(3); + when others => null; + end case; + else + load_bus <= dvy_bus; + end if; + end process; + + p_pc : process + begin + wait until rising_edge(CLK_6); + if (dma_ld_l = '0') then + adma_bus <= load_bus; + else + if (latch_l(0) = '0') or (latch_l(2) = '0') then + adma_bus <= adma_bus + "1"; + end if; + end if; + end process; + -- + -- address decoder + -- + p_addr_sel : process(VMEM_L, adma_bus, adma0, C_ADDR, C_RW_L) + begin + if (VMEM_L = '0') then + am_bus <= C_ADDR(12 downto 0); + vw_l <= C_RW_L; + else + am_bus <= adma_bus & adma0; + vw_l <= '1'; + end if; + end process; + + p_am_decode : process(am_bus) + begin + vram1_l <= '1'; + vram2_l <= '1'; + vrom1_l <= '1'; + vrom2_l <= '1'; + vrom3_l <= '1'; + case am_bus(12 downto 10) is + when "000" => vram1_l <= '0'; + when "001" => vram2_l <= '0'; + when "010" => vrom1_l <= '0'; + when "011" => vrom1_l <= '0'; + when "100" => vrom2_l <= '0'; + when "101" => vrom2_l <= '0'; + when "110" => vrom3_l <= '0'; -- AJS? + when "111" => vrom3_l <= '0'; + + when others => null; + end case; + end process; + + p_am_reg : process + begin + wait until rising_edge(CLK_6); + vram1_t1_l <= vram1_l; + vram2_t1_l <= vram2_l; + vrom1_t1_l <= vrom1_l; + vrom2_t1_l <= vrom2_l; + vrom3_t1_l <= vrom3_l; + end process; + + -- only cpu can write to vector ram + ram_din <= C_DIN; + C_DOUT <= memory_dout; + + -- vector memory + u_vector_ram_1 : entity work.LLANDER_RAM + port map ( + ADDR => am_bus(9 downto 0), + DIN => ram_din, + DOUT => ram_dout_1, + RW_L => vw_l, + CS_L => vram1_l, + ENA => ena_1_5M, + CLK => CLK_6 + ); + + u_vector_ram_2 : entity work.LLANDER_RAM + port map ( + ADDR => am_bus(9 downto 0), + DIN => ram_din, + DOUT => ram_dout_2, + RW_L => vw_l, + CS_L => vram2_l, + ENA => ena_1_5M, + CLK => CLK_6 + ); + +u_vector_rom_0 : entity work.LLANDER_VEC_ROM_0 + port map ( + addr => am_bus(10 downto 0), + data => rom_dout_1, + clk => CLK_6 + ); + +u_vector_rom_1 : entity work.LLANDER_VEC_ROM_1 + port map ( + addr => am_bus(10 downto 0), + data => rom_dout_2, + clk => CLK_6 + ); + +u_vector_rom_2 : entity work.LLANDER_VEC_ROM_2 + port map ( + addr => am_bus(10 downto 0), + data => rom_dout_3, + clk => CLK_6 + ); + + p_memory_data_mux : process(vram1_t1_l, vram2_t1_l, vrom1_t1_l, vrom2_t1_l, vrom3_t1_l,ram_dout_1, ram_dout_2, rom_dout_1, rom_dout_2,rom_dout_3) + begin + -- cpu buffer enabled when VMEM_L = 0 + memory_dout <= (others => '0'); + if (vram1_t1_l = '0') then + memory_dout <= ram_dout_1; + elsif (vram2_t1_l = '0') then + memory_dout <= ram_dout_2; + elsif (vrom1_t1_l = '0') then + memory_dout <= rom_dout_1; -- AJS?? + elsif (vrom2_t1_l = '0') then + memory_dout <= rom_dout_2; -- AJS?? + elsif (vrom3_t1_l = '0') then + memory_dout <= rom_dout_3; -- AJS?? + else + memory_dout <= (others => 'X'); + end if; + end process; + -- + -- data memory latches + -- + p_latch : process + begin + wait until rising_edge(CLK_6); + -- latch3 + if ((alphanum_l = '0') and (latch_l(0) = '0')) or (latch_l(3) ='0') then + scale <= memory_dout(7 downto 4); + dvx_bus(11 downto 8) <= memory_dout(3 downto 0); + end if; + + -- latch2 + if (alphanum_l = '0') then + dvx_bus(7 downto 0) <= x"00"; + elsif (latch_l(2) = '0') then + dvx_bus(7 downto 0) <= memory_dout(7 downto 0); + end if; + + -- we know we have a sync reset + -- latch1 + if (DMA_RESET_L = '0') or (RESET_L = '0') or (dma_go_l = '0') then + timer <= x"0"; + dvy_bus(11 downto 8) <= x"0"; + elsif (latch_l(1) = '0') then + timer <= memory_dout(7 downto 4); + dvy_bus(11 downto 8) <= memory_dout(3 downto 0); + end if; + + -- latch0 + if (DMA_RESET_L = '0') or (RESET_L = '0') or (dma_go_l = '0') or (alphanum_l = '0') then + dvy_bus(7 downto 0) <= x"00"; + elsif (latch_l(0) = '0') then + dvy_bus(7 downto 0) <= memory_dout(7 downto 0); + end if; + end process; + + -- + -- vector timer + -- + p_scale_reg : process + begin + wait until rising_edge(CLK_6); + if (latch_l(2) = '0') and (timer(3) = '1') and (timer(1) = '1') then + scale_reg <= scale; + end if; + end process; + + p_vector_timer : process(timer, dvx_bus, dvy_bus, scale_reg) + variable sel : std_logic; + variable mux : std_logic_vector(3 downto 0); + variable add : std_logic_vector(3 downto 0); + variable dec : std_logic_vector(9 downto 0); + begin + sel := '1'; + if (timer = "1111") then + sel := '0'; + end if; + alphanum_l <= sel; + + if (sel = '0') then + mux := '0' & dvx_bus(11) & not dvx_bus(11) & dvy_bus(11); + else + mux := timer; + end if; + + + add := scale_reg + mux; + + timer_load <= "1111111111"; + case add is + when "0000" => timer_load <= "1111111110"; + when "0001" => timer_load <= "1111111101"; + when "0010" => timer_load <= "1111111011"; + when "0011" => timer_load <= "1111110111"; + when "0100" => timer_load <= "1111101111"; + when "0101" => timer_load <= "1111011111"; + when "0110" => timer_load <= "1110111111"; + when "0111" => timer_load <= "1101111111"; + when "1000" => timer_load <= "1011111111"; + when "1001" => timer_load <= "0111111111"; + when others => timer_load <= "1111111111"; + end case; + + end process; + + p_vector_timer_counter : process + begin + wait until rising_edge(CLK_6); + if (go = '0') then + timer_counter <= "1" & timer_load & '1'; + elsif (ENA_1_5M = '1') then + timer_counter <= timer_counter + "1"; + end if; + + end process; + + p_stop : process(timer_counter) + begin + stop <= '0'; + if (timer_counter = x"FFF") then + stop <= '1'; + end if; + end process; + + -- + -- Rate Multipliers + -- vgck is 1.5Mhz clock + -- + p_ratemul_reg : process(go, CLK_6) + begin + -- share a reg here + if (go = '0') then + ratemul_reg <= (others => '0'); + elsif rising_edge(CLK_6) then + if (ENA_1_5M = '1') then + ratemul_reg <= ratemul_reg + "1"; + end if; + end if; + end process; + + p_ratemulx_and : process(ratemul_reg, ratemulx_reg_and) + begin + ratemulx_reg_and(0) <= ratemul_reg(0); + for i in 1 to 9 loop + ratemulx_reg_and(i) <= ratemul_reg(i) and ratemulx_reg_and(i-1); + end loop; + end process; + + p_ratemuly_and : process(ratemul_reg, ratemuly_reg_and) + begin + ratemuly_reg_and(0) <= ratemul_reg(0); + for i in 1 to 9 loop + ratemuly_reg_and(i) <= ratemul_reg(i) and ratemuly_reg_and(i-1); + end loop; + end process; + + p_ratemulx_rate : process(ratemulx_reg_and, ratemul_reg, dvx_bus) + begin + ratemulx_rate_out(0) <= (not ratemul_reg(0)) and dvx_bus(9); + for i in 1 to 9 loop + ratemulx_rate_out(i) <= (not ratemul_reg(i)) and ratemulx_reg_and(i-1) and dvx_bus(9-i); + end loop; + end process; + + p_ratemuly_rate : process(ratemuly_reg_and, ratemul_reg, dvy_bus) + begin + ratemuly_rate_out(0) <= (not ratemul_reg(0)) and dvy_bus(9); + for i in 1 to 9 loop + ratemuly_rate_out(i) <= (not ratemul_reg(i)) and ratemuly_reg_and(i-1) and dvy_bus(9-i); + end loop; + end process; + + p_ratemul_op : process + begin + wait until rising_edge(CLK_6); + -- we can afford a register here as the enables are every 4 clocks + if (go = '0') then -- clear + ratemulx_op <= '0'; + ratemuly_op <= '0'; + else + ratemulx_op <= '1'; + if (ratemulx_rate_out = "0000000000") then + ratemulx_op <= '0'; + end if; + + ratemuly_op <= '1'; + if (ratemuly_rate_out = "0000000000") then + ratemuly_op <= '0'; + end if; + end if; + end process; + -- + -- x/y position counter + -- + p_x_pos : process + begin + wait until rising_edge(CLK_6); + if (timer(0) = '0') and (halt_strobe_l = '0') then + xpos_bus <= dvx_bus(11 downto 0); + elsif (ENA_1_5M = '1') and (go = '1') and (ratemulx_op = '1') then + if (dvx_bus(10) = '0') then + xpos_bus <= xpos_bus + "1"; + else + xpos_bus <= xpos_bus - "1"; + end if; + end if; + end process; + + p_y_pos : process + begin + wait until rising_edge(CLK_6); + if (timer(0) = '0') and (halt_strobe_l = '0') then + ypos_bus <= dvy_bus(11 downto 0); + elsif (ENA_1_5M = '1') and (go = '1') and (ratemuly_op = '1') then + if (dvy_bus(10) = '0') then + ypos_bus <= ypos_bus + "1"; + else + ypos_bus <= ypos_bus - "1"; + end if; + end if; + end process; + -- + -- output stages + -- + p_output : process(RESET_L, CLK_6) + begin + if (RESET_L = '0') then + X_VECTOR <= "1000000000"; + Y_VECTOR <= "1000000000"; + Z_VECTOR <= "0000"; + BEAM_ON <= '0'; + elsif rising_edge(CLK_6) then + -- clamp beam at edges + if (xpos_bus(10) = '0') then + X_VECTOR <= xpos_bus(9 downto 0); + else + for i in 0 to 9 loop + X_VECTOR(i) <= not xpos_bus(11); + end loop; + end if; + + if (ypos_bus(10) = '0') then + Y_VECTOR <= ypos_bus(9 downto 0); + else + for i in 0 to 9 loop + Y_VECTOR(i) <= not ypos_bus(11); + end loop; + end if; + + BEAM_ON <= '0'; + Z_VECTOR <= "0000"; + if (xpos_bus(11 downto 10) = "00") and + (ypos_bus(11 downto 10) = "00") then + BEAM_ON <= '1'; + if (blank_l = '1') then + Z_VECTOR <= scale; + end if; + end if; + end if; + end process; + +end architecture RTL; diff --git a/Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/ovo.vhd b/Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/ovo.vhd new file mode 100644 index 00000000..6b2c340e --- /dev/null +++ b/Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/ovo.vhd @@ -0,0 +1,180 @@ +-------------------------------------------------------------------------------- +-- Overlay +-------------------------------------------------------------------------------- +-- DO 10/2017 +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY work; +USE work.base_pack.ALL; + +ENTITY ovo IS + GENERIC ( + COLS : natural :=32; + LINES : natural :=2; + RGB : unsigned(23 DOWNTO 0) :=x"FFFFFF"); + PORT ( + -- VGA IN + i_r : IN uv8; + i_g : IN uv8; + i_b : IN uv8; + i_hs : IN std_logic; + i_vs : IN std_logic; + i_de : IN std_logic; + i_en : IN std_logic; + i_clk : IN std_logic; + + -- VGA_OUT + o_r : OUT uv8; + o_g : OUT uv8; + o_b : OUT uv8; + o_hs : OUT std_logic; + o_vs : OUT std_logic; + o_de : OUT std_logic; + + -- Control + ena : IN std_logic; -- Overlay ON/OFF + + -- Probes + in0 : IN unsigned(0 TO COLS*5-1); + in1 : IN unsigned(0 TO COLS*5-1) + ); +END ENTITY ovo; + +--############################################################################## + +ARCHITECTURE rtl OF ovo IS + TYPE arr_slv8 IS ARRAY (natural RANGE <>) OF uv8; + CONSTANT chars : arr_slv8 :=( + x"3E", x"63", x"73", x"7B", x"6F", x"67", x"3E", x"00", -- 0 + x"0C", x"0E", x"0C", x"0C", x"0C", x"0C", x"3F", x"00", -- 1 + x"1E", x"33", x"30", x"1C", x"06", x"33", x"3F", x"00", -- 2 + x"1E", x"33", x"30", x"1C", x"30", x"33", x"1E", x"00", -- 3 + x"38", x"3C", x"36", x"33", x"7F", x"30", x"78", x"00", -- 4 + x"3F", x"03", x"1F", x"30", x"30", x"33", x"1E", x"00", -- 5 + x"1C", x"06", x"03", x"1F", x"33", x"33", x"1E", x"00", -- 6 + x"3F", x"33", x"30", x"18", x"0C", x"0C", x"0C", x"00", -- 7 + x"1E", x"33", x"33", x"1E", x"33", x"33", x"1E", x"00", -- 8 + x"1E", x"33", x"33", x"3E", x"30", x"18", x"0E", x"00", -- 9 + x"0C", x"1E", x"33", x"33", x"3F", x"33", x"33", x"00", -- A + x"3F", x"66", x"66", x"3E", x"66", x"66", x"3F", x"00", -- B + x"3C", x"66", x"03", x"03", x"03", x"66", x"3C", x"00", -- C + x"1F", x"36", x"66", x"66", x"66", x"36", x"1F", x"00", -- D + x"7F", x"46", x"16", x"1E", x"16", x"46", x"7F", x"00", -- E + x"7F", x"46", x"16", x"1E", x"16", x"06", x"0F", x"00", -- F + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", --' ' 10 + x"00", x"00", x"3F", x"00", x"00", x"3F", x"00", x"00", -- = 11 + x"00", x"0C", x"0C", x"3F", x"0C", x"0C", x"00", x"00", -- + 12 + x"00", x"00", x"00", x"3F", x"00", x"00", x"00", x"00", -- - 13 + x"18", x"0C", x"06", x"03", x"06", x"0C", x"18", x"00", -- < 14 + x"06", x"0C", x"18", x"30", x"18", x"0C", x"06", x"00", -- > 15 + x"08", x"1C", x"36", x"63", x"41", x"00", x"00", x"00", -- ^ 16 + x"08", x"1C", x"36", x"63", x"41", x"00", x"00", x"00", -- v 17 + x"18", x"0C", x"06", x"06", x"06", x"0C", x"18", x"00", -- ( 18 + x"06", x"0C", x"18", x"18", x"18", x"0C", x"06", x"00", -- ) 19 + x"00", x"0C", x"0C", x"00", x"00", x"0C", x"0C", x"00", -- : 1A + x"00", x"00", x"00", x"00", x"00", x"0C", x"0C", x"00", -- . 1B + x"00", x"00", x"00", x"00", x"00", x"0C", x"0C", x"06", -- , 1C + x"1E", x"33", x"30", x"18", x"0C", x"00", x"0C", x"00", -- ? 1D + x"18", x"18", x"18", x"00", x"18", x"18", x"18", x"00", -- | 1E + x"36", x"36", x"7F", x"36", x"7F", x"36", x"36", x"00"); -- # 1F + + SIGNAL vcpt,hcpt,hcpt2 : natural RANGE 0 TO 4095; + SIGNAL vin0,vin1 : unsigned(0 TO COLS*5-1); + + SIGNAL t_r,t_g,t_b : uv8; + SIGNAL t_hs,t_vs,t_de : std_logic; + + SIGNAL col : uv8; + SIGNAL de : std_logic; + + SIGNAL in0s,in1s : unsigned(in0'range); +BEGIN + + in0s<=in0 WHEN rising_edge(i_clk); + in1s<=in1 WHEN rising_edge(i_clk); + + ---------------------------------------------------------- + Megamix:PROCESS(i_clk) IS + VARIABLE vin_v : unsigned(0 TO COLS*5-1); + VARIABLE char_v : unsigned(4 DOWNTO 0); + BEGIN + IF rising_edge(i_clk) THEN + IF i_en='1' THEN + ---------------------------------- + -- Propagate VGA signals. 2 cycles delay + t_r<=i_r; + t_g<=i_g; + t_b<=i_b; + t_hs<=i_hs; + t_vs<=i_vs; + t_de<=i_de; + + o_r<=t_r; + o_g<=t_g; + o_b<=t_b; + o_hs<=t_hs; + o_vs<=t_vs; + o_de<=t_de; + + ---------------------------------- + -- Latch sampled values during vertical sync + IF i_vs='1' THEN + vin0<=in0s; + vin1<=in1s; + END IF; + + ---------------------------------- + IF i_vs='1' THEN + vcpt<=0; + de<='0'; + ELSIF i_hs='1' AND t_hs='0' AND de='1' THEN + vcpt<=(vcpt+1) MOD 4096; + END IF; + + ---------------------------------- + IF (vcpt/8) MOD 2=0 THEN + vin_v:=vin0; + ELSE + vin_v:=vin1; + END IF; + + IF i_hs='1' THEN + hcpt<=0; + ELSIF i_de='1' THEN + hcpt<=(hcpt+1) MOD 4096; + de<='1'; + END IF; + hcpt2<=hcpt; + + ---------------------------------- + -- Pick characters + IF hcpt>3)) hps_io -( - .clk_sys(clk_sys), - .HPS_BUS(HPS_BUS), - - .conf_str(CONF_STR), - - .buttons(buttons), - .status(status), - .forced_scandoubler(forced_scandoubler), - - .ioctl_download(ioctl_download), - .ioctl_wr(ioctl_wr), - .ioctl_addr(ioctl_addr), - .ioctl_dout(ioctl_dout), - - .joystick_0(joystk1), - .joystick_1(joystk2), - .ps2_key(ps2_key) -); - -wire pressed = ps2_key[9]; -wire [8:0] code = ps2_key[8:0]; -always @(posedge clk_sys) begin - reg old_state; - old_state <= ps2_key[10]; - - if(old_state != ps2_key[10]) begin - casex(code) - 'hX75: btn_up <= pressed; // up - 'hX72: btn_down <= pressed; // down - 'hX6B: btn_left <= pressed; // left - 'hX74: btn_right <= pressed; // right - 'h029: btn_trig1 <= pressed; // space - 'h014: btn_trig2 <= pressed; // ctrl - 'h005: btn_one_player <= pressed; // F1 - 'h006: btn_two_players <= pressed; // F2 - - // JPAC/IPAC/MAME Style Codes - 'h016: btn_start_1 <= pressed; // 1 - 'h01E: btn_start_2 <= pressed; // 2 - 'h02E: btn_coin_1 <= pressed; // 5 - 'h036: btn_coin_2 <= pressed; // 6 - 'h02D: btn_up_2 <= pressed; // R - 'h02B: btn_down_2 <= pressed; // F - 'h023: btn_left_2 <= pressed; // D - 'h034: btn_right_2 <= pressed; // G - 'h01C: btn_trig1_2 <= pressed; // A - 'h01B: btn_trig2_2 <= pressed; // S - endcase - end -end - -reg btn_up = 0; -reg btn_down = 0; -reg btn_right = 0; -reg btn_left = 0; -reg btn_trig1 = 0; -reg btn_trig2 = 0; -reg btn_one_player = 0; -reg btn_two_players = 0; - -reg btn_start_1 = 0; -reg btn_start_2 = 0; -reg btn_coin_1 = 0; -reg btn_coin_2 = 0; -reg btn_up_2 = 0; -reg btn_down_2 = 0; -reg btn_left_2 = 0; -reg btn_right_2 = 0; -reg btn_trig1_2 = 0; -reg btn_trig2_2 = 0; - - -wire m_up2 = btn_up_2 | joystk2[3]; -wire m_down2 = btn_down_2 | joystk2[2]; -wire m_left2 = btn_left_2 | joystk2[1]; -wire m_right2 = btn_right_2 | joystk2[0]; -wire m_trig21 = btn_trig1_2 | joystk2[4]; -wire m_trig22 = btn_trig2_2 | joystk2[5]; - -wire m_start1 = btn_one_player | joystk1[6] | joystk2[6] | btn_start_1; -wire m_start2 = btn_two_players | joystk1[7] | joystk2[7] | btn_start_2; - -wire m_up1 = btn_up | joystk1[3] | (bCabinet ? 1'b0 : m_up2); -wire m_down1 = btn_down | joystk1[2] | (bCabinet ? 1'b0 : m_down2); -wire m_left1 = btn_left | joystk1[1] | (bCabinet ? 1'b0 : m_left2); -wire m_right1 = btn_right | joystk1[0] | (bCabinet ? 1'b0 : m_right2); -wire m_trig11 = btn_trig1 | joystk1[4] | (bCabinet ? 1'b0 : m_trig21); -wire m_trig12 = btn_trig2 | joystk1[5] | (bCabinet ? 1'b0 : m_trig22); - -wire m_coin1 = btn_one_player | btn_coin_1 | joystk1[8]; -wire m_coin2 = btn_two_players| btn_coin_2 | joystk2[8]; -wire m_coin = m_coin1|m_coin2; - - -/////////////////////////////////////////////////// - -wire hblank, vblank; -wire ce_vid; -wire hs, vs; -wire [3:0] r,g,b; - -reg ce_pix; -always @(posedge clk_hdmi) begin - reg old_clk; - old_clk <= ce_vid; - ce_pix <= old_clk & ~ce_vid; -end - -arcade_rotate_fx #(256,192,12) arcade_video -( - .*, - - .clk_video(clk_hdmi), - - .RGB_in({r,g,b}), - .HBlank(hblank), - .VBlank(vblank), - .HSync(~hs), - .VSync(~vs), - - .fx(0), - .no_rotate(1'b1) -); - -wire PCLK; -wire [8:0] HPOS,VPOS; -wire [11:0] POUT; -HVGEN hvgen -( - .HPOS(HPOS),.VPOS(VPOS),.PCLK(PCLK),.iRGB(POUT), - .oRGB({b,g,r}),.HBLK(hblank),.VBLK(vblank),.HSYN(hs),.VSYN(vs) -); -assign ce_vid = PCLK; - - -wire [15:0] AOUT; -assign AUDIO_L = AOUT; -assign AUDIO_R = AOUT; -assign AUDIO_S = 1'b0; // unsigned - - -/////////////////////////////////////////////////// - -wire [7:0] iDSW1 = {`DIFFICULTY,`DEMOSOUND,`EXTEND2ND,`EXTEND1ST,`LIVES, `CABINET}; // 8'b1_0_01_1_10_0; -wire [7:0] iDSW2 = {`ENDLESS,`FREEPLAY,1'b0,`ALLOW_CONTINUE,`NAMELETTERS,`COINAGE}; // 8'b1_1_0_0_1_111; - -wire [7:0] iCTR1 = ~{ 2'b11, m_start1, 1'b0, m_trig11, m_trig12, m_right1, m_left1 }; -wire [7:0] iCTR2 = ~{ ~m_coin,1'b1, m_start2, 1'b0, m_trig21, m_trig22, m_right2, m_left2 }; - -wire iRST = RESET | status[0] | buttons[1] | ioctl_download; - -wire [7:0] oPIX; -assign POUT = {{oPIX[7:6],oPIX[1:0]},{oPIX[5:4],oPIX[1:0]},{oPIX[3:2],oPIX[1:0]}}; - - -FPGA_NINJAKUN GameCore -( - .RESET(iRST),.MCLK(clk_49M), - - .CTR1(iCTR1),.CTR2(iCTR2), - .DSW1(iDSW1),.DSW2(iDSW2), - - .PH(HPOS),.PV(VPOS), - .PCLK(PCLK),.POUT(oPIX), - .SNDOUT(AOUT), - - .ROMCL(clk_sys),.ROMAD(ioctl_addr),.ROMDT(ioctl_dout),.ROMEN(ioctl_wr) -); - -endmodule - - -module HVGEN -( - output [8:0] HPOS, - output [8:0] VPOS, - input PCLK, - input [11:0] iRGB, - - output reg [11:0] oRGB, - output reg HBLK = 1, - output reg VBLK = 1, - output reg HSYN = 1, - output reg VSYN = 1 -); - -reg [8:0] hcnt = 0; -reg [8:0] vcnt = 0; - -assign HPOS = hcnt-16; -assign VPOS = vcnt-16; - -always @(posedge PCLK) begin - case (hcnt) - 15: begin HBLK <= 0; hcnt <= hcnt+1; end - 272: begin HBLK <= 1; hcnt <= hcnt+1; end - 311: begin HSYN <= 0; hcnt <= hcnt+1; end - 342: begin HSYN <= 1; hcnt <= 471; end - 511: begin hcnt <= 0; - case (vcnt) - 15: begin VBLK <= 0; vcnt <= vcnt+1; end - 207: begin VBLK <= 1; vcnt <= vcnt+1; end - 226: begin VSYN <= 0; vcnt <= vcnt+1; end - 233: begin VSYN <= 1; vcnt <= 483; end - 511: begin vcnt <= 0; end - default: vcnt <= vcnt+1; - endcase - end - default: hcnt <= hcnt+1; - endcase - oRGB <= (HBLK|VBLK) ? 12'h0 : iRGB; -end - -endmodule - - diff --git a/Arcade_MiST/NinjaKun_MiST/mister/LICENSE b/Arcade_MiST/NinjaKun_MiST/mister/LICENSE deleted file mode 100644 index 94a9ed02..00000000 --- a/Arcade_MiST/NinjaKun_MiST/mister/LICENSE +++ /dev/null @@ -1,674 +0,0 @@ - GNU GENERAL PUBLIC LICENSE - Version 3, 29 June 2007 - - Copyright (C) 2007 Free Software Foundation, Inc. - Everyone is permitted to copy and distribute verbatim copies - of this license document, but changing it is not allowed. - - Preamble - - The GNU General Public License is a free, copyleft license for -software and other kinds of works. - - The licenses for most software and other practical works are designed -to take away your freedom to share and change the works. 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But first, please read -. diff --git a/Arcade_MiST/NinjaKun_MiST/mister/README.txt b/Arcade_MiST/NinjaKun_MiST/mister/README.txt deleted file mode 100644 index 1dca0244..00000000 --- a/Arcade_MiST/NinjaKun_MiST/mister/README.txt +++ /dev/null @@ -1,74 +0,0 @@ ---------------------------------------------------------------------------------- --- --- Arcade: Ninja-Kun port to MiSTer by MiSTer-X --- 20 October 2019 --- ---------------------------------------------------------------------------------- --- FPGA Ninja-Kun for Spartan-6 ------------------------------------------------- --- Copyright (c) 2011 MiSTer-X ---------------------------------------------------------------------------------- --- T80/T80s - Version : 0242 ------------------------------ --- Z80 compatible microprocessor core --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) ---------------------------------------------------------------------------------- --- YM2149 (AY-3-8910) --- Copyright (c) MikeJ - Jan 2005 ---------------------------------------------------------------------------------- --- --- --- Keyboard inputs : --- --- F2 : Coin + Start 2 players --- F1 : Coin + Start 1 player --- UP,DOWN,LEFT,RIGHT arrows : Movements --- SPACE : Shot --- CTRL : Jump --- --- MAME/IPAC/JPAC Style Keyboard inputs: --- 5 : Coin 1 --- 6 : Coin 2 --- 1 : Start 1 Player --- 2 : Start 2 Players --- R,F,D,G : Player 2 Movements --- A : Player 2 Shot --- S : Player 2 Jump --- --- Joystick support. --- --- --- known bug: Sometimes BG screen glitches. --- ---------------------------------------------------------------------------------- --- 23 October 2019 ---------------------------------------------------------------------------------- --- FIXED: Analog video is shifted to right. ---------------------------------------------------------------------------------- - - *** Attention *** - -ROM is not included. In order to use this arcade, you need to provide a correct ROM file. - -Find this zip file somewhere. You need to find the file exactly as required. -Do not rename other zip files even if they also represent the same game - they are not compatible! -The name of zip is taken from M.A.M.E. project, so you can get more info about -hashes and contained files there. - -To generate the ROM using Windows: -1) Copy the zip into "releases" directory -2) Execute bat file - it will show the name of zip file containing required files. -3) Put required zip into the same directory and execute the bat again. -4) If everything will go without errors or warnings, then you will get the a.*.rom file. -5) Copy generated a.*.rom into root of SD card along with the Arcade-*.rbf file - -To generate the ROM using Linux/MacOS: -1) Copy the zip into "releases" directory -2) Execute build_rom.sh -3) Copy generated a.*.rom into root of SD card along with the Arcade-*.rbf file - -To generate the ROM using MiSTer: -1) scp "releases" directory along with the zip file onto MiSTer:/media/fat/ -2) Using OSD execute build_rom.sh -3) Copy generated a.*.rom into root of SD card along with the Arcade-*.rbf file - diff --git a/Arcade_MiST/NinjaKun_MiST/mister/build_rom.bat b/Arcade_MiST/NinjaKun_MiST/mister/build_rom.bat deleted file mode 100644 index 4237b880..00000000 --- a/Arcade_MiST/NinjaKun_MiST/mister/build_rom.bat +++ /dev/null @@ -1,45 +0,0 @@ -@powershell -NoProfile -ExecutionPolicy Unrestricted "$s=[scriptblock]::create((gc \"%~f0\"|?{$_.readcount -gt 1})-join\"`n\");&$s" %*&goto:eof -#============================================================== -$zip="ninjakun.zip" - -$ifiles=` - "ninja-6.7n","ninja-7.7p","ninja-8.7s","ninja-9.7t",` - "ninja-10.2c","ninja-11.2d","ninja-12.4c","ninja-13.4d",` - "ninja-1.7a","ninja-2.7b","ninja-3.7d","ninja-4.7e",` - "ninja-5.7h","ninja-2.7b","ninja-3.7d","ninja-4.7e" - -$ofile="a.ninjakun.rom" -$ofileMd5sumValid="99e80f22f7a77cf1d574ce89486b385f" - -if (!(Test-Path "./$zip")) { - echo "Error: Cannot find $zip file." - echo "" - echo "Put $zip into the same directory." -} -else { - Expand-Archive -Path "./$zip" -Destination ./tmp/ -Force - - cd tmp - Get-Content $ifiles -Enc Byte -Read 512 | Set-Content "../$ofile" -Enc Byte - cd .. - Remove-Item ./tmp -Recurse -Force - - $ofileMD5sumCurrent=(Get-FileHash -Algorithm md5 "./$ofile").Hash.toLower() - if ($ofileMD5sumCurrent -ne $ofileMd5sumValid) { - echo "Expected checksum: $ofileMd5sumValid" - echo " Actual checksum: $ofileMd5sumCurrent" - echo "" - echo "Error: Generated $ofile is invalid." - echo "" - echo "This is more likely due to incorrect $zip content." - } - else { - echo "Checksum verification passed." - echo "" - echo "Copy $ofile into root of SD card along with the rbf file." - } -} -echo "" -echo "" -pause - diff --git a/Arcade_MiST/NinjaKun_MiST/mister/build_rom.ini b/Arcade_MiST/NinjaKun_MiST/mister/build_rom.ini deleted file mode 100644 index b6428ae3..00000000 --- a/Arcade_MiST/NinjaKun_MiST/mister/build_rom.ini +++ /dev/null @@ -1,4 +0,0 @@ -zip=ninjakun.zip -ifiles=(ninja-6.7n ninja-7.7p ninja-8.7s ninja-9.7t ninja-10.2c ninja-11.2d ninja-12.4c ninja-13.4d ninja-1.7a ninja-2.7b ninja-3.7d ninja-4.7e ninja-5.7h ninja-2.7b ninja-3.7d ninja-4.7e) -ofile=a.ninjakun.rom -ofileMd5sumValid=99e80f22f7a77cf1d574ce89486b385f diff --git a/Arcade_MiST/NinjaKun_MiST/mister/build_rom.sh b/Arcade_MiST/NinjaKun_MiST/mister/build_rom.sh deleted file mode 100644 index 2b1f85f7..00000000 --- a/Arcade_MiST/NinjaKun_MiST/mister/build_rom.sh +++ /dev/null @@ -1,100 +0,0 @@ -#!/bin/bash - -exit_with_error() { - echo -e "\nERROR:\n${1}\n" - exit 1 -} - -check_dependencies() { - if [[ $OSTYPE == darwin* ]]; then - for j in unzip md5 cat cut; do - command -v ${j} > /dev/null 2>&1 || exit_with_error "This script requires\n${j}" - done - else - for j in unzip md5sum cat cut; do - command -v ${j} > /dev/null 2>&1 || exit_with_error "This script requires\n${j}" - done - fi -} - -check_permissions () { - if [ ! -w ${BASEDIR} ]; then - exit_with_error "Cannot write to\n${BASEDIR}" - fi -} - -read_ini () { - if [ ! -f ${BASEDIR}/build_rom.ini ]; then - exit_with_error "Missing build_rom.ini" - else - source ${BASEDIR}/build_rom.ini - fi -} - -uncompress_zip() { - if [ -f ${BASEDIR}/${zip} ]; then - tmpdir=tmp.`date +%Y%m%d%H%M%S%s` - unzip -qq -d ${BASEDIR}/${tmpdir}/ ${BASEDIR}/${zip} - if [ $? != 0 ] ; then - rm -rf ${BASEDIR}/$tmpdir - exit_with_error "Something went wrong\nwhen extracting\n${zip}" - fi - else - exit_with_error "Cannot find ${zip}" - fi -} - -generate_rom() { - for i in "${ifiles[@]}"; do - # ensure provided zip contains required files - if [ ! -f "${BASEDIR}/${tmpdir}/${i}" ]; then - rm -rf ${BASEDIR}/$tmpdir - exit_with_error "Provided ${zip}\nis missing required file:\n\n${i}" - else - cat ${BASEDIR}/${tmpdir}/${i} >> ${BASEDIR}/${tmpdir}/${ofile} - fi - done -} - -validate_rom() { - - if [[ $OSTYPE == darwin* ]]; then - ofileMd5sumCurrent=$(md5 -r ${BASEDIR}/${tmpdir}/${ofile}|cut -f 1 -d " ") - else - ofileMd5sumCurrent=$(md5sum ${BASEDIR}/${tmpdir}/${ofile}|cut -f 1 -d " ") - fi - - if [[ "${ofileMd5sumValid}" != "${ofileMd5sumCurrent}" ]]; then - echo -e "\nExpected checksum:\n${ofileMd5sumValid}" - echo -e "Actual checksum:\n${ofileMd5sumCurrent}" - mv ${BASEDIR}/${tmpdir}/${ofile} . - rm -rf ${BASEDIR}/$tmpdir - exit_with_error "Generated ${ofile}\nis invalid.\nThis is more likely\ndue to incorrect\n${zip} content." - else - mv ${BASEDIR}/${tmpdir}/${ofile} ${BASEDIR}/. - rm -rf ${BASEDIR}/$tmpdir - echo -e "\nChecksum verification passed\n\nCopy the ${ofile}\ninto root of SD card\nalong with the rbf file.\n" - fi -} - -BASEDIR=$(dirname "$0") - -echo "Generating ROM ..." - -## verify dependencies -check_dependencies - -## verify write permissions -check_permissions - -## load ini -read_ini - -## extract package -uncompress_zip - -## build rom -generate_rom - -## verify rom -validate_rom diff --git a/Arcade_MiST/NinjaKun_MiST/mister/ninjakun_romarb.v b/Arcade_MiST/NinjaKun_MiST/mister/ninjakun_romarb.v deleted file mode 100644 index d6e4cd78..00000000 --- a/Arcade_MiST/NinjaKun_MiST/mister/ninjakun_romarb.v +++ /dev/null @@ -1,80 +0,0 @@ -// Copyright (c) 2011 MiSTer-X - -module NINJAKUN_ROMARB -( - input CLK, - - input [12:0] FGCAD, - output [31:0] FGCDT, - - input [12:0] BGCAD, - output [31:0] BGCDT, - - input [12:0] SPCAD, - output [31:0] SPCDT, - - output reg [2:0] PHASE, - - input [14:0] CP0AD, - output [7:0] CP0DT, - - input [14:0] CP1AD, - output [7:0] CP1DT -); - -wire CL = ~CLK; - -always @( posedge CL ) PHASE <= PHASE+1; - -NJFGROM sprom( CL, SPCAD, SPCDT ); -NJFGROM fgrom( CL, FGCAD, FGCDT ); -NJBGROM bgrom( CL, BGCAD, BGCDT ); - -NJCPU0I cpu0i( CL, CP0AD, CP0DT ); -NJCPU1I cpu1i( CL, {(CP1AD[14]|CP1AD[13]),CP1AD[12:0]}, CP1DT ); - -endmodule - -module NINJAKUN_CPUMUX -( - input CLK24M, - input [2:0] PHASE, - - input [15:0] CP0AD, - input [7:0] CP0OD, - output [7:0] CP0ID, - input CP0RD, - input CP0WR, - - input [15:0] CP1AD, - input [7:0] CP1OD, - output [7:0] CP1ID, - input CP1RD, - input CP1WR, - - output [15:0] CPADR, - output [7:0] CPODT, - input [7:0] CPIDT, - output CPRED, - output CPWRT -); - -reg CSIDE; -reg [7:0] CP0D, CP1D; -always @( posedge CLK24M ) begin - case (PHASE) - 4: begin CP1D <= CPIDT; CSIDE <= 0; end - 0: begin CP0D <= CPIDT; CSIDE <= 1; end - default:; - endcase -end - -assign CPADR = CSIDE ? CP1AD : CP0AD; -assign CPODT = CSIDE ? CP1OD : CP0OD; -assign CPRED = CSIDE ? CP1RD : CP0RD; -assign CPWRT = CSIDE ? CP1WR : CP0WR; - -assign CP0ID = CSIDE ? CP0D : CPIDT; -assign CP1ID = CSIDE ? CPIDT : CP1D; - -endmodule diff --git a/Arcade_MiST/NinjaKun_MiST/mister/rommap.txt b/Arcade_MiST/NinjaKun_MiST/mister/rommap.txt deleted file mode 100644 index ea7c701c..00000000 --- a/Arcade_MiST/NinjaKun_MiST/mister/rommap.txt +++ /dev/null @@ -1,7 +0,0 @@ - -00000-07FFF GFX1-0,1,2,3 -08000-0FFFF GFX2-0,1,2,3 -10000-17FFF CPU0-0,1,2,3 -18000-1FFFF CPU1-0,CPU0-1,2,3 - -[EOF] diff --git a/Arcade_MiST/NinjaKun_MiST/mister/roms.v b/Arcade_MiST/NinjaKun_MiST/mister/roms.v deleted file mode 100644 index dcda9151..00000000 --- a/Arcade_MiST/NinjaKun_MiST/mister/roms.v +++ /dev/null @@ -1,103 +0,0 @@ -// Copyright (c) 2019 MiSTer-X - -module DLROM #(parameter AW,parameter DW) -( - input CL0, - input [(AW-1):0] AD0, - output reg [(DW-1):0] DO0, - - input CL1, - input [(AW-1):0] AD1, - input [(DW-1):0] DI1, - input WE1 -); - -reg [(DW-1):0] core[0:((2**AW)-1)]; - -always @(posedge CL0) DO0 <= core[AD0]; -always @(posedge CL1) if (WE1) core[AD1] <= DI1; - -endmodule - - -module NJFGROM -( - input CL, - input [12:0] AD, - output [31:0] DT, - - input ROMCL, - input [16:0] ROMAD, - input [7:0] ROMDT, - input ROMEN -); - -wire ROME = ROMEN & (ROMAD[16:15]==2'b00); -wire ROME0 = ROME & ~ROMAD[13]; -wire ROME1 = ROME & ROMAD[13]; - -DLROM #(13,8) R0(CL,AD,DT[ 7: 0], ROMCL,{ROMAD[14],ROMAD[12:1]},ROMDT,ROME0 & ~ROMAD[0]); -DLROM #(13,8) R1(CL,AD,DT[15: 8], ROMCL,{ROMAD[14],ROMAD[12:1]},ROMDT,ROME1 & ~ROMAD[0]); -DLROM #(13,8) R2(CL,AD,DT[23:16], ROMCL,{ROMAD[14],ROMAD[12:1]},ROMDT,ROME0 & ROMAD[0]); -DLROM #(13,8) R3(CL,AD,DT[31:24], ROMCL,{ROMAD[14],ROMAD[12:1]},ROMDT,ROME1 & ROMAD[0]); - -endmodule - - -module NJBGROM -( - input CL, - input [12:0] AD, - output [31:0] DT, - - input ROMCL, - input [16:0] ROMAD, - input [7:0] ROMDT, - input ROMEN -); - -wire ROME = ROMEN & (ROMAD[16:15]==2'b01); -wire ROME0 = ROME & ~ROMAD[13]; -wire ROME1 = ROME & ROMAD[13]; - -DLROM #(13,8) R0(CL,AD,DT[ 7: 0], ROMCL,{ROMAD[14],ROMAD[12:1]},ROMDT,ROME0 & ~ROMAD[0]); -DLROM #(13,8) R1(CL,AD,DT[15: 8], ROMCL,{ROMAD[14],ROMAD[12:1]},ROMDT,ROME1 & ~ROMAD[0]); -DLROM #(13,8) R2(CL,AD,DT[23:16], ROMCL,{ROMAD[14],ROMAD[12:1]},ROMDT,ROME0 & ROMAD[0]); -DLROM #(13,8) R3(CL,AD,DT[31:24], ROMCL,{ROMAD[14],ROMAD[12:1]},ROMDT,ROME1 & ROMAD[0]); - -endmodule - - -module NJC0ROM -( - input CL, - input [14:0] AD, - output [7:0] DT, - - input ROMCL, - input [16:0] ROMAD, - input [7:0] ROMDT, - input ROMEN -); - -DLROM #(15,8) r(CL,AD,DT,ROMCL,ROMAD,ROMDT,ROMEN & (ROMAD[16:15]==2'b10)); - -endmodule - - -module NJC1ROM -( - input CL, - input [14:0] AD, - output [7:0] DT, - - input ROMCL, - input [16:0] ROMAD, - input [7:0] ROMDT, - input ROMEN -); - -DLROM #(15,8) r(CL,AD,DT,ROMCL,ROMAD,ROMDT,ROMEN & (ROMAD[16:15]==2'b11)); - -endmodule - diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/DPRAM1024.v b/Arcade_MiST/NinjaKun_MiST/rtl/DPRAM1024.v deleted file mode 100644 index e5a0fec0..00000000 --- a/Arcade_MiST/NinjaKun_MiST/rtl/DPRAM1024.v +++ /dev/null @@ -1,246 +0,0 @@ -// megafunction wizard: %RAM: 2-PORT% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: altsyncram - -// ============================================================ -// File Name: DPRAM1024.v -// Megafunction Name(s): -// altsyncram -// -// Simulation Library Files(s): -// altera_mf -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 17.1.0 Build 590 10/25/2017 SJ Lite Edition -// ************************************************************ - - -//Copyright (C) 2017 Intel Corporation. All rights reserved. -//Your use of Intel Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files from any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Intel Program License -//Subscription Agreement, the Intel Quartus Prime License Agreement, -//the Intel FPGA IP License Agreement, or other applicable license -//agreement, including, without limitation, that your use is for -//the sole purpose of programming logic devices manufactured by -//Intel and sold by Intel or its authorized distributors. Please -//refer to the applicable agreement for further details. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module DPRAM1024 ( - address_a, - address_b, - clock_a, - clock_b, - data_a, - data_b, - wren_a, - wren_b, - q_a, - q_b); - - input [9:0] address_a; - input [9:0] address_b; - input clock_a; - input clock_b; - input [7:0] data_a; - input [7:0] data_b; - input wren_a; - input wren_b; - output [7:0] q_a; - output [7:0] q_b; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_off -`endif - tri1 clock_a; - tri0 wren_a; - tri0 wren_b; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_on -`endif - - wire [7:0] sub_wire0; - wire [7:0] sub_wire1; - wire [7:0] q_a = sub_wire0[7:0]; - wire [7:0] q_b = sub_wire1[7:0]; - - altsyncram altsyncram_component ( - .address_a (address_a), - .address_b (address_b), - .clock0 (clock_a), - .clock1 (clock_b), - .data_a (data_a), - .data_b (data_b), - .wren_a (wren_a), - .wren_b (wren_b), - .q_a (sub_wire0), - .q_b (sub_wire1), - .aclr0 (1'b0), - .aclr1 (1'b0), - .addressstall_a (1'b0), - .addressstall_b (1'b0), - .byteena_a (1'b1), - .byteena_b (1'b1), - .clocken0 (1'b1), - .clocken1 (1'b1), - .clocken2 (1'b1), - .clocken3 (1'b1), - .eccstatus (), - .rden_a (1'b1), - .rden_b (1'b1)); - defparam - altsyncram_component.address_reg_b = "CLOCK1", - altsyncram_component.clock_enable_input_a = "BYPASS", - altsyncram_component.clock_enable_input_b = "BYPASS", - altsyncram_component.clock_enable_output_a = "BYPASS", - altsyncram_component.clock_enable_output_b = "BYPASS", - altsyncram_component.indata_reg_b = "CLOCK1", - altsyncram_component.intended_device_family = "Cyclone III", - altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = 1024, - altsyncram_component.numwords_b = 1024, - altsyncram_component.operation_mode = "BIDIR_DUAL_PORT", - altsyncram_component.outdata_aclr_a = "NONE", - altsyncram_component.outdata_aclr_b = "NONE", - altsyncram_component.outdata_reg_a = "CLOCK0", - altsyncram_component.outdata_reg_b = "CLOCK1", - altsyncram_component.power_up_uninitialized = "FALSE", - altsyncram_component.ram_block_type = "M9K", - altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", - altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ", - altsyncram_component.widthad_a = 10, - altsyncram_component.widthad_b = 10, - altsyncram_component.width_a = 8, - altsyncram_component.width_b = 8, - altsyncram_component.width_byteena_a = 1, - altsyncram_component.width_byteena_b = 1, - altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1"; - - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" -// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" -// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" -// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" -// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" -// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" -// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" -// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" -// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" -// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" -// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" -// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" -// Retrieval info: PRIVATE: CLRdata NUMERIC "0" -// Retrieval info: PRIVATE: CLRq NUMERIC "0" -// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" -// Retrieval info: PRIVATE: CLRrren NUMERIC "0" -// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" -// Retrieval info: PRIVATE: CLRwren NUMERIC "0" -// Retrieval info: PRIVATE: Clock NUMERIC "5" -// Retrieval info: PRIVATE: Clock_A NUMERIC "0" -// Retrieval info: PRIVATE: Clock_B NUMERIC "0" -// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" -// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" -// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" -// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" -// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" -// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192" -// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" -// Retrieval info: PRIVATE: MIFfilename STRING "" -// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" -// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" -// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1" -// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" -// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" -// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" -// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" -// Retrieval info: PRIVATE: REGdata NUMERIC "1" -// Retrieval info: PRIVATE: REGq NUMERIC "1" -// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" -// Retrieval info: PRIVATE: REGrren NUMERIC "0" -// Retrieval info: PRIVATE: REGwraddress NUMERIC "1" -// Retrieval info: PRIVATE: REGwren NUMERIC "1" -// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" -// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" -// Retrieval info: PRIVATE: VarWidth NUMERIC "0" -// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8" -// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8" -// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8" -// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8" -// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" -// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" -// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" -// Retrieval info: PRIVATE: enable NUMERIC "0" -// Retrieval info: PRIVATE: rden NUMERIC "0" -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1" -// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" -// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" -// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" -// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" -// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024" -// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024" -// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" -// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" -// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" -// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" -// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1" -// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" -// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K" -// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" -// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ" -// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10" -// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10" -// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" -// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8" -// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" -// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" -// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1" -// Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL "address_a[9..0]" -// Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL "address_b[9..0]" -// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a" -// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b" -// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]" -// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL "data_b[7..0]" -// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]" -// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL "q_b[7..0]" -// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a" -// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b" -// Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0 -// Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0 -// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0 -// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0 -// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0 -// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0 -// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 -// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 -// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0 -// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0 -// Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM1024.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM1024.inc FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM1024.cmp FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM1024.bsf FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM1024_inst.v FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM1024_bb.v FALSE -// Retrieval info: LIB_FILE: altera_mf diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/NinjaKun_MiST/rtl/cpu/T80.vhd deleted file mode 100644 index 398fa0df..00000000 --- a/Arcade_MiST/NinjaKun_MiST/rtl/cpu/T80.vhd +++ /dev/null @@ -1,1073 +0,0 @@ --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0210 : Fixed wait and halt --- --- 0211 : Fixed Refresh addition and IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson --- --- 0235 : Added clock enable and IM 2 fix by Mike Johnson --- --- 0237 : Changed 8080 I/O address output, added IntE output --- --- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag --- --- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode --- --- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80 is - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); -end T80; - -architecture rtl of T80 is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - -- Registers - signal ACC, F : std_logic_vector(7 downto 0); - signal Ap, Fp : std_logic_vector(7 downto 0); - signal I : std_logic_vector(7 downto 0); - signal R : unsigned(7 downto 0); - signal SP, PC : unsigned(15 downto 0); - signal RegDIH : std_logic_vector(7 downto 0); - signal RegDIL : std_logic_vector(7 downto 0); - signal RegBusA : std_logic_vector(15 downto 0); - signal RegBusB : std_logic_vector(15 downto 0); - signal RegBusC : std_logic_vector(15 downto 0); - signal RegAddrA_r : std_logic_vector(2 downto 0); - signal RegAddrA : std_logic_vector(2 downto 0); - signal RegAddrB_r : std_logic_vector(2 downto 0); - signal RegAddrB : std_logic_vector(2 downto 0); - signal RegAddrC : std_logic_vector(2 downto 0); - signal RegWEH : std_logic; - signal RegWEL : std_logic; - signal Alternate : std_logic; - - -- Help Registers - signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register - signal IR : std_logic_vector(7 downto 0); -- Instruction register - signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector - signal RegBusA_r : std_logic_vector(15 downto 0); - - signal ID16 : signed(15 downto 0); - signal Save_Mux : std_logic_vector(7 downto 0); - - signal TState : unsigned(2 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal IntE_FF1 : std_logic; - signal IntE_FF2 : std_logic; - signal Halt_FF : std_logic; - signal BusReq_s : std_logic; - signal BusAck : std_logic; - signal ClkEn : std_logic; - signal NMI_s : std_logic; - signal INT_s : std_logic; - signal IStatus : std_logic_vector(1 downto 0); - - signal DI_Reg : std_logic_vector(7 downto 0); - signal T_Res : std_logic; - signal XY_State : std_logic_vector(1 downto 0); - signal Pre_XY_F_M : std_logic_vector(2 downto 0); - signal NextIs_XY_Fetch : std_logic; - signal XY_Ind : std_logic; - signal No_BTR : std_logic; - signal BTR_r : std_logic; - signal Auto_Wait : std_logic; - signal Auto_Wait_t1 : std_logic; - signal Auto_Wait_t2 : std_logic; - signal IncDecZ : std_logic; - - -- ALU signals - signal BusB : std_logic_vector(7 downto 0); - signal BusA : std_logic_vector(7 downto 0); - signal ALU_Q : std_logic_vector(7 downto 0); - signal F_Out : std_logic_vector(7 downto 0); - - -- Registered micro code outputs - signal Read_To_Reg_r : std_logic_vector(4 downto 0); - signal Arith16_r : std_logic; - signal Z16_r : std_logic; - signal ALU_Op_r : std_logic_vector(3 downto 0); - signal Save_ALU_r : std_logic; - signal PreserveC_r : std_logic; - signal MCycles : std_logic_vector(2 downto 0); - - -- Micro code outputs - signal MCycles_d : std_logic_vector(2 downto 0); - signal TStates : std_logic_vector(2 downto 0); - signal IntCycle : std_logic; - signal NMICycle : std_logic; - signal Inc_PC : std_logic; - signal Inc_WZ : std_logic; - signal IncDec_16 : std_logic_vector(3 downto 0); - signal Prefix : std_logic_vector(1 downto 0); - signal Read_To_Acc : std_logic; - signal Read_To_Reg : std_logic; - signal Set_BusB_To : std_logic_vector(3 downto 0); - signal Set_BusA_To : std_logic_vector(3 downto 0); - signal ALU_Op : std_logic_vector(3 downto 0); - signal Save_ALU : std_logic; - signal PreserveC : std_logic; - signal Arith16 : std_logic; - signal Set_Addr_To : std_logic_vector(2 downto 0); - signal Jump : std_logic; - signal JumpE : std_logic; - signal JumpXY : std_logic; - signal Call : std_logic; - signal RstP : std_logic; - signal LDZ : std_logic; - signal LDW : std_logic; - signal LDSPHL : std_logic; - signal IORQ_i : std_logic; - signal Special_LD : std_logic_vector(2 downto 0); - signal ExchangeDH : std_logic; - signal ExchangeRp : std_logic; - signal ExchangeAF : std_logic; - signal ExchangeRS : std_logic; - signal I_DJNZ : std_logic; - signal I_CPL : std_logic; - signal I_CCF : std_logic; - signal I_SCF : std_logic; - signal I_RETN : std_logic; - signal I_BT : std_logic; - signal I_BC : std_logic; - signal I_BTR : std_logic; - signal I_RLD : std_logic; - signal I_RRD : std_logic; - signal I_INRC : std_logic; - signal SetDI : std_logic; - signal SetEI : std_logic; - signal IMode : std_logic_vector(1 downto 0); - signal Halt : std_logic; - -begin - - mcode : T80_MCode - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - IR => IR, - ISet => ISet, - MCycle => MCycle, - F => F, - NMICycle => NMICycle, - IntCycle => IntCycle, - MCycles => MCycles_d, - TStates => TStates, - Prefix => Prefix, - Inc_PC => Inc_PC, - Inc_WZ => Inc_WZ, - IncDec_16 => IncDec_16, - Read_To_Acc => Read_To_Acc, - Read_To_Reg => Read_To_Reg, - Set_BusB_To => Set_BusB_To, - Set_BusA_To => Set_BusA_To, - ALU_Op => ALU_Op, - Save_ALU => Save_ALU, - PreserveC => PreserveC, - Arith16 => Arith16, - Set_Addr_To => Set_Addr_To, - IORQ => IORQ_i, - Jump => Jump, - JumpE => JumpE, - JumpXY => JumpXY, - Call => Call, - RstP => RstP, - LDZ => LDZ, - LDW => LDW, - LDSPHL => LDSPHL, - Special_LD => Special_LD, - ExchangeDH => ExchangeDH, - ExchangeRp => ExchangeRp, - ExchangeAF => ExchangeAF, - ExchangeRS => ExchangeRS, - I_DJNZ => I_DJNZ, - I_CPL => I_CPL, - I_CCF => I_CCF, - I_SCF => I_SCF, - I_RETN => I_RETN, - I_BT => I_BT, - I_BC => I_BC, - I_BTR => I_BTR, - I_RLD => I_RLD, - I_RRD => I_RRD, - I_INRC => I_INRC, - SetDI => SetDI, - SetEI => SetEI, - IMode => IMode, - Halt => Halt, - NoRead => NoRead, - Write => Write); - - alu : T80_ALU - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - Arith16 => Arith16_r, - Z16 => Z16_r, - ALU_Op => ALU_Op_r, - IR => IR(5 downto 0), - ISet => ISet, - BusA => BusA, - BusB => BusB, - F_In => F, - Q => ALU_Q, - F_Out => F_Out); - - ClkEn <= CEN and not BusAck; - - T_Res <= '1' when TState = unsigned(TStates) else '0'; - - NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and - ((Set_Addr_To = aXY) or - (MCycle = "001" and IR = "11001011") or - (MCycle = "001" and IR = "00110110")) else '0'; - - Save_Mux <= BusB when ExchangeRp = '1' else - DI_Reg when Save_ALU_r = '0' else - ALU_Q; - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - PC <= (others => '0'); -- Program Counter - A <= (others => '0'); - TmpAddr <= (others => '0'); - IR <= "00000000"; - ISet <= "00"; - XY_State <= "00"; - IStatus <= "00"; - MCycles <= "000"; - DO <= "00000000"; - - ACC <= (others => '1'); - F <= (others => '1'); - Ap <= (others => '1'); - Fp <= (others => '1'); - I <= (others => '0'); - R <= (others => '0'); - SP <= (others => '1'); - Alternate <= '0'; - - Read_To_Reg_r <= "00000"; - F <= (others => '1'); - Arith16_r <= '0'; - BTR_r <= '0'; - Z16_r <= '0'; - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - PreserveC_r <= '0'; - XY_Ind <= '0'; - - elsif CLK_n'event and CLK_n = '1' then - - if ClkEn = '1' then - - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - Read_To_Reg_r <= "00000"; - - MCycles <= MCycles_d; - - if IMode /= "11" then - IStatus <= IMode; - end if; - - Arith16_r <= Arith16; - PreserveC_r <= PreserveC; - if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then - Z16_r <= '1'; - else - Z16_r <= '0'; - end if; - - if MCycle = "001" and TState(2) = '0' then - -- MCycle = 1 and TState = 1, 2, or 3 - - if TState = 2 and Wait_n = '1' then - if Mode < 2 then - A(7 downto 0) <= std_logic_vector(R); - A(15 downto 8) <= I; - R(6 downto 0) <= R(6 downto 0) + 1; - end if; - - if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then - PC <= PC + 1; - end if; - - if IntCycle = '1' and IStatus = "01" then - IR <= "11111111"; - elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then - IR <= "00000000"; - else - IR <= DInst; - end if; - - ISet <= "00"; - if Prefix /= "00" then - if Prefix = "11" then - if IR(5) = '1' then - XY_State <= "10"; - else - XY_State <= "01"; - end if; - else - if Prefix = "10" then - XY_State <= "00"; - XY_Ind <= '0'; - end if; - ISet <= Prefix; - end if; - else - XY_State <= "00"; - XY_Ind <= '0'; - end if; - end if; - - else - -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) - - if MCycle = "110" then - XY_Ind <= '1'; - if Prefix = "01" then - ISet <= "01"; - end if; - end if; - - if T_Res = '1' then - BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; - if Jump = '1' then - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(DI_Reg); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - elsif JumpXY = '1' then - A <= RegBusC; - PC <= unsigned(RegBusC); - elsif Call = '1' or RstP = '1' then - A <= TmpAddr; - PC <= unsigned(TmpAddr); - elsif MCycle = MCycles and NMICycle = '1' then - A <= "0000000001100110"; - PC <= "0000000001100110"; - elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then - A(15 downto 8) <= I; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(I); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - else - case Set_Addr_To is - when aXY => - if XY_State = "00" then - A <= RegBusC; - else - if NextIs_XY_Fetch = '1' then - A <= std_logic_vector(PC); - else - A <= TmpAddr; - end if; - end if; - when aIOA => - if Mode = 3 then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - elsif Mode = 2 then - -- Duplicate I/O address on 8080 - A(15 downto 8) <= DI_Reg; - else - A(15 downto 8) <= ACC; - end if; - A(7 downto 0) <= DI_Reg; - when aSP => - A <= std_logic_vector(SP); - when aBC => - if Mode = 3 and IORQ_i = '1' then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - A(7 downto 0) <= RegBusC(7 downto 0); - else - A <= RegBusC; - end if; - when aDE => - A <= RegBusC; - when aZI => - if Inc_WZ = '1' then - A <= std_logic_vector(unsigned(TmpAddr) + 1); - else - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - end if; - when others => - A <= std_logic_vector(PC); - end case; - end if; - - Save_ALU_r <= Save_ALU; - ALU_Op_r <= ALU_Op; - - if I_CPL = '1' then - -- CPL - ACC <= not ACC; - F(Flag_Y) <= not ACC(5); - F(Flag_H) <= '1'; - F(Flag_X) <= not ACC(3); - F(Flag_N) <= '1'; - end if; - if I_CCF = '1' then - -- CCF - F(Flag_C) <= not F(Flag_C); - F(Flag_Y) <= ACC(5); - F(Flag_H) <= F(Flag_C); - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - if I_SCF = '1' then - -- SCF - F(Flag_C) <= '1'; - F(Flag_Y) <= ACC(5); - F(Flag_H) <= '0'; - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - end if; - - if TState = 2 and Wait_n = '1' then - if ISet = "01" and MCycle = "111" then - IR <= DInst; - end if; - if JumpE = '1' then - PC <= unsigned(signed(PC) + signed(DI_Reg)); - elsif Inc_PC = '1' then - PC <= PC + 1; - end if; - if BTR_r = '1' then - PC <= PC - 2; - end if; - if RstP = '1' then - TmpAddr <= (others =>'0'); - TmpAddr(5 downto 3) <= IR(5 downto 3); - end if; - end if; - if TState = 3 and MCycle = "110" then - TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); - end if; - - if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then - if IncDec_16(2 downto 0) = "111" then - if IncDec_16(3) = '1' then - SP <= SP - 1; - else - SP <= SP + 1; - end if; - end if; - end if; - - if LDSPHL = '1' then - SP <= unsigned(RegBusC); - end if; - if ExchangeAF = '1' then - Ap <= ACC; - ACC <= Ap; - Fp <= F; - F <= Fp; - end if; - if ExchangeRS = '1' then - Alternate <= not Alternate; - end if; - end if; - - if TState = 3 then - if LDZ = '1' then - TmpAddr(7 downto 0) <= DI_Reg; - end if; - if LDW = '1' then - TmpAddr(15 downto 8) <= DI_Reg; - end if; - - if Special_LD(2) = '1' then - case Special_LD(1 downto 0) is - when "00" => - ACC <= I; - F(Flag_P) <= IntE_FF2; - when "01" => - ACC <= std_logic_vector(R); - F(Flag_P) <= IntE_FF2; - when "10" => - I <= ACC; - when others => - R <= unsigned(ACC); - end case; - end if; - end if; - - if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then - if Mode = 3 then - F(6) <= F_Out(6); - F(5) <= F_Out(5); - F(7) <= F_Out(7); - if PreserveC_r = '0' then - F(4) <= F_Out(4); - end if; - else - F(7 downto 1) <= F_Out(7 downto 1); - if PreserveC_r = '0' then - F(Flag_C) <= F_Out(0); - end if; - end if; - end if; - if T_Res = '1' and I_INRC = '1' then - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - if DI_Reg(7 downto 0) = "00000000" then - F(Flag_Z) <= '1'; - else - F(Flag_Z) <= '0'; - end if; - F(Flag_S) <= DI_Reg(7); - F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor - DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); - end if; - - if TState = 1 and Auto_Wait_t1 = '0' then - DO <= BusB; - if I_RLD = '1' then - DO(3 downto 0) <= BusA(3 downto 0); - DO(7 downto 4) <= BusB(3 downto 0); - end if; - if I_RRD = '1' then - DO(3 downto 0) <= BusB(7 downto 4); - DO(7 downto 4) <= BusA(3 downto 0); - end if; - end if; - - if T_Res = '1' then - Read_To_Reg_r(3 downto 0) <= Set_BusA_To; - Read_To_Reg_r(4) <= Read_To_Reg; - if Read_To_Acc = '1' then - Read_To_Reg_r(3 downto 0) <= "0111"; - Read_To_Reg_r(4) <= '1'; - end if; - end if; - - if TState = 1 and I_BT = '1' then - F(Flag_X) <= ALU_Q(3); - F(Flag_Y) <= ALU_Q(1); - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - end if; - if I_BC = '1' or I_BT = '1' then - F(Flag_P) <= IncDecZ; - end if; - - if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10111" => - ACC <= Save_Mux; - when "10110" => - DO <= Save_Mux; - when "11000" => - SP(7 downto 0) <= unsigned(Save_Mux); - when "11001" => - SP(15 downto 8) <= unsigned(Save_Mux); - when "11011" => - F <= Save_Mux; - when others => - end case; - end if; - - end if; - - end if; - - end process; - ---------------------------------------------------------------------------- --- --- BC('), DE('), HL('), IX and IY --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - -- Bus A / Write - RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then - RegAddrA_r <= XY_State(1) & "11"; - end if; - - -- Bus B - RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then - RegAddrB_r <= XY_State(1) & "11"; - end if; - - -- Address from register - RegAddrC <= Alternate & Set_Addr_To(1 downto 0); - -- Jump (HL), LD SP,HL - if (JumpXY = '1' or LDSPHL = '1') then - RegAddrC <= Alternate & "10"; - end if; - if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then - RegAddrC <= XY_State(1) & "11"; - end if; - - if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then - IncDecZ <= F_Out(Flag_Z); - end if; - if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then - if ID16 = 0 then - IncDecZ <= '0'; - else - IncDecZ <= '1'; - end if; - end if; - - RegBusA_r <= RegBusA; - end if; - end if; - end process; - - RegAddrA <= - -- 16 bit increment/decrement - Alternate & IncDec_16(1 downto 0) when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else - XY_State(1) & "11" when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else - -- EX HL,DL - Alternate & "10" when ExchangeDH = '1' and TState = 3 else - Alternate & "01" when ExchangeDH = '1' and TState = 4 else - -- Bus A / Write - RegAddrA_r; - - RegAddrB <= - -- EX HL,DL - Alternate & "01" when ExchangeDH = '1' and TState = 3 else - -- Bus B - RegAddrB_r; - - ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else - signed(RegBusA) + 1; - - process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegWEH <= '0'; - RegWEL <= '0'; - if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => - RegWEH <= not Read_To_Reg_r(0); - RegWEL <= Read_To_Reg_r(0); - when others => - end case; - end if; - - if ExchangeDH = '1' and (TState = 3 or TState = 4) then - RegWEH <= '1'; - RegWEL <= '1'; - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - case IncDec_16(1 downto 0) is - when "00" | "01" | "10" => - RegWEH <= '1'; - RegWEL <= '1'; - when others => - end case; - end if; - end process; - - process (Save_Mux, RegBusB, RegBusA_r, ID16, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegDIH <= Save_Mux; - RegDIL <= Save_Mux; - - if ExchangeDH = '1' and TState = 3 then - RegDIH <= RegBusB(15 downto 8); - RegDIL <= RegBusB(7 downto 0); - end if; - if ExchangeDH = '1' and TState = 4 then - RegDIH <= RegBusA_r(15 downto 8); - RegDIL <= RegBusA_r(7 downto 0); - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - RegDIH <= std_logic_vector(ID16(15 downto 8)); - RegDIL <= std_logic_vector(ID16(7 downto 0)); - end if; - end process; - - Regs : T80_Reg - port map( - Clk => CLK_n, - CEN => ClkEn, - WEH => RegWEH, - WEL => RegWEL, - AddrA => RegAddrA, - AddrB => RegAddrB, - AddrC => RegAddrC, - DIH => RegDIH, - DIL => RegDIL, - DOAH => RegBusA(15 downto 8), - DOAL => RegBusA(7 downto 0), - DOBH => RegBusB(15 downto 8), - DOBL => RegBusB(7 downto 0), - DOCH => RegBusC(15 downto 8), - DOCL => RegBusC(7 downto 0)); - ---------------------------------------------------------------------------- --- --- Buses --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - case Set_BusB_To is - when "0111" => - BusB <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusB_To(0) = '1' then - BusB <= RegBusB(7 downto 0); - else - BusB <= RegBusB(15 downto 8); - end if; - when "0110" => - BusB <= DI_Reg; - when "1000" => - BusB <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusB <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusB <= "00000001"; - when "1011" => - BusB <= F; - when "1100" => - BusB <= std_logic_vector(PC(7 downto 0)); - when "1101" => - BusB <= std_logic_vector(PC(15 downto 8)); - when "1110" => - BusB <= "00000000"; - when others => - BusB <= "--------"; - end case; - - case Set_BusA_To is - when "0111" => - BusA <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusA_To(0) = '1' then - BusA <= RegBusA(7 downto 0); - else - BusA <= RegBusA(15 downto 8); - end if; - when "0110" => - BusA <= DI_Reg; - when "1000" => - BusA <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusA <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusA <= "00000000"; - when others => - BusB <= "--------"; - end case; - end if; - end if; - end process; - ---------------------------------------------------------------------------- --- --- Generate external control signals --- ---------------------------------------------------------------------------- - process (RESET_n,CLK_n) - begin - if RESET_n = '0' then - RFSH_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then - RFSH_n <= '0'; - else - RFSH_n <= '1'; - end if; - end if; - end if; - end process; - - MC <= std_logic_vector(MCycle); - TS <= std_logic_vector(TState); - DI_Reg <= DI; - HALT_n <= not Halt_FF; - BUSAK_n <= not BusAck; - IntCycle_n <= not IntCycle; - IntE <= IntE_FF1; - IORQ <= IORQ_i; - Stop <= I_DJNZ; - -------------------------------------------------------------------------- --- --- Syncronise inputs --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - variable OldNMI_n : std_logic; - begin - if RESET_n = '0' then - BusReq_s <= '0'; - INT_s <= '0'; - NMI_s <= '0'; - OldNMI_n := '0'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - BusReq_s <= not BUSRQ_n; - INT_s <= not INT_n; - if NMICycle = '1' then - NMI_s <= '0'; - elsif NMI_n = '0' and OldNMI_n = '1' then - NMI_s <= '1'; - end if; - OldNMI_n := NMI_n; - end if; - end if; - end process; - -------------------------------------------------------------------------- --- --- Main state machine --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - MCycle <= "001"; - TState <= "000"; - Pre_XY_F_M <= "000"; - Halt_FF <= '0'; - BusAck <= '0'; - NMICycle <= '0'; - IntCycle <= '0'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - No_BTR <= '0'; - Auto_Wait_t1 <= '0'; - Auto_Wait_t2 <= '0'; - M1_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - if T_Res = '1' then - Auto_Wait_t1 <= '0'; - else - Auto_Wait_t1 <= Auto_Wait or IORQ_i; - end if; - Auto_Wait_t2 <= Auto_Wait_t1; - No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or - (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or - (I_BTR and (not IR(4) or F(Flag_Z))); - if TState = 2 then - if SetEI = '1' then - IntE_FF1 <= '1'; - IntE_FF2 <= '1'; - end if; - if I_RETN = '1' then - IntE_FF1 <= IntE_FF2; - end if; - end if; - if TState = 3 then - if SetDI = '1' then - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - end if; - if IntCycle = '1' or NMICycle = '1' then - Halt_FF <= '0'; - end if; - if MCycle = "001" and TState = 2 and Wait_n = '1' then - M1_n <= '1'; - end if; - if BusReq_s = '1' and BusAck = '1' then - else - BusAck <= '0'; - if TState = 2 and Wait_n = '0' then - elsif T_Res = '1' then - if Halt = '1' then - Halt_FF <= '1'; - end if; - if BusReq_s = '1' then - BusAck <= '1'; - else - TState <= "001"; - if NextIs_XY_Fetch = '1' then - MCycle <= "110"; - Pre_XY_F_M <= MCycle; - if IR = "00110110" and Mode = 0 then - Pre_XY_F_M <= "010"; - end if; - elsif (MCycle = "111") or - (MCycle = "110" and Mode = 1 and ISet /= "01") then - MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); - elsif (MCycle = MCycles) or - No_BTR = '1' or - (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then - M1_n <= '0'; - MCycle <= "001"; - IntCycle <= '0'; - NMICycle <= '0'; - if NMI_s = '1' and Prefix = "00" then - NMICycle <= '1'; - IntE_FF1 <= '0'; - elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then - IntCycle <= '1'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - else - MCycle <= std_logic_vector(unsigned(MCycle) + 1); - end if; - end if; - else - if (Auto_Wait = '1' and Auto_Wait_t2 = '0') nor - (IOWait = 1 and IORQ_i = '1' and Auto_Wait_t1 = '0') then - TState <= TState + 1; - end if; - end if; - end if; - if TState = 0 then - M1_n <= '0'; - end if; - end if; - end if; - end process; - - process (IntCycle, NMICycle, MCycle) - begin - Auto_Wait <= '0'; - if IntCycle = '1' or NMICycle = '1' then - if MCycle = "001" then - Auto_Wait <= '1'; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/NinjaKun_MiST/rtl/cpu/T80_ALU.vhd deleted file mode 100644 index 86fddce7..00000000 --- a/Arcade_MiST/NinjaKun_MiST/rtl/cpu/T80_ALU.vhd +++ /dev/null @@ -1,351 +0,0 @@ --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0238 : Fixed zero flag for 16 bit SBC and ADC --- --- 0240 : Added GB operations --- --- 0242 : Cleanup --- --- 0247 : Cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_ALU is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); -end T80_ALU; - -architecture rtl of T80_ALU is - - procedure AddSub(A : std_logic_vector; - B : std_logic_vector; - Sub : std_logic; - Carry_In : std_logic; - signal Res : out std_logic_vector; - signal Carry : out std_logic) is - variable B_i : unsigned(A'length - 1 downto 0); - variable Res_i : unsigned(A'length + 1 downto 0); - begin - if Sub = '1' then - B_i := not unsigned(B); - else - B_i := unsigned(B); - end if; - Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); - Carry <= Res_i(A'length + 1); - Res <= std_logic_vector(Res_i(A'length downto 1)); - end; - - -- AddSub variables (temporary signals) - signal UseCarry : std_logic; - signal Carry7_v : std_logic; - signal Overflow_v : std_logic; - signal HalfCarry_v : std_logic; - signal Carry_v : std_logic; - signal Q_v : std_logic_vector(7 downto 0); - - signal BitMask : std_logic_vector(7 downto 0); - -begin - - with IR(5 downto 3) select BitMask <= "00000001" when "000", - "00000010" when "001", - "00000100" when "010", - "00001000" when "011", - "00010000" when "100", - "00100000" when "101", - "01000000" when "110", - "10000000" when others; - - UseCarry <= not ALU_Op(2) and ALU_Op(0); - AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); - AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); - AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); - OverFlow_v <= Carry_v xor Carry7_v; - - process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) - variable Q_t : std_logic_vector(7 downto 0); - variable DAA_Q : unsigned(8 downto 0); - begin - Q_t := "--------"; - F_Out <= F_In; - DAA_Q := "---------"; - case ALU_Op is - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => - F_Out(Flag_N) <= '0'; - F_Out(Flag_C) <= '0'; - case ALU_OP(2 downto 0) is - when "000" | "001" => -- ADD, ADC - Q_t := Q_v; - F_Out(Flag_C) <= Carry_v; - F_Out(Flag_H) <= HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "010" | "011" | "111" => -- SUB, SBC, CP - Q_t := Q_v; - F_Out(Flag_N) <= '1'; - F_Out(Flag_C) <= not Carry_v; - F_Out(Flag_H) <= not HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "100" => -- AND - Q_t(7 downto 0) := BusA and BusB; - F_Out(Flag_H) <= '1'; - when "101" => -- XOR - Q_t(7 downto 0) := BusA xor BusB; - F_Out(Flag_H) <= '0'; - when others => -- OR "110" - Q_t(7 downto 0) := BusA or BusB; - F_Out(Flag_H) <= '0'; - end case; - if ALU_Op(2 downto 0) = "111" then -- CP - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - else - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - end if; - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - if Z16 = '1' then - F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC - end if; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - case ALU_Op(2 downto 0) is - when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP - when others => - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - end case; - if Arith16 = '1' then - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - F_Out(Flag_P) <= F_In(Flag_P); - end if; - when "1100" => - -- DAA - F_Out(Flag_H) <= F_In(Flag_H); - F_Out(Flag_C) <= F_In(Flag_C); - DAA_Q(7 downto 0) := unsigned(BusA); - DAA_Q(8) := '0'; - if F_In(Flag_N) = '0' then - -- After addition - -- Alow > 9 or H = 1 - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if (DAA_Q(3 downto 0) > 9) then - F_Out(Flag_H) <= '1'; - else - F_Out(Flag_H) <= '0'; - end if; - DAA_Q := DAA_Q + 6; - end if; - -- new Ahigh > 9 or C = 1 - if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q + 96; -- 0x60 - end if; - else - -- After subtraction - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if DAA_Q(3 downto 0) > 5 then - F_Out(Flag_H) <= '0'; - end if; - DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; - end if; - if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q - 352; -- 0x160 - end if; - end if; - F_Out(Flag_X) <= DAA_Q(3); - F_Out(Flag_Y) <= DAA_Q(5); - F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); - Q_t := std_logic_vector(DAA_Q(7 downto 0)); - if DAA_Q(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= DAA_Q(7); - F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor - DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); - when "1101" | "1110" => - -- RLD, RRD - Q_t(7 downto 4) := BusA(7 downto 4); - if ALU_Op(0) = '1' then - Q_t(3 downto 0) := BusB(7 downto 4); - else - Q_t(3 downto 0) := BusB(3 downto 0); - end if; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - when "1001" => - -- BIT - Q_t(7 downto 0) := BusB and BitMask; - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - F_Out(Flag_P) <= '1'; - else - F_Out(Flag_Z) <= '0'; - F_Out(Flag_P) <= '0'; - end if; - F_Out(Flag_H) <= '1'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= '0'; - F_Out(Flag_Y) <= '0'; - if IR(2 downto 0) /= "110" then - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - end if; - when "1010" => - -- SET - Q_t(7 downto 0) := BusB or BitMask; - when "1011" => - -- RES - Q_t(7 downto 0) := BusB and not BitMask; - when "1000" => - -- ROT - case IR(5 downto 3) is - when "000" => -- RLC - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := BusA(7); - F_Out(Flag_C) <= BusA(7); - when "010" => -- RL - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(7); - when "001" => -- RRC - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(0); - F_Out(Flag_C) <= BusA(0); - when "011" => -- RR - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(0); - when "100" => -- SLA - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '0'; - F_Out(Flag_C) <= BusA(7); - when "110" => -- SLL (Undocumented) / SWAP - if Mode = 3 then - Q_t(7 downto 4) := BusA(3 downto 0); - Q_t(3 downto 0) := BusA(7 downto 4); - F_Out(Flag_C) <= '0'; - else - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '1'; - F_Out(Flag_C) <= BusA(7); - end if; - when "101" => -- SRA - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(7); - F_Out(Flag_C) <= BusA(0); - when others => -- SRL - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := '0'; - F_Out(Flag_C) <= BusA(0); - end case; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - if ISet = "00" then - F_Out(Flag_P) <= F_In(Flag_P); - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - end if; - when others => - null; - end case; - Q <= Q_t; - end process; - -end; diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/NinjaKun_MiST/rtl/cpu/T80_MCode.vhd deleted file mode 100644 index 4cc30f35..00000000 --- a/Arcade_MiST/NinjaKun_MiST/rtl/cpu/T80_MCode.vhd +++ /dev/null @@ -1,1934 +0,0 @@ --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0235 : Added IM 2 fix by Mike Johnson --- --- 0238 : Added NoRead signal --- --- 0238b: Fixed instruction timing for POP and DJNZ --- --- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes --- --- 0242 : Fixed I/O instruction timing, cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_MCode is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic - ); -end T80_MCode; - -architecture rtl of T80_MCode is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; --- constant aNone : std_logic_vector(2 downto 0) := "000"; --- constant aXY : std_logic_vector(2 downto 0) := "001"; --- constant aIOA : std_logic_vector(2 downto 0) := "010"; --- constant aSP : std_logic_vector(2 downto 0) := "011"; --- constant aBC : std_logic_vector(2 downto 0) := "100"; --- constant aDE : std_logic_vector(2 downto 0) := "101"; --- constant aZI : std_logic_vector(2 downto 0) := "110"; - - function is_cc_true( - F : std_logic_vector(7 downto 0); - cc : bit_vector(2 downto 0) - ) return boolean is - begin - if Mode = 3 then - case cc is - when "000" => return F(7) = '0'; -- NZ - when "001" => return F(7) = '1'; -- Z - when "010" => return F(4) = '0'; -- NC - when "011" => return F(4) = '1'; -- C - when "100" => return false; - when "101" => return false; - when "110" => return false; - when "111" => return false; - end case; - else - case cc is - when "000" => return F(6) = '0'; -- NZ - when "001" => return F(6) = '1'; -- Z - when "010" => return F(0) = '0'; -- NC - when "011" => return F(0) = '1'; -- C - when "100" => return F(2) = '0'; -- PO - when "101" => return F(2) = '1'; -- PE - when "110" => return F(7) = '0'; -- P - when "111" => return F(7) = '1'; -- M - end case; - end if; - end; - -begin - - process (IR, ISet, MCycle, F, NMICycle, IntCycle) - variable DDD : std_logic_vector(2 downto 0); - variable SSS : std_logic_vector(2 downto 0); - variable DPair : std_logic_vector(1 downto 0); - variable IRB : bit_vector(7 downto 0); - begin - DDD := IR(5 downto 3); - SSS := IR(2 downto 0); - DPair := IR(5 downto 4); - IRB := to_bitvector(IR); - - MCycles <= "001"; - if MCycle = "001" then - TStates <= "100"; - else - TStates <= "011"; - end if; - Prefix <= "00"; - Inc_PC <= '0'; - Inc_WZ <= '0'; - IncDec_16 <= "0000"; - Read_To_Acc <= '0'; - Read_To_Reg <= '0'; - Set_BusB_To <= "0000"; - Set_BusA_To <= "0000"; - ALU_Op <= "0" & IR(5 downto 3); - Save_ALU <= '0'; - PreserveC <= '0'; - Arith16 <= '0'; - IORQ <= '0'; - Set_Addr_To <= aNone; - Jump <= '0'; - JumpE <= '0'; - JumpXY <= '0'; - Call <= '0'; - RstP <= '0'; - LDZ <= '0'; - LDW <= '0'; - LDSPHL <= '0'; - Special_LD <= "000"; - ExchangeDH <= '0'; - ExchangeRp <= '0'; - ExchangeAF <= '0'; - ExchangeRS <= '0'; - I_DJNZ <= '0'; - I_CPL <= '0'; - I_CCF <= '0'; - I_SCF <= '0'; - I_RETN <= '0'; - I_BT <= '0'; - I_BC <= '0'; - I_BTR <= '0'; - I_RLD <= '0'; - I_RRD <= '0'; - I_INRC <= '0'; - SetDI <= '0'; - SetEI <= '0'; - IMode <= "11"; - Halt <= '0'; - NoRead <= '0'; - Write <= '0'; - - case ISet is - when "00" => - ------------------------------------------------------------------------------- --- --- Unprefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is --- 8 BIT LOAD GROUP - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- LD r,r' - Set_BusB_To(2 downto 0) <= SSS; - ExchangeRp <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => - -- LD r,n - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => - -- LD r,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => - -- LD (HL),r - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110110" => - -- LD (HL),n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00001010" => - -- LD A,(BC) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00011010" => - -- LD A,(DE) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00111010" => - if Mode = 3 then - -- LDD A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end if; - when "00000010" => - -- LD (BC),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00010010" => - -- LD (DE),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110010" => - if Mode = 3 then - -- LDD (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - end if; - --- 16 BIT LOAD GROUP - when "00000001"|"00010001"|"00100001"|"00110001" => - -- LD dd,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1000"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1001"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "00101010" => - if Mode = 3 then - -- LDI A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD HL,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end if; - when "00100010" => - if Mode = 3 then - -- LDI (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD (nn),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "0101"; -- L - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "0100"; -- H - when 5 => - Write <= '1'; - when others => null; - end case; - end if; - when "11111001" => - -- LD SP,HL - TStates <= "110"; - LDSPHL <= '1'; - when "11000101"|"11010101"|"11100101"|"11110101" => - -- PUSH qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "0111"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 2 => - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "1011"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - Write <= '1'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "11000001"|"11010001"|"11100001"|"11110001" => - -- POP qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1011"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - IncDec_16 <= "0111"; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "0111"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - --- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP - when "11101011" => - if Mode /= 3 then - -- EX DE,HL - ExchangeDH <= '1'; - end if; - when "00001000" => - if Mode = 3 then - -- LD (nn),SP - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "1000"; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "1001"; - when 5 => - Write <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EX AF,AF' - ExchangeAF <= '1'; - end if; - when "11011001" => - if Mode = 3 then - -- RETI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - SetEI <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EXX - ExchangeRS <= '1'; - end if; - when "11100011" => - if Mode /= 3 then - -- EX (SP),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0101"; - Set_BusB_To <= "0101"; - Set_Addr_To <= aSP; - when 3 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - TStates <= "100"; - Write <= '1'; - when 4 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0100"; - Set_BusB_To <= "0100"; - Set_Addr_To <= aSP; - when 5 => - IncDec_16 <= "1111"; - TStates <= "101"; - Write <= '1'; - when others => null; - end case; - end if; - --- 8 BIT ARITHMETIC AND LOGICAL GROUP - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- ADD A,r - -- ADC A,r - -- SUB A,r - -- SBC A,r - -- AND A,r - -- OR A,r - -- XOR A,r - -- CP A,r - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- ADD A,(HL) - -- ADC A,(HL) - -- SUB A,(HL) - -- SBC A,(HL) - -- AND A,(HL) - -- OR A,(HL) - -- XOR A,(HL) - -- CP A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - when others => null; - end case; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- ADD A,n - -- ADC A,n - -- SUB A,n - -- SBC A,n - -- AND A,n - -- OR A,n - -- XOR A,n - -- CP A,n - MCycles <= "010"; - if MCycle = "010" then - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - end if; - when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => - -- INC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - when "00110100" => - -- INC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => - -- DEC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0010"; - when "00110101" => - -- DEC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - ALU_Op <= "0010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - --- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS - when "00100111" => - -- DAA - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - ALU_Op <= "1100"; - Save_ALU <= '1'; - when "00101111" => - -- CPL - I_CPL <= '1'; - when "00111111" => - -- CCF - I_CCF <= '1'; - when "00110111" => - -- SCF - I_SCF <= '1'; - when "00000000" => - if NMICycle = '1' then - -- NMI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when others => null; - end case; - elsif IntCycle = '1' then - -- INT (IM 2) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - LDZ <= '1'; - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when 4 => - Inc_PC <= '1'; - LDZ <= '1'; - when 5 => - Jump <= '1'; - when others => null; - end case; - else - -- NOP - end if; - when "01110110" => - -- HALT - Halt <= '1'; - when "11110011" => - -- DI - SetDI <= '1'; - when "11111011" => - -- EI - SetEI <= '1'; - --- 16 BIT ARITHMETIC GROUP - when "00001001"|"00011001"|"00101001"|"00111001" => - -- ADD HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - Arith16 <= '1'; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - Arith16 <= '1'; - when others => - end case; - when "00000011"|"00010011"|"00100011"|"00110011" => - -- INC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "01"; - IncDec_16(1 downto 0) <= DPair; - when "00001011"|"00011011"|"00101011"|"00111011" => - -- DEC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "11"; - IncDec_16(1 downto 0) <= DPair; - --- ROTATE AND SHIFT GROUP - when "00000111" - -- RLCA - |"00010111" - -- RLA - |"00001111" - -- RRCA - |"00011111" => - -- RRA - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - --- JUMP GROUP - when "11000011" => - -- JP nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - Jump <= '1'; - when others => null; - end case; - when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+C),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "01" => - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - when "10" => - -- LD A,($FF00+C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => - end case; - when "11" => - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end case; - else - -- JP cc,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Jump <= '1'; - end if; - when others => null; - end case; - end if; - when "00011000" => - if Mode /= 2 then - -- JR e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00111000" => - if Mode /= 2 then - -- JR C,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00110000" => - if Mode /= 2 then - -- JR NC,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00101000" => - if Mode /= 2 then - -- JR Z,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00100000" => - if Mode /= 2 then - -- JR NZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "11101001" => - -- JP (HL) - JumpXY <= '1'; - when "00010000" => - if Mode = 3 then - I_DJNZ <= '1'; - elsif Mode < 2 then - -- DJNZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - I_DJNZ <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= "000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - I_DJNZ <= '1'; - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - --- CALL AND RETURN GROUP - when "11001101" => - -- CALL nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - IncDec_16 <= "1111"; - Inc_PC <= '1'; - TStates <= "100"; - Set_Addr_To <= aSP; - LDW <= '1'; - Set_BusB_To <= "1101"; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => - if IR(5) = '0' or Mode /= 3 then - -- CALL cc,nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - LDW <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - TStates <= "100"; - Set_BusB_To <= "1101"; - else - MCycles <= "011"; - end if; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - end if; - when "11001001" => - -- RET - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+nn),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "01" => - -- ADD SP,n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - ALU_Op <= "0000"; - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To <= "1000"; - Set_BusB_To <= "0110"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To <= "1001"; - Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! - when others => - end case; - when "10" => - -- LD A,($FF00+nn) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "11" => - -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end case; - else - -- RET cc - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Set_Addr_TO <= aSP; - else - MCycles <= "001"; - end if; - TStates <= "101"; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - end if; - when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => - -- RST p - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - Write <= '1'; - RstP <= '1'; - when others => null; - end case; - --- INPUT AND OUTPUT GROUP - when "11011011" => - if Mode /= 3 then - -- IN A,(n) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => null; - end case; - end if; - when "11010011" => - if Mode /= 3 then - -- OUT (n),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - IORQ <= '1'; - when others => null; - end case; - end if; - ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- --- MULTIBYTE INSTRUCTIONS ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- - - when "11001011" => - if Mode /= 2 then - Prefix <= "01"; - end if; - - when "11101101" => - if Mode < 2 then - Prefix <= "10"; - end if; - - when "11011101"|"11111101" => - if Mode < 2 then - Prefix <= "11"; - end if; - - end case; - - when "01" => - ------------------------------------------------------------------------------- --- --- CB prefixed instructions --- ------------------------------------------------------------------------------- - - Set_BusA_To(2 downto 0) <= IR(2 downto 0); - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => - -- RLC r - -- RL r - -- RRC r - -- RR r - -- SLA r - -- SRA r - -- SRL r - -- SLL r (Undocumented) / SWAP r - if MCycle = "001" then - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => - -- RLC (HL) - -- RL (HL) - -- RRC (HL) - -- RR (HL) - -- SRA (HL) - -- SRL (HL) - -- SLA (HL) - -- SLL (HL) (Undocumented) / SWAP (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => - end case; - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- BIT b,r - if MCycle = "001" then - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - ALU_Op <= "1001"; - end if; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => - -- BIT b,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => - end case; - when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => - -- SET b,r - if MCycle = "001" then - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- SET b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => - end case; - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- RES b,r - if MCycle = "001" then - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- RES b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => - end case; - end case; - - when others => - ------------------------------------------------------------------------------- --- --- ED prefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" - - - |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" - | "10100100"|"10100101"|"10100110"|"10100111" - | "10101100"|"10101101"|"10101110"|"10101111" - | "10110100"|"10110101"|"10110110"|"10110111" - | "10111100"|"10111101"|"10111110"|"10111111" - |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => - null; -- NOP, undocumented - when "01111110"|"01111111" => - -- NOP, undocumented - null; --- 8 BIT LOAD GROUP - when "01010111" => - -- LD A,I - Special_LD <= "100"; - TStates <= "101"; - when "01011111" => - -- LD A,R - Special_LD <= "101"; - TStates <= "101"; - when "01000111" => - -- LD I,A - Special_LD <= "110"; - TStates <= "101"; - when "01001111" => - -- LD R,A - Special_LD <= "111"; - TStates <= "101"; --- 16 BIT LOAD GROUP - when "01001011"|"01011011"|"01101011"|"01111011" => - -- LD dd,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1000"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '1'; - end if; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1001"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "01000011"|"01010011"|"01100011"|"01110011" => - -- LD (nn),dd - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1000"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1001"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 5 => - Write <= '1'; - when others => null; - end case; - when "10100000" | "10101000" | "10110000" | "10111000" => - -- LDI, LDD, LDIR, LDDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0000"; - Set_Addr_To <= aDE; - if IR(3) = '0' then - IncDec_16 <= "0110"; -- IX - else - IncDec_16 <= "1110"; - end if; - when 3 => - I_BT <= '1'; - TStates <= "101"; - Write <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0101"; -- DE - else - IncDec_16 <= "1101"; - end if; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100001" | "10101001" | "10110001" | "10111001" => - -- CPI, CPD, CPIR, CPDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0111"; - Save_ALU <= '1'; - PreserveC <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0110"; - else - IncDec_16 <= "1110"; - end if; - when 3 => - NoRead <= '1'; - I_BC <= '1'; - TStates <= "101"; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => - -- NEG - Alu_OP <= "0010"; - Set_BusB_To <= "0111"; - Set_BusA_To <= "1010"; - Read_To_Acc <= '1'; - Save_ALU <= '1'; - when "01000110"|"01001110"|"01100110"|"01101110" => - -- IM 0 - IMode <= "00"; - when "01010110"|"01110110" => - -- IM 1 - IMode <= "01"; - when "01011110"|"01110111" => - -- IM 2 - IMode <= "10"; --- 16 bit arithmetic - when "01001010"|"01011010"|"01101010"|"01111010" => - -- ADC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0001"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01000010"|"01010010"|"01100010"|"01110010" => - -- SBC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01101111" => - -- RLD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1101"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RLD <= '1'; - Write <= '1'; - when others => - end case; - when "01100111" => - -- RRD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1110"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RRD <= '1'; - Write <= '1'; - when others => - end case; - when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => - -- RETI, RETN - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - when others => null; - end case; - when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => - -- IN r,(C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - IORQ <= '1'; - if IR(5 downto 3) /= "110" then - Read_To_Reg <= '1'; - Set_BusA_To(2 downto 0) <= IR(5 downto 3); - end if; - I_INRC <= '1'; - when others => - end case; - when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => - -- OUT (C),r - -- OUT (C),0 - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To(2 downto 0) <= IR(5 downto 3); - if IR(5 downto 3) = "110" then - Set_BusB_To(3) <= '1'; - end if; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "10100010" | "10101010" | "10110010" | "10111010" => - -- INI, IND, INIR, INDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - IORQ <= '1'; - Set_BusB_To <= "0110"; - Set_Addr_To <= aXY; - when 3 => - if IR(3) = '0' then - IncDec_16 <= "0010"; - else - IncDec_16 <= "1010"; - end if; - TStates <= "100"; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100011" | "10101011" | "10110011" | "10111011" => - -- OUTI, OUTD, OTIR, OTDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_To <= aXY; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - Set_BusB_To <= "0110"; - Set_Addr_To <= aBC; - when 3 => - if IR(3) = '0' then - IncDec_16 <= "0010"; - else - IncDec_16 <= "1010"; - end if; - IORQ <= '1'; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - end case; - - end case; - - if Mode = 1 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "011"; - end if; - end if; - - if Mode = 3 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "100"; - end if; - end if; - - if Mode < 2 then - if MCycle = "110" then - Inc_PC <= '1'; - if Mode = 1 then - Set_Addr_To <= aXY; - TStates <= "100"; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - end if; - if IRB = "00110110" or IRB = "11001011" then - Set_Addr_To <= aNone; - end if; - end if; - if MCycle = "111" then - if Mode = 0 then - TStates <= "101"; - end if; - if ISet /= "01" then - Set_Addr_To <= aXY; - end if; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - if IRB = "00110110" or ISet = "01" then - -- LD (HL),n - Inc_PC <= '1'; - else - NoRead <= '1'; - end if; - end if; - end if; - - end process; - -end; diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/NinjaKun_MiST/rtl/cpu/T80_Pack.vhd deleted file mode 100644 index ac7d34da..00000000 --- a/Arcade_MiST/NinjaKun_MiST/rtl/cpu/T80_Pack.vhd +++ /dev/null @@ -1,208 +0,0 @@ --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- - -library IEEE; -use IEEE.std_logic_1164.all; - -package T80_Pack is - - component T80 - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); - end component; - - component T80_Reg - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); - end component; - - component T80_MCode - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic - ); - end component; - - component T80_ALU - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); - end component; - -end; diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/NinjaKun_MiST/rtl/cpu/T80_Reg.vhd deleted file mode 100644 index 828485fb..00000000 --- a/Arcade_MiST/NinjaKun_MiST/rtl/cpu/T80_Reg.vhd +++ /dev/null @@ -1,105 +0,0 @@ --- --- T80 Registers, technology independent --- --- Version : 0244 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t51/ --- --- Limitations : --- --- File history : --- --- 0242 : Initial release --- --- 0244 : Changed to single register file --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_Reg is - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); -end T80_Reg; - -architecture rtl of T80_Reg is - - type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); - signal RegsH : Register_Image(0 to 7); - signal RegsL : Register_Image(0 to 7); - -begin - - process (Clk) - begin - if Clk'event and Clk = '1' then - if CEN = '1' then - if WEH = '1' then - RegsH(to_integer(unsigned(AddrA))) <= DIH; - end if; - if WEL = '1' then - RegsL(to_integer(unsigned(AddrA))) <= DIL; - end if; - end if; - end if; - end process; - - DOAH <= RegsH(to_integer(unsigned(AddrA))); - DOAL <= RegsL(to_integer(unsigned(AddrA))); - DOBH <= RegsH(to_integer(unsigned(AddrB))); - DOBL <= RegsL(to_integer(unsigned(AddrB))); - DOCH <= RegsH(to_integer(unsigned(AddrC))); - DOCL <= RegsL(to_integer(unsigned(AddrC))); - -end; diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/cpu/T80s.vhd b/Arcade_MiST/NinjaKun_MiST/rtl/cpu/T80s.vhd deleted file mode 100644 index 5b612110..00000000 --- a/Arcade_MiST/NinjaKun_MiST/rtl/cpu/T80s.vhd +++ /dev/null @@ -1,190 +0,0 @@ --- --- Z80 compatible microprocessor core, synchronous top level --- Different timing than the original z80 --- Inputs needs to be synchronous and outputs may glitch --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0210 : Fixed read with wait --- --- 0211 : Fixed interrupt cycle --- --- 0235 : Updated for T80 interface change --- --- 0236 : Added T2Write generic --- --- 0237 : Fixed T2Write with wait state --- --- 0238 : Updated for T80 interface change --- --- 0240 : Updated for T80 interface change --- --- 0242 : Updated for T80 interface change --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80s is - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2 - IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - MREQ_n : out std_logic; - IORQ_n : out std_logic; - RD_n : out std_logic; - WR_n : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0) - ); -end T80s; - -architecture rtl of T80s is - - signal CEN : std_logic; - signal IntCycle_n : std_logic; - signal NoRead : std_logic; - signal Write : std_logic; - signal IORQ : std_logic; - signal DI_Reg : std_logic_vector(7 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal TState : std_logic_vector(2 downto 0); - -begin - - CEN <= '1'; - - u0 : T80 - generic map( - Mode => Mode, - IOWait => IOWait) - port map( - CEN => CEN, - M1_n => M1_n, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => RFSH_n, - HALT_n => HALT_n, - WAIT_n => Wait_n, - INT_n => INT_n, - NMI_n => NMI_n, - RESET_n => RESET_n, - BUSRQ_n => BUSRQ_n, - BUSAK_n => BUSAK_n, - CLK_n => CLK_n, - A => A, - DInst => DI, - DI => DI_Reg, - DO => DO, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n); - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - DI_Reg <= "00000000"; - elsif CLK_n'event and CLK_n = '1' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - if MCycle = "001" then - if TState = "001" or (TState = "010" and Wait_n = '0') then - RD_n <= not IntCycle_n; - MREQ_n <= not IntCycle_n; - IORQ_n <= IntCycle_n; - end if; - if TState = "011" then - MREQ_n <= '0'; - end if; - else - if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then - RD_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - if T2Write = 0 then - if TState = "010" and Write = '1' then - WR_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - else - if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then - WR_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - end if; - end if; - if TState = "010" and Wait_n = '1' then - DI_Reg <= DI; - end if; - end if; - end process; - -end; diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/dpram_1r1w.vhd b/Arcade_MiST/NinjaKun_MiST/rtl/dpram_1r1w.vhd deleted file mode 100644 index 73f3d5d1..00000000 --- a/Arcade_MiST/NinjaKun_MiST/rtl/dpram_1r1w.vhd +++ /dev/null @@ -1,101 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY dpram_1r1w IS - GENERIC - ( - widthad_a : natural; - width_a : natural := 8; - outdata_reg_b : string := "UNREGISTERED" - ); - PORT - ( - data : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - rdaddress : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - rdclock : IN STD_LOGIC ; - rdclocken : IN STD_LOGIC := '1'; - wraddress : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - wrclock : IN STD_LOGIC ; - wrclocken : IN STD_LOGIC := '1'; - wren : IN STD_LOGIC := '1'; - q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); -END dpram_1r1w; - - -ARCHITECTURE SYN OF dpram_1r1w IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - - COMPONENT altsyncram - GENERIC ( - address_reg_b : STRING; - clock_enable_input_a : STRING; - clock_enable_input_b : STRING; - clock_enable_output_b : STRING; - intended_device_family : STRING; - lpm_type : STRING; - numwords_a : NATURAL; - numwords_b : NATURAL; - operation_mode : STRING; - outdata_aclr_b : STRING; - outdata_reg_b : STRING; - power_up_uninitialized : STRING; - widthad_a : NATURAL; - widthad_b : NATURAL; - width_a : NATURAL; - width_b : NATURAL; - width_byteena_a : NATURAL - ); - PORT ( - clocken0 : IN STD_LOGIC ; - clocken1 : IN STD_LOGIC ; - wren_a : IN STD_LOGIC ; - clock0 : IN STD_LOGIC ; - clock1 : IN STD_LOGIC ; - address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - q <= sub_wire0(width_a-1 DOWNTO 0); - - altsyncram_component : altsyncram - GENERIC MAP ( - address_reg_b => "CLOCK1", - clock_enable_input_a => "BYPASS", - clock_enable_input_b => "BYPASS", - clock_enable_output_b => "BYPASS", - intended_device_family => "Cyclone III", - lpm_type => "altsyncram", - numwords_a => 2**widthad_a, - numwords_b => 2**widthad_a, - operation_mode => "DUAL_PORT", - outdata_aclr_b => "NONE", - outdata_reg_b => outdata_reg_b, - power_up_uninitialized => "FALSE", - widthad_a => widthad_a, - widthad_b => widthad_a, - width_a => width_a, - width_b => width_a, - width_byteena_a => 1 - ) - PORT MAP ( - clocken0 => wrclocken, - clocken1 => rdclocken, - wren_a => wren, - clock0 => wrclock, - clock1 => rdclock, - address_a => wraddress, - address_b => rdaddress, - data_a => data, - q_b => sub_wire0 - ); - -END SYN; diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/mems.v b/Arcade_MiST/NinjaKun_MiST/rtl/mems.v deleted file mode 100644 index e943fd5b..00000000 --- a/Arcade_MiST/NinjaKun_MiST/rtl/mems.v +++ /dev/null @@ -1,116 +0,0 @@ -// Copyright (c) 2011 MiSTer-X - -module VDPRAM400x2 -( - input CL0, - input [10:0] AD0, - input WR0, - input [7:0] WD0, - output [7:0] RD0, - - input CL1, - input [9:0] AD1, - output [15:0] RD1 -); - -reg A10; -always @( posedge CL0 ) A10 <= AD0[10]; - -wire [7:0] RD00, RD01; -DPRAM400 LS( CL0, AD0[9:0], WR0 & (~AD0[10]), WD0, RD00, CL1, AD1, 1'b0, 8'h0, RD1[ 7:0] ); -DPRAM400 HS( CL0, AD0[9:0], WR0 & ( AD0[10]), WD0, RD01, CL1, AD1, 1'b0, 8'h0, RD1[15:8] ); - -assign RD0 = A10 ? RD01 : RD00; - -endmodule - - -module DPRAM800 -( - input CL0, - input [10:0] AD0, - input WE0, - input [7:0] WD0, - output reg [7:0] RD0, - - input CL1, - input [10:0] AD1, - input WE1, - input [7:0] WD1, - output reg [7:0] RD1 -); - -reg [7:0] core[0:2047]; - -always @( posedge CL0 ) begin - if (WE0) core[AD0] <= WD0; - RD0 <= core[AD0]; -end - -always @( posedge CL1 ) begin - if (WE1) core[AD1] <= WD1; - RD1 <= core[AD1]; -end - -endmodule - - -module DPRAM400 -( - input CL0, - input [9:0] AD0, - input WE0, - input [7:0] WD0, - output reg [7:0] RD0, - - input CL1, - input [9:0] AD1, - input WE1, - input [7:0] WD1, - output reg [7:0] RD1 -); - -reg [7:0] core[0:1023]; - -always @( posedge CL0 ) begin - if (WE0) core[AD0] <= WD0; - RD0 <= core[AD0]; -end - -always @( posedge CL1 ) begin - if (WE1) core[AD1] <= WD1; - RD1 <= core[AD1]; -end - -endmodule - - -module DPRAM200 -( - input CL0, - input [8:0] AD0, - input WE0, - input [7:0] WD0, - output reg [7:0] RD0, - - input CL1, - input [8:0] AD1, - input WE1, - input [7:0] WD1, - output reg [7:0] RD1 -); - -reg [7:0] core[0:511]; - -always @( posedge CL0 ) begin - if (WE0) core[AD0] <= WD0; - RD0 <= core[AD0]; -end - -always @( posedge CL1 ) begin - if (WE1) core[AD1] <= WD1; - RD1 <= core[AD1]; -end - -endmodule - diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_video.v b/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_video.v deleted file mode 100644 index 44311d33..00000000 --- a/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_video.v +++ /dev/null @@ -1,164 +0,0 @@ -// Copyright (c) 2011,19 MiSTer-X - -module ninjakun_video -( - input RESET, - input VCLKx4, - input VCLK, - input [8:0] PH, - input [8:0] PV, - - output [8:0] PALAD, // Pixel Output (Palet Index) - - output [9:0] FGVAD, // FG - input [15:0] FGVDT, - - output [9:0] BGVAD, // BG - input [15:0] BGVDT, - input [7:0] BGSCX, - input [7:0] BGSCY, - - output [10:0] SPAAD, // Sprite - input [7:0] SPADT, - - output VBLK, - input DBGPD, // Palet Display (for Debug) -// output [12:0] sp_rom_addr, -// input [31:0] sp_rom_data, -// output [12:0] fg_rom_addr, -// input [31:0] fg_rom_data, - output [12:0] bg_rom_addr, - input [31:0] bg_rom_data -); - -assign VBLK = (PV>=193); - -// ROMs -wire SPCFT = 1'b1; -wire [12:0] SPCAD; -wire [31:0] SPCDT; - -wire [12:0] FGCAD; -wire [31:0] FGCDT; - -wire [12:0] BGCAD; -wire [31:0] BGCDT; - -//NJFGROM sprom(~VCLKx4, SPCAD, SPCDT, ROMCL, ROMAD, ROMDT, ROMEN); -//NJFGROM fgrom( ~VCLK, FGCAD, FGCDT, ROMCL, ROMAD, ROMDT, ROMEN); -//NJBGROM bgrom( ~VCLK, BGCAD, BGCDT, ROMCL, ROMAD, ROMDT, ROMEN); -//assign sp_rom_addr = SPCAD; -//assign SPCDT = sp_rom_data; -//assign fg_rom_addr = FGCAD; -//assign FGCDT = fg_rom_data; -/* -static GFXDECODE_START( gfx_ninjakun ) - GFXDECODE_ENTRY( "gfx1", 0, layout16x16, 0x200, 16 ) // sprites - GFXDECODE_ENTRY( "gfx1", 0, layout8x8, 0x000, 16 ) // fg tiles - GFXDECODE_ENTRY( "gfx2", 0, layout8x8, 0x100, 16 ) // bg tiles -GFXDECODE_END*/ - -assign bg_rom_addr = BGCAD; -assign BGCDT = bg_rom_data; - -fg1_rom fg1_rom ( - .clk(~VCLKx4),//if sprite ? ~VCLKx4 : ~VCLK - .addr(SPCAD),//if sprite ? SPCAD : FGCAD - .data(SPCDT[7:0])//if sprite ? SPCDT[7:0] : FGCDT[7:0] -); - -fg2_rom fg2_rom ( - .clk(~VCLKx4), - .addr(SPCAD), - .data(SPCDT[15:8]) -); - -fg3_rom fg3_rom ( - .clk(~VCLKx4), - .addr(SPCAD), - .data(SPCDT[23:16]) -); - -fg4_rom fg4_rom ( - .clk(~VCLKx4), - .addr(SPCAD), - .data(SPCDT[31:24]) -);/* - -fg1_rom fg1_rom ( - .clk(~VCLK),//if sprite ? ~VCLKx4 : ~VCLK - .addr(FGCAD),//if sprite ? SPCAD : FGCAD - .data(FGCDT[7:0])//if sprite ? SPCDT[7:0] : FGCDT[7:0] -); - -fg2_rom fg2_rom ( - .clk(~VCLK), - .addr(FGCAD), - .data(FGCDT[15:8]) -); - -fg3_rom fg3_rom ( - .clk(~VCLK), - .addr(FGCAD), - .data(FGCDT[23:16]) -); - -fg4_rom fg4_rom ( - .clk(~VCLK), - .addr(FGCAD), - .data(FGCDT[31:24]) -);*/ - -// Fore-Ground Scanline Generator -wire FGPRI; -wire [8:0] FGOUT; -ninjakun_fg fg( - VCLK, - PH, PV, - FGVAD, FGVDT, - FGCAD, FGCDT, - {FGPRI, FGOUT} -); -wire FGOPQ =(FGOUT[3:0]!=0); -wire FGPPQ = FGOPQ & (~FGPRI); - -// Back-Ground Scanline Generator -wire [8:0] BGOUT; -ninjakun_bg bg( - VCLK, - PH, PV, - BGSCX, BGSCY, - BGVAD, BGVDT, - BGCAD, BGCDT, - BGOUT -); - -// Sprite Scanline Generator -wire [8:0] SPOUT; -ninjakun_sp sp( - VCLKx4, VCLK, - PH, PV, - SPAAD, SPADT, - SPCAD, SPCDT, SPCFT, - SPOUT -); -wire SPOPQ = (SPOUT[3:0]!=0); - -// Palet Display (for Debug) -wire [8:0] PDOUT = (PV[7]|PV[8]) ? 0 : {PV[6:2],PH[7:4]}; - -// Color Mixer -dataselector_4D_9B dataselector_4D_9B( - .OUT(PALAD), - .EN1(DBGPD), - .IN1(PDOUT), - .EN2(FGPPQ), - .IN2(FGOUT), - .EN3(SPOPQ), - .IN3(SPOUT), - .EN4(FGOPQ), - .IN4(FGOUT), - .IND(BGOUT) -); - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/rom/NINJAKUN.ROM b/Arcade_MiST/NinjaKun_MiST/rtl/rom/NINJAKUN.ROM deleted file mode 100644 index 3f9f5ec0..00000000 Binary files a/Arcade_MiST/NinjaKun_MiST/rtl/rom/NINJAKUN.ROM and /dev/null differ diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/rom/bg.bin b/Arcade_MiST/NinjaKun_MiST/rtl/rom/bg.bin deleted file mode 100644 index cee34345..00000000 Binary files a/Arcade_MiST/NinjaKun_MiST/rtl/rom/bg.bin and /dev/null differ diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/rom/cpu1_rom.bin b/Arcade_MiST/NinjaKun_MiST/rtl/rom/cpu1_rom.bin deleted file mode 100644 index 8f814bf9..00000000 Binary files a/Arcade_MiST/NinjaKun_MiST/rtl/rom/cpu1_rom.bin and /dev/null differ diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/rom/cpu2_rom.bin b/Arcade_MiST/NinjaKun_MiST/rtl/rom/cpu2_rom.bin deleted file mode 100644 index 3d59804f..00000000 Binary files a/Arcade_MiST/NinjaKun_MiST/rtl/rom/cpu2_rom.bin and /dev/null differ diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/rom/fg1_rom.vhd b/Arcade_MiST/NinjaKun_MiST/rtl/rom/fg1_rom.vhd deleted file mode 100644 index ac847c73..00000000 --- a/Arcade_MiST/NinjaKun_MiST/rtl/rom/fg1_rom.vhd +++ /dev/null @@ -1,534 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity fg1_rom is -port ( - clk : in std_logic; - addr : in std_logic_vector(12 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of fg1_rom is - type rom is array(0 to 8191) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"AA",X"AA",X"99",X"99",X"AA",X"AA",X"99",X"99",X"AA",X"AA",X"99",X"99",X"AA",X"AA",X"99",X"99", - X"55",X"55",X"EE",X"EE",X"58",X"88",X"8B",X"BB",X"99",X"9B",X"97",X"78",X"99",X"AA",X"AA",X"AA", - X"55",X"55",X"EE",X"55",X"88",X"88",X"88",X"BB",X"9B",X"BB",X"99",X"AA",X"9A",X"A9",X"99",X"99", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"11",X"11",X"11",X"21",X"21",X"12",X"12", - X"21",X"21",X"22",X"22",X"32",X"32",X"23",X"23",X"32",X"32",X"33",X"33",X"43",X"43",X"34",X"34", - X"43",X"43",X"34",X"34",X"54",X"54",X"45",X"45",X"54",X"54",X"45",X"45",X"65",X"65",X"56",X"56", - X"65",X"65",X"56",X"56",X"76",X"76",X"67",X"67",X"76",X"76",X"67",X"67",X"87",X"87",X"78",X"78", - X"87",X"87",X"78",X"78",X"98",X"98",X"89",X"89",X"98",X"98",X"89",X"89",X"A9",X"A9",X"9A",X"9A", - X"A9",X"A9",X"9A",X"9A",X"BA",X"BA",X"AB",X"AB",X"BA",X"BA",X"AB",X"AB",X"CB",X"CB",X"BC",X"BC", - X"CB",X"CB",X"BC",X"BC",X"DC",X"DC",X"CD",X"CD",X"DC",X"DC",X"CD",X"CD",X"ED",X"ED",X"DE",X"DE", - X"ED",X"ED",X"DE",X"DE",X"FE",X"FE",X"EF",X"EF",X"FE",X"FE",X"EF",X"EF",X"FF",X"FF",X"FF",X"FF", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"40", - X"00",X"00",X"00",X"00",X"00",X"04",X"00",X"4A",X"00",X"AA",X"00",X"DA",X"04",X"AA",X"00",X"AA", - X"4A",X"A4",X"4A",X"AA",X"AA",X"AA",X"AA",X"AD",X"AA",X"AA",X"AD",X"AA",X"AA",X"AA",X"AA",X"AD", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"44",X"00",X"4A",X"00",X"A4",X"00",X"AA",X"04",X"AA",X"44",X"AA",X"AA", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"00",X"41",X"00",X"11",X"40",X"11",X"44",X"11", - X"00",X"00",X"00",X"00",X"00",X"04",X"00",X"04",X"00",X"04",X"00",X"04",X"00",X"04",X"00",X"44", - X"44",X"44",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11", - X"00",X"11",X"44",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11", - X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11", - X"44",X"44",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11", - X"44",X"44",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11", - X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11", - X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11", - X"44",X"44",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11", - X"00",X"00",X"40",X"00",X"14",X"00",X"14",X"00",X"14",X"00",X"14",X"00",X"14",X"00",X"14",X"00", - X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11", - X"11",X"40",X"11",X"14",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11", - X"DA",X"AA",X"AA",X"AA",X"AA",X"DA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA", - X"A4",X"11",X"AA",X"33",X"AA",X"44",X"44",X"AA",X"4A",X"44",X"AA",X"33",X"A4",X"33",X"44",X"44", - X"AA",X"DA",X"AA",X"AA",X"AA",X"A4",X"4A",X"4F",X"E4",X"A4",X"E4",X"44",X"5E",X"04",X"5E",X"04", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"44",X"44",X"00",X"DD",X"00",X"DD",X"00",X"DD", - X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"44",X"44", - X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"44",X"44", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"44",X"44",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"44",X"44",X"DD",X"DD",X"DD",X"4D",X"DD",X"4D", - X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"44",X"44", - X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"44",X"44", - X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"44",X"44",X"DD",X"D4",X"DD",X"D4",X"DD",X"D4", - X"FF",X"5E",X"FF",X"5E",X"FF",X"5E",X"FF",X"E5",X"44",X"E5",X"34",X"E5",X"34",X"56",X"34",X"56", - X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"44",X"44", - X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"44",X"44", - X"66",X"88",X"66",X"57",X"66",X"58",X"66",X"55",X"66",X"22",X"66",X"99",X"66",X"BB",X"65",X"99", - X"88",X"88",X"77",X"77",X"58",X"88",X"35",X"55",X"32",X"22",X"39",X"99",X"39",X"BB",X"39",X"99", - X"5E",X"04",X"65",X"04",X"65",X"04",X"65",X"04",X"66",X"44",X"66",X"44",X"66",X"44",X"44",X"E4", - X"00",X"DD",X"00",X"DD",X"00",X"54",X"00",X"C4",X"00",X"C4",X"00",X"C4",X"00",X"C4",X"00",X"C4", - X"00",X"E4",X"00",X"E4",X"00",X"4E",X"00",X"4E",X"00",X"4E",X"00",X"4C",X"00",X"4C",X"00",X"4C", - X"00",X"C4",X"00",X"C4",X"00",X"C4",X"04",X"44",X"49",X"99",X"04",X"BB",X"00",X"55",X"00",X"54", - X"DD",X"DD",X"DD",X"DD",X"44",X"44",X"44",X"44",X"44",X"44",X"44",X"44",X"44",X"44",X"44",X"44", - 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if; -end process; -end architecture; diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/rom/fg2_rom.vhd b/Arcade_MiST/NinjaKun_MiST/rtl/rom/fg2_rom.vhd deleted file mode 100644 index b5a6213b..00000000 --- a/Arcade_MiST/NinjaKun_MiST/rtl/rom/fg2_rom.vhd +++ /dev/null @@ -1,534 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity fg2_rom is -port ( - clk : in std_logic; - addr : in std_logic_vector(12 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of fg2_rom is - type rom is array(0 to 8191) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"AA",X"AA",X"99",X"99",X"AA",X"AA",X"99",X"99",X"AA",X"AA",X"99",X"99",X"AA",X"AA",X"99",X"99", - X"55",X"55",X"EE",X"E5",X"88",X"88",X"BB",X"BB",X"99",X"BB",X"77",X"99",X"9A",X"AA",X"AA",X"AA", - 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if; -end process; -end architecture; diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/rom/fg3_rom.vhd b/Arcade_MiST/NinjaKun_MiST/rtl/rom/fg3_rom.vhd deleted file mode 100644 index 37d9a012..00000000 --- a/Arcade_MiST/NinjaKun_MiST/rtl/rom/fg3_rom.vhd +++ /dev/null @@ -1,534 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity fg3_rom is -port ( - clk : in std_logic; - addr : in std_logic_vector(12 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of fg3_rom is - type rom is array(0 to 8191) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"EE",X"EE",X"EE",X"FF",X"EE",X"CC",X"EE",X"DD",X"EE",X"EE",X"EE",X"FF",X"EE",X"CC",X"EE",X"DD", - X"DC",X"DE",X"DC",X"DE",X"DC",X"DE",X"DC",X"DE",X"DC",X"DE",X"DC",X"DE",X"DC",X"DE",X"DC",X"DE", - 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if; -end process; -end architecture; diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/rom/fg4_rom.vhd b/Arcade_MiST/NinjaKun_MiST/rtl/rom/fg4_rom.vhd deleted file mode 100644 index f5f8e8a4..00000000 --- a/Arcade_MiST/NinjaKun_MiST/rtl/rom/fg4_rom.vhd +++ /dev/null @@ -1,534 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity fg4_rom is -port ( - clk : in std_logic; - addr : in std_logic_vector(12 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of fg4_rom is - type rom is array(0 to 8191) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"FE",X"E0",X"FF",X"F0",X"FC",X"C0",X"FD",X"D0",X"FE",X"E0",X"FF",X"F0",X"FC",X"C0",X"FD",X"D0", - X"EC",X"FE",X"EC",X"FE",X"EC",X"FE",X"EC",X"FE",X"EC",X"FE",X"EC",X"FE",X"EC",X"FE",X"EC",X"FE", - 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if; -end process; -end architecture; diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninja-1.7a b/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninja-1.7a deleted file mode 100644 index a238ebdb..00000000 Binary files a/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninja-1.7a and /dev/null differ diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninja-10.2c b/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninja-10.2c deleted file mode 100644 index b8841200..00000000 Binary files a/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninja-10.2c and /dev/null differ diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninja-11.2d b/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninja-11.2d deleted file mode 100644 index 16ec82ea..00000000 Binary files a/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninja-11.2d and /dev/null differ diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninja-12.4c b/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninja-12.4c deleted file mode 100644 index 34fd365b..00000000 Binary files a/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninja-12.4c and /dev/null differ diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninja-13.4d b/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninja-13.4d deleted file mode 100644 index 471234d5..00000000 Binary files a/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninja-13.4d and /dev/null differ diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninja-2.7b b/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninja-2.7b deleted file mode 100644 index 3f5d524f..00000000 Binary files a/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninja-2.7b and /dev/null differ diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninja-3.7d b/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninja-3.7d deleted file mode 100644 index fad4caaf..00000000 Binary files a/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninja-3.7d and /dev/null differ diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninja-4.7e b/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninja-4.7e deleted file mode 100644 index fb1115b0..00000000 Binary files a/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninja-4.7e and /dev/null differ diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninja-5.7h b/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninja-5.7h deleted file mode 100644 index 8c204db5..00000000 Binary files a/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninja-5.7h and /dev/null differ diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninja-6.7n b/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninja-6.7n deleted file mode 100644 index 6a3e9f83..00000000 Binary files a/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninja-6.7n and /dev/null differ diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninja-7.7p b/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninja-7.7p deleted file mode 100644 index ca6345b5..00000000 Binary files a/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninja-7.7p and /dev/null differ diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninja-8.7s b/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninja-8.7s deleted file mode 100644 index 03945de2..00000000 Binary files a/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninja-8.7s and /dev/null differ diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninja-9.7t b/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninja-9.7t deleted file mode 100644 index 507aa9eb..00000000 Binary files a/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninja-9.7t and /dev/null differ diff --git a/Arcade_MiST/NinjaKun_MiST/NinjaKun_MiST.qpf b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/NinjaKun_MiST.qpf similarity index 100% rename from Arcade_MiST/NinjaKun_MiST/NinjaKun_MiST.qpf rename to Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/NinjaKun_MiST.qpf diff --git a/Arcade_MiST/NinjaKun_MiST/NinjaKun_MiST.qsf b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/NinjaKun_MiST.qsf similarity index 95% rename from Arcade_MiST/NinjaKun_MiST/NinjaKun_MiST.qsf rename to Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/NinjaKun_MiST.qsf index 33f2539b..8938f2a8 100644 --- a/Arcade_MiST/NinjaKun_MiST/NinjaKun_MiST.qsf +++ b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/NinjaKun_MiST.qsf @@ -245,17 +245,9 @@ set_global_assignment -name VHDL_FILE rtl/rom/fg3_rom.vhd set_global_assignment -name VHDL_FILE rtl/rom/fg2_rom.vhd set_global_assignment -name VHDL_FILE rtl/rom/fg1_rom.vhd set_global_assignment -name VERILOG_FILE rtl/z80ip.v -set_global_assignment -name VHDL_FILE rtl/cpu/T80s.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd -set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd set_global_assignment -name VERILOG_FILE rtl/pll.v set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv -set_global_assignment -name QIP_FILE ../../common/mist/mist.qip set_global_assignment -name VERILOG_FILE rtl/mems.v -set_global_assignment -name VHDL_FILE rtl/dpram_1r1w.vhd -set_global_assignment -name VHDL_FILE rtl/dpram.vhd -set_global_assignment -name VERILOG_FILE rtl/DPRAM1024.v +set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip +set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/NinjaKun_MiST/Snapshot/NINJAKUN.ROM b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/Snapshot/NINJAKUN.ROM similarity index 100% rename from Arcade_MiST/NinjaKun_MiST/Snapshot/NINJAKUN.ROM rename to Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/Snapshot/NINJAKUN.ROM diff --git a/Arcade_MiST/NinjaKun_MiST/clean.bat b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/clean.bat similarity index 100% rename from Arcade_MiST/NinjaKun_MiST/clean.bat rename to Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/clean.bat diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/NinjaKun_MiST.sv b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/NinjaKun_MiST.sv similarity index 100% rename from Arcade_MiST/NinjaKun_MiST/rtl/NinjaKun_MiST.sv rename to Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/NinjaKun_MiST.sv diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/YM2149_linmix_sep.vhd b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/YM2149_linmix_sep.vhd similarity index 100% rename from Arcade_MiST/NinjaKun_MiST/rtl/YM2149_linmix_sep.vhd rename to Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/YM2149_linmix_sep.vhd diff --git a/Arcade_MiST/Sega Zaxxon Hardware/rtl/build_id.tcl b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/build_id.tcl similarity index 100% rename from Arcade_MiST/Sega Zaxxon Hardware/rtl/build_id.tcl rename to Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/build_id.tcl diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/dataselector_3D_8B.v b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/dataselector_3D_8B.v similarity index 100% rename from Arcade_MiST/NinjaKun_MiST/rtl/dataselector_3D_8B.v rename to Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/dataselector_3D_8B.v diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/dataselector_4D_9B.v b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/dataselector_4D_9B.v similarity index 100% rename from Arcade_MiST/NinjaKun_MiST/rtl/dataselector_4D_9B.v rename to Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/dataselector_4D_9B.v diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/dataselector_5D_8B.v b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/dataselector_5D_8B.v similarity index 100% rename from Arcade_MiST/NinjaKun_MiST/rtl/dataselector_5D_8B.v rename to Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/dataselector_5D_8B.v diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/dpram.vhd b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/dpram.vhd similarity index 100% rename from Arcade_MiST/NinjaKun_MiST/rtl/dpram.vhd rename to Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/dpram.vhd diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/hvgen.v b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/hvgen.v similarity index 100% rename from Arcade_MiST/NinjaKun_MiST/rtl/hvgen.v rename to Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/hvgen.v diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/mems.v b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/mems.v new file mode 100644 index 00000000..e143d0d8 --- /dev/null +++ b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/mems.v @@ -0,0 +1,305 @@ +// Copyright (c) 2011 MiSTer-X + +module VDPRAM400x2 +( + input CL0, + input [10:0] AD0, + input WR0, + input [7:0] WD0, + output [7:0] RD0, + + input CL1, + input [9:0] AD1, + output [15:0] RD1 +); + +reg A10; +always @( posedge CL0 ) A10 <= AD0[10]; + +wire [7:0] RD00, RD01; +DPRAM400 LS( CL0, AD0[9:0], WR0 & (~AD0[10]), WD0, RD00, CL1, AD1, 1'b0, 8'h0, RD1[ 7:0] ); +DPRAM400 HS( CL0, AD0[9:0], WR0 & ( AD0[10]), WD0, RD01, CL1, AD1, 1'b0, 8'h0, RD1[15:8] ); + +assign RD0 = A10 ? RD01 : RD00; + +endmodule + + +module DPRAM800 +( + input CL0, + input [10:0] AD0, + input WE0, + input [7:0] WD0, + output reg [7:0] RD0, + + input CL1, + input [10:0] AD1, + input WE1, + input [7:0] WD1, + output reg [7:0] RD1 +); + +reg [7:0] core[0:2047]; + +always @( posedge CL0 ) begin + if (WE0) core[AD0] <= WD0; + RD0 <= core[AD0]; +end + +always @( posedge CL1 ) begin + if (WE1) core[AD1] <= WD1; + RD1 <= core[AD1]; +end + +endmodule + + +module DPRAM400 +( + input CL0, + input [9:0] AD0, + input WE0, + input [7:0] WD0, + output reg [7:0] RD0, + + input CL1, + input [9:0] AD1, + input WE1, + input [7:0] WD1, + output reg [7:0] RD1 +); + +reg [7:0] core[0:1023]; + +always @( posedge CL0 ) begin + if (WE0) core[AD0] <= WD0; + RD0 <= core[AD0]; +end + +always @( posedge CL1 ) begin + if (WE1) core[AD1] <= WD1; + RD1 <= core[AD1]; +end + +endmodule + + +module DPRAM200 +( + input CL0, + input [8:0] AD0, + input WE0, + input [7:0] WD0, + output reg [7:0] RD0, + + input CL1, + input [8:0] AD1, + input WE1, + input [7:0] WD1, + output reg [7:0] RD1 +); + +reg [7:0] core[0:511]; + +always @( posedge CL0 ) begin + if (WE0) core[AD0] <= WD0; + RD0 <= core[AD0]; +end + +always @( posedge CL1 ) begin + if (WE1) core[AD1] <= WD1; + RD1 <= core[AD1]; +end + +endmodule + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module DPRAM1024 ( + address_a, + address_b, + clock_a, + clock_b, + data_a, + data_b, + wren_a, + wren_b, + q_a, + q_b); + + input [9:0] address_a; + input [9:0] address_b; + input clock_a; + input clock_b; + input [7:0] data_a; + input [7:0] data_b; + input wren_a; + input wren_b; + output [7:0] q_a; + output [7:0] q_b; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock_a; + tri0 wren_a; + tri0 wren_b; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [7:0] sub_wire0; + wire [7:0] sub_wire1; + wire [7:0] q_a = sub_wire0[7:0]; + wire [7:0] q_b = sub_wire1[7:0]; + + altsyncram altsyncram_component ( + .address_a (address_a), + .address_b (address_b), + .clock0 (clock_a), + .clock1 (clock_b), + .data_a (data_a), + .data_b (data_b), + .wren_a (wren_a), + .wren_b (wren_b), + .q_a (sub_wire0), + .q_b (sub_wire1), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .eccstatus (), + .rden_a (1'b1), + .rden_b (1'b1)); + defparam + altsyncram_component.address_reg_b = "CLOCK1", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.indata_reg_b = "CLOCK1", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 1024, + altsyncram_component.numwords_b = 1024, + altsyncram_component.operation_mode = "BIDIR_DUAL_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_a = "CLOCK0", + altsyncram_component.outdata_reg_b = "CLOCK1", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.ram_block_type = "M9K", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ", + altsyncram_component.widthad_a = 10, + altsyncram_component.widthad_b = 10, + altsyncram_component.width_a = 8, + altsyncram_component.width_b = 8, + altsyncram_component.width_byteena_a = 1, + altsyncram_component.width_byteena_b = 1, + altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1"; + + +endmodule + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module fg_sp_dulport_rom ( + address_a, + address_b, + clock_a, + clock_b, + q_a, + q_b); + + input [12:0] address_a; + input [12:0] address_b; + input clock_a; + input clock_b; + output [31:0] q_a; + output [31:0] q_b; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock_a; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [31:0] sub_wire0; + wire [31:0] sub_wire1; + wire sub_wire2 = 1'h0; + wire [31:0] sub_wire3 = 32'h0; + wire [31:0] q_b = sub_wire0[31:0]; + wire [31:0] q_a = sub_wire1[31:0]; + + altsyncram altsyncram_component ( + .clock0 (clock_a), + .wren_a (sub_wire2), + .address_b (address_b), + .clock1 (clock_b), + .data_b (sub_wire3), + .wren_b (sub_wire2), + .address_a (address_a), + .data_a (sub_wire3), + .q_b (sub_wire0), + .q_a (sub_wire1) + // synopsys translate_off + , + .aclr0 (), + .aclr1 (), + .addressstall_a (), + .addressstall_b (), + .byteena_a (), + .byteena_b (), + .clocken0 (), + .clocken1 (), + .clocken2 (), + .clocken3 (), + .eccstatus (), + .rden_a (), + .rden_b () + // synopsys translate_on + ); + defparam + altsyncram_component.address_reg_b = "CLOCK1", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.indata_reg_b = "CLOCK1", +`ifdef NO_PLI + altsyncram_component.init_file = "./rom/gfx1.rif" +`else + altsyncram_component.init_file = "./rom/gfx1.hex" +`endif +, + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 8192, + altsyncram_component.numwords_b = 8192, + altsyncram_component.operation_mode = "BIDIR_DUAL_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_a = "CLOCK0", + altsyncram_component.outdata_reg_b = "CLOCK1", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.ram_block_type = "M9K", + altsyncram_component.widthad_a = 13, + altsyncram_component.widthad_b = 13, + altsyncram_component.width_a = 32, + altsyncram_component.width_b = 32, + altsyncram_component.width_byteena_a = 1, + altsyncram_component.width_byteena_b = 1, + altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1"; + + +endmodule \ No newline at end of file diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_adec.v b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_adec.v similarity index 100% rename from Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_adec.v rename to Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_adec.v diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_bg.v b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_bg.v similarity index 100% rename from Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_bg.v rename to Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_bg.v diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_clkgen.v b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_clkgen.v similarity index 100% rename from Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_clkgen.v rename to Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_clkgen.v diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_cpumux.v b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_cpumux.v similarity index 100% rename from Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_cpumux.v rename to Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_cpumux.v diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_fg.v b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_fg.v similarity index 100% rename from Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_fg.v rename to Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_fg.v diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_input.v b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_input.v similarity index 100% rename from Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_input.v rename to Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_input.v diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_io_video.v b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_io_video.v similarity index 100% rename from Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_io_video.v rename to Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_io_video.v diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_irqgen.v b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_irqgen.v similarity index 100% rename from Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_irqgen.v rename to Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_irqgen.v diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_main.v b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_main.v similarity index 98% rename from Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_main.v rename to Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_main.v index e5ad660d..dab109fa 100644 --- a/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_main.v +++ b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_main.v @@ -1,5 +1,4 @@ -module ninjakun_main -( +module ninjakun_main( input RESET, input CLK24M, input CLK3M, diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_psg.v b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_psg.v similarity index 100% rename from Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_psg.v rename to Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_psg.v diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_sadec.v b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_sadec.v similarity index 100% rename from Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_sadec.v rename to Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_sadec.v diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_sp.v b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_sp.v similarity index 100% rename from Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_sp.v rename to Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_sp.v diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_top.v b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_top.v similarity index 100% rename from Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_top.v rename to Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_top.v diff --git a/Arcade_MiST/Nova2001_MiST/NinjaKun_MiST/rtl/ninjakun_video.v b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_video.v similarity index 100% rename from Arcade_MiST/Nova2001_MiST/NinjaKun_MiST/rtl/ninjakun_video.v rename to Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_video.v diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/pll.v b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/pll.v similarity index 98% rename from Arcade_MiST/NinjaKun_MiST/rtl/pll.v rename to Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/pll.v index d8ab4161..fd9fef10 100644 --- a/Arcade_MiST/NinjaKun_MiST/rtl/pll.v +++ b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/pll.v @@ -14,11 +14,11 @@ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // -// 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition +// 13.1.0 Build 162 10/23/2013 SJ Web Edition // ************************************************************ -//Copyright (C) 1991-2014 Altera Corporation +//Copyright (C) 1991-2013 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files from any of the foregoing @@ -179,7 +179,7 @@ endmodule // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" -// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" // Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" @@ -209,12 +209,12 @@ endmodule // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" // Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" -// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "16" // Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000" // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "6.00000000" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" diff --git a/Arcade_MiST/Nova2001_MiST/NinjaKun_MiST/rtl/rom/gfx1.hex b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/rom/gfx1.hex similarity index 100% rename from Arcade_MiST/Nova2001_MiST/NinjaKun_MiST/rtl/rom/gfx1.hex rename to Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/rom/gfx1.hex diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/rom/make_rom.bat b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/rom/make_rom.bat similarity index 53% rename from Arcade_MiST/NinjaKun_MiST/rtl/rom/make_rom.bat rename to Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/rom/make_rom.bat index f0b8bc52..488a426c 100644 --- a/Arcade_MiST/NinjaKun_MiST/rtl/rom/make_rom.bat +++ b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/rom/make_rom.bat @@ -3,10 +3,10 @@ copy /b ninja-5.7h + ninja-2.7b + ninja-3.7d + ninja-4.7e cpu2_rom.bin copy /b ninja-10.2c + ninja-11.2d + ninja-12.4c + ninja-13.4d bg.bin copy /b cpu1_rom.bin + cpu2_rom.bin + bg.bin NINJAKUN.ROM - -make_vhdl_prom.exe ninja-10.2c fg1_rom.vhd -make_vhdl_prom.exe ninja-11.2d fg2_rom.vhd -make_vhdl_prom.exe ninja-12.4c fg3_rom.vhd -make_vhdl_prom.exe ninja-13.4d fg4_rom.vhd +copy /b ninja-6.7n + ninja-7.7p + ninja-8.7s + ninja-9.7t fg.bin +make_vhdl_prom.exe ninja-6.7n fg1_rom.vhd +make_vhdl_prom.exe ninja-7.7p fg2_rom.vhd +make_vhdl_prom.exe ninja-8.7s fg3_rom.vhd +make_vhdl_prom.exe ninja-9.7t fg4_rom.vhd pause \ No newline at end of file diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/rom/make_vhdl_prom.exe b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/rom/make_vhdl_prom.exe similarity index 100% rename from Arcade_MiST/NinjaKun_MiST/rtl/rom/make_vhdl_prom.exe rename to Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/rom/make_vhdl_prom.exe diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/rom/ninjakun.zip b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/rom/ninjakun.zip similarity index 100% rename from Arcade_MiST/NinjaKun_MiST/rtl/rom/ninjakun.zip rename to Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/rom/ninjakun.zip diff --git a/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/rom/srec_cat.exe b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/rom/srec_cat.exe new file mode 100644 index 00000000..39c7b3c8 Binary files /dev/null and b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/rom/srec_cat.exe differ diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/sdram.sv b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/sdram.sv similarity index 100% rename from Arcade_MiST/NinjaKun_MiST/rtl/sdram.sv rename to Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/sdram.sv diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/spram.vhd b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/spram.vhd similarity index 100% rename from Arcade_MiST/NinjaKun_MiST/rtl/spram.vhd rename to Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/spram.vhd diff --git a/Arcade_MiST/NinjaKun_MiST/rtl/z80ip.v b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/z80ip.v similarity index 97% rename from Arcade_MiST/NinjaKun_MiST/rtl/z80ip.v rename to Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/z80ip.v index 8d55182f..922eaede 100644 --- a/Arcade_MiST/NinjaKun_MiST/rtl/z80ip.v +++ b/Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/z80ip.v @@ -20,7 +20,7 @@ wire nmireq = 0; wire i_mreq, i_iorq, i_rd, i_wr, i_rfsh; T80s cpu( - .CLK_n(~clk), + .CLK(~clk), .RESET_n(~reset_in), .INT_n(~intreq), .NMI_n(~nmireq), diff --git a/Arcade_MiST/Sega Zaxxon Hardware/README.txt b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/README.txt similarity index 100% rename from Arcade_MiST/Sega Zaxxon Hardware/README.txt rename to Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/README.txt diff --git a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/Release/ZAXXON.ROM b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/Release/ZAXXON.ROM new file mode 100644 index 00000000..df86695d Binary files /dev/null and b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/Release/ZAXXON.ROM differ diff --git a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/Release/Zaxxon.rbf b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/Release/Zaxxon.rbf new file mode 100644 index 00000000..53acfab0 Binary files /dev/null and b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/Release/Zaxxon.rbf differ diff --git a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon.qpf b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/Zaxxon.qpf similarity index 100% rename from Arcade_MiST/Sega Zaxxon Hardware/Zaxxon.qpf rename to Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/Zaxxon.qpf diff --git a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon.qsf b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/Zaxxon.qsf similarity index 97% rename from Arcade_MiST/Sega Zaxxon Hardware/Zaxxon.qsf rename to Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/Zaxxon.qsf index 6106b3c3..9cdc4d54 100644 --- a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon.qsf +++ b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/Zaxxon.qsf @@ -41,7 +41,7 @@ # ======================== set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL -set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" # Pin & Location Assignments @@ -215,13 +215,12 @@ set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_RO set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name ENABLE_SIGNALTAP OFF set_global_assignment -name USE_SIGNALTAP_FILE output_files/zaxx.stp -set_global_assignment -name VERILOG_FILE rtl/pll_mist.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/Zaxxon_MiST.sv set_global_assignment -name VHDL_FILE rtl/zaxxon.vhd +set_global_assignment -name VERILOG_FILE rtl/pll_mist.v set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv set_global_assignment -name VHDL_FILE rtl/dpram.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/Zaxxon_MiST.sv set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd -set_global_assignment -name QIP_FILE ../../common/mist/mist.qip -set_global_assignment -name QIP_FILE ../../common/CPU/T80/T80.qip -set_global_assignment -name SIGNALTAP_FILE output_files/zaxx.stp +set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip +set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon.sdc b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/Zaxxon.sdc similarity index 100% rename from Arcade_MiST/Sega Zaxxon Hardware/Zaxxon.sdc rename to Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/Zaxxon.sdc diff --git a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/clean.bat b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade_MiST/Sega Zaxxon Hardware/rtl/Zaxxon_MiST.sv b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/Zaxxon_MiST.sv similarity index 100% rename from Arcade_MiST/Sega Zaxxon Hardware/rtl/Zaxxon_MiST.sv rename to Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/Zaxxon_MiST.sv diff --git a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/build_id.tcl b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Sega Zaxxon Hardware/rtl/dpram.vhd b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/dpram.vhd similarity index 100% rename from Arcade_MiST/Sega Zaxxon Hardware/rtl/dpram.vhd rename to Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/dpram.vhd diff --git a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/gen_ram.vhd b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/gen_ram.vhd new file mode 100644 index 00000000..f1a95608 --- /dev/null +++ b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/gen_ram.vhd @@ -0,0 +1,84 @@ +-- ----------------------------------------------------------------------- +-- +-- Syntiac's generic VHDL support files. +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- +-- Modified April 2016 by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +-- Remove address register when writing +-- +-- ----------------------------------------------------------------------- +-- +-- gen_rwram.vhd +-- +-- ----------------------------------------------------------------------- +-- +-- generic ram. +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +entity gen_ram is + generic ( + dWidth : integer := 8; + aWidth : integer := 10 + ); + port ( + clk : in std_logic; + we : in std_logic; + addr : in std_logic_vector((aWidth-1) downto 0); + d : in std_logic_vector((dWidth-1) downto 0); + q : out std_logic_vector((dWidth-1) downto 0) + ); +end entity; + +-- ----------------------------------------------------------------------- + +architecture rtl of gen_ram is + subtype addressRange is integer range 0 to ((2**aWidth)-1); + type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0); + signal ram: ramDef; + + signal rAddrReg : std_logic_vector((aWidth-1) downto 0); + signal qReg : std_logic_vector((dWidth-1) downto 0); +begin +-- ----------------------------------------------------------------------- +-- Signals to entity interface +-- ----------------------------------------------------------------------- +-- q <= qReg; + +-- ----------------------------------------------------------------------- +-- Memory write +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if we = '1' then + ram(to_integer(unsigned(addr))) <= d; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Memory read +-- ----------------------------------------------------------------------- +process(clk) + begin + if rising_edge(clk) then +-- qReg <= ram(to_integer(unsigned(rAddrReg))); +-- rAddrReg <= addr; +---- qReg <= ram(to_integer(unsigned(addr))); + q <= ram(to_integer(unsigned(addr))); + end if; + end process; +--q <= ram(to_integer(unsigned(addr))); +end architecture; + diff --git a/Arcade_MiST/Sega Zaxxon Hardware/rtl/pll_mist.v b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/pll_mist.v similarity index 100% rename from Arcade_MiST/Sega Zaxxon Hardware/rtl/pll_mist.v rename to Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/pll_mist.v diff --git a/Arcade_MiST/Sega Zaxxon Hardware/rtl/sdram.sv b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/sdram.sv similarity index 100% rename from Arcade_MiST/Sega Zaxxon Hardware/rtl/sdram.sv rename to Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/sdram.sv diff --git a/Arcade_MiST/Sega Zaxxon Hardware/rtl/zaxxon.vhd b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/zaxxon.vhd similarity index 100% rename from Arcade_MiST/Sega Zaxxon Hardware/rtl/zaxxon.vhd rename to Arcade_MiST/Sega Zaxxon Hardware/Zaxxon_MiST/rtl/zaxxon.vhd diff --git a/common/mist/mist2.qip b/common/mist/mist2.qip deleted file mode 100644 index cf389ff2..00000000 --- a/common/mist/mist2.qip +++ /dev/null @@ -1,16 +0,0 @@ -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) mist.vhd] -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) user_io.v] -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) data_io.v] -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) mist_video.v] -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scandoubler.v] -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) osd.v] -set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) rgb2ypbpr.sv] -set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) cofi.sv] -set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sdram.sv] ---set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) dpram.vhd] ---set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) spram.vhd] ---set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) sprom.vhd] ---set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) dac.vhd] - - -