diff --git a/Arcade_MiST/Midway MCR 1/rtl/sdram.sv b/Arcade_MiST/Midway MCR 1/rtl/sdram.sv
index bc78584d..e99f4621 100644
--- a/Arcade_MiST/Midway MCR 1/rtl/sdram.sv	
+++ b/Arcade_MiST/Midway MCR 1/rtl/sdram.sv	
@@ -61,6 +61,8 @@ module sdram (
 	output reg [15:0] snd_q
 );
 
+parameter  MHZ = 16'd80; // 80 MHz default clock, set it to proper value to calculate refresh rate
+
 localparam RASCAS_DELAY   = 3'd2;   // tRCD=20ns -> 2 cycles@<100MHz
 localparam BURST_LENGTH   = 3'b000; // 000=1, 001=2, 010=4, 011=8
 localparam ACCESS_TYPE    = 1'b0;   // 0=sequential, 1=interleaved
@@ -70,8 +72,8 @@ localparam NO_WRITE_BURST = 1'b1;   // 0= write burst enabled, 1=only single acc
 
 localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH}; 
 
-// 64ms/8192 rows = 7.8us -> 842 cycles@108MHz
-localparam RFRSH_CYCLES = 10'd842;
+// 64ms/8192 rows = 7.8us
+localparam RFRSH_CYCLES = 16'd78*MHZ/4'd10;
 
 // ---------------------------------------------------------------------
 // ------------------------ cycle state machine ------------------------
@@ -162,6 +164,8 @@ localparam PORT_SND   = 2'd1;
 
 reg  [2:0] next_port[2];
 reg  [2:0] port[2];
+reg        port1_state;
+reg        port2_state;
 
 reg        refresh;
 reg [10:0] refresh_cnt;
@@ -172,7 +176,7 @@ always @(*) begin
 	if (refresh) begin
 		next_port[0] = PORT_NONE;
 		addr_latch_next[0] = addr_latch[0];
-	end else if (port1_req ^ port1_ack) begin
+	end else if (port1_req ^ port1_state) begin
 		next_port[0] = PORT_REQ;
 		addr_latch_next[0] = { 1'b0, port1_a };
 	end else if (cpu1_addr != addr_last[PORT_CPU1]) begin
@@ -186,7 +190,7 @@ end
 
 // PORT2: bank 2,3
 always @(*) begin
-	if (port2_req ^ port2_ack) begin
+	if (port2_req ^ port2_state) begin
 		next_port[1] = PORT_REQ;
 		addr_latch_next[1] = { 1'b1, port2_a };
 	end else if (snd_addr != addr_last2[PORT_SND]) begin
@@ -243,6 +247,7 @@ always @(posedge clk) begin
 					{ oe_latch[0], we_latch[0] } <= { ~port1_we, port1_we };
 					ds[0] <= port1_ds;
 					din_latch[0] <= port1_d;
+					port1_state <= port1_req;
 				end else begin
 					{ oe_latch[0], we_latch[0] } <= 2'b10;
 					ds[0] <= 2'b11;
@@ -266,6 +271,7 @@ always @(posedge clk) begin
 					{ oe_latch[1], we_latch[1] } <= { ~port2_we, port2_we };
 					ds[1] <= port2_ds;
 					din_latch[1] <= port2_d;
+					port2_state <= port2_req;
 				end else begin
 					{ oe_latch[1], we_latch[1] } <= 2'b10;
 					ds[1] <= 2'b11;