From 6d2e39a333250a2fe9f9d6edbe4def62a2548083 Mon Sep 17 00:00:00 2001 From: Gyorgy Szombathelyi Date: Thu, 22 Jul 2021 11:06:33 +0200 Subject: [PATCH] Update T48 --- common/CPU/t48/README | 38 +- common/CPU/t48/T48.qip | 3 - common/CPU/t48/alu-c.vhd | 2 +- common/CPU/t48/alu.vhd | 36 +- common/CPU/t48/alu_pack-p.vhd | 18 +- common/CPU/t48/bus_mux-c.vhd | 2 +- common/CPU/t48/bus_mux.vhd | 15 +- common/CPU/t48/clock_ctrl-c.vhd | 2 +- common/CPU/t48/clock_ctrl.vhd | 54 +-- common/CPU/t48/cond_branch-c.vhd | 2 +- common/CPU/t48/cond_branch.vhd | 18 +- common/CPU/t48/cond_branch_pack-p.vhd | 15 +- common/CPU/t48/db_bus-c.vhd | 2 +- common/CPU/t48/db_bus.vhd | 25 +- common/CPU/t48/decoder-c.vhd | 6 +- common/CPU/t48/decoder.vhd | 298 +++++------- common/CPU/t48/decoder_pack-p.vhd | 368 ++++++++++++++- common/CPU/t48/dmem_ctrl-c.vhd | 2 +- common/CPU/t48/dmem_ctrl.vhd | 24 +- common/CPU/t48/dmem_ctrl_pack-p.vhd | 15 +- common/CPU/t48/i8039.qip | 26 ++ common/CPU/t48/int-c.vhd | 2 +- common/CPU/t48/int.vhd | 38 +- common/CPU/t48/opc_decoder-c.vhd | 23 - common/CPU/t48/opc_decoder.vhd | 182 -------- common/CPU/t48/opc_table-c.vhd | 18 - common/CPU/t48/opc_table.vhd | 425 ------------------ common/CPU/t48/p1-c.vhd | 2 +- common/CPU/t48/p1.vhd | 24 +- common/CPU/t48/p2-c.vhd | 2 +- common/CPU/t48/p2.vhd | 39 +- common/CPU/t48/pmem_ctrl-c.vhd | 2 +- common/CPU/t48/pmem_ctrl.vhd | 25 +- common/CPU/t48/pmem_ctrl_pack-p.vhd | 15 +- common/CPU/t48/psw-c.vhd | 2 +- common/CPU/t48/psw.vhd | 33 +- common/CPU/t48/syn_ram-e.vhd | 73 --- common/CPU/t48/system/generic_ram_ena-c.vhd | 2 +- common/CPU/t48/system/generic_ram_ena.vhd | 2 +- common/CPU/t48/system/t48_rom-e.vhd | 15 +- common/CPU/t48/system/t48_rom-struct-a.vhd | 21 +- common/CPU/t48/system/t48_rom-struct-c.vhd | 2 +- .../CPU/t48/system/t48_system_comp_pack-p.vhd | 2 +- common/CPU/t48/system/t49_rom-e.vhd | 15 +- common/CPU/t48/system/t49_rom-struct-a.vhd | 21 +- common/CPU/t48/system/t49_rom-struct-c.vhd | 2 +- common/CPU/t48/system/t8039-c.vhd | 2 +- common/CPU/t48/system/t8039.vhd | 25 +- common/CPU/t48/system/t8039_notri-c.vhd | 2 +- common/CPU/t48/system/t8039_notri.vhd | 25 +- common/CPU/t48/system/t8048-c.vhd | 2 +- common/CPU/t48/system/t8048.vhd | 47 +- common/CPU/t48/system/t8048_notri-c.vhd | 2 +- common/CPU/t48/system/t8048_notri.vhd | 29 +- common/CPU/t48/system/t8050_wb-c.vhd | 2 +- common/CPU/t48/system/t8050_wb.vhd | 25 +- common/CPU/t48/system/wb_master-c.vhd | 2 +- common/CPU/t48/system/wb_master.vhd | 27 +- common/CPU/t48/t48_comp_pack-p.vhd | 27 +- common/CPU/t48/t48_core-c.vhd | 2 +- common/CPU/t48/t48_core.vhd | 50 +-- common/CPU/t48/t48_core_comp_pack-p.vhd | 2 +- common/CPU/t48/t48_pack-p.vhd | 2 +- common/CPU/t48/t48_tb_pack-p.vhd | 2 +- common/CPU/t48/t8243/t8243-c.vhd | 19 + common/CPU/t48/t8243/t8243.vhd | 137 ++++++ common/CPU/t48/t8243/t8243_async_notri-c.vhd | 19 + common/CPU/t48/t8243/t8243_async_notri.vhd | 124 +++++ common/CPU/t48/t8243/t8243_comp_pack-p.vhd | 132 ++++++ common/CPU/t48/t8243/t8243_core-c.vhd | 14 + common/CPU/t48/t8243/t8243_core.vhd | 291 ++++++++++++ common/CPU/t48/t8243/t8243_sync_notri-c.vhd | 19 + common/CPU/t48/t8243/t8243_sync_notri.vhd | 153 +++++++ common/CPU/t48/timer-c.vhd | 2 +- common/CPU/t48/timer.vhd | 34 +- 75 files changed, 1494 insertions(+), 1683 deletions(-) create mode 100644 common/CPU/t48/i8039.qip delete mode 100644 common/CPU/t48/opc_decoder-c.vhd delete mode 100644 common/CPU/t48/opc_decoder.vhd delete mode 100644 common/CPU/t48/opc_table-c.vhd delete mode 100644 common/CPU/t48/opc_table.vhd delete mode 100644 common/CPU/t48/syn_ram-e.vhd create mode 100644 common/CPU/t48/t8243/t8243-c.vhd create mode 100644 common/CPU/t48/t8243/t8243.vhd create mode 100644 common/CPU/t48/t8243/t8243_async_notri-c.vhd create mode 100644 common/CPU/t48/t8243/t8243_async_notri.vhd create mode 100644 common/CPU/t48/t8243/t8243_comp_pack-p.vhd create mode 100644 common/CPU/t48/t8243/t8243_core-c.vhd create mode 100644 common/CPU/t48/t8243/t8243_core.vhd create mode 100644 common/CPU/t48/t8243/t8243_sync_notri-c.vhd create mode 100644 common/CPU/t48/t8243/t8243_sync_notri.vhd diff --git a/common/CPU/t48/README b/common/CPU/t48/README index eaf9b150..a516f561 100644 --- a/common/CPU/t48/README +++ b/common/CPU/t48/README @@ -1,8 +1,7 @@ README for the T48 uController project ====================================== -Version: $Date: 2006/07/16 01:59:23 $ -$Name: $ +Version: $Id: README 295 2009-04-01 19:32:48Z arniml $ Introduction @@ -92,6 +91,14 @@ t48 | | | \-- rtl_sim : Directory for running simulations. | + +-- syn + | | + | \-- t8048 : T8048 toplevel example synthesis. + | | + | +-- b5x300 : for SpartanIIe 300. + | | + | \-- jopcyc : for Cyclone EP1C12. + | \-- sw : General purpose scripts and files. | +-- i8039emu : An MCS-48 emulator written in C. @@ -224,7 +231,9 @@ required ROM files for internal and external program ROM. The target 'simu' copies these files automatically to the simulation directory. So most likely, for running a test case or any other software, you will want to issue: -$ make -f VERIF_DIR/include/Makefile.cell simu clean +$ make -f VERIF_DIR/include/Makefile.cell all clean + +The 'all' target generates hex files for all supported testbenches. The only supported assembler is Alfred Arnold's macroassembler AS. See @@ -261,3 +270,26 @@ script. For each test cell, it steps through the sequence It is highly recommended to redirect the output of run_regression.pl into a file. Otherwise, analyzing the messages related to each test cell is almost impossible. + + +FPGA Implementation +------------------- + +All of the design files contain pure RTL code. Also the RAM for the data +memory is described by generic RTL code. It should be translated automatically +by the tool chain to a technology specific RAM macro. + +There is a generic method for the program memory ROM as well, although this +project uses a flow where hex-files are loaded by lpm_rom.vhd as the default +method. Convert the ROM image to an RTL VHDL file with one of the two +following commands (either from hex or bin format): + + $ hex2rom -b [rom image file] rom_t48 10l8s > rom_t48.vhd + $ hex2rom -b [rom image file] rom_t49 11l8s > rom_t49.vhd + +The option -b specifies that [rom image file] contains binary data. Skip this +option to process a file in hex format. + +These resulting RTL representations are instantiated by t48_rom-struct-a.vhd +and t49_rom-struct-a.vhd. Altera and Xilinx design tools will detect and +extract the ROM and turn it into a memory macro. diff --git a/common/CPU/t48/T48.qip b/common/CPU/t48/T48.qip index f6fc09da..ccbecd7c 100644 --- a/common/CPU/t48/T48.qip +++ b/common/CPU/t48/T48.qip @@ -4,14 +4,11 @@ set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) t48_pack-p set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) t48_core_comp_pack-p.vhd ] set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) t48_core.vhd ] set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) t48_comp_pack-p.vhd ] -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) syn_ram-e.vhd ] set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) psw.vhd ] set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) pmem_ctrl_pack-p.vhd ] set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) pmem_ctrl.vhd ] set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) p2.vhd ] set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) p1.vhd ] -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) opc_table.vhd ] -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) opc_decoder.vhd ] set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) int.vhd ] set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) dmem_ctrl_pack-p.vhd ] set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) dmem_ctrl.vhd ] diff --git a/common/CPU/t48/alu-c.vhd b/common/CPU/t48/alu-c.vhd index 93fe8528..4cfa70a9 100644 --- a/common/CPU/t48/alu-c.vhd +++ b/common/CPU/t48/alu-c.vhd @@ -3,7 +3,7 @@ -- The Arithmetic Logic Unit (ALU). -- It contains the ALU core plus the Accumulator and the Temp Reg. -- --- $Id: alu-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ +-- $Id: alu-c.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) -- diff --git a/common/CPU/t48/alu.vhd b/common/CPU/t48/alu.vhd index 140bd4c8..7bf8c4cb 100644 --- a/common/CPU/t48/alu.vhd +++ b/common/CPU/t48/alu.vhd @@ -3,7 +3,7 @@ -- The Arithmetic Logic Unit (ALU). -- It contains the ALU core plus the Accumulator and the Temp Reg. -- --- $Id: alu.vhd,v 1.9 2005/06/11 10:08:43 arniml Exp $ +-- $Id: alu.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) -- @@ -413,37 +413,3 @@ begin (others => bus_idle_level_c); end rtl; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: alu.vhd,v $ --- Revision 1.9 2005/06/11 10:08:43 arniml --- introduce prefix 't48_' for all packages, entities and configurations --- --- Revision 1.8 2004/04/24 23:43:56 arniml --- move from std_logic_arith to numeric_std --- --- Revision 1.7 2004/04/07 22:09:03 arniml --- remove unused signals --- --- Revision 1.6 2004/04/07 20:56:23 arniml --- default assignment for aux_carry_o --- --- Revision 1.5 2004/04/06 20:21:53 arniml --- fix sensitivity list --- --- Revision 1.4 2004/04/06 18:10:41 arniml --- rework adder and force resource sharing between ADD, INC and DEC --- --- Revision 1.3 2004/04/04 14:18:52 arniml --- add measures to implement XCHD --- --- Revision 1.2 2004/03/28 21:08:51 arniml --- support for DA instruction --- --- Revision 1.1 2004/03/23 21:31:52 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/common/CPU/t48/alu_pack-p.vhd b/common/CPU/t48/alu_pack-p.vhd index 71c1e4ba..7794cd4c 100644 --- a/common/CPU/t48/alu_pack-p.vhd +++ b/common/CPU/t48/alu_pack-p.vhd @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------- -- --- $Id: alu_pack-p.vhd,v 1.3 2005/06/11 10:08:43 arniml Exp $ +-- $Id: alu_pack-p.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) -- @@ -33,19 +33,3 @@ package t48_alu_pack is subtype alu_operand_t is std_logic_vector(word_width_c downto 0); end t48_alu_pack; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: alu_pack-p.vhd,v $ --- Revision 1.3 2005/06/11 10:08:43 arniml --- introduce prefix 't48_' for all packages, entities and configurations --- --- Revision 1.2 2004/04/04 14:18:53 arniml --- add measures to implement XCHD --- --- Revision 1.1 2004/03/23 21:31:52 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/common/CPU/t48/bus_mux-c.vhd b/common/CPU/t48/bus_mux-c.vhd index ccec86af..66209210 100644 --- a/common/CPU/t48/bus_mux-c.vhd +++ b/common/CPU/t48/bus_mux-c.vhd @@ -3,7 +3,7 @@ -- The T48 Bus Connector. -- Multiplexes all drivers of the T48 bus. -- --- $Id: bus_mux-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ +-- $Id: bus_mux-c.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) -- diff --git a/common/CPU/t48/bus_mux.vhd b/common/CPU/t48/bus_mux.vhd index 8d09b331..2d1da4b3 100644 --- a/common/CPU/t48/bus_mux.vhd +++ b/common/CPU/t48/bus_mux.vhd @@ -3,7 +3,7 @@ -- The T48 Bus Connector. -- Multiplexes all drivers of the T48 bus. -- --- $Id: bus_mux.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ +-- $Id: bus_mux.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) -- @@ -98,16 +98,3 @@ begin end generate; end rtl; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: bus_mux.vhd,v $ --- Revision 1.2 2005/06/11 10:08:43 arniml --- introduce prefix 't48_' for all packages, entities and configurations --- --- Revision 1.1 2004/03/23 21:31:52 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/common/CPU/t48/clock_ctrl-c.vhd b/common/CPU/t48/clock_ctrl-c.vhd index b36b70eb..a061baa0 100644 --- a/common/CPU/t48/clock_ctrl-c.vhd +++ b/common/CPU/t48/clock_ctrl-c.vhd @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------- -- --- $Id: clock_ctrl-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ +-- $Id: clock_ctrl-c.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- The clock control unit. -- diff --git a/common/CPU/t48/clock_ctrl.vhd b/common/CPU/t48/clock_ctrl.vhd index 3fd967ee..e6d0ef7a 100644 --- a/common/CPU/t48/clock_ctrl.vhd +++ b/common/CPU/t48/clock_ctrl.vhd @@ -3,7 +3,7 @@ -- The Clock Control unit. -- Clock States and Machine Cycles are generated here. -- --- $Id: clock_ctrl.vhd,v 1.12 2006/07/14 01:04:35 arniml Exp $ +-- $Id: clock_ctrl.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2004, 2005, Arnim Laeuger (arniml@opencores.org) -- @@ -395,55 +395,3 @@ begin wr_o <= wr_q; end rtl; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: clock_ctrl.vhd,v $ --- Revision 1.12 2006/07/14 01:04:35 arniml --- Fix bug report --- "Deassertion of PROG too early" --- PROG is deasserted at end of XTAL3 now --- --- Revision 1.11 2006/06/20 00:46:38 arniml --- new input xtal_en_i gates xtal_i base clock --- --- Revision 1.10 2005/11/01 21:24:21 arniml --- * shift assertion of ALE and PROG to xtal3 --- * correct change of revision 1.8 --- --- Revision 1.9 2005/06/11 10:08:43 arniml --- introduce prefix 't48_' for all packages, entities and configurations --- --- Revision 1.8 2005/06/09 22:15:10 arniml --- Use en_clk_i instead of xtal3_s for generation of external signals. --- This is required when the core runs with full xtal clock instead --- of xtal/3 (xtal_div_3_g = 0). --- --- Revision 1.7 2005/05/04 20:12:36 arniml --- Fix bug report: --- "Wrong clock applied to T0" --- t0_o is generated inside clock_ctrl with a separate flip-flop running --- with xtal_i --- --- Revision 1.6 2004/10/25 20:31:12 arniml --- remove PROG and end of XTAL2, see comment for details --- --- Revision 1.5 2004/10/25 19:35:41 arniml --- deassert rd_q, wr_q and prog_q at end of XTAL3 --- --- Revision 1.4 2004/04/24 23:44:25 arniml --- move from std_logic_arith to numeric_std --- --- Revision 1.3 2004/04/18 18:56:23 arniml --- reset machine state to MSTATE3 to allow proper instruction fetch --- after reset --- --- Revision 1.2 2004/03/28 12:55:06 arniml --- move code for PROG out of if-branch for xtal3_s --- --- Revision 1.1 2004/03/23 21:31:52 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/common/CPU/t48/cond_branch-c.vhd b/common/CPU/t48/cond_branch-c.vhd index 15a0b7e7..fd9e7d6b 100644 --- a/common/CPU/t48/cond_branch-c.vhd +++ b/common/CPU/t48/cond_branch-c.vhd @@ -3,7 +3,7 @@ -- The Conditional Branch Logic unit. -- Decisions whether to take a jump or not are made here. -- --- $Id: cond_branch-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ +-- $Id: cond_branch-c.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) -- diff --git a/common/CPU/t48/cond_branch.vhd b/common/CPU/t48/cond_branch.vhd index a97f871c..11e2f1dc 100644 --- a/common/CPU/t48/cond_branch.vhd +++ b/common/CPU/t48/cond_branch.vhd @@ -3,7 +3,7 @@ -- The Conditional Branch Logic unit. -- Decisions whether to take a jump or not are made here. -- --- $Id: cond_branch.vhd,v 1.3 2005/06/11 10:08:43 arniml Exp $ +-- $Id: cond_branch.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) -- @@ -199,19 +199,3 @@ begin take_branch_o <= take_branch_q; end rtl; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: cond_branch.vhd,v $ --- Revision 1.3 2005/06/11 10:08:43 arniml --- introduce prefix 't48_' for all packages, entities and configurations --- --- Revision 1.2 2004/04/24 23:44:25 arniml --- move from std_logic_arith to numeric_std --- --- Revision 1.1 2004/03/23 21:31:52 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/common/CPU/t48/cond_branch_pack-p.vhd b/common/CPU/t48/cond_branch_pack-p.vhd index e6a029f3..74f0cdf8 100644 --- a/common/CPU/t48/cond_branch_pack-p.vhd +++ b/common/CPU/t48/cond_branch_pack-p.vhd @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------- -- --- $Id: cond_branch_pack-p.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ +-- $Id: cond_branch_pack-p.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) -- @@ -26,16 +26,3 @@ package t48_cond_branch_pack is subtype comp_value_t is std_logic_vector(2 downto 0); end t48_cond_branch_pack; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: cond_branch_pack-p.vhd,v $ --- Revision 1.2 2005/06/11 10:08:43 arniml --- introduce prefix 't48_' for all packages, entities and configurations --- --- Revision 1.1 2004/03/23 21:31:52 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/common/CPU/t48/db_bus-c.vhd b/common/CPU/t48/db_bus-c.vhd index 2047eb9f..b47532bf 100644 --- a/common/CPU/t48/db_bus-c.vhd +++ b/common/CPU/t48/db_bus-c.vhd @@ -3,7 +3,7 @@ -- The BUS unit. -- Implements the BUS port logic. -- --- $Id: db_bus-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ +-- $Id: db_bus-c.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) -- diff --git a/common/CPU/t48/db_bus.vhd b/common/CPU/t48/db_bus.vhd index 54e6b199..746df29d 100644 --- a/common/CPU/t48/db_bus.vhd +++ b/common/CPU/t48/db_bus.vhd @@ -3,7 +3,7 @@ -- The BUS unit. -- Implements the BUS port logic. -- --- $Id: db_bus.vhd,v 1.5 2005/06/11 10:08:43 arniml Exp $ +-- $Id: db_bus.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) -- @@ -144,26 +144,3 @@ begin db_i; end rtl; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: db_bus.vhd,v $ --- Revision 1.5 2005/06/11 10:08:43 arniml --- introduce prefix 't48_' for all packages, entities and configurations --- --- Revision 1.4 2005/06/09 22:16:26 arniml --- Implement db_dir_o glitch-safe --- --- Revision 1.3 2004/10/25 20:30:18 arniml --- delay db_dir_o by one machine cycle --- this fixes the timing relation between BUS data and WR' --- --- Revision 1.2 2004/04/04 14:15:45 arniml --- add dump_compare support --- --- Revision 1.1 2004/03/23 21:31:52 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/common/CPU/t48/decoder-c.vhd b/common/CPU/t48/decoder-c.vhd index efcebaf0..4ad089d0 100644 --- a/common/CPU/t48/decoder-c.vhd +++ b/common/CPU/t48/decoder-c.vhd @@ -3,7 +3,7 @@ -- The Decoder unit. -- It decodes the instruction opcodes and executes them. -- --- $Id: decoder-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ +-- $Id: decoder-c.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) -- @@ -15,10 +15,6 @@ configuration t48_decoder_rtl_c0 of t48_decoder is for rtl - for opc_decoder_b: t48_opc_decoder - use configuration work.t48_opc_decoder_rtl_c0; - end for; - for int_b: t48_int use configuration work.t48_int_rtl_c0; end for; diff --git a/common/CPU/t48/decoder.vhd b/common/CPU/t48/decoder.vhd index 49dc2b3f..d7627ca4 100644 --- a/common/CPU/t48/decoder.vhd +++ b/common/CPU/t48/decoder.vhd @@ -3,7 +3,7 @@ -- The Decoder unit. -- It decodes the instruction opcodes and executes them. -- --- $Id: decoder.vhd,v 1.25 2006/06/20 00:46:03 arniml Exp $ +-- $Id: decoder.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) -- @@ -164,7 +164,6 @@ use work.t48_pack.all; use work.t48_alu_pack.all; use work.t48_decoder_pack.all; -use work.t48_comp_pack.t48_opc_decoder; use work.t48_comp_pack.t48_int; -- pragma translate_off @@ -180,7 +179,7 @@ architecture rtl of t48_decoder is signal opc_multi_cycle_s : boolean; signal opc_read_bus_s : boolean; signal opc_inj_int_s : boolean; - signal opc_opcode_s : word_t; + signal opc_opcode_q : word_t; signal opc_mnemonic_s : mnemonic_t; signal last_cycle_s : boolean; @@ -236,6 +235,10 @@ architecture rtl of t48_decoder is signal int_pending_s : boolean; signal int_in_progress_s : boolean; + -- the mnemonic + signal mnemonic_rec_s : mnemonic_rec_t; + signal mnemonic_q : mnemonic_t; + -- pragma translate_off signal istrobe_res_q : std_logic; signal istrobe_q : std_logic; @@ -244,24 +247,59 @@ architecture rtl of t48_decoder is begin + -- pragma translate_off + + -- Register Mnemonic -------------------------------------------------------- + assert (register_mnemonic_g = 1) or (register_mnemonic_g = 0) + report "register_mnemonic_g must be either 1 or 0!" + severity failure; + + -- pragma translate_on + + ----------------------------------------------------------------------------- -- Opcode Decoder + -- + mnemonic_rec_s <= decode_opcode_f(opcode => opc_opcode_q); + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process opc_regs + -- + -- Purpose: + -- Implements the opcode and mnemonic registers. + -- + opc_regs: process (res_i, clk_i) + begin + if res_i = res_active_c then + opc_opcode_q <= (others => '0'); -- NOP + mnemonic_q <= MN_NOP; + + elsif clk_i'event and clk_i = clk_active_c then + if en_clk_i then + + if opc_read_bus_s then + opc_opcode_q <= data_i; + elsif opc_inj_int_s then + opc_opcode_q <= "00010100"; + else + mnemonic_q <= mnemonic_rec_s.mnemonic; + end if; + + end if; + + end if; + + end process opc_regs; + -- + opc_multi_cycle_s <= mnemonic_rec_s.multi_cycle; + opc_mnemonic_s <= mnemonic_q + when register_mnemonic_g = 1 else + mnemonic_rec_s.mnemonic; + -- ----------------------------------------------------------------------------- - opc_decoder_b : t48_opc_decoder - generic map ( - register_mnemonic_g => register_mnemonic_g - ) - port map ( - clk_i => clk_i, - res_i => res_i, - en_clk_i => en_clk_i, - data_i => data_i, - read_bus_i => opc_read_bus_s, - inj_int_i => opc_inj_int_s, - opcode_o => opc_opcode_s, - mnemonic_o => opc_mnemonic_s, - multi_cycle_o => opc_multi_cycle_s - ); ----------------------------------------------------------------------------- @@ -420,7 +458,7 @@ begin clk_mstate_i, clk_second_cycle_i, cnd_take_branch_i, - opc_opcode_s, + opc_opcode_q, opc_mnemonic_s, psw_carry_i, psw_f0_i, @@ -433,7 +471,7 @@ begin procedure address_indirect_3_f is begin -- apply dmem address from selected register for indirect mode - if opc_opcode_s(3) = '0' or enable_quartus_bugfix_c then + if opc_opcode_q(3) = '0' or enable_quartus_bugfix_c then dm_read_dmem_o <= true; dm_write_dmem_addr_o <= true; dm_addr_type_o <= DM_PLAIN; @@ -508,7 +546,7 @@ begin clk_assert_wr_o <= false; cnd_branch_cond_o <= COND_ON_BIT; cnd_compute_take_o <= false; - cnd_comp_value_o <= opc_opcode_s(7 downto 5); + cnd_comp_value_o <= opc_opcode_q(7 downto 5); dm_addr_type_o <= DM_REG; tim_read_timer_o <= false; tim_write_timer_o <= false; @@ -554,10 +592,10 @@ begin -- prepare potential register indirect address mode if not clk_second_cycle_i and clk_mstate_i = MSTATE2 then data_s <= (others => '0'); - if opc_opcode_s(3) = '1' then - data_s(2 downto 0) <= opc_opcode_s(2 downto 0); + if opc_opcode_q(3) = '1' then + data_s(2 downto 0) <= opc_opcode_q(2 downto 0); else - data_s(2 downto 0) <= "00" & opc_opcode_s(0); + data_s(2 downto 0) <= "00" & opc_opcode_q(0); end if; read_dec_s <= true; @@ -573,7 +611,7 @@ begin -- read RAM once for indirect address mode when MSTATE3 => if not enable_quartus_bugfix_c or - opc_opcode_s(3) = '0' then + opc_opcode_q(3) = '0' then address_indirect_3_f; end if; @@ -585,7 +623,7 @@ begin when MSTATE5 => and_or_xor_add_5_f(alu_op => ALU_ADD); - if opc_opcode_s(4) = '1' then + if opc_opcode_q(4) = '1' then alu_use_carry_o <= true; end if; @@ -612,7 +650,7 @@ begin when MSTATE3 => and_or_xor_add_5_f(alu_op => ALU_ADD); - if opc_opcode_s(4) = '1' then + if opc_opcode_q(4) = '1' then alu_use_carry_o <= true; end if; @@ -633,7 +671,7 @@ begin -- read RAM once for indirect address mode when MSTATE3 => if not enable_quartus_bugfix_c or - opc_opcode_s(3) = '0' then + opc_opcode_q(3) = '0' then address_indirect_3_f; end if; @@ -678,9 +716,9 @@ begin if not clk_second_cycle_i then -- read port to Temp Reg if clk_mstate_i = MSTATE5 then - if opc_opcode_s(1 downto 0) = "00" then + if opc_opcode_q(1 downto 0) = "00" then add_read_bus_s <= true; - elsif opc_opcode_s(1) = '0' then + elsif opc_opcode_q(1) = '0' then p1_read_p1_o <= true; p1_read_reg_o <= true; else @@ -709,9 +747,9 @@ begin alu_op_o <= ALU_AND; alu_read_alu_o <= true; - if opc_opcode_s(1 downto 0) = "00" then + if opc_opcode_q(1 downto 0) = "00" then bus_write_bus_o <= true; - elsif opc_opcode_s(1) = '0' then + elsif opc_opcode_q(1) = '0' then p1_write_p1_o <= true; else p2_write_p2_o <= true; @@ -786,7 +824,7 @@ begin read_dec_s <= true; if not int_pending_s then -- store high part of target address in Program Counter - data_s <= "0000" & mb_v & opc_opcode_s(7 downto 5); + data_s <= "0000" & mb_v & opc_opcode_q(7 downto 5); else -- apply high part of vector address manually data_s <= (others => '0'); @@ -821,7 +859,7 @@ begin when MN_CLR_F => -- store 0 to selected flag if clk_mstate_i = MSTATE3 then - if opc_opcode_s(5) = '0' then + if opc_opcode_q(5) = '0' then psw_special_data_o <= '0'; psw_write_f0_o <= true; else @@ -851,7 +889,7 @@ begin when MN_CPL_f => -- write inverse of selected flag back to flag if clk_mstate_i = MSTATE3 then - if opc_opcode_s(5) = '0' then + if opc_opcode_q(5) = '0' then psw_special_data_o <= not psw_f0_i; psw_write_f0_o <= true; else @@ -906,7 +944,7 @@ begin case clk_mstate_i is when MSTATE4 => -- DEC Rr: store data from RAM to shadow Accumulator - if opc_opcode_s(6) = '1' then + if opc_opcode_q(6) = '1' then dm_read_dmem_o <= true; alu_write_shadow_o <= true; end if; @@ -915,7 +953,7 @@ begin alu_op_o <= ALU_DEC; alu_read_alu_o <= true; - if opc_opcode_s(6) = '0' then + if opc_opcode_q(6) = '0' then -- write DEC of Accumulator to Accumulator alu_write_accu_o <= true; else @@ -931,7 +969,7 @@ begin -- Mnemonic DIS_EN_I ---------------------------------------------------- when MN_DIS_EN_I => if clk_mstate_i = MSTATE3 then - if opc_opcode_s(4) = '1' then + if opc_opcode_q(4) = '1' then dis_i_s <= true; else en_i_s <= true; @@ -941,7 +979,7 @@ begin -- Mnemonic DIS_EN_TCNTI ------------------------------------------------ when MN_DIS_EN_TCNTI => if clk_mstate_i = MSTATE3 then - if opc_opcode_s(4) = '1' then + if opc_opcode_q(4) = '1' then dis_tcnti_s <= true; else en_tcnti_s <= true; @@ -996,7 +1034,7 @@ begin if clk_second_cycle_i and clk_mstate_i = MSTATE2 then alu_write_accu_o <= true; - if opc_opcode_s(1) = '0' then + if opc_opcode_q(1) = '0' then p1_read_p1_o <= true; else p2_read_p2_o <= true; @@ -1020,13 +1058,13 @@ begin -- read RAM once for indirect address mode when MSTATE3 => if not enable_quartus_bugfix_c or - opc_opcode_s(3) = '0' then + opc_opcode_q(3) = '0' then address_indirect_3_f; end if; when MSTATE4 => -- INC Rr; INC @ Rr: store data from RAM to shadow Accumulator - if opc_opcode_s(3 downto 2) /= "01" then + if opc_opcode_q(3 downto 2) /= "01" then dm_read_dmem_o <= true; alu_write_shadow_o <= true; end if; @@ -1035,7 +1073,7 @@ begin alu_op_o <= ALU_INC; alu_read_alu_o <= true; - if opc_opcode_s(3 downto 2) = "01" then + if opc_opcode_q(3 downto 2) = "01" then -- write INC output of ALU to Accumulator alu_write_accu_o <= true; else @@ -1079,7 +1117,7 @@ begin -- start branch calculation if clk_mstate_i = MSTATE3 then cnd_compute_take_o <= true; - cnd_comp_value_o(0) <= opc_opcode_s(4); + cnd_comp_value_o(0) <= opc_opcode_q(4); end if; else @@ -1099,7 +1137,7 @@ begin -- start branch calculation if clk_mstate_i = MSTATE3 then cnd_compute_take_o <= true; - if opc_opcode_s(7) = '1' then + if opc_opcode_q(7) = '1' then -- JF0 cnd_branch_cond_o <= COND_F0; else @@ -1132,7 +1170,7 @@ begin -- store high part of target address in Program Counter when MSTATE2 => - data_s <= "0000" & mb_v & opc_opcode_s(7 downto 5); + data_s <= "0000" & mb_v & opc_opcode_q(7 downto 5); read_dec_s <= true; pm_write_pch_o <= true; @@ -1187,7 +1225,7 @@ begin -- Mnemonic JT ---------------------------------------------------------- when MN_JT => assert_psen_s <= true; - if opc_opcode_s(6) = '0' then + if opc_opcode_q(6) = '0' then cnd_branch_cond_o <= COND_T0; else cnd_branch_cond_o <= COND_T1; @@ -1197,7 +1235,7 @@ begin -- start branch calculation if clk_mstate_i = MSTATE3 then cnd_compute_take_o <= true; - cnd_comp_value_o(0) <= opc_opcode_s(4); + cnd_comp_value_o(0) <= opc_opcode_q(4); end if; else @@ -1240,7 +1278,7 @@ begin if clk_mstate_i = MSTATE3 then alu_read_alu_o <= true; cnd_compute_take_o <= true; - cnd_comp_value_o(0) <= opc_opcode_s(6); + cnd_comp_value_o(0) <= opc_opcode_q(6); end if; else @@ -1268,7 +1306,7 @@ begin -- read RAM once for indirect address mode when MSTATE3 => if not enable_quartus_bugfix_c or - opc_opcode_s(3) = '0' then + opc_opcode_q(3) = '0' then address_indirect_3_f; end if; @@ -1304,7 +1342,7 @@ begin -- read RAM once for indirect address mode when MSTATE3 => if not enable_quartus_bugfix_c or - opc_opcode_s(3) = '0' then + opc_opcode_q(3) = '0' then address_indirect_3_f; end if; @@ -1325,7 +1363,7 @@ begin -- read RAM once for indirect address mode if not clk_second_cycle_i and clk_mstate_i = MSTATE3 then if not enable_quartus_bugfix_c or - opc_opcode_s(3) = '0' then + opc_opcode_q(3) = '0' then address_indirect_3_f; end if; end if; @@ -1339,7 +1377,7 @@ begin -- Mnemonic MOV_T ------------------------------------------------------- when MN_MOV_T => if clk_mstate_i = MSTATE3 then - if opc_opcode_s(5) = '1' then + if opc_opcode_q(5) = '1' then alu_read_alu_o <= true; -- MOV T, A tim_write_timer_o <= true; else @@ -1358,9 +1396,9 @@ begin when MSTATE3 => data_s(7 downto 4) <= (others => '0'); - data_s(1 downto 0) <= opc_opcode_s(1 downto 0); + data_s(1 downto 0) <= opc_opcode_q(1 downto 0); -- decide which 8243 command to use - case opc_opcode_s(7 downto 4) is + case opc_opcode_q(7 downto 4) is when "1001" => data_s(3 downto 2) <= "11"; -- ANLD command when "1000" => @@ -1408,7 +1446,7 @@ begin when MSTATE3 => data_s <= "0000" & "00" & -- 8243 command: read - opc_opcode_s(1 downto 0); + opc_opcode_q(1 downto 0); read_dec_s <= true; p2_write_exp_o <= true; @@ -1459,7 +1497,7 @@ begin -- (skip page offset update from Program Counter) if clk_mstate_i = MSTATE3 then alu_read_alu_o <= true; - if opc_opcode_s(6) = '0' then + if opc_opcode_q(6) = '0' then pm_addr_type_o <= PM_PAGE; else pm_addr_type_o <= PM_PAGE3; @@ -1481,7 +1519,7 @@ begin when MN_MOVX => bus_bidir_bus_o <= true; - if opc_opcode_s(4) = '0' then + if opc_opcode_q(4) = '0' then clk_assert_rd_o <= true; else clk_assert_wr_o <= true; @@ -1497,7 +1535,7 @@ begin -- store contents of Accumulator to BUS when MSTATE5 => - if opc_opcode_s(4) = '1' then + if opc_opcode_q(4) = '1' then alu_read_alu_o <= true; bus_write_bus_o <= true; end if; @@ -1508,7 +1546,7 @@ begin else if clk_mstate_i = MSTATE2 then - if opc_opcode_s(4) = '0' then + if opc_opcode_q(4) = '0' then -- store contents of BUS in Accumulator add_read_bus_s <= true; alu_write_accu_o <= true; @@ -1532,7 +1570,7 @@ begin -- read RAM once for indirect address mode when MSTATE3 => if not enable_quartus_bugfix_c or - opc_opcode_s(3) = '0' then + opc_opcode_q(3) = '0' then address_indirect_3_f; end if; @@ -1577,9 +1615,9 @@ begin if not clk_second_cycle_i then -- read port to Temp Reg if clk_mstate_i = MSTATE5 then - if opc_opcode_s(1 downto 0) = "00" then + if opc_opcode_q(1 downto 0) = "00" then add_read_bus_s <= true; - elsif opc_opcode_s(1) = '0' then + elsif opc_opcode_q(1) = '0' then p1_read_p1_o <= true; p1_read_reg_o <= true; else @@ -1608,9 +1646,9 @@ begin alu_op_o <= ALU_OR; alu_read_alu_o <= true; - if opc_opcode_s(1 downto 0) = "00" then + if opc_opcode_q(1 downto 0) = "00" then bus_write_bus_o <= true; - elsif opc_opcode_s(1) = '0' then + elsif opc_opcode_q(1) = '0' then p1_write_p1_o <= true; else p2_write_p2_o <= true; @@ -1625,7 +1663,7 @@ begin -- Mnemonic OUTL_EXT ---------------------------------------------------- when MN_OUTL_EXT => - if opc_opcode_s(4) = '0' then + if opc_opcode_q(4) = '0' then clk_assert_wr_o <= true; end if; @@ -1633,8 +1671,8 @@ begin if not clk_second_cycle_i and clk_mstate_i = MSTATE4 then alu_read_alu_o <= true; - if opc_opcode_s(4) = '1' then - if opc_opcode_s(1) = '0' then + if opc_opcode_q(4) = '1' then + if opc_opcode_q(1) = '0' then p1_write_p1_o <= true; else p2_write_p2_o <= true; @@ -1680,7 +1718,7 @@ begin when MSTATE1 => dm_read_dmem_o <= true; pm_write_pch_o <= true; - if opc_opcode_s(4) = '1' then + if opc_opcode_q(4) = '1' then psw_write_psw_o <= true; retr_executed_s <= true; end if; @@ -1702,7 +1740,7 @@ begin alu_read_alu_o <= true; alu_write_accu_o <= true; - if opc_opcode_s(4) = '1' then + if opc_opcode_q(4) = '1' then psw_special_data_o <= alu_carry_i; psw_write_carry_o <= true; alu_use_carry_o <= true; @@ -1716,7 +1754,7 @@ begin alu_read_alu_o <= true; alu_write_accu_o <= true; - if opc_opcode_s(4) = '0' then + if opc_opcode_q(4) = '0' then psw_special_data_o <= alu_carry_i; psw_write_carry_o <= true; alu_use_carry_o <= true; @@ -1726,7 +1764,7 @@ begin -- Mnemonic SEL_MB ------------------------------------------------------ when MN_SEL_MB => if clk_mstate_i = MSTATE3 then - if opc_opcode_s(4) = '1' then + if opc_opcode_q(4) = '1' then set_mb_s <= true; else clear_mb_s <= true; @@ -1736,7 +1774,7 @@ begin -- Mnemonic SEL_RB ------------------------------------------------------ when MN_SEL_RB => if clk_mstate_i = MSTATE3 then - psw_special_data_o <= opc_opcode_s(4); + psw_special_data_o <= opc_opcode_q(4); psw_write_bs_o <= true; end if; @@ -1749,7 +1787,7 @@ begin -- Mnemonic STRT -------------------------------------------------------- when MN_STRT => if clk_mstate_i = MSTATE3 then - if opc_opcode_s(4) = '1' then + if opc_opcode_q(4) = '1' then tim_start_t_o <= true; else tim_start_cnt_o <= true; @@ -1771,7 +1809,7 @@ begin -- read RAM once for indirect address mode when MSTATE3 => if not enable_quartus_bugfix_c or - opc_opcode_s(3) = '0' then + opc_opcode_q(3) = '0' then address_indirect_3_f; end if; @@ -1781,7 +1819,7 @@ begin dm_read_dmem_o <= true; alu_write_accu_o <= true; alu_write_temp_reg_o <= true; - if opc_opcode_s(4) = '1' then + if opc_opcode_q(4) = '1' then -- XCHD -- only write lower nibble of Accumulator alu_accu_low_o <= true; @@ -1791,7 +1829,7 @@ begin when MSTATE5 => dm_write_dmem_s <= true; alu_read_alu_o <= true; - if opc_opcode_s(4) = '1' then + if opc_opcode_q(4) = '1' then -- XCHD -- concatenate shadow Accumulator and Temp Reg alu_op_o <= ALU_CONCAT; @@ -1808,7 +1846,7 @@ begin -- read RAM once for indirect address mode when MSTATE3 => if not enable_quartus_bugfix_c or - opc_opcode_s(3) = '0' then + opc_opcode_q(3) = '0' then address_indirect_3_f; end if; @@ -1968,107 +2006,3 @@ begin bus_read_bus_o <= bus_read_bus_s or add_read_bus_s; end rtl; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: decoder.vhd,v $ --- Revision 1.25 2006/06/20 00:46:03 arniml --- new input xtal_en_i --- --- Revision 1.24 2005/11/14 21:12:29 arniml --- suppress p2_output_pch_o when MOVX operation is accessing the --- external memory --- --- Revision 1.23 2005/11/07 19:25:01 arniml --- fix sensitivity list --- --- Revision 1.22 2005/11/01 21:25:37 arniml --- * suppress p2_output_pch_o when p2_output_exp is active --- * wire xtal_i to interrupt module --- --- Revision 1.21 2005/10/31 10:08:33 arniml --- Suppress assertion of bus_read_bus_s when interrupt is pending. --- This should fix bug report --- "PROBLEM WHEN INT AND JMP" --- --- Revision 1.20 2005/09/13 21:08:34 arniml --- move check for int_pending_s into ea_i_='0' branch --- this fixes a glitch on PCH when an interrutp occurs --- during external program memory fetch --- --- Revision 1.19 2005/06/11 10:08:43 arniml --- introduce prefix 't48_' for all packages, entities and configurations --- --- Revision 1.18 2005/06/09 22:18:28 arniml --- Move latching of BUS to MSTATE2 --- -> sample BUS at the end of RD' --- --- Revision 1.17 2005/05/09 22:26:08 arniml --- remove obsolete output stack_high_o --- --- Revision 1.16 2004/10/25 19:39:24 arniml --- Fix bug report: --- "RD' and WR' not asserted for INS A, BUS and OUTL BUS, A" --- rd is asserted for INS A, BUS --- wr is asserted for OUTL BUS, A --- P1, P2 and BUS are written in first instruction cycle --- --- Revision 1.15 2004/09/12 00:35:44 arniml --- Fix bug report: --- "PSENn Timing" --- PSEN is now only asserted for the second cycle if explicitely --- requested by assert_psen_s. --- The previous implementation asserted PSEN together with RD or WR. --- --- Revision 1.14 2004/06/30 21:18:28 arniml --- Fix bug report: --- "Program Memory bank can be switched during interrupt" --- int module emits int_in_progress signal that is used inside the decoder --- to hold mb low for JMP and CALL during interrupts --- --- Revision 1.13 2004/05/20 21:51:40 arniml --- clean-up use of ea_i --- --- Revision 1.12 2004/05/17 14:40:09 arniml --- assert p2_read_p2_o when expander port is read --- --- Revision 1.11 2004/05/16 15:33:39 arniml --- work around bug in Quartus II 4.0 --- --- Revision 1.10 2004/04/25 16:22:03 arniml --- adjust external timing of BUS --- --- Revision 1.9 2004/04/24 11:22:55 arniml --- removed superfluous signal from sensitivity list --- --- Revision 1.8 2004/04/18 18:57:43 arniml --- + enhance instruction strobe generation --- + rework address output under EA=1 conditions --- --- Revision 1.7 2004/04/15 22:06:05 arniml --- + add marker for injected calls --- + suppress intstruction strobes for injected calls --- --- Revision 1.6 2004/04/14 20:53:33 arniml --- make istrobe visible through testbench package --- --- Revision 1.5 2004/04/07 22:09:03 arniml --- remove unused signals --- --- Revision 1.4 2004/04/04 14:18:53 arniml --- add measures to implement XCHD --- --- Revision 1.3 2004/03/28 21:15:48 arniml --- implemented mnemonic DA --- --- Revision 1.2 2004/03/28 13:06:32 arniml --- implement mnemonics: --- + MOVD_A_PP --- + OUTD_PP_A -> ANLD PP, A; MOVD PP, A; ORLD PP, A --- --- Revision 1.1 2004/03/23 21:31:52 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/common/CPU/t48/decoder_pack-p.vhd b/common/CPU/t48/decoder_pack-p.vhd index 5051e3d5..9b817650 100644 --- a/common/CPU/t48/decoder_pack-p.vhd +++ b/common/CPU/t48/decoder_pack-p.vhd @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------- -- --- $Id: decoder_pack-p.vhd,v 1.3 2005/06/11 10:08:43 arniml Exp $ +-- $Id: decoder_pack-p.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) -- @@ -8,6 +8,11 @@ -- ------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; + +use work.t48_pack.word_t; + package t48_decoder_pack is ----------------------------------------------------------------------------- @@ -71,20 +76,353 @@ package t48_decoder_pack is MN_XRL, MN_XRL_A_DATA); + type mnemonic_rec_t is + record + mnemonic : mnemonic_t; + multi_cycle : boolean; + end record; + + function decode_opcode_f(opcode : in word_t) return + mnemonic_rec_t; + end t48_decoder_pack; -------------------------------------------------------------------------------- --- File History: --- --- $Log: decoder_pack-p.vhd,v $ --- Revision 1.3 2005/06/11 10:08:43 arniml --- introduce prefix 't48_' for all packages, entities and configurations --- --- Revision 1.2 2004/03/28 13:09:53 arniml --- merge MN_ANLD, MN_MOVD_PP_A and MN_ORLD_PP_A to OUTLD_PP_A --- --- Revision 1.1 2004/03/23 21:31:52 arniml --- initial check-in --- -------------------------------------------------------------------------------- +package body t48_decoder_pack is + + function decode_opcode_f(opcode : in word_t) return + mnemonic_rec_t is + variable mnemonic_v : mnemonic_t; + variable multi_cycle_v : boolean; + variable result_v : mnemonic_rec_t; + begin + -- default assignment + mnemonic_v := MN_NOP; + multi_cycle_v := false; + + case opcode is + -- Mnemonic ADD --------------------------------------------------------- + when "01101000" | "01101001" | "01101010" | "01101011" | -- ADD A, Rr + "01101100" | "01101101" | "01101110" | "01101111" | -- + "01100000" | "01100001" | -- ADD A, @ Rr + "01111000" | "01111001" | "01111010" | "01111011" | -- ADDC A, Rr + "01111100" | "01111101" | "01111110" | "01111111" | -- + "01110000" | "01110001" => -- ADDC A, @ Rr + mnemonic_v := MN_ADD; + + -- Mnemonic ADD_A_DATA -------------------------------------------------- + when "00000011" | -- ADD A, data + "00010011" => -- ADDC A, data + mnemonic_v := MN_ADD_A_DATA; + multi_cycle_v := true; + + -- Mnemonic ANL --------------------------------------------------------- + when "01011000" | "01011001" | "01011010" | "01011011" | -- ANL A, Rr + "01011100" | "01011101" | "01011110" | "01011111" | -- + "01010000" | "01010001" => -- ANL A, @ Rr + mnemonic_v := MN_ANL; + + -- Mnemonic ANL_A_DATA -------------------------------------------------- + when "01010011" => -- ANL A, data + mnemonic_v := MN_ANL_A_DATA; + multi_cycle_v := true; + + -- Mnemonic ANL_EXT ----------------------------------------------------- + when "10011000" | -- ANL BUS, data + "10011001" | "10011010" => -- ANL PP, data + mnemonic_v := MN_ANL_EXT; + multi_cycle_v := true; + + -- Mnemonic CALL -------------------------------------------------------- + when "00010100" | "00110100" | "01010100" | "01110100" | -- CALL addr + "10010100" | "10110100" | "11010100" | "11110100" => -- + mnemonic_v := MN_CALL; + multi_cycle_v := true; + + -- Mnemonic CLR_A ------------------------------------------------------- + when "00100111" => -- CLR A + mnemonic_v := MN_CLR_A; + + -- Mnemonic CLR_C ------------------------------------------------------- + when "10010111" => -- CLR C + mnemonic_v := MN_CLR_C; + + -- Mnemonic CLR_F ------------------------------------------------------- + when "10000101" | -- CLR F0 + "10100101" => + mnemonic_v := MN_CLR_F; + + -- Mnemonic CPL_A ------------------------------------------------------- + when "00110111" => -- CPL A + mnemonic_v := MN_CPL_A; + + -- Mnemonic CPL_C ------------------------------------------------------- + when "10100111" => -- CPL C + mnemonic_v := MN_CPL_C; + + -- Mnemonic CPL_F ------------------------------------------------------- + when "10010101" | -- CPL F0 + "10110101" => -- CPL F1 + mnemonic_v := MN_CPL_F; + + -- Mnemonic DA ---------------------------------------------------------- + when "01010111" => -- DA D + mnemonic_v := MN_DA; + + -- Mnemonic DEC --------------------------------------------------------- + when "11001000" | "11001001" | "11001010" | "11001011" | -- DEC Rr + "11001100" | "11001101" | "11001110" | "11001111" | -- + "00000111" => -- DEC A + mnemonic_v := MN_DEC; + + -- Mnemonic DIS_EN_I ---------------------------------------------------- + when "00010101" | -- DIS I + "00000101" => -- EN I + mnemonic_v := MN_DIS_EN_I; + + -- Mnemonic DIS_EN_TCNTI ------------------------------------------------ + when "00110101" | -- DIS TCNTI + "00100101" => -- EN TCNTI + mnemonic_v := MN_DIS_EN_TCNTI; + + -- Mnemonic DJNZ -------------------------------------------------------- + when "11101000" | "11101001" | "11101010" | "11101011" | -- DJNZ Rr, addr + "11101100" | "11101101" | "11101110" | "11101111" => -- + mnemonic_v := MN_DJNZ; + multi_cycle_v := true; + + -- Mnemonic ENT0_CLK ---------------------------------------------------- + when "01110101" => -- ENT0 CLK + mnemonic_v := MN_ENT0_CLK; + + -- Mnemonic IN ---------------------------------------------------------- + when "00001001" | "00001010" => -- IN A, Pp + mnemonic_v := MN_IN; + multi_cycle_v := true; + + -- Mnemonic INC --------------------------------------------------------- + when "00010111" | -- INC A + "00011000" | "00011001" | "00011010" | "00011011" | -- INC Rr + "00011100" | "00011101" | "00011110" | "00011111" | -- + "00010000" | "00010001" => -- INC @ Rr + mnemonic_v := MN_INC; + + -- Mnemonic INS --------------------------------------------------------- + when "00001000" => -- INS A, BUS + mnemonic_v := MN_INS; + multi_cycle_v := true; + + -- Mnemonic JBB --------------------------------------------------------- + when "00010010" | "00110010" | "01010010" | "01110010" | -- JBb addr + "10010010" | "10110010" | "11010010" | "11110010" => -- + mnemonic_v := MN_JBB; + multi_cycle_v := true; + + -- Mnemonic JC ---------------------------------------------------------- + when "11110110" | -- JC addr + "11100110" => -- JNC addr + mnemonic_v := MN_JC; + multi_cycle_v := true; + + -- Mnemonic JF ---------------------------------------------------------- + when "10110110" | -- JF0 addr + "01110110" => -- JF1 addr + mnemonic_v := MN_JF; + multi_cycle_v := true; + + -- Mnemonic JMP --------------------------------------------------------- + when "00000100" | "00100100" | "01000100" | "01100100" | -- JMP addr + "10000100" | "10100100" | "11000100" | "11100100" => -- + mnemonic_v := MN_JMP; + multi_cycle_v := true; + + -- Mnemonic JMPP -------------------------------------------------------- + when "10110011" => -- JMPP @ A + mnemonic_v := MN_JMPP; + multi_cycle_v := true; + + -- Mnemonic JNI --------------------------------------------------------- + when "10000110" => -- JNI addr + mnemonic_v := MN_JNI; + multi_cycle_v := true; + + -- Mnemonic JT ---------------------------------------------------------- + when "00100110" | -- JNT0 addr + "01000110" | -- JNT1 addr + "00110110" | -- JT0 addr + "01010110" => -- JT1 addr + mnemonic_v := MN_JT; + multi_cycle_v := true; + + -- Mnemonic JTF --------------------------------------------------------- + when "00010110" => -- JTF addr + mnemonic_v := MN_JTF; + multi_cycle_v := true; + + -- Mnemonic JZ ---------------------------------------------------------- + when "10010110" | -- JNZ addr + "11000110" => -- JZ addr + mnemonic_v := MN_JZ; + multi_cycle_v := true; + + -- Mnemonic MOV_A_DATA -------------------------------------------------- + when "00100011" => -- MOV A, data + mnemonic_v := MN_MOV_A_DATA; + multi_cycle_v := true; + + -- Mnemonic MOV_A_PSW --------------------------------------------------- + when "11000111" => -- MOV A, PSW + mnemonic_v := MN_MOV_A_PSW; + + -- Mnemonic MOV_A_RR ---------------------------------------------------- + when "11111000" | "11111001" | "11111010" | "11111011" | -- MOV A, Rr + "11111100" | "11111101" | "11111110" | "11111111" | -- + "11110000" | "11110001" => -- MOV A, @ Rr + mnemonic_v := MN_MOV_A_RR; + + -- Mnemonic MOV_PSW_A --------------------------------------------------- + when "11010111" => -- MOV PSW, A + mnemonic_v := MN_MOV_PSW_A; + + -- Mnemonic MOV_RR ------------------------------------------------------ + when "10101000" | "10101001" | "10101010" | "10101011" | -- MOV Rr, A + "10101100" | "10101101" | "10101110" | "10101111" | -- + "10100000" | "10100001" => -- MOV @ Rr, A + mnemonic_v := MN_MOV_RR; + + -- Mnemonic MOV_RR_DATA ------------------------------------------------- + when "10111000" | "10111001" | "10111010" | "10111011" | -- MOV Rr, data + "10111100" | "10111101" | "10111110" | "10111111" | -- + "10110000" | "10110001" => -- MOV @ Rr, data + mnemonic_v := MN_MOV_RR_DATA; + multi_cycle_v := true; + + -- Mnemonic MOV_T ------------------------------------------------------- + when "01100010" | -- MOV T, A + "01000010" => -- MOV A, T + mnemonic_v := MN_MOV_T; + + -- Mnemonic MOVD_A_PP --------------------------------------------------- + when "00001100" | "00001101" | "00001110" | "00001111" => -- MOVD A, Pp + mnemonic_v := MN_MOVD_A_PP; + multi_cycle_v := true; + + -- Mnemonic MOVP -------------------------------------------------------- + when "10100011" | -- MOVP A, @ A + "11100011" => -- MOVP3 A, @ A + mnemonic_v := MN_MOVP; + multi_cycle_v := true; + + -- Mnemonic MOVX -------------------------------------------------------- + when "10000000" | "10000001" | -- MOVX A, @ Rr + "10010000" | "10010001" => -- MOVX @ Rr, A + mnemonic_v := MN_MOVX; + multi_cycle_v := true; + + -- Mnemonic NOP --------------------------------------------------------- + when "00000000" => -- NOP + mnemonic_v := MN_NOP; + + -- Mnemonic ORL --------------------------------------------------------- + when "01001000" | "01001001" | "01001010" | "01001011" | -- ORL A, Rr + "01001100" | "01001101" | "01001110" | "01001111" | -- + "01000000" | "01000001" => -- ORL A, @ Rr + mnemonic_v := MN_ORL; + + -- Mnemonic ORL_A_DATA -------------------------------------------------- + when "01000011" => -- ORL A, data + mnemonic_v := MN_ORL_A_DATA; + multi_cycle_v := true; + + -- Mnemonic ORL_EXT ----------------------------------------------------- + when "10001000" | -- ORL BUS, data + "10001001" | "10001010" => -- ORL Pp, data + mnemonic_v := MN_ORL_EXT; + multi_cycle_v := true; + + -- Mnemonic OUTD_PP_A --------------------------------------------------- + when "00111100" | "00111101" | "00111110" | "00111111" | -- MOVD Pp, A + "10011100" | "10011101" | "10011110" | "10011111" | -- ANLD PP, A + "10001100" | "10001101" | "10001110" | "10001111" => -- ORLD Pp, A + mnemonic_v := MN_OUTD_PP_A; + multi_cycle_v := true; + + -- Mnemonic OUTL_EXT ---------------------------------------------------- + when "00111001" | "00111010" | -- OUTL Pp, A + "00000010" => -- OUTL BUS, A + mnemonic_v := MN_OUTL_EXT; + multi_cycle_v := true; + + -- Mnemonic RET --------------------------------------------------------- + when "10000011" | -- RET + "10010011" => -- RETR + mnemonic_v := MN_RET; + multi_cycle_v := true; + + -- Mnemonic RL ---------------------------------------------------------- + when "11100111" | -- RL A + "11110111" => -- RLC A + mnemonic_v := MN_RL; + + -- Mnemonic RR ---------------------------------------------------------- + when "01110111" | -- RR A + "01100111" => -- RRC A + mnemonic_v := MN_RR; + + -- Mnemonic SEL_MB ------------------------------------------------------ + when "11100101" | -- SEL MB0 + "11110101" => -- SEL MB1 + mnemonic_v := MN_SEL_MB; + + -- Mnemonic SEL_RB ------------------------------------------------------ + when "11000101" | -- SEL RB0 + "11010101" => -- SEL RB1 + mnemonic_v := MN_SEL_RB; + + -- Mnemonic STOP_TCNT --------------------------------------------------- + when "01100101" => -- STOP TCNT + mnemonic_v := MN_STOP_TCNT; + + -- Mnemonic START ------------------------------------------------------- + when "01000101" | -- STRT CNT + "01010101" => -- STRT T + mnemonic_v := MN_STRT; + + -- Mnemonic SWAP -------------------------------------------------------- + when "01000111" => -- SWAP A + mnemonic_v := MN_SWAP; + + -- Mnemonic XCH --------------------------------------------------------- + when "00101000" | "00101001" | "00101010" | "00101011" | -- XCH A, Rr + "00101100" | "00101101" | "00101110" | "00101111" | -- + "00100000" | "00100001" | -- XCH A, @ Rr + "00110000" | "00110001" => -- XCHD A, @ Rr + mnemonic_v := MN_XCH; + + -- Mnemonic XRL --------------------------------------------------------- + when "11011000" | "11011001" | "11011010" | "11011011" | -- XRL A, Rr + "11011100" | "11011101" | "11011110" | "11011111" | -- + "11010000" | "11010001" => -- XRL A, @ Rr + mnemonic_v := MN_XRL; + + -- Mnemonic XRL_A_DATA -------------------------------------------------- + when "11010011" => -- XRL A, data + mnemonic_v := MN_XRL_A_DATA; + multi_cycle_v := true; + + when others => + -- pragma translate_off + assert now = 0 ns + report "Unknown opcode." + severity warning; + -- pragma translate_on + + end case; + + result_v.mnemonic := mnemonic_v; + result_v.multi_cycle := multi_cycle_v; + + return result_v; + end; + +end t48_decoder_pack; diff --git a/common/CPU/t48/dmem_ctrl-c.vhd b/common/CPU/t48/dmem_ctrl-c.vhd index c82948c1..98535433 100644 --- a/common/CPU/t48/dmem_ctrl-c.vhd +++ b/common/CPU/t48/dmem_ctrl-c.vhd @@ -3,7 +3,7 @@ -- The Data Memory control unit. -- All accesses to the Data Memory are managed here. -- --- $Id: dmem_ctrl-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ +-- $Id: dmem_ctrl-c.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) -- diff --git a/common/CPU/t48/dmem_ctrl.vhd b/common/CPU/t48/dmem_ctrl.vhd index 9b42861a..e682de44 100644 --- a/common/CPU/t48/dmem_ctrl.vhd +++ b/common/CPU/t48/dmem_ctrl.vhd @@ -3,7 +3,7 @@ -- The Data Memory control unit. -- All accesses to the Data Memory are managed here. -- --- $Id: dmem_ctrl.vhd,v 1.5 2006/06/20 01:07:16 arniml Exp $ +-- $Id: dmem_ctrl.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) -- @@ -200,25 +200,3 @@ begin dmem_we_o <= to_stdLogic(write_dmem_i); end rtl; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: dmem_ctrl.vhd,v $ --- Revision 1.5 2006/06/20 01:07:16 arniml --- add note about clock enable for data memory RAM macro --- --- Revision 1.4 2005/06/11 10:08:43 arniml --- introduce prefix 't48_' for all packages, entities and configurations --- --- Revision 1.3 2004/04/24 23:44:25 arniml --- move from std_logic_arith to numeric_std --- --- Revision 1.2 2004/04/18 18:58:29 arniml --- clean up sensitivity list --- --- Revision 1.1 2004/03/23 21:31:52 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/common/CPU/t48/dmem_ctrl_pack-p.vhd b/common/CPU/t48/dmem_ctrl_pack-p.vhd index 3bde1b7c..64f04b15 100644 --- a/common/CPU/t48/dmem_ctrl_pack-p.vhd +++ b/common/CPU/t48/dmem_ctrl_pack-p.vhd @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------- -- --- $Id: dmem_ctrl_pack-p.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ +-- $Id: dmem_ctrl_pack-p.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) -- @@ -19,16 +19,3 @@ package t48_dmem_ctrl_pack is DM_STACK_HIGH); end t48_dmem_ctrl_pack; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: dmem_ctrl_pack-p.vhd,v $ --- Revision 1.2 2005/06/11 10:08:43 arniml --- introduce prefix 't48_' for all packages, entities and configurations --- --- Revision 1.1 2004/03/23 21:31:52 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/common/CPU/t48/i8039.qip b/common/CPU/t48/i8039.qip new file mode 100644 index 00000000..10c83a48 --- /dev/null +++ b/common/CPU/t48/i8039.qip @@ -0,0 +1,26 @@ +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) system/t8039_notri.vhd] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) system/generic_ram_ena.vhd] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) alu.vhd] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) alu_pack-p.vhd] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) bus_mux.vhd] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) clock_ctrl.vhd] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) cond_branch.vhd] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) cond_branch_pack-p.vhd] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) db_bus.vhd] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) decoder.vhd] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) decoder_pack-p.vhd] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) dmem_ctrl.vhd] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) dmem_ctrl_pack-p.vhd] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) int.vhd] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) p1.vhd] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) p2.vhd] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) pmem_ctrl.vhd] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) pmem_ctrl_pack-p.vhd] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) psw.vhd] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) t48_comp_pack-p.vhd] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) t48_core.vhd] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) t48_core_comp_pack-p.vhd] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) t48_pack-p.vhd] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) t48_tb_pack-p.vhd] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) timer.vhd] + diff --git a/common/CPU/t48/int-c.vhd b/common/CPU/t48/int-c.vhd index 6f7d4d8f..d6e707ca 100644 --- a/common/CPU/t48/int-c.vhd +++ b/common/CPU/t48/int-c.vhd @@ -3,7 +3,7 @@ -- The Interrupt Controller. -- It collects the interrupt sources and notifies the decoder. -- --- $Id: int-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ +-- $Id: int-c.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- All rights reserved -- diff --git a/common/CPU/t48/int.vhd b/common/CPU/t48/int.vhd index 170d4982..3b180892 100644 --- a/common/CPU/t48/int.vhd +++ b/common/CPU/t48/int.vhd @@ -3,7 +3,7 @@ -- The Interrupt Controller. -- It collects the interrupt sources and notifies the decoder. -- --- $Id: int.vhd,v 1.7 2006/06/20 00:46:03 arniml Exp $ +-- $Id: int.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) -- @@ -251,39 +251,3 @@ begin int_in_progress_o <= int_in_progress_q and int_state_q /= IDLE; end rtl; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: int.vhd,v $ --- Revision 1.7 2006/06/20 00:46:03 arniml --- new input xtal_en_i --- --- Revision 1.6 2005/11/01 21:26:24 arniml --- operate ale_q and int_q with xtal_i after shift of ALE assertion to XTAL3 --- --- Revision 1.5 2005/09/13 21:00:16 arniml --- Fix bug reports: --- "Target address of JMP to Program Memory Bank 1 corrupted by interrupt" --- "Return address of CALL to Program Memory Bank 1 corrupted by interrupt" --- int_in_progress_o was active one cycle before int_pending_o is --- asserted. this confused the mb multiplexer which determines the state of --- the memory bank selection flag --- --- Revision 1.4 2005/06/11 10:08:43 arniml --- introduce prefix 't48_' for all packages, entities and configurations --- --- Revision 1.3 2004/07/11 16:51:33 arniml --- cleanup copyright notice --- --- Revision 1.2 2004/06/30 21:18:28 arniml --- Fix bug report: --- "Program Memory bank can be switched during interrupt" --- int module emits int_in_progress signal that is used inside the decoder --- to hold mb low for JMP and CALL during interrupts --- --- Revision 1.1 2004/03/23 21:31:52 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/common/CPU/t48/opc_decoder-c.vhd b/common/CPU/t48/opc_decoder-c.vhd deleted file mode 100644 index d8888988..00000000 --- a/common/CPU/t48/opc_decoder-c.vhd +++ /dev/null @@ -1,23 +0,0 @@ -------------------------------------------------------------------------------- --- --- The Opcode Decoder. --- Derives instruction mnemonics and multicycle information --- using the OPC table unit. --- --- $Id: opc_decoder-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ --- --- All rights reserved --- -------------------------------------------------------------------------------- - -configuration t48_opc_decoder_rtl_c0 of t48_opc_decoder is - - for rtl - - for opc_table_b: t48_opc_table - use configuration work.t48_opc_table_rtl_c0; - end for; - - end for; - -end t48_opc_decoder_rtl_c0; diff --git a/common/CPU/t48/opc_decoder.vhd b/common/CPU/t48/opc_decoder.vhd deleted file mode 100644 index c002232c..00000000 --- a/common/CPU/t48/opc_decoder.vhd +++ /dev/null @@ -1,182 +0,0 @@ -------------------------------------------------------------------------------- --- --- The Opcode Decoder. --- Derives instruction mnemonics and multicycle information --- using the OPC table unit. --- --- $Id: opc_decoder.vhd,v 1.3 2005/06/11 10:08:43 arniml Exp $ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t48/ --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -use work.t48_pack.word_t; -use work.t48_decoder_pack.mnemonic_t; - -entity t48_opc_decoder is - - generic ( - -- store mnemonic in flip-flops (registered-out) - register_mnemonic_g : integer := 1 - ); - - port ( - -- Global Interface ------------------------------------------------------- - clk_i : in std_logic; - res_i : in std_logic; - en_clk_i : in boolean; - -- T48 Bus Interface ------------------------------------------------------ - data_i : in word_t; - read_bus_i : in boolean; - -- Decoder Interface ------------------------------------------------------ - inj_int_i : in boolean; - opcode_o : out word_t; - mnemonic_o : out mnemonic_t; - multi_cycle_o : out boolean - ); - -end t48_opc_decoder; - - -use work.t48_pack.clk_active_c; -use work.t48_pack.res_active_c; -use work.t48_pack.to_boolean; ---use work.decoder_pack.MN_NOP; -use work.t48_decoder_pack.all; - -use work.t48_comp_pack.t48_opc_table; - -architecture rtl of t48_opc_decoder is - - -- the opcode register - signal opcode_q : word_t; - - -- the mnemonic - signal mnemonic_s, - mnemonic_q : mnemonic_t; - - signal multi_cycle_s : std_logic; - -begin - - ----------------------------------------------------------------------------- - -- Verify the generics - ----------------------------------------------------------------------------- - - -- pragma translate_off - - -- Register Mnemonic -------------------------------------------------------- - assert (register_mnemonic_g = 1) or (register_mnemonic_g = 0) - report "register_mnemonic_g must be either 1 or 0!" - severity failure; - - -- pragma translate_on - - - ----------------------------------------------------------------------------- - -- Opcode Decoder Table - ----------------------------------------------------------------------------- - opc_table_b : t48_opc_table - port map ( - opcode_i => opcode_q, - multi_cycle_o => multi_cycle_s, - mnemonic_o => mnemonic_s - ); - - - ----------------------------------------------------------------------------- - -- Process regs - -- - -- Purpose: - -- Implements the opcode and mnemonic registers. - -- - regs: process (res_i, clk_i) - begin - if res_i = res_active_c then - opcode_q <= (others => '0'); -- NOP - mnemonic_q <= MN_NOP; - - elsif clk_i'event and clk_i = clk_active_c then - if en_clk_i then - - if read_bus_i then - opcode_q <= data_i; - elsif inj_int_i then - opcode_q <= "00010100"; - else - mnemonic_q <= mnemonic_s; - end if; - - end if; - - end if; - - end process regs; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Output Mapping. - ----------------------------------------------------------------------------- - opcode_o <= opcode_q; - multi_cycle_o <= to_boolean(multi_cycle_s); - mnemonic_o <= mnemonic_q - when register_mnemonic_g = 1 else - mnemonic_s; - -end rtl; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: opc_decoder.vhd,v $ --- Revision 1.3 2005/06/11 10:08:43 arniml --- introduce prefix 't48_' for all packages, entities and configurations --- --- Revision 1.2 2004/07/11 16:51:33 arniml --- cleanup copyright notice --- --- Revision 1.1 2004/03/23 21:31:52 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/common/CPU/t48/opc_table-c.vhd b/common/CPU/t48/opc_table-c.vhd deleted file mode 100644 index 96c1de95..00000000 --- a/common/CPU/t48/opc_table-c.vhd +++ /dev/null @@ -1,18 +0,0 @@ -------------------------------------------------------------------------------- --- --- The Opcode Decoder Table. --- Decodes the given opcode to instruction mnemonics. --- Also derives the multicycle information. --- --- $Id: opc_table-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ --- --- All rights reserved --- -------------------------------------------------------------------------------- - -configuration t48_opc_table_rtl_c0 of t48_opc_table is - - for rtl - end for; - -end t48_opc_table_rtl_c0; diff --git a/common/CPU/t48/opc_table.vhd b/common/CPU/t48/opc_table.vhd deleted file mode 100644 index 883f4887..00000000 --- a/common/CPU/t48/opc_table.vhd +++ /dev/null @@ -1,425 +0,0 @@ -------------------------------------------------------------------------------- --- --- The Opcode Decoder Table. --- Decodes the given opcode to instruction mnemonics. --- Also derives the multicycle information. --- --- $Id: opc_table.vhd,v 1.4 2005/06/11 10:08:43 arniml Exp $ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t48/ --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -use work.t48_pack.word_t; -use work.t48_decoder_pack.mnemonic_t; - -entity t48_opc_table is - - port ( - opcode_i : in word_t; - multi_cycle_o : out std_logic; - mnemonic_o : out mnemonic_t - ); - -end t48_opc_table; - - -use work.t48_decoder_pack.all; - -architecture rtl of t48_opc_table is - -begin - - ----------------------------------------------------------------------------- - -- Process opc_decode - -- - -- Purpose: - -- Decode the opcode to the set of mnemonics. - -- - opc_decode: process (opcode_i) - begin - -- default assignment - mnemonic_o <= MN_NOP; - multi_cycle_o <= '0'; - - case opcode_i is - -- Mnemonic ADD --------------------------------------------------------- - when "01101000" | "01101001" | "01101010" | "01101011" | -- ADD A, Rr - "01101100" | "01101101" | "01101110" | "01101111" | -- - "01100000" | "01100001" | -- ADD A, @ Rr - "01111000" | "01111001" | "01111010" | "01111011" | -- ADDC A, Rr - "01111100" | "01111101" | "01111110" | "01111111" | -- - "01110000" | "01110001" => -- ADDC A, @ Rr - mnemonic_o <= MN_ADD; - - -- Mnemonic ADD_A_DATA -------------------------------------------------- - when "00000011" | -- ADD A, data - "00010011" => -- ADDC A, data - mnemonic_o <= MN_ADD_A_DATA; - multi_cycle_o <= '1'; - - -- Mnemonic ANL --------------------------------------------------------- - when "01011000" | "01011001" | "01011010" | "01011011" | -- ANL A, Rr - "01011100" | "01011101" | "01011110" | "01011111" | -- - "01010000" | "01010001" => -- ANL A, @ Rr - mnemonic_o <= MN_ANL; - - -- Mnemonic ANL_A_DATA -------------------------------------------------- - when "01010011" => -- ANL A, data - mnemonic_o <= MN_ANL_A_DATA; - multi_cycle_o <= '1'; - - -- Mnemonic ANL_EXT ----------------------------------------------------- - when "10011000" | -- ANL BUS, data - "10011001" | "10011010" => -- ANL PP, data - mnemonic_o <= MN_ANL_EXT; - multi_cycle_o <= '1'; - - -- Mnemonic CALL -------------------------------------------------------- - when "00010100" | "00110100" | "01010100" | "01110100" | -- CALL addr - "10010100" | "10110100" | "11010100" | "11110100" => -- - mnemonic_o <= MN_CALL; - multi_cycle_o <= '1'; - - -- Mnemonic CLR_A ------------------------------------------------------- - when "00100111" => -- CLR A - mnemonic_o <= MN_CLR_A; - - -- Mnemonic CLR_C ------------------------------------------------------- - when "10010111" => -- CLR C - mnemonic_o <= MN_CLR_C; - - -- Mnemonic CLR_F ------------------------------------------------------- - when "10000101" | -- CLR F0 - "10100101" => - mnemonic_o <= MN_CLR_F; - - -- Mnemonic CPL_A ------------------------------------------------------- - when "00110111" => -- CPL A - mnemonic_o <= MN_CPL_A; - - -- Mnemonic CPL_C ------------------------------------------------------- - when "10100111" => -- CPL C - mnemonic_o <= MN_CPL_C; - - -- Mnemonic CPL_F ------------------------------------------------------- - when "10010101" | -- CPL F0 - "10110101" => -- CPL F1 - mnemonic_o <= MN_CPL_F; - - -- Mnemonic DA ---------------------------------------------------------- - when "01010111" => -- DA D - mnemonic_o <= MN_DA; - - -- Mnemonic DEC --------------------------------------------------------- - when "11001000" | "11001001" | "11001010" | "11001011" | -- DEC Rr - "11001100" | "11001101" | "11001110" | "11001111" | -- - "00000111" => -- DEC A - mnemonic_o <= MN_DEC; - - -- Mnemonic DIS_EN_I ---------------------------------------------------- - when "00010101" | -- DIS I - "00000101" => -- EN I - mnemonic_o <= MN_DIS_EN_I; - - -- Mnemonic DIS_EN_TCNTI ------------------------------------------------ - when "00110101" | -- DIS TCNTI - "00100101" => -- EN TCNTI - mnemonic_o <= MN_DIS_EN_TCNTI; - - -- Mnemonic DJNZ -------------------------------------------------------- - when "11101000" | "11101001" | "11101010" | "11101011" | -- DJNZ Rr, addr - "11101100" | "11101101" | "11101110" | "11101111" => -- - mnemonic_o <= MN_DJNZ; - multi_cycle_o <= '1'; - - -- Mnemonic ENT0_CLK ---------------------------------------------------- - when "01110101" => -- ENT0 CLK - mnemonic_o <= MN_ENT0_CLK; - - -- Mnemonic IN ---------------------------------------------------------- - when "00001001" | "00001010" => -- IN A, Pp - mnemonic_o <= MN_IN; - multi_cycle_o <= '1'; - - -- Mnemonic INC --------------------------------------------------------- - when "00010111" | -- INC A - "00011000" | "00011001" | "00011010" | "00011011" | -- INC Rr - "00011100" | "00011101" | "00011110" | "00011111" | -- - "00010000" | "00010001" => -- INC @ Rr - mnemonic_o <= MN_INC; - - -- Mnemonic INS --------------------------------------------------------- - when "00001000" => -- INS A, BUS - mnemonic_o <= MN_INS; - multi_cycle_o <= '1'; - - -- Mnemonic JBB --------------------------------------------------------- - when "00010010" | "00110010" | "01010010" | "01110010" | -- JBb addr - "10010010" | "10110010" | "11010010" | "11110010" => -- - mnemonic_o <= MN_JBB; - multi_cycle_o <= '1'; - - -- Mnemonic JC ---------------------------------------------------------- - when "11110110" | -- JC addr - "11100110" => -- JNC addr - mnemonic_o <= MN_JC; - multi_cycle_o <= '1'; - - -- Mnemonic JF ---------------------------------------------------------- - when "10110110" | -- JF0 addr - "01110110" => -- JF1 addr - mnemonic_o <= MN_JF; - multi_cycle_o <= '1'; - - -- Mnemonic JMP --------------------------------------------------------- - when "00000100" | "00100100" | "01000100" | "01100100" | -- JMP addr - "10000100" | "10100100" | "11000100" | "11100100" => -- - mnemonic_o <= MN_JMP; - multi_cycle_o <= '1'; - - -- Mnemonic JMPP -------------------------------------------------------- - when "10110011" => -- JMPP @ A - mnemonic_o <= MN_JMPP; - multi_cycle_o <= '1'; - - -- Mnemonic JNI --------------------------------------------------------- - when "10000110" => -- JNI addr - mnemonic_o <= MN_JNI; - multi_cycle_o <= '1'; - - -- Mnemonic JT ---------------------------------------------------------- - when "00100110" | -- JNT0 addr - "01000110" | -- JNT1 addr - "00110110" | -- JT0 addr - "01010110" => -- JT1 addr - mnemonic_o <= MN_JT; - multi_cycle_o <= '1'; - - -- Mnemonic JTF --------------------------------------------------------- - when "00010110" => -- JTF addr - mnemonic_o <= MN_JTF; - multi_cycle_o <= '1'; - - -- Mnemonic JZ ---------------------------------------------------------- - when "10010110" | -- JNZ addr - "11000110" => -- JZ addr - mnemonic_o <= MN_JZ; - multi_cycle_o <= '1'; - - -- Mnemonic MOV_A_DATA -------------------------------------------------- - when "00100011" => -- MOV A, data - mnemonic_o <= MN_MOV_A_DATA; - multi_cycle_o <= '1'; - - -- Mnemonic MOV_A_PSW --------------------------------------------------- - when "11000111" => -- MOV A, PSW - mnemonic_o <= MN_MOV_A_PSW; - - -- Mnemonic MOV_A_RR ---------------------------------------------------- - when "11111000" | "11111001" | "11111010" | "11111011" | -- MOV A, Rr - "11111100" | "11111101" | "11111110" | "11111111" | -- - "11110000" | "11110001" => -- MOV A, @ Rr - mnemonic_o <= MN_MOV_A_RR; - - -- Mnemonic MOV_PSW_A --------------------------------------------------- - when "11010111" => -- MOV PSW, A - mnemonic_o <= MN_MOV_PSW_A; - - -- Mnemonic MOV_RR ------------------------------------------------------ - when "10101000" | "10101001" | "10101010" | "10101011" | -- MOV Rr, A - "10101100" | "10101101" | "10101110" | "10101111" | -- - "10100000" | "10100001" => -- MOV @ Rr, A - mnemonic_o <= MN_MOV_RR; - - -- Mnemonic MOV_RR_DATA ------------------------------------------------- - when "10111000" | "10111001" | "10111010" | "10111011" | -- MOV Rr, data - "10111100" | "10111101" | "10111110" | "10111111" | -- - "10110000" | "10110001" => -- MOV @ Rr, data - mnemonic_o <= MN_MOV_RR_DATA; - multi_cycle_o <= '1'; - - -- Mnemonic MOV_T ------------------------------------------------------- - when "01100010" | -- MOV T, A - "01000010" => -- MOV A, T - mnemonic_o <= MN_MOV_T; - - -- Mnemonic MOVD_A_PP --------------------------------------------------- - when "00001100" | "00001101" | "00001110" | "00001111" => -- MOVD A, Pp - mnemonic_o <= MN_MOVD_A_PP; - multi_cycle_o <= '1'; - - -- Mnemonic MOVP -------------------------------------------------------- - when "10100011" | -- MOVP A, @ A - "11100011" => -- MOVP3 A, @ A - mnemonic_o <= MN_MOVP; - multi_cycle_o <= '1'; - - -- Mnemonic MOVX -------------------------------------------------------- - when "10000000" | "10000001" | -- MOVX A, @ Rr - "10010000" | "10010001" => -- MOVX @ Rr, A - mnemonic_o <= MN_MOVX; - multi_cycle_o <= '1'; - - -- Mnemonic NOP --------------------------------------------------------- - when "00000000" => -- NOP - mnemonic_o <= MN_NOP; - - -- Mnemonic ORL --------------------------------------------------------- - when "01001000" | "01001001" | "01001010" | "01001011" | -- ORL A, Rr - "01001100" | "01001101" | "01001110" | "01001111" | -- - "01000000" | "01000001" => -- ORL A, @ Rr - mnemonic_o <= MN_ORL; - - -- Mnemonic ORL_A_DATA -------------------------------------------------- - when "01000011" => -- ORL A, data - mnemonic_o <= MN_ORL_A_DATA; - multi_cycle_o <= '1'; - - -- Mnemonic ORL_EXT ----------------------------------------------------- - when "10001000" | -- ORL BUS, data - "10001001" | "10001010" => -- ORL Pp, data - mnemonic_o <= MN_ORL_EXT; - multi_cycle_o <= '1'; - - -- Mnemonic OUTD_PP_A --------------------------------------------------- - when "00111100" | "00111101" | "00111110" | "00111111" | -- MOVD Pp, A - "10011100" | "10011101" | "10011110" | "10011111" | -- ANLD PP, A - "10001100" | "10001101" | "10001110" | "10001111" => -- ORLD Pp, A - mnemonic_o <= MN_OUTD_PP_A; - multi_cycle_o <= '1'; - - -- Mnemonic OUTL_EXT ---------------------------------------------------- - when "00111001" | "00111010" | -- OUTL Pp, A - "00000010" => -- OUTL BUS, A - mnemonic_o <= MN_OUTL_EXT; - multi_cycle_o <= '1'; - - -- Mnemonic RET --------------------------------------------------------- - when "10000011" | -- RET - "10010011" => -- RETR - mnemonic_o <= MN_RET; - multi_cycle_o <= '1'; - - -- Mnemonic RL ---------------------------------------------------------- - when "11100111" | -- RL A - "11110111" => -- RLC A - mnemonic_o <= MN_RL; - - -- Mnemonic RR ---------------------------------------------------------- - when "01110111" | -- RR A - "01100111" => -- RRC A - mnemonic_o <= MN_RR; - - -- Mnemonic SEL_MB ------------------------------------------------------ - when "11100101" | -- SEL MB0 - "11110101" => -- SEL MB1 - mnemonic_o <= MN_SEL_MB; - - -- Mnemonic SEL_RB ------------------------------------------------------ - when "11000101" | -- SEL RB0 - "11010101" => -- SEL RB1 - mnemonic_o <= MN_SEL_RB; - - -- Mnemonic STOP_TCNT --------------------------------------------------- - when "01100101" => -- STOP TCNT - mnemonic_o <= MN_STOP_TCNT; - - -- Mnemonic START ------------------------------------------------------- - when "01000101" | -- STRT CNT - "01010101" => -- STRT T - mnemonic_o <= MN_STRT; - - -- Mnemonic SWAP -------------------------------------------------------- - when "01000111" => -- SWAP A - mnemonic_o <= MN_SWAP; - - -- Mnemonic XCH --------------------------------------------------------- - when "00101000" | "00101001" | "00101010" | "00101011" | -- XCH A, Rr - "00101100" | "00101101" | "00101110" | "00101111" | -- - "00100000" | "00100001" | -- XCH A, @ Rr - "00110000" | "00110001" => -- XCHD A, @ Rr - mnemonic_o <= MN_XCH; - - -- Mnemonic XRL --------------------------------------------------------- - when "11011000" | "11011001" | "11011010" | "11011011" | -- XRL A, Rr - "11011100" | "11011101" | "11011110" | "11011111" | -- - "11010000" | "11010001" => -- XRL A, @ Rr - mnemonic_o <= MN_XRL; - - -- Mnemonic XRL_A_DATA -------------------------------------------------- - when "11010011" => -- XRL A, data - mnemonic_o <= MN_XRL_A_DATA; - multi_cycle_o <= '1'; - - when others => - -- pragma translate_off - assert now = 0 ns - report "Unknown opcode." - severity warning; - -- pragma translate_on - - end case; - - end process opc_decode; - -- - ----------------------------------------------------------------------------- - -end rtl; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: opc_table.vhd,v $ --- Revision 1.4 2005/06/11 10:08:43 arniml --- introduce prefix 't48_' for all packages, entities and configurations --- --- Revision 1.3 2004/07/11 16:51:33 arniml --- cleanup copyright notice --- --- Revision 1.2 2004/03/28 13:10:48 arniml --- merge MN_ANLD, MN_MOVD_PP_A and MN_ORLD_PP_A to OUTLD_PP_A --- --- Revision 1.1 2004/03/23 21:31:52 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/common/CPU/t48/p1-c.vhd b/common/CPU/t48/p1-c.vhd index 246a296b..67617a5b 100644 --- a/common/CPU/t48/p1-c.vhd +++ b/common/CPU/t48/p1-c.vhd @@ -3,7 +3,7 @@ -- The Port 1 unit. -- Implements the Port 1 logic. -- --- $Id: p1-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ +-- $Id: p1-c.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- All rights reserved -- diff --git a/common/CPU/t48/p1.vhd b/common/CPU/t48/p1.vhd index 694846a9..a5fdb050 100644 --- a/common/CPU/t48/p1.vhd +++ b/common/CPU/t48/p1.vhd @@ -3,7 +3,7 @@ -- The Port 1 unit. -- Implements the Port 1 logic. -- --- $Id: p1.vhd,v 1.5 2005/06/11 10:08:43 arniml Exp $ +-- $Id: p1.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) -- @@ -149,25 +149,3 @@ begin p1_low_imp_o <= low_imp_q; end rtl; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: p1.vhd,v $ --- Revision 1.5 2005/06/11 10:08:43 arniml --- introduce prefix 't48_' for all packages, entities and configurations --- --- Revision 1.4 2004/07/11 16:51:33 arniml --- cleanup copyright notice --- --- Revision 1.3 2004/05/17 14:37:53 arniml --- reorder data_o generation --- --- Revision 1.2 2004/03/29 19:39:58 arniml --- rename pX_limp to pX_low_imp --- --- Revision 1.1 2004/03/23 21:31:52 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/common/CPU/t48/p2-c.vhd b/common/CPU/t48/p2-c.vhd index dff1c4cf..afce4365 100644 --- a/common/CPU/t48/p2-c.vhd +++ b/common/CPU/t48/p2-c.vhd @@ -3,7 +3,7 @@ -- The Port 2 unit. -- Implements the Port 2 logic. -- --- $Id: p2-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ +-- $Id: p2-c.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- All rights reserved -- diff --git a/common/CPU/t48/p2.vhd b/common/CPU/t48/p2.vhd index fed0e344..db942602 100644 --- a/common/CPU/t48/p2.vhd +++ b/common/CPU/t48/p2.vhd @@ -3,7 +3,7 @@ -- The Port 2 unit. -- Implements the Port 2 logic. -- --- $Id: p2.vhd,v 1.9 2006/06/20 00:46:04 arniml Exp $ +-- $Id: p2.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) -- @@ -236,40 +236,3 @@ begin p2h_low_imp_o <= h_low_imp_del_q; end rtl; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: p2.vhd,v $ --- Revision 1.9 2006/06/20 00:46:04 arniml --- new input xtal_en_i --- --- Revision 1.8 2005/11/01 21:27:55 arniml --- * change low impedance markers for P2 --- separate marker for low and high part --- * p2_o output is also registered to prevent combinational --- output to pads --- --- Revision 1.7 2005/06/11 10:08:43 arniml --- introduce prefix 't48_' for all packages, entities and configurations --- --- Revision 1.6 2004/07/11 16:51:33 arniml --- cleanup copyright notice --- --- Revision 1.5 2004/05/17 13:52:46 arniml --- Fix bug "ANL and ORL to P1/P2 read port status instead of port output register" --- --- Revision 1.4 2004/04/24 23:44:25 arniml --- move from std_logic_arith to numeric_std --- --- Revision 1.3 2004/03/29 19:39:58 arniml --- rename pX_limp to pX_low_imp --- --- Revision 1.2 2004/03/28 13:11:43 arniml --- rework Port 2 expander handling --- --- Revision 1.1 2004/03/23 21:31:53 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/common/CPU/t48/pmem_ctrl-c.vhd b/common/CPU/t48/pmem_ctrl-c.vhd index 8cadaaaf..06c9b981 100644 --- a/common/CPU/t48/pmem_ctrl-c.vhd +++ b/common/CPU/t48/pmem_ctrl-c.vhd @@ -3,7 +3,7 @@ -- The Program Memory control unit. -- All operations related to the Program Memory are managed here. -- --- $Id: pmem_ctrl-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ +-- $Id: pmem_ctrl-c.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- All rights reserved -- diff --git a/common/CPU/t48/pmem_ctrl.vhd b/common/CPU/t48/pmem_ctrl.vhd index 51c801fa..183668fa 100644 --- a/common/CPU/t48/pmem_ctrl.vhd +++ b/common/CPU/t48/pmem_ctrl.vhd @@ -3,7 +3,7 @@ -- The Program Memory control unit. -- All operations related to the Program Memory are managed here. -- --- $Id: pmem_ctrl.vhd,v 1.5 2005/06/11 10:08:43 arniml Exp $ +-- $Id: pmem_ctrl.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) -- @@ -220,26 +220,3 @@ begin pmem_addr_o <= pmem_addr_q; end rtl; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: pmem_ctrl.vhd,v $ --- Revision 1.5 2005/06/11 10:08:43 arniml --- introduce prefix 't48_' for all packages, entities and configurations --- --- Revision 1.4 2005/06/08 19:13:53 arniml --- fix bug report --- "MSB of Program Counter changed upon PC increment" --- --- Revision 1.3 2004/07/11 16:51:33 arniml --- cleanup copyright notice --- --- Revision 1.2 2004/04/24 23:44:25 arniml --- move from std_logic_arith to numeric_std --- --- Revision 1.1 2004/03/23 21:31:53 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/common/CPU/t48/pmem_ctrl_pack-p.vhd b/common/CPU/t48/pmem_ctrl_pack-p.vhd index c1d45d69..202c51b2 100644 --- a/common/CPU/t48/pmem_ctrl_pack-p.vhd +++ b/common/CPU/t48/pmem_ctrl_pack-p.vhd @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------- -- --- $Id: pmem_ctrl_pack-p.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ +-- $Id: pmem_ctrl_pack-p.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) -- @@ -18,16 +18,3 @@ package t48_pmem_ctrl_pack is PM_PAGE3); end t48_pmem_ctrl_pack; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: pmem_ctrl_pack-p.vhd,v $ --- Revision 1.2 2005/06/11 10:08:43 arniml --- introduce prefix 't48_' for all packages, entities and configurations --- --- Revision 1.1 2004/03/23 21:31:53 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/common/CPU/t48/psw-c.vhd b/common/CPU/t48/psw-c.vhd index 049e8f5a..bf62f497 100644 --- a/common/CPU/t48/psw-c.vhd +++ b/common/CPU/t48/psw-c.vhd @@ -3,7 +3,7 @@ -- The Program Status Word (PSW). -- Implements the PSW with its special bits. -- --- $Id: psw-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ +-- $Id: psw-c.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- All rights reserved -- diff --git a/common/CPU/t48/psw.vhd b/common/CPU/t48/psw.vhd index 87664f82..7eea9d61 100644 --- a/common/CPU/t48/psw.vhd +++ b/common/CPU/t48/psw.vhd @@ -3,7 +3,7 @@ -- The Program Status Word (PSW). -- Implements the PSW with its special bits. -- --- $Id: psw.vhd,v 1.8 2005/06/11 10:08:43 arniml Exp $ +-- $Id: psw.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) -- @@ -210,34 +210,3 @@ begin bs_o <= psw_q(bs_c); end rtl; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: psw.vhd,v $ --- Revision 1.8 2005/06/11 10:08:43 arniml --- introduce prefix 't48_' for all packages, entities and configurations --- --- Revision 1.7 2004/07/11 16:51:33 arniml --- cleanup copyright notice --- --- Revision 1.6 2004/04/24 23:44:25 arniml --- move from std_logic_arith to numeric_std --- --- Revision 1.5 2004/04/24 11:25:39 arniml --- removed dummy_s - workaround not longer needed for GHDL 0.11.1 --- --- Revision 1.4 2004/04/18 18:59:01 arniml --- add temporary workaround for GHDL 0.11 --- --- Revision 1.3 2004/04/04 14:15:45 arniml --- add dump_compare support --- --- Revision 1.2 2004/03/28 21:28:13 arniml --- take auxiliary carry from direct ALU connection --- --- Revision 1.1 2004/03/23 21:31:53 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/common/CPU/t48/syn_ram-e.vhd b/common/CPU/t48/syn_ram-e.vhd deleted file mode 100644 index 45059493..00000000 --- a/common/CPU/t48/syn_ram-e.vhd +++ /dev/null @@ -1,73 +0,0 @@ -------------------------------------------------------------------------------- --- --- A synchronous parametrizable RAM. --- --- $Id: syn_ram-e.vhd,v 1.1 2004/03/24 21:32:27 arniml Exp $ --- --- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t48/ --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity syn_ram is - - generic ( - address_width_g : positive := 8 - ); - port ( - clk_i : in std_logic; - res_i : in std_logic; - ram_addr_i : in std_logic_vector(address_width_g-1 downto 0); - ram_data_i : in std_logic_vector(7 downto 0); - ram_we_i : in std_logic; - ram_data_o : out std_logic_vector(7 downto 0) - ); - -end syn_ram; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: syn_ram-e.vhd,v $ --- Revision 1.1 2004/03/24 21:32:27 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/common/CPU/t48/system/generic_ram_ena-c.vhd b/common/CPU/t48/system/generic_ram_ena-c.vhd index 29506088..b1b13f0c 100644 --- a/common/CPU/t48/system/generic_ram_ena-c.vhd +++ b/common/CPU/t48/system/generic_ram_ena-c.vhd @@ -2,7 +2,7 @@ -- -- Parametrizable, generic RAM with enable. -- --- $Id: generic_ram_ena-c.vhd,v 1.1.1.1 2006/11/25 22:15:41 arnim Exp $ +-- $Id: generic_ram_ena-c.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org) -- diff --git a/common/CPU/t48/system/generic_ram_ena.vhd b/common/CPU/t48/system/generic_ram_ena.vhd index 299e2b43..f3772aea 100644 --- a/common/CPU/t48/system/generic_ram_ena.vhd +++ b/common/CPU/t48/system/generic_ram_ena.vhd @@ -2,7 +2,7 @@ -- -- Parametrizable, generic RAM with enable. -- --- $Id: generic_ram_ena.vhd,v 1.1.1.1 2006/11/25 22:15:41 arnim Exp $ +-- $Id: generic_ram_ena.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org) -- diff --git a/common/CPU/t48/system/t48_rom-e.vhd b/common/CPU/t48/system/t48_rom-e.vhd index f2bc147c..359159e2 100644 --- a/common/CPU/t48/system/t48_rom-e.vhd +++ b/common/CPU/t48/system/t48_rom-e.vhd @@ -2,7 +2,7 @@ -- -- T8x48 ROM -- --- $Id: t48_rom-e.vhd,v 1.1.1.1 2006/11/25 22:15:41 arnim Exp $ +-- $Id: t48_rom-e.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org) -- @@ -55,16 +55,3 @@ entity t48_rom is ); end t48_rom; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: t48_rom-e.vhd,v $ --- Revision 1.1.1.1 2006/11/25 22:15:41 arnim --- copied from opencores.org repository release 1.0 --- --- Revision 1.1 2006/06/21 00:59:15 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/common/CPU/t48/system/t48_rom-struct-a.vhd b/common/CPU/t48/system/t48_rom-struct-a.vhd index 0735cc38..b75eddf3 100644 --- a/common/CPU/t48/system/t48_rom-struct-a.vhd +++ b/common/CPU/t48/system/t48_rom-struct-a.vhd @@ -2,7 +2,7 @@ -- -- T8x48 ROM -- --- $Id: t48_rom-struct-a.vhd,v 1.1.1.3 2006/11/26 10:07:52 arnim Exp $ +-- $Id: t48_rom-struct-a.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org) -- @@ -63,22 +63,3 @@ begin ); end struct; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: t48_rom-struct-a.vhd,v $ --- Revision 1.1.1.3 2006/11/26 10:07:52 arnim --- incremental import for release 1.0 --- --- Revision 1.3 2006/11/26 12:53:28 arniml --- fix entity port names --- --- Revision 1.2 2006/11/26 11:58:28 arniml --- fix component name --- --- Revision 1.1 2006/06/21 00:59:15 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/common/CPU/t48/system/t48_rom-struct-c.vhd b/common/CPU/t48/system/t48_rom-struct-c.vhd index 3c9602fa..c492056e 100644 --- a/common/CPU/t48/system/t48_rom-struct-c.vhd +++ b/common/CPU/t48/system/t48_rom-struct-c.vhd @@ -2,7 +2,7 @@ -- -- T8x48 ROM -- --- $Id: t48_rom-struct-c.vhd,v 1.1.1.1 2006/11/26 10:07:52 arnim Exp $ +-- $Id: t48_rom-struct-c.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org) -- diff --git a/common/CPU/t48/system/t48_system_comp_pack-p.vhd b/common/CPU/t48/system/t48_system_comp_pack-p.vhd index ac28bb3c..76b7266f 100644 --- a/common/CPU/t48/system/t48_system_comp_pack-p.vhd +++ b/common/CPU/t48/system/t48_system_comp_pack-p.vhd @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------- -- --- $Id: t48_system_comp_pack-p.vhd,v 1.8 2006/06/20 00:47:08 arniml Exp $ +-- $Id: t48_system_comp_pack-p.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) -- diff --git a/common/CPU/t48/system/t49_rom-e.vhd b/common/CPU/t48/system/t49_rom-e.vhd index 2fd569dd..7a8f6f58 100644 --- a/common/CPU/t48/system/t49_rom-e.vhd +++ b/common/CPU/t48/system/t49_rom-e.vhd @@ -2,7 +2,7 @@ -- -- T8x49 ROM -- --- $Id: t49_rom-e.vhd,v 1.1.1.1 2006/11/25 22:15:41 arnim Exp $ +-- $Id: t49_rom-e.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org) -- @@ -55,16 +55,3 @@ entity t49_rom is ); end t49_rom; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: t49_rom-e.vhd,v $ --- Revision 1.1.1.1 2006/11/25 22:15:41 arnim --- copied from opencores.org repository release 1.0 --- --- Revision 1.1 2006/06/21 00:59:15 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/common/CPU/t48/system/t49_rom-struct-a.vhd b/common/CPU/t48/system/t49_rom-struct-a.vhd index e60ebe37..25b6cd53 100644 --- a/common/CPU/t48/system/t49_rom-struct-a.vhd +++ b/common/CPU/t48/system/t49_rom-struct-a.vhd @@ -2,7 +2,7 @@ -- -- T8x49 ROM -- --- $Id: t49_rom-struct-a.vhd,v 1.1.1.3 2006/11/26 10:07:52 arnim Exp $ +-- $Id: t49_rom-struct-a.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org) -- @@ -63,22 +63,3 @@ begin ); end struct; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: t49_rom-struct-a.vhd,v $ --- Revision 1.1.1.3 2006/11/26 10:07:52 arnim --- incremental import for release 1.0 --- --- Revision 1.3 2006/11/26 12:53:28 arniml --- fix entity port names --- --- Revision 1.2 2006/11/26 11:58:28 arniml --- fix component name --- --- Revision 1.1 2006/06/21 00:59:15 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/common/CPU/t48/system/t49_rom-struct-c.vhd b/common/CPU/t48/system/t49_rom-struct-c.vhd index 33294688..e70e28c8 100644 --- a/common/CPU/t48/system/t49_rom-struct-c.vhd +++ b/common/CPU/t48/system/t49_rom-struct-c.vhd @@ -2,7 +2,7 @@ -- -- T8x49 ROM -- --- $Id: t49_rom-struct-c.vhd,v 1.1.1.1 2006/11/26 10:07:52 arnim Exp $ +-- $Id: t49_rom-struct-c.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org) -- diff --git a/common/CPU/t48/system/t8039-c.vhd b/common/CPU/t48/system/t8039-c.vhd index 1daac1ad..9fcd7bff 100644 --- a/common/CPU/t48/system/t8039-c.vhd +++ b/common/CPU/t48/system/t8039-c.vhd @@ -2,7 +2,7 @@ -- -- T8039 Microcontroller System -- --- $Id: t8039-c.vhd,v 1.2 2004/12/03 19:43:12 arniml Exp $ +-- $Id: t8039-c.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) -- diff --git a/common/CPU/t48/system/t8039.vhd b/common/CPU/t48/system/t8039.vhd index f9c4bc54..eef0fc98 100644 --- a/common/CPU/t48/system/t8039.vhd +++ b/common/CPU/t48/system/t8039.vhd @@ -2,8 +2,7 @@ -- -- T8039 Microcontroller System -- --- $Id: t8039.vhd,v 1.7 2006/07/14 01:13:32 arniml Exp $ --- $Name: $ +-- $Id: t8039.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) -- @@ -181,25 +180,3 @@ begin ----------------------------------------------------------------------------- end struct; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: t8039.vhd,v $ --- Revision 1.7 2006/07/14 01:13:32 arniml --- name keyword added --- --- Revision 1.6 2006/06/20 00:47:08 arniml --- new input xtal_en_i --- --- Revision 1.5 2005/11/02 23:41:43 arniml --- properly drive P1 and P2 with low impedance markers --- --- Revision 1.4 2005/11/01 21:37:45 arniml --- wire signals for P2 low impedance marker issue --- --- Revision 1.3 2004/12/03 19:43:12 arniml --- added hierarchy t8039_notri --- -------------------------------------------------------------------------------- diff --git a/common/CPU/t48/system/t8039_notri-c.vhd b/common/CPU/t48/system/t8039_notri-c.vhd index 0bf090f5..b39c43e6 100644 --- a/common/CPU/t48/system/t8039_notri-c.vhd +++ b/common/CPU/t48/system/t8039_notri-c.vhd @@ -3,7 +3,7 @@ -- T8039 Microcontroller System -- 8039 toplevel without tri-states -- --- $Id: t8039_notri-c.vhd,v 1.2 2006/06/21 01:02:35 arniml Exp $ +-- $Id: t8039_notri-c.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) -- diff --git a/common/CPU/t48/system/t8039_notri.vhd b/common/CPU/t48/system/t8039_notri.vhd index e88da2cd..502ce450 100644 --- a/common/CPU/t48/system/t8039_notri.vhd +++ b/common/CPU/t48/system/t8039_notri.vhd @@ -3,8 +3,7 @@ -- T8039 Microcontroller System -- 8039 toplevel without tri-states -- --- $Id: t8039_notri.vhd,v 1.5 2006/07/14 01:13:32 arniml Exp $ --- $Name: $ +-- $Id: t8039_notri.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) -- @@ -203,25 +202,3 @@ begin ); end struct; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: t8039_notri.vhd,v $ --- Revision 1.5 2006/07/14 01:13:32 arniml --- name keyword added --- --- Revision 1.4 2006/06/21 01:02:35 arniml --- replaced syn_ram with generic_ram_ena --- --- Revision 1.3 2006/06/20 00:47:08 arniml --- new input xtal_en_i --- --- Revision 1.2 2005/11/01 21:38:10 arniml --- wire signals for P2 low impedance marker issue --- --- Revision 1.1 2004/12/03 19:42:34 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/common/CPU/t48/system/t8048-c.vhd b/common/CPU/t48/system/t8048-c.vhd index b3d7d0a7..c79053d1 100644 --- a/common/CPU/t48/system/t8048-c.vhd +++ b/common/CPU/t48/system/t8048-c.vhd @@ -2,7 +2,7 @@ -- -- T8048 Microcontroller System -- --- $Id: t8048-c.vhd,v 1.2 2004/12/01 23:09:47 arniml Exp $ +-- $Id: t8048-c.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) -- diff --git a/common/CPU/t48/system/t8048.vhd b/common/CPU/t48/system/t8048.vhd index 4222cefa..1a2e89f9 100644 --- a/common/CPU/t48/system/t8048.vhd +++ b/common/CPU/t48/system/t8048.vhd @@ -2,8 +2,7 @@ -- -- T8048 Microcontroller System -- --- $Id: t8048.vhd,v 1.11 2006/07/14 01:13:32 arniml Exp $ --- $Name: $ +-- $Id: t8048.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) -- @@ -185,47 +184,3 @@ begin end struct; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: t8048.vhd,v $ --- Revision 1.11 2006/07/14 01:13:32 arniml --- name keyword added --- --- Revision 1.10 2006/06/20 00:47:08 arniml --- new input xtal_en_i --- --- Revision 1.9 2005/11/02 23:41:43 arniml --- properly drive P1 and P2 with low impedance markers --- --- Revision 1.8 2005/11/01 21:38:31 arniml --- wire signals for P2 low impedance marker issue --- --- Revision 1.7 2004/12/03 19:44:36 arniml --- removed obsolete constant --- --- Revision 1.6 2004/12/02 22:08:42 arniml --- introduced generic gate_port_input_g --- forces masking of P1 and P2 input bus --- --- Revision 1.5 2004/12/01 23:09:47 arniml --- intruduced hierarchy t8048_notri where all system functionality --- except bidirectional ports is handled --- --- Revision 1.4 2004/10/24 09:10:16 arniml --- Fix for: --- P1 constantly in push-pull mode in t8048 --- --- Revision 1.3 2004/05/20 21:58:26 arniml --- Fix for: --- External Program Memory ignored when EA = 0 --- --- Revision 1.2 2004/03/29 19:40:14 arniml --- rename pX_limp to pX_low_imp --- --- Revision 1.1 2004/03/24 21:32:27 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/common/CPU/t48/system/t8048_notri-c.vhd b/common/CPU/t48/system/t8048_notri-c.vhd index 03e7ec8d..19dc635d 100644 --- a/common/CPU/t48/system/t8048_notri-c.vhd +++ b/common/CPU/t48/system/t8048_notri-c.vhd @@ -2,7 +2,7 @@ -- -- T8048 Microcontroller System -- --- $Id: t8048_notri-c.vhd,v 1.2 2006/06/21 01:02:16 arniml Exp $ +-- $Id: t8048_notri-c.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) -- diff --git a/common/CPU/t48/system/t8048_notri.vhd b/common/CPU/t48/system/t8048_notri.vhd index 891ba5a9..adbbec35 100644 --- a/common/CPU/t48/system/t8048_notri.vhd +++ b/common/CPU/t48/system/t8048_notri.vhd @@ -3,8 +3,7 @@ -- T8048 Microcontroller System -- 8048 toplevel without tri-states -- --- $Id: t8048_notri.vhd,v 1.7 2006/07/14 01:13:32 arniml Exp $ --- $Name: $ +-- $Id: t8048_notri.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) -- @@ -243,29 +242,3 @@ begin ); end struct; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: t8048_notri.vhd,v $ --- Revision 1.7 2006/07/14 01:13:32 arniml --- name keyword added --- --- Revision 1.6 2006/06/21 01:02:16 arniml --- replaced syn_rom and syn_ram with t48_rom and generic_ram_ena --- --- Revision 1.5 2006/06/20 00:47:08 arniml --- new input xtal_en_i --- --- Revision 1.4 2005/11/01 21:38:48 arniml --- wire signals for P2 low impedance marker issue --- --- Revision 1.3 2004/12/02 22:08:42 arniml --- introduced generic gate_port_input_g --- forces masking of P1 and P2 input bus --- --- Revision 1.2 2004/12/01 23:08:08 arniml --- update --- -------------------------------------------------------------------------------- diff --git a/common/CPU/t48/system/t8050_wb-c.vhd b/common/CPU/t48/system/t8050_wb-c.vhd index 1fe1ccc3..db420066 100644 --- a/common/CPU/t48/system/t8050_wb-c.vhd +++ b/common/CPU/t48/system/t8050_wb-c.vhd @@ -2,7 +2,7 @@ -- -- T8048 Microcontroller System -- --- $Id: t8050_wb-c.vhd,v 1.2 2005/06/11 10:19:14 arniml Exp $ +-- $Id: t8050_wb-c.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) -- diff --git a/common/CPU/t48/system/t8050_wb.vhd b/common/CPU/t48/system/t8050_wb.vhd index 348db797..3351a965 100644 --- a/common/CPU/t48/system/t8050_wb.vhd +++ b/common/CPU/t48/system/t8050_wb.vhd @@ -3,8 +3,7 @@ -- T8048 Microcontroller System -- 8050 toplevel with Wishbone interface -- --- $Id: t8050_wb.vhd,v 1.5 2006/07/14 01:14:22 arniml Exp $ --- $Name: $ +-- $Id: t8050_wb.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) -- @@ -289,25 +288,3 @@ begin ); end struct; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: t8050_wb.vhd,v $ --- Revision 1.5 2006/07/14 01:14:22 arniml --- name keyword added --- --- Revision 1.4 2006/06/20 00:58:49 arniml --- new input xtal_en_i --- --- Revision 1.3 2005/11/01 21:39:14 arniml --- wire signals for P2 low impedance marker issue --- --- Revision 1.2 2005/06/11 10:16:05 arniml --- introduce prefix 't48_' for wb_master entity and configuration --- --- Revision 1.1 2005/05/08 10:36:59 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/common/CPU/t48/system/wb_master-c.vhd b/common/CPU/t48/system/wb_master-c.vhd index 89673ecb..45bf7674 100644 --- a/common/CPU/t48/system/wb_master-c.vhd +++ b/common/CPU/t48/system/wb_master-c.vhd @@ -2,7 +2,7 @@ -- -- The Wishbone master module. -- --- $Id: wb_master-c.vhd,v 1.2 2005/06/11 10:16:05 arniml Exp $ +-- $Id: wb_master-c.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) -- diff --git a/common/CPU/t48/system/wb_master.vhd b/common/CPU/t48/system/wb_master.vhd index f1f6993e..bc053fab 100644 --- a/common/CPU/t48/system/wb_master.vhd +++ b/common/CPU/t48/system/wb_master.vhd @@ -2,7 +2,7 @@ -- -- The Wishbone master module. -- --- $Id: wb_master.vhd,v 1.5 2005/06/11 10:16:05 arniml Exp $ +-- $Id: wb_master.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) -- @@ -247,28 +247,3 @@ begin '0'; end rtl; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: wb_master.vhd,v $ --- Revision 1.5 2005/06/11 10:16:05 arniml --- introduce prefix 't48_' for wb_master entity and configuration --- --- Revision 1.4 2005/05/10 22:36:23 arniml --- save data from wishbone bus in register bank with wb_ack --- necessary to hold data from peripheral/memory until it is read by T48 --- --- Revision 1.3 2005/05/08 10:36:07 arniml --- simplify address range: --- - configuration range --- - Wishbone range --- --- Revision 1.2 2005/05/06 18:54:03 arniml --- assign default for state_s --- --- Revision 1.1 2005/05/05 19:49:03 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/common/CPU/t48/t48_comp_pack-p.vhd b/common/CPU/t48/t48_comp_pack-p.vhd index 6ac4ae5e..3fbdaad4 100644 --- a/common/CPU/t48/t48_comp_pack-p.vhd +++ b/common/CPU/t48/t48_comp_pack-p.vhd @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------- -- --- $Id: t48_comp_pack-p.vhd,v 1.11 2006/06/20 00:46:04 arniml Exp $ +-- $Id: t48_comp_pack-p.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2004, 2005, Arnim Laeuger (arniml@opencores.org) -- @@ -265,31 +265,6 @@ package t48_comp_pack is ); end component; - component t48_opc_table - port ( - opcode_i : in word_t; - multi_cycle_o : out std_logic; - mnemonic_o : out mnemonic_t - ); - end component; - - component t48_opc_decoder - generic ( - register_mnemonic_g : integer := 1 - ); - port ( - clk_i : in std_logic; - res_i : in std_logic; - en_clk_i : in boolean; - data_i : in word_t; - read_bus_i : in boolean; - inj_int_i : in boolean; - opcode_o : out word_t; - mnemonic_o : out mnemonic_t; - multi_cycle_o : out boolean - ); - end component; - component t48_timer generic ( sample_t1_state_g : integer := 4 diff --git a/common/CPU/t48/t48_core-c.vhd b/common/CPU/t48/t48_core-c.vhd index 8f0d3595..8ec7082d 100644 --- a/common/CPU/t48/t48_core-c.vhd +++ b/common/CPU/t48/t48_core-c.vhd @@ -2,7 +2,7 @@ -- -- T48 Microcontroller Core -- --- $Id: t48_core-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ +-- $Id: t48_core-c.vhd 295 2009-04-01 19:32:48Z arniml $ -- ------------------------------------------------------------------------------- diff --git a/common/CPU/t48/t48_core.vhd b/common/CPU/t48/t48_core.vhd index b1b1cb33..0ce73dbc 100644 --- a/common/CPU/t48/t48_core.vhd +++ b/common/CPU/t48/t48_core.vhd @@ -2,8 +2,7 @@ -- -- T48 Microcontroller Core -- --- $Id: t48_core.vhd,v 1.12 2006/07/14 01:12:08 arniml Exp $ --- $Name: $ +-- $Id: t48_core.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2004, 2005, Arnim Laeuger (arniml@opencores.org) -- @@ -631,50 +630,3 @@ begin pmem_addr_o <= pmem_addr_s; end struct; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: t48_core.vhd,v $ --- Revision 1.12 2006/07/14 01:12:08 arniml --- * name tag added --- * restriction concerning expander port removed --- --- Revision 1.11 2006/06/20 00:46:04 arniml --- new input xtal_en_i --- --- Revision 1.10 2005/11/01 21:32:58 arniml --- wire signals for P2 low impeddance marker issue --- --- Revision 1.9 2005/06/11 10:08:43 arniml --- introduce prefix 't48_' for all packages, entities and configurations --- --- Revision 1.8 2005/05/04 20:12:37 arniml --- Fix bug report: --- "Wrong clock applied to T0" --- t0_o is generated inside clock_ctrl with a separate flip-flop running --- with xtal_i --- --- Revision 1.7 2004/05/01 11:58:04 arniml --- update notice about expander port instructions --- --- Revision 1.6 2004/04/07 22:09:03 arniml --- remove unused signals --- --- Revision 1.5 2004/04/04 14:18:53 arniml --- add measures to implement XCHD --- --- Revision 1.4 2004/03/29 19:39:58 arniml --- rename pX_limp to pX_low_imp --- --- Revision 1.3 2004/03/28 21:27:50 arniml --- update wiring for DA support --- --- Revision 1.2 2004/03/28 13:13:20 arniml --- connect control signal for Port 2 expander --- --- Revision 1.1 2004/03/23 21:31:53 arniml --- initial check-in --- -------------------------------------------------------------------------------- diff --git a/common/CPU/t48/t48_core_comp_pack-p.vhd b/common/CPU/t48/t48_core_comp_pack-p.vhd index c633f5bc..0d3aca45 100644 --- a/common/CPU/t48/t48_core_comp_pack-p.vhd +++ b/common/CPU/t48/t48_core_comp_pack-p.vhd @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------- -- --- $Id: t48_core_comp_pack-p.vhd,v 1.5 2006/06/21 01:03:28 arniml Exp $ +-- $Id: t48_core_comp_pack-p.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) -- diff --git a/common/CPU/t48/t48_pack-p.vhd b/common/CPU/t48/t48_pack-p.vhd index f95fa752..9d20d7e7 100644 --- a/common/CPU/t48/t48_pack-p.vhd +++ b/common/CPU/t48/t48_pack-p.vhd @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------- -- --- $Id: t48_pack-p.vhd,v 1.1 2004/03/23 21:31:53 arniml Exp $ +-- $Id: t48_pack-p.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) -- diff --git a/common/CPU/t48/t48_tb_pack-p.vhd b/common/CPU/t48/t48_tb_pack-p.vhd index 3b0d3a16..157320f4 100644 --- a/common/CPU/t48/t48_tb_pack-p.vhd +++ b/common/CPU/t48/t48_tb_pack-p.vhd @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------- -- --- $Id: t48_tb_pack-p.vhd,v 1.2 2004/04/14 20:53:54 arniml Exp $ +-- $Id: t48_tb_pack-p.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) -- diff --git a/common/CPU/t48/t8243/t8243-c.vhd b/common/CPU/t48/t8243/t8243-c.vhd new file mode 100644 index 00000000..8d010626 --- /dev/null +++ b/common/CPU/t48/t8243/t8243-c.vhd @@ -0,0 +1,19 @@ +------------------------------------------------------------------------------- +-- +-- T8243 Core +-- +-- $Id: t8243-c.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +------------------------------------------------------------------------------- + +configuration t8243_struct_c0 of t8243 is + + for struct + + for t8243_async_notri_b: t8243_async_notri + use configuration work.t8243_async_notri_struct_c0; + end for; + + end for; + +end t8243_struct_c0; diff --git a/common/CPU/t48/t8243/t8243.vhd b/common/CPU/t48/t8243/t8243.vhd new file mode 100644 index 00000000..8275a831 --- /dev/null +++ b/common/CPU/t48/t8243/t8243.vhd @@ -0,0 +1,137 @@ +------------------------------------------------------------------------------- +-- +-- The T8243 asynchronous toplevel +-- +-- $Id: t8243.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t48/ +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity t8243 is + + port ( + -- Control Interface ------------------------------------------------------ + cs_n_i : in std_logic; + prog_n_i : in std_logic; + -- Port 2 Interface ------------------------------------------------------- + p2_b : inout std_logic_vector(3 downto 0); + -- Port 4 Interface ------------------------------------------------------- + p4_b : inout std_logic_vector(3 downto 0); + -- Port 5 Interface ------------------------------------------------------- + p5_b : inout std_logic_vector(3 downto 0); + -- Port 6 Interface ------------------------------------------------------- + p6_b : inout std_logic_vector(3 downto 0); + -- Port 7 Interface ------------------------------------------------------- + p7_b : inout std_logic_vector(3 downto 0) + ); + +end t8243; + + +use work.t8243_comp_pack.t8243_async_notri; + +architecture struct of t8243 is + + signal p2_s, + p4_s, + p5_s, + p6_s, + p7_s : std_logic_vector(3 downto 0); + signal p2_en_s, + p4_en_s, + p5_en_s, + p6_en_s, + p7_en_s : std_logic; + + signal vdd_s : std_logic; + +begin + + vdd_s <= '1'; + + + ----------------------------------------------------------------------------- + -- The asynchronous T8243 + ----------------------------------------------------------------------------- + t8243_async_notri_b : t8243_async_notri + port map ( + reset_n_i => vdd_s, -- or generate power-on reset + cs_n_i => cs_n_i, + prog_n_i => prog_n_i, + p2_i => p2_b, + p2_o => p2_s, + p2_en_o => p2_en_s, + p4_i => p4_b, + p4_o => p4_s, + p4_en_o => p4_en_s, + p5_i => p5_b, + p5_o => p5_s, + p5_en_o => p5_en_s, + p6_i => p6_b, + p6_o => p6_s, + p6_en_o => p6_en_s, + p7_i => p7_b, + p7_o => p7_s, + p7_en_o => p7_en_s + ); + + + ----------------------------------------------------------------------------- + -- Bidirectional pad structures + ----------------------------------------------------------------------------- + p2_b <= p2_s + when p2_en_s = '1' else + (others => 'Z'); + p4_b <= p4_s + when p4_en_s = '1' else + (others => 'Z'); + p5_b <= p5_s + when p5_en_s = '1' else + (others => 'Z'); + p6_b <= p6_s + when p6_en_s = '1' else + (others => 'Z'); + p7_b <= p7_s + when p7_en_s = '1' else + (others => 'Z'); + +end struct; diff --git a/common/CPU/t48/t8243/t8243_async_notri-c.vhd b/common/CPU/t48/t8243/t8243_async_notri-c.vhd new file mode 100644 index 00000000..053cac56 --- /dev/null +++ b/common/CPU/t48/t8243/t8243_async_notri-c.vhd @@ -0,0 +1,19 @@ +------------------------------------------------------------------------------- +-- +-- T8243 Core +-- +-- $Id: t8243_async_notri-c.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +------------------------------------------------------------------------------- + +configuration t8243_async_notri_struct_c0 of t8243_async_notri is + + for struct + + for t8243_core_b: t8243_core + use configuration work.t8243_core_rtl_c0; + end for; + + end for; + +end t8243_async_notri_struct_c0; diff --git a/common/CPU/t48/t8243/t8243_async_notri.vhd b/common/CPU/t48/t8243/t8243_async_notri.vhd new file mode 100644 index 00000000..3a526256 --- /dev/null +++ b/common/CPU/t48/t8243/t8243_async_notri.vhd @@ -0,0 +1,124 @@ +------------------------------------------------------------------------------- +-- +-- The T8243 asynchronous toplevel without tri-state signals +-- +-- $Id: t8243_async_notri.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t48/ +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity t8243_async_notri is + + port ( + -- System Interface ------------------------------------------------------- + reset_n_i : in std_logic; + -- Control Interface ------------------------------------------------------ + cs_n_i : in std_logic; + prog_n_i : in std_logic; + -- Port 2 Interface ------------------------------------------------------- + p2_i : in std_logic_vector(3 downto 0); + p2_o : out std_logic_vector(3 downto 0); + p2_en_o : out std_logic; + -- Port 4 Interface ------------------------------------------------------- + p4_i : in std_logic_vector(3 downto 0); + p4_o : out std_logic_vector(3 downto 0); + p4_en_o : out std_logic; + -- Port 5 Interface ------------------------------------------------------- + p5_i : in std_logic_vector(3 downto 0); + p5_o : out std_logic_vector(3 downto 0); + p5_en_o : out std_logic; + -- Port 6 Interface ------------------------------------------------------- + p6_i : in std_logic_vector(3 downto 0); + p6_o : out std_logic_vector(3 downto 0); + p6_en_o : out std_logic; + -- Port 7 Interface ------------------------------------------------------- + p7_i : in std_logic_vector(3 downto 0); + p7_o : out std_logic_vector(3 downto 0); + p7_en_o : out std_logic + ); + +end t8243_async_notri; + + +use work.t8243_comp_pack.t8243_core; + +architecture struct of t8243_async_notri is + + signal vdd_s : std_logic; + +begin + + vdd_s <= '1'; + + + ----------------------------------------------------------------------------- + -- The T8243 Core + ----------------------------------------------------------------------------- + t8243_core_b : t8243_core + generic map ( + clk_fall_level_g => 0 + ) + port map ( + clk_i => prog_n_i, + clk_rise_en_i => vdd_s, + clk_fall_en_i => vdd_s, + reset_n_i => reset_n_i, + cs_n_i => cs_n_i, + prog_n_i => prog_n_i, + p2_i => p2_i, + p2_o => p2_o, + p2_en_o => p2_en_o, + p4_i => p4_i, + p4_o => p4_o, + p4_en_o => p4_en_o, + p5_i => p5_i, + p5_o => p5_o, + p5_en_o => p5_en_o, + p6_i => p6_i, + p6_o => p6_o, + p6_en_o => p6_en_o, + p7_i => p7_i, + p7_o => p7_o, + p7_en_o => p7_en_o + ); + +end struct; diff --git a/common/CPU/t48/t8243/t8243_comp_pack-p.vhd b/common/CPU/t48/t8243/t8243_comp_pack-p.vhd new file mode 100644 index 00000000..a164229f --- /dev/null +++ b/common/CPU/t48/t8243/t8243_comp_pack-p.vhd @@ -0,0 +1,132 @@ +------------------------------------------------------------------------------- +-- +-- $Id: t8243_comp_pack-p.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +package t8243_comp_pack is + + component t8243_core + generic ( + clk_fall_level_g : integer := 0 + ); + port ( + -- System Interface ----------------------------------------------------- + clk_i : in std_logic; + clk_rise_en_i : in std_logic; + clk_fall_en_i : in std_logic; + reset_n_i : in std_logic; + -- Control Interface ---------------------------------------------------- + cs_n_i : in std_logic; + prog_n_i : in std_logic; + -- Port 2 Interface ----------------------------------------------------- + p2_i : in std_logic_vector(3 downto 0); + p2_o : out std_logic_vector(3 downto 0); + p2_en_o : out std_logic; + -- Port 4 Interface ----------------------------------------------------- + p4_i : in std_logic_vector(3 downto 0); + p4_o : out std_logic_vector(3 downto 0); + p4_en_o : out std_logic; + -- Port 5 Interface ----------------------------------------------------- + p5_i : in std_logic_vector(3 downto 0); + p5_o : out std_logic_vector(3 downto 0); + p5_en_o : out std_logic; + -- Port 6 Interface ----------------------------------------------------- + p6_i : in std_logic_vector(3 downto 0); + p6_o : out std_logic_vector(3 downto 0); + p6_en_o : out std_logic; + -- Port 7 Interface ----------------------------------------------------- + p7_i : in std_logic_vector(3 downto 0); + p7_o : out std_logic_vector(3 downto 0); + p7_en_o : out std_logic + ); + end component; + + component t8243_sync_notri + port ( + -- System Interface ----------------------------------------------------- + clk_i : in std_logic; + clk_en_i : in std_logic; + reset_n_i : in std_logic; + -- Control Interface ---------------------------------------------------- + cs_n_i : in std_logic; + prog_n_i : in std_logic; + -- Port 2 Interface ----------------------------------------------------- + p2_i : in std_logic_vector(3 downto 0); + p2_o : out std_logic_vector(3 downto 0); + p2_en_o : out std_logic; + -- Port 4 Interface ----------------------------------------------------- + p4_i : in std_logic_vector(3 downto 0); + p4_o : out std_logic_vector(3 downto 0); + p4_en_o : out std_logic; + -- Port 5 Interface ----------------------------------------------------- + p5_i : in std_logic_vector(3 downto 0); + p5_o : out std_logic_vector(3 downto 0); + p5_en_o : out std_logic; + -- Port 6 Interface ----------------------------------------------------- + p6_i : in std_logic_vector(3 downto 0); + p6_o : out std_logic_vector(3 downto 0); + p6_en_o : out std_logic; + -- Port 7 Interface ----------------------------------------------------- + p7_i : in std_logic_vector(3 downto 0); + p7_o : out std_logic_vector(3 downto 0); + p7_en_o : out std_logic + ); + end component; + + component t8243_async_notri + port ( + -- System Interface ----------------------------------------------------- + reset_n_i : in std_logic; + -- Control Interface ---------------------------------------------------- + cs_n_i : in std_logic; + prog_n_i : in std_logic; + -- Port 2 Interface ----------------------------------------------------- + p2_i : in std_logic_vector(3 downto 0); + p2_o : out std_logic_vector(3 downto 0); + p2_en_o : out std_logic; + -- Port 4 Interface ----------------------------------------------------- + p4_i : in std_logic_vector(3 downto 0); + p4_o : out std_logic_vector(3 downto 0); + p4_en_o : out std_logic; + -- Port 5 Interface ----------------------------------------------------- + p5_i : in std_logic_vector(3 downto 0); + p5_o : out std_logic_vector(3 downto 0); + p5_en_o : out std_logic; + -- Port 6 Interface ----------------------------------------------------- + p6_i : in std_logic_vector(3 downto 0); + p6_o : out std_logic_vector(3 downto 0); + p6_en_o : out std_logic; + -- Port 7 Interface ----------------------------------------------------- + p7_i : in std_logic_vector(3 downto 0); + p7_o : out std_logic_vector(3 downto 0); + p7_en_o : out std_logic + ); + end component; + + component t8243 + port ( + -- Control Interface ---------------------------------------------------- + cs_n_i : in std_logic; + prog_n_i : in std_logic; + -- Port 2 Interface ----------------------------------------------------- + p2_b : inout std_logic_vector(3 downto 0); + -- Port 4 Interface ----------------------------------------------------- + p4_b : inout std_logic_vector(3 downto 0); + -- Port 5 Interface ----------------------------------------------------- + p5_b : inout std_logic_vector(3 downto 0); + -- Port 6 Interface ----------------------------------------------------- + p6_b : inout std_logic_vector(3 downto 0); + -- Port 7 Interface ----------------------------------------------------- + p7_b : inout std_logic_vector(3 downto 0) + ); + end component; + +end; diff --git a/common/CPU/t48/t8243/t8243_core-c.vhd b/common/CPU/t48/t8243/t8243_core-c.vhd new file mode 100644 index 00000000..d2c6e9ce --- /dev/null +++ b/common/CPU/t48/t8243/t8243_core-c.vhd @@ -0,0 +1,14 @@ +------------------------------------------------------------------------------- +-- +-- T8243 Core +-- +-- $Id: t8243_core-c.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +------------------------------------------------------------------------------- + +configuration t8243_core_rtl_c0 of t8243_core is + + for rtl + end for; + +end t8243_core_rtl_c0; diff --git a/common/CPU/t48/t8243/t8243_core.vhd b/common/CPU/t48/t8243/t8243_core.vhd new file mode 100644 index 00000000..a9a5235f --- /dev/null +++ b/common/CPU/t48/t8243/t8243_core.vhd @@ -0,0 +1,291 @@ +------------------------------------------------------------------------------- +-- +-- The T8243 Core +-- This is the core module implementing all functionality of the +-- original 8243 chip. +-- +-- $Id: t8243_core.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t48/ +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee. std_logic_1164.all; + +entity t8243_core is + + generic ( + clk_fall_level_g : integer := 0 + ); + port ( + -- System Interface ------------------------------------------------------- + clk_i : in std_logic; + clk_rise_en_i : in std_logic; + clk_fall_en_i : in std_logic; + reset_n_i : in std_logic; + -- Control Interface ------------------------------------------------------ + cs_n_i : in std_logic; + prog_n_i : in std_logic; + -- Port 2 Interface ------------------------------------------------------- + p2_i : in std_logic_vector(3 downto 0); + p2_o : out std_logic_vector(3 downto 0); + p2_en_o : out std_logic; + -- Port 4 Interface ------------------------------------------------------- + p4_i : in std_logic_vector(3 downto 0); + p4_o : out std_logic_vector(3 downto 0); + p4_en_o : out std_logic; + -- Port 5 Interface ------------------------------------------------------- + p5_i : in std_logic_vector(3 downto 0); + p5_o : out std_logic_vector(3 downto 0); + p5_en_o : out std_logic; + -- Port 6 Interface ------------------------------------------------------- + p6_i : in std_logic_vector(3 downto 0); + p6_o : out std_logic_vector(3 downto 0); + p6_en_o : out std_logic; + -- Port 7 Interface ------------------------------------------------------- + p7_i : in std_logic_vector(3 downto 0); + p7_o : out std_logic_vector(3 downto 0); + p7_en_o : out std_logic + ); + +end t8243_core; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of t8243_core is + + function int2stdlogic_f(level_i : in integer) return std_logic is + begin + if level_i = 0 then + return '0'; + else + return '1'; + end if; + end; + + constant clk_fall_level_c : std_logic := int2stdlogic_f(clk_fall_level_g); + + type instr_t is (INSTR_READ, INSTR_WRITE, INSTR_ORLD, INSTR_ANLD); + signal instr_q : instr_t; + + constant port_4_c : integer := 4; + constant port_5_c : integer := 5; + constant port_6_c : integer := 6; + constant port_7_c : integer := 7; + + subtype port_range_t is natural range port_7_c downto port_4_c; + signal px_sel_q : std_logic_vector(port_range_t); + + signal px_en_q : std_logic_vector(port_range_t); + signal p2_en_q : std_logic; + + subtype port_vector_t is std_logic_vector(3 downto 0); + type four_ports_t is array (port_range_t) of port_vector_t; + signal px_latch_q : four_ports_t; + + signal data_s : port_vector_t; + + signal p2_s, + p4_s, + p5_s, + p6_s, + p7_s : port_vector_t; + +begin + + -- get rid of H and L + p2_s <= to_X01(p2_i); + p4_s <= to_X01(p4_i); + p5_s <= to_X01(p5_i); + p6_s <= to_X01(p6_i); + p7_s <= to_X01(p7_i); + + ----------------------------------------------------------------------------- + -- Process ctrl_seq + -- + -- Purpose: + -- Implements the sequential elements that control the T8243 core. + -- * latch port number + -- * latch instruction + -- + ctrl_seq: process (clk_i, cs_n_i) + begin + if cs_n_i = '1' then + px_sel_q <= (others => '0'); + p2_en_q <= '0'; + instr_q <= INSTR_WRITE; + + elsif clk_i'event and clk_i = clk_fall_level_c then + if cs_n_i = '0' and clk_fall_en_i = '1' then + -- enable addressed port ---------------------------------------------- + px_sel_q <= (others => '0'); + px_sel_q(to_integer(unsigned(p2_s(1 downto 0))) + + port_range_t'low) <= '1'; + + p2_en_q <= '0'; + + -- decode instruction ------------------------------------------------- + case p2_s(3 downto 2) is + when "00" => + instr_q <= INSTR_READ; + p2_en_q <= '1'; + when "01" => + instr_q <= INSTR_WRITE; + when "10" => + instr_q <= INSTR_ORLD; + when "11" => + instr_q <= INSTR_ANLD; + when others => + null; + end case; + + end if; + + end if; + end process ctrl_seq; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process port_seq + -- + -- Purpose: + -- Implements the sequential elements of the four ports. + -- + port_seq: process (clk_i, reset_n_i) + begin + if reset_n_i = '0' then + px_en_q <= (others => '0'); + px_latch_q <= (others => (others => '0')); + + elsif rising_edge(clk_i) then + if cs_n_i = '0' and clk_rise_en_i = '1' then + for idx in port_range_t loop + if px_sel_q(idx) = '1' then + if instr_q = INSTR_READ then + -- port is being read from, switch off output enable + px_en_q(idx) <= '0'; + + else + -- port is being written to, enable output + px_en_q(idx) <= '1'; + -- and latch value + px_latch_q(idx) <= data_s; + end if; + end if; + end loop; + end if; + + end if; + end process port_seq; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process data_gen + -- + -- Purpose: + -- Generates the data for the four port latches. + -- * determines data inputs + -- * calculates result of instruction + -- + -- Multiplexes the read value for P2. + -- + data_gen: process (px_sel_q, + instr_q, + p2_s, + px_latch_q, + p4_s, p5_s, p6_s, p7_s) + variable port_v : port_vector_t; + begin + -- select addressed port + case px_sel_q is + when "0001" => + port_v := px_latch_q(port_4_c); + p2_o <= p4_s; + when "0010" => + port_v := px_latch_q(port_5_c); + p2_o <= p5_s; + when "0100" => + port_v := px_latch_q(port_6_c); + p2_o <= p6_s; + when "1000" => + port_v := px_latch_q(port_7_c); + p2_o <= p7_s; + when others => + port_v := (others => '-'); + p2_o <= (others => '-'); + end case; + + case instr_q is + when INSTR_WRITE => + data_s <= p2_s; + when INSTR_ORLD => + data_s <= p2_s or port_v; + when INSTR_ANLD => + data_s <= p2_s and port_v; + when others => + data_s <= (others => '-'); + end case; + + end process; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output mapping + ----------------------------------------------------------------------------- + p2_en_o <= '1' + when cs_n_i = '0' and prog_n_i = '0' and p2_en_q = '1' else + '0'; + p4_o <= px_latch_q(port_4_c); + p4_en_o <= px_en_q(port_4_c); + p5_o <= px_latch_q(port_5_c); + p5_en_o <= px_en_q(port_5_c); + p6_o <= px_latch_q(port_6_c); + p6_en_o <= px_en_q(port_6_c); + p7_o <= px_latch_q(port_7_c); + p7_en_o <= px_en_q(port_7_c); + +end rtl; diff --git a/common/CPU/t48/t8243/t8243_sync_notri-c.vhd b/common/CPU/t48/t8243/t8243_sync_notri-c.vhd new file mode 100644 index 00000000..d10b7839 --- /dev/null +++ b/common/CPU/t48/t8243/t8243_sync_notri-c.vhd @@ -0,0 +1,19 @@ +------------------------------------------------------------------------------- +-- +-- T8243 Core +-- +-- $Id: t8243_sync_notri-c.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +------------------------------------------------------------------------------- + +configuration t8243_sync_notri_struct_c0 of t8243_sync_notri is + + for struct + + for t8243_core_b: t8243_core + use configuration work.t8243_core_rtl_c0; + end for; + + end for; + +end t8243_sync_notri_struct_c0; diff --git a/common/CPU/t48/t8243/t8243_sync_notri.vhd b/common/CPU/t48/t8243/t8243_sync_notri.vhd new file mode 100644 index 00000000..980b664d --- /dev/null +++ b/common/CPU/t48/t8243/t8243_sync_notri.vhd @@ -0,0 +1,153 @@ +------------------------------------------------------------------------------- +-- +-- The T8243 synchronous toplevel without tri-state signals +-- +-- $Id: t8243_sync_notri.vhd 295 2009-04-01 19:32:48Z arniml $ +-- +-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t48/ +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity t8243_sync_notri is + + port ( + -- System Interface ------------------------------------------------------- + clk_i : in std_logic; + clk_en_i : in std_logic; + reset_n_i : in std_logic; + -- Control Interface ------------------------------------------------------ + cs_n_i : in std_logic; + prog_n_i : in std_logic; + -- Port 2 Interface ------------------------------------------------------- + p2_i : in std_logic_vector(3 downto 0); + p2_o : out std_logic_vector(3 downto 0); + p2_en_o : out std_logic; + -- Port 4 Interface ------------------------------------------------------- + p4_i : in std_logic_vector(3 downto 0); + p4_o : out std_logic_vector(3 downto 0); + p4_en_o : out std_logic; + -- Port 5 Interface ------------------------------------------------------- + p5_i : in std_logic_vector(3 downto 0); + p5_o : out std_logic_vector(3 downto 0); + p5_en_o : out std_logic; + -- Port 6 Interface ------------------------------------------------------- + p6_i : in std_logic_vector(3 downto 0); + p6_o : out std_logic_vector(3 downto 0); + p6_en_o : out std_logic; + -- Port 7 Interface ------------------------------------------------------- + p7_i : in std_logic_vector(3 downto 0); + p7_o : out std_logic_vector(3 downto 0); + p7_en_o : out std_logic + ); + +end t8243_sync_notri; + + +use work.t8243_comp_pack.t8243_core; + +architecture struct of t8243_sync_notri is + + signal prog_n_q : std_logic; + signal clk_rise_en_s, + clk_fall_en_s : std_logic; + +begin + + ----------------------------------------------------------------------------- + -- Process edge_detect + -- + -- Purpose: + -- Implements the sequential element required for edge detection + -- on the PROG input. + -- + edge_detect: process (clk_i, reset_n_i) + begin + if reset_n_i = '0' then + prog_n_q <= '1'; + elsif rising_edge(clk_i) then + if clk_en_i = '1' then + prog_n_q <= prog_n_i; + end if; + end if; + end process edge_detect; + -- + ----------------------------------------------------------------------------- + + + -- clock enables to detect rising and falling edges of PROG + clk_rise_en_s <= clk_en_i and + not prog_n_q and prog_n_i; + clk_fall_en_s <= clk_en_i and + prog_n_q and not prog_n_i; + + + ----------------------------------------------------------------------------- + -- The T8243 Core + ----------------------------------------------------------------------------- + t8243_core_b : t8243_core + generic map ( + clk_fall_level_g => 1 + ) + port map ( + clk_i => clk_i, + clk_rise_en_i => clk_rise_en_s, + clk_fall_en_i => clk_fall_en_s, + reset_n_i => reset_n_i, + cs_n_i => cs_n_i, + prog_n_i => prog_n_i, + p2_i => p2_i, + p2_o => p2_o, + p2_en_o => p2_en_o, + p4_i => p4_i, + p4_o => p4_o, + p4_en_o => p4_en_o, + p5_i => p5_i, + p5_o => p5_o, + p5_en_o => p5_en_o, + p6_i => p6_i, + p6_o => p6_o, + p6_en_o => p6_en_o, + p7_i => p7_i, + p7_o => p7_o, + p7_en_o => p7_en_o + ); + +end struct; diff --git a/common/CPU/t48/timer-c.vhd b/common/CPU/t48/timer-c.vhd index 8304089e..83a5da33 100644 --- a/common/CPU/t48/timer-c.vhd +++ b/common/CPU/t48/timer-c.vhd @@ -2,7 +2,7 @@ -- -- The Timer/Counter unit. -- --- $Id: timer-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $ +-- $Id: timer-c.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- All rights reserved -- diff --git a/common/CPU/t48/timer.vhd b/common/CPU/t48/timer.vhd index 5edb5c15..37f3e8bb 100644 --- a/common/CPU/t48/timer.vhd +++ b/common/CPU/t48/timer.vhd @@ -2,7 +2,7 @@ -- -- The Timer/Counter unit. -- --- $Id: timer.vhd,v 1.7 2006/11/30 14:31:59 arniml Exp $ +-- $Id: timer.vhd 295 2009-04-01 19:32:48Z arniml $ -- -- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) -- @@ -250,35 +250,3 @@ begin overflow_o <= to_stdLogic(overflow_q); end rtl; - - -------------------------------------------------------------------------------- --- File History: --- --- $Log: timer.vhd,v $ --- Revision 1.7 2006/11/30 14:31:59 arniml --- reset counter_q --- --- Revision 1.6 2005/06/11 10:08:43 arniml --- introduce prefix 't48_' for all packages, entities and configurations --- --- Revision 1.5 2004/07/11 16:51:33 arniml --- cleanup copyright notice --- --- Revision 1.4 2004/07/04 13:06:45 arniml --- counter_q is not cleared during reset --- this would match all different descriptions of the Counter as --- a) if the software assumes that the Counter is modified during reset, it --- will initialize the Counter anyhow --- b) the special case 'Counter not modified during reset' is covered --- --- Revision 1.3 2004/05/16 15:32:57 arniml --- fix edge detector bug for counter --- --- Revision 1.2 2004/04/15 22:05:13 arniml --- increment prescaler with MSTATE4 --- --- Revision 1.1 2004/03/23 21:31:53 arniml --- initial check-in --- --------------------------------------------------------------------------------