diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/Release/time_pilot_mist.rbf b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/Release/time_pilot_mist.rbf
index e61d146f..7671b44a 100644
Binary files a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/Release/time_pilot_mist.rbf and b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/Release/time_pilot_mist.rbf differ
diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/DebugSystem.vhd b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/DebugSystem.vhd
deleted file mode 100644
index 27f115c9..00000000
--- a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/DebugSystem.vhd	
+++ /dev/null
@@ -1,197 +0,0 @@
--- Z80, Monitor ROM, 4k RAM and two 16450 UARTs
--- that can be synthesized and used with
--- the NoICE debugger that can be found at
--- http://www.noicedebugger.com/
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity DebugSystem is
-	port(
-		Reset_n		: in std_logic;
-		Clk			: in std_logic;
-		NMI_n		: in std_logic;
-		RXD0		: in std_logic;
-		CTS0		: in std_logic;
-		DSR0		: in std_logic;
-		RI0			: in std_logic;
-		DCD0		: in std_logic;
-		RXD1		: in std_logic;
-		CTS1		: in std_logic;
-		DSR1		: in std_logic;
-		RI1			: in std_logic;
-		DCD1		: in std_logic;
-		TXD0		: out std_logic;
-		RTS0		: out std_logic;
-		DTR0		: out std_logic;
-		TXD1		: out std_logic;
-		RTS1		: out std_logic;
-		DTR1		: out std_logic;
-As			: out std_logic_vector(15 downto 0);
-Ds			: out std_logic_vector(7 downto 0);
-ROM_Ds		: out std_logic_vector(7 downto 0)
-	);
-end DebugSystem;
-
-architecture struct of DebugSystem is
-
-	signal M1_n			: std_logic;
-	signal MREQ_n		: std_logic;
-	signal IORQ_n		: std_logic;
-	signal RD_n			: std_logic;
-	signal WR_n			: std_logic;
-	signal RFSH_n		: std_logic;
-	signal HALT_n		: std_logic;
-	signal WAIT_n		: std_logic;
-	signal INT_n		: std_logic;
-	signal RESET_s		: std_logic;
-	signal BUSRQ_n		: std_logic;
-	signal BUSAK_n		: std_logic;
-	signal A			: std_logic_vector(15 downto 0);
-	signal D			: std_logic_vector(7 downto 0);
-	signal ROM_D		: std_logic_vector(7 downto 0);
-	signal SRAM_D		: std_logic_vector(7 downto 0);
-	signal UART0_D		: std_logic_vector(7 downto 0);
-	signal UART1_D		: std_logic_vector(7 downto 0);
-	signal CPU_D		: std_logic_vector(7 downto 0);
-
-	signal Mirror		: std_logic;
-
-	signal IOWR_n		: std_logic;
-	signal RAMCS_n		: std_logic;
-	signal UART0CS_n	: std_logic;
-	signal UART1CS_n	: std_logic;
-
-	signal BaudOut0		: std_logic;
-	signal BaudOut1		: std_logic;
-
-begin
-   As <= A;
-   Ds	<= D;
-	ROM_Ds <= ROM_D;
-
-	Wait_n <= '1';
-	BusRq_n <= '1';
-	INT_n <= '1';
-
-	process (Reset_n, Clk)
-	begin
-		if Reset_n = '0' then
-			Reset_s <= '0';
-			Mirror <= '0';
-		elsif Clk'event and Clk = '1' then
-			Reset_s <= '1';
-			if IORQ_n = '0' and A(7 downto 4) = "1111" then
-				Mirror <= D(0);
-			end if;
-		end if;
-	end process;
-
-	IOWR_n <= WR_n or IORQ_n;
-	RAMCS_n <= (not Mirror and not A(15)) or MREQ_n;
-	UART0CS_n <= '0' when IORQ_n = '0' and A(7 downto 3) = "00000" else '1';
-	UART1CS_n <= '0' when IORQ_n = '0' and A(7 downto 3) = "10000" else '1';
-
---	CPU_D <=
---		SRAM_D when RAMCS_n = '0' else
---		UART0_D when UART0CS_n = '0' else
---		UART1_D when UART1CS_n = '0' else
---		ROM_D;
-
-	CPU_D <=
-		ROM_D;
-
-	u0 : entity work.T80s
-			generic map(Mode => 0, T2Write => 1, IOWait => 0)
---			generic map(Mode => 1, T2Write => 1, IOWait => 0)
-			port map(
-				RESET_n => RESET_s,
-				CLK_n => Clk,
-				WAIT_n => WAIT_n,
-				INT_n => INT_n,
-				NMI_n => NMI_n,
-				BUSRQ_n => BUSRQ_n,
-				M1_n => M1_n,
-				MREQ_n => MREQ_n,
-				IORQ_n => IORQ_n,
-				RD_n => RD_n,
-				WR_n => WR_n,
-				RFSH_n => RFSH_n,
-				HALT_n => HALT_n,
-				BUSAK_n => BUSAK_n,
-				A => A,
-				DI => CPU_D,
-				DO => D);
-
-	-- u1 : entity work.MonZ80
-	--		port map(
-	--			Clk => Clk,
-	--			A => A(10 downto 0),
-	--			D => ROM_D);
-
-	 u1 : entity work.bagmanrom
-			port map(
-				clock => not Clk,
-				address => A(14 downto 0),
-				q => ROM_D);
-
-	u2 : entity work.SSRAM
-			generic map(
-				AddrWidth => 12)
-			port map(
-				Clk => Clk,
-				CE_n => RAMCS_n,
-				WE_n => WR_n,
-				A => A(11 downto 0),
-				DIn => D,
-				DOut => SRAM_D);
-
-	u3 : entity work.T16450
-			port map(
-				MR_n => Reset_s,
-				XIn => Clk,
-				RClk => BaudOut0,
-				CS_n => UART0CS_n,
-				Rd_n => RD_n, 
-				Wr_n => IOWR_n,
-				A => A(2 downto 0),
-				D_In => D,
-				D_Out => UART0_D,
-				SIn => RXD0,
-				CTS_n => CTS0,
-				DSR_n => DSR0,
-				RI_n => RI0,
-				DCD_n => DCD0,
-				SOut => TXD0,
-				RTS_n => RTS0,
-				DTR_n => DTR0,
-				OUT1_n => open,
-				OUT2_n => open,
-				BaudOut => BaudOut0,
-				Intr => open);
-
-	u4 : entity work.T16450
-			port map(
-				MR_n => Reset_s,
-				XIn => Clk,
-				RClk => BaudOut1,
-				CS_n => UART1CS_n,
-				Rd_n => RD_n, 
-				Wr_n => IOWR_n,
-				A => A(2 downto 0),
-				D_In => D,
-				D_Out => UART1_D,
-				SIn => RXD1,
-				CTS_n => CTS1,
-				DSR_n => DSR1,
-				RI_n => RI1,
-				DCD_n => DCD1,
-				SOut => TXD1,
-				RTS_n => RTS1,
-				DTR_n => DTR1,
-				OUT1_n => open,
-				OUT2_n => open,
-				BaudOut => BaudOut1,
-				Intr => open);
-
-end;
diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/DebugSystemXR.vhd b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/DebugSystemXR.vhd
deleted file mode 100644
index ca8fa877..00000000
--- a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/DebugSystemXR.vhd	
+++ /dev/null
@@ -1,185 +0,0 @@
--- Z80, Monitor ROM, external SRAM interface and two 16450 UARTs
--- that can be synthesized and used with
--- the NoICE debugger that can be found at
--- http://www.noicedebugger.com/
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity DebugSystemXR is
-	port(
-		Reset_n		: in std_logic;
-		Clk			: in std_logic;
-		NMI_n		: in std_logic;
-		OE_n		: out std_logic;
-		WE_n		: out std_logic;
-		RAMCS_n		: out std_logic;
-		ROMCS_n		: out std_logic;
-		PGM_n		: out std_logic;
-		A			: out std_logic_vector(16 downto 0);
-		D			: inout std_logic_vector(7 downto 0);
-		RXD0		: in std_logic;
-		CTS0		: in std_logic;
-		DSR0		: in std_logic;
-		RI0			: in std_logic;
-		DCD0		: in std_logic;
-		RXD1		: in std_logic;
-		CTS1		: in std_logic;
-		DSR1		: in std_logic;
-		RI1			: in std_logic;
-		DCD1		: in std_logic;
-		TXD0		: out std_logic;
-		RTS0		: out std_logic;
-		DTR0		: out std_logic;
-		TXD1		: out std_logic;
-		RTS1		: out std_logic;
-		DTR1		: out std_logic
-	);
-end entity DebugSystemXR;
-
-architecture struct of DebugSystemXR is
-
-	signal M1_n			: std_logic;
-	signal MREQ_n		: std_logic;
-	signal IORQ_n		: std_logic;
-	signal RD_n			: std_logic;
-	signal WR_n			: std_logic;
-	signal RFSH_n		: std_logic;
-	signal HALT_n		: std_logic;
-	signal WAIT_n		: std_logic;
-	signal INT_n		: std_logic;
-	signal RESET_s		: std_logic;
-	signal BUSRQ_n		: std_logic;
-	signal BUSAK_n		: std_logic;
-	signal A_i			: std_logic_vector(15 downto 0);
-	signal D_i			: std_logic_vector(7 downto 0);
-	signal ROM_D		: std_logic_vector(7 downto 0);
-	signal UART0_D		: std_logic_vector(7 downto 0);
-	signal UART1_D		: std_logic_vector(7 downto 0);
-	signal CPU_D		: std_logic_vector(7 downto 0);
-
-	signal Mirror		: std_logic;
-
-	signal IOWR_n		: std_logic;
-	signal RAMCS_n_i	: std_logic;
-	signal UART0CS_n	: std_logic;
-	signal UART1CS_n	: std_logic;
-
-	signal BaudOut0		: std_logic;
-	signal BaudOut1		: std_logic;
-
-begin
-
-	Wait_n <= '1';
-	BusRq_n <= '1';
-	INT_n <= '1';
-
-	OE_n <= RD_n;
-	WE_n <= WR_n;
-	RAMCS_n <= RAMCS_n_i;
-	ROMCS_n <= '1';
-	PGM_n <= '1';
-	A(14 downto 0) <= A_i(14 downto 0);
-	A(16 downto 15) <= "00";
-	D <= D_i when WR_n = '0' else "ZZZZZZZZ";
-
-	process (Reset_n, Clk)
-	begin
-		if Reset_n = '0' then
-			Reset_s <= '0';
-			Mirror <= '0';
-		elsif Clk'event and Clk = '1' then
-			Reset_s <= '1';
-			if IORQ_n = '0' and A_i(7 downto 4) = "1111" then
-				Mirror <= D_i(0);
-			end if;
-		end if;
-	end process;
-
-	IOWR_n <= WR_n or IORQ_n;
-	RAMCS_n_i <= (not Mirror and not A_i(15)) or MREQ_n;
-	UART0CS_n <= '0' when IORQ_n = '0' and A_i(7 downto 3) = "00000" else '1';
-	UART1CS_n <= '0' when IORQ_n = '0' and A_i(7 downto 3) = "10000" else '1';
-
-	CPU_D <=
-		D when RAMCS_n_i = '0' else
-		UART0_D when UART0CS_n = '0' else
-		UART1_D when UART1CS_n = '0' else
-		ROM_D;
-
-	u0 : entity work.T80s
-			generic map(Mode => 1, T2Write => 1, IOWait => 0)
-			port map(
-				RESET_n => RESET_s,
-				CLK_n => Clk,
-				WAIT_n => WAIT_n,
-				INT_n => INT_n,
-				NMI_n => NMI_n,
-				BUSRQ_n => BUSRQ_n,
-				M1_n => M1_n,
-				MREQ_n => MREQ_n,
-				IORQ_n => IORQ_n,
-				RD_n => RD_n,
-				WR_n => WR_n,
-				RFSH_n => RFSH_n,
-				HALT_n => HALT_n,
-				BUSAK_n => BUSAK_n,
-				A => A_i,
-				DI => CPU_D,
-				DO => D_i);
-
-	u1 : entity work.MonZ80
-			port map(
-				Clk => Clk,
-				A => A_i(10 downto 0),
-				D => ROM_D);
-
-	u3 : entity work.T16450
-			port map(
-				MR_n => Reset_s,
-				XIn => Clk,
-				RClk => BaudOut0,
-				CS_n => UART0CS_n,
-				Rd_n => RD_n,
-				Wr_n => IOWR_n,
-				A => A_i(2 downto 0),
-				D_In => D_i,
-				D_Out => UART0_D,
-				SIn => RXD0,
-				CTS_n => CTS0,
-				DSR_n => DSR0,
-				RI_n => RI0,
-				DCD_n => DCD0,
-				SOut => TXD0,
-				RTS_n => RTS0,
-				DTR_n => DTR0,
-				OUT1_n => open,
-				OUT2_n => open,
-				BaudOut => BaudOut0,
-				Intr => open);
-
-	u4 : entity work.T16450
-			port map(
-				MR_n => Reset_s,
-				XIn => Clk,
-				RClk => BaudOut1,
-				CS_n => UART1CS_n,
-				Rd_n => RD_n,
-				Wr_n => IOWR_n,
-				A => A_i(2 downto 0),
-				D_In => D_i,
-				D_Out => UART1_D,
-				SIn => RXD1,
-				CTS_n => CTS1,
-				DSR_n => DSR1,
-				RI_n => RI1,
-				DCD_n => DCD1,
-				SOut => TXD1,
-				RTS_n => RTS1,
-				DTR_n => DTR1,
-				OUT1_n => open,
-				OUT2_n => open,
-				BaudOut => BaudOut1,
-				Intr => open);
-
-end;
diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80.vhd b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80/T80.vhd
similarity index 100%
rename from Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80.vhd
rename to Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80/T80.vhd
diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T8080se.vhd b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80/T8080se.vhd
similarity index 100%
rename from Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T8080se.vhd
rename to Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80/T8080se.vhd
diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80_ALU.vhd b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80/T80_ALU.vhd
similarity index 100%
rename from Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80_ALU.vhd
rename to Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80/T80_ALU.vhd
diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80_MCode.vhd b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80/T80_MCode.vhd
similarity index 100%
rename from Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80_MCode.vhd
rename to Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80/T80_MCode.vhd
diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80_Pack.vhd b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80/T80_Pack.vhd
similarity index 100%
rename from Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80_Pack.vhd
rename to Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80/T80_Pack.vhd
diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80_Reg.vhd b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80/T80_Reg.vhd
similarity index 100%
rename from Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80_Reg.vhd
rename to Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80/T80_Reg.vhd
diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80se.vhd b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80/T80se.vhd
similarity index 100%
rename from Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80se.vhd
rename to Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80/T80se.vhd
diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80/pll.qip b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80/pll.qip
new file mode 100644
index 00000000..e69de29b
diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/TimePilot_MiST.sv b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/TimePilot_MiST.sv
new file mode 100644
index 00000000..6ad5c739
--- /dev/null
+++ b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/TimePilot_MiST.sv	
@@ -0,0 +1,205 @@
+//============================================================================
+//  Arcade: Time Pilot
+//
+//  Port to MiST
+//  Copyright (C) 2017 Gehstock
+//
+// Time pilot by Dar (darfpga@aol.fr) (29/10/2017)
+// http://darfpga.blogspot.fr
+//
+//  This program is free software; you can redistribute it and/or modify it
+//  under the terms of the GNU General Public License as published by the Free
+//  Software Foundation; either version 2 of the License, or (at your option)
+//  any later version.
+//
+//  This program is distributed in the hope that it will be useful, but WITHOUT
+//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+//  more details.
+//
+//  You should have received a copy of the GNU General Public License along
+//  with this program; if not, write to the Free Software Foundation, Inc.,
+//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+//============================================================================
+
+module TimePilot_MiST(
+	output        LED,						
+	output  [5:0] VGA_R,
+	output  [5:0] VGA_G,
+	output  [5:0] VGA_B,
+	output        VGA_HS,
+	output        VGA_VS,
+	output        AUDIO_L,
+	output        AUDIO_R,	
+	input         SPI_SCK,
+	output        SPI_DO,
+	input         SPI_DI,
+	input         SPI_SS2,
+	input         SPI_SS3,
+	input         CONF_DATA0,
+	input         CLOCK_27
+);
+
+`include "rtl\build_id.v" 
+
+localparam CONF_STR = {
+	"TimePilot;;",
+	"O2,Rotate Controls,Off,On;",
+	"O34,Scanlines,Off,25%,50%,75%;",
+	"T6,Reset;",
+	"V,v1.10.",`BUILD_DATE
+};
+
+assign LED = 1;
+assign AUDIO_R = AUDIO_L;
+
+wire clock_24, clock_14, clock_12, pix_ce;
+wire pll_locked;
+pll pll(
+	.inclk0(CLOCK_27),
+	.areset(0),
+	.c0(clock_24),//24,57600000
+	.c1(clock_14),//14.31800000
+	.c2(clock_12),//12.28800000
+	.locked(pll_locked)
+	);
+
+wire [31:0] status;
+wire  [1:0] buttons;
+wire  [1:0] switches;
+wire  [7:0] joystick_0;
+wire  [7:0] joystick_1;
+wire        scandoublerD;
+wire        ypbpr;
+wire [10:0] ps2_key;
+reg	[10:0] audio;
+wire 			hb, vb;
+wire        blankn = ~(hb | vb);
+wire 			ce_vid;
+wire 			hs, vs;
+wire  [4:0] r,g,b;
+
+time_pilot time_pilot(
+	.clock_12(clock_12),
+	.clock_14(clock_14),
+	.reset(status[0] | status[6] | buttons[1]),
+	.video_r(r),
+	.video_g(g),
+	.video_b(b),
+	.video_hblank(hb),
+	.video_vblank(vb),
+	.video_clk(pix_ce),
+	.video_hs(hs),
+	.video_vs(vs),
+	.audio_out(audio), 
+	.dip_switch_1("FF"), // Coinage_B / Coinage_A
+	.dip_switch_2("4B"), // Sound(8)/Difficulty(7-5)/Bonus(4)/Cocktail(3)/lives(2-1)
+	.start2(btn_two_players),
+	.start1(btn_one_player),
+	.coin1(btn_coin),
+	.fire1(m_fire),
+	.right1(m_right),
+	.left1(m_left),
+	.down1(m_down),
+	.up1(m_up),
+	.fire2(m_fire),
+	.right2(m_right),
+	.left2(m_left),
+	.down2(m_down),
+	.up2(m_up),
+	.dbg_cpu_addr()
+	);
+	
+video_mixer video_mixer(
+	.clk_sys(clock_24),
+	.ce_pix(pix_ce),
+	.ce_pix_actual(pix_ce),
+	.SPI_SCK(SPI_SCK),
+	.SPI_SS3(SPI_SS3),
+	.SPI_DI(SPI_DI),
+	.R(blankn ? r[2:0] : "000"),
+	.G(blankn ? g[2:0] : "000"),
+	.B(blankn ? b[2:0] : "000"),
+	.HSync(hs),
+	.VSync(vs),
+	.VGA_R(VGA_R),
+	.VGA_G(VGA_G),
+	.VGA_B(VGA_B),
+	.VGA_VS(VGA_VS),
+	.VGA_HS(VGA_HS),
+	.rotate({1'b1,status[2]}),
+	.scandoublerD(scandoublerD),
+	.scanlines(scandoublerD ? 2'b00 : status[4:3]),
+	.ypbpr(ypbpr),
+	.ypbpr_full(1),
+	.line_start(0),
+	.mono(0)
+	);
+
+mist_io #(
+	.STRLEN(($size(CONF_STR)>>3)))
+mist_io(
+	.clk_sys        (clock_24       ),
+	.conf_str       (CONF_STR       ),
+	.SPI_SCK        (SPI_SCK        ),
+	.CONF_DATA0     (CONF_DATA0     ),
+	.SPI_SS2			 (SPI_SS2        ),
+	.SPI_DO         (SPI_DO         ),
+	.SPI_DI         (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches   	 (switches       ),
+	.scandoublerD	 (scandoublerD	  ),
+	.ypbpr          (ypbpr          ),
+	.ps2_key			 (ps2_key        ),
+	.joystick_0   	 (joystick_0     ),
+	.joystick_1     (joystick_1     ),
+	.status         (status         )
+	);
+
+dac dac(
+	.clk_i(clock_24),
+	.res_n_i(1),
+	.dac_i({audio, 5'b00000}),
+	.dac_o(AUDIO_L)
+	);
+
+wire m_up     = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3];
+wire m_down   = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2];
+wire m_left   = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1];
+wire m_right  = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0];
+wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
+wire m_bomb   = btn_fire2 | joystick_0[5] | joystick_1[5];
+
+reg btn_one_player = 0;
+reg btn_two_players = 0;
+reg btn_left = 0;
+reg btn_right = 0;
+reg btn_down = 0;
+reg btn_up = 0;
+reg btn_fire1 = 0;
+reg btn_fire2 = 0;
+reg btn_fire3 = 0;
+reg btn_coin  = 0;
+wire       pressed = ps2_key[9];
+wire [7:0] code    = ps2_key[7:0];	
+
+always @(posedge clock_24) begin
+	reg old_state;
+	old_state <= ps2_key[10];
+	if(old_state != ps2_key[10]) begin
+		case(code)
+			'h75: btn_up         	<= pressed; // up
+			'h72: btn_down        	<= pressed; // down
+			'h6B: btn_left      		<= pressed; // left
+			'h74: btn_right       	<= pressed; // right
+			'h76: btn_coin				<= pressed; // ESC
+			'h05: btn_one_player   	<= pressed; // F1
+			'h06: btn_two_players  	<= pressed; // F2
+			'h14: btn_fire3 			<= pressed; // ctrl
+			'h11: btn_fire2 			<= pressed; // alt
+			'h29: btn_fire1   		<= pressed; // Space
+		endcase
+	end
+end
+
+endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/build_id.tcl b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/build_id.tcl
index 5c0eba0c..938515d8 100644
--- a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/build_id.tcl	
+++ b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/build_id.tcl	
@@ -17,12 +17,12 @@ proc generateBuildID_Verilog {} {
 	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
 
 	# Create a Verilog file for output
-	set outputFileName "build_id.vhd"
+	set outputFileName "rtl/build_id.v"
 	set outputFile [open $outputFileName "w"]
 
 	# Output the Verilog source
-	puts $outputFile "constant BUILD_DATE : String(1 to 6) := \"$buildDate\""
-	puts $outputFile "constant BUILD_TIME : String(1 to 6) := \"$buildTime\""
+	puts $outputFile "`define BUILD_DATE \"$buildDate\""
+	puts $outputFile "`define BUILD_TIME \"$buildTime\""
 	close $outputFile
 
 	# Send confirmation message to the Messages window
diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/build_id.v b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/build_id.v
new file mode 100644
index 00000000..880c953c
--- /dev/null
+++ b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/build_id.v	
@@ -0,0 +1,2 @@
+`define BUILD_DATE "190309"
+`define BUILD_TIME "175043"
diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/dac.vhd b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/dac.vhd
index 9f696b0b..477e625f 100644
--- a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/dac.vhd	
+++ b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/dac.vhd	
@@ -20,7 +20,7 @@ library ieee;
 
 entity dac is
 	generic (
-		C_bits  : integer := 11
+		C_bits  : integer := 15
 	);
 	port (
 		clk_i   : in  std_logic;
diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/keyboard.v b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/keyboard.v
deleted file mode 100644
index 89f7e34e..00000000
--- a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/keyboard.v	
+++ /dev/null
@@ -1,82 +0,0 @@
-
-
-module keyboard
-(
-	input  clk,
-	input  reset,
-	input  ps2_kbd_clk,
-	input  ps2_kbd_data,
-
-	output reg[7:0] joystick
-);
-
-reg [11:0] shift_reg = 12'hFFF;
-wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]};
-wire [7:0] kcode = kdata[9:2];
-reg        release_btn = 0;
-
-reg  [7:0] code;
-reg        input_strobe = 0;
-
-always @(negedge clk) begin
-	reg old_reset = 0;
-
-	old_reset <= reset;
-
-	if(~old_reset & reset)begin
-		joystick <= 0;
-	end
-
-	if(input_strobe) begin
-		case(code)
-			'h16: joystick[1] <= ~release_btn; // 1
-			'h1E: joystick[2] <= ~release_btn; // 2
-
-			'h75: joystick[4] <= ~release_btn; // arrow up
-			'h72: joystick[5] <= ~release_btn; // arrow down
-			'h6B: joystick[6] <= ~release_btn; // arrow left
-			'h74: joystick[7] <= ~release_btn; // arrow right
-
-			'h29: joystick[0] <= ~release_btn; // Space
-			'h11: joystick[1] <= ~release_btn; // Left Alt
-			'h0d: joystick[2] <= ~release_btn; // Tab
-			'h76: joystick[3] <= ~release_btn; // Escape
-		endcase
-	end
-end
-
-always @(posedge clk) begin
-	reg [3:0] prev_clk  = 0;
-	reg       old_reset = 0;
-	reg       action = 0;
-
-	old_reset <= reset;
-	input_strobe <= 0;
-
-	if(~old_reset & reset)begin
-		prev_clk  <= 0;
-		shift_reg <= 12'hFFF;
-	end else begin
-		prev_clk <= {ps2_kbd_clk,prev_clk[3:1]};
-		if(prev_clk == 1) begin
-			if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin
-				shift_reg <= 12'hFFF;
-				if (kcode == 8'he0) ;
-				// Extended key code follows
-				else if (kcode == 8'hf0)
-					// Release code follows
-					action <= 1;
-				else begin
-					// Cancel extended/release flags for next time
-					action <= 0;
-					release_btn <= action;
-					code <= kcode;
-					input_strobe <= 1;
-				end
-			end else begin
-				shift_reg <= kdata;
-			end
-		end
-	end
-end
-endmodule
diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/mist_io.v b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/mist_io.v
index ad233a3b..2f41221f 100644
--- a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/mist_io.v	
+++ b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/mist_io.v	
@@ -5,6 +5,7 @@
 // http://code.google.com/p/mist-board/
 //
 // Copyright (c) 2014 Till Harbaum <till@harbaum.org>
+// Copyright (c) 2015-2017 Sorgelig
 //
 // This source file is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published
@@ -47,13 +48,16 @@ module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
 	output            SPI_DO,
 	input             SPI_DI,
 
-	output reg  [7:0] joystick_0,
-	output reg  [7:0] joystick_1,
+	output reg [7:0] joystick_0,
+	output reg [7:0] joystick_1,
+//	output reg [31:0] joystick_2,
+//	output reg [31:0] joystick_3,
+//	output reg [31:0] joystick_4,
 	output reg [15:0] joystick_analog_0,
 	output reg [15:0] joystick_analog_1,
 	output      [1:0] buttons,
 	output      [1:0] switches,
-	output            scandoubler_disable,
+	output            scandoublerD,
 	output            ypbpr,
 
 	output reg [31:0] status,
@@ -61,13 +65,13 @@ module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
 	// SD config
 	input             sd_conf,
 	input             sd_sdhc,
-	output            img_mounted, // signaling that new image has been mounted
+	output      [1:0] img_mounted, // signaling that new image has been mounted
 	output reg [31:0] img_size,    // size of image in bytes
 
 	// SD block level access
 	input      [31:0] sd_lba,
-	input             sd_rd,
-	input             sd_wr,
+	input       [1:0] sd_rd,
+	input       [1:0] sd_wr,
 	output reg        sd_ack,
 	output reg        sd_ack_conf,
 
@@ -82,192 +86,222 @@ module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
 	output reg        ps2_kbd_data,
 	output            ps2_mouse_clk,
 	output reg        ps2_mouse_data,
-	input             ps2_caps_led,
+
+	// ps2 alternative interface. 
+
+	// [8] - extended, [9] - pressed, [10] - toggles with every press/release
+	output reg [10:0] ps2_key = 0,
+
+	// [24] - toggles with every event
+	output reg [24:0] ps2_mouse = 0,
 
 	// ARM -> FPGA download
+	input             ioctl_ce,
 	output reg        ioctl_download = 0, // signal indicating an active download
 	output reg  [7:0] ioctl_index,        // menu index used to upload the file
-	output            ioctl_wr,
+	output reg        ioctl_wr = 0,
 	output reg [24:0] ioctl_addr,
 	output reg  [7:0] ioctl_dout
 );
 
-reg [7:0] b_data;
-reg [6:0] sbuf;
-reg [7:0] cmd;
-reg [2:0] bit_cnt;    // counts bits 0-7 0-7 ...
-reg [9:0] byte_cnt;   // counts bytes
 reg [7:0] but_sw;
 reg [2:0] stick_idx;
 
-reg    mount_strobe = 0;
+reg [1:0] mount_strobe = 0;
 assign img_mounted  = mount_strobe;
 
 assign buttons = but_sw[1:0];
 assign switches = but_sw[3:2];
-assign scandoubler_disable = but_sw[4];
+assign scandoublerD = but_sw[4];
 assign ypbpr = but_sw[5];
 
-wire [7:0] spi_dout = { sbuf, SPI_DI};
-
 // this variant of user_io is for 8 bit cores (type == a4) only
 wire [7:0] core_type = 8'ha4;
 
 // command byte read by the io controller
-wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd };
+wire       drive_sel = sd_rd[1] | sd_wr[1];
+wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] };
+
+reg [7:0] cmd;
+reg [2:0] bit_cnt;    // counts bits 0-7 0-7 ...
+reg [9:0] byte_cnt;   // counts bytes
 
 reg spi_do;
 assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
 
-wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1};
+reg [7:0] spi_data_out;
 
-// drive MISO only when transmitting core id
-always@(negedge SPI_SCK) begin
-	if(!CONF_DATA0) begin
-		// first byte returned is always core type, further bytes are 
-		// command dependent
-      if(byte_cnt == 0) begin
-		  spi_do <= core_type[~bit_cnt];
+// SPI transmitter
+always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt];
 
-		end else begin
-			case(cmd)
-				// reading config string
-				8'h14: begin
-					// returning a byte from string
-						if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}];
-							else spi_do <= 0;
-					end
-
-				// reading sd card status
-				8'h16: begin
-						if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt];
-						else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}];
-						else spi_do <= 0;
-					end
-
-				// reading sd card write data
-				8'h18:
-						spi_do <= b_data[~bit_cnt];
-
-				// reading keyboard LED status
-				8'h1f:
-						spi_do <= kbd_led[~bit_cnt];
-
-				default:
-						spi_do <= 0;
-			endcase
-		end
-   end
-end
-
-reg b_wr2,b_wr3;
-always @(negedge clk_sys) begin
-	b_wr3      <= b_wr2;
-	sd_buff_wr <= b_wr3;
-end
+reg [7:0] spi_data_in;
+reg       spi_data_ready = 0;
 
 // SPI receiver
 always@(posedge SPI_SCK or posedge CONF_DATA0) begin
+	reg [6:0]  sbuf;
+	reg [31:0] sd_lba_r;
+	reg        drive_sel_r;
 
 	if(CONF_DATA0) begin
-		b_wr2 <= 0;
 	   bit_cnt <= 0;
 	   byte_cnt <= 0;
-		sd_ack <= 0;
-		sd_ack_conf <= 0;
-	end else begin
-		b_wr2 <= 0;
-
-		sbuf <= spi_dout[6:0];
+		spi_data_out <= core_type;
+	end
+	else
+	begin
 		bit_cnt <= bit_cnt + 1'd1;
-		if(bit_cnt == 5) begin
-			if (byte_cnt == 0) sd_buff_addr <= 0;
-			if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1;
-			if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0;
-		end
+		sbuf <= {sbuf[5:0], SPI_DI};
 
 		// finished reading command byte
       if(bit_cnt == 7) begin
+			if(!byte_cnt) cmd <= {sbuf, SPI_DI};
+
+			spi_data_in <= {sbuf, SPI_DI};
+			spi_data_ready <= ~spi_data_ready;
 			if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
-			if(byte_cnt == 0) begin
-				cmd <= spi_dout;
-
-				if(spi_dout == 8'h19) begin
-					sd_ack_conf  <= 1;
-					sd_buff_addr <= 0;
-				end
-				if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin
-					sd_ack       <= 1;
-					sd_buff_addr <= 0;
-				end
-				if(spi_dout == 8'h18) b_data <= sd_buff_din;
-
-				mount_strobe <= 0;
-
-			end else begin
 			
-				case(cmd)
-					// buttons and switches
-					8'h01: but_sw <= spi_dout; 
-					8'h02: joystick_0 <= spi_dout;
-					8'h03: joystick_1 <= spi_dout;
+			spi_data_out <= 0;
+			case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd})
+				// reading config string
+				8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8];
 
-					// store incoming ps2 mouse bytes 
-					8'h04: begin
-							ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; 
-							ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
-						end
+				// reading sd card status
+				8'h16: if(byte_cnt == 0) begin
+							spi_data_out <= sd_cmd;
+							sd_lba_r <= sd_lba;
+							drive_sel_r <= drive_sel;
+						end else if (byte_cnt == 1) begin
+							spi_data_out <= drive_sel_r;
+						end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8];
 
-					// store incoming ps2 keyboard bytes 
-					8'h05: begin
-							ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; 
-							ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
-						end
-				
-					8'h15: status[7:0] <= spi_dout;
-				
-					// send SD config IO -> FPGA
-					// flag that download begins
-					// sd card knows data is config if sd_dout_strobe is asserted
-					// with sd_ack still being inactive (low)
-					8'h19,
-					// send sector IO -> FPGA
-					// flag that download begins
-					8'h17: begin
-							sd_buff_dout <= spi_dout;
-							b_wr2 <= 1;
-						end
+				// reading sd card write data
+				8'h18: spi_data_out <= sd_buff_din;
+			endcase
+		end
+	end
+end
 
-					8'h18: b_data <= sd_buff_din;
+reg [31:0] ps2_key_raw = 0;
+wire       pressed  = (ps2_key_raw[15:8] != 8'hf0);
+wire       extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
 
-					// joystick analog
-					8'h1a: begin
-							// first byte is joystick index
-							if(byte_cnt == 1) stick_idx <= spi_dout[2:0];
-							else if(byte_cnt == 2) begin
-								// second byte is x axis
-								if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout;
-									else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout;
-							end else if(byte_cnt == 3) begin
-								// third byte is y axis
-								if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout;
-									else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout;
-							end
-						end
+// transfer to clk_sys domain
+always@(posedge clk_sys) begin
+	reg old_ss1, old_ss2;
+	reg old_ready1, old_ready2;
+	reg [2:0] b_wr;
+	reg       got_ps2 = 0;
 
-					// notify image selection
-					8'h1c: mount_strobe <= 1;
+	old_ss1 <= CONF_DATA0;
+	old_ss2 <= old_ss1;
+	old_ready1 <= spi_data_ready;
+	old_ready2 <= old_ready1;
+	
+	sd_buff_wr <= b_wr[0];
+	if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
+	b_wr <= (b_wr<<1);
 
-					// send image info
-					8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout;
-
-					// status, 32bit version
-					8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout;
-					default: ;
-				endcase
+	if(old_ss2) begin
+		got_ps2      <= 0;
+		sd_ack       <= 0;
+		sd_ack_conf  <= 0;
+		sd_buff_addr <= 0;
+		if(got_ps2) begin
+			if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24]; 
+			if(cmd == 5) begin
+				ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]};
+				if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed
+				if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released
+				if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause  pressed
 			end
 		end
 	end
+	else
+	if(old_ready2 ^ old_ready1) begin
+
+		if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
+
+		if(byte_cnt < 2) begin
+
+			if (cmd == 8'h19) sd_ack_conf  <= 1;
+			if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1;
+			mount_strobe <= 0;
+
+			if(cmd == 5) ps2_key_raw <= 0;
+		end else begin
+		
+			case(cmd)
+				// buttons and switches
+				8'h01: but_sw <= spi_data_in; 
+				8'h02: joystick_0 <= spi_data_in;
+				8'h03: joystick_1 <= spi_data_in;
+//				8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in;
+//				8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in;
+//				8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in;
+//				8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in;
+//				8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in;
+				// store incoming ps2 mouse bytes 
+				8'h04: begin
+						got_ps2 <= 1;
+						case(byte_cnt)
+							2: ps2_mouse[7:0]   <= spi_data_in;
+							3: ps2_mouse[15:8]  <= spi_data_in;
+							4: ps2_mouse[23:16] <= spi_data_in;
+						endcase 
+						ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in; 
+						ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
+					end
+
+				// store incoming ps2 keyboard bytes 
+				8'h05: begin
+						got_ps2 <= 1;
+						ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in}; 						
+						ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in; 
+						ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
+					end
+			
+				8'h15: status[7:0] <= spi_data_in;
+			
+				// send SD config IO -> FPGA
+				// flag that download begins
+				// sd card knows data is config if sd_dout_strobe is asserted
+				// with sd_ack still being inactive (low)
+				8'h19,
+				// send sector IO -> FPGA
+				// flag that download begins
+				8'h17: begin
+						sd_buff_dout <= spi_data_in;
+						b_wr <= 1;
+					end
+
+				// joystick analog
+				8'h1a: begin
+						// first byte is joystick index
+						if(byte_cnt == 2) stick_idx <= spi_data_in[2:0];
+						else if(byte_cnt == 3) begin
+							// second byte is x axis
+							if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in;
+								else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in;
+						end else if(byte_cnt == 4) begin
+							// third byte is y axis
+							if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in;
+								else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in;
+						end
+					end
+
+				// notify image selection
+				8'h1c: mount_strobe[spi_data_in[0]] <= 1;
+
+				// send image info
+				8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in;
+
+				// status, 32bit version
+				8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in;
+				default: ;
+			endcase
+		end
+	end
 end
 
 
@@ -422,6 +456,8 @@ localparam UIO_FILE_TX      = 8'h53;
 localparam UIO_FILE_TX_DAT  = 8'h54;
 localparam UIO_FILE_INDEX   = 8'h55;
 
+reg        rdownload = 0;
+
 // data_io has its own SPI interface to the io controller
 always@(posedge SPI_SCK, posedge SPI_SS2) begin
 	reg  [6:0] sbuf;
@@ -431,15 +467,10 @@ always@(posedge SPI_SCK, posedge SPI_SS2) begin
 
 	if(SPI_SS2) cnt <= 0;
 	else begin
-		rclk <= 0;
-
 		// don't shift in last bit. It is evaluated directly
 		// when writing to ram
 		if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
 
-		// increase target address after write
-		if(rclk) addr <= addr + 1'd1;
-
 		// count 0-7 8-15 8-15 ... 
 		if(cnt < 15) cnt <= cnt + 1'd1;
 			else cnt <= 8;
@@ -451,11 +482,15 @@ always@(posedge SPI_SCK, posedge SPI_SS2) begin
 		if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
 			// prepare 
 			if(SPI_DI) begin
-				addr <= 0;
-				ioctl_download <= 1; 
+				case(ioctl_index[4:0]) 
+							1: addr <= 25'h200000; // TRD buffer  at 2MB
+							2: addr <= 25'h400000; // tape buffer at 4MB 
+					default: addr <= 25'h150000; // boot rom
+				endcase
+				rdownload <= 1; 
 			end else begin
 				addr_w <= addr;
-				ioctl_download <= 0;
+				rdownload <= 0;
 			end
 		end
 
@@ -463,7 +498,8 @@ always@(posedge SPI_SCK, posedge SPI_SS2) begin
 		if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
 			addr_w <= addr;
 			data_w <= {sbuf, SPI_DI};
-			rclk <= 1;
+			addr <= addr + 1'd1;
+			rclk <= ~rclk;
 		end
 
       // expose file (menu) index
@@ -471,21 +507,24 @@ always@(posedge SPI_SCK, posedge SPI_SS2) begin
 	end
 end
 
-assign ioctl_wr = |ioctl_wrd;
-reg [1:0] ioctl_wrd;
-
-always@(negedge clk_sys) begin
+// transfer to ioctl_clk domain.
+// ioctl_index is set before ioctl_download, so it's stable already
+always@(posedge clk_sys) begin
 	reg        rclkD, rclkD2;
 
-	rclkD    <= rclk;
-	rclkD2   <= rclkD;
-	ioctl_wrd<= {ioctl_wrd[0],1'b0};
+	if(ioctl_ce) begin
+		ioctl_download <= rdownload;
 
-	if(rclkD & ~rclkD2) begin
-		ioctl_dout <= data_w;
-		ioctl_addr <= addr_w;
-		ioctl_wrd  <= 2'b11;
+		rclkD    <= rclk;
+		rclkD2   <= rclkD;
+		ioctl_wr <= 0;
+
+		if(rclkD != rclkD2) begin
+			ioctl_dout <= data_w;
+			ioctl_addr <= addr_w;
+			ioctl_wr   <= 1;
+		end
 	end
 end
 
-endmodule
+endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/mist_pll_12M_14M.vhd b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/mist_pll_12M_14M.vhd
deleted file mode 100644
index 4865e696..00000000
--- a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/mist_pll_12M_14M.vhd	
+++ /dev/null
@@ -1,424 +0,0 @@
--- megafunction wizard: %ALTPLL%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: altpll 
-
--- ============================================================
--- File Name: mist_pll_12M_14M.vhd
--- Megafunction Name(s):
--- 			altpll
---
--- Simulation Library Files(s):
--- 			altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 13.1.0 Build 162 10/23/2013 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.all;
-
-ENTITY mist_pll_12M_14M IS
-	PORT
-	(
-		inclk0		: IN STD_LOGIC  := '0';
-		c0		: OUT STD_LOGIC ;
-		c1		: OUT STD_LOGIC ;
-		c2		: OUT STD_LOGIC ;
-		locked		: OUT STD_LOGIC 
-	);
-END mist_pll_12M_14M;
-
-
-ARCHITECTURE SYN OF mist_pll_12m_14m IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC ;
-	SIGNAL sub_wire2	: STD_LOGIC ;
-	SIGNAL sub_wire3	: STD_LOGIC ;
-	SIGNAL sub_wire4	: STD_LOGIC ;
-	SIGNAL sub_wire5	: STD_LOGIC ;
-	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
-	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
-	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
-
-
-
-	COMPONENT altpll
-	GENERIC (
-		bandwidth_type		: STRING;
-		clk0_divide_by		: NATURAL;
-		clk0_duty_cycle		: NATURAL;
-		clk0_multiply_by		: NATURAL;
-		clk0_phase_shift		: STRING;
-		clk1_divide_by		: NATURAL;
-		clk1_duty_cycle		: NATURAL;
-		clk1_multiply_by		: NATURAL;
-		clk1_phase_shift		: STRING;
-		clk2_divide_by		: NATURAL;
-		clk2_duty_cycle		: NATURAL;
-		clk2_multiply_by		: NATURAL;
-		clk2_phase_shift		: STRING;
-		compensate_clock		: STRING;
-		inclk0_input_frequency		: NATURAL;
-		intended_device_family		: STRING;
-		lpm_hint		: STRING;
-		lpm_type		: STRING;
-		operation_mode		: STRING;
-		pll_type		: STRING;
-		port_activeclock		: STRING;
-		port_areset		: STRING;
-		port_clkbad0		: STRING;
-		port_clkbad1		: STRING;
-		port_clkloss		: STRING;
-		port_clkswitch		: STRING;
-		port_configupdate		: STRING;
-		port_fbin		: STRING;
-		port_inclk0		: STRING;
-		port_inclk1		: STRING;
-		port_locked		: STRING;
-		port_pfdena		: STRING;
-		port_phasecounterselect		: STRING;
-		port_phasedone		: STRING;
-		port_phasestep		: STRING;
-		port_phaseupdown		: STRING;
-		port_pllena		: STRING;
-		port_scanaclr		: STRING;
-		port_scanclk		: STRING;
-		port_scanclkena		: STRING;
-		port_scandata		: STRING;
-		port_scandataout		: STRING;
-		port_scandone		: STRING;
-		port_scanread		: STRING;
-		port_scanwrite		: STRING;
-		port_clk0		: STRING;
-		port_clk1		: STRING;
-		port_clk2		: STRING;
-		port_clk3		: STRING;
-		port_clk4		: STRING;
-		port_clk5		: STRING;
-		port_clkena0		: STRING;
-		port_clkena1		: STRING;
-		port_clkena2		: STRING;
-		port_clkena3		: STRING;
-		port_clkena4		: STRING;
-		port_clkena5		: STRING;
-		port_extclk0		: STRING;
-		port_extclk1		: STRING;
-		port_extclk2		: STRING;
-		port_extclk3		: STRING;
-		self_reset_on_loss_lock		: STRING;
-		width_clock		: NATURAL
-	);
-	PORT (
-			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
-			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-			locked	: OUT STD_LOGIC 
-	);
-	END COMPONENT;
-
-BEGIN
-	sub_wire7_bv(0 DOWNTO 0) <= "0";
-	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
-	sub_wire4    <= sub_wire0(2);
-	sub_wire3    <= sub_wire0(0);
-	sub_wire1    <= sub_wire0(1);
-	c1    <= sub_wire1;
-	locked    <= sub_wire2;
-	c0    <= sub_wire3;
-	c2    <= sub_wire4;
-	sub_wire5    <= inclk0;
-	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
-
-	altpll_component : altpll
-	GENERIC MAP (
-		bandwidth_type => "AUTO",
-		clk0_divide_by => 420,
-		clk0_duty_cycle => 50,
-		clk0_multiply_by => 191,
-		clk0_phase_shift => "0",
-		clk1_divide_by => 360,
-		clk1_duty_cycle => 50,
-		clk1_multiply_by => 191,
-		clk1_phase_shift => "0",
-		clk2_divide_by => 105,
-		clk2_duty_cycle => 50,
-		clk2_multiply_by => 191,
-		clk2_phase_shift => "0",
-		compensate_clock => "CLK0",
-		inclk0_input_frequency => 37037,
-		intended_device_family => "Cyclone III",
-		lpm_hint => "CBX_MODULE_PREFIX=mist_pll_12M_14M",
-		lpm_type => "altpll",
-		operation_mode => "NORMAL",
-		pll_type => "AUTO",
-		port_activeclock => "PORT_UNUSED",
-		port_areset => "PORT_UNUSED",
-		port_clkbad0 => "PORT_UNUSED",
-		port_clkbad1 => "PORT_UNUSED",
-		port_clkloss => "PORT_UNUSED",
-		port_clkswitch => "PORT_UNUSED",
-		port_configupdate => "PORT_UNUSED",
-		port_fbin => "PORT_UNUSED",
-		port_inclk0 => "PORT_USED",
-		port_inclk1 => "PORT_UNUSED",
-		port_locked => "PORT_USED",
-		port_pfdena => "PORT_UNUSED",
-		port_phasecounterselect => "PORT_UNUSED",
-		port_phasedone => "PORT_UNUSED",
-		port_phasestep => "PORT_UNUSED",
-		port_phaseupdown => "PORT_UNUSED",
-		port_pllena => "PORT_UNUSED",
-		port_scanaclr => "PORT_UNUSED",
-		port_scanclk => "PORT_UNUSED",
-		port_scanclkena => "PORT_UNUSED",
-		port_scandata => "PORT_UNUSED",
-		port_scandataout => "PORT_UNUSED",
-		port_scandone => "PORT_UNUSED",
-		port_scanread => "PORT_UNUSED",
-		port_scanwrite => "PORT_UNUSED",
-		port_clk0 => "PORT_USED",
-		port_clk1 => "PORT_USED",
-		port_clk2 => "PORT_USED",
-		port_clk3 => "PORT_UNUSED",
-		port_clk4 => "PORT_UNUSED",
-		port_clk5 => "PORT_UNUSED",
-		port_clkena0 => "PORT_UNUSED",
-		port_clkena1 => "PORT_UNUSED",
-		port_clkena2 => "PORT_UNUSED",
-		port_clkena3 => "PORT_UNUSED",
-		port_clkena4 => "PORT_UNUSED",
-		port_clkena5 => "PORT_UNUSED",
-		port_extclk0 => "PORT_UNUSED",
-		port_extclk1 => "PORT_UNUSED",
-		port_extclk2 => "PORT_UNUSED",
-		port_extclk3 => "PORT_UNUSED",
-		self_reset_on_loss_lock => "OFF",
-		width_clock => 5
-	)
-	PORT MAP (
-		inclk => sub_wire6,
-		clk => sub_wire0,
-		locked => sub_wire2
-	);
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
--- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
--- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
--- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
--- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
--- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
--- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
--- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
--- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
--- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
--- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "420"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "360"
--- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "105"
--- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "12.278571"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "14.325000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "49.114285"
--- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
--- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
--- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
--- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
--- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
--- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
--- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
--- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
--- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "191"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "191"
--- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "191"
--- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "12.28800000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "14.31800000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "49.15200000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
--- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
--- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
--- Retrieval info: PRIVATE: RECONFIG_FILE STRING "mist_pll_12M_14M.mif"
--- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
--- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
--- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
--- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
--- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
--- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
--- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
--- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
--- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
--- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
--- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
--- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "420"
--- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "191"
--- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "360"
--- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "191"
--- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "105"
--- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "191"
--- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
--- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
--- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
--- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
--- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
--- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
--- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
--- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
--- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
--- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
--- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
--- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
--- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
--- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
--- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
--- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL mist_pll_12M_14M.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL mist_pll_12M_14M.ppf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL mist_pll_12M_14M.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL mist_pll_12M_14M.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL mist_pll_12M_14M.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL mist_pll_12M_14M_inst.vhd FALSE
--- Retrieval info: LIB_FILE: altera_mf
--- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/osd.v b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/osd.v
index c62c10af..b9181763 100644
--- a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/osd.v	
+++ b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/osd.v	
@@ -11,13 +11,15 @@ module osd (
 	input        SPI_SS3,
 	input        SPI_DI,
 
+	input  [1:0] rotate, //[0] - rotate [1] - left or right
+
 	// VGA signals coming from core
 	input  [5:0] R_in,
 	input  [5:0] G_in,
 	input  [5:0] B_in,
 	input        HSync,
 	input        VSync,
-	
+
 	// VGA signals going to video connector
 	output [5:0] R_out,
 	output [5:0] G_out,
@@ -59,7 +61,7 @@ always@(posedge SPI_SCK, posedge SPI_SS3) begin
 
 		if(cnt == 7) begin
 			cmd <= {sbuf[6:0], SPI_DI};
-      
+
 			// lower three command bits are line address
 			bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
 
@@ -91,7 +93,7 @@ reg  [9:0] vs_low, vs_high;
 wire       vs_pol = vs_high < vs_low;
 wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
 
-wire doublescan = (dsp_height>350); 
+wire doublescan = (dsp_height>350);
 
 reg ce_pix;
 always @(negedge clk_sys) begin
@@ -124,13 +126,13 @@ always @(posedge clk_sys) begin
 		hsD2 <= hsD;
 
 		// falling edge of HSync
-		if(!hsD && hsD2) begin	
+		if(!hsD && hsD2) begin
 			h_cnt <= 0;
 			hs_high <= h_cnt;
 		end
 
 		// rising edge of HSync
-		else if(hsD && !hsD2) begin	
+		else if(hsD && !hsD2) begin
 			h_cnt <= 0;
 			hs_low <= h_cnt;
 			v_cnt <= v_cnt + 1'd1;
@@ -142,13 +144,13 @@ always @(posedge clk_sys) begin
 		vsD2 <= vsD;
 
 		// falling edge of VSync
-		if(!vsD && vsD2) begin	
+		if(!vsD && vsD2) begin
 			v_cnt <= 0;
 			vs_high <= v_cnt;
 		end
 
 		// rising edge of VSync
-		else if(vsD && !vsD2) begin	
+		else if(vsD && !vsD2) begin
 			v_cnt <= 0;
 			vs_low <= v_cnt;
 		end
@@ -160,17 +162,30 @@ wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
 wire [9:0] h_osd_end   = h_osd_start + OSD_WIDTH;
 wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
 wire [9:0] v_osd_end   = v_osd_start + (OSD_HEIGHT<<doublescan);
-wire [9:0] osd_hcnt    = h_cnt - h_osd_start + 1'd1;  // one pixel offset for osd_byte register
+wire [9:0] osd_hcnt    = h_cnt - h_osd_start;
 wire [9:0] osd_vcnt    = v_cnt - v_osd_start;
+wire [9:0] osd_hcnt_next  = osd_hcnt + 2'd1;  // one pixel offset for osd pixel
+wire [9:0] osd_hcnt_next2 = osd_hcnt + 2'd2;  // two pixel offset for osd byte address register
 
-wire osd_de = osd_enable && 
+wire osd_de = osd_enable &&
               (HSync != hs_pol) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
               (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
 
-reg  [7:0] osd_byte; 
-always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}];
+reg [10:0] osd_buffer_addr;
+wire [7:0] osd_byte = osd_buffer[osd_buffer_addr];
+reg        osd_pixel;
 
-wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
+always @(posedge clk_sys) begin
+    if(ce_pix) begin
+		osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5],
+		                                rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) :
+										            (doublescan ?  osd_vcnt[7:0]  : {osd_vcnt[6:0], 1'b0})} :
+		                               {doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]};
+
+		osd_pixel <= rotate[0]  ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] :
+		                          osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
+	end
+end
 
 assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
 assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};
diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/pll.ppf b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/pll.ppf
new file mode 100644
index 00000000..53102b77
--- /dev/null
+++ b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/pll.ppf	
@@ -0,0 +1,13 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="pll" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="areset" direction="input" scope="external"  />
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+<pin name="c2" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>
diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/mist_pll_12M_14M.qip b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/pll.qip
similarity index 57%
rename from Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/mist_pll_12M_14M.qip
rename to Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/pll.qip
index 02816126..afd958be 100644
--- a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/mist_pll_12M_14M.qip	
+++ b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/pll.qip	
@@ -1,4 +1,4 @@
 set_global_assignment -name IP_TOOL_NAME "ALTPLL"
 set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "mist_pll_12M_14M.vhd"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "mist_pll_12M_14M.ppf"]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/pll.v b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/pll.v
new file mode 100644
index 00000000..99e50db7
--- /dev/null
+++ b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/pll.v	
@@ -0,0 +1,376 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: pll.v
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.4 Build 182 03/12/2014 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2014 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module pll (
+	areset,
+	inclk0,
+	c0,
+	c1,
+	c2,
+	locked);
+
+	input	  areset;
+	input	  inclk0;
+	output	  c0;
+	output	  c1;
+	output	  c2;
+	output	  locked;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri0	  areset;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [4:0] sub_wire0;
+	wire  sub_wire2;
+	wire [0:0] sub_wire7 = 1'h0;
+	wire [2:2] sub_wire4 = sub_wire0[2:2];
+	wire [0:0] sub_wire3 = sub_wire0[0:0];
+	wire [1:1] sub_wire1 = sub_wire0[1:1];
+	wire  c1 = sub_wire1;
+	wire  locked = sub_wire2;
+	wire  c0 = sub_wire3;
+	wire  c2 = sub_wire4;
+	wire  sub_wire5 = inclk0;
+	wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
+
+	altpll	altpll_component (
+				.areset (areset),
+				.inclk (sub_wire6),
+				.clk (sub_wire0),
+				.locked (sub_wire2),
+				.activeclock (),
+				.clkbad (),
+				.clkena ({6{1'b1}}),
+				.clkloss (),
+				.clkswitch (1'b0),
+				.configupdate (1'b0),
+				.enable0 (),
+				.enable1 (),
+				.extclk (),
+				.extclkena ({4{1'b1}}),
+				.fbin (1'b1),
+				.fbmimicbidir (),
+				.fbout (),
+				.fref (),
+				.icdrclk (),
+				.pfdena (1'b1),
+				.phasecounterselect ({4{1'b1}}),
+				.phasedone (),
+				.phasestep (1'b1),
+				.phaseupdown (1'b1),
+				.pllena (1'b1),
+				.scanaclr (1'b0),
+				.scanclk (1'b0),
+				.scanclkena (1'b1),
+				.scandata (1'b0),
+				.scandataout (),
+				.scandone (),
+				.scanread (1'b0),
+				.scanwrite (1'b0),
+				.sclkout0 (),
+				.sclkout1 (),
+				.vcooverrange (),
+				.vcounderrange ());
+	defparam
+		altpll_component.bandwidth_type = "AUTO",
+		altpll_component.clk0_divide_by = 78,
+		altpll_component.clk0_duty_cycle = 50,
+		altpll_component.clk0_multiply_by = 71,
+		altpll_component.clk0_phase_shift = "0",
+		altpll_component.clk1_divide_by = 134,
+		altpll_component.clk1_duty_cycle = 50,
+		altpll_component.clk1_multiply_by = 71,
+		altpll_component.clk1_phase_shift = "0",
+		altpll_component.clk2_divide_by = 156,
+		altpll_component.clk2_duty_cycle = 50,
+		altpll_component.clk2_multiply_by = 71,
+		altpll_component.clk2_phase_shift = "0",
+		altpll_component.compensate_clock = "CLK0",
+		altpll_component.inclk0_input_frequency = 37037,
+		altpll_component.intended_device_family = "Cyclone III",
+		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
+		altpll_component.lpm_type = "altpll",
+		altpll_component.operation_mode = "NORMAL",
+		altpll_component.pll_type = "AUTO",
+		altpll_component.port_activeclock = "PORT_UNUSED",
+		altpll_component.port_areset = "PORT_USED",
+		altpll_component.port_clkbad0 = "PORT_UNUSED",
+		altpll_component.port_clkbad1 = "PORT_UNUSED",
+		altpll_component.port_clkloss = "PORT_UNUSED",
+		altpll_component.port_clkswitch = "PORT_UNUSED",
+		altpll_component.port_configupdate = "PORT_UNUSED",
+		altpll_component.port_fbin = "PORT_UNUSED",
+		altpll_component.port_inclk0 = "PORT_USED",
+		altpll_component.port_inclk1 = "PORT_UNUSED",
+		altpll_component.port_locked = "PORT_USED",
+		altpll_component.port_pfdena = "PORT_UNUSED",
+		altpll_component.port_phasecounterselect = "PORT_UNUSED",
+		altpll_component.port_phasedone = "PORT_UNUSED",
+		altpll_component.port_phasestep = "PORT_UNUSED",
+		altpll_component.port_phaseupdown = "PORT_UNUSED",
+		altpll_component.port_pllena = "PORT_UNUSED",
+		altpll_component.port_scanaclr = "PORT_UNUSED",
+		altpll_component.port_scanclk = "PORT_UNUSED",
+		altpll_component.port_scanclkena = "PORT_UNUSED",
+		altpll_component.port_scandata = "PORT_UNUSED",
+		altpll_component.port_scandataout = "PORT_UNUSED",
+		altpll_component.port_scandone = "PORT_UNUSED",
+		altpll_component.port_scanread = "PORT_UNUSED",
+		altpll_component.port_scanwrite = "PORT_UNUSED",
+		altpll_component.port_clk0 = "PORT_USED",
+		altpll_component.port_clk1 = "PORT_USED",
+		altpll_component.port_clk2 = "PORT_USED",
+		altpll_component.port_clk3 = "PORT_UNUSED",
+		altpll_component.port_clk4 = "PORT_UNUSED",
+		altpll_component.port_clk5 = "PORT_UNUSED",
+		altpll_component.port_clkena0 = "PORT_UNUSED",
+		altpll_component.port_clkena1 = "PORT_UNUSED",
+		altpll_component.port_clkena2 = "PORT_UNUSED",
+		altpll_component.port_clkena3 = "PORT_UNUSED",
+		altpll_component.port_clkena4 = "PORT_UNUSED",
+		altpll_component.port_clkena5 = "PORT_UNUSED",
+		altpll_component.port_extclk0 = "PORT_UNUSED",
+		altpll_component.port_extclk1 = "PORT_UNUSED",
+		altpll_component.port_extclk2 = "PORT_UNUSED",
+		altpll_component.port_extclk3 = "PORT_UNUSED",
+		altpll_component.self_reset_on_loss_lock = "OFF",
+		altpll_component.width_clock = 5;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "78"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "134"
+// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "156"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.576923"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "14.305970"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.288462"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "71"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "71"
+// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "71"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.57627100"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "14.31800000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.28800000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "78"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "71"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "134"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "71"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "156"
+// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "71"
+// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/time_pilot.vhd b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/time_pilot.vhd
index 7ec1d6d4..62cf1974 100644
--- a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/time_pilot.vhd	
+++ b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/time_pilot.vhd	
@@ -84,8 +84,6 @@ port(
 	clock_12     : in std_logic;
 	clock_14     : in std_logic;
 	reset        : in std_logic;
-
-	-- tv15Khz_mode : in std_logic;
 	video_r        : out std_logic_vector(4 downto 0);
 	video_g        : out std_logic_vector(4 downto 0);
 	video_b        : out std_logic_vector(4 downto 0);
diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/video_mixer.sv b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/video_mixer.sv
index 04cfd4ba..79d8ca03 100644
--- a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/video_mixer.sv	
+++ b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/video_mixer.sv	
@@ -20,8 +20,8 @@
 
 module video_mixer
 #(
-	parameter LINE_LENGTH  = 768,
-	parameter HALF_DEPTH   = 0,
+	parameter LINE_LENGTH  = 480,
+	parameter HALF_DEPTH   = 1,
 
 	parameter OSD_COLOR    = 3'd4,
 	parameter OSD_X_OFFSET = 10'd0,
@@ -50,7 +50,7 @@ module video_mixer
 	input  [1:0] scanlines,
 
 	// 0 = HVSync 31KHz, 1 = CSync 15KHz
-	input        scandoubler_disable,
+	input        scandoublerD,
 
 	// High quality 2x scaling
 	input        hq2x,
@@ -60,7 +60,7 @@ module video_mixer
 
 	// 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space)
 	input        ypbpr_full,
-
+	input  [1:0] rotate, //[0] - rotate [1] - left or right
 	// color
 	input [DWIDTH:0] R,
 	input [DWIDTH:0] G,
@@ -113,9 +113,9 @@ scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler
 	.b_out(B_sd)
 );
 
-wire [DWIDTH:0] rt  = (scandoubler_disable ? R : R_sd);
-wire [DWIDTH:0] gt  = (scandoubler_disable ? G : G_sd);
-wire [DWIDTH:0] bt  = (scandoubler_disable ? B : B_sd);
+wire [DWIDTH:0] rt  = (scandoublerD ? R : R_sd);
+wire [DWIDTH:0] gt  = (scandoublerD ? G : G_sd);
+wire [DWIDTH:0] bt  = (scandoublerD ? B : B_sd);
 
 generate
 	if(HALF_DEPTH) begin
@@ -129,8 +129,8 @@ generate
 	end
 endgenerate
 
-wire       hs = (scandoubler_disable ? HSync : hs_sd);
-wire       vs = (scandoubler_disable ? VSync : vs_sd);
+wire       hs = (scandoublerD ? HSync : hs_sd);
+wire       vs = (scandoublerD ? VSync : vs_sd);
 
 reg scanline = 0;
 always @(posedge clk_sys) begin
@@ -182,6 +182,7 @@ osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd
 	.B_in(b_out),
 	.HSync(hs),
 	.VSync(vs),
+	.rotate(rotate),
 
 	.R_out(red),
 	.G_out(green),
@@ -236,7 +237,7 @@ wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[1
 assign VGA_R  = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) :   red;
 assign VGA_G  = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] :  y[7:2]) : green;
 assign VGA_B  = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) :  blue;
-assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd;
-assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd;
+assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd;
+assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd;
 
 endmodule
diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/time_pilot_mist.qsf b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/time_pilot_mist.qsf
index 91879fd5..b903f7cd 100644
--- a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/time_pilot_mist.qsf	
+++ b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/time_pilot_mist.qsf	
@@ -1,6 +1,6 @@
 # -------------------------------------------------------------------------- #
 #
-# Copyright (C) 1991-2013 Altera Corporation
+# Copyright (C) 1991-2014 Altera Corporation
 # Your use of Altera Corporation's design tools, logic functions 
 # and other software and tools, and its AMPP partner logic 
 # functions, and any output files from any of the foregoing 
@@ -17,8 +17,8 @@
 # -------------------------------------------------------------------------- #
 #
 # Quartus II 64-Bit
-# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-# Date created = 14:18:08  November 05, 2017
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 17:50:10  March 09, 2019
 #
 # -------------------------------------------------------------------------- #
 #
@@ -43,53 +43,39 @@ set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:45:13 JUNE 17,2016"
 set_global_assignment -name LAST_QUARTUS_VERSION 13.1
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name TOP_LEVEL_ENTITY time_pilot_mist
-
-# Classic Timing Assignments
-# ==========================
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
 set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
-# Analysis & Synthesis Assignments
-# ================================
-set_global_assignment -name FAMILY "Cyclone III"
-
-# Fitter Assignments
-# ==================
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
-set_global_assignment -name DEVICE EP3C25E144C8
-set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
-set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
-set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
-
-# EDA Netlist Writer Assignments
-# ==============================
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
-
-# Assembler Assignments
-# =====================
-set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
-set_global_assignment -name GENERATE_RBF_FILE ON
-
-# SignalTap II Assignments
-# ========================
-set_global_assignment -name ENABLE_SIGNALTAP OFF
-set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp
-
-# Power Estimation Assignments
-# ============================
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-
-
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/TimePilot_MiST.sv
+set_global_assignment -name VHDL_FILE rtl/time_pilot.vhd
+set_global_assignment -name VHDL_FILE rtl/time_pilot_sprite_grphx.vhd
+set_global_assignment -name VHDL_FILE rtl/time_pilot_sprite_color_lut.vhd
+set_global_assignment -name VHDL_FILE rtl/time_pilot_sound_prog.vhd
+set_global_assignment -name VHDL_FILE rtl/time_pilot_sound_board.vhd
+set_global_assignment -name VHDL_FILE rtl/time_pilot_prog.vhd
+set_global_assignment -name VHDL_FILE rtl/time_pilot_palette_green_red.vhd
+set_global_assignment -name VHDL_FILE rtl/time_pilot_palette_blue_green.vhd
+set_global_assignment -name VHDL_FILE rtl/time_pilot_char_grphx.vhd
+set_global_assignment -name VHDL_FILE rtl/time_pilot_char_color_lut.vhd
+set_global_assignment -name VHDL_FILE rtl/gen_video.vhd
+set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
+set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80se.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
+set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
+set_global_assignment -name VERILOG_FILE rtl/pll.v
+set_global_assignment -name VERILOG_FILE rtl/osd.v
+set_global_assignment -name VERILOG_FILE rtl/mist_io.v
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
+set_global_assignment -name VHDL_FILE rtl/dac.vhd
 
+# Pin & Location Assignments
+# ==========================
 set_location_assignment PIN_7 -to LED
 set_location_assignment PIN_54 -to CLOCK_27
 set_location_assignment PIN_144 -to VGA_R[5]
@@ -121,47 +107,77 @@ set_location_assignment PIN_127 -to SPI_SS2
 set_location_assignment PIN_91 -to SPI_SS3
 set_location_assignment PIN_13 -to CONF_DATA0
 
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
 
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name TOP_LEVEL_ENTITY TimePilot_MiST
+set_global_assignment -name FAMILY "Cyclone III"
 
+# Fitter Assignments
+# ==================
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
 set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
 set_global_assignment -name ENABLE_NCE_PIN OFF
+
+# EDA Netlist Writer Assignments
+# ==============================
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+
+# SignalTap II Assignments
+# ========================
+set_global_assignment -name ENABLE_SIGNALTAP OFF
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp
+
+# Power Estimation Assignments
+# ============================
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# Advanced I/O Timing Assignments
+# ===============================
 set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
 set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
 set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
 set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name VHDL_FILE rtl/time_pilot_mist.vhd
-set_global_assignment -name VHDL_FILE rtl/time_pilot.vhd
-set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
-set_global_assignment -name VHDL_FILE rtl/time_pilot_sprite_grphx.vhd
-set_global_assignment -name VHDL_FILE rtl/time_pilot_sprite_color_lut.vhd
-set_global_assignment -name VHDL_FILE rtl/time_pilot_sound_prog.vhd
-set_global_assignment -name VHDL_FILE rtl/time_pilot_sound_board.vhd
-set_global_assignment -name VHDL_FILE rtl/time_pilot_prog.vhd
-set_global_assignment -name VHDL_FILE rtl/time_pilot_palette_green_red.vhd
-set_global_assignment -name VHDL_FILE rtl/time_pilot_palette_blue_green.vhd
-set_global_assignment -name VHDL_FILE rtl/time_pilot_char_grphx.vhd
-set_global_assignment -name VHDL_FILE rtl/time_pilot_char_color_lut.vhd
-set_global_assignment -name VHDL_FILE rtl/T8080se.vhd
-set_global_assignment -name VHDL_FILE rtl/T80se.vhd
-set_global_assignment -name VHDL_FILE rtl/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/T80.vhd
-set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
-set_global_assignment -name VERILOG_FILE rtl/osd.v
-set_global_assignment -name QIP_FILE rtl/mist_pll_12M_14M.qip
-set_global_assignment -name VERILOG_FILE rtl/mist_io.v
-set_global_assignment -name VERILOG_FILE rtl/keyboard.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
-set_global_assignment -name VHDL_FILE rtl/gen_video.vhd
-set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
-set_global_assignment -name VHDL_FILE rtl/dac.vhd
 
-set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
+# ----------------------------
+# start ENTITY(TimePilot_MiST)
 
+	# start DESIGN_PARTITION(Top)
+	# ---------------------------
+
+		# Incremental Compilation Assignments
+		# ===================================
+		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+	# end DESIGN_PARTITION(Top)
+	# -------------------------
+
+# end ENTITY(TimePilot_MiST)
+# --------------------------
+set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file