From 6f0c1dec2b5b80b3d954981f072508e6efc7a5dd Mon Sep 17 00:00:00 2001 From: Gyorgy Szombathelyi Date: Wed, 31 Mar 2021 19:27:12 +0200 Subject: [PATCH] MCR1: add NVRAM save support --- Arcade_MiST/Midway MCR 1/rtl/MCR1_MiST.sv | 14 ++++-- Arcade_MiST/Midway MCR 1/rtl/cmos_ram.vhd | 59 ++++++++++++++--------- Arcade_MiST/Midway MCR 1/rtl/kick.vhd | 19 +++++--- 3 files changed, 59 insertions(+), 33 deletions(-) diff --git a/Arcade_MiST/Midway MCR 1/rtl/MCR1_MiST.sv b/Arcade_MiST/Midway MCR 1/rtl/MCR1_MiST.sv index 2b1ce657..e0cfd932 100644 --- a/Arcade_MiST/Midway MCR 1/rtl/MCR1_MiST.sv +++ b/Arcade_MiST/Midway MCR 1/rtl/MCR1_MiST.sv @@ -57,6 +57,7 @@ localparam CONF_STR = { "O5,Blend,Off,On;", "DIP;", "O6,Service,Off,On;", + "R2048,Save NVRAM;", "T0,Reset;", "V,v1.1.",`BUILD_DATE }; @@ -163,10 +164,12 @@ wire [15:0] rom_do; wire [13:0] snd_addr; wire [15:0] snd_do; wire ioctl_downl; +wire ioctl_upl; wire [7:0] ioctl_index; wire ioctl_wr; wire [24:0] ioctl_addr; wire [7:0] ioctl_dout; +wire [7:0] ioctl_din; /* ROM structure 00000-07FFF CPU1 @@ -179,11 +182,14 @@ data_io data_io( .SPI_SCK ( SPI_SCK ), .SPI_SS2 ( SPI_SS2 ), .SPI_DI ( SPI_DI ), + .SPI_DO ( SPI_DO ), .ioctl_download( ioctl_downl ), + .ioctl_upload ( ioctl_upl ), .ioctl_index ( ioctl_index ), .ioctl_wr ( ioctl_wr ), .ioctl_addr ( ioctl_addr ), - .ioctl_dout ( ioctl_dout ) + .ioctl_dout ( ioctl_dout ), + .ioctl_din ( ioctl_din ) ); reg port1_req, port2_req; @@ -222,7 +228,7 @@ always @(posedge clk_sys) begin ioctl_wr_last <= ioctl_wr; if (ioctl_downl) begin - if (~ioctl_wr_last && ioctl_wr) begin + if (~ioctl_wr_last && ioctl_wr && ioctl_index == 0) begin port1_req <= ~port1_req; port2_req <= ~port2_req; end @@ -278,7 +284,9 @@ kick kick( .dl_addr ( dl_addr[16:0] ), .dl_data ( ioctl_dout ), - .dl_wr ( ioctl_wr ) + .dl_wr ( ioctl_wr && ioctl_index == 0 ), + .up_data ( ioctl_din ), + .cmos_wr ( ioctl_wr && ioctl_index == 8'hff ) ); wire vs_out; diff --git a/Arcade_MiST/Midway MCR 1/rtl/cmos_ram.vhd b/Arcade_MiST/Midway MCR 1/rtl/cmos_ram.vhd index c5e34893..828e0292 100644 --- a/Arcade_MiST/Midway MCR 1/rtl/cmos_ram.vhd +++ b/Arcade_MiST/Midway MCR 1/rtl/cmos_ram.vhd @@ -32,11 +32,16 @@ entity cmos_ram is aWidth : integer := 10 ); port ( - clk : in std_logic; - we : in std_logic; - addr : in std_logic_vector((aWidth-1) downto 0); - d : in std_logic_vector((dWidth-1) downto 0); - q : out std_logic_vector((dWidth-1) downto 0) + clk_a : in std_logic; + we_a : in std_logic; + addr_a : in std_logic_vector((aWidth-1) downto 0); + d_a : in std_logic_vector((dWidth-1) downto 0); + q_a : out std_logic_vector((dWidth-1) downto 0); + clk_b : in std_logic; + we_b : in std_logic; + addr_b : in std_logic_vector((aWidth-1) downto 0); + d_b : in std_logic_vector((dWidth-1) downto 0); + q_b : out std_logic_vector((dWidth-1) downto 0) ); end entity; @@ -319,38 +324,44 @@ architecture rtl of cmos_ram is -- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF" --FF0-FFF ); - signal rAddrReg : std_logic_vector((aWidth-1) downto 0); - signal qReg : std_logic_vector((dWidth-1) downto 0); begin --- ----------------------------------------------------------------------- --- Signals to entity interface --- ----------------------------------------------------------------------- --- q <= qReg; -- ----------------------------------------------------------------------- -- Memory write -- ----------------------------------------------------------------------- - process(clk) + process(clk_a) begin - if rising_edge(clk) then - if we = '1' then - ram(to_integer(unsigned(addr))) <= d; + if rising_edge(clk_a) then + if we_a = '1' then + ram(to_integer(unsigned(addr_a))) <= d_a; end if; end if; end process; - + + process(clk_b) + begin + if rising_edge(clk_b) then + if we_b = '1' then + ram(to_integer(unsigned(addr_b))) <= d_b; + end if; + end if; + end process; + -- ----------------------------------------------------------------------- -- Memory read -- ----------------------------------------------------------------------- -process(clk) + process(clk_a) begin - if rising_edge(clk) then --- qReg <= ram(to_integer(unsigned(rAddrReg))); --- rAddrReg <= addr; ----- qReg <= ram(to_integer(unsigned(addr))); - q <= ram(to_integer(unsigned(addr))); + if rising_edge(clk_a) then + q_a <= ram(to_integer(unsigned(addr_a))); end if; end process; ---q <= ram(to_integer(unsigned(addr))); -end architecture; + process(clk_b) + begin + if rising_edge(clk_b) then + q_b <= ram(to_integer(unsigned(addr_b))); + end if; + end process; + +end architecture; diff --git a/Arcade_MiST/Midway MCR 1/rtl/kick.vhd b/Arcade_MiST/Midway MCR 1/rtl/kick.vhd index 0c082381..0041a2d5 100644 --- a/Arcade_MiST/Midway MCR 1/rtl/kick.vhd +++ b/Arcade_MiST/Midway MCR 1/rtl/kick.vhd @@ -189,7 +189,9 @@ port( dl_addr : in std_logic_vector(16 downto 0); dl_data : in std_logic_vector( 7 downto 0); - dl_wr : in std_logic + dl_wr : in std_logic; + up_data : out std_logic_vector(7 downto 0); + cmos_wr : in std_logic ); end kick; @@ -755,11 +757,16 @@ cpu_rom_rd <= '1' when cpu_mreq_n = '0' and cpu_rd_n = '0' and cpu_addr(15 downt wram : entity work.cmos_ram generic map( dWidth => 8, aWidth => 11) port map( - clk => clock_vidn, - we => wram_we, - addr => cpu_addr(10 downto 0), - d => cpu_do, - q => wram_do + clk_a => clock_vidn, + addr_a => cpu_addr(10 downto 0), + d_a => cpu_do, + we_a => wram_we, + q_a => wram_do, + clk_b => clock_vid, + we_b => cmos_wr, + addr_b => dl_addr(10 downto 0), + d_b => dl_data, + q_b => up_data ); -- video RAM 0xFC00-0xFFFF