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Moon Patrol: give direct E clock to sound board, no need for divider

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This commit is contained in:
Gyorgy Szombathelyi
2019-05-30 18:29:04 +02:00
parent a378fb71ab
commit 729994b5c9
3 changed files with 44 additions and 103 deletions
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70
Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/Clock.vhd
View File

@@ -45,8 +45,7 @@ ENTITY Clock IS
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC
c2 : OUT STD_LOGIC
);
END Clock;
@@ -58,10 +57,9 @@ ARCHITECTURE SYN OF clock IS
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
@@ -80,10 +78,6 @@ ARCHITECTURE SYN OF clock IS
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
clk3_divide_by : NATURAL;
clk3_duty_cycle : NATURAL;
clk3_multiply_by : NATURAL;
clk3_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
@@ -141,23 +135,21 @@ ARCHITECTURE SYN OF clock IS
END COMPONENT;
BEGIN
sub_wire7_bv(0 DOWNTO 0) <= "0";
sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
sub_wire4 <= sub_wire0(2);
sub_wire3 <= sub_wire0(0);
sub_wire2 <= sub_wire0(3);
sub_wire6_bv(0 DOWNTO 0) <= "0";
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
sub_wire3 <= sub_wire0(2);
sub_wire2 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
c3 <= sub_wire2;
c0 <= sub_wire3;
c2 <= sub_wire4;
sub_wire5 <= inclk0;
sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
c0 <= sub_wire2;
c2 <= sub_wire3;
sub_wire4 <= inclk0;
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1350,
clk0_divide_by => 5400,
clk0_duty_cycle => 50,
clk0_multiply_by => 179,
clk0_phase_shift => "0",
@@ -169,10 +161,6 @@ BEGIN
clk2_duty_cycle => 50,
clk2_multiply_by => 8,
clk2_phase_shift => "0",
clk3_divide_by => 208,
clk3_duty_cycle => 50,
clk3_multiply_by => 185,
clk3_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 37037,
intended_device_family => "Cyclone III",
@@ -208,7 +196,7 @@ BEGIN
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_USED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
@@ -224,7 +212,7 @@ BEGIN
width_clock => 5
)
PORT MAP (
inclk => sub_wire6,
inclk => sub_wire5,
clk => sub_wire0
);
@@ -254,15 +242,12 @@ END SYN;
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1396"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "20"
-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "208"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "3.580000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.895000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "6.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "24.014423"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -285,40 +270,32 @@ END SYN;
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "185"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "37"
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "185"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "3.58000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "0.89500000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "6.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "24.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "24.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
@@ -343,23 +320,20 @@ END SYN;
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1350"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5400"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "179"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
@@ -371,10 +345,6 @@ END SYN;
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "8"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "208"
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "185"
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
@@ -409,7 +379,7 @@ END SYN;
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
@@ -428,14 +398,12 @@ END SYN;
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock.inc FALSE

73
Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/moon_patrol_sound_board.vhd
View File

@@ -26,7 +26,7 @@ use ieee.numeric_std.all;
entity moon_patrol_sound_board is
port(
clock_3p58 : in std_logic;
clock_E : in std_logic; -- 3.58 Mhz/4
reset : in std_logic;
select_sound : in std_logic_vector(7 downto 0);
@@ -66,10 +66,6 @@ architecture struct of moon_patrol_sound_board is
end component;
signal reset_n : std_logic;
signal clock_div : std_logic_vector(3 downto 0);
signal cpu_clock_en : std_logic;
signal cpu_clock : std_logic;
signal cpu_addr : std_logic_vector(15 downto 0);
signal cpu_di : std_logic_vector( 7 downto 0);
signal cpu_do : std_logic_vector( 7 downto 0);
@@ -160,22 +156,6 @@ reset_n <= not reset;
dbg_cpu_addr <= cpu_addr;
-- clock divider
process (reset, clock_3p58)
begin
if reset='1' then
clock_div <= (others => '0');
else
if rising_edge(clock_3p58) then
clock_div <= clock_div + '1';
end if;
end if;
end process;
-- cpu_clock is 3.58/4
cpu_clock <= clock_div(1);
cpu_clock_en <= '1' when clock_div(1 downto 0) = "00" else '0';
-- cs
wram_cs <= '1' when cpu_addr(15 downto 7) = X"00"&'1' else '0'; -- 0080-00FF
ports_cs <= '1' when cpu_addr(15 downto 4) = X"000" else '0'; -- 0000-000F
@@ -184,10 +164,10 @@ irqraz_cs <= '1' when cpu_addr(14 downto 12) = "001" else '0'; -- 1000-1FFF
rom_cs <= '1' when cpu_addr(14 downto 12) = "111" else '0'; -- 7000-7FFF / F000-FFFF
-- write enables
wram_we <= '1' when cpu_rw = '0' and cpu_clock = '1' and wram_cs = '1' else '0';
ports_we <= '1' when cpu_rw = '0' and cpu_clock = '1' and ports_cs = '1' else '0';
adpcm_we <= '1' when cpu_rw = '0' and cpu_clock = '1' and adpcm_cs = '1' else '0';
irqraz_we <= '1' when cpu_rw = '0' and cpu_clock = '1' and irqraz_cs = '1' else '0';
wram_we <= '1' when cpu_rw = '0' and wram_cs = '1' else '0';
ports_we <= '1' when cpu_rw = '0' and ports_cs = '1' else '0';
adpcm_we <= '1' when cpu_rw = '0' and adpcm_cs = '1' else '0';
irqraz_we <= '1' when cpu_rw = '0' and irqraz_cs = '1' else '0';
-- mux cpu in data between roms/io/wram
cpu_di <=
@@ -199,22 +179,19 @@ cpu_di <=
rom_do when rom_cs = '1' else X"55";
-- irq to cpu
process (reset, clock_div(0))
variable select_sound_7r : std_logic;
process (reset, clock_E)
begin
if reset='1' then
cpu_irq <= '0';
select_sound_7r := '0';
elsif rising_edge(clock_3p58) then
if clock_div(0) = '1' then --rising_edge(clock_div(0)) then
select_sound_7r <= '0';
elsif rising_edge(clock_E) then
if select_sound_7r = '0' and select_sound(7) = '1' then
cpu_irq <= '1';
end if;
if irqraz_we = '1' then
cpu_irq <= '0';
end if;
select_sound_7r := select_sound(7);
end if;
select_sound_7r <= select_sound(7);
end if;
end process;
@@ -222,22 +199,20 @@ end process;
cpu_nmi <= adpcm_vclk;
-- 6803 ports 1 and 2 (only)
process (reset, clock_div(0))
process (reset, clock_E)
begin
if reset='1' then
port1_ddr <= (others=>'0'); -- port1 set as input
port1_data <= (others=>'0'); -- port1 data set to 0
port2_ddr <= ("11100000"); -- port2 bit 7 to 5 should always remain output to simulate mode data
port2_data <= ("01000000"); -- port2 data bit 7 to 5 set to 2 (for mode 2 at start up)
elsif rising_edge(clock_3p58) then
if clock_div(0) = '1' then --rising_edge(clock_div(0)) then
elsif rising_edge(clock_E) then
if ports_cs = '1' and ports_we = '1' then
if cpu_addr(3 downto 0) = X"0" then port1_ddr <= cpu_do; end if;
if cpu_addr(3 downto 0) = X"1" then port2_ddr <= cpu_do and "11100000"; end if;
if cpu_addr(3 downto 0) = X"2" then port1_data <= cpu_do; end if;
if cpu_addr(3 downto 0) = X"3" then port2_data <= cpu_do; end if;
end if;
end if;
end if;
end process;
@@ -253,21 +228,19 @@ port2_bus <= X"FF";
-- latch adpcm (msm5205) data in
process (reset, clock_div(0))
process (reset, clock_E)
begin
if reset='1' then
adpcm_0_di <= (others=>'0');
elsif rising_edge(clock_3p58) then
if clock_div(0) = '1' then --rising_edge(clock_div(0)) then
elsif rising_edge(clock_E) then
if adpcm_cs = '1' and adpcm_we = '1' then
if cpu_addr(1) = '0' then adpcm_0_di <= cpu_do(3 downto 0); end if;
end if;
end if;
end if;
end process;
-- adcpm clocks and computation -- make 24kHz and vclk 8/6/4kHz
adpcm_clocks : process(clock_3p58, ay1_port_b_do)
adpcm_clocks : process(clock_E, ay1_port_b_do)
variable clock_div_a : integer range 0 to 148 := 0;
variable clock_div_b : integer range 0 to 5 := 0;
variable step : integer range 0 to 48;
@@ -276,8 +249,8 @@ adpcm_clocks : process(clock_3p58, ay1_port_b_do)
variable dn : integer range -32768 to 32767;
variable adpcm_signal_n : integer range -32768 to 32767;
begin
if rising_edge(clock_3p58) then
if clock_div_a = 148 then -- 24kHz
if rising_edge(clock_E) then
if clock_div_a = 37 then -- 24kHz
clock_div_a := 0;
case ay1_port_b_do(3 downto 2) is
@@ -342,7 +315,7 @@ audio_out <= audio(12 downto 1);
-- microprocessor 6800/01/03
main_cpu : entity work.cpu68
port map(
clk => cpu_clock,-- E clock input (falling edge)
clk => clock_E, -- E clock input (falling edge)
rst => reset, -- reset input (active high)
rw => cpu_rw, -- read not write output
vma => open, -- valid memory address (active high)
@@ -360,7 +333,7 @@ port map(
-- cpu program rom
cpu_prog_rom : entity work.moon_patrol_sound_prog
port map(
clk => clock_3p58, -- 3p58/2
clk => clock_E,
addr => cpu_addr(11 downto 0),
data => rom_do
);
@@ -368,7 +341,7 @@ port map(
cpu_ram : entity work.spram
generic map( widthad_a => 7)
port map(
clock => clock_3p58, -- 3p58/2
clock => clock_E,
address => cpu_addr(6 downto 0),
data => cpu_do,
wren => wram_we,
@@ -388,8 +361,8 @@ port map(
ay83910_inst1: YM2149
port map (
CLK => clock_3p58,
CE => cpu_clock_en,
CLK => clock_E,
CE => '1',
RESET => not reset_n,
A8 => '1',
A9_L => port2_data(4),
@@ -417,8 +390,8 @@ port map(
ay83910_inst2: YM2149
port map (
CLK => clock_3p58,
CE => cpu_clock_en,
CLK => clock_E,
CE => '1',
RESET => not reset_n,
A8 => '1',
A9_L => port2_data(3),

4
Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/mpatrol.vhd
View File

@@ -162,7 +162,7 @@ begin
Clock_inst : entity work.Clock
port map (
inclk0 => CLOCK_27,
c0 => clk_aud, -- 3.58
c0 => clk_aud, -- 3.58/4
c1 => clk_sys, -- 6
c2 => clk_vid -- 24
);
@@ -265,7 +265,7 @@ u_keyboard : keyboard
moon_patrol_sound_board : entity work.moon_patrol_sound_board
port map(
clock_3p58 => clk_aud,
clock_E => clk_aud,
reset => clkrst_i.arst,
select_sound => sound_data,
audio_out => audio_out,