diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/OzmaWars.qsf b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/OzmaWars.qsf index cb54b9ca..2ac4728e 100644 --- a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/OzmaWars.qsf +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/OzmaWars.qsf @@ -44,30 +44,6 @@ set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39 NOVEMBER 20, 2 set_global_assignment -name LAST_QUARTUS_VERSION 13.1 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" -set_global_assignment -name SYSTEMVERILOG_FILE rtl/OzmaWars_mist.sv -set_global_assignment -name VHDL_FILE rtl/invaders.vhd -set_global_assignment -name VHDL_FILE rtl/mw8080.vhd -set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/OzmaWars_memory.sv -set_global_assignment -name VHDL_FILE rtl/dac.vhd -set_global_assignment -name VHDL_FILE rtl/sprom.vhd -set_global_assignment -name VHDL_FILE rtl/spram.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd -set_global_assignment -name VHDL_FILE rtl/pll.vhd -set_global_assignment -name QIP_FILE ../../../../common/mist/mist.qip -set_global_assignment -name QIP_FILE "D:/Github/Mist_FPGA/common/mist/mist.qip" -set_global_assignment -name VHDL_FILE rtl/roms/mw01.vhd -set_global_assignment -name VHDL_FILE rtl/roms/mw02.vhd -set_global_assignment -name VHDL_FILE rtl/roms/mw03.vhd -set_global_assignment -name VHDL_FILE rtl/roms/mw04.vhd -set_global_assignment -name VHDL_FILE rtl/roms/mw05.vhd -set_global_assignment -name VHDL_FILE rtl/roms/mw06.vhd -set_global_assignment -name VHDL_FILE rtl/OzmaWars_overlay.vhd # Pin & Location Assignments # ========================== @@ -177,4 +153,27 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" - # end ENTITY(OzmaWars_mist) # ------------------------- +set_global_assignment -name SYSTEMVERILOG_FILE rtl/OzmaWars_mist.sv +set_global_assignment -name VHDL_FILE rtl/invaders.vhd +set_global_assignment -name VHDL_FILE rtl/mw8080.vhd +set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/OzmaWars_memory.sv +set_global_assignment -name VHDL_FILE rtl/OzmaWars_overlay.vhd +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name VHDL_FILE rtl/sprom.vhd +set_global_assignment -name VHDL_FILE rtl/spram.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd +set_global_assignment -name VHDL_FILE rtl/pll.vhd +set_global_assignment -name QIP_FILE ../../../../common/mist/mist.qip +set_global_assignment -name VHDL_FILE rtl/roms/mw01.vhd +set_global_assignment -name VHDL_FILE rtl/roms/mw02.vhd +set_global_assignment -name VHDL_FILE rtl/roms/mw03.vhd +set_global_assignment -name VHDL_FILE rtl/roms/mw04.vhd +set_global_assignment -name VHDL_FILE rtl/roms/mw05.vhd +set_global_assignment -name VHDL_FILE rtl/roms/mw06.vhd set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/Release/OzmaWars.rbf b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/Release/OzmaWars.rbf index e0d58517..b79f4bb3 100644 Binary files a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/Release/OzmaWars.rbf and b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/Release/OzmaWars.rbf differ diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/OzmaWars_overlay.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/OzmaWars_overlay.vhd index 601c1d9b..96f7fa35 100644 --- a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/OzmaWars_overlay.vhd +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/OzmaWars_overlay.vhd @@ -11,6 +11,7 @@ entity OzmaWars_overlay is Rst_n_s : in std_logic; HSync : in std_logic; VSync : in std_logic; + CAB : in std_logic_vector(7 downto 0); O_VIDEO_R : out std_logic; O_VIDEO_G : out std_logic; O_VIDEO_B : out std_logic; @@ -24,11 +25,30 @@ architecture rtl of OzmaWars_overlay is signal HCnt : std_logic_vector(11 downto 0); signal VCnt : std_logic_vector(11 downto 0); signal HSync_t1 : std_logic; + + signal Overlay_A1 : boolean; + signal Overlay_A2 : boolean; + signal Overlay_A3 : boolean; + signal Overlay_A3_VCnt : boolean; + + signal Overlay_B1 : boolean; + signal Overlay_B2 : boolean; + signal Overlay_B2_VCnt : boolean; + signal Overlay_G1 : boolean; - signal Overlay_G2 : boolean; + + signal Overlay_P1 : boolean; + signal Overlay_R1 : boolean; - signal Overlay_G1_VCnt : boolean; + signal Overlay_R2 : boolean; + + signal Overlay_Y1 : boolean; + signal Overlay_Y2 : boolean; + signal Overlay_Y2_VCnt : boolean; + signal VideoRGB : std_logic_vector(2 downto 0); + signal col_data : std_logic_vector(3 downto 0); + begin process (Rst_n_s, Clk) variable cnt : unsigned(3 downto 0); @@ -51,10 +71,28 @@ begin HCnt <= (others => '0'); VCnt <= (others => '0'); HSync_t1 <= '0'; - Overlay_G1_VCnt <= false; + + Overlay_A1 <= false; + Overlay_A2 <= false; + Overlay_A3 <= false; + Overlay_A3_VCnt <= false; + + Overlay_B1 <= false; + Overlay_B2 <= false; + Overlay_B2_VCnt <= false; + Overlay_G1 <= false; - Overlay_G2 <= false; + + Overlay_P1 <= false; + Overlay_R1 <= false; + Overlay_R2 <= false; + + Overlay_Y1 <= false; + Overlay_Y2 <= false; + Overlay_Y2_VCnt <= false; + + elsif Clk'event and Clk = '1' then HSync_t1 <= HSync; HStart := (HSync_t1 = '0') and (HSync = '1'); @@ -72,50 +110,111 @@ begin end if; if HStart then - if (Vcnt = x"1F") then - Overlay_G1_VCnt <= true; - elsif (Vcnt = x"95") then - Overlay_G1_VCnt <= false; + if (Vcnt = 0) then + Overlay_A3_VCnt <= true; + elsif (Vcnt = 86) then + Overlay_B2_VCnt <= true; + Overlay_A3_VCnt <= false; + elsif (Vcnt = 168) then + Overlay_Y2_VCnt <= true; + Overlay_B2_VCnt <= false; + elsif (Vcnt = 232) then + Overlay_Y2_VCnt <= false; end if; + end if; + + if (HCnt = 500) and Overlay_A3_VCnt then + Overlay_A3 <= true; + elsif (HCnt = 540) then + Overlay_A3 <= false; + end if; + + if (HCnt = 486) and Overlay_B2_VCnt then + Overlay_B2 <= true; + elsif (HCnt = 540) then + Overlay_B2 <= false; end if; - if (HCnt = x"027") and Overlay_G1_VCnt then - Overlay_G1 <= true; - elsif (HCnt = x"046") then - Overlay_G1 <= false; + if (HCnt = 486) and Overlay_Y2_VCnt then + Overlay_Y2 <= true; + elsif (HCnt = 540) then + Overlay_Y2 <= false; end if; - if (HCnt = x"046") then - Overlay_G2 <= true; - elsif (HCnt = x"0B6") then - Overlay_G2 <= false; - end if; - - if (HCnt = x"1A6") then + if (HCnt = 64) then + Overlay_R2 <= true; + elsif (HCnt = 96) then + Overlay_A2 <= true; + Overlay_R2 <= false; + elsif (HCnt = 120) then + Overlay_A2 <= false; Overlay_R1 <= true; - elsif (HCnt = x"1E6") then + elsif (HCnt = 166) then Overlay_R1 <= false; - end if; - + Overlay_Y1 <= true; + elsif (HCnt = 228) then + Overlay_Y1 <= false; + Overlay_P1 <= true; + elsif (HCnt = 292) then + Overlay_P1 <= false; + Overlay_A1 <= true; + elsif (HCnt = 358) then + Overlay_G1 <= true; + Overlay_A1 <= false; + elsif (HCnt = 430) then + Overlay_G1 <= false; + Overlay_B1 <= true; + elsif (HCnt = 486) then + Overlay_B1 <= false; +-- if Overlay_A3_VCnt then +-- Overlay_A2 <= true; +-- if Overlay_B2_VCnt then +-- Overlay_B2 <= true; +-- if Overlay_Y2_VCnt then +-- Overlay_Y2 <= true; +-- elsif (HCnt = 500) then +-- Overlay_A3 <= false; +-- elsif (HCnt = 540) then +-- Overlay_B2 <= false; +-- Overlay_Y2 <= false; + end if; end if; end process; - p_video_out_comb : process(Video, Overlay_G1, Overlay_G2, Overlay_R1) + p_video_out_comb : process(Video, Overlay_G1, Overlay_B1, Overlay_B2, Overlay_A1, Overlay_A2, Overlay_A3, Overlay_P1, Overlay_Y1, Overlay_Y2, Overlay_R1, Overlay_R2) begin if (Video = '0') then VideoRGB <= "000"; else - if Overlay_G1 or Overlay_G2 then + if Overlay_A1 or Overlay_A2 or Overlay_A3 then--AQUA + VideoRGB <= "011"; + elsif Overlay_B1 or Overlay_B2 then--BLUE + VideoRGB <= "001"; + elsif Overlay_G1 then--GREEN VideoRGB <= "010"; - elsif Overlay_R1 then - VideoRGB <= "100"; - else - VideoRGB <= "111"; + elsif Overlay_P1 then--PINK + VideoRGB <= "101"; + elsif Overlay_R1 or Overlay_R2 then--RED + VideoRGB <= "100"; + elsif Overlay_Y1 or Overlay_Y2 then--YELLOW + VideoRGB <= "110"; + else + VideoRGB <= "111";--WHITE end if; end if; end process; + +-- colPROM: entity work.clr +--port map( +-- clk => Clk, +-- addr => CAB, --should be Video Counters +-- data => col_data +--); - +-- O_VIDEO_R <= col_data(2); +-- O_VIDEO_G <= col_data(1); +-- O_VIDEO_B <= col_data(0); + O_VIDEO_R <= VideoRGB(2) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); O_VIDEO_G <= VideoRGB(1) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); O_VIDEO_B <= VideoRGB(0) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2); diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/invaders.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/invaders.vhd index 7bff683d..e35bdc82 100644 --- a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/invaders.vhd +++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/Ozma Wars_MiST/rtl/invaders.vhd @@ -209,7 +209,7 @@ begin GDB0(6) <= '1';-- GDB0(7) <= '1';-- - GDB1(0) <= not Coin; + GDB1(0) <= Coin; GDB1(1) <= not Sel2Player; GDB1(2) <= not Sel1Player; GDB1(3) <= '1'; diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Colony7/Colony7.qsf b/Arcade_MiST/Williams 6809 rev.1 Hardware/Colony7/Colony7.qsf index d3a9e469..615cda6e 100644 --- a/Arcade_MiST/Williams 6809 rev.1 Hardware/Colony7/Colony7.qsf +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Colony7/Colony7.qsf @@ -18,7 +18,7 @@ # # Quartus II 64-Bit # Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 21:08:45 June 09, 2019 +# Date created = 20:12:31 June 11, 2019 # # -------------------------------------------------------------------------- # # @@ -56,7 +56,6 @@ set_global_assignment -name VHDL_FILE rtl/pia6821.vhd set_global_assignment -name VHDL_FILE rtl/cpu68.vhd set_global_assignment -name VHDL_FILE rtl/cpu09l_128.vhd set_global_assignment -name QIP_FILE rtl/pll_mist.qip -set_global_assignment -name VERILOG_FILE rtl/data_io.v set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd set_global_assignment -name VHDL_FILE rtl/dac.vhd @@ -145,9 +144,9 @@ set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON # Analysis & Synthesis Assignments # ================================ set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name TOP_LEVEL_ENTITY Colony7_MiST set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name TOP_LEVEL_ENTITY Colony7_MiST # Fitter Assignments # ================== @@ -185,6 +184,26 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" - # -------------------------- # start ENTITY(Colony7_MiST) + # Pin & Location Assignments + # ========================== + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*] + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*] + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0] + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1] + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS + set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*] + set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*] + + # Fitter Assignments + # ================== + set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_* + set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_* + # start DESIGN_PARTITION(Top) # --------------------------- @@ -193,10 +212,10 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top # end DESIGN_PARTITION(Top) # ------------------------- # end ENTITY(Colony7_MiST) -# ------------------------ -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file +# ------------------------ \ No newline at end of file diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Colony7/ReadMe.txt b/Arcade_MiST/Williams 6809 rev.1 Hardware/Colony7/ReadMe.txt index 539e52c1..659139bf 100644 --- a/Arcade_MiST/Williams 6809 rev.1 Hardware/Colony7/ReadMe.txt +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Colony7/ReadMe.txt @@ -1,6 +1,29 @@ -Williams Colony 7 +--------------------------------------------------------------------------------- +-- +-- Arcade: Colony 7 port to MiST by Gehstock +-- 11 June 2019 +-- +--------------------------------------------------------------------------------- +-- A simulation model of Williams 6809 hardware +-- by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr + +--------------------------------------------------------------------------------- +-- +-- Only controls and OSD are rotated on Video output. +-- +-- +-- Keyboard inputs : +-- +-- ESC : Coin +-- F2 : Start 2 players +-- F1 : Start 1 player +-- UP,DOWN,LEFT,RIGHT arrows : Movements +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- -Port to MiST COLONY7.ROM is required at the root of the SD-Card. diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Colony7/Release/Colony7.rbf b/Arcade_MiST/Williams 6809 rev.1 Hardware/Colony7/Release/Colony7.rbf index 817f59c7..410a1fe1 100644 Binary files a/Arcade_MiST/Williams 6809 rev.1 Hardware/Colony7/Release/Colony7.rbf and b/Arcade_MiST/Williams 6809 rev.1 Hardware/Colony7/Release/Colony7.rbf differ diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Colony7/rtl/Colony7_MiST.sv b/Arcade_MiST/Williams 6809 rev.1 Hardware/Colony7/rtl/Colony7_MiST.sv index 4e250c34..1d3ba159 100644 --- a/Arcade_MiST/Williams 6809 rev.1 Hardware/Colony7/rtl/Colony7_MiST.sv +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Colony7/rtl/Colony7_MiST.sv @@ -39,20 +39,20 @@ localparam CONF_STR = { "O2,Rotate Controls,Off,On;", "O34,Scanlines,Off,25%,50%,75%;", "T6,Reset;", - "V,v1.0.5",`BUILD_DATE + "V,v1.1.0",`BUILD_DATE }; assign LED = 1; +assign AUDIO_R = AUDIO_L; -wire clk_sys, clock_6, clock_1p79, clock_0p89; +wire clk_sys, clock_6, clock_0p89; wire pll_locked; pll_mist pll( .inclk0(CLOCK_27), .areset(0), .c0(clk_sys),//36 .c1(clock_6),//6 - .c2(clock_1p79),//1.79 - .c3(clock_0p89),//0.89 + .c2(clock_0p89),//0.89 .locked(pll_locked) ); @@ -70,9 +70,9 @@ wire blankn; wire [2:0] r,g; wire [1:0] b; -wire [14:0] cart_addr; -wire [15:0] sdram_do; -wire cart_rd; +wire [14:0] rom_addr; +wire [15:0] rom_do; +wire rom_rd; wire ioctl_downl; wire [7:0] ioctl_index; wire ioctl_wr; @@ -99,9 +99,9 @@ sdram cart .init ( ~pll_locked ), .clk ( clk_sys ), .wtbt ( 2'b00 ), - .dout ( sdram_do ), + .dout ( rom_do ), .din ( {ioctl_dout, ioctl_dout} ), - .addr ( ioctl_downl ? ioctl_addr : cart_addr ), + .addr ( ioctl_downl ? ioctl_addr : rom_addr ), .we ( ioctl_downl & ioctl_wr ), .rd ( !ioctl_downl), .ready() @@ -118,35 +118,29 @@ always @(posedge clk_sys) begin end defender defender ( - .clock_6 (clock_6), - .clk_1p79 (clock_1p79), - .clk_0p89 (clock_0p89), - .reset ( reset ), - - .video_r ( r ), - .video_g ( g ), - .video_b ( b ), - .video_hs ( hs ), - .video_vs ( vs ), - .video_blankn ( blankn ), - - .audio_out ( audio ), - - .roms_addr ( cart_addr ), - .roms_do ( sdram_do[7:0] ), - - .btn_two_players ( btn_two_players ), - .btn_one_player ( btn_one_player ), - .btn_left_coin ( btn_coin ), - - .btn_fire1(m_fire1), - .btn_fire2(m_fire2), - .btn_fire3(m_fire3), - - .btn_down(m_down), - .btn_up(m_up), - .btn_left(m_left), - .btn_right(m_right) + .clock_6 (clock_6 ), + .clk_0p89 (clock_0p89 ), + .reset ( reset ), + .video_r ( r ), + .video_g ( g ), + .video_b ( b ), + .video_hs ( hs ), + .video_vs ( vs ), + .video_blankn ( blankn ), + .audio_out ( audio ), + .roms_addr ( rom_addr ), + .roms_do ( rom_do[7:0] ), + .vma ( rom_rd ), + .btn_two_players ( btn_two_players ), + .btn_one_player ( btn_one_player ), + .btn_left_coin ( btn_coin ), + .btn_fire1 ( m_fire1 ), + .btn_fire2 ( m_fire2 ), + .btn_fire3 ( m_fire3 ), + .btn_down ( m_down ), + .btn_up ( m_up ), + .btn_left ( m_left ), + .btn_right ( m_right ) ); mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video( @@ -191,17 +185,13 @@ user_io( .status (status ) ); -wire dac_o; -assign AUDIO_L = dac_o; -assign AUDIO_R = dac_o; - dac #( .C_bits(15)) dac( .clk_i(clk_sys), .res_n_i(1), .dac_i({audio,audio}), - .dac_o(dac_o) + .dac_o(AUDIO_L) ); wire m_up = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3]; @@ -212,7 +202,6 @@ wire m_right = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_righ wire m_fire1 = btn_fire1 | joystick_0[4] | joystick_1[4]; wire m_fire2 = btn_fire2 | joystick_0[5] | joystick_1[5]; wire m_fire3 = btn_fire3 | joystick_0[6] | joystick_1[6]; -wire m_fire4 = btn_fire4 | joystick_0[7] | joystick_1[7]; reg btn_one_player = 0; reg btn_two_players = 0; @@ -223,11 +212,7 @@ reg btn_up = 0; reg btn_fire1 = 0; reg btn_fire2 = 0; reg btn_fire3 = 0; -reg btn_fire4 = 0; reg btn_coin = 0; -reg btn_advance = 0; -reg btn_auto_up = 0; -reg btn_score_reset = 0; wire key_pressed; wire [7:0] key_code; wire key_strobe; @@ -242,13 +227,9 @@ always @(posedge clk_sys) begin 'h76: btn_coin <= key_pressed; // ESC 'h05: btn_one_player <= key_pressed; // F1 'h06: btn_two_players <= key_pressed; // F2 - 'h12: btn_fire4 <= key_pressed; // l shift 'h14: btn_fire3 <= key_pressed; // ctrl 'h11: btn_fire2 <= key_pressed; // alt 'h29: btn_fire1 <= key_pressed; // Space - 'h1C: btn_advance <= key_pressed; // A - 'h3C: btn_auto_up <= key_pressed; // U - 'h33: btn_score_reset <= key_pressed; // H endcase end end diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Colony7/rtl/defender.vhd b/Arcade_MiST/Williams 6809 rev.1 Hardware/Colony7/rtl/defender.vhd index c1aca256..7462802c 100644 --- a/Arcade_MiST/Williams 6809 rev.1 Hardware/Colony7/rtl/defender.vhd +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Colony7/rtl/defender.vhd @@ -123,42 +123,32 @@ use ieee.numeric_std.all; entity defender is port( - clk_sys : in std_logic; - clock_6 : in std_logic; - clk_1p79 : in std_logic; - clk_0p89 : in std_logic; - reset : in std_logic; - - dbg_cpu_addr : out std_logic_vector(15 downto 0); --- tv15Khz_mode : in std_logic; - video_r : out std_logic_vector(2 downto 0); - video_g : out std_logic_vector(2 downto 0); - video_b : out std_logic_vector(1 downto 0); --- video_clk : out std_logic; - video_csync : out std_logic; - video_blankn : out std_logic; - video_hs : out std_logic; - video_vs : out std_logic; - - audio_out : out std_logic_vector(7 downto 0); - - roms_addr : out std_logic_vector(14 downto 0); - roms_do : in std_logic_vector( 7 downto 0); - - btn_left_coin : in std_logic; - btn_one_player : in std_logic; - btn_two_players: in std_logic; - - btn_fire1 : in std_logic; - btn_fire2 : in std_logic; - btn_fire3 : in std_logic; - btn_down : in std_logic; - btn_up : in std_logic; - btn_left : in std_logic; - btn_right : in std_logic; - + clk_sys : in std_logic; + clock_6 : in std_logic; + clk_0p89 : in std_logic; + reset : in std_logic; + video_r : out std_logic_vector(2 downto 0); + video_g : out std_logic_vector(2 downto 0); + video_b : out std_logic_vector(1 downto 0); + video_csync : out std_logic; + video_blankn : out std_logic; + video_hs : out std_logic; + video_vs : out std_logic; + audio_out : out std_logic_vector(7 downto 0); + roms_addr : out std_logic_vector(14 downto 0); + roms_do : in std_logic_vector( 7 downto 0); + vma : out std_logic; + btn_left_coin : in std_logic; + btn_one_player : in std_logic; + btn_two_players : in std_logic; + btn_fire1 : in std_logic; + btn_fire2 : in std_logic; + btn_fire3 : in std_logic; + btn_down : in std_logic; + btn_up : in std_logic; + btn_left : in std_logic; + btn_right : in std_logic; cmd_select_players_btn : out std_logic - ); end defender; @@ -166,10 +156,7 @@ architecture struct of defender is signal reset_n: std_logic; signal clock_div : std_logic_vector(1 downto 0); - signal clock_6n : std_logic; - - signal cpu_clock : std_logic; signal cpu_addr : std_logic_vector(15 downto 0); signal cpu_di : std_logic_vector( 7 downto 0); signal cpu_do : std_logic_vector( 7 downto 0); @@ -184,10 +171,6 @@ architecture struct of defender is signal wram1_we : std_logic; signal wram2_do : std_logic_vector( 7 downto 0); signal wram2_we : std_logic; - - --signal roms_addr : std_logic_vector(14 downto 0); - --signal roms_do : std_logic_vector( 7 downto 0); - signal roms_io_do : std_logic_vector( 7 downto 0); signal io_we : std_logic; @@ -283,15 +266,12 @@ architecture struct of defender is signal hsync0,hsync1,hsync2,csync,hblank,vblank : std_logic; signal select_sound : std_logic_vector(5 downto 0); - + signal cpu_ce : std_logic; + begin clock_6n <= not clock_6; reset_n <= not reset; - --- for debug -dbg_cpu_addr <= cpu_addr; - -- make pixels counters and cpu clock -- in original hardware cpu clock = 1us = 6pixels @@ -300,30 +280,14 @@ process (reset, clock_6n) begin if reset='1' then pixel_cnt <= "000"; - cpu_clock <= '0'; else if rising_edge(clock_6n) then if pixel_cnt = "101" then pixel_cnt <= "000"; - cpu_clock <= '0'; else pixel_cnt <= pixel_cnt + '1'; end if; - - if pixel_cnt = "010" then - cpu_clock <= '1'; - end if; - - if pixel_cnt = "011" then -- speed up processor (two clocks / 1us) - cpu_clock <= '0'; - end if; - - if pixel_cnt = "100" then - cpu_clock <= '1'; - end if; - - end if; end if; end process; @@ -353,8 +317,7 @@ begin vcnt <= vcnt + '1'; end if; end if; - end if; - + end if; end if; end if; end process; @@ -387,7 +350,7 @@ video_scan_addr <= screen_ctrl & vcnt(7 downto 0); -- mux cpu addr/scan addr to wram wram_addr <= - cpu_addr(7 downto 0) & cpu_to_video_do(5 downto 0) when cpu_clock = '1' else + cpu_addr(7 downto 0) & cpu_to_video_do(5 downto 0) when cpu_ce = '1' else video_scan_do & hcnt; -- mux cpu addr/pixels data to palette addr @@ -426,14 +389,14 @@ begin end process; -- pias cs -io_cs <= '1' when cpu_clock = '1' and cpu_addr(15 downto 12) = X"C" and rom_page ="000" else '0'; +io_cs <= '1' when cpu_ce = '1' and cpu_addr(15 downto 12) = X"C" and rom_page ="000" else '0'; pia_rom_cs <= '1' when io_cs = '1' and cpu_addr(11 downto 10) = "11" and cpu_addr(2) = '0' else '0'; -- CC00-CC03 pia_io_cs <= '1' when io_cs = '1' and cpu_addr(11 downto 10) = "11" and cpu_addr(2) = '1' else '0'; -- CC04-CC07 -- write enables -wram_we <= '1' when cpu_rw = '0' and cpu_clock = '1' and cpu_addr(15 downto 12) < X"C" else '0'; -io_we <= '1' when cpu_rw = '0' and cpu_clock = '1' and cpu_addr(15 downto 12) = X"C" and rom_page ="000" else '0'; -rom_page_we <= '1' when cpu_rw = '0' and cpu_clock = '1' and cpu_addr(15 downto 12) = X"D" else '0'; +wram_we <= '1' when cpu_rw = '0' and cpu_ce = '1' and cpu_addr(15 downto 12) < X"C" else '0'; +io_we <= '1' when cpu_rw = '0' and cpu_ce = '1' and cpu_addr(15 downto 12) = X"C" and rom_page ="000" else '0'; +rom_page_we <= '1' when cpu_rw = '0' and cpu_ce = '1' and cpu_addr(15 downto 12) = X"D" else '0'; palette_we <= '1' when io_we = '1' and cpu_addr(11 downto 10) = "00" and cpu_addr(4) = '0' else '0'; -- C000-C00F screen_ctrl_we <= '1' when io_we = '1' and cpu_addr(11 downto 10) = "00" and cpu_addr(4) = '1' else '0'; -- C010-C01F @@ -479,7 +442,7 @@ begin end if; end process; -pias_clock <= clock_6; --not cpu_clock; +pias_clock <= clock_6; pia_rom_pa_i(0) <= '1'; pia_rom_pa_i(1) <= '0'; @@ -517,13 +480,14 @@ cpu_irq <= pia_rom_irqa or pia_rom_irqb; -- pia rom to sound board select_sound <= pia_rom_pb_o(5 downto 0); +cpu_ce <= '1' when pixel_cnt = "100" or pixel_cnt = "010" else '0'; -- microprocessor 6809 main_cpu : entity work.cpu09 port map( - clk => cpu_clock,-- E clock input (falling edge) + clk => clock_6,-- E clock input (falling edge) rst => reset, -- reset input (active high) - vma => open, -- valid memory address (active high) + vma => vma, -- valid memory address (active high) lic_out => open, -- last instruction cycle (active high) ifetch => open, -- instruction fetch cycle (active high) opfetch => open, -- opcode fetch (active high) @@ -537,7 +501,7 @@ port map( firq => '0', -- fast interrupt request input (active high) nmi => '0', -- non maskable interrupt request input (active high) halt => '0', -- halt input (active high) grants DMA - hold => '0' -- hold input (active high) extend bus cycle + hold => not cpu_ce -- hold input (active high) extend bus cycle ); -- cpu/video wram 0 @@ -716,10 +680,10 @@ if rising_edge(clock_6n) then end if; if hcnt = hcnt_base-2 then hblank <= '1'; - elsif hcnt = hcnt_base+11-64 then hblank <= '0'; + elsif hcnt = hcnt_base+12-64 then hblank <= '0'; end if; - if vcnt = 492 then vblank <= '1'; -- 492 ok + if vcnt = 502 then vblank <= '1'; -- 492 ok elsif vcnt = 262 then vblank <= '0'; -- 262 ok end if; @@ -738,7 +702,6 @@ end process; -- sound board defender_sound_board : entity work.defender_sound_board port map( - clk_1p79 => clk_1p79, clk_0p89 => clk_0p89, reset => reset, hand => '1', diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Colony7/rtl/defender_sound_board.vhd b/Arcade_MiST/Williams 6809 rev.1 Hardware/Colony7/rtl/defender_sound_board.vhd index 2aeac4fe..5cc028dd 100644 --- a/Arcade_MiST/Williams 6809 rev.1 Hardware/Colony7/rtl/defender_sound_board.vhd +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Colony7/rtl/defender_sound_board.vhd @@ -27,7 +27,6 @@ use ieee.numeric_std.all; entity defender_sound_board is port( - clk_1p79 : in std_logic; clk_0p89 : in std_logic; reset : in std_logic; hand : in std_logic; @@ -41,7 +40,6 @@ architecture struct of defender_sound_board is signal reset_n : std_logic; - signal cpu_clock : std_logic; signal cpu_addr : std_logic_vector(15 downto 0); signal cpu_di : std_logic_vector( 7 downto 0); signal cpu_do : std_logic_vector( 7 downto 0); @@ -55,7 +53,6 @@ architecture struct of defender_sound_board is signal rom_cs : std_logic; signal rom_do : std_logic_vector( 7 downto 0); - signal pia_clock : std_logic; signal pia_rw_n : std_logic; signal pia_cs : std_logic; signal pia_irqa : std_logic; @@ -70,7 +67,6 @@ begin reset_n <= not reset; dbg_cpu_addr <= cpu_addr; -cpu_clock <= clk_0p89; -- pia cs @@ -79,8 +75,8 @@ pia_cs <= '1' when cpu_addr(14 downto 12) = 0 and cpu_addr(10) = '1' else '0'; rom_cs <= '1' when cpu_addr(15 downto 12) = X"F" else '0'; -- F800-FFFF -- write enables -wram_we <= '1' when cpu_rw = '0' and cpu_clock = '1' and wram_cs = '1' else '0'; -pia_rw_n <= '0' when cpu_rw = '0' and cpu_clock = '1' and pia_cs = '1' else '1'; +wram_we <= '1' when cpu_rw = '0' and wram_cs = '1' else '0'; +pia_rw_n <= '0' when cpu_rw = '0' and pia_cs = '1' else '1'; -- mux cpu in data between roms/io/wram cpu_di <= @@ -89,7 +85,6 @@ cpu_di <= rom_do when rom_cs = '1' else X"55"; -- pia I/O -pia_clock <= clk_1p79; -- 3p58/2 audio_out <= pia_pa_o; pia_pb_i <= hand & '1' & select_sound(5 downto 0); @@ -103,7 +98,7 @@ cpu_irq <= pia_irqa or pia_irqb; -- microprocessor 6800 main_cpu : entity work.cpu68 port map( - clk => cpu_clock,-- E clock input (falling edge) + clk => clk_0p89,-- E clock input (falling edge) rst => reset, -- reset input (active high) rw => cpu_rw, -- read not write output vma => open, -- valid memory address (active high) @@ -121,7 +116,7 @@ port map( -- cpu program rom cpu_prog_rom : entity work.defender_sound port map( - clk => clk_1p79, + clk => clk_0p89, addr => cpu_addr(10 downto 0), data => rom_do ); @@ -130,7 +125,7 @@ port map( cpu_ram : entity work.gen_ram generic map( dWidth => 8, aWidth => 7) port map( - clk => clk_1p79, + clk => clk_0p89, we => wram_we, addr => cpu_addr(6 downto 0), d => cpu_do, @@ -141,7 +136,7 @@ port map( pia : entity work.pia6821 port map ( - clk => clk_1p79, + clk => clk_0p89, rst => reset, cs => pia_cs, rw => pia_rw_n, diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Colony7/rtl/pll_mist.vhd b/Arcade_MiST/Williams 6809 rev.1 Hardware/Colony7/rtl/pll_mist.vhd index b54b7a75..1bd8e50f 100644 --- a/Arcade_MiST/Williams 6809 rev.1 Hardware/Colony7/rtl/pll_mist.vhd +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Colony7/rtl/pll_mist.vhd @@ -47,7 +47,6 @@ ENTITY pll_mist IS c0 : OUT STD_LOGIC ; c1 : OUT STD_LOGIC ; c2 : OUT STD_LOGIC ; - c3 : OUT STD_LOGIC ; locked : OUT STD_LOGIC ); END pll_mist; @@ -61,10 +60,9 @@ ARCHITECTURE SYN OF pll_mist IS SIGNAL sub_wire3 : STD_LOGIC ; SIGNAL sub_wire4 : STD_LOGIC ; SIGNAL sub_wire5 : STD_LOGIC ; - SIGNAL sub_wire6 : STD_LOGIC ; - SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire8_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); @@ -83,10 +81,6 @@ ARCHITECTURE SYN OF pll_mist IS clk2_duty_cycle : NATURAL; clk2_multiply_by : NATURAL; clk2_phase_shift : STRING; - clk3_divide_by : NATURAL; - clk3_duty_cycle : NATURAL; - clk3_multiply_by : NATURAL; - clk3_phase_shift : STRING; compensate_clock : STRING; inclk0_input_frequency : NATURAL; intended_device_family : STRING; @@ -147,19 +141,17 @@ ARCHITECTURE SYN OF pll_mist IS END COMPONENT; BEGIN - sub_wire8_bv(0 DOWNTO 0) <= "0"; - sub_wire8 <= To_stdlogicvector(sub_wire8_bv); - sub_wire5 <= sub_wire0(2); - sub_wire4 <= sub_wire0(0); - sub_wire2 <= sub_wire0(3); + sub_wire7_bv(0 DOWNTO 0) <= "0"; + sub_wire7 <= To_stdlogicvector(sub_wire7_bv); + sub_wire4 <= sub_wire0(2); + sub_wire3 <= sub_wire0(0); sub_wire1 <= sub_wire0(1); c1 <= sub_wire1; - c3 <= sub_wire2; - locked <= sub_wire3; - c0 <= sub_wire4; - c2 <= sub_wire5; - sub_wire6 <= inclk0; - sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6; + locked <= sub_wire2; + c0 <= sub_wire3; + c2 <= sub_wire4; + sub_wire5 <= inclk0; + sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; altpll_component : altpll GENERIC MAP ( @@ -172,14 +164,10 @@ BEGIN clk1_duty_cycle => 50, clk1_multiply_by => 2, clk1_phase_shift => "0", - clk2_divide_by => 181, + clk2_divide_by => 91, clk2_duty_cycle => 50, - clk2_multiply_by => 12, + clk2_multiply_by => 3, clk2_phase_shift => "0", - clk3_divide_by => 91, - clk3_duty_cycle => 50, - clk3_multiply_by => 3, - clk3_phase_shift => "0", compensate_clock => "CLK0", inclk0_input_frequency => 37037, intended_device_family => "Cyclone III", @@ -215,7 +203,7 @@ BEGIN port_clk0 => "PORT_USED", port_clk1 => "PORT_USED", port_clk2 => "PORT_USED", - port_clk3 => "PORT_USED", + port_clk3 => "PORT_UNUSED", port_clk4 => "PORT_UNUSED", port_clk5 => "PORT_UNUSED", port_clkena0 => "PORT_UNUSED", @@ -233,9 +221,9 @@ BEGIN ) PORT MAP ( areset => areset, - inclk => sub_wire7, + inclk => sub_wire6, clk => sub_wire0, - locked => sub_wire3 + locked => sub_wire2 ); @@ -263,16 +251,13 @@ END SYN; -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" -- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3" -- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9" --- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "181" --- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "91" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "91" -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "36.000000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "6.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "1.790055" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "0.890110" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "0.890110" -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -295,40 +280,32 @@ END SYN; -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" -- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" -- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" -- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4" -- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2" --- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "12" --- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "3" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "3" -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" -- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "36.00000000" -- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "6.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "1.79000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "0.89000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "0.89000000" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" -- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" -- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg" -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" -- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" @@ -353,18 +330,15 @@ END SYN; -- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" -- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" -- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" -- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" -- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: USE_CLK0 STRING "1" -- Retrieval info: PRIVATE: USE_CLK1 STRING "1" -- Retrieval info: PRIVATE: USE_CLK2 STRING "1" --- Retrieval info: PRIVATE: USE_CLK3 STRING "1" -- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" -- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" -- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" -- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all @@ -377,14 +351,10 @@ END SYN; -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" -- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "181" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "91" -- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "12" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "3" -- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "91" --- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "3" --- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" @@ -419,7 +389,7 @@ END SYN; -- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" @@ -440,7 +410,6 @@ END SYN; -- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" -- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" -- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" --- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" -- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" -- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 @@ -449,7 +418,6 @@ END SYN; -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 -- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 --- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 -- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.ppf TRUE diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/Defender_MiST.qsf b/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/Defender_MiST.qsf index 3090fd9d..9e2f788b 100644 --- a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/Defender_MiST.qsf +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/Defender_MiST.qsf @@ -18,7 +18,7 @@ # # Quartus II 64-Bit # Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 18:04:04 June 09, 2019 +# Date created = 20:24:55 June 11, 2019 # # -------------------------------------------------------------------------- # # @@ -52,12 +52,10 @@ set_global_assignment -name VHDL_FILE rtl/defender_sound.vhd set_global_assignment -name VHDL_FILE rtl/defender_decoder_3.vhd set_global_assignment -name VHDL_FILE rtl/defender_decoder_2.vhd set_global_assignment -name VHDL_FILE rtl/defender_cmos_ram.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/YM2149.sv set_global_assignment -name VHDL_FILE rtl/pia6821.vhd set_global_assignment -name VHDL_FILE rtl/cpu68.vhd set_global_assignment -name VHDL_FILE rtl/cpu09l_128.vhd set_global_assignment -name QIP_FILE rtl/pll_mist.qip -set_global_assignment -name VERILOG_FILE rtl/data_io.v set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd set_global_assignment -name VHDL_FILE rtl/dac.vhd @@ -146,9 +144,9 @@ set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON # Analysis & Synthesis Assignments # ================================ set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name TOP_LEVEL_ENTITY Defender_MiST set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name TOP_LEVEL_ENTITY Defender_MiST # Fitter Assignments # ================== @@ -186,6 +184,26 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" - # --------------------------- # start ENTITY(Defender_MiST) + # Pin & Location Assignments + # ========================== + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*] + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*] + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0] + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1] + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS + set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*] + set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*] + + # Fitter Assignments + # ================== + set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_* + set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_* + # start DESIGN_PARTITION(Top) # --------------------------- @@ -194,10 +212,10 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top # end DESIGN_PARTITION(Top) # ------------------------- # end ENTITY(Defender_MiST) -# ------------------------- -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file +# ------------------------- \ No newline at end of file diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/ReadMe.txt b/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/ReadMe.txt index 5e7bd428..2265b0dd 100644 --- a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/ReadMe.txt +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/ReadMe.txt @@ -1,17 +1,36 @@ -Williams Defender +--------------------------------------------------------------------------------- +-- +-- Arcade: Defender port to MiST by Gehstock +-- 11 June 2019 +-- +--------------------------------------------------------------------------------- +-- A simulation model of Williams 6809 hardware +-- by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr + +--------------------------------------------------------------------------------- +-- +-- Only controls and OSD are rotated on Video output. +-- +-- +-- Keyboard inputs : +-- +-- Fire = Fire or Space +-- Thrust = Fire2 or ALT +-- Smart Bomb = Fire3 or CTRL +-- Hyperspace = Fire4 or 1 +-- Change Direction = Left or Right +-- Up = Up +-- Down = Down + +-- Advance = A +-- Auto up = U +-- Score_reset = H +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- -Port to MiST DEFENDER.ROM is required at the root of the SD-Card. - Fire = Fire or Space - Thrust = Fire2 or ALT - Smart Bomb = Fire3 or CTRL - Hyperspace = Fire4 or 1 - Change Direction = Left or Right - Up = Up - Down = Down - - Advance = A - Auto up = U - Score_reset = H \ No newline at end of file diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/Release/Defender_MiST.rbf b/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/Release/Defender_MiST.rbf index f0eaa5fe..31d3196f 100644 Binary files a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/Release/Defender_MiST.rbf and b/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/Release/Defender_MiST.rbf differ diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/Defender_MiST.sv b/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/Defender_MiST.sv index 7db9417a..04d56a58 100644 --- a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/Defender_MiST.sv +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/Defender_MiST.sv @@ -38,20 +38,20 @@ localparam CONF_STR = { "DEFENDER;;", "O34,Scanlines,Off,25%,50%,75%;", "T6,Reset;", - "V,v1.0.5",`BUILD_DATE + "V,v1.1.0",`BUILD_DATE }; assign LED = 1; +assign SDRAM_CLK = clk_sys; -wire clk_sys, clock_6, clock_1p79, clock_0p89; +wire clk_sys, clock_6, clock_0p89; wire pll_locked; pll_mist pll( .inclk0(CLOCK_27), .areset(0), .c0(clk_sys),//36 .c1(clock_6),//6 - .c2(clock_1p79),//1.79 - .c3(clock_0p89),//0.89 + .c2(clock_0p89),//0.89 .locked(pll_locked) ); @@ -63,15 +63,15 @@ wire [7:0] joystick_1; wire scandoublerD; wire ypbpr; wire [10:0] ps2_key; -wire [7:0] audio; +wire [7:0] audio; wire hs, vs; wire blankn; wire [2:0] r,g; wire [1:0] b; -wire [14:0] cart_addr; -wire [15:0] sdram_do; -wire cart_rd; +wire [14:0] rom_addr; +wire [15:0] rom_do; +wire rom_rd; wire ioctl_downl; wire [7:0] ioctl_index; wire ioctl_wr; @@ -89,8 +89,6 @@ data_io data_io ( .ioctl_addr ( ioctl_addr ), .ioctl_dout ( ioctl_dout ) ); - -assign SDRAM_CLK = clk_sys; sdram cart ( @@ -98,11 +96,11 @@ sdram cart .init ( ~pll_locked ), .clk ( clk_sys ), .wtbt ( 2'b00 ), - .dout ( sdram_do ), + .dout ( rom_do ), .din ( {ioctl_dout, ioctl_dout} ), - .addr ( ioctl_downl ? ioctl_addr : cart_addr ), + .addr ( ioctl_downl ? ioctl_addr : rom_addr ), .we ( ioctl_downl & ioctl_wr ), - .rd ( !ioctl_downl), + .rd ( !ioctl_downl & rom_rd ), .ready() ); @@ -117,41 +115,33 @@ always @(posedge clk_sys) begin end defender defender ( - .clock_6 (clock_6), - .clk_1p79 (clock_1p79), - .clk_0p89 (clock_0p89), - .reset ( reset ), - - .video_r ( r ), - .video_g ( g ), - .video_b ( b ), - .video_hs ( hs ), - .video_vs ( vs ), - .video_blankn ( blankn ), - - .audio_out ( audio ), - - .roms_addr ( cart_addr ), - .roms_do ( sdram_do[7:0] ), - - .btn_two_players ( btn_two_players ), - .btn_one_player ( btn_one_player ), - .btn_left_coin ( btn_coin ), - - .btn_auto_up(btn_auto_up), - .btn_advance(btn_advance), + .clock_6 (clock_6), + .clk_0p89 (clock_0p89), + .reset ( reset ), + .video_r ( r ), + .video_g ( g ), + .video_b ( b ), + .video_hs ( hs ), + .video_vs ( vs ), + .video_blankn ( blankn ), + .audio_out ( audio ), + .roms_addr ( rom_addr ), + .roms_do ( rom_do[7:0] ), + .vma ( rom_rd ), + .btn_two_players ( btn_two_players ), + .btn_one_player ( btn_one_player ), + .btn_left_coin ( btn_coin ), + .btn_auto_up (btn_auto_up), + .btn_advance (btn_advance), .btn_high_score_reset(btn_score_reset), - - - .btn_fire(m_fire1), - .btn_thrust(m_fire2), - .btn_smart_bomb(m_fire3), - .btn_hyperSpace(m_fire4), - .btn_reverse(m_left | m_right), - .btn_down(m_down), - .btn_up(m_up), - - .sw_coktail_table(1) + .btn_fire (m_fire1), + .btn_thrust (m_fire2), + .btn_smart_bomb (m_fire3), + .btn_hyperSpace (m_fire4), + .btn_reverse (m_left | m_right), + .btn_down (m_down), + .btn_up (m_up), + .sw_coktail_table (1) ); mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video( diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/data_io.v b/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/data_io.v deleted file mode 100644 index 4ca9518c..00000000 --- a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/data_io.v +++ /dev/null @@ -1,115 +0,0 @@ -// -// data_io.v -// -// data_io for the MiST board -// http://code.google.com/p/mist-board/ -// -// Copyright (c) 2014 Till Harbaum -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -/////////////////////////////////////////////////////////////////////// - -module data_io -( - input clk_sys, - input SPI_SCK, - input SPI_SS2, - input SPI_DI, - - // ARM -> FPGA download - output reg ioctl_download = 0, // signal indicating an active download - output reg [7:0] ioctl_index, // menu index used to upload the file - output ioctl_wr, - output reg [24:0] ioctl_addr, - output reg [7:0] ioctl_dout -); - -/////////////////////////////// DOWNLOADING /////////////////////////////// - -reg [7:0] data_w; -reg [24:0] addr_w; -reg rclk = 0; - -localparam UIO_FILE_TX = 8'h53; -localparam UIO_FILE_TX_DAT = 8'h54; -localparam UIO_FILE_INDEX = 8'h55; - -// data_io has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS2) begin - reg [6:0] sbuf; - reg [7:0] cmd; - reg [4:0] cnt; - reg [24:0] addr; - - if(SPI_SS2) cnt <= 0; - else begin - rclk <= 0; - - // don't shift in last bit. It is evaluated directly - // when writing to ram - if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; - - // increase target address after write - if(rclk) addr <= addr + 1'd1; - - // count 0-7 8-15 8-15 ... - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - // finished command byte - if(cnt == 7) cmd <= {sbuf, SPI_DI}; - - // prepare/end transmission - if((cmd == UIO_FILE_TX) && (cnt == 15)) begin - // prepare - if(SPI_DI) begin - addr <= 0; - ioctl_download <= 1; - end else begin - addr_w <= addr; - ioctl_download <= 0; - end - end - - // command 0x54: UIO_FILE_TX - if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin - addr_w <= addr; - data_w <= {sbuf, SPI_DI}; - rclk <= 1; - end - - // expose file (menu) index - if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; - end -end - -assign ioctl_wr = |ioctl_wrd; -reg [1:0] ioctl_wrd; - -always@(negedge clk_sys) begin - reg rclkD, rclkD2; - - rclkD <= rclk; - rclkD2 <= rclkD; - ioctl_wrd<= {ioctl_wrd[0],1'b0}; - - if(rclkD & ~rclkD2) begin - ioctl_dout <= data_w; - ioctl_addr <= addr_w; - ioctl_wrd <= 2'b11; - end -end - -endmodule diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/defender.vhd b/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/defender.vhd index a434393f..a09e380e 100644 --- a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/defender.vhd +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/defender.vhd @@ -125,28 +125,19 @@ entity defender is port( clk_sys : in std_logic; clock_6 : in std_logic; - clk_1p79 : in std_logic; clk_0p89 : in std_logic; reset : in std_logic; - - dbg_cpu_addr : out std_logic_vector(15 downto 0); --- tv15Khz_mode : in std_logic; video_r : out std_logic_vector(2 downto 0); video_g : out std_logic_vector(2 downto 0); video_b : out std_logic_vector(1 downto 0); --- video_clk : out std_logic; video_csync : out std_logic; video_blankn : out std_logic; video_hs : out std_logic; video_vs : out std_logic; - - audio_out : out std_logic_vector(7 downto 0); - - roms_addr : out std_logic_vector(14 downto 0); - roms_do : in std_logic_vector( 7 downto 0); - - - + audio_out : out std_logic_vector(7 downto 0); + roms_addr : out std_logic_vector(14 downto 0); + roms_do : in std_logic_vector( 7 downto 0); + vma : out std_logic; btn_auto_up : in std_logic; btn_advance : in std_logic; btn_high_score_reset : in std_logic; @@ -162,11 +153,8 @@ port( btn_reverse : in std_logic; btn_down : in std_logic; btn_up : in std_logic; - sw_coktail_table : in std_logic; - cmd_select_players_btn : out std_logic - ); end defender; @@ -176,8 +164,6 @@ architecture struct of defender is signal clock_div : std_logic_vector(1 downto 0); signal clock_6n : std_logic; - - signal cpu_clock : std_logic; signal cpu_addr : std_logic_vector(15 downto 0); signal cpu_di : std_logic_vector( 7 downto 0); signal cpu_do : std_logic_vector( 7 downto 0); @@ -192,10 +178,6 @@ architecture struct of defender is signal wram1_we : std_logic; signal wram2_do : std_logic_vector( 7 downto 0); signal wram2_we : std_logic; - - --signal roms_addr : std_logic_vector(14 downto 0); - --signal roms_do : std_logic_vector( 7 downto 0); - signal roms_io_do : std_logic_vector( 7 downto 0); signal io_we : std_logic; @@ -291,14 +273,12 @@ architecture struct of defender is signal hsync0,hsync1,hsync2,csync,hblank,vblank : std_logic; signal select_sound : std_logic_vector(5 downto 0); - + signal cpu_ce : std_logic; + begin clock_6n <= not clock_6; reset_n <= not reset; - --- for debug -dbg_cpu_addr <= cpu_addr; -- make pixels counters and cpu clock @@ -308,30 +288,14 @@ process (reset, clock_6n) begin if reset='1' then pixel_cnt <= "000"; - cpu_clock <= '0'; else if rising_edge(clock_6n) then if pixel_cnt = "101" then pixel_cnt <= "000"; - cpu_clock <= '0'; else pixel_cnt <= pixel_cnt + '1'; - end if; - - if pixel_cnt = "010" then - cpu_clock <= '1'; - end if; - - if pixel_cnt = "011" then -- speed up processor (two clocks / 1us) - cpu_clock <= '0'; - end if; - - if pixel_cnt = "100" then - cpu_clock <= '1'; - end if; - - + end if; end if; end if; end process; @@ -395,7 +359,7 @@ video_scan_addr <= screen_ctrl & vcnt(7 downto 0); -- mux cpu addr/scan addr to wram wram_addr <= - cpu_addr(7 downto 0) & cpu_to_video_do(5 downto 0) when cpu_clock = '1' else + cpu_addr(7 downto 0) & cpu_to_video_do(5 downto 0) when cpu_ce = '1' else video_scan_do & hcnt; -- mux cpu addr/pixels data to palette addr @@ -434,14 +398,14 @@ begin end process; -- pias cs -io_cs <= '1' when cpu_clock = '1' and cpu_addr(15 downto 12) = X"C" and rom_page ="000" else '0'; +io_cs <= '1' when cpu_ce = '1' and cpu_addr(15 downto 12) = X"C" and rom_page ="000" else '0'; pia_rom_cs <= '1' when io_cs = '1' and cpu_addr(11 downto 10) = "11" and cpu_addr(2) = '0' else '0'; -- CC00-CC03 pia_io_cs <= '1' when io_cs = '1' and cpu_addr(11 downto 10) = "11" and cpu_addr(2) = '1' else '0'; -- CC04-CC07 -- write enables -wram_we <= '1' when cpu_rw = '0' and cpu_clock = '1' and cpu_addr(15 downto 12) < X"C" else '0'; -io_we <= '1' when cpu_rw = '0' and cpu_clock = '1' and cpu_addr(15 downto 12) = X"C" and rom_page ="000" else '0'; -rom_page_we <= '1' when cpu_rw = '0' and cpu_clock = '1' and cpu_addr(15 downto 12) = X"D" else '0'; +wram_we <= '1' when cpu_rw = '0' and cpu_ce = '1' and cpu_addr(15 downto 12) < X"C" else '0'; +io_we <= '1' when cpu_rw = '0' and cpu_ce = '1' and cpu_addr(15 downto 12) = X"C" and rom_page ="000" else '0'; +rom_page_we <= '1' when cpu_rw = '0' and cpu_ce = '1' and cpu_addr(15 downto 12) = X"D" else '0'; palette_we <= '1' when io_we = '1' and cpu_addr(11 downto 10) = "00" and cpu_addr(4) = '0' else '0'; -- C000-C00F screen_ctrl_we <= '1' when io_we = '1' and cpu_addr(11 downto 10) = "00" and cpu_addr(4) = '1' else '0'; -- C010-C01F @@ -548,13 +512,14 @@ cpu_irq <= pia_rom_irqa or pia_rom_irqb; -- pia rom to sound board select_sound <= pia_rom_pb_o(5 downto 0); +cpu_ce <= '1' when pixel_cnt = "100" or pixel_cnt = "010" else '0'; -- microprocessor 6809 main_cpu : entity work.cpu09 port map( - clk => cpu_clock,-- E clock input (falling edge) + clk => clock_6, -- E clock input (falling edge) rst => reset, -- reset input (active high) - vma => open, -- valid memory address (active high) + vma => vma, -- valid memory address (active high) lic_out => open, -- last instruction cycle (active high) ifetch => open, -- instruction fetch cycle (active high) opfetch => open, -- opcode fetch (active high) @@ -567,8 +532,8 @@ port map( irq => cpu_irq, -- interrupt request input (active high) firq => '0', -- fast interrupt request input (active high) nmi => '0', -- non maskable interrupt request input (active high) - halt => '0', -- halt input (active high) grants DMA - hold => '0' -- hold input (active high) extend bus cycle + halt => '0', -- not cpu_ce -- hold input (active high) extend bus cycle + hold => not cpu_ce -- hold input (active high) extend bus cycle ); -- cpu program rom @@ -766,10 +731,10 @@ if rising_edge(clock_6n) then end if; if hcnt = hcnt_base-2 then hblank <= '1'; - elsif hcnt = hcnt_base+11-64 then hblank <= '0'; + elsif hcnt = hcnt_base+12-64 then hblank <= '0'; end if; - if vcnt = 492 then vblank <= '1'; -- 492 ok + if vcnt = 502 then vblank <= '1'; -- 492 ok elsif vcnt = 262 then vblank <= '0'; -- 262 ok end if; @@ -788,13 +753,10 @@ end process; -- sound board defender_sound_board : entity work.defender_sound_board port map( - clk_1p79 => clk_1p79, clk_0p89 => clk_0p89, reset => reset, select_sound => select_sound, - audio_out => audio_out, - - dbg_cpu_addr => open --dbg_cpu_addr + audio_out => audio_out ); end struct; \ No newline at end of file diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/defender_sound_board.vhd b/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/defender_sound_board.vhd index 5fdd8293..944defac 100644 --- a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/defender_sound_board.vhd +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/defender_sound_board.vhd @@ -27,14 +27,10 @@ use ieee.numeric_std.all; entity defender_sound_board is port( - clk_1p79 : in std_logic; clk_0p89 : in std_logic; reset : in std_logic; - select_sound : in std_logic_vector(5 downto 0); - audio_out : out std_logic_vector( 7 downto 0); - - dbg_cpu_addr : out std_logic_vector(15 downto 0) + audio_out : out std_logic_vector( 7 downto 0) ); end defender_sound_board; @@ -42,7 +38,6 @@ architecture struct of defender_sound_board is signal reset_n : std_logic; - signal cpu_clock : std_logic; signal cpu_addr : std_logic_vector(15 downto 0); signal cpu_di : std_logic_vector( 7 downto 0); signal cpu_do : std_logic_vector( 7 downto 0); @@ -70,7 +65,6 @@ architecture struct of defender_sound_board is -- ca2 speech data N/C -- cb2 speech clock N/C - signal pia_clock : std_logic; signal pia_rw_n : std_logic; signal pia_cs : std_logic; signal pia_irqa : std_logic; @@ -84,8 +78,6 @@ begin reset_n <= not reset; -dbg_cpu_addr <= cpu_addr; -cpu_clock <= clk_0p89; -- pia cs @@ -94,8 +86,8 @@ pia_cs <= '1' when cpu_addr(15 downto 12) = X"0" and cpu_addr(10) = '1' else '0 rom_cs <= '1' when cpu_addr(15 downto 12) = X"F" else '0'; -- F800-FFFF -- write enables -wram_we <= '1' when cpu_rw = '0' and cpu_clock = '1' and wram_cs = '1' else '0'; -pia_rw_n <= '0' when cpu_rw = '0' and cpu_clock = '1' and pia_cs = '1' else '1'; +wram_we <= '1' when cpu_rw = '0' and wram_cs = '1' else '0'; +pia_rw_n <= '0' when cpu_rw = '0' and pia_cs = '1' else '1'; -- mux cpu in data between roms/io/wram cpu_di <= @@ -104,7 +96,6 @@ cpu_di <= rom_do when rom_cs = '1' else X"55"; -- pia I/O -pia_clock <= clk_1p79; -- 3p58/2 audio_out <= pia_pa_o; pia_pb_i(4 downto 0) <= select_sound(4 downto 0); @@ -120,7 +111,7 @@ cpu_irq <= pia_irqa or pia_irqb; -- microprocessor 6800 main_cpu : entity work.cpu68 port map( - clk => cpu_clock,-- E clock input (falling edge) + clk => clk_0p89,-- E clock input (falling edge) rst => reset, -- reset input (active high) rw => cpu_rw, -- read not write output vma => open, -- valid memory address (active high) @@ -138,7 +129,7 @@ port map( -- cpu program rom cpu_prog_rom : entity work.defender_sound port map( - clk => clk_1p79, + clk => clk_0p89, addr => cpu_addr(10 downto 0), data => rom_do ); @@ -147,7 +138,7 @@ port map( cpu_ram : entity work.gen_ram generic map( dWidth => 8, aWidth => 7) port map( - clk => clk_1p79, + clk => clk_0p89, we => wram_we, addr => cpu_addr(6 downto 0), d => cpu_do, @@ -158,7 +149,7 @@ port map( pia : entity work.pia6821 port map ( - clk => clk_1p79, + clk => clk_0p89, rst => reset, cs => pia_cs, rw => pia_rw_n, diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/pll_mist.vhd b/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/pll_mist.vhd index b54b7a75..1bd8e50f 100644 --- a/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/pll_mist.vhd +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Defender/rtl/pll_mist.vhd @@ -47,7 +47,6 @@ ENTITY pll_mist IS c0 : OUT STD_LOGIC ; c1 : OUT STD_LOGIC ; c2 : OUT STD_LOGIC ; - c3 : OUT STD_LOGIC ; locked : OUT STD_LOGIC ); END pll_mist; @@ -61,10 +60,9 @@ ARCHITECTURE SYN OF pll_mist IS SIGNAL sub_wire3 : STD_LOGIC ; SIGNAL sub_wire4 : STD_LOGIC ; SIGNAL sub_wire5 : STD_LOGIC ; - SIGNAL sub_wire6 : STD_LOGIC ; - SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire8_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); @@ -83,10 +81,6 @@ ARCHITECTURE SYN OF pll_mist IS clk2_duty_cycle : NATURAL; clk2_multiply_by : NATURAL; clk2_phase_shift : STRING; - clk3_divide_by : NATURAL; - clk3_duty_cycle : NATURAL; - clk3_multiply_by : NATURAL; - clk3_phase_shift : STRING; compensate_clock : STRING; inclk0_input_frequency : NATURAL; intended_device_family : STRING; @@ -147,19 +141,17 @@ ARCHITECTURE SYN OF pll_mist IS END COMPONENT; BEGIN - sub_wire8_bv(0 DOWNTO 0) <= "0"; - sub_wire8 <= To_stdlogicvector(sub_wire8_bv); - sub_wire5 <= sub_wire0(2); - sub_wire4 <= sub_wire0(0); - sub_wire2 <= sub_wire0(3); + sub_wire7_bv(0 DOWNTO 0) <= "0"; + sub_wire7 <= To_stdlogicvector(sub_wire7_bv); + sub_wire4 <= sub_wire0(2); + sub_wire3 <= sub_wire0(0); sub_wire1 <= sub_wire0(1); c1 <= sub_wire1; - c3 <= sub_wire2; - locked <= sub_wire3; - c0 <= sub_wire4; - c2 <= sub_wire5; - sub_wire6 <= inclk0; - sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6; + locked <= sub_wire2; + c0 <= sub_wire3; + c2 <= sub_wire4; + sub_wire5 <= inclk0; + sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; altpll_component : altpll GENERIC MAP ( @@ -172,14 +164,10 @@ BEGIN clk1_duty_cycle => 50, clk1_multiply_by => 2, clk1_phase_shift => "0", - clk2_divide_by => 181, + clk2_divide_by => 91, clk2_duty_cycle => 50, - clk2_multiply_by => 12, + clk2_multiply_by => 3, clk2_phase_shift => "0", - clk3_divide_by => 91, - clk3_duty_cycle => 50, - clk3_multiply_by => 3, - clk3_phase_shift => "0", compensate_clock => "CLK0", inclk0_input_frequency => 37037, intended_device_family => "Cyclone III", @@ -215,7 +203,7 @@ BEGIN port_clk0 => "PORT_USED", port_clk1 => "PORT_USED", port_clk2 => "PORT_USED", - port_clk3 => "PORT_USED", + port_clk3 => "PORT_UNUSED", port_clk4 => "PORT_UNUSED", port_clk5 => "PORT_UNUSED", port_clkena0 => "PORT_UNUSED", @@ -233,9 +221,9 @@ BEGIN ) PORT MAP ( areset => areset, - inclk => sub_wire7, + inclk => sub_wire6, clk => sub_wire0, - locked => sub_wire3 + locked => sub_wire2 ); @@ -263,16 +251,13 @@ END SYN; -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" -- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3" -- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9" --- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "181" --- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "91" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "91" -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "36.000000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "6.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "1.790055" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "0.890110" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "0.890110" -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -295,40 +280,32 @@ END SYN; -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" -- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" -- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" -- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4" -- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2" --- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "12" --- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "3" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "3" -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" -- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "36.00000000" -- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "6.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "1.79000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "0.89000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "0.89000000" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" -- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" -- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg" -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" -- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" @@ -353,18 +330,15 @@ END SYN; -- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" -- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" -- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" -- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" -- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: USE_CLK0 STRING "1" -- Retrieval info: PRIVATE: USE_CLK1 STRING "1" -- Retrieval info: PRIVATE: USE_CLK2 STRING "1" --- Retrieval info: PRIVATE: USE_CLK3 STRING "1" -- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" -- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" -- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" -- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all @@ -377,14 +351,10 @@ END SYN; -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" -- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "181" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "91" -- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "12" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "3" -- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "91" --- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "3" --- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" @@ -419,7 +389,7 @@ END SYN; -- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" @@ -440,7 +410,6 @@ END SYN; -- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" -- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" -- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" --- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" -- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" -- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 @@ -449,7 +418,6 @@ END SYN; -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 -- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 --- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 -- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.ppf TRUE diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/Jin_MiST.qsf b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/Jin_MiST.qsf index 47e84678..27e3786f 100644 --- a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/Jin_MiST.qsf +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/Jin_MiST.qsf @@ -18,14 +18,14 @@ # # Quartus II 64-Bit # Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 18:04:04 June 09, 2019 +# Date created = 19:59:06 June 11, 2019 # # -------------------------------------------------------------------------- # # # Notes: # # 1) The default values for assignments are stored in the file: -# Defender_MiST_assignment_defaults.qdf +# Jin_MiST_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # @@ -52,12 +52,10 @@ set_global_assignment -name VHDL_FILE rtl/defender_sound.vhd set_global_assignment -name VHDL_FILE rtl/defender_decoder_3.vhd set_global_assignment -name VHDL_FILE rtl/defender_decoder_2.vhd set_global_assignment -name VHDL_FILE rtl/defender_cmos_ram.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/YM2149.sv set_global_assignment -name VHDL_FILE rtl/pia6821.vhd set_global_assignment -name VHDL_FILE rtl/cpu68.vhd set_global_assignment -name VHDL_FILE rtl/cpu09l_128.vhd set_global_assignment -name QIP_FILE rtl/pll_mist.qip -set_global_assignment -name VERILOG_FILE rtl/data_io.v set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd set_global_assignment -name VHDL_FILE rtl/dac.vhd @@ -183,8 +181,28 @@ set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall -# --------------------------- -# start ENTITY(Defender_MiST) +# ---------------------- +# start ENTITY(Jin_MiST) + + # Pin & Location Assignments + # ========================== + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*] + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*] + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0] + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1] + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS + set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*] + set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*] + + # Fitter Assignments + # ================== + set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_* + set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_* # start DESIGN_PARTITION(Top) # --------------------------- @@ -194,10 +212,10 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top # end DESIGN_PARTITION(Top) # ------------------------- -# end ENTITY(Defender_MiST) -# ------------------------- -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file +# end ENTITY(Jin_MiST) +# -------------------- \ No newline at end of file diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/ReadMe.txt b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/ReadMe.txt index 4e5a5bfd..255d7363 100644 --- a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/ReadMe.txt +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/ReadMe.txt @@ -1,6 +1,35 @@ -Williams Jin +--------------------------------------------------------------------------------- +-- +-- Arcade: Jin port to MiST by Gehstock +-- 11 June 2019 +-- +--------------------------------------------------------------------------------- +-- A simulation model of Williams 6809 hardware +-- by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr + +--------------------------------------------------------------------------------- +-- +-- Only controls and OSD are rotated on Video output. +-- +-- +-- Keyboard inputs : +-- +-- +-- Keyboard inputs : +-- +-- ESC : Coin +-- F1 : Start 1 player +-- F2 : Start 2 player +-- SPACE : ? +-- Control : ? +-- ARROW KEYS : Movements +-- +-- Joystick support. +-- +-- +--------------------------------------------------------------------------------- -Port to MiST JIN.ROM is required at the root of the SD-Card. diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/Release/Jin_MiST.rbf b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/Release/Jin_MiST.rbf index 6eccda88..cbcc7a1f 100644 Binary files a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/Release/Jin_MiST.rbf and b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/Release/Jin_MiST.rbf differ diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/Jin_MiST.sv b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/Jin_MiST.sv index dd2b83fa..68b498cf 100644 --- a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/Jin_MiST.sv +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/Jin_MiST.sv @@ -39,20 +39,20 @@ localparam CONF_STR = { "O2,Rotate Controls,Off,On;", "O34,Scanlines,Off,25%,50%,75%;", "T6,Reset;", - "V,v1.0.5",`BUILD_DATE + "V,v1.1.0",`BUILD_DATE }; assign LED = 1; +assign AUDIO_R = AUDIO_L; -wire clk_sys, clock_6, clock_1p79, clock_0p89; +wire clk_sys, clock_6, clock_0p89; wire pll_locked; pll_mist pll( .inclk0(CLOCK_27), .areset(0), .c0(clk_sys),//36 .c1(clock_6),//6 - .c2(clock_1p79),//1.79 - .c3(clock_0p89),//0.89 + .c2(clock_0p89),//0.89 .locked(pll_locked) ); @@ -70,9 +70,9 @@ wire blankn; wire [2:0] r,g; wire [1:0] b; -wire [14:0] cart_addr; -wire [15:0] sdram_do; -wire cart_rd; +wire [14:0] rom_addr; +wire [15:0] rom_do; +wire rom_rd; wire ioctl_downl; wire [7:0] ioctl_index; wire ioctl_wr; @@ -99,11 +99,11 @@ sdram cart .init ( ~pll_locked ), .clk ( clk_sys ), .wtbt ( 2'b00 ), - .dout ( sdram_do ), + .dout ( rom_do ), .din ( {ioctl_dout, ioctl_dout} ), - .addr ( ioctl_downl ? ioctl_addr : cart_addr ), + .addr ( ioctl_downl ? ioctl_addr : rom_addr ), .we ( ioctl_downl & ioctl_wr ), - .rd ( !ioctl_downl), + .rd ( !ioctl_downl & rom_rd ), .ready() ); @@ -118,34 +118,34 @@ always @(posedge clk_sys) begin end defender defender ( - .clock_6 (clock_6), - .clk_1p79 (clock_1p79), - .clk_0p89 (clock_0p89), - .reset ( reset ), + .clock_6 ( clock_6 ), + .clk_0p89 ( clock_0p89 ), + .reset ( reset ), - .video_r ( r ), - .video_g ( g ), - .video_b ( b ), - .video_hs ( hs ), - .video_vs ( vs ), - .video_blankn ( blankn ), + .video_r ( r ), + .video_g ( g ), + .video_b ( b ), + .video_hs ( hs ), + .video_vs ( vs ), + .video_blankn ( blankn ), - .audio_out ( audio ), + .audio_out ( audio ), - .roms_addr ( cart_addr ), - .roms_do ( sdram_do[7:0] ), + .roms_addr ( rom_addr ), + .roms_do ( rom_do[7:0] ), + .vma ( rom_rd ), - .btn_two_players ( btn_two_players ), - .btn_one_player ( btn_one_player ), - .btn_left_coin ( btn_coin ), + .btn_two_players ( btn_two_players ), + .btn_one_player ( btn_one_player ), + .btn_left_coin ( btn_coin ), - .btn_fire(m_fire), - .btn_fire2(m_bomb), + .btn_fire (m_fire ), + .btn_fire2 (m_bomb ), - .btn_left(m_left), - .btn_right(m_right), - .btn_down(m_down), - .btn_up(m_up) + .btn_left (m_left ), + .btn_right (m_right ), + .btn_down (m_down ), + .btn_up (m_up ) ); mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video( @@ -190,17 +190,13 @@ user_io( .status (status ) ); -wire dac_o; -assign AUDIO_L = dac_o; -assign AUDIO_R = dac_o; - dac #( .C_bits(15)) dac( .clk_i(clk_sys), .res_n_i(1), .dac_i({audio,audio}), - .dac_o(dac_o) + .dac_o(AUDIO_L) ); // Rotated Normal @@ -219,7 +215,6 @@ reg btn_down = 0; reg btn_up = 0; reg btn_fire1 = 0; reg btn_fire2 = 0; -reg btn_fire3 = 0; reg btn_coin = 0; wire key_pressed; wire [7:0] key_code; @@ -235,7 +230,6 @@ always @(posedge clk_sys) begin 'h76: btn_coin <= key_pressed; // ESC 'h05: btn_one_player <= key_pressed; // F1 'h06: btn_two_players <= key_pressed; // F2 - 'h14: btn_fire3 <= key_pressed; // ctrl 'h11: btn_fire2 <= key_pressed; // alt 'h29: btn_fire1 <= key_pressed; // Space endcase diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/YM2149.sv b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/YM2149.sv deleted file mode 100644 index eae73bb3..00000000 --- a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/YM2149.sv +++ /dev/null @@ -1,329 +0,0 @@ -// -// Copyright (c) MikeJ - Jan 2005 -// Copyright (c) 2016-2018 Sorgelig -// -// All rights reserved -// -// Redistribution and use in source and synthezised forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// Redistributions in synthesized form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// -// Neither the name of the author nor the names of other contributors may -// be used to endorse or promote products derived from this software without -// specific prior written permission. -// -// THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. -// - - -// BDIR BC MODE -// 0 0 inactive -// 0 1 read value -// 1 0 write value -// 1 1 set address -// - -module YM2149 -( - input CLK, // Global clock - input CE, // PSG Clock enable - input RESET, // Chip RESET (set all Registers to '0', active hi) - input BDIR, // Bus Direction (0 - read , 1 - write) - input BC, // Bus control - input A8, - input A9_L, - input [7:0] DI, // Data In - output [7:0] DO, // Data Out - output [7:0] CHANNEL_A, // PSG Output channel A - output [7:0] CHANNEL_B, // PSG Output channel B - output [7:0] CHANNEL_C, // PSG Output channel C - - input SEL, - input MODE, - - output [5:0] ACTIVE, - - input [7:0] IOA_in, - output [7:0] IOA_out, - - input [7:0] IOB_in, - output [7:0] IOB_out -); - -assign ACTIVE = ~ymreg[7][5:0]; -assign IOA_out = ymreg[7][6] ? ymreg[14] : 8'hff; -assign IOB_out = ymreg[7][7] ? ymreg[15] : 8'hff; - -reg [7:0] addr; -reg [7:0] ymreg[16]; -wire cs = !A9_L & A8; - -// Write to PSG -reg env_reset; -always @(posedge CLK) begin - if(RESET) begin - ymreg <= '{default:0}; - ymreg[7] <= '1; - addr <= '0; - env_reset <= 0; - end else begin - env_reset <= 0; - if(cs & BDIR) begin - if(BC) addr <= DI; - else if(!addr[7:4]) begin - ymreg[addr[3:0]] <= DI; - env_reset <= (addr == 13); - end - end - end -end - -// Read from PSG -assign DO = dout; -reg [7:0] dout; -always_comb begin - dout = 8'hFF; - if(cs & ~BDIR & BC & !addr[7:4]) begin - case(addr[3:0]) - 0: dout = ymreg[0]; - 1: dout = ymreg[1][3:0]; - 2: dout = ymreg[2]; - 3: dout = ymreg[3][3:0]; - 4: dout = ymreg[4]; - 5: dout = ymreg[5][3:0]; - 6: dout = ymreg[6][4:0]; - 7: dout = ymreg[7]; - 8: dout = ymreg[8][4:0]; - 9: dout = ymreg[9][4:0]; - 10: dout = ymreg[10][4:0]; - 11: dout = ymreg[11]; - 12: dout = ymreg[12]; - 13: dout = ymreg[13][3:0]; - 14: dout = ymreg[7][6] ? ymreg[14] : IOA_in; - 15: dout = ymreg[7][7] ? ymreg[15] : IOB_in; - endcase - end -end - -reg ena_div; -reg ena_div_noise; - -// p_divider -always @(posedge CLK) begin - reg [3:0] cnt_div; - reg noise_div; - - if(CE) begin - ena_div <= 0; - ena_div_noise <= 0; - if(!cnt_div) begin - cnt_div <= {SEL, 3'b111}; - ena_div <= 1; - - noise_div <= (~noise_div); - if (noise_div) ena_div_noise <= 1; - end else begin - cnt_div <= cnt_div - 1'b1; - end - end -end - - -reg [2:0] noise_gen_op; - -// p_noise_gen -always @(posedge CLK) begin - reg [16:0] poly17; - reg [4:0] noise_gen_cnt; - - if(CE) begin - if (ena_div_noise) begin - if (!ymreg[6][4:0] || noise_gen_cnt >= ymreg[6][4:0] - 1'd1) begin - noise_gen_cnt <= 0; - poly17 <= {(poly17[0] ^ poly17[2] ^ !poly17), poly17[16:1]}; - end else begin - noise_gen_cnt <= noise_gen_cnt + 1'd1; - end - noise_gen_op <= {3{poly17[0]}}; - end - end -end - -wire [11:0] tone_gen_freq[1:3]; -assign tone_gen_freq[1] = {ymreg[1][3:0], ymreg[0]}; -assign tone_gen_freq[2] = {ymreg[3][3:0], ymreg[2]}; -assign tone_gen_freq[3] = {ymreg[5][3:0], ymreg[4]}; - -reg [3:1] tone_gen_op; - -//p_tone_gens -always @(posedge CLK) begin - integer i; - reg [11:0] tone_gen_cnt[1:3]; - - if(CE) begin - // looks like real chips count up - we need to get the Exact behaviour .. - - for (i = 1; i <= 3; i = i + 1) begin - if(ena_div) begin - if (tone_gen_freq[i]) begin - if (tone_gen_cnt[i] >= (tone_gen_freq[i] - 1'd1)) begin - tone_gen_cnt[i] <= 0; - tone_gen_op[i] <= ~tone_gen_op[i]; - end else begin - tone_gen_cnt[i] <= tone_gen_cnt[i] + 1'd1; - end - end else begin - tone_gen_op[i] <= ymreg[7][i]; - tone_gen_cnt[i] <= 0; - end - end - end - end -end - -reg env_ena; -wire [15:0] env_gen_comp = {ymreg[12], ymreg[11]} ? {ymreg[12], ymreg[11]} - 1'd1 : 16'd0; - -//p_envelope_freq -always @(posedge CLK) begin - reg [15:0] env_gen_cnt; - - if(CE) begin - env_ena <= 0; - if(ena_div) begin - if (env_gen_cnt >= env_gen_comp) begin - env_gen_cnt <= 0; - env_ena <= 1; - end else begin - env_gen_cnt <= (env_gen_cnt + 1'd1); - end - end - end -end - -reg [4:0] env_vol; - -wire is_bot = (env_vol == 5'b00000); -wire is_bot_p1 = (env_vol == 5'b00001); -wire is_top_m1 = (env_vol == 5'b11110); -wire is_top = (env_vol == 5'b11111); - -always @(posedge CLK) begin - reg env_hold; - reg env_inc; - - // envelope shapes - // C AtAlH - // 0 0 x x \___ - // - // 0 1 x x /___ - // - // 1 0 0 0 \\\\ - // - // 1 0 0 1 \___ - // - // 1 0 1 0 \/\/ - // ___ - // 1 0 1 1 \ - // - // 1 1 0 0 //// - // ___ - // 1 1 0 1 / - // - // 1 1 1 0 /\/\ - // - // 1 1 1 1 /___ - - if(env_reset | RESET) begin - // load initial state - if(!ymreg[13][2]) begin // attack - env_vol <= 5'b11111; - env_inc <= 0; // -1 - end else begin - env_vol <= 5'b00000; - env_inc <= 1; // +1 - end - env_hold <= 0; - end - else if(CE) begin - if (env_ena) begin - if (!env_hold) begin - if (env_inc) env_vol <= (env_vol + 5'b00001); - else env_vol <= (env_vol + 5'b11111); - end - - // envelope shape control. - if(!ymreg[13][3]) begin - if(!env_inc) begin // down - if(is_bot_p1) env_hold <= 1; - end else if (is_top) env_hold <= 1; - end else if(ymreg[13][0]) begin // hold = 1 - if(!env_inc) begin // down - if(ymreg[13][1]) begin // alt - if(is_bot) env_hold <= 1; - end else if(is_bot_p1) env_hold <= 1; - end else if(ymreg[13][1]) begin // alt - if(is_top) env_hold <= 1; - end else if(is_top_m1) env_hold <= 1; - end else if(ymreg[13][1]) begin // alternate - if(env_inc == 1'b0) begin // down - if(is_bot_p1) env_hold <= 1; - if(is_bot) begin - env_hold <= 0; - env_inc <= 1; - end - end else begin - if(is_top_m1) env_hold <= 1; - if(is_top) begin - env_hold <= 0; - env_inc <= 0; - end - end - end - end - end -end - -reg [5:0] A,B,C; -always @(posedge CLK) begin - A <= {MODE, ~((ymreg[7][0] | tone_gen_op[1]) & (ymreg[7][3] | noise_gen_op[0])) ? 5'd0 : ymreg[8][4] ? env_vol[4:0] : { ymreg[8][3:0], ymreg[8][3]}}; - B <= {MODE, ~((ymreg[7][1] | tone_gen_op[2]) & (ymreg[7][4] | noise_gen_op[1])) ? 5'd0 : ymreg[9][4] ? env_vol[4:0] : { ymreg[9][3:0], ymreg[9][3]}}; - C <= {MODE, ~((ymreg[7][2] | tone_gen_op[3]) & (ymreg[7][5] | noise_gen_op[2])) ? 5'd0 : ymreg[10][4] ? env_vol[4:0] : {ymreg[10][3:0], ymreg[10][3]}}; -end - -wire [7:0] volTable[64] = '{ - //YM2149 - 8'h00, 8'h01, 8'h01, 8'h02, 8'h02, 8'h03, 8'h03, 8'h04, - 8'h06, 8'h07, 8'h09, 8'h0a, 8'h0c, 8'h0e, 8'h11, 8'h13, - 8'h17, 8'h1b, 8'h20, 8'h25, 8'h2c, 8'h35, 8'h3e, 8'h47, - 8'h54, 8'h66, 8'h77, 8'h88, 8'ha1, 8'hc0, 8'he0, 8'hff, - - //AY8910 - 8'h00, 8'h00, 8'h03, 8'h03, 8'h04, 8'h04, 8'h06, 8'h06, - 8'h0a, 8'h0a, 8'h0f, 8'h0f, 8'h15, 8'h15, 8'h22, 8'h22, - 8'h28, 8'h28, 8'h41, 8'h41, 8'h5b, 8'h5b, 8'h72, 8'h72, - 8'h90, 8'h90, 8'hb5, 8'hb5, 8'hd7, 8'hd7, 8'hff, 8'hff -}; - -assign CHANNEL_A = volTable[A]; -assign CHANNEL_B = volTable[B]; -assign CHANNEL_C = volTable[C]; - -endmodule diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/data_io.v b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/data_io.v deleted file mode 100644 index 4ca9518c..00000000 --- a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/data_io.v +++ /dev/null @@ -1,115 +0,0 @@ -// -// data_io.v -// -// data_io for the MiST board -// http://code.google.com/p/mist-board/ -// -// Copyright (c) 2014 Till Harbaum -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -/////////////////////////////////////////////////////////////////////// - -module data_io -( - input clk_sys, - input SPI_SCK, - input SPI_SS2, - input SPI_DI, - - // ARM -> FPGA download - output reg ioctl_download = 0, // signal indicating an active download - output reg [7:0] ioctl_index, // menu index used to upload the file - output ioctl_wr, - output reg [24:0] ioctl_addr, - output reg [7:0] ioctl_dout -); - -/////////////////////////////// DOWNLOADING /////////////////////////////// - -reg [7:0] data_w; -reg [24:0] addr_w; -reg rclk = 0; - -localparam UIO_FILE_TX = 8'h53; -localparam UIO_FILE_TX_DAT = 8'h54; -localparam UIO_FILE_INDEX = 8'h55; - -// data_io has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS2) begin - reg [6:0] sbuf; - reg [7:0] cmd; - reg [4:0] cnt; - reg [24:0] addr; - - if(SPI_SS2) cnt <= 0; - else begin - rclk <= 0; - - // don't shift in last bit. It is evaluated directly - // when writing to ram - if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; - - // increase target address after write - if(rclk) addr <= addr + 1'd1; - - // count 0-7 8-15 8-15 ... - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - // finished command byte - if(cnt == 7) cmd <= {sbuf, SPI_DI}; - - // prepare/end transmission - if((cmd == UIO_FILE_TX) && (cnt == 15)) begin - // prepare - if(SPI_DI) begin - addr <= 0; - ioctl_download <= 1; - end else begin - addr_w <= addr; - ioctl_download <= 0; - end - end - - // command 0x54: UIO_FILE_TX - if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin - addr_w <= addr; - data_w <= {sbuf, SPI_DI}; - rclk <= 1; - end - - // expose file (menu) index - if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; - end -end - -assign ioctl_wr = |ioctl_wrd; -reg [1:0] ioctl_wrd; - -always@(negedge clk_sys) begin - reg rclkD, rclkD2; - - rclkD <= rclk; - rclkD2 <= rclkD; - ioctl_wrd<= {ioctl_wrd[0],1'b0}; - - if(rclkD & ~rclkD2) begin - ioctl_dout <= data_w; - ioctl_addr <= addr_w; - ioctl_wrd <= 2'b11; - end -end - -endmodule diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/defender.vhd b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/defender.vhd index 2ac38c26..6d4de71e 100644 --- a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/defender.vhd +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/defender.vhd @@ -123,43 +123,33 @@ use ieee.numeric_std.all; entity defender is port( - clk_sys : in std_logic; - clock_6 : in std_logic; - clk_1p79 : in std_logic; - clk_0p89 : in std_logic; - reset : in std_logic; - - dbg_cpu_addr : out std_logic_vector(15 downto 0); --- tv15Khz_mode : in std_logic; - video_r : out std_logic_vector(2 downto 0); - video_g : out std_logic_vector(2 downto 0); - video_b : out std_logic_vector(1 downto 0); --- video_clk : out std_logic; - video_csync : out std_logic; - video_blankn : out std_logic; - video_hs : out std_logic; - video_vs : out std_logic; - - audio_out : out std_logic_vector(7 downto 0); - - roms_addr : out std_logic_vector(14 downto 0); - roms_do : in std_logic_vector( 7 downto 0); - - btn_left_coin : in std_logic; - btn_one_player : in std_logic; - btn_two_players: in std_logic; - - btn_fire : in std_logic; - btn_fire2 : in std_logic; - btn_right : in std_logic; - btn_left : in std_logic; - btn_down : in std_logic; - btn_up : in std_logic; - - sw_coktail_table : in std_logic; - - cmd_select_players_btn : out std_logic + clk_sys : in std_logic; + clock_6 : in std_logic; + clk_0p89 : in std_logic; + reset : in std_logic; + video_r : out std_logic_vector(2 downto 0); + video_g : out std_logic_vector(2 downto 0); + video_b : out std_logic_vector(1 downto 0); + video_csync : out std_logic; + video_blankn : out std_logic; + video_hs : out std_logic; + video_vs : out std_logic; + audio_out : out std_logic_vector(7 downto 0); + roms_addr : out std_logic_vector(14 downto 0); + roms_do : in std_logic_vector( 7 downto 0); + vma : out std_logic; + btn_left_coin : in std_logic; + btn_one_player : in std_logic; + btn_two_players : in std_logic; + btn_fire : in std_logic; + btn_fire2 : in std_logic; + btn_right : in std_logic; + btn_left : in std_logic; + btn_down : in std_logic; + btn_up : in std_logic; + sw_coktail : in std_logic; + select_players : out std_logic ); end defender; @@ -169,8 +159,6 @@ architecture struct of defender is signal clock_div : std_logic_vector(1 downto 0); signal clock_6n : std_logic; - - signal cpu_clock : std_logic; signal cpu_addr : std_logic_vector(15 downto 0); signal cpu_di : std_logic_vector( 7 downto 0); signal cpu_do : std_logic_vector( 7 downto 0); @@ -185,10 +173,6 @@ architecture struct of defender is signal wram1_we : std_logic; signal wram2_do : std_logic_vector( 7 downto 0); signal wram2_we : std_logic; - - --signal roms_addr : std_logic_vector(14 downto 0); - --signal roms_do : std_logic_vector( 7 downto 0); - signal roms_io_do : std_logic_vector( 7 downto 0); signal io_we : std_logic; @@ -283,16 +267,13 @@ architecture struct of defender is signal hsync0,hsync1,hsync2,csync,hblank,vblank : std_logic; - signal select_sound : std_logic_vector(5 downto 0); + signal select_sound : std_logic_vector(5 downto 0); + signal cpu_ce : std_logic; begin clock_6n <= not clock_6; -reset_n <= not reset; - --- for debug -dbg_cpu_addr <= cpu_addr; - +reset_n <= not reset; -- make pixels counters and cpu clock -- in original hardware cpu clock = 1us = 6pixels @@ -301,30 +282,15 @@ process (reset, clock_6n) begin if reset='1' then pixel_cnt <= "000"; - cpu_clock <= '0'; + else if rising_edge(clock_6n) then if pixel_cnt = "101" then pixel_cnt <= "000"; - cpu_clock <= '0'; else pixel_cnt <= pixel_cnt + '1'; - end if; - - if pixel_cnt = "010" then - cpu_clock <= '1'; - end if; - - if pixel_cnt = "011" then -- speed up processor (two clocks / 1us) - cpu_clock <= '0'; - end if; - - if pixel_cnt = "100" then - cpu_clock <= '1'; - end if; - - + end if; end if; end if; end process; @@ -388,7 +354,7 @@ video_scan_addr <= screen_ctrl & vcnt(7 downto 0); -- mux cpu addr/scan addr to wram wram_addr <= - cpu_addr(7 downto 0) & cpu_to_video_do(5 downto 0) when cpu_clock = '1' else + cpu_addr(7 downto 0) & cpu_to_video_do(5 downto 0) when cpu_ce = '1' else video_scan_do & hcnt; -- mux cpu addr/pixels data to palette addr @@ -427,14 +393,14 @@ begin end process; -- pias cs -io_cs <= '1' when cpu_clock = '1' and cpu_addr(15 downto 12) = X"C" and rom_page ="000" else '0'; +io_cs <= '1' when cpu_ce = '1' and cpu_addr(15 downto 12) = X"C" and rom_page ="000" else '0'; pia_rom_cs <= '1' when io_cs = '1' and cpu_addr(11 downto 10) = "11" and cpu_addr(2) = '0' else '0'; -- CC00-CC03 pia_io_cs <= '1' when io_cs = '1' and cpu_addr(11 downto 10) = "11" and cpu_addr(2) = '1' else '0'; -- CC04-CC07 -- write enables -wram_we <= '1' when cpu_rw = '0' and cpu_clock = '1' and cpu_addr(15 downto 12) < X"C" else '0'; -io_we <= '1' when cpu_rw = '0' and cpu_clock = '1' and cpu_addr(15 downto 12) = X"C" and rom_page ="000" else '0'; -rom_page_we <= '1' when cpu_rw = '0' and cpu_clock = '1' and cpu_addr(15 downto 12) = X"D" else '0'; +wram_we <= '1' when cpu_rw = '0' and cpu_ce = '1' and cpu_addr(15 downto 12) < X"C" else '0'; +io_we <= '1' when cpu_rw = '0' and cpu_ce = '1' and cpu_addr(15 downto 12) = X"C" and rom_page ="000" else '0'; +rom_page_we <= '1' when cpu_rw = '0' and cpu_ce = '1' and cpu_addr(15 downto 12) = X"D" else '0'; palette_we <= '1' when io_we = '1' and cpu_addr(11 downto 10) = "00" and cpu_addr(4) = '0' else '0'; -- C000-C00F screen_ctrl_we <= '1' when io_we = '1' and cpu_addr(11 downto 10) = "00" and cpu_addr(4) = '1' else '0'; -- C010-C01F @@ -516,7 +482,7 @@ pia_io_pb_i <= "00000000";--unknown/Level completed/Level completed/unknown/Live -- IN2 -- pia io ca/cb -cmd_select_players_btn <= pia_io_cb2_o; +select_players <= pia_io_cb2_o; -- pia rom ca1/Cb1 vcnt_240 <= '1' when vcnt(7 downto 4) = X"F" else '0'; @@ -528,13 +494,14 @@ cpu_irq <= pia_rom_irqa or pia_rom_irqb; -- pia rom to sound board select_sound <= pia_rom_pb_o(5 downto 0); +cpu_ce <= '1' when pixel_cnt = "100" or pixel_cnt = "010" else '0'; -- microprocessor 6809 main_cpu : entity work.cpu09 port map( - clk => cpu_clock,-- E clock input (falling edge) + clk => clock_6,-- E clock input (falling edge) rst => reset, -- reset input (active high) - vma => open, -- valid memory address (active high) + vma => vma, -- valid memory address (active high) lic_out => open, -- last instruction cycle (active high) ifetch => open, -- instruction fetch cycle (active high) opfetch => open, -- opcode fetch (active high) @@ -548,7 +515,7 @@ port map( firq => '0', -- fast interrupt request input (active high) nmi => '0', -- non maskable interrupt request input (active high) halt => '0', -- halt input (active high) grants DMA - hold => '0' -- hold input (active high) extend bus cycle + hold => not cpu_ce-- hold input (active high) extend bus cycle ); -- cpu program rom @@ -746,10 +713,10 @@ if rising_edge(clock_6n) then end if; if hcnt = hcnt_base-2 then hblank <= '1'; - elsif hcnt = hcnt_base+11-64 then hblank <= '0'; + elsif hcnt = hcnt_base+12-64 then hblank <= '0'; end if; - if vcnt = 492 then vblank <= '1'; -- 492 ok + if vcnt = 502 then vblank <= '1'; -- 492 ok elsif vcnt = 262 then vblank <= '0'; -- 262 ok end if; @@ -768,13 +735,10 @@ end process; -- sound board defender_sound_board : entity work.defender_sound_board port map( - clk_1p79 => clk_1p79, clk_0p89 => clk_0p89, reset => reset, select_sound => select_sound, - audio_out => audio_out, - - dbg_cpu_addr => open --dbg_cpu_addr + audio_out => audio_out ); end struct; \ No newline at end of file diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/defender_sound_board.vhd b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/defender_sound_board.vhd index 5fdd8293..0f295241 100644 --- a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/defender_sound_board.vhd +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/defender_sound_board.vhd @@ -27,22 +27,16 @@ use ieee.numeric_std.all; entity defender_sound_board is port( - clk_1p79 : in std_logic; clk_0p89 : in std_logic; reset : in std_logic; - select_sound : in std_logic_vector(5 downto 0); - audio_out : out std_logic_vector( 7 downto 0); - - dbg_cpu_addr : out std_logic_vector(15 downto 0) + audio_out : out std_logic_vector( 7 downto 0) ); end defender_sound_board; architecture struct of defender_sound_board is signal reset_n : std_logic; - - signal cpu_clock : std_logic; signal cpu_addr : std_logic_vector(15 downto 0); signal cpu_di : std_logic_vector( 7 downto 0); signal cpu_do : std_logic_vector( 7 downto 0); @@ -70,7 +64,6 @@ architecture struct of defender_sound_board is -- ca2 speech data N/C -- cb2 speech clock N/C - signal pia_clock : std_logic; signal pia_rw_n : std_logic; signal pia_cs : std_logic; signal pia_irqa : std_logic; @@ -84,18 +77,14 @@ begin reset_n <= not reset; -dbg_cpu_addr <= cpu_addr; -cpu_clock <= clk_0p89; - - -- pia cs wram_cs <= '1' when cpu_addr(15 downto 8) = X"00" else '0'; -- 0000-007F pia_cs <= '1' when cpu_addr(15 downto 12) = X"0" and cpu_addr(10) = '1' else '0'; -- 8400-8403 ? => 0400-0403 rom_cs <= '1' when cpu_addr(15 downto 12) = X"F" else '0'; -- F800-FFFF -- write enables -wram_we <= '1' when cpu_rw = '0' and cpu_clock = '1' and wram_cs = '1' else '0'; -pia_rw_n <= '0' when cpu_rw = '0' and cpu_clock = '1' and pia_cs = '1' else '1'; +wram_we <= '1' when cpu_rw = '0' and wram_cs = '1' else '0'; +pia_rw_n <= '0' when cpu_rw = '0' and pia_cs = '1' else '1'; -- mux cpu in data between roms/io/wram cpu_di <= @@ -104,7 +93,6 @@ cpu_di <= rom_do when rom_cs = '1' else X"55"; -- pia I/O -pia_clock <= clk_1p79; -- 3p58/2 audio_out <= pia_pa_o; pia_pb_i(4 downto 0) <= select_sound(4 downto 0); @@ -120,7 +108,7 @@ cpu_irq <= pia_irqa or pia_irqb; -- microprocessor 6800 main_cpu : entity work.cpu68 port map( - clk => cpu_clock,-- E clock input (falling edge) + clk => clk_0p89,-- E clock input (falling edge) rst => reset, -- reset input (active high) rw => cpu_rw, -- read not write output vma => open, -- valid memory address (active high) @@ -138,7 +126,7 @@ port map( -- cpu program rom cpu_prog_rom : entity work.defender_sound port map( - clk => clk_1p79, + clk => clk_0p89, addr => cpu_addr(10 downto 0), data => rom_do ); @@ -147,7 +135,7 @@ port map( cpu_ram : entity work.gen_ram generic map( dWidth => 8, aWidth => 7) port map( - clk => clk_1p79, + clk => clk_0p89, we => wram_we, addr => cpu_addr(6 downto 0), d => cpu_do, @@ -158,7 +146,7 @@ port map( pia : entity work.pia6821 port map ( - clk => clk_1p79, + clk => clk_0p89, rst => reset, cs => pia_cs, rw => pia_rw_n, diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/pll_mist.ppf b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/pll_mist.ppf index db79bfc9..c8ed5c67 100644 --- a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/pll_mist.ppf +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/pll_mist.ppf @@ -7,7 +7,6 @@ - diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/pll_mist.vhd b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/pll_mist.vhd index b54b7a75..1bd8e50f 100644 --- a/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/pll_mist.vhd +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Jin/rtl/pll_mist.vhd @@ -47,7 +47,6 @@ ENTITY pll_mist IS c0 : OUT STD_LOGIC ; c1 : OUT STD_LOGIC ; c2 : OUT STD_LOGIC ; - c3 : OUT STD_LOGIC ; locked : OUT STD_LOGIC ); END pll_mist; @@ -61,10 +60,9 @@ ARCHITECTURE SYN OF pll_mist IS SIGNAL sub_wire3 : STD_LOGIC ; SIGNAL sub_wire4 : STD_LOGIC ; SIGNAL sub_wire5 : STD_LOGIC ; - SIGNAL sub_wire6 : STD_LOGIC ; - SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire8_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); @@ -83,10 +81,6 @@ ARCHITECTURE SYN OF pll_mist IS clk2_duty_cycle : NATURAL; clk2_multiply_by : NATURAL; clk2_phase_shift : STRING; - clk3_divide_by : NATURAL; - clk3_duty_cycle : NATURAL; - clk3_multiply_by : NATURAL; - clk3_phase_shift : STRING; compensate_clock : STRING; inclk0_input_frequency : NATURAL; intended_device_family : STRING; @@ -147,19 +141,17 @@ ARCHITECTURE SYN OF pll_mist IS END COMPONENT; BEGIN - sub_wire8_bv(0 DOWNTO 0) <= "0"; - sub_wire8 <= To_stdlogicvector(sub_wire8_bv); - sub_wire5 <= sub_wire0(2); - sub_wire4 <= sub_wire0(0); - sub_wire2 <= sub_wire0(3); + sub_wire7_bv(0 DOWNTO 0) <= "0"; + sub_wire7 <= To_stdlogicvector(sub_wire7_bv); + sub_wire4 <= sub_wire0(2); + sub_wire3 <= sub_wire0(0); sub_wire1 <= sub_wire0(1); c1 <= sub_wire1; - c3 <= sub_wire2; - locked <= sub_wire3; - c0 <= sub_wire4; - c2 <= sub_wire5; - sub_wire6 <= inclk0; - sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6; + locked <= sub_wire2; + c0 <= sub_wire3; + c2 <= sub_wire4; + sub_wire5 <= inclk0; + sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; altpll_component : altpll GENERIC MAP ( @@ -172,14 +164,10 @@ BEGIN clk1_duty_cycle => 50, clk1_multiply_by => 2, clk1_phase_shift => "0", - clk2_divide_by => 181, + clk2_divide_by => 91, clk2_duty_cycle => 50, - clk2_multiply_by => 12, + clk2_multiply_by => 3, clk2_phase_shift => "0", - clk3_divide_by => 91, - clk3_duty_cycle => 50, - clk3_multiply_by => 3, - clk3_phase_shift => "0", compensate_clock => "CLK0", inclk0_input_frequency => 37037, intended_device_family => "Cyclone III", @@ -215,7 +203,7 @@ BEGIN port_clk0 => "PORT_USED", port_clk1 => "PORT_USED", port_clk2 => "PORT_USED", - port_clk3 => "PORT_USED", + port_clk3 => "PORT_UNUSED", port_clk4 => "PORT_UNUSED", port_clk5 => "PORT_UNUSED", port_clkena0 => "PORT_UNUSED", @@ -233,9 +221,9 @@ BEGIN ) PORT MAP ( areset => areset, - inclk => sub_wire7, + inclk => sub_wire6, clk => sub_wire0, - locked => sub_wire3 + locked => sub_wire2 ); @@ -263,16 +251,13 @@ END SYN; -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" -- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3" -- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9" --- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "181" --- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "91" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "91" -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "36.000000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "6.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "1.790055" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "0.890110" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "0.890110" -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -295,40 +280,32 @@ END SYN; -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" -- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" -- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" -- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4" -- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2" --- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "12" --- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "3" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "3" -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" -- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "36.00000000" -- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "6.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "1.79000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "0.89000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "0.89000000" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" -- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" -- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg" -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" -- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" @@ -353,18 +330,15 @@ END SYN; -- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" -- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" -- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" -- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" -- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: USE_CLK0 STRING "1" -- Retrieval info: PRIVATE: USE_CLK1 STRING "1" -- Retrieval info: PRIVATE: USE_CLK2 STRING "1" --- Retrieval info: PRIVATE: USE_CLK3 STRING "1" -- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" -- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" -- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" -- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all @@ -377,14 +351,10 @@ END SYN; -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" -- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "181" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "91" -- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "12" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "3" -- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "91" --- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "3" --- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" @@ -419,7 +389,7 @@ END SYN; -- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" @@ -440,7 +410,6 @@ END SYN; -- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" -- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" -- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" --- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" -- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" -- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 @@ -449,7 +418,6 @@ END SYN; -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 -- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 --- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 -- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.ppf TRUE diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Mayday/Mayday.qsf b/Arcade_MiST/Williams 6809 rev.1 Hardware/Mayday/Mayday.qsf index a4bb174b..baf7e096 100644 --- a/Arcade_MiST/Williams 6809 rev.1 Hardware/Mayday/Mayday.qsf +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Mayday/Mayday.qsf @@ -18,14 +18,14 @@ # # Quartus II 64-Bit # Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 18:04:04 June 09, 2019 +# Date created = 19:25:26 June 11, 2019 # # -------------------------------------------------------------------------- # # # Notes: # # 1) The default values for assignments are stored in the file: -# Defender_MiST_assignment_defaults.qdf +# Mayday_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # @@ -52,15 +52,13 @@ set_global_assignment -name VHDL_FILE rtl/defender_sound.vhd set_global_assignment -name VHDL_FILE rtl/defender_decoder_3.vhd set_global_assignment -name VHDL_FILE rtl/defender_decoder_2.vhd set_global_assignment -name VHDL_FILE rtl/defender_cmos_ram.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/YM2149.sv set_global_assignment -name VHDL_FILE rtl/pia6821.vhd set_global_assignment -name VHDL_FILE rtl/cpu68.vhd set_global_assignment -name VHDL_FILE rtl/cpu09l_128.vhd -set_global_assignment -name QIP_FILE rtl/pll_mist.qip -set_global_assignment -name VERILOG_FILE rtl/data_io.v set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name VHDL_FILE rtl/pll_mist.vhd set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip # Pin & Location Assignments @@ -146,9 +144,9 @@ set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON # Analysis & Synthesis Assignments # ================================ set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name TOP_LEVEL_ENTITY Mayday_MiST set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name TOP_LEVEL_ENTITY Mayday_MiST # Fitter Assignments # ================== @@ -183,8 +181,28 @@ set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall -# --------------------------- -# start ENTITY(Defender_MiST) +# ------------------------- +# start ENTITY(Mayday_MiST) + + # Pin & Location Assignments + # ========================== + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*] + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*] + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0] + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1] + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE + set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS + set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*] + set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*] + + # Fitter Assignments + # ================== + set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_* + set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_* # start DESIGN_PARTITION(Top) # --------------------------- @@ -194,10 +212,10 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top # end DESIGN_PARTITION(Top) # ------------------------- -# end ENTITY(Defender_MiST) -# ------------------------- -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file +# end ENTITY(Mayday_MiST) +# ----------------------- \ No newline at end of file diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Mayday/ReadMe.txt b/Arcade_MiST/Williams 6809 rev.1 Hardware/Mayday/ReadMe.txt index 799e9e88..c0740115 100644 --- a/Arcade_MiST/Williams 6809 rev.1 Hardware/Mayday/ReadMe.txt +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Mayday/ReadMe.txt @@ -1,22 +1,25 @@ -Williams Mayday +--------------------------------------------------------------------------------- +-- +-- Arcade: Mayday port to MiST by Gehstock +-- 11 June 2019 +-- +--------------------------------------------------------------------------------- +-- A simulation model of Williams 6809 hardware +-- by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr -Port to MiST - -MAYDAY.ROM is required at the root of the SD-Card. - - Fire Forward = Fire or Space - Mayday = Fire2 or ALT - Fire Backward = Fire3 or CTRL - - Change Direction = Left or Right - Up = Up - Down = Down - - Advance = A - Auto up = U - Service = H - - - - -ToDo Sound is missing sometimes \ No newline at end of file +--------------------------------------------------------------------------------- +-- +-- Only controls and OSD are rotated on Video output. +-- +-- +-- Keyboard inputs : +-- +-- ESC : Coin +-- F2 : Start 2 players +-- F1 : Start 1 player +-- UP,DOWN,LEFT,RIGHT arrows : Movements +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- \ No newline at end of file diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Mayday/Release/Mayday.rbf b/Arcade_MiST/Williams 6809 rev.1 Hardware/Mayday/Release/Mayday.rbf index 8c25246c..01cc5002 100644 Binary files a/Arcade_MiST/Williams 6809 rev.1 Hardware/Mayday/Release/Mayday.rbf and b/Arcade_MiST/Williams 6809 rev.1 Hardware/Mayday/Release/Mayday.rbf differ diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Mayday/rtl/Mayday_MiST.sv b/Arcade_MiST/Williams 6809 rev.1 Hardware/Mayday/rtl/Mayday_MiST.sv index d5fcfbc3..2fc1354d 100644 --- a/Arcade_MiST/Williams 6809 rev.1 Hardware/Mayday/rtl/Mayday_MiST.sv +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Mayday/rtl/Mayday_MiST.sv @@ -32,26 +32,27 @@ module Mayday_MiST( output SDRAM_CKE ); +assign LED = 1; +assign AUDIO_R = AUDIO_L; +assign SDRAM_CLK = clk_sys; + `include "rtl/build_id.v" localparam CONF_STR = { "MAYDAY;;", "O34,Scanlines,Off,25%,50%,75%;", "T6,Reset;", - "V,v1.0.5",`BUILD_DATE + "V,v1.1.0",`BUILD_DATE }; -assign LED = 1; - -wire clk_sys, clock_6, clock_1p79, clock_0p89; +wire clk_sys, clock_6, clock_0p89; wire pll_locked; pll_mist pll( .inclk0(CLOCK_27), .areset(0), .c0(clk_sys),//36 .c1(clock_6),//6 - .c2(clock_1p79),//1.79 - .c3(clock_0p89),//0.89 + .c2(clock_0p89),//0.89 .locked(pll_locked) ); @@ -63,22 +64,22 @@ wire [7:0] joystick_1; wire scandoublerD; wire ypbpr; wire [10:0] ps2_key; -wire [7:0] audio; +wire [7:0] audio; wire hs, vs; wire blankn; wire [2:0] r,g; wire [1:0] b; -wire [14:0] cart_addr; -wire [15:0] sdram_do; -wire cart_rd; +wire [14:0] rom_addr; +wire [15:0] rom_do; +wire rom_rd; wire ioctl_downl; wire [7:0] ioctl_index; wire ioctl_wr; wire [24:0] ioctl_addr; wire [7:0] ioctl_dout; -data_io data_io ( +data_io data_io( .clk_sys ( clk_sys ), .SPI_SCK ( SPI_SCK ), .SPI_SS2 ( SPI_SS2 ), @@ -89,20 +90,17 @@ data_io data_io ( .ioctl_addr ( ioctl_addr ), .ioctl_dout ( ioctl_dout ) ); - -assign SDRAM_CLK = clk_sys; -sdram cart -( +sdram cart( .*, .init ( ~pll_locked ), .clk ( clk_sys ), .wtbt ( 2'b00 ), - .dout ( sdram_do ), + .dout ( rom_do ), .din ( {ioctl_dout, ioctl_dout} ), - .addr ( ioctl_downl ? ioctl_addr : cart_addr ), + .addr ( ioctl_downl ? ioctl_addr : rom_addr ), .we ( ioctl_downl & ioctl_wr ), - .rd ( !ioctl_downl), + .rd ( !ioctl_downl & rom_rd ), .ready() ); @@ -116,42 +114,33 @@ always @(posedge clk_sys) begin reset <= status[0] | buttons[1] | status[6] | ~rom_loaded; end -defender defender ( - .clock_6 (clock_6), - .clk_1p79 (clock_1p79), - .clk_0p89 (clock_0p89), - .reset (reset), - - .video_r ( r ), - .video_g ( g ), - .video_b ( b ), - .video_hs ( hs ), - .video_vs ( vs ), - .video_blankn ( blankn ), - - .audio_out ( audio ), - - .roms_addr ( cart_addr ), - .roms_do ( sdram_do[7:0] ), - - .btn_two_players ( btn_two_players ),// - .btn_one_player ( btn_one_player ),// - .btn_left_coin ( btn_coin ),// - - .btn_auto_up(btn_auto_up),// - .btn_advance(btn_advance),// - .btn_service(btn_service),// - - - .btn_ffire(m_fire1),//SPACE - .btn_bfire(m_fire3),//CTRL - .btn_mayday(m_fire3),//ALT - - .btn_right(m_left | m_right), - .btn_down(m_down), - .btn_up(m_up), - - .sw_coktail_table(1) +defender defender( + .clock_6 (clock_6), + .clk_0p89 (clock_0p89), + .reset (reset), + .video_r ( r ), + .video_g ( g ), + .video_b ( b ), + .video_hs ( hs ), + .video_vs ( vs ), + .video_blankn ( blankn ), + .audio_out ( audio ), + .roms_addr ( rom_addr ), + .roms_do ( rom_do[7:0] ), + .vma ( rom_rd ), + .btn_two_players ( btn_two_players ), + .btn_one_player ( btn_one_player ), + .btn_left_coin ( btn_coin ), + .btn_auto_up (btn_auto_up), + .btn_advance (btn_advance), + .btn_service (btn_service), + .btn_ffire (m_fire1), + .btn_bfire (m_fire2), + .btn_mayday (m_fire3), + .btn_right (m_left | m_right), + .btn_down (m_down), + .btn_up (m_up), + .sw_coktail_table (1) ); mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video( @@ -196,17 +185,13 @@ user_io( .status (status ) ); -wire dac_o; -assign AUDIO_L = dac_o; -assign AUDIO_R = dac_o; - dac #( .C_bits(15)) dac( .clk_i(clk_sys), .res_n_i(1), .dac_i({audio,audio}), - .dac_o(dac_o) + .dac_o(AUDIO_L) ); wire m_up = btn_up | joystick_0[3] | joystick_1[3]; @@ -216,7 +201,6 @@ wire m_right = btn_right | joystick_0[0] | joystick_1[0]; wire m_fire1 = btn_fire1 | joystick_0[4] | joystick_1[4]; wire m_fire2 = btn_fire2 | joystick_0[5] | joystick_1[5]; wire m_fire3 = btn_fire3 | joystick_0[6] | joystick_1[6]; -wire m_fire4 = btn_fire4 | joystick_0[7] | joystick_1[7]; reg btn_one_player = 0; reg btn_two_players = 0; @@ -227,7 +211,6 @@ reg btn_up = 0; reg btn_fire1 = 0; reg btn_fire2 = 0; reg btn_fire3 = 0; -reg btn_fire4 = 0; reg btn_coin = 0; reg btn_advance = 0; reg btn_auto_up = 0; @@ -246,7 +229,6 @@ always @(posedge clk_sys) begin 'h76: btn_coin <= key_pressed; // ESC 'h05: btn_one_player <= key_pressed; // F1 'h06: btn_two_players <= key_pressed; // F2 - 'h12: btn_fire4 <= key_pressed; // l shift 'h14: btn_fire3 <= key_pressed; // ctrl 'h11: btn_fire2 <= key_pressed; // alt 'h29: btn_fire1 <= key_pressed; // Space diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Mayday/rtl/data_io.v b/Arcade_MiST/Williams 6809 rev.1 Hardware/Mayday/rtl/data_io.v deleted file mode 100644 index 4ca9518c..00000000 --- a/Arcade_MiST/Williams 6809 rev.1 Hardware/Mayday/rtl/data_io.v +++ /dev/null @@ -1,115 +0,0 @@ -// -// data_io.v -// -// data_io for the MiST board -// http://code.google.com/p/mist-board/ -// -// Copyright (c) 2014 Till Harbaum -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -/////////////////////////////////////////////////////////////////////// - -module data_io -( - input clk_sys, - input SPI_SCK, - input SPI_SS2, - input SPI_DI, - - // ARM -> FPGA download - output reg ioctl_download = 0, // signal indicating an active download - output reg [7:0] ioctl_index, // menu index used to upload the file - output ioctl_wr, - output reg [24:0] ioctl_addr, - output reg [7:0] ioctl_dout -); - -/////////////////////////////// DOWNLOADING /////////////////////////////// - -reg [7:0] data_w; -reg [24:0] addr_w; -reg rclk = 0; - -localparam UIO_FILE_TX = 8'h53; -localparam UIO_FILE_TX_DAT = 8'h54; -localparam UIO_FILE_INDEX = 8'h55; - -// data_io has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS2) begin - reg [6:0] sbuf; - reg [7:0] cmd; - reg [4:0] cnt; - reg [24:0] addr; - - if(SPI_SS2) cnt <= 0; - else begin - rclk <= 0; - - // don't shift in last bit. It is evaluated directly - // when writing to ram - if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; - - // increase target address after write - if(rclk) addr <= addr + 1'd1; - - // count 0-7 8-15 8-15 ... - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - // finished command byte - if(cnt == 7) cmd <= {sbuf, SPI_DI}; - - // prepare/end transmission - if((cmd == UIO_FILE_TX) && (cnt == 15)) begin - // prepare - if(SPI_DI) begin - addr <= 0; - ioctl_download <= 1; - end else begin - addr_w <= addr; - ioctl_download <= 0; - end - end - - // command 0x54: UIO_FILE_TX - if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin - addr_w <= addr; - data_w <= {sbuf, SPI_DI}; - rclk <= 1; - end - - // expose file (menu) index - if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; - end -end - -assign ioctl_wr = |ioctl_wrd; -reg [1:0] ioctl_wrd; - -always@(negedge clk_sys) begin - reg rclkD, rclkD2; - - rclkD <= rclk; - rclkD2 <= rclkD; - ioctl_wrd<= {ioctl_wrd[0],1'b0}; - - if(rclkD & ~rclkD2) begin - ioctl_dout <= data_w; - ioctl_addr <= addr_w; - ioctl_wrd <= 2'b11; - end -end - -endmodule diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Mayday/rtl/defender.vhd b/Arcade_MiST/Williams 6809 rev.1 Hardware/Mayday/rtl/defender.vhd index 847e141a..de4083b8 100644 --- a/Arcade_MiST/Williams 6809 rev.1 Hardware/Mayday/rtl/defender.vhd +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Mayday/rtl/defender.vhd @@ -123,50 +123,35 @@ use ieee.numeric_std.all; entity defender is port( - clk_sys : in std_logic; - clock_6 : in std_logic; - clk_1p79 : in std_logic; - clk_0p89 : in std_logic; - reset : in std_logic; - - dbg_cpu_addr : out std_logic_vector(15 downto 0); --- tv15Khz_mode : in std_logic; - video_r : out std_logic_vector(2 downto 0); - video_g : out std_logic_vector(2 downto 0); - video_b : out std_logic_vector(1 downto 0); --- video_clk : out std_logic; - video_csync : out std_logic; - video_blankn : out std_logic; - video_hs : out std_logic; - video_vs : out std_logic; - - audio_out : out std_logic_vector(7 downto 0); - - roms_addr : out std_logic_vector(14 downto 0); - roms_do : in std_logic_vector( 7 downto 0); - - - - btn_auto_up : in std_logic; - btn_advance : in std_logic; - btn_service : in std_logic; - - btn_left_coin : in std_logic; - btn_one_player : in std_logic; - btn_two_players: in std_logic; - - btn_ffire : in std_logic; - btn_bfire : in std_logic; - btn_mayday : in std_logic; - - btn_right : in std_logic; - btn_down : in std_logic; - btn_up : in std_logic; - + clk_sys : in std_logic; + clock_6 : in std_logic; + clk_0p89 : in std_logic; + reset : in std_logic; + video_r : out std_logic_vector(2 downto 0); + video_g : out std_logic_vector(2 downto 0); + video_b : out std_logic_vector(1 downto 0); + video_csync : out std_logic; + video_blankn : out std_logic; + video_hs : out std_logic; + video_vs : out std_logic; + audio_out : out std_logic_vector(7 downto 0); + roms_addr : out std_logic_vector(14 downto 0); + roms_do : in std_logic_vector( 7 downto 0); + vma : out std_logic; + btn_auto_up : in std_logic; + btn_advance : in std_logic; + btn_service : in std_logic; + btn_left_coin : in std_logic; + btn_one_player : in std_logic; + btn_two_players : in std_logic; + btn_ffire : in std_logic; + btn_bfire : in std_logic; + btn_mayday : in std_logic; + btn_right : in std_logic; + btn_down : in std_logic; + btn_up : in std_logic; sw_coktail_table : in std_logic; - cmd_select_players_btn : out std_logic - ); end defender; @@ -176,8 +161,6 @@ architecture struct of defender is signal clock_div : std_logic_vector(1 downto 0); signal clock_6n : std_logic; - - signal cpu_clock : std_logic; signal cpu_a : std_logic_vector(15 downto 0); signal cpu_addr : std_logic_vector(15 downto 0); signal cpu_di : std_logic_vector( 7 downto 0); @@ -292,16 +275,13 @@ architecture struct of defender is signal hsync0,hsync1,hsync2,csync,hblank,vblank : std_logic; signal select_sound : std_logic_vector(5 downto 0); - + signal cpu_ce : std_logic; + begin clock_6n <= not clock_6; reset_n <= not reset; --- for debug -dbg_cpu_addr <= cpu_addr; - - -- make pixels counters and cpu clock -- in original hardware cpu clock = 1us = 6pixels -- here one make 2 cpu clock within 1us @@ -309,30 +289,14 @@ process (reset, clock_6n) begin if reset='1' then pixel_cnt <= "000"; - cpu_clock <= '0'; else if rising_edge(clock_6n) then if pixel_cnt = "101" then pixel_cnt <= "000"; - cpu_clock <= '0'; else pixel_cnt <= pixel_cnt + '1'; end if; - - if pixel_cnt = "010" then - cpu_clock <= '1'; - end if; - - if pixel_cnt = "011" then -- speed up processor (two clocks / 1us) - cpu_clock <= '0'; - end if; - - if pixel_cnt = "100" then - cpu_clock <= '1'; - end if; - - end if; end if; end process; @@ -396,7 +360,7 @@ video_scan_addr <= screen_ctrl & vcnt(7 downto 0); -- mux cpu addr/scan addr to wram wram_addr <= - cpu_addr(7 downto 0) & cpu_to_video_do(5 downto 0) when cpu_clock = '1' else + cpu_addr(7 downto 0) & cpu_to_video_do(5 downto 0) when cpu_ce = '1' else video_scan_do & hcnt; -- mux cpu addr/pixels data to palette addr @@ -435,14 +399,14 @@ begin end process; -- pias cs -io_cs <= '1' when cpu_clock = '1' and cpu_addr(15 downto 12) = X"C" and rom_page ="000" else '0'; +io_cs <= '1' when cpu_ce = '1' and cpu_addr(15 downto 12) = X"C" and rom_page ="000" else '0'; pia_rom_cs <= '1' when io_cs = '1' and cpu_addr(11 downto 10) = "11" and cpu_addr(2) = '0' else '0'; -- CC00-CC03 pia_io_cs <= '1' when io_cs = '1' and cpu_addr(11 downto 10) = "11" and cpu_addr(2) = '1' else '0'; -- CC04-CC07 -- write enables -wram_we <= '1' when cpu_rw = '0' and cpu_clock = '1' and cpu_addr(15 downto 12) < X"C" else '0'; -io_we <= '1' when cpu_rw = '0' and cpu_clock = '1' and cpu_addr(15 downto 12) = X"C" and rom_page ="000" else '0'; -rom_page_we <= '1' when cpu_rw = '0' and cpu_clock = '1' and cpu_addr(15 downto 12) = X"D" else '0'; +wram_we <= '1' when cpu_rw = '0' and cpu_ce = '1' and cpu_addr(15 downto 12) < X"C" else '0'; +io_we <= '1' when cpu_rw = '0' and cpu_ce = '1' and cpu_addr(15 downto 12) = X"C" and rom_page ="000" else '0'; +rom_page_we <= '1' when cpu_rw = '0' and cpu_ce = '1' and cpu_addr(15 downto 12) = X"D" else '0'; palette_we <= '1' when io_we = '1' and cpu_addr(11 downto 10) = "00" and cpu_addr(4) = '0' else '0'; -- C000-C00F screen_ctrl_we <= '1' when io_we = '1' and cpu_addr(11 downto 10) = "00" and cpu_addr(4) = '1' else '0'; -- C010-C01F @@ -550,13 +514,14 @@ cpu_irq <= pia_rom_irqa or pia_rom_irqb; -- pia rom to sound board select_sound <= pia_rom_pb_o(5 downto 0); +cpu_ce <= '1' when pixel_cnt = "100" or pixel_cnt = "010" else '0'; -- microprocessor 6809 main_cpu : entity work.cpu09 port map( - clk => cpu_clock,-- E clock input (falling edge) + clk => clock_6,-- E clock input (falling edge) rst => reset, -- reset input (active high) - vma => open, -- valid memory address (active high) + vma => vma, -- valid memory address (active high) lic_out => open, -- last instruction cycle (active high) ifetch => open, -- instruction fetch cycle (active high) opfetch => open, -- opcode fetch (active high) @@ -570,7 +535,7 @@ port map( firq => '0', -- fast interrupt request input (active high) nmi => '0', -- non maskable interrupt request input (active high) halt => '0', -- halt input (active high) grants DMA - hold => '0' -- hold input (active high) extend bus cycle + hold => not cpu_ce-- hold input (active high) extend bus cycle ); -- Mayday protection. @@ -765,10 +730,10 @@ if rising_edge(clock_6n) then end if; if hcnt = hcnt_base-2 then hblank <= '1'; - elsif hcnt = hcnt_base+11-64 then hblank <= '0'; + elsif hcnt = hcnt_base+12-64 then hblank <= '0'; end if; - if vcnt = 492 then vblank <= '1'; -- 492 ok + if vcnt = 502 then vblank <= '1'; -- 492 ok elsif vcnt = 262 then vblank <= '0'; -- 262 ok end if; @@ -787,7 +752,6 @@ end process; -- sound board defender_sound_board : entity work.defender_sound_board port map( - clk_1p79 => clk_1p79, clk_0p89 => clk_0p89, reset => reset, select_sound => select_sound, diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Mayday/rtl/defender_sound_board.vhd b/Arcade_MiST/Williams 6809 rev.1 Hardware/Mayday/rtl/defender_sound_board.vhd index 5fdd8293..623fbece 100644 --- a/Arcade_MiST/Williams 6809 rev.1 Hardware/Mayday/rtl/defender_sound_board.vhd +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Mayday/rtl/defender_sound_board.vhd @@ -27,22 +27,16 @@ use ieee.numeric_std.all; entity defender_sound_board is port( - clk_1p79 : in std_logic; clk_0p89 : in std_logic; reset : in std_logic; - select_sound : in std_logic_vector(5 downto 0); - audio_out : out std_logic_vector( 7 downto 0); - - dbg_cpu_addr : out std_logic_vector(15 downto 0) + audio_out : out std_logic_vector( 7 downto 0) ); end defender_sound_board; architecture struct of defender_sound_board is signal reset_n : std_logic; - - signal cpu_clock : std_logic; signal cpu_addr : std_logic_vector(15 downto 0); signal cpu_di : std_logic_vector( 7 downto 0); signal cpu_do : std_logic_vector( 7 downto 0); @@ -55,22 +49,6 @@ architecture struct of defender_sound_board is signal rom_cs : std_logic; signal rom_do : std_logic_vector( 7 downto 0); - --- pia port a --- bit 0-7 audio output - --- pia port b --- bit 0-4 select sound input (sel0-4) --- bit 5-6 switch sound/notes/speech on/off --- bit 7 sel5 - --- pia io ca/cb --- ca1 vdd --- cb1 sound trigger (sel0-5 = 1) --- ca2 speech data N/C --- cb2 speech clock N/C - - signal pia_clock : std_logic; signal pia_rw_n : std_logic; signal pia_cs : std_logic; signal pia_irqa : std_logic; @@ -83,19 +61,14 @@ architecture struct of defender_sound_board is begin reset_n <= not reset; - -dbg_cpu_addr <= cpu_addr; -cpu_clock <= clk_0p89; - - -- pia cs -wram_cs <= '1' when cpu_addr(15 downto 8) = X"00" else '0'; -- 0000-007F -pia_cs <= '1' when cpu_addr(15 downto 12) = X"0" and cpu_addr(10) = '1' else '0'; -- 8400-8403 ? => 0400-0403 -rom_cs <= '1' when cpu_addr(15 downto 12) = X"F" else '0'; -- F800-FFFF +wram_cs <= '1' when cpu_addr(15 downto 8) = X"00" else '0'; +pia_cs <= '1' when cpu_addr(15 downto 12) = X"0" and cpu_addr(10) = '1' else '0'; +rom_cs <= '1' when cpu_addr(15 downto 12) = X"F" else '0'; -- write enables -wram_we <= '1' when cpu_rw = '0' and cpu_clock = '1' and wram_cs = '1' else '0'; -pia_rw_n <= '0' when cpu_rw = '0' and cpu_clock = '1' and pia_cs = '1' else '1'; +wram_we <= '1' when cpu_rw = '0' and wram_cs = '1' else '0'; +pia_rw_n <= '0' when cpu_rw = '0' and pia_cs = '1' else '1'; -- mux cpu in data between roms/io/wram cpu_di <= @@ -104,7 +77,6 @@ cpu_di <= rom_do when rom_cs = '1' else X"55"; -- pia I/O -pia_clock <= clk_1p79; -- 3p58/2 audio_out <= pia_pa_o; pia_pb_i(4 downto 0) <= select_sound(4 downto 0); @@ -120,7 +92,7 @@ cpu_irq <= pia_irqa or pia_irqb; -- microprocessor 6800 main_cpu : entity work.cpu68 port map( - clk => cpu_clock,-- E clock input (falling edge) + clk => clk_0p89, -- E clock input (falling edge) rst => reset, -- reset input (active high) rw => cpu_rw, -- read not write output vma => open, -- valid memory address (active high) @@ -138,7 +110,7 @@ port map( -- cpu program rom cpu_prog_rom : entity work.defender_sound port map( - clk => clk_1p79, + clk => clk_0p89, addr => cpu_addr(10 downto 0), data => rom_do ); @@ -147,7 +119,7 @@ port map( cpu_ram : entity work.gen_ram generic map( dWidth => 8, aWidth => 7) port map( - clk => clk_1p79, + clk => clk_0p89, we => wram_we, addr => cpu_addr(6 downto 0), d => cpu_do, @@ -158,7 +130,7 @@ port map( pia : entity work.pia6821 port map ( - clk => clk_1p79, + clk => clk_0p89, rst => reset, cs => pia_cs, rw => pia_rw_n, diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Mayday/rtl/pll_mist.ppf b/Arcade_MiST/Williams 6809 rev.1 Hardware/Mayday/rtl/pll_mist.ppf index db79bfc9..c8ed5c67 100644 --- a/Arcade_MiST/Williams 6809 rev.1 Hardware/Mayday/rtl/pll_mist.ppf +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Mayday/rtl/pll_mist.ppf @@ -7,7 +7,6 @@ - diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Mayday/rtl/pll_mist.vhd b/Arcade_MiST/Williams 6809 rev.1 Hardware/Mayday/rtl/pll_mist.vhd index b54b7a75..1bd8e50f 100644 --- a/Arcade_MiST/Williams 6809 rev.1 Hardware/Mayday/rtl/pll_mist.vhd +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Mayday/rtl/pll_mist.vhd @@ -47,7 +47,6 @@ ENTITY pll_mist IS c0 : OUT STD_LOGIC ; c1 : OUT STD_LOGIC ; c2 : OUT STD_LOGIC ; - c3 : OUT STD_LOGIC ; locked : OUT STD_LOGIC ); END pll_mist; @@ -61,10 +60,9 @@ ARCHITECTURE SYN OF pll_mist IS SIGNAL sub_wire3 : STD_LOGIC ; SIGNAL sub_wire4 : STD_LOGIC ; SIGNAL sub_wire5 : STD_LOGIC ; - SIGNAL sub_wire6 : STD_LOGIC ; - SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire8_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); @@ -83,10 +81,6 @@ ARCHITECTURE SYN OF pll_mist IS clk2_duty_cycle : NATURAL; clk2_multiply_by : NATURAL; clk2_phase_shift : STRING; - clk3_divide_by : NATURAL; - clk3_duty_cycle : NATURAL; - clk3_multiply_by : NATURAL; - clk3_phase_shift : STRING; compensate_clock : STRING; inclk0_input_frequency : NATURAL; intended_device_family : STRING; @@ -147,19 +141,17 @@ ARCHITECTURE SYN OF pll_mist IS END COMPONENT; BEGIN - sub_wire8_bv(0 DOWNTO 0) <= "0"; - sub_wire8 <= To_stdlogicvector(sub_wire8_bv); - sub_wire5 <= sub_wire0(2); - sub_wire4 <= sub_wire0(0); - sub_wire2 <= sub_wire0(3); + sub_wire7_bv(0 DOWNTO 0) <= "0"; + sub_wire7 <= To_stdlogicvector(sub_wire7_bv); + sub_wire4 <= sub_wire0(2); + sub_wire3 <= sub_wire0(0); sub_wire1 <= sub_wire0(1); c1 <= sub_wire1; - c3 <= sub_wire2; - locked <= sub_wire3; - c0 <= sub_wire4; - c2 <= sub_wire5; - sub_wire6 <= inclk0; - sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6; + locked <= sub_wire2; + c0 <= sub_wire3; + c2 <= sub_wire4; + sub_wire5 <= inclk0; + sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; altpll_component : altpll GENERIC MAP ( @@ -172,14 +164,10 @@ BEGIN clk1_duty_cycle => 50, clk1_multiply_by => 2, clk1_phase_shift => "0", - clk2_divide_by => 181, + clk2_divide_by => 91, clk2_duty_cycle => 50, - clk2_multiply_by => 12, + clk2_multiply_by => 3, clk2_phase_shift => "0", - clk3_divide_by => 91, - clk3_duty_cycle => 50, - clk3_multiply_by => 3, - clk3_phase_shift => "0", compensate_clock => "CLK0", inclk0_input_frequency => 37037, intended_device_family => "Cyclone III", @@ -215,7 +203,7 @@ BEGIN port_clk0 => "PORT_USED", port_clk1 => "PORT_USED", port_clk2 => "PORT_USED", - port_clk3 => "PORT_USED", + port_clk3 => "PORT_UNUSED", port_clk4 => "PORT_UNUSED", port_clk5 => "PORT_UNUSED", port_clkena0 => "PORT_UNUSED", @@ -233,9 +221,9 @@ BEGIN ) PORT MAP ( areset => areset, - inclk => sub_wire7, + inclk => sub_wire6, clk => sub_wire0, - locked => sub_wire3 + locked => sub_wire2 ); @@ -263,16 +251,13 @@ END SYN; -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" -- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3" -- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9" --- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "181" --- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "91" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "91" -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "36.000000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "6.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "1.790055" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "0.890110" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "0.890110" -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -295,40 +280,32 @@ END SYN; -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" -- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" -- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" -- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4" -- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2" --- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "12" --- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "3" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "3" -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" -- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "36.00000000" -- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "6.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "1.79000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "0.89000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "0.89000000" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" -- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" -- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg" -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" -- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" @@ -353,18 +330,15 @@ END SYN; -- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" -- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" -- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" -- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" -- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: USE_CLK0 STRING "1" -- Retrieval info: PRIVATE: USE_CLK1 STRING "1" -- Retrieval info: PRIVATE: USE_CLK2 STRING "1" --- Retrieval info: PRIVATE: USE_CLK3 STRING "1" -- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" -- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" -- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" -- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all @@ -377,14 +351,10 @@ END SYN; -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" -- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "181" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "91" -- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "12" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "3" -- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "91" --- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "3" --- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" @@ -419,7 +389,7 @@ END SYN; -- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" @@ -440,7 +410,6 @@ END SYN; -- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" -- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" -- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" --- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" -- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" -- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 @@ -449,7 +418,6 @@ END SYN; -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 -- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 --- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 -- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.ppf TRUE diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Colony7/rtl/data_io.v b/common/mist/data_io.v similarity index 100% rename from Arcade_MiST/Williams 6809 rev.1 Hardware/Colony7/rtl/data_io.v rename to common/mist/data_io.v diff --git a/common/mist/mist.qip b/common/mist/mist.qip index fd63ad20..d908a3bc 100644 --- a/common/mist/mist.qip +++ b/common/mist/mist.qip @@ -1,5 +1,6 @@ set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) mist.vhd] set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) user_io.v] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) data_io.v] set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) mist_video.v] set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scandoubler.v] set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) osd.v]