diff --git a/Arcade_MiST/Pacman Hardware/Alibaba_MiST/Alibaba.qpf b/Arcade_MiST/Namco Pacman Hardware/Alibaba_MiST/Alibaba.qpf
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Alibaba_MiST/Alibaba.qpf
rename to Arcade_MiST/Namco Pacman Hardware/Alibaba_MiST/Alibaba.qpf
diff --git a/Arcade_MiST/Pacman Hardware/Alibaba_MiST/Alibaba.qsf b/Arcade_MiST/Namco Pacman Hardware/Alibaba_MiST/Alibaba.qsf
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Alibaba_MiST/Alibaba.qsf
rename to Arcade_MiST/Namco Pacman Hardware/Alibaba_MiST/Alibaba.qsf
diff --git a/Arcade_MiST/Pacman Hardware/Alibaba_MiST/Alibaba.sdc b/Arcade_MiST/Namco Pacman Hardware/Alibaba_MiST/Alibaba.sdc
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Alibaba_MiST/Alibaba.sdc
rename to Arcade_MiST/Namco Pacman Hardware/Alibaba_MiST/Alibaba.sdc
diff --git a/Arcade_MiST/Pacman Hardware/Alibaba_MiST/README.txt b/Arcade_MiST/Namco Pacman Hardware/Alibaba_MiST/README.txt
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Alibaba_MiST/README.txt
rename to Arcade_MiST/Namco Pacman Hardware/Alibaba_MiST/README.txt
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/clean.bat b/Arcade_MiST/Namco Pacman Hardware/Alibaba_MiST/clean.bat
similarity index 100%
rename from Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/clean.bat
rename to Arcade_MiST/Namco Pacman Hardware/Alibaba_MiST/clean.bat
diff --git a/Arcade_MiST/Pacman Hardware/Alibaba_MiST/rtl/Alibaba.sv b/Arcade_MiST/Namco Pacman Hardware/Alibaba_MiST/rtl/Alibaba.sv
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Alibaba_MiST/rtl/Alibaba.sv
rename to Arcade_MiST/Namco Pacman Hardware/Alibaba_MiST/rtl/Alibaba.sv
diff --git a/Arcade_MiST/Pacman Hardware/Alibaba_MiST/rtl/ROM/GFX1.vhd b/Arcade_MiST/Namco Pacman Hardware/Alibaba_MiST/rtl/ROM/GFX1.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Alibaba_MiST/rtl/ROM/GFX1.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Alibaba_MiST/rtl/ROM/GFX1.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Alibaba_MiST/rtl/ROM/PROM1_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Alibaba_MiST/rtl/ROM/PROM1_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Alibaba_MiST/rtl/ROM/PROM1_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Alibaba_MiST/rtl/ROM/PROM1_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Alibaba_MiST/rtl/ROM/PROM3_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Alibaba_MiST/rtl/ROM/PROM3_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Alibaba_MiST/rtl/ROM/PROM3_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Alibaba_MiST/rtl/ROM/PROM3_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Alibaba_MiST/rtl/ROM/PROM4_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Alibaba_MiST/rtl/ROM/PROM4_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Alibaba_MiST/rtl/ROM/PROM4_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Alibaba_MiST/rtl/ROM/PROM4_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Alibaba_MiST/rtl/ROM/PROM7_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Alibaba_MiST/rtl/ROM/PROM7_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Alibaba_MiST/rtl/ROM/PROM7_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Alibaba_MiST/rtl/ROM/PROM7_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Alibaba_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Namco Pacman Hardware/Alibaba_MiST/rtl/ROM/ROM_PGM_0.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Alibaba_MiST/rtl/ROM/ROM_PGM_0.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Alibaba_MiST/rtl/ROM/ROM_PGM_0.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Alibaba_MiST/rtl/ROM/ROM_PGM_1.vhd b/Arcade_MiST/Namco Pacman Hardware/Alibaba_MiST/rtl/ROM/ROM_PGM_1.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Alibaba_MiST/rtl/ROM/ROM_PGM_1.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Alibaba_MiST/rtl/ROM/ROM_PGM_1.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Alibaba_MiST/rtl/alibaba.vhd b/Arcade_MiST/Namco Pacman Hardware/Alibaba_MiST/rtl/alibaba.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Alibaba_MiST/rtl/alibaba.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Alibaba_MiST/rtl/alibaba.vhd
diff --git a/Arcade_MiST/Namco Mappy Hardware/rtl/build_id.tcl b/Arcade_MiST/Namco Pacman Hardware/Alibaba_MiST/rtl/build_id.tcl
similarity index 100%
rename from Arcade_MiST/Namco Mappy Hardware/rtl/build_id.tcl
rename to Arcade_MiST/Namco Pacman Hardware/Alibaba_MiST/rtl/build_id.tcl
diff --git a/Arcade_MiST/Pacman Hardware/Alibaba_MiST/rtl/dpram.vhd b/Arcade_MiST/Namco Pacman Hardware/Alibaba_MiST/rtl/dpram.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Alibaba_MiST/rtl/dpram.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Alibaba_MiST/rtl/dpram.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Alibaba_MiST/rtl/pacman_audio.vhd b/Arcade_MiST/Namco Pacman Hardware/Alibaba_MiST/rtl/pacman_audio.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Alibaba_MiST/rtl/pacman_audio.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Alibaba_MiST/rtl/pacman_audio.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Alibaba_MiST/rtl/pacman_video.vhd b/Arcade_MiST/Namco Pacman Hardware/Alibaba_MiST/rtl/pacman_video.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Alibaba_MiST/rtl/pacman_video.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Alibaba_MiST/rtl/pacman_video.vhd
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/pll.qip b/Arcade_MiST/Namco Pacman Hardware/Alibaba_MiST/rtl/pll.qip
similarity index 100%
rename from Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/pll.qip
rename to Arcade_MiST/Namco Pacman Hardware/Alibaba_MiST/rtl/pll.qip
diff --git a/Arcade_MiST/Pacman Hardware/Alibaba_MiST/rtl/pll.v b/Arcade_MiST/Namco Pacman Hardware/Alibaba_MiST/rtl/pll.v
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Alibaba_MiST/rtl/pll.v
rename to Arcade_MiST/Namco Pacman Hardware/Alibaba_MiST/rtl/pll.v
diff --git a/Arcade_MiST/Pacman Hardware/Birdiy_MiST/Birdiy.qpf b/Arcade_MiST/Namco Pacman Hardware/Birdiy_MiST/Birdiy.qpf
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Birdiy_MiST/Birdiy.qpf
rename to Arcade_MiST/Namco Pacman Hardware/Birdiy_MiST/Birdiy.qpf
diff --git a/Arcade_MiST/Pacman Hardware/Birdiy_MiST/Birdiy.qsf b/Arcade_MiST/Namco Pacman Hardware/Birdiy_MiST/Birdiy.qsf
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Birdiy_MiST/Birdiy.qsf
rename to Arcade_MiST/Namco Pacman Hardware/Birdiy_MiST/Birdiy.qsf
diff --git a/Arcade_MiST/Pacman Hardware/Birdiy_MiST/Birdiy.sdc b/Arcade_MiST/Namco Pacman Hardware/Birdiy_MiST/Birdiy.sdc
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Birdiy_MiST/Birdiy.sdc
rename to Arcade_MiST/Namco Pacman Hardware/Birdiy_MiST/Birdiy.sdc
diff --git a/Arcade_MiST/Pacman Hardware/Birdiy_MiST/README.txt b/Arcade_MiST/Namco Pacman Hardware/Birdiy_MiST/README.txt
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Birdiy_MiST/README.txt
rename to Arcade_MiST/Namco Pacman Hardware/Birdiy_MiST/README.txt
diff --git a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/clean.bat b/Arcade_MiST/Namco Pacman Hardware/Birdiy_MiST/clean.bat
similarity index 100%
rename from Arcade_MiST/Namco Rally X Hardware/Test_MiST/clean.bat
rename to Arcade_MiST/Namco Pacman Hardware/Birdiy_MiST/clean.bat
diff --git a/Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/Birdiy.sv b/Arcade_MiST/Namco Pacman Hardware/Birdiy_MiST/rtl/Birdiy.sv
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/Birdiy.sv
rename to Arcade_MiST/Namco Pacman Hardware/Birdiy_MiST/rtl/Birdiy.sv
diff --git a/Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/ROM/GFX1.vhd b/Arcade_MiST/Namco Pacman Hardware/Birdiy_MiST/rtl/ROM/GFX1.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/ROM/GFX1.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Birdiy_MiST/rtl/ROM/GFX1.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/ROM/PROM1_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Birdiy_MiST/rtl/ROM/PROM1_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/ROM/PROM1_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Birdiy_MiST/rtl/ROM/PROM1_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/ROM/PROM3_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Birdiy_MiST/rtl/ROM/PROM3_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/ROM/PROM3_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Birdiy_MiST/rtl/ROM/PROM3_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/ROM/PROM4_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Birdiy_MiST/rtl/ROM/PROM4_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/ROM/PROM4_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Birdiy_MiST/rtl/ROM/PROM4_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/ROM/PROM7_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Birdiy_MiST/rtl/ROM/PROM7_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/ROM/PROM7_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Birdiy_MiST/rtl/ROM/PROM7_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Namco Pacman Hardware/Birdiy_MiST/rtl/ROM/ROM_PGM_0.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/ROM/ROM_PGM_0.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Birdiy_MiST/rtl/ROM/ROM_PGM_0.vhd
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/build_id.tcl b/Arcade_MiST/Namco Pacman Hardware/Birdiy_MiST/rtl/build_id.tcl
similarity index 100%
rename from Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/build_id.tcl
rename to Arcade_MiST/Namco Pacman Hardware/Birdiy_MiST/rtl/build_id.tcl
diff --git a/Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/dpram.vhd b/Arcade_MiST/Namco Pacman Hardware/Birdiy_MiST/rtl/dpram.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/dpram.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Birdiy_MiST/rtl/dpram.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/pacman.vhd b/Arcade_MiST/Namco Pacman Hardware/Birdiy_MiST/rtl/pacman.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/pacman.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Birdiy_MiST/rtl/pacman.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/pacman_audio.vhd b/Arcade_MiST/Namco Pacman Hardware/Birdiy_MiST/rtl/pacman_audio.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/pacman_audio.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Birdiy_MiST/rtl/pacman_audio.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/pacman_video.vhd b/Arcade_MiST/Namco Pacman Hardware/Birdiy_MiST/rtl/pacman_video.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/pacman_video.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Birdiy_MiST/rtl/pacman_video.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/pacman_vram_addr.vhd b/Arcade_MiST/Namco Pacman Hardware/Birdiy_MiST/rtl/pacman_vram_addr.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/pacman_vram_addr.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Birdiy_MiST/rtl/pacman_vram_addr.vhd
diff --git a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/pll.qip b/Arcade_MiST/Namco Pacman Hardware/Birdiy_MiST/rtl/pll.qip
similarity index 100%
rename from Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/pll.qip
rename to Arcade_MiST/Namco Pacman Hardware/Birdiy_MiST/rtl/pll.qip
diff --git a/Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/pll.v b/Arcade_MiST/Namco Pacman Hardware/Birdiy_MiST/rtl/pll.v
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/pll.v
rename to Arcade_MiST/Namco Pacman Hardware/Birdiy_MiST/rtl/pll.v
diff --git a/Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/CrushRoller.qpf b/Arcade_MiST/Namco Pacman Hardware/Crush_Roller_MiST/CrushRoller.qpf
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/CrushRoller.qpf
rename to Arcade_MiST/Namco Pacman Hardware/Crush_Roller_MiST/CrushRoller.qpf
diff --git a/Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/CrushRoller.qsf b/Arcade_MiST/Namco Pacman Hardware/Crush_Roller_MiST/CrushRoller.qsf
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/CrushRoller.qsf
rename to Arcade_MiST/Namco Pacman Hardware/Crush_Roller_MiST/CrushRoller.qsf
diff --git a/Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/CrushRoller.sdc b/Arcade_MiST/Namco Pacman Hardware/Crush_Roller_MiST/CrushRoller.sdc
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/CrushRoller.sdc
rename to Arcade_MiST/Namco Pacman Hardware/Crush_Roller_MiST/CrushRoller.sdc
diff --git a/Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/README.txt b/Arcade_MiST/Namco Pacman Hardware/Crush_Roller_MiST/README.txt
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/README.txt
rename to Arcade_MiST/Namco Pacman Hardware/Crush_Roller_MiST/README.txt
diff --git a/Arcade_MiST/Pacman Hardware/Alibaba_MiST/clean.bat b/Arcade_MiST/Namco Pacman Hardware/Crush_Roller_MiST/clean.bat
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Alibaba_MiST/clean.bat
rename to Arcade_MiST/Namco Pacman Hardware/Crush_Roller_MiST/clean.bat
diff --git a/Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/rtl/CrushRoller.sv b/Arcade_MiST/Namco Pacman Hardware/Crush_Roller_MiST/rtl/CrushRoller.sv
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/rtl/CrushRoller.sv
rename to Arcade_MiST/Namco Pacman Hardware/Crush_Roller_MiST/rtl/CrushRoller.sv
diff --git a/Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/rtl/ROM/GFX1.vhd b/Arcade_MiST/Namco Pacman Hardware/Crush_Roller_MiST/rtl/ROM/GFX1.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/rtl/ROM/GFX1.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Crush_Roller_MiST/rtl/ROM/GFX1.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/rtl/ROM/PROM1_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Crush_Roller_MiST/rtl/ROM/PROM1_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/rtl/ROM/PROM1_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Crush_Roller_MiST/rtl/ROM/PROM1_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/rtl/ROM/PROM3_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Crush_Roller_MiST/rtl/ROM/PROM3_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/rtl/ROM/PROM3_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Crush_Roller_MiST/rtl/ROM/PROM3_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/rtl/ROM/PROM4_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Crush_Roller_MiST/rtl/ROM/PROM4_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/rtl/ROM/PROM4_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Crush_Roller_MiST/rtl/ROM/PROM4_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/rtl/ROM/PROM7_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Crush_Roller_MiST/rtl/ROM/PROM7_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/rtl/ROM/PROM7_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Crush_Roller_MiST/rtl/ROM/PROM7_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Namco Pacman Hardware/Crush_Roller_MiST/rtl/ROM/ROM_PGM_0.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/rtl/ROM/ROM_PGM_0.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Crush_Roller_MiST/rtl/ROM/ROM_PGM_0.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/rtl/ROM/ROM_PGM_1.vhd b/Arcade_MiST/Namco Pacman Hardware/Crush_Roller_MiST/rtl/ROM/ROM_PGM_1.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/rtl/ROM/ROM_PGM_1.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Crush_Roller_MiST/rtl/ROM/ROM_PGM_1.vhd
diff --git a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/build_id.tcl b/Arcade_MiST/Namco Pacman Hardware/Crush_Roller_MiST/rtl/build_id.tcl
similarity index 100%
rename from Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/build_id.tcl
rename to Arcade_MiST/Namco Pacman Hardware/Crush_Roller_MiST/rtl/build_id.tcl
diff --git a/Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/rtl/dpram.vhd b/Arcade_MiST/Namco Pacman Hardware/Crush_Roller_MiST/rtl/dpram.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/rtl/dpram.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Crush_Roller_MiST/rtl/dpram.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/rtl/pacman.vhd b/Arcade_MiST/Namco Pacman Hardware/Crush_Roller_MiST/rtl/pacman.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/rtl/pacman.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Crush_Roller_MiST/rtl/pacman.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/rtl/pacman_audio.vhd b/Arcade_MiST/Namco Pacman Hardware/Crush_Roller_MiST/rtl/pacman_audio.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/rtl/pacman_audio.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Crush_Roller_MiST/rtl/pacman_audio.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/rtl/pacman_video.vhd b/Arcade_MiST/Namco Pacman Hardware/Crush_Roller_MiST/rtl/pacman_video.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/rtl/pacman_video.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Crush_Roller_MiST/rtl/pacman_video.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/rtl/pacman_vram_addr.vhd b/Arcade_MiST/Namco Pacman Hardware/Crush_Roller_MiST/rtl/pacman_vram_addr.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/rtl/pacman_vram_addr.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Crush_Roller_MiST/rtl/pacman_vram_addr.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/rtl/pll.qip b/Arcade_MiST/Namco Pacman Hardware/Crush_Roller_MiST/rtl/pll.qip
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/rtl/pll.qip
rename to Arcade_MiST/Namco Pacman Hardware/Crush_Roller_MiST/rtl/pll.qip
diff --git a/Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/rtl/pll.vhd b/Arcade_MiST/Namco Pacman Hardware/Crush_Roller_MiST/rtl/pll.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/rtl/pll.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Crush_Roller_MiST/rtl/pll.vhd
diff --git a/Arcade_MiST/Pacman Hardware/DreamShopper_MiST/DreamShopper.qpf b/Arcade_MiST/Namco Pacman Hardware/DreamShopper_MiST/DreamShopper.qpf
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/DreamShopper_MiST/DreamShopper.qpf
rename to Arcade_MiST/Namco Pacman Hardware/DreamShopper_MiST/DreamShopper.qpf
diff --git a/Arcade_MiST/Pacman Hardware/DreamShopper_MiST/DreamShopper.qsf b/Arcade_MiST/Namco Pacman Hardware/DreamShopper_MiST/DreamShopper.qsf
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/DreamShopper_MiST/DreamShopper.qsf
rename to Arcade_MiST/Namco Pacman Hardware/DreamShopper_MiST/DreamShopper.qsf
diff --git a/Arcade_MiST/Pacman Hardware/DreamShopper_MiST/DreamShopper.sdc b/Arcade_MiST/Namco Pacman Hardware/DreamShopper_MiST/DreamShopper.sdc
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/DreamShopper_MiST/DreamShopper.sdc
rename to Arcade_MiST/Namco Pacman Hardware/DreamShopper_MiST/DreamShopper.sdc
diff --git a/Arcade_MiST/Pacman Hardware/DreamShopper_MiST/README.txt b/Arcade_MiST/Namco Pacman Hardware/DreamShopper_MiST/README.txt
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/DreamShopper_MiST/README.txt
rename to Arcade_MiST/Namco Pacman Hardware/DreamShopper_MiST/README.txt
diff --git a/Arcade_MiST/Pacman Hardware/Birdiy_MiST/clean.bat b/Arcade_MiST/Namco Pacman Hardware/DreamShopper_MiST/clean.bat
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Birdiy_MiST/clean.bat
rename to Arcade_MiST/Namco Pacman Hardware/DreamShopper_MiST/clean.bat
diff --git a/Arcade_MiST/Pacman Hardware/DreamShopper_MiST/rtl/DreamShopper.sv b/Arcade_MiST/Namco Pacman Hardware/DreamShopper_MiST/rtl/DreamShopper.sv
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/DreamShopper_MiST/rtl/DreamShopper.sv
rename to Arcade_MiST/Namco Pacman Hardware/DreamShopper_MiST/rtl/DreamShopper.sv
diff --git a/Arcade_MiST/Pacman Hardware/DreamShopper_MiST/rtl/ROM/GFX1.vhd b/Arcade_MiST/Namco Pacman Hardware/DreamShopper_MiST/rtl/ROM/GFX1.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/DreamShopper_MiST/rtl/ROM/GFX1.vhd
rename to Arcade_MiST/Namco Pacman Hardware/DreamShopper_MiST/rtl/ROM/GFX1.vhd
diff --git a/Arcade_MiST/Pacman Hardware/DreamShopper_MiST/rtl/ROM/PROM4_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/DreamShopper_MiST/rtl/ROM/PROM4_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/DreamShopper_MiST/rtl/ROM/PROM4_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/DreamShopper_MiST/rtl/ROM/PROM4_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/DreamShopper_MiST/rtl/ROM/PROM7_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/DreamShopper_MiST/rtl/ROM/PROM7_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/DreamShopper_MiST/rtl/ROM/PROM7_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/DreamShopper_MiST/rtl/ROM/PROM7_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/DreamShopper_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Namco Pacman Hardware/DreamShopper_MiST/rtl/ROM/ROM_PGM_0.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/DreamShopper_MiST/rtl/ROM/ROM_PGM_0.vhd
rename to Arcade_MiST/Namco Pacman Hardware/DreamShopper_MiST/rtl/ROM/ROM_PGM_0.vhd
diff --git a/Arcade_MiST/Pacman Hardware/DreamShopper_MiST/rtl/ROM/ROM_PGM_1.vhd b/Arcade_MiST/Namco Pacman Hardware/DreamShopper_MiST/rtl/ROM/ROM_PGM_1.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/DreamShopper_MiST/rtl/ROM/ROM_PGM_1.vhd
rename to Arcade_MiST/Namco Pacman Hardware/DreamShopper_MiST/rtl/ROM/ROM_PGM_1.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Alibaba_MiST/rtl/build_id.tcl b/Arcade_MiST/Namco Pacman Hardware/DreamShopper_MiST/rtl/build_id.tcl
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Alibaba_MiST/rtl/build_id.tcl
rename to Arcade_MiST/Namco Pacman Hardware/DreamShopper_MiST/rtl/build_id.tcl
diff --git a/Arcade_MiST/Pacman Hardware/DreamShopper_MiST/rtl/dpram.vhd b/Arcade_MiST/Namco Pacman Hardware/DreamShopper_MiST/rtl/dpram.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/DreamShopper_MiST/rtl/dpram.vhd
rename to Arcade_MiST/Namco Pacman Hardware/DreamShopper_MiST/rtl/dpram.vhd
diff --git a/Arcade_MiST/Pacman Hardware/DreamShopper_MiST/rtl/dreamshp.vhd b/Arcade_MiST/Namco Pacman Hardware/DreamShopper_MiST/rtl/dreamshp.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/DreamShopper_MiST/rtl/dreamshp.vhd
rename to Arcade_MiST/Namco Pacman Hardware/DreamShopper_MiST/rtl/dreamshp.vhd
diff --git a/Arcade_MiST/Pacman Hardware/DreamShopper_MiST/rtl/dreamshp_video.vhd b/Arcade_MiST/Namco Pacman Hardware/DreamShopper_MiST/rtl/dreamshp_video.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/DreamShopper_MiST/rtl/dreamshp_video.vhd
rename to Arcade_MiST/Namco Pacman Hardware/DreamShopper_MiST/rtl/dreamshp_video.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Alibaba_MiST/rtl/pll.qip b/Arcade_MiST/Namco Pacman Hardware/DreamShopper_MiST/rtl/pll.qip
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Alibaba_MiST/rtl/pll.qip
rename to Arcade_MiST/Namco Pacman Hardware/DreamShopper_MiST/rtl/pll.qip
diff --git a/Arcade_MiST/Pacman Hardware/DreamShopper_MiST/rtl/pll.v b/Arcade_MiST/Namco Pacman Hardware/DreamShopper_MiST/rtl/pll.v
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/DreamShopper_MiST/rtl/pll.v
rename to Arcade_MiST/Namco Pacman Hardware/DreamShopper_MiST/rtl/pll.v
diff --git a/Arcade_MiST/Pacman Hardware/DreamShopper_MiST/rtl/ym2149.sv b/Arcade_MiST/Namco Pacman Hardware/DreamShopper_MiST/rtl/ym2149.sv
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/DreamShopper_MiST/rtl/ym2149.sv
rename to Arcade_MiST/Namco Pacman Hardware/DreamShopper_MiST/rtl/ym2149.sv
diff --git a/Arcade_MiST/Pacman Hardware/Eeekk_MiST/Eeekk.qpf b/Arcade_MiST/Namco Pacman Hardware/Eeekk_MiST/Eeekk.qpf
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eeekk_MiST/Eeekk.qpf
rename to Arcade_MiST/Namco Pacman Hardware/Eeekk_MiST/Eeekk.qpf
diff --git a/Arcade_MiST/Pacman Hardware/Eeekk_MiST/Eeekk.qsf b/Arcade_MiST/Namco Pacman Hardware/Eeekk_MiST/Eeekk.qsf
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eeekk_MiST/Eeekk.qsf
rename to Arcade_MiST/Namco Pacman Hardware/Eeekk_MiST/Eeekk.qsf
diff --git a/Arcade_MiST/Pacman Hardware/Eeekk_MiST/Eeekk.sdc b/Arcade_MiST/Namco Pacman Hardware/Eeekk_MiST/Eeekk.sdc
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eeekk_MiST/Eeekk.sdc
rename to Arcade_MiST/Namco Pacman Hardware/Eeekk_MiST/Eeekk.sdc
diff --git a/Arcade_MiST/Pacman Hardware/Eeekk_MiST/README.txt b/Arcade_MiST/Namco Pacman Hardware/Eeekk_MiST/README.txt
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eeekk_MiST/README.txt
rename to Arcade_MiST/Namco Pacman Hardware/Eeekk_MiST/README.txt
diff --git a/Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/clean.bat b/Arcade_MiST/Namco Pacman Hardware/Eeekk_MiST/clean.bat
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/clean.bat
rename to Arcade_MiST/Namco Pacman Hardware/Eeekk_MiST/clean.bat
diff --git a/Arcade_MiST/Pacman Hardware/Eeekk_MiST/rtl/Eeekk.sv b/Arcade_MiST/Namco Pacman Hardware/Eeekk_MiST/rtl/Eeekk.sv
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eeekk_MiST/rtl/Eeekk.sv
rename to Arcade_MiST/Namco Pacman Hardware/Eeekk_MiST/rtl/Eeekk.sv
diff --git a/Arcade_MiST/Pacman Hardware/Eeekk_MiST/rtl/ROM/GFX1.vhd b/Arcade_MiST/Namco Pacman Hardware/Eeekk_MiST/rtl/ROM/GFX1.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eeekk_MiST/rtl/ROM/GFX1.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Eeekk_MiST/rtl/ROM/GFX1.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Eeekk_MiST/rtl/ROM/PROM1_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Eeekk_MiST/rtl/ROM/PROM1_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eeekk_MiST/rtl/ROM/PROM1_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Eeekk_MiST/rtl/ROM/PROM1_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Eeekk_MiST/rtl/ROM/PROM3_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Eeekk_MiST/rtl/ROM/PROM3_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eeekk_MiST/rtl/ROM/PROM3_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Eeekk_MiST/rtl/ROM/PROM3_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Eeekk_MiST/rtl/ROM/PROM4_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Eeekk_MiST/rtl/ROM/PROM4_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eeekk_MiST/rtl/ROM/PROM4_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Eeekk_MiST/rtl/ROM/PROM4_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Eeekk_MiST/rtl/ROM/PROM7_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Eeekk_MiST/rtl/ROM/PROM7_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eeekk_MiST/rtl/ROM/PROM7_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Eeekk_MiST/rtl/ROM/PROM7_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Eeekk_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Namco Pacman Hardware/Eeekk_MiST/rtl/ROM/ROM_PGM_0.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eeekk_MiST/rtl/ROM/ROM_PGM_0.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Eeekk_MiST/rtl/ROM/ROM_PGM_0.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Eeekk_MiST/rtl/ROM/ROM_PGM_1.vhd b/Arcade_MiST/Namco Pacman Hardware/Eeekk_MiST/rtl/ROM/ROM_PGM_1.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eeekk_MiST/rtl/ROM/ROM_PGM_1.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Eeekk_MiST/rtl/ROM/ROM_PGM_1.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/build_id.tcl b/Arcade_MiST/Namco Pacman Hardware/Eeekk_MiST/rtl/build_id.tcl
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/build_id.tcl
rename to Arcade_MiST/Namco Pacman Hardware/Eeekk_MiST/rtl/build_id.tcl
diff --git a/Arcade_MiST/Pacman Hardware/Eeekk_MiST/rtl/dpram.vhd b/Arcade_MiST/Namco Pacman Hardware/Eeekk_MiST/rtl/dpram.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eeekk_MiST/rtl/dpram.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Eeekk_MiST/rtl/dpram.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Eeekk_MiST/rtl/eeekk.vhd b/Arcade_MiST/Namco Pacman Hardware/Eeekk_MiST/rtl/eeekk.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eeekk_MiST/rtl/eeekk.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Eeekk_MiST/rtl/eeekk.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Eeekk_MiST/rtl/pacman_audio.vhd b/Arcade_MiST/Namco Pacman Hardware/Eeekk_MiST/rtl/pacman_audio.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eeekk_MiST/rtl/pacman_audio.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Eeekk_MiST/rtl/pacman_audio.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Eeekk_MiST/rtl/pacman_video.vhd b/Arcade_MiST/Namco Pacman Hardware/Eeekk_MiST/rtl/pacman_video.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eeekk_MiST/rtl/pacman_video.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Eeekk_MiST/rtl/pacman_video.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/pll.qip b/Arcade_MiST/Namco Pacman Hardware/Eeekk_MiST/rtl/pll.qip
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Birdiy_MiST/rtl/pll.qip
rename to Arcade_MiST/Namco Pacman Hardware/Eeekk_MiST/rtl/pll.qip
diff --git a/Arcade_MiST/Pacman Hardware/Eeekk_MiST/rtl/pll.v b/Arcade_MiST/Namco Pacman Hardware/Eeekk_MiST/rtl/pll.v
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eeekk_MiST/rtl/pll.v
rename to Arcade_MiST/Namco Pacman Hardware/Eeekk_MiST/rtl/pll.v
diff --git a/Arcade_MiST/Pacman Hardware/Eggor_MiST/Eggor.qpf b/Arcade_MiST/Namco Pacman Hardware/Eggor_MiST/Eggor.qpf
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eggor_MiST/Eggor.qpf
rename to Arcade_MiST/Namco Pacman Hardware/Eggor_MiST/Eggor.qpf
diff --git a/Arcade_MiST/Pacman Hardware/Eggor_MiST/Eggor.qsf b/Arcade_MiST/Namco Pacman Hardware/Eggor_MiST/Eggor.qsf
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eggor_MiST/Eggor.qsf
rename to Arcade_MiST/Namco Pacman Hardware/Eggor_MiST/Eggor.qsf
diff --git a/Arcade_MiST/Pacman Hardware/Eggor_MiST/Eggor.sdc b/Arcade_MiST/Namco Pacman Hardware/Eggor_MiST/Eggor.sdc
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eggor_MiST/Eggor.sdc
rename to Arcade_MiST/Namco Pacman Hardware/Eggor_MiST/Eggor.sdc
diff --git a/Arcade_MiST/Pacman Hardware/Eggor_MiST/README.txt b/Arcade_MiST/Namco Pacman Hardware/Eggor_MiST/README.txt
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eggor_MiST/README.txt
rename to Arcade_MiST/Namco Pacman Hardware/Eggor_MiST/README.txt
diff --git a/Arcade_MiST/Pacman Hardware/DreamShopper_MiST/clean.bat b/Arcade_MiST/Namco Pacman Hardware/Eggor_MiST/clean.bat
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/DreamShopper_MiST/clean.bat
rename to Arcade_MiST/Namco Pacman Hardware/Eggor_MiST/clean.bat
diff --git a/Arcade_MiST/Pacman Hardware/Eggor_MiST/rtl/Eggor.sv b/Arcade_MiST/Namco Pacman Hardware/Eggor_MiST/rtl/Eggor.sv
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eggor_MiST/rtl/Eggor.sv
rename to Arcade_MiST/Namco Pacman Hardware/Eggor_MiST/rtl/Eggor.sv
diff --git a/Arcade_MiST/Pacman Hardware/Eggor_MiST/rtl/ROM/GFX1.vhd b/Arcade_MiST/Namco Pacman Hardware/Eggor_MiST/rtl/ROM/GFX1.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eggor_MiST/rtl/ROM/GFX1.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Eggor_MiST/rtl/ROM/GFX1.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Eggor_MiST/rtl/ROM/PROM1_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Eggor_MiST/rtl/ROM/PROM1_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eggor_MiST/rtl/ROM/PROM1_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Eggor_MiST/rtl/ROM/PROM1_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Eggor_MiST/rtl/ROM/PROM3_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Eggor_MiST/rtl/ROM/PROM3_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eggor_MiST/rtl/ROM/PROM3_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Eggor_MiST/rtl/ROM/PROM3_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Eggor_MiST/rtl/ROM/PROM4_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Eggor_MiST/rtl/ROM/PROM4_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eggor_MiST/rtl/ROM/PROM4_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Eggor_MiST/rtl/ROM/PROM4_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Eggor_MiST/rtl/ROM/PROM7_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Eggor_MiST/rtl/ROM/PROM7_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eggor_MiST/rtl/ROM/PROM7_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Eggor_MiST/rtl/ROM/PROM7_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Eggor_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Namco Pacman Hardware/Eggor_MiST/rtl/ROM/ROM_PGM_0.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eggor_MiST/rtl/ROM/ROM_PGM_0.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Eggor_MiST/rtl/ROM/ROM_PGM_0.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/rtl/build_id.tcl b/Arcade_MiST/Namco Pacman Hardware/Eggor_MiST/rtl/build_id.tcl
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Crush_Roller_MiST/rtl/build_id.tcl
rename to Arcade_MiST/Namco Pacman Hardware/Eggor_MiST/rtl/build_id.tcl
diff --git a/Arcade_MiST/Pacman Hardware/Eggor_MiST/rtl/dpram.vhd b/Arcade_MiST/Namco Pacman Hardware/Eggor_MiST/rtl/dpram.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eggor_MiST/rtl/dpram.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Eggor_MiST/rtl/dpram.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Eggor_MiST/rtl/pacman.vhd b/Arcade_MiST/Namco Pacman Hardware/Eggor_MiST/rtl/pacman.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eggor_MiST/rtl/pacman.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Eggor_MiST/rtl/pacman.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Eggor_MiST/rtl/pacman_audio.vhd b/Arcade_MiST/Namco Pacman Hardware/Eggor_MiST/rtl/pacman_audio.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eggor_MiST/rtl/pacman_audio.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Eggor_MiST/rtl/pacman_audio.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Eggor_MiST/rtl/pacman_video.vhd b/Arcade_MiST/Namco Pacman Hardware/Eggor_MiST/rtl/pacman_video.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eggor_MiST/rtl/pacman_video.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Eggor_MiST/rtl/pacman_video.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Eggor_MiST/rtl/pacman_vram_addr.vhd b/Arcade_MiST/Namco Pacman Hardware/Eggor_MiST/rtl/pacman_vram_addr.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eggor_MiST/rtl/pacman_vram_addr.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Eggor_MiST/rtl/pacman_vram_addr.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Eggor_MiST/rtl/pll.qip b/Arcade_MiST/Namco Pacman Hardware/Eggor_MiST/rtl/pll.qip
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eggor_MiST/rtl/pll.qip
rename to Arcade_MiST/Namco Pacman Hardware/Eggor_MiST/rtl/pll.qip
diff --git a/Arcade_MiST/Pacman Hardware/Eggor_MiST/rtl/pll.vhd b/Arcade_MiST/Namco Pacman Hardware/Eggor_MiST/rtl/pll.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eggor_MiST/rtl/pll.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Eggor_MiST/rtl/pll.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Eyes_MiST/Eyes.qpf b/Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/Eyes.qpf
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eyes_MiST/Eyes.qpf
rename to Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/Eyes.qpf
diff --git a/Arcade_MiST/Pacman Hardware/Eyes_MiST/Eyes.qsf b/Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/Eyes.qsf
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eyes_MiST/Eyes.qsf
rename to Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/Eyes.qsf
diff --git a/Arcade_MiST/Pacman Hardware/Eyes_MiST/Eyes.sdc b/Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/Eyes.sdc
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eyes_MiST/Eyes.sdc
rename to Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/Eyes.sdc
diff --git a/Arcade_MiST/Pacman Hardware/Eyes_MiST/README.txt b/Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/README.txt
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eyes_MiST/README.txt
rename to Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/README.txt
diff --git a/Arcade_MiST/Pacman Hardware/Eeekk_MiST/clean.bat b/Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/clean.bat
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eeekk_MiST/clean.bat
rename to Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/clean.bat
diff --git a/Arcade_MiST/Pacman Hardware/Eyes_MiST/rtl/Eyes.sv b/Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/rtl/Eyes.sv
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eyes_MiST/rtl/Eyes.sv
rename to Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/rtl/Eyes.sv
diff --git a/Arcade_MiST/Pacman Hardware/Eyes_MiST/rtl/ROM/GFX1.vhd b/Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/rtl/ROM/GFX1.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eyes_MiST/rtl/ROM/GFX1.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/rtl/ROM/GFX1.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Eyes_MiST/rtl/ROM/PROM1_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/rtl/ROM/PROM1_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eyes_MiST/rtl/ROM/PROM1_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/rtl/ROM/PROM1_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Eyes_MiST/rtl/ROM/PROM3_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/rtl/ROM/PROM3_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eyes_MiST/rtl/ROM/PROM3_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/rtl/ROM/PROM3_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Eyes_MiST/rtl/ROM/PROM4_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/rtl/ROM/PROM4_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eyes_MiST/rtl/ROM/PROM4_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/rtl/ROM/PROM4_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Eyes_MiST/rtl/ROM/PROM7_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/rtl/ROM/PROM7_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eyes_MiST/rtl/ROM/PROM7_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/rtl/ROM/PROM7_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Eyes_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/rtl/ROM/ROM_PGM_0.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eyes_MiST/rtl/ROM/ROM_PGM_0.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/rtl/ROM/ROM_PGM_0.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Eyes_MiST/rtl/ROM/ROM_PGM_1.vhd b/Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/rtl/ROM/ROM_PGM_1.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eyes_MiST/rtl/ROM/ROM_PGM_1.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/rtl/ROM/ROM_PGM_1.vhd
diff --git a/Arcade_MiST/Pacman Hardware/DreamShopper_MiST/rtl/build_id.tcl b/Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/rtl/build_id.tcl
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/DreamShopper_MiST/rtl/build_id.tcl
rename to Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/rtl/build_id.tcl
diff --git a/Arcade_MiST/Pacman Hardware/Eyes_MiST/rtl/dpram.vhd b/Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/rtl/dpram.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eyes_MiST/rtl/dpram.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/rtl/dpram.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Eyes_MiST/rtl/pacman.vhd b/Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/rtl/pacman.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eyes_MiST/rtl/pacman.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/rtl/pacman.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Eyes_MiST/rtl/pacman_audio.vhd b/Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/rtl/pacman_audio.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eyes_MiST/rtl/pacman_audio.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/rtl/pacman_audio.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Eyes_MiST/rtl/pacman_rom_descrambler.vhd b/Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/rtl/pacman_rom_descrambler.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eyes_MiST/rtl/pacman_rom_descrambler.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/rtl/pacman_rom_descrambler.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Eyes_MiST/rtl/pacman_video.vhd b/Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/rtl/pacman_video.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eyes_MiST/rtl/pacman_video.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/rtl/pacman_video.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Eyes_MiST/rtl/pacman_vram_addr.vhd b/Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/rtl/pacman_vram_addr.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eyes_MiST/rtl/pacman_vram_addr.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/rtl/pacman_vram_addr.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Eyes_MiST/rtl/pll.qip b/Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/rtl/pll.qip
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eyes_MiST/rtl/pll.qip
rename to Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/rtl/pll.qip
diff --git a/Arcade_MiST/Pacman Hardware/Eyes_MiST/rtl/pll.vhd b/Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/rtl/pll.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eyes_MiST/rtl/pll.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/rtl/pll.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Eyes_MiST/rtl/sega_decode.vhd b/Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/rtl/sega_decode.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eyes_MiST/rtl/sega_decode.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Eyes_MiST/rtl/sega_decode.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Gorkans_MiST/Gorkans.qpf b/Arcade_MiST/Namco Pacman Hardware/Gorkans_MiST/Gorkans.qpf
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Gorkans_MiST/Gorkans.qpf
rename to Arcade_MiST/Namco Pacman Hardware/Gorkans_MiST/Gorkans.qpf
diff --git a/Arcade_MiST/Pacman Hardware/Gorkans_MiST/Gorkans.qsf b/Arcade_MiST/Namco Pacman Hardware/Gorkans_MiST/Gorkans.qsf
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Gorkans_MiST/Gorkans.qsf
rename to Arcade_MiST/Namco Pacman Hardware/Gorkans_MiST/Gorkans.qsf
diff --git a/Arcade_MiST/Pacman Hardware/Gorkans_MiST/Gorkans.sdc b/Arcade_MiST/Namco Pacman Hardware/Gorkans_MiST/Gorkans.sdc
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Gorkans_MiST/Gorkans.sdc
rename to Arcade_MiST/Namco Pacman Hardware/Gorkans_MiST/Gorkans.sdc
diff --git a/Arcade_MiST/Pacman Hardware/Gorkans_MiST/README.txt b/Arcade_MiST/Namco Pacman Hardware/Gorkans_MiST/README.txt
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Gorkans_MiST/README.txt
rename to Arcade_MiST/Namco Pacman Hardware/Gorkans_MiST/README.txt
diff --git a/Arcade_MiST/Pacman Hardware/Eggor_MiST/clean.bat b/Arcade_MiST/Namco Pacman Hardware/Gorkans_MiST/clean.bat
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eggor_MiST/clean.bat
rename to Arcade_MiST/Namco Pacman Hardware/Gorkans_MiST/clean.bat
diff --git a/Arcade_MiST/Pacman Hardware/Gorkans_MiST/rtl/Gorkans.sv b/Arcade_MiST/Namco Pacman Hardware/Gorkans_MiST/rtl/Gorkans.sv
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Gorkans_MiST/rtl/Gorkans.sv
rename to Arcade_MiST/Namco Pacman Hardware/Gorkans_MiST/rtl/Gorkans.sv
diff --git a/Arcade_MiST/Pacman Hardware/Gorkans_MiST/rtl/ROM/GFX1.vhd b/Arcade_MiST/Namco Pacman Hardware/Gorkans_MiST/rtl/ROM/GFX1.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Gorkans_MiST/rtl/ROM/GFX1.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Gorkans_MiST/rtl/ROM/GFX1.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Gorkans_MiST/rtl/ROM/PROM1_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Gorkans_MiST/rtl/ROM/PROM1_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Gorkans_MiST/rtl/ROM/PROM1_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Gorkans_MiST/rtl/ROM/PROM1_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Gorkans_MiST/rtl/ROM/PROM3_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Gorkans_MiST/rtl/ROM/PROM3_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Gorkans_MiST/rtl/ROM/PROM3_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Gorkans_MiST/rtl/ROM/PROM3_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Gorkans_MiST/rtl/ROM/PROM4_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Gorkans_MiST/rtl/ROM/PROM4_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Gorkans_MiST/rtl/ROM/PROM4_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Gorkans_MiST/rtl/ROM/PROM4_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Gorkans_MiST/rtl/ROM/PROM7_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Gorkans_MiST/rtl/ROM/PROM7_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Gorkans_MiST/rtl/ROM/PROM7_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Gorkans_MiST/rtl/ROM/PROM7_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Gorkans_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Namco Pacman Hardware/Gorkans_MiST/rtl/ROM/ROM_PGM_0.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Gorkans_MiST/rtl/ROM/ROM_PGM_0.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Gorkans_MiST/rtl/ROM/ROM_PGM_0.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Gorkans_MiST/rtl/ROM/ROM_PGM_1.vhd b/Arcade_MiST/Namco Pacman Hardware/Gorkans_MiST/rtl/ROM/ROM_PGM_1.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Gorkans_MiST/rtl/ROM/ROM_PGM_1.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Gorkans_MiST/rtl/ROM/ROM_PGM_1.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Eeekk_MiST/rtl/build_id.tcl b/Arcade_MiST/Namco Pacman Hardware/Gorkans_MiST/rtl/build_id.tcl
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eeekk_MiST/rtl/build_id.tcl
rename to Arcade_MiST/Namco Pacman Hardware/Gorkans_MiST/rtl/build_id.tcl
diff --git a/Arcade_MiST/Pacman Hardware/Gorkans_MiST/rtl/dpram.vhd b/Arcade_MiST/Namco Pacman Hardware/Gorkans_MiST/rtl/dpram.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Gorkans_MiST/rtl/dpram.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Gorkans_MiST/rtl/dpram.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Gorkans_MiST/rtl/pacman.vhd b/Arcade_MiST/Namco Pacman Hardware/Gorkans_MiST/rtl/pacman.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Gorkans_MiST/rtl/pacman.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Gorkans_MiST/rtl/pacman.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Gorkans_MiST/rtl/pacman_audio.vhd b/Arcade_MiST/Namco Pacman Hardware/Gorkans_MiST/rtl/pacman_audio.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Gorkans_MiST/rtl/pacman_audio.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Gorkans_MiST/rtl/pacman_audio.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Gorkans_MiST/rtl/pacman_video.vhd b/Arcade_MiST/Namco Pacman Hardware/Gorkans_MiST/rtl/pacman_video.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Gorkans_MiST/rtl/pacman_video.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Gorkans_MiST/rtl/pacman_video.vhd
diff --git a/Arcade_MiST/Pacman Hardware/DreamShopper_MiST/rtl/pll.qip b/Arcade_MiST/Namco Pacman Hardware/Gorkans_MiST/rtl/pll.qip
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/DreamShopper_MiST/rtl/pll.qip
rename to Arcade_MiST/Namco Pacman Hardware/Gorkans_MiST/rtl/pll.qip
diff --git a/Arcade_MiST/Pacman Hardware/Gorkans_MiST/rtl/pll.v b/Arcade_MiST/Namco Pacman Hardware/Gorkans_MiST/rtl/pll.v
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Gorkans_MiST/rtl/pll.v
rename to Arcade_MiST/Namco Pacman Hardware/Gorkans_MiST/rtl/pll.v
diff --git a/Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/LizardWizard.qpf b/Arcade_MiST/Namco Pacman Hardware/Lizard_Wizard_MiST/LizardWizard.qpf
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/LizardWizard.qpf
rename to Arcade_MiST/Namco Pacman Hardware/Lizard_Wizard_MiST/LizardWizard.qpf
diff --git a/Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/LizardWizard.qsf b/Arcade_MiST/Namco Pacman Hardware/Lizard_Wizard_MiST/LizardWizard.qsf
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/LizardWizard.qsf
rename to Arcade_MiST/Namco Pacman Hardware/Lizard_Wizard_MiST/LizardWizard.qsf
diff --git a/Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/LizardWizard.sdc b/Arcade_MiST/Namco Pacman Hardware/Lizard_Wizard_MiST/LizardWizard.sdc
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/LizardWizard.sdc
rename to Arcade_MiST/Namco Pacman Hardware/Lizard_Wizard_MiST/LizardWizard.sdc
diff --git a/Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/README.txt b/Arcade_MiST/Namco Pacman Hardware/Lizard_Wizard_MiST/README.txt
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/README.txt
rename to Arcade_MiST/Namco Pacman Hardware/Lizard_Wizard_MiST/README.txt
diff --git a/Arcade_MiST/Pacman Hardware/Eyes_MiST/clean.bat b/Arcade_MiST/Namco Pacman Hardware/Lizard_Wizard_MiST/clean.bat
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eyes_MiST/clean.bat
rename to Arcade_MiST/Namco Pacman Hardware/Lizard_Wizard_MiST/clean.bat
diff --git a/Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/rtl/LizardWizard.sv b/Arcade_MiST/Namco Pacman Hardware/Lizard_Wizard_MiST/rtl/LizardWizard.sv
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/rtl/LizardWizard.sv
rename to Arcade_MiST/Namco Pacman Hardware/Lizard_Wizard_MiST/rtl/LizardWizard.sv
diff --git a/Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/GFX1.vhd b/Arcade_MiST/Namco Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/GFX1.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/GFX1.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/GFX1.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/PROM1_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/PROM1_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/PROM1_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/PROM1_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/PROM3_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/PROM3_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/PROM3_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/PROM3_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/PROM4_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/PROM4_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/PROM4_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/PROM4_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/PROM7_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/PROM7_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/PROM7_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/PROM7_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Namco Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/ROM_PGM_0.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/ROM_PGM_0.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/ROM_PGM_0.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/ROM_PGM_1.vhd b/Arcade_MiST/Namco Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/ROM_PGM_1.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/ROM_PGM_1.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/ROM_PGM_1.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Eggor_MiST/rtl/build_id.tcl b/Arcade_MiST/Namco Pacman Hardware/Lizard_Wizard_MiST/rtl/build_id.tcl
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eggor_MiST/rtl/build_id.tcl
rename to Arcade_MiST/Namco Pacman Hardware/Lizard_Wizard_MiST/rtl/build_id.tcl
diff --git a/Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/rtl/dpram.vhd b/Arcade_MiST/Namco Pacman Hardware/Lizard_Wizard_MiST/rtl/dpram.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/rtl/dpram.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Lizard_Wizard_MiST/rtl/dpram.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/rtl/pacman.vhd b/Arcade_MiST/Namco Pacman Hardware/Lizard_Wizard_MiST/rtl/pacman.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/rtl/pacman.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Lizard_Wizard_MiST/rtl/pacman.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/rtl/pacman_audio.vhd b/Arcade_MiST/Namco Pacman Hardware/Lizard_Wizard_MiST/rtl/pacman_audio.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/rtl/pacman_audio.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Lizard_Wizard_MiST/rtl/pacman_audio.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/rtl/pacman_video.vhd b/Arcade_MiST/Namco Pacman Hardware/Lizard_Wizard_MiST/rtl/pacman_video.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/rtl/pacman_video.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Lizard_Wizard_MiST/rtl/pacman_video.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/rtl/pacman_vram_addr.vhd b/Arcade_MiST/Namco Pacman Hardware/Lizard_Wizard_MiST/rtl/pacman_vram_addr.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/rtl/pacman_vram_addr.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Lizard_Wizard_MiST/rtl/pacman_vram_addr.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/rtl/pll.qip b/Arcade_MiST/Namco Pacman Hardware/Lizard_Wizard_MiST/rtl/pll.qip
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/rtl/pll.qip
rename to Arcade_MiST/Namco Pacman Hardware/Lizard_Wizard_MiST/rtl/pll.qip
diff --git a/Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/rtl/pll.vhd b/Arcade_MiST/Namco Pacman Hardware/Lizard_Wizard_MiST/rtl/pll.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/rtl/pll.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Lizard_Wizard_MiST/rtl/pll.vhd
diff --git a/Arcade_MiST/Pacman Hardware/MrTNT_MiST/MrTNT.qpf b/Arcade_MiST/Namco Pacman Hardware/MrTNT_MiST/MrTNT.qpf
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MrTNT_MiST/MrTNT.qpf
rename to Arcade_MiST/Namco Pacman Hardware/MrTNT_MiST/MrTNT.qpf
diff --git a/Arcade_MiST/Pacman Hardware/MrTNT_MiST/MrTNT.qsf b/Arcade_MiST/Namco Pacman Hardware/MrTNT_MiST/MrTNT.qsf
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MrTNT_MiST/MrTNT.qsf
rename to Arcade_MiST/Namco Pacman Hardware/MrTNT_MiST/MrTNT.qsf
diff --git a/Arcade_MiST/Pacman Hardware/MrTNT_MiST/MrTNT.sdc b/Arcade_MiST/Namco Pacman Hardware/MrTNT_MiST/MrTNT.sdc
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MrTNT_MiST/MrTNT.sdc
rename to Arcade_MiST/Namco Pacman Hardware/MrTNT_MiST/MrTNT.sdc
diff --git a/Arcade_MiST/Pacman Hardware/MrTNT_MiST/README.txt b/Arcade_MiST/Namco Pacman Hardware/MrTNT_MiST/README.txt
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MrTNT_MiST/README.txt
rename to Arcade_MiST/Namco Pacman Hardware/MrTNT_MiST/README.txt
diff --git a/Arcade_MiST/Pacman Hardware/Gorkans_MiST/clean.bat b/Arcade_MiST/Namco Pacman Hardware/MrTNT_MiST/clean.bat
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Gorkans_MiST/clean.bat
rename to Arcade_MiST/Namco Pacman Hardware/MrTNT_MiST/clean.bat
diff --git a/Arcade_MiST/Pacman Hardware/MrTNT_MiST/rtl/MrTNT.sv b/Arcade_MiST/Namco Pacman Hardware/MrTNT_MiST/rtl/MrTNT.sv
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MrTNT_MiST/rtl/MrTNT.sv
rename to Arcade_MiST/Namco Pacman Hardware/MrTNT_MiST/rtl/MrTNT.sv
diff --git a/Arcade_MiST/Pacman Hardware/MrTNT_MiST/rtl/ROM/GFX1.vhd b/Arcade_MiST/Namco Pacman Hardware/MrTNT_MiST/rtl/ROM/GFX1.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MrTNT_MiST/rtl/ROM/GFX1.vhd
rename to Arcade_MiST/Namco Pacman Hardware/MrTNT_MiST/rtl/ROM/GFX1.vhd
diff --git a/Arcade_MiST/Pacman Hardware/MrTNT_MiST/rtl/ROM/PROM1_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/MrTNT_MiST/rtl/ROM/PROM1_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MrTNT_MiST/rtl/ROM/PROM1_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/MrTNT_MiST/rtl/ROM/PROM1_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/MrTNT_MiST/rtl/ROM/PROM3_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/MrTNT_MiST/rtl/ROM/PROM3_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MrTNT_MiST/rtl/ROM/PROM3_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/MrTNT_MiST/rtl/ROM/PROM3_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/MrTNT_MiST/rtl/ROM/PROM4_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/MrTNT_MiST/rtl/ROM/PROM4_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MrTNT_MiST/rtl/ROM/PROM4_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/MrTNT_MiST/rtl/ROM/PROM4_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/MrTNT_MiST/rtl/ROM/PROM7_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/MrTNT_MiST/rtl/ROM/PROM7_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MrTNT_MiST/rtl/ROM/PROM7_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/MrTNT_MiST/rtl/ROM/PROM7_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/MrTNT_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Namco Pacman Hardware/MrTNT_MiST/rtl/ROM/ROM_PGM_0.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MrTNT_MiST/rtl/ROM/ROM_PGM_0.vhd
rename to Arcade_MiST/Namco Pacman Hardware/MrTNT_MiST/rtl/ROM/ROM_PGM_0.vhd
diff --git a/Arcade_MiST/Pacman Hardware/MrTNT_MiST/rtl/ROM/ROM_PGM_1.vhd b/Arcade_MiST/Namco Pacman Hardware/MrTNT_MiST/rtl/ROM/ROM_PGM_1.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MrTNT_MiST/rtl/ROM/ROM_PGM_1.vhd
rename to Arcade_MiST/Namco Pacman Hardware/MrTNT_MiST/rtl/ROM/ROM_PGM_1.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Eyes_MiST/rtl/build_id.tcl b/Arcade_MiST/Namco Pacman Hardware/MrTNT_MiST/rtl/build_id.tcl
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eyes_MiST/rtl/build_id.tcl
rename to Arcade_MiST/Namco Pacman Hardware/MrTNT_MiST/rtl/build_id.tcl
diff --git a/Arcade_MiST/Pacman Hardware/MrTNT_MiST/rtl/dpram.vhd b/Arcade_MiST/Namco Pacman Hardware/MrTNT_MiST/rtl/dpram.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MrTNT_MiST/rtl/dpram.vhd
rename to Arcade_MiST/Namco Pacman Hardware/MrTNT_MiST/rtl/dpram.vhd
diff --git a/Arcade_MiST/Pacman Hardware/MrTNT_MiST/rtl/pacman.vhd b/Arcade_MiST/Namco Pacman Hardware/MrTNT_MiST/rtl/pacman.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MrTNT_MiST/rtl/pacman.vhd
rename to Arcade_MiST/Namco Pacman Hardware/MrTNT_MiST/rtl/pacman.vhd
diff --git a/Arcade_MiST/Pacman Hardware/MrTNT_MiST/rtl/pacman_audio.vhd b/Arcade_MiST/Namco Pacman Hardware/MrTNT_MiST/rtl/pacman_audio.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MrTNT_MiST/rtl/pacman_audio.vhd
rename to Arcade_MiST/Namco Pacman Hardware/MrTNT_MiST/rtl/pacman_audio.vhd
diff --git a/Arcade_MiST/Pacman Hardware/MrTNT_MiST/rtl/pacman_video.vhd b/Arcade_MiST/Namco Pacman Hardware/MrTNT_MiST/rtl/pacman_video.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MrTNT_MiST/rtl/pacman_video.vhd
rename to Arcade_MiST/Namco Pacman Hardware/MrTNT_MiST/rtl/pacman_video.vhd
diff --git a/Arcade_MiST/Pacman Hardware/MrTNT_MiST/rtl/pacman_vram_addr.vhd b/Arcade_MiST/Namco Pacman Hardware/MrTNT_MiST/rtl/pacman_vram_addr.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MrTNT_MiST/rtl/pacman_vram_addr.vhd
rename to Arcade_MiST/Namco Pacman Hardware/MrTNT_MiST/rtl/pacman_vram_addr.vhd
diff --git a/Arcade_MiST/Pacman Hardware/MrTNT_MiST/rtl/pll.qip b/Arcade_MiST/Namco Pacman Hardware/MrTNT_MiST/rtl/pll.qip
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MrTNT_MiST/rtl/pll.qip
rename to Arcade_MiST/Namco Pacman Hardware/MrTNT_MiST/rtl/pll.qip
diff --git a/Arcade_MiST/Pacman Hardware/MrTNT_MiST/rtl/pll.vhd b/Arcade_MiST/Namco Pacman Hardware/MrTNT_MiST/rtl/pll.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MrTNT_MiST/rtl/pll.vhd
rename to Arcade_MiST/Namco Pacman Hardware/MrTNT_MiST/rtl/pll.vhd
diff --git a/Arcade_MiST/Pacman Hardware/MsPacman_MiST/MSPacman.qpf b/Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/MSPacman.qpf
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MsPacman_MiST/MSPacman.qpf
rename to Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/MSPacman.qpf
diff --git a/Arcade_MiST/Pacman Hardware/MsPacman_MiST/MSPacman.qsf b/Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/MSPacman.qsf
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MsPacman_MiST/MSPacman.qsf
rename to Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/MSPacman.qsf
diff --git a/Arcade_MiST/Pacman Hardware/MsPacman_MiST/MSPacman.sdc b/Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/MSPacman.sdc
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MsPacman_MiST/MSPacman.sdc
rename to Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/MSPacman.sdc
diff --git a/Arcade_MiST/Pacman Hardware/MsPacman_MiST/README.txt b/Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/README.txt
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MsPacman_MiST/README.txt
rename to Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/README.txt
diff --git a/Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/clean.bat b/Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/clean.bat
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/clean.bat
rename to Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/clean.bat
diff --git a/Arcade_MiST/Pacman Hardware/MsPacman_MiST/rtl/MSPacman.sv b/Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/rtl/MSPacman.sv
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MsPacman_MiST/rtl/MSPacman.sv
rename to Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/rtl/MSPacman.sv
diff --git a/Arcade_MiST/Pacman Hardware/MsPacman_MiST/rtl/ROM/GFX1.vhd b/Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/rtl/ROM/GFX1.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MsPacman_MiST/rtl/ROM/GFX1.vhd
rename to Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/rtl/ROM/GFX1.vhd
diff --git a/Arcade_MiST/Pacman Hardware/MsPacman_MiST/rtl/ROM/PROM1_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/rtl/ROM/PROM1_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MsPacman_MiST/rtl/ROM/PROM1_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/rtl/ROM/PROM1_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/MsPacman_MiST/rtl/ROM/PROM3_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/rtl/ROM/PROM3_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MsPacman_MiST/rtl/ROM/PROM3_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/rtl/ROM/PROM3_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/MsPacman_MiST/rtl/ROM/PROM4_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/rtl/ROM/PROM4_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MsPacman_MiST/rtl/ROM/PROM4_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/rtl/ROM/PROM4_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/MsPacman_MiST/rtl/ROM/PROM7_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/rtl/ROM/PROM7_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MsPacman_MiST/rtl/ROM/PROM7_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/rtl/ROM/PROM7_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/MsPacman_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/rtl/ROM/ROM_PGM_0.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MsPacman_MiST/rtl/ROM/ROM_PGM_0.vhd
rename to Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/rtl/ROM/ROM_PGM_0.vhd
diff --git a/Arcade_MiST/Pacman Hardware/MsPacman_MiST/rtl/ROM/ROM_PGM_1.vhd b/Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/rtl/ROM/ROM_PGM_1.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MsPacman_MiST/rtl/ROM/ROM_PGM_1.vhd
rename to Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/rtl/ROM/ROM_PGM_1.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Gorkans_MiST/rtl/build_id.tcl b/Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/rtl/build_id.tcl
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Gorkans_MiST/rtl/build_id.tcl
rename to Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/rtl/build_id.tcl
diff --git a/Arcade_MiST/Pacman Hardware/MsPacman_MiST/rtl/dpram.vhd b/Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/rtl/dpram.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MsPacman_MiST/rtl/dpram.vhd
rename to Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/rtl/dpram.vhd
diff --git a/Arcade_MiST/Pacman Hardware/MsPacman_MiST/rtl/pacman.vhd b/Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/rtl/pacman.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MsPacman_MiST/rtl/pacman.vhd
rename to Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/rtl/pacman.vhd
diff --git a/Arcade_MiST/Pacman Hardware/MsPacman_MiST/rtl/pacman_audio.vhd b/Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/rtl/pacman_audio.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MsPacman_MiST/rtl/pacman_audio.vhd
rename to Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/rtl/pacman_audio.vhd
diff --git a/Arcade_MiST/Pacman Hardware/MsPacman_MiST/rtl/pacman_rom_descrambler.vhd b/Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/rtl/pacman_rom_descrambler.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MsPacman_MiST/rtl/pacman_rom_descrambler.vhd
rename to Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/rtl/pacman_rom_descrambler.vhd
diff --git a/Arcade_MiST/Pacman Hardware/MsPacman_MiST/rtl/pacman_video.vhd b/Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/rtl/pacman_video.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MsPacman_MiST/rtl/pacman_video.vhd
rename to Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/rtl/pacman_video.vhd
diff --git a/Arcade_MiST/Pacman Hardware/MsPacman_MiST/rtl/pacman_vram_addr.vhd b/Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/rtl/pacman_vram_addr.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MsPacman_MiST/rtl/pacman_vram_addr.vhd
rename to Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/rtl/pacman_vram_addr.vhd
diff --git a/Arcade_MiST/Pacman Hardware/MsPacman_MiST/rtl/pll.qip b/Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/rtl/pll.qip
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MsPacman_MiST/rtl/pll.qip
rename to Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/rtl/pll.qip
diff --git a/Arcade_MiST/Pacman Hardware/MsPacman_MiST/rtl/pll.vhd b/Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/rtl/pll.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MsPacman_MiST/rtl/pll.vhd
rename to Arcade_MiST/Namco Pacman Hardware/MsPacman_MiST/rtl/pll.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/ManiacMiner.qpf b/Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/ManiacMiner.qpf
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/ManiacMiner.qpf
rename to Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/ManiacMiner.qpf
diff --git a/Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/ManiacMiner.qsf b/Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/ManiacMiner.qsf
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/ManiacMiner.qsf
rename to Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/ManiacMiner.qsf
diff --git a/Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/ManiacMiner.sdc b/Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/ManiacMiner.sdc
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/ManiacMiner.sdc
rename to Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/ManiacMiner.sdc
diff --git a/Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/README.txt b/Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/README.txt
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/README.txt
rename to Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/README.txt
diff --git a/Arcade_MiST/Pacman Hardware/MrTNT_MiST/clean.bat b/Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/clean.bat
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MrTNT_MiST/clean.bat
rename to Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/clean.bat
diff --git a/Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/rtl/ManiacMiner.sv b/Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/rtl/ManiacMiner.sv
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/rtl/ManiacMiner.sv
rename to Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/rtl/ManiacMiner.sv
diff --git a/Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/rtl/ROM/ROM_PGM_0.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/rtl/ROM/ROM_PGM_0.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/rtl/ROM/ROM_PGM_0.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/rtl/ROM/ROM_PGM_1.vhd b/Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/rtl/ROM/ROM_PGM_1.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/rtl/ROM/ROM_PGM_1.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/rtl/ROM/ROM_PGM_1.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/rtl/ROM/gfx1.vhd b/Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/rtl/ROM/gfx1.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/rtl/ROM/gfx1.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/rtl/ROM/gfx1.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/rtl/ROM/prom1_dst.vhd b/Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/rtl/ROM/prom1_dst.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/rtl/ROM/prom1_dst.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/rtl/ROM/prom1_dst.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/rtl/ROM/prom3_dst.vhd b/Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/rtl/ROM/prom3_dst.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/rtl/ROM/prom3_dst.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/rtl/ROM/prom3_dst.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/rtl/ROM/prom4_dst.vhd b/Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/rtl/ROM/prom4_dst.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/rtl/ROM/prom4_dst.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/rtl/ROM/prom4_dst.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/rtl/ROM/prom7_dst.vhd b/Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/rtl/ROM/prom7_dst.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/rtl/ROM/prom7_dst.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/rtl/ROM/prom7_dst.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/rtl/build_id.tcl b/Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/rtl/build_id.tcl
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Lizard_Wizard_MiST/rtl/build_id.tcl
rename to Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/rtl/build_id.tcl
diff --git a/Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/rtl/dpram.vhd b/Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/rtl/dpram.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/rtl/dpram.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/rtl/dpram.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/rtl/pacman.vhd b/Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/rtl/pacman.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/rtl/pacman.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/rtl/pacman.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/rtl/pacman_audio.vhd b/Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/rtl/pacman_audio.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/rtl/pacman_audio.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/rtl/pacman_audio.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/rtl/pacman_rom_descrambler.vhd b/Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/rtl/pacman_rom_descrambler.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/rtl/pacman_rom_descrambler.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/rtl/pacman_rom_descrambler.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/rtl/pacman_video.vhd b/Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/rtl/pacman_video.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/rtl/pacman_video.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/rtl/pacman_video.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/rtl/pacman_vram_addr.vhd b/Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/rtl/pacman_vram_addr.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/rtl/pacman_vram_addr.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/rtl/pacman_vram_addr.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/rtl/pll.qip b/Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/rtl/pll.qip
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/rtl/pll.qip
rename to Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/rtl/pll.qip
diff --git a/Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/rtl/pll.vhd b/Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/rtl/pll.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/rtl/pll.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/rtl/pll.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/rtl/sega_decode.vhd b/Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/rtl/sega_decode.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/rtl/sega_decode.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Pac Manic Miner Man_MiST/rtl/sega_decode.vhd
diff --git a/Arcade_MiST/Pacman Hardware/PacmanClub_MiST/PacmanClub.qpf b/Arcade_MiST/Namco Pacman Hardware/PacmanClub_MiST/PacmanClub.qpf
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/PacmanClub_MiST/PacmanClub.qpf
rename to Arcade_MiST/Namco Pacman Hardware/PacmanClub_MiST/PacmanClub.qpf
diff --git a/Arcade_MiST/Pacman Hardware/PacmanClub_MiST/PacmanClub.qsf b/Arcade_MiST/Namco Pacman Hardware/PacmanClub_MiST/PacmanClub.qsf
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/PacmanClub_MiST/PacmanClub.qsf
rename to Arcade_MiST/Namco Pacman Hardware/PacmanClub_MiST/PacmanClub.qsf
diff --git a/Arcade_MiST/Pacman Hardware/PacmanClub_MiST/PacmanClub.sdc b/Arcade_MiST/Namco Pacman Hardware/PacmanClub_MiST/PacmanClub.sdc
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/PacmanClub_MiST/PacmanClub.sdc
rename to Arcade_MiST/Namco Pacman Hardware/PacmanClub_MiST/PacmanClub.sdc
diff --git a/Arcade_MiST/Pacman Hardware/PacmanClub_MiST/README.txt b/Arcade_MiST/Namco Pacman Hardware/PacmanClub_MiST/README.txt
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/PacmanClub_MiST/README.txt
rename to Arcade_MiST/Namco Pacman Hardware/PacmanClub_MiST/README.txt
diff --git a/Arcade_MiST/Pacman Hardware/MsPacman_MiST/clean.bat b/Arcade_MiST/Namco Pacman Hardware/PacmanClub_MiST/clean.bat
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MsPacman_MiST/clean.bat
rename to Arcade_MiST/Namco Pacman Hardware/PacmanClub_MiST/clean.bat
diff --git a/Arcade_MiST/Pacman Hardware/PacmanClub_MiST/rtl/PacmanClub.sv b/Arcade_MiST/Namco Pacman Hardware/PacmanClub_MiST/rtl/PacmanClub.sv
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/PacmanClub_MiST/rtl/PacmanClub.sv
rename to Arcade_MiST/Namco Pacman Hardware/PacmanClub_MiST/rtl/PacmanClub.sv
diff --git a/Arcade_MiST/Pacman Hardware/PacmanClub_MiST/rtl/ROM/GFX1.vhd b/Arcade_MiST/Namco Pacman Hardware/PacmanClub_MiST/rtl/ROM/GFX1.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/PacmanClub_MiST/rtl/ROM/GFX1.vhd
rename to Arcade_MiST/Namco Pacman Hardware/PacmanClub_MiST/rtl/ROM/GFX1.vhd
diff --git a/Arcade_MiST/Pacman Hardware/PacmanClub_MiST/rtl/ROM/PROM1_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/PacmanClub_MiST/rtl/ROM/PROM1_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/PacmanClub_MiST/rtl/ROM/PROM1_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/PacmanClub_MiST/rtl/ROM/PROM1_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/PacmanClub_MiST/rtl/ROM/PROM3_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/PacmanClub_MiST/rtl/ROM/PROM3_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/PacmanClub_MiST/rtl/ROM/PROM3_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/PacmanClub_MiST/rtl/ROM/PROM3_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/PacmanClub_MiST/rtl/ROM/PROM4_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/PacmanClub_MiST/rtl/ROM/PROM4_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/PacmanClub_MiST/rtl/ROM/PROM4_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/PacmanClub_MiST/rtl/ROM/PROM4_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/PacmanClub_MiST/rtl/ROM/PROM7_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/PacmanClub_MiST/rtl/ROM/PROM7_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/PacmanClub_MiST/rtl/ROM/PROM7_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/PacmanClub_MiST/rtl/ROM/PROM7_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/PacmanClub_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Namco Pacman Hardware/PacmanClub_MiST/rtl/ROM/ROM_PGM_0.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/PacmanClub_MiST/rtl/ROM/ROM_PGM_0.vhd
rename to Arcade_MiST/Namco Pacman Hardware/PacmanClub_MiST/rtl/ROM/ROM_PGM_0.vhd
diff --git a/Arcade_MiST/Pacman Hardware/PacmanClub_MiST/rtl/ROM/ROM_PGM_1.vhd b/Arcade_MiST/Namco Pacman Hardware/PacmanClub_MiST/rtl/ROM/ROM_PGM_1.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/PacmanClub_MiST/rtl/ROM/ROM_PGM_1.vhd
rename to Arcade_MiST/Namco Pacman Hardware/PacmanClub_MiST/rtl/ROM/ROM_PGM_1.vhd
diff --git a/Arcade_MiST/Pacman Hardware/MrTNT_MiST/rtl/build_id.tcl b/Arcade_MiST/Namco Pacman Hardware/PacmanClub_MiST/rtl/build_id.tcl
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MrTNT_MiST/rtl/build_id.tcl
rename to Arcade_MiST/Namco Pacman Hardware/PacmanClub_MiST/rtl/build_id.tcl
diff --git a/Arcade_MiST/Pacman Hardware/PacmanClub_MiST/rtl/dpram.vhd b/Arcade_MiST/Namco Pacman Hardware/PacmanClub_MiST/rtl/dpram.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/PacmanClub_MiST/rtl/dpram.vhd
rename to Arcade_MiST/Namco Pacman Hardware/PacmanClub_MiST/rtl/dpram.vhd
diff --git a/Arcade_MiST/Pacman Hardware/PacmanClub_MiST/rtl/pacman.vhd b/Arcade_MiST/Namco Pacman Hardware/PacmanClub_MiST/rtl/pacman.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/PacmanClub_MiST/rtl/pacman.vhd
rename to Arcade_MiST/Namco Pacman Hardware/PacmanClub_MiST/rtl/pacman.vhd
diff --git a/Arcade_MiST/Pacman Hardware/PacmanClub_MiST/rtl/pacman_audio.vhd b/Arcade_MiST/Namco Pacman Hardware/PacmanClub_MiST/rtl/pacman_audio.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/PacmanClub_MiST/rtl/pacman_audio.vhd
rename to Arcade_MiST/Namco Pacman Hardware/PacmanClub_MiST/rtl/pacman_audio.vhd
diff --git a/Arcade_MiST/Pacman Hardware/PacmanClub_MiST/rtl/pacman_video.vhd b/Arcade_MiST/Namco Pacman Hardware/PacmanClub_MiST/rtl/pacman_video.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/PacmanClub_MiST/rtl/pacman_video.vhd
rename to Arcade_MiST/Namco Pacman Hardware/PacmanClub_MiST/rtl/pacman_video.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Eeekk_MiST/rtl/pll.qip b/Arcade_MiST/Namco Pacman Hardware/PacmanClub_MiST/rtl/pll.qip
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Eeekk_MiST/rtl/pll.qip
rename to Arcade_MiST/Namco Pacman Hardware/PacmanClub_MiST/rtl/pll.qip
diff --git a/Arcade_MiST/Pacman Hardware/PacmanClub_MiST/rtl/pll.v b/Arcade_MiST/Namco Pacman Hardware/PacmanClub_MiST/rtl/pll.v
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/PacmanClub_MiST/rtl/pll.v
rename to Arcade_MiST/Namco Pacman Hardware/PacmanClub_MiST/rtl/pll.v
diff --git a/Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/PacmanPlus.qpf b/Arcade_MiST/Namco Pacman Hardware/PacmanPlus_MiST/PacmanPlus.qpf
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/PacmanPlus.qpf
rename to Arcade_MiST/Namco Pacman Hardware/PacmanPlus_MiST/PacmanPlus.qpf
diff --git a/Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/PacmanPlus.qsf b/Arcade_MiST/Namco Pacman Hardware/PacmanPlus_MiST/PacmanPlus.qsf
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/PacmanPlus.qsf
rename to Arcade_MiST/Namco Pacman Hardware/PacmanPlus_MiST/PacmanPlus.qsf
diff --git a/Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/PacmanPlus.sdc b/Arcade_MiST/Namco Pacman Hardware/PacmanPlus_MiST/PacmanPlus.sdc
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/PacmanPlus.sdc
rename to Arcade_MiST/Namco Pacman Hardware/PacmanPlus_MiST/PacmanPlus.sdc
diff --git a/Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/README.txt b/Arcade_MiST/Namco Pacman Hardware/PacmanPlus_MiST/README.txt
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/README.txt
rename to Arcade_MiST/Namco Pacman Hardware/PacmanPlus_MiST/README.txt
diff --git a/Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/clean.bat b/Arcade_MiST/Namco Pacman Hardware/PacmanPlus_MiST/clean.bat
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/clean.bat
rename to Arcade_MiST/Namco Pacman Hardware/PacmanPlus_MiST/clean.bat
diff --git a/Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/rtl/PacmanPlus.sv b/Arcade_MiST/Namco Pacman Hardware/PacmanPlus_MiST/rtl/PacmanPlus.sv
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/rtl/PacmanPlus.sv
rename to Arcade_MiST/Namco Pacman Hardware/PacmanPlus_MiST/rtl/PacmanPlus.sv
diff --git a/Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/rtl/ROM/GFX1.vhd b/Arcade_MiST/Namco Pacman Hardware/PacmanPlus_MiST/rtl/ROM/GFX1.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/rtl/ROM/GFX1.vhd
rename to Arcade_MiST/Namco Pacman Hardware/PacmanPlus_MiST/rtl/ROM/GFX1.vhd
diff --git a/Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/rtl/ROM/PROM1_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/PacmanPlus_MiST/rtl/ROM/PROM1_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/rtl/ROM/PROM1_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/PacmanPlus_MiST/rtl/ROM/PROM1_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/rtl/ROM/PROM3_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/PacmanPlus_MiST/rtl/ROM/PROM3_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/rtl/ROM/PROM3_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/PacmanPlus_MiST/rtl/ROM/PROM3_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/rtl/ROM/PROM4_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/PacmanPlus_MiST/rtl/ROM/PROM4_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/rtl/ROM/PROM4_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/PacmanPlus_MiST/rtl/ROM/PROM4_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/rtl/ROM/PROM7_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/PacmanPlus_MiST/rtl/ROM/PROM7_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/rtl/ROM/PROM7_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/PacmanPlus_MiST/rtl/ROM/PROM7_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Namco Pacman Hardware/PacmanPlus_MiST/rtl/ROM/ROM_PGM_0.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/rtl/ROM/ROM_PGM_0.vhd
rename to Arcade_MiST/Namco Pacman Hardware/PacmanPlus_MiST/rtl/ROM/ROM_PGM_0.vhd
diff --git a/Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/rtl/ROM/ROM_PGM_1.vhd b/Arcade_MiST/Namco Pacman Hardware/PacmanPlus_MiST/rtl/ROM/ROM_PGM_1.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/rtl/ROM/ROM_PGM_1.vhd
rename to Arcade_MiST/Namco Pacman Hardware/PacmanPlus_MiST/rtl/ROM/ROM_PGM_1.vhd
diff --git a/Arcade_MiST/Pacman Hardware/MsPacman_MiST/rtl/build_id.tcl b/Arcade_MiST/Namco Pacman Hardware/PacmanPlus_MiST/rtl/build_id.tcl
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/MsPacman_MiST/rtl/build_id.tcl
rename to Arcade_MiST/Namco Pacman Hardware/PacmanPlus_MiST/rtl/build_id.tcl
diff --git a/Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/rtl/dpram.vhd b/Arcade_MiST/Namco Pacman Hardware/PacmanPlus_MiST/rtl/dpram.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/rtl/dpram.vhd
rename to Arcade_MiST/Namco Pacman Hardware/PacmanPlus_MiST/rtl/dpram.vhd
diff --git a/Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/rtl/pacman.vhd b/Arcade_MiST/Namco Pacman Hardware/PacmanPlus_MiST/rtl/pacman.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/rtl/pacman.vhd
rename to Arcade_MiST/Namco Pacman Hardware/PacmanPlus_MiST/rtl/pacman.vhd
diff --git a/Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/rtl/pacman_audio.vhd b/Arcade_MiST/Namco Pacman Hardware/PacmanPlus_MiST/rtl/pacman_audio.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/rtl/pacman_audio.vhd
rename to Arcade_MiST/Namco Pacman Hardware/PacmanPlus_MiST/rtl/pacman_audio.vhd
diff --git a/Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/rtl/pacman_video.vhd b/Arcade_MiST/Namco Pacman Hardware/PacmanPlus_MiST/rtl/pacman_video.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/rtl/pacman_video.vhd
rename to Arcade_MiST/Namco Pacman Hardware/PacmanPlus_MiST/rtl/pacman_video.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Gorkans_MiST/rtl/pll.qip b/Arcade_MiST/Namco Pacman Hardware/PacmanPlus_MiST/rtl/pll.qip
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Gorkans_MiST/rtl/pll.qip
rename to Arcade_MiST/Namco Pacman Hardware/PacmanPlus_MiST/rtl/pll.qip
diff --git a/Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/rtl/pll.v b/Arcade_MiST/Namco Pacman Hardware/PacmanPlus_MiST/rtl/pll.v
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/rtl/pll.v
rename to Arcade_MiST/Namco Pacman Hardware/PacmanPlus_MiST/rtl/pll.v
diff --git a/Arcade_MiST/Pacman Hardware/Pacman_MiST/Pacman.qpf b/Arcade_MiST/Namco Pacman Hardware/Pacman_MiST/Pacman.qpf
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pacman_MiST/Pacman.qpf
rename to Arcade_MiST/Namco Pacman Hardware/Pacman_MiST/Pacman.qpf
diff --git a/Arcade_MiST/Pacman Hardware/Pacman_MiST/Pacman.qsf b/Arcade_MiST/Namco Pacman Hardware/Pacman_MiST/Pacman.qsf
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pacman_MiST/Pacman.qsf
rename to Arcade_MiST/Namco Pacman Hardware/Pacman_MiST/Pacman.qsf
diff --git a/Arcade_MiST/Pacman Hardware/Pacman_MiST/Pacman.sdc b/Arcade_MiST/Namco Pacman Hardware/Pacman_MiST/Pacman.sdc
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pacman_MiST/Pacman.sdc
rename to Arcade_MiST/Namco Pacman Hardware/Pacman_MiST/Pacman.sdc
diff --git a/Arcade_MiST/Pacman Hardware/Pacman_MiST/README.txt b/Arcade_MiST/Namco Pacman Hardware/Pacman_MiST/README.txt
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pacman_MiST/README.txt
rename to Arcade_MiST/Namco Pacman Hardware/Pacman_MiST/README.txt
diff --git a/Arcade_MiST/Pacman Hardware/PacmanClub_MiST/clean.bat b/Arcade_MiST/Namco Pacman Hardware/Pacman_MiST/clean.bat
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/PacmanClub_MiST/clean.bat
rename to Arcade_MiST/Namco Pacman Hardware/Pacman_MiST/clean.bat
diff --git a/Arcade_MiST/Pacman Hardware/Pacman_MiST/rtl/Pacman.sv b/Arcade_MiST/Namco Pacman Hardware/Pacman_MiST/rtl/Pacman.sv
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pacman_MiST/rtl/Pacman.sv
rename to Arcade_MiST/Namco Pacman Hardware/Pacman_MiST/rtl/Pacman.sv
diff --git a/Arcade_MiST/Pacman Hardware/Pacman_MiST/rtl/ROM/GFX1.vhd b/Arcade_MiST/Namco Pacman Hardware/Pacman_MiST/rtl/ROM/GFX1.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pacman_MiST/rtl/ROM/GFX1.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Pacman_MiST/rtl/ROM/GFX1.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Pacman_MiST/rtl/ROM/PROM1_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Pacman_MiST/rtl/ROM/PROM1_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pacman_MiST/rtl/ROM/PROM1_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Pacman_MiST/rtl/ROM/PROM1_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Pacman_MiST/rtl/ROM/PROM4_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Pacman_MiST/rtl/ROM/PROM4_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pacman_MiST/rtl/ROM/PROM4_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Pacman_MiST/rtl/ROM/PROM4_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Pacman_MiST/rtl/ROM/PROM7_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Pacman_MiST/rtl/ROM/PROM7_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pacman_MiST/rtl/ROM/PROM7_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Pacman_MiST/rtl/ROM/PROM7_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Pacman_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Namco Pacman Hardware/Pacman_MiST/rtl/ROM/ROM_PGM_0.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pacman_MiST/rtl/ROM/ROM_PGM_0.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Pacman_MiST/rtl/ROM/ROM_PGM_0.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Pacman_MiST/rtl/ROM/ROM_PGM_1.vhd b/Arcade_MiST/Namco Pacman Hardware/Pacman_MiST/rtl/ROM/ROM_PGM_1.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pacman_MiST/rtl/ROM/ROM_PGM_1.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Pacman_MiST/rtl/ROM/ROM_PGM_1.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/rtl/build_id.tcl b/Arcade_MiST/Namco Pacman Hardware/Pacman_MiST/rtl/build_id.tcl
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pac Manic Miner Man_MiST/rtl/build_id.tcl
rename to Arcade_MiST/Namco Pacman Hardware/Pacman_MiST/rtl/build_id.tcl
diff --git a/Arcade_MiST/Pacman Hardware/Pacman_MiST/rtl/dpram.vhd b/Arcade_MiST/Namco Pacman Hardware/Pacman_MiST/rtl/dpram.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pacman_MiST/rtl/dpram.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Pacman_MiST/rtl/dpram.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Pacman_MiST/rtl/pacman.vhd b/Arcade_MiST/Namco Pacman Hardware/Pacman_MiST/rtl/pacman.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pacman_MiST/rtl/pacman.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Pacman_MiST/rtl/pacman.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Pacman_MiST/rtl/pacman_audio.vhd b/Arcade_MiST/Namco Pacman Hardware/Pacman_MiST/rtl/pacman_audio.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pacman_MiST/rtl/pacman_audio.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Pacman_MiST/rtl/pacman_audio.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Pacman_MiST/rtl/pacman_video.vhd b/Arcade_MiST/Namco Pacman Hardware/Pacman_MiST/rtl/pacman_video.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pacman_MiST/rtl/pacman_video.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Pacman_MiST/rtl/pacman_video.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Pacman_MiST/rtl/pacman_vram_addr.vhd b/Arcade_MiST/Namco Pacman Hardware/Pacman_MiST/rtl/pacman_vram_addr.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pacman_MiST/rtl/pacman_vram_addr.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Pacman_MiST/rtl/pacman_vram_addr.vhd
diff --git a/Arcade_MiST/Pacman Hardware/PacmanClub_MiST/rtl/pll.qip b/Arcade_MiST/Namco Pacman Hardware/Pacman_MiST/rtl/pll.qip
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/PacmanClub_MiST/rtl/pll.qip
rename to Arcade_MiST/Namco Pacman Hardware/Pacman_MiST/rtl/pll.qip
diff --git a/Arcade_MiST/Pacman Hardware/Pacman_MiST/rtl/pll.v b/Arcade_MiST/Namco Pacman Hardware/Pacman_MiST/rtl/pll.v
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pacman_MiST/rtl/pll.v
rename to Arcade_MiST/Namco Pacman Hardware/Pacman_MiST/rtl/pll.v
diff --git a/Arcade_MiST/Pacman Hardware/Pengo_MiST/Pengo.qpf b/Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/Pengo.qpf
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pengo_MiST/Pengo.qpf
rename to Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/Pengo.qpf
diff --git a/Arcade_MiST/Pacman Hardware/Pengo_MiST/Pengo.qsf b/Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/Pengo.qsf
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pengo_MiST/Pengo.qsf
rename to Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/Pengo.qsf
diff --git a/Arcade_MiST/Pacman Hardware/Pengo_MiST/Pengo.sdc b/Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/Pengo.sdc
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pengo_MiST/Pengo.sdc
rename to Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/Pengo.sdc
diff --git a/Arcade_MiST/Pacman Hardware/Pengo_MiST/README.txt b/Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/README.txt
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pengo_MiST/README.txt
rename to Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/README.txt
diff --git a/Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/clean.bat b/Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/clean.bat
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/clean.bat
rename to Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/clean.bat
diff --git a/Arcade_MiST/Pacman Hardware/Pengo_MiST/rtl/Pengo.sv b/Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/rtl/Pengo.sv
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pengo_MiST/rtl/Pengo.sv
rename to Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/rtl/Pengo.sv
diff --git a/Arcade_MiST/Pacman Hardware/Pengo_MiST/rtl/ROM/GFX1.vhd b/Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/rtl/ROM/GFX1.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pengo_MiST/rtl/ROM/GFX1.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/rtl/ROM/GFX1.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Pengo_MiST/rtl/ROM/PROM1_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/rtl/ROM/PROM1_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pengo_MiST/rtl/ROM/PROM1_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/rtl/ROM/PROM1_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Pengo_MiST/rtl/ROM/PROM3_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/rtl/ROM/PROM3_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pengo_MiST/rtl/ROM/PROM3_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/rtl/ROM/PROM3_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Pengo_MiST/rtl/ROM/PROM4_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/rtl/ROM/PROM4_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pengo_MiST/rtl/ROM/PROM4_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/rtl/ROM/PROM4_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Pengo_MiST/rtl/ROM/PROM7_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/rtl/ROM/PROM7_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pengo_MiST/rtl/ROM/PROM7_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/rtl/ROM/PROM7_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Pengo_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/rtl/ROM/ROM_PGM_0.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pengo_MiST/rtl/ROM/ROM_PGM_0.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/rtl/ROM/ROM_PGM_0.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Pengo_MiST/rtl/ROM/ROM_PGM_1.vhd b/Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/rtl/ROM/ROM_PGM_1.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pengo_MiST/rtl/ROM/ROM_PGM_1.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/rtl/ROM/ROM_PGM_1.vhd
diff --git a/Arcade_MiST/Pacman Hardware/PacmanClub_MiST/rtl/build_id.tcl b/Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/rtl/build_id.tcl
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/PacmanClub_MiST/rtl/build_id.tcl
rename to Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/rtl/build_id.tcl
diff --git a/Arcade_MiST/Pacman Hardware/Pengo_MiST/rtl/dpram.vhd b/Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/rtl/dpram.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pengo_MiST/rtl/dpram.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/rtl/dpram.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Pengo_MiST/rtl/pacman.vhd b/Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/rtl/pacman.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pengo_MiST/rtl/pacman.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/rtl/pacman.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Pengo_MiST/rtl/pacman_audio.vhd b/Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/rtl/pacman_audio.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pengo_MiST/rtl/pacman_audio.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/rtl/pacman_audio.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Pengo_MiST/rtl/pacman_rom_descrambler.vhd b/Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/rtl/pacman_rom_descrambler.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pengo_MiST/rtl/pacman_rom_descrambler.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/rtl/pacman_rom_descrambler.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Pengo_MiST/rtl/pacman_video.vhd b/Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/rtl/pacman_video.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pengo_MiST/rtl/pacman_video.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/rtl/pacman_video.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Pengo_MiST/rtl/pacman_vram_addr.vhd b/Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/rtl/pacman_vram_addr.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pengo_MiST/rtl/pacman_vram_addr.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/rtl/pacman_vram_addr.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Pengo_MiST/rtl/pll.qip b/Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/rtl/pll.qip
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pengo_MiST/rtl/pll.qip
rename to Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/rtl/pll.qip
diff --git a/Arcade_MiST/Pacman Hardware/Pengo_MiST/rtl/pll.vhd b/Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/rtl/pll.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pengo_MiST/rtl/pll.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/rtl/pll.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Pengo_MiST/rtl/sega_decode.vhd b/Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/rtl/sega_decode.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pengo_MiST/rtl/sega_decode.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Pengo_MiST/rtl/sega_decode.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Ponpoko_MiST/Ponpoko.qpf b/Arcade_MiST/Namco Pacman Hardware/Ponpoko_MiST/Ponpoko.qpf
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Ponpoko_MiST/Ponpoko.qpf
rename to Arcade_MiST/Namco Pacman Hardware/Ponpoko_MiST/Ponpoko.qpf
diff --git a/Arcade_MiST/Pacman Hardware/Ponpoko_MiST/Ponpoko.qsf b/Arcade_MiST/Namco Pacman Hardware/Ponpoko_MiST/Ponpoko.qsf
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Ponpoko_MiST/Ponpoko.qsf
rename to Arcade_MiST/Namco Pacman Hardware/Ponpoko_MiST/Ponpoko.qsf
diff --git a/Arcade_MiST/Pacman Hardware/Ponpoko_MiST/Ponpoko.sdc b/Arcade_MiST/Namco Pacman Hardware/Ponpoko_MiST/Ponpoko.sdc
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Ponpoko_MiST/Ponpoko.sdc
rename to Arcade_MiST/Namco Pacman Hardware/Ponpoko_MiST/Ponpoko.sdc
diff --git a/Arcade_MiST/Pacman Hardware/Ponpoko_MiST/README.txt b/Arcade_MiST/Namco Pacman Hardware/Ponpoko_MiST/README.txt
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Ponpoko_MiST/README.txt
rename to Arcade_MiST/Namco Pacman Hardware/Ponpoko_MiST/README.txt
diff --git a/Arcade_MiST/Pacman Hardware/Pacman_MiST/clean.bat b/Arcade_MiST/Namco Pacman Hardware/Ponpoko_MiST/clean.bat
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pacman_MiST/clean.bat
rename to Arcade_MiST/Namco Pacman Hardware/Ponpoko_MiST/clean.bat
diff --git a/Arcade_MiST/Pacman Hardware/Ponpoko_MiST/rtl/Ponpoko.sv b/Arcade_MiST/Namco Pacman Hardware/Ponpoko_MiST/rtl/Ponpoko.sv
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Ponpoko_MiST/rtl/Ponpoko.sv
rename to Arcade_MiST/Namco Pacman Hardware/Ponpoko_MiST/rtl/Ponpoko.sv
diff --git a/Arcade_MiST/Pacman Hardware/Ponpoko_MiST/rtl/ROM/GFX1.vhd b/Arcade_MiST/Namco Pacman Hardware/Ponpoko_MiST/rtl/ROM/GFX1.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Ponpoko_MiST/rtl/ROM/GFX1.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Ponpoko_MiST/rtl/ROM/GFX1.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Ponpoko_MiST/rtl/ROM/PROM1_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Ponpoko_MiST/rtl/ROM/PROM1_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Ponpoko_MiST/rtl/ROM/PROM1_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Ponpoko_MiST/rtl/ROM/PROM1_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Ponpoko_MiST/rtl/ROM/PROM3_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Ponpoko_MiST/rtl/ROM/PROM3_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Ponpoko_MiST/rtl/ROM/PROM3_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Ponpoko_MiST/rtl/ROM/PROM3_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Ponpoko_MiST/rtl/ROM/PROM4_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Ponpoko_MiST/rtl/ROM/PROM4_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Ponpoko_MiST/rtl/ROM/PROM4_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Ponpoko_MiST/rtl/ROM/PROM4_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Ponpoko_MiST/rtl/ROM/PROM7_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Ponpoko_MiST/rtl/ROM/PROM7_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Ponpoko_MiST/rtl/ROM/PROM7_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Ponpoko_MiST/rtl/ROM/PROM7_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Ponpoko_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Namco Pacman Hardware/Ponpoko_MiST/rtl/ROM/ROM_PGM_0.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Ponpoko_MiST/rtl/ROM/ROM_PGM_0.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Ponpoko_MiST/rtl/ROM/ROM_PGM_0.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Ponpoko_MiST/rtl/ROM/ROM_PGM_1.vhd b/Arcade_MiST/Namco Pacman Hardware/Ponpoko_MiST/rtl/ROM/ROM_PGM_1.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Ponpoko_MiST/rtl/ROM/ROM_PGM_1.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Ponpoko_MiST/rtl/ROM/ROM_PGM_1.vhd
diff --git a/Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/rtl/build_id.tcl b/Arcade_MiST/Namco Pacman Hardware/Ponpoko_MiST/rtl/build_id.tcl
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/rtl/build_id.tcl
rename to Arcade_MiST/Namco Pacman Hardware/Ponpoko_MiST/rtl/build_id.tcl
diff --git a/Arcade_MiST/Pacman Hardware/Ponpoko_MiST/rtl/dpram.vhd b/Arcade_MiST/Namco Pacman Hardware/Ponpoko_MiST/rtl/dpram.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Ponpoko_MiST/rtl/dpram.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Ponpoko_MiST/rtl/dpram.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Ponpoko_MiST/rtl/pacman.vhd b/Arcade_MiST/Namco Pacman Hardware/Ponpoko_MiST/rtl/pacman.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Ponpoko_MiST/rtl/pacman.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Ponpoko_MiST/rtl/pacman.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Ponpoko_MiST/rtl/pacman_audio.vhd b/Arcade_MiST/Namco Pacman Hardware/Ponpoko_MiST/rtl/pacman_audio.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Ponpoko_MiST/rtl/pacman_audio.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Ponpoko_MiST/rtl/pacman_audio.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Ponpoko_MiST/rtl/pacman_video.vhd b/Arcade_MiST/Namco Pacman Hardware/Ponpoko_MiST/rtl/pacman_video.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Ponpoko_MiST/rtl/pacman_video.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Ponpoko_MiST/rtl/pacman_video.vhd
diff --git a/Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/rtl/pll.qip b/Arcade_MiST/Namco Pacman Hardware/Ponpoko_MiST/rtl/pll.qip
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/PacmanPlus_MiST/rtl/pll.qip
rename to Arcade_MiST/Namco Pacman Hardware/Ponpoko_MiST/rtl/pll.qip
diff --git a/Arcade_MiST/Pacman Hardware/Ponpoko_MiST/rtl/pll.v b/Arcade_MiST/Namco Pacman Hardware/Ponpoko_MiST/rtl/pll.v
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Ponpoko_MiST/rtl/pll.v
rename to Arcade_MiST/Namco Pacman Hardware/Ponpoko_MiST/rtl/pll.v
diff --git a/Arcade_MiST/Pacman Hardware/ReadMe.txt b/Arcade_MiST/Namco Pacman Hardware/ReadMe.txt
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/ReadMe.txt
rename to Arcade_MiST/Namco Pacman Hardware/ReadMe.txt
diff --git a/Arcade_MiST/Pacman Hardware/SuperGlob_MiST/README.txt b/Arcade_MiST/Namco Pacman Hardware/SuperGlob_MiST/README.txt
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/SuperGlob_MiST/README.txt
rename to Arcade_MiST/Namco Pacman Hardware/SuperGlob_MiST/README.txt
diff --git a/Arcade_MiST/Pacman Hardware/SuperGlob_MiST/SuperGlob.qpf b/Arcade_MiST/Namco Pacman Hardware/SuperGlob_MiST/SuperGlob.qpf
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/SuperGlob_MiST/SuperGlob.qpf
rename to Arcade_MiST/Namco Pacman Hardware/SuperGlob_MiST/SuperGlob.qpf
diff --git a/Arcade_MiST/Pacman Hardware/SuperGlob_MiST/SuperGlob.qsf b/Arcade_MiST/Namco Pacman Hardware/SuperGlob_MiST/SuperGlob.qsf
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/SuperGlob_MiST/SuperGlob.qsf
rename to Arcade_MiST/Namco Pacman Hardware/SuperGlob_MiST/SuperGlob.qsf
diff --git a/Arcade_MiST/Pacman Hardware/SuperGlob_MiST/SuperGlob.sdc b/Arcade_MiST/Namco Pacman Hardware/SuperGlob_MiST/SuperGlob.sdc
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/SuperGlob_MiST/SuperGlob.sdc
rename to Arcade_MiST/Namco Pacman Hardware/SuperGlob_MiST/SuperGlob.sdc
diff --git a/Arcade_MiST/Pacman Hardware/Pengo_MiST/clean.bat b/Arcade_MiST/Namco Pacman Hardware/SuperGlob_MiST/clean.bat
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pengo_MiST/clean.bat
rename to Arcade_MiST/Namco Pacman Hardware/SuperGlob_MiST/clean.bat
diff --git a/Arcade_MiST/Pacman Hardware/SuperGlob_MiST/rtl/ROM/GFX1.vhd b/Arcade_MiST/Namco Pacman Hardware/SuperGlob_MiST/rtl/ROM/GFX1.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/SuperGlob_MiST/rtl/ROM/GFX1.vhd
rename to Arcade_MiST/Namco Pacman Hardware/SuperGlob_MiST/rtl/ROM/GFX1.vhd
diff --git a/Arcade_MiST/Pacman Hardware/SuperGlob_MiST/rtl/ROM/PROM1_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/SuperGlob_MiST/rtl/ROM/PROM1_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/SuperGlob_MiST/rtl/ROM/PROM1_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/SuperGlob_MiST/rtl/ROM/PROM1_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/SuperGlob_MiST/rtl/ROM/PROM3_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/SuperGlob_MiST/rtl/ROM/PROM3_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/SuperGlob_MiST/rtl/ROM/PROM3_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/SuperGlob_MiST/rtl/ROM/PROM3_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/SuperGlob_MiST/rtl/ROM/PROM4_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/SuperGlob_MiST/rtl/ROM/PROM4_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/SuperGlob_MiST/rtl/ROM/PROM4_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/SuperGlob_MiST/rtl/ROM/PROM4_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/SuperGlob_MiST/rtl/ROM/PROM7_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/SuperGlob_MiST/rtl/ROM/PROM7_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/SuperGlob_MiST/rtl/ROM/PROM7_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/SuperGlob_MiST/rtl/ROM/PROM7_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/SuperGlob_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Namco Pacman Hardware/SuperGlob_MiST/rtl/ROM/ROM_PGM_0.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/SuperGlob_MiST/rtl/ROM/ROM_PGM_0.vhd
rename to Arcade_MiST/Namco Pacman Hardware/SuperGlob_MiST/rtl/ROM/ROM_PGM_0.vhd
diff --git a/Arcade_MiST/Pacman Hardware/SuperGlob_MiST/rtl/ROM/ROM_PGM_1.vhd b/Arcade_MiST/Namco Pacman Hardware/SuperGlob_MiST/rtl/ROM/ROM_PGM_1.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/SuperGlob_MiST/rtl/ROM/ROM_PGM_1.vhd
rename to Arcade_MiST/Namco Pacman Hardware/SuperGlob_MiST/rtl/ROM/ROM_PGM_1.vhd
diff --git a/Arcade_MiST/Pacman Hardware/SuperGlob_MiST/rtl/SuperGlob.sv b/Arcade_MiST/Namco Pacman Hardware/SuperGlob_MiST/rtl/SuperGlob.sv
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/SuperGlob_MiST/rtl/SuperGlob.sv
rename to Arcade_MiST/Namco Pacman Hardware/SuperGlob_MiST/rtl/SuperGlob.sv
diff --git a/Arcade_MiST/Pacman Hardware/Pacman_MiST/rtl/build_id.tcl b/Arcade_MiST/Namco Pacman Hardware/SuperGlob_MiST/rtl/build_id.tcl
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pacman_MiST/rtl/build_id.tcl
rename to Arcade_MiST/Namco Pacman Hardware/SuperGlob_MiST/rtl/build_id.tcl
diff --git a/Arcade_MiST/Pacman Hardware/SuperGlob_MiST/rtl/dpram.vhd b/Arcade_MiST/Namco Pacman Hardware/SuperGlob_MiST/rtl/dpram.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/SuperGlob_MiST/rtl/dpram.vhd
rename to Arcade_MiST/Namco Pacman Hardware/SuperGlob_MiST/rtl/dpram.vhd
diff --git a/Arcade_MiST/Pacman Hardware/SuperGlob_MiST/rtl/pacman.vhd b/Arcade_MiST/Namco Pacman Hardware/SuperGlob_MiST/rtl/pacman.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/SuperGlob_MiST/rtl/pacman.vhd
rename to Arcade_MiST/Namco Pacman Hardware/SuperGlob_MiST/rtl/pacman.vhd
diff --git a/Arcade_MiST/Pacman Hardware/SuperGlob_MiST/rtl/pacman_audio.vhd b/Arcade_MiST/Namco Pacman Hardware/SuperGlob_MiST/rtl/pacman_audio.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/SuperGlob_MiST/rtl/pacman_audio.vhd
rename to Arcade_MiST/Namco Pacman Hardware/SuperGlob_MiST/rtl/pacman_audio.vhd
diff --git a/Arcade_MiST/Pacman Hardware/SuperGlob_MiST/rtl/pacman_video.vhd b/Arcade_MiST/Namco Pacman Hardware/SuperGlob_MiST/rtl/pacman_video.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/SuperGlob_MiST/rtl/pacman_video.vhd
rename to Arcade_MiST/Namco Pacman Hardware/SuperGlob_MiST/rtl/pacman_video.vhd
diff --git a/Arcade_MiST/Pacman Hardware/SuperGlob_MiST/rtl/pacman_vram_addr.vhd b/Arcade_MiST/Namco Pacman Hardware/SuperGlob_MiST/rtl/pacman_vram_addr.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/SuperGlob_MiST/rtl/pacman_vram_addr.vhd
rename to Arcade_MiST/Namco Pacman Hardware/SuperGlob_MiST/rtl/pacman_vram_addr.vhd
diff --git a/Arcade_MiST/Pacman Hardware/SuperGlob_MiST/rtl/pll.qip b/Arcade_MiST/Namco Pacman Hardware/SuperGlob_MiST/rtl/pll.qip
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/SuperGlob_MiST/rtl/pll.qip
rename to Arcade_MiST/Namco Pacman Hardware/SuperGlob_MiST/rtl/pll.qip
diff --git a/Arcade_MiST/Pacman Hardware/SuperGlob_MiST/rtl/pll.vhd b/Arcade_MiST/Namco Pacman Hardware/SuperGlob_MiST/rtl/pll.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/SuperGlob_MiST/rtl/pll.vhd
rename to Arcade_MiST/Namco Pacman Hardware/SuperGlob_MiST/rtl/pll.vhd
diff --git a/Arcade_MiST/Pacman Hardware/VanVanCar_MiST/README.txt b/Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/README.txt
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/VanVanCar_MiST/README.txt
rename to Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/README.txt
diff --git a/Arcade_MiST/Pacman Hardware/VanVanCar_MiST/VanVanCar.qpf b/Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/VanVanCar.qpf
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/VanVanCar_MiST/VanVanCar.qpf
rename to Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/VanVanCar.qpf
diff --git a/Arcade_MiST/Pacman Hardware/VanVanCar_MiST/VanVanCar.qsf b/Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/VanVanCar.qsf
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/VanVanCar_MiST/VanVanCar.qsf
rename to Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/VanVanCar.qsf
diff --git a/Arcade_MiST/Pacman Hardware/VanVanCar_MiST/VanVanCar.sdc b/Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/VanVanCar.sdc
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/VanVanCar_MiST/VanVanCar.sdc
rename to Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/VanVanCar.sdc
diff --git a/Arcade_MiST/Pacman Hardware/Ponpoko_MiST/clean.bat b/Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/clean.bat
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Ponpoko_MiST/clean.bat
rename to Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/clean.bat
diff --git a/Arcade_MiST/Pacman Hardware/VanVanCar_MiST/rtl/ROM/GFX1.vhd b/Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/rtl/ROM/GFX1.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/VanVanCar_MiST/rtl/ROM/GFX1.vhd
rename to Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/rtl/ROM/GFX1.vhd
diff --git a/Arcade_MiST/Pacman Hardware/VanVanCar_MiST/rtl/ROM/PROM4_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/rtl/ROM/PROM4_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/VanVanCar_MiST/rtl/ROM/PROM4_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/rtl/ROM/PROM4_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/VanVanCar_MiST/rtl/ROM/PROM7_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/rtl/ROM/PROM7_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/VanVanCar_MiST/rtl/ROM/PROM7_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/rtl/ROM/PROM7_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/VanVanCar_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/rtl/ROM/ROM_PGM_0.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/VanVanCar_MiST/rtl/ROM/ROM_PGM_0.vhd
rename to Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/rtl/ROM/ROM_PGM_0.vhd
diff --git a/Arcade_MiST/Pacman Hardware/VanVanCar_MiST/rtl/ROM/ROM_PGM_1.vhd b/Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/rtl/ROM/ROM_PGM_1.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/VanVanCar_MiST/rtl/ROM/ROM_PGM_1.vhd
rename to Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/rtl/ROM/ROM_PGM_1.vhd
diff --git a/Arcade_MiST/Pacman Hardware/VanVanCar_MiST/rtl/VanVanCar.sv b/Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/rtl/VanVanCar.sv
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/VanVanCar_MiST/rtl/VanVanCar.sv
rename to Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/rtl/VanVanCar.sv
diff --git a/Arcade_MiST/Pacman Hardware/Pengo_MiST/rtl/build_id.tcl b/Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/rtl/build_id.tcl
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pengo_MiST/rtl/build_id.tcl
rename to Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/rtl/build_id.tcl
diff --git a/Arcade_MiST/Pacman Hardware/VanVanCar_MiST/rtl/dpram.vhd b/Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/rtl/dpram.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/VanVanCar_MiST/rtl/dpram.vhd
rename to Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/rtl/dpram.vhd
diff --git a/Arcade_MiST/Pacman Hardware/VanVanCar_MiST/rtl/pll.qip b/Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/rtl/pll.qip
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/VanVanCar_MiST/rtl/pll.qip
rename to Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/rtl/pll.qip
diff --git a/Arcade_MiST/Pacman Hardware/VanVanCar_MiST/rtl/pll.vhd b/Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/rtl/pll.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/VanVanCar_MiST/rtl/pll.vhd
rename to Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/rtl/pll.vhd
diff --git a/Arcade_MiST/Pacman Hardware/VanVanCar_MiST/rtl/sn76489/COPYING b/Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/rtl/sn76489/COPYING
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/VanVanCar_MiST/rtl/sn76489/COPYING
rename to Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/rtl/sn76489/COPYING
diff --git a/Arcade_MiST/Pacman Hardware/VanVanCar_MiST/rtl/sn76489/README b/Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/rtl/sn76489/README
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/VanVanCar_MiST/rtl/sn76489/README
rename to Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/rtl/sn76489/README
diff --git a/Arcade_MiST/Pacman Hardware/VanVanCar_MiST/rtl/sn76489/sn76489_attenuator.vhd b/Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/rtl/sn76489/sn76489_attenuator.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/VanVanCar_MiST/rtl/sn76489/sn76489_attenuator.vhd
rename to Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/rtl/sn76489/sn76489_attenuator.vhd
diff --git a/Arcade_MiST/Pacman Hardware/VanVanCar_MiST/rtl/sn76489/sn76489_clock_div.vhd b/Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/rtl/sn76489/sn76489_clock_div.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/VanVanCar_MiST/rtl/sn76489/sn76489_clock_div.vhd
rename to Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/rtl/sn76489/sn76489_clock_div.vhd
diff --git a/Arcade_MiST/Pacman Hardware/VanVanCar_MiST/rtl/sn76489/sn76489_latch_ctrl.vhd b/Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/rtl/sn76489/sn76489_latch_ctrl.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/VanVanCar_MiST/rtl/sn76489/sn76489_latch_ctrl.vhd
rename to Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/rtl/sn76489/sn76489_latch_ctrl.vhd
diff --git a/Arcade_MiST/Pacman Hardware/VanVanCar_MiST/rtl/sn76489/sn76489_noise.vhd b/Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/rtl/sn76489/sn76489_noise.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/VanVanCar_MiST/rtl/sn76489/sn76489_noise.vhd
rename to Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/rtl/sn76489/sn76489_noise.vhd
diff --git a/Arcade_MiST/Pacman Hardware/VanVanCar_MiST/rtl/sn76489/sn76489_tone.vhd b/Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/rtl/sn76489/sn76489_tone.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/VanVanCar_MiST/rtl/sn76489/sn76489_tone.vhd
rename to Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/rtl/sn76489/sn76489_tone.vhd
diff --git a/Arcade_MiST/Pacman Hardware/VanVanCar_MiST/rtl/sn76489/sn76489_top.vhd b/Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/rtl/sn76489/sn76489_top.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/VanVanCar_MiST/rtl/sn76489/sn76489_top.vhd
rename to Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/rtl/sn76489/sn76489_top.vhd
diff --git a/Arcade_MiST/Pacman Hardware/VanVanCar_MiST/rtl/vanvan.vhd b/Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/rtl/vanvan.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/VanVanCar_MiST/rtl/vanvan.vhd
rename to Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/rtl/vanvan.vhd
diff --git a/Arcade_MiST/Pacman Hardware/VanVanCar_MiST/rtl/vanvan_video.vhd b/Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/rtl/vanvan_video.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/VanVanCar_MiST/rtl/vanvan_video.vhd
rename to Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/rtl/vanvan_video.vhd
diff --git a/Arcade_MiST/Pacman Hardware/VanVanCar_MiST/rtl/vanvan_vram_addr.vhd b/Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/rtl/vanvan_vram_addr.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/VanVanCar_MiST/rtl/vanvan_vram_addr.vhd
rename to Arcade_MiST/Namco Pacman Hardware/VanVanCar_MiST/rtl/vanvan_vram_addr.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Woodpecker_MiST/README.txt b/Arcade_MiST/Namco Pacman Hardware/Woodpecker_MiST/README.txt
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Woodpecker_MiST/README.txt
rename to Arcade_MiST/Namco Pacman Hardware/Woodpecker_MiST/README.txt
diff --git a/Arcade_MiST/Pacman Hardware/Woodpecker_MiST/Woodpecker.qpf b/Arcade_MiST/Namco Pacman Hardware/Woodpecker_MiST/Woodpecker.qpf
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Woodpecker_MiST/Woodpecker.qpf
rename to Arcade_MiST/Namco Pacman Hardware/Woodpecker_MiST/Woodpecker.qpf
diff --git a/Arcade_MiST/Pacman Hardware/Woodpecker_MiST/Woodpecker.qsf b/Arcade_MiST/Namco Pacman Hardware/Woodpecker_MiST/Woodpecker.qsf
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Woodpecker_MiST/Woodpecker.qsf
rename to Arcade_MiST/Namco Pacman Hardware/Woodpecker_MiST/Woodpecker.qsf
diff --git a/Arcade_MiST/Pacman Hardware/Woodpecker_MiST/Woodpecker.sdc b/Arcade_MiST/Namco Pacman Hardware/Woodpecker_MiST/Woodpecker.sdc
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Woodpecker_MiST/Woodpecker.sdc
rename to Arcade_MiST/Namco Pacman Hardware/Woodpecker_MiST/Woodpecker.sdc
diff --git a/Arcade_MiST/Pacman Hardware/SuperGlob_MiST/clean.bat b/Arcade_MiST/Namco Pacman Hardware/Woodpecker_MiST/clean.bat
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/SuperGlob_MiST/clean.bat
rename to Arcade_MiST/Namco Pacman Hardware/Woodpecker_MiST/clean.bat
diff --git a/Arcade_MiST/Pacman Hardware/Woodpecker_MiST/rtl/ROM/GFX1.vhd b/Arcade_MiST/Namco Pacman Hardware/Woodpecker_MiST/rtl/ROM/GFX1.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Woodpecker_MiST/rtl/ROM/GFX1.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Woodpecker_MiST/rtl/ROM/GFX1.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Woodpecker_MiST/rtl/ROM/PROM1_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Woodpecker_MiST/rtl/ROM/PROM1_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Woodpecker_MiST/rtl/ROM/PROM1_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Woodpecker_MiST/rtl/ROM/PROM1_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Woodpecker_MiST/rtl/ROM/PROM3_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Woodpecker_MiST/rtl/ROM/PROM3_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Woodpecker_MiST/rtl/ROM/PROM3_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Woodpecker_MiST/rtl/ROM/PROM3_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Woodpecker_MiST/rtl/ROM/PROM4_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Woodpecker_MiST/rtl/ROM/PROM4_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Woodpecker_MiST/rtl/ROM/PROM4_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Woodpecker_MiST/rtl/ROM/PROM4_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Woodpecker_MiST/rtl/ROM/PROM7_DST.vhd b/Arcade_MiST/Namco Pacman Hardware/Woodpecker_MiST/rtl/ROM/PROM7_DST.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Woodpecker_MiST/rtl/ROM/PROM7_DST.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Woodpecker_MiST/rtl/ROM/PROM7_DST.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Woodpecker_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Namco Pacman Hardware/Woodpecker_MiST/rtl/ROM/ROM_PGM_0.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Woodpecker_MiST/rtl/ROM/ROM_PGM_0.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Woodpecker_MiST/rtl/ROM/ROM_PGM_0.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Woodpecker_MiST/rtl/ROM/ROM_PGM_1.vhd b/Arcade_MiST/Namco Pacman Hardware/Woodpecker_MiST/rtl/ROM/ROM_PGM_1.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Woodpecker_MiST/rtl/ROM/ROM_PGM_1.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Woodpecker_MiST/rtl/ROM/ROM_PGM_1.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Woodpecker_MiST/rtl/Woodpecker.sv b/Arcade_MiST/Namco Pacman Hardware/Woodpecker_MiST/rtl/Woodpecker.sv
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Woodpecker_MiST/rtl/Woodpecker.sv
rename to Arcade_MiST/Namco Pacman Hardware/Woodpecker_MiST/rtl/Woodpecker.sv
diff --git a/Arcade_MiST/Pacman Hardware/Ponpoko_MiST/rtl/build_id.tcl b/Arcade_MiST/Namco Pacman Hardware/Woodpecker_MiST/rtl/build_id.tcl
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Ponpoko_MiST/rtl/build_id.tcl
rename to Arcade_MiST/Namco Pacman Hardware/Woodpecker_MiST/rtl/build_id.tcl
diff --git a/Arcade_MiST/Pacman Hardware/Woodpecker_MiST/rtl/dpram.vhd b/Arcade_MiST/Namco Pacman Hardware/Woodpecker_MiST/rtl/dpram.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Woodpecker_MiST/rtl/dpram.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Woodpecker_MiST/rtl/dpram.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Woodpecker_MiST/rtl/pacman.vhd b/Arcade_MiST/Namco Pacman Hardware/Woodpecker_MiST/rtl/pacman.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Woodpecker_MiST/rtl/pacman.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Woodpecker_MiST/rtl/pacman.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Woodpecker_MiST/rtl/pacman_audio.vhd b/Arcade_MiST/Namco Pacman Hardware/Woodpecker_MiST/rtl/pacman_audio.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Woodpecker_MiST/rtl/pacman_audio.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Woodpecker_MiST/rtl/pacman_audio.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Woodpecker_MiST/rtl/pacman_video.vhd b/Arcade_MiST/Namco Pacman Hardware/Woodpecker_MiST/rtl/pacman_video.vhd
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Woodpecker_MiST/rtl/pacman_video.vhd
rename to Arcade_MiST/Namco Pacman Hardware/Woodpecker_MiST/rtl/pacman_video.vhd
diff --git a/Arcade_MiST/Pacman Hardware/Pacman_MiST/rtl/pll.qip b/Arcade_MiST/Namco Pacman Hardware/Woodpecker_MiST/rtl/pll.qip
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Pacman_MiST/rtl/pll.qip
rename to Arcade_MiST/Namco Pacman Hardware/Woodpecker_MiST/rtl/pll.qip
diff --git a/Arcade_MiST/Pacman Hardware/Woodpecker_MiST/rtl/pll.v b/Arcade_MiST/Namco Pacman Hardware/Woodpecker_MiST/rtl/pll.v
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Woodpecker_MiST/rtl/pll.v
rename to Arcade_MiST/Namco Pacman Hardware/Woodpecker_MiST/rtl/pll.v
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/RallyX.srf b/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/RallyX.srf
deleted file mode 100644
index 8b5f796f..00000000
--- a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/RallyX.srf	
+++ /dev/null
@@ -1,55 +0,0 @@
-{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Found combinational loop of 47 nodes" {  } {  } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." {  } {  } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" {  } {  } 0 12110 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" {  } {  } 0 332043 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 169085 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 174073 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 13009 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 10230 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 10235 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 332060 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 10296 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_cvo_mode_banks" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_pll.sv" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_common_frame_counter.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_ldc.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "genlock_enable_sync" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "u_calculate_mode" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "genlock_enable" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "reset_value" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_cvo_core.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_packet_transfer.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "RST" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_scaler_alg_core" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "cvo_core" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "vip_HPS_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_dil_scheduler.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
diff --git a/Arcade_MiST/Namco Rally X Hardware/ReadMe.txt b/Arcade_MiST/Namco Rally X Hardware/ReadMe.txt
deleted file mode 100644
index 990c1c2c..00000000
--- a/Arcade_MiST/Namco Rally X Hardware/ReadMe.txt	
+++ /dev/null
@@ -1 +0,0 @@
-Need Schematics
\ No newline at end of file
diff --git a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/README.txt b/Arcade_MiST/Namco Rally X Hardware/Test_MiST/README.txt
deleted file mode 100644
index ecd31ab0..00000000
--- a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/README.txt	
+++ /dev/null
@@ -1,16 +0,0 @@
----------------------------------------------------------------------------------
--- 
--- Arcade: Rally-X  port to MiST
--- 19 September 2019
--- From: https://github.com/MrX-8B/MiSTer-Arcade-RallyX
--- 
-
----------------------------------------------------------------------------------
--- FPGA New Rally-X for Spartan-3 Starter Board
-------------------------------------------------
--- Copyright (c) 2005 MiSTer-X
----------------------------------------------------------------------------------
--- T80/T80s - Version : 0242
------------------------------
--- Z80 compatible microprocessor core
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
\ No newline at end of file
diff --git a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/RallyX.qpf b/Arcade_MiST/Namco Rally X Hardware/Test_MiST/RallyX.qpf
deleted file mode 100644
index 1c259ca0..00000000
--- a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/RallyX.qpf	
+++ /dev/null
@@ -1,31 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2017  Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Intel Program License 
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel MegaCore Function License Agreement, or other 
-# applicable license agreement, including, without limitation, 
-# that your use is for the sole purpose of programming logic 
-# devices manufactured by Intel and sold by Intel or its 
-# authorized distributors.  Please refer to the applicable 
-# agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition
-# Date created = 04:04:47  October 16, 2017
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "17.0"
-DATE = "04:04:47  October 16, 2017"
-
-# Revisions
-
-PROJECT_REVISION = "RallyX"
diff --git a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/RallyX.qsf b/Arcade_MiST/Namco Rally X Hardware/Test_MiST/RallyX.qsf
deleted file mode 100644
index d75bc85c..00000000
--- a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/RallyX.qsf	
+++ /dev/null
@@ -1,167 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2014 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
-# Date created = 16:37:48  September 22, 2019
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-#		RallyX_assignment_defaults.qdf
-#    If this file doesn't exist, see file:
-#		assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-#    file is updated automatically by the Quartus II software
-#    and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-
-# Project-Wide Assignments
-# ========================
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30  APRIL 20, 2017"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
-set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-
-# Pin & Location Assignments
-# ==========================
-set_location_assignment PIN_7 -to LED
-set_location_assignment PIN_54 -to CLOCK_27
-set_location_assignment PIN_144 -to VGA_R[5]
-set_location_assignment PIN_143 -to VGA_R[4]
-set_location_assignment PIN_142 -to VGA_R[3]
-set_location_assignment PIN_141 -to VGA_R[2]
-set_location_assignment PIN_137 -to VGA_R[1]
-set_location_assignment PIN_135 -to VGA_R[0]
-set_location_assignment PIN_133 -to VGA_B[5]
-set_location_assignment PIN_132 -to VGA_B[4]
-set_location_assignment PIN_125 -to VGA_B[3]
-set_location_assignment PIN_121 -to VGA_B[2]
-set_location_assignment PIN_120 -to VGA_B[1]
-set_location_assignment PIN_115 -to VGA_B[0]
-set_location_assignment PIN_114 -to VGA_G[5]
-set_location_assignment PIN_113 -to VGA_G[4]
-set_location_assignment PIN_112 -to VGA_G[3]
-set_location_assignment PIN_111 -to VGA_G[2]
-set_location_assignment PIN_110 -to VGA_G[1]
-set_location_assignment PIN_106 -to VGA_G[0]
-set_location_assignment PIN_136 -to VGA_VS
-set_location_assignment PIN_119 -to VGA_HS
-set_location_assignment PIN_65 -to AUDIO_L
-set_location_assignment PIN_80 -to AUDIO_R
-set_location_assignment PIN_105 -to SPI_DO
-set_location_assignment PIN_88 -to SPI_DI
-set_location_assignment PIN_126 -to SPI_SCK
-set_location_assignment PIN_127 -to SPI_SS2
-set_location_assignment PIN_91 -to SPI_SS3
-set_location_assignment PIN_13 -to CONF_DATA0
-set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
-
-# Classic Timing Assignments
-# ==========================
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-
-# Analysis & Synthesis Assignments
-# ================================
-set_global_assignment -name FAMILY "Cyclone III"
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
-set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
-set_global_assignment -name TOP_LEVEL_ENTITY rallyX_mist
-
-# Fitter Assignments
-# ==================
-set_global_assignment -name DEVICE EP3C25E144C8
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
-set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
-set_global_assignment -name ENABLE_NCE_PIN OFF
-set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
-set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
-set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
-
-# Assembler Assignments
-# =====================
-set_global_assignment -name GENERATE_RBF_FILE ON
-set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
-
-# Power Estimation Assignments
-# ============================
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-
-# Advanced I/O Timing Assignments
-# ===============================
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
-
-# -------------------------
-# start ENTITY(rallyX_mist)
-
-	# start DESIGN_PARTITION(Top)
-	# ---------------------------
-
-		# Incremental Compilation Assignments
-		# ===================================
-		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-
-	# end DESIGN_PARTITION(Top)
-	# -------------------------
-
-# end ENTITY(rallyX_mist)
-# -----------------------
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/rallyX_mist.sv
-set_global_assignment -name VERILOG_FILE rtl/fpga_nrx.v
-set_global_assignment -name VERILOG_FILE rtl/nrx_video.v
-set_global_assignment -name VERILOG_FILE rtl/nrx_hvgen.v
-set_global_assignment -name VERILOG_FILE rtl/nrx_sprite.v
-set_global_assignment -name VERILOG_FILE rtl/nrx_psg_voice.v
-set_global_assignment -name VERILOG_FILE rtl/nrx_namco.v
-set_global_assignment -name VHDL_FILE rtl/roms/jng_snd_rom.vhd
-set_global_assignment -name VHDL_FILE rtl/roms/jng_prg_rom.vhd
-set_global_assignment -name VHDL_FILE rtl/roms/jng_pal_rom.vhd
-set_global_assignment -name VHDL_FILE rtl/roms/jng_dot_rom.vhd
-set_global_assignment -name VHDL_FILE rtl/roms/jng_col_rom.vhd
-set_global_assignment -name VHDL_FILE rtl/roms/jng_chr_rom.vhd
-set_global_assignment -name VERILOG_FILE rtl/rams.v
-set_global_assignment -name VERILOG_FILE rtl/pll.v
-set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
-set_global_assignment -name VHDL_FILE rtl/dpram.vhd
-set_global_assignment -name VHDL_FILE rtl/time_pilot_sound_board.vhd
-set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
-set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd
-set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/RallyX.srf b/Arcade_MiST/Namco Rally X Hardware/Test_MiST/RallyX.srf
deleted file mode 100644
index 8b5f796f..00000000
--- a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/RallyX.srf	
+++ /dev/null
@@ -1,55 +0,0 @@
-{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Found combinational loop of 47 nodes" {  } {  } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." {  } {  } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" {  } {  } 0 12110 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" {  } {  } 0 332043 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 169085 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 174073 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 13009 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 10230 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 10235 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 332060 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 10296 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_cvo_mode_banks" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_pll.sv" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_common_frame_counter.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_ldc.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "genlock_enable_sync" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "u_calculate_mode" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "genlock_enable" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "reset_value" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_cvo_core.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_packet_transfer.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "RST" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_scaler_alg_core" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "cvo_core" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "vip_HPS_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_dil_scheduler.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
diff --git a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/T80/T80.vhd
deleted file mode 100644
index 398fa0df..00000000
--- a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/T80/T80.vhd	
+++ /dev/null
@@ -1,1073 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0208 : First complete release
---
---	0210 : Fixed wait and halt
---
---	0211 : Fixed Refresh addition and IM 1
---
---	0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---	0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
---	0235 : Added clock enable and IM 2 fix by Mike Johnson
---
---	0237 : Changed 8080 I/O address output, added IntE output
---
---	0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
---	0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
---	0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
---	0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
-	generic(
-		Mode : integer := 0;	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait : integer := 0;	-- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		RESET_n		: in std_logic;
-		CLK_n		: in std_logic;
-		CEN			: in std_logic;
-		WAIT_n		: in std_logic;
-		INT_n		: in std_logic;
-		NMI_n		: in std_logic;
-		BUSRQ_n		: in std_logic;
-		M1_n		: out std_logic;
-		IORQ		: out std_logic;
-		NoRead		: out std_logic;
-		Write		: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
-		DInst		: in std_logic_vector(7 downto 0);
-		DI			: in std_logic_vector(7 downto 0);
-		DO			: out std_logic_vector(7 downto 0);
-		MC			: out std_logic_vector(2 downto 0);
-		TS			: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE		: out std_logic;
-		Stop		: out std_logic
-	);
-end T80;
-
-architecture rtl of T80 is
-
-	constant aNone	: std_logic_vector(2 downto 0) := "111";
-	constant aBC	: std_logic_vector(2 downto 0) := "000";
-	constant aDE	: std_logic_vector(2 downto 0) := "001";
-	constant aXY	: std_logic_vector(2 downto 0) := "010";
-	constant aIOA	: std_logic_vector(2 downto 0) := "100";
-	constant aSP	: std_logic_vector(2 downto 0) := "101";
-	constant aZI	: std_logic_vector(2 downto 0) := "110";
-
-	-- Registers
-	signal ACC, F			: std_logic_vector(7 downto 0);
-	signal Ap, Fp			: std_logic_vector(7 downto 0);
-	signal I				: std_logic_vector(7 downto 0);
-	signal R				: unsigned(7 downto 0);
-	signal SP, PC			: unsigned(15 downto 0);
-	signal RegDIH			: std_logic_vector(7 downto 0);
-	signal RegDIL			: std_logic_vector(7 downto 0);
-	signal RegBusA			: std_logic_vector(15 downto 0);
-	signal RegBusB			: std_logic_vector(15 downto 0);
-	signal RegBusC			: std_logic_vector(15 downto 0);
-	signal RegAddrA_r		: std_logic_vector(2 downto 0);
-	signal RegAddrA			: std_logic_vector(2 downto 0);
-	signal RegAddrB_r		: std_logic_vector(2 downto 0);
-	signal RegAddrB			: std_logic_vector(2 downto 0);
-	signal RegAddrC			: std_logic_vector(2 downto 0);
-	signal RegWEH			: std_logic;
-	signal RegWEL			: std_logic;
-	signal Alternate		: std_logic;
-
-	-- Help Registers
-	signal TmpAddr			: std_logic_vector(15 downto 0);	-- Temporary address register
-	signal IR				: std_logic_vector(7 downto 0);		-- Instruction register
-	signal ISet				: std_logic_vector(1 downto 0);		-- Instruction set selector
-	signal RegBusA_r		: std_logic_vector(15 downto 0);
-
-	signal ID16				: signed(15 downto 0);
-	signal Save_Mux			: std_logic_vector(7 downto 0);
-
-	signal TState			: unsigned(2 downto 0);
-	signal MCycle			: std_logic_vector(2 downto 0);
-	signal IntE_FF1			: std_logic;
-	signal IntE_FF2			: std_logic;
-	signal Halt_FF			: std_logic;
-	signal BusReq_s			: std_logic;
-	signal BusAck			: std_logic;
-	signal ClkEn			: std_logic;
-	signal NMI_s			: std_logic;
-	signal INT_s			: std_logic;
-	signal IStatus			: std_logic_vector(1 downto 0);
-
-	signal DI_Reg			: std_logic_vector(7 downto 0);
-	signal T_Res			: std_logic;
-	signal XY_State			: std_logic_vector(1 downto 0);
-	signal Pre_XY_F_M		: std_logic_vector(2 downto 0);
-	signal NextIs_XY_Fetch	: std_logic;
-	signal XY_Ind			: std_logic;
-	signal No_BTR			: std_logic;
-	signal BTR_r			: std_logic;
-	signal Auto_Wait		: std_logic;
-	signal Auto_Wait_t1		: std_logic;
-	signal Auto_Wait_t2		: std_logic;
-	signal IncDecZ			: std_logic;
-
-	-- ALU signals
-	signal BusB				: std_logic_vector(7 downto 0);
-	signal BusA				: std_logic_vector(7 downto 0);
-	signal ALU_Q			: std_logic_vector(7 downto 0);
-	signal F_Out			: std_logic_vector(7 downto 0);
-
-	-- Registered micro code outputs
-	signal Read_To_Reg_r	: std_logic_vector(4 downto 0);
-	signal Arith16_r		: std_logic;
-	signal Z16_r			: std_logic;
-	signal ALU_Op_r			: std_logic_vector(3 downto 0);
-	signal Save_ALU_r		: std_logic;
-	signal PreserveC_r		: std_logic;
-	signal MCycles			: std_logic_vector(2 downto 0);
-
-	-- Micro code outputs
-	signal MCycles_d		: std_logic_vector(2 downto 0);
-	signal TStates			: std_logic_vector(2 downto 0);
-	signal IntCycle			: std_logic;
-	signal NMICycle			: std_logic;
-	signal Inc_PC			: std_logic;
-	signal Inc_WZ			: std_logic;
-	signal IncDec_16		: std_logic_vector(3 downto 0);
-	signal Prefix			: std_logic_vector(1 downto 0);
-	signal Read_To_Acc		: std_logic;
-	signal Read_To_Reg		: std_logic;
-	signal Set_BusB_To		: std_logic_vector(3 downto 0);
-	signal Set_BusA_To		: std_logic_vector(3 downto 0);
-	signal ALU_Op			: std_logic_vector(3 downto 0);
-	signal Save_ALU			: std_logic;
-	signal PreserveC		: std_logic;
-	signal Arith16			: std_logic;
-	signal Set_Addr_To		: std_logic_vector(2 downto 0);
-	signal Jump				: std_logic;
-	signal JumpE			: std_logic;
-	signal JumpXY			: std_logic;
-	signal Call				: std_logic;
-	signal RstP				: std_logic;
-	signal LDZ				: std_logic;
-	signal LDW				: std_logic;
-	signal LDSPHL			: std_logic;
-	signal IORQ_i			: std_logic;
-	signal Special_LD		: std_logic_vector(2 downto 0);
-	signal ExchangeDH		: std_logic;
-	signal ExchangeRp		: std_logic;
-	signal ExchangeAF		: std_logic;
-	signal ExchangeRS		: std_logic;
-	signal I_DJNZ			: std_logic;
-	signal I_CPL			: std_logic;
-	signal I_CCF			: std_logic;
-	signal I_SCF			: std_logic;
-	signal I_RETN			: std_logic;
-	signal I_BT				: std_logic;
-	signal I_BC				: std_logic;
-	signal I_BTR			: std_logic;
-	signal I_RLD			: std_logic;
-	signal I_RRD			: std_logic;
-	signal I_INRC			: std_logic;
-	signal SetDI			: std_logic;
-	signal SetEI			: std_logic;
-	signal IMode			: std_logic_vector(1 downto 0);
-	signal Halt				: std_logic;
-
-begin
-
-	mcode : T80_MCode
-		generic map(
-			Mode => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			IR => IR,
-			ISet => ISet,
-			MCycle => MCycle,
-			F => F,
-			NMICycle => NMICycle,
-			IntCycle => IntCycle,
-			MCycles => MCycles_d,
-			TStates => TStates,
-			Prefix => Prefix,
-			Inc_PC => Inc_PC,
-			Inc_WZ => Inc_WZ,
-			IncDec_16 => IncDec_16,
-			Read_To_Acc => Read_To_Acc,
-			Read_To_Reg => Read_To_Reg,
-			Set_BusB_To => Set_BusB_To,
-			Set_BusA_To => Set_BusA_To,
-			ALU_Op => ALU_Op,
-			Save_ALU => Save_ALU,
-			PreserveC => PreserveC,
-			Arith16 => Arith16,
-			Set_Addr_To => Set_Addr_To,
-			IORQ => IORQ_i,
-			Jump => Jump,
-			JumpE => JumpE,
-			JumpXY => JumpXY,
-			Call => Call,
-			RstP => RstP,
-			LDZ => LDZ,
-			LDW => LDW,
-			LDSPHL => LDSPHL,
-			Special_LD => Special_LD,
-			ExchangeDH => ExchangeDH,
-			ExchangeRp => ExchangeRp,
-			ExchangeAF => ExchangeAF,
-			ExchangeRS => ExchangeRS,
-			I_DJNZ => I_DJNZ,
-			I_CPL => I_CPL,
-			I_CCF => I_CCF,
-			I_SCF => I_SCF,
-			I_RETN => I_RETN,
-			I_BT => I_BT,
-			I_BC => I_BC,
-			I_BTR => I_BTR,
-			I_RLD => I_RLD,
-			I_RRD => I_RRD,
-			I_INRC => I_INRC,
-			SetDI => SetDI,
-			SetEI => SetEI,
-			IMode => IMode,
-			Halt => Halt,
-			NoRead => NoRead,
-			Write => Write);
-
-	alu : T80_ALU
-		generic map(
-			Mode => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			Arith16 => Arith16_r,
-			Z16 => Z16_r,
-			ALU_Op => ALU_Op_r,
-			IR => IR(5 downto 0),
-			ISet => ISet,
-			BusA => BusA,
-			BusB => BusB,
-			F_In => F,
-			Q => ALU_Q,
-			F_Out => F_Out);
-
-	ClkEn <= CEN and not BusAck;
-
-	T_Res <= '1' when TState = unsigned(TStates) else '0';
-
-	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
-							((Set_Addr_To = aXY) or
-							(MCycle = "001" and IR = "11001011") or
-							(MCycle = "001" and IR = "00110110")) else '0';
-
-	Save_Mux <= BusB when ExchangeRp = '1' else
-		DI_Reg when Save_ALU_r = '0' else
-		ALU_Q;
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			PC <= (others => '0');  -- Program Counter
-			A <= (others => '0');
-			TmpAddr <= (others => '0');
-			IR <= "00000000";
-			ISet <= "00";
-			XY_State <= "00";
-			IStatus <= "00";
-			MCycles <= "000";
-			DO <= "00000000";
-
-			ACC <= (others => '1');
-			F <= (others => '1');
-			Ap <= (others => '1');
-			Fp <= (others => '1');
-			I <= (others => '0');
-			R <= (others => '0');
-			SP <= (others => '1');
-			Alternate <= '0';
-
-			Read_To_Reg_r <= "00000";
-			F <= (others => '1');
-			Arith16_r <= '0';
-			BTR_r <= '0';
-			Z16_r <= '0';
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			PreserveC_r <= '0';
-			XY_Ind <= '0';
-
-		elsif CLK_n'event and CLK_n = '1' then
-
-			if ClkEn = '1' then
-
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			Read_To_Reg_r <= "00000";
-
-			MCycles <= MCycles_d;
-
-			if IMode /= "11" then
-				IStatus <= IMode;
-			end if;
-
-			Arith16_r <= Arith16;
-			PreserveC_r <= PreserveC;
-			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
-				Z16_r <= '1';
-			else
-				Z16_r <= '0';
-			end if;
-
-			if MCycle  = "001" and TState(2) = '0' then
-			-- MCycle = 1 and TState = 1, 2, or 3
-
-				if TState = 2 and Wait_n = '1' then
-					if Mode < 2 then
-						A(7 downto 0) <= std_logic_vector(R);
-						A(15 downto 8) <= I;
-						R(6 downto 0) <= R(6 downto 0) + 1;
-					end if;
-
-					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
-						PC <= PC + 1;
-					end if;
-
-					if IntCycle = '1' and IStatus = "01" then
-						IR <= "11111111";
-					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
-						IR <= "00000000";
-					else
-						IR <= DInst;
-					end if;
-
-					ISet <= "00";
-					if Prefix /= "00" then
-						if Prefix = "11" then
-							if IR(5) = '1' then
-								XY_State <= "10";
-							else
-								XY_State <= "01";
-							end if;
-						else
-							if Prefix = "10" then
-								XY_State <= "00";
-								XY_Ind <= '0';
-							end if;
-							ISet <= Prefix;
-						end if;
-					else
-						XY_State <= "00";
-						XY_Ind <= '0';
-					end if;
-				end if;
-
-			else
-			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
-				if MCycle = "110" then
-					XY_Ind <= '1';
-					if Prefix = "01" then
-						ISet <= "01";
-					end if;
-				end if;
-
-				if T_Res = '1' then
-					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
-					if Jump = '1' then
-						A(15 downto 8) <= DI_Reg;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(DI_Reg);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					elsif JumpXY = '1' then
-						A <= RegBusC;
-						PC <= unsigned(RegBusC);
-					elsif Call = '1' or RstP = '1' then
-						A <= TmpAddr;
-						PC <= unsigned(TmpAddr);
-					elsif MCycle = MCycles and NMICycle = '1' then
-						A <= "0000000001100110";
-						PC <= "0000000001100110";
-					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
-						A(15 downto 8) <= I;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(I);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					else
-						case Set_Addr_To is
-						when aXY =>
-							if XY_State = "00" then
-								A <= RegBusC;
-							else
-								if NextIs_XY_Fetch = '1' then
-									A <= std_logic_vector(PC);
-								else
-									A <= TmpAddr;
-								end if;
-							end if;
-						when aIOA =>
-							if Mode = 3 then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-							elsif Mode = 2 then
-								-- Duplicate I/O address on 8080
-								A(15 downto 8) <= DI_Reg;
-							else
-								A(15 downto 8) <= ACC;
-							end if;
-							A(7 downto 0) <= DI_Reg;
-						when aSP =>
-							A <= std_logic_vector(SP);
-						when aBC =>
-							if Mode = 3 and IORQ_i = '1' then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-								A(7 downto 0) <= RegBusC(7 downto 0);
-							else
-								A <= RegBusC;
-							end if;
-						when aDE =>
-							A <= RegBusC;
-						when aZI =>
-							if Inc_WZ = '1' then
-								A <= std_logic_vector(unsigned(TmpAddr) + 1);
-							else
-								A(15 downto 8) <= DI_Reg;
-								A(7 downto 0) <= TmpAddr(7 downto 0);
-							end if;
-						when others =>
-							A <= std_logic_vector(PC);
-						end case;
-					end if;
-
-					Save_ALU_r <= Save_ALU;
-					ALU_Op_r <= ALU_Op;
-
-					if I_CPL = '1' then
-						-- CPL
-						ACC <= not ACC;
-						F(Flag_Y) <= not ACC(5);
-						F(Flag_H) <= '1';
-						F(Flag_X) <= not ACC(3);
-						F(Flag_N) <= '1';
-					end if;
-					if I_CCF = '1' then
-						-- CCF
-						F(Flag_C) <= not F(Flag_C);
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= F(Flag_C);
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-					if I_SCF = '1' then
-						-- SCF
-						F(Flag_C) <= '1';
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= '0';
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-				end if;
-
-				if TState = 2 and Wait_n = '1' then
-					if ISet = "01" and MCycle = "111" then
-						IR <= DInst;
-					end if;
-					if JumpE = '1' then
-						PC <= unsigned(signed(PC) + signed(DI_Reg));
-					elsif Inc_PC = '1' then
-						PC <= PC + 1;
-					end if;
-					if BTR_r = '1' then
-						PC <= PC - 2;
-					end if;
-					if RstP = '1' then
-						TmpAddr <= (others =>'0');
-						TmpAddr(5 downto 3) <= IR(5 downto 3);
-					end if;
-				end if;
-				if TState = 3 and MCycle = "110" then
-					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
-				end if;
-
-				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
-					if IncDec_16(2 downto 0) = "111" then
-						if IncDec_16(3) = '1' then
-							SP <= SP - 1;
-						else
-							SP <= SP + 1;
-						end if;
-					end if;
-				end if;
-
-				if LDSPHL = '1' then
-					SP <= unsigned(RegBusC);
-				end if;
-				if ExchangeAF = '1' then
-					Ap <= ACC;
-					ACC <= Ap;
-					Fp <= F;
-					F <= Fp;
-				end if;
-				if ExchangeRS = '1' then
-					Alternate <= not Alternate;
-				end if;
-			end if;
-
-			if TState = 3 then
-				if LDZ = '1' then
-					TmpAddr(7 downto 0) <= DI_Reg;
-				end if;
-				if LDW = '1' then
-					TmpAddr(15 downto 8) <= DI_Reg;
-				end if;
-
-				if Special_LD(2) = '1' then
-					case Special_LD(1 downto 0) is
-					when "00" =>
-						ACC <= I;
-						F(Flag_P) <= IntE_FF2;
-					when "01" =>
-						ACC <= std_logic_vector(R);
-						F(Flag_P) <= IntE_FF2;
-					when "10" =>
-						I <= ACC;
-					when others =>
-						R <= unsigned(ACC);
-					end case;
-				end if;
-			end if;
-
-			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
-				if Mode = 3 then
-					F(6) <= F_Out(6);
-					F(5) <= F_Out(5);
-					F(7) <= F_Out(7);
-					if PreserveC_r = '0' then
-						F(4) <= F_Out(4);
-					end if;
-				else
-					F(7 downto 1) <= F_Out(7 downto 1);
-					if PreserveC_r = '0' then
-						F(Flag_C) <= F_Out(0);
-					end if;
-				end if;
-			end if;
-			if T_Res = '1' and I_INRC = '1' then
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-				if DI_Reg(7 downto 0) = "00000000" then
-					F(Flag_Z) <= '1';
-				else
-					F(Flag_Z) <= '0';
-				end if;
-				F(Flag_S) <= DI_Reg(7);
-				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
-					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
-			end if;
-
-			if TState = 1 and Auto_Wait_t1 = '0' then
-				DO <= BusB;
-				if I_RLD = '1' then
-					DO(3 downto 0) <= BusA(3 downto 0);
-					DO(7 downto 4) <= BusB(3 downto 0);
-				end if;
-				if I_RRD = '1' then
-					DO(3 downto 0) <= BusB(7 downto 4);
-					DO(7 downto 4) <= BusA(3 downto 0);
-				end if;
-			end if;
-
-			if T_Res = '1' then
-				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
-				Read_To_Reg_r(4) <= Read_To_Reg;
-				if Read_To_Acc = '1' then
-					Read_To_Reg_r(3 downto 0) <= "0111";
-					Read_To_Reg_r(4) <= '1';
-				end if;
-			end if;
-
-			if TState = 1 and I_BT = '1' then
-				F(Flag_X) <= ALU_Q(3);
-				F(Flag_Y) <= ALU_Q(1);
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-			end if;
-			if I_BC = '1' or I_BT = '1' then
-				F(Flag_P) <= IncDecZ;
-			end if;
-
-			if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or
-				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-				case Read_To_Reg_r is
-				when "10111" =>
-					ACC <= Save_Mux;
-				when "10110" =>
-					DO <= Save_Mux;
-				when "11000" =>
-					SP(7 downto 0) <= unsigned(Save_Mux);
-				when "11001" =>
-					SP(15 downto 8) <= unsigned(Save_Mux);
-				when "11011" =>
-					F <= Save_Mux;
-				when others =>
-				end case;
-			end if;
-
-		end if;
-
-		end if;
-
-	end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-				-- Bus A / Write
-				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
-					RegAddrA_r <= XY_State(1) & "11";
-				end if;
-
-				-- Bus B
-				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
-					RegAddrB_r <= XY_State(1) & "11";
-				end if;
-
-				-- Address from register
-				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-				-- Jump (HL), LD SP,HL
-				if (JumpXY = '1' or LDSPHL = '1') then
-					RegAddrC <= Alternate & "10";
-				end if;
-				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
-					RegAddrC <= XY_State(1) & "11";
-				end if;
-
-				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
-					IncDecZ <= F_Out(Flag_Z);
-				end if;
-				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
-					if ID16 = 0 then
-						IncDecZ <= '0';
-					else
-						IncDecZ <= '1';
-					end if;
-				end if;
-
-				RegBusA_r <= RegBusA;
-			end if;
-		end if;
-	end process;
-
-	RegAddrA <=
-			-- 16 bit increment/decrement
-			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
-			XY_State(1) & "11" when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-			-- EX HL,DL
-			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
-			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-			-- Bus A / Write
-			RegAddrA_r;
-
-	RegAddrB <=
-			-- EX HL,DL
-			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-			-- Bus B
-			RegAddrB_r;
-
-	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
-			signed(RegBusA) + 1;
-
-	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegWEH <= '0';
-		RegWEL <= '0';
-		if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or
-			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-			case Read_To_Reg_r is
-			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
-				RegWEH <= not Read_To_Reg_r(0);
-				RegWEL <= Read_To_Reg_r(0);
-			when others =>
-			end case;
-		end if;
-
-		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
-			RegWEH <= '1';
-			RegWEL <= '1';
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			case IncDec_16(1 downto 0) is
-			when "00" | "01" | "10" =>
-				RegWEH <= '1';
-				RegWEL <= '1';
-			when others =>
-			end case;
-		end if;
-	end process;
-
-	process (Save_Mux, RegBusB, RegBusA_r, ID16,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegDIH <= Save_Mux;
-		RegDIL <= Save_Mux;
-
-		if ExchangeDH = '1' and TState = 3 then
-			RegDIH <= RegBusB(15 downto 8);
-			RegDIL <= RegBusB(7 downto 0);
-		end if;
-		if ExchangeDH = '1' and TState = 4 then
-			RegDIH <= RegBusA_r(15 downto 8);
-			RegDIL <= RegBusA_r(7 downto 0);
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			RegDIH <= std_logic_vector(ID16(15 downto 8));
-			RegDIL <= std_logic_vector(ID16(7 downto 0));
-		end if;
-	end process;
-
-	Regs : T80_Reg
-		port map(
-			Clk => CLK_n,
-			CEN => ClkEn,
-			WEH => RegWEH,
-			WEL => RegWEL,
-			AddrA => RegAddrA,
-			AddrB => RegAddrB,
-			AddrC => RegAddrC,
-			DIH => RegDIH,
-			DIL => RegDIL,
-			DOAH => RegBusA(15 downto 8),
-			DOAL => RegBusA(7 downto 0),
-			DOBH => RegBusB(15 downto 8),
-			DOBL => RegBusB(7 downto 0),
-			DOCH => RegBusC(15 downto 8),
-			DOCL => RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-			case Set_BusB_To is
-			when "0111" =>
-				BusB <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusB_To(0) = '1' then
-					BusB <= RegBusB(7 downto 0);
-				else
-					BusB <= RegBusB(15 downto 8);
-				end if;
-			when "0110" =>
-				BusB <= DI_Reg;
-			when "1000" =>
-				BusB <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusB <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusB <= "00000001";
-			when "1011" =>
-				BusB <= F;
-			when "1100" =>
-				BusB <= std_logic_vector(PC(7 downto 0));
-			when "1101" =>
-				BusB <= std_logic_vector(PC(15 downto 8));
-			when "1110" =>
-				BusB <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-
-			case Set_BusA_To is
-			when "0111" =>
-				BusA <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusA_To(0) = '1' then
-					BusA <= RegBusA(7 downto 0);
-				else
-					BusA <= RegBusA(15 downto 8);
-				end if;
-			when "0110" =>
-				BusA <= DI_Reg;
-			when "1000" =>
-				BusA <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusA <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusA <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-			end if;
-		end if;
-	end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
-	process (RESET_n,CLK_n)
-	begin
-		if RESET_n = '0' then
-			RFSH_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
-				RFSH_n <= '0';
-			else
-				RFSH_n <= '1';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	MC <= std_logic_vector(MCycle);
-	TS <= std_logic_vector(TState);
-	DI_Reg <= DI;
-	HALT_n <= not Halt_FF;
-	BUSAK_n <= not BusAck;
-	IntCycle_n <= not IntCycle;
-	IntE <= IntE_FF1;
-	IORQ <= IORQ_i;
-	Stop <= I_DJNZ;
-
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-		variable OldNMI_n : std_logic;
-	begin
-		if RESET_n = '0' then
-			BusReq_s <= '0';
-			INT_s <= '0';
-			NMI_s <= '0';
-			OldNMI_n := '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			BusReq_s <= not BUSRQ_n;
-			INT_s <= not INT_n;
-			if NMICycle = '1' then
-				NMI_s <= '0';
-			elsif NMI_n = '0' and OldNMI_n = '1' then
-				NMI_s <= '1';
-			end if;
-			OldNMI_n := NMI_n;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			MCycle <= "001";
-			TState <= "000";
-			Pre_XY_F_M <= "000";
-			Halt_FF <= '0';
-			BusAck <= '0';
-			NMICycle <= '0';
-			IntCycle <= '0';
-			IntE_FF1 <= '0';
-			IntE_FF2 <= '0';
-			No_BTR <= '0';
-			Auto_Wait_t1 <= '0';
-			Auto_Wait_t2 <= '0';
-			M1_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			if T_Res = '1' then
-				Auto_Wait_t1 <= '0';
-			else
-				Auto_Wait_t1 <= Auto_Wait or IORQ_i;
-			end if;
-			Auto_Wait_t2 <= Auto_Wait_t1;
-			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
-					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
-					(I_BTR and (not IR(4) or F(Flag_Z)));
-			if TState = 2 then
-				if SetEI = '1' then
-					IntE_FF1 <= '1';
-					IntE_FF2 <= '1';
-				end if;
-				if I_RETN = '1' then
-					IntE_FF1 <= IntE_FF2;
-				end if;
-			end if;
-			if TState = 3 then
-				if SetDI = '1' then
-					IntE_FF1 <= '0';
-					IntE_FF2 <= '0';
-				end if;
-			end if;
-			if IntCycle = '1' or NMICycle = '1' then
-				Halt_FF <= '0';
-			end if;
-			if MCycle = "001" and TState = 2 and Wait_n = '1' then
-				M1_n <= '1';
-			end if;
-			if BusReq_s = '1' and BusAck = '1' then
-			else
-				BusAck <= '0';
-				if TState = 2 and Wait_n = '0' then
-				elsif T_Res = '1' then
-					if Halt = '1' then
-						Halt_FF <= '1';
-					end if;
-					if BusReq_s = '1' then
-						BusAck <= '1';
-					else
-						TState <= "001";
-						if NextIs_XY_Fetch = '1' then
-							MCycle <= "110";
-							Pre_XY_F_M <= MCycle;
-							if IR = "00110110" and Mode = 0 then
-								Pre_XY_F_M <= "010";
-							end if;
-						elsif (MCycle = "111") or
-							(MCycle = "110" and Mode = 1 and ISet /= "01") then
-							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
-						elsif (MCycle = MCycles) or
-							No_BTR = '1' or
-							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
-							M1_n <= '0';
-							MCycle <= "001";
-							IntCycle <= '0';
-							NMICycle <= '0';
-							if NMI_s = '1' and Prefix = "00" then
-								NMICycle <= '1';
-								IntE_FF1 <= '0';
-							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
-								IntCycle <= '1';
-								IntE_FF1 <= '0';
-								IntE_FF2 <= '0';
-							end if;
-						else
-							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
-						end if;
-					end if;
-				else
-					if (Auto_Wait = '1' and Auto_Wait_t2 = '0') nor
-						(IOWait = 1 and IORQ_i = '1' and Auto_Wait_t1 = '0') then
-						TState <= TState + 1;
-					end if;
-				end if;
-			end if;
-			if TState = 0 then
-				M1_n <= '0';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	process (IntCycle, NMICycle, MCycle)
-	begin
-		Auto_Wait <= '0';
-		if IntCycle = '1' or NMICycle = '1' then
-			if MCycle = "001" then
-				Auto_Wait <= '1';
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/T80/T80_ALU.vhd
deleted file mode 100644
index 86fddce7..00000000
--- a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/T80/T80_ALU.vhd	
+++ /dev/null
@@ -1,351 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---	0238 : Fixed zero flag for 16 bit SBC and ADC
---
---	0240 : Added GB operations
---
---	0242 : Cleanup
---
---	0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16		: in std_logic;
-		Z16			: in std_logic;
-		ALU_Op		: in std_logic_vector(3 downto 0);
-		IR			: in std_logic_vector(5 downto 0);
-		ISet		: in std_logic_vector(1 downto 0);
-		BusA		: in std_logic_vector(7 downto 0);
-		BusB		: in std_logic_vector(7 downto 0);
-		F_In		: in std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
-	procedure AddSub(A : std_logic_vector;
-					B : std_logic_vector;
-					Sub : std_logic;
-					Carry_In : std_logic;
-					signal Res : out std_logic_vector;
-					signal Carry : out std_logic) is
-		variable B_i		: unsigned(A'length - 1 downto 0);
-		variable Res_i		: unsigned(A'length + 1 downto 0);
-	begin
-		if Sub = '1' then
-			B_i := not unsigned(B);
-		else
-			B_i := unsigned(B);
-		end if;
-		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
-		Carry <= Res_i(A'length + 1);
-		Res <= std_logic_vector(Res_i(A'length downto 1));
-	end;
-
-	-- AddSub variables (temporary signals)
-	signal	UseCarry		: std_logic;
-	signal	Carry7_v		: std_logic;
-	signal	Overflow_v		: std_logic;
-	signal	HalfCarry_v		: std_logic;
-	signal	Carry_v			: std_logic;
-	signal	Q_v				: std_logic_vector(7 downto 0);
-
-	signal	BitMask			: std_logic_vector(7 downto 0);
-
-begin
-
-	with IR(5 downto 3) select BitMask <= "00000001" when "000",
-									"00000010" when "001",
-									"00000100" when "010",
-									"00001000" when "011",
-									"00010000" when "100",
-									"00100000" when "101",
-									"01000000" when "110",
-									"10000000" when others;
-
-	UseCarry <= not ALU_Op(2) and ALU_Op(0);
-	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
-	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
-	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-	OverFlow_v <= Carry_v xor Carry7_v;
-
-	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
-		variable Q_t : std_logic_vector(7 downto 0);
-		variable DAA_Q : unsigned(8 downto 0);
-	begin
-		Q_t := "--------";
-		F_Out <= F_In;
-		DAA_Q := "---------";
-		case ALU_Op is
-		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_C) <= '0';
-			case ALU_OP(2 downto 0) is
-			when "000" | "001" => -- ADD, ADC
-				Q_t := Q_v;
-				F_Out(Flag_C) <= Carry_v;
-				F_Out(Flag_H) <= HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "010" | "011" | "111" => -- SUB, SBC, CP
-				Q_t := Q_v;
-				F_Out(Flag_N) <= '1';
-				F_Out(Flag_C) <= not Carry_v;
-				F_Out(Flag_H) <= not HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "100" => -- AND
-				Q_t(7 downto 0) := BusA and BusB;
-				F_Out(Flag_H) <= '1';
-			when "101" => -- XOR
-				Q_t(7 downto 0) := BusA xor BusB;
-				F_Out(Flag_H) <= '0';
-			when others => -- OR "110"
-				Q_t(7 downto 0) := BusA or BusB;
-				F_Out(Flag_H) <= '0';
-			end case;
-			if ALU_Op(2 downto 0) = "111" then -- CP
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			else
-				F_Out(Flag_X) <= Q_t(3);
-				F_Out(Flag_Y) <= Q_t(5);
-			end if;
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				if Z16 = '1' then
-					F_Out(Flag_Z) <= F_In(Flag_Z);	-- 16 bit ADC,SBC
-				end if;
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			case ALU_Op(2 downto 0) is
-			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
-			when others =>
-				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			end case;
-			if Arith16 = '1' then
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-				F_Out(Flag_P) <= F_In(Flag_P);
-			end if;
-		when "1100" =>
-			-- DAA
-			F_Out(Flag_H) <= F_In(Flag_H);
-			F_Out(Flag_C) <= F_In(Flag_C);
-			DAA_Q(7 downto 0) := unsigned(BusA);
-			DAA_Q(8) := '0';
-			if F_In(Flag_N) = '0' then
-				-- After addition
-				-- Alow > 9 or H = 1
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if (DAA_Q(3 downto 0) > 9) then
-						F_Out(Flag_H) <= '1';
-					else
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q := DAA_Q + 6;
-				end if;
-				-- new Ahigh > 9 or C = 1
-				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q + 96; -- 0x60
-				end if;
-			else
-				-- After subtraction
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if DAA_Q(3 downto 0) > 5 then
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
-				end if;
-				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q - 352; -- 0x160
-				end if;
-			end if;
-			F_Out(Flag_X) <= DAA_Q(3);
-			F_Out(Flag_Y) <= DAA_Q(5);
-			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
-			Q_t := std_logic_vector(DAA_Q(7 downto 0));
-			if DAA_Q(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= DAA_Q(7);
-			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
-				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
-		when "1101" | "1110" =>
-			-- RLD, RRD
-			Q_t(7 downto 4) := BusA(7 downto 4);
-			if ALU_Op(0) = '1' then
-				Q_t(3 downto 0) := BusB(7 downto 4);
-			else
-				Q_t(3 downto 0) := BusB(3 downto 0);
-			end if;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-		when "1001" =>
-			-- BIT
-			Q_t(7 downto 0) := BusB and BitMask;
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				F_Out(Flag_P) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-				F_Out(Flag_P) <= '0';
-			end if;
-			F_Out(Flag_H) <= '1';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= '0';
-			F_Out(Flag_Y) <= '0';
-			if IR(2 downto 0) /= "110" then
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			end if;
-		when "1010" =>
-			-- SET
-			Q_t(7 downto 0) := BusB or BitMask;
-		when "1011" =>
-			-- RES
-			Q_t(7 downto 0) := BusB and not BitMask;
-		when "1000" =>
-			-- ROT
-			case IR(5 downto 3) is
-			when "000" => -- RLC
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := BusA(7);
-				F_Out(Flag_C) <= BusA(7);
-			when "010" => -- RL
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(7);
-			when "001" => -- RRC
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(0);
-				F_Out(Flag_C) <= BusA(0);
-			when "011" => -- RR
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(0);
-			when "100" => -- SLA
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := '0';
-				F_Out(Flag_C) <= BusA(7);
-			when "110" => -- SLL (Undocumented) / SWAP
-				if Mode = 3 then
-					Q_t(7 downto 4) := BusA(3 downto 0);
-					Q_t(3 downto 0) := BusA(7 downto 4);
-					F_Out(Flag_C) <= '0';
-				else
-					Q_t(7 downto 1) := BusA(6 downto 0);
-					Q_t(0) := '1';
-					F_Out(Flag_C) <= BusA(7);
-				end if;
-			when "101" => -- SRA
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(7);
-				F_Out(Flag_C) <= BusA(0);
-			when others => -- SRL
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := '0';
-				F_Out(Flag_C) <= BusA(0);
-			end case;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			if ISet = "00" then
-				F_Out(Flag_P) <= F_In(Flag_P);
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-			end if;
-		when others =>
-			null;
-		end case;
-		Q <= Q_t;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/T80/T80_MCode.vhd
deleted file mode 100644
index 4cc30f35..00000000
--- a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/T80/T80_MCode.vhd	
+++ /dev/null
@@ -1,1934 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0208 : First complete release
---
---	0211 : Fixed IM 1
---
---	0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---	0235 : Added IM 2 fix by Mike Johnson
---
---	0238 : Added NoRead signal
---
---	0238b: Fixed instruction timing for POP and DJNZ
---
---	0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
---
---	0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_MCode is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in std_logic_vector(7 downto 0);
-		ISet			: in std_logic_vector(1 downto 0);
-		MCycle			: in std_logic_vector(2 downto 0);
-		F				: in std_logic_vector(7 downto 0);
-		NMICycle		: in std_logic;
-		IntCycle		: in std_logic;
-		MCycles			: out std_logic_vector(2 downto 0);
-		TStates			: out std_logic_vector(2 downto 0);
-		Prefix			: out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC			: out std_logic;
-		Inc_WZ			: out std_logic;
-		IncDec_16		: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg		: out std_logic;
-		Read_To_Acc		: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op			: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC		: out std_logic;
-		Arith16			: out std_logic;
-		Set_Addr_To		: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY			: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ				: out std_logic;
-		LDW				: out std_logic;
-		LDSPHL			: out std_logic;
-		Special_LD		: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH		: out std_logic;
-		ExchangeRp		: out std_logic;
-		ExchangeAF		: out std_logic;
-		ExchangeRS		: out std_logic;
-		I_DJNZ			: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN			: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC			: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead			: out std_logic;
-		Write			: out std_logic
-	);
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
-	constant aNone	: std_logic_vector(2 downto 0) := "111";
-	constant aBC	: std_logic_vector(2 downto 0) := "000";
-	constant aDE	: std_logic_vector(2 downto 0) := "001";
-	constant aXY	: std_logic_vector(2 downto 0) := "010";
-	constant aIOA	: std_logic_vector(2 downto 0) := "100";
-	constant aSP	: std_logic_vector(2 downto 0) := "101";
-	constant aZI	: std_logic_vector(2 downto 0) := "110";
---	constant aNone	: std_logic_vector(2 downto 0) := "000";
---	constant aXY	: std_logic_vector(2 downto 0) := "001";
---	constant aIOA	: std_logic_vector(2 downto 0) := "010";
---	constant aSP	: std_logic_vector(2 downto 0) := "011";
---	constant aBC	: std_logic_vector(2 downto 0) := "100";
---	constant aDE	: std_logic_vector(2 downto 0) := "101";
---	constant aZI	: std_logic_vector(2 downto 0) := "110";
-
-	function is_cc_true(
-		F : std_logic_vector(7 downto 0);
-		cc : bit_vector(2 downto 0)
-		) return boolean is
-	begin
-		if Mode = 3 then
-			case cc is
-			when "000" => return F(7) = '0'; -- NZ
-			when "001" => return F(7) = '1'; -- Z
-			when "010" => return F(4) = '0'; -- NC
-			when "011" => return F(4) = '1'; -- C
-			when "100" => return false;
-			when "101" => return false;
-			when "110" => return false;
-			when "111" => return false;
-			end case;
-		else
-			case cc is
-			when "000" => return F(6) = '0'; -- NZ
-			when "001" => return F(6) = '1'; -- Z
-			when "010" => return F(0) = '0'; -- NC
-			when "011" => return F(0) = '1'; -- C
-			when "100" => return F(2) = '0'; -- PO
-			when "101" => return F(2) = '1'; -- PE
-			when "110" => return F(7) = '0'; -- P
-			when "111" => return F(7) = '1'; -- M
-			end case;
-		end if;
-	end;
-
-begin
-
-	process (IR, ISet, MCycle, F, NMICycle, IntCycle)
-		variable DDD : std_logic_vector(2 downto 0);
-		variable SSS : std_logic_vector(2 downto 0);
-		variable DPair : std_logic_vector(1 downto 0);
-		variable IRB : bit_vector(7 downto 0);
-	begin
-		DDD := IR(5 downto 3);
-		SSS := IR(2 downto 0);
-		DPair := IR(5 downto 4);
-		IRB := to_bitvector(IR);
-
-		MCycles <= "001";
-		if MCycle = "001" then
-			TStates <= "100";
-		else
-			TStates <= "011";
-		end if;
-		Prefix <= "00";
-		Inc_PC <= '0';
-		Inc_WZ <= '0';
-		IncDec_16 <= "0000";
-		Read_To_Acc <= '0';
-		Read_To_Reg <= '0';
-		Set_BusB_To <= "0000";
-		Set_BusA_To <= "0000";
-		ALU_Op <= "0" & IR(5 downto 3);
-		Save_ALU <= '0';
-		PreserveC <= '0';
-		Arith16 <= '0';
-		IORQ <= '0';
-		Set_Addr_To <= aNone;
-		Jump <= '0';
-		JumpE <= '0';
-		JumpXY <= '0';
-		Call <= '0';
-		RstP <= '0';
-		LDZ <= '0';
-		LDW <= '0';
-		LDSPHL <= '0';
-		Special_LD <= "000";
-		ExchangeDH <= '0';
-		ExchangeRp <= '0';
-		ExchangeAF <= '0';
-		ExchangeRS <= '0';
-		I_DJNZ <= '0';
-		I_CPL <= '0';
-		I_CCF <= '0';
-		I_SCF <= '0';
-		I_RETN <= '0';
-		I_BT <= '0';
-		I_BC <= '0';
-		I_BTR <= '0';
-		I_RLD <= '0';
-		I_RRD <= '0';
-		I_INRC <= '0';
-		SetDI <= '0';
-		SetEI <= '0';
-		IMode <= "11";
-		Halt <= '0';
-		NoRead <= '0';
-		Write <= '0';
-
-		case ISet is
-		when "00" =>
-
-------------------------------------------------------------------------------
---
---	Unprefixed instructions
---
-------------------------------------------------------------------------------
-
-		case IRB is
--- 8 BIT LOAD GROUP
-		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-			-- LD r,r'
-			Set_BusB_To(2 downto 0) <= SSS;
-			ExchangeRp <= '1';
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-			-- LD r,n
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-			-- LD r,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-			-- LD (HL),r
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110110" =>
-			-- LD (HL),n
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00001010" =>
-			-- LD A,(BC)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00011010" =>
-			-- LD A,(DE)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00111010" =>
-			if Mode = 3 then
-				-- LDD A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD A,(nn)
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-				when 4 =>
-					Read_To_Acc <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00000010" =>
-			-- LD (BC),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00010010" =>
-			-- LD (DE),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110010" =>
-			if Mode = 3 then
-				-- LDD (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),A
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					Set_BusB_To <= "0111";
-				when 4 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 16 BIT LOAD GROUP
-		when "00000001"|"00010001"|"00100001"|"00110001" =>
-			-- LD dd,nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1000";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1001";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-		when "00101010" =>
-			if Mode = 3 then
-				-- LDI A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD HL,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Set_BusA_To(2 downto 0) <= "101"; -- L
-					Read_To_Reg <= '1';
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Set_BusA_To(2 downto 0) <= "100"; -- H
-					Read_To_Reg <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00100010" =>
-			if Mode = 3 then
-				-- LDI (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "0101"; -- L
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "0100"; -- H
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11111001" =>
-			-- LD SP,HL
-			TStates <= "110";
-			LDSPHL <= '1';
-		when "11000101"|"11010101"|"11100101"|"11110101" =>
-			-- PUSH qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_TO <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "0111";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '0';
-					Set_BusB_To(3) <= '0';
-				end if;
-			when 2 =>
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "1011";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '1';
-					Set_BusB_To(3) <= '0';
-				end if;
-				Write <= '1';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "11000001"|"11010001"|"11100001"|"11110001" =>
-			-- POP qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1011";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				IncDec_16 <= "0111";
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "0111";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
-		when "11101011" =>
-			if Mode /= 3 then
-				-- EX DE,HL
-				ExchangeDH <= '1';
-			end if;
-		when "00001000" =>
-			if Mode = 3 then
-				-- LD (nn),SP
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "1000";
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "1001";
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EX AF,AF'
-				ExchangeAF <= '1';
-			end if;
-		when "11011001" =>
-			if Mode = 3 then
-				-- RETI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-					SetEI <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EXX
-				ExchangeRS <= '1';
-			end if;
-		when "11100011" =>
-			if Mode /= 3 then
-				-- EX (SP),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aSP;
-				when 2 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0101";
-					Set_BusB_To <= "0101";
-					Set_Addr_To <= aSP;
-				when 3 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0100";
-					Set_BusB_To <= "0100";
-					Set_Addr_To <= aSP;
-				when 5 =>
-					IncDec_16 <= "1111";
-					TStates <= "101";
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
-		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-			-- ADD A,r
-			-- ADC A,r
-			-- SUB A,r
-			-- SBC A,r
-			-- AND A,r
-			-- OR A,r
-			-- XOR A,r
-			-- CP A,r
-			Set_BusB_To(2 downto 0) <= SSS;
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-			-- ADD A,(HL)
-			-- ADC A,(HL)
-			-- SUB A,(HL)
-			-- SBC A,(HL)
-			-- AND A,(HL)
-			-- OR A,(HL)
-			-- XOR A,(HL)
-			-- CP A,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			when others => null;
-			end case;
-		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-			-- ADD A,n
-			-- ADC A,n
-			-- SUB A,n
-			-- SBC A,n
-			-- AND A,n
-			-- OR A,n
-			-- XOR A,n
-			-- CP A,n
-			MCycles <= "010";
-			if MCycle = "010" then
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			end if;
-		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-			-- INC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0000";
-		when "00110100" =>
-			-- INC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				ALU_Op <= "0000";
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-			-- DEC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0010";
-		when "00110101" =>
-			-- DEC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				ALU_Op <= "0010";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
-		when "00100111" =>
-			-- DAA
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			ALU_Op <= "1100";
-			Save_ALU <= '1';
-		when "00101111" =>
-			-- CPL
-			I_CPL <= '1';
-		when "00111111" =>
-			-- CCF
-			I_CCF <= '1';
-		when "00110111" =>
-			-- SCF
-			I_SCF <= '1';
-		when "00000000" =>
-			if NMICycle = '1' then
-				-- NMI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif IntCycle = '1' then
-				-- INT (IM 2)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					LDZ <= '1';
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 5 =>
-					Jump <= '1';
-				when others => null;
-				end case;
-			else
-				-- NOP
-			end if;
-		when "01110110" =>
-			-- HALT
-			Halt <= '1';
-		when "11110011" =>
-			-- DI
-			SetDI <= '1';
-		when "11111011" =>
-			-- EI
-			SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
-		when "00001001"|"00011001"|"00101001"|"00111001" =>
-			-- ADD HL,ss
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				NoRead <= '1';
-				ALU_Op <= "0000";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusA_To(2 downto 0) <= "101";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-				when others =>
-					Set_BusB_To <= "1000";
-				end case;
-				TStates <= "100";
-				Arith16 <= '1';
-			when 3 =>
-				NoRead <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				ALU_Op <= "0001";
-				Set_BusA_To(2 downto 0) <= "100";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-				when others =>
-					Set_BusB_To <= "1001";
-				end case;
-				Arith16 <= '1';
-			when others =>
-			end case;
-		when "00000011"|"00010011"|"00100011"|"00110011" =>
-			-- INC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "01";
-			IncDec_16(1 downto 0) <= DPair;
-		when "00001011"|"00011011"|"00101011"|"00111011" =>
-			-- DEC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "11";
-			IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
-		when "00000111"
-			-- RLCA
-			|"00010111"
-			-- RLA
-			|"00001111"
-			-- RRCA
-			|"00011111" =>
-			-- RRA
-			Set_BusA_To(2 downto 0) <= "111";
-			ALU_Op <= "1000";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-
--- JUMP GROUP
-		when "11000011" =>
-			-- JP nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				Inc_PC <= '1';
-				Jump <= '1';
-			when others => null;
-			end case;
-		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+C),A
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-						Set_BusB_To	<= "0111";
-					when 2 =>
-						Write <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "01" =>
-					-- LD (nn),A
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						Set_BusB_To <= "0111";
-					when 4 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "10" =>
-					-- LD A,($FF00+C)
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-					when 2 =>
-						Read_To_Acc <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "11" =>
-					-- LD A,(nn)
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-					when 4 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- JP cc,nn
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Jump <= '1';
-					end if;
-				when others => null;
-				end case;
-			end if;
-		when "00011000" =>
-			if Mode /= 2 then
-				-- JR e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00111000" =>
-			if Mode /= 2 then
-				-- JR C,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00110000" =>
-			if Mode /= 2 then
-				-- JR NC,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00101000" =>
-			if Mode /= 2 then
-				-- JR Z,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00100000" =>
-			if Mode /= 2 then
-				-- JR NZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "11101001" =>
-			-- JP (HL)
-			JumpXY <= '1';
-		when "00010000" =>
-			if Mode = 3 then
-				I_DJNZ <= '1';
-			elsif Mode < 2 then
-				-- DJNZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					I_DJNZ <= '1';
-					Set_BusB_To <= "1010";
-					Set_BusA_To(2 downto 0) <= "000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					I_DJNZ <= '1';
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-
--- CALL AND RETURN GROUP
-		when "11001101" =>
-			-- CALL nn
-			MCycles <= "101";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				IncDec_16 <= "1111";
-				Inc_PC <= '1';
-				TStates <= "100";
-				Set_Addr_To <= aSP;
-				LDW <= '1';
-				Set_BusB_To <= "1101";
-			when 4 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 5 =>
-				Write <= '1';
-				Call <= '1';
-			when others => null;
-			end case;
-		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
-			if IR(5) = '0' or Mode /= 3 then
-				-- CALL cc,nn
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					LDW <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						IncDec_16 <= "1111";
-						Set_Addr_TO <= aSP;
-						TStates <= "100";
-						Set_BusB_To <= "1101";
-					else
-						MCycles <= "011";
-					end if;
-				when 4 =>
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 5 =>
-					Write <= '1';
-					Call <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11001001" =>
-			-- RET
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				Set_Addr_TO <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				LDZ <= '1';
-			when 3 =>
-				Jump <= '1';
-				IncDec_16 <= "0111";
-			when others => null;
-			end case;
-		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+nn),A
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-						Set_BusB_To	<= "0111";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "01" =>
-					-- ADD SP,n
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						ALU_Op <= "0000";
-						Inc_PC <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_BusA_To <= "1000";
-						Set_BusB_To <= "0110";
-					when 3 =>
-						NoRead <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						ALU_Op <= "0001";
-						Set_BusA_To <= "1001";
-						Set_BusB_To <= "1110";	-- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
-					when others =>
-					end case;
-				when "10" =>
-					-- LD A,($FF00+nn)
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-					when 3 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				when "11" =>
-					-- LD HL,SP+n	-- Not correct !!!!!!!!!!!!!!!!!!!
-					MCycles <= "101";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						LDW <= '1';
-					when 4 =>
-						Set_BusA_To(2 downto 0) <= "101"; -- L
-						Read_To_Reg <= '1';
-						Inc_WZ <= '1';
-						Set_Addr_To <= aZI;
-					when 5 =>
-						Set_BusA_To(2 downto 0) <= "100"; -- H
-						Read_To_Reg <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- RET cc
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Set_Addr_TO <= aSP;
-					else
-						MCycles <= "001";
-					end if;
-					TStates <= "101";
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-				when others => null;
-				end case;
-			end if;
-		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-			-- RST p
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1101";
-			when 2 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 3 =>
-				Write <= '1';
-				RstP <= '1';
-			when others => null;
-			end case;
-
--- INPUT AND OUTPUT GROUP
-		when "11011011" =>
-			if Mode /= 3 then
-				-- IN A,(n)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-				when 3 =>
-					Read_To_Acc <= '1';
-					IORQ <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11010011" =>
-			if Mode /= 3 then
-				-- OUT (n),A
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-					Set_BusB_To	<= "0111";
-				when 3 =>
-					Write <= '1';
-					IORQ <= '1';
-				when others => null;
-				end case;
-			end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
-		when "11001011" =>
-			if Mode /= 2 then
-				Prefix <= "01";
-			end if;
-
-		when "11101101" =>
-			if Mode < 2 then
-				Prefix <= "10";
-			end if;
-
-		when "11011101"|"11111101" =>
-			if Mode < 2 then
-				Prefix <= "11";
-			end if;
-
-		end case;
-
-		when "01" =>
-
-------------------------------------------------------------------------------
---
---	CB prefixed instructions
---
-------------------------------------------------------------------------------
-
-			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
-			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-				-- RLC r
-				-- RL r
-				-- RRC r
-				-- RR r
-				-- SLA r
-				-- SRA r
-				-- SRL r
-				-- SLL r (Undocumented) / SWAP r
-				if MCycle = "001" then
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-				end if;
-			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-				-- RLC (HL)
-				-- RL (HL)
-				-- RRC (HL)
-				-- RR (HL)
-				-- SRA (HL)
-				-- SRL (HL)
-				-- SLA (HL)
-				-- SLL (HL) (Undocumented) / SWAP (HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
-				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-				-- BIT b,r
-				if MCycle = "001" then
-					Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-					ALU_Op <= "1001";
-				end if;
-			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-				-- BIT b,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1001";
-					TStates <= "100";
-				when others =>
-				end case;
-			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-				-- SET b,r
-				if MCycle = "001" then
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-				end if;
-			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-				-- SET b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-				-- RES b,r
-				if MCycle = "001" then
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-				end if;
-			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-				-- RES b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			end case;
-
-		when others =>
-
-------------------------------------------------------------------------------
---
---	ED prefixed instructions
---
-------------------------------------------------------------------------------
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
-				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
-				|                                            "10100100"|"10100101"|"10100110"|"10100111"
-				|                                            "10101100"|"10101101"|"10101110"|"10101111"
-				|                                            "10110100"|"10110101"|"10110110"|"10110111"
-				|                                            "10111100"|"10111101"|"10111110"|"10111111"
-				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
-				null; -- NOP, undocumented
-			when "01111110"|"01111111" =>
-				-- NOP, undocumented
-				null;
--- 8 BIT LOAD GROUP
-			when "01010111" =>
-				-- LD A,I
-				Special_LD <= "100";
-				TStates <= "101";
-			when "01011111" =>
-				-- LD A,R
-				Special_LD <= "101";
-				TStates <= "101";
-			when "01000111" =>
-				-- LD I,A
-				Special_LD <= "110";
-				TStates <= "101";
-			when "01001111" =>
-				-- LD R,A
-				Special_LD <= "111";
-				TStates <= "101";
--- 16 BIT LOAD GROUP
-			when "01001011"|"01011011"|"01101011"|"01111011" =>
-				-- LD dd,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1000";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '1';
-					end if;
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1001";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '0';
-					end if;
-				when others => null;
-				end case;
-			when "01000011"|"01010011"|"01100011"|"01110011" =>
-				-- LD (nn),dd
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1000";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1001";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10100000" | "10101000" | "10110000" | "10111000" =>
-				-- LDI, LDD, LDIR, LDDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0000";
-					Set_Addr_To <= aDE;
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- IX
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					I_BT <= '1';
-					TStates <= "101";
-					Write <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0101"; -- DE
-					else
-						IncDec_16 <= "1101";
-					end if;
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100001" | "10101001" | "10110001" | "10111001" =>
-				-- CPI, CPD, CPIR, CPDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0111";
-					Save_ALU <= '1';
-					PreserveC <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0110";
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					I_BC <= '1';
-					TStates <= "101";
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-				-- NEG
-				Alu_OP <= "0010";
-				Set_BusB_To <= "0111";
-				Set_BusA_To <= "1010";
-				Read_To_Acc <= '1';
-				Save_ALU <= '1';
-			when "01000110"|"01001110"|"01100110"|"01101110" =>
-				-- IM 0
-				IMode <= "00";
-			when "01010110"|"01110110" =>
-				-- IM 1
-				IMode <= "01";
-			when "01011110"|"01110111" =>
-				-- IM 2
-				IMode <= "10";
--- 16 bit arithmetic
-			when "01001010"|"01011010"|"01101010"|"01111010" =>
-				-- ADC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0001";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-						when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0001";
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-					when others =>
-						Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01000010"|"01010010"|"01100010"|"01110010" =>
-				-- SBC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-					when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					when others =>
-							Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01101111" =>
-				-- RLD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1101";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RLD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01100111" =>
-				-- RRD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1110";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RRD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-				-- RETI, RETN
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-				when others => null;
-				end case;
-			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-				-- IN r,(C)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-				when 2 =>
-					IORQ <= '1';
-					if IR(5 downto 3) /= "110" then
-						Read_To_Reg <= '1';
-						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
-					end if;
-					I_INRC <= '1';
-				when others =>
-				end case;
-			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-				-- OUT (C),r
-				-- OUT (C),0
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To(2 downto 0)	<= IR(5 downto 3);
-					if IR(5 downto 3) = "110" then
-						Set_BusB_To(3) <= '1';
-					end if;
-				when 2 =>
-					Write <= '1';
-					IORQ <= '1';
-				when others =>
-				end case;
-			when "10100010" | "10101010" | "10110010" | "10111010" =>
-				-- INI, IND, INIR, INDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					IORQ <= '1';
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aXY;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0010";
-					else
-						IncDec_16 <= "1010";
-					end if;
-					TStates <= "100";
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100011" | "10101011" | "10110011" | "10111011" =>
-				-- OUTI, OUTD, OTIR, OTDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aBC;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0010";
-					else
-						IncDec_16 <= "1010";
-					end if;
-					IORQ <= '1';
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end case;
-
-		end case;
-
-		if Mode = 1 then
-			if MCycle = "001" then
---				TStates <= "100";
-			else
-				TStates <= "011";
-			end if;
-		end if;
-
-		if Mode = 3 then
-			if MCycle = "001" then
---				TStates <= "100";
-			else
-				TStates <= "100";
-			end if;
-		end if;
-
-		if Mode < 2 then
-			if MCycle = "110" then
-				Inc_PC <= '1';
-				if Mode = 1 then
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-					Set_BusB_To(2 downto 0) <= SSS;
-					Set_BusB_To(3) <= '0';
-				end if;
-				if IRB = "00110110" or IRB = "11001011" then
-					Set_Addr_To <= aNone;
-				end if;
-			end if;
-			if MCycle = "111" then
-				if Mode = 0 then
-					TStates <= "101";
-				end if;
-				if ISet /= "01" then
-					Set_Addr_To <= aXY;
-				end if;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-				if IRB = "00110110" or ISet = "01" then
-					-- LD (HL),n
-					Inc_PC <= '1';
-				else
-					NoRead <= '1';
-				end if;
-			end if;
-		end if;
-
-	end process;
-
-end;
diff --git a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/T80/T80_Pack.vhd
deleted file mode 100644
index ac7d34da..00000000
--- a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/T80/T80_Pack.vhd	
+++ /dev/null
@@ -1,208 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
-	component T80
-	generic(
-		Mode : integer := 0;	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait : integer := 0;	-- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		RESET_n		: in std_logic;
-		CLK_n		: in std_logic;
-		CEN			: in std_logic;
-		WAIT_n		: in std_logic;
-		INT_n		: in std_logic;
-		NMI_n		: in std_logic;
-		BUSRQ_n		: in std_logic;
-		M1_n		: out std_logic;
-		IORQ		: out std_logic;
-		NoRead		: out std_logic;
-		Write		: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
-		DInst		: in std_logic_vector(7 downto 0);
-		DI			: in std_logic_vector(7 downto 0);
-		DO			: out std_logic_vector(7 downto 0);
-		MC			: out std_logic_vector(2 downto 0);
-		TS			: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE		: out std_logic;
-		Stop		: out std_logic
-	);
-	end component;
-
-	component T80_Reg
-	port(
-		Clk			: in std_logic;
-		CEN			: in std_logic;
-		WEH			: in std_logic;
-		WEL			: in std_logic;
-		AddrA		: in std_logic_vector(2 downto 0);
-		AddrB		: in std_logic_vector(2 downto 0);
-		AddrC		: in std_logic_vector(2 downto 0);
-		DIH			: in std_logic_vector(7 downto 0);
-		DIL			: in std_logic_vector(7 downto 0);
-		DOAH		: out std_logic_vector(7 downto 0);
-		DOAL		: out std_logic_vector(7 downto 0);
-		DOBH		: out std_logic_vector(7 downto 0);
-		DOBL		: out std_logic_vector(7 downto 0);
-		DOCH		: out std_logic_vector(7 downto 0);
-		DOCL		: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-	component T80_MCode
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in std_logic_vector(7 downto 0);
-		ISet			: in std_logic_vector(1 downto 0);
-		MCycle			: in std_logic_vector(2 downto 0);
-		F				: in std_logic_vector(7 downto 0);
-		NMICycle		: in std_logic;
-		IntCycle		: in std_logic;
-		MCycles			: out std_logic_vector(2 downto 0);
-		TStates			: out std_logic_vector(2 downto 0);
-		Prefix			: out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC			: out std_logic;
-		Inc_WZ			: out std_logic;
-		IncDec_16		: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg		: out std_logic;
-		Read_To_Acc		: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op			: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC		: out std_logic;
-		Arith16			: out std_logic;
-		Set_Addr_To		: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY			: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ				: out std_logic;
-		LDW				: out std_logic;
-		LDSPHL			: out std_logic;
-		Special_LD		: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH		: out std_logic;
-		ExchangeRp		: out std_logic;
-		ExchangeAF		: out std_logic;
-		ExchangeRS		: out std_logic;
-		I_DJNZ			: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN			: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC			: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead			: out std_logic;
-		Write			: out std_logic
-	);
-	end component;
-
-	component T80_ALU
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16		: in std_logic;
-		Z16			: in std_logic;
-		ALU_Op		: in std_logic_vector(3 downto 0);
-		IR			: in std_logic_vector(5 downto 0);
-		ISet		: in std_logic_vector(1 downto 0);
-		BusA		: in std_logic_vector(7 downto 0);
-		BusB		: in std_logic_vector(7 downto 0);
-		F_In		: in std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-end;
diff --git a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/T80/T80_Reg.vhd
deleted file mode 100644
index 828485fb..00000000
--- a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/T80/T80_Reg.vhd	
+++ /dev/null
@@ -1,105 +0,0 @@
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
---	0242 : Initial release
---
---	0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
-	port(
-		Clk			: in std_logic;
-		CEN			: in std_logic;
-		WEH			: in std_logic;
-		WEL			: in std_logic;
-		AddrA		: in std_logic_vector(2 downto 0);
-		AddrB		: in std_logic_vector(2 downto 0);
-		AddrC		: in std_logic_vector(2 downto 0);
-		DIH			: in std_logic_vector(7 downto 0);
-		DIL			: in std_logic_vector(7 downto 0);
-		DOAH		: out std_logic_vector(7 downto 0);
-		DOAL		: out std_logic_vector(7 downto 0);
-		DOBH		: out std_logic_vector(7 downto 0);
-		DOBL		: out std_logic_vector(7 downto 0);
-		DOCH		: out std_logic_vector(7 downto 0);
-		DOCL		: out std_logic_vector(7 downto 0)
-	);
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
-	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
-	signal	RegsH	: Register_Image(0 to 7);
-	signal	RegsL	: Register_Image(0 to 7);
-
-begin
-
-	process (Clk)
-	begin
-		if Clk'event and Clk = '1' then
-			if CEN = '1' then
-				if WEH = '1' then
-					RegsH(to_integer(unsigned(AddrA))) <= DIH;
-				end if;
-				if WEL = '1' then
-					RegsL(to_integer(unsigned(AddrA))) <= DIL;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	DOAH <= RegsH(to_integer(unsigned(AddrA)));
-	DOAL <= RegsL(to_integer(unsigned(AddrA)));
-	DOBH <= RegsH(to_integer(unsigned(AddrB)));
-	DOBL <= RegsL(to_integer(unsigned(AddrB)));
-	DOCH <= RegsH(to_integer(unsigned(AddrC)));
-	DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
diff --git a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/T80/T80s.vhd b/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/T80/T80s.vhd
deleted file mode 100644
index 5b612110..00000000
--- a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/T80/T80s.vhd	
+++ /dev/null
@@ -1,190 +0,0 @@
---
--- Z80 compatible microprocessor core, synchronous top level
--- Different timing than the original z80
--- Inputs needs to be synchronous and outputs may glitch
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0208 : First complete release
---
---	0210 : Fixed read with wait
---
---	0211 : Fixed interrupt cycle
---
---	0235 : Updated for T80 interface change
---
---	0236 : Added T2Write generic
---
---	0237 : Fixed T2Write with wait state
---
---	0238 : Updated for T80 interface change
---
---	0240 : Updated for T80 interface change
---
---	0242 : Updated for T80 interface change
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80s is
-	generic(
-		Mode : integer := 0;	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		T2Write : integer := 0;	-- 0 => WR_n active in T3, /=0 => WR_n active in T2
-		IOWait : integer := 1	-- 0 => Single cycle I/O, 1 => Std I/O cycle
-	);
-	port(
-		RESET_n		: in std_logic;
-		CLK_n		: in std_logic;
-		WAIT_n		: in std_logic;
-		INT_n		: in std_logic;
-		NMI_n		: in std_logic;
-		BUSRQ_n		: in std_logic;
-		M1_n		: out std_logic;
-		MREQ_n		: out std_logic;
-		IORQ_n		: out std_logic;
-		RD_n		: out std_logic;
-		WR_n		: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
-		DI			: in std_logic_vector(7 downto 0);
-		DO			: out std_logic_vector(7 downto 0)
-	);
-end T80s;
-
-architecture rtl of T80s is
-
-	signal CEN			: std_logic;
-	signal IntCycle_n	: std_logic;
-	signal NoRead		: std_logic;
-	signal Write		: std_logic;
-	signal IORQ			: std_logic;
-	signal DI_Reg		: std_logic_vector(7 downto 0);
-	signal MCycle		: std_logic_vector(2 downto 0);
-	signal TState		: std_logic_vector(2 downto 0);
-
-begin
-
-	CEN <= '1';
-
-	u0 : T80
-		generic map(
-			Mode => Mode,
-			IOWait => IOWait)
-		port map(
-			CEN => CEN,
-			M1_n => M1_n,
-			IORQ => IORQ,
-			NoRead => NoRead,
-			Write => Write,
-			RFSH_n => RFSH_n,
-			HALT_n => HALT_n,
-			WAIT_n => Wait_n,
-			INT_n => INT_n,
-			NMI_n => NMI_n,
-			RESET_n => RESET_n,
-			BUSRQ_n => BUSRQ_n,
-			BUSAK_n => BUSAK_n,
-			CLK_n => CLK_n,
-			A => A,
-			DInst => DI,
-			DI => DI_Reg,
-			DO => DO,
-			MC => MCycle,
-			TS => TState,
-			IntCycle_n => IntCycle_n);
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			RD_n <= '1';
-			WR_n <= '1';
-			IORQ_n <= '1';
-			MREQ_n <= '1';
-			DI_Reg <= "00000000";
-		elsif CLK_n'event and CLK_n = '1' then
-			RD_n <= '1';
-			WR_n <= '1';
-			IORQ_n <= '1';
-			MREQ_n <= '1';
-			if MCycle = "001" then
-				if TState = "001" or (TState = "010" and Wait_n = '0') then
-					RD_n <= not IntCycle_n;
-					MREQ_n <= not IntCycle_n;
-					IORQ_n <= IntCycle_n;
-				end if;
-				if TState = "011" then
-					MREQ_n <= '0';
-				end if;
-			else
-				if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
-					RD_n <= '0';
-					IORQ_n <= not IORQ;
-					MREQ_n <= IORQ;
-				end if;
-				if T2Write = 0 then
-					if TState = "010" and Write = '1' then
-						WR_n <= '0';
-						IORQ_n <= not IORQ;
-						MREQ_n <= IORQ;
-					end if;
-				else
-					if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
-						WR_n <= '0';
-						IORQ_n <= not IORQ;
-						MREQ_n <= IORQ;
-					end if;
-				end if;
-			end if;
-			if TState = "010" and Wait_n = '1' then
-				DI_Reg <= DI;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/T80/T80se.vhd b/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/T80/T80se.vhd
deleted file mode 100644
index ac8886a8..00000000
--- a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/T80/T80se.vhd	
+++ /dev/null
@@ -1,184 +0,0 @@
---
--- Z80 compatible microprocessor core, synchronous top level with clock enable
--- Different timing than the original z80
--- Inputs needs to be synchronous and outputs may glitch
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0235 : First release
---
---	0236 : Added T2Write generic
---
---	0237 : Fixed T2Write with wait state
---
---	0238 : Updated for T80 interface change
---
---	0240 : Updated for T80 interface change
---
---	0242 : Updated for T80 interface change
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80se is
-	generic(
-		Mode : integer := 0;	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		T2Write : integer := 0;	-- 0 => WR_n active in T3, /=0 => WR_n active in T2
-		IOWait : integer := 1	-- 0 => Single cycle I/O, 1 => Std I/O cycle
-	);
-	port(
-		RESET_n		: in std_logic;
-		CLK_n		: in std_logic;
-		CLKEN		: in std_logic;
-		WAIT_n		: in std_logic;
-		INT_n		: in std_logic;
-		NMI_n		: in std_logic;
-		BUSRQ_n		: in std_logic;
-		M1_n		: out std_logic;
-		MREQ_n		: out std_logic;
-		IORQ_n		: out std_logic;
-		RD_n		: out std_logic;
-		WR_n		: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
-		DI			: in std_logic_vector(7 downto 0);
-		DO			: out std_logic_vector(7 downto 0)
-	);
-end T80se;
-
-architecture rtl of T80se is
-
-	signal IntCycle_n	: std_logic;
-	signal NoRead		: std_logic;
-	signal Write		: std_logic;
-	signal IORQ			: std_logic;
-	signal DI_Reg		: std_logic_vector(7 downto 0);
-	signal MCycle		: std_logic_vector(2 downto 0);
-	signal TState		: std_logic_vector(2 downto 0);
-
-begin
-
-	u0 : T80
-		generic map(
-			Mode => Mode,
-			IOWait => IOWait)
-		port map(
-			CEN => CLKEN,
-			M1_n => M1_n,
-			IORQ => IORQ,
-			NoRead => NoRead,
-			Write => Write,
-			RFSH_n => RFSH_n,
-			HALT_n => HALT_n,
-			WAIT_n => Wait_n,
-			INT_n => INT_n,
-			NMI_n => NMI_n,
-			RESET_n => RESET_n,
-			BUSRQ_n => BUSRQ_n,
-			BUSAK_n => BUSAK_n,
-			CLK_n => CLK_n,
-			A => A,
-			DInst => DI,
-			DI => DI_Reg,
-			DO => DO,
-			MC => MCycle,
-			TS => TState,
-			IntCycle_n => IntCycle_n);
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			RD_n <= '1';
-			WR_n <= '1';
-			IORQ_n <= '1';
-			MREQ_n <= '1';
-			DI_Reg <= "00000000";
-		elsif CLK_n'event and CLK_n = '1' then
-			if CLKEN = '1' then
-				RD_n <= '1';
-				WR_n <= '1';
-				IORQ_n <= '1';
-				MREQ_n <= '1';
-				if MCycle = "001" then
-					if TState = "001" or (TState = "010" and Wait_n = '0') then
-						RD_n <= not IntCycle_n;
-						MREQ_n <= not IntCycle_n;
-						IORQ_n <= IntCycle_n;
-					end if;
-					if TState = "011" then
-						MREQ_n <= '0';
-					end if;
-				else
-					if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
-						RD_n <= '0';
-						IORQ_n <= not IORQ;
-						MREQ_n <= IORQ;
-					end if;
-					if T2Write = 0 then
-						if TState = "010" and Write = '1' then
-							WR_n <= '0';
-							IORQ_n <= not IORQ;
-							MREQ_n <= IORQ;
-						end if;
-					else
-						if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
-							WR_n <= '0';
-							IORQ_n <= not IORQ;
-							MREQ_n <= IORQ;
-						end if;
-					end if;
-				end if;
-				if TState = "010" and Wait_n = '1' then
-					DI_Reg <= DI;
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/YM2149_linmix_sep.vhd b/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/YM2149_linmix_sep.vhd
deleted file mode 100644
index 27f26749..00000000
--- a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/YM2149_linmix_sep.vhd	
+++ /dev/null
@@ -1,553 +0,0 @@
--- changes for seperate audio outputs and enable now enables cpu access as well
---
--- A simulation model of YM2149 (AY-3-8910 with bells on)
-
--- Copyright (c) MikeJ - Jan 2005
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- You are responsible for any legal issues arising from your use of this code.
---
--- The latest version of this file can be found at: www.fpgaarcade.com
---
--- Email support@fpgaarcade.com
---
--- Revision list
---
--- version 001 initial release
---
--- Clues from MAME sound driver and Kazuhiro TSUJIKAWA
---
--- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V)
--- vol 15 .. 0
--- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132
--- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order
--- to produced all the required values.
--- (The first part of the curve is a bit steeper and the last bit is more linear than expected)
---
--- NOTE, this component uses LINEAR mixing of the three analogue channels, and is only
--- accurate for designs where the outputs are buffered and not simply wired together.
--- The ouput level is more complex in that case and requires a larger table.
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_arith.all;
-  use ieee.std_logic_unsigned.all;
-
-entity YM2149 is
-  port (
-  -- data bus
-  I_DA                : in  std_logic_vector(7 downto 0);
-  O_DA                : out std_logic_vector(7 downto 0);
-  O_DA_OE_L           : out std_logic;
-  -- control
-  I_A9_L              : in  std_logic;
-  I_A8                : in  std_logic;
-  I_BDIR              : in  std_logic;
-  I_BC2               : in  std_logic;
-  I_BC1               : in  std_logic;
-  I_SEL_L             : in  std_logic;
-
-  O_AUDIO             : out std_logic_vector(7 downto 0);
-  O_CHAN              : out std_logic_vector(1 downto 0);
-  -- port a
-  I_IOA               : in  std_logic_vector(7 downto 0);
-  O_IOA               : out std_logic_vector(7 downto 0);
-  O_IOA_OE_L          : out std_logic;
-  -- port b
-  I_IOB               : in  std_logic_vector(7 downto 0);
-  O_IOB               : out std_logic_vector(7 downto 0);
-  O_IOB_OE_L          : out std_logic;
-
-  ENA                 : in  std_logic; -- clock enable for higher speed operation
-  RESET_L             : in  std_logic;
-  CLK                 : in  std_logic  -- note 6 Mhz
-  );
-end;
-
-architecture RTL of YM2149 is
-  type  array_16x8   is array (0 to 15) of std_logic_vector( 7 downto 0);
-  type  array_3x12   is array (1 to  3) of std_logic_vector(11 downto 0);
-
-  signal cnt_div              : std_logic_vector(3 downto 0) := (others => '0');
-  signal cnt_div_t1           : std_logic_vector(3 downto 0);
-  signal noise_div            : std_logic := '0';
-  signal ena_div              : std_logic;
-  signal ena_div_noise        : std_logic;
-  signal poly17               : std_logic_vector(16 downto 0) := (others => '0');
-
-  -- registers
-  signal addr                 : std_logic_vector(7 downto 0);
-  signal busctrl_addr         : std_logic;
-  signal busctrl_we           : std_logic;
-  signal busctrl_re           : std_logic;
-
-  signal reg                  : array_16x8;
-  signal env_reset            : std_logic;
-  signal ioa_inreg            : std_logic_vector(7 downto 0);
-  signal iob_inreg            : std_logic_vector(7 downto 0);
-
-  signal noise_gen_cnt        : std_logic_vector(4 downto 0);
-  signal noise_gen_op         : std_logic;
-  signal tone_gen_cnt         : array_3x12 := (others => (others => '0'));
-  signal tone_gen_op          : std_logic_vector(3 downto 1) := "000";
-
-  signal env_gen_cnt          : std_logic_vector(15 downto 0);
-  signal env_ena              : std_logic;
-  signal env_hold             : std_logic;
-  signal env_inc              : std_logic;
-  signal env_vol              : std_logic_vector(4 downto 0);
-
-  signal tone_ena_l           : std_logic;
-  signal tone_src             : std_logic;
-  signal noise_ena_l          : std_logic;
-  signal chan_vol             : std_logic_vector(4 downto 0);
-
-  signal dac_amp              : std_logic_vector(7 downto 0);
-begin
-  -- cpu i/f
-  p_busdecode            : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8)
-    variable cs : std_logic;
-    variable sel : std_logic_vector(2 downto 0);
-  begin
-    -- BDIR BC2 BC1 MODE
-    --   0   0   0  inactive
-    --   0   0   1  address
-    --   0   1   0  inactive
-    --   0   1   1  read
-    --   1   0   0  address
-    --   1   0   1  inactive
-    --   1   1   0  write
-    --   1   1   1  read
-    busctrl_addr <= '0';
-    busctrl_we <= '0';
-    busctrl_re <= '0';
-
-    cs := '0';
-    if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then
-      cs := '1';
-    end if;
-
-    sel := (I_BDIR & I_BC2 & I_BC1);
-    case sel is
-      when "000" => null;
-      when "001" => busctrl_addr <= '1';
-      when "010" => null;
-      when "011" => busctrl_re   <= cs;
-      when "100" => busctrl_addr <= '1';
-      when "101" => null;
-      when "110" => busctrl_we   <= cs;
-      when "111" => busctrl_addr <= '1';
-      when others => null;
-    end case;
-  end process;
-
-  p_oe                   : process(busctrl_re)
-  begin
-    -- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns
-    O_DA_OE_L <= not (busctrl_re);
-  end process;
-
-  --
-  -- CLOCKED
-  --
-  p_waddr                : process(RESET_L, CLK)
-  begin
-    -- looks like registers are latches in real chip, but the address is caught at the end of the address state.
-    if (RESET_L = '0') then
-      addr <= (others => '0');
-    elsif rising_edge(CLK) then
-      if (ENA = '1') then
-        if (busctrl_addr = '1') then
-          addr <= I_DA;
-        end if;
-      end if;
-    end if;
-  end process;
-
-  p_wdata                : process(RESET_L, CLK)
-  begin
-    if (RESET_L = '0') then
-      reg <= (others => (others => '0'));
-      env_reset <= '1';
-    elsif rising_edge(CLK) then
-      if (ENA = '1') then
-        env_reset <= '0';
-        if (busctrl_we = '1') then
-          case addr(3 downto 0) is
-            when x"0" => reg(0)  <= I_DA;
-            when x"1" => reg(1)  <= I_DA;
-            when x"2" => reg(2)  <= I_DA;
-            when x"3" => reg(3)  <= I_DA;
-            when x"4" => reg(4)  <= I_DA;
-            when x"5" => reg(5)  <= I_DA;
-            when x"6" => reg(6)  <= I_DA;
-            when x"7" => reg(7)  <= I_DA;
-            when x"8" => reg(8)  <= I_DA;
-            when x"9" => reg(9)  <= I_DA;
-            when x"A" => reg(10) <= I_DA;
-            when x"B" => reg(11) <= I_DA;
-            when x"C" => reg(12) <= I_DA;
-            when x"D" => reg(13) <= I_DA; env_reset <= '1';
-            when x"E" => reg(14) <= I_DA;
-            when x"F" => reg(15) <= I_DA;
-            when others => null;
-          end case;
-        end if;
-      end if;
-    end if;
-  end process;
-
-  p_rdata                : process(busctrl_re, addr, reg, ioa_inreg, iob_inreg)
-  begin
-    O_DA <= (others => '0'); -- 'X'
-    if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator
-      case addr(3 downto 0) is
-        when x"0" => O_DA <= reg(0) ;
-        when x"1" => O_DA <= "0000" & reg(1)(3 downto 0) ;
-        when x"2" => O_DA <= reg(2) ;
-        when x"3" => O_DA <= "0000" & reg(3)(3 downto 0) ;
-        when x"4" => O_DA <= reg(4) ;
-        when x"5" => O_DA <= "0000" & reg(5)(3 downto 0) ;
-        when x"6" => O_DA <= "000"  & reg(6)(4 downto 0) ;
-        when x"7" => O_DA <= reg(7) ;
-        when x"8" => O_DA <= "000"  & reg(8)(4 downto 0) ;
-        when x"9" => O_DA <= "000"  & reg(9)(4 downto 0) ;
-        when x"A" => O_DA <= "000"  & reg(10)(4 downto 0) ;
-        when x"B" => O_DA <= reg(11);
-        when x"C" => O_DA <= reg(12);
-        when x"D" => O_DA <= "0000" & reg(13)(3 downto 0);
-        when x"E" => if (reg(7)(6) = '0') then -- input
-                       O_DA <= ioa_inreg;
-                     else
-                       O_DA <= reg(14); -- read output reg
-                     end if;
-        when x"F" => if (Reg(7)(7) = '0') then
-                       O_DA <= iob_inreg;
-                     else
-                       O_DA <= reg(15);
-                     end if;
-        when others => null;
-      end case;
-    end if;
-  end process;
-  --
-  p_divider              : process
-  begin
-    wait until rising_edge(CLK);
-    -- / 8 when SEL is high and /16 when SEL is low
-    if (ENA = '1') then
-      ena_div <= '0';
-      ena_div_noise <= '0';
-      if (cnt_div = "0000") then
-        cnt_div <= (not I_SEL_L) & "111";
-        ena_div <= '1';
-
-        noise_div <= not noise_div;
-        if (noise_div = '1') then
-          ena_div_noise <= '1';
-        end if;
-      else
-        cnt_div <= cnt_div - "1";
-      end if;
-    end if;
-  end process;
-
-  p_noise_gen            : process
-    variable noise_gen_comp : std_logic_vector(4 downto 0);
-    variable poly17_zero : std_logic;
-  begin
-    wait until rising_edge(CLK);
-    if (reg(6)(4 downto 0) = "00000") then
-      noise_gen_comp := "00000";
-    else
-      noise_gen_comp := (reg(6)(4 downto 0) - "1");
-    end if;
-
-    poly17_zero := '0';
-    if (poly17 = "00000000000000000") then poly17_zero := '1'; end if;
-
-    if (ENA = '1') then
-      if (ena_div_noise = '1') then -- divider ena
-
-        if (noise_gen_cnt >= noise_gen_comp) then
-          noise_gen_cnt <= "00000";
-          poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1);
-        else
-          noise_gen_cnt <= (noise_gen_cnt + "1");
-        end if;
-      end if;
-    end if;
-  end process;
-  noise_gen_op <= poly17(0);
-
-  p_tone_gens            : process
-    variable tone_gen_freq : array_3x12;
-    variable tone_gen_comp : array_3x12;
-  begin
-    wait until rising_edge(CLK);
-    -- looks like real chips count up - we need to get the Exact behaviour ..
-    tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0);
-    tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2);
-    tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4);
-    -- period 0 = period 1
-    for i in 1 to 3 loop
-      if (tone_gen_freq(i) = x"000") then
-        tone_gen_comp(i) := x"000";
-      else
-        tone_gen_comp(i) := (tone_gen_freq(i) - "1");
-      end if;
-    end loop;
-
-    if (ENA = '1') then
-      for i in 1 to 3 loop
-        if (ena_div = '1') then -- divider ena
-
-          if (tone_gen_cnt(i) >= tone_gen_comp(i)) then
-            tone_gen_cnt(i) <= x"000";
-            tone_gen_op(i) <= not tone_gen_op(i);
-          else
-            tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1");
-          end if;
-        end if;
-      end loop;
-    end if;
-  end process;
-
-  p_envelope_freq        : process
-    variable env_gen_freq : std_logic_vector(15 downto 0);
-    variable env_gen_comp : std_logic_vector(15 downto 0);
-  begin
-    wait until rising_edge(CLK);
-    env_gen_freq := reg(12) & reg(11);
-    -- envelope freqs 1 and 0 are the same.
-    if (env_gen_freq = x"0000") then
-      env_gen_comp := x"0000";
-    else
-      env_gen_comp := (env_gen_freq - "1");
-    end if;
-
-    if (ENA = '1') then
-      env_ena <= '0';
-      if (ena_div = '1') then -- divider ena
-        if (env_gen_cnt >= env_gen_comp) then
-          env_gen_cnt <= x"0000";
-          env_ena <= '1';
-        else
-          env_gen_cnt <= (env_gen_cnt + "1");
-        end if;
-      end if;
-    end if;
-  end process;
-
-  p_envelope_shape       : process(env_reset, reg, CLK)
-    variable is_bot    : boolean;
-    variable is_bot_p1 : boolean;
-    variable is_top_m1 : boolean;
-    variable is_top    : boolean;
-  begin
-    if (env_reset = '1') then
-      -- load initial state
-      if (reg(13)(2) = '0') then -- attack
-        env_vol <= "11111";
-        env_inc <= '0'; -- -1
-      else
-        env_vol <= "00000";
-        env_inc <= '1'; -- +1
-      end if;
-      env_hold <= '0';
-
-    elsif rising_edge(CLK) then
-      is_bot    := (env_vol = "00000");
-      is_bot_p1 := (env_vol = "00001");
-      is_top_m1 := (env_vol = "11110");
-      is_top    := (env_vol = "11111");
-
-      if (ENA = '1') then
-        if (env_ena = '1') then
-          if (env_hold = '0') then
-            if (env_inc = '1') then
-              env_vol <= (env_vol + "00001");
-            else
-              env_vol <= (env_vol + "11111");
-            end if;
-          end if;
-
-          -- envelope shape control.
-          if (reg(13)(3) = '0') then
-            if (env_inc = '0') then -- down
-              if is_bot_p1 then env_hold <= '1'; end if;
-            else
-              if is_top then env_hold <= '1'; end if;
-            end if;
-          else
-            if (reg(13)(0) = '1') then -- hold = 1
-              if (env_inc = '0') then -- down
-                if (reg(13)(1) = '1') then -- alt
-                  if is_bot    then env_hold <= '1'; end if;
-                else
-                  if is_bot_p1 then env_hold <= '1'; end if;
-                end if;
-              else
-                if (reg(13)(1) = '1') then -- alt
-                  if is_top    then env_hold <= '1'; end if;
-                else
-                  if is_top_m1 then env_hold <= '1'; end if;
-                end if;
-              end if;
-
-            elsif (reg(13)(1) = '1') then -- alternate
-              if (env_inc = '0') then -- down
-                if is_bot_p1 then env_hold <= '1'; end if;
-                if is_bot    then env_hold <= '0'; env_inc <= '1'; end if;
-              else
-                if is_top_m1 then env_hold <= '1'; end if;
-                if is_top    then env_hold <= '0'; env_inc <= '0'; end if;
-              end if;
-            end if;
-
-          end if;
-        end if;
-      end if;
-    end if;
-  end process;
-
-  p_chan_mixer           : process(cnt_div, reg, tone_gen_op)
-  begin
-    tone_ena_l  <= '1'; tone_src <= '1';
-    noise_ena_l <= '1'; chan_vol <= "00000";
-    case cnt_div(1 downto 0) is
-      when "00" =>
-        tone_ena_l  <= reg(7)(0); tone_src <= tone_gen_op(1); chan_vol <= reg(8)(4 downto 0);
-        noise_ena_l <= reg(7)(3);
-      when "01" =>
-        tone_ena_l  <= reg(7)(1); tone_src <= tone_gen_op(2); chan_vol <= reg(9)(4 downto 0);
-        noise_ena_l <= reg(7)(4);
-      when "10" =>
-        tone_ena_l  <= reg(7)(2); tone_src <= tone_gen_op(3); chan_vol <= reg(10)(4 downto 0);
-        noise_ena_l <= reg(7)(5);
-      when "11" => null; -- tone gen outputs become valid on this clock
-      when others => null;
-    end case;
-  end process;
-
-  p_op_mixer             : process
-    variable chan_mixed : std_logic;
-    variable chan_amp : std_logic_vector(4 downto 0);
-  begin
-    wait until rising_edge(CLK);
-    if (ENA = '1') then
-
-      chan_mixed := (tone_ena_l or tone_src) and (noise_ena_l or noise_gen_op);
-
-      chan_amp := (others => '0');
-      if (chan_mixed = '1') then
-        if (chan_vol(4) = '0') then
-          if (chan_vol(3 downto 0) = "0000") then -- nothing is easy ! make sure quiet is quiet
-            chan_amp := "00000";
-          else
-            chan_amp := chan_vol(3 downto 0) & '1'; -- make sure level 31 (env) = level 15 (tone)
-          end if;
-        else
-          chan_amp := env_vol(4 downto 0);
-        end if;
-      end if;
-
-      dac_amp <= x"00";
-      case chan_amp is
-        when "11111" => dac_amp <= x"FF";
-        when "11110" => dac_amp <= x"D9";
-        when "11101" => dac_amp <= x"BA";
-        when "11100" => dac_amp <= x"9F";
-        when "11011" => dac_amp <= x"88";
-        when "11010" => dac_amp <= x"74";
-        when "11001" => dac_amp <= x"63";
-        when "11000" => dac_amp <= x"54";
-        when "10111" => dac_amp <= x"48";
-        when "10110" => dac_amp <= x"3D";
-        when "10101" => dac_amp <= x"34";
-        when "10100" => dac_amp <= x"2C";
-        when "10011" => dac_amp <= x"25";
-        when "10010" => dac_amp <= x"1F";
-        when "10001" => dac_amp <= x"1A";
-        when "10000" => dac_amp <= x"16";
-        when "01111" => dac_amp <= x"13";
-        when "01110" => dac_amp <= x"10";
-        when "01101" => dac_amp <= x"0D";
-        when "01100" => dac_amp <= x"0B";
-        when "01011" => dac_amp <= x"09";
-        when "01010" => dac_amp <= x"08";
-        when "01001" => dac_amp <= x"07";
-        when "01000" => dac_amp <= x"06";
-        when "00111" => dac_amp <= x"05";
-        when "00110" => dac_amp <= x"04";
-        when "00101" => dac_amp <= x"03";
-        when "00100" => dac_amp <= x"03";
-        when "00011" => dac_amp <= x"02";
-        when "00010" => dac_amp <= x"02";
-        when "00001" => dac_amp <= x"01";
-        when "00000" => dac_amp <= x"00";
-        when others => null;
-      end case;
-
-      cnt_div_t1 <= cnt_div;
-    end if;
-  end process;
-
-  p_audio_output         : process(RESET_L, CLK)
-  begin
-    if (RESET_L = '0') then
-      O_AUDIO <= (others => '0');
-      O_CHAN  <= (others => '0');
-    elsif rising_edge(CLK) then
-
-      if (ENA = '1') then
-        O_AUDIO <= dac_amp(7 downto 0);
-        O_CHAN  <= cnt_div_t1(1 downto 0);
-      end if;
-    end if;
-  end process;
-
-  p_io_ports             : process(reg)
-  begin
-    O_IOA      <= reg(14);
-    O_IOA_OE_L <= not reg(7)(6);
-    O_IOB      <= reg(15);
-    O_IOB_OE_L <= not reg(7)(7);
-  end process;
-
-  p_io_ports_inreg       : process
-  begin
-    wait until rising_edge(CLK);
-    if (ENA = '1') then -- resync
-      ioa_inreg <= I_IOA;
-      iob_inreg <= I_IOB;
-    end if;
-  end process;
-end architecture RTL;
diff --git a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/dpram.vhd b/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/dpram.vhd
deleted file mode 100644
index cda0f3cd..00000000
--- a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/dpram.vhd	
+++ /dev/null
@@ -1,123 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.all;
-
-ENTITY dpram IS
-	GENERIC
-	(
-		init_file			: string := "";
-		numwords_a		: natural := 0;   -- not used any more
-		widthad_a			: natural;
-		width_a				: natural := 8;
-    outdata_reg_a : string := "UNREGISTERED";
-    outdata_reg_b : string := "UNREGISTERED"
-	);
-	PORT
-	(
-		address_a		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
-		address_b		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
-		clock_a		: IN STD_LOGIC ;
-		clock_b		: IN STD_LOGIC ;
-		data_a		: IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
-		data_b		: IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
-		wren_a		: IN STD_LOGIC  := '1';
-		wren_b		: IN STD_LOGIC  := '1';
-		q_a		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
-		q_b		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
-	);
-END dpram;
-
-
-ARCHITECTURE SYN OF dpram IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
-
-	COMPONENT altsyncram
-	GENERIC (
-		address_reg_b		: STRING;
-		clock_enable_input_a		: STRING;
-		clock_enable_input_b		: STRING;
-		clock_enable_output_a		: STRING;
-		clock_enable_output_b		: STRING;
-		indata_reg_b		: STRING;
-		init_file		: STRING;
-		intended_device_family		: STRING;
-		lpm_type		: STRING;
-		numwords_a		: NATURAL;
-		numwords_b		: NATURAL;
-		operation_mode		: STRING;
-		outdata_aclr_a		: STRING;
-		outdata_aclr_b		: STRING;
-		outdata_reg_a		: STRING;
-		outdata_reg_b		: STRING;
-		power_up_uninitialized		: STRING;
-		widthad_a		: NATURAL;
-		widthad_b		: NATURAL;
-		width_a		: NATURAL;
-		width_b		: NATURAL;
-		width_byteena_a		: NATURAL;
-		width_byteena_b		: NATURAL;
-		wrcontrol_wraddress_reg_b		: STRING
-	);
-	PORT (
-			wren_a	: IN STD_LOGIC ;
-			clock0	: IN STD_LOGIC ;
-			wren_b	: IN STD_LOGIC ;
-			clock1	: IN STD_LOGIC ;
-			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
-			address_b	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
-			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
-			q_b	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
-			data_a	: IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
-			data_b	: IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
-	);
-	END COMPONENT;
-
-BEGIN
-	q_a    <= sub_wire0(width_a-1 DOWNTO 0);
-	q_b    <= sub_wire1(width_a-1 DOWNTO 0);
-
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		address_reg_b => "CLOCK1",
-		clock_enable_input_a => "BYPASS",
-		clock_enable_input_b => "BYPASS",
-		clock_enable_output_a => "BYPASS",
-		clock_enable_output_b => "BYPASS",
-		indata_reg_b => "CLOCK1",
-		init_file => init_file,
-		intended_device_family => "Cyclone III",
-		lpm_type => "altsyncram",
-		numwords_a => 2**widthad_a,
-		numwords_b => 2**widthad_a,
-		operation_mode => "BIDIR_DUAL_PORT",
-		outdata_aclr_a => "NONE",
-		outdata_aclr_b => "NONE",
-		outdata_reg_a => outdata_reg_a,
-		outdata_reg_b => outdata_reg_b,
-		power_up_uninitialized => "FALSE",
-		widthad_a => widthad_a,
-		widthad_b => widthad_a,
-		width_a => width_a,
-		width_b => width_a,
-		width_byteena_a => 1,
-		width_byteena_b => 1,
-		wrcontrol_wraddress_reg_b => "CLOCK1"
-	)
-	PORT MAP (
-		wren_a => wren_a,
-		clock0 => clock_a,
-		wren_b => wren_b,
-		clock1 => clock_b,
-		address_a => address_a,
-		address_b => address_b,
-		data_a => data_a,
-		data_b => data_b,
-		q_a => sub_wire0,
-		q_b => sub_wire1
-	);
-
-END SYN;
diff --git a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/fpga_nrx.v b/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/fpga_nrx.v
deleted file mode 100644
index 5f2f23be..00000000
--- a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/fpga_nrx.v	
+++ /dev/null
@@ -1,206 +0,0 @@
-/**************************************************************
-	FPGA New Rally-X (Main part)
-***************************************************************/
-module fpga_nrx
-(
-	input				RESET,		// RESET
-	input				CLK24M,		// Clock 24.576MHz
-	input				CLK14M,
-	output			hsync,
-	output			vsync,
-	output			hblank,
-	output			vblank,
-	output  [2:0]	r,
-	output  [2:0]	g,
-	output  [1:0]	b,
-	
-
-	output  [10:0]	SND,
-
-	input   [7:0]	DSW,			// DipSW
-	input	  [7:0]	CTR1,			// Controler (Negative logic)
-	input	  [7:0]	CTR2,
-
-	output  [1:0]	LAMP
-);
-
-
-//--------------------------------------------------
-//  Clock Generators
-//--------------------------------------------------
-reg [2:0] _CCLK;
-always @( posedge CLK24M ) _CCLK <= _CCLK+1;
-
-wire	CLK    = CLK24M;		// 24MHz
-//wire	CCLKx2 = _CCLK[1];	// CPU CLOCKx2 : 6.0MHz
-wire	CCLK   = _CCLK[2];	// CPU CLOCK   : 3.0MHz
-
-
-//--------------------------------------------------
-//  CPU
-//--------------------------------------------------
-// memory access signals
-wire			rd, wr, me, ie, rf, m1;
-wire [15:0] ad;
-wire [7:0]  odt, viddata;
-
-wire			mx      = rf & (~me);
-wire			mr		  = mx & (~rd);
-wire			mw      = mx & (~wr);
-
-// interrupt signal/vector generator & other latches
-reg			inte  = 1'b0;
-reg			intl  = 1'b0;
-reg  [7:0]	intv  = 8'h0;
-
-reg			lp0r  = 1'b0;
-reg			lp1r  = 1'b0;
-assign		LAMP  = { lp1r, lp0r };
-
-wire			vblk  = (VP==224)&(HP<=8);
-
-wire			lat_Wce = ( ad[15:4] == 12'hA18 ) & mw;
-
-//wire			bngw = ( lat_Wce & ( ad[3:0] == 4'h0 ) );
-wire			iewr = ( lat_Wce & ( ad[3:0] == 4'h1 ) );
-//wire			flip = ( lat_Wce & ( ad[3:0] == 4'h3 ) );
-wire			lp0w = ( lat_Wce & ( ad[3:0] == 4'h4 ) );
-wire			lp1w = ( lat_Wce & ( ad[3:0] == 4'h5 ) );
-wire			iowr = ( (~wr) & (~ie) & m1 );
-
-wire  [7:0]	sound_cmd = ( ad[15:8]  == 8'b1010_0001 ) & mw ? odt : 0;
-wire			sound_trig = ( lat_Wce & ( ad[3:0] == 4'h0 ) );
-
-
-always @( posedge CCLK ) begin
-	if ( iowr ) intv <= odt;
-	if ( vblk ) intl <= 1'b1;
-	if ( iewr ) begin
-		inte <= odt[0];
-		intl <= 1'b0; 
-	end
-//	if ( bngw ) bang <= odt[0];
-	if ( lp0w ) lp0r <= odt[0];
-	if ( lp1w ) lp1r <= odt[0];
-end
-
-wire	irq_n = ~( intl & inte );
-
-
-// address decoders
-wire	rom_Rce = ( ( ad[15:14] == 2'b00        ) & mr );		// $0000-$3FFF(R)
-wire	ram_Rce = ( ( ad[15:11] == 5'b1001_1    ) & mr );		// $9800-$9FFF(R)
-wire	ram_Wce = ( ( ad[15:11] == 5'b1001_1    ) & mw );		// $9800-$9FFF(W)
-wire	inp_Rce = ( ( ad[15:12] == 4'b1010      ) & mr );		// $A000-$AFFF(R)
-//wire	snd_Wce = ( ( ad[15:8]  == 8'b1010_0001 ) & mw );		// $A100-$A1FF(W)
-wire	vid_Rce;
-
-
-wire [7:0]	romdata;
-jng_prg_rom jng_prg_rom (
-	.clk(CCLK),
-	.addr(ad[13:0]),
-	.data(romdata)
-	);
-
-// Work RAM (2KB)
-wire [7:0] ramdata;
-GSPRAM #(11,8) workram( 
-	.CL(CCLK), 
-	.AD(ad[10:0]), 
-	.WE(ram_Wce), 
-	.DI(odt), 
-	.DO(ramdata) 
-	);
-
-
-// Controler/DipSW input
-wire [7:0]  in0data = CTR1;
-wire [7:0]  in1data = CTR2;
-wire [7:0]  in2data = DSW;
-wire [7:0]  inpdata = ad[8] ? in2data : ad[7] ? in1data : in0data;
-
-
-// databus selector
-wire [7:0]	romd  = rom_Rce ? romdata : 8'h00;
-wire [7:0]  ramd  = ram_Rce ? ramdata : 8'h00;
-wire [7:0]  vidd  = vid_Rce ? viddata : 8'h00;
-wire [7:0]	inpd  = inp_Rce ? inpdata : 8'h00;
-wire [7:0]	irqv  = ( (~m1) & (~ie) ) ? intv : 8'h00;
-
-wire [7:0]	idt   = romd | ramd | irqv | vidd | inpd;
-
-
-T80s z80(
-	.RESET_n(~RESET), 
-	.CLK(~CCLK),
-	.WAIT_n(1'b1), 
-	.INT_n(1'b1),
-	.NMI_n(irq_n),
-	.BUSRQ_n(1'b1), 
-	.DI(idt),
-	.M1_n(m1), 
-	.MREQ_n(me), 
-	.IORQ_n(ie), 
-	.RD_n(rd), 
-	.WR_n(wr), 
-	.RFSH_n(rf), 
-	.HALT_n(), 
-	.BUSAK_n(),
-	.A(ad),
-	.DO(odt)
-	);
-
-//--------------------------------------------------
-//  VIDEO
-//--------------------------------------------------
-wire	 [8:0]	HP;
-wire   [8:0]	VP;
-wire 				PCLK;
-
-nrx_video video( 
-	.VCLKx4(CLK),  
-	.HPOS(HP+3), 
-	.VPOS(VP+1), 
-	.PCLK(PCLK), 
-	.POUT({b,g,r}), 
-	.CPUCLK(CCLK), 
-	.CPUADDR(ad),
-	.CPUDI(odt),   
-	.CPUDO(viddata),
-	.CPUME(mx),    
-	.CPUWE(mw), 
-	.CPUDT(vid_Rce)
-	);
-	
-nrx_hvgen hvgen(
-	.HPOS(HP),
-	.VPOS(VP),
-	.PCLK(PCLK),
-	.HBLK(hblank),
-	.VBLK(vblank),
-	.HSYN(hsync),
-	.VSYN(vsync)
-	);
-
-//--------------------------------------------------
-//  SOUND
-//--------------------------------------------------
-/*
-nrx_sound sound(
-	.CLK24M(CLK), 
-	.CCLK(CCLK), 
-	.SND(SND),
-	.AD(ad), 
-	.DI(odt[3:0]),
-	.WR(snd_Wce),
-	.BANG(bang)
-	);*/
-time_pilot_sound_board sound(
-	.clock_14(CLK14M),
-	.reset(RESET),
-	.sound_cmd(sound_cmd),
-	.sound_trig(sound_trig),
-	.audio_out(SND)
-	);
-endmodule
diff --git a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/gen_ram.vhd b/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/gen_ram.vhd
deleted file mode 100644
index f1a95608..00000000
--- a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/gen_ram.vhd	
+++ /dev/null
@@ -1,84 +0,0 @@
--- -----------------------------------------------------------------------
---
--- Syntiac's generic VHDL support files.
---
--- -----------------------------------------------------------------------
--- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
--- http://www.syntiac.com/fpga64.html
---
--- Modified April 2016 by Dar (darfpga@aol.fr) 
--- http://darfpga.blogspot.fr
---   Remove address register when writing
---
--- -----------------------------------------------------------------------
---
--- gen_rwram.vhd
---
--- -----------------------------------------------------------------------
---
--- generic ram.
---
--- -----------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
--- -----------------------------------------------------------------------
-
-entity gen_ram is
-	generic (
-		dWidth : integer := 8;
-		aWidth : integer := 10
-	);
-	port (
-		clk : in std_logic;
-		we : in std_logic;
-		addr : in std_logic_vector((aWidth-1) downto 0);
-		d : in std_logic_vector((dWidth-1) downto 0);
-		q : out std_logic_vector((dWidth-1) downto 0)
-	);
-end entity;
-
--- -----------------------------------------------------------------------
-
-architecture rtl of gen_ram is
-	subtype addressRange is integer range 0 to ((2**aWidth)-1);
-	type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0);
-	signal ram: ramDef;
-
-	signal rAddrReg : std_logic_vector((aWidth-1) downto 0);
-	signal qReg : std_logic_vector((dWidth-1) downto 0);
-begin
--- -----------------------------------------------------------------------
--- Signals to entity interface
--- -----------------------------------------------------------------------
---	q <= qReg;
-
--- -----------------------------------------------------------------------
--- Memory write
--- -----------------------------------------------------------------------
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if we = '1' then
-				ram(to_integer(unsigned(addr))) <= d;
-			end if;
-		end if;
-	end process;
-	
--- -----------------------------------------------------------------------
--- Memory read
--- -----------------------------------------------------------------------
-process(clk)
-	begin
-		if rising_edge(clk) then
---			qReg <= ram(to_integer(unsigned(rAddrReg)));
---			rAddrReg <= addr;
-----			qReg <= ram(to_integer(unsigned(addr)));
-      q <= ram(to_integer(unsigned(addr)));
-		end if;
-	end process;
---q <= ram(to_integer(unsigned(addr)));
-end architecture;
-
diff --git a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/nrx_hvgen.v b/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/nrx_hvgen.v
deleted file mode 100644
index 0318fa92..00000000
--- a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/nrx_hvgen.v	
+++ /dev/null
@@ -1,36 +0,0 @@
-module nrx_hvgen
-(
-	output  [8:0]		HPOS,
-	output  [8:0]		VPOS,
-	input 				PCLK,
-	output reg			HBLK = 1,
-	output reg			VBLK = 1,
-	output reg			HSYN = 1,
-	output reg			VSYN = 1
-);
-
-reg [8:0] hcnt = 0;
-reg [8:0] vcnt = 0;
-
-assign HPOS = hcnt;
-assign VPOS = vcnt;
-
-always @(posedge PCLK) begin
-	case (hcnt)
-		287: begin HBLK <= 1; HSYN <= 0; hcnt <= hcnt+1; end
-		311: begin HSYN <= 1; hcnt <= hcnt+1; end
-		383: begin
-			HBLK <= 0; HSYN <= 1; hcnt <= 0;
-			case (vcnt)
-				223: begin VBLK <= 1; vcnt <= vcnt+1; end
-				226: begin VSYN <= 0; vcnt <= vcnt+1; end
-				233: begin VSYN <= 1; vcnt <= vcnt+1; end
-				242: begin VBLK <= 0; vcnt <= 0; end
-				default: vcnt <= vcnt+1;
-			endcase
-		end
-		default: hcnt <= hcnt+1;
-	endcase
-end
-
-endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/nrx_namco.v b/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/nrx_namco.v
deleted file mode 100644
index 5a40777b..00000000
--- a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/nrx_namco.v	
+++ /dev/null
@@ -1,35 +0,0 @@
-/**************************************************************
-	FPGA New Rally-X (Sound Part)
-***************************************************************/
-
-module nrx_namco
-(
-	input			clk,
-	input [7:0] a0,
-	input	[7:0] a1,
-	input	[7:0] a2,
-	output reg [3:0] d0,
-	output reg [3:0] d1,
-	output reg [3:0] d2
-);
-
-reg  [1:0] ph=0;
-
-reg  [7:0] ad;
-wire [7:0] dt;
-nrx_nam_rom namrom(
-	.clk(clk),
-	.addr(ad), 
-	.data(dt)
-	);
-
-always @(negedge clk) begin
-	case (ph)
-	0: begin d2 <= dt[3:0]; ad <= a0; ph <= 1; end
-	1: begin d0 <= dt[3:0]; ad <= a1; ph <= 2; end
-	2: begin d1 <= dt[3:0]; ad <= a2; ph <= 0; end
-	default:;
-	endcase
-end
-
-endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/nrx_psg_voice.v b/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/nrx_psg_voice.v
deleted file mode 100644
index 18a04bae..00000000
--- a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/nrx_psg_voice.v	
+++ /dev/null
@@ -1,28 +0,0 @@
-/**************************************************************
-	FPGA New Rally-X (Sound Part)
-***************************************************************/
-module nrx_psg_voice
-(
-	input					clk,
-	output	[3:0]		out,
-
-	input		[19:0]	freq,
-	input		[3:0]		vol,
-	input		[2:0]		vn,
-
-	output	[7:0]		waveaddr,
-	input		[3:0]		wavedata
-);
-
-reg [19:0] counter = 20'h0;
-reg  [7:0] outreg0;
-
-assign waveaddr = { vn, counter[19:15] };
-assign out = outreg0[7:4];
-
-always @ ( posedge clk ) begin
-	outreg0 = ( { 4'b0000, wavedata } * { 4'b0000, vol } );
-	counter <= counter + freq;
-end
-
-endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/nrx_sound.v b/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/nrx_sound.v
deleted file mode 100644
index 4284ff95..00000000
--- a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/nrx_sound.v	
+++ /dev/null
@@ -1,133 +0,0 @@
-/**************************************************************
-	FPGA New Rally-X (Sound Part)
-***************************************************************/
-
-
-module nrx_sound
-(
-	input					CLK24M,
-	input					CCLK,
-	output reg [7:0]	SND,
-	input	 [15:0]	AD,
-	input  [3:0]	DI,
-	input				WR,
-
-	input				BANG
-);
-
-reg [11:0] ccnt;
-always @( posedge CLK24M ) ccnt <= ccnt+1;
-
-wire	CLK6K   = ccnt[11];
-wire  SCLKx8  = ccnt[4];
-wire	SCLK    = ccnt[7];
-
-wire  [7:0]		wa0, wa1, wa2;
-wire  [3:0]		wd0, wd1, wd2;/*
-nrx_namco namco(
-	.clk(SCLKx8),
-	.a0(wa0),
-	.a1(wa1),
-	.a2(wa2),
-	.d0(wd0),
-	.d1(wd1),
-	.d2(wd2)
-	);*/
-
-reg		  		bWavPlay = 1'b0;
-reg  [13:0] 	wap = 14'h0000;
-wire  [7:0] 	wdp;
-wire  [7:0]		wo = bWavPlay ? wdp : 8'h80;
-
-jng_snd_rom jng_snd_rom (
-	.clk(CLK6K),
-	.addr(wap),
-	.data(wdp)
-	);
-
-always @( posedge CLK6K ) begin
-	if ( BANG && (~bWavPlay) ) bWavPlay <= 1'b1;
-	if ( bWavPlay ) begin
-		wap <= wap+1;
-		if ( wap == 14'h29FF ) begin
-			wap <= 14'h0000;
-			bWavPlay <= 1'b0;
-		end
-	end
-end
-
-reg	[19:0]	f0;
-reg	[15:0]	fq1, fq2;
-reg	[3:0]		v0, v1, v2;
-reg	[2:0]		n0, n1, n2;
-
-wire	[19:0]	f1 = { fq1, 4'b0000 };
-wire	[19:0]	f2 = { fq2, 4'b0000 };
-
-wire	[3:0]		o0,  o1,  o2;
-
-nrx_psg_voice voice0( 
-	.clk(SCLK), 
-	.out(o0), 
-	.freq(f0), 
-	.vol(v0), 
-	.vn(n0), 
-	.waveaddr(wa0), 
-	.wavedata(wd0) 
-	);
-	
-nrx_psg_voice voice1( 
-	.clk(SCLK), 
-	.out(o1), 
-	.freq(f1), 
-	.vol(v1), 
-	.vn(n1), 
-	.waveaddr(wa1), 
-	.wavedata(wd1) 
-	);
-
-nrx_psg_voice voice2( 
-	.clk(SCLK), 
-	.out(o2), 
-	.freq(f2), 
-	.vol(v2), 
-	.vn(n2), 
-	.waveaddr(wa2), 
-	.wavedata(wd2) 
-	);	
-
-reg [7:0] wout;
-always @( posedge SCLK ) SND <= ( { 2'b0, wo } ) + ( o0 + o1 + o2 );
-
-always @( posedge CCLK ) begin
-	if ( WR ) case ( AD[4:0] )
-
-		5'h05:	n0         <= DI[2:0];
-		5'h0A:	n1         <= DI[2:0];
-		5'h0F:	n2         <= DI[2:0];
-
-		5'h10:	f0[3:0]    <= DI;
-		5'h11:	f0[7:4]    <= DI;
-		5'h12:	f0[11:8]   <= DI;
-		5'h13:	f0[15:12]  <= DI;
-		5'h14:	f0[19:16]  <= DI;
-		5'h15:   v0         <= DI;
-
-		5'h16:	fq1[3:0]   <= DI;
-		5'h17:	fq1[7:4]   <= DI;
-		5'h18:	fq1[11:8]  <= DI;
-		5'h19:	fq1[15:12] <= DI;
-		5'h1A:   v1         <= DI;
-
-		5'h1B:	fq2[3:0]   <= DI;
-		5'h1C:	fq2[7:4]   <= DI;
-		5'h1D:	fq2[11:8]  <= DI;
-		5'h1E:	fq2[15:12] <= DI;
-		5'h1F:   v2         <= DI;
-
-		default: ;
-
-	endcase
-end
-
-endmodule
diff --git a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/nrx_sprite.v b/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/nrx_sprite.v
deleted file mode 100644
index c84dfa33..00000000
--- a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/nrx_sprite.v	
+++ /dev/null
@@ -1,154 +0,0 @@
-
-module NRX_SPRITE
-(
-	input					VCLKx4,
-	input					HBLK,
-
-	input	 [8:0]		HPOS,
-	input	 [8:0]		VPOS,
-
-	output reg [10:0]	SPRAADRS,
-	input  [15:0]		SPRADATA,
-
-	output [3:0]		ARAMADRS,
-	input	 [7:0]		ARAMDATA,
-
-	output [11:0]		SPCHRADR,
-	input	 [7:0]		SPCHRDAT,
-
-	output [7:0]		DROMAD,
-	input  [7:0]		DROMDT,
-
-	output reg [8:0]	SPCOL
-);
-
-reg [1:0] clkcnt;
-always @( posedge VCLKx4 ) clkcnt<=clkcnt+1;
-wire VCLKx2 = clkcnt[0];
-wire VCLK	= clkcnt[1];
-
-wire SIDE = VPOS[0];
-
-
-reg  [19:0] SPATR0;
-reg  [36:0] SPATRS[0:31];
-reg	[3:0] WWADR;
-reg			bHit;
-
-assign ARAMADRS = SPRAADRS[3:0];
-
-
-reg	[7:0] WRADR;
-reg	[8:0] HPOSW;
-reg	[8:0] SPWCL;
-
-wire [36:0] SPA  = SPATRS[{~SIDE,WRADR[7:4]}];
-
-wire	[3:0] SH	 = WRADR[3:0]+4'h4;
-wire	[3:0] SV	 = SPA[35:32];
-
-wire	[2:0] SPFY = { 3{SPA[1]} };
-wire	[1:0] SPFX = { 1'b0, SPA[0] };
-wire	[5:0] SPPL = SPA[29:24];
-
-assign SPCHRADR  = { SPA[7:2], ( SV[3] ^ SPA[1] ), ( SH[3:2] ^ SPFX ), ( SV[2:0] ^ SPFY ) };
-wire	[7:0] CHRO = SPCHRDAT;
-
-
-wire	[8:0] YM =  ( SPRADATA[15:8] + 8'h10 ) + VPOS[7:0];
-
-assign DROMAD = { 1'b0, (~SPA[19:17]), SPA[33:32], WRADR[3:2] };
-
-always @ ( posedge VCLKx2 ) begin
-
-	// in H-BLANK
-	if ( HBLK ) begin
-
-		// Sprite V-hit check & list-up
-		if ( SPRAADRS < 10'h20 ) begin
-			if ( SPRAADRS[0] ) begin
-				if ( bHit ) begin
-					SPATRS[{SIDE,WWADR}] <= { 1'b1, SPATR0[3:0], SPRADATA, SPATR0[19:4] };
-					WWADR <= WWADR+1;
-				end
-			end
-			else begin
-				if ( YM[7:4] == 4'b1111 ) begin
-					bHit	<= 1;
-					SPATR0 <= { SPRADATA, YM[3:0] };
-				end
-				else bHit <= 0;
-			end
-			SPRAADRS <= ( SPRAADRS == 10'h1F ) ? 10'h34 : (SPRAADRS+1);
-		end
-		// Rader-dot V-hit check & list-up
-		else begin
-			if ( SPRAADRS < 10'h40 ) begin
-				if ( YM[7:2] == 6'b111111 ) begin
-					SPATRS[{SIDE,WWADR}] <= { 1'b0, 2'b00, YM[1:0], 8'h0, ARAMDATA, SPRADATA };
-					WWADR <= WWADR+1;
-				end
-				SPRAADRS <= SPRAADRS+1;
-			end
-			else SPATRS[{SIDE,WWADR}] <= 0;
-		end
-
-		if ( SPA ) begin
-			// Rend Sprite
-			if ( SPA[36] ) begin
-				HPOSW <= ( WRADR[3:0] ) ? (HPOSW+1) : { SPA[31], SPA[23:16] };
-				case ( SH[1:0] ^ {2{SPFX[0]}} )
-					2'b00: SPWCL <= { 1'b0, SPPL, CHRO[7], CHRO[3] };
-					2'b01: SPWCL <= { 1'b0, SPPL, CHRO[6], CHRO[2] };
-					2'b10: SPWCL <= { 1'b0, SPPL, CHRO[5], CHRO[1] };
-					2'b11: SPWCL <= { 1'b0, SPPL, CHRO[4], CHRO[0] };
-				endcase
-				WRADR <= WRADR+1;
-			end
-			// Rend Rader-dot
-			else begin
-				HPOSW <= ( WRADR[3:0] ) ? (HPOSW+1) : ({ (~SPA[16]), SPA[7:0] });
-				SPWCL <= ( DROMDT[1:0] != 2'b11 ) ? { 1'b1, 6'b000100, DROMDT[1:0] } : 0;
-				WRADR <= WRADR+4;
-			end
-		end
-		else SPWCL <= 0;
-
-	end
-
-	// in H-DISP
-	else begin
-		SPRAADRS <= 10'h14;
-		WWADR <= 0;
-		WRADR <= 0;
-		SPWCL <= 0;
-	end
-
-end
-
-
-reg  [9:0] radr0=0,radr1=1;
-wire [8:0] SPCOLi;
-dpram #(
-	.widthad_a(10),
-	.width_a(9))
-linebuffer(
-	.address_a({SIDE,HPOS}),
-	.address_b({~SIDE,HPOSW}),
-	.clock_a(VCLKx2),
-	.clock_b(VCLKx2),
-	.data_a(9'h0),
-	.data_b(SPWCL),
-	.wren_a(radr0==radr1),
-	.wren_b((SPWCL[0]|SPWCL[1])),
-	.q_a(SPCOLi),
-	.q_b()
-	);
-	
-always @(posedge VCLK) radr0 <= {SIDE,HPOS};
-always @(negedge VCLK) begin 
-	if (radr0!=radr1) SPCOL <= SPCOLi;
-	radr1 <= radr0;
-end
-
-endmodule
diff --git a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/nrx_video.v b/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/nrx_video.v
deleted file mode 100644
index e1b85314..00000000
--- a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/nrx_video.v	
+++ /dev/null
@@ -1,241 +0,0 @@
-/**************************************************************
-	FPGA New Rally-X (Video Part)
-***************************************************************/
-module nrx_video
-(
-	input				 VCLKx4,		// 24.976MHz
-
-	input  [8:0]		HPOS,
-	input  [8:0]		VPOS,
-	output				PCLK,
-	output reg [7:0]	POUT,
-
-	input					CPUCLK,
-	input	 [15:0]		CPUADDR,
-	input	 [7:0]		CPUDI,
-	output [7:0]		CPUDO,
-	input					CPUME,
-	input					CPUWE,
-	output				CPUDT
-);
-
-//-----------------------------------------
-//  Clock generators
-//-----------------------------------------
-reg VCLKx2;
-always @( posedge VCLKx4 ) begin
-	VCLKx2 <= ~VCLKx2;
-end
-
-reg VCLK;
-always @( posedge VCLKx2 ) begin
-	VCLK   <= ~VCLK;
-end
-
-//-----------------------------------------
-//  BG scroll registers
-//-----------------------------------------
-reg [7:0] BGHSCR;
-reg [7:0] BGVSCR;
-
-always @ ( posedge CPUCLK ) begin
-	if ( ( CPUADDR == 16'hA130 ) & CPUME & CPUWE ) begin
-		BGHSCR <= CPUDI-3;
-	end
-	if ( ( CPUADDR == 16'hA140 ) & CPUME & CPUWE ) begin
-		BGVSCR <= CPUDI;
-	end
-end
-
-
-//-----------------------------------------
-//  HV
-//-----------------------------------------
-wire [8:0] BGHPOS = HPOS + { 1'b0, BGHSCR };
-wire [8:0] BGVPOS = VPOS + { 1'b0, BGVSCR };
-
-wire oHB = ( HPOS > 288 ) ? 1 : 0;
-wire oVB = ( VPOS > 224 ) ? 1 : 0;
-
-
-//----------------------------------------
-//  VideoRAM Scanner
-//----------------------------------------
-wire				BF	= ( HPOS >= 224 );
-wire	[8:0]		HP  = BF ? HPOS : BGHPOS;
-wire	[8:0]		VP  = ( BF ? VPOS : BGVPOS ) + 9'h0F;
-
-wire	[10:0]	SPRAADRS;
-wire	[3:0]		ARAMADRS;
-
-reg	[10:0]	VRAMADRS;
-always @ ( HPOS ) begin
-	VRAMADRS <= oHB ? 
-		SPRAADRS :
-		BF ? { 1'b0, VP[7:3], 2'b00, HP[5:3] } : { 1'b1, VP[7:3], HP[7:3] };
-end
-
-wire	[7:0]		CHRC;
-wire	[7:0]		ATTR;
-wire	[7:0]		ARDT;
-
-wire	[7:0]		V0DO, V1DO;
-
-wire				CEV0	= ( ( CPUADDR[15:12] == 4'b1000 ) & (~CPUADDR[11]) ) & CPUME;
-wire				CEV1	= ( ( CPUADDR[15:12] == 4'b1000 ) &   CPUADDR[11]  ) & CPUME;
-wire				CEAT  = (   CPUADDR[15:4]  == 12'b1010_0000_0000         ) & CPUME;
-
-wire	[7:0]		DTV0	= CEV0 ? V0DO : 8'h00;
-wire	[7:0]		DTV1	= CEV1 ? V1DO : 8'h00;
-
-assign			CPUDO = DTV0 | DTV1;
-assign			CPUDT = ( ~CPUWE ) & ( CEV0 | CEV1 );
-
-GDPRAM #(11,8) vram0( VCLKx4, VRAMADRS, CHRC, CPUCLK, CPUADDR[10:0], ( CPUWE & CEV0 ), CPUDI, V0DO );  
-/*dpram #(
-	.widthad_a(11),
-	.width_a(8))
-vram0(
-	.address_a(VRAMADRS),
-	.address_b(CPUADDR[10:0]),
-	.clock_a(VCLKx4),
-	.clock_b(CPUCLK),
-	.data_a(),
-	.data_b(CPUDI),
-	.wren_a(),
-	.wren_b(( CPUWE & CEV0 )),
-	.q_a(CHRC),
-	.q_b(V0DO)
-	);*/
-	
-GDPRAM #(11,8)	vram1( VCLKx4, VRAMADRS, ATTR, CPUCLK, CPUADDR[10:0], ( CPUWE & CEV1 ), CPUDI, V1DO ); 
-/*dpram #(
-	.widthad_a(11),
-	.width_a(8))
-vram1(
-	.address_a(VRAMADRS),
-	.address_b(CPUADDR[10:0]),
-	.clock_a(VCLKx4),
-	.clock_b(CPUCLK),
-	.data_a(),
-	.data_b(CPUDI),
-	.wren_a(),
-	.wren_b(( CPUWE & CEV1 )),
-	.q_a(ATTR),
-	.q_b(V1DO)
-	); */
-GDPRAM #(4,8)	aram0( VCLKx4, ARAMADRS, ARDT, CPUCLK, CPUADDR[3:0],  ( CPUWE & CEAT ), CPUDI );
-/*dpram #(
-	.widthad_a(8),
-	.width_a(4))
-aram0(
-	.address_a(ARAMADRS),
-	.address_b(CPUADDR[3:0]),
-	.clock_a(VCLKx4),
-	.clock_b(CPUCLK),
-	.data_a(),
-	.data_b(CPUDI),
-	.wren_a(),
-	.wren_b(( CPUWE & CEAT )),
-	.q_a(ARDT),
-	.q_b()
-	); */
-	
-wire				BGF = ATTR[5];
-
-
-//----------------------------------------
-//  BG/Sprite chip data reader
-//----------------------------------------
-wire				BGFX = ATTR[6];
-wire	[2:0]		BGFY = { ATTR[7], ATTR[7], ATTR[7] };
-
-wire	[11:0]	SPCHRADR;
-wire	[11:0]	CHRA = oHB ? SPCHRADR : { CHRC, ( HP[2] ^ BGFX ), ( VP[2:0] ^ BGFY ) };
-
-wire	[7:0]		CHRO;
-jng_chr_rom chrrom(
-	.clk(VCLKx4),
-	.addr(CHRA), 
-	.data(CHRO)
-);
-
-//----------------------------------------
-//  Rader-dot chip ROM
-//----------------------------------------
-wire  [7:0] 	DROMAD;
-wire  [7:0] 	DROMDT;
-jng_dot_rom dotrom(
-	.clk(VCLKx4),
-	.addr(DROMAD), 
-	.data(DROMDT)
-	);
-
-//----------------------------------------
-//  BG/FG scanline generator
-//----------------------------------------
-wire [5:0] BGPL = ATTR[5:0];
-reg  [7:0] BGCOL;
-
-always @ ( posedge VCLK ) begin
-	case ( HP[1:0]^{2{BGFX}} )
-		2'b00: BGCOL <= { BGPL, CHRO[4], CHRO[0] };
-		2'b01: BGCOL <= { BGPL, CHRO[5], CHRO[1] };
-		2'b10: BGCOL <= { BGPL, CHRO[6], CHRO[2] };
-		2'b11: BGCOL <= { BGPL, CHRO[7], CHRO[3] };
-	endcase
-end	
-
-
-//----------------------------------------
-//  Sprite Engine
-//----------------------------------------
-wire [8:0] SPCOL;
-NRX_SPRITE speng( 
-	.VCLKx4(VCLKx4), 
-	.HBLK(oHB), 
-	.HPOS(HPOS), 
-	.VPOS(VPOS), 
-	.SPRAADRS(SPRAADRS), 
-	.SPRADATA({ ATTR, CHRC }), 
-	.ARAMADRS(ARAMADRS), 
-	.ARAMDATA(ARDT), 
-	.SPCHRADR(SPCHRADR), 
-	.SPCHRDAT(CHRO), 
-	.DROMAD(DROMAD), 
-	.DROMDT(DROMDT), 
-	.SPCOL(SPCOL) 
-	);
-
-
-//----------------------------------------
-//  Color mixer
-//----------------------------------------
-wire bBGOPAQUE = ( ( BF | BGF ) & (~SPCOL[8]) );
-wire bSPTRANSP = ( SPCOL[1:0] == 2'b00 );
-
-wire	[7:0]		OUTCOL = ( bBGOPAQUE | bSPTRANSP ) ? BGCOL : SPCOL[7:0];
-wire	[3:0]		CLUT;
-jng_col_rom colrom(
-	.clk(~VCLKx4),
-	.addr(OUTCOL), 
-	.data(CLUT)
-	);
-
-wire	[4:0]		PALA = SPCOL[8] ? SPCOL[4:0] : { 1'b0, CLUT };
-wire	[7:0]		PALO;
-
-jng_pal_rom palrom(
-	.clk(VCLKx4),
-	.addr(PALA), 
-	.data(PALO)
-	);
-
-//----------------------------------------
-//  Color output
-//----------------------------------------
-always @ ( posedge PCLK ) POUT <= (oHB|oVB) ? 8'h0 : PALO;
-assign PCLK = VCLK;
-
-
-endmodule
diff --git a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/rallyX_mist.sv b/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/rallyX_mist.sv
deleted file mode 100644
index 066e1192..00000000
--- a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/rallyX_mist.sv	
+++ /dev/null
@@ -1,172 +0,0 @@
-module rallyX_mist (
-	output        LED,
-	output  [5:0] VGA_R,
-	output  [5:0] VGA_G,
-	output  [5:0] VGA_B,
-	output        VGA_HS,
-	output        VGA_VS,
-	output        AUDIO_L,
-	output        AUDIO_R,
-	input         SPI_SCK,
-	output        SPI_DO,
-	input         SPI_DI,
-	input         SPI_SS2,
-	input         SPI_SS3,
-	input         CONF_DATA0,
-	input         CLOCK_27
-);
-
-`include "rtl\build_id.v" 
-
-localparam CONF_STR = {
-	"RallyX;;",
-	"O8A,Difficulty,M1,M2,M3,M4,M5,M6,M7,M8;",
-	"OBC,Bonus Life,M1,M2,M3,Nothing;",
-	"OF,Service Mode,Off,On;",
-	"O34,Scanlines,None,CRT 25%,CRT 50%,CRT 75%;",
-	"O5,Blend ,Off,On;",
-	"T6,Reset;",
-	"V,v1.00.",`BUILD_DATE
-};
-
-assign 		LED = 1;
-assign 		AUDIO_R = AUDIO_L;
-
-wire clock_24, clock_14;
-pll pll(
-	.inclk0(CLOCK_27),
-	.c0(clock_24),//24.576MHz
-	.c1(clock_14)
-	);
-
-wire [31:0] status;
-wire  [1:0] buttons;
-wire  [1:0] switches;
-wire [11:0] kbjoy;
-wire  [7:0] joystick_0;
-wire  [7:0] joystick_1;
-wire        scandoublerD;
-wire        ypbpr;
-wire  [10:0] audio;
-wire 			hs, vs;
-wire 			hb, vb;
-wire 			blankn = ~(hb | vb);
-wire [2:0] 	r, g;
-wire [1:0] 	b;
-wire 			key_strobe;
-wire 			key_pressed;
-wire  [7:0] key_code;
-
-
-wire  [7:0] iDSW  = ~{ 2'b00, status[10:8], status[12:11], status[15] };
-wire  [7:0] iCTR1 = ~{ btn_coin, btn_one_player, m_up1, m_down1, m_right1, m_left1, m_fire1, 1'b0 };
-wire  [7:0] iCTR2 = ~{ btn_coin, btn_two_players, m_up2, m_down2, m_right2, m_left2, m_fire2, 1'b0 };
-
-
-fpga_nrx fpga_nrx(
-	.RESET(status[0] | status[6] | buttons[1]),
-	.CLK24M(clock_24),
-	.CLK14M(clock_14),
-	.hsync(hs),
-	.vsync(vs),
-	.hblank(hb),
-	.vblank(vb),
-	.r(r),
-	.g(g),
-	.b(b),
-	.SND(audio),
-	.DSW(iDSW),
-	.CTR1(iCTR1),
-	.CTR2(iCTR2),
-	.LAMP()
-	);
-
-	
-mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video(
-	.clk_sys        ( clock_24         ),
-	.SPI_SCK        ( SPI_SCK          ),
-	.SPI_SS3        ( SPI_SS3          ),
-	.SPI_DI         ( SPI_DI           ),
-	.R              ( blankn ? r : 0   ),
-	.G              ( blankn ? g : 0   ),
-	.B              ( blankn ? {b,1'b0} : 0   ),
-	.HSync          ( hs               ),
-	.VSync          ( vs               ),
-	.VGA_R          ( VGA_R            ),
-	.VGA_G          ( VGA_G            ),
-	.VGA_B          ( VGA_B            ),
-	.VGA_VS         ( VGA_VS           ),
-	.VGA_HS         ( VGA_HS           ),
-	.blend          ( status[5]        ),
-	.scandoubler_disable( scandoublerD ),
-	.scanlines      ( status[4:3]      ),
-	.ypbpr          ( ypbpr            )
-	);
-	
-user_io #(.STRLEN(($size(CONF_STR)>>3)))user_io(
-	.clk_sys        (clock_24       ),
-	.conf_str       (CONF_STR       ),
-	.SPI_CLK        (SPI_SCK        ),
-	.SPI_SS_IO      (CONF_DATA0     ),
-	.SPI_MISO       (SPI_DO         ),
-	.SPI_MOSI       (SPI_DI         ),
-	.buttons        (buttons        ),
-	.switches       (switches       ),
-	.scandoubler_disable (scandoublerD	  ),
-	.ypbpr          (ypbpr          ),
-	.key_strobe     (key_strobe     ),
-	.key_pressed    (key_pressed    ),
-	.key_code       (key_code       ),
-	.joystick_0     (joystick_0     ),
-	.joystick_1     (joystick_1     ),
-	.status         (status         )
-	);
-
-dac #(.C_bits(11))dac(
-	.clk_i(clock_24),
-	.res_n_i(1),
-	.dac_i(audio),
-	.dac_o(AUDIO_L)
-	);
-	
-wire m_up1     = btn_up | joystick_0[3];
-wire m_down1   = btn_down | joystick_0[2];
-wire m_left1   = btn_left | joystick_0[1];
-wire m_right1  = btn_right | joystick_0[0];
-wire m_fire1   = btn_fire1 | joystick_0[4];
-
-wire m_up2     = joystick_1[3];
-wire m_down2   = joystick_1[2];
-wire m_left2   = joystick_1[1];
-wire m_right2  = joystick_1[0];
-wire m_fire2   = joystick_1[4];
-
-
-reg btn_one_player = 0;
-reg btn_two_players = 0;
-reg btn_left = 0;
-reg btn_right = 0;
-reg btn_down = 0;
-reg btn_up = 0;
-reg btn_fire1 = 0;
-reg btn_coin  = 0;
-
-always @(posedge clock_24) begin
-	reg old_state;
-	old_state <= key_strobe;
-	if(old_state != key_strobe) begin
-		case(key_code)
-			'h75: btn_up         	<= key_pressed; // up
-			'h72: btn_down        	<= key_pressed; // down
-			'h6B: btn_left      		<= key_pressed; // left
-			'h74: btn_right       	<= key_pressed; // right
-			'h76: btn_coin				<= key_pressed; // ESC
-			'h05: btn_one_player   	<= key_pressed; // F1
-			'h06: btn_two_players  	<= key_pressed; // F2
-			'h29: btn_fire1   		<= key_pressed; // Space
-		endcase
-	end
-end
-
-
-endmodule
diff --git a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/rams.v b/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/rams.v
deleted file mode 100644
index 4d579578..00000000
--- a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/rams.v	
+++ /dev/null
@@ -1,64 +0,0 @@
-
-
-
-module GSPRAM #(parameter AW,parameter DW)
-(
-	input							CL,
-	input [(AW-1):0]			AD,
-	input							WE,
-	input [(DW-1):0]			DI,
-	output reg [(DW-1):0]	DO
-);
-
-reg [(DW-1):0] core[0:((2**AW)-1)];
-
-always @(posedge CL) begin
-	DO <= core[AD];
-	if (WE) core[AD] <= DI;
-end
-	
-endmodule
-
-
-module GDPRAM #(parameter AW,parameter DW)
-(
-	input							CL0,
-	input [(AW-1):0]			AD0,
-	output reg [(DW-1):0]	DO0,
-
-	input							CL1,
-	input [(AW-1):0]			AD1,
-	input							WE1,
-	input [(DW-1):0]			DI1,
-	output reg [(DW-1):0]	DO1
-);
-
-reg [(DW-1):0] core[0:((2**AW)-1)];
-
-always @(posedge CL0) DO0 <= core[AD0];
-always @(posedge CL1) begin DO1 <= core[AD1]; if (WE1) core[AD1] <= DI1; end
-
-endmodule
-
-/*
-module GLINEBUF #(parameter AW,parameter DW)
-(
-	input							CL0,
-	input	 [(AW-1):0]			AD0,
-	input							WE0,
-	output reg [(DW-1):0]	DO0,
-
-	input							CL1,
-	input	 [(AW-1):0]			AD1,
-	input							WE1,
-	input	 [(DW-1):0]			DI1
-);
-
-reg [(DW-1):0] core[0:((2**AW)-1)];
-
-always @(posedge CL0) begin DO0 <= core[AD0]; if (WE0) core[AD0] <= 0; end
-always @(posedge CL1) if (WE1) core[AD1] <= DI1;
-
-endmodule*/
-
-
diff --git a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/roms/jng_chr_rom.vhd b/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/roms/jng_chr_rom.vhd
deleted file mode 100644
index 7936c894..00000000
--- a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/roms/jng_chr_rom.vhd	
+++ /dev/null
@@ -1,278 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity jng_chr_rom is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(11 downto 0);
-	data : out std_logic_vector(7 downto 0)
-);
-end entity;
-
-architecture prom of jng_chr_rom is
-	type rom is array(0 to  4095) of std_logic_vector(7 downto 0);
-	signal rom_data: rom := (
-		X"80",X"C0",X"20",X"20",X"60",X"C0",X"80",X"00",X"30",X"70",X"C0",X"80",X"80",X"70",X"30",X"00",
-		X"20",X"20",X"E0",X"E0",X"20",X"20",X"00",X"00",X"00",X"00",X"F0",X"F0",X"40",X"00",X"00",X"00",
-		X"20",X"20",X"A0",X"A0",X"E0",X"E0",X"60",X"00",X"60",X"F0",X"B0",X"90",X"90",X"C0",X"40",X"00",
-		X"C0",X"E0",X"20",X"20",X"20",X"60",X"40",X"00",X"80",X"D0",X"F0",X"B0",X"90",X"80",X"00",X"00",
-		X"80",X"E0",X"E0",X"80",X"80",X"80",X"80",X"00",X"00",X"F0",X"F0",X"C0",X"60",X"30",X"10",X"00",
-		X"C0",X"E0",X"20",X"20",X"20",X"60",X"40",X"00",X"10",X"B0",X"A0",X"A0",X"A0",X"E0",X"E0",X"00",
-		X"C0",X"E0",X"20",X"20",X"20",X"E0",X"C0",X"00",X"00",X"90",X"90",X"90",X"D0",X"70",X"30",X"00",
-		X"00",X"00",X"00",X"E0",X"E0",X"00",X"00",X"00",X"C0",X"E0",X"B0",X"90",X"80",X"C0",X"C0",X"00",
-		X"C0",X"E0",X"A0",X"A0",X"20",X"20",X"C0",X"00",X"00",X"60",X"90",X"90",X"B0",X"F0",X"60",X"00",
-		X"80",X"C0",X"60",X"20",X"20",X"20",X"00",X"00",X"70",X"F0",X"90",X"90",X"90",X"F0",X"60",X"00",
-		X"40",X"40",X"20",X"00",X"00",X"00",X"00",X"00",X"40",X"40",X"80",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"00",X"00",X"00",X"00",X"00",X"10",X"20",X"20",
-		X"40",X"40",X"40",X"00",X"00",X"00",X"00",X"00",X"40",X"40",X"40",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"40",X"40",X"40",X"00",X"00",X"00",X"00",X"00",X"40",X"40",X"40",
-		X"80",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"20",X"20",X"10",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"20",X"40",X"40",X"00",X"00",X"00",X"00",X"00",X"80",X"40",X"40",
-		X"00",X"00",X"00",X"00",X"90",X"F0",X"52",X"61",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"90",X"F0",X"A4",X"68",
-		X"30",X"20",X"28",X"28",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"40",X"41",X"41",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"0C",X"00",X"F0",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"30",X"E0",X"A4",X"78",
-		X"10",X"F0",X"00",X"0C",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"78",X"A4",X"E0",X"30",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"28",X"28",X"20",X"30",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"41",X"41",X"40",X"E0",
-		X"61",X"52",X"F0",X"90",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"68",X"A4",X"F0",X"90",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"C0",X"70",X"52",X"E1",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"00",X"F0",X"80",
-		X"E1",X"52",X"70",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"F0",X"00",X"03",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"81",X"F0",X"D2",X"61",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"18",X"F0",X"B4",X"68",
-		X"30",X"10",X"18",X"18",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"80",X"81",X"81",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"0C",X"00",X"10",X"F0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"70",X"E0",X"A4",X"69",
-		X"F0",X"10",X"00",X"0C",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"69",X"A4",X"E0",X"70",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"18",X"18",X"10",X"30",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"81",X"81",X"80",X"C0",
-		X"61",X"D2",X"F0",X"81",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"68",X"B4",X"F0",X"18",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"E0",X"70",X"52",X"69",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"00",X"80",X"F0",
-		X"69",X"52",X"70",X"E0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"F0",X"80",X"00",X"03",X"00",X"00",X"00",X"00",
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-		X"E0",X"C0",X"80",X"00",X"00",X"08",X"0C",X"0E",X"70",X"30",X"10",X"00",X"00",X"01",X"03",X"07",
-		X"C0",X"80",X"00",X"00",X"08",X"0C",X"0E",X"0F",X"30",X"10",X"00",X"00",X"01",X"03",X"07",X"0F",
-		X"80",X"00",X"00",X"08",X"0C",X"0E",X"0F",X"0D",X"30",X"00",X"00",X"01",X"03",X"07",X"0F",X"0B",
-		X"00",X"00",X"08",X"0C",X"0E",X"0F",X"0D",X"09",X"00",X"00",X"01",X"03",X"07",X"0F",X"0B",X"09",
-		X"00",X"80",X"C0",X"E0",X"E0",X"C0",X"80",X"00",X"00",X"10",X"30",X"70",X"70",X"30",X"10",X"00",
-		X"00",X"00",X"80",X"C0",X"C0",X"80",X"00",X"00",X"00",X"30",X"70",X"F0",X"F0",X"70",X"30",X"00",
-		X"00",X"00",X"80",X"81",X"81",X"00",X"00",X"00",X"00",X"70",X"F0",X"F0",X"F0",X"F0",X"E0",X"00",
-		X"00",X"00",X"01",X"03",X"03",X"01",X"00",X"00",X"00",X"E0",X"F0",X"F0",X"F0",X"E0",X"C0",X"00",
-		X"00",X"01",X"03",X"07",X"07",X"03",X"01",X"00",X"00",X"80",X"C0",X"E0",X"E0",X"C0",X"80",X"00",
-		X"01",X"03",X"07",X"0F",X"0F",X"07",X"03",X"01",X"00",X"00",X"80",X"C0",X"C0",X"80",X"00",X"00",
-		X"03",X"06",X"0F",X"0F",X"0F",X"0F",X"06",X"03",X"00",X"00",X"00",X"81",X"81",X"80",X"00",X"00",
-		X"07",X"0C",X"0E",X"0F",X"0F",X"0E",X"0C",X"07",X"00",X"00",X"01",X"03",X"03",X"01",X"00",X"00",
-		X"C0",X"E0",X"F0",X"F0",X"E0",X"C0",X"00",X"00",X"00",X"10",X"30",X"30",X"10",X"00",X"00",X"00",
-		X"80",X"C0",X"E0",X"E0",X"C0",X"80",X"00",X"00",X"10",X"30",X"70",X"70",X"30",X"10",X"00",X"00",
-		X"C0",X"E0",X"E0",X"C1",X"81",X"00",X"00",X"00",X"30",X"70",X"70",X"30",X"10",X"00",X"00",X"00",
-		X"E0",X"E0",X"C1",X"83",X"03",X"01",X"00",X"00",X"70",X"70",X"30",X"10",X"00",X"00",X"00",X"00",
-		X"E0",X"C1",X"83",X"07",X"07",X"03",X"01",X"00",X"70",X"30",X"10",X"00",X"00",X"00",X"00",X"00",
-		X"C1",X"83",X"07",X"0F",X"0F",X"07",X"03",X"01",X"30",X"10",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"83",X"06",X"0F",X"0F",X"0F",X"0F",X"06",X"03",X"10",X"00",X"00",X"01",X"01",X"00",X"00",X"00",
-		X"07",X"0C",X"0E",X"0F",X"0F",X"0E",X"0C",X"07",X"00",X"00",X"01",X"03",X"03",X"01",X"00",X"00",
-		X"C0",X"E0",X"F0",X"F0",X"E0",X"C0",X"00",X"00",X"00",X"10",X"30",X"30",X"10",X"00",X"00",X"00",
-		X"00",X"C0",X"E0",X"F0",X"F0",X"E0",X"C0",X"00",X"00",X"00",X"10",X"30",X"30",X"10",X"00",X"00",
-		X"08",X"60",X"F0",X"F0",X"F0",X"F0",X"60",X"00",X"01",X"00",X"00",X"10",X"10",X"00",X"00",X"00",
-		X"0C",X"38",X"70",X"F0",X"F0",X"70",X"30",X"00",X"03",X"01",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"0E",X"1C",X"38",X"70",X"70",X"30",X"10",X"00",X"07",X"03",X"01",X"00",X"00",X"00",X"00",X"00",
-		X"0F",X"0E",X"1C",X"38",X"30",X"10",X"00",X"00",X"0F",X"07",X"03",X"01",X"00",X"00",X"00",X"00",
-		X"0D",X"0F",X"0E",X"1C",X"18",X"00",X"00",X"00",X"0B",X"0F",X"07",X"03",X"01",X"00",X"00",X"00",
-		X"09",X"0D",X"0F",X"0E",X"0C",X"08",X"00",X"00",X"09",X"0B",X"0F",X"07",X"03",X"01",X"00",X"00",
-		X"00",X"80",X"C0",X"E0",X"F0",X"D0",X"90",X"20",X"00",X"10",X"30",X"70",X"F0",X"B0",X"90",X"40",
-		X"80",X"C0",X"E0",X"F0",X"D0",X"90",X"20",X"00",X"10",X"30",X"70",X"F0",X"B0",X"90",X"40",X"00",
-		X"C0",X"E0",X"F0",X"D0",X"90",X"20",X"00",X"00",X"30",X"70",X"F0",X"B0",X"90",X"40",X"00",X"00",
-		X"E0",X"F0",X"D0",X"90",X"20",X"00",X"00",X"00",X"70",X"F0",X"B0",X"90",X"40",X"00",X"00",X"00",
-		X"F0",X"D0",X"90",X"20",X"00",X"00",X"00",X"00",X"F0",X"B0",X"90",X"40",X"00",X"00",X"00",X"00",
-		X"D0",X"90",X"20",X"00",X"00",X"00",X"00",X"00",X"B0",X"90",X"40",X"00",X"00",X"00",X"00",X"00",
-		X"90",X"20",X"00",X"00",X"00",X"00",X"00",X"00",X"90",X"40",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"20",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"E0",X"90",X"C0",X"E0",X"E0",X"C0",X"90",X"E0",X"00",X"10",X"30",X"70",X"70",X"30",X"10",X"00",
-		X"C0",X"20",X"80",X"C0",X"C0",X"80",X"20",X"C0",X"10",X"30",X"70",X"F0",X"F0",X"70",X"30",X"10",
-		X"80",X"40",X"00",X"80",X"80",X"00",X"40",X"80",X"30",X"60",X"F0",X"F0",X"F0",X"F0",X"60",X"30",
-		X"00",X"80",X"00",X"00",X"00",X"00",X"80",X"00",X"70",X"C0",X"E0",X"F0",X"F0",X"E0",X"C0",X"70",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"E0",X"90",X"C0",X"E0",X"E0",X"C0",X"90",X"E0",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"20",X"80",X"C0",X"C0",X"80",X"20",X"C0",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"40",X"00",X"80",X"80",X"00",X"40",X"80",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"00",X"00",X"00",X"00",X"80",X"00",
-		X"80",X"C0",X"E0",X"F0",X"D0",X"90",X"20",X"00",X"10",X"30",X"70",X"F0",X"B0",X"90",X"40",X"00",
-		X"80",X"C0",X"E0",X"F0",X"D0",X"90",X"20",X"00",X"10",X"30",X"70",X"F0",X"B0",X"90",X"40",X"00",
-		X"C0",X"E0",X"F0",X"D0",X"90",X"20",X"00",X"00",X"30",X"70",X"F0",X"B0",X"90",X"40",X"00",X"00",
-		X"E0",X"F0",X"D0",X"90",X"20",X"00",X"00",X"00",X"70",X"F0",X"B0",X"90",X"40",X"00",X"00",X"00",
-		X"F0",X"D0",X"90",X"20",X"00",X"00",X"00",X"00",X"F0",X"B0",X"90",X"40",X"00",X"00",X"00",X"00",
-		X"D0",X"90",X"20",X"00",X"00",X"00",X"00",X"00",X"B0",X"90",X"40",X"00",X"00",X"00",X"00",X"00",
-		X"90",X"20",X"00",X"00",X"00",X"00",X"00",X"00",X"90",X"40",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"20",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"80",X"C0",X"E0",X"F0",X"F0",X"E0",X"C0",X"80",X"30",X"40",X"10",X"30",X"30",X"10",X"40",X"30",
-		X"80",X"C0",X"E0",X"F0",X"F0",X"E0",X"C0",X"80",X"30",X"40",X"10",X"30",X"30",X"10",X"40",X"30",
-		X"C0",X"60",X"F0",X"F0",X"F0",X"F0",X"60",X"C0",X"10",X"20",X"00",X"10",X"10",X"00",X"20",X"10",
-		X"E0",X"30",X"70",X"F0",X"F0",X"70",X"30",X"E0",X"00",X"10",X"00",X"00",X"00",X"00",X"10",X"00",
-		X"70",X"90",X"30",X"70",X"70",X"30",X"90",X"70",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"30",X"40",X"10",X"30",X"30",X"10",X"40",X"30",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"10",X"20",X"00",X"10",X"10",X"00",X"20",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"10",X"00",X"00",X"00",X"00",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"50",X"A0",X"50",X"A0",X"50",X"A0",X"F0",X"00",X"50",X"60",X"50",X"60",X"50",X"20",X"10",X"00",
-		X"00",X"F0",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"00",X"10",X"20",X"50",X"60",X"50",X"60",X"50",
-		X"A0",X"60",X"A0",X"60",X"A0",X"40",X"80",X"00",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"F0",X"00",
-		X"00",X"80",X"40",X"A0",X"60",X"A0",X"60",X"A0",X"00",X"F0",X"50",X"A0",X"50",X"A0",X"50",X"A0",
-		X"A0",X"50",X"A0",X"50",X"A0",X"50",X"F0",X"00",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"F0",X"00",
-		X"00",X"F0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"00",X"F0",X"50",X"A0",X"50",X"A0",X"50",X"A0",
-		X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"60",X"50",X"60",X"50",X"60",X"50",X"60",X"50",
-		X"60",X"A0",X"60",X"A0",X"60",X"A0",X"60",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",
-		X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"20",
-		X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"20",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",
-		X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"40",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",
-		X"40",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",
-		X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",
-		X"C0",X"20",X"50",X"90",X"90",X"50",X"20",X"C0",X"30",X"40",X"A0",X"90",X"90",X"A0",X"40",X"30",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"20",X"40",X"20",X"90",X"20",X"40",X"20",X"90",X"50",X"A0",X"50",X"20",X"50",X"A0",X"50",X"20",
-		X"20",X"50",X"A0",X"50",X"80",X"20",X"50",X"80",X"20",X"50",X"A0",X"50",X"80",X"20",X"50",X"80",
-		X"20",X"50",X"A0",X"50",X"00",X"20",X"10",X"A0",X"20",X"90",X"40",X"20",X"50",X"A0",X"50",X"20",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/roms/jng_col_rom.vhd b/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/roms/jng_col_rom.vhd
deleted file mode 100644
index 49e9603b..00000000
--- a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/roms/jng_col_rom.vhd	
+++ /dev/null
@@ -1,38 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity jng_col_rom is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(7 downto 0);
-	data : out std_logic_vector(7 downto 0)
-);
-end entity;
-
-architecture prom of jng_col_rom is
-	type rom is array(0 to  255) of std_logic_vector(7 downto 0);
-	signal rom_data: rom := (
-		X"00",X"00",X"00",X"0F",X"00",X"00",X"01",X"0F",X"00",X"00",X"02",X"0F",X"00",X"00",X"04",X"0F",
-		X"00",X"00",X"0C",X"0F",X"00",X"00",X"0E",X"0F",X"00",X"00",X"0F",X"0F",X"00",X"01",X"00",X"0F",
-		X"00",X"01",X"01",X"0F",X"00",X"01",X"02",X"0F",X"00",X"01",X"04",X"0F",X"00",X"01",X"0C",X"0F",
-		X"00",X"01",X"0E",X"0F",X"00",X"01",X"0F",X"0F",X"00",X"02",X"00",X"0F",X"00",X"02",X"01",X"0F",
-		X"00",X"02",X"02",X"0F",X"00",X"02",X"04",X"0F",X"00",X"02",X"0C",X"0F",X"00",X"02",X"0E",X"0F",
-		X"00",X"02",X"0F",X"0F",X"00",X"04",X"00",X"0F",X"00",X"04",X"01",X"0F",X"00",X"04",X"02",X"0F",
-		X"00",X"04",X"04",X"0F",X"00",X"04",X"0C",X"0F",X"00",X"04",X"0E",X"0F",X"00",X"04",X"0F",X"0F",
-		X"00",X"0C",X"00",X"0F",X"00",X"0C",X"01",X"0F",X"00",X"0C",X"02",X"0F",X"00",X"0C",X"04",X"0F",
-		X"00",X"0C",X"0C",X"0F",X"00",X"0C",X"0E",X"0F",X"00",X"0C",X"0F",X"0F",X"00",X"0E",X"00",X"0F",
-		X"00",X"0E",X"01",X"0F",X"00",X"0E",X"02",X"0F",X"00",X"0E",X"04",X"0F",X"00",X"0E",X"0C",X"0F",
-		X"00",X"0E",X"0E",X"0F",X"00",X"0E",X"0F",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"01",X"0F",
-		X"00",X"0F",X"02",X"0F",X"00",X"0F",X"04",X"0F",X"00",X"0F",X"0C",X"0F",X"00",X"0F",X"0E",X"0F",
-		X"00",X"0F",X"0F",X"0F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"01",X"02",X"09",X"00",X"0F",X"09",X"02",X"00",X"02",X"01",X"04",
-		X"00",X"0C",X"0F",X"0A",X"00",X"07",X"05",X"08",X"00",X"0D",X"04",X"06",X"00",X"02",X"04",X"0B");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/roms/jng_dot_rom.vhd b/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/roms/jng_dot_rom.vhd
deleted file mode 100644
index 74c632c5..00000000
--- a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/roms/jng_dot_rom.vhd	
+++ /dev/null
@@ -1,38 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity jng_dot_rom is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(7 downto 0);
-	data : out std_logic_vector(7 downto 0)
-);
-end entity;
-
-architecture prom of jng_dot_rom is
-	type rom is array(0 to  255) of std_logic_vector(7 downto 0);
-	signal rom_data: rom := (
-		X"00",X"00",X"00",X"00",X"00",X"02",X"02",X"00",X"00",X"02",X"02",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"02",X"02",X"00",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"00",X"02",X"02",X"00",
-		X"00",X"02",X"02",X"00",X"02",X"01",X"01",X"02",X"02",X"01",X"01",X"02",X"00",X"02",X"02",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"02",X"00",X"00",X"02",X"02",X"02",X"00",X"00",X"02",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"00",X"00",X"01",X"01",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"01",X"01",X"00",X"01",X"01",X"01",X"01",X"01",X"00",X"01",X"01",X"00",X"01",X"01",X"00",
-		X"00",X"01",X"01",X"00",X"01",X"02",X"02",X"01",X"01",X"02",X"02",X"01",X"00",X"01",X"01",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"01",X"00",X"00",X"01",X"01",X"01",X"00",X"00",X"01",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"02",X"02",X"00",X"00",X"02",X"02",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"02",X"02",X"00",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"00",X"02",X"02",X"00",
-		X"00",X"02",X"02",X"00",X"02",X"01",X"01",X"02",X"02",X"01",X"01",X"02",X"00",X"02",X"02",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"02",X"00",X"00",X"02",X"02",X"02",X"00",X"00",X"02",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"00",X"00",X"01",X"01",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"01",X"01",X"00",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"00",X"01",X"01",X"00",
-		X"00",X"01",X"01",X"00",X"01",X"02",X"02",X"01",X"01",X"02",X"02",X"01",X"00",X"01",X"01",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"01",X"00",X"00",X"01",X"01",X"01",X"00",X"00",X"01",X"00",X"00");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/roms/jng_pal_rom.vhd b/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/roms/jng_pal_rom.vhd
deleted file mode 100644
index 78dca849..00000000
--- a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/roms/jng_pal_rom.vhd	
+++ /dev/null
@@ -1,24 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity jng_pal_rom is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(4 downto 0);
-	data : out std_logic_vector(7 downto 0)
-);
-end entity;
-
-architecture prom of jng_pal_rom is
-	type rom is array(0 to  31) of std_logic_vector(7 downto 0);
-	signal rom_data: rom := (
-		X"00",X"07",X"38",X"3C",X"3F",X"8C",X"E0",X"27",X"AA",X"8C",X"1F",X"B6",X"C0",X"C7",X"F8",X"FE",
-		X"00",X"3F",X"FE",X"67",X"00",X"3F",X"FE",X"67",X"00",X"3F",X"FE",X"67",X"00",X"3F",X"FE",X"67");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/roms/jng_prg_rom.vhd b/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/roms/jng_prg_rom.vhd
deleted file mode 100644
index 7b2b0c96..00000000
--- a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/roms/jng_prg_rom.vhd	
+++ /dev/null
@@ -1,1046 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity jng_prg_rom is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(13 downto 0);
-	data : out std_logic_vector(7 downto 0)
-);
-end entity;
-
-architecture prom of jng_prg_rom is
-	type rom is array(0 to  16383) of std_logic_vector(7 downto 0);
-	signal rom_data: rom := (
-		X"AF",X"32",X"81",X"A1",X"C3",X"24",X"14",X"FF",X"85",X"6F",X"D0",X"24",X"C9",X"FF",X"FF",X"FF",
-		X"7B",X"C6",X"20",X"5F",X"D0",X"14",X"C9",X"FF",X"87",X"CF",X"5E",X"23",X"56",X"C9",X"FF",X"FF",
-		X"7D",X"D6",X"20",X"6F",X"D0",X"25",X"C9",X"FF",X"7B",X"D6",X"20",X"5F",X"D0",X"15",X"C9",X"FF",
-		X"E1",X"DF",X"EB",X"E9",X"FF",X"FF",X"FF",X"FF",X"7E",X"FE",X"40",X"C8",X"12",X"23",X"D7",X"18",
-		X"F7",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"AF",X"32",X"81",X"A1",X"32",X"80",X"A0",X"3A",X"2C",X"99",
-		X"32",X"30",X"A1",X"3A",X"2D",X"99",X"32",X"40",X"A1",X"21",X"00",X"9C",X"11",X"14",X"80",X"01",
-		X"0C",X"00",X"ED",X"B0",X"21",X"10",X"9C",X"11",X"14",X"88",X"01",X"0C",X"00",X"ED",X"B0",X"21",
-		X"24",X"9C",X"11",X"34",X"80",X"01",X"08",X"00",X"ED",X"B0",X"21",X"34",X"9C",X"11",X"34",X"88",
-		X"01",X"08",X"00",X"ED",X"B0",X"21",X"44",X"9C",X"11",X"34",X"A0",X"01",X"08",X"00",X"ED",X"B0",
-		X"CD",X"5E",X"2D",X"CD",X"84",X"2D",X"3A",X"00",X"A0",X"2F",X"32",X"03",X"98",X"3A",X"80",X"A0",
-		X"2F",X"32",X"04",X"98",X"3A",X"00",X"A1",X"2F",X"32",X"05",X"98",X"CD",X"C2",X"2F",X"CD",X"0E",
-		X"30",X"CD",X"DB",X"2F",X"21",X"E8",X"00",X"E5",X"3A",X"20",X"99",X"F7",X"D4",X"01",X"01",X"04",
-		X"D0",X"07",X"35",X"0A",X"D0",X"0C",X"6B",X"0E",X"CD",X"69",X"30",X"CD",X"8D",X"30",X"CD",X"5F",
-		X"33",X"21",X"02",X"98",X"34",X"21",X"00",X"98",X"7E",X"A7",X"28",X"01",X"35",X"2A",X"06",X"98",
-		X"7C",X"B5",X"28",X"04",X"2B",X"22",X"06",X"98",X"3E",X"01",X"32",X"81",X"A1",X"C9",X"4A",X"55",
-		X"4E",X"47",X"4C",X"45",X"52",X"40",X"43",X"52",X"45",X"44",X"49",X"54",X"40",X"4C",X"4F",X"4F",
-		X"50",X"20",X"40",X"42",X"4F",X"4D",X"42",X"20",X"54",X"49",X"4D",X"45",X"52",X"20",X"40",X"48",
-		X"49",X"20",X"53",X"43",X"4F",X"52",X"45",X"40",X"50",X"55",X"53",X"48",X"20",X"53",X"54",X"41",
-		X"52",X"54",X"20",X"42",X"55",X"54",X"54",X"4F",X"4E",X"40",X"4F",X"4E",X"45",X"20",X"50",X"4C",
-		X"41",X"59",X"45",X"52",X"20",X"4F",X"4E",X"4C",X"59",X"20",X"20",X"20",X"40",X"4F",X"4E",X"45",
-		X"20",X"4F",X"52",X"20",X"54",X"57",X"4F",X"20",X"50",X"4C",X"41",X"59",X"45",X"52",X"53",X"40",
-		X"4F",X"4E",X"45",X"40",X"54",X"57",X"4F",X"40",X"01",X"55",X"50",X"40",X"02",X"55",X"50",X"40",
-		X"47",X"41",X"4D",X"45",X"20",X"4F",X"56",X"45",X"52",X"40",X"53",X"43",X"4F",X"52",X"45",X"20",
-		X"52",X"41",X"4E",X"4B",X"49",X"4E",X"47",X"40",X"50",X"4C",X"41",X"59",X"45",X"52",X"40",X"45",
-		X"4E",X"44",X"40",X"45",X"4E",X"45",X"4D",X"59",X"40",X"50",X"4F",X"49",X"4E",X"54",X"53",X"40",
-		X"5C",X"20",X"4B",X"4F",X"4E",X"41",X"4D",X"49",X"20",X"01",X"09",X"08",X"01",X"40",X"50",X"4C",
-		X"41",X"59",X"45",X"52",X"20",X"4F",X"4E",X"45",X"40",X"50",X"4C",X"41",X"59",X"45",X"52",X"20",
-		X"54",X"57",X"4F",X"40",X"21",X"F0",X"01",X"E5",X"3A",X"21",X"99",X"F7",X"F1",X"01",X"1B",X"02",
-		X"27",X"02",X"34",X"02",X"44",X"02",X"56",X"02",X"67",X"02",X"6E",X"02",X"97",X"02",X"F8",X"02",
-		X"C9",X"3E",X"01",X"32",X"83",X"A1",X"32",X"2F",X"99",X"CD",X"0A",X"02",X"CD",X"05",X"1B",X"3E",
-		X"1E",X"32",X"00",X"98",X"CD",X"1B",X"03",X"C3",X"FC",X"03",X"CD",X"84",X"1A",X"21",X"0E",X"01",
-		X"11",X"85",X"81",X"0E",X"BA",X"CD",X"DA",X"16",X"C3",X"48",X"30",X"3A",X"00",X"98",X"A7",X"C0",
-		X"CD",X"D1",X"1A",X"C0",X"C3",X"FC",X"03",X"3A",X"23",X"99",X"A7",X"CA",X"FC",X"03",X"3E",X"07",
-		X"32",X"21",X"99",X"C9",X"3A",X"23",X"99",X"A7",X"20",X"F4",X"AF",X"32",X"21",X"99",X"3E",X"05",
-		X"32",X"20",X"99",X"C9",X"3A",X"23",X"99",X"A7",X"20",X"E4",X"CD",X"B9",X"19",X"D8",X"3E",X"FF",
-		X"32",X"00",X"98",X"C3",X"FC",X"03",X"3A",X"23",X"99",X"A7",X"20",X"05",X"3A",X"00",X"98",X"A7",
-		X"C0",X"CD",X"1B",X"03",X"C3",X"FC",X"03",X"CD",X"D1",X"1A",X"C0",X"C3",X"FC",X"03",X"3A",X"23",
-		X"99",X"A7",X"20",X"0A",X"AF",X"32",X"21",X"99",X"3E",X"04",X"32",X"20",X"99",X"C9",X"3E",X"01",
-		X"32",X"83",X"A1",X"32",X"2F",X"99",X"21",X"38",X"01",X"11",X"16",X"85",X"0E",X"A3",X"CD",X"DA",
-		X"16",X"CD",X"17",X"0F",X"C3",X"FC",X"03",X"CD",X"75",X"03",X"11",X"15",X"85",X"3A",X"23",X"99",
-		X"FE",X"01",X"20",X"05",X"21",X"4A",X"01",X"18",X"03",X"21",X"5D",X"01",X"0E",X"A3",X"CD",X"DA",
-		X"16",X"3A",X"04",X"98",X"E6",X"C0",X"C8",X"21",X"23",X"99",X"E6",X"80",X"28",X"0C",X"7E",X"D6",
-		X"01",X"27",X"77",X"3E",X"00",X"32",X"10",X"99",X"18",X"13",X"7E",X"FE",X"02",X"D8",X"D6",X"01",
-		X"27",X"D6",X"01",X"27",X"77",X"CD",X"4E",X"03",X"3E",X"01",X"32",X"10",X"99",X"AF",X"32",X"11",
-		X"99",X"CD",X"27",X"03",X"CD",X"48",X"30",X"CD",X"AD",X"1A",X"CD",X"FB",X"33",X"3E",X"1E",X"32",
-		X"00",X"98",X"CD",X"1B",X"03",X"C3",X"FC",X"03",X"3A",X"00",X"98",X"A7",X"C0",X"CD",X"D1",X"1A",
-		X"C0",X"21",X"A2",X"88",X"11",X"20",X"00",X"06",X"03",X"36",X"8E",X"19",X"10",X"FB",X"21",X"62",
-		X"8B",X"06",X"03",X"36",X"8E",X"19",X"10",X"FB",X"C3",X"F4",X"03",X"3E",X"20",X"32",X"01",X"98",
-		X"21",X"00",X"84",X"22",X"52",X"98",X"C9",X"3E",X"03",X"32",X"00",X"9F",X"AF",X"32",X"01",X"9F",
-		X"32",X"02",X"9F",X"32",X"0A",X"9F",X"3A",X"34",X"99",X"A7",X"28",X"05",X"3E",X"FF",X"32",X"00",
-		X"9F",X"21",X"01",X"9F",X"34",X"CD",X"94",X"03",X"3E",X"0A",X"32",X"03",X"9F",X"C9",X"3E",X"03",
-		X"32",X"40",X"9F",X"AF",X"32",X"41",X"9F",X"32",X"42",X"9F",X"32",X"4A",X"9F",X"3A",X"34",X"99",
-		X"A7",X"28",X"05",X"3E",X"FF",X"32",X"40",X"9F",X"21",X"41",X"9F",X"34",X"CD",X"AB",X"03",X"3E",
-		X"0A",X"32",X"43",X"9F",X"C9",X"21",X"00",X"99",X"06",X"10",X"36",X"00",X"23",X"10",X"FB",X"21",
-		X"00",X"9F",X"06",X"10",X"36",X"00",X"23",X"10",X"FB",X"21",X"40",X"9F",X"06",X"10",X"36",X"00",
-		X"23",X"10",X"FB",X"C9",X"7E",X"FE",X"19",X"38",X"02",X"3E",X"17",X"21",X"C2",X"03",X"CF",X"7E",
-		X"32",X"08",X"9F",X"3E",X"19",X"CF",X"7E",X"32",X"09",X"9F",X"C9",X"7E",X"FE",X"19",X"38",X"02",
-		X"3E",X"17",X"21",X"C2",X"03",X"CF",X"7E",X"32",X"48",X"9F",X"3E",X"19",X"CF",X"7E",X"32",X"49",
-		X"9F",X"C9",X"00",X"03",X"04",X"05",X"04",X"05",X"06",X"07",X"04",X"07",X"07",X"07",X"05",X"07",
-		X"07",X"07",X"05",X"08",X"08",X"08",X"06",X"08",X"08",X"08",X"07",X"00",X"02",X"03",X"04",X"03",
-		X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"04",X"05",X"05",X"05",X"04",X"06",X"06",X"06",X"04",
-		X"07",X"07",X"07",X"04",X"21",X"20",X"99",X"34",X"23",X"36",X"00",X"C9",X"21",X"21",X"99",X"34",
-		X"C9",X"21",X"1F",X"04",X"E5",X"3A",X"21",X"99",X"F7",X"20",X"04",X"42",X"04",X"52",X"04",X"8F",
-		X"04",X"F3",X"04",X"3F",X"05",X"16",X"06",X"8B",X"06",X"A6",X"06",X"B6",X"06",X"D2",X"06",X"C9",
-		X"AF",X"32",X"08",X"98",X"3C",X"32",X"83",X"A1",X"32",X"2F",X"99",X"21",X"00",X"9F",X"7E",X"A7",
-		X"28",X"04",X"35",X"C3",X"FC",X"03",X"21",X"0A",X"9F",X"7E",X"36",X"00",X"32",X"04",X"9F",X"C3",
-		X"FC",X"03",X"3A",X"01",X"9F",X"32",X"01",X"99",X"CD",X"84",X"32",X"C0",X"CD",X"C3",X"1A",X"C3",
-		X"FC",X"03",X"CD",X"B8",X"1A",X"CD",X"0A",X"02",X"CD",X"8F",X"31",X"3A",X"10",X"99",X"A7",X"20",
-		X"29",X"21",X"2F",X"01",X"11",X"C2",X"82",X"CD",X"E7",X"30",X"21",X"2F",X"01",X"11",X"C1",X"82",
-		X"CD",X"E7",X"30",X"CD",X"DD",X"04",X"21",X"00",X"9F",X"11",X"00",X"99",X"01",X"10",X"00",X"ED",
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-		X"37",X"32",X"08",X"9C",X"21",X"00",X"05",X"22",X"15",X"99",X"22",X"1A",X"99",X"C3",X"FE",X"30",
-		X"3D",X"32",X"18",X"98",X"C0",X"AF",X"32",X"18",X"9C",X"C9",X"3A",X"02",X"99",X"A7",X"C0",X"2F",
-		X"32",X"02",X"99",X"D9",X"21",X"00",X"99",X"34",X"CD",X"06",X"19",X"CD",X"F7",X"33",X"D9",X"C9",
-		X"3A",X"04",X"99",X"A7",X"C8",X"3A",X"02",X"98",X"E6",X"1F",X"C0",X"CD",X"A5",X"2F",X"E6",X"07",
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-		X"98",X"21",X"60",X"98",X"86",X"77",X"D0",X"21",X"8A",X"9A",X"11",X"8B",X"9A",X"01",X"0B",X"00",
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-		X"ED",X"B8",X"21",X"55",X"9B",X"11",X"57",X"9B",X"01",X"16",X"00",X"ED",X"B8",X"2A",X"40",X"9B",
-		X"11",X"20",X"00",X"19",X"22",X"40",X"9B",X"C9",X"3A",X"03",X"99",X"A7",X"28",X"2A",X"FE",X"08",
-		X"D0",X"21",X"A4",X"8B",X"11",X"E0",X"FF",X"47",X"4F",X"36",X"96",X"19",X"10",X"FB",X"21",X"44",
-		X"8B",X"36",X"A4",X"21",X"A4",X"83",X"47",X"36",X"38",X"19",X"10",X"FB",X"3E",X"07",X"91",X"D8",
-		X"C8",X"47",X"36",X"20",X"19",X"10",X"FB",X"C9",X"21",X"A4",X"83",X"11",X"E0",X"FF",X"06",X"08",
-		X"36",X"20",X"19",X"10",X"FB",X"C9",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/roms/jng_snd_rom.vhd b/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/roms/jng_snd_rom.vhd
deleted file mode 100644
index daa71a58..00000000
--- a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/roms/jng_snd_rom.vhd	
+++ /dev/null
@@ -1,278 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity jng_snd_rom is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(11 downto 0);
-	data : out std_logic_vector(7 downto 0)
-);
-end entity;
-
-architecture prom of jng_snd_rom is
-	type rom is array(0 to  4095) of std_logic_vector(7 downto 0);
-	signal rom_data: rom := (
-		X"21",X"00",X"20",X"06",X"00",X"C3",X"B2",X"01",X"32",X"00",X"50",X"3A",X"00",X"40",X"C9",X"FF",
-		X"32",X"00",X"70",X"3A",X"00",X"60",X"C9",X"FF",X"78",X"CF",X"79",X"32",X"00",X"40",X"C9",X"FF",
-		X"78",X"D7",X"79",X"32",X"00",X"60",X"C9",X"FF",X"87",X"85",X"6F",X"7C",X"CE",X"00",X"67",X"7E",
-		X"23",X"66",X"6F",X"E9",X"FF",X"FF",X"FF",X"FF",X"D9",X"08",X"CD",X"40",X"00",X"08",X"D9",X"C9",
-		X"3E",X"0E",X"CF",X"B7",X"28",X"09",X"F2",X"79",X"00",X"CB",X"BF",X"CD",X"6C",X"00",X"C9",X"21",
-		X"00",X"20",X"06",X"0C",X"AF",X"77",X"23",X"10",X"FC",X"C9",X"21",X"00",X"20",X"06",X"06",X"0E",
-		X"07",X"BE",X"28",X"05",X"23",X"23",X"10",X"F9",X"41",X"79",X"90",X"C9",X"CD",X"5A",X"00",X"C8",
-		X"AF",X"77",X"23",X"77",X"C9",X"13",X"23",X"22",X"28",X"32",X"1A",X"20",X"CD",X"5A",X"00",X"28",
-		X"04",X"23",X"36",X"00",X"C9",X"3A",X"1A",X"20",X"21",X"75",X"00",X"06",X"02",X"BE",X"28",X"19",
-		X"23",X"10",X"FA",X"06",X"02",X"BE",X"28",X"21",X"23",X"10",X"FA",X"AF",X"CD",X"5A",X"00",X"28",
-		X"3A",X"3A",X"1A",X"20",X"77",X"23",X"36",X"00",X"C9",X"AF",X"CD",X"5A",X"00",X"28",X"05",X"FE",
-		X"04",X"FA",X"C9",X"00",X"CD",X"37",X"01",X"18",X"58",X"AF",X"CD",X"5A",X"00",X"28",X"05",X"FE",
-		X"04",X"F2",X"C9",X"00",X"CD",X"62",X"01",X"18",X"40",X"21",X"1A",X"20",X"46",X"0E",X"00",X"21",
-		X"00",X"20",X"3D",X"87",X"5F",X"51",X"19",X"70",X"23",X"71",X"C9",X"CD",X"37",X"01",X"CD",X"62",
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-		X"70",X"73",X"B5",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/roms/jungler.zip b/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/roms/jungler.zip
deleted file mode 100644
index 8cfd2780..00000000
Binary files a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/roms/jungler.zip and /dev/null differ
diff --git a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/roms/make_jungler_proms.bat b/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/roms/make_jungler_proms.bat
deleted file mode 100644
index b93d9228..00000000
--- a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/roms/make_jungler_proms.bat	
+++ /dev/null
@@ -1,15 +0,0 @@
-copy /B jungr1 + jungr2 + jungr3 + jungr4 JUNGLER.ROM
-make_vhdl_prom JUNGLER.ROM jng_prg_rom.vhd
-
-copy /B 5k + 5m gfx1.bin
-make_vhdl_prom gfx1.bin jng_chr_rom.vhd
-
-make_vhdl_prom 82s129.10g jng_dot_rom.vhd
-
-make_vhdl_prom 1b jng_snd_rom.vhd
-
-
-
-make_vhdl_prom 18s030.8b jng_pal_rom.vhd
-make_vhdl_prom tbp24s10.9d jng_col_rom.vhd
-
diff --git a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/time_pilot_sound_board.vhd b/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/time_pilot_sound_board.vhd
deleted file mode 100644
index 3043d74a..00000000
--- a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/time_pilot_sound_board.vhd	
+++ /dev/null
@@ -1,426 +0,0 @@
----------------------------------------------------------------------------------
--- Time pilot sound board by Dar (darfpga@aol.fr) (29/10/2017)
--- http://darfpga.blogspot.fr
----------------------------------------------------------------------------------
--- gen_ram.vhd
--------------------------------- 
--- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
--- http://www.syntiac.com/fpga64.html
----------------------------------------------------------------------------------
--- T80/T80se - Version : 0247
------------------------------
--- Z80 compatible microprocessor core
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
----------------------------------------------------------------------------------
--- YM2149 (AY-3-8910)
--- Copyright (c) MikeJ - Jan 2005
----------------------------------------------------------------------------------
--- Educational use only
--- Do not redistribute synthetized file with roms
--- Do not redistribute roms whatever the form
--- Use at your own risk
----------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.numeric_std.all;
-
-entity time_pilot_sound_board is
-port(
- clock_14     : in std_logic;
- reset        : in std_logic;
-
- sound_cmd    : in std_logic_vector(7 downto 0);
- sound_trig   : in std_logic;
- 
- audio_out    : out std_logic_vector(10 downto 0);
- 
- dbg_cpu_addr : out std_logic_vector(15 downto 0)
- );
-end time_pilot_sound_board;
-
-architecture struct of time_pilot_sound_board is
-
- signal reset_n: std_logic;
- signal clock_14n : std_logic;
- 
- signal clock_div1 : std_logic_vector(11 downto 0) := (others => '0');
- signal biquinary_div : std_logic_vector(3 downto 0) := (others => '0');
- 
- signal cpu_clock  : std_logic;
- signal ayx_clock  : std_logic;
-
- signal cpu_addr   : std_logic_vector(15 downto 0);
- signal cpu_di     : std_logic_vector( 7 downto 0);
- signal cpu_do     : std_logic_vector( 7 downto 0);
- signal cpu_wr_n   : std_logic;
- signal cpu_mreq_n : std_logic;
- signal cpu_irq_n  : std_logic;
- signal cpu_iorq_n : std_logic;
- signal cpu_m1_n   : std_logic;
-
- signal cpu_rom_do : std_logic_vector( 7 downto 0);
- signal wram_do    : std_logic_vector( 7 downto 0);
- signal wram_we    : std_logic;
- 
- signal clr_irq_n  : std_logic;
- signal sen1_n     : std_logic;
- signal sen2_n     : std_logic;
- signal sen3_n     : std_logic;
- signal sen4_n     : std_logic;
-
- signal sound_trig_r : std_logic;
- 
- signal ay1_do          : std_logic_vector(7 downto 0);
- signal ay1_cs_n        : std_logic;
- signal ay1_bdir        : std_logic;
- signal ay1_bc1         : std_logic;
- signal ay1_audio_muxed : std_logic_vector(7 downto 0);
- signal ay1_audio_chan  : std_logic_vector(1 downto 0);
- signal ay1_port_b_di   : std_logic_vector(7 downto 0);
-  
- signal ay2_do          : std_logic_vector(7 downto 0);
- signal ay2_cs_n        : std_logic;
- signal ay2_bdir        : std_logic;
- signal ay2_bc1         : std_logic;
- signal ay2_audio_muxed : std_logic_vector(7 downto 0);
- signal ay2_audio_chan  : std_logic_vector(1 downto 0);
- 
- signal ay1_chan_a : std_logic_vector(7 downto 0);
- signal ay1_chan_b : std_logic_vector(7 downto 0);
- signal ay1_chan_c : std_logic_vector(7 downto 0);
- signal ay2_chan_a : std_logic_vector(7 downto 0);
- signal ay2_chan_b : std_logic_vector(7 downto 0);
- signal ay2_chan_c : std_logic_vector(7 downto 0);
- 
- signal filter_cmd_we : std_logic;
- signal filter_cmd    : std_logic_vector(11 downto 0);
- signal mult_cmd      : std_logic_vector(1 downto 0);
- signal mult_value    : integer range 0 to 779;
- 
- signal Vc_1a : integer range -256*1024 to 256*1024-1;
- signal Vc_1b : integer range -256*1024 to 256*1024-1;
- signal Vc_1c : integer range -256*1024 to 256*1024-1;
- signal Vc_2a : integer range -256*1024 to 256*1024-1;
- signal Vc_2b : integer range -256*1024 to 256*1024-1;
- signal Vc_2c : integer range -256*1024 to 256*1024-1;
- signal Vc    : integer range -256*1024 to 256*1024-1;
- signal Vin   : integer range -256 to 255;
- signal dV    : integer range -512 to 511;
- signal Vcn_a : integer range -1024*1024 to 1024*1024-1;
- signal Vcn_b : integer range -1024*1024 to 1024*1024-1;
- signal Vcn_c : integer range  -256*1024 to  256*1024-1;
- 
-begin
-
-clock_14n <= not clock_14;
-reset_n   <= not reset;
-
--- debug 
-process (reset, clock_14)
-begin
- if rising_edge(clock_14) and cpu_mreq_n ='0' then
-   dbg_cpu_addr <= cpu_addr;
- end if;
-end process;
-
---------------------------------------------------------
--- RC filters equation
---
--- Vc  : capacitor voltage = output voltage
--- fs  : sample frequency
--- Vin : voltage at resistor input
---
--- Vc(k+1) = Vc(k) + (Vin-Vc(k))/(fs.R.C) 
---
--- Vcn * 1024 <= Vcn * 1024 + (Vin-Vc) * 1024/(fs.R.C)
--- With Vcn = 1024 * Vc
---------------------------------------------------------
--- Filters will be run at 14.318MHz/512 = 27.96KHz
---------------------------------------------------------
--- 6 filters have to be implemented
--- RC equation is time multiplexed to save multiplier
--- for small FPGA
---------------------------------------------------------
-
--- mux Vc 
-with clock_div1(3 downto 0) select
-Vc <= Vc_1a when X"0",  -- Vc_xy : [0..255*1024]
-		Vc_1b when X"1",  -- => Vc : [-256*1024..255*1024] 
-		Vc_1c when X"2",
-		Vc_2a when X"3",
-		Vc_2b when X"4",
-		Vc_2c when others;
-			
--- mux Vin
-with clock_div1(3 downto 0) select
-Vin <= 	to_integer(unsigned(ay1_chan_a)) when X"0",   -- ayx_chan_y : [0..255]
-			to_integer(unsigned(ay1_chan_b)) when X"1",   -- => Vin     : [-256:255]
-			to_integer(unsigned(ay1_chan_c)) when X"2",
-			to_integer(unsigned(ay2_chan_a)) when X"3",
-			to_integer(unsigned(ay2_chan_b)) when X"4",
-			to_integer(unsigned(ay2_chan_c)) when others;
-
--- compute dV
-dV  <= Vin-Vc/1024;  -- Vc/1024 : [0..255], dv : [-255..511] => [-512..511]
-
--- mux filter cmd
-with clock_div1(3 downto 0) select
-mult_cmd <=  filter_cmd( 7 downto  6) when X"0",
-				 filter_cmd( 9 downto  8) when X"1",
-				 filter_cmd(11 downto 10) when X"2",
-				 filter_cmd( 1 downto  0) when X"3",
-				 filter_cmd( 3 downto  2) when X"4",
-				 filter_cmd( 5 downto  4) when others;
-				 
--- mux multiplier value
-with mult_cmd select
-mult_value <= 779 when "10", -- 0.047uF/1KOhm => (1024/fs.R.C = 779, cut fcy 3386Hz)
-			     166 when "01", -- 0.220uF/1KOhm => (1024/fs.R.C = 166, cut fcy  723Hz)
-			     137 when "11", -- 0.267uF/1KOhm => (1024/fs.R.C = 137, cut fcy  596Hz)
-				  779 when others; -- Not use
-				 
--- compute Vcn
-Vcn_a <= Vin*1024 when mult_cmd = "00" else Vc + dv*mult_value; -- => Vcn_a : [-1024*1024..1023*1024]
-
--- limit to > 0
-Vcn_b <= 0        when Vcn_a < 0 else Vcn_a; 
-
--- limit to < 255*1024
-Vcn_c <= 255*1024 when Vcn_b > 255*1024 else Vcn_b;
-
--- demux/store result and mix channels				
-process (clock_14)  
-begin
-	if rising_edge(clock_14) then -- 14.318MHz/512 => fs = 27.96KHz
-	
-		-- demux & down sample
-		if clock_div1(8 downto 0) = '0'&X"00" then Vc_1a <= Vcn_c; end if;
-		if clock_div1(8 downto 0) = '0'&X"01" then Vc_1b <= Vcn_c; end if;
-		if clock_div1(8 downto 0) = '0'&X"02" then Vc_1c <= Vcn_c; end if;
-		if clock_div1(8 downto 0) = '0'&X"03" then Vc_2a <= Vcn_c; end if;
-		if clock_div1(8 downto 0) = '0'&X"04" then Vc_2b <= Vcn_c; end if;
-		if clock_div1(8 downto 0) = '0'&X"05" then Vc_2c <= Vcn_c; end if;
-
-		-- rescale and mix channels with down sample
-		if clock_div1(8 downto 0) = '0'&X"06" then
-			audio_out <= std_logic_vector(to_unsigned(Vc_1a/1024,11)) +
-					   	 std_logic_vector(to_unsigned(Vc_1b/1024,11)) +
-							 std_logic_vector(to_unsigned(Vc_1c/1024,11)) +
-							 std_logic_vector(to_unsigned(Vc_2a/1024,11)) +
-							 std_logic_vector(to_unsigned(Vc_2b/1024,11)) +
-							 std_logic_vector(to_unsigned(Vc_2c/1024,11));		
-		end if;
-	end if;
-end process;
-
-			
--- divide clocks 
--- random generator ?
-process (clock_14)
-begin
-	if reset='1' then
-		clock_div1 <= (others =>'0');
-		biquinary_div <= (others =>'0');
-	else 
-		if rising_edge(clock_14) then
-			clock_div1  <= clock_div1 + '1';
-			
-			if clock_div1 = X"800" then
-				if biquinary_div(3 downto 1) = "100" then
-					biquinary_div(3 downto 1) <= "000";
-				   biquinary_div(0) <= not biquinary_div(0);	
-				else
-					biquinary_div(3 downto 1) <= biquinary_div(3 downto 1) + '1';
-				end if;
-			end if;			
-		
-		end if;
-	end if;   		
-end process;
-
--- make clocks for cpu and sound generators
-cpu_clock <= clock_div1(2);
-ayx_clock <= not clock_div1(2);
-
--- mux rom/ram/devices data ouput to cpu data input w.r.t cpu address
-cpu_di <= cpu_rom_do   when cpu_addr(15 downto 12) = "0000" else -- 0000-0FFF
-			 wram_do      when cpu_addr(15 downto 12) = "0011" else -- 3000-3FFF
-			 ay1_do       when cpu_addr(15 downto 13) = "010"  else -- 4000-5FFF
-			 ay2_do       when cpu_addr(15 downto 13) = "011"  else -- 6000-7FFF
-   		 X"FF";
-
---	write enable to working ram and filter command register		 
-wram_we   <= '1' when cpu_wr_n = '0' and cpu_addr(15 downto 12) = "0011" else '0';
-filter_cmd_we <= '1' when cpu_wr_n = '0' and cpu_addr(15) = '1' else '0';
-
--- chip select with r/w direction to AY chips
-sen1_n <= '0' when cpu_mreq_n = '0' and cpu_addr(15 downto 12) = X"4" else '1';
-sen2_n <= '0' when cpu_mreq_n = '0' and cpu_addr(15 downto 12) = X"5" else '1';
-sen3_n <= '0' when cpu_mreq_n = '0' and cpu_addr(15 downto 12) = X"6" else '1';
-sen4_n <= '0' when cpu_mreq_n = '0' and cpu_addr(15 downto 12) = X"7" else '1';
-
--- finalise AY r/w & address controls
-ay1_bc1   <= not sen2_n or (    cpu_wr_n and not sen1_n);
-ay1_bdir  <= not sen2_n or (not cpu_wr_n and not sen1_n);
-ay1_cs_n  <= sen1_n and sen2_n;
-
-ay2_bc1   <= not sen4_n or (    cpu_wr_n and not sen3_n);
-ay2_bdir  <= not sen4_n or (not cpu_wr_n and not sen3_n);
-ay2_cs_n  <= sen3_n and sen4_n;
-
--- input random (?) to AY1 chip
-ay1_port_b_di <= biquinary_div(0)&biquinary_div(3)&biquinary_div(2)&clock_div1(11)&"0000";
-
--- clear irq when reset and irq acknowledge
-clr_irq_n <= reset_n and (cpu_m1_n or cpu_iorq_n); 
-
--- regsiter filters commands (11 bits data are cpu address)
-process (cpu_clock)
-begin
-	if rising_edge(cpu_clock) then
-		if filter_cmd_we = '1' then filter_cmd <= cpu_addr(11 downto 0); end if;
-	end if;	
-end process;
-
--- latch sound trigger rising edge to set cpu_irq, and manage clear
-process (clock_14)
-begin
-	if rising_edge(clock_14) then
-		
-		sound_trig_r <= sound_trig;	
-		
-		if clr_irq_n = '0' then
-			cpu_irq_n <= '1';
-		else	
-			if sound_trig ='1' and sound_trig_r = '0' then
-				cpu_irq_n <= '0';
-			end if;
-		end if;
-		
-	end if;	
-end process;
-
--- demux AY chips output
-process (ayx_clock)
-begin
-	if rising_edge(ayx_clock) then
-		if ay1_audio_chan = "00" then ay1_chan_a <= ay1_audio_muxed; end if;
-		if ay1_audio_chan = "01" then ay1_chan_b <= ay1_audio_muxed; end if;
-		if ay1_audio_chan = "10" then ay1_chan_c <= ay1_audio_muxed; end if;
-		if ay2_audio_chan = "00" then ay2_chan_a <= ay2_audio_muxed; end if;
-		if ay2_audio_chan = "01" then ay2_chan_b <= ay2_audio_muxed; end if;
-		if ay2_audio_chan = "10" then ay2_chan_c <= ay2_audio_muxed; end if;
-	end if;	
-end process;
-
--- microprocessor Z80
-cpu : entity work.T80s
-generic map(Mode => 0, T2Write => 1, IOWait => 1)
-port map(
-  RESET_n => reset_n,
-  CLK   	 => not cpu_clock,
- -- CLKEN   => '1',
-  WAIT_n  => '1',
-  INT_n   => cpu_irq_n,
-  NMI_n   => '1',
-  BUSRQ_n => '1',
-  M1_n    => cpu_m1_n,
-  MREQ_n  => cpu_mreq_n,
-  IORQ_n  => cpu_iorq_n,
-  RD_n    => open,
-  WR_n    => cpu_wr_n,
-  RFSH_n  => open,
-  HALT_n  => open,
-  BUSAK_n => open,
-  A       => cpu_addr,
-  DI      => cpu_di,
-  DO      => cpu_do
-);
-
--- cpu1 program ROM
-rom_cpu1 : entity work.jng_snd_rom
-port map(
- clk  => clock_14n,
- addr => cpu_addr(11 downto 0),
- data => cpu_rom_do
-);
-
--- working RAM
-wram : entity work.gen_ram
-generic map( dWidth => 8, aWidth => 10)
-port map(
- clk  => clock_14n,
- we   => wram_we,
- addr => cpu_addr(9 downto 0),
- d    => cpu_do,
- q    => wram_do
-);
-
--- AY-3-8910 #1
-ay_3_8910_1 : entity work.YM2149
-port map(
-  -- data bus
-  I_DA       => cpu_do,    -- in  std_logic_vector(7 downto 0);
-  O_DA       => ay1_do,    -- out std_logic_vector(7 downto 0);
-  O_DA_OE_L  => open,      -- out std_logic;
-  -- control
-  I_A9_L     => ay1_cs_n,  -- in  std_logic;
-  I_A8       => '1',       -- in  std_logic;
-  I_BDIR     => ay1_bdir,  -- in  std_logic;
-  I_BC2      => '1',       -- in  std_logic;
-  I_BC1      => ay1_bc1,   -- in  std_logic;
-  I_SEL_L    => '1',       -- in  std_logic;
-
-  O_AUDIO    => ay1_audio_muxed, -- out std_logic_vector(7 downto 0);
-  O_CHAN     => ay1_audio_chan,  -- out std_logic_vector(1 downto 0);
-  
-  -- port a
-  I_IOA      => sound_cmd, -- in  std_logic_vector(7 downto 0);
-  O_IOA      => open,      -- out std_logic_vector(7 downto 0);
-  O_IOA_OE_L => open,      -- out std_logic;
-  -- port b
-  I_IOB      => ay1_port_b_di,   -- in  std_logic_vector(7 downto 0);
-  O_IOB      => open,            -- out std_logic_vector(7 downto 0);
-  O_IOB_OE_L => open,            -- out std_logic;
-
-  ENA        => '1', --cpu_ena,         -- in  std_logic; -- clock enable for higher speed operation
-  RESET_L    => reset_n,         -- in  std_logic;
-  CLK        => ayx_clock        -- in  std_logic  -- note 6 Mhz
-);
-
--- AY-3-8910 #2
-ay_3_8910_2 : entity work.YM2149
-port map(
-  -- data bus
-  I_DA       => cpu_do,    -- in  std_logic_vector(7 downto 0);
-  O_DA       => ay2_do,    -- out std_logic_vector(7 downto 0);
-  O_DA_OE_L  => open,      -- out std_logic;
-  -- control
-  I_A9_L     => ay2_cs_n,  -- in  std_logic;
-  I_A8       => '1',       -- in  std_logic;
-  I_BDIR     => ay2_bdir,  -- in  std_logic;
-  I_BC2      => '1',       -- in  std_logic;
-  I_BC1      => ay2_bc1,   -- in  std_logic;
-  I_SEL_L    => '1',       -- in  std_logic;
-
-  O_AUDIO    => ay2_audio_muxed, -- out std_logic_vector(7 downto 0);
-  O_CHAN     => ay2_audio_chan,  -- out std_logic_vector(1 downto 0);
-  
-  -- port a
-  I_IOA      => (others => '0'), -- in  std_logic_vector(7 downto 0);
-  O_IOA      => open,            -- out std_logic_vector(7 downto 0);
-  O_IOA_OE_L => open,            -- out std_logic;
-  -- port b
-  I_IOB      => (others => '0'), -- in  std_logic_vector(7 downto 0);
-  O_IOB      => open,            -- out std_logic_vector(7 downto 0);
-  O_IOB_OE_L => open,            -- out std_logic;
-
-  ENA        => '1', --cpu_ena,         -- in  std_logic; -- clock enable for higher speed operation
-  RESET_L    => reset_n,         -- in  std_logic;
-  CLK        => ayx_clock        -- in  std_logic  -- note 6 Mhz
-);
-
-
-end struct;
\ No newline at end of file
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/README.txt b/Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/README.txt
similarity index 100%
rename from Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/README.txt
rename to Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/README.txt
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/RallyX.qpf b/Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/RallyX.qpf
similarity index 100%
rename from Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/RallyX.qpf
rename to Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/RallyX.qpf
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/RallyX.qsf b/Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/RallyX.qsf
similarity index 100%
rename from Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/RallyX.qsf
rename to Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/RallyX.qsf
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/RallyX.sdc b/Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/RallyX.sdc
similarity index 100%
rename from Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/RallyX.sdc
rename to Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/RallyX.sdc
diff --git a/Arcade_MiST/Pacman Hardware/VanVanCar_MiST/clean.bat b/Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/clean.bat
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/VanVanCar_MiST/clean.bat
rename to Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/clean.bat
diff --git a/Arcade_MiST/Pacman Hardware/SuperGlob_MiST/rtl/build_id.tcl b/Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/build_id.tcl
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/SuperGlob_MiST/rtl/build_id.tcl
rename to Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/build_id.tcl
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/dpram.vhd b/Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/dpram.vhd
similarity index 100%
rename from Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/dpram.vhd
rename to Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/dpram.vhd
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/fpga_nrx.v b/Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/fpga_nrx.v
similarity index 100%
rename from Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/fpga_nrx.v
rename to Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/fpga_nrx.v
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/gen_ram.vhd b/Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/gen_ram.vhd
similarity index 100%
rename from Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/gen_ram.vhd
rename to Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/gen_ram.vhd
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/nrx_hvgen.v b/Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/nrx_hvgen.v
similarity index 100%
rename from Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/nrx_hvgen.v
rename to Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/nrx_hvgen.v
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/nrx_namco.v b/Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/nrx_namco.v
similarity index 100%
rename from Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/nrx_namco.v
rename to Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/nrx_namco.v
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/nrx_psg_voice.v b/Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/nrx_psg_voice.v
similarity index 100%
rename from Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/nrx_psg_voice.v
rename to Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/nrx_psg_voice.v
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/nrx_sound.v b/Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/nrx_sound.v
similarity index 100%
rename from Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/nrx_sound.v
rename to Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/nrx_sound.v
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/nrx_sprite.v b/Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/nrx_sprite.v
similarity index 100%
rename from Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/nrx_sprite.v
rename to Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/nrx_sprite.v
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/nrx_video.v b/Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/nrx_video.v
similarity index 100%
rename from Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/nrx_video.v
rename to Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/nrx_video.v
diff --git a/Arcade_MiST/Pacman Hardware/Ponpoko_MiST/rtl/pll.qip b/Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/pll.qip
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Ponpoko_MiST/rtl/pll.qip
rename to Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/pll.qip
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/pll.v b/Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/pll.v
similarity index 100%
rename from Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/pll.v
rename to Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/pll.v
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/rallyX_mist.sv b/Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/rallyX_mist.sv
similarity index 100%
rename from Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/rallyX_mist.sv
rename to Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/rallyX_mist.sv
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/rams.v b/Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/rams.v
similarity index 100%
rename from Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/rams.v
rename to Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/rams.v
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/roms/nrx_chr_rom.vhd b/Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/roms/nrx_chr_rom.vhd
similarity index 100%
rename from Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/roms/nrx_chr_rom.vhd
rename to Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/roms/nrx_chr_rom.vhd
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/roms/nrx_col_rom.vhd b/Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/roms/nrx_col_rom.vhd
similarity index 100%
rename from Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/roms/nrx_col_rom.vhd
rename to Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/roms/nrx_col_rom.vhd
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/roms/nrx_dot_rom.vhd b/Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/roms/nrx_dot_rom.vhd
similarity index 100%
rename from Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/roms/nrx_dot_rom.vhd
rename to Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/roms/nrx_dot_rom.vhd
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/roms/nrx_nam_rom.vhd b/Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/roms/nrx_nam_rom.vhd
similarity index 100%
rename from Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/roms/nrx_nam_rom.vhd
rename to Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/roms/nrx_nam_rom.vhd
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/roms/nrx_nchr_rom.vhd b/Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/roms/nrx_nchr_rom.vhd
similarity index 100%
rename from Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/roms/nrx_nchr_rom.vhd
rename to Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/roms/nrx_nchr_rom.vhd
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/roms/nrx_nprg_rom.vhd b/Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/roms/nrx_nprg_rom.vhd
similarity index 100%
rename from Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/roms/nrx_nprg_rom.vhd
rename to Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/roms/nrx_nprg_rom.vhd
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/roms/nrx_pal_rom.vhd b/Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/roms/nrx_pal_rom.vhd
similarity index 100%
rename from Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/roms/nrx_pal_rom.vhd
rename to Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/roms/nrx_pal_rom.vhd
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/roms/nrx_prg_rom.vhd b/Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/roms/nrx_prg_rom.vhd
similarity index 100%
rename from Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/roms/nrx_prg_rom.vhd
rename to Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/roms/nrx_prg_rom.vhd
diff --git a/Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/roms/nrx_wav_rom.vhd b/Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/roms/nrx_wav_rom.vhd
similarity index 100%
rename from Arcade_MiST/Namco Rally X Hardware/RallyX_MiST/rtl/roms/nrx_wav_rom.vhd
rename to Arcade_MiST/Namco Rally-X Hardware/RallyX_MiST/rtl/roms/nrx_wav_rom.vhd
diff --git a/Arcade_MiST/Namco Mappy Hardware/Mappy_Hardware.qpf b/Arcade_MiST/Namco Super Pacman Hardware/Mappy_Hardware.qpf
similarity index 100%
rename from Arcade_MiST/Namco Mappy Hardware/Mappy_Hardware.qpf
rename to Arcade_MiST/Namco Super Pacman Hardware/Mappy_Hardware.qpf
diff --git a/Arcade_MiST/Namco Mappy Hardware/Mappy_Hardware.qsf b/Arcade_MiST/Namco Super Pacman Hardware/Mappy_Hardware.qsf
similarity index 100%
rename from Arcade_MiST/Namco Mappy Hardware/Mappy_Hardware.qsf
rename to Arcade_MiST/Namco Super Pacman Hardware/Mappy_Hardware.qsf
diff --git a/Arcade_MiST/Namco Mappy Hardware/Mappy_Hardware.sdc b/Arcade_MiST/Namco Super Pacman Hardware/Mappy_Hardware.sdc
similarity index 100%
rename from Arcade_MiST/Namco Mappy Hardware/Mappy_Hardware.sdc
rename to Arcade_MiST/Namco Super Pacman Hardware/Mappy_Hardware.sdc
diff --git a/Arcade_MiST/Namco Mappy Hardware/README.txt b/Arcade_MiST/Namco Super Pacman Hardware/README.txt
similarity index 100%
rename from Arcade_MiST/Namco Mappy Hardware/README.txt
rename to Arcade_MiST/Namco Super Pacman Hardware/README.txt
diff --git a/Arcade_MiST/Namco Mappy Hardware/clean.bat b/Arcade_MiST/Namco Super Pacman Hardware/clean.bat
similarity index 100%
rename from Arcade_MiST/Namco Mappy Hardware/clean.bat
rename to Arcade_MiST/Namco Super Pacman Hardware/clean.bat
diff --git a/Arcade_MiST/Namco Mappy Hardware/meta/Dig Dug 2.mra b/Arcade_MiST/Namco Super Pacman Hardware/meta/Dig Dug 2.mra
similarity index 100%
rename from Arcade_MiST/Namco Mappy Hardware/meta/Dig Dug 2.mra
rename to Arcade_MiST/Namco Super Pacman Hardware/meta/Dig Dug 2.mra
diff --git a/Arcade_MiST/Namco Mappy Hardware/meta/Mappy.mra b/Arcade_MiST/Namco Super Pacman Hardware/meta/Mappy.mra
similarity index 100%
rename from Arcade_MiST/Namco Mappy Hardware/meta/Mappy.mra
rename to Arcade_MiST/Namco Super Pacman Hardware/meta/Mappy.mra
diff --git a/Arcade_MiST/Namco Mappy Hardware/meta/Motos.mra b/Arcade_MiST/Namco Super Pacman Hardware/meta/Motos.mra
similarity index 100%
rename from Arcade_MiST/Namco Mappy Hardware/meta/Motos.mra
rename to Arcade_MiST/Namco Super Pacman Hardware/meta/Motos.mra
diff --git a/Arcade_MiST/Namco Mappy Hardware/meta/The Tower of Druaga.mra b/Arcade_MiST/Namco Super Pacman Hardware/meta/The Tower of Druaga.mra
similarity index 100%
rename from Arcade_MiST/Namco Mappy Hardware/meta/The Tower of Druaga.mra
rename to Arcade_MiST/Namco Super Pacman Hardware/meta/The Tower of Druaga.mra
diff --git a/Arcade_MiST/Namco Mappy Hardware/rtl/TheTowerofDruaga_mist.sv b/Arcade_MiST/Namco Super Pacman Hardware/rtl/TheTowerofDruaga_mist.sv
similarity index 100%
rename from Arcade_MiST/Namco Mappy Hardware/rtl/TheTowerofDruaga_mist.sv
rename to Arcade_MiST/Namco Super Pacman Hardware/rtl/TheTowerofDruaga_mist.sv
diff --git a/Arcade_MiST/Pacman Hardware/VanVanCar_MiST/rtl/build_id.tcl b/Arcade_MiST/Namco Super Pacman Hardware/rtl/build_id.tcl
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/VanVanCar_MiST/rtl/build_id.tcl
rename to Arcade_MiST/Namco Super Pacman Hardware/rtl/build_id.tcl
diff --git a/Arcade_MiST/Namco Mappy Hardware/rtl/dpram.vhd b/Arcade_MiST/Namco Super Pacman Hardware/rtl/dpram.vhd
similarity index 100%
rename from Arcade_MiST/Namco Mappy Hardware/rtl/dpram.vhd
rename to Arcade_MiST/Namco Super Pacman Hardware/rtl/dpram.vhd
diff --git a/Arcade_MiST/Namco Mappy Hardware/rtl/druaga_sprite.v b/Arcade_MiST/Namco Super Pacman Hardware/rtl/druaga_sprite.v
similarity index 100%
rename from Arcade_MiST/Namco Mappy Hardware/rtl/druaga_sprite.v
rename to Arcade_MiST/Namco Super Pacman Hardware/rtl/druaga_sprite.v
diff --git a/Arcade_MiST/Namco Mappy Hardware/rtl/druaga_video.v b/Arcade_MiST/Namco Super Pacman Hardware/rtl/druaga_video.v
similarity index 100%
rename from Arcade_MiST/Namco Mappy Hardware/rtl/druaga_video.v
rename to Arcade_MiST/Namco Super Pacman Hardware/rtl/druaga_video.v
diff --git a/Arcade_MiST/Namco Mappy Hardware/rtl/fpga_druaga.v b/Arcade_MiST/Namco Super Pacman Hardware/rtl/fpga_druaga.v
similarity index 100%
rename from Arcade_MiST/Namco Mappy Hardware/rtl/fpga_druaga.v
rename to Arcade_MiST/Namco Super Pacman Hardware/rtl/fpga_druaga.v
diff --git a/Arcade_MiST/Namco Mappy Hardware/rtl/hvgen.v b/Arcade_MiST/Namco Super Pacman Hardware/rtl/hvgen.v
similarity index 100%
rename from Arcade_MiST/Namco Mappy Hardware/rtl/hvgen.v
rename to Arcade_MiST/Namco Super Pacman Hardware/rtl/hvgen.v
diff --git a/Arcade_MiST/Namco Mappy Hardware/rtl/ioctrl.v b/Arcade_MiST/Namco Super Pacman Hardware/rtl/ioctrl.v
similarity index 100%
rename from Arcade_MiST/Namco Mappy Hardware/rtl/ioctrl.v
rename to Arcade_MiST/Namco Super Pacman Hardware/rtl/ioctrl.v
diff --git a/Arcade_MiST/Namco Mappy Hardware/rtl/ioctrl_0.v b/Arcade_MiST/Namco Super Pacman Hardware/rtl/ioctrl_0.v
similarity index 100%
rename from Arcade_MiST/Namco Mappy Hardware/rtl/ioctrl_0.v
rename to Arcade_MiST/Namco Super Pacman Hardware/rtl/ioctrl_0.v
diff --git a/Arcade_MiST/Namco Mappy Hardware/rtl/ioctrl_1.v b/Arcade_MiST/Namco Super Pacman Hardware/rtl/ioctrl_1.v
similarity index 100%
rename from Arcade_MiST/Namco Mappy Hardware/rtl/ioctrl_1.v
rename to Arcade_MiST/Namco Super Pacman Hardware/rtl/ioctrl_1.v
diff --git a/Arcade_MiST/Namco Mappy Hardware/rtl/mc6809/cpucore.v b/Arcade_MiST/Namco Super Pacman Hardware/rtl/mc6809/cpucore.v
similarity index 100%
rename from Arcade_MiST/Namco Mappy Hardware/rtl/mc6809/cpucore.v
rename to Arcade_MiST/Namco Super Pacman Hardware/rtl/mc6809/cpucore.v
diff --git a/Arcade_MiST/Namco Mappy Hardware/rtl/pll.v b/Arcade_MiST/Namco Super Pacman Hardware/rtl/pll.v
similarity index 100%
rename from Arcade_MiST/Namco Mappy Hardware/rtl/pll.v
rename to Arcade_MiST/Namco Super Pacman Hardware/rtl/pll.v
diff --git a/Arcade_MiST/Namco Mappy Hardware/rtl/sdram.sv b/Arcade_MiST/Namco Super Pacman Hardware/rtl/sdram.sv
similarity index 100%
rename from Arcade_MiST/Namco Mappy Hardware/rtl/sdram.sv
rename to Arcade_MiST/Namco Super Pacman Hardware/rtl/sdram.sv
diff --git a/Arcade_MiST/Namco Mappy Hardware/rtl/wsg.v b/Arcade_MiST/Namco Super Pacman Hardware/rtl/wsg.v
similarity index 100%
rename from Arcade_MiST/Namco Mappy Hardware/rtl/wsg.v
rename to Arcade_MiST/Namco Super Pacman Hardware/rtl/wsg.v
diff --git a/Arcade_MiST/Pacman Hardware/Woodpecker_MiST/clean.bat b/Arcade_MiST/Pacman Hardware/Woodpecker_MiST/clean.bat
deleted file mode 100644
index b3b7c3b5..00000000
--- a/Arcade_MiST/Pacman Hardware/Woodpecker_MiST/clean.bat	
+++ /dev/null
@@ -1,37 +0,0 @@
-@echo off
-del /s *.bak
-del /s *.orig
-del /s *.rej
-del /s *~
-rmdir /s /q db
-rmdir /s /q incremental_db
-rmdir /s /q output_files
-rmdir /s /q simulation
-rmdir /s /q greybox_tmp
-rmdir /s /q hc_output
-rmdir /s /q .qsys_edit
-rmdir /s /q hps_isw_handoff
-rmdir /s /q sys\.qsys_edit
-rmdir /s /q sys\vip
-cd sys
-for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
-cd ..
-for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
-del build_id.v
-del c5_pin_model_dump.txt
-del PLLJ_PLLSPE_INFO.txt
-del /s *.qws
-del /s *.ppf
-del /s *.ddb
-del /s *.csv
-del /s *.cmp
-del /s *.sip
-del /s *.spd
-del /s *.bsf
-del /s *.f
-del /s *.sopcinfo
-del /s *.xml
-del /s new_rtl_netlist
-del /s old_rtl_netlist
-
-pause
diff --git a/Arcade_MiST/Pacman Hardware/Woodpecker_MiST/rtl/build_id.tcl b/Arcade_MiST/Pacman Hardware/Woodpecker_MiST/rtl/build_id.tcl
deleted file mode 100644
index 938515d8..00000000
--- a/Arcade_MiST/Pacman Hardware/Woodpecker_MiST/rtl/build_id.tcl	
+++ /dev/null
@@ -1,35 +0,0 @@
-# ================================================================================
-#
-# Build ID Verilog Module Script
-# Jeff Wiencrot - 8/1/2011
-#
-# Generates a Verilog module that contains a timestamp,
-# from the current build. These values are available from the build_date, build_time,
-# physical_address, and host_name output ports of the build_id module in the build_id.v
-# Verilog source file.
-#
-# ================================================================================
-
-proc generateBuildID_Verilog {} {
-
-	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
-	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
-	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
-
-	# Create a Verilog file for output
-	set outputFileName "rtl/build_id.v"
-	set outputFile [open $outputFileName "w"]
-
-	# Output the Verilog source
-	puts $outputFile "`define BUILD_DATE \"$buildDate\""
-	puts $outputFile "`define BUILD_TIME \"$buildTime\""
-	close $outputFile
-
-	# Send confirmation message to the Messages window
-	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
-	post_message "Date:             $buildDate"
-	post_message "Time:             $buildTime"
-}
-
-# Comment out this line to prevent the process from automatically executing when the file is sourced:
-generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/Sonson_MiST.qsf b/Arcade_MiST/SonSon Hardware/Sonson_MiST/Sonson_MiST.qsf
index 7c7f9830..2cb18b50 100644
--- a/Arcade_MiST/SonSon Hardware/Sonson_MiST/Sonson_MiST.qsf	
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/Sonson_MiST.qsf	
@@ -1,6 +1,6 @@
 # -------------------------------------------------------------------------- #
 #
-# Copyright (C) 1991-2013 Altera Corporation
+# Copyright (C) 1991-2014 Altera Corporation
 # Your use of Altera Corporation's design tools, logic functions 
 # and other software and tools, and its AMPP partner logic 
 # functions, and any output files from any of the foregoing 
@@ -17,8 +17,8 @@
 # -------------------------------------------------------------------------- #
 #
 # Quartus II 64-Bit
-# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-# Date created = 21:06:00  February 29, 2020
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 19:13:36  October 04, 2019
 #
 # -------------------------------------------------------------------------- #
 #
@@ -39,11 +39,11 @@
 
 # Project-Wide Assignments
 # ========================
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.2
 set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:48:06 MAY 24,2017"
 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 
 # Pin & Location Assignments
 # ==========================
@@ -76,6 +76,7 @@ set_location_assignment PIN_88 -to SPI_DI
 set_location_assignment PIN_126 -to SPI_SCK
 set_location_assignment PIN_127 -to SPI_SS2
 set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_90 -to SPI_SS4
 set_location_assignment PIN_13 -to CONF_DATA0
 set_location_assignment PIN_49 -to SDRAM_A[0]
 set_location_assignment PIN_44 -to SDRAM_A[1]
@@ -118,34 +119,27 @@ set_location_assignment PIN_33 -to SDRAM_CKE
 set_location_assignment PIN_43 -to SDRAM_CLK
 set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
 
+
+
 # Classic Timing Assignments
 # ==========================
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
 set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
 
 # Analysis & Synthesis Assignments
 # ================================
 set_global_assignment -name FAMILY "Cyclone III"
-set_global_assignment -name TOP_LEVEL_ENTITY SonSon_MiST
 set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
 set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
-set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
-set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
-set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE ON
-set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
-set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
-set_global_assignment -name SEARCH_PATH common/CPU/T80/ -tag from_archive
-set_global_assignment -name SEARCH_PATH common/mist/ -tag from_archive
-set_global_assignment -name SEARCH_PATH rtl/ -tag from_archive
+set_global_assignment -name TOP_LEVEL_ENTITY SonSon_MiST
+set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
+set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
 
 # Fitter Assignments
 # ==================
 set_global_assignment -name DEVICE EP3C25E144C8
-set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
-set_global_assignment -name ENABLE_NCE_PIN OFF
-set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
 set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
 set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
 set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
@@ -155,23 +149,20 @@ set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO
 set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
 set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
 set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
-set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
 
 # Assembler Assignments
 # =====================
-set_global_assignment -name GENERATE_RBF_FILE ON
 set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
 
 # SignalTap II Assignments
 # ========================
 set_global_assignment -name ENABLE_SIGNALTAP OFF
-set_global_assignment -name USE_SIGNALTAP_FILE output_files/mcr3.stp
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/druaga.stp
 
 # Power Estimation Assignments
 # ============================
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
 set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
 
 # Advanced I/O Timing Assignments
@@ -181,14 +172,8 @@ set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
 set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
 set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
 
-# -----------------------------
-# start ENTITY(LodeRunner_MiST)
-
-	# Pin & Location Assignments
-	# ==========================
-
-	# Fitter Assignments
-	# ==================
+# -----------------------------------
+# start ENTITY(TheTowerofDruaga_mist)
 
 	# start DESIGN_PARTITION(Top)
 	# ---------------------------
@@ -199,8 +184,12 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 	# end DESIGN_PARTITION(Top)
 	# -------------------------
 
-# end ENTITY(LodeRunner_MiST)
-# ---------------------------
+# end ENTITY(TheTowerofDruaga_mist)
+# ---------------------------------
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/SonSon_MiST.sv
 set_global_assignment -name VHDL_FILE rtl/target_top.vhd
 set_global_assignment -name VHDL_FILE rtl/platform_pkg.vhd
@@ -213,23 +202,27 @@ set_global_assignment -name VHDL_FILE rtl/video_mixer.vhd
 set_global_assignment -name VHDL_FILE rtl/video_controller_pkg_body.vhd
 set_global_assignment -name VHDL_FILE rtl/video_controller_pkg.vhd
 set_global_assignment -name VHDL_FILE rtl/video_controller.vhd
-set_global_assignment -name VHDL_FILE rtl/tilemapctl_e.vhd
-set_global_assignment -name VHDL_FILE rtl/tilemapctl.vhd
 set_global_assignment -name VHDL_FILE rtl/spritereg.vhd
 set_global_assignment -name VHDL_FILE rtl/spritectl.vhd
 set_global_assignment -name VHDL_FILE rtl/sprite_pkg_body.vhd
 set_global_assignment -name VHDL_FILE rtl/sprite_pkg.vhd
 set_global_assignment -name VHDL_FILE rtl/sprite_array.vhd
 set_global_assignment -name VHDL_FILE rtl/bitmapctl_e.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu09s.vhd
-set_global_assignment -name VHDL_FILE rtl/sound.vhd
+set_global_assignment -name VHDL_FILE rtl/tilemapctl_e.vhd
+set_global_assignment -name VHDL_FILE rtl/tilemapctl.vhd
+set_global_assignment -name VHDL_FILE rtl/sonson_soundboard.vhd
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/YM2149.sv
+set_global_assignment -name VHDL_FILE rtl/sound.vhd
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
-set_global_assignment -name VHDL_FILE rtl/pll_mist.vhd
+set_global_assignment -name VERILOG_FILE rtl/pll.v
 set_global_assignment -name VHDL_FILE rtl/dprom_2r.vhd
 set_global_assignment -name VHDL_FILE rtl/dpram.vhd
-set_global_assignment -name VHDL_FILE rtl/spram.vhd
 set_global_assignment -name VHDL_FILE rtl/sprom.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu09s.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/sonson/sound_rom.vhd
+set_global_assignment -name VHDL_FILE ../../../common/CPU/T80/Z80.vhd
+set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
 set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
@@ -265,5 +258,6 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
 set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
 set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
 set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
-set_global_assignment -name VERILOG_FILE "rtl/mc6809-master/mc6809i.v"
+set_global_assignment -name VERILOG_FILE ../../../common/CPU/MC6809/mc6809.v
+set_global_assignment -name VERILOG_FILE ../../../common/CPU/MC6809/mc6809i.v
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/RallyX.sdc b/Arcade_MiST/SonSon Hardware/Sonson_MiST/Sonson_MiST.sdc
similarity index 79%
rename from Arcade_MiST/Namco Rally X Hardware/Test_MiST/RallyX.sdc
rename to Arcade_MiST/SonSon Hardware/Sonson_MiST/Sonson_MiST.sdc
index f91c127c..80fe5371 100644
--- a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/RallyX.sdc	
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/Sonson_MiST.sdc	
@@ -53,6 +53,8 @@ set_time_format -unit ns -decimal_places 3
 
 create_clock -name {SPI_SCK}  -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
 
+set sys_clk   "pll|altpll_component|auto_generated|pll1|clk[0]"
+set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
 #**************************************************************
 # Create Generated Clock
 #**************************************************************
@@ -79,15 +81,21 @@ set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [ge
 set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS2}]
 set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS3}]
 
+set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]]
+set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]]
+
 #**************************************************************
 # Set Output Delay
 #**************************************************************
 
-set_output_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DO}]
-set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_L}]
-set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_R}]
-set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {LED}]
-set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {VGA_*}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks $sys_clk]  1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks $sys_clk]  1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks $sys_clk]  1.000 [get_ports {LED}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks $sys_clk]  1.000 [get_ports {VGA_*}]
+
+set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
 
 #**************************************************************
 # Set Clock Groups
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/SonSon_MiST.sv b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/SonSon_MiST.sv
index 51c1cb8f..ce52ed4b 100644
--- a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/SonSon_MiST.sv	
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/SonSon_MiST.sv	
@@ -1,3 +1,38 @@
+/***************************************************************************
+Son Son memory map (preliminary)
+driver by Mirko Buffoni
+MAIN CPU:
+0000-0fff RAM
+1000-13ff Video RAM
+1400-17ff Color RAM
+2020-207f Sprites
+4000-ffff ROM
+read:
+3002      IN0
+3003      IN1
+3004      IN2
+3005      DSW0
+3006      DSW1
+write:
+3000      horizontal scroll
+3008      watchdog reset
+3018      flipscreen (inverted)
+3010      command for the audio CPU
+3019      trigger FIRQ on audio CPU
+SOUND CPU:
+0000-07ff RAM
+e000-ffff ROM
+read:
+a000      command from the main CPU
+write:
+2000      8910 #1 control
+2001      8910 #1 write
+4000      8910 #2 control
+4001      8910 #2 write
+TODO:
+- Fix Service Mode Output Test: press p1/p2 shot to insert coin
+- Flip Screen DIP is noted in service manual and added to DIP LOCATIONS, but not working.
+***************************************************************************/
 module SonSon_MiST(
 	output        LED,						
 	output  [5:0] VGA_R,
@@ -51,15 +86,15 @@ wire       test   = status[8];
 
 assign LED = ~ioctl_downl;
 assign SDRAM_CKE = 1; 
-
-wire clk_sys, clk_vid;
+assign SDRAM_CLK = clk_sd;
+wire clk_sys, clk_vid, clk_sd;
 wire pll_locked;
-pll_mist pll(
+pll pll(
 	.inclk0(CLOCK_27),
 	.areset(0),
 	.c0(clk_sys),//20
 	.c1(clk_vid),//40
-	.c2(SDRAM_CLK),
+	.c2(clk_sd),
 	.locked(pll_locked)
 	);
 
@@ -105,9 +140,6 @@ wire [12:0] tile_rom_addr;
 //wire [12:0] tile_addr;
 wire [15:0] tile_do;
 
-wire [14:0] sp_addr; //todo
-wire [31:0] sp_do; //todo
-
 wire        ioctl_downl;
 wire  [7:0] ioctl_index;
 wire        ioctl_wr;
@@ -115,7 +147,7 @@ wire [24:0] ioctl_addr;
 wire  [7:0] ioctl_dout;
 
 data_io data_io(
-	.clk_sys       ( clk_sys      ),
+	.clk_sys       ( clk_sd      ),
 	.SPI_SCK       ( SPI_SCK      ),
 	.SPI_SS2       ( SPI_SS2      ),
 	.SPI_DI        ( SPI_DI       ),
@@ -126,13 +158,11 @@ data_io data_io(
 	.ioctl_dout    ( ioctl_dout   )
 );
 
-wire [24:0] sp_ioctl_addr = ioctl_addr - 17'h10000; //todo
-
 reg port1_req, port2_req;
 sdram sdram(
 	.*,
 	.init_n        ( pll_locked   ),
-	.clk           ( SDRAM_CLK      ),
+	.clk           ( clk_sd      ),
 
 	// port1 used for main + sound CPU
 	.port1_req     ( port1_req    ),
@@ -145,20 +175,17 @@ sdram sdram(
 
 	.cpu1_addr     ( ioctl_downl ? 16'hffff : {1'b0, cpu_rom_addr[15:1]} ),
 	.cpu1_q        ( rom_do ),
-	.cpu2_addr     ( ioctl_downl ? 16'hffff : (16'h6000 + tile_rom_addr[12:1]) ),
-	.cpu2_q        ( tile_do ),
+	.snd_addr     ( ioctl_downl ? 16'hffff : (16'h6000 + tile_rom_addr[12:1]) ),
+	.snd_q        ( tile_do ),
 
 	// port2 for sprite graphics
-	.port2_req     ( port2_req ),
+	.port2_req     ( ),
 	.port2_ack     ( ),
-	.port2_a       ( {sp_ioctl_addr[23:1]} ),
-	.port2_ds      ( {sp_ioctl_addr[0], ~sp_ioctl_addr[0]} ),
-	.port2_we      ( ioctl_downl ),
-	.port2_d       ( {ioctl_dout, ioctl_dout} ),
-	.port2_q       ( ),
-
-	.sp_addr       ( ioctl_downl ? 15'h7fff : sp_addr ),
-	.sp_q          ( sp_do )
+	.port2_a       ( ),
+	.port2_ds      ( ),
+	.port2_we      ( ),
+	.port2_d       ( ),
+	.port2_q       ( )
 );
 
 // ROM download controller
@@ -209,12 +236,11 @@ target_top target_top(
 	.vid_r(r),
 	.vid_g(g),
 	.vid_b(b),
-		
 	.inputs_p1(~{2'b00,m_down,m_up,m_right,m_left,1'b0,m_fireC}),
-   .inputs_p2(~{2'b00,m_down2,m_up2,m_right2,m_left2,1'b0,m_fire2C}),
-   .inputs_sys(~{2'b00,m_coin2,m_coin1,2'b00,m_two_players,m_one_player}),
-   .inputs_dip1(~{flip,test,"011111"}),
-   .inputs_dip2(~{freeze,"1111111"}),
+	.inputs_p2(~{2'b00,m_down2,m_up2,m_right2,m_left2,1'b0,m_fire2C}),
+	.inputs_sys(~{2'b00,m_coin2,m_coin1,2'b00,m_two_players,m_one_player}),
+	.inputs_dip1(~{flip,test,"011111"}),
+	.inputs_dip2(~{freeze,"1111111"}),
 	.cpu_rom_addr(cpu_rom_addr),
 	.cpu_rom_do(cpu_rom_addr[0] ? rom_do[15:8] : rom_do[7:0]),
 	.tile_rom_addr(tile_rom_addr),
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/platform.vhd b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/platform.vhd
index bef11d3c..90fd0984 100644
--- a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/platform.vhd	
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/platform.vhd	
@@ -388,7 +388,7 @@ begin
       widthad_a		=> 13
     )
     port map
-    (
+   (
       clock			=> clk_video,
       address		=> tilemap_i(1).tile_a(12 downto 0),
       q					=> tilemap_o(1).tile_d(7 downto 0)
@@ -398,18 +398,18 @@ begin
  -- ss_8_b5_inst : entity work.sprom
   --  generic map
   --  (
-  --   init_file		=> "./roms/ss_8_b5.hex",
+  ---   init_file		=> "./roms/ss_8_b5.hex",
   --    widthad_a		=> 13
-  --  )
-  --  port map
-  --  (
-  --    clock			=> clk_video,
-  --    address		=> tilemap_i(1).tile_a(12 downto 0),
-   --  q					=> tilemap_o(1).tile_d(15 downto 8)
-   -- );
+ --   )
+ --   port map
+ --   (
+ --     clock			=> clk_video,
+ --     address		=> tilemap_i(1).tile_a(12 downto 0),
+ --    q					=> tilemap_o(1).tile_d(15 downto 8)
+ --   );
 
 --tile_rom_addr <= tilemap_i(1).tile_a(12 downto 0);
---tilemap_o(1).tile_d(15 downto 0) <= tile_rom_do(15 downto 0);
+--tilemap_o(1).tile_d(15 downto 0) <= tile_rom_do;
 
   BLK_SPRITES : block---will not fit in FPGA Block Ram
     signal bit0_1       : std_logic_vector(7 downto 0);   -- offset 0
diff --git a/Arcade_MiST/Pacman Hardware/Woodpecker_MiST/rtl/pll.qip b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pll.qip
similarity index 100%
rename from Arcade_MiST/Pacman Hardware/Woodpecker_MiST/rtl/pll.qip
rename to Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pll.qip
diff --git a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/pll.v b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pll.v
similarity index 82%
rename from Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/pll.v
rename to Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pll.v
index 538fc3f4..34b615f3 100644
--- a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/pll.v	
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pll.v	
@@ -37,33 +37,46 @@
 `timescale 1 ps / 1 ps
 // synopsys translate_on
 module pll (
+	areset,
 	inclk0,
 	c0,
 	c1,
+	c2,
 	locked);
 
+	input	  areset;
 	input	  inclk0;
 	output	  c0;
 	output	  c1;
+	output	  c2;
 	output	  locked;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri0	  areset;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
 
 	wire [4:0] sub_wire0;
 	wire  sub_wire2;
-	wire [0:0] sub_wire6 = 1'h0;
+	wire [0:0] sub_wire7 = 1'h0;
+	wire [2:2] sub_wire4 = sub_wire0[2:2];
 	wire [0:0] sub_wire3 = sub_wire0[0:0];
 	wire [1:1] sub_wire1 = sub_wire0[1:1];
 	wire  c1 = sub_wire1;
 	wire  locked = sub_wire2;
 	wire  c0 = sub_wire3;
-	wire  sub_wire4 = inclk0;
-	wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
+	wire  c2 = sub_wire4;
+	wire  sub_wire5 = inclk0;
+	wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
 
 	altpll	altpll_component (
-				.inclk (sub_wire5),
+				.areset (areset),
+				.inclk (sub_wire6),
 				.clk (sub_wire0),
 				.locked (sub_wire2),
 				.activeclock (),
-				.areset (1'b0),
 				.clkbad (),
 				.clkena ({6{1'b1}}),
 				.clkloss (),
@@ -98,14 +111,18 @@ module pll (
 				.vcounderrange ());
 	defparam
 		altpll_component.bandwidth_type = "AUTO",
-		altpll_component.clk0_divide_by = 78,
+		altpll_component.clk0_divide_by = 27,
 		altpll_component.clk0_duty_cycle = 50,
-		altpll_component.clk0_multiply_by = 71,
+		altpll_component.clk0_multiply_by = 20,
 		altpll_component.clk0_phase_shift = "0",
-		altpll_component.clk1_divide_by = 430,
+		altpll_component.clk1_divide_by = 27,
 		altpll_component.clk1_duty_cycle = 50,
-		altpll_component.clk1_multiply_by = 223,
+		altpll_component.clk1_multiply_by = 40,
 		altpll_component.clk1_phase_shift = "0",
+		altpll_component.clk2_divide_by = 40,
+		altpll_component.clk2_duty_cycle = 50,
+		altpll_component.clk2_multiply_by = 83,
+		altpll_component.clk2_phase_shift = "0",
 		altpll_component.compensate_clock = "CLK0",
 		altpll_component.inclk0_input_frequency = 37037,
 		altpll_component.intended_device_family = "Cyclone III",
@@ -114,7 +131,7 @@ module pll (
 		altpll_component.operation_mode = "NORMAL",
 		altpll_component.pll_type = "AUTO",
 		altpll_component.port_activeclock = "PORT_UNUSED",
-		altpll_component.port_areset = "PORT_UNUSED",
+		altpll_component.port_areset = "PORT_USED",
 		altpll_component.port_clkbad0 = "PORT_UNUSED",
 		altpll_component.port_clkbad1 = "PORT_UNUSED",
 		altpll_component.port_clkloss = "PORT_UNUSED",
@@ -140,7 +157,7 @@ module pll (
 		altpll_component.port_scanwrite = "PORT_UNUSED",
 		altpll_component.port_clk0 = "PORT_USED",
 		altpll_component.port_clk1 = "PORT_USED",
-		altpll_component.port_clk2 = "PORT_UNUSED",
+		altpll_component.port_clk2 = "PORT_USED",
 		altpll_component.port_clk3 = "PORT_UNUSED",
 		altpll_component.port_clk4 = "PORT_UNUSED",
 		altpll_component.port_clk5 = "PORT_UNUSED",
@@ -179,12 +196,15 @@ endmodule
 // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
 // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
 // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "78"
-// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "430"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
+// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "40"
 // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
 // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.576923"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "14.002326"
+// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "20.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "40.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "56.025002"
 // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -205,28 +225,36 @@ endmodule
 // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
 // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
 // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
 // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
 // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
 // Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "71"
-// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "223"
+// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "20"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "40"
+// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "83"
 // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.57600000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "14.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "20.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "40.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "56.00000000"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
 // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
 // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
 // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
 // Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
 // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
 // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
 // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
 // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
 // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
 // Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
 // Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
@@ -248,25 +276,32 @@ endmodule
 // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
 // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
 // Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
 // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
 // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
 // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
 // Retrieval info: PRIVATE: USE_CLK0 STRING "1"
 // Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
 // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
 // Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
 // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
 // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "78"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
 // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "71"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "20"
 // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "430"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
 // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "223"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "40"
 // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "40"
+// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "83"
+// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
 // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
@@ -274,7 +309,7 @@ endmodule
 // Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
 // Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
 // Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
 // Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
@@ -300,7 +335,7 @@ endmodule
 // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
 // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
 // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
@@ -317,14 +352,18 @@ endmodule
 // Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
 // Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
 // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
 // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
 // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
 // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
 // Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
 // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
 // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
 // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
 // Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
 // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/make.bat b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/make.bat
index 1f1c106b..009a9193 100644
--- a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/make.bat	
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/make.bat	
@@ -5,3 +5,6 @@ copy /b ss_7.b6 + ss_8.b5 tile.rom
 copy /b ss_9.m5 + ss_10.m6 + ss_11.m3 + ss_12.m4 + ss_13.m1 + ss_14.m2 sprite.rom
 
 copy /b cpu.rom + tile.rom + sprite.rom SONSON.ROM
+
+
+make_vhdl_prom ss_6.c11 sound_rom.vhd
\ No newline at end of file
diff --git a/Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/roms/make_vhdl_prom.exe b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/make_vhdl_prom.exe
similarity index 100%
rename from Arcade_MiST/Namco Rally X Hardware/Test_MiST/rtl/roms/make_vhdl_prom.exe
rename to Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/make_vhdl_prom.exe
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/sound_rom.vhd b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/sound_rom.vhd
new file mode 100644
index 00000000..92eb6481
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/sound_rom.vhd	
@@ -0,0 +1,534 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity sound_rom is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(12 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of sound_rom is
+	type rom is array(0 to  8191) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"86",X"FF",X"1F",X"8A",X"8E",X"00",X"00",X"CC",X"00",X"00",X"ED",X"81",X"8C",X"07",X"FF",X"23",
+		X"F9",X"10",X"CE",X"08",X"00",X"BD",X"E0",X"76",X"1C",X"AF",X"20",X"FE",X"34",X"FF",X"0C",X"00",
+		X"BD",X"E0",X"2F",X"BD",X"E1",X"3F",X"BD",X"F2",X"5D",X"BD",X"E0",X"40",X"35",X"FF",X"3B",X"96",
+		X"01",X"26",X"01",X"39",X"0F",X"01",X"CE",X"E6",X"78",X"96",X"02",X"84",X"1F",X"48",X"6E",X"D6",
+		X"5F",X"CE",X"01",X"00",X"4F",X"74",X"01",X"1A",X"49",X"74",X"01",X"19",X"49",X"74",X"01",X"18",
+		X"49",X"74",X"01",X"14",X"49",X"74",X"01",X"13",X"49",X"74",X"01",X"12",X"49",X"8B",X"C0",X"C6",
+		X"07",X"F7",X"20",X"00",X"B7",X"20",X"01",X"39",X"34",X"7E",X"B6",X"A0",X"00",X"97",X"02",X"86",
+		X"FF",X"97",X"01",X"35",X"7E",X"3B",X"CE",X"02",X"00",X"86",X"20",X"C6",X"1B",X"6F",X"C4",X"33",
+		X"C6",X"5A",X"26",X"F9",X"39",X"0B",X"3C",X"0A",X"9B",X"0A",X"02",X"09",X"73",X"08",X"EB",X"08",
+		X"6B",X"07",X"F2",X"07",X"80",X"07",X"14",X"06",X"AE",X"06",X"4E",X"05",X"F4",X"05",X"9E",X"05",
+		X"4D",X"05",X"01",X"04",X"B9",X"04",X"75",X"04",X"35",X"03",X"F9",X"03",X"C0",X"03",X"8A",X"03",
+		X"57",X"03",X"27",X"02",X"FA",X"02",X"CF",X"02",X"A7",X"02",X"81",X"02",X"5D",X"02",X"3B",X"02",
+		X"1B",X"01",X"FC",X"01",X"E0",X"01",X"C5",X"01",X"A5",X"01",X"94",X"01",X"7D",X"01",X"68",X"01",
+		X"53",X"01",X"40",X"01",X"2E",X"01",X"1D",X"01",X"0D",X"00",X"FE",X"00",X"F0",X"00",X"E2",X"00",
+		X"D6",X"00",X"CA",X"00",X"BE",X"00",X"B4",X"00",X"AA",X"00",X"A0",X"00",X"97",X"00",X"8F",X"00",
+		X"87",X"00",X"7F",X"00",X"78",X"00",X"71",X"00",X"6B",X"00",X"65",X"00",X"5F",X"00",X"5A",X"00",
+		X"55",X"00",X"50",X"00",X"4C",X"00",X"47",X"00",X"43",X"00",X"40",X"00",X"3C",X"00",X"39",X"00",
+		X"35",X"00",X"32",X"00",X"30",X"00",X"2D",X"00",X"2A",X"00",X"28",X"00",X"26",X"00",X"24",X"00",
+		X"22",X"00",X"20",X"00",X"1E",X"00",X"1C",X"00",X"1B",X"00",X"19",X"00",X"18",X"00",X"16",X"00",
+		X"15",X"00",X"14",X"00",X"13",X"00",X"12",X"00",X"11",X"00",X"10",X"00",X"0F",X"00",X"0E",X"BD",
+		X"E1",X"46",X"BD",X"E1",X"6B",X"39",X"8E",X"02",X"00",X"0F",X"0F",X"0F",X"04",X"A6",X"84",X"27",
+		X"0B",X"9B",X"0F",X"BD",X"E1",X"9E",X"96",X"0F",X"81",X"03",X"24",X"0E",X"0C",X"04",X"96",X"04",
+		X"81",X"0F",X"27",X"06",X"86",X"20",X"30",X"86",X"20",X"E3",X"39",X"8E",X"04",X"60",X"C6",X"60",
+		X"A6",X"84",X"26",X"08",X"8E",X"04",X"00",X"A6",X"84",X"26",X"12",X"39",X"BD",X"EE",X"5B",X"86",
+		X"20",X"30",X"86",X"BD",X"EE",X"5B",X"86",X"20",X"30",X"86",X"7E",X"EE",X"5B",X"BD",X"EE",X"5B",
+		X"86",X"20",X"30",X"86",X"BD",X"EE",X"5B",X"86",X"20",X"30",X"86",X"7E",X"EE",X"60",X"CE",X"E1",
+		X"A6",X"96",X"04",X"48",X"6E",X"D6",X"E1",X"C4",X"E2",X"07",X"E2",X"2F",X"E2",X"E5",X"E3",X"BC",
+		X"E3",X"BD",X"E4",X"24",X"E4",X"75",X"E4",X"88",X"E4",X"C6",X"E4",X"FB",X"E5",X"2F",X"E5",X"C6",
+		X"E5",X"C7",X"E6",X"10",X"6A",X"0D",X"27",X"1B",X"A6",X"0D",X"44",X"CE",X"E1",X"D3",X"A6",X"C6",
+		X"A7",X"07",X"39",X"01",X"02",X"03",X"05",X"07",X"09",X"0A",X"0B",X"0C",X"0D",X"0D",X"0D",X"0C",
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+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"E0",X"68",X"E0",X"1C",X"FF",X"FF",X"FF",X"FF",X"E0",X"00");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sdram.sv b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sdram.sv
index 41f5b7a8..bc78584d 100644
--- a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sdram.sv	
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sdram.sv	
@@ -44,12 +44,10 @@ module sdram (
 	input      [23:1] port1_a,
 	input       [1:0] port1_ds,
 	input      [15:0] port1_d,
-	output reg [15:0] port1_q,
+	output     [15:0] port1_q,
 
-	input      [16:1] cpu1_addr,
+	input      [15:1] cpu1_addr,
 	output reg [15:0] cpu1_q,
-	input      [16:1] cpu2_addr,
-	output reg [15:0] cpu2_q,
 
 	input             port2_req,
 	output reg        port2_ack,
@@ -57,14 +55,14 @@ module sdram (
 	input      [23:1] port2_a,
 	input       [1:0] port2_ds,
 	input      [15:0] port2_d,
-	output reg [31:0] port2_q,
-	
-	input      [16:2] sp_addr,
-	output reg [31:0] sp_q
+	output     [15:0] port2_q,
+
+	input      [15:1] snd_addr,
+	output reg [15:0] snd_q
 );
 
 localparam RASCAS_DELAY   = 3'd2;   // tRCD=20ns -> 2 cycles@<100MHz
-localparam BURST_LENGTH   = 3'b001; // 000=1, 001=2, 010=4, 011=8
+localparam BURST_LENGTH   = 3'b000; // 000=1, 001=2, 010=4, 011=8
 localparam ACCESS_TYPE    = 1'b0;   // 0=sequential, 1=interleaved
 localparam CAS_LATENCY    = 3'd2;   // 2/3 allowed
 localparam OP_MODE        = 2'b00;  // only 00 (standard operation) allowed
@@ -83,24 +81,21 @@ localparam RFRSH_CYCLES = 10'd842;
  SDRAM state machine for 2 bank interleaved access
  1 word burst, CL2
 cmd issued  registered
- 0 RAS0     cas1 - data0 read burst terminated
+ 0 RAS0     cas1
  1          ras0
- 2          data1 returned
- 3 CAS0     data1 returned
- 4 RAS1     cas0
- 5          ras1
- 6 CAS1     data0 returned
+ 2 CAS0     data1 returned
+ 3 RAS1     cas0
+ 4          ras1
+ 5 CAS1     data0 returned
 */
 
 localparam STATE_RAS0      = 3'd0;   // first state in cycle
-localparam STATE_RAS1      = 3'd4;   // Second ACTIVE command after RAS0 + tRRD (15ns)
-localparam STATE_CAS0      = STATE_RAS0 + RASCAS_DELAY + 1'd1; // CAS phase - 3
-localparam STATE_CAS1      = STATE_RAS1 + RASCAS_DELAY; // CAS phase - 6
-localparam STATE_READ0     = 3'd0;// STATE_CAS0 + CAS_LATENCY + 2'd2; // 7
+localparam STATE_RAS1      = 3'd3;   // Second ACTIVE command after RAS0 + tRRD (15ns)
+localparam STATE_CAS0      = STATE_RAS0 + RASCAS_DELAY; // CAS phase - 3
+localparam STATE_CAS1      = STATE_RAS1 + RASCAS_DELAY; // CAS phase - 5
+localparam STATE_READ0     = 3'd0; //STATE_CAS0 + CAS_LATENCY + 1'd1; // 7
 localparam STATE_READ1     = 3'd3;
-localparam STATE_DS1b      = 3'd0;
-localparam STATE_READ1b    = 3'd4;
-localparam STATE_LAST      = 3'd6;
+localparam STATE_LAST      = 3'd5;
 
 reg [2:0] t;
 
@@ -142,7 +137,7 @@ localparam CMD_PRECHARGE       = 4'b0010;
 localparam CMD_AUTO_REFRESH    = 4'b0001;
 localparam CMD_LOAD_MODE       = 4'b0000;
 
-reg [3:0]  sd_cmd;   // current command sent to sd ram
+reg  [3:0] sd_cmd;   // current command sent to sd ram
 reg [15:0] sd_din;
 // drive control signals according to current command
 assign SDRAM_nCS  = sd_cmd[3];
@@ -152,24 +147,21 @@ assign SDRAM_nWE  = sd_cmd[0];
 
 reg [24:1] addr_latch[2];
 reg [24:1] addr_latch_next[2];
-reg [16:1] addr_last[2];
-reg [16:2] addr_last2[2];
+reg [15:1] addr_last[2];
+reg [15:1] addr_last2[2];
 reg [15:0] din_latch[2];
 reg  [1:0] oe_latch;
 reg  [1:0] we_latch;
 reg  [1:0] ds[2];
 
-reg        port1_state;
-reg        port2_state;
-
 localparam PORT_NONE  = 2'd0;
 localparam PORT_CPU1  = 2'd1;
-localparam PORT_CPU2  = 2'd2;
-localparam PORT_SP    = 2'd1;
-localparam PORT_REQ   = 2'd3;
+localparam PORT_REQ   = 2'd2;
 
-reg  [1:0] next_port[2];
-reg  [1:0] port[2];
+localparam PORT_SND   = 2'd1;
+
+reg  [2:0] next_port[2];
+reg  [2:0] port[2];
 
 reg        refresh;
 reg [10:0] refresh_cnt;
@@ -180,29 +172,26 @@ always @(*) begin
 	if (refresh) begin
 		next_port[0] = PORT_NONE;
 		addr_latch_next[0] = addr_latch[0];
-	end else if (port1_req ^ port1_state) begin
+	end else if (port1_req ^ port1_ack) begin
 		next_port[0] = PORT_REQ;
 		addr_latch_next[0] = { 1'b0, port1_a };
 	end else if (cpu1_addr != addr_last[PORT_CPU1]) begin
 		next_port[0] = PORT_CPU1;
-		addr_latch_next[0] = { 8'd0, cpu1_addr };
-	end else if (cpu2_addr != addr_last[PORT_CPU2]) begin
-		next_port[0] = PORT_CPU2;
-		addr_latch_next[0] = { 8'd0, cpu2_addr };
+		addr_latch_next[0] = { 9'd0, cpu1_addr };
 	end else begin
 		next_port[0] = PORT_NONE;
 		addr_latch_next[0] = addr_latch[0];
 	end
 end
 
-// PORT1: bank 2,3
+// PORT2: bank 2,3
 always @(*) begin
-	if (port2_req ^ port2_state) begin
+	if (port2_req ^ port2_ack) begin
 		next_port[1] = PORT_REQ;
 		addr_latch_next[1] = { 1'b1, port2_a };
-	end else if (sp_addr != addr_last2[PORT_SP]) begin
-		next_port[1] = PORT_SP;
-		addr_latch_next[1] = { 1'b1, 7'd0, sp_addr, 1'b0 };
+	end else if (snd_addr != addr_last2[PORT_SND]) begin
+		next_port[1] = PORT_SND;
+		addr_latch_next[1] = { 1'b1, 8'd0, snd_addr };
 	end else begin
 		next_port[1] = PORT_NONE;
 		addr_latch_next[1] = addr_latch[1];
@@ -249,12 +238,11 @@ always @(posedge clk) begin
 				sd_cmd <= CMD_ACTIVE;
 				SDRAM_A <= addr_latch_next[0][22:10];
 				SDRAM_BA <= addr_latch_next[0][24:23];
-				addr_last[next_port[0]] <= addr_latch_next[0][16:1];
+				addr_last[next_port[0]] <= addr_latch_next[0][15:1];
 				if (next_port[0] == PORT_REQ) begin
 					{ oe_latch[0], we_latch[0] } <= { ~port1_we, port1_we };
 					ds[0] <= port1_ds;
 					din_latch[0] <= port1_d;
-					port1_state <= port1_req;
 				end else begin
 					{ oe_latch[0], we_latch[0] } <= 2'b10;
 					ds[0] <= 2'b11;
@@ -273,12 +261,11 @@ always @(posedge clk) begin
 				sd_cmd <= CMD_ACTIVE;
 				SDRAM_A <= addr_latch_next[1][22:10];
 				SDRAM_BA <= addr_latch_next[1][24:23];
-				addr_last2[next_port[1]] <= addr_latch_next[1][16:2];
+				addr_last2[next_port[1]] <= addr_latch_next[1][15:1];
 				if (next_port[1] == PORT_REQ) begin
-					{ oe_latch[1], we_latch[1] } <= { ~port1_we, port1_we };
+					{ oe_latch[1], we_latch[1] } <= { ~port2_we, port2_we };
 					ds[1] <= port2_ds;
 					din_latch[1] <= port2_d;
-					port2_state <= port2_req;
 				end else begin
 					{ oe_latch[1], we_latch[1] } <= 2'b10;
 					ds[1] <= 2'b11;
@@ -320,25 +307,13 @@ always @(posedge clk) begin
 			case(port[0])
 				PORT_REQ:  begin port1_q <= sd_din; port1_ack <= port1_req; end
 				PORT_CPU1: begin cpu1_q  <= sd_din; end
-				PORT_CPU2: begin cpu2_q  <= sd_din; end
 				default: ;
 			endcase;
 		end
-
 		if(t == STATE_READ1 && oe_latch[1]) begin
 			case(port[1])
-				PORT_REQ:	port2_q[15:0] <= sd_din;
-				PORT_SP :    sp_q[15:0] <= sd_din;
-				default: ;
-			endcase;
-		end
-
-		if(t == STATE_DS1b && oe_latch[1]) { SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
-
-		if(t == STATE_READ1b && oe_latch[1]) begin
-			case(port[1])
-				PORT_REQ: begin port2_q[31:16] <= sd_din; port2_ack <= port2_req; end
-				PORT_SP : begin    sp_q[31:16] <= sd_din; end
+				PORT_REQ:  begin port2_q <= sd_din; port2_ack <= port2_req; end
+				PORT_SND:  begin snd_q   <= sd_din; end
 				default: ;
 			endcase;
 		end
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sonson_soundboard.vhd b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sonson_soundboard.vhd
new file mode 100644
index 00000000..60574062
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sonson_soundboard.vhd	
@@ -0,0 +1,315 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+library work;
+
+--SOUND CPU:
+--0000-07ff RAM
+--e000-ffff ROM
+--read:
+--a000      command from the main CPU
+--write:
+--2000      8910 #1 control
+--2001      8910 #1 write
+--4000      8910 #2 control
+--4001      8910 #2 write
+
+--WRITE_HANDLER( sonson_sh_irqtrigger_w )
+--{
+--	static int last;
+--	if (last == 0 && data == 1)
+--	{
+--		 setting bit 0 low then high triggers IRQ on the sound CPU 
+--		cpu_cause_interrupt(1,M6809_INT_FIRQ);
+--	}
+---	last = data;
+--}
+
+--void sonson_state::sound_map(address_map &map)
+--{
+--	map(0x0000, 0x07ff).ram();
+--	map(0x2000, 0x2001).w("ay1", FUNC(ay8910_device::address_data_w));
+--	map(0x4000, 0x4001).w("ay2", FUNC(ay8910_device::address_data_w));
+--	map(0xa000, 0xa000).r("soundlatch", FUNC(generic_latch_8_device::read));
+--	map(0xe000, 0xffff).rom();
+--}
+
+/* basic machine hardware */
+--	{
+--		{
+--			CPU_M6809,
+--			2000000,	/* 2 Mhz (?) */
+--			readmem,writemem,0,0,
+--			interrupt,1
+--		},
+--		{
+--			CPU_M6809 | CPU_AUDIO_CPU,
+--			2000000,	/* 2 Mhz (?) */
+--			sound_readmem,sound_writemem,0,0,
+--			interrupt,4	/* FIRQs are triggered by the main CPU */
+--		},
+--	},
+	
+	
+entity sonson_soundboard is
+  port(
+  clk_2      	: in std_logic;
+  clk_1p5      : in std_logic;
+  sound_rd     : in std_logic;--a000      command from the main CPU
+  areset       : in std_logic;
+  sound_data   : in std_logic_vector(7 downto 0);
+  audio_out    : out std_logic_vector(11 downto 0)
+  );
+  
+  end sonson_soundboard;
+
+architecture SYN of sonson_soundboard is
+
+  component YM2149
+  port (
+    CLK         : in  std_logic;
+    CE          : in  std_logic;
+    RESET       : in  std_logic;
+    A8          : in  std_logic := '1';
+    A9_L        : in  std_logic := '0';
+    BDIR        : in  std_logic; -- Bus Direction (0 - read , 1 - write)
+    BC          : in  std_logic; -- Bus control
+    DI          : in  std_logic_vector(7 downto 0);
+    DO          : out std_logic_vector(7 downto 0);
+    CHANNEL_A   : out std_logic_vector(7 downto 0);
+    CHANNEL_B   : out std_logic_vector(7 downto 0);
+    CHANNEL_C   : out std_logic_vector(7 downto 0);
+
+    SEL         : in  std_logic;
+    MODE        : in  std_logic;
+
+    ACTIVE      : out std_logic_vector(5 downto 0);
+
+    IOA_in      : in  std_logic_vector(7 downto 0);
+    IOA_out     : out std_logic_vector(7 downto 0);
+
+    IOB_in      : in  std_logic_vector(7 downto 0);
+    IOB_out     : out std_logic_vector(7 downto 0)
+    );
+  end component;
+  
+   COMPONENT mc6809i
+	GENERIC ( ILLEGAL_INSTRUCTIONS : STRING := "GHOST" );
+	PORT
+	(
+		D		:	 IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		DOut		:	 OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		ADDR		:	 OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		RnW		:	 OUT STD_LOGIC;
+		E		:	 IN STD_LOGIC;
+		Q		:	 IN STD_LOGIC;
+		BS		:	 OUT STD_LOGIC;
+		BA		:	 OUT STD_LOGIC;
+		nIRQ		:	 IN STD_LOGIC;
+		nFIRQ		:	 IN STD_LOGIC;
+		nNMI		:	 IN STD_LOGIC;
+		AVMA		:	 OUT STD_LOGIC;
+		BUSY		:	 OUT STD_LOGIC;
+		LIC		:	 OUT STD_LOGIC;
+		nHALT		:	 IN STD_LOGIC;
+		nRESET		:	 IN STD_LOGIC;
+		nDMABREQ		:	 IN STD_LOGIC;
+		RegData		:	 OUT STD_LOGIC_VECTOR(111 DOWNTO 0)
+	);
+END COMPONENT;
+  
+   signal reset      : std_logic := '1';
+	signal reset_cnt  : integer range 0 to 1000000 := 1000000;
+	signal cpu_addr   : std_logic_vector(15 downto 0);
+	signal cpu_di     : std_logic_vector( 7 downto 0);
+	signal cpu_do     : std_logic_vector( 7 downto 0);
+	signal cpu_rw     : std_logic;
+	signal cpu_irq    : std_logic;
+	signal cpu_nmi    : std_logic;
+
+
+
+   signal clk_2M_en			   : std_logic;
+	signal cpu_clk_en          : std_logic;
+	signal cpu_reset			   : std_logic;
+	
+	
+	signal wram_cs   : std_logic;
+	signal wram_we   : std_logic;
+	signal wram_do   : std_logic_vector( 7 downto 0);
+ 
+	signal rom_cs    : std_logic;
+	signal rom_do    : std_logic_vector( 7 downto 0);
+
+	signal ay1_chan_a    : std_logic_vector(7 downto 0);
+	signal ay1_chan_b    : std_logic_vector(7 downto 0);
+	signal ay1_chan_c    : std_logic_vector(7 downto 0);
+	signal ay1_do        : std_logic_vector(7 downto 0);
+	signal ay1_audio     : std_logic_vector(9 downto 0);
+	signal ay1_port_b_do : std_logic_vector(7 downto 0);
+ 
+	signal ay2_chan_a    : std_logic_vector(7 downto 0);
+	signal ay2_chan_b    : std_logic_vector(7 downto 0);
+	signal ay2_chan_c    : std_logic_vector(7 downto 0);
+	signal ay2_do        : std_logic_vector(7 downto 0);
+	signal ay2_audio     : std_logic_vector(9 downto 0);
+	
+	signal ay1_control    : std_logic;
+	signal ay1_write    : std_logic;
+	signal ay2_control    : std_logic;
+	signal ay2_write    : std_logic;
+	
+	signal ports_cs    : std_logic;
+	signal ports_we    : std_logic;
+  
+	signal port1_bus   : std_logic_vector(7 downto 0);  
+	signal port1_data  : std_logic_vector(7 downto 0);
+	signal port1_ddr   : std_logic_vector(7 downto 0);
+	signal port1_in    : std_logic_vector(7 downto 0);
+ 
+	signal port2_bus   : std_logic_vector(7 downto 0);  
+	signal port2_data  : std_logic_vector(7 downto 0);
+	signal port2_ddr   : std_logic_vector(7 downto 0);
+	signal port2_in    : std_logic_vector(7 downto 0);
+
+	
+	begin
+
+	-- cs
+wram_cs   <= '1' when cpu_addr(15 downto 12) = "0000" else '0';		--0000-07ff RAM 			0000 1000 0000 0000
+rom_cs    <= '1' when cpu_addr(15 downto 13) = "111" else '0';			--e000-ffff ROM 			1110 0000 00000000
+ay1_control <= '1' when cpu_addr(13 downto 0) = X"2000" else '0';		--2000 8910 #1 control	0010 0000 0000 0000
+ay1_write <= '1' when cpu_addr(13 downto 0) = X"2001" else '0';		--2001 8910 #1 write		0010 0000 0000 0001
+ay2_control <= '1' when cpu_addr(14 downto 0) = X"4000" else '0';		--4000 8910 #2 control	0100 0000 0000 0000
+ay2_write <= '1' when cpu_addr(14 downto 0) = X"4001" else '0';		--4001 8910 #2 write		0100 0000 0000 0001
+
+--ports_cs  <= '1' when cpu_addr(15 downto  4) = X"000"    else '0'; -- 0000-000F
+--adpcm_cs  <= '1' when cpu_addr(14 downto 11) = "0001"    else '0'; -- 0800-0FFF / 8800-8FFF
+--irqraz_cs <= '1' when cpu_addr(14 downto 12) = "001"     else '0'; -- 1000-1FFF / 9000-9FFF
+
+	
+-- write enables
+wram_we <=   '1' when cpu_rw = '0' and wram_cs =   '1' else '0';
+
+
+
+--ports_we <=  '1' when cpu_rw = '0' and ports_cs =  '1' else '0';
+--adpcm_we <=  '1' when cpu_rw = '0' and adpcm_cs =  '1' else '0';
+--irqraz_we <= '1' when cpu_rw = '0' and irqraz_cs = '1' else '0';
+
+-- mux cpu in data between roms/io/wram
+cpu_di <=	wram_do when wram_cs = '1' else
+				sound_data when sound_rd = '1' else
+--				port1_ddr when ports_cs = '1' and cpu_addr(3 downto 0) = X"0" else
+--				port2_ddr when ports_cs = '1' and cpu_addr(3 downto 0) = X"1" else
+--				port1_in  when ports_cs = '1' and cpu_addr(3 downto 0) = X"2" else
+--				port2_in  when ports_cs = '1' and cpu_addr(3 downto 0) = X"3" else
+				rom_do when rom_cs = '1' else X"FF";
+
+
+
+
+	cpu_inst : mc6809i
+	port map
+    (
+    D				=> cpu_di,
+    DOut			=> cpu_do,
+    ADDR	  		=> cpu_addr,
+    RnW			=> cpu_rw,
+    E   			=> '1',
+    Q				=> clk_2,
+    BS     		=> open,
+    BA     		=> open,
+    nIRQ			=> not cpu_irq,
+    nFIRQ		=> '1',
+    nNMI			=> '1',
+    AVMA  		=> open,
+    BUSY  		=> open,
+	 LIC  		=> open,
+    nHALT		=> '1',	 
+    nRESET		=> not cpu_reset,
+    nDMABREQ  	=> '1',
+    RegData		=> open
+    );
+	 
+	 
+cpu_prog_rom : entity work.sound_rom
+port map(
+	clk  		=> clk_2,
+	addr 		=> cpu_addr(12 downto 0),
+	data 		=> rom_do
+);
+
+cpu_ram : entity work.spram
+	generic map( widthad_a => 11)
+port map(
+	clock  	=> clk_2,
+	wren   	=> wram_we,
+	address 	=> cpu_addr(11 downto 0),
+	data    	=> cpu_do,
+	q    		=> wram_do
+);
+
+ay83910_inst1: YM2149
+  port map (
+    CLK         => clk_1p5,
+    CE          => '1',
+    RESET       => reset,
+    A8          => '1',
+    A9_L        => port2_data(4),
+    BDIR        => port2_data(0),
+    BC          => port2_data(2),
+    DI          => port1_data,
+    DO          => ay1_do,
+    CHANNEL_A   => ay1_chan_a,
+    CHANNEL_B   => ay1_chan_b,
+    CHANNEL_C   => ay1_chan_c,
+
+    SEL         => '0',
+    MODE        => '1',
+
+    ACTIVE      => open,
+
+    IOA_in      => (others => '0'),--select_sound_r,
+    IOA_out     => open,
+
+    IOB_in      => (others => '0'),
+    IOB_out     => ay1_port_b_do
+    );
+
+  ay1_audio <= "0000000000" + ay1_chan_a + ay1_chan_b + ay1_chan_c;
+
+  ay83910_inst2: YM2149
+  port map (
+    CLK         => clk_1p5,
+    CE          => '1',
+    RESET       => reset,
+    A8          => '1',
+    A9_L        => port2_data(3),
+    BDIR        => port2_data(0),
+    BC          => port2_data(2),
+    DI          => port1_data,
+    DO          => ay2_do,
+    CHANNEL_A   => ay2_chan_a,
+    CHANNEL_B   => ay2_chan_b,
+    CHANNEL_C   => ay2_chan_c,
+
+    SEL         => '0',
+    MODE        => '1',
+
+    ACTIVE      => open,
+
+    IOA_in      => (others => '0'),
+    IOA_out     => open,
+
+    IOB_in      => (others => '0'),
+    IOB_out     => open
+    );
+
+  ay2_audio <= "0000000000" + ay2_chan_a + ay2_chan_b + ay2_chan_c;
+
+
+
+
+end SYN;
\ No newline at end of file