From 4240e1b8c338c951b4fe05cdec4b69f573ecddf0 Mon Sep 17 00:00:00 2001 From: Marcel Date: Tue, 12 Mar 2019 05:20:39 +0100 Subject: [PATCH 1/2] Delete Pisces.sv --- .../TripleDrawPoker_MiST/rtl/Pisces.sv | 193 ------------------ 1 file changed, 193 deletions(-) delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/Pisces.sv diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/Pisces.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/Pisces.sv deleted file mode 100644 index 13aa31aa..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/Pisces.sv +++ /dev/null @@ -1,193 +0,0 @@ -//============================================================================ -// Arcade: Catacomb -// -// Port to MiSTer -// Copyright (C) 2017 Sorgelig -// -// This program is free software; you can redistribute it and/or modify it -// under the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 of the License, or (at your option) -// any later version. -// -// This program is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -// more details. -// -// You should have received a copy of the GNU General Public License along -// with this program; if not, write to the Free Software Foundation, Inc., -// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -//============================================================================ - -module Pisces -( - output LED, - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_HS, - output VGA_VS, - output AUDIO_L, - output AUDIO_R, - input SPI_SCK, - output SPI_DO, - input SPI_DI, - input SPI_SS2, - input SPI_SS3, - input CONF_DATA0, - input CLOCK_27 -); - -`include "rtl\build_id.v" - -localparam CONF_STR = { - "Pisces;;", - "O2,Rotate Controls,Off,On;", - "O34,Scanlines,Off,25%,50%,75%;", - "T6,Reset;", - "V,v1.20.",`BUILD_DATE -}; - -assign LED = 1; -assign AUDIO_R = AUDIO_L; - -wire clk_24, clk_18, clk_12, clk_6; -wire pll_locked; -pll pll( - .inclk0(CLOCK_27), - .areset(0), - .c0(clk_24), - .c1(clk_18), - .c2(clk_12), - .c3(clk_6) - ); - -wire [31:0] status; -wire [1:0] buttons; -wire [1:0] switches; -wire [7:0] joystick_0; -wire [7:0] joystick_1; -wire scandoublerD; -wire ypbpr; -wire [10:0] ps2_key; -wire [7:0] audio_a, audio_b; -wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a}; -wire hs, vs; -wire hb, vb; -wire blankn = ~(hb | vb); -wire [2:0] r,g,b; - -galaxian catacomb( - .W_CLK_18M(clk_18), - .W_CLK_12M(clk_12), - .W_CLK_6M(clk_6), - .I_RESET(status[0] | status[6] | buttons[1]), - .P1_CSJUDLR({btn_coin,btn_one_player,m_fire,m_up,m_down,m_left,m_right}), - .P2_CSJUDLR({1'b0, btn_two_players,m_fire,m_up,m_down,m_left,m_right}), - .W_R(r), - .W_G(g), - .W_B(b), - .W_H_SYNC(hs), - .W_V_SYNC(vs), - .HBLANK(hb), - .VBLANK(vb), - .W_SDAT_A(audio_a), - .W_SDAT_B(audio_b) - ); - -video_mixer video_mixer( - .clk_sys(clk_24), - .ce_pix(clk_6), - .ce_pix_actual(clk_6), - .SPI_SCK(SPI_SCK), - .SPI_SS3(SPI_SS3), - .SPI_DI(SPI_DI), - .R(blankn ? r : "000"), - .G(blankn ? g : "000"), - .B(blankn ? b : "000"), - .HSync(hs), - .VSync(vs), - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS), - .rotate({1'b1,status[2]}), - .scandoublerD(scandoublerD), - .scanlines(scandoublerD ? 2'b00 : status[4:3]), - .ypbpr(ypbpr), - .ypbpr_full(1), - .line_start(0), - .mono(0) - ); - -mist_io #( - .STRLEN(($size(CONF_STR)>>3))) -mist_io( - .clk_sys (clk_24 ), - .conf_str (CONF_STR ), - .SPI_SCK (SPI_SCK ), - .CONF_DATA0 (CONF_DATA0 ), - .SPI_SS2 (SPI_SS2 ), - .SPI_DO (SPI_DO ), - .SPI_DI (SPI_DI ), - .buttons (buttons ), - .switches (switches ), - .scandoublerD (scandoublerD ), - .ypbpr (ypbpr ), - .ps2_key (ps2_key ), - .joystick_0 (joystick_0 ), - .joystick_1 (joystick_1 ), - .status (status ) - ); - -dac #( - .msbi_g(15)) -dac( - .clk_i(clk_24), - .res_n_i(1), - .dac_i({audio,5'd0}), - .dac_o(AUDIO_L) - ); - -// Rotated Normal -wire m_up = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3]; -wire m_down = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2]; -wire m_left = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1]; -wire m_right = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0]; -wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; -wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5]; - -reg btn_one_player = 0; -reg btn_two_players = 0; -reg btn_left = 0; -reg btn_right = 0; -reg btn_down = 0; -reg btn_up = 0; -reg btn_fire1 = 0; -reg btn_fire2 = 0; -reg btn_fire3 = 0; -reg btn_coin = 0; -wire pressed = ps2_key[9]; -wire [7:0] code = ps2_key[7:0]; - -always @(posedge clk_24) begin - reg old_state; - old_state <= ps2_key[10]; - if(old_state != ps2_key[10]) begin - case(code) - 'h75: btn_up <= pressed; // up - 'h72: btn_down <= pressed; // down - 'h6B: btn_left <= pressed; // left - 'h74: btn_right <= pressed; // right - 'h76: btn_coin <= pressed; // ESC - 'h05: btn_one_player <= pressed; // F1 - 'h06: btn_two_players <= pressed; // F2 - 'h14: btn_fire3 <= pressed; // ctrl - 'h11: btn_fire2 <= pressed; // alt - 'h29: btn_fire1 <= pressed; // Space - endcase - end -end - -endmodule \ No newline at end of file From 594972678b1864afeab59fab48e8e2cf86f554f8 Mon Sep 17 00:00:00 2001 From: Marcel Date: Tue, 12 Mar 2019 05:23:30 +0100 Subject: [PATCH 2/2] Delete galaxian.vhd --- .../TripleDrawPoker_MiST/rtl/galaxian.vhd | 442 ------------------ 1 file changed, 442 deletions(-) delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/galaxian.vhd diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/galaxian.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/galaxian.vhd deleted file mode 100644 index a44c4a1e..00000000 --- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/galaxian.vhd +++ /dev/null @@ -1,442 +0,0 @@ ------------------------------------------------------------------------------- --- FPGA GALAXIAN --- --- Version downto 2.50 --- --- Copyright(c) 2004 Katsumi Degawa , All rights reserved --- --- Important not --- --- This program is freeware for non-commercial use. --- The author does not guarantee this program. --- You can use this at your own risk. --- --- 2004- 4-30 galaxian modify by K.DEGAWA --- 2004- 5- 6 first release. --- 2004- 8-23 Improvement with T80-IP. --- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. ------------------------------------------------------------------------------- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - ---use work.pkg_galaxian.all; - -entity galaxian is - port( - W_CLK_18M : in std_logic; - W_CLK_12M : in std_logic; - W_CLK_6M : in std_logic; - - P1_CSJUDLR : in std_logic_vector(6 downto 0); - P2_CSJUDLR : in std_logic_vector(6 downto 0); - I_RESET : in std_logic; - - W_R : out std_logic_vector(2 downto 0); - W_G : out std_logic_vector(2 downto 0); - W_B : out std_logic_vector(2 downto 0); - HBLANK : out std_logic; - VBLANK : out std_logic; - W_H_SYNC : out std_logic; - W_V_SYNC : out std_logic; - W_SDAT_A : out std_logic_vector( 7 downto 0); - W_SDAT_B : out std_logic_vector( 7 downto 0); - O_CMPBL : out std_logic - ); -end; - -architecture RTL of galaxian is - -- CPU ADDRESS BUS - signal W_A : std_logic_vector(15 downto 0) := (others => '0'); - -- CPU IF - signal W_CPU_CLK : std_logic := '0'; - signal W_CPU_MREQn : std_logic := '0'; - signal W_CPU_NMIn : std_logic := '0'; - signal W_CPU_RDn : std_logic := '0'; - signal W_CPU_RFSHn : std_logic := '0'; - signal W_CPU_WAITn : std_logic := '0'; - signal W_CPU_WRn : std_logic := '0'; - signal W_CPU_WR : std_logic := '0'; - signal W_RESETn : std_logic := '0'; - -------- H and V COUNTER ------------------------- - signal W_C_BLn : std_logic := '0'; - signal W_C_BLnX : std_logic := '0'; - signal W_C_BLXn : std_logic := '0'; - signal W_H_BL : std_logic := '0'; - signal W_H_SYNC_int : std_logic := '0'; - signal W_V_BLn : std_logic := '0'; - signal W_V_BL2n : std_logic := '0'; - signal W_V_SYNC_int : std_logic := '0'; - signal W_H_CNT : std_logic_vector(8 downto 0) := (others => '0'); - signal W_V_CNT : std_logic_vector(7 downto 0) := (others => '0'); - -------- CPU RAM ---------------------------- - signal W_CPU_RAM_DO : std_logic_vector(7 downto 0) := (others => '0'); - -------- ADDRESS DECDER ---------------------- - signal W_BD_G : std_logic := '0'; - signal W_CPU_RAM_CS : std_logic := '0'; - signal W_CPU_RAM_RD : std_logic := '0'; --- signal W_CPU_RAM_WR : std_logic := '0'; - signal W_CPU_ROM_CS : std_logic := '0'; - signal W_DIP_OE : std_logic := '0'; - signal W_H_FLIP : std_logic := '0'; - signal W_DRIVER_WE : std_logic := '0'; - signal W_OBJ_RAM_RD : std_logic := '0'; - signal W_OBJ_RAM_RQ : std_logic := '0'; - signal W_OBJ_RAM_WR : std_logic := '0'; - signal W_PITCH : std_logic := '0'; - signal W_SOUND_WE : std_logic := '0'; - signal W_STARS_ON : std_logic := '0'; - signal W_STARS_OFFn : std_logic := '0'; - signal W_SW0_OE : std_logic := '0'; - signal W_SW1_OE : std_logic := '0'; - signal W_V_FLIP : std_logic := '0'; - signal W_VID_RAM_RD : std_logic := '0'; - signal W_VID_RAM_WR : std_logic := '0'; - signal W_WDR_OE : std_logic := '0'; - --------- INPORT ----------------------------- - signal W_SW_DO : std_logic_vector( 7 downto 0) := (others => '0'); - --------- VIDEO ----------------------------- - signal W_VID_DO : std_logic_vector( 7 downto 0) := (others => '0'); - ----- DATA I/F ------------------------------------- - signal W_CPU_ROM_DO : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_CPU_ROM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_BDO : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_BDI : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_CPU_RAM_CLK : std_logic := '0'; - signal W_VOL1 : std_logic := '0'; - signal W_VOL2 : std_logic := '0'; - signal W_FIRE : std_logic := '0'; - signal W_HIT : std_logic := '0'; - signal W_FS : std_logic_vector( 2 downto 0) := (others => '0'); - - signal blx_comb : std_logic := '0'; - signal W_1VF : std_logic := '0'; - signal W_256HnX : std_logic := '0'; - signal W_8HF : std_logic := '0'; - signal W_DAC_A : std_logic := '0'; - signal W_DAC_B : std_logic := '0'; - signal W_MISSILEn : std_logic := '0'; - signal W_SHELLn : std_logic := '0'; - signal W_MS_D : std_logic := '0'; - signal W_MS_R : std_logic := '0'; - signal W_MS_G : std_logic := '0'; - signal W_MS_B : std_logic := '0'; - - signal new_sw : std_logic_vector( 2 downto 0) := (others => '0'); - signal in_game : std_logic_vector( 1 downto 0) := (others => '0'); - signal ROM_D : std_logic_vector( 7 downto 0) := (others => '0'); - signal rst_count : std_logic_vector( 3 downto 0) := (others => '0'); - signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_STARS_B : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_STARS_G : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_STARS_R : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); - signal W_VIDEO_B : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_VIDEO_G : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_VIDEO_R : std_logic_vector( 2 downto 0) := (others => '0'); - signal W_WAV_A0 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_A1 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_A2 : std_logic_vector(18 downto 0) := (others => '0'); - signal W_WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_WAV_D2 : std_logic_vector( 7 downto 0) := (others => '0'); - signal W_DAC : std_logic_vector( 3 downto 0) := (others => '0'); - signal gfx_bank : std_logic; - -begin - mc_vid : entity work.MC_VIDEO - port map( - I_CLK_18M => W_CLK_18M, - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_H_CNT => W_H_CNT, - I_V_CNT => W_V_CNT, - I_H_FLIP => W_H_FLIP, - I_V_FLIP => W_V_FLIP, - I_V_BLn => W_V_BLn, - I_C_BLn => W_C_BLn, - I_A => W_A(9 downto 0), - I_OBJ_SUB_A => "000", - I_BD => W_BDI, - I_OBJ_RAM_RQ => W_OBJ_RAM_RQ, - I_OBJ_RAM_RD => W_OBJ_RAM_RD, - I_OBJ_RAM_WR => W_OBJ_RAM_WR, - I_VID_RAM_RD => W_VID_RAM_RD, - I_VID_RAM_WR => W_VID_RAM_WR, - I_DRIVER_WR => W_DRIVER_WE, - I_BANK => gfx_bank, - O_C_BLnX => W_C_BLnX, - O_8HF => W_8HF, - O_256HnX => W_256HnX, - O_1VF => W_1VF, - O_MISSILEn => W_MISSILEn, - O_SHELLn => W_SHELLn, - O_BD => W_VID_DO, - O_VID => W_VID, - O_COL => W_COL - ); - - cpu : entity work.T80as - port map ( - RESET_n => W_RESETn, - CLK_n => W_CPU_CLK, - WAIT_n => W_CPU_WAITn, - INT_n => '1', - NMI_n => W_CPU_NMIn, - BUSRQ_n => '1', - MREQ_n => W_CPU_MREQn, - RD_n => W_CPU_RDn, - WR_n => W_CPU_WRn, - RFSH_n => W_CPU_RFSHn, - A => W_A, - DI => W_BDO, - DO => W_BDI, - M1_n => open, - IORQ_n => open, - HALT_n => open, - BUSAK_n => open, - DOE => open - ); - - mc_cpu_ram : entity work.MC_CPU_RAM - port map ( - I_CLK => W_CPU_RAM_CLK, - I_ADDR => W_A(9 downto 0), - I_D => W_BDI, - I_WE => W_CPU_WR, - I_OE => W_CPU_RAM_RD, - O_D => W_CPU_RAM_DO - ); - - mc_adec : entity work.MC_ADEC - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_CPU_CLK => W_CPU_CLK, - I_RSTn => W_RESETn, - - I_CPU_A => W_A, - I_CPU_D => W_BDI(0), - I_MREQn => W_CPU_MREQn, - I_RFSHn => W_CPU_RFSHn, - I_RDn => W_CPU_RDn, - I_WRn => W_CPU_WRn, - I_H_BL => W_H_BL, - I_V_BLn => W_V_BLn, - - O_WAITn => W_CPU_WAITn, - O_NMIn => W_CPU_NMIn, - O_CPU_ROM_CS => W_CPU_ROM_CS, - O_CPU_RAM_RD => W_CPU_RAM_RD, --- O_CPU_RAM_WR => W_CPU_RAM_WR, - O_CPU_RAM_CS => W_CPU_RAM_CS, - O_OBJ_RAM_RD => W_OBJ_RAM_RD, - O_OBJ_RAM_WR => W_OBJ_RAM_WR, - O_OBJ_RAM_RQ => W_OBJ_RAM_RQ, - O_VID_RAM_RD => W_VID_RAM_RD, - O_VID_RAM_WR => W_VID_RAM_WR, - O_SW0_OE => W_SW0_OE, - O_SW1_OE => W_SW1_OE, - O_DIP_OE => W_DIP_OE, - O_WDR_OE => W_WDR_OE, - O_DRIVER_WE => W_DRIVER_WE, - O_SOUND_WE => W_SOUND_WE, - O_PITCH => W_PITCH, - O_H_FLIP => W_H_FLIP, - O_V_FLIP => W_V_FLIP, - O_BD_G => W_BD_G, - O_STARS_ON => W_STARS_ON - ); - --- active high buttons - mc_inport : entity work.MC_INPORT - port map ( - I_COIN1 => P1_CSJUDLR(6), - I_COIN2 => P2_CSJUDLR(6), - I_1P_START => P1_CSJUDLR(5), - I_2P_START => P2_CSJUDLR(5), - I_1P_SH => P1_CSJUDLR(4), - I_2P_SH => P2_CSJUDLR(4), - I_1P_LE => P1_CSJUDLR(1), - I_2P_LE => P2_CSJUDLR(1), - I_1P_RI => P1_CSJUDLR(0), - I_2P_RI => P2_CSJUDLR(0), - I_SW0_OE => W_SW0_OE, - I_SW1_OE => W_SW1_OE, - I_DIP_OE => W_DIP_OE, - O_D => W_SW_DO - ); - - mc_hv : entity work.MC_HV_COUNT - port map( - I_CLK => W_CLK_6M, - I_RSTn => W_RESETn, - O_H_CNT => W_H_CNT, - O_H_SYNC => W_H_SYNC_int, - O_H_BL => W_H_BL, - O_V_CNT => W_V_CNT, - O_V_SYNC => W_V_SYNC_int, - O_V_BL2n => W_V_BL2n, - O_V_BLn => W_V_BLn, - O_C_BLn => W_C_BLn - ); - - mc_col_pal : entity work.MC_COL_PAL - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_VID => W_VID, - I_COL => W_COL, - I_C_BLnX => W_C_BLnX, - O_C_BLXn => W_C_BLXn, - O_STARS_OFFn => W_STARS_OFFn, - O_R => W_VIDEO_R, - O_G => W_VIDEO_G, - O_B => W_VIDEO_B - ); - - mc_stars : entity work.MC_STARS - port map ( - I_CLK_18M => W_CLK_18M, - I_CLK_6M => W_CLK_6M, - I_H_FLIP => W_H_FLIP, - I_V_SYNC => W_V_SYNC_int, - I_8HF => W_8HF, - I_256HnX => W_256HnX, - I_1VF => W_1VF, - I_2V => W_V_CNT(1), - I_STARS_ON => W_STARS_ON, - I_STARS_OFFn => W_STARS_OFFn, - O_R => W_STARS_R, - O_G => W_STARS_G, - O_B => W_STARS_B, - O_NOISE => open - ); - - mc_sound_a : entity work.MC_SOUND_A - port map( - I_CLK_12M => W_CLK_12M, - I_CLK_6M => W_CLK_6M, - I_H_CNT1 => W_H_CNT(1), - I_BD => W_BDI, - I_PITCH => W_PITCH, - I_VOL1 => W_VOL1, - I_VOL2 => W_VOL2, - O_SDAT => W_SDAT_A, - O_DO => open - ); - ---------- ROM ------------------------------------------------------- - mc_roms : entity work.sprom - generic map ( - init_file => "./ROM/prog.hex", - widthad_a => 14, - width_a => 8) - port map ( - address => W_A(13 downto 0), - clock => W_CLK_12M, - q => W_CPU_ROM_DO - ); - --------- VIDEO ----------------------------- - blx_comb <= not ( W_C_BLXn and W_V_BL2n ); - W_V_SYNC <= not W_V_SYNC_int; - W_H_SYNC <= not W_H_SYNC_int; - O_CMPBL <= W_C_BLnX; - - -- MISSILE => Yellow ; - -- SHELL => White ; - W_MS_D <= not (W_MISSILEn and W_SHELLn); - W_MS_R <= not blx_comb and W_MS_D; - W_MS_G <= not blx_comb and W_MS_D; - W_MS_B <= not blx_comb and W_MS_D and not W_SHELLn ; - - W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0"); - W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0"); - W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0"); - - process(W_CLK_6M) - begin - if rising_edge(W_CLK_6M) then - HBLANK <= not W_C_BLXn; - VBLANK <= not W_V_BL2n; - end if; - end process; - - ------ CPU I/F ------------------------------------- - - W_CPU_CLK <= W_H_CNT(0); - W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS; - - W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0'); - - W_RESETn <= not I_RESET; - W_BDO <= W_SW_DO or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ; - W_CPU_WR <= not W_CPU_WRn; - - new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE; - - process(W_CPU_CLK, I_RESET) - begin - if (I_RESET = '1') then - rst_count <= (others => '0'); - elsif rising_edge( W_CPU_CLK) then - if ( rst_count /= x"f") then - rst_count <= rst_count + 1; - end if; - end if; - end process; - ------ Parts 9L --------- - process(W_CLK_12M, I_RESET) - begin - if (I_RESET = '1') then - W_FS <= (others=>'0'); - W_HIT <= '0'; - W_FIRE <= '0'; - W_VOL1 <= '0'; - W_VOL2 <= '0'; - elsif rising_edge(W_CLK_12M) then - if (W_SOUND_WE = '1') then - case(W_A(2 downto 0)) is - when "000" => W_FS(0) <= W_BDI(0); - when "001" => W_FS(1) <= W_BDI(0); - when "010" => W_FS(2) <= W_BDI(0); - when "011" => W_HIT <= W_BDI(0); --- when "100" => UNUSED <= W_BDI(0); - when "101" => W_FIRE <= W_BDI(0); - when "110" => W_VOL1 <= W_BDI(0); - when "111" => W_VOL2 <= W_BDI(0); - when others => null; - end case; - end if; - end if; - end process; - ------ Parts 9M --------- - process(W_CLK_12M, I_RESET) - begin - if (I_RESET = '1') then - W_DAC <= (others=>'0'); - elsif rising_edge(W_CLK_12M) then - if (W_DRIVER_WE = '1') then - case(W_A(2 downto 0)) is - -- next 4 outputs go off board via ULN2075 buffer --- when "000" => 1P START <= W_BDI(0); --- when "001" => 2P START <= W_BDI(0); - when "010" => gfx_bank <= W_BDI(0); --- when "011" => COIN CTR <= W_BDI(0); - when "100" => W_DAC(0) <= W_BDI(0); -- 1M - when "101" => W_DAC(1) <= W_BDI(0); -- 470K - when "110" => W_DAC(2) <= W_BDI(0); -- 220K - when "111" => W_DAC(3) <= W_BDI(0); -- 100K - when others => null; - end case; - end if; - end if; - end process; - -------------------------------------------------------------------------------- -end RTL;