From 7dc45126090cd764dee7321f1a6f759f753f39fb Mon Sep 17 00:00:00 2001 From: Marcel Date: Wed, 19 Aug 2020 16:49:42 +0200 Subject: [PATCH] Remove GaPlus --- Arcade_MiST/Namco Gaplus/Gaplus.qpf | 31 - Arcade_MiST/Namco Gaplus/Gaplus.qsf | 261 --------- Arcade_MiST/Namco Gaplus/Gaplus.sdc | 134 ----- Arcade_MiST/Namco Gaplus/README.txt | 70 --- Arcade_MiST/Namco Gaplus/Snapshot/Gaplus.rbf | Bin 363919 -> 0 bytes Arcade_MiST/Namco Gaplus/clean.bat | 41 -- Arcade_MiST/Namco Gaplus/rtl/BUF64_53.v | 215 ------- Arcade_MiST/Namco Gaplus/rtl/Gaplus_MiST.sv | 272 --------- Arcade_MiST/Namco Gaplus/rtl/LBUF512_9.v | 254 --------- Arcade_MiST/Namco Gaplus/rtl/build_id.tcl | 35 -- Arcade_MiST/Namco Gaplus/rtl/dpram.vhd | 58 -- Arcade_MiST/Namco Gaplus/rtl/dpram2.vhd | 129 ----- .../Namco Gaplus/rtl/gaplus_abusdriver.v | 65 --- Arcade_MiST/Namco Gaplus/rtl/gaplus_bg.v | 20 - Arcade_MiST/Namco Gaplus/rtl/gaplus_io.v | 428 -------------- Arcade_MiST/Namco Gaplus/rtl/gaplus_main.v | 104 ---- Arcade_MiST/Namco Gaplus/rtl/gaplus_sound.v | 168 ------ Arcade_MiST/Namco Gaplus/rtl/gaplus_sp.v | 40 -- Arcade_MiST/Namco Gaplus/rtl/gaplus_sprite.v | 294 ---------- Arcade_MiST/Namco Gaplus/rtl/gaplus_srams.v | 124 ---- Arcade_MiST/Namco Gaplus/rtl/gaplus_stargen.v | 92 --- Arcade_MiST/Namco Gaplus/rtl/gaplus_sub.v | 96 ---- Arcade_MiST/Namco Gaplus/rtl/gaplus_top.v | 189 ------- Arcade_MiST/Namco Gaplus/rtl/gaplus_video.v | 234 -------- Arcade_MiST/Namco Gaplus/rtl/hvgen.v | 41 -- Arcade_MiST/Namco Gaplus/rtl/pll.qip | 4 - Arcade_MiST/Namco Gaplus/rtl/pll.v | 337 ----------- Arcade_MiST/Namco Gaplus/rtl/rams.v | 87 --- Arcade_MiST/Namco Gaplus/rtl/rom/bg.vhd | 534 ------------------ Arcade_MiST/Namco Gaplus/rtl/rom/make.bat | 20 - .../Namco Gaplus/rtl/rom/make_vhdl_prom.exe | Bin 119861 -> 0 bytes Arcade_MiST/Namco Gaplus/rtl/rom/obj1.vhd | 534 ------------------ Arcade_MiST/Namco Gaplus/rtl/rom/obj2.vhd | 534 ------------------ Arcade_MiST/Namco Gaplus/rtl/rom/obj3.vhd | 534 ------------------ Arcade_MiST/Namco Gaplus/rtl/rom/obj4.vhd | 534 ------------------ Arcade_MiST/Namco Gaplus/rtl/rom/pal_b.vhd | 38 -- Arcade_MiST/Namco Gaplus/rtl/rom/pal_c.vhd | 38 -- Arcade_MiST/Namco Gaplus/rtl/rom/pal_g.vhd | 38 -- Arcade_MiST/Namco Gaplus/rtl/rom/pal_r.vhd | 38 -- Arcade_MiST/Namco Gaplus/rtl/rom/pal_sh.vhd | 54 -- Arcade_MiST/Namco Gaplus/rtl/rom/pal_sl.vhd | 54 -- Arcade_MiST/Namco Gaplus/rtl/rom/sound.vhd | 534 ------------------ Arcade_MiST/Namco Gaplus/rtl/rom/wave.vhd | 38 -- Arcade_MiST/Namco Gaplus/rtl/sdram.sv | 368 ------------ Arcade_MiST/Namco Gaplus/rtl/wsg_aux.v | 121 ---- 45 files changed, 7834 deletions(-) delete mode 100644 Arcade_MiST/Namco Gaplus/Gaplus.qpf delete mode 100644 Arcade_MiST/Namco Gaplus/Gaplus.qsf delete mode 100644 Arcade_MiST/Namco Gaplus/Gaplus.sdc delete mode 100644 Arcade_MiST/Namco Gaplus/README.txt delete mode 100644 Arcade_MiST/Namco Gaplus/Snapshot/Gaplus.rbf delete mode 100644 Arcade_MiST/Namco Gaplus/clean.bat delete mode 100644 Arcade_MiST/Namco Gaplus/rtl/BUF64_53.v delete mode 100644 Arcade_MiST/Namco Gaplus/rtl/Gaplus_MiST.sv delete mode 100644 Arcade_MiST/Namco Gaplus/rtl/LBUF512_9.v delete mode 100644 Arcade_MiST/Namco Gaplus/rtl/build_id.tcl delete mode 100644 Arcade_MiST/Namco Gaplus/rtl/dpram.vhd delete mode 100644 Arcade_MiST/Namco Gaplus/rtl/dpram2.vhd delete mode 100644 Arcade_MiST/Namco Gaplus/rtl/gaplus_abusdriver.v delete mode 100644 Arcade_MiST/Namco Gaplus/rtl/gaplus_bg.v delete mode 100644 Arcade_MiST/Namco Gaplus/rtl/gaplus_io.v delete mode 100644 Arcade_MiST/Namco Gaplus/rtl/gaplus_main.v delete mode 100644 Arcade_MiST/Namco Gaplus/rtl/gaplus_sound.v delete mode 100644 Arcade_MiST/Namco Gaplus/rtl/gaplus_sp.v delete mode 100644 Arcade_MiST/Namco Gaplus/rtl/gaplus_sprite.v delete mode 100644 Arcade_MiST/Namco Gaplus/rtl/gaplus_srams.v delete mode 100644 Arcade_MiST/Namco Gaplus/rtl/gaplus_stargen.v delete mode 100644 Arcade_MiST/Namco Gaplus/rtl/gaplus_sub.v delete mode 100644 Arcade_MiST/Namco Gaplus/rtl/gaplus_top.v delete mode 100644 Arcade_MiST/Namco Gaplus/rtl/gaplus_video.v delete mode 100644 Arcade_MiST/Namco Gaplus/rtl/hvgen.v delete mode 100644 Arcade_MiST/Namco Gaplus/rtl/pll.qip delete mode 100644 Arcade_MiST/Namco Gaplus/rtl/pll.v delete mode 100644 Arcade_MiST/Namco Gaplus/rtl/rams.v delete mode 100644 Arcade_MiST/Namco Gaplus/rtl/rom/bg.vhd delete mode 100644 Arcade_MiST/Namco Gaplus/rtl/rom/make.bat delete mode 100644 Arcade_MiST/Namco Gaplus/rtl/rom/make_vhdl_prom.exe delete mode 100644 Arcade_MiST/Namco Gaplus/rtl/rom/obj1.vhd delete mode 100644 Arcade_MiST/Namco Gaplus/rtl/rom/obj2.vhd delete mode 100644 Arcade_MiST/Namco Gaplus/rtl/rom/obj3.vhd delete mode 100644 Arcade_MiST/Namco Gaplus/rtl/rom/obj4.vhd delete mode 100644 Arcade_MiST/Namco Gaplus/rtl/rom/pal_b.vhd delete mode 100644 Arcade_MiST/Namco Gaplus/rtl/rom/pal_c.vhd delete mode 100644 Arcade_MiST/Namco Gaplus/rtl/rom/pal_g.vhd delete mode 100644 Arcade_MiST/Namco Gaplus/rtl/rom/pal_r.vhd delete mode 100644 Arcade_MiST/Namco Gaplus/rtl/rom/pal_sh.vhd delete mode 100644 Arcade_MiST/Namco Gaplus/rtl/rom/pal_sl.vhd delete mode 100644 Arcade_MiST/Namco Gaplus/rtl/rom/sound.vhd delete mode 100644 Arcade_MiST/Namco Gaplus/rtl/rom/wave.vhd delete mode 100644 Arcade_MiST/Namco Gaplus/rtl/sdram.sv delete mode 100644 Arcade_MiST/Namco Gaplus/rtl/wsg_aux.v diff --git a/Arcade_MiST/Namco Gaplus/Gaplus.qpf b/Arcade_MiST/Namco Gaplus/Gaplus.qpf deleted file mode 100644 index 6afe260e..00000000 --- a/Arcade_MiST/Namco Gaplus/Gaplus.qpf +++ /dev/null @@ -1,31 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition -# Date created = 00:21:03 December 03, 2019 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.1" -DATE = "00:21:03 December 03, 2019" - -# Revisions - -PROJECT_REVISION = "Gaplus" - diff --git a/Arcade_MiST/Namco Gaplus/Gaplus.qsf b/Arcade_MiST/Namco Gaplus/Gaplus.qsf deleted file mode 100644 index 4731f0f0..00000000 --- a/Arcade_MiST/Namco Gaplus/Gaplus.qsf +++ /dev/null @@ -1,261 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Full Version -# Date created = 21:19:44 June 20, 2020 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# Gaplus_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" - -# Pin & Location Assignments -# ========================== -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_54 -to CLOCK_27 -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PIN_49 -to SDRAM_A[0] -set_location_assignment PIN_44 -to SDRAM_A[1] -set_location_assignment PIN_42 -to SDRAM_A[2] -set_location_assignment PIN_39 -to SDRAM_A[3] -set_location_assignment PIN_4 -to SDRAM_A[4] -set_location_assignment PIN_6 -to SDRAM_A[5] -set_location_assignment PIN_8 -to SDRAM_A[6] -set_location_assignment PIN_10 -to SDRAM_A[7] -set_location_assignment PIN_11 -to SDRAM_A[8] -set_location_assignment PIN_28 -to SDRAM_A[9] -set_location_assignment PIN_50 -to SDRAM_A[10] -set_location_assignment PIN_30 -to SDRAM_A[11] -set_location_assignment PIN_32 -to SDRAM_A[12] -set_location_assignment PIN_83 -to SDRAM_DQ[0] -set_location_assignment PIN_79 -to SDRAM_DQ[1] -set_location_assignment PIN_77 -to SDRAM_DQ[2] -set_location_assignment PIN_76 -to SDRAM_DQ[3] -set_location_assignment PIN_72 -to SDRAM_DQ[4] -set_location_assignment PIN_71 -to SDRAM_DQ[5] -set_location_assignment PIN_69 -to SDRAM_DQ[6] -set_location_assignment PIN_68 -to SDRAM_DQ[7] -set_location_assignment PIN_86 -to SDRAM_DQ[8] -set_location_assignment PIN_87 -to SDRAM_DQ[9] -set_location_assignment PIN_98 -to SDRAM_DQ[10] -set_location_assignment PIN_99 -to SDRAM_DQ[11] -set_location_assignment PIN_100 -to SDRAM_DQ[12] -set_location_assignment PIN_101 -to SDRAM_DQ[13] -set_location_assignment PIN_103 -to SDRAM_DQ[14] -set_location_assignment PIN_104 -to SDRAM_DQ[15] -set_location_assignment PIN_58 -to SDRAM_BA[0] -set_location_assignment PIN_51 -to SDRAM_BA[1] -set_location_assignment PIN_85 -to SDRAM_DQMH -set_location_assignment PIN_67 -to SDRAM_DQML -set_location_assignment PIN_60 -to SDRAM_nRAS -set_location_assignment PIN_64 -to SDRAM_nCAS -set_location_assignment PIN_66 -to SDRAM_nWE -set_location_assignment PIN_59 -to SDRAM_nCS -set_location_assignment PIN_33 -to SDRAM_CKE -set_location_assignment PIN_43 -to SDRAM_CLK -set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" - -# Classic Timing Assignments -# ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name TOP_LEVEL_ENTITY Gaplus_MiST -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 -set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP - -# Fitter Assignments -# ================== -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF -set_global_assignment -name ENABLE_NCE_PIN OFF -set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" - -# Assembler Assignments -# ===================== -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF - -# SignalTap II Assignments -# ======================== -set_global_assignment -name ENABLE_SIGNALTAP OFF -set_global_assignment -name USE_SIGNALTAP_FILE output_files/zaxx.stp - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - -# Advanced I/O Timing Assignments -# =============================== -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - -# ------------------------- -# start ENTITY(Gaplus_MiST) - - # Pin & Location Assignments - # ========================== - set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*] - set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*] - set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0] - set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1] - set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH - set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML - set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS - set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS - set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE - set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS - set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*] - set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*] - - # Fitter Assignments - # ================== - set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*] - set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*] - set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*] - set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML - set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH - set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS - set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS - set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE - set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS - set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE - set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK - set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*] - set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*] - set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*] - set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS - set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS - set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L - set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R - set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top - set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top - set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(Gaplus_MiST) -# ----------------------- -set_global_assignment -name SYSTEMVERILOG_FILE rtl/Gaplus_MiST.sv -set_global_assignment -name VERILOG_FILE rtl/gaplus_top.v -set_global_assignment -name VERILOG_FILE rtl/gaplus_main.v -set_global_assignment -name VERILOG_FILE rtl/gaplus_sub.v -set_global_assignment -name VERILOG_FILE rtl/gaplus_sound.v -set_global_assignment -name VERILOG_FILE rtl/gaplus_video.v -set_global_assignment -name VERILOG_FILE rtl/gaplus_sprite.v -set_global_assignment -name VERILOG_FILE rtl/gaplus_abusdriver.v -set_global_assignment -name VERILOG_FILE rtl/gaplus_stargen.v -set_global_assignment -name VERILOG_FILE rtl/gaplus_bg.v -set_global_assignment -name VERILOG_FILE rtl/gaplus_sp.v -set_global_assignment -name VERILOG_FILE rtl/gaplus_io.v -set_global_assignment -name VERILOG_FILE rtl/wsg_aux.v -set_global_assignment -name VERILOG_FILE rtl/gaplus_srams.v -set_global_assignment -name VERILOG_FILE rtl/LBUF512_9.v -set_global_assignment -name VERILOG_FILE rtl/BUF64_53.v -set_global_assignment -name VERILOG_FILE rtl/pll.v -set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv -set_global_assignment -name VERILOG_FILE rtl/hvgen.v -set_global_assignment -name VHDL_FILE rtl/dpram.vhd -set_global_assignment -name VHDL_FILE rtl/dpram2.vhd -set_global_assignment -name VHDL_FILE rtl/rom/wave.vhd -set_global_assignment -name VHDL_FILE rtl/rom/sound.vhd -set_global_assignment -name VHDL_FILE rtl/rom/pal_r.vhd -set_global_assignment -name VHDL_FILE rtl/rom/pal_g.vhd -set_global_assignment -name VHDL_FILE rtl/rom/pal_b.vhd -set_global_assignment -name VHDL_FILE rtl/rom/pal_c.vhd -set_global_assignment -name VHDL_FILE rtl/rom/pal_sh.vhd -set_global_assignment -name VHDL_FILE rtl/rom/pal_sl.vhd -set_global_assignment -name VHDL_FILE rtl/rom/bg.vhd -set_global_assignment -name VHDL_FILE rtl/rom/obj1.vhd -set_global_assignment -name VHDL_FILE rtl/rom/obj2.vhd -set_global_assignment -name VHDL_FILE rtl/rom/obj3.vhd -set_global_assignment -name VHDL_FILE rtl/rom/obj4.vhd -set_global_assignment -name QIP_FILE ../../common/CPU/MC6809/mc6809.qip -set_global_assignment -name QIP_FILE ../../common/mist/mist.qip -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Namco Gaplus/Gaplus.sdc b/Arcade_MiST/Namco Gaplus/Gaplus.sdc deleted file mode 100644 index 33ffd42f..00000000 --- a/Arcade_MiST/Namco Gaplus/Gaplus.sdc +++ /dev/null @@ -1,134 +0,0 @@ -## Generated SDC file "vectrex_MiST.out.sdc" - -## Copyright (C) 1991-2013 Altera Corporation -## Your use of Altera Corporation's design tools, logic functions -## and other software and tools, and its AMPP partner logic -## functions, and any output files from any of the foregoing -## (including device programming or simulation files), and any -## associated documentation or information are expressly subject -## to the terms and conditions of the Altera Program License -## Subscription Agreement, Altera MegaCore Function License -## Agreement, or other applicable license agreement, including, -## without limitation, that your use is for the sole purpose of -## programming logic devices manufactured by Altera and sold by -## Altera or its authorized distributors. Please refer to the -## applicable agreement for further details. - - -## VENDOR "Altera" -## PROGRAM "Quartus II" -## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" - -## DATE "Sun Jun 24 12:53:00 2018" - -## -## DEVICE "EP3C25E144C8" -## - -# Clock constraints - -# Automatically constrain PLL and other generated clocks -derive_pll_clocks -create_base_clocks - -# Automatically calculate clock uncertainty to jitter and other effects. -derive_clock_uncertainty - -# tsu/th constraints - -# tco constraints - -# tpd constraints - -#************************************************************** -# Time Information -#************************************************************** - -set_time_format -unit ns -decimal_places 3 - - - -#************************************************************** -# Create Clock -#************************************************************** - -create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}] - -set sys_clk "pll|altpll_component|auto_generated|pll1|clk[1]" -set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[0]" -#************************************************************** -# Create Generated Clock -#************************************************************** - - -#************************************************************** -# Set Clock Latency -#************************************************************** - - - -#************************************************************** -# Set Clock Uncertainty -#************************************************************** - -#************************************************************** -# Set Input Delay -#************************************************************** - -set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}] - -set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]] -set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]] - -#************************************************************** -# Set Output Delay -#************************************************************** - -set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}] -set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_L}] -set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_R}] -set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {LED}] -set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {VGA_*}] - -set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] -set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] - -#************************************************************** -# Set Clock Groups -#************************************************************** - -set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}] - -#************************************************************** -# Set False Path -#************************************************************** - - - -#************************************************************** -# Set Multicycle Path -#************************************************************** - -set_multicycle_path -to {VGA_*[*]} -setup 2 -set_multicycle_path -to {VGA_*[*]} -hold 1 - -#************************************************************** -# Set Maximum Delay -#************************************************************** - - - -#************************************************************** -# Set Minimum Delay -#************************************************************** - - - -#************************************************************** -# Set Input Transition -#************************************************************** - diff --git a/Arcade_MiST/Namco Gaplus/README.txt b/Arcade_MiST/Namco Gaplus/README.txt deleted file mode 100644 index 708b84fb..00000000 --- a/Arcade_MiST/Namco Gaplus/README.txt +++ /dev/null @@ -1,70 +0,0 @@ ---------------------------------------------------------------------------------- --- --- Arcade: Gaplus port to MiST by Gehstock --- 04 June 2020 --- ---------------------------------------------------------------------------------- --- FPGA Gaplus for XILINX Spartan-3 --------------------------------------- --- Copyright (c) 2007 MiSTer-X ---------------------------------------------------------------------------------- --- Cycle-Accurate 6809 Core --- Revision 1.0 - 13th August 2016 ---------------------------------------------------- --- Copyright (c) 2016, Greg Miller ---------------------------------------------------------------------------------- --- --- --- Keyboard inputs : --- --- F2 : Coin + Start 2 players --- F1 : Coin + Start 1 player --- UP,DOWN,LEFT,RIGHT arrows : Movements --- SPACE/CTRL : Fire --- --- MAME/IPAC/JPAC Style Keyboard inputs: --- 5 : Coin 1 --- 6 : Coin 2 --- 1 : Start 1 Player --- 2 : Start 2 Players --- R,F,D,G : Player 2 Movements --- A/S : Player 2 Fire --- --- Joystick support. --- ---------------------------------------------------------------------------------- --- 05 October 2019 ------------------------------- --- Fixed: Typo in the OSD. ---------------------------------------------------------------------------------- --- 26 October 2019 ------------------------------- --- Changed: Abolished rotation of control direction in Horz mode. ---------------------------------------------------------------------------------- - - *** Attention *** - -ROM is not included. In order to use this arcade, you need to provide a correct ROM file. - -Find this zip file somewhere. You need to find the file exactly as required. -Do not rename other zip files even if they also represent the same game - they are not compatible! -The name of zip is taken from M.A.M.E. project, so you can get more info about -hashes and contained files there. - -To generate the ROM using Windows: -1) Copy the zip into "releases" directory -2) Execute bat file - it will show the name of zip file containing required files. -3) Put required zip into the same directory and execute the bat again. -4) If everything will go without errors or warnings, then you will get the a.*.rom file. -5) Copy generated a.*.rom into root of SD card along with the Arcade-*.rbf file - -To generate the ROM using Linux/MacOS: -1) Copy the zip into "releases" directory -2) Execute build_rom.sh -3) Copy generated a.*.rom into root of SD card along with the Arcade-*.rbf file - -To generate the ROM using MiSTer: -1) scp "releases" directory along with the zip file onto MiSTer:/media/fat/ -2) Using OSD execute build_rom.sh -3) Copy generated a.*.rom into root of SD card along with the Arcade-*.rbf file - diff --git a/Arcade_MiST/Namco Gaplus/Snapshot/Gaplus.rbf b/Arcade_MiST/Namco Gaplus/Snapshot/Gaplus.rbf deleted file mode 100644 index d6f40321be17837c5288bb9dd5ecccfca0592ac6..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 363919 zcmeFae|#L*b=W&Q7(#1>k%%*7=A{U)q{h zm_$vJm|;{|v0eLp&n$+7D9S(NfBI>C1kR5;ckVs+oO91T=iD=^uYK+7!_pTE`0FoU z`SO>)^jClL>{q_>mH+mouYKijzWn8{eU+QPk&`lT;@>3{iKU%#RM;h$PS3~WEk z^>^UKQNY=P?QfT5-_BXus{-54+xxiwy6megp9DgnESIy~f2$zvY=^S_7dn^ymCxl} z>9Z`C^S6qF)ZdPST$k;?(7Eidd@k=uJ7xKcJ(ul$v*)s(vcBLUP|m@!{2QHLsJ@h! zaD5w6E@juB6JQXKvkgcc!AZ^nQg%J`pIkd$|6J~`J?&rJsLu8DxW3M-fQJET!2sV( zn_sWa_0P)t?f42U1h4X$&_bZRm%4Hv0dl?(2(H(cZ?C_7EH`gKIlrYJ=|gb11(5p{ zK;D@HQeY<_&*gp^5Ly0uAaxFJ!FIfwKm`~8 zlfd@t?e}GQc`oso0;J9D@+V`K=W^Z!xPXjTK*~z!m-LTnACPhZ>8pQr?I>lJ069x3&0K}!fVTxDF6CK@<@zje z3h)8JP2PC|D9h!U-2aCykn0l4GCBVzVEg?Wu7d}GKE?a;P+ph#2<-)=T*_n+GUsG^ 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m_four_players; - -arcade_inputs inputs ( - .clk ( CLOCK_49 ), - .key_strobe ( key_strobe ), - .key_pressed ( key_pressed ), - .key_code ( key_code ), - .joystick_0 ( joystick_0 ), - .joystick_1 ( joystick_1 ), - .rotate ( status[2] ), - .orientation ( {1'b1, 1'b1}), - .joyswap ( 1'b0 ), - .oneplayer ( 1'b1 ), - .controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ), - .player1 ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ), - .player2 ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} ) -); - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Namco Gaplus/rtl/LBUF512_9.v b/Arcade_MiST/Namco Gaplus/rtl/LBUF512_9.v deleted file mode 100644 index 8c343d44..00000000 --- a/Arcade_MiST/Namco Gaplus/rtl/LBUF512_9.v +++ /dev/null @@ -1,254 +0,0 @@ -// megafunction wizard: %RAM: 2-PORT% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: altsyncram - -// ============================================================ -// File Name: LBUF512_9.v -// Megafunction Name(s): -// altsyncram -// -// Simulation Library Files(s): -// altera_mf -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 13.1.4 Build 182 03/12/2014 SJ Full Version -// ************************************************************ - - -//Copyright (C) 1991-2014 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files from any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module LBUF512_9 ( - address_a, - address_b, - clock_a, - clock_b, - data_a, - data_b, - rden_a, - rden_b, - wren_a, - wren_b, - q_a, - q_b); - - input [8:0] address_a; - input [8:0] address_b; - input clock_a; - input clock_b; - input [8:0] data_a; - input [8:0] data_b; - input rden_a; - input rden_b; - input wren_a; - input wren_b; - output [8:0] q_a; - output [8:0] q_b; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_off -`endif - tri1 clock_a; - tri1 rden_a; - tri1 rden_b; - tri0 wren_a; - tri0 wren_b; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_on -`endif - - wire [8:0] sub_wire0; - wire [8:0] sub_wire1; - wire [8:0] q_a = sub_wire0[8:0]; - wire [8:0] q_b = sub_wire1[8:0]; - - altsyncram altsyncram_component ( - .clock0 (clock_a), - .wren_a (wren_a), - .address_b (address_b), - .clock1 (clock_b), - .data_b (data_b), - .rden_a (rden_a), - .wren_b (wren_b), - .address_a (address_a), - .data_a (data_a), - .rden_b (rden_b), - .q_a (sub_wire0), - .q_b (sub_wire1), - .aclr0 (1'b0), - .aclr1 (1'b0), - .addressstall_a (1'b0), - .addressstall_b (1'b0), - .byteena_a (1'b1), - .byteena_b (1'b1), - .clocken0 (1'b1), - .clocken1 (1'b1), - .clocken2 (1'b1), - .clocken3 (1'b1), - .eccstatus ()); - defparam - altsyncram_component.address_reg_b = "CLOCK1", - altsyncram_component.clock_enable_input_a = "BYPASS", - altsyncram_component.clock_enable_input_b = "BYPASS", - altsyncram_component.clock_enable_output_a = "BYPASS", - altsyncram_component.clock_enable_output_b = "BYPASS", - altsyncram_component.indata_reg_b = "CLOCK1", - altsyncram_component.intended_device_family = "Cyclone III", - altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = 512, - altsyncram_component.numwords_b = 512, - altsyncram_component.operation_mode = "BIDIR_DUAL_PORT", - altsyncram_component.outdata_aclr_a = "NONE", - altsyncram_component.outdata_aclr_b = "NONE", - altsyncram_component.outdata_reg_a = "CLOCK0", - altsyncram_component.outdata_reg_b = "CLOCK1", - altsyncram_component.power_up_uninitialized = "FALSE", - altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", - altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ", - altsyncram_component.widthad_a = 9, - altsyncram_component.widthad_b = 9, - altsyncram_component.width_a = 9, - altsyncram_component.width_b = 9, - altsyncram_component.width_byteena_a = 1, - altsyncram_component.width_byteena_b = 1, - altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1"; - - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" -// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" -// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" -// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" -// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" -// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" -// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9" -// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" -// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" -// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" -// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" -// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" -// Retrieval info: PRIVATE: CLRdata NUMERIC "0" -// Retrieval info: PRIVATE: CLRq NUMERIC "0" -// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" -// Retrieval info: PRIVATE: CLRrren NUMERIC "0" -// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" -// Retrieval info: PRIVATE: CLRwren NUMERIC "0" -// Retrieval info: PRIVATE: Clock NUMERIC "5" -// Retrieval info: PRIVATE: Clock_A NUMERIC "0" -// Retrieval info: PRIVATE: Clock_B NUMERIC "0" -// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" -// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" -// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" -// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" -// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" -// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -// Retrieval info: PRIVATE: MEMSIZE NUMERIC "4608" -// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" -// Retrieval info: PRIVATE: MIFfilename STRING "" -// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" -// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" -// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1" -// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" -// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" -// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" -// Retrieval info: PRIVATE: REGdata NUMERIC "1" -// Retrieval info: PRIVATE: REGq NUMERIC "1" -// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" -// Retrieval info: PRIVATE: REGrren NUMERIC "1" -// Retrieval info: PRIVATE: REGwraddress NUMERIC "1" -// Retrieval info: PRIVATE: REGwren NUMERIC "1" -// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" -// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" -// Retrieval info: PRIVATE: VarWidth NUMERIC "0" -// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "9" -// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "9" -// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "9" -// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "9" -// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" -// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" -// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" -// Retrieval info: PRIVATE: enable NUMERIC "0" -// Retrieval info: PRIVATE: rden NUMERIC "1" -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1" -// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" -// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" -// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" -// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" -// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512" -// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "512" -// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" -// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" -// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" -// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" -// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1" -// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" -// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" -// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ" -// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9" -// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "9" -// Retrieval info: CONSTANT: WIDTH_A NUMERIC "9" -// Retrieval info: CONSTANT: WIDTH_B NUMERIC "9" -// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" -// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" -// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1" -// Retrieval info: USED_PORT: address_a 0 0 9 0 INPUT NODEFVAL "address_a[8..0]" -// Retrieval info: USED_PORT: address_b 0 0 9 0 INPUT NODEFVAL "address_b[8..0]" -// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a" -// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b" -// Retrieval info: USED_PORT: data_a 0 0 9 0 INPUT NODEFVAL "data_a[8..0]" -// Retrieval info: USED_PORT: data_b 0 0 9 0 INPUT NODEFVAL "data_b[8..0]" -// Retrieval info: USED_PORT: q_a 0 0 9 0 OUTPUT NODEFVAL "q_a[8..0]" -// Retrieval info: USED_PORT: q_b 0 0 9 0 OUTPUT NODEFVAL "q_b[8..0]" -// Retrieval info: USED_PORT: rden_a 0 0 0 0 INPUT VCC "rden_a" -// Retrieval info: USED_PORT: rden_b 0 0 0 0 INPUT VCC "rden_b" -// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a" -// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b" -// Retrieval info: CONNECT: @address_a 0 0 9 0 address_a 0 0 9 0 -// Retrieval info: CONNECT: @address_b 0 0 9 0 address_b 0 0 9 0 -// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0 -// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0 -// Retrieval info: CONNECT: @data_a 0 0 9 0 data_a 0 0 9 0 -// Retrieval info: CONNECT: @data_b 0 0 9 0 data_b 0 0 9 0 -// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden_a 0 0 0 0 -// Retrieval info: CONNECT: @rden_b 0 0 0 0 rden_b 0 0 0 0 -// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 -// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 -// Retrieval info: CONNECT: q_a 0 0 9 0 @q_a 0 0 9 0 -// Retrieval info: CONNECT: q_b 0 0 9 0 @q_b 0 0 9 0 -// Retrieval info: GEN_FILE: TYPE_NORMAL LBUF512_9.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL LBUF512_9.inc FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL LBUF512_9.cmp FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL LBUF512_9.bsf FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL LBUF512_9_inst.v FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL LBUF512_9_bb.v FALSE -// Retrieval info: LIB_FILE: altera_mf diff --git a/Arcade_MiST/Namco Gaplus/rtl/build_id.tcl b/Arcade_MiST/Namco Gaplus/rtl/build_id.tcl deleted file mode 100644 index 938515d8..00000000 --- a/Arcade_MiST/Namco Gaplus/rtl/build_id.tcl +++ /dev/null @@ -1,35 +0,0 @@ -# ================================================================================ -# -# Build ID Verilog Module Script -# Jeff Wiencrot - 8/1/2011 -# -# Generates a Verilog module that contains a timestamp, -# from the current build. These values are available from the build_date, build_time, -# physical_address, and host_name output ports of the build_id module in the build_id.v -# Verilog source file. -# -# ================================================================================ - -proc generateBuildID_Verilog {} { - - # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate [ clock format [ clock seconds ] -format %y%m%d ] - set buildTime [ clock format [ clock seconds ] -format %H%M%S ] - - # Create a Verilog file for output - set outputFileName "rtl/build_id.v" - set outputFile [open $outputFileName "w"] - - # Output the Verilog source - puts $outputFile "`define BUILD_DATE \"$buildDate\"" - puts $outputFile "`define BUILD_TIME \"$buildTime\"" - close $outputFile - - # Send confirmation message to the Messages window - post_message "Generated build identification Verilog module: [pwd]/$outputFileName" - post_message "Date: $buildDate" - post_message "Time: $buildTime" -} - -# Comment out this line to prevent the process from automatically executing when the file is sourced: -generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Namco Gaplus/rtl/dpram.vhd b/Arcade_MiST/Namco Gaplus/rtl/dpram.vhd deleted file mode 100644 index 78823ec4..00000000 --- a/Arcade_MiST/Namco Gaplus/rtl/dpram.vhd +++ /dev/null @@ -1,58 +0,0 @@ -------------------------------------------------------------------------------- --- $Id: dpram.vhd,v 1.1 2006/02/23 21:46:45 arnim Exp $ -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity dpram is - -generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 -); -port ( - clk_a_i : in std_logic; - en_a_i : in std_logic; - we_i : in std_logic; - addr_a_i : in std_logic_vector(addr_width_g-1 downto 0); - data_a_i : in std_logic_vector(data_width_g-1 downto 0); - data_a_o : out std_logic_vector(data_width_g-1 downto 0); - clk_b_i : in std_logic; - addr_b_i : in std_logic_vector(addr_width_g-1 downto 0); - data_b_o : out std_logic_vector(data_width_g-1 downto 0) -); - -end dpram; - - -library ieee; -use ieee.numeric_std.all; - -architecture rtl of dpram is - - type ram_t is array (natural range 2**addr_width_g-1 downto 0) of std_logic_vector(data_width_g-1 downto 0); - signal ram_q : ram_t; - -begin - - mem_a: process (clk_a_i) - begin - if rising_edge(clk_a_i) then - if we_i = '1' and en_a_i = '1' then - ram_q(to_integer(unsigned(addr_a_i))) <= data_a_i; - data_a_o <= data_a_i; - else - data_a_o <= ram_q(to_integer(unsigned(addr_a_i))); - end if; - end if; - end process mem_a; - - mem_b: process (clk_b_i) - begin - if rising_edge(clk_b_i) then - data_b_o <= ram_q(to_integer(unsigned(addr_b_i))); - end if; - end process mem_b; - -end rtl; diff --git a/Arcade_MiST/Namco Gaplus/rtl/dpram2.vhd b/Arcade_MiST/Namco Gaplus/rtl/dpram2.vhd deleted file mode 100644 index 87ba69f9..00000000 --- a/Arcade_MiST/Namco Gaplus/rtl/dpram2.vhd +++ /dev/null @@ -1,129 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY dpram2 IS - GENERIC - ( - widthad_a : natural; - width_a : natural := 8; - outdata_reg_a : string := "UNREGISTERED"; - outdata_reg_b : string := "UNREGISTERED" - ); - PORT - ( - address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - clock_a : IN STD_LOGIC ; - clock_b : IN STD_LOGIC ; - data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - wren_a : IN STD_LOGIC := '1'; - wren_b : IN STD_LOGIC := '1'; - q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); -END dpram2; - - -ARCHITECTURE SYN OF dpram2 IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - - - - COMPONENT altsyncram - GENERIC ( - address_reg_b : STRING; - clock_enable_input_a : STRING; - clock_enable_input_b : STRING; - clock_enable_output_a : STRING; - clock_enable_output_b : STRING; - indata_reg_b : STRING; - init_file : STRING; - intended_device_family : STRING; - lpm_type : STRING; - numwords_a : NATURAL; - numwords_b : NATURAL; - operation_mode : STRING; - outdata_aclr_a : STRING; - outdata_aclr_b : STRING; - outdata_reg_a : STRING; - outdata_reg_b : STRING; - power_up_uninitialized : STRING; - read_during_write_mode_port_a : STRING; - read_during_write_mode_port_b : STRING; - widthad_a : NATURAL; - widthad_b : NATURAL; - width_a : NATURAL; - width_b : NATURAL; - width_byteena_a : NATURAL; - width_byteena_b : NATURAL; - wrcontrol_wraddress_reg_b : STRING - ); - PORT ( - wren_a : IN STD_LOGIC ; - clock0 : IN STD_LOGIC ; - wren_b : IN STD_LOGIC ; - clock1 : IN STD_LOGIC ; - address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - q_a <= sub_wire0(width_a-1 DOWNTO 0); - q_b <= sub_wire1(width_a-1 DOWNTO 0); - - altsyncram_component : altsyncram - GENERIC MAP ( - address_reg_b => "CLOCK1", - clock_enable_input_a => "BYPASS", - clock_enable_input_b => "BYPASS", - clock_enable_output_a => "BYPASS", - clock_enable_output_b => "BYPASS", - indata_reg_b => "CLOCK1", - init_file => "", - intended_device_family => "Cyclone III", - lpm_type => "altsyncram", - numwords_a => 2**widthad_a, - numwords_b => 2**widthad_a, - operation_mode => "BIDIR_DUAL_PORT", - outdata_aclr_a => "NONE", - outdata_aclr_b => "NONE", - outdata_reg_a => outdata_reg_a, - outdata_reg_b => outdata_reg_a, - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", - widthad_a => widthad_a, - widthad_b => widthad_a, - width_a => width_a, - width_b => width_a, - width_byteena_a => 1, - width_byteena_b => 1, - wrcontrol_wraddress_reg_b => "CLOCK1" - ) - PORT MAP ( - wren_a => wren_a, - clock0 => clock_a, - wren_b => wren_b, - clock1 => clock_b, - address_a => address_a, - address_b => address_b, - data_a => data_a, - data_b => data_b, - q_a => sub_wire0, - q_b => sub_wire1 - ); - - - -END SYN; diff --git a/Arcade_MiST/Namco Gaplus/rtl/gaplus_abusdriver.v b/Arcade_MiST/Namco Gaplus/rtl/gaplus_abusdriver.v deleted file mode 100644 index 9f82da1b..00000000 --- a/Arcade_MiST/Namco Gaplus/rtl/gaplus_abusdriver.v +++ /dev/null @@ -1,65 +0,0 @@ - -module gaplus_busdriver -( - input iENABLE, - input iSELECT, - - input [31:0] iBUS0, - input [31:0] iBUS1, - - output [31:0] oBUS - -); - -assign oBUS = iENABLE ? ( iSELECT ? iBUS0 : iBUS1 ) : 0; - -endmodule - - -module dataselector2 -( - output [7:0] oDATA, - - input iSEL0, - input [7:0] iDATA0, - - input iSEL1, - input [7:0] iDATA1, - - input [7:0] dData -); - -assign oDATA = iSEL0 ? iDATA0 : - iSEL1 ? iDATA1 : - dData; - -endmodule - -module dataselector4 -( - output [7:0] oDATA, - - input iSEL0, - input [7:0] iDATA0, - - input iSEL1, - input [7:0] iDATA1, - - input iSEL2, - input [7:0] iDATA2, - - input iSEL3, - input [7:0] iDATA3, - - input [7:0] dData -); - -assign oDATA = iSEL0 ? iDATA0 : - iSEL1 ? iDATA1 : - iSEL2 ? iDATA2 : - iSEL3 ? iDATA3 : - dData; - -endmodule - - diff --git a/Arcade_MiST/Namco Gaplus/rtl/gaplus_bg.v b/Arcade_MiST/Namco Gaplus/rtl/gaplus_bg.v deleted file mode 100644 index b72442d8..00000000 --- a/Arcade_MiST/Namco Gaplus/rtl/gaplus_bg.v +++ /dev/null @@ -1,20 +0,0 @@ -module gaplus_bg( - input clk, - input [13:0] ad, - output [7:0] dt -); - -wire [7:0] dt0; -bg bg( - .clk(clk), - .addr(ad), - .data(dt0) -); - -reg ad13; -always @( negedge clk ) ad13 <= ad[13]; - -assign dt = ad13 ? {4'h0,dt0[7:4]} : dt0; - - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Namco Gaplus/rtl/gaplus_io.v b/Arcade_MiST/Namco Gaplus/rtl/gaplus_io.v deleted file mode 100644 index 5d035ad2..00000000 --- a/Arcade_MiST/Namco Gaplus/rtl/gaplus_io.v +++ /dev/null @@ -1,428 +0,0 @@ -/******************************************** - I/O Module for "FPGA Gaplus" - - Copyright (c) 2007,2019 MiSTer-X -*********************************************/ -module gaplus_io -( - input reset, - input clk, - input VBLK, - - input [15:0] cpu_ad, - input cpu_vma, - input cpu_wr, - input [7:0] cpu_wd, - output [7:0] cpu_rd, - output cpu_cs, - - input [31:0] INP0, - input [31:0] INP1, - input [3:0] INP2, - - output pcm_kick -); - -wire io_cs = ( cpu_ad[15:8] == 8'h68 ) & cpu_vma; - -wire iochp0_cs = ( cpu_ad[7:4] == 4'h0 ) & io_cs; -wire iochp1_cs = ( cpu_ad[7:4] == 4'h1 ) & io_cs; -wire iocust_cs = ( cpu_ad[7:4] == 4'h2 ) & io_cs; - -wire [3:0] iochp0_rd; -wire [3:0] iochp1_rd; -wire [3:0] iocust_rd; - -wire [3:0] io_rd = iochp0_cs ? iochp0_rd : - iochp1_cs ? iochp1_rd : - iocust_cs ? iocust_rd : - 4'hF; - -assign cpu_cs = io_cs; -assign cpu_rd = { 4'hF, io_rd }; - -GAPLUS_IO_CUS0 iochp0( reset, clk, VBLK, iochp0_cs, cpu_ad[3:0], iochp0_rd, cpu_wd[3:0], cpu_wr, INP0 ); -GAPLUS_IO_CUS1 iochp1( reset, clk, VBLK, iochp1_cs, cpu_ad[3:0], iochp1_rd, cpu_wd[3:0], cpu_wr, INP1 ); -GAPLUS_IO_CUS2 iocust( reset, clk, iocust_cs, cpu_ad[3:0], iocust_rd, cpu_wd, cpu_wr, pcm_kick, INP2 ); - -endmodule - - -//---------------------------------------------------------------- -module GAPLUS_IO_CUS0 -( - input reset, - input clk, - input VB, - input cs, - input [3:0] adrs, - output [3:0] rd, - input [3:0] wd, - input we, - - input [31:0] INPORT -); - -reg [3:0] regs [0:15]; - -reg [3:0] out; - - -reg [7:0] credits; -reg [7:0] credit_add, credit_sub; - -reg [31:0] pINPORT,fINPORT; -wire [31:0] iINPORT = ( fINPORT ^ pINPORT ) & fINPORT; - -wire [3:0] CREDIT_ONES, CREDIT_TENS; -BCDCONV creditsBCD( credits, CREDIT_ONES, CREDIT_TENS ); - -reg pVB; - -always @ ( posedge clk or posedge reset ) begin - - if ( reset ) begin - out <= 4'hF; - credits <= 0; - - pVB <= 1'b0; - end - else begin - - if (~VB) pVB <= 1'b0; - else if (~pVB) begin - - if (regs[4'h8]==4'h4) begin - - credit_add = 0; - credit_sub = 0; - - if ( iINPORT[0] & ( credits < 99 ) ) begin - credit_add = 8'h01; - credits = credits + 1; - end - - if ( regs[4'h9] == 0 ) begin - if ( ( credits >= 2 ) & iINPORT[15] ) begin - credit_sub = 8'h02; - credits = credits - 2; - end else if ( ( credits >= 1 ) & iINPORT[14] ) begin - credit_sub = 8'h01; - credits = credits - 1; - end - end - end - - pINPORT <= fINPORT; - fINPORT <= INPORT; - pVB <= 1'b1; - end - - if (cs) begin - if (we) regs[adrs] <= wd; - else out <= regs[adrs]; - end - - - case ( regs[4'h8] ) - - 4'h1: begin // Switches Input - - regs[4'h0] <= fINPORT[3:0]; - regs[4'h1] <= fINPORT[7:4]; - regs[4'h2] <= fINPORT[11:8]; - regs[4'h3] <= fINPORT[15:12]; - - end - - // 4'h2: begin end // Coinage Setting (not impl.) - - 4'h4: begin // Handle Coin & Switches Input - - regs[4'h0] <= CREDIT_TENS; - regs[4'h1] <= CREDIT_ONES; - regs[4'h2] <= credit_add; - regs[4'h3] <= credit_sub; - - regs[4'h4] <= fINPORT[7:4]; - regs[4'h5] <= { fINPORT[14], iINPORT[14], fINPORT[12], iINPORT[12] }; - regs[4'h6] <= INPORT[11:8]; - regs[4'h7] <= { fINPORT[15], iINPORT[15], fINPORT[13], iINPORT[13] }; - - end - - //4'h7: begin end - - 4'h8: begin // bootup check ( impl. for Gaplus ) - regs[4'h0] <= 4'h6; - regs[4'h1] <= 4'h9; - end - - 4'h9: begin // DIP Switches Input - - regs[4'h0] <= fINPORT[3:0]; - regs[4'h2] <= fINPORT[7:4]; - regs[4'h4] <= fINPORT[11:8]; - regs[4'h6] <= fINPORT[15:12]; - - regs[4'h1] <= fINPORT[19:16]; - regs[4'h3] <= fINPORT[23:20]; - regs[4'h5] <= fINPORT[27:24]; - regs[4'h7] <= fINPORT[31:28]; - - end - - default: ; - - endcase - - end - -end - -assign rd = out; - -endmodule - - -//---------------------------------------------------------------- -module GAPLUS_IO_CUS1 -( - input reset, - input clk, - input VB, - input cs, - input [3:0] adrs, - output [3:0] rd, - input [3:0] wd, - input we, - - input [31:0] INPORT -); - -reg [3:0] regs [0:15]; -reg [3:0] out; - -reg [7:0] credits; -reg [7:0] credit_add, credit_sub; - -reg [31:0] pINPORT,fINPORT; -wire [31:0] iINPORT = ( fINPORT ^ pINPORT ) & fINPORT; - -wire [3:0] CREDIT_ONES, CREDIT_TENS; -BCDCONV creditsBCD( credits, CREDIT_ONES, CREDIT_TENS ); - -reg pVB; - -always @ ( posedge clk or posedge reset ) begin - - if ( reset ) begin - out <= 4'hF; - credits <= 0; - - pVB <= 1'b0; - end - else begin - - if (~VB) pVB <= 1'b0; - else if (~pVB) begin - - if (regs[4'h8]==4'h3) begin - credit_add = 0; - credit_sub = 0; - - if ( iINPORT[0] & ( credits < 99 ) ) begin - credit_add = 8'h01; - credits = credits + 1; - end - - if ( regs[4'h9] == 0 ) begin - if ( ( credits >= 2 ) & iINPORT[15] ) begin - credit_sub = 8'h02; - credits = credits - 2; - end else if ( ( credits >= 1 ) & iINPORT[14] ) begin - credit_sub = 8'h01; - credits = credits - 1; - end - end - end - - pINPORT <= fINPORT; - fINPORT <= INPORT; - - pVB <= 1'b1; - end - - if (cs) begin - if (we) regs[adrs] <= wd; - else out <= regs[adrs]; - end - - case ( regs[4'h8] ) - - 4'h1: begin // Switches Input - - regs[4'h4] <= fINPORT[3:0]; - regs[4'h5] <= fINPORT[7:4]; - regs[4'h6] <= fINPORT[11:8]; - regs[4'h7] <= fINPORT[15:12]; - - end - - // 4'h2: begin end // Coinage Setting (not impl.) - - 4'h3: begin // Handle Coin & Switches Input - - regs[4'h0] <= credit_add; - regs[4'h1] <= credit_sub; - regs[4'h2] <= CREDIT_TENS; - regs[4'h3] <= CREDIT_ONES; - - regs[4'h4] <= fINPORT[7:4]; - regs[4'h5] <= { fINPORT[14], iINPORT[14], fINPORT[12], iINPORT[12] }; - regs[4'h6] <= INPORT[11:8]; - regs[4'h7] <= { fINPORT[15], iINPORT[15], fINPORT[13], iINPORT[13] }; - - end - - 4'h4: begin // DIP Switches Input - - regs[4'h0] <= fINPORT[3:0]; - regs[4'h2] <= fINPORT[7:4]; - regs[4'h4] <= fINPORT[11:8]; - regs[4'h6] <= fINPORT[15:12]; - - regs[4'h1] <= fINPORT[19:16]; - regs[4'h3] <= fINPORT[23:20]; - regs[4'h5] <= fINPORT[27:24]; - regs[4'h7] <= fINPORT[31:28]; - - end - - 4'h5: begin // bootup check ( impl. for GAPLUS ) - regs[4'h0] <= 4'hF; - regs[4'h1] <= 4'hF; - end - - default: ; - - endcase - - end - -end - -assign rd = out; - -endmodule - - -//---------------------------------------------------------------- -module GAPLUS_IO_CUS2 -( - input reset, - input clk, - input cs, - input [3:0] adrs, - output [7:0] rd, - input [7:0] wd, - input we, - output kickpcm, - - input [3:0] INP -); - -reg [7:0] mode; -reg [7:0] regs [0:15]; -reg [7:0] out; - -reg [8:0] nkick; - -always @ ( posedge clk or posedge reset ) begin - - if ( reset ) begin - nkick <= 0; - out <= 8'hFF; - end - else begin - if ( cs ) begin - if ( we ) begin - regs[adrs] <= wd; - if ( adrs == 4'h8 ) mode <= wd; - else if ( adrs == 4'h9 ) nkick <= 9'h1FF; - end - else begin - case ( adrs ) - 4'h0: out <= INP; // {SRVSW,Cabinet,2'b11} - 4'h1: out <= ( mode == 4'h2 ) ? regs[adrs] : 4'hF; - 4'h2: out <= ( mode == 4'h2 ) ? 4'hF : 4'hE; - 4'h3: out <= ( mode == 4'h2 ) ? regs[adrs] : 4'h1; - default: out <= regs[adrs]; - endcase - end - end - if ( nkick != 0 ) nkick <= nkick - 1; - end - -end - -assign rd = out; -assign kickpcm = ( nkick != 0 ); - -endmodule - - -//---------------------------------------------------------------- -module add3(in,out); - -input [3:0] in; -output [3:0] out; -reg [3:0] out; - -always @ (in) - case (in) - 4'b0000: out <= 4'b0000; - 4'b0001: out <= 4'b0001; - 4'b0010: out <= 4'b0010; - 4'b0011: out <= 4'b0011; - 4'b0100: out <= 4'b0100; - 4'b0101: out <= 4'b1000; - 4'b0110: out <= 4'b1001; - 4'b0111: out <= 4'b1010; - 4'b1000: out <= 4'b1011; - 4'b1001: out <= 4'b1100; - default: out <= 4'b0000; - endcase - -endmodule - - -module BCDCONV(A,ONES,TENS); - -input [7:0] A; -output [3:0] ONES, TENS; -wire [3:0] c1,c2,c3,c4,c5,c6,c7; -wire [3:0] d1,d2,d3,d4,d5,d6,d7; - -assign d1 = {1'b0,A[7:5]}; -assign d2 = {c1[2:0],A[4]}; -assign d3 = {c2[2:0],A[3]}; -assign d4 = {c3[2:0],A[2]}; -assign d5 = {c4[2:0],A[1]}; -assign d6 = {1'b0,c1[3],c2[3],c3[3]}; -assign d7 = {c6[2:0],c4[3]}; - -add3 m1(d1,c1); -add3 m2(d2,c2); -add3 m3(d3,c3); -add3 m4(d4,c4); -add3 m5(d5,c5); -add3 m6(d6,c6); -add3 m7(d7,c7); - -assign ONES = {c5[2:0],A[0]}; -assign TENS = {c7[2:0],c5[3]}; - -endmodule - - diff --git a/Arcade_MiST/Namco Gaplus/rtl/gaplus_main.v b/Arcade_MiST/Namco Gaplus/rtl/gaplus_main.v deleted file mode 100644 index 64510004..00000000 --- a/Arcade_MiST/Namco Gaplus/rtl/gaplus_main.v +++ /dev/null @@ -1,104 +0,0 @@ -/******************************************** - CPU Modules for "FPGA Gaplus" - - Copyright (c) 2007,2019 MiSTer-X -*********************************************/ - -//---------------------------------------- -// Main CPU -//---------------------------------------- -module gaplus_main -( - input MCPU_CLK, - input RESET, - input VBLK, - - input [31:0] INP0, - input [31:0] INP1, - input [3:0] INP2, - - output [15:0] mcpu_ma, - output mcpu_we, - output [7:0] mcpu_do, - input [7:0] mcpu_mr, - - output snd_we, - input [7:0] snd_rd, - - output mcpu_star_cs, - - output SUB_RESET, - output kick_explode, - output [14:0] main_cpu_addr, - input [7:0] main_cpu_do -); - -wire [7:0] mcpu_di; -wire mcpu_rw, mcpu_vma; -wire mcpu_wr = ~mcpu_rw; -wire mcpu_rd = mcpu_rw; - -wire mcpu_irom_cs = ( mcpu_ma[15] ) & mcpu_vma; -wire mcpu_mram_cs = ( mcpu_ma[15:13] == 3'b000 ) & mcpu_vma; -wire mcpu_srst_cs = ( mcpu_ma[15:12] == 4'b1000 ) & mcpu_vma & mcpu_wr; -wire mcpu_irqe_cs = ( mcpu_ma[15:12] == 4'b0111 ) & mcpu_vma & mcpu_wr; -wire mcpu_sndw_cs = ( mcpu_ma[15:11] == 5'b01100 ) & mcpu_vma; -wire mcpu_iocr_cs; - -wire [7:0] mrom_d; -assign main_cpu_addr = mcpu_ma[14:0]; -assign mrom_d = main_cpu_do; - -assign mcpu_we = mcpu_mram_cs & mcpu_wr; -assign snd_we = mcpu_sndw_cs & mcpu_wr; - -reg mirq_en = 1'b1; -wire mcpu_irq = (~mirq_en) & VBLK; - -reg _SUBRESET = 1'b1; -assign SUB_RESET = _SUBRESET; - -always @ ( negedge MCPU_CLK or posedge RESET ) begin - if ( RESET ) begin - _SUBRESET <= 1; - mirq_en <= 1; - end else begin - if ( mcpu_srst_cs ) _SUBRESET <= mcpu_ma[11]; - if ( mcpu_irqe_cs ) mirq_en <= mcpu_ma[11]; - end -end - -wire [7:0] io_rd; -dataselector4 mcpudsel( - mcpu_di, - mcpu_irom_cs, mrom_d, - mcpu_mram_cs, mcpu_mr, - mcpu_sndw_cs, snd_rd, - mcpu_iocr_cs, io_rd, - 8'hFF -); - -cpu6809 maincpu ( - .clkx2(MCPU_CLK), - .rst(RESET), - .rw(mcpu_rw), - .vma(mcpu_vma), - .address(mcpu_ma), - .data_in(mcpu_di), - .data_out(mcpu_do), - .halt(1'b0), - .hold(1'b0), - .irq(mcpu_irq), - .firq(1'b0), - .nmi(1'b0) -); - -gaplus_io io( - RESET, MCPU_CLK, VBLK, - mcpu_ma, mcpu_vma, mcpu_wr, mcpu_do, io_rd, mcpu_iocr_cs, - INP0, INP1, INP2, kick_explode -); - -assign mcpu_star_cs = ( mcpu_ma[15:11] == 5'b10100 ) & mcpu_vma & mcpu_wr; - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Namco Gaplus/rtl/gaplus_sound.v b/Arcade_MiST/Namco Gaplus/rtl/gaplus_sound.v deleted file mode 100644 index 3a3ed681..00000000 --- a/Arcade_MiST/Namco Gaplus/rtl/gaplus_sound.v +++ /dev/null @@ -1,168 +0,0 @@ -/******************************************* - Sound Module for "FPGA Gaplus" - - Copyright (c) 2007,2019 MiSTer-X -********************************************/ -module gaplus_sound -( - input RESET, - - input CPUCLK, - input CLK24M, - - input VB, - - input com_clk, - input [10:0] com_adrs, - input [7:0] com_wd, - output [7:0] com_rd, - input com_we, - - input pcm_kick, - - output [7:0] SND, - input SND_ENABLE -); - -wire wave_c; -wire [7:0] wave_a; -wire [7:0] wave_d; -wave wave( - .clk(wave_c), - .addr(wave_a), - .data(wave_d) -); -wire [12:0] sndrom_a; -wire [7:0] sndrom_d; -sound sound ( - .clk(CPUCLK), - .addr(sndrom_a), - .data(sndrom_d) -); -wire [15:0] SNDCPU_ADRS; -wire SNDCPU_VMA; -wire SNDCPU_RW; - -wire SNDCPU_WE = ( ~SNDCPU_RW ); -wire SNDCPU_RE = ( SNDCPU_RW ); - -assign sndrom_a = SNDCPU_ADRS[12:0]; -wire [7:0] sndram_d; - -wire sndreg_cs = ( ( SNDCPU_ADRS[15:6] == 10'b0000000000 ) & SNDCPU_VMA ); // $0000-$003F -wire sndram_cs = ( ( SNDCPU_ADRS[15:13] == 3'b000 ) & (~sndreg_cs) & SNDCPU_VMA ); // $0000-$1FFF ($400 image) -wire sndrom_cs = ( ( SNDCPU_ADRS[15:14] == 2'b11 ) & SNDCPU_VMA ); // $C000-$FFFF -wire sndirq_cs = ( ( SNDCPU_ADRS[15:14] == 2'b01 ) & SNDCPU_VMA ); // $4000 - -wire SNDCPU_RESET = RESET; - -reg SNDCPU_IRQEN; -wire SNDCPU_IRQ = VB & ( ~SNDCPU_IRQEN ); - -wire SNDCPU_IRQWE = ( sndirq_cs & SNDCPU_WE ); - -always @( negedge CPUCLK or posedge RESET ) begin - if ( RESET ) begin - SNDCPU_IRQEN <= 1'b1; - end - else begin - if ( SNDCPU_IRQWE ) SNDCPU_IRQEN <= SNDCPU_ADRS[13]; - end -end - -wire [7:0] SNDCPU_DO; -wire [7:0] SNDCPU_DI; - -dataselector2 sndcpu_disel( SNDCPU_DI, sndram_cs, sndram_d, sndrom_cs, sndrom_d, 8'hFF ); - -cpu6809 sndcpu ( - .clkx2(CPUCLK), - .rst(SNDCPU_RESET), - .rw(SNDCPU_RW), - .vma(SNDCPU_VMA), - .address(SNDCPU_ADRS), - .data_in(SNDCPU_DI), - .data_out(SNDCPU_DO), - .halt(1'b0), - .hold(1'b0), - .irq(SNDCPU_IRQ), - .firq(1'b0), - .nmi(1'b0) -); - -dpram2#(11,8)sndram( - .address_a(com_adrs), - .address_b(SNDCPU_ADRS[10:0]), - .clock_a(com_clk), - .clock_b(CPUCLK), - .data_a(com_wd), - .data_b(SNDCPU_DO), - .wren_a(com_we), - .wren_b(sndram_cs & SNDCPU_WE), - .q_a(com_rd), - .q_b(sndram_d) - ); - - -wire pcmclk; -wire [7:0] pcmdat; -pcmplayer pcmplay( pcmclk, RESET, pcm_kick, pcmdat); - - -WSG_8CH_AUX wsg ( - CLK24M, - RESET, - SNDCPU_ADRS[5:0], SNDCPU_DO, sndreg_cs & SNDCPU_WE, - wave_c, wave_a, wave_d, - pcmclk, pcmdat, - SND_ENABLE, - SND -); - - -endmodule - - -module pcmplayer -( - input pcm_clk, - input RESET, - input pcm_kick, - - output reg [7:0] sepcm -); - -reg sekick; -reg [15:0] seadrs; - -wire [7:0] pcm_data; -//DLROM #(15,8) pcm( pcm_clk, seadrs, pcm_data, ROMCL,ROMAD,ROMDT,ROMEN & (ROMAD[17:15]==3'b01_1) ); -//pcm pcm ( -// .clk(pcm_clk), -// .addr(seadrs), -// .data(pcm_data) -//); -always @ ( posedge pcm_clk or posedge RESET ) begin - - if ( RESET ) begin - sekick <= 0; - sepcm <= 0; - end - else begin - if ( sekick ) begin - if ( seadrs >= 16'h8000 ) begin - sekick <= 0; - end - else begin - sepcm <= { 1'b0, pcm_data[7:1] }; - seadrs <= seadrs + 1; - end - end else begin - sekick <= pcm_kick; - seadrs <= 0; - end - end - -end - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Namco Gaplus/rtl/gaplus_sp.v b/Arcade_MiST/Namco Gaplus/rtl/gaplus_sp.v deleted file mode 100644 index 349228a6..00000000 --- a/Arcade_MiST/Namco Gaplus/rtl/gaplus_sp.v +++ /dev/null @@ -1,40 +0,0 @@ -module gaplus_sp( - input clk, - input [14:0] ad, - output [15:0] dt -); - -reg [1:0] _ad; -wire [7:0] dt0, dt1, dt2, dt3; -always @( posedge clk ) _ad <= ad[14:13]; - -obj1 obj1( - .clk(clk), - .addr(ad[12:0]), - .data(dt0) -); - -obj2 obj2( - .clk(clk), - .addr(ad[12:0]), - .data(dt1) -); - -obj3 obj3( - .clk(clk), - .addr(ad[12:0]), - .data(dt2) -); - -obj4 obj4( - .clk(clk), - .addr(ad[12:0]), - .data(dt3) -); - -assign dt = ( _ad == 2'b11 ) ? { 8'h0, dt3 } : - ( _ad == 2'b10 ) ? { 8'h0, dt2 } : - ( _ad == 2'b01 ) ? { dt3, dt1 } : - /* ( _ad == 2'b00 )?*/{ dt3, dt0 } ; - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Namco Gaplus/rtl/gaplus_sprite.v b/Arcade_MiST/Namco Gaplus/rtl/gaplus_sprite.v deleted file mode 100644 index 85257007..00000000 --- a/Arcade_MiST/Namco Gaplus/rtl/gaplus_sprite.v +++ /dev/null @@ -1,294 +0,0 @@ -/********************************************** - Sprite Engine for "FPGA Gaplus" - - Copyright (c) 2007,2019 MiSTer-X -***********************************************/ -module gaplus_sprite -( - input VCLKx4, - input VCLK, - - input [8:0] HPOS, - input [8:0] VPOS, - - input HB, - input VB, - - output [14:0] SPCH_A, - input [15:0] SPCH_D, - - output [6:0] SPRA_A, - input [23:0] SPRA_D, - - output [8:0] CLUT_A -); - -wire wwclk, wrwe, vpr; -wire [5:0] wrwad; -wire [28:0] wrwd0; -wire [23:0] wrwd1; - -wire wrclk, lwe, vpw; -wire [5:0] wrrad; -wire [28:0] spra0; -wire [23:0] spra1; -wire [8:0] lwp; -wire [8:0] lwd; - -wire [8:0] dout; - -GAPLUS_SPRITE_REGSCAN scan( VCLKx4, HB, VPOS, SPRA_A, SPRA_D, wwclk, wrwad, wrwd0, wrwd1, wrwe, vpr ); -GAPLUS_SPRITE_WRAM wram( wwclk, wrwad, wrwd0, wrwd1, wrwe, wrclk, wrrad, spra0, spra1 ); -GAPLUS_SPRITE_REND rend( VCLK, HB, vpr, spra0, spra1, wrclk, wrrad, SPCH_A, SPCH_D, vpw, lwp, lwd, lwe ); -GAPLUS_SPRITE_LBUF lbuf( VCLK, vpw, lwe, lwp, lwd, HPOS, dout ); - -assign CLUT_A = dout; - -endmodule - - -//---------------------------------------- -// Scanline Renderer -//---------------------------------------- -module GAPLUS_SPRITE_REND -( - input VCLK, - input HB, - input vpr, - input [28:0] spra0, - input [23:0] spra1, - output wrclk, - output [5:0] wrrad, - output [14:0] SPCH_A, - input [15:0] SPCH_D, - - output vpw, - output [8:0] wp, - output [8:0] wd, - output we -); - -reg [7:0] phase; -reg [5:0] hc; - -wire xf = spra0[16]; -wire yf = spra0[17]; - -wire xs = spra0[19]; -wire ys = spra0[21]; - -wire dp = spra0[23]; - -wire [1:0] coffs = dp ? 0 : { (~spra0[28])^((~yf)&ys), hc[4]^(xf&xs) }; - -wire [8:0] chipno = { spra0[22], spra0[7:0] } + { 7'h0, coffs }; -wire [5:0] paltno = { spra1[5:0] }; - -wire [3:0] va = spra0[27:24]^{yf,yf,yf,yf}; -wire [1:0] pdp = ( hc[1:0]^{xf,xf} ); - -wire [2:0] pixd = ( pdp == 0 ) ? { chipno[7] ? SPCH_D[11] : SPCH_D[15], SPCH_D[7], SPCH_D[3] } : - ( pdp == 1 ) ? { chipno[7] ? SPCH_D[10] : SPCH_D[14], SPCH_D[6], SPCH_D[2] } : - ( pdp == 2 ) ? { chipno[7] ? SPCH_D[ 9] : SPCH_D[13], SPCH_D[5], SPCH_D[1] } : - { chipno[7] ? SPCH_D[ 8] : SPCH_D[12], SPCH_D[4], SPCH_D[0] }; - -assign we = xs ? ( hc < 32 ) : ( hc < 16 ); -assign wd = { paltno, pixd }; - -reg hbedge2; -always @ ( posedge VCLK ) begin - if ( HB & (~hbedge2) ) begin - phase <= 0; - hbedge2 <= 1; - end - else begin - if (~HB) hbedge2 <= 0; - if (~phase[7]) begin - case ( phase[1:0] ) - 2'h0: begin - hc <= 0; - phase <= phase + 1; - end - 2'h1: phase <= phase + 1; - 2'h2: if (~we) phase <= phase + 2; else hc <= hc + 1; - default: begin end - endcase - end - end - -end - -assign wrclk = VCLK; -assign wrrad = { vpr, phase[6:2] }; -assign SPCH_A = { chipno, va[3], hc[3:2]^{2{xf}}, va[2:0] }; - -assign vpw = ~vpr; -assign wp = ( spra1[16:8] - 88 ) + hc; - -endmodule - -//---------------------------------------- -// Attribute Register Scanner -//---------------------------------------- -module GAPLUS_SPRITE_REGSCAN -( - input VCLKx4, - input HB, - input [7:0] VPOS, - output [6:0] SPRA_A, - input [23:0] SPRA_D, - output wwclk, - output [5:0] wrwad, - output [28:0] wrwd0, - output [23:0] wrwd1, - output wrwe, - output vpr -); - -reg [11:0] hcntx4; -reg hbedge, vpf; - -always @ ( posedge VCLKx4 ) begin - - if ( HB & (~hbedge) ) begin - hcntx4 <= 0; - vpf <= ~vpf; - hbedge <= 1; - end else begin - if (~HB) hbedge <= 0; - hcntx4 <= hcntx4 + 1; - end - -end - -assign vpr = vpf; -wire vpw = ~vpf; - -reg [23:0] nspra0; -reg [23:0] nspra1; - -reg [7:0] nvpos; -reg [5:0] hramad; - -reg wrwe0; - -//wire [8:0] nxt = nspra1[16:8] - 87; -wire [7:0] nyt = nspra0[15:8] + 27; - -wire nys = nspra0[21]; -wire [7:0] nvt = nvpos + nyt; -wire nvh = nys ? ( nvt[7:5] == 3'b111 ) : ( nvt[7:4] == 4'b1111 ); - -wire son = (~nspra1[17]) & ( nspra0[15:8] != 8'hF0 ) & ( nspra1[16:8] != 9'h00 ); - -wire [11:0] _hcntx4 = hcntx4 - 32; - -wire wrclr = ( hcntx4 < 32 ); -assign wwclk = VCLKx4; -assign wrwd0 = wrclr ? 0 : { nvt[4:0], nspra0 }; -assign wrwd1 = wrclr ? 0 : nspra1; -assign wrwad = wrclr ? { vpw, hcntx4[4:0] } : { vpw, hramad[4:0] }; -assign wrwe = wrclr ? 1 : wrwe0; - -always @ ( posedge VCLKx4 ) begin - - if ( hcntx4 == 0 ) begin - hramad <= 0; - nvpos <= VPOS[7:0]; - wrwe0 <= 0; - end - else begin - if ( ( hcntx4 < 544 ) & ( hramad < 32 ) ) begin - case ( hcntx4[2:0] ) - 3'h0: nspra0 <= SPRA_D; - 3'h1: nspra1 <= SPRA_D; - 3'h4: wrwe0 <= nvh & son; - 3'h5: begin - if ( wrwe0 ) hramad <= hramad + 1; - wrwe0 <= 0; - end - default: begin end - endcase - end - end -end - -assign SPRA_A = { _hcntx4[8:3], _hcntx4[0] }; - -endmodule - -//---------------------------------------- -// Work RAM -//---------------------------------------- -module GAPLUS_SPRITE_WRAM( CLKw, ADRSw, Dw0, Dw1, we, CLKr, ADRSr, Dr0, Dr1 ); - -input CLKw; -input [5:0] ADRSw; -input [28:0] Dw0; -input [23:0] Dw1; -input we; - -input CLKr; -input [5:0] ADRSr; -output [28:0] Dr0; -output [23:0] Dr1; - -BUF64_53 mem ( - {Dw1,Dw0},ADRSr,CLKr, - ADRSw,CLKw,we,{Dr1,Dr0} -); - -endmodule - - -//---------------------------------------- -// Line Double Buffer -//---------------------------------------- -module GAPLUS_SPRITE_LBUF( CLK, SIDE1, WEN, ADRSW, IN, ADRSR, OUT ); - -input CLK; -input SIDE1; -input WEN; -input [8:0] ADRSW; -input [8:0] IN; -input [8:0] ADRSR; -output [8:0] OUT; - -wire [8:0] OUT0, OUT1; - -wire SIDE0 = ~SIDE1; -wire OPAQUE = ( IN[2:0] != 0 ); - -assign OUT = SIDE1 ? OUT1 : OUT0; - -LINEBUF buf0( CLK, SIDE0 ? 1 : ( WEN & SIDE1 & OPAQUE ), SIDE0 ? ADRSR-1 : ADRSW, SIDE0 ? 0 : IN, CLK, SIDE0, ADRSR, OUT0 ); -LINEBUF buf1( CLK, SIDE1 ? 1 : ( WEN & SIDE0 & OPAQUE ), SIDE1 ? ADRSR-1 : ADRSW, SIDE1 ? 0 : IN, CLK, SIDE1, ADRSR, OUT1 ); - -endmodule - - -module LINEBUF( CLKW, WEN, ADRSW, IN, CLKR, REN, ADRSR, OUT ); - -input CLKW; -input WEN; -input [8:0] ADRSW; -input [8:0] IN; -input CLKR; -input REN; -input [8:0] ADRSR; -output [8:0] OUT; - -wire [8:0] dum; - -LBUF512_9 mem ( - ADRSR,ADRSW, - CLKR,CLKW, - 9'h0,IN, - REN,1'b0, - 1'b0,WEN, - OUT,dum -); - - -endmodule - diff --git a/Arcade_MiST/Namco Gaplus/rtl/gaplus_srams.v b/Arcade_MiST/Namco Gaplus/rtl/gaplus_srams.v deleted file mode 100644 index 7a3ca8a4..00000000 --- a/Arcade_MiST/Namco Gaplus/rtl/gaplus_srams.v +++ /dev/null @@ -1,124 +0,0 @@ -/********************************************** - Share memory module for "FPGA Gaplus" - - Copyright (c) 2007,2019 MiSTer-X -***********************************************/ -module gaplus_sharemem -( - input clk, - input vclk, - - input sel, - - input [15:0] ad0, - output [7:0] rd0, - input [7:0] wd0, - input we0, - - input [15:0] ad1, - output [7:0] rd1, - input [7:0] wd1, - input we1, - - input [9:0] vram_a, - output [15:0] vram_d, - - input [6:0] spra_a, - output [23:0] spra_d -); - -wire [6:0] dum; -wire [15:0] ad; -wire [7:0] wd; -wire we; - -gaplus_busdriver arb( 1'b1, - sel, - { 7'h0, ad0[15:0], wd0[7:0], we0 }, - { 7'h0, ad1[15:0], wd1[7:0], we1 }, - { dum, ad[15:0], wd[7:0], we } -); - -wire [7:0] o3I, o3J, o3M, o3K, o3L; - -wire e3I = ( ad[15:10] == 6'b000000 ); -wire e3J = ( ad[15:10] == 6'b000001 ); -wire e3M = ( ad[15:11] == 5'b00001 ); -wire e3K = ( ad[15:11] == 5'b00010 ); -wire e3L = ( ad[15:11] == 5'b00011 ); - -wire [7:0] rd = e3I ? o3I : - e3J ? o3J : - e3M ? o3M : - e3K ? o3K : - e3L ? o3L : - 8'hFF; - -//DPRAM_1024V sram3I( clk, ad[9:0], wd, o3I, we & e3I, vclk, vram_a, vram_d[7:0] ); -dpram #(10,8) sram3I( - .clk_a_i(clk), - .en_a_i(1), - .we_i(we & e3I), - .addr_a_i(ad[9:0]), - .data_a_i(wd), - .data_a_o(o3I), - .clk_b_i(vclk), - .addr_b_i(vram_a), - .data_b_o(vram_d[7:0]) -); - -//DPRAM_1024V sram3J( clk, ad[9:0], wd, o3J, we & e3J, vclk, vram_a, vram_d[15:8] ); -dpram #(10,8) sram3J( - .clk_a_i(clk), - .en_a_i(1), - .we_i(we & e3J), - .addr_a_i(ad[9:0]), - .data_a_i(wd), - .data_a_o(o3J), - .clk_b_i(vclk), - .addr_b_i(vram_a), - .data_b_o(vram_d[15:8]) -); - -//DPRAM_2048V sram3M( clk, ad[10:0], wd, o3M, we & e3M, vclk, { 4'b1111, spra_a }, spra_d[7:0] ); -dpram #(11,8) sram3M( - .clk_a_i(clk), - .en_a_i(1), - .we_i(we & e3M), - .addr_a_i(ad[10:0]), - .data_a_i(wd), - .data_a_o(o3M), - .clk_b_i(vclk), - .addr_b_i({ 4'b1111, spra_a }), - .data_b_o(spra_d[7:0]) -); -//DPRAM_2048V sram3K( clk, ad[10:0], wd, o3K, we & e3K, vclk, { 4'b1111, spra_a }, spra_d[15:8] ); -dpram #(11,8) sram3K( - .clk_a_i(clk), - .en_a_i(1), - .we_i(we & e3K), - .addr_a_i(ad[10:0]), - .data_a_i(wd), - .data_a_o(o3K), - .clk_b_i(vclk), - .addr_b_i({ 4'b1111, spra_a }), - .data_b_o(spra_d[15:8]) -); -//DPRAM_2048V sram3L( clk, ad[10:0], wd, o3L, we & e3L, vclk, { 4'b1111, spra_a }, spra_d[23:16] ); -dpram #(11,8) sram3L( - .clk_a_i(clk), - .en_a_i(1), - .we_i(we & e3L), - .addr_a_i(ad[10:0]), - .data_a_i(wd), - .data_a_o(o3L), - .clk_b_i(vclk), - .addr_b_i({ 4'b1111, spra_a }), - .data_b_o(spra_d[23:16]) -); - -assign rd0 = rd; -assign rd1 = rd; - -endmodule - diff --git a/Arcade_MiST/Namco Gaplus/rtl/gaplus_stargen.v b/Arcade_MiST/Namco Gaplus/rtl/gaplus_stargen.v deleted file mode 100644 index e6b7955d..00000000 --- a/Arcade_MiST/Namco Gaplus/rtl/gaplus_stargen.v +++ /dev/null @@ -1,92 +0,0 @@ -/********************************************* - StarField Generator for "FPGA Gaplus" - - Copyright (c) 2007,2019 MiSTer-X -**********************************************/ -module gaplus_stargen -( - input VCLK, - input RESET, - - input VB, - - input [4:0] C1, - input [4:0] C2, - input [4:0] C3, - - output reg [7:0] OUT -); - -reg vbtrig; - -reg [11:0] sp1, sp2, sp3; -reg sp1d, sp2d, sp3d; - -reg [15:0] sLFSR1 = 16'hACE1, LFSR1; -reg [15:0] sLFSR2 = 16'hACE1, LFSR2; -reg [15:0] sLFSR3 = 16'hACE1, LFSR3; - -wire [7:0] oSTAR1 = ( LFSR1[15:8] == 8'h80 ) ? LFSR1[7:0] : 0; -wire [7:0] oSTAR2 = ( LFSR2[15:8] == 8'h90 ) ? LFSR2[7:0] : 0; -wire [7:0] oSTAR3 = ( LFSR3[15:8] == 8'hA0 ) ? LFSR3[7:0] : 0; - - -function [15:0] LFSR; -input [15:0] in; -input dir; - if ( dir ) LFSR = { in[14:0], ((in[15]^in[4])^in[2])^in[1] }; // backward - else LFSR = { ((in[0]^in[2])^in[3])^in[5], in[15:1] }; // forward -endfunction - -always @ ( posedge VCLK or posedge RESET ) begin - - if ( RESET ) begin - - sLFSR1 <= 16'hACE1; - sLFSR2 <= 16'hACE1; - sLFSR3 <= 16'hACE1; - - OUT <= 0; - - vbtrig <= 0; - - end - else begin - - if ( VB & (~vbtrig) ) begin - - sp1 <= C1[4] ? (12'd384 * C1[2:0]) : C1[2:0]; sp1d <= C1[3]; - sp2 <= C2[4] ? (12'd384 * C2[2:0]) : C2[2:0]; sp2d <= C2[3]; - sp3 <= C3[4] ? (12'd384 * C3[2:0]) : C3[2:0]; sp3d <= C3[3]; - - LFSR1 <= sLFSR1; - LFSR2 <= sLFSR2; - LFSR3 <= sLFSR3; - - vbtrig <= 1; - - end - else begin - - if ( ~VB ) begin - OUT <= ( oSTAR1 ? oSTAR1 : ( oSTAR2 ? oSTAR2 : oSTAR3 ) ); - - LFSR1 <= LFSR(LFSR1,0); - LFSR2 <= LFSR(LFSR2,0); - LFSR3 <= LFSR(LFSR3,0); - - vbtrig <= 0; - end - - if ( sp1 ) begin sLFSR1 <= LFSR(sLFSR1,~sp1d); sp1 <= sp1-1; end - if ( sp2 ) begin sLFSR2 <= LFSR(sLFSR2,~sp2d); sp2 <= sp2-1; end - if ( sp3 ) begin sLFSR3 <= LFSR(sLFSR3,~sp3d); sp3 <= sp3-1; end - - end - - end - -end - -endmodule - diff --git a/Arcade_MiST/Namco Gaplus/rtl/gaplus_sub.v b/Arcade_MiST/Namco Gaplus/rtl/gaplus_sub.v deleted file mode 100644 index aa47f4ce..00000000 --- a/Arcade_MiST/Namco Gaplus/rtl/gaplus_sub.v +++ /dev/null @@ -1,96 +0,0 @@ -//---------------------------------------- -// Sub CPU -//---------------------------------------- -module gaplus_sub -( - input SCPU_CLK, - input RESET, - input VBLK, - - input [7:0] scpu_mr, - output [15:0] scpu_ma, - output scpu_we, - output [7:0] scpu_do, - output [14:0] sub_cpu_addr, - input [7:0] sub_cpu_do -); - -wire [7:0] scpu_di; -wire scpu_rw, scpu_vma; -wire scpu_wr = ~scpu_rw; -wire scpu_rd = scpu_rw; - -wire scpu_irom_cs = ( scpu_ma[15] ) & scpu_vma; -wire scpu_mram_cs = ( scpu_ma[15:13] == 3'b000 ) & scpu_vma; -wire scpu_irqe_cs = ( scpu_ma[15:12] == 4'b0110 ) & scpu_vma; - -wire [7:0] srom_d; -assign sub_cpu_addr = scpu_ma[14:0]; -assign srom_d = sub_cpu_do; - -dataselector2 scpu_disel( scpu_di, scpu_irom_cs, srom_d, scpu_mram_cs, scpu_mr, 8'hFF ); - -assign scpu_we = scpu_mram_cs & scpu_wr; - -reg sirq_en = 1'b1; -wire scpu_irq = (~sirq_en) & VBLK; - -always @ ( negedge SCPU_CLK or posedge RESET ) begin - if ( RESET ) begin - sirq_en <= 1'b1; - end else begin - if ( scpu_irqe_cs ) sirq_en <= (~scpu_ma[0]); - end -end - -cpu6809 subcpu ( - .clkx2(SCPU_CLK), - .rst(RESET), - .rw(scpu_rw), - .vma(scpu_vma), - .address(scpu_ma), - .data_in(scpu_di), - .data_out(scpu_do), - .halt(1'b0), - .hold(1'b0), - .irq(scpu_irq), - .firq(1'b0), - .nmi(1'b0) -); - -endmodule - - -// CPU core wrapper -module cpu6809 -( - input clkx2, - input rst, - output rw, - output vma, - output [15:0] address, - input [7:0] data_in, - output [7:0] data_out, - input halt, - input hold, - input irq, - input firq, - input nmi -); - -// Phase Generator -reg rE=1'b0, rQ=1'b0; -always @(posedge clkx2) rQ <= ~rQ; -always @(negedge clkx2) rE <= ~rE; - -// CPU core -mc6809i core ( - .D(data_in),.DOut(data_out),.ADDR(address),.RnW(rw),.E(rE),.Q(rQ), - .nIRQ(~irq),.nFIRQ(~firq),.nNMI(~nmi), - .nHALT(~halt),.nRESET(~rst), - .nDMABREQ(1'b1) -); - -assign vma = rE; - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Namco Gaplus/rtl/gaplus_top.v b/Arcade_MiST/Namco Gaplus/rtl/gaplus_top.v deleted file mode 100644 index bea0c60f..00000000 --- a/Arcade_MiST/Namco Gaplus/rtl/gaplus_top.v +++ /dev/null @@ -1,189 +0,0 @@ -/********************************************************* - FPGA Gaplus port to MiSTer - - Copyright (c) 2007,2019 MiSTer-X -**********************************************************/ -module gaplus_top -( - input RESET, // RESET - input MCLK, // MasterClock: 49.125MHz - - input [8:0] PH, // Screen H - input [8:0] PV, // Screen V - output PCLK, // Pixel Clock - output [11:0] POUT, // Pixel Color - - output [7:0] SOUT, // Sound Out - - // Sticks and Buttons (Active Logic) - input [4:0] INP0, // 1P {B1,L,D,R,U} - input [4:0] INP1, // 2P {B1,L,D,R,U} - input [2:0] INP2, // {Coin,Start2P,Start1P} - - input [7:0] DSW0, // DIPSWs (Active Logic) - input [7:0] DSW1, - input [7:0] DSW2, - output [14:0] main_cpu_addr, - input [7:0] main_cpu_do, - output [14:0] sub_cpu_addr, - input [7:0] sub_cpu_do -); - -//---------------------------------------- -// Input port connection -//---------------------------------------- -wire CIN1 = INP2[2]; -wire ST1P = INP2[0]; -wire ST2P = INP2[1]; - -wire TRG1 = INP0[4]; -wire TRG2 = INP1[4]; - -wire [3:0] P1 = INP0[3:0]; // {L,D,R,U} -wire [3:0] P2 = INP1[3:0]; -wire [3:0] BUTS = { ST2P, ST1P, TRG2, TRG1 }; -wire [3:0] CINS = { 1'b0, 1'b0, 1'b0, CIN1 }; // {Service,none,Coin2,Coin1} - -wire [31:0] INTF0 = { 16'h0, BUTS, P2, P1, CINS }; -wire [31:0] INTF1 = {{DSW0[3:0],DSW1[7:4],DSW1[3:0],DSW0[7:4]},{DSW0[3:0],DSW1[7:4],DSW1[3:0],DSW0[7:4]}}; -wire [3:0] INTF2 = { DSW2[1:0], 2'b11 }; // {Serv.Mode(Gal3),Cabinet,2'b11} - - -//---------------------------------------- -// Clock Generator -//---------------------------------------- -reg [4:0] CLKS; -always @( posedge MCLK ) CLKS <= CLKS+1; - -wire CLK50M = MCLK; -wire CLK25M = CLKS[0]; -wire CLK12M5 = CLKS[1]; -wire CLK6M25 = CLKS[2]; -wire CLK3M125 = CLKS[3]; -wire CLK1M60 = CLKS[4]; - -wire VCLK_x4 = CLK25M; -wire VCLK_x2 = CLK12M5; -wire VCLK_x1 = CLK6M25; - -wire VCLKx2 = VCLK_x2; - -wire CPUCLKx4 = CLK6M25; -wire CPUCLKx2 = CLK3M125; -wire CPUCLK = CLK1M60; - -wire MCPU_CLK = CPUCLKx2; -wire SCPU_CLK = ~CPUCLKx2; - - -assign PCLK = VCLK_x1; - - -//---------------------------------------- -// Share Memory Module -//---------------------------------------- -wire [15:0] mcpu_ma; -wire [7:0] mcpu_mr; -wire [7:0] mcpu_do; -wire mcpu_we; - -wire [15:0] scpu_ma; -wire [7:0] scpu_mr; -wire [7:0] scpu_do; -wire scpu_we; - -wire [10:0] vram_a; -wire [15:0] vram_d; - -wire [ 6:0] spra_a; -wire [23:0] spra_d; - - -gaplus_sharemem smem -( - CPUCLKx4, - CLK50M, - MCPU_CLK, - mcpu_ma, mcpu_mr, mcpu_do, mcpu_we, - scpu_ma, scpu_mr, scpu_do, scpu_we, - vram_a, vram_d, - spra_a, spra_d -); - - -//---------------------------------------- -// Video Module -//---------------------------------------- -wire mcpu_star_cs; -wire oVB; - -gaplus_video video -( - .CLK50M(CLK50M), - .VCLKx4(VCLK_x4), - .VCLKx2(VCLK_x2), - .VCLK(VCLK_x1), - .RESET(RESET), - - .PH(PH),.PV(PV), - .POUT(POUT),.VB(oVB), - - .VRAM_A(vram_a), .VRAM_D(vram_d), - .SPRA_A(spra_a), .SPRA_D(spra_d), - - .STAR_AD(mcpu_ma[1:0]), - .STAR_DT(mcpu_do), - .STAR_WE(mcpu_star_cs) -); - - -//---------------------------------------- -// MAIN CPU -//---------------------------------------- -wire SUB_RESET; -wire kick_explode; -wire [7:0] snd_rd; -wire snd_we; - -gaplus_main main -( - MCPU_CLK, RESET, oVB, - INTF0, INTF1, INTF2, - mcpu_ma, mcpu_we, mcpu_do, mcpu_mr, - snd_we, snd_rd, - mcpu_star_cs, - SUB_RESET, kick_explode, - main_cpu_addr, main_cpu_do -// ROMCL,ROMAD,ROMDT,ROMEN -); - - -//---------------------------------------- -// Sub CPU -//---------------------------------------- -gaplus_sub sub -( - SCPU_CLK, SUB_RESET, oVB, - scpu_mr, - scpu_ma, scpu_we, scpu_do, - sub_cpu_addr, sub_cpu_do -); - - -//---------------------------------------- -// Sound Module -//---------------------------------------- -gaplus_sound sound -( - SUB_RESET, - MCPU_CLK, - VCLK_x4, - oVB, - CLK50M, { 1'b0, mcpu_ma[9:0] }, mcpu_do, snd_rd, snd_we, - kick_explode, - SOUT, - ~SUB_RESET -); - - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Namco Gaplus/rtl/gaplus_video.v b/Arcade_MiST/Namco Gaplus/rtl/gaplus_video.v deleted file mode 100644 index 1ff52c2f..00000000 --- a/Arcade_MiST/Namco Gaplus/rtl/gaplus_video.v +++ /dev/null @@ -1,234 +0,0 @@ -/******************************************* - Video Module for "FPGA Gaplus" - - Copyright (c) 2007,2019 MiSTer-X -********************************************/ -module gaplus_video -( - input CLK50M, // 50.0MHz - input VCLKx4, // 25.0MHz - input VCLKx2, // 12.5MHz - input VCLK, // 6.25MHz - - input RESET, - - input [8:0] PH, - input [8:0] PV, - output [11:0] POUT, - output VB, - - output [10:0] VRAM_A, - input [15:0] VRAM_D, - - output [6:0] SPRA_A, - input [23:0] SPRA_D, - - input [1:0] STAR_AD, - input [7:0] STAR_DT, - input STAR_WE -); - - -wire [8:0] HPOS = PH-16; -wire [8:0] VPOS = PV; - -assign VB = (PV == 224) & (PH < 32); -wire oHB = (PH >= 290); - - -//---------------------------------------- -// ROMs -//---------------------------------------- -wire [7:0] PALT_A; -wire [7:0] PALT_R, PALT_G, PALT_B; -wire [11:0] PALT_D; -pal_r pal_r( - .clk(CLK50M), - .addr(PALT_A), - .data(PALT_R) -); - -pal_g pal_g( - .clk(CLK50M), - .addr(PALT_A), - .data(PALT_G) -); - -pal_b pal_b( - .clk(CLK50M), - .addr(PALT_A), - .data(PALT_B) -); -assign PALT_D = {PALT_B[3:0],PALT_G[3:0],PALT_R[3:0]}; - -wire [7:0] CLT0_A; -wire [7:0] CLT0_D; -pal_c pal_c( - .clk(CLK50M), - .addr(CLT0_A), - .data(CLT0_D) -); - -wire [9:0] CLT1_A; -wire [7:0] CLT1_D; -pal_sl pal_sl( - .clk(CLK50M), - .addr(CLT1_A[8:0]), - .data(CLT1_D[3:0]) -); - -pal_sh pal_sh( - .clk(CLK50M), - .addr(CLT1_A[8:0]), - .data(CLT1_D[7:4]) -); - -wire [13:0] BGCH_A; -wire [7:0] BGCH_D; -gaplus_bg gaplus_bg( - .clk(CLK50M), - .ad(BGCH_A), - .dt(BGCH_D) -); - -wire [14:0] SPCH_A; -wire [15:0] SPCH_D; -gaplus_sp gaplus_sp( - .clk(CLK50M), - .ad(SPCH_A), - .dt(SPCH_D) -); - -//---------------------------------------- -// BG Scanline Generator -//---------------------------------------- -reg [7:0] BGPN; -reg BGHI; - -wire [5:0] COL = HPOS[8:3]; -wire [5:0] ROW = VPOS[8:3] + 6'h02; - -wire [8:0] CHRC = { VRAM_D[15], VRAM_D[7:0] }; -wire [5:0] BGPL = VRAM_D[13:8]; -wire PRIO = VRAM_D[14]; - -wire [8:0] HP = HPOS; -wire [8:0] VP = VPOS; - -wire [7:0] CHRO = BGCH_D; - -wire [1:0] p0 = { 1'b1, ~HP[0] }; -wire [1:0] p1 = { 1'b0, ~HP[0] }; - -always @ ( posedge VCLK ) begin - BGPN <= { BGPL, CHRO[p0[1]], CHRO[p1[1]] }; - BGHI <= PRIO; -end - -gaplus_busdriver vramadrs( 1'b1, COL[5], { COL[4:0], ROW[4:0] }, { ROW[4:0], COL[4:0] }, VRAM_A ); - -assign BGCH_A = { CHRC, ~HP[2], HP[1], VP[2:0] }; -assign CLT0_A = BGPN; - -wire [7:0] BGCOL = { 4'hF, CLT0_D[3:0] }; -wire BGOPQ = (CLT0_D[3:0]!=4'hF); - - -//---------------------------------------- -// Sprite Engine -//---------------------------------------- -wire [7:0] SPCOL = CLT1_D; -wire SPOPQ = (CLT1_D!=8'hFF); -wire oVB; -gaplus_sprite sprite -( - VCLKx4, - VCLK, - HPOS, VPOS, - oHB, oVB, - SPCH_A, SPCH_D, - SPRA_A, SPRA_D, - CLT1_A -); - - -//---------------------------------------- -// StarField Generator -//---------------------------------------- -reg [7:0] starreg0; -reg [4:0] starreg1; -reg [4:0] starreg2; -reg [4:0] starreg3; - -always @ ( posedge VCLKx4 or posedge RESET ) begin - if ( RESET ) begin - starreg0 <= 0; - starreg1 <= 0; - starreg2 <= 0; - starreg3 <= 0; - end - else begin - if ( STAR_WE ) begin - case ( STAR_AD ) - 2'h0: starreg0 <= STAR_DT; - 2'h1: starreg1 <= stargen_com(STAR_DT); - 2'h2: starreg2 <= stargen_com(STAR_DT); - 2'h3: starreg3 <= stargen_com(STAR_DT); - default: begin end - endcase - end - end -end - -wire [7:0] _oSTAR; -wire [7:0] oSTAR = _oSTAR & { 8{starreg0[0]} }; - -function [4:0] stargen_com; -input [7:0] com; - - case (com) - - 8'h86: stargen_com = { 1'b0, 1'b0, 3'h1 }; - 8'h85: stargen_com = { 1'b0, 1'b0, 3'h2 }; - 8'h06: stargen_com = { 1'b0, 1'b0, 3'h3 }; - - 8'h80: stargen_com = { 1'b0, 1'b1, 3'h1 }; - 8'h82: stargen_com = { 1'b0, 1'b1, 3'h2 }; - 8'h81: stargen_com = { 1'b0, 1'b1, 3'h3 }; - - 8'h9F: stargen_com = { 1'b1, 1'b0, 3'h3 }; - 8'hAF: stargen_com = { 1'b1, 1'b0, 3'h2 }; - - default: stargen_com = 0; - - endcase - -endfunction - - -gaplus_stargen stargen( - VCLK, - RESET, - VB, - starreg1, - starreg2, - starreg3, - _oSTAR -); - -//---------------------------------------- -// Color mixer & Pixel output -//---------------------------------------- -wire BGHIOPQ = BGHI & BGOPQ; -wire SPTRNSP = ~SPOPQ; - -dataselector2 colormixer( - PALT_A, - BGHIOPQ | ( SPTRNSP & BGOPQ ), BGCOL, - SPOPQ, SPCOL, - oSTAR -); - -assign POUT = { PALT_D[11:8],PALT_D[7:4],PALT_D[3:0]}; - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Namco Gaplus/rtl/hvgen.v b/Arcade_MiST/Namco Gaplus/rtl/hvgen.v deleted file mode 100644 index 46dc5f38..00000000 --- a/Arcade_MiST/Namco Gaplus/rtl/hvgen.v +++ /dev/null @@ -1,41 +0,0 @@ -module hvgen -( - output [8:0] HPOS, - output [8:0] VPOS, - input PCLK, - input [11:0] iRGB, - - output reg [11:0] oRGB, - output reg HBLK = 1, - output reg VBLK = 1, - output reg HSYN = 1, - output reg VSYN = 1 -); - -reg [8:0] hcnt = 0; -reg [8:0] vcnt = 0; - -assign HPOS = hcnt; -assign VPOS = vcnt; - -always @(posedge PCLK) begin - case (hcnt) - 0: begin HBLK <= 0; hcnt <= hcnt+1; end - 289: begin HBLK <= 1; hcnt <= hcnt+1; end - 311: begin HSYN <= 0; hcnt <= hcnt+1; end - 342: begin HSYN <= 1; hcnt <= 471; end - 511: begin hcnt <= 0; - case (vcnt) - 223: begin VBLK <= 1; vcnt <= vcnt+1; end - 226: begin VSYN <= 0; vcnt <= vcnt+1; end - 233: begin VSYN <= 1; vcnt <= 483; end - 511: begin VBLK <= 0; vcnt <= 0; end - default: vcnt <= vcnt+1; - endcase - end - default: hcnt <= hcnt+1; - endcase - oRGB <= (HBLK|VBLK) ? 12'h0 : iRGB; -end - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Namco Gaplus/rtl/pll.qip b/Arcade_MiST/Namco Gaplus/rtl/pll.qip deleted file mode 100644 index afd958be..00000000 --- a/Arcade_MiST/Namco Gaplus/rtl/pll.qip +++ /dev/null @@ -1,4 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade_MiST/Namco Gaplus/rtl/pll.v b/Arcade_MiST/Namco Gaplus/rtl/pll.v deleted file mode 100644 index 2e335944..00000000 --- a/Arcade_MiST/Namco Gaplus/rtl/pll.v +++ /dev/null @@ -1,337 +0,0 @@ -// megafunction wizard: %ALTPLL% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: altpll - -// ============================================================ -// File Name: pll.v -// Megafunction Name(s): -// altpll -// -// Simulation Library Files(s): -// altera_mf -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 13.1.4 Build 182 03/12/2014 SJ Full Version -// ************************************************************ - - -//Copyright (C) 1991-2014 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files from any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module pll ( - inclk0, - c0, - c1, - locked); - - input inclk0; - output c0; - output c1; - output locked; - - wire [4:0] sub_wire0; - wire sub_wire2; - wire [0:0] sub_wire6 = 1'h0; - wire [0:0] sub_wire3 = sub_wire0[0:0]; - wire [1:1] sub_wire1 = sub_wire0[1:1]; - wire c1 = sub_wire1; - wire locked = sub_wire2; - wire c0 = sub_wire3; - wire sub_wire4 = inclk0; - wire [1:0] sub_wire5 = {sub_wire6, sub_wire4}; - - altpll altpll_component ( - .inclk (sub_wire5), - .clk (sub_wire0), - .locked (sub_wire2), - .activeclock (), - .areset (1'b0), - .clkbad (), - .clkena ({6{1'b1}}), - .clkloss (), - .clkswitch (1'b0), - .configupdate (1'b0), - .enable0 (), - .enable1 (), - .extclk (), - .extclkena ({4{1'b1}}), - .fbin (1'b1), - .fbmimicbidir (), - .fbout (), - .fref (), - .icdrclk (), - .pfdena (1'b1), - .phasecounterselect ({4{1'b1}}), - .phasedone (), - .phasestep (1'b1), - .phaseupdown (1'b1), - .pllena (1'b1), - .scanaclr (1'b0), - .scanclk (1'b0), - .scanclkena (1'b1), - .scandata (1'b0), - .scandataout (), - .scandone (), - .scanread (1'b0), - .scanwrite (1'b0), - .sclkout0 (), - .sclkout1 (), - .vcooverrange (), - .vcounderrange ()); - defparam - altpll_component.bandwidth_type = "AUTO", - altpll_component.clk0_divide_by = 50, - altpll_component.clk0_duty_cycle = 50, - altpll_component.clk0_multiply_by = 91, - altpll_component.clk0_phase_shift = "0", - altpll_component.clk1_divide_by = 16, - altpll_component.clk1_duty_cycle = 50, - altpll_component.clk1_multiply_by = 51, - altpll_component.clk1_phase_shift = "0", - altpll_component.compensate_clock = "CLK0", - altpll_component.inclk0_input_frequency = 37037, - altpll_component.intended_device_family = "Cyclone III", - altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", - altpll_component.lpm_type = "altpll", - altpll_component.operation_mode = "NORMAL", - altpll_component.pll_type = "AUTO", - altpll_component.port_activeclock = "PORT_UNUSED", - altpll_component.port_areset = "PORT_UNUSED", - altpll_component.port_clkbad0 = "PORT_UNUSED", - altpll_component.port_clkbad1 = "PORT_UNUSED", - altpll_component.port_clkloss = "PORT_UNUSED", - altpll_component.port_clkswitch = "PORT_UNUSED", - altpll_component.port_configupdate = "PORT_UNUSED", - altpll_component.port_fbin = "PORT_UNUSED", - altpll_component.port_inclk0 = "PORT_USED", - altpll_component.port_inclk1 = "PORT_UNUSED", - altpll_component.port_locked = "PORT_USED", - altpll_component.port_pfdena = "PORT_UNUSED", - altpll_component.port_phasecounterselect = "PORT_UNUSED", - altpll_component.port_phasedone = "PORT_UNUSED", - altpll_component.port_phasestep = "PORT_UNUSED", - altpll_component.port_phaseupdown = "PORT_UNUSED", - altpll_component.port_pllena = "PORT_UNUSED", - altpll_component.port_scanaclr = "PORT_UNUSED", - altpll_component.port_scanclk = "PORT_UNUSED", - altpll_component.port_scanclkena = "PORT_UNUSED", - altpll_component.port_scandata = "PORT_UNUSED", - altpll_component.port_scandataout = "PORT_UNUSED", - altpll_component.port_scandone = "PORT_UNUSED", - altpll_component.port_scanread = "PORT_UNUSED", - altpll_component.port_scanwrite = "PORT_UNUSED", - altpll_component.port_clk0 = "PORT_USED", - altpll_component.port_clk1 = "PORT_USED", - altpll_component.port_clk2 = "PORT_UNUSED", - altpll_component.port_clk3 = "PORT_UNUSED", - altpll_component.port_clk4 = "PORT_UNUSED", - altpll_component.port_clk5 = "PORT_UNUSED", - altpll_component.port_clkena0 = "PORT_UNUSED", - altpll_component.port_clkena1 = "PORT_UNUSED", - altpll_component.port_clkena2 = "PORT_UNUSED", - altpll_component.port_clkena3 = "PORT_UNUSED", - altpll_component.port_clkena4 = "PORT_UNUSED", - altpll_component.port_clkena5 = "PORT_UNUSED", - altpll_component.port_extclk0 = "PORT_UNUSED", - altpll_component.port_extclk1 = "PORT_UNUSED", - altpll_component.port_extclk2 = "PORT_UNUSED", - altpll_component.port_extclk3 = "PORT_UNUSED", - altpll_component.self_reset_on_loss_lock = "OFF", - altpll_component.width_clock = 5; - - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" -// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" -// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" -// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" -// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" -// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" -// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" -// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" -// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" -// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" -// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" -// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" -// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" -// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" -// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" -// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" -// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "50" -// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "16" -// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "49.139999" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "86.062500" -// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" -// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" -// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" -// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" -// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" -// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" -// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" -// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" -// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" -// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" -// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" -// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" -// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" -// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" -// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" -// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" -// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" -// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" -// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "91" -// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "51" -// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" -// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "49.14772700" -// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "86.00852300" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" -// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" -// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" -// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" -// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" -// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" -// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" -// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" -// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" -// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" -// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" -// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" -// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" -// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" -// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" -// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" -// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" -// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" -// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" -// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" -// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" -// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" -// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" -// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" -// Retrieval info: PRIVATE: SPREAD_USE STRING "0" -// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" -// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" -// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" -// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" -// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" -// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -// Retrieval info: PRIVATE: USE_CLK0 STRING "1" -// Retrieval info: PRIVATE: USE_CLK1 STRING "1" -// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" -// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" -// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" -// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" -// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "50" -// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "91" -// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "16" -// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "51" -// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" -// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" -// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" -// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" -// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" -// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" -// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" -// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" -// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" -// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" -// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" -// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 -// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 -// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 -// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 -// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE -// Retrieval info: LIB_FILE: altera_mf -// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Namco Gaplus/rtl/rams.v b/Arcade_MiST/Namco Gaplus/rtl/rams.v deleted file mode 100644 index 125c0656..00000000 --- a/Arcade_MiST/Namco Gaplus/rtl/rams.v +++ /dev/null @@ -1,87 +0,0 @@ -/******************************************** - RAM Modules for "FPGA Gaplus" - - Copyright (c) 2007,2019 MiSTer-X -*********************************************/ -module DPRAM_1024V( CL0, ADRS0, IN0, OUT0, WR0, CL1, ADRS1, OUT1 ); -input CL0; -input [9:0] ADRS0; -input [7:0] IN0; -output [7:0] OUT0; -input WR0; -input CL1; -input [9:0] ADRS1; -output [7:0] OUT1; - -reg [7:0] ramcore[0:1023]; -reg [7:0] OUT0; -reg [7:0] OUT1; - -always @( posedge CL0 ) begin - if ( WR0 ) ramcore[ADRS0] <= IN0; - else OUT0 <= ramcore[ADRS0]; -end - -always @( posedge CL1 ) begin - OUT1 <= ramcore[ADRS1]; -end - -endmodule - - -module DPRAM_2048( CL0, ADRS0, IN0, OUT0, WR0, CL1, ADRS1, IN1, OUT1, WR1 ); - -input CL0; -input [10:0] ADRS0; -input [7:0] IN0; -output [7:0] OUT0; -input WR0; - -input CL1; -input [10:0] ADRS1; -input [7:0] IN1; -output [7:0] OUT1; -input WR1; - -reg [7:0] ramcore[0:2047]; -reg [7:0] OUT0; -reg [7:0] OUT1; - -always @( posedge CL0 ) begin - if ( WR0 ) ramcore[ADRS0] <= IN0; - else OUT0 <= ramcore[ADRS0]; -end - -always @( posedge CL1 ) begin - if ( WR1 ) ramcore[ADRS1] <= IN1; - else OUT1 <= ramcore[ADRS1]; -end - -endmodule - - -module DPRAM_2048V( CL0, ADRS0, IN0, OUT0, WR0, CL1, ADRS1, OUT1 ); -input CL0; -input [10:0] ADRS0; -input [7:0] IN0; -output [7:0] OUT0; -input WR0; -input CL1; -input [10:0] ADRS1; -output [7:0] OUT1; - -reg [7:0] ramcore[0:2047]; -reg [7:0] OUT0; -reg [7:0] OUT1; - -always @( posedge CL0 ) begin - if ( WR0 ) ramcore[ADRS0] <= IN0; - else OUT0 <= ramcore[ADRS0]; -end - -always @( posedge CL1 ) begin - OUT1 <= ramcore[ADRS1]; -end - -endmodule - diff --git a/Arcade_MiST/Namco Gaplus/rtl/rom/bg.vhd b/Arcade_MiST/Namco Gaplus/rtl/rom/bg.vhd deleted file mode 100644 index 08742da3..00000000 --- a/Arcade_MiST/Namco Gaplus/rtl/rom/bg.vhd +++ /dev/null @@ -1,534 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity bg is -port ( - clk : in std_logic; - addr : in std_logic_vector(12 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of bg is - type rom is array(0 to 8191) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"B0",X"60",X"C0",X"80",X"C0",X"90",X"30",X"70",X"C0",X"80",X"40",X"C0",X"90",X"34",X"74",X"FC", - X"90",X"30",X"70",X"F0",X"B0",X"B0",X"60",X"30",X"F0",X"F0",X"B0",X"60",X"C0",X"C0",X"90",X"30", - X"F0",X"70",X"74",X"94",X"94",X"C4",X"44",X"40",X"BC",X"F9",X"F9",X"F9",X"F9",X"79",X"79",X"9C", - X"80",X"80",X"80",X"C0",X"60",X"60",X"B0",X"B0",X"90",X"C0",X"40",X"40",X"00",X"80",X"80",X"C0", - X"00",X"80",X"80",X"00",X"00",X"00",X"00",X"00",X"9C",X"C4",X"44",X"44",X"00",X"04",X"04",X"04", - X"30",X"C0",X"40",X"00",X"00",X"00",X"00",X"00",X"60",X"60",X"C0",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"04",X"04",X"04",X"0C",X"C9",X"0C",X"09",X"09",X"09",X"07",X"07",X"07",X"0F", - X"00",X"00",X"00",X"00",X"00",X"C0",X"60",X"B0",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"60", - X"69",X"B9",X"F7",X"F7",X"F7",X"F7",X"F7",X"FF",X"CF",X"6B",X"BB",X"FB",X"FB",X"FB",X"F6",X"F6", - X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"70",X"B0",X"F4",X"F4",X"F4",X"F4",X"F4",X"FC",X"F9", - X"FF",X"7F",X"9F",X"CB",X"0B",X"0B",X"0B",X"0B",X"F6",X"F6",X"36",X"CC",X"C8",X"08",X"08",X"08", - X"90",X"C0",X"00",X"04",X"04",X"04",X"04",X"04",X"79",X"99",X"C9",X"09",X"09",X"07",X"07",X"07", - X"0B",X"06",X"06",X"06",X"06",X"06",X"06",X"06",X"08",X"08",X"08",X"00",X"04",X"04",X"04",X"04", - X"04",X"04",X"04",X"0C",X"0C",X"8C",X"CC",X"CC",X"07",X"07",X"07",X"07",X"07",X"07",X"07",X"87", - X"06",X"06",X"06",X"46",X"46",X"C6",X"96",X"36",X"04",X"44",X"C4",X"94",X"94",X"34",X"74",X"F4", - X"69",X"B9",X"B9",X"B9",X"B9",X"69",X"C9",X"89",X"8F",X"CF",X"CF",X"CF",X"CF",X"8F",X"4F",X"CF", - X"76",X"F6",X"F6",X"F6",X"F6",X"B6",X"36",X"66",X"F4",X"F4",X"F4",X"B4",X"34",X"64",X"C4",X"C4", - X"49",X"C9",X"99",X"39",X"79",X"F9",X"F9",X"FC",X"9F",X"3F",X"7F",X"FF",X"FF",X"FF",X"FF",X"B7", - X"C6",X"C6",X"36",X"F6",X"FB",X"FB",X"FB",X"FB",X"C4",X"C0",X"38",X"F8",X"F8",X"F8",X"F8",X"F8", - X"6C",X"3C",X"FC",X"F4",X"F4",X"F4",X"F4",X"F4",X"C7",X"67",X"37",X"F7",X"F7",X"F7",X"F7",X"F7", - X"FB",X"FB",X"FB",X"FF",X"FF",X"FF",X"FF",X"F7",X"F8",X"F8",X"FC",X"F6",X"B6",X"36",X"36",X"36", - X"F4",X"74",X"74",X"90",X"90",X"40",X"40",X"00",X"F7",X"F9",X"F9",X"F9",X"F9",X"79",X"79",X"9C", - X"77",X"77",X"97",X"99",X"49",X"49",X"09",X"0C",X"B6",X"BB",X"FB",X"7B",X"3B",X"CF",X"0F",X"07", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"9C",X"44",X"44",X"04",X"04",X"00",X"00",X"00", - X"0C",X"04",X"C4",X"34",X"F4",X"F0",X"F0",X"F0",X"07",X"07",X"C7",X"C9",X"39",X"F9",X"FC",X"FC", - X"80",X"C0",X"30",X"F0",X"F0",X"F0",X"F0",X"F0",X"00",X"C0",X"60",X"B0",X"F0",X"F0",X"F0",X"F0", - X"F0",X"F0",X"F0",X"F0",X"30",X"C0",X"40",X"00",X"F4",X"F4",X"F4",X"F4",X"74",X"94",X"CC",X"0C", - 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gp2-7.6s pal_c.vhd - -make_vhdl_prom gp2-6.6p pal_sl.vhd -make_vhdl_prom gp2-5.6n pal_sh.vhd - -make_vhdl_prom gp2-1.4b sound.vhd -make_vhdl_prom gp2-4.3f wave.vhd - -make_vhdl_prom gp2-11.11p obj1.vhd -make_vhdl_prom gp2-10.11n obj2.vhd -make_vhdl_prom gp2-12.11r obj3.vhd -make_vhdl_prom gp2-9.11m obj4.vhd - -make_vhdl_prom gp2-5.8s bg.vhd -copy /b gp2-4.8d + gp2-4.8d + gp2-3b.8c + gp2-2b.8b + gp2-8.11d + gp2-8.11d + gp2-7.11c + gp2-6.11b GAPLUS.ROM \ No newline at end of file diff --git a/Arcade_MiST/Namco Gaplus/rtl/rom/make_vhdl_prom.exe b/Arcade_MiST/Namco Gaplus/rtl/rom/make_vhdl_prom.exe deleted file mode 100644 index 1e5618bf9417eaeb90556e3021a78e9860a815e8..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 119861 zcmeFa34D~*^*4T>XXcqD3p0TP!#R;I3im94{WDd))P*nEKjw;3-)UlQLkgOB&vHgLsaCW=mlXa{` zB=P6lm;e@v{KDCr72jJL2<`Y#zVq?1{Yk!c9UVkEOl{aj(9wTgqPA~#laeRfnks`n z77K^+LSEnO;;I^=ZlJFn_)xxu_}KmmMPc9UShLJGMD(5b5Z`h_l7EHBcMg}ipW^%Q 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H%=`ZUgl -// Copyright (c) 2019 Gyorgy Szombathelyi -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -module sdram ( - - // interface to the MT48LC16M16 chip - inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus - output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus - output reg SDRAM_DQML, // two byte masks - output reg SDRAM_DQMH, // two byte masks - output reg [1:0] SDRAM_BA, // two banks - output SDRAM_nCS, // a single chip select - output SDRAM_nWE, // write enable - output SDRAM_nRAS, // row address select - output SDRAM_nCAS, // columns address select - - // cpu/chipset interface - input init_n, // init signal after FPGA config to initialize RAM - input clk, // sdram clock - - input port1_req, - output reg port1_ack, - input port1_we, - input [23:1] port1_a, - input [1:0] port1_ds, - input [15:0] port1_d, - output reg [15:0] port1_q, - - input [16:1] cpu1_addr, - output reg [15:0] cpu1_q, - input [16:1] cpu2_addr, - output reg [15:0] cpu2_q, - - input port2_req, - output reg port2_ack, - input port2_we, - input [23:1] port2_a, - input [1:0] port2_ds, - input [15:0] port2_d, - output reg [31:0] port2_q, - - input [16:2] bg_addr, - output reg [31:0] bg_q, - input [16:2] fg_addr, - output reg [31:0] fg_q, - input [16:2] sp_addr, - output reg [31:0] sp_q, - output reg sp_rdy -); - -localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz -localparam BURST_LENGTH = 3'b001; // 000=1, 001=2, 010=4, 011=8 -localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved -localparam CAS_LATENCY = 3'd2; // 2/3 allowed -localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed -localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write - -localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH}; - -// 64ms/8192 rows = 7.8us -> 842 cycles@108MHz -localparam RFRSH_CYCLES = 10'd842; - -// --------------------------------------------------------------------- -// ------------------------ cycle state machine ------------------------ -// --------------------------------------------------------------------- - -/* - SDRAM state machine for 2 bank interleaved access - 2 words burst, CL2 -cmd issued registered - 0 RAS0 cas1 - data0 read burst terminated - 1 ras0 - 2 data1 returned - 3 CAS0 data1 returned - 4 RAS1 cas0 - 5 ras1 - 6 CAS1 data0 returned -*/ - -localparam STATE_RAS0 = 3'd0; // first state in cycle -localparam STATE_RAS1 = 3'd4; // Second ACTIVE command after RAS0 + tRRD (15ns) -localparam STATE_CAS0 = STATE_RAS0 + RASCAS_DELAY + 1'd1; // CAS phase - 3 -localparam STATE_CAS1 = STATE_RAS1 + RASCAS_DELAY; // CAS phase - 6 -localparam STATE_READ0 = 3'd0;// STATE_CAS0 + CAS_LATENCY + 2'd2; // 7 -localparam STATE_READ1 = 3'd3; -localparam STATE_DS1b = 3'd0; -localparam STATE_READ1b = 3'd4; -localparam STATE_LAST = 3'd6; - -reg [2:0] t; - -always @(posedge clk) begin - t <= t + 1'd1; - if (t == STATE_LAST) t <= STATE_RAS0; -end - -// --------------------------------------------------------------------- -// --------------------------- startup/reset --------------------------- -// --------------------------------------------------------------------- - -// wait 1ms (32 8Mhz cycles) after FPGA config is done before going -// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0) -reg [4:0] reset; -reg init = 1'b1; -always @(posedge clk, negedge init_n) begin - if(!init_n) begin - reset <= 5'h1f; - init <= 1'b1; - end else begin - if((t == STATE_LAST) && (reset != 0)) reset <= reset - 5'd1; - init <= !(reset == 0); - end -end - -// --------------------------------------------------------------------- -// ------------------ generate ram control signals --------------------- -// --------------------------------------------------------------------- - -// all possible commands -localparam CMD_INHIBIT = 4'b1111; -localparam CMD_NOP = 4'b0111; -localparam CMD_ACTIVE = 4'b0011; -localparam CMD_READ = 4'b0101; -localparam CMD_WRITE = 4'b0100; -localparam CMD_BURST_TERMINATE = 4'b0110; -localparam CMD_PRECHARGE = 4'b0010; -localparam CMD_AUTO_REFRESH = 4'b0001; -localparam CMD_LOAD_MODE = 4'b0000; - -reg [3:0] sd_cmd; // current command sent to sd ram -reg [15:0] sd_din; -// drive control signals according to current command -assign SDRAM_nCS = sd_cmd[3]; -assign SDRAM_nRAS = sd_cmd[2]; -assign SDRAM_nCAS = sd_cmd[1]; -assign SDRAM_nWE = sd_cmd[0]; - -reg [24:1] addr_latch[2]; -reg [24:1] addr_latch_next[2]; -reg [16:1] addr_last[2]; -reg [16:2] addr_last2[4]; -reg [15:0] din_latch[2]; -reg [1:0] oe_latch; -reg [1:0] we_latch; -reg [1:0] ds[2]; - -reg port1_state; -reg port2_state; - -localparam PORT_NONE = 3'd0; -localparam PORT_CPU1 = 3'd1; -localparam PORT_CPU2 = 3'd2; -localparam PORT_SP = 3'd1; -localparam PORT_FG = 3'd2; -localparam PORT_BG = 3'd3; -localparam PORT_REQ = 3'd4; - -reg [2:0] next_port[2]; -reg [2:0] port[2]; - -reg refresh; -reg [10:0] refresh_cnt; -wire need_refresh = (refresh_cnt >= RFRSH_CYCLES); - -// PORT1: bank 0,1 -always @(*) begin - if (refresh) begin - next_port[0] = PORT_NONE; - addr_latch_next[0] = addr_latch[0]; - end else if (port1_req ^ port1_state) begin - next_port[0] = PORT_REQ; - addr_latch_next[0] = { 1'b0, port1_a }; - end else if (cpu1_addr != addr_last[PORT_CPU1]) begin - next_port[0] = PORT_CPU1; - addr_latch_next[0] = { 8'd0, cpu1_addr }; - end else if (cpu2_addr != addr_last[PORT_CPU2]) begin - next_port[0] = PORT_CPU2; - addr_latch_next[0] = { 8'd0, cpu2_addr }; - end else begin - next_port[0] = PORT_NONE; - addr_latch_next[0] = addr_latch[0]; - end -end - -// PORT1: bank 2,3 -always @(*) begin - if (port2_req ^ port2_state) begin - next_port[1] = PORT_REQ; - addr_latch_next[1] = { 1'b1, port2_a }; - end else if (sp_addr != addr_last2[PORT_SP]) begin - next_port[1] = PORT_SP; - addr_latch_next[1] = { 1'b1, 7'd0, sp_addr, 1'b0 }; - end else if (fg_addr != addr_last2[PORT_FG]) begin - next_port[1] = PORT_FG; - addr_latch_next[1] = { 1'b1, 7'd0, fg_addr, 1'b0 }; - end else if (bg_addr != addr_last2[PORT_BG]) begin - next_port[1] = PORT_BG; - addr_latch_next[1] = { 1'b1, 7'd0, bg_addr, 1'b0 }; - end else begin - next_port[1] = PORT_NONE; - addr_latch_next[1] = addr_latch[1]; - end -end - -always @(posedge clk) begin - - // permanently latch ram data to reduce delays - sd_din <= SDRAM_DQ; - SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ; - { SDRAM_DQMH, SDRAM_DQML } <= 2'b11; - sd_cmd <= CMD_NOP; // default: idle - refresh_cnt <= refresh_cnt + 1'd1; - - sp_rdy <= 0; - - if(init) begin - // initialization takes place at the end of the reset phase - if(t == STATE_RAS0) begin - - if(reset == 15) begin - sd_cmd <= CMD_PRECHARGE; - SDRAM_A[10] <= 1'b1; // precharge all banks - end - - if(reset == 10 || reset == 8) begin - sd_cmd <= CMD_AUTO_REFRESH; - end - - if(reset == 2) begin - sd_cmd <= CMD_LOAD_MODE; - SDRAM_A <= MODE; - SDRAM_BA <= 2'b00; - end - end - end else begin - // RAS phase - // bank 0,1 - if(t == STATE_RAS0) begin - addr_latch[0] <= addr_latch_next[0]; - port[0] <= next_port[0]; - { oe_latch[0], we_latch[0] } <= 2'b00; - - if (next_port[0] != PORT_NONE) begin - sd_cmd <= CMD_ACTIVE; - SDRAM_A <= addr_latch_next[0][22:10]; - SDRAM_BA <= addr_latch_next[0][24:23]; - addr_last[next_port[0]] <= addr_latch_next[0][16:1]; - if (next_port[0] == PORT_REQ) begin - { oe_latch[0], we_latch[0] } <= { ~port1_we, port1_we }; - ds[0] <= port1_ds; - din_latch[0] <= port1_d; - port1_state <= port1_req; - end else begin - { oe_latch[0], we_latch[0] } <= 2'b10; - ds[0] <= 2'b11; - end - end - end - - // bank 2,3 - if(t == STATE_RAS1) begin - refresh <= 1'b0; - addr_latch[1] <= addr_latch_next[1]; - { oe_latch[1], we_latch[1] } <= 2'b00; - port[1] <= next_port[1]; - - if (next_port[1] != PORT_NONE) begin - sd_cmd <= CMD_ACTIVE; - SDRAM_A <= addr_latch_next[1][22:10]; - SDRAM_BA <= addr_latch_next[1][24:23]; - addr_last2[next_port[1]] <= addr_latch_next[1][16:2]; - if (next_port[1] == PORT_REQ) begin - { oe_latch[1], we_latch[1] } <= { ~port1_we, port1_we }; - ds[1] <= port2_ds; - din_latch[1] <= port2_d; - port2_state <= port2_req; - end else begin - { oe_latch[1], we_latch[1] } <= 2'b10; - ds[1] <= 2'b11; - end - end - - if (next_port[1] == PORT_NONE && need_refresh && !we_latch[0] && !oe_latch[0]) begin - refresh <= 1'b1; - refresh_cnt <= 0; - sd_cmd <= CMD_AUTO_REFRESH; - end - end - - // CAS phase - if(t == STATE_CAS0 && (we_latch[0] || oe_latch[0])) begin - sd_cmd <= we_latch[0]?CMD_WRITE:CMD_READ; - { SDRAM_DQMH, SDRAM_DQML } <= ~ds[0]; - if (we_latch[0]) begin - SDRAM_DQ <= din_latch[0]; - port1_ack <= port1_req; - end - SDRAM_A <= { 4'b0010, addr_latch[0][9:1] }; // auto precharge - SDRAM_BA <= addr_latch[0][24:23]; - end - - if(t == STATE_CAS1 && (we_latch[1] || oe_latch[1])) begin - sd_cmd <= we_latch[1]?CMD_WRITE:CMD_READ; - { SDRAM_DQMH, SDRAM_DQML } <= ~ds[1]; - if (we_latch[1]) begin - SDRAM_DQ <= din_latch[1]; - port2_ack <= port2_req; - end - SDRAM_A <= { 4'b0010, addr_latch[1][9:1] }; // auto precharge - SDRAM_BA <= addr_latch[1][24:23]; - end - - // Data returned - if(t == STATE_READ0 && oe_latch[0]) begin - case(port[0]) - PORT_REQ: begin port1_q <= sd_din; port1_ack <= port1_req; end - PORT_CPU1: begin cpu1_q <= sd_din; end - PORT_CPU2: begin cpu2_q <= sd_din; end - default: ; - endcase; - end - - if(t == STATE_READ1 && oe_latch[1]) begin - case(port[1]) - PORT_REQ: port2_q[15:0] <= sd_din; - PORT_FG : fg_q[15:0] <= sd_din; - PORT_BG : bg_q[15:0] <= sd_din; - PORT_SP : sp_q[15:0] <= sd_din; - default: ; - endcase; - end - - if(t == STATE_DS1b && oe_latch[1]) { SDRAM_DQMH, SDRAM_DQML } <= ~ds[1]; - - if(t == STATE_READ1b && oe_latch[1]) begin - case(port[1]) - PORT_REQ: begin port2_q[31:16] <= sd_din; port2_ack <= port2_req; end - PORT_FG : begin fg_q[31:16] <= sd_din; end - PORT_BG : begin bg_q[31:16] <= sd_din; end - PORT_SP : begin sp_q[31:16] <= sd_din; sp_rdy <= 1; end - default: ; - endcase; - end - - end -end - -endmodule diff --git a/Arcade_MiST/Namco Gaplus/rtl/wsg_aux.v b/Arcade_MiST/Namco Gaplus/rtl/wsg_aux.v deleted file mode 100644 index 059cdda9..00000000 --- a/Arcade_MiST/Namco Gaplus/rtl/wsg_aux.v +++ /dev/null @@ -1,121 +0,0 @@ -/************************************************* - Wave-base Sound Generator (8CH) with AUX-in - - Copyright (c) 2007,2019 MiSTer-X -**************************************************/ -module WSG_8CH_AUX -( - CLK24M, - RST, - - ADDR, - DATA, - WE, - - WAVE_CL, - WAVE_AD, - WAVE_DT, - - AUX_CL, - AUX_DT, - - WSG_ENABLE, - - SND -); - -input CLK24M; -input RST; - -input [5:0] ADDR; -input [7:0] DATA; -input WE; - -output WAVE_CL; -output [7:0] WAVE_AD; -input [7:0] WAVE_DT; - -output AUX_CL; -input [7:0] AUX_DT; - -input WSG_ENABLE; - -output [7:0] SND; - - -//------------------------------------------- -// Clock Generator & Ctrl Registers -//------------------------------------------- -reg [9:0] clk24k_cnt = 0; - -wire CLK_WSGx8 = clk24k_cnt[6]; // 24KHz*8 -wire CLK_WSG = clk24k_cnt[9]; // 24KHz - -reg [7:0] fl [0:7]; -reg [7:0] fm [0:7]; -reg [3:0] fh [0:7]; -reg [2:0] fv [0:7]; -reg [3:0] v [0:7]; - -wire [2:0] ra = ADDR[5:3]; -wire [2:0] rc = clk24k_cnt[2:0]; - -always @( posedge CLK24M ) begin - if ( RST ) begin - v[rc] <= 0; - end - else if ( WE ) begin - case ( ADDR[2:0] ) - 3'h3: v[ra] <= DATA[3:0]; - 3'h4: fl[ra] <= DATA; - 3'h5: fm[ra] <= DATA; - 3'h6: begin - fh[ra] <= DATA[3:0]; - fv[ra] <= DATA[6:4]; - end - default: begin end - endcase - end - clk24k_cnt <= clk24k_cnt + 1; -end - -//------------------------------------------- -// WSG core (8ch) -//------------------------------------------- -reg [2:0] phase = 0; - -reg [7:0] o, ot; -reg [19:0] c [0:7]; -reg [7:0] wa; -reg [3:0] wm; -reg en; - -wire [19:0] fq = { fh[phase], fm[phase], fl[phase] }; -wire [7:0] va = WAVE_DT[3:0] * wm; - -wire [19:0] cx = c[phase]; - -assign WAVE_CL = CLK_WSGx8; -assign WAVE_AD = wa; - -always @ ( negedge CLK_WSGx8 ) begin - if ( phase ) begin - ot <= ot + (en ? { 4'h0, va[7:4] } : 8'h0); - end else begin - o <= ot; - ot <= en ? { 4'h0, va[7:4] } : 8'h0; - end - c[phase] <= cx + fq; - en <= (fq!=0); - wm <= v[phase]; - wa <= { fv[phase], cx[19:15] }; - phase <= phase + 1; -end - -wire [7:0] _o = o[6:0] + AUX_DT; -wire [7:0] wsgmix = ( _o[6:0] | {7{_o[7]}} ); - -assign AUX_CL = CLK_WSG; -assign SND = wsgmix; - -endmodule