From 7f8bb6d08a9c864ef07f3da9b817ea96a79e5a79 Mon Sep 17 00:00:00 2001 From: Marcel Date: Mon, 23 Sep 2019 14:03:18 +0200 Subject: [PATCH] add DigDug Project Files --- .../DigDug_MiST/DigDug_MiST.qpf | 31 + .../DigDug_MiST/DigDug_MiST.qsf | 232 ++ .../DigDug_MiST/DigDug_MiST.srf | 12 + .../Galaga Hardware/DigDug_MiST/clean.bat | 37 + .../Galaga Hardware/DigDug_MiST/readme.txt | 58 + .../DigDug_MiST/rtl/DIGDUG_CORES.v | 205 ++ .../DigDug_MiST/rtl/DIGDUG_CUSIO.v | 266 ++ .../DigDug_MiST/rtl/DIGDUG_IODEV.v | 197 ++ .../DigDug_MiST/rtl/DIGDUG_SPRITE.v | 113 + .../DigDug_MiST/rtl/DIGDUG_VIDEO.v | 148 + .../Galaga Hardware/DigDug_MiST/rtl/DigDug.sv | 211 ++ .../DigDug_MiST/rtl/FPGA_DIGDUG.v | 138 + .../DigDug_MiST/rtl/LINEBUF.qip | 4 + .../Galaga Hardware/DigDug_MiST/rtl/LINEBUF.v | 246 ++ .../DigDug_MiST/rtl/TV80/tv80_alu.v | 442 +++ .../DigDug_MiST/rtl/TV80/tv80_core.v | 1356 +++++++++ .../DigDug_MiST/rtl/TV80/tv80_mcode.v | 2653 +++++++++++++++++ .../DigDug_MiST/rtl/TV80/tv80_reg.v | 71 + .../DigDug_MiST/rtl/TV80/tv80s.v | 164 + .../DigDug_MiST/rtl/build_id.tcl | 35 + .../Galaga Hardware/DigDug_MiST/rtl/cpucore.v | 84 + .../Galaga Hardware/DigDug_MiST/rtl/dprams.v | 130 + .../Galaga Hardware/DigDug_MiST/rtl/hvgen.v | 40 + .../Galaga Hardware/DigDug_MiST/rtl/pll.qip | 4 + .../Galaga Hardware/DigDug_MiST/rtl/pll.v | 337 +++ .../DigDug_MiST/rtl/roms/136007.109 | Bin 0 -> 256 bytes .../DigDug_MiST/rtl/roms/136007.110 | Bin 0 -> 256 bytes .../DigDug_MiST/rtl/roms/136007.111 | Bin 0 -> 256 bytes .../DigDug_MiST/rtl/roms/136007.112 | Bin 0 -> 256 bytes .../DigDug_MiST/rtl/roms/136007.113 | Bin 0 -> 32 bytes .../DigDug_MiST/rtl/roms/51xx.bin | Bin 0 -> 1024 bytes .../DigDug_MiST/rtl/roms/53xx.bin | Bin 0 -> 1024 bytes .../DigDug_MiST/rtl/roms/DIGDUG.ROM | Bin 0 -> 16384 bytes .../DigDug_MiST/rtl/roms/bgchip_rom.vhd | 278 ++ .../DigDug_MiST/rtl/roms/bgclut_rom.vhd | 38 + .../DigDug_MiST/rtl/roms/bgscrn_rom.vhd | 278 ++ .../DigDug_MiST/rtl/roms/build_fpga_image.bat | 24 + .../rtl/roms/build_fpga_image2.bat | 24 + .../Galaga Hardware/DigDug_MiST/rtl/roms/cpu0 | Bin 0 -> 16384 bytes .../DigDug_MiST/rtl/roms/cpu0_rom.vhd | 1046 +++++++ .../Galaga Hardware/DigDug_MiST/rtl/roms/cpu1 | Bin 0 -> 8192 bytes .../DigDug_MiST/rtl/roms/cpu1_rom.vhd | 534 ++++ .../DigDug_MiST/rtl/roms/cpu2_rom.vhd | 278 ++ .../DigDug_MiST/rtl/roms/dd1.1 | Bin 0 -> 4096 bytes .../DigDug_MiST/rtl/roms/dd1.10b | 1 + .../DigDug_MiST/rtl/roms/dd1.11 | Bin 0 -> 4096 bytes .../DigDug_MiST/rtl/roms/dd1.12 | Bin 0 -> 4096 bytes .../DigDug_MiST/rtl/roms/dd1.13 | Bin 0 -> 4096 bytes .../DigDug_MiST/rtl/roms/dd1.14 | Bin 0 -> 4096 bytes .../DigDug_MiST/rtl/roms/dd1.15 | Bin 0 -> 4096 bytes .../DigDug_MiST/rtl/roms/dd1.2 | Bin 0 -> 4096 bytes .../DigDug_MiST/rtl/roms/dd1.3 | Bin 0 -> 4096 bytes .../DigDug_MiST/rtl/roms/dd1.4b | Bin 0 -> 4096 bytes .../DigDug_MiST/rtl/roms/dd1.5b | Bin 0 -> 4096 bytes .../DigDug_MiST/rtl/roms/dd1.6b | Bin 0 -> 4096 bytes .../DigDug_MiST/rtl/roms/dd1.7 | Bin 0 -> 4096 bytes .../DigDug_MiST/rtl/roms/dd1.9 | Bin 0 -> 2048 bytes .../DigDug_MiST/rtl/roms/dd1a.1 | Bin 0 -> 4096 bytes .../DigDug_MiST/rtl/roms/dd1a.2 | Bin 0 -> 4096 bytes .../DigDug_MiST/rtl/roms/dd1a.3 | Bin 0 -> 4096 bytes .../DigDug_MiST/rtl/roms/dd1a.4 | Bin 0 -> 4096 bytes .../DigDug_MiST/rtl/roms/dd1a.5 | Bin 0 -> 4096 bytes .../DigDug_MiST/rtl/roms/dd1a.6 | Bin 0 -> 4096 bytes .../DigDug_MiST/rtl/roms/digdug (1).zip | Bin 0 -> 29303 bytes .../DigDug_MiST/rtl/roms/fgchip_rom.vhd | 150 + .../DigDug_MiST/rtl/roms/make_vhdl_prom.exe | Bin 0 -> 119861 bytes .../DigDug_MiST/rtl/roms/palette_rom.vhd | 24 + .../DigDug_MiST/rtl/roms/spchip | Bin 0 -> 16384 bytes .../DigDug_MiST/rtl/roms/spchip_rom.vhd | 1046 +++++++ .../DigDug_MiST/rtl/roms/spclut_rom.vhd | 38 + .../DigDug_MiST/rtl/roms/wave_rom.vhd | 38 + .../Galaga Hardware/DigDug_MiST/rtl/wsg.v | 249 ++ .../Power_Surge_MiST/rtl/power_surge.vhd | 6 +- Arcade_MiST/README.txt | 4 + 74 files changed, 11267 insertions(+), 3 deletions(-) create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/DigDug_MiST.qpf create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/DigDug_MiST.qsf create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/DigDug_MiST.srf create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/clean.bat create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/readme.txt create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/DIGDUG_CORES.v create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/DIGDUG_CUSIO.v create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/DIGDUG_IODEV.v create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/DIGDUG_SPRITE.v create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/DIGDUG_VIDEO.v create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/DigDug.sv create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/FPGA_DIGDUG.v create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/LINEBUF.qip create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/LINEBUF.v create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/TV80/tv80_alu.v create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/TV80/tv80_core.v create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/TV80/tv80_mcode.v create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/TV80/tv80_reg.v create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/TV80/tv80s.v create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/build_id.tcl create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/cpucore.v create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/dprams.v create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/hvgen.v create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/pll.qip create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/pll.v create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/136007.109 create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/136007.110 create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/136007.111 create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/136007.112 create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/136007.113 create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/51xx.bin create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/53xx.bin create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/DIGDUG.ROM create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/bgchip_rom.vhd create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/bgclut_rom.vhd create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/bgscrn_rom.vhd create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/build_fpga_image.bat create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/build_fpga_image2.bat create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/cpu0 create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/cpu0_rom.vhd create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/cpu1 create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/cpu1_rom.vhd create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/cpu2_rom.vhd create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/dd1.1 create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/dd1.10b create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/dd1.11 create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/dd1.12 create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/dd1.13 create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/dd1.14 create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/dd1.15 create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/dd1.2 create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/dd1.3 create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/dd1.4b create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/dd1.5b create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/dd1.6b create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/dd1.7 create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/dd1.9 create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/dd1a.1 create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/dd1a.2 create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/dd1a.3 create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/dd1a.4 create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/dd1a.5 create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/dd1a.6 create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/digdug (1).zip create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/fgchip_rom.vhd create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/make_vhdl_prom.exe create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/palette_rom.vhd create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/spchip create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/spchip_rom.vhd create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/spclut_rom.vhd create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/wave_rom.vhd create mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/wsg.v diff --git a/Arcade_MiST/Galaga Hardware/DigDug_MiST/DigDug_MiST.qpf b/Arcade_MiST/Galaga Hardware/DigDug_MiST/DigDug_MiST.qpf new file mode 100644 index 00000000..4b195324 --- /dev/null +++ b/Arcade_MiST/Galaga Hardware/DigDug_MiST/DigDug_MiST.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition +# Date created = 04:04:47 October 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.0" +DATE = "04:04:47 October 16, 2017" + +# Revisions + +PROJECT_REVISION = "DigDug_MiST" diff --git a/Arcade_MiST/Galaga Hardware/DigDug_MiST/DigDug_MiST.qsf b/Arcade_MiST/Galaga Hardware/DigDug_MiST/DigDug_MiST.qsf new file mode 100644 index 00000000..17ca3263 --- /dev/null +++ b/Arcade_MiST/Galaga Hardware/DigDug_MiST/DigDug_MiST.qsf @@ -0,0 +1,232 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2014 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition +# Date created = 13:43:38 September 23, 2019 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# DigDug_MiST_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name SYSTEMVERILOG_FILE rtl/DigDug.sv +set_global_assignment -name VERILOG_FILE rtl/FPGA_DIGDUG.v +set_global_assignment -name VERILOG_FILE rtl/DIGDUG_CORES.v +set_global_assignment -name VERILOG_FILE rtl/cpucore.v +set_global_assignment -name VERILOG_FILE rtl/DIGDUG_CUSIO.v +set_global_assignment -name VERILOG_FILE rtl/DIGDUG_IODEV.v +set_global_assignment -name VERILOG_FILE rtl/DIGDUG_SPRITE.v +set_global_assignment -name VERILOG_FILE rtl/DIGDUG_VIDEO.v +set_global_assignment -name VERILOG_FILE rtl/hvgen.v +set_global_assignment -name VERILOG_FILE rtl/dprams.v +set_global_assignment -name VERILOG_FILE rtl/wsg.v +set_global_assignment -name VERILOG_FILE rtl/LINEBUF.v +set_global_assignment -name VERILOG_FILE rtl/pll.v +set_global_assignment -name VERILOG_FILE rtl/TV80/tv80s.v +set_global_assignment -name VERILOG_FILE rtl/TV80/tv80_reg.v +set_global_assignment -name VERILOG_FILE rtl/TV80/tv80_mcode.v +set_global_assignment -name VERILOG_FILE rtl/TV80/tv80_core.v +set_global_assignment -name VERILOG_FILE rtl/TV80/tv80_alu.v +set_global_assignment -name VHDL_FILE rtl/roms/wave_rom.vhd +set_global_assignment -name VHDL_FILE rtl/roms/spclut_rom.vhd +set_global_assignment -name VHDL_FILE rtl/roms/spchip_rom.vhd +set_global_assignment -name VHDL_FILE rtl/roms/palette_rom.vhd +set_global_assignment -name VHDL_FILE rtl/roms/fgchip_rom.vhd +set_global_assignment -name VHDL_FILE rtl/roms/cpu2_rom.vhd +set_global_assignment -name VHDL_FILE rtl/roms/cpu1_rom.vhd +set_global_assignment -name VHDL_FILE rtl/roms/cpu0_rom.vhd +set_global_assignment -name VHDL_FILE rtl/roms/bgscrn_rom.vhd +set_global_assignment -name VHDL_FILE rtl/roms/bgclut_rom.vhd +set_global_assignment -name VHDL_FILE rtl/roms/bgchip_rom.vhd +set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip +set_global_assignment -name SYSTEMVERILOG_FILE ../../../common/mist/sdram.sv + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PIN_49 -to SDRAM_A[0] +set_location_assignment PIN_44 -to SDRAM_A[1] +set_location_assignment PIN_42 -to SDRAM_A[2] +set_location_assignment PIN_39 -to SDRAM_A[3] +set_location_assignment PIN_4 -to SDRAM_A[4] +set_location_assignment PIN_6 -to SDRAM_A[5] +set_location_assignment PIN_8 -to SDRAM_A[6] +set_location_assignment PIN_10 -to SDRAM_A[7] +set_location_assignment PIN_11 -to SDRAM_A[8] +set_location_assignment PIN_28 -to SDRAM_A[9] +set_location_assignment PIN_50 -to SDRAM_A[10] +set_location_assignment PIN_30 -to SDRAM_A[11] +set_location_assignment PIN_32 -to SDRAM_A[12] +set_location_assignment PIN_83 -to SDRAM_DQ[0] +set_location_assignment PIN_79 -to SDRAM_DQ[1] +set_location_assignment PIN_77 -to SDRAM_DQ[2] +set_location_assignment PIN_76 -to SDRAM_DQ[3] +set_location_assignment PIN_72 -to SDRAM_DQ[4] +set_location_assignment PIN_71 -to SDRAM_DQ[5] +set_location_assignment PIN_69 -to SDRAM_DQ[6] +set_location_assignment PIN_68 -to SDRAM_DQ[7] +set_location_assignment PIN_86 -to SDRAM_DQ[8] +set_location_assignment PIN_87 -to SDRAM_DQ[9] +set_location_assignment PIN_98 -to SDRAM_DQ[10] +set_location_assignment PIN_99 -to SDRAM_DQ[11] +set_location_assignment PIN_100 -to SDRAM_DQ[12] +set_location_assignment PIN_101 -to SDRAM_DQ[13] +set_location_assignment PIN_103 -to SDRAM_DQ[14] +set_location_assignment PIN_104 -to SDRAM_DQ[15] +set_location_assignment PIN_58 -to SDRAM_BA[0] +set_location_assignment PIN_51 -to SDRAM_BA[1] +set_location_assignment PIN_85 -to SDRAM_DQMH +set_location_assignment PIN_67 -to SDRAM_DQML +set_location_assignment PIN_60 -to SDRAM_nRAS +set_location_assignment PIN_64 -to SDRAM_nCAS +set_location_assignment PIN_66 -to SDRAM_nWE +set_location_assignment PIN_59 -to SDRAM_nCS +set_location_assignment PIN_33 -to SDRAM_CKE +set_location_assignment PIN_43 -to SDRAM_CLK +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP +set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001 +set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name TOP_LEVEL_ENTITY DigDug + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# EDA Netlist Writer Assignments +# ============================== +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# start EDA_TOOL_SETTINGS(eda_simulation) +# --------------------------------------- + + # EDA Netlist Writer Assignments + # ============================== + set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation + +# end EDA_TOOL_SETTINGS(eda_simulation) +# ------------------------------------- + +# -------------------- +# start ENTITY(DigDug) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(DigDug) +# ------------------ +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Galaga Hardware/DigDug_MiST/DigDug_MiST.srf b/Arcade_MiST/Galaga Hardware/DigDug_MiST/DigDug_MiST.srf new file mode 100644 index 00000000..474c9fa9 --- /dev/null +++ b/Arcade_MiST/Galaga Hardware/DigDug_MiST/DigDug_MiST.srf @@ -0,0 +1,12 @@ +{ "" "" "" "Verilog HDL Declaration warning at tv80s.v(55): \"do\" is SystemVerilog-2005 keyword" { } { } 0 10463 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Unrecognized synthesis attribute \"dc_script_begin\" at rtl/TV80/tv80_reg.v(67)" { } { } 0 10335 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Net \"R\" at tv80_core.v(97) has no driver or initial value, using a default initial value '0'" { } { } 0 10030 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL warning at tv80_core.v(97): object R used but never assigned" { } { } 0 10858 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 10335 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 10463 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 10230 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 276027 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 10268 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 10273 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 10270 "" 0 0 "Quartus II" 0 -1 0 ""} diff --git a/Arcade_MiST/Galaga Hardware/DigDug_MiST/clean.bat b/Arcade_MiST/Galaga Hardware/DigDug_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade_MiST/Galaga Hardware/DigDug_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade_MiST/Galaga Hardware/DigDug_MiST/readme.txt b/Arcade_MiST/Galaga Hardware/DigDug_MiST/readme.txt new file mode 100644 index 00000000..f734e49f --- /dev/null +++ b/Arcade_MiST/Galaga Hardware/DigDug_MiST/readme.txt @@ -0,0 +1,58 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: DigDug port to MiSTer by MiSTer-X +-- 21 September 2019 +-- +--------------------------------------------------------------------------------- +-- FPGA DigDug for XILINX Spartan-6 +------------------------------------------------ +-- Copyright (c) 2017 MiSTer-X +--------------------------------------------------------------------------------- +-- T80/T80s - Version : 0242 +----------------------------- +-- TV80 8-Bit Microprocessor Core +-- Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org) +-- +-- Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org) +--------------------------------------------------------------------------------- +-- +-- +-- Keyboard inputs : +-- +-- F2 : Coin + Start 2 players +-- F1 : Coin + Start 1 player +-- UP,DOWN,LEFT,RIGHT arrows : Movements +-- SPACE,CTRL : Pump +-- +-- +-- Joystick support. +-- +-- +--------------------------------------------------------------------------------- + + *** Attention *** + +ROM is not included. In order to use this arcade, you need to provide a correct ROM file. + +Find this zip file somewhere. You need to find the file exactly as required. +Do not rename other zip files even if they also represent the same game - they are not compatible! +The name of zip is taken from M.A.M.E. project, so you can get more info about +hashes and contained files there. + +To generate the ROM using Windows: +1) Copy the zip into "releases" directory +2) Execute bat file - it will show the name of zip file containing required files. +3) Put required zip into the same directory and execute the bat again. +4) If everything will go without errors or warnings, then you will get the a.*.rom file. +5) Copy generated a.*.rom into root of SD card along with the Arcade-*.rbf file + +To generate the ROM using Linux/MacOS: +1) Copy the zip into "releases" directory +2) Execute build_rom.sh +3) Copy generated a.*.rom into root of SD card along with the Arcade-*.rbf file + +To generate the ROM using MiSTer: +1) scp "releases" directory along with the zip file onto MiSTer:/media/fat/ +2) Using OSD execute build_rom.sh +3) Copy generated a.*.rom into root of SD card along with the Arcade-*.rbf file + diff --git a/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/DIGDUG_CORES.v b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/DIGDUG_CORES.v new file mode 100644 index 00000000..755bc250 --- /dev/null +++ b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/DIGDUG_CORES.v @@ -0,0 +1,205 @@ +//-------------------------------------------- +// FPGA DigDug (CPU part) +// +// Copyright (c) 2017 MiSTer-X +//-------------------------------------------- +module DIGDUG_CORES +( + input MCLK, // Clock (48.0MHz) + input [2:0] RSTS, // RESET [2:0] + input [2:0] IRQS, // IRQ [2:0] + input [2:0] NMIS, // NMI [2:0] + + output DEV_CL, // I/O device Interface + output [15:0] DEV_AD, + output DEV_RD, + input DEV_DV, + input [7:0] DEV_DO, + output DEV_WR, + output [7:0] DEV_DI +); + +//----------------------------------------------- +// CPU0 +//----------------------------------------------- +wire CPU0CL; +wire [15:0] CPU0AD; +wire CPU0RD; +wire CPU0DV; +wire [7:0] CPU0DI; +wire CPU0WR; +wire [7:0] CPU0DO; + +wire [7:0] CPU0IR; +//DLROM #(14,8) rom0( DEV_CL, CPU0AD[13:0], CPU0IR, ROMCL,ROMAD[13:0],ROMDT,ROMEN & (ROMAD[15:14]==2'b00) ); +cpu0_rom rom0( + .clk(DEV_CL), + .addr(CPU0AD[13:0]), + .data(CPU0IR) +); + +wire NMI0; +CPUNMIACK n0( RSTS[0], CPU0CL, CPU0AD, NMIS[0], NMI0 ); + +CPUCORE cpu0 ( + .RESET(RSTS[0]),.CLK(CPU0CL), + .IRQ(IRQS[0]),.NMI(NMI0), + .AD(CPU0AD),.IR(CPU0IR), + .RD(CPU0RD),.DV(CPU0DV),.DI(CPU0DI), + .WR(CPU0WR),.DO(CPU0DO) +); + + +//----------------------------------------------- +// CPU1 +//----------------------------------------------- +wire CPU1CL; +wire [15:0] CPU1AD; +wire CPU1RD; +wire CPU1DV; +wire [7:0] CPU1DI; +wire CPU1WR; +wire [7:0] CPU1DO; + +wire [7:0] CPU1IR; +//DLROM #(13,8) rom1( DEV_CL, CPU1AD[12:0], CPU1IR, ROMCL,ROMAD[12:0],ROMDT,ROMEN & (ROMAD[15:13]==3'b100) ); +cpu1_rom rom1( + .clk(DEV_CL), + .addr(CPU0AD[12:0]), + .data(CPU1IR) +); + +CPUCORE cpu1 ( + .RESET(RSTS[1]),.CLK(CPU1CL), + .IRQ(IRQS[1]),.NMI(NMIS[1]), + .AD(CPU1AD),.IR(CPU1IR), + .RD(CPU1RD),.DV(CPU1DV),.DI(CPU1DI), + .WR(CPU1WR),.DO(CPU1DO) +); + + +//----------------------------------------------- +// CPU2 +//----------------------------------------------- +wire CPU2CL; +wire [15:0] CPU2AD; +wire CPU2RD; +wire CPU2DV; +wire [7:0] CPU2DI; +wire CPU2WR; +wire [7:0] CPU2DO; + +wire [7:0] CPU2IR; +//DLROM #(12,8) rom2( DEV_CL, CPU2AD[11:0], CPU2IR, ROMCL,ROMAD[11:0],ROMDT,ROMEN & (ROMAD[15:12]==4'hA) ); +cpu2_rom rom2( + .clk(DEV_CL), + .addr(CPU0AD[11:0]), + .data(CPU2IR) +); + +wire NMI2; +CPUNMIACK n2( RSTS[2], CPU2CL, CPU2AD, NMIS[2], NMI2 ); + +CPUCORE cpu2 ( + .RESET(RSTS[2]),.CLK(CPU2CL), + .IRQ(IRQS[2]),.NMI(NMI2), + .AD(CPU2AD),.IR(CPU2IR), + .RD(CPU2RD),.DV(CPU2DV),.DI(CPU2DI), + .WR(CPU2WR),.DO(CPU2DO) +); + + +//----------------------------------------------- +// CPU Access Arbiter +//----------------------------------------------- +CPUARB arb +( + MCLK, + DEV_CL, DEV_AD, DEV_RD, DEV_DV, DEV_DO, DEV_WR, DEV_DI, + CPU0CL, CPU0AD, CPU0RD, CPU0DV, CPU0DI, CPU0WR, CPU0DO, + CPU1CL, CPU1AD, CPU1RD, CPU1DV, CPU1DI, CPU1WR, CPU1DO, + CPU2CL, CPU2AD, CPU2RD, CPU2DV, CPU2DI, CPU2WR, CPU2DO +); + +endmodule + + +module CPUARB +( + input CLK48M, + + output DEV_CL, + output [15:0] DEV_AD, + output DEV_RD, + input DEV_DV, + input [7:0] DEV_DO, + output DEV_WR, + output [7:0] DEV_DI, + + output CPU0CL, + input [15:0] CPU0AD, + input CPU0RD, + output CPU0DV, + output [7:0] CPU0DI, + input CPU0WR, + input [7:0] CPU0DO, + + output CPU1CL, + input [15:0] CPU1AD, + input CPU1RD, + output CPU1DV, + output [7:0] CPU1DI, + input CPU1WR, + input [7:0] CPU1DO, + + output CPU2CL, + input [15:0] CPU2AD, + input CPU2RD, + output CPU2DV, + output [7:0] CPU2DI, + input CPU2WR, + input [7:0] CPU2DO +); + +reg [1:0] clkdiv; +always @( posedge CLK48M ) clkdiv <= clkdiv+1; +wire CLK24M = clkdiv[0]; +wire CLK12M = clkdiv[1]; + +reg [3:0] CLKS = 4'b1000; +reg [3:0] BUSS = 4'b0001; +always @( posedge CLK12M ) CLKS <= {CLKS[2:0],CLKS[3]}; +always @( negedge CLK12M ) BUSS <= {BUSS[2:0],BUSS[3]}; + +assign CPU0CL = CLKS[0]; +assign CPU1CL = CLKS[1]; +assign CPU2CL = CLKS[2]; + +assign DEV_CL = CLK24M; + +assign DEV_AD = BUSS[0] ? CPU0AD : + BUSS[1] ? CPU1AD : + BUSS[2] ? CPU2AD : 0; + +assign DEV_RD = BUSS[0] ? CPU0RD : + BUSS[1] ? CPU1RD : + BUSS[2] ? CPU2RD : 0; + +assign CPU0DV = BUSS[0] ? DEV_DV : 0; +assign CPU1DV = BUSS[1] ? DEV_DV : 0; +assign CPU2DV = BUSS[2] ? DEV_DV : 0; + +assign CPU0DI = BUSS[0] ? DEV_DO : 0; +assign CPU1DI = BUSS[1] ? DEV_DO : 0; +assign CPU2DI = BUSS[2] ? DEV_DO : 0; + +assign DEV_WR = BUSS[0] ? CPU0WR : + BUSS[1] ? CPU1WR : + BUSS[2] ? CPU2WR : 0; + +assign DEV_DI = BUSS[0] ? CPU0DO : + BUSS[1] ? CPU1DO : + BUSS[2] ? CPU2DO : 0; + +endmodule + diff --git a/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/DIGDUG_CUSIO.v b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/DIGDUG_CUSIO.v new file mode 100644 index 00000000..eae7125f --- /dev/null +++ b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/DIGDUG_CUSIO.v @@ -0,0 +1,266 @@ +//----------------------------------------------- +// FPGA DigDug (Custom I/O chip emulation part) +// +// Copyright (c) 2017 MiSTer-X +//----------------------------------------------- +module DIGDUG_CUSIO +( + input RESET, + input VBLK, + + input [7:0] INP0, + input [7:0] INP1, + input [7:0] DSW0, + input [7:0] DSW1, + + input CL, + input CS, + input WR, + input [4:0] AD, + input [7:0] DI, + output [7:0] DO, + output NMI0 +); + +reg MODE; +reg [7:0] COMMAND; + +reg [3:0] r2, r3, r4, r5; +reg [3:0] LCINPCRE, LCREPCIN, LCOINS; +reg [3:0] RCINPCRE, RCREPCIN, RCOINS; +reg CREDITAT; +reg [7:0] CREDITS; + +reg [11:0] CLK50uc; +reg CLK50u; + +always @( posedge CL ) begin + if (RESET) begin + CLK50u <= 0; + CLK50uc <= 0; + end + else begin + if ( CLK50uc == 2200 ) CLK50u <= 1'b1; + if ( CLK50uc == 2400 ) begin + CLK50u <= 1'b0; + CLK50uc <= 0; + end + else CLK50uc <= CLK50uc + 1; + end +end + +reg NMI0EN = 1'b0; +assign NMI0 = NMI0EN & CLK50u; + +always @( posedge CL or posedge RESET ) begin + if (RESET) begin + NMI0EN <= 0; + MODE <= 0; + COMMAND <= 0; + + LCINPCRE <= 0; + LCREPCIN <= 0; + RCINPCRE <= 0; + RCREPCIN <= 0; + CREDITAT <= 0; + end + else begin + if (CS&WR) begin + if (AD[4]) begin + // command write + COMMAND <= DI; + MODE <= (DI==8'hA1) ? 1'b1 : ((DI==8'hC1)|(DI==8'hE1)) ? 0 : MODE; + NMI0EN <= (DI!=8'h10); + end + else begin + // data write + if (COMMAND == 8'hC1) case (AD[3:0]) + 4'h2: r2 <= DI[3:0]; + 4'h3: r3 <= DI[3:0]; + 4'h4: r4 <= DI[3:0]; + 4'h5: r5 <= DI[3:0]; + 4'h8: begin + LCINPCRE <= r2; + LCREPCIN <= r3; + RCINPCRE <= r4; + RCREPCIN <= r5; + CREDITAT <= 1'b1; + end + default:; + endcase + end + end + end +end + + +// data read +wire [3:0] ADR = AD[3:0]; +wire [7:0] NONE = 8'hFF; + +reg [7:0] SW_CC; +reg [7:0] SW_P1; +reg [7:0] SW_P2; + +wire [7:0] ST_CC; +BCDCONV bcd( CREDITS, ST_CC[3:0], ST_CC[7:4] ); + +reg [7:0] ST_P1 = 8'hF8; +reg [7:0] ST_P2 = 8'hF8; + +wire [7:0] SWMODE = (ADR==0) ? (~SW_CC) : + (ADR==1) ? (~SW_P1) : + (ADR==2) ? (~SW_P2) : NONE; + +wire [7:0] STMODE = (ADR==0) ? ST_CC : + (ADR==1) ? ST_P1 : + (ADR==2) ? ST_P2 : NONE; + +wire [7:0] READh71 = MODE ? SWMODE : STMODE; + +wire [7:0] READhB1 = {8{~(ADR<=2)}}; + +wire [7:0] READhD2 = (ADR==0) ? DSW0 : + (ADR==1) ? DSW1 : NONE; + +wire [7:0] READDAT = (COMMAND == 8'h71) ? READh71 : + (COMMAND == 8'hB1) ? READhB1 : + (COMMAND == 8'hD2) ? READhD2 : NONE; + +assign DO = AD[4] ? COMMAND : READDAT; + +//------------------------------------------------------------ + +// INP0 = { SERVICE, 1'b0, m_coin2, m_coin1, m_start2, m_start1, m_pump2, m_pump1 }; +// INP1 = { m_left2, m_down2, m_right2, m_up2, m_left1, m_down1, m_right1, m_up1 }; + +reg [15:0] pINP,piINP,piINP0,piINP1,piINP2; +wire [15:0] nINP = {INP0,INP1}; +wire [15:0] iINP = (pINP^nINP) & nINP; + +function [3:0] stick; +input [3:0] stk; + stick = stk[0] ? 0 : + stk[1] ? 2 : + stk[2] ? 4 : + stk[3] ? 6 : 8; +endfunction + +always @( posedge VBLK or posedge RESET ) begin + if (RESET) begin + LCOINS = 0; + RCOINS = 0; + CREDITS = 0; + + SW_CC <= 0; + SW_P1 <= 0; + SW_P2 <= 0; + ST_P1 <= 8'hF8; + ST_P2 <= 8'hF8; + + pINP <= 0; + piINP <= 0; + piINP0 <= 0; + piINP1 <= 0; + piINP2 <= 0; + end + else begin + + SW_CC <= {nINP[15],1'b0,piINP[11],piINP[10],2'b00,iINP[13],iINP[12]}; + SW_P1 <= {2'b00, pINP[8], iINP[8],nINP[3:0]}; + SW_P2 <= {2'b00, pINP[9], iINP[9],nINP[7:4]}; + ST_P1 <= {2'b11,~pINP[8],~iINP[8],stick(nINP[3:0])}; + ST_P2 <= {2'b11,~pINP[9],~iINP[9],stick(nINP[7:4])}; + + if (CREDITAT) begin + if ( LCINPCRE > 0 ) begin + if ( iINP[12] & ( CREDITS < 99 ) ) begin + LCOINS = LCOINS+1; + if ( LCOINS >= LCINPCRE ) begin + CREDITS = CREDITS + LCREPCIN; + LCOINS = 0; + end + end + if ( iINP[13] & ( CREDITS < 99 ) ) begin + RCOINS = RCOINS+1; + if ( RCOINS >= RCINPCRE ) begin + CREDITS = CREDITS + RCREPCIN; + RCOINS = 0; + end + end + end + else CREDITS = 2; + if ( CREDITS > 99 ) CREDITS = 99; + + if ( piINP[10] & (CREDITS >= 1) ) CREDITS = CREDITS-1; + if ( piINP[11] & (CREDITS >= 2) ) CREDITS = CREDITS-2; + end + + pINP <= nINP; + piINP0 <= iINP; + piINP1 <= piINP0; + piINP2 <= piINP1; + piINP <= piINP2; // delay start buttons + + end +end + +endmodule + + + +//---------------------------------------- +// BCD Converter +//---------------------------------------- +module add3(in,out); + +input [3:0] in; +output [3:0] out; +reg [3:0] out; + +always @ (in) + case (in) + 4'b0000: out <= 4'b0000; + 4'b0001: out <= 4'b0001; + 4'b0010: out <= 4'b0010; + 4'b0011: out <= 4'b0011; + 4'b0100: out <= 4'b0100; + 4'b0101: out <= 4'b1000; + 4'b0110: out <= 4'b1001; + 4'b0111: out <= 4'b1010; + 4'b1000: out <= 4'b1011; + 4'b1001: out <= 4'b1100; + default: out <= 4'b0000; + endcase + +endmodule + + +module BCDCONV(A,ONES,TENS); + +input [7:0] A; +output [3:0] ONES, TENS; +wire [3:0] c1,c2,c3,c4,c5,c6,c7; +wire [3:0] d1,d2,d3,d4,d5,d6,d7; + +assign d1 = {1'b0,A[7:5]}; +assign d2 = {c1[2:0],A[4]}; +assign d3 = {c2[2:0],A[3]}; +assign d4 = {c3[2:0],A[2]}; +assign d5 = {c4[2:0],A[1]}; +assign d6 = {1'b0,c1[3],c2[3],c3[3]}; +assign d7 = {c6[2:0],c4[3]}; + +add3 m1(d1,c1); +add3 m2(d2,c2); +add3 m3(d3,c3); +add3 m4(d4,c4); +add3 m5(d5,c5); +add3 m6(d6,c6); +add3 m7(d7,c7); + +assign ONES = {c5[2:0],A[0]}; +assign TENS = {c7[2:0],c5[3]}; + +endmodule + diff --git a/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/DIGDUG_IODEV.v b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/DIGDUG_IODEV.v new file mode 100644 index 00000000..5314b0bc --- /dev/null +++ b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/DIGDUG_IODEV.v @@ -0,0 +1,197 @@ +//-------------------------------------------- +// FPGA DigDug (I/O device part) +// +// Copyright (c) 2017 MiSTer-X +//-------------------------------------------- +module DIGDUG_IODEV +( + input RESET, + + input [7:0] INP0, + input [7:0] INP1, + input [7:0] DSW0, + input [7:0] DSW1, + + input VBLK, // V-BLANK + + input CL, // CPU Interface + input [15:0] AD, + input WR, + input [7:0] DI, + input RD, + output DV, + output [7:0] DO, + + output [2:0] RSTS, // CPU Reset Ctrl & Interrupt + output [2:0] IRQS, + output [2:0] NMIS, + + input CLK48M, + output PCMCLK, + output [7:0] PCMOUT, + + output WAVECL, // Wave ROM + output [7:0] WAVEAD, + input [3:0] WAVEDT, + + input FGSCCL, // FG VRAM + input [9:0] FGSCAD, + output [7:0] FGSCDT, + + input SPATCL, // SP ARAM + input [6:0] SPATAD, + output [23:0] SPATDT, + + output [1:0] BG_SELECT, // Video Ctrl. + output [1:0] BG_COLBNK, + output BG_CUTOFF, + output FG_CLMODE + +); + +// Work & Video Memory +wire CSM0 = (AD[15:11] == 5'b1000_0); // $8000-$87FF +wire CSM1 = (AD[15:11] == 5'b1000_1); // $8800-$8FFF +wire CSM2 = (AD[15:11] == 5'b1001_0); // $9000-$97FF +wire CSM3 = (AD[15:11] == 5'b1001_1); // $9800-$9FFF + +wire [10:0] MAD = AD[10:0]; +wire [7:0] DOM0, DOM1, DOM2, DOM3; +DPR2KV ram0( CL, MAD, CSM0, WR, DI, DOM0, FGSCCL, {1'b0,FGSCAD}, FGSCDT ); // (FGTX) $8000-$8300 +DPR2KV ram1( CL, MAD, CSM1, WR, DI, DOM1, SPATCL, {4'h7,SPATAD}, SPATDT[ 7: 0] ); // (SPA0) $8B80-$8BFF +DPR2KV ram2( CL, MAD, CSM2, WR, DI, DOM2, SPATCL, {4'h7,SPATAD}, SPATDT[15: 8] ); // (SPA1) $9380-$93FF +DPR2KV ram3( CL, MAD, CSM3, WR, DI, DOM3, SPATCL, {4'h7,SPATAD}, SPATDT[23:16] ); // (SPA2) $9B80-$9BFF + + +// NAMCO WSG +wire WSGWR =( AD[15:5] == 11'b0110_1000_000 ) & WR; // $6800-$681F +WSG_3CH wsg( CLK48M, RESET, CL, AD[4:0], DI[3:0], WSGWR, WAVECL, WAVEAD, WAVEDT, PCMCLK, PCMOUT ); + + +// NAMCO Custom I/O Chip +wire CSCUSIO = (AD[15:9] == 7'b0111_000); // $70xx-$71xx +wire [7:0] DOCUSIO; +wire NMI0; +DIGDUG_CUSIO cusio( RESET, VBLK, INP0, INP1, DSW0, DSW1, CL, CSCUSIO, WR, {AD[8],AD[3:0]}, DI, DOCUSIO, NMI0 ); + + +// Video Ctrl Latches +wire VLWR = (AD[15:3] == 13'b1010_0000_0000_0) & WR; // $A000-$A007 +DIGDUG_VLATCH vlats( RESET, CL, AD[2:0], VLWR, DI[0], BG_SELECT, BG_COLBNK, BG_CUTOFF, FG_CLMODE ); + + +// CPU Ctrl Latches +wire CLWR = (AD[15:3] == 13'b0110_1000_0010_0) & WR; // $6820-$6827 +wire NMI2; +DIGDUG_CLATCH clats( RESET, CL, AD[2:0], CLWR, DI[0], VBLK, RSTS, IRQS, NMI2 ); + + +// To CPU +assign DV = CSM0|CSM1|CSM2|CSM3|CSCUSIO; +assign DO = CSM0 ? DOM0 : CSM1 ? DOM1 : CSM2 ? DOM2 : CSM3 ? DOM3 : CSCUSIO ? DOCUSIO : 8'hFF; +assign NMIS = {NMI2,1'b0,NMI0}; + +endmodule + + +module DIGDUG_VLATCH +( + input RESET, + input CL, + input [2:0] AD, + input WR, + input DI, + + output reg [1:0] BG_SELECT, + output reg [1:0] BG_COLBNK, + output reg BG_CUTOFF, + output reg FG_CLMODE +); + +always @( posedge CL or posedge RESET ) begin + if (RESET) begin + BG_SELECT <= 2'b00; + BG_COLBNK <= 2'b00; + BG_CUTOFF <= 1'b0; + FG_CLMODE <= 1'b0; + end + else begin + if (WR) case(AD) + 3'h0: BG_SELECT[0] <= DI; + 3'h1: BG_SELECT[1] <= DI; + 3'h2: FG_CLMODE <= DI; + 3'h3: BG_CUTOFF <= DI; + 3'h4: BG_COLBNK[0] <= DI; + 3'h5: BG_COLBNK[1] <= DI; + default:; + endcase + end +end + +endmodule + + +module DIGDUG_CLATCH +( + input RESET, + input CL, // 24MHz + input [2:0] AD, + input WR, + input DI, + + input VBLK, + output [2:0] RSTS, + output [2:0] IRQS, + output NMI2 +); + +// OSC 120Hz +`define H120FLOW (12500) +reg [3:0] clkdiv; +always @( posedge CL ) clkdiv <= clkdiv+1; +reg [13:0] H120CNT; +always @( posedge clkdiv[3] or posedge RESET ) begin + if (RESET) H120CNT <= 0; + else H120CNT <= (H120CNT==`H120FLOW) ? 0 : (H120CNT+1); +end +wire H120 = ( H120CNT >= (`H120FLOW-200) ) ? 1'b1 : 0; + + +reg IRQ0EN, IRQ0LC; +reg IRQ1EN, IRQ1LC; +reg NMI2EN, NMI2LC; +reg NMI0LC; + +reg C12RST = 1'b1; +reg pH120; + +always @( posedge CL or posedge RESET ) begin + if (RESET) begin + IRQ0EN <= 1'b0; IRQ0LC <= 1'b0; + IRQ1EN <= 1'b0; IRQ1LC <= 1'b0; + NMI2EN <= 1'b0; NMI2LC <= 1'b0; + C12RST <= 1'b1; NMI0LC <= 1'b0; + pH120 <= 1'b0; + end + else begin + if (WR) begin + case(AD) + 3'h0: begin IRQ0EN <= DI; if (~DI) IRQ0LC <= 1'b0; end + 3'h1: begin IRQ1EN <= DI; if (~DI) IRQ1LC <= 1'b0; end + 3'h2: begin NMI2EN <=~DI; if ( DI) NMI2LC <= 1'b0; end + 3'h3: C12RST <= ~DI; + default:; + endcase + end + if (VBLK) begin IRQ0LC <= 1'b1; IRQ1LC <= 1'b1; end + if ((pH120^H120)&H120) NMI2LC <= 1'b1; + pH120 <= H120; + end +end + +assign RSTS = {{2{C12RST}},RESET}; +assign IRQS = {1'b0,(IRQ1EN & IRQ1LC),(IRQ0EN & IRQ0LC)}; +assign NMI2 = (NMI2EN & NMI2LC); + +endmodule + diff --git a/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/DIGDUG_SPRITE.v b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/DIGDUG_SPRITE.v new file mode 100644 index 00000000..cb9ecc7d --- /dev/null +++ b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/DIGDUG_SPRITE.v @@ -0,0 +1,113 @@ +//-------------------------------------------- +// FPGA DigDug (Sprite part) +// +// Copyright (c) 2017 MiSTer-X +//-------------------------------------------- +module DIGDUG_SPRITE +( + input RCLK, // Rendering Clock + input VCLK, // Video Dot Clock + input VCLKx2, // Video Dot Clockx2 + + input [8:0] POSH, + input [8:0] POSV, + + output SPATCL, + output [6:0] SPATAD, + input [23:0] SPATDT, + + output reg [4:0] SPCOL +); + +wire [8:0] PH = POSH+1; +wire [8:0] PV = POSV+2; +wire [8:0] TY; + + +reg [3:0] PHASE; +reg SIDE; + +reg [7:0] ADR; +reg [23:0] ATR0, ATR1; + +reg [8:0] WXP; +reg [8:0] WCN; + + +wire SZ = ATR0[7]; // Size +wire [8:0] SS = SZ ? 32 : 16; // Size (Pixels) +wire [5:0] SC = ATR1[5:0]; // Color +wire [8:0] SX = {1'b0,ATR1[15:8]}-9'd39; // Position X +wire [8:0] SY = (9'd256-TY); // Position Y +wire [8:0] SU = (SS-WCN)^{9{ATR0[16]}}; // Position U +wire [8:0] SV = (PV-SY )^{9{ATR0[17]}}; // Position V +wire [7:0] SM = ATR0[7:0]; // Code (for Normal) +wire [7:0] SL = {SM[7]|SM[5],SM[6]|SM[4],SM[3:0],SV[4],SU[4]}; // Code (for Size) +wire [7:0] SN = SZ ? SL : SM; // Code +wire SD = ATR1[17]|((PV=(SY+SS)); // Visiblity (False:Visible) + +assign TY = ((({1'b0,ATR0[15:8]}+1)+(SZ ? 9'd16 : 9'd0)) & 9'd255) + 9'd30; + +wire ABORT = (PH==288); +wire STANDBY = (PH!=289); +wire ATRTAIL = (ADR[7]); +wire DRAWING = (WCN!=1); + + +assign SPATCL = ~RCLK; +assign SPATAD = ADR[6:0]; + +wire [8:0] WSX = {1'b0,SX[7:0]} + ((SX[7:0]<8'd16) ? 9'd256 : 9'd0); + +always @( posedge RCLK ) begin + if (ABORT) begin PHASE <= 0; WCN <= 0; end + else case (PHASE) + `define LOOP (PHASE) + `define NEXT (PHASE+1) + `define NXTA (1) + 0: begin SIDE <= PV[0]; ADR <= 0; WCN <= 0; PHASE <= STANDBY ? `LOOP : `NEXT; end + 1: begin PHASE <= ATRTAIL ? `NXTA : `NEXT; end + 2: begin ATR0 <= SPATDT; ADR <= ADR+1; PHASE <= `NEXT; end + 3: begin ATR1 <= SPATDT; ADR <= ADR+1; PHASE <= `NEXT; end + 4: begin WXP <= WSX; WCN <= SS; PHASE <= SD ? `NXTA : `NEXT; end + // CHIP Read + 5: begin /* CLUT Read */ PHASE <= `NEXT; end + // LBUF Write + 6: begin WXP <= WXP+1; WCN <= WCN-1; PHASE <= DRAWING ? 5 : `NXTA; end + default:; + endcase +end + +wire [7:0] CHRD; +//DLROMe #(14,8) spchip((PHASE==5),~RCLK,{SN,SV[3],SU[3:2],SV[2:0]},CHRD, ROMCL,ROMAD[14:0],ROMDT,ROMEN & (ROMAD[15:14]==2'b01)); +spchip_rom spchip( + .clk(~RCLK), + .addr({SN,SV[3],SU[3:2],SV[2:0]}), + .data(CHRD) +); + +wire [7:0] PIX = CHRD << (SU[1:0]); + +wire [7:0] WDT; +//DLROMe #(8,8) spclut((PHASE==5), RCLK,{SC,PIX[7],PIX[3]},WDT, ROMCL,ROMAD[7:0],ROMDT,ROMEN & (ROMAD[15:8]==8'hD9)); +spclut_rom spclut( + .clk(RCLK), + .addr({SC,PIX[7],PIX[3]}), + .data(WDT) +); + +wire [4:0] LBOUT; +LBUF1K lbuf ( + ~RCLK, {SIDE,WXP}, (PHASE==6) & (PIX[7]|PIX[3]), {4'h1,WDT[3:0]}, + VCLKx2, {~SIDE,PH}, (radr0==radr1), 8'h0, LBOUT +); + +reg [9:0] radr0=0,radr1=1; +always @(posedge VCLK) radr0 <= {~SIDE,PH}; +always @(negedge VCLK) begin + if (radr0!=radr1) SPCOL <= LBOUT; + radr1 <= radr0; +end + +endmodule + diff --git a/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/DIGDUG_VIDEO.v b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/DIGDUG_VIDEO.v new file mode 100644 index 00000000..c21251fa --- /dev/null +++ b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/DIGDUG_VIDEO.v @@ -0,0 +1,148 @@ +//-------------------------------------------- +// FPGA DigDug (Video part) +// +// Copyright (c) 2017 MiSTer-X +//-------------------------------------------- +module DIGDUG_VIDEO +( + input CLK48M, + input [8:0] POSH, + input [8:0] POSV, + + input [1:0] BG_SELECT, + input [1:0] BG_COLBNK, + input BG_CUTOFF, + input FG_CLMODE, + + output FGSCCL, + output [9:0] FGSCAD, + input [7:0] FGSCDT, + + output SPATCL, + output [6:0] SPATAD, + input [23:0] SPATDT, + + output VBLK, + output PCLK, + output [7:0] POUT +); + +//--------------------------------------- +// Clock Generator +//--------------------------------------- +reg [2:0] clkdiv; +always @( posedge CLK48M ) clkdiv <= clkdiv+1; +wire VCLKx8 = CLK48M; +//wire VCLKx4 = clkdiv[0]; +wire VCLKx2 = clkdiv[1]; +wire VCLK = clkdiv[2]; + + +//--------------------------------------- +// Local Offset +//--------------------------------------- +reg [8:0] PH, PV; +always@( posedge VCLK ) begin + PH <= POSH-1; + PV <= POSV-2; +end + + +//--------------------------------------- +// VRAM Scan Address Generator +//--------------------------------------- +wire [5:0] SCOL = PH[8:3]-2; +wire [5:0] SROW = PV[8:3]+2; +wire [9:0] VSAD = SCOL[5] ? {SCOL[4:0],SROW[4:0]} : {SROW[4:0],SCOL[4:0]}; + + +//--------------------------------------- +// Sprite ScanLine Generator +//--------------------------------------- +wire [4:0] SPCOL; + +DIGDUG_SPRITE sprite +( + .RCLK(VCLKx8),.VCLK(VCLK),.VCLKx2(VCLKx2), + .POSH(PH-1),.POSV(PV), + .SPATCL(SPATCL),.SPATAD(SPATAD),.SPATDT(SPATDT), + + .SPCOL(SPCOL) +); + + +//--------------------------------------- +// FG ScanLine Generator +//--------------------------------------- +reg [4:0] FGCOL; + +assign FGSCCL = VCLKx2; +assign FGSCAD = VSAD; + +wire [10:0] FGCHAD = {1'b0,FGSCDT[6:0],PV[2:0]}; +wire [7:0] FGCHDT; +//DLROM #(11,8) fgchip(~VCLKx2,FGCHAD,FGCHDT, ROMCL,ROMAD[10:0],ROMDT,ROMEN & (ROMAD[15:11]=={4'hD,1'b0})); +fgchip_rom fgchip( + .clk(~VCLKx2), + .addr(FGCHAD), + .data(FGCHDT) +); + +wire [7:0] FGCHPX = FGCHDT >> (PH[2:0]); + +wire [3:0] FGCLUT = FG_CLMODE ? FGSCDT[3:0] : ({FGSCDT[7:5],1'b0}|{2'b00,FGSCDT[4],1'b0}); + +always @( posedge VCLKx2 ) FGCOL <= {FGCHPX[0],FGCLUT}; + + +//--------------------------------------- +// BG ScanLine Generator +//--------------------------------------- +wire [3:0] BGCOL; + +wire [11:0] BGSCAD = {BG_SELECT,VSAD}; +wire [7:0] BGSCDT; +//DLROM #(12,8) bgscrn(VCLKx2,BGSCAD,BGSCDT, ROMCL,ROMAD[11:0],ROMDT,ROMEN & (ROMAD[15:12]==4'hB)); +bgscrn_rom bgscrn( + .clk(VCLKx2), + .addr(BGSCAD), + .data(BGSCDT) +); + +wire [11:0] BGCHAD = {BGSCDT,~PH[2],PV[2:0]}; +wire [7:0] BGCHDT; +//DLROM #(12,8) bgchip(~VCLKx2,BGCHAD,BGCHDT, ROMCL,ROMAD[11:0],ROMDT,ROMEN & (ROMAD[15:12]==4'hC)); +bgchip_rom bgchip( + .clk(~VCLKx2), + .addr(BGCHAD), + .data(BGCHDT) +); + +wire [7:0] BGCHPI = BGCHDT << (PH[1:0]); +wire [1:0] BGCHPX = {BGCHPI[7],BGCHPI[3]}; + +wire [7:0] BGCLAD = BG_CUTOFF ? {6'h0F,BGCHPX} : {BG_COLBNK,BGSCDT[7:4],BGCHPX}; +//DLROM #(8,4) bgclut(VCLKx2,BGCLAD,BGCOL, ROMCL,ROMAD[7:0],ROMDT,ROMEN & (ROMAD[15:8]==8'hDA)); +bgclut_rom bgclut( + .clk(VCLKx2), + .addr(BGCLAD), + .data(BGCOL) +); + +//--------------------------------------- +// Color Mixer & Pixel Output +//--------------------------------------- +wire [4:0] CMIX = SPCOL[4] ? {1'b1,SPCOL[3:0]} : FGCOL[4] ? {1'b0,FGCOL[3:0]} : {1'b0,BGCOL}; + +//DLROM #(5,8) palet( VCLK, CMIX, POUT, ROMCL,ROMAD[4:0],ROMDT,ROMEN & (ROMAD[15:5]=={8'hDB,3'b000}) ); +palette_rom palet( + .clk(VCLK), + .addr(CMIX), + .data(POUT) +); + +assign PCLK = ~VCLK; +assign VBLK = (PH<16)&(PV==224); + +endmodule + diff --git a/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/DigDug.sv b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/DigDug.sv new file mode 100644 index 00000000..fb990976 --- /dev/null +++ b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/DigDug.sv @@ -0,0 +1,211 @@ +module DigDug( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "DIGDUG;;", + "O89,Difficulty,Medium,Hardest,Easy,Hard;", + "OAB,Life,3,5,1,2;", + "OCE,Bonus Life,M3,M4,M5,M6,M7,Nothing,M1,M2;", + "OF,Allow Continue,No,Yes;", + "OG,Demo Sound,Off,On;", + "OH,Service Mode,Off,On;", + "O34,Scanlines,None,CRT 25%,CRT 50%,CRT 75%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + +assign LED = ~ioctl_downl; +assign AUDIO_R = AUDIO_L; + +wire clock_48, pll_locked; +pll pll( + .inclk0(CLOCK_27), + .c0(clock_48), + .c1(SDRAM_CLK), + .locked (pll_locked) + ); + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [11:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoublerD; +wire ypbpr; +wire [7:0] audio; +wire hs, vs; +wire hb, vb; +wire blankn = ~(hb | vb); +wire [3:0] r, g, b; +wire key_strobe; +wire key_pressed; +wire [7:0] key_code; +wire [7:0] ioctl_index; +wire ioctl_downl; +wire ioctl_wr; +wire [24:0] ioctl_addr; +wire [7:0] ioctl_dout; +wire [13:0] rom_addr; +wire [15:0] rom_do; + +reg reset = 1; +reg rom_loaded = 0; +always @(posedge clock_48) begin + reg ioctl_downlD; + ioctl_downlD <= ioctl_downl; + if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1; + reset <= status[0] | buttons[1] | status[6] | ~rom_loaded; +end + +wire [7:0] oPIX; +assign POUT = {oPIX[7:6],2'b00,oPIX[5:3],1'b0,oPIX[2:0],1'b0}; +wire PCLK; +wire [8:0] HPOS,VPOS; +wire [11:0] POUT; +hvgen hvgen( + .HPOS(HPOS), + .VPOS(VPOS), + .PCLK(PCLK), + .iRGB(POUT), + .oRGB({b,g,r}), + .HBLK(hb), + .VBLK(vb), + .HSYN(hs), + .VSYN(vs) +); + + +wire [1:0] COIA = 2'b00; // 1coin/1credit +wire [2:0] COIB = 3'b001; // 1coin/1credit +wire CABI = 1'b1; +wire FRZE = 1'b1; + +wire [1:0] DIFC = status[9:8]+2'h2; +wire [1:0] LIFE = status[11:10]+2'h2; +wire [2:0] EXMD = status[14:12]+3'h3; +wire CONT = ~status[15]; +wire DSND = ~status[16]; +wire SERVICE = status[17]; + +FPGA_DIGDUG GameCore( + .RESET(reset), + .MCLK(clock_48), + .INP0({SERVICE, 1'b0, 1'b0, btn_coin, btn_two_players, btn_one_player, m_fire2, m_fire1 }), + .INP1({m_left2, m_down2, m_right2, m_up2, m_left1, m_down1, m_right1, m_up1}), + .DSW0({LIFE,EXMD,COIB}), + .DSW1({COIA,FRZE,DSND,CONT,CABI,DIFC}), + .PH(HPOS), + .PV(VPOS), + .PCLK(PCLK), + .POUT(oPIX), + .SOUT(audio) +); + +mist_video #(.COLOR_DEPTH(4), .SD_HCNT_WIDTH(10)) mist_video( + .clk_sys ( clock_48 ), + .SPI_SCK ( SPI_SCK ), + .SPI_SS3 ( SPI_SS3 ), + .SPI_DI ( SPI_DI ), + .R ( blankn ? r : 0 ), + .G ( blankn ? g : 0 ), + .B ( blankn ? b : 0 ), + .HSync ( hs ), + .VSync ( vs ), + .VGA_R ( VGA_R ), + .VGA_G ( VGA_G ), + .VGA_B ( VGA_B ), + .VGA_VS ( VGA_VS ), + .VGA_HS ( VGA_HS ), + .scandoubler_disable( scandoublerD ), + .scanlines ( status[4:3] ), + .ypbpr ( ypbpr ) + ); + +user_io #(.STRLEN(($size(CONF_STR)>>3)))user_io( + .clk_sys (clock_48 ), + .conf_str (CONF_STR ), + .SPI_CLK (SPI_SCK ), + .SPI_SS_IO (CONF_DATA0 ), + .SPI_MISO (SPI_DO ), + .SPI_MOSI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable (scandoublerD ), + .ypbpr (ypbpr ), + .key_strobe (key_strobe ), + .key_pressed (key_pressed ), + .key_code (key_code ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) + ); + +dac #(.C_bits(16))dac( + .clk_i(clock_48), + .res_n_i(1), + .dac_i({audio,audio}), + .dac_o(AUDIO_L) + ); + +wire m_up1 = btn_up | joystick_0[3]; +wire m_down1 = btn_down | joystick_0[2]; +wire m_left1 = btn_left | joystick_0[1]; +wire m_right1 = btn_right | joystick_0[0]; +wire m_fire1 = btn_fire1 | joystick_0[4]; + +wire m_up2 = joystick_1[3]; +wire m_down2 = joystick_1[2]; +wire m_left2 = joystick_1[1]; +wire m_right2 = joystick_1[0]; +wire m_fire2 = joystick_1[4]; + + +reg btn_one_player = 0; +reg btn_two_players = 0; +reg btn_left = 0; +reg btn_right = 0; +reg btn_down = 0; +reg btn_up = 0; +reg btn_fire1 = 0; +//reg btn_fire2 = 0; +//reg btn_fire3 = 0; +reg btn_coin = 0; + +always @(posedge clock_48) begin + reg old_state; + old_state <= key_strobe; + if(old_state != key_strobe) begin + case(key_code) + 'h75: btn_up <= key_pressed; // up + 'h72: btn_down <= key_pressed; // down + 'h6B: btn_left <= key_pressed; // left + 'h74: btn_right <= key_pressed; // right + 'h76: btn_coin <= key_pressed; // ESC + 'h05: btn_one_player <= key_pressed; // F1 + 'h06: btn_two_players <= key_pressed; // F2 + // 'h14: btn_fire3 <= key_pressed; // ctrl + // 'h11: btn_fire2 <= key_pressed; // alt + 'h29: btn_fire1 <= key_pressed; // Space + endcase + end +end + + +endmodule diff --git a/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/FPGA_DIGDUG.v b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/FPGA_DIGDUG.v new file mode 100644 index 00000000..ecb0f3f3 --- /dev/null +++ b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/FPGA_DIGDUG.v @@ -0,0 +1,138 @@ +//-------------------------------------------- +// FPGA DigDug (Top module) +// +// Copyright (c) 2017 MiSTer-X +//-------------------------------------------- +module FPGA_DIGDUG +( + input RESET, // RESET + input MCLK, // Master Clock (48.0MHz) = VCLKx8 + input [7:0] INP0, // Control Panel + input [7:0] INP1, + input [7:0] DSW0, + input [7:0] DSW1, + + input [8:0] PH, // PIXEL H + input [8:0] PV, // PIXEL V + output PCLK, // PIXEL CLOCK + output [7:0] POUT, // PIXEL OUT + + output reg [7:0] SOUT +); + +// Common I/O Device Bus +wire DEV_CL; +wire [15:0] DEV_AD; +wire DEV_RD; +wire DEV_DV; +wire [7:0] DEV_DO; +wire DEV_WR; +wire [7:0] DEV_DI; + + +//----------------------------------------------- +// CPUs +//----------------------------------------------- +wire [2:0] RSTS,IRQS,NMIS; + +DIGDUG_CORES cores +( + .MCLK(MCLK), + .RSTS(RSTS), + .IRQS(IRQS), + .NMIS(NMIS), + .DEV_CL(DEV_CL), + .DEV_AD(DEV_AD), + .DEV_RD(DEV_RD), + .DEV_DV(DEV_DV), + .DEV_DO(DEV_DO), + .DEV_WR(DEV_WR), + .DEV_DI(DEV_DI) +); + + +//----------------------------------------------- +// Sound wave ROM +//----------------------------------------------- +wire WAVECL; +wire [7:0] WAVEAD; +wire [7:0] WAVEDT; + +//DLROM #(8,4) wave(WAVECL,WAVEAD,WAVEDT, ROMCL,ROMAD[7:0],ROMDT,ROMEN & (ROMAD[15:8]==8'hD8)); +wave_rom wave( + .clk(WAVECL), + .addr(WAVEAD), + .data(WAVEDT) +); + + +//----------------------------------------------- +// Common I/O Device Module +//----------------------------------------------- +wire PCMCLK; +wire [7:0] PCMOUT; +always @(posedge PCMCLK) SOUT <= PCMOUT; + +wire FGSCCL; +wire [9:0] FGSCAD; +wire [7:0] FGSCDT; + +wire SPATCL; +wire [6:0] SPATAD; +wire [23:0] SPATDT; + +wire [1:0] BG_SELECT; +wire [1:0] BG_COLBNK; +wire BG_CUTOFF; +wire FG_CLMODE; + +wire VBLK; + +DIGDUG_IODEV iodev +( + .RESET(RESET), + .VBLK(VBLK), + + .INP0(INP0), + .INP1(INP1), + .DSW0(DSW0), + .DSW1(DSW1), + + .CL(DEV_CL), // Access Clock: 24.0MHz + .AD(DEV_AD),.WR(DEV_WR),.DI(DEV_DI), + .RD(DEV_RD),.DV(DEV_DV),.DO(DEV_DO), + + .RSTS(RSTS),.IRQS(IRQS),.NMIS(NMIS), + + .CLK48M(MCLK),.PCMCLK(PCMCLK),.PCMOUT(PCMOUT), + + .WAVECL(WAVECL),.WAVEAD(WAVEAD),.WAVEDT(WAVEDT[3:0]), + + .FGSCCL(FGSCCL),.FGSCAD(FGSCAD),.FGSCDT(FGSCDT), + .SPATCL(SPATCL),.SPATAD(SPATAD),.SPATDT(SPATDT), + + .BG_SELECT(BG_SELECT),.BG_COLBNK(BG_COLBNK),.BG_CUTOFF(BG_CUTOFF), + .FG_CLMODE(FG_CLMODE) +); + + +//----------------------------------------------- +// Video Module +//----------------------------------------------- +DIGDUG_VIDEO video +( + .CLK48M(MCLK), + .POSH(PH+1),.POSV(PV+2), + + .BG_SELECT(BG_SELECT),.BG_COLBNK(BG_COLBNK),.BG_CUTOFF(BG_CUTOFF), + .FG_CLMODE(FG_CLMODE), + + .FGSCCL(FGSCCL),.FGSCAD(FGSCAD),.FGSCDT(FGSCDT), + .SPATCL(SPATCL),.SPATAD(SPATAD),.SPATDT(SPATDT), + + .VBLK(VBLK),.PCLK(PCLK),.POUT(POUT) +); + + +endmodule + diff --git a/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/LINEBUF.qip b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/LINEBUF.qip new file mode 100644 index 00000000..cde1a836 --- /dev/null +++ b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/LINEBUF.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" +set_global_assignment -name IP_TOOL_VERSION "17.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "LINEBUF.v"] diff --git a/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/LINEBUF.v b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/LINEBUF.v new file mode 100644 index 00000000..ed6e358b --- /dev/null +++ b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/LINEBUF.v @@ -0,0 +1,246 @@ +// megafunction wizard: %RAM: 2-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: LINEBUF.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 17.1.0 Build 590 10/25/2017 SJ Lite Edition +// ************************************************************ + + +//Copyright (C) 2017 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module LINEBUF ( + address_a, + address_b, + clock_a, + clock_b, + data_a, + data_b, + wren_a, + wren_b, + q_a, + q_b); + + input [9:0] address_a; + input [9:0] address_b; + input clock_a; + input clock_b; + input [7:0] data_a; + input [7:0] data_b; + input wren_a; + input wren_b; + output [7:0] q_a; + output [7:0] q_b; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock_a; + tri0 wren_a; + tri0 wren_b; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [7:0] sub_wire0; + wire [7:0] sub_wire1; + wire [7:0] q_a = sub_wire0[7:0]; + wire [7:0] q_b = sub_wire1[7:0]; + + altsyncram altsyncram_component ( + .address_a (address_a), + .address_b (address_b), + .clock0 (clock_a), + .clock1 (clock_b), + .data_a (data_a), + .data_b (data_b), + .wren_a (wren_a), + .wren_b (wren_b), + .q_a (sub_wire0), + .q_b (sub_wire1), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .eccstatus (), + .rden_a (1'b1), + .rden_b (1'b1)); + defparam + altsyncram_component.address_reg_b = "CLOCK1", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.indata_reg_b = "CLOCK1", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 1024, + altsyncram_component.numwords_b = 1024, + altsyncram_component.operation_mode = "BIDIR_DUAL_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.ram_block_type = "M9K", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ", + altsyncram_component.widthad_a = 10, + altsyncram_component.widthad_b = 10, + altsyncram_component.width_a = 8, + altsyncram_component.width_b = 8, + altsyncram_component.width_byteena_a = 1, + altsyncram_component.width_byteena_b = 1, + altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1"; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLRdata NUMERIC "0" +// Retrieval info: PRIVATE: CLRq NUMERIC "0" +// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRrren NUMERIC "0" +// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRwren NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "5" +// Retrieval info: PRIVATE: Clock_A NUMERIC "0" +// Retrieval info: PRIVATE: Clock_B NUMERIC "0" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192" +// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" +// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" +// Retrieval info: PRIVATE: REGdata NUMERIC "1" +// Retrieval info: PRIVATE: REGq NUMERIC "0" +// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" +// Retrieval info: PRIVATE: REGrren NUMERIC "0" +// Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +// Retrieval info: PRIVATE: REGwren NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" +// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +// Retrieval info: PRIVATE: VarWidth NUMERIC "0" +// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8" +// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8" +// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8" +// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8" +// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: enable NUMERIC "0" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024" +// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10" +// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" +// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1" +// Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL "address_a[9..0]" +// Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL "address_b[9..0]" +// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a" +// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b" +// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]" +// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL "data_b[7..0]" +// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]" +// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL "q_b[7..0]" +// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a" +// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b" +// Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0 +// Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0 +// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0 +// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 +// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 +// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0 +// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL LINEBUF.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL LINEBUF.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL LINEBUF.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL LINEBUF.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL LINEBUF_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL LINEBUF_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf diff --git a/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/TV80/tv80_alu.v b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/TV80/tv80_alu.v new file mode 100644 index 00000000..2f015e21 --- /dev/null +++ b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/TV80/tv80_alu.v @@ -0,0 +1,442 @@ +// +// TV80 8-Bit Microprocessor Core +// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org) +// +// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +module tv80_alu (/*AUTOARG*/ + // Outputs + Q, F_Out, + // Inputs + Arith16, Z16, ALU_Op, IR, ISet, BusA, BusB, F_In + ); + + parameter Mode = 0; + parameter Flag_C = 0; + parameter Flag_N = 1; + parameter Flag_P = 2; + parameter Flag_X = 3; + parameter Flag_H = 4; + parameter Flag_Y = 5; + parameter Flag_Z = 6; + parameter Flag_S = 7; + + input Arith16; + input Z16; + input [3:0] ALU_Op ; + input [5:0] IR; + input [1:0] ISet; + input [7:0] BusA; + input [7:0] BusB; + input [7:0] F_In; + output [7:0] Q; + output [7:0] F_Out; + reg [7:0] Q; + reg [7:0] F_Out; + + function [4:0] AddSub4; + input [3:0] A; + input [3:0] B; + input Sub; + input Carry_In; + begin + AddSub4 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + Carry_In; + end + endfunction // AddSub4 + + function [3:0] AddSub3; + input [2:0] A; + input [2:0] B; + input Sub; + input Carry_In; + begin + AddSub3 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + Carry_In; + end + endfunction // AddSub4 + + function [1:0] AddSub1; + input A; + input B; + input Sub; + input Carry_In; + begin + AddSub1 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + Carry_In; + end + endfunction // AddSub4 + + // AddSub variables (temporary signals) + reg UseCarry; + reg Carry7_v; + reg OverFlow_v; + reg HalfCarry_v; + reg Carry_v; + reg [7:0] Q_v; + + reg [7:0] BitMask; + + + always @(/*AUTOSENSE*/ALU_Op or BusA or BusB or F_In or IR) + begin + case (IR[5:3]) + 3'b000 : BitMask = 8'b00000001; + 3'b001 : BitMask = 8'b00000010; + 3'b010 : BitMask = 8'b00000100; + 3'b011 : BitMask = 8'b00001000; + 3'b100 : BitMask = 8'b00010000; + 3'b101 : BitMask = 8'b00100000; + 3'b110 : BitMask = 8'b01000000; + default: BitMask = 8'b10000000; + endcase // case(IR[5:3]) + + UseCarry = ~ ALU_Op[2] && ALU_Op[0]; + { HalfCarry_v, Q_v[3:0] } = AddSub4(BusA[3:0], BusB[3:0], ALU_Op[1], ALU_Op[1] ^ (UseCarry && F_In[Flag_C]) ); + { Carry7_v, Q_v[6:4] } = AddSub3(BusA[6:4], BusB[6:4], ALU_Op[1], HalfCarry_v); + { Carry_v, Q_v[7] } = AddSub1(BusA[7], BusB[7], ALU_Op[1], Carry7_v); + OverFlow_v = Carry_v ^ Carry7_v; + end // always @ * + + reg [7:0] Q_t; + reg [8:0] DAA_Q; + + always @ (/*AUTOSENSE*/ALU_Op or Arith16 or BitMask or BusA or BusB + or Carry_v or F_In or HalfCarry_v or IR or ISet + or OverFlow_v or Q_v or Z16) + begin + Q_t = 8'hxx; + DAA_Q = {9{1'bx}}; + + F_Out = F_In; + case (ALU_Op) + 4'b0000, 4'b0001, 4'b0010, 4'b0011, 4'b0100, 4'b0101, 4'b0110, 4'b0111 : + begin + F_Out[Flag_N] = 1'b0; + F_Out[Flag_C] = 1'b0; + + case (ALU_Op[2:0]) + + 3'b000, 3'b001 : // ADD, ADC + begin + Q_t = Q_v; + F_Out[Flag_C] = Carry_v; + F_Out[Flag_H] = HalfCarry_v; + F_Out[Flag_P] = OverFlow_v; + end + + 3'b010, 3'b011, 3'b111 : // SUB, SBC, CP + begin + Q_t = Q_v; + F_Out[Flag_N] = 1'b1; + F_Out[Flag_C] = ~ Carry_v; + F_Out[Flag_H] = ~ HalfCarry_v; + F_Out[Flag_P] = OverFlow_v; + end + + 3'b100 : // AND + begin + Q_t[7:0] = BusA & BusB; + F_Out[Flag_H] = 1'b1; + end + + 3'b101 : // XOR + begin + Q_t[7:0] = BusA ^ BusB; + F_Out[Flag_H] = 1'b0; + end + + default : // OR 3'b110 + begin + Q_t[7:0] = BusA | BusB; + F_Out[Flag_H] = 1'b0; + end + + endcase // case(ALU_OP[2:0]) + + if (ALU_Op[2:0] == 3'b111 ) + begin // CP + F_Out[Flag_X] = BusB[3]; + F_Out[Flag_Y] = BusB[5]; + end + else + begin + F_Out[Flag_X] = Q_t[3]; + F_Out[Flag_Y] = Q_t[5]; + end + + if (Q_t[7:0] == 8'b00000000 ) + begin + F_Out[Flag_Z] = 1'b1; + if (Z16 == 1'b1 ) + begin + F_Out[Flag_Z] = F_In[Flag_Z]; // 16 bit ADC,SBC + end + end + else + begin + F_Out[Flag_Z] = 1'b0; + end // else: !if(Q_t[7:0] == 8'b00000000 ) + + F_Out[Flag_S] = Q_t[7]; + case (ALU_Op[2:0]) + 3'b000, 3'b001, 3'b010, 3'b011, 3'b111 : // ADD, ADC, SUB, SBC, CP + ; + + default : + F_Out[Flag_P] = ~(^Q_t); + endcase // case(ALU_Op[2:0]) + + if (Arith16 == 1'b1 ) + begin + F_Out[Flag_S] = F_In[Flag_S]; + F_Out[Flag_Z] = F_In[Flag_Z]; + F_Out[Flag_P] = F_In[Flag_P]; + end + end // case: 4'b0000, 4'b0001, 4'b0010, 4'b0011, 4'b0100, 4'b0101, 4'b0110, 4'b0111 + + 4'b1100 : + begin + // DAA + F_Out[Flag_H] = F_In[Flag_H]; + F_Out[Flag_C] = F_In[Flag_C]; + DAA_Q[7:0] = BusA; + DAA_Q[8] = 1'b0; + if (F_In[Flag_N] == 1'b0 ) + begin + // After addition + // Alow > 9 || H == 1 + if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 ) + begin + if ((DAA_Q[3:0] > 9) ) + begin + F_Out[Flag_H] = 1'b1; + end + else + begin + F_Out[Flag_H] = 1'b0; + end + DAA_Q = DAA_Q + 6; + end // if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 ) + + // new Ahigh > 9 || C == 1 + if (DAA_Q[8:4] > 9 || F_In[Flag_C] == 1'b1 ) + begin + DAA_Q = DAA_Q + 96; // 0x60 + end + end + else + begin + // After subtraction + if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 ) + begin + if (DAA_Q[3:0] > 5 ) + begin + F_Out[Flag_H] = 1'b0; + end + DAA_Q[7:0] = DAA_Q[7:0] - 6; + end + if (BusA > 153 || F_In[Flag_C] == 1'b1 ) + begin + DAA_Q = DAA_Q - 352; // 0x160 + end + end // else: !if(F_In[Flag_N] == 1'b0 ) + + F_Out[Flag_X] = DAA_Q[3]; + F_Out[Flag_Y] = DAA_Q[5]; + F_Out[Flag_C] = F_In[Flag_C] || DAA_Q[8]; + Q_t = DAA_Q[7:0]; + + if (DAA_Q[7:0] == 8'b00000000 ) + begin + F_Out[Flag_Z] = 1'b1; + end + else + begin + F_Out[Flag_Z] = 1'b0; + end + + F_Out[Flag_S] = DAA_Q[7]; + F_Out[Flag_P] = ~ (^DAA_Q); + end // case: 4'b1100 + + 4'b1101, 4'b1110 : + begin + // RLD, RRD + Q_t[7:4] = BusA[7:4]; + if (ALU_Op[0] == 1'b1 ) + begin + Q_t[3:0] = BusB[7:4]; + end + else + begin + Q_t[3:0] = BusB[3:0]; + end + F_Out[Flag_H] = 1'b0; + F_Out[Flag_N] = 1'b0; + F_Out[Flag_X] = Q_t[3]; + F_Out[Flag_Y] = Q_t[5]; + if (Q_t[7:0] == 8'b00000000 ) + begin + F_Out[Flag_Z] = 1'b1; + end + else + begin + F_Out[Flag_Z] = 1'b0; + end + F_Out[Flag_S] = Q_t[7]; + F_Out[Flag_P] = ~(^Q_t); + end // case: when 4'b1101, 4'b1110 + + 4'b1001 : + begin + // BIT + Q_t[7:0] = BusB & BitMask; + F_Out[Flag_S] = Q_t[7]; + if (Q_t[7:0] == 8'b00000000 ) + begin + F_Out[Flag_Z] = 1'b1; + F_Out[Flag_P] = 1'b1; + end + else + begin + F_Out[Flag_Z] = 1'b0; + F_Out[Flag_P] = 1'b0; + end + F_Out[Flag_H] = 1'b1; + F_Out[Flag_N] = 1'b0; + F_Out[Flag_X] = 1'b0; + F_Out[Flag_Y] = 1'b0; + if (IR[2:0] != 3'b110 ) + begin + F_Out[Flag_X] = BusB[3]; + F_Out[Flag_Y] = BusB[5]; + end + end // case: when 4'b1001 + + 4'b1010 : + // SET + Q_t[7:0] = BusB | BitMask; + + 4'b1011 : + // RES + Q_t[7:0] = BusB & ~ BitMask; + + 4'b1000 : + begin + // ROT + case (IR[5:3]) + 3'b000 : // RLC + begin + Q_t[7:1] = BusA[6:0]; + Q_t[0] = BusA[7]; + F_Out[Flag_C] = BusA[7]; + end + + 3'b010 : // RL + begin + Q_t[7:1] = BusA[6:0]; + Q_t[0] = F_In[Flag_C]; + F_Out[Flag_C] = BusA[7]; + end + + 3'b001 : // RRC + begin + Q_t[6:0] = BusA[7:1]; + Q_t[7] = BusA[0]; + F_Out[Flag_C] = BusA[0]; + end + + 3'b011 : // RR + begin + Q_t[6:0] = BusA[7:1]; + Q_t[7] = F_In[Flag_C]; + F_Out[Flag_C] = BusA[0]; + end + + 3'b100 : // SLA + begin + Q_t[7:1] = BusA[6:0]; + Q_t[0] = 1'b0; + F_Out[Flag_C] = BusA[7]; + end + + 3'b110 : // SLL (Undocumented) / SWAP + begin + if (Mode == 3 ) + begin + Q_t[7:4] = BusA[3:0]; + Q_t[3:0] = BusA[7:4]; + F_Out[Flag_C] = 1'b0; + end + else + begin + Q_t[7:1] = BusA[6:0]; + Q_t[0] = 1'b1; + F_Out[Flag_C] = BusA[7]; + end // else: !if(Mode == 3 ) + end // case: 3'b110 + + 3'b101 : // SRA + begin + Q_t[6:0] = BusA[7:1]; + Q_t[7] = BusA[7]; + F_Out[Flag_C] = BusA[0]; + end + + default : // SRL + begin + Q_t[6:0] = BusA[7:1]; + Q_t[7] = 1'b0; + F_Out[Flag_C] = BusA[0]; + end + endcase // case(IR[5:3]) + + F_Out[Flag_H] = 1'b0; + F_Out[Flag_N] = 1'b0; + F_Out[Flag_X] = Q_t[3]; + F_Out[Flag_Y] = Q_t[5]; + F_Out[Flag_S] = Q_t[7]; + if (Q_t[7:0] == 8'b00000000 ) + begin + F_Out[Flag_Z] = 1'b1; + end + else + begin + F_Out[Flag_Z] = 1'b0; + end + F_Out[Flag_P] = ~(^Q_t); + + if (ISet == 2'b00 ) + begin + F_Out[Flag_P] = F_In[Flag_P]; + F_Out[Flag_S] = F_In[Flag_S]; + F_Out[Flag_Z] = F_In[Flag_Z]; + end + end // case: 4'b1000 + + + default : + ; + + endcase // case(ALU_Op) + + Q = Q_t; + end // always @ (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + +endmodule // T80_ALU diff --git a/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/TV80/tv80_core.v b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/TV80/tv80_core.v new file mode 100644 index 00000000..b9f7193a --- /dev/null +++ b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/TV80/tv80_core.v @@ -0,0 +1,1356 @@ +// +// TV80 8-Bit Microprocessor Core +// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org) +// +// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +//`define TV80_REFRESH + +module tv80_core (/*AUTOARG*/ + // Outputs + m1_n, iorq, no_read, write, rfsh_n, halt_n, busak_n, A, do, mc, ts, + intcycle_n, IntE, stop, + // Inputs + reset_n, clk, cen, wait_n, int_n, nmi_n, busrq_n, dinst, di + ); + // Beginning of automatic inputs (from unused autoinst inputs) + // End of automatics + + parameter Mode = 0; // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + parameter IOWait = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle + parameter Flag_C = 0; + parameter Flag_N = 1; + parameter Flag_P = 2; + parameter Flag_X = 3; + parameter Flag_H = 4; + parameter Flag_Y = 5; + parameter Flag_Z = 6; + parameter Flag_S = 7; + + input reset_n; + input clk; + input cen; + input wait_n; + input int_n; + input nmi_n; + input busrq_n; + output m1_n; + output iorq; + output no_read; + output write; + output rfsh_n; + output halt_n; + output busak_n; + output [15:0] A; + input [7:0] dinst; + input [7:0] di; + output [7:0] do; + output [6:0] mc; + output [6:0] ts; + output intcycle_n; + output IntE; + output stop; + + reg m1_n; + reg iorq; + reg rfsh_n; + reg halt_n; + reg busak_n; + reg [15:0] A; + reg [7:0] do; + reg [6:0] mc; + reg [6:0] ts; + reg intcycle_n; + reg IntE; + reg stop; + + parameter aNone = 3'b111; + parameter aBC = 3'b000; + parameter aDE = 3'b001; + parameter aXY = 3'b010; + parameter aIOA = 3'b100; + parameter aSP = 3'b101; + parameter aZI = 3'b110; + + // Registers + reg [7:0] ACC, F; + reg [7:0] Ap, Fp; + reg [7:0] I; + reg [7:0] R; + reg [15:0] SP, PC; + reg [7:0] RegDIH; + reg [7:0] RegDIL; + wire [15:0] RegBusA; + wire [15:0] RegBusB; + wire [15:0] RegBusC; + reg [2:0] RegAddrA_r; + reg [2:0] RegAddrA; + reg [2:0] RegAddrB_r; + reg [2:0] RegAddrB; + reg [2:0] RegAddrC; + reg RegWEH; + reg RegWEL; + reg Alternate; + + // Help Registers + reg [15:0] TmpAddr; // Temporary address register + reg [7:0] IR; // Instruction register + reg [1:0] ISet; // Instruction set selector + reg [15:0] RegBusA_r; + + reg [15:0] ID16; + reg [7:0] Save_Mux; + + reg [6:0] tstate; + reg [6:0] mcycle; + reg last_mcycle, last_tstate; + reg IntE_FF1; + reg IntE_FF2; + reg Halt_FF; + reg BusReq_s; + reg BusAck; + reg ClkEn; + reg NMI_s; + reg INT_s; + reg [1:0] IStatus; + + reg [7:0] DI_Reg; + reg T_Res; + reg [1:0] XY_State; + reg [2:0] Pre_XY_F_M; + reg NextIs_XY_Fetch; + reg XY_Ind; + reg No_BTR; + reg BTR_r; + reg Auto_Wait; + reg Auto_Wait_t1; + reg Auto_Wait_t2; + reg IncDecZ; + + // ALU signals + reg [7:0] BusB; + reg [7:0] BusA; + wire [7:0] ALU_Q; + wire [7:0] F_Out; + + // Registered micro code outputs + reg [4:0] Read_To_Reg_r; + reg Arith16_r; + reg Z16_r; + reg [3:0] ALU_Op_r; + reg Save_ALU_r; + reg PreserveC_r; + reg [2:0] mcycles; + + // Micro code outputs + wire [2:0] mcycles_d; + wire [2:0] tstates; + reg IntCycle; + reg NMICycle; + wire Inc_PC; + wire Inc_WZ; + wire [3:0] IncDec_16; + wire [1:0] Prefix; + wire Read_To_Acc; + wire Read_To_Reg; + wire [3:0] Set_BusB_To; + wire [3:0] Set_BusA_To; + wire [3:0] ALU_Op; + wire Save_ALU; + wire PreserveC; + wire Arith16; + wire [2:0] Set_Addr_To; + wire Jump; + wire JumpE; + wire JumpXY; + wire Call; + wire RstP; + wire LDZ; + wire LDW; + wire LDSPHL; + wire iorq_i; + wire [2:0] Special_LD; + wire ExchangeDH; + wire ExchangeRp; + wire ExchangeAF; + wire ExchangeRS; + wire I_DJNZ; + wire I_CPL; + wire I_CCF; + wire I_SCF; + wire I_RETN; + wire I_BT; + wire I_BC; + wire I_BTR; + wire I_RLD; + wire I_RRD; + wire I_INRC; + wire SetDI; + wire SetEI; + wire [1:0] IMode; + wire Halt; + + reg [15:0] PC16; + reg [15:0] PC16_B; + reg [15:0] SP16, SP16_A, SP16_B; + reg [15:0] ID16_B; + reg Oldnmi_n; + + tv80_mcode #(Mode, Flag_C, Flag_N, Flag_P, Flag_X, Flag_H, Flag_Y, Flag_Z, Flag_S) i_mcode + ( + .IR (IR), + .ISet (ISet), + .MCycle (mcycle), + .F (F), + .NMICycle (NMICycle), + .IntCycle (IntCycle), + .MCycles (mcycles_d), + .TStates (tstates), + .Prefix (Prefix), + .Inc_PC (Inc_PC), + .Inc_WZ (Inc_WZ), + .IncDec_16 (IncDec_16), + .Read_To_Acc (Read_To_Acc), + .Read_To_Reg (Read_To_Reg), + .Set_BusB_To (Set_BusB_To), + .Set_BusA_To (Set_BusA_To), + .ALU_Op (ALU_Op), + .Save_ALU (Save_ALU), + .PreserveC (PreserveC), + .Arith16 (Arith16), + .Set_Addr_To (Set_Addr_To), + .IORQ (iorq_i), + .Jump (Jump), + .JumpE (JumpE), + .JumpXY (JumpXY), + .Call (Call), + .RstP (RstP), + .LDZ (LDZ), + .LDW (LDW), + .LDSPHL (LDSPHL), + .Special_LD (Special_LD), + .ExchangeDH (ExchangeDH), + .ExchangeRp (ExchangeRp), + .ExchangeAF (ExchangeAF), + .ExchangeRS (ExchangeRS), + .I_DJNZ (I_DJNZ), + .I_CPL (I_CPL), + .I_CCF (I_CCF), + .I_SCF (I_SCF), + .I_RETN (I_RETN), + .I_BT (I_BT), + .I_BC (I_BC), + .I_BTR (I_BTR), + .I_RLD (I_RLD), + .I_RRD (I_RRD), + .I_INRC (I_INRC), + .SetDI (SetDI), + .SetEI (SetEI), + .IMode (IMode), + .Halt (Halt), + .NoRead (no_read), + .Write (write) + ); + + tv80_alu #(Mode, Flag_C, Flag_N, Flag_P, Flag_X, Flag_H, Flag_Y, Flag_Z, Flag_S) i_alu + ( + .Arith16 (Arith16_r), + .Z16 (Z16_r), + .ALU_Op (ALU_Op_r), + .IR (IR[5:0]), + .ISet (ISet), + .BusA (BusA), + .BusB (BusB), + .F_In (F), + .Q (ALU_Q), + .F_Out (F_Out) + ); + + function [6:0] number_to_bitvec; + input [2:0] num; + begin + case (num) + 1 : number_to_bitvec = 7'b0000001; + 2 : number_to_bitvec = 7'b0000010; + 3 : number_to_bitvec = 7'b0000100; + 4 : number_to_bitvec = 7'b0001000; + 5 : number_to_bitvec = 7'b0010000; + 6 : number_to_bitvec = 7'b0100000; + 7 : number_to_bitvec = 7'b1000000; + default : number_to_bitvec = 7'bx; + endcase // case(num) + end + endfunction // number_to_bitvec + + always @(/*AUTOSENSE*/mcycle or mcycles or tstate or tstates) + begin + case (mcycles) + 1 : last_mcycle = mcycle[0]; + 2 : last_mcycle = mcycle[1]; + 3 : last_mcycle = mcycle[2]; + 4 : last_mcycle = mcycle[3]; + 5 : last_mcycle = mcycle[4]; + 6 : last_mcycle = mcycle[5]; + 7 : last_mcycle = mcycle[6]; + default : last_mcycle = 1'bx; + endcase // case(mcycles) + + case (tstates) + 0 : last_tstate = tstate[0]; + 1 : last_tstate = tstate[1]; + 2 : last_tstate = tstate[2]; + 3 : last_tstate = tstate[3]; + 4 : last_tstate = tstate[4]; + 5 : last_tstate = tstate[5]; + 6 : last_tstate = tstate[6]; + default : last_tstate = 1'bx; + endcase + end // always @ (... + + + always @(/*AUTOSENSE*/ALU_Q or BusAck or BusB or DI_Reg + or ExchangeRp or IR or Save_ALU_r or Set_Addr_To or XY_Ind + or XY_State or cen or last_tstate or mcycle) + begin + ClkEn = cen && ~ BusAck; + + if (last_tstate) + T_Res = 1'b1; + else T_Res = 1'b0; + + if (XY_State != 2'b00 && XY_Ind == 1'b0 && + ((Set_Addr_To == aXY) || + (mcycle[0] && IR == 8'b11001011) || + (mcycle[0] && IR == 8'b00110110))) + NextIs_XY_Fetch = 1'b1; + else + NextIs_XY_Fetch = 1'b0; + + if (ExchangeRp) + Save_Mux = BusB; + else if (!Save_ALU_r) + Save_Mux = DI_Reg; + else + Save_Mux = ALU_Q; + end // always @ * + + always @ (posedge clk) + begin + if (reset_n == 1'b0 ) + begin + PC <= #1 0; // Program Counter + A <= #1 0; + TmpAddr <= #1 0; + IR <= #1 8'b00000000; + ISet <= #1 2'b00; + XY_State <= #1 2'b00; + IStatus <= #1 2'b00; + mcycles <= #1 3'b000; + do <= #1 8'b00000000; + + ACC <= #1 8'hFF; + F <= #1 8'hFF; + Ap <= #1 8'hFF; + Fp <= #1 8'hFF; + I <= #1 0; + `ifdef TV80_REFRESH + R <= #1 0; + `endif + SP <= #1 16'hFFFF; + Alternate <= #1 1'b0; + + Read_To_Reg_r <= #1 5'b00000; + Arith16_r <= #1 1'b0; + BTR_r <= #1 1'b0; + Z16_r <= #1 1'b0; + ALU_Op_r <= #1 4'b0000; + Save_ALU_r <= #1 1'b0; + PreserveC_r <= #1 1'b0; + XY_Ind <= #1 1'b0; + end + else + begin + + if (ClkEn == 1'b1 ) + begin + + ALU_Op_r <= #1 4'b0000; + Save_ALU_r <= #1 1'b0; + Read_To_Reg_r <= #1 5'b00000; + + mcycles <= #1 mcycles_d; + + if (IMode != 2'b11 ) + begin + IStatus <= #1 IMode; + end + + Arith16_r <= #1 Arith16; + PreserveC_r <= #1 PreserveC; + if (ISet == 2'b10 && ALU_Op[2] == 1'b0 && ALU_Op[0] == 1'b1 && mcycle[2] ) + begin + Z16_r <= #1 1'b1; + end + else + begin + Z16_r <= #1 1'b0; + end + + if (mcycle[0] && (tstate[1] | tstate[2] | tstate[3] )) + begin + // mcycle == 1 && tstate == 1, 2, || 3 + if (tstate[2] && wait_n == 1'b1 ) + begin + `ifdef TV80_REFRESH + if (Mode < 2 ) + begin + A[7:0] <= #1 R; + A[15:8] <= #1 I; + R[6:0] <= #1 R[6:0] + 1; + end + `endif + if (Jump == 1'b0 && Call == 1'b0 && NMICycle == 1'b0 && IntCycle == 1'b0 && ~ (Halt_FF == 1'b1 || Halt == 1'b1) ) + begin + PC <= #1 PC16; + end + + if (IntCycle == 1'b1 && IStatus == 2'b01 ) + begin + IR <= #1 8'b11111111; + end + else if (Halt_FF == 1'b1 || (IntCycle == 1'b1 && IStatus == 2'b10) || NMICycle == 1'b1 ) + begin + IR <= #1 8'b00000000; + end + else + begin + IR <= #1 dinst; + end + + ISet <= #1 2'b00; + if (Prefix != 2'b00 ) + begin + if (Prefix == 2'b11 ) + begin + if (IR[5] == 1'b1 ) + begin + XY_State <= #1 2'b10; + end + else + begin + XY_State <= #1 2'b01; + end + end + else + begin + if (Prefix == 2'b10 ) + begin + XY_State <= #1 2'b00; + XY_Ind <= #1 1'b0; + end + ISet <= #1 Prefix; + end + end + else + begin + XY_State <= #1 2'b00; + XY_Ind <= #1 1'b0; + end + end // if (tstate == 2 && wait_n == 1'b1 ) + + + end + else + begin + // either (mcycle > 1) OR (mcycle == 1 AND tstate > 3) + + if (mcycle[5] ) + begin + XY_Ind <= #1 1'b1; + if (Prefix == 2'b01 ) + begin + ISet <= #1 2'b01; + end + end + + if (T_Res == 1'b1 ) + begin + BTR_r <= #1 (I_BT || I_BC || I_BTR) && ~ No_BTR; + if (Jump == 1'b1 ) + begin + A[15:8] <= #1 DI_Reg; + A[7:0] <= #1 TmpAddr[7:0]; + PC[15:8] <= #1 DI_Reg; + PC[7:0] <= #1 TmpAddr[7:0]; + end + else if (JumpXY == 1'b1 ) + begin + A <= #1 RegBusC; + PC <= #1 RegBusC; + end else if (Call == 1'b1 || RstP == 1'b1 ) + begin + A <= #1 TmpAddr; + PC <= #1 TmpAddr; + end + else if (last_mcycle && NMICycle == 1'b1 ) + begin + A <= #1 16'b0000000001100110; + PC <= #1 16'b0000000001100110; + end + else if (mcycle[2] && IntCycle == 1'b1 && IStatus == 2'b10 ) + begin + A[15:8] <= #1 I; + A[7:0] <= #1 TmpAddr[7:0]; + PC[15:8] <= #1 I; + PC[7:0] <= #1 TmpAddr[7:0]; + end + else + begin + case (Set_Addr_To) + aXY : + begin + if (XY_State == 2'b00 ) + begin + A <= #1 RegBusC; + end + else + begin + if (NextIs_XY_Fetch == 1'b1 ) + begin + A <= #1 PC; + end + else + begin + A <= #1 TmpAddr; + end + end // else: !if(XY_State == 2'b00 ) + end // case: aXY + + aIOA : + begin + if (Mode == 3 ) + begin + // Memory map I/O on GBZ80 + A[15:8] <= #1 8'hFF; + end + else if (Mode == 2 ) + begin + // Duplicate I/O address on 8080 + A[15:8] <= #1 DI_Reg; + end + else + begin + A[15:8] <= #1 ACC; + end + A[7:0] <= #1 DI_Reg; + end // case: aIOA + + + aSP : + begin + A <= #1 SP; + end + + aBC : + begin + if (Mode == 3 && iorq_i == 1'b1 ) + begin + // Memory map I/O on GBZ80 + A[15:8] <= #1 8'hFF; + A[7:0] <= #1 RegBusC[7:0]; + end + else + begin + A <= #1 RegBusC; + end + end // case: aBC + + aDE : + begin + A <= #1 RegBusC; + end + + aZI : + begin + if (Inc_WZ == 1'b1 ) + begin + A <= #1 TmpAddr + 1; + end + else + begin + A[15:8] <= #1 DI_Reg; + A[7:0] <= #1 TmpAddr[7:0]; + end + end // case: aZI + + default : + begin + A <= #1 PC; + end + endcase // case(Set_Addr_To) + + end // else: !if(mcycle[2] && IntCycle == 1'b1 && IStatus == 2'b10 ) + + + Save_ALU_r <= #1 Save_ALU; + ALU_Op_r <= #1 ALU_Op; + + if (I_CPL == 1'b1 ) + begin + // CPL + ACC <= #1 ~ ACC; + F[Flag_Y] <= #1 ~ ACC[5]; + F[Flag_H] <= #1 1'b1; + F[Flag_X] <= #1 ~ ACC[3]; + F[Flag_N] <= #1 1'b1; + end + if (I_CCF == 1'b1 ) + begin + // CCF + F[Flag_C] <= #1 ~ F[Flag_C]; + F[Flag_Y] <= #1 ACC[5]; + F[Flag_H] <= #1 F[Flag_C]; + F[Flag_X] <= #1 ACC[3]; + F[Flag_N] <= #1 1'b0; + end + if (I_SCF == 1'b1 ) + begin + // SCF + F[Flag_C] <= #1 1'b1; + F[Flag_Y] <= #1 ACC[5]; + F[Flag_H] <= #1 1'b0; + F[Flag_X] <= #1 ACC[3]; + F[Flag_N] <= #1 1'b0; + end + end // if (T_Res == 1'b1 ) + + + if (tstate[2] && wait_n == 1'b1 ) + begin + if (ISet == 2'b01 && mcycle[6] ) + begin + IR <= #1 dinst; + end + if (JumpE == 1'b1 ) + begin + PC <= #1 PC16; + end + else if (Inc_PC == 1'b1 ) + begin + //PC <= #1 PC + 1; + PC <= #1 PC16; + end + if (BTR_r == 1'b1 ) + begin + //PC <= #1 PC - 2; + PC <= #1 PC16; + end + if (RstP == 1'b1 ) + begin + TmpAddr <= #1 { 10'h0, IR[5:3], 3'h0 }; + //TmpAddr <= #1 (others =>1'b0); + //TmpAddr[5:3] <= #1 IR[5:3]; + end + end + if (tstate[3] && mcycle[5] ) + begin + TmpAddr <= #1 SP16; + end + + if ((tstate[2] && wait_n == 1'b1) || (tstate[4] && mcycle[0]) ) + begin + if (IncDec_16[2:0] == 3'b111 ) + begin + SP <= #1 SP16; + end + end + + if (LDSPHL == 1'b1 ) + begin + SP <= #1 RegBusC; + end + if (ExchangeAF == 1'b1 ) + begin + Ap <= #1 ACC; + ACC <= #1 Ap; + Fp <= #1 F; + F <= #1 Fp; + end + if (ExchangeRS == 1'b1 ) + begin + Alternate <= #1 ~ Alternate; + end + end // else: !if(mcycle == 3'b001 && tstate(2) == 1'b0 ) + + + if (tstate[3] ) + begin + if (LDZ == 1'b1 ) + begin + TmpAddr[7:0] <= #1 DI_Reg; + end + if (LDW == 1'b1 ) + begin + TmpAddr[15:8] <= #1 DI_Reg; + end + + if (Special_LD[2] == 1'b1 ) + begin + case (Special_LD[1:0]) + 2'b00 : + begin + ACC <= #1 I; + F[Flag_P] <= #1 IntE_FF2; + end + + 2'b01 : + begin + ACC <= #1 R; + F[Flag_P] <= #1 IntE_FF2; + end + + 2'b10 : + I <= #1 ACC; + + `ifdef TV80_REFRESH + default : + R <= #1 ACC; + `else + default : ; + `endif + endcase + end + end // if (tstate == 3 ) + + + if ((I_DJNZ == 1'b0 && Save_ALU_r == 1'b1) || ALU_Op_r == 4'b1001 ) + begin + if (Mode == 3 ) + begin + F[6] <= #1 F_Out[6]; + F[5] <= #1 F_Out[5]; + F[7] <= #1 F_Out[7]; + if (PreserveC_r == 1'b0 ) + begin + F[4] <= #1 F_Out[4]; + end + end + else + begin + F[7:1] <= #1 F_Out[7:1]; + if (PreserveC_r == 1'b0 ) + begin + F[Flag_C] <= #1 F_Out[0]; + end + end + end // if ((I_DJNZ == 1'b0 && Save_ALU_r == 1'b1) || ALU_Op_r == 4'b1001 ) + + if (T_Res == 1'b1 && I_INRC == 1'b1 ) + begin + F[Flag_H] <= #1 1'b0; + F[Flag_N] <= #1 1'b0; + if (DI_Reg[7:0] == 8'b00000000 ) + begin + F[Flag_Z] <= #1 1'b1; + end + else + begin + F[Flag_Z] <= #1 1'b0; + end + F[Flag_S] <= #1 DI_Reg[7]; + F[Flag_P] <= #1 ~ (^DI_Reg[7:0]); + end // if (T_Res == 1'b1 && I_INRC == 1'b1 ) + + + if (tstate[1] && Auto_Wait_t1 == 1'b0 ) + begin + do <= #1 BusB; + if (I_RLD == 1'b1 ) + begin + do[3:0] <= #1 BusA[3:0]; + do[7:4] <= #1 BusB[3:0]; + end + if (I_RRD == 1'b1 ) + begin + do[3:0] <= #1 BusB[7:4]; + do[7:4] <= #1 BusA[3:0]; + end + end + + if (T_Res == 1'b1 ) + begin + Read_To_Reg_r[3:0] <= #1 Set_BusA_To; + Read_To_Reg_r[4] <= #1 Read_To_Reg; + if (Read_To_Acc == 1'b1 ) + begin + Read_To_Reg_r[3:0] <= #1 4'b0111; + Read_To_Reg_r[4] <= #1 1'b1; + end + end + + if (tstate[1] && I_BT == 1'b1 ) + begin + F[Flag_X] <= #1 ALU_Q[3]; + F[Flag_Y] <= #1 ALU_Q[1]; + F[Flag_H] <= #1 1'b0; + F[Flag_N] <= #1 1'b0; + end + if (I_BC == 1'b1 || I_BT == 1'b1 ) + begin + F[Flag_P] <= #1 IncDecZ; + end + + if ((tstate[1] && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) || + (Save_ALU_r == 1'b1 && ALU_Op_r != 4'b0111) ) + begin + case (Read_To_Reg_r) + 5'b10111 : + ACC <= #1 Save_Mux; + 5'b10110 : + do <= #1 Save_Mux; + 5'b11000 : + SP[7:0] <= #1 Save_Mux; + 5'b11001 : + SP[15:8] <= #1 Save_Mux; + 5'b11011 : + F <= #1 Save_Mux; + endcase + end // if ((tstate == 1 && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||... + end // if (ClkEn == 1'b1 ) + end // else: !if(reset_n == 1'b0 ) + end + + + //------------------------------------------------------------------------- + // + // BC('), DE('), HL('), IX && IY + // + //------------------------------------------------------------------------- + always @ (posedge clk) + begin + if (ClkEn == 1'b1 ) + begin + // Bus A / Write + RegAddrA_r <= #1 { Alternate, Set_BusA_To[2:1] }; + if (XY_Ind == 1'b0 && XY_State != 2'b00 && Set_BusA_To[2:1] == 2'b10 ) + begin + RegAddrA_r <= #1 { XY_State[1], 2'b11 }; + end + + // Bus B + RegAddrB_r <= #1 { Alternate, Set_BusB_To[2:1] }; + if (XY_Ind == 1'b0 && XY_State != 2'b00 && Set_BusB_To[2:1] == 2'b10 ) + begin + RegAddrB_r <= #1 { XY_State[1], 2'b11 }; + end + + // Address from register + RegAddrC <= #1 { Alternate, Set_Addr_To[1:0] }; + // Jump (HL), LD SP,HL + if ((JumpXY == 1'b1 || LDSPHL == 1'b1) ) + begin + RegAddrC <= #1 { Alternate, 2'b10 }; + end + if (((JumpXY == 1'b1 || LDSPHL == 1'b1) && XY_State != 2'b00) || (mcycle[5]) ) + begin + RegAddrC <= #1 { XY_State[1], 2'b11 }; + end + + if (I_DJNZ == 1'b1 && Save_ALU_r == 1'b1 && Mode < 2 ) + begin + IncDecZ <= #1 F_Out[Flag_Z]; + end + if ((tstate[2] || (tstate[3] && mcycle[0])) && IncDec_16[2:0] == 3'b100 ) + begin + if (ID16 == 0 ) + begin + IncDecZ <= #1 1'b0; + end + else + begin + IncDecZ <= #1 1'b1; + end + end + + RegBusA_r <= #1 RegBusA; + end + + end // always @ (posedge clk) + + + always @(/*AUTOSENSE*/Alternate or ExchangeDH or IncDec_16 + or RegAddrA_r or RegAddrB_r or XY_State or mcycle or tstate) + begin + if ((tstate[2] || (tstate[3] && mcycle[0] && IncDec_16[2] == 1'b1)) && XY_State == 2'b00) + RegAddrA = { Alternate, IncDec_16[1:0] }; + else if ((tstate[2] || (tstate[3] && mcycle[0] && IncDec_16[2] == 1'b1)) && IncDec_16[1:0] == 2'b10) + RegAddrA = { XY_State[1], 2'b11 }; + else if (ExchangeDH == 1'b1 && tstate[3]) + RegAddrA = { Alternate, 2'b10 }; + else if (ExchangeDH == 1'b1 && tstate[4]) + RegAddrA = { Alternate, 2'b01 }; + else + RegAddrA = RegAddrA_r; + + if (ExchangeDH == 1'b1 && tstate[3]) + RegAddrB = { Alternate, 2'b01 }; + else + RegAddrB = RegAddrB_r; + end // always @ * + + + always @(/*AUTOSENSE*/ALU_Op_r or Auto_Wait_t1 or ExchangeDH + or IncDec_16 or Read_To_Reg_r or Save_ALU_r or mcycle + or tstate or wait_n) + begin + RegWEH = 1'b0; + RegWEL = 1'b0; + if ((tstate[1] && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) || + (Save_ALU_r == 1'b1 && ALU_Op_r != 4'b0111) ) + begin + case (Read_To_Reg_r) + 5'b10000 , 5'b10001 , 5'b10010 , 5'b10011 , 5'b10100 , 5'b10101 : + begin + RegWEH = ~ Read_To_Reg_r[0]; + RegWEL = Read_To_Reg_r[0]; + end + endcase // case(Read_To_Reg_r) + + end // if ((tstate == 1 && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||... + + + if (ExchangeDH == 1'b1 && (tstate[3] || tstate[4]) ) + begin + RegWEH = 1'b1; + RegWEL = 1'b1; + end + + if (IncDec_16[2] == 1'b1 && ((tstate[2] && wait_n == 1'b1 && mcycle != 3'b001) || (tstate[3] && mcycle[0])) ) + begin + case (IncDec_16[1:0]) + 2'b00 , 2'b01 , 2'b10 : + begin + RegWEH = 1'b1; + RegWEL = 1'b1; + end + endcase + end + end // always @ * + + + always @(/*AUTOSENSE*/ExchangeDH or ID16 or IncDec_16 or RegBusA_r + or RegBusB or Save_Mux or mcycle or tstate) + begin + RegDIH = Save_Mux; + RegDIL = Save_Mux; + + if (ExchangeDH == 1'b1 && tstate[3] ) + begin + RegDIH = RegBusB[15:8]; + RegDIL = RegBusB[7:0]; + end + else if (ExchangeDH == 1'b1 && tstate[4] ) + begin + RegDIH = RegBusA_r[15:8]; + RegDIL = RegBusA_r[7:0]; + end + else if (IncDec_16[2] == 1'b1 && ((tstate[2] && mcycle != 3'b001) || (tstate[3] && mcycle[0])) ) + begin + RegDIH = ID16[15:8]; + RegDIL = ID16[7:0]; + end + end + + tv80_reg i_reg + ( + .clk (clk), + .CEN (ClkEn), + .WEH (RegWEH), + .WEL (RegWEL), + .AddrA (RegAddrA), + .AddrB (RegAddrB), + .AddrC (RegAddrC), + .DIH (RegDIH), + .DIL (RegDIL), + .DOAH (RegBusA[15:8]), + .DOAL (RegBusA[7:0]), + .DOBH (RegBusB[15:8]), + .DOBL (RegBusB[7:0]), + .DOCH (RegBusC[15:8]), + .DOCL (RegBusC[7:0]) + ); + + //------------------------------------------------------------------------- + // + // Buses + // + //------------------------------------------------------------------------- + + always @ (posedge clk) + begin + if (ClkEn == 1'b1 ) + begin + case (Set_BusB_To) + 4'b0111 : + BusB <= #1 ACC; + 4'b0000 , 4'b0001 , 4'b0010 , 4'b0011 , 4'b0100 , 4'b0101 : + begin + if (Set_BusB_To[0] == 1'b1 ) + begin + BusB <= #1 RegBusB[7:0]; + end + else + begin + BusB <= #1 RegBusB[15:8]; + end + end + 4'b0110 : + BusB <= #1 DI_Reg; + 4'b1000 : + BusB <= #1 SP[7:0]; + 4'b1001 : + BusB <= #1 SP[15:8]; + 4'b1010 : + BusB <= #1 8'b00000001; + 4'b1011 : + BusB <= #1 F; + 4'b1100 : + BusB <= #1 PC[7:0]; + 4'b1101 : + BusB <= #1 PC[15:8]; + 4'b1110 : + BusB <= #1 8'b00000000; + default : + BusB <= #1 8'hxx; + endcase + + case (Set_BusA_To) + 4'b0111 : + BusA <= #1 ACC; + 4'b0000 , 4'b0001 , 4'b0010 , 4'b0011 , 4'b0100 , 4'b0101 : + begin + if (Set_BusA_To[0] == 1'b1 ) + begin + BusA <= #1 RegBusA[7:0]; + end + else + begin + BusA <= #1 RegBusA[15:8]; + end + end + 4'b0110 : + BusA <= #1 DI_Reg; + 4'b1000 : + BusA <= #1 SP[7:0]; + 4'b1001 : + BusA <= #1 SP[15:8]; + 4'b1010 : + BusA <= #1 8'b00000000; + default : + BusB <= #1 8'hxx; + endcase + end + end + + //------------------------------------------------------------------------- + // + // Generate external control signals + // + //------------------------------------------------------------------------- +`ifdef TV80_REFRESH + always @ (posedge clk) + begin + if (reset_n == 1'b0 ) + begin + rfsh_n <= #1 1'b1; + end + else + begin + if (cen == 1'b1 ) + begin + if (mcycle[0] && ((tstate[2] && wait_n == 1'b1) || tstate[3]) ) + begin + rfsh_n <= #1 1'b0; + end + else + begin + rfsh_n <= #1 1'b1; + end + end + end + end +`endif + + always @(/*AUTOSENSE*/BusAck or Halt_FF or I_DJNZ or IntCycle + or IntE_FF1 or di or iorq_i or mcycle or tstate) + begin + mc = mcycle; + ts = tstate; + DI_Reg = di; + halt_n = ~ Halt_FF; + busak_n = ~ BusAck; + intcycle_n = ~ IntCycle; + IntE = IntE_FF1; + iorq = iorq_i; + stop = I_DJNZ; + end + + //----------------------------------------------------------------------- + // + // Syncronise inputs + // + //----------------------------------------------------------------------- + + always @ (posedge clk) + begin : sync_inputs + + if (reset_n == 1'b0 ) + begin + BusReq_s <= #1 1'b0; + INT_s <= #1 1'b0; + NMI_s <= #1 1'b0; + Oldnmi_n <= #1 1'b0; + end + else + begin + if (cen == 1'b1 ) + begin + BusReq_s <= #1 ~ busrq_n; + INT_s <= #1 ~ int_n; + if (NMICycle == 1'b1 ) + begin + NMI_s <= #1 1'b0; + end + else if (nmi_n == 1'b0 && Oldnmi_n == 1'b1 ) + begin + NMI_s <= #1 1'b1; + end + Oldnmi_n <= #1 nmi_n; + end + end + end + + //----------------------------------------------------------------------- + // + // Main state machine + // + //----------------------------------------------------------------------- + + always @ (posedge clk) + begin + if (reset_n == 1'b0 ) + begin + mcycle <= #1 7'b0000001; + tstate <= #1 7'b0000001; + Pre_XY_F_M <= #1 3'b000; + Halt_FF <= #1 1'b0; + BusAck <= #1 1'b0; + NMICycle <= #1 1'b0; + IntCycle <= #1 1'b0; + IntE_FF1 <= #1 1'b0; + IntE_FF2 <= #1 1'b0; + No_BTR <= #1 1'b0; + Auto_Wait_t1 <= #1 1'b0; + Auto_Wait_t2 <= #1 1'b0; + m1_n <= #1 1'b1; + end + else + begin + if (cen == 1'b1 ) + begin + if (T_Res == 1'b1 ) + begin + Auto_Wait_t1 <= #1 1'b0; + end + else + begin + Auto_Wait_t1 <= #1 Auto_Wait || iorq_i; + end + Auto_Wait_t2 <= #1 Auto_Wait_t1; + No_BTR <= #1 (I_BT && (~ IR[4] || ~ F[Flag_P])) || + (I_BC && (~ IR[4] || F[Flag_Z] || ~ F[Flag_P])) || + (I_BTR && (~ IR[4] || F[Flag_Z])); + if (tstate[2] ) + begin + if (SetEI == 1'b1 ) + begin + IntE_FF1 <= #1 1'b1; + IntE_FF2 <= #1 1'b1; + end + if (I_RETN == 1'b1 ) + begin + IntE_FF1 <= #1 IntE_FF2; + end + end + if (tstate[3] ) + begin + if (SetDI == 1'b1 ) + begin + IntE_FF1 <= #1 1'b0; + IntE_FF2 <= #1 1'b0; + end + end + if (IntCycle == 1'b1 || NMICycle == 1'b1 ) + begin + Halt_FF <= #1 1'b0; + end + if (mcycle[0] && tstate[2] && wait_n == 1'b1 ) + begin + m1_n <= #1 1'b1; + end + if (BusReq_s == 1'b1 && BusAck == 1'b1 ) + begin + end + else + begin + BusAck <= #1 1'b0; + if (tstate[2] && wait_n == 1'b0 ) + begin + end + else if (T_Res == 1'b1 ) + begin + if (Halt == 1'b1 ) + begin + Halt_FF <= #1 1'b1; + end + if (BusReq_s == 1'b1 ) + begin + BusAck <= #1 1'b1; + end + else + begin + tstate <= #1 7'b0000010; + if (NextIs_XY_Fetch == 1'b1 ) + begin + mcycle <= #1 7'b0100000; + Pre_XY_F_M <= #1 mcycle; + if (IR == 8'b00110110 && Mode == 0 ) + begin + Pre_XY_F_M <= #1 3'b010; + end + end + else if ((mcycle[6]) || (mcycle[5] && Mode == 1 && ISet != 2'b01) ) + begin + mcycle <= #1 number_to_bitvec(Pre_XY_F_M + 1); + end + else if ((last_mcycle) || + No_BTR == 1'b1 || + (mcycle[1] && I_DJNZ == 1'b1 && IncDecZ == 1'b1) ) + begin + m1_n <= #1 1'b0; + mcycle <= #1 7'b0000001; + IntCycle <= #1 1'b0; + NMICycle <= #1 1'b0; + if (NMI_s == 1'b1 && Prefix == 2'b00 ) + begin + NMICycle <= #1 1'b1; + IntE_FF1 <= #1 1'b0; + end + else if ((IntE_FF1 == 1'b1 && INT_s == 1'b1) && Prefix == 2'b00 && SetEI == 1'b0 ) + begin + IntCycle <= #1 1'b1; + IntE_FF1 <= #1 1'b0; + IntE_FF2 <= #1 1'b0; + end + end + else + begin + mcycle <= #1 { mcycle[5:0], mcycle[6] }; + end + end + end + else + begin // verilog has no "nor" operator + if ( ~(Auto_Wait == 1'b1 && Auto_Wait_t2 == 1'b0) && + ~(IOWait == 1 && iorq_i == 1'b1 && Auto_Wait_t1 == 1'b0) ) + begin + tstate <= #1 { tstate[5:0], tstate[6] }; + end + end + end + if (tstate[0]) + begin + m1_n <= #1 1'b0; + end + end + end + end + + always @(/*AUTOSENSE*/BTR_r or DI_Reg or IncDec_16 or JumpE or PC + or RegBusA or RegBusC or SP or tstate) + begin + if (JumpE == 1'b1 ) + begin + PC16_B = { {8{DI_Reg[7]}}, DI_Reg }; + end + else if (BTR_r == 1'b1 ) + begin + PC16_B = -2; + end + else + begin + PC16_B = 1; + end + + if (tstate[3]) + begin + SP16_A = RegBusC; + SP16_B = { {8{DI_Reg[7]}}, DI_Reg }; + end + else + begin + // suspect that ID16 and SP16 could be shared + SP16_A = SP; + + if (IncDec_16[3] == 1'b1) + SP16_B = -1; + else + SP16_B = 1; + end + + if (IncDec_16[3]) + ID16_B = -1; + else + ID16_B = 1; + + ID16 = RegBusA + ID16_B; + PC16 = PC + PC16_B; + SP16 = SP16_A + SP16_B; + end // always @ * + + + always @(/*AUTOSENSE*/IntCycle or NMICycle or mcycle) + begin + Auto_Wait = 1'b0; + if (IntCycle == 1'b1 || NMICycle == 1'b1 ) + begin + if (mcycle[0] ) + begin + Auto_Wait = 1'b1; + end + end + end // always @ * + +// synopsys dc_script_begin +// set_attribute current_design "revision" "$Id: tv80_core.v,v 1.5 2005/01/26 18:55:47 ghutchis Exp $" -type string -quiet +// synopsys dc_script_end +endmodule // T80 + diff --git a/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/TV80/tv80_mcode.v b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/TV80/tv80_mcode.v new file mode 100644 index 00000000..325e5a8c --- /dev/null +++ b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/TV80/tv80_mcode.v @@ -0,0 +1,2653 @@ +// +// TV80 8-Bit Microprocessor Core +// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org) +// +// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +module tv80_mcode + (/*AUTOARG*/ + // Outputs + MCycles, TStates, Prefix, Inc_PC, Inc_WZ, IncDec_16, Read_To_Reg, + Read_To_Acc, Set_BusA_To, Set_BusB_To, ALU_Op, Save_ALU, PreserveC, + Arith16, Set_Addr_To, IORQ, Jump, JumpE, JumpXY, Call, RstP, LDZ, + LDW, LDSPHL, Special_LD, ExchangeDH, ExchangeRp, ExchangeAF, + ExchangeRS, I_DJNZ, I_CPL, I_CCF, I_SCF, I_RETN, I_BT, I_BC, I_BTR, + I_RLD, I_RRD, I_INRC, SetDI, SetEI, IMode, Halt, NoRead, Write, + // Inputs + IR, ISet, MCycle, F, NMICycle, IntCycle + ); + + parameter Mode = 0; + parameter Flag_C = 0; + parameter Flag_N = 1; + parameter Flag_P = 2; + parameter Flag_X = 3; + parameter Flag_H = 4; + parameter Flag_Y = 5; + parameter Flag_Z = 6; + parameter Flag_S = 7; + + input [7:0] IR; + input [1:0] ISet ; + input [6:0] MCycle ; + input [7:0] F ; + input NMICycle ; + input IntCycle ; + output [2:0] MCycles ; + output [2:0] TStates ; + output [1:0] Prefix ; // None,BC,ED,DD/FD + output Inc_PC ; + output Inc_WZ ; + output [3:0] IncDec_16 ; // BC,DE,HL,SP 0 is inc + output Read_To_Reg ; + output Read_To_Acc ; + output [3:0] Set_BusA_To ; // B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + output [3:0] Set_BusB_To ; // B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + output [3:0] ALU_Op ; + output Save_ALU ; + output PreserveC ; + output Arith16 ; + output [2:0] Set_Addr_To ; // aNone,aXY,aIOA,aSP,aBC,aDE,aZI + output IORQ ; + output Jump ; + output JumpE ; + output JumpXY ; + output Call ; + output RstP ; + output LDZ ; + output LDW ; + output LDSPHL ; + output [2:0] Special_LD ; // A,I;A,R;I,A;R,A;None + output ExchangeDH ; + output ExchangeRp ; + output ExchangeAF ; + output ExchangeRS ; + output I_DJNZ ; + output I_CPL ; + output I_CCF ; + output I_SCF ; + output I_RETN ; + output I_BT ; + output I_BC ; + output I_BTR ; + output I_RLD ; + output I_RRD ; + output I_INRC ; + output SetDI ; + output SetEI ; + output [1:0] IMode ; + output Halt ; + output NoRead ; + output Write ; + + // regs + reg [2:0] MCycles ; + reg [2:0] TStates ; + reg [1:0] Prefix ; // None,BC,ED,DD/FD + reg Inc_PC ; + reg Inc_WZ ; + reg [3:0] IncDec_16 ; // BC,DE,HL,SP 0 is inc + reg Read_To_Reg ; + reg Read_To_Acc ; + reg [3:0] Set_BusA_To ; // B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + reg [3:0] Set_BusB_To ; // B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + reg [3:0] ALU_Op ; + reg Save_ALU ; + reg PreserveC ; + reg Arith16 ; + reg [2:0] Set_Addr_To ; // aNone,aXY,aIOA,aSP,aBC,aDE,aZI + reg IORQ ; + reg Jump ; + reg JumpE ; + reg JumpXY ; + reg Call ; + reg RstP ; + reg LDZ ; + reg LDW ; + reg LDSPHL ; + reg [2:0] Special_LD ; // A,I;A,R;I,A;R,A;None + reg ExchangeDH ; + reg ExchangeRp ; + reg ExchangeAF ; + reg ExchangeRS ; + reg I_DJNZ ; + reg I_CPL ; + reg I_CCF ; + reg I_SCF ; + reg I_RETN ; + reg I_BT ; + reg I_BC ; + reg I_BTR ; + reg I_RLD ; + reg I_RRD ; + reg I_INRC ; + reg SetDI ; + reg SetEI ; + reg [1:0] IMode ; + reg Halt ; + reg NoRead ; + reg Write ; + + parameter aNone = 3'b111; + parameter aBC = 3'b000; + parameter aDE = 3'b001; + parameter aXY = 3'b010; + parameter aIOA = 3'b100; + parameter aSP = 3'b101; + parameter aZI = 3'b110; + // constant aNone : std_logic_vector[2:0] = 3'b000; + // constant aXY : std_logic_vector[2:0] = 3'b001; + // constant aIOA : std_logic_vector[2:0] = 3'b010; + // constant aSP : std_logic_vector[2:0] = 3'b011; + // constant aBC : std_logic_vector[2:0] = 3'b100; + // constant aDE : std_logic_vector[2:0] = 3'b101; + // constant aZI : std_logic_vector[2:0] = 3'b110; + + function is_cc_true; + input [7:0] F; + input [2:0] cc; + begin + if (Mode == 3 ) + begin + case (cc) + 3'b000 : is_cc_true = F[7] == 1'b0; // NZ + 3'b001 : is_cc_true = F[7] == 1'b1; // Z + 3'b010 : is_cc_true = F[4] == 1'b0; // NC + 3'b011 : is_cc_true = F[4] == 1'b1; // C + 3'b100 : is_cc_true = 0; + 3'b101 : is_cc_true = 0; + 3'b110 : is_cc_true = 0; + 3'b111 : is_cc_true = 0; + endcase + end + else + begin + case (cc) + 3'b000 : is_cc_true = F[6] == 1'b0; // NZ + 3'b001 : is_cc_true = F[6] == 1'b1; // Z + 3'b010 : is_cc_true = F[0] == 1'b0; // NC + 3'b011 : is_cc_true = F[0] == 1'b1; // C + 3'b100 : is_cc_true = F[2] == 1'b0; // PO + 3'b101 : is_cc_true = F[2] == 1'b1; // PE + 3'b110 : is_cc_true = F[7] == 1'b0; // P + 3'b111 : is_cc_true = F[7] == 1'b1; // M + endcase + end + end + endfunction // is_cc_true + + + reg [2:0] DDD; + reg [2:0] SSS; + reg [1:0] DPAIR; + + always @ (/*AUTOSENSE*/F or IR or ISet or IntCycle or MCycle + or NMICycle) + begin + DDD = IR[5:3]; + SSS = IR[2:0]; + DPAIR = IR[5:4]; + + MCycles = 3'b001; + if (MCycle[0] ) + begin + TStates = 3'b100; + end + else + begin + TStates = 3'b011; + end + Prefix = 2'b00; + Inc_PC = 1'b0; + Inc_WZ = 1'b0; + IncDec_16 = 4'b0000; + Read_To_Acc = 1'b0; + Read_To_Reg = 1'b0; + Set_BusB_To = 4'b0000; + Set_BusA_To = 4'b0000; + ALU_Op = { 1'b0, IR[5:3] }; + Save_ALU = 1'b0; + PreserveC = 1'b0; + Arith16 = 1'b0; + IORQ = 1'b0; + Set_Addr_To = aNone; + Jump = 1'b0; + JumpE = 1'b0; + JumpXY = 1'b0; + Call = 1'b0; + RstP = 1'b0; + LDZ = 1'b0; + LDW = 1'b0; + LDSPHL = 1'b0; + Special_LD = 3'b000; + ExchangeDH = 1'b0; + ExchangeRp = 1'b0; + ExchangeAF = 1'b0; + ExchangeRS = 1'b0; + I_DJNZ = 1'b0; + I_CPL = 1'b0; + I_CCF = 1'b0; + I_SCF = 1'b0; + I_RETN = 1'b0; + I_BT = 1'b0; + I_BC = 1'b0; + I_BTR = 1'b0; + I_RLD = 1'b0; + I_RRD = 1'b0; + I_INRC = 1'b0; + SetDI = 1'b0; + SetEI = 1'b0; + IMode = 2'b11; + Halt = 1'b0; + NoRead = 1'b0; + Write = 1'b0; + + case (ISet) + 2'b00 : + begin + + //---------------------------------------------------------------------------- + // + // Unprefixed instructions + // + //---------------------------------------------------------------------------- + + casex (IR) + // 8 BIT LOAD GROUP + 8'b01xxxxxx : + begin + if (IR[5:0] == 6'b110110) + Halt = 1'b1; + else if (IR[2:0] == 3'b110) + begin + // LD r,(HL) + MCycles = 3'b010; + if (MCycle[0]) + Set_Addr_To = aXY; + if (MCycle[1]) + begin + Set_BusA_To[2:0] = DDD; + Read_To_Reg = 1'b1; + end + end // if (IR[2:0] == 3'b110) + else if (IR[5:3] == 3'b110) + begin + // LD (HL),r + MCycles = 3'b010; + if (MCycle[0]) + begin + Set_Addr_To = aXY; + Set_BusB_To[2:0] = SSS; + Set_BusB_To[3] = 1'b0; + end + if (MCycle[1]) + Write = 1'b1; + end // if (IR[5:3] == 3'b110) + else + begin + Set_BusB_To[2:0] = SSS; + ExchangeRp = 1'b1; + Set_BusA_To[2:0] = DDD; + Read_To_Reg = 1'b1; + end // else: !if(IR[5:3] == 3'b110) + end // case: 8'b01xxxxxx + + 8'b00xxx110 : + begin + if (IR[5:3] == 3'b110) + begin + // LD (HL),n + MCycles = 3'b011; + if (MCycle[1]) + begin + Inc_PC = 1'b1; + Set_Addr_To = aXY; + Set_BusB_To[2:0] = SSS; + Set_BusB_To[3] = 1'b0; + end + if (MCycle[2]) + Write = 1'b1; + end // if (IR[5:3] == 3'b110) + else + begin + // LD r,n + MCycles = 3'b010; + if (MCycle[1]) + begin + Inc_PC = 1'b1; + Set_BusA_To[2:0] = DDD; + Read_To_Reg = 1'b1; + end + end + end + + 8'b00001010 : + begin + // LD A,(BC) + MCycles = 3'b010; + if (MCycle[0]) + Set_Addr_To = aBC; + if (MCycle[1]) + Read_To_Acc = 1'b1; + end // case: 8'b00001010 + + 8'b00011010 : + begin + // LD A,(DE) + MCycles = 3'b010; + if (MCycle[0]) + Set_Addr_To = aDE; + if (MCycle[1]) + Read_To_Acc = 1'b1; + end // case: 8'b00011010 + + 8'b00111010 : + begin + if (Mode == 3 ) + begin + // LDD A,(HL) + MCycles = 3'b010; + if (MCycle[0]) + Set_Addr_To = aXY; + if (MCycle[1]) + begin + Read_To_Acc = 1'b1; + IncDec_16 = 4'b1110; + end + end + else + begin + // LD A,(nn) + MCycles = 3'b100; + if (MCycle[1]) + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + if (MCycle[2]) + begin + Set_Addr_To = aZI; + Inc_PC = 1'b1; + end + if (MCycle[3]) + begin + Read_To_Acc = 1'b1; + end + end // else: !if(Mode == 3 ) + end // case: 8'b00111010 + + 8'b00000010 : + begin + // LD (BC),A + MCycles = 3'b010; + if (MCycle[0]) + begin + Set_Addr_To = aBC; + Set_BusB_To = 4'b0111; + end + if (MCycle[1]) + begin + Write = 1'b1; + end + end // case: 8'b00000010 + + 8'b00010010 : + begin + // LD (DE),A + MCycles = 3'b010; + case (1'b1) // MCycle + MCycle[0] : + begin + Set_Addr_To = aDE; + Set_BusB_To = 4'b0111; + end + MCycle[1] : + Write = 1'b1; + default :; + endcase // case(MCycle) + end // case: 8'b00010010 + + 8'b00110010 : + begin + if (Mode == 3 ) + begin + // LDD (HL),A + MCycles = 3'b010; + case (1'b1) // MCycle + MCycle[0] : + begin + Set_Addr_To = aXY; + Set_BusB_To = 4'b0111; + end + MCycle[1] : + begin + Write = 1'b1; + IncDec_16 = 4'b1110; + end + default :; + endcase // case(MCycle) + + end + else + begin + // LD (nn),A + MCycles = 3'b100; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + MCycle[2] : + begin + Set_Addr_To = aZI; + Inc_PC = 1'b1; + Set_BusB_To = 4'b0111; + end + MCycle[3] : + begin + Write = 1'b1; + end + default :; + endcase + end // else: !if(Mode == 3 ) + end // case: 8'b00110010 + + + // 16 BIT LOAD GROUP + 8'b00000001,8'b00010001,8'b00100001,8'b00110001 : + begin + // LD dd,nn + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + Read_To_Reg = 1'b1; + if (DPAIR == 2'b11 ) + begin + Set_BusA_To[3:0] = 4'b1000; + end + else + begin + Set_BusA_To[2:1] = DPAIR; + Set_BusA_To[0] = 1'b1; + end + end // case: 2 + + MCycle[2] : + begin + Inc_PC = 1'b1; + Read_To_Reg = 1'b1; + if (DPAIR == 2'b11 ) + begin + Set_BusA_To[3:0] = 4'b1001; + end + else + begin + Set_BusA_To[2:1] = DPAIR; + Set_BusA_To[0] = 1'b0; + end + end // case: 3 + + default :; + endcase // case(MCycle) + end // case: 8'b00000001,8'b00010001,8'b00100001,8'b00110001 + + 8'b00101010 : + begin + if (Mode == 3 ) + begin + // LDI A,(HL) + MCycles = 3'b010; + case (1'b1) // MCycle + MCycle[0] : + Set_Addr_To = aXY; + MCycle[1] : + begin + Read_To_Acc = 1'b1; + IncDec_16 = 4'b0110; + end + + default :; + endcase + end + else + begin + // LD HL,(nn) + MCycles = 3'b101; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + MCycle[2] : + begin + Set_Addr_To = aZI; + Inc_PC = 1'b1; + LDW = 1'b1; + end + MCycle[3] : + begin + Set_BusA_To[2:0] = 3'b101; // L + Read_To_Reg = 1'b1; + Inc_WZ = 1'b1; + Set_Addr_To = aZI; + end + MCycle[4] : + begin + Set_BusA_To[2:0] = 3'b100; // H + Read_To_Reg = 1'b1; + end + default :; + endcase + end // else: !if(Mode == 3 ) + end // case: 8'b00101010 + + 8'b00100010 : + begin + if (Mode == 3 ) + begin + // LDI (HL),A + MCycles = 3'b010; + case (1'b1) // MCycle + MCycle[0] : + begin + Set_Addr_To = aXY; + Set_BusB_To = 4'b0111; + end + MCycle[1] : + begin + Write = 1'b1; + IncDec_16 = 4'b0110; + end + default :; + endcase + end + else + begin + // LD (nn),HL + MCycles = 3'b101; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + + MCycle[2] : + begin + Set_Addr_To = aZI; + Inc_PC = 1'b1; + LDW = 1'b1; + Set_BusB_To = 4'b0101; // L + end + + MCycle[3] : + begin + Inc_WZ = 1'b1; + Set_Addr_To = aZI; + Write = 1'b1; + Set_BusB_To = 4'b0100; // H + end + MCycle[4] : + Write = 1'b1; + default :; + endcase + end // else: !if(Mode == 3 ) + end // case: 8'b00100010 + + 8'b11111001 : + begin + // LD SP,HL + TStates = 3'b110; + LDSPHL = 1'b1; + end + + 8'b11xx0101 : + begin + // PUSH qq + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[0] : + begin + TStates = 3'b101; + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + if (DPAIR == 2'b11 ) + begin + Set_BusB_To = 4'b0111; + end + else + begin + Set_BusB_To[2:1] = DPAIR; + Set_BusB_To[0] = 1'b0; + Set_BusB_To[3] = 1'b0; + end + end // case: 1 + + MCycle[1] : + begin + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + if (DPAIR == 2'b11 ) + begin + Set_BusB_To = 4'b1011; + end + else + begin + Set_BusB_To[2:1] = DPAIR; + Set_BusB_To[0] = 1'b1; + Set_BusB_To[3] = 1'b0; + end + Write = 1'b1; + end // case: 2 + + MCycle[2] : + Write = 1'b1; + default :; + endcase // case(MCycle) + end // case: 8'b11000101,8'b11010101,8'b11100101,8'b11110101 + + 8'b11xx0001 : + begin + // POP qq + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[0] : + Set_Addr_To = aSP; + MCycle[1] : + begin + IncDec_16 = 4'b0111; + Set_Addr_To = aSP; + Read_To_Reg = 1'b1; + if (DPAIR == 2'b11 ) + begin + Set_BusA_To[3:0] = 4'b1011; + end + else + begin + Set_BusA_To[2:1] = DPAIR; + Set_BusA_To[0] = 1'b1; + end + end // case: 2 + + MCycle[2] : + begin + IncDec_16 = 4'b0111; + Read_To_Reg = 1'b1; + if (DPAIR == 2'b11 ) + begin + Set_BusA_To[3:0] = 4'b0111; + end + else + begin + Set_BusA_To[2:1] = DPAIR; + Set_BusA_To[0] = 1'b0; + end + end // case: 3 + + default :; + endcase // case(MCycle) + end // case: 8'b11000001,8'b11010001,8'b11100001,8'b11110001 + + + // EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + 8'b11101011 : + begin + if (Mode != 3 ) + begin + // EX DE,HL + ExchangeDH = 1'b1; + end + end + + 8'b00001000 : + begin + if (Mode == 3 ) + begin + // LD (nn),SP + MCycles = 3'b101; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + + MCycle[2] : + begin + Set_Addr_To = aZI; + Inc_PC = 1'b1; + LDW = 1'b1; + Set_BusB_To = 4'b1000; + end + + MCycle[3] : + begin + Inc_WZ = 1'b1; + Set_Addr_To = aZI; + Write = 1'b1; + Set_BusB_To = 4'b1001; + end + + MCycle[4] : + Write = 1'b1; + default :; + endcase + end + else if (Mode < 2 ) + begin + // EX AF,AF' + ExchangeAF = 1'b1; + end + end // case: 8'b00001000 + + 8'b11011001 : + begin + if (Mode == 3 ) + begin + // RETI + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[0] : + Set_Addr_To = aSP; + MCycle[1] : + begin + IncDec_16 = 4'b0111; + Set_Addr_To = aSP; + LDZ = 1'b1; + end + + MCycle[2] : + begin + Jump = 1'b1; + IncDec_16 = 4'b0111; + I_RETN = 1'b1; + SetEI = 1'b1; + end + default :; + endcase + end + else if (Mode < 2 ) + begin + // EXX + ExchangeRS = 1'b1; + end + end // case: 8'b11011001 + + 8'b11100011 : + begin + if (Mode != 3 ) + begin + // EX (SP),HL + MCycles = 3'b101; + case (1'b1) // MCycle + MCycle[0] : + Set_Addr_To = aSP; + MCycle[1] : + begin + Read_To_Reg = 1'b1; + Set_BusA_To = 4'b0101; + Set_BusB_To = 4'b0101; + Set_Addr_To = aSP; + end + MCycle[2] : + begin + IncDec_16 = 4'b0111; + Set_Addr_To = aSP; + TStates = 3'b100; + Write = 1'b1; + end + MCycle[3] : + begin + Read_To_Reg = 1'b1; + Set_BusA_To = 4'b0100; + Set_BusB_To = 4'b0100; + Set_Addr_To = aSP; + end + MCycle[4] : + begin + IncDec_16 = 4'b1111; + TStates = 3'b101; + Write = 1'b1; + end + + default :; + endcase + end // if (Mode != 3 ) + end // case: 8'b11100011 + + + // 8 BIT ARITHMETIC AND LOGICAL GROUP + 8'b10xxxxxx : + begin + if (IR[2:0] == 3'b110) + begin + // ADD A,(HL) + // ADC A,(HL) + // SUB A,(HL) + // SBC A,(HL) + // AND A,(HL) + // OR A,(HL) + // XOR A,(HL) + // CP A,(HL) + MCycles = 3'b010; + case (1'b1) // MCycle + MCycle[0] : + Set_Addr_To = aXY; + MCycle[1] : + begin + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + Set_BusB_To[2:0] = SSS; + Set_BusA_To[2:0] = 3'b111; + end + + default :; + endcase // case(MCycle) + end // if (IR[2:0] == 3'b110) + else + begin + // ADD A,r + // ADC A,r + // SUB A,r + // SBC A,r + // AND A,r + // OR A,r + // XOR A,r + // CP A,r + Set_BusB_To[2:0] = SSS; + Set_BusA_To[2:0] = 3'b111; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + end // else: !if(IR[2:0] == 3'b110) + end // case: 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,... + + 8'b11xxx110 : + begin + // ADD A,n + // ADC A,n + // SUB A,n + // SBC A,n + // AND A,n + // OR A,n + // XOR A,n + // CP A,n + MCycles = 3'b010; + if (MCycle[1] ) + begin + Inc_PC = 1'b1; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + Set_BusB_To[2:0] = SSS; + Set_BusA_To[2:0] = 3'b111; + end + end + + 8'b00xxx100 : + begin + if (IR[5:3] == 3'b110) + begin + // INC (HL) + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[0] : + Set_Addr_To = aXY; + MCycle[1] : + begin + TStates = 3'b100; + Set_Addr_To = aXY; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + PreserveC = 1'b1; + ALU_Op = 4'b0000; + Set_BusB_To = 4'b1010; + Set_BusA_To[2:0] = DDD; + end // case: 2 + + MCycle[2] : + Write = 1'b1; + default :; + endcase // case(MCycle) + end // case: 8'b00110100 + else + begin + // INC r + Set_BusB_To = 4'b1010; + Set_BusA_To[2:0] = DDD; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + PreserveC = 1'b1; + ALU_Op = 4'b0000; + end + end + + 8'b00xxx101 : + begin + if (IR[5:3] == 3'b110) + begin + // DEC (HL) + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[0] : + Set_Addr_To = aXY; + MCycle[1] : + begin + TStates = 3'b100; + Set_Addr_To = aXY; + ALU_Op = 4'b0010; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + PreserveC = 1'b1; + Set_BusB_To = 4'b1010; + Set_BusA_To[2:0] = DDD; + end // case: 2 + + MCycle[2] : + Write = 1'b1; + default :; + endcase // case(MCycle) + end + else + begin + // DEC r + Set_BusB_To = 4'b1010; + Set_BusA_To[2:0] = DDD; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + PreserveC = 1'b1; + ALU_Op = 4'b0010; + end + end + + // GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + 8'b00100111 : + begin + // DAA + Set_BusA_To[2:0] = 3'b111; + Read_To_Reg = 1'b1; + ALU_Op = 4'b1100; + Save_ALU = 1'b1; + end + + 8'b00101111 : + // CPL + I_CPL = 1'b1; + + 8'b00111111 : + // CCF + I_CCF = 1'b1; + + 8'b00110111 : + // SCF + I_SCF = 1'b1; + + 8'b00000000 : + begin + if (NMICycle == 1'b1 ) + begin + // NMI + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[0] : + begin + TStates = 3'b101; + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + Set_BusB_To = 4'b1101; + end + + MCycle[1] : + begin + TStates = 3'b100; + Write = 1'b1; + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + Set_BusB_To = 4'b1100; + end + + MCycle[2] : + begin + TStates = 3'b100; + Write = 1'b1; + end + + default :; + endcase // case(MCycle) + + end + else if (IntCycle == 1'b1 ) + begin + // INT (IM 2) + MCycles = 3'b101; + case (1'b1) // MCycle + MCycle[0] : + begin + LDZ = 1'b1; + TStates = 3'b101; + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + Set_BusB_To = 4'b1101; + end + + MCycle[1] : + begin + TStates = 3'b100; + Write = 1'b1; + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + Set_BusB_To = 4'b1100; + end + + MCycle[2] : + begin + TStates = 3'b100; + Write = 1'b1; + end + + MCycle[3] : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + + MCycle[4] : + Jump = 1'b1; + default :; + endcase + end + end // case: 8'b00000000 + + 8'b11110011 : + // DI + SetDI = 1'b1; + + 8'b11111011 : + // EI + SetEI = 1'b1; + + // 16 BIT ARITHMETIC GROUP + 8'b00001001,8'b00011001,8'b00101001,8'b00111001 : + begin + // ADD HL,ss + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[1] : + begin + NoRead = 1'b1; + ALU_Op = 4'b0000; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + Set_BusA_To[2:0] = 3'b101; + case (IR[5:4]) + 0,1,2 : + begin + Set_BusB_To[2:1] = IR[5:4]; + Set_BusB_To[0] = 1'b1; + end + + default : + Set_BusB_To = 4'b1000; + endcase // case(IR[5:4]) + + TStates = 3'b100; + Arith16 = 1'b1; + end // case: 2 + + MCycle[2] : + begin + NoRead = 1'b1; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + ALU_Op = 4'b0001; + Set_BusA_To[2:0] = 3'b100; + case (IR[5:4]) + 0,1,2 : + Set_BusB_To[2:1] = IR[5:4]; + default : + Set_BusB_To = 4'b1001; + endcase + Arith16 = 1'b1; + end // case: 3 + + default :; + endcase // case(MCycle) + end // case: 8'b00001001,8'b00011001,8'b00101001,8'b00111001 + + 8'b00000011,8'b00010011,8'b00100011,8'b00110011 : + begin + // INC ss + TStates = 3'b110; + IncDec_16[3:2] = 2'b01; + IncDec_16[1:0] = DPAIR; + end + + 8'b00001011,8'b00011011,8'b00101011,8'b00111011 : + begin + // DEC ss + TStates = 3'b110; + IncDec_16[3:2] = 2'b11; + IncDec_16[1:0] = DPAIR; + end + + // ROTATE AND SHIFT GROUP + 8'b00000111, + // RLCA + 8'b00010111, + // RLA + 8'b00001111, + // RRCA + 8'b00011111 : + // RRA + begin + Set_BusA_To[2:0] = 3'b111; + ALU_Op = 4'b1000; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + end // case: 8'b00000111,... + + + // JUMP GROUP + 8'b11000011 : + begin + // JP nn + MCycles = 3'b011; + if (MCycle[1]) + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + + if (MCycle[2]) + begin + Inc_PC = 1'b1; + Jump = 1'b1; + end + + end // case: 8'b11000011 + + 8'b11xxx010 : + begin + if (IR[5] == 1'b1 && Mode == 3 ) + begin + case (IR[4:3]) + 2'b00 : + begin + // LD ($FF00+C),A + MCycles = 3'b010; + case (1'b1) // MCycle + MCycle[0] : + begin + Set_Addr_To = aBC; + Set_BusB_To = 4'b0111; + end + MCycle[1] : + begin + Write = 1'b1; + IORQ = 1'b1; + end + + default :; + endcase // case(MCycle) + end // case: 2'b00 + + 2'b01 : + begin + // LD (nn),A + MCycles = 3'b100; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + + MCycle[2] : + begin + Set_Addr_To = aZI; + Inc_PC = 1'b1; + Set_BusB_To = 4'b0111; + end + + MCycle[3] : + Write = 1'b1; + default :; + endcase // case(MCycle) + end // case: default :... + + 2'b10 : + begin + // LD A,($FF00+C) + MCycles = 3'b010; + case (1'b1) // MCycle + MCycle[0] : + Set_Addr_To = aBC; + MCycle[1] : + begin + Read_To_Acc = 1'b1; + IORQ = 1'b1; + end + default :; + endcase // case(MCycle) + end // case: 2'b10 + + 2'b11 : + begin + // LD A,(nn) + MCycles = 3'b100; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + MCycle[2] : + begin + Set_Addr_To = aZI; + Inc_PC = 1'b1; + end + MCycle[3] : + Read_To_Acc = 1'b1; + default :; + endcase // case(MCycle) + end + endcase + end + else + begin + // JP cc,nn + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + MCycle[2] : + begin + Inc_PC = 1'b1; + if (is_cc_true(F, IR[5:3]) ) + begin + Jump = 1'b1; + end + end + + default :; + endcase + end // else: !if(DPAIR == 2'b11 ) + end // case: 8'b11000010,8'b11001010,8'b11010010,8'b11011010,8'b11100010,8'b11101010,8'b11110010,8'b11111010 + + 8'b00011000 : + begin + if (Mode != 2 ) + begin + // JR e + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[1] : + Inc_PC = 1'b1; + MCycle[2] : + begin + NoRead = 1'b1; + JumpE = 1'b1; + TStates = 3'b101; + end + default :; + endcase + end // if (Mode != 2 ) + end // case: 8'b00011000 + + // Conditional relative jumps (JR [C/NC/Z/NZ], e) + 8'b001xx000 : + begin + if (Mode != 2 ) + begin + MCycles = 3'd3; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + + case (IR[4:3]) + 0 : MCycles = (F[Flag_Z]) ? 3'd2 : 3'd3; + 1 : MCycles = (!F[Flag_Z]) ? 3'd2 : 3'd3; + 2 : MCycles = (F[Flag_C]) ? 3'd2 : 3'd3; + 3 : MCycles = (!F[Flag_C]) ? 3'd2 : 3'd3; + endcase + end + + MCycle[2] : + begin + NoRead = 1'b1; + JumpE = 1'b1; + TStates = 3'd5; + end + default :; + endcase + end // if (Mode != 2 ) + end // case: 8'b00111000 + + 8'b11101001 : + // JP (HL) + JumpXY = 1'b1; + + 8'b00010000 : + begin + if (Mode == 3 ) + begin + I_DJNZ = 1'b1; + end + else if (Mode < 2 ) + begin + // DJNZ,e + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[0] : + begin + TStates = 3'b101; + I_DJNZ = 1'b1; + Set_BusB_To = 4'b1010; + Set_BusA_To[2:0] = 3'b000; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + ALU_Op = 4'b0010; + end + MCycle[1] : + begin + I_DJNZ = 1'b1; + Inc_PC = 1'b1; + end + MCycle[2] : + begin + NoRead = 1'b1; + JumpE = 1'b1; + TStates = 3'b101; + end + default :; + endcase + end // if (Mode < 2 ) + end // case: 8'b00010000 + + + // CALL AND RETURN GROUP + 8'b11001101 : + begin + // CALL nn + MCycles = 3'b101; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + MCycle[2] : + begin + IncDec_16 = 4'b1111; + Inc_PC = 1'b1; + TStates = 3'b100; + Set_Addr_To = aSP; + LDW = 1'b1; + Set_BusB_To = 4'b1101; + end + MCycle[3] : + begin + Write = 1'b1; + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + Set_BusB_To = 4'b1100; + end + MCycle[4] : + begin + Write = 1'b1; + Call = 1'b1; + end + default :; + endcase // case(MCycle) + end // case: 8'b11001101 + + 8'b11000100,8'b11001100,8'b11010100,8'b11011100,8'b11100100,8'b11101100,8'b11110100,8'b11111100 : + begin + if (IR[5] == 1'b0 || Mode != 3 ) + begin + // CALL cc,nn + MCycles = 3'b101; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + MCycle[2] : + begin + Inc_PC = 1'b1; + LDW = 1'b1; + if (is_cc_true(F, IR[5:3]) ) + begin + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + TStates = 3'b100; + Set_BusB_To = 4'b1101; + end + else + begin + MCycles = 3'b011; + end // else: !if(is_cc_true(F, IR[5:3]) ) + end // case: 3 + + MCycle[3] : + begin + Write = 1'b1; + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + Set_BusB_To = 4'b1100; + end + + MCycle[4] : + begin + Write = 1'b1; + Call = 1'b1; + end + + default :; + endcase + end // if (IR[5] == 1'b0 || Mode != 3 ) + end // case: 8'b11000100,8'b11001100,8'b11010100,8'b11011100,8'b11100100,8'b11101100,8'b11110100,8'b11111100 + + 8'b11001001 : + begin + // RET + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[0] : + begin + TStates = 3'b101; + Set_Addr_To = aSP; + end + + MCycle[1] : + begin + IncDec_16 = 4'b0111; + Set_Addr_To = aSP; + LDZ = 1'b1; + end + + MCycle[2] : + begin + Jump = 1'b1; + IncDec_16 = 4'b0111; + end + + default :; + endcase // case(MCycle) + end // case: 8'b11001001 + + 8'b11000000,8'b11001000,8'b11010000,8'b11011000,8'b11100000,8'b11101000,8'b11110000,8'b11111000 : + begin + if (IR[5] == 1'b1 && Mode == 3 ) + begin + case (IR[4:3]) + 2'b00 : + begin + // LD ($FF00+nn),A + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + Set_Addr_To = aIOA; + Set_BusB_To = 4'b0111; + end + + MCycle[2] : + Write = 1'b1; + default :; + endcase // case(MCycle) + end // case: 2'b00 + + 2'b01 : + begin + // ADD SP,n + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[1] : + begin + ALU_Op = 4'b0000; + Inc_PC = 1'b1; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + Set_BusA_To = 4'b1000; + Set_BusB_To = 4'b0110; + end + + MCycle[2] : + begin + NoRead = 1'b1; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + ALU_Op = 4'b0001; + Set_BusA_To = 4'b1001; + Set_BusB_To = 4'b1110; // Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + end + + default :; + endcase // case(MCycle) + end // case: 2'b01 + + 2'b10 : + begin + // LD A,($FF00+nn) + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + Set_Addr_To = aIOA; + end + + MCycle[2] : + Read_To_Acc = 1'b1; + default :; + endcase // case(MCycle) + end // case: 2'b10 + + 2'b11 : + begin + // LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles = 3'b101; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + + MCycle[2] : + begin + Set_Addr_To = aZI; + Inc_PC = 1'b1; + LDW = 1'b1; + end + + MCycle[3] : + begin + Set_BusA_To[2:0] = 3'b101; // L + Read_To_Reg = 1'b1; + Inc_WZ = 1'b1; + Set_Addr_To = aZI; + end + + MCycle[4] : + begin + Set_BusA_To[2:0] = 3'b100; // H + Read_To_Reg = 1'b1; + end + + default :; + endcase // case(MCycle) + end // case: 2'b11 + + endcase // case(IR[4:3]) + + end + else + begin + // RET cc + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[0] : + begin + if (is_cc_true(F, IR[5:3]) ) + begin + Set_Addr_To = aSP; + end + else + begin + MCycles = 3'b001; + end + TStates = 3'b101; + end // case: 1 + + MCycle[1] : + begin + IncDec_16 = 4'b0111; + Set_Addr_To = aSP; + LDZ = 1'b1; + end + MCycle[2] : + begin + Jump = 1'b1; + IncDec_16 = 4'b0111; + end + default :; + endcase + end // else: !if(IR[5] == 1'b1 && Mode == 3 ) + end // case: 8'b11000000,8'b11001000,8'b11010000,8'b11011000,8'b11100000,8'b11101000,8'b11110000,8'b11111000 + + 8'b11000111,8'b11001111,8'b11010111,8'b11011111,8'b11100111,8'b11101111,8'b11110111,8'b11111111 : + begin + // RST p + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[0] : + begin + TStates = 3'b101; + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + Set_BusB_To = 4'b1101; + end + + MCycle[1] : + begin + Write = 1'b1; + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + Set_BusB_To = 4'b1100; + end + + MCycle[2] : + begin + Write = 1'b1; + RstP = 1'b1; + end + + default :; + endcase // case(MCycle) + end // case: 8'b11000111,8'b11001111,8'b11010111,8'b11011111,8'b11100111,8'b11101111,8'b11110111,8'b11111111 + + // INPUT AND OUTPUT GROUP + 8'b11011011 : + begin + if (Mode != 3 ) + begin + // IN A,(n) + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + Set_Addr_To = aIOA; + end + + MCycle[2] : + begin + Read_To_Acc = 1'b1; + IORQ = 1'b1; + end + + default :; + endcase + end // if (Mode != 3 ) + end // case: 8'b11011011 + + 8'b11010011 : + begin + if (Mode != 3 ) + begin + // OUT (n),A + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + Set_Addr_To = aIOA; + Set_BusB_To = 4'b0111; + end + + MCycle[2] : + begin + Write = 1'b1; + IORQ = 1'b1; + end + + default :; + endcase + end // if (Mode != 3 ) + end // case: 8'b11010011 + + + //---------------------------------------------------------------------------- + //---------------------------------------------------------------------------- + // MULTIBYTE INSTRUCTIONS + //---------------------------------------------------------------------------- + //---------------------------------------------------------------------------- + + 8'b11001011 : + begin + if (Mode != 2 ) + begin + Prefix = 2'b01; + end + end + + 8'b11101101 : + begin + if (Mode < 2 ) + begin + Prefix = 2'b10; + end + end + + 8'b11011101,8'b11111101 : + begin + if (Mode < 2 ) + begin + Prefix = 2'b11; + end + end + + endcase // case(IR) + end // case: 2'b00 + + + 2'b01 : + begin + + + //---------------------------------------------------------------------------- + // + // CB prefixed instructions + // + //---------------------------------------------------------------------------- + + Set_BusA_To[2:0] = IR[2:0]; + Set_BusB_To[2:0] = IR[2:0]; + + case (IR) + 8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000111, + 8'b00010000,8'b00010001,8'b00010010,8'b00010011,8'b00010100,8'b00010101,8'b00010111, + 8'b00001000,8'b00001001,8'b00001010,8'b00001011,8'b00001100,8'b00001101,8'b00001111, + 8'b00011000,8'b00011001,8'b00011010,8'b00011011,8'b00011100,8'b00011101,8'b00011111, + 8'b00100000,8'b00100001,8'b00100010,8'b00100011,8'b00100100,8'b00100101,8'b00100111, + 8'b00101000,8'b00101001,8'b00101010,8'b00101011,8'b00101100,8'b00101101,8'b00101111, + 8'b00110000,8'b00110001,8'b00110010,8'b00110011,8'b00110100,8'b00110101,8'b00110111, + 8'b00111000,8'b00111001,8'b00111010,8'b00111011,8'b00111100,8'b00111101,8'b00111111 : + begin + // RLC r + // RL r + // RRC r + // RR r + // SLA r + // SRA r + // SRL r + // SLL r (Undocumented) / SWAP r + if (MCycle[0] ) begin + ALU_Op = 4'b1000; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + end + end // case: 8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000111,... + + 8'b00000110, 8'b00001110, 8'b00010110, 8'b00011110, + 8'b00100110, 8'b00101110, 8'b00110110, 8'b00111110 : + begin + // RLC (HL) + // RL (HL) + // RRC (HL) + // RR (HL) + // SRA (HL) + // SRL (HL) + // SLA (HL) + // SLL (HL) (Undocumented) / SWAP (HL) + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[0], MCycle[6] : + Set_Addr_To = aXY; + MCycle[1] : + begin + ALU_Op = 4'b1000; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + Set_Addr_To = aXY; + TStates = 3'b100; + end + + MCycle[2] : + Write = 1'b1; + default :; + endcase // case(MCycle) + end // case: 8'b00000110,8'b00010110,8'b00001110,8'b00011110,8'b00101110,8'b00111110,8'b00100110,8'b00110110 + + 8'b01000000,8'b01000001,8'b01000010,8'b01000011,8'b01000100,8'b01000101,8'b01000111, + 8'b01001000,8'b01001001,8'b01001010,8'b01001011,8'b01001100,8'b01001101,8'b01001111, + 8'b01010000,8'b01010001,8'b01010010,8'b01010011,8'b01010100,8'b01010101,8'b01010111, + 8'b01011000,8'b01011001,8'b01011010,8'b01011011,8'b01011100,8'b01011101,8'b01011111, + 8'b01100000,8'b01100001,8'b01100010,8'b01100011,8'b01100100,8'b01100101,8'b01100111, + 8'b01101000,8'b01101001,8'b01101010,8'b01101011,8'b01101100,8'b01101101,8'b01101111, + 8'b01110000,8'b01110001,8'b01110010,8'b01110011,8'b01110100,8'b01110101,8'b01110111, + 8'b01111000,8'b01111001,8'b01111010,8'b01111011,8'b01111100,8'b01111101,8'b01111111 : + begin + // BIT b,r + if (MCycle[0] ) + begin + Set_BusB_To[2:0] = IR[2:0]; + ALU_Op = 4'b1001; + end + end // case: 8'b01000000,8'b01000001,8'b01000010,8'b01000011,8'b01000100,8'b01000101,8'b01000111,... + + 8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01110110,8'b01111110 : + begin + // BIT b,(HL) + MCycles = 3'b010; + case (1'b1) // MCycle + MCycle[0], MCycle[6] : + Set_Addr_To = aXY; + MCycle[1] : + begin + ALU_Op = 4'b1001; + TStates = 3'b100; + end + + default :; + endcase // case(MCycle) + end // case: 8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01110110,8'b01111110 + + 8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000111, + 8'b11001000,8'b11001001,8'b11001010,8'b11001011,8'b11001100,8'b11001101,8'b11001111, + 8'b11010000,8'b11010001,8'b11010010,8'b11010011,8'b11010100,8'b11010101,8'b11010111, + 8'b11011000,8'b11011001,8'b11011010,8'b11011011,8'b11011100,8'b11011101,8'b11011111, + 8'b11100000,8'b11100001,8'b11100010,8'b11100011,8'b11100100,8'b11100101,8'b11100111, + 8'b11101000,8'b11101001,8'b11101010,8'b11101011,8'b11101100,8'b11101101,8'b11101111, + 8'b11110000,8'b11110001,8'b11110010,8'b11110011,8'b11110100,8'b11110101,8'b11110111, + 8'b11111000,8'b11111001,8'b11111010,8'b11111011,8'b11111100,8'b11111101,8'b11111111 : + begin + // SET b,r + if (MCycle[0] ) + begin + ALU_Op = 4'b1010; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + end + end // case: 8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000111,... + + 8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110 : + begin + // SET b,(HL) + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[0], MCycle[6] : + Set_Addr_To = aXY; + MCycle[1] : + begin + ALU_Op = 4'b1010; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + Set_Addr_To = aXY; + TStates = 3'b100; + end + MCycle[2] : + Write = 1'b1; + default :; + endcase // case(MCycle) + end // case: 8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110 + + 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111, + 8'b10001000,8'b10001001,8'b10001010,8'b10001011,8'b10001100,8'b10001101,8'b10001111, + 8'b10010000,8'b10010001,8'b10010010,8'b10010011,8'b10010100,8'b10010101,8'b10010111, + 8'b10011000,8'b10011001,8'b10011010,8'b10011011,8'b10011100,8'b10011101,8'b10011111, + 8'b10100000,8'b10100001,8'b10100010,8'b10100011,8'b10100100,8'b10100101,8'b10100111, + 8'b10101000,8'b10101001,8'b10101010,8'b10101011,8'b10101100,8'b10101101,8'b10101111, + 8'b10110000,8'b10110001,8'b10110010,8'b10110011,8'b10110100,8'b10110101,8'b10110111, + 8'b10111000,8'b10111001,8'b10111010,8'b10111011,8'b10111100,8'b10111101,8'b10111111 : + begin + // RES b,r + if (MCycle[0] ) + begin + ALU_Op = 4'b1011; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + end + end // case: 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,... + + 8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110 : + begin + // RES b,(HL) + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[0], MCycle[6] : + Set_Addr_To = aXY; + MCycle[1] : + begin + ALU_Op = 4'b1011; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + Set_Addr_To = aXY; + TStates = 3'b100; + end + + MCycle[2] : + Write = 1'b1; + default :; + endcase // case(MCycle) + end // case: 8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110 + + endcase // case(IR) + end // case: 2'b01 + + + default : + begin : default_ed_block + + //---------------------------------------------------------------------------- + // + // ED prefixed instructions + // + //---------------------------------------------------------------------------- + + case (IR) + /* + * Undocumented NOP instructions commented out to reduce size of mcode + * + 8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000110,8'b00000111 + ,8'b00001000,8'b00001001,8'b00001010,8'b00001011,8'b00001100,8'b00001101,8'b00001110,8'b00001111 + ,8'b00010000,8'b00010001,8'b00010010,8'b00010011,8'b00010100,8'b00010101,8'b00010110,8'b00010111 + ,8'b00011000,8'b00011001,8'b00011010,8'b00011011,8'b00011100,8'b00011101,8'b00011110,8'b00011111 + ,8'b00100000,8'b00100001,8'b00100010,8'b00100011,8'b00100100,8'b00100101,8'b00100110,8'b00100111 + ,8'b00101000,8'b00101001,8'b00101010,8'b00101011,8'b00101100,8'b00101101,8'b00101110,8'b00101111 + ,8'b00110000,8'b00110001,8'b00110010,8'b00110011,8'b00110100,8'b00110101,8'b00110110,8'b00110111 + ,8'b00111000,8'b00111001,8'b00111010,8'b00111011,8'b00111100,8'b00111101,8'b00111110,8'b00111111 + + + ,8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000110,8'b10000111 + ,8'b10001000,8'b10001001,8'b10001010,8'b10001011,8'b10001100,8'b10001101,8'b10001110,8'b10001111 + ,8'b10010000,8'b10010001,8'b10010010,8'b10010011,8'b10010100,8'b10010101,8'b10010110,8'b10010111 + ,8'b10011000,8'b10011001,8'b10011010,8'b10011011,8'b10011100,8'b10011101,8'b10011110,8'b10011111 + , 8'b10100100,8'b10100101,8'b10100110,8'b10100111 + , 8'b10101100,8'b10101101,8'b10101110,8'b10101111 + , 8'b10110100,8'b10110101,8'b10110110,8'b10110111 + , 8'b10111100,8'b10111101,8'b10111110,8'b10111111 + ,8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000110,8'b11000111 + ,8'b11001000,8'b11001001,8'b11001010,8'b11001011,8'b11001100,8'b11001101,8'b11001110,8'b11001111 + ,8'b11010000,8'b11010001,8'b11010010,8'b11010011,8'b11010100,8'b11010101,8'b11010110,8'b11010111 + ,8'b11011000,8'b11011001,8'b11011010,8'b11011011,8'b11011100,8'b11011101,8'b11011110,8'b11011111 + ,8'b11100000,8'b11100001,8'b11100010,8'b11100011,8'b11100100,8'b11100101,8'b11100110,8'b11100111 + ,8'b11101000,8'b11101001,8'b11101010,8'b11101011,8'b11101100,8'b11101101,8'b11101110,8'b11101111 + ,8'b11110000,8'b11110001,8'b11110010,8'b11110011,8'b11110100,8'b11110101,8'b11110110,8'b11110111 + ,8'b11111000,8'b11111001,8'b11111010,8'b11111011,8'b11111100,8'b11111101,8'b11111110,8'b11111111 : + ; // NOP, undocumented + + 8'b01111110,8'b01111111 : + // NOP, undocumented + ; + */ + + // 8 BIT LOAD GROUP + 8'b01010111 : + begin + // LD A,I + Special_LD = 3'b100; + TStates = 3'b101; + end + + 8'b01011111 : + begin + // LD A,R + Special_LD = 3'b101; + TStates = 3'b101; + end + + 8'b01000111 : + begin + // LD I,A + Special_LD = 3'b110; + TStates = 3'b101; + end + + 8'b01001111 : + begin + // LD R,A + Special_LD = 3'b111; + TStates = 3'b101; + end + + // 16 BIT LOAD GROUP + 8'b01001011,8'b01011011,8'b01101011,8'b01111011 : + begin + // LD dd,(nn) + MCycles = 3'b101; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + + MCycle[2] : + begin + Set_Addr_To = aZI; + Inc_PC = 1'b1; + LDW = 1'b1; + end + + MCycle[3] : + begin + Read_To_Reg = 1'b1; + if (IR[5:4] == 2'b11 ) + begin + Set_BusA_To = 4'b1000; + end + else + begin + Set_BusA_To[2:1] = IR[5:4]; + Set_BusA_To[0] = 1'b1; + end + Inc_WZ = 1'b1; + Set_Addr_To = aZI; + end // case: 4 + + MCycle[4] : + begin + Read_To_Reg = 1'b1; + if (IR[5:4] == 2'b11 ) + begin + Set_BusA_To = 4'b1001; + end + else + begin + Set_BusA_To[2:1] = IR[5:4]; + Set_BusA_To[0] = 1'b0; + end + end // case: 5 + + default :; + endcase // case(MCycle) + end // case: 8'b01001011,8'b01011011,8'b01101011,8'b01111011 + + + 8'b01000011,8'b01010011,8'b01100011,8'b01110011 : + begin + // LD (nn),dd + MCycles = 3'b101; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + + MCycle[2] : + begin + Set_Addr_To = aZI; + Inc_PC = 1'b1; + LDW = 1'b1; + if (IR[5:4] == 2'b11 ) + begin + Set_BusB_To = 4'b1000; + end + else + begin + Set_BusB_To[2:1] = IR[5:4]; + Set_BusB_To[0] = 1'b1; + Set_BusB_To[3] = 1'b0; + end + end // case: 3 + + MCycle[3] : + begin + Inc_WZ = 1'b1; + Set_Addr_To = aZI; + Write = 1'b1; + if (IR[5:4] == 2'b11 ) + begin + Set_BusB_To = 4'b1001; + end + else + begin + Set_BusB_To[2:1] = IR[5:4]; + Set_BusB_To[0] = 1'b0; + Set_BusB_To[3] = 1'b0; + end + end // case: 4 + + MCycle[4] : + begin + Write = 1'b1; + end + + default :; + endcase // case(MCycle) + end // case: 8'b01000011,8'b01010011,8'b01100011,8'b01110011 + + 8'b10100000 , 8'b10101000 , 8'b10110000 , 8'b10111000 : + begin + // LDI, LDD, LDIR, LDDR + MCycles = 3'b100; + case (1'b1) // MCycle + MCycle[0] : + begin + Set_Addr_To = aXY; + IncDec_16 = 4'b1100; // BC + end + + MCycle[1] : + begin + Set_BusB_To = 4'b0110; + Set_BusA_To[2:0] = 3'b111; + ALU_Op = 4'b0000; + Set_Addr_To = aDE; + if (IR[3] == 1'b0 ) + begin + IncDec_16 = 4'b0110; // IX + end + else + begin + IncDec_16 = 4'b1110; + end + end // case: 2 + + MCycle[2] : + begin + I_BT = 1'b1; + TStates = 3'b101; + Write = 1'b1; + if (IR[3] == 1'b0 ) + begin + IncDec_16 = 4'b0101; // DE + end + else + begin + IncDec_16 = 4'b1101; + end + end // case: 3 + + MCycle[3] : + begin + NoRead = 1'b1; + TStates = 3'b101; + end + + default :; + endcase // case(MCycle) + end // case: 8'b10100000 , 8'b10101000 , 8'b10110000 , 8'b10111000 + + 8'b10100001 , 8'b10101001 , 8'b10110001 , 8'b10111001 : + begin + // CPI, CPD, CPIR, CPDR + MCycles = 3'b100; + case (1'b1) // MCycle + MCycle[0] : + begin + Set_Addr_To = aXY; + IncDec_16 = 4'b1100; // BC + end + + MCycle[1] : + begin + Set_BusB_To = 4'b0110; + Set_BusA_To[2:0] = 3'b111; + ALU_Op = 4'b0111; + Save_ALU = 1'b1; + PreserveC = 1'b1; + if (IR[3] == 1'b0 ) + begin + IncDec_16 = 4'b0110; + end + else + begin + IncDec_16 = 4'b1110; + end + end // case: 2 + + MCycle[2] : + begin + NoRead = 1'b1; + I_BC = 1'b1; + TStates = 3'b101; + end + + MCycle[3] : + begin + NoRead = 1'b1; + TStates = 3'b101; + end + + default :; + endcase // case(MCycle) + end // case: 8'b10100001 , 8'b10101001 , 8'b10110001 , 8'b10111001 + + 8'b01000100,8'b01001100,8'b01010100,8'b01011100,8'b01100100,8'b01101100,8'b01110100,8'b01111100 : + begin + // NEG + ALU_Op = 4'b0010; + Set_BusB_To = 4'b0111; + Set_BusA_To = 4'b1010; + Read_To_Acc = 1'b1; + Save_ALU = 1'b1; + end + + 8'b01000110,8'b01001110,8'b01100110,8'b01101110 : + begin + // IM 0 + IMode = 2'b00; + end + + 8'b01010110,8'b01110110 : + // IM 1 + IMode = 2'b01; + + 8'b01011110,8'b01110111 : + // IM 2 + IMode = 2'b10; + + // 16 bit arithmetic + 8'b01001010,8'b01011010,8'b01101010,8'b01111010 : + begin + // ADC HL,ss + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[1] : + begin + NoRead = 1'b1; + ALU_Op = 4'b0001; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + Set_BusA_To[2:0] = 3'b101; + case (IR[5:4]) + 0,1,2 : + begin + Set_BusB_To[2:1] = IR[5:4]; + Set_BusB_To[0] = 1'b1; + end + default : + Set_BusB_To = 4'b1000; + endcase + TStates = 3'b100; + end // case: 2 + + MCycle[2] : + begin + NoRead = 1'b1; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + ALU_Op = 4'b0001; + Set_BusA_To[2:0] = 3'b100; + case (IR[5:4]) + 0,1,2 : + begin + Set_BusB_To[2:1] = IR[5:4]; + Set_BusB_To[0] = 1'b0; + end + default : + Set_BusB_To = 4'b1001; + endcase // case(IR[5:4]) + end // case: 3 + + default :; + endcase // case(MCycle) + end // case: 8'b01001010,8'b01011010,8'b01101010,8'b01111010 + + 8'b01000010,8'b01010010,8'b01100010,8'b01110010 : + begin + // SBC HL,ss + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[1] : + begin + NoRead = 1'b1; + ALU_Op = 4'b0011; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + Set_BusA_To[2:0] = 3'b101; + case (IR[5:4]) + 0,1,2 : + begin + Set_BusB_To[2:1] = IR[5:4]; + Set_BusB_To[0] = 1'b1; + end + default : + Set_BusB_To = 4'b1000; + endcase + TStates = 3'b100; + end // case: 2 + + MCycle[2] : + begin + NoRead = 1'b1; + ALU_Op = 4'b0011; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + Set_BusA_To[2:0] = 3'b100; + case (IR[5:4]) + 0,1,2 : + Set_BusB_To[2:1] = IR[5:4]; + default : + Set_BusB_To = 4'b1001; + endcase + end // case: 3 + + default :; + + endcase // case(MCycle) + end // case: 8'b01000010,8'b01010010,8'b01100010,8'b01110010 + + 8'b01101111 : + begin + // RLD + MCycles = 3'b100; + case (1'b1) // MCycle + MCycle[1] : + begin + NoRead = 1'b1; + Set_Addr_To = aXY; + end + + MCycle[2] : + begin + Read_To_Reg = 1'b1; + Set_BusB_To[2:0] = 3'b110; + Set_BusA_To[2:0] = 3'b111; + ALU_Op = 4'b1101; + TStates = 3'b100; + Set_Addr_To = aXY; + Save_ALU = 1'b1; + end + + MCycle[3] : + begin + I_RLD = 1'b1; + Write = 1'b1; + end + + default :; + endcase // case(MCycle) + end // case: 8'b01101111 + + 8'b01100111 : + begin + // RRD + MCycles = 3'b100; + case (1'b1) // MCycle + MCycle[1] : + Set_Addr_To = aXY; + MCycle[2] : + begin + Read_To_Reg = 1'b1; + Set_BusB_To[2:0] = 3'b110; + Set_BusA_To[2:0] = 3'b111; + ALU_Op = 4'b1110; + TStates = 3'b100; + Set_Addr_To = aXY; + Save_ALU = 1'b1; + end + + MCycle[3] : + begin + I_RRD = 1'b1; + Write = 1'b1; + end + + default :; + endcase // case(MCycle) + end // case: 8'b01100111 + + 8'b01000101,8'b01001101,8'b01010101,8'b01011101,8'b01100101,8'b01101101,8'b01110101,8'b01111101 : + begin + // RETI, RETN + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[0] : + Set_Addr_To = aSP; + + MCycle[1] : + begin + IncDec_16 = 4'b0111; + Set_Addr_To = aSP; + LDZ = 1'b1; + end + + MCycle[2] : + begin + Jump = 1'b1; + IncDec_16 = 4'b0111; + I_RETN = 1'b1; + end + + default :; + endcase // case(MCycle) + end // case: 8'b01000101,8'b01001101,8'b01010101,8'b01011101,8'b01100101,8'b01101101,8'b01110101,8'b01111101 + + 8'b01000000,8'b01001000,8'b01010000,8'b01011000,8'b01100000,8'b01101000,8'b01110000,8'b01111000 : + begin + // IN r,(C) + MCycles = 3'b010; + case (1'b1) // MCycle + MCycle[0] : + Set_Addr_To = aBC; + + MCycle[1] : + begin + IORQ = 1'b1; + if (IR[5:3] != 3'b110 ) + begin + Read_To_Reg = 1'b1; + Set_BusA_To[2:0] = IR[5:3]; + end + I_INRC = 1'b1; + end + + default :; + endcase // case(MCycle) + end // case: 8'b01000000,8'b01001000,8'b01010000,8'b01011000,8'b01100000,8'b01101000,8'b01110000,8'b01111000 + + 8'b01000001,8'b01001001,8'b01010001,8'b01011001,8'b01100001,8'b01101001,8'b01110001,8'b01111001 : + begin + // OUT (C),r + // OUT (C),0 + MCycles = 3'b010; + case (1'b1) // MCycle + MCycle[0] : + begin + Set_Addr_To = aBC; + Set_BusB_To[2:0] = IR[5:3]; + if (IR[5:3] == 3'b110 ) + begin + Set_BusB_To[3] = 1'b1; + end + end + + MCycle[1] : + begin + Write = 1'b1; + IORQ = 1'b1; + end + + default :; + endcase // case(MCycle) + end // case: 8'b01000001,8'b01001001,8'b01010001,8'b01011001,8'b01100001,8'b01101001,8'b01110001,8'b01111001 + + 8'b10100010 , 8'b10101010 , 8'b10110010 , 8'b10111010 : + begin + // INI, IND, INIR, INDR + MCycles = 3'b100; + case (1'b1) // MCycle + MCycle[0] : + begin + Set_Addr_To = aBC; + Set_BusB_To = 4'b1010; + Set_BusA_To = 4'b0000; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + ALU_Op = 4'b0010; + end + + MCycle[1] : + begin + IORQ = 1'b1; + Set_BusB_To = 4'b0110; + Set_Addr_To = aXY; + end + + MCycle[2] : + begin + if (IR[3] == 1'b0 ) + begin + IncDec_16 = 4'b0110; + end + else + begin + IncDec_16 = 4'b1110; + end + TStates = 3'b100; + Write = 1'b1; + I_BTR = 1'b1; + end // case: 3 + + MCycle[3] : + begin + NoRead = 1'b1; + TStates = 3'b101; + end + + default :; + endcase // case(MCycle) + end // case: 8'b10100010 , 8'b10101010 , 8'b10110010 , 8'b10111010 + + 8'b10100011 , 8'b10101011 , 8'b10110011 , 8'b10111011 : + begin + // OUTI, OUTD, OTIR, OTDR + MCycles = 3'b100; + case (1'b1) // MCycle + MCycle[0] : + begin + TStates = 3'b101; + Set_Addr_To = aXY; + Set_BusB_To = 4'b1010; + Set_BusA_To = 4'b0000; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + ALU_Op = 4'b0010; + end + + MCycle[1] : + begin + Set_BusB_To = 4'b0110; + Set_Addr_To = aBC; + if (IR[3] == 1'b0 ) + begin + IncDec_16 = 4'b0110; + end + else + begin + IncDec_16 = 4'b1110; + end + end + + MCycle[2] : + begin + if (IR[3] == 1'b0 ) + begin + IncDec_16 = 4'b0010; + end + else + begin + IncDec_16 = 4'b1010; + end + IORQ = 1'b1; + Write = 1'b1; + I_BTR = 1'b1; + end // case: 3 + + MCycle[3] : + begin + NoRead = 1'b1; + TStates = 3'b101; + end + + default :; + endcase // case(MCycle) + end // case: 8'b10100011 , 8'b10101011 , 8'b10110011 , 8'b10111011 + + endcase // case(IR) + end // block: default_ed_block + endcase // case(ISet) + + if (Mode == 1 ) + begin + if (MCycle[0] ) + begin + //TStates = 3'b100; + end + else + begin + TStates = 3'b011; + end + end + + if (Mode == 3 ) + begin + if (MCycle[0] ) + begin + //TStates = 3'b100; + end + else + begin + TStates = 3'b100; + end + end + + if (Mode < 2 ) + begin + if (MCycle[5] ) + begin + Inc_PC = 1'b1; + if (Mode == 1 ) + begin + Set_Addr_To = aXY; + TStates = 3'b100; + Set_BusB_To[2:0] = SSS; + Set_BusB_To[3] = 1'b0; + end + if (IR == 8'b00110110 || IR == 8'b11001011 ) + begin + Set_Addr_To = aNone; + end + end + if (MCycle[6] ) + begin + if (Mode == 0 ) + begin + TStates = 3'b101; + end + if (ISet != 2'b01 ) + begin + Set_Addr_To = aXY; + end + Set_BusB_To[2:0] = SSS; + Set_BusB_To[3] = 1'b0; + if (IR == 8'b00110110 || ISet == 2'b01 ) + begin + // LD (HL),n + Inc_PC = 1'b1; + end + else + begin + NoRead = 1'b1; + end + end + end // if (Mode < 2 ) + + end // always @ (IR, ISet, MCycle, F, NMICycle, IntCycle) + + // synopsys dc_script_begin + // set_attribute current_design "revision" "$Id: tv80_mcode.v,v 1.6 2005/12/13 19:17:09 ghutchis Exp $" -type string -quiet + // synopsys dc_script_end +endmodule // T80_MCode diff --git a/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/TV80/tv80_reg.v b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/TV80/tv80_reg.v new file mode 100644 index 00000000..8218407b --- /dev/null +++ b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/TV80/tv80_reg.v @@ -0,0 +1,71 @@ +// +// TV80 8-Bit Microprocessor Core +// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org) +// +// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +module tv80_reg (/*AUTOARG*/ + // Outputs + DOBH, DOAL, DOCL, DOBL, DOCH, DOAH, + // Inputs + AddrC, AddrA, AddrB, DIH, DIL, clk, CEN, WEH, WEL + ); + input [2:0] AddrC; + output [7:0] DOBH; + input [2:0] AddrA; + input [2:0] AddrB; + input [7:0] DIH; + output [7:0] DOAL; + output [7:0] DOCL; + input [7:0] DIL; + output [7:0] DOBL; + output [7:0] DOCH; + output [7:0] DOAH; + input clk, CEN, WEH, WEL; + + reg [7:0] RegsH [0:7]; + reg [7:0] RegsL [0:7]; + + always @(posedge clk) + begin + if (CEN) + begin + if (WEH) RegsH[AddrA] <= DIH; + if (WEL) RegsL[AddrA] <= DIL; + end + end + + assign DOAH = RegsH[AddrA]; + assign DOAL = RegsL[AddrA]; + assign DOBH = RegsH[AddrB]; + assign DOBL = RegsL[AddrB]; + assign DOCH = RegsH[AddrC]; + assign DOCL = RegsL[AddrC]; + + // break out ram bits for waveform debug + wire [7:0] H = RegsH[2]; + wire [7:0] L = RegsL[2]; + +// synopsys dc_script_begin +// set_attribute current_design "revision" "$Id: tv80_reg.v,v 1.1 2004/05/16 17:39:57 ghutchis Exp $" -type string -quiet +// synopsys dc_script_end +endmodule + diff --git a/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/TV80/tv80s.v b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/TV80/tv80s.v new file mode 100644 index 00000000..34269bc7 --- /dev/null +++ b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/TV80/tv80s.v @@ -0,0 +1,164 @@ +// +// TV80 8-Bit Microprocessor Core +// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org) +// +// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +//`define TV80_REFRESH + +module tv80s (/*AUTOARG*/ + // Outputs + m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n, A, do, + // Inputs + reset_n, clk, wait_n, int_n, nmi_n, busrq_n, di + ); + + parameter Mode = 0; // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + parameter T2Write = 1; // 0 => wr_n active in T3, /=0 => wr_n active in T2 + parameter IOWait = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle + + + input reset_n; + input clk; + input wait_n; + input int_n; + input nmi_n; + input busrq_n; + output m1_n; + output mreq_n; + output iorq_n; + output rd_n; + output wr_n; + output rfsh_n; + output halt_n; + output busak_n; + output [15:0] A; + input [7:0] di; + output [7:0] do; + + reg mreq_n; + reg iorq_n; + reg rd_n; + reg wr_n; + + wire cen; + wire intcycle_n; + wire no_read; + wire write; + wire iorq; + reg [7:0] di_reg; + wire [6:0] mcycle; + wire [6:0] tstate; + + assign cen = 1; + + tv80_core #(Mode, IOWait) i_tv80_core + ( + .cen (cen), + .m1_n (m1_n), + .iorq (iorq), + .no_read (no_read), + .write (write), + .rfsh_n (rfsh_n), + .halt_n (halt_n), + .wait_n (wait_n), + .int_n (int_n), + .nmi_n (nmi_n), + .reset_n (reset_n), + .busrq_n (busrq_n), + .busak_n (busak_n), + .clk (clk), + .IntE (), + .stop (), + .A (A), + .dinst (di), + .di (di_reg), + .do (do), + .mc (mcycle), + .ts (tstate), + .intcycle_n (intcycle_n) + ); + + always @(posedge clk) + begin + if (!reset_n) + begin + rd_n <= #1 1'b1; + wr_n <= #1 1'b1; + iorq_n <= #1 1'b1; + mreq_n <= #1 1'b1; + di_reg <= #1 0; + end + else + begin + rd_n <= #1 1'b1; + wr_n <= #1 1'b1; + iorq_n <= #1 1'b1; + mreq_n <= #1 1'b1; + if (mcycle[0]) + begin + if (tstate[1] || (tstate[2] && wait_n == 1'b0)) + begin + rd_n <= #1 ~ intcycle_n; + mreq_n <= #1 ~ intcycle_n; + iorq_n <= #1 intcycle_n; + end + `ifdef TV80_REFRESH + if (tstate[3]) + mreq_n <= #1 1'b0; + `endif + end // if (mcycle[0]) + else + begin + if ((tstate[1] || (tstate[2] && wait_n == 1'b0)) && no_read == 1'b0 && write == 1'b0) + begin + rd_n <= #1 1'b0; + iorq_n <= #1 ~ iorq; + mreq_n <= #1 iorq; + end + if (T2Write == 0) + begin + if (tstate[2] && write == 1'b1) + begin + wr_n <= #1 1'b0; + iorq_n <= #1 ~ iorq; + mreq_n <= #1 iorq; + end + end + else + begin + if ((tstate[1] || (tstate[2] && wait_n == 1'b0)) && write == 1'b1) + begin + wr_n <= #1 1'b0; + iorq_n <= #1 ~ iorq; + mreq_n <= #1 iorq; + end + end // else: !if(T2write == 0) + + end // else: !if(mcycle[0]) + + if (tstate[2] && wait_n == 1'b1) + di_reg <= #1 di; + end // else: !if(!reset_n) + end // always @ (posedge clk or negedge reset_n) + +endmodule // t80s + diff --git a/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/build_id.tcl b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/cpucore.v b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/cpucore.v new file mode 100644 index 00000000..0fe9d063 --- /dev/null +++ b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/cpucore.v @@ -0,0 +1,84 @@ +module CPUCORE +( + input RESET, + input CLK, + input IRQ, + input NMI, + output RD, + output WR, + output [15:0] AD, + input DV, + input [7:0] DI, + input [7:0] IR, + output [7:0] DO +); + +wire [7:0] m_do; +wire [15:0] m_ad; +wire m_irq, m_nmi, m_me, m_ie, m_rd, m_wr; + +wire m_mx = (~m_me); +wire m_mr = (~m_rd) & m_mx; +wire m_mw = (~m_wr) & m_mx; + +wire cs_mrom = ( m_ad[15:14] == 2'b00 ); +wire cs_nodv = cs_mrom; + +wire [7:0] m_di = cs_mrom ? IR : DV ? DI : 8'hFF; + +assign m_irq = ~IRQ; +assign m_nmi = ~NMI; + +tv80s core( + .mreq_n(m_me), + .iorq_n(m_ie), + .rd_n(m_rd), + .wr_n(m_wr), + .A(m_ad), + .do(m_do), + + .reset_n(~RESET), + .clk(CLK), + .wait_n(1'b1), + .int_n(m_irq), + .nmi_n(m_nmi), + .busrq_n(1'b1), + .di(m_di) +); + +assign RD = m_mr & ~cs_nodv; +assign WR = m_mw & ~cs_nodv; +assign AD = m_ad; +assign DO = m_do; + +endmodule + + +//----------------------------------------------- +// NMI Ack Control +//----------------------------------------------- +module CPUNMIACK +( + input RST, + input CL, + input [15:0] AD, + input NMI, + output reg NMIo +); + +reg pNMI = 1'b0; +wire NMIACK = ( AD == 16'h0066 ); +always @( negedge CL or posedge RST ) begin + if (RST) begin + pNMI <= 1'b0; + NMIo <= 1'b0; + end + else begin + if (NMIACK) NMIo <= 0; + else if ((pNMI^NMI) & NMI) NMIo <= 1'b1; + pNMI <= NMI; + end +end + +endmodule + diff --git a/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/dprams.v b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/dprams.v new file mode 100644 index 00000000..a13ac415 --- /dev/null +++ b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/dprams.v @@ -0,0 +1,130 @@ +//-------------------------------------------- +// Dualport RAM modules for FPGA DigDug +// +// Copyright (c) 2017 MiSTer-X +//-------------------------------------------- +module DPR2KV +( + input CL0, + input [10:0] AD0, + input EN0, + input WR0, + input [7:0] DI0, + output [7:0] DO0, + + input CL1, + input [10:0] AD1, + output [7:0] DO1 +); + +DPR2K ram( + CL0, AD0, EN0, WR0, DI0, DO0, + CL1, AD1, 1'b1, 1'b0, 8'h0, DO1 +); + +endmodule + + +module DPR2K +( + input CL0, + input [10:0] AD0, + input EN0, + input WR0, + input [7:0] DI0, + output reg [7:0] DO0, + + input CL1, + input [10:0] AD1, + input EN1, + input WR1, + input [7:0] DI1, + output reg [7:0] DO1 +); + +reg [7:0] mram[0:2047]; + +always @( posedge CL0 ) begin + if (EN0) begin + DO0 <= mram[AD0]; + if (WR0) mram[AD0] <= DI0; + end +end + +always @( posedge CL1 ) begin + if (EN1) begin + DO1 <= mram[AD1]; + if (WR1) mram[AD1] <= DI1; + end +end + +endmodule + + +module LBUF1K +( + input CL0, + input [9:0] AD0, + input WR0, + input [7:0] DI0, + + input CL1, + input [9:0] AD1, + input WR1, + input [7:0] DI1, + output [7:0] DO1 +); + +wire [7:0] non; + +LINEBUF lbuf( + AD0,AD1, + CL0,CL1, + DI0,DI1, + WR0,WR1, + non,DO1 +); + +endmodule + + +module DLROM #(parameter AW,parameter DW) +( + input CL0, + input [(AW-1):0] AD0, + output reg [(DW-1):0] DO0, + + input CL1, + input [(AW-1):0] AD1, + input [(DW-1):0] DI1, + input WE1 +); + +reg [DW:0] core[0:((2**AW)-1)]; + +always @(posedge CL0) DO0 <= core[AD0]; +always @(posedge CL1) if (WE1) core[AD1] <= DI1; + +endmodule + + +module DLROMe #(parameter AW,parameter DW) +( + input RE0, + input CL0, + input [(AW-1):0] AD0, + output reg [(DW-1):0] DO0, + + input CL1, + input [(AW-1):0] AD1, + input [(DW-1):0] DI1, + input WE1 +); + +reg [DW:0] core[0:((2**AW)-1)]; + +always @(posedge CL0) if (RE0) DO0 <= core[AD0]; +always @(posedge CL1) if (WE1) core[AD1] <= DI1; + +endmodule + diff --git a/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/hvgen.v b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/hvgen.v new file mode 100644 index 00000000..481dc9c2 --- /dev/null +++ b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/hvgen.v @@ -0,0 +1,40 @@ +module hvgen +( + output [8:0] HPOS, + output [8:0] VPOS, + input PCLK, + input [11:0] iRGB, + + output reg [11:0] oRGB, + output reg HBLK = 1, + output reg VBLK = 1, + output reg HSYN = 1, + output reg VSYN = 1 +); + +reg [8:0] hcnt = 0; +reg [8:0] vcnt = 0; + +assign HPOS = hcnt; +assign VPOS = vcnt; + +always @(posedge PCLK) begin + case (hcnt) + 289: begin HBLK <= 1; HSYN <= 0; hcnt <= hcnt+1; end + 311: begin HSYN <= 1; hcnt <= hcnt+1; end + 383: begin + HBLK <= 0; HSYN <= 1; hcnt <= 0; + case (vcnt) + 223: begin VBLK <= 1; vcnt <= vcnt+1; end + 226: begin VSYN <= 0; vcnt <= vcnt+1; end + 233: begin VSYN <= 1; vcnt <= vcnt+1; end + 262: begin VBLK <= 0; vcnt <= 0; end + default: vcnt <= vcnt+1; + endcase + end + default: hcnt <= hcnt+1; + endcase + oRGB <= (HBLK|VBLK|(hcnt==0)) ? 12'h0 : iRGB; +end + +endmodule diff --git a/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/pll.qip b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/pll.qip new file mode 100644 index 00000000..afd958be --- /dev/null +++ b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/pll.v b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/pll.v new file mode 100644 index 00000000..1c6a642e --- /dev/null +++ b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/pll.v @@ -0,0 +1,337 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.4 Build 182 03/12/2014 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2014 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + inclk0, + c0, + c1, + locked); + + input inclk0; + output c0; + output c1; + output locked; + + wire [4:0] sub_wire0; + wire sub_wire2; + wire [0:0] sub_wire6 = 1'h0; + wire [0:0] sub_wire3 = sub_wire0[0:0]; + wire [1:1] sub_wire1 = sub_wire0[1:1]; + wire c1 = sub_wire1; + wire locked = sub_wire2; + wire c0 = sub_wire3; + wire sub_wire4 = inclk0; + wire [1:0] sub_wire5 = {sub_wire6, sub_wire4}; + + altpll altpll_component ( + .inclk (sub_wire5), + .clk (sub_wire0), + .locked (sub_wire2), + .activeclock (), + .areset (1'b0), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 1125, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 2048, + altpll_component.clk0_phase_shift = "0", + altpll_component.clk1_divide_by = 25, + altpll_component.clk1_duty_cycle = 50, + altpll_component.clk1_multiply_by = 91, + altpll_component.clk1_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_UNUSED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_USED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "39" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "25" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "49.152000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "98.279999" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "71" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "91" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "49.15200000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "98.30400000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1125" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2048" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "25" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "91" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/136007.109 b/Arcade_MiST/Galaga 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zSji<==JJj!phy?CG~ajw)t)xX18wE_aLZQQV9Q+5AwpGOmif?SnJYW$kV!Re{mS~~ zH`^=^f1hby+OfE)aq*3fHe)kbZobx*hW%aL!llsvG`uo{`$fmpoT%fXV`t7Z oM{dqV%td^3Ivu^Lmb#yI(Ukm9uuf;BIT!zzpZ(W9ZhPtf0w&^C_5c6? literal 0 HcmV?d00001 diff --git a/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/bgchip_rom.vhd b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/bgchip_rom.vhd new file mode 100644 index 00000000..fcb66301 --- /dev/null +++ b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/bgchip_rom.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity bgchip_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of bgchip_rom is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F3",X"F1",X"E1",X"F3",X"F3",X"F1",X"F1",X"F3",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"FF",X"FF",X"EF",X"FF",X"7F",X"FF",X"FF",X"7F",X"FF",X"DF",X"FF",X"FF",X"FF",X"FF",X"7F",X"FF", + X"C3",X"E1",X"E1",X"C3",X"C3",X"E1",X"E1",X"C3",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"68",X"18",X"78",X"18",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"01", + X"78",X"78",X"78",X"69",X"0F",X"0F",X"0F",X"00",X"07",X"07",X"07",X"03",X"03",X"01",X"00",X"00", + X"00",X"00",X"00",X"88",X"00",X"02",X"0A",X"0E",X"00",X"22",X"77",X"FF",X"22",X"27",X"2F",X"2F", + X"0E",X"08",X"0A",X"0A",X"0E",X"0E",X"00",X"00",X"3C",X"3C",X"3C",X"E1",X"E3",X"26",X"22",X"00", + X"00",X"00",X"00",X"00",X"00",X"68",X"18",X"78",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01", + 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X"F0",X"F0",X"0F",X"0F",X"F0",X"F0",X"0F",X"0F",X"F0",X"F0",X"0F",X"0F",X"F0",X"F0",X"0F",X"0F", + X"F0",X"F0",X"0F",X"0F",X"F0",X"F0",X"0F",X"0F",X"F0",X"F0",X"0F",X"0F",X"F0",X"F0",X"0F",X"0F", + X"F0",X"F0",X"0F",X"0F",X"F0",X"F0",X"0F",X"0F",X"F0",X"F0",X"0F",X"0F",X"F0",X"F0",X"0F",X"0F", + X"F0",X"F0",X"0F",X"0F",X"F0",X"F0",X"0F",X"0F",X"F0",X"F0",X"0F",X"0F",X"F0",X"F0",X"0F",X"0F", + X"F0",X"F0",X"0F",X"0F",X"F0",X"F0",X"0F",X"0F",X"B0",X"F0",X"0F",X"0F",X"F0",X"F0",X"0F",X"0F"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/bgclut_rom.vhd b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/bgclut_rom.vhd new file mode 100644 index 00000000..261b1934 --- /dev/null +++ b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/bgclut_rom.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity bgclut_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of bgclut_rom is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"06",X"08",X"01",X"00",X"02",X"08",X"0A",X"06",X"01",X"01",X"03",X"01",X"03",X"03",X"05", + X"03",X"05",X"05",X"07",X"02",X"06",X"08",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"09",X"08",X"0B",X"00",X"02",X"08",X"0A",X"09",X"0B",X"0C",X"0E",X"0C",X"0E",X"09",X"01", + X"09",X"01",X"07",X"03",X"02",X"06",X"08",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"09",X"08",X"0B",X"00",X"02",X"08",X"0A",X"09",X"0B",X"0C",X"09",X"0C",X"09",X"00",X"0D", + X"00",X"0D",X"09",X"0C",X"02",X"06",X"08",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"09",X"08",X"0E",X"00",X"02",X"08",X"0A",X"09",X"0E",X"05",X"0E",X"05",X"0E",X"0C",X"0E", + X"0C",X"0E",X"07",X"0E",X"02",X"06",X"08",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/bgscrn_rom.vhd b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/bgscrn_rom.vhd new file mode 100644 index 00000000..2de4e04c --- /dev/null +++ b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/bgscrn_rom.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity bgscrn_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of bgscrn_rom is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"10",X"11",X"10",X"11", + X"10",X"11",X"10",X"11",X"10",X"11",X"10",X"11",X"10",X"11",X"10",X"11",X"10",X"11",X"01",X"01", + X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"12",X"13",X"12",X"13", + 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/b dd1.15 + dd1.14 + dd1.13 + dd1.12 spchip +make_vhdl_prom.exe spchip spchip_rom.vhd + +make_vhdl_prom.exe dd1.11 bgchip_rom.vhd + +make_vhdl_prom.exe dd1.10b bgscrn_rom.vhd + +make_vhdl_prom.exe 136007.113 palette_rom.vhd +make_vhdl_prom.exe 136007.111 spclut_rom.vhd +make_vhdl_prom.exe 136007.112 bgclut_rom.vhd + +make_vhdl_prom.exe 136007.110 wave_rom.vhd +pause diff --git a/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/build_fpga_image2.bat b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/build_fpga_image2.bat new file mode 100644 index 00000000..621b1852 --- /dev/null +++ b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/build_fpga_image2.bat @@ -0,0 +1,24 @@ + +copy /b dd1.1 + dd1.2 + dd1.3 + dd1.4b cpu0 +make_vhdl_prom.exe cpu0 cpu0_rom.vhd + +copy /b dd1.5b + dd1.6b cpu1 +make_vhdl_prom.exe cpu1 cpu1_rom.vhd + +make_vhdl_prom.exe dd1.7 cpu2_rom.vhd + +make_vhdl_prom.exe dd1.9 fgchip_rom.vhd + +copy /b dd1.15 + dd1.14 + dd1.13 + dd1.12 spchip +make_vhdl_prom.exe spchip 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Hardware/DigDug_MiST/rtl/roms/fgchip_rom.vhd b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/fgchip_rom.vhd new file mode 100644 index 00000000..5ccebb1a --- /dev/null +++ b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/fgchip_rom.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity fgchip_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of fgchip_rom is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"60",X"F0",X"F8",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"F8",X"F0",X"80",X"00", + X"00",X"66",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"99",X"00", + X"00",X"06",X"0F",X"1F",X"3F",X"3F",X"3F",X"3F",X"3F",X"3F",X"3F",X"3F",X"1F",X"0F",X"01",X"00", + X"FC",X"FE",X"FE",X"FC",X"F8",X"F0",X"00",X"00",X"7F",X"3F",X"3F",X"3F",X"1F",X"0F",X"00",X"00", + X"FC",X"FE",X"FE",X"FC",X"FC",X"FE",X"FE",X"FC",X"7F",X"3F",X"3F",X"7F",X"7F",X"3F",X"3F",X"7F", + X"00",X"00",X"F0",X"F8",X"FC",X"FE",X"FE",X"FC",X"00",X"00",X"0F",X"1F",X"3F",X"7F",X"7F",X"3F", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"01",X"03",X"03",X"01",X"01",X"03",X"03",X"01", + X"00",X"00",X"00",X"00",X"00",X"00",X"66",X"FF",X"FF",X"66",X"00",X"00",X"00",X"00",X"00",X"00", + X"1C",X"3E",X"43",X"41",X"61",X"3E",X"1C",X"00",X"40",X"40",X"7F",X"7F",X"42",X"40",X"00",X"00", + X"46",X"4F",X"5D",X"59",X"79",X"73",X"62",X"00",X"31",X"7B",X"4F",X"4D",X"49",X"61",X"20",X"00", + X"10",X"7F",X"7F",X"13",X"16",X"1C",X"18",X"00",X"38",X"7D",X"45",X"45",X"45",X"67",X"27",X"00", + X"30",X"79",X"49",X"49",X"4B",X"7E",X"3C",X"00",X"03",X"07",X"0D",X"79",X"71",X"03",X"03",X"00", + X"30",X"76",X"59",X"59",X"4D",X"4F",X"36",X"00",X"1E",X"3F",X"69",X"49",X"49",X"4F",X"06",X"00", + X"7C",X"7E",X"13",X"11",X"13",X"7E",X"7C",X"00",X"36",X"7F",X"49",X"49",X"49",X"7F",X"7F",X"00", + X"22",X"63",X"41",X"41",X"63",X"3E",X"1C",X"00",X"1C",X"3E",X"63",X"41",X"41",X"7F",X"7F",X"00", + X"41",X"49",X"49",X"49",X"49",X"7F",X"7F",X"00",X"01",X"09",X"09",X"09",X"09",X"7F",X"7F",X"00", + X"79",X"79",X"49",X"41",X"63",X"3E",X"1C",X"00",X"7F",X"7F",X"08",X"08",X"08",X"7F",X"7F",X"00", + X"41",X"41",X"7F",X"7F",X"41",X"41",X"00",X"00",X"3F",X"7F",X"40",X"40",X"40",X"60",X"20",X"00", + X"41",X"63",X"76",X"3C",X"18",X"7F",X"7F",X"00",X"40",X"40",X"40",X"40",X"7F",X"7F",X"00",X"00", + X"7F",X"7F",X"0E",X"1C",X"0E",X"7F",X"7F",X"00",X"7F",X"7F",X"38",X"1C",X"0E",X"7F",X"7F",X"00", + X"3E",X"7F",X"41",X"41",X"41",X"7F",X"3E",X"00",X"0E",X"1F",X"11",X"11",X"11",X"7F",X"7F",X"00", + X"5E",X"3F",X"71",X"51",X"41",X"7F",X"3E",X"00",X"4E",X"6F",X"79",X"31",X"11",X"7F",X"7F",X"00", + X"30",X"7A",X"4B",X"49",X"49",X"6F",X"26",X"00",X"01",X"01",X"7F",X"7F",X"01",X"01",X"00",X"00", + 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X"00",X"C0",X"E0",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/make_vhdl_prom.exe b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/make_vhdl_prom.exe new file mode 100644 index 0000000000000000000000000000000000000000..1e5618bf9417eaeb90556e3021a78e9860a815e8 GIT binary patch literal 119861 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a/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/spchip_rom.vhd b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/spchip_rom.vhd new file mode 100644 index 00000000..91ca59d9 --- /dev/null +++ b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/spchip_rom.vhd @@ -0,0 +1,1046 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity spchip_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of spchip_rom is + type rom is array(0 to 16383) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"01",X"03",X"07",X"03",X"01",X"00",X"70",X"10",X"30",X"70",X"0F",X"70",X"30", + X"00",X"B0",X"80",X"F0",X"FE",X"FF",X"F1",X"F1",X"00",X"C0",X"C0",X"C0",X"80",X"0E",X"C8",X"88", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"77",X"AA",X"AA",X"F0",X"30",X"00",X"00",X"00", + X"FE",X"FF",X"FF",X"F0",X"F0",X"F0",X"E0",X"00",X"E0",X"E0",X"E0",X"E0",X"C0",X"80",X"00",X"00", + X"00",X"00",X"00",X"01",X"03",X"07",X"03",X"01",X"00",X"10",X"00",X"00",X"10",X"0F",X"10",X"30", + X"00",X"E0",X"60",X"F0",X"FE",X"FF",X"F1",X"F1",X"00",X"00",X"00",X"80",X"C0",X"0E",X"C8",X"88", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"77",X"AA",X"AA",X"F0",X"30",X"00",X"00",X"00", + X"FE",X"FF",X"FF",X"F0",X"F0",X"F0",X"E0",X"00",X"E0",X"E0",X"E0",X"E0",X"C0",X"80",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"10",X"00",X"00",X"00",X"00",X"E6",X"91",X"F7",X"91", + X"00",X"02",X"07",X"0F",X"02",X"52",X"D2",X"D2",X"00",X"00",X"00",X"08",X"00",X"20",X"A0",X"E0", + X"70",X"70",X"70",X"30",X"30",X"10",X"00",X"00",X"F7",X"F7",X"F7",X"F6",X"F0",X"F0",X"F0",X"00", + X"F3",X"F3",X"F3",X"FE",X"DE",X"42",X"02",X"00",X"E0",X"80",X"A0",X"A0",X"E0",X"E0",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"10",X"00",X"00",X"00",X"00",X"E6",X"91",X"F7",X"91", + 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X"00",X"00",X"0C",X"0E",X"1E",X"0D",X"0B",X"8F",X"00",X"00",X"00",X"00",X"C0",X"38",X"0C",X"0C", + X"07",X"07",X"07",X"03",X"00",X"00",X"00",X"00",X"FF",X"3F",X"1B",X"17",X"0F",X"0F",X"07",X"00", + X"EF",X"8F",X"0B",X"0D",X"0E",X"0E",X"0C",X"00",X"0C",X"0C",X"0C",X"08",X"00",X"00",X"00",X"00", + X"00",X"30",X"70",X"80",X"00",X"80",X"40",X"30",X"00",X"C0",X"E0",X"E0",X"60",X"20",X"10",X"10", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"10",X"30",X"30",X"70",X"40",X"00",X"E0",X"40",X"C0",X"80",X"80",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"33",X"77",X"77",X"00",X"00",X"77",X"FF",X"FF",X"67",X"AB",X"CF", + X"00",X"00",X"CC",X"EE",X"FE",X"DD",X"BB",X"7F",X"00",X"00",X"00",X"00",X"E0",X"98",X"CC",X"CC", + X"77",X"77",X"77",X"33",X"00",X"00",X"00",X"00",X"0F",X"CF",X"AB",X"67",X"FF",X"FF",X"77",X"00", + X"1F",X"7F",X"BB",X"DD",X"EE",X"EE",X"CC",X"00",X"CC",X"CC",X"CC",X"88",X"00",X"00",X"00",X"00", + X"00",X"30",X"70",X"F0",X"00",X"80",X"40",X"30",X"00",X"C0",X"E0",X"E0",X"E0",X"60",X"10",X"10", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"30",X"70",X"70",X"E0",X"00",X"F0",X"20",X"E0",X"C0",X"C0",X"80",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/spclut_rom.vhd b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/spclut_rom.vhd new file mode 100644 index 00000000..75033912 --- /dev/null +++ b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/spclut_rom.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity spclut_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of spclut_rom is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"0F",X"01",X"05",X"0C",X"0F",X"01",X"06",X"05",X"0F",X"01",X"03",X"05",X"0F",X"00",X"06",X"05", + X"0F",X"08",X"09",X"0A",X"0F",X"01",X"06",X"07",X"0F",X"00",X"00",X"00",X"0F",X"01",X"06",X"04", + X"0F",X"01",X"00",X"05",X"0F",X"01",X"0F",X"05",X"0F",X"00",X"04",X"00",X"0F",X"06",X"07",X"0B", + X"0F",X"05",X"03",X"05",X"0F",X"01",X"03",X"08",X"0F",X"01",X"03",X"08",X"0F",X"00",X"03",X"05", + X"0F",X"05",X"03",X"08",X"0F",X"0E",X"0B",X"0D",X"0F",X"05",X"08",X"01",X"0F",X"01",X"05",X"03", + X"0F",X"09",X"07",X"02",X"0F",X"06",X"01",X"0D",X"0F",X"06",X"03",X"09",X"0F",X"06",X"03",X"0B", + X"0F",X"06",X"03",X"01",X"0F",X"07",X"03",X"05",X"0F",X"0D",X"05",X"01",X"0F",X"0D",X"05",X"03", + X"0F",X"04",X"03",X"07",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/wave_rom.vhd b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/wave_rom.vhd new file mode 100644 index 00000000..62066094 --- /dev/null +++ b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/roms/wave_rom.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity wave_rom is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of wave_rom is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"07",X"09",X"0A",X"0B",X"0C",X"0D",X"0D",X"0E",X"0E",X"0E",X"0D",X"0D",X"0C",X"0B",X"0A",X"09", + X"07",X"05",X"04",X"03",X"02",X"01",X"01",X"00",X"00",X"00",X"01",X"01",X"02",X"03",X"04",X"05", + X"07",X"09",X"0A",X"0B",X"07",X"0D",X"0D",X"07",X"0E",X"07",X"0D",X"0D",X"07",X"0B",X"0A",X"09", + X"07",X"05",X"07",X"03",X"07",X"01",X"07",X"00",X"07",X"00",X"07",X"01",X"07",X"03",X"07",X"05", + X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"0B",X"0D",X"0E",X"0D",X"0C",X"0A",X"08",X"08",X"08",X"0A",X"0C",X"0D",X"0E",X"0D",X"0B",X"08", + X"04",X"02",X"01",X"02",X"03",X"05",X"07",X"07",X"07",X"05",X"03",X"02",X"01",X"02",X"04",X"07", + X"07",X"0A",X"0C",X"0D",X"0E",X"0D",X"0C",X"0A",X"07",X"04",X"02",X"01",X"00",X"01",X"02",X"04", + X"07",X"0B",X"0D",X"0E",X"0D",X"0B",X"07",X"03",X"01",X"00",X"01",X"03",X"07",X"0E",X"07",X"00", + X"07",X"0E",X"0C",X"09",X"0C",X"0E",X"0A",X"07",X"0C",X"0F",X"0D",X"08",X"0A",X"0B",X"07",X"02", + X"08",X"0D",X"09",X"04",X"05",X"07",X"02",X"00",X"03",X"08",X"05",X"01",X"03",X"06",X"03",X"01", + X"07",X"08",X"0A",X"0C",X"0E",X"0D",X"0C",X"0C",X"0B",X"0A",X"08",X"07",X"05",X"06",X"07",X"08", + X"08",X"09",X"0A",X"0B",X"09",X"08",X"06",X"05",X"04",X"04",X"03",X"02",X"04",X"06",X"08",X"09", + X"0A",X"0C",X"0C",X"0A",X"07",X"07",X"08",X"0B",X"0D",X"0E",X"0D",X"0A",X"06",X"05",X"05",X"07", + X"09",X"09",X"08",X"04",X"01",X"00",X"01",X"03",X"06",X"07",X"07",X"04",X"02",X"02",X"04",X"07"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/wsg.v b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/wsg.v new file mode 100644 index 00000000..1b023f45 --- /dev/null +++ b/Arcade_MiST/Galaga Hardware/DigDug_MiST/rtl/wsg.v @@ -0,0 +1,249 @@ +//-------------------------------------------- +// Wave-base Sound Generator (3ch) +// +// Copyright (c) 2017 MiSTer-X +//-------------------------------------------- +module WSG_3CH +( + input CLK48M, + input RESET, + + input CPUCLK, + input [4:0] ADRS, + input [3:0] DATA, + input WR, + + output WROMCLK, + output [7:0] WROMADR, + input [3:0] WROMDAT, + + output PCMCLK, + output [7:0] PCMOUT +); + +wire WSGCLKx4; +WSGCLKGEN cgen( CLK48M, WSGCLKx4 ); + +wire [2:0] W0, W1, W2; +wire [3:0] V0, V1, V2; +wire [19:0] F0; +wire [15:0] F1, F2; + +WSGREGS regs +( + RESET, + CPUCLK, ADRS, WR, DATA, + + W0, W1, W2, + V0, V1, V2, + F0, F1, F2 +); + +WSGCORE core +( + RESET, WSGCLKx4, + WROMCLK, WROMADR, WROMDAT, + + W0, W1, W2, + V0, V1, V2, + F0, F1, F2, + + PCMCLK, PCMOUT +); + +endmodule + + +module WSGREGS +( + input RESET, + input CPUCLK, + input [4:0] ADRS, + input WR, + input [3:0] DATA, + + output reg [2:0] W0, + output reg [2:0] W1, + output reg [2:0] W2, + + output reg [3:0] V0, + output reg [3:0] V1, + output reg [3:0] V2, + + output reg [19:0] F0, + output reg [15:0] F1, + output reg [15:0] F2 +); + +always @ ( posedge CPUCLK or posedge RESET ) begin + + if ( RESET ) begin + + W0 <= 0; + W1 <= 0; + W2 <= 0; + + F0 <= 0; + F1 <= 0; + F2 <= 0; + + V0 <= 0; + V1 <= 0; + V2 <= 0; + + end + else begin + + if ( WR ) case ( ADRS ) + + 5'h05: W0 <= DATA[2:0]; + 5'h0A: W1 <= DATA[2:0]; + 5'h0F: W2 <= DATA[2:0]; + + 5'h15: V0 <= DATA; + 5'h1A: V1 <= DATA; + 5'h1F: V2 <= DATA; + + 5'h10: F0[3:0] <= DATA; + 5'h11: F0[7:4] <= DATA; + 5'h12: F0[11:8] <= DATA; + 5'h13: F0[15:12] <= DATA; + 5'h14: F0[19:16] <= DATA; + + 5'h16: F1[3:0] <= DATA; + 5'h17: F1[7:4] <= DATA; + 5'h18: F1[11:8] <= DATA; + 5'h19: F1[15:12] <= DATA; + + 5'h1B: F2[3:0] <= DATA; + 5'h1C: F2[7:4] <= DATA; + 5'h1D: F2[11:8] <= DATA; + 5'h1E: F2[15:12] <= DATA; + + default:; + + endcase + + end + +end + +endmodule + + +module WSGCORE +( + input RESET, + input WSGCLKx4, + + output WROMCLK, + output [7:0] WROMADR, + input [3:0] WROMDAT, + + input [2:0] W0, + input [2:0] W1, + input [2:0] W2, + + input [3:0] V0, + input [3:0] V1, + input [3:0] V2, + + input [19:0] F0, + input [15:0] F1, + input [15:0] F2, + + output reg outclk, + output reg [7:0] sndout +); + +reg [7:0] waveadr, cc1, cc2; + +reg [19:0] c0; +reg [15:0] c1, c2; + +reg [3:0] wavevol; +wire [7:0] waveout = wavevol * WROMDAT; + +reg [9:0] sndmix; +wire [10:0] sndmixdown = { 1'b0, sndmix }; + +reg [1:0] phase; +always @ ( posedge WSGCLKx4 or posedge RESET ) begin + + if ( RESET ) begin + phase <= 0; + sndout <= 0; + outclk <= 0; + cc1 <= 0; + cc2 <= 0; + end + else begin + + case ( phase ) + + 0: begin + sndout <= ( sndmixdown[9:2] | {8{sndmixdown[10]}} ); + + cc1 <= {W1,c1[15:11]}; + cc2 <= {W2,c2[15:11]}; + + sndmix <= 0; + waveadr <= {W0,c0[19:15]}; + wavevol <= (F0!=0) ? V0 : 0; + end + + 1: begin + outclk <= 1'b1; + sndmix <= sndmix + waveout; + + waveadr <= cc1; + wavevol <= (F1!=0) ? V1 : 0; + end + + 2: begin + sndmix <= sndmix + waveout; + + waveadr <= cc2; + wavevol <= (F2!=0) ? V2 : 0; + end + + 3: begin + outclk <= 0; + sndmix <= sndmix + waveout; + end + + default:; + + endcase + + phase <= phase+1; + + c0 <= c0 + F0; + c1 <= c1 + F1; + c2 <= c2 + F2; + + end + +end + +assign WROMCLK = ~WSGCLKx4; +assign WROMADR = waveadr; + +endmodule + + +/* + Clock Generator + in: 48000000Hz -> out: 96000Hz +*/ +module WSGCLKGEN( input in, output reg out ); +reg [7:0] count; +always @( posedge in ) begin + if (count > 8'd249) begin + count <= count - 8'd249; + out <= ~out; + end + else count <= count + 8'd1; +end +endmodule + diff --git a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/power_surge.vhd b/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/power_surge.vhd index 4a230484..2cad8bca 100644 --- a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/power_surge.vhd +++ b/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/power_surge.vhd @@ -96,8 +96,8 @@ port( roms_addr : out std_logic_vector(14 downto 0); roms_do : in std_logic_vector(7 downto 0); roms_rd : out std_logic; - dip_switch_1 : in std_logic_vector(7 downto 0); -- Coinage_B / Coinage_A - dip_switch_2 : in std_logic_vector(7 downto 0); -- Sound(8)/Difficulty(7-5)/Bonus(4)/Cocktail(3)/lives(2-1) + dip_switch_1 : in std_logic_vector(7 downto 0);--Cabinet Unknown Lives Lives Initial_Energy Unknown Unknown Unknown + dip_switch_2 : in std_logic_vector(7 downto 0);--Stop_at_Junctions, Unknown, Unknown, Cheat, Coin_B Coin_B Coin_A Coin_A start2 : in std_logic; start1 : in std_logic; @@ -343,7 +343,7 @@ spram_addr <= cpu_addr(7 downto 0) when cpu_ena = '1' else "00" & spcnt & pxcnt( wram_we <= '1' when cpu_wr_n = '0' and cpu_ena = '1' and cpu_addr(15 downto 12) = X"A" else '0'; spram1_we <= '1' when cpu_wr_n = '0' and cpu_ena = '1' and cpu_addr(15 downto 12) = X"B" and cpu_addr(10) = '0' else '0'; spram2_we <= '1' when cpu_wr_n = '0' and cpu_ena = '1' and cpu_addr(15 downto 12) = X"B" and cpu_addr(10) = '1' else '0'; -C0xx_we <= '1' when cpu_wr_n = '0' and cpu_ena = '1' and cpu_addr(15 downto 8) = "11000000" else '0'; +C0xx_we <= '1' when cpu_wr_n = '0' and cpu_ena = '1' and cpu_addr(15 downto 8) = "11000000" else '0';-- C3xx_we <= '1' when cpu_wr_n = '0' and cpu_ena = '1' and cpu_addr(15 downto 12) = X"C" and cpu_addr(9 downto 8) = "11" else '0'; process (clock_6) diff --git a/Arcade_MiST/README.txt b/Arcade_MiST/README.txt index 537bd957..96ae6b1a 100644 --- a/Arcade_MiST/README.txt +++ b/Arcade_MiST/README.txt @@ -70,6 +70,7 @@ Aviable Arcade Cores #Konami Classic Pooyan + Power Surge Time Pilot #Midway / Taito 8080 Hardware @@ -82,6 +83,9 @@ Aviable Arcade Cores Space Laser Super Earth Invasion +#Namco Rally X Hardware + Rally X + #Non Arcade 2048 Arkanoid