From 80d874dcceda83796652e85c582e0ffdd033bdc1 Mon Sep 17 00:00:00 2001
From: Marcel <marceljenke@gmail.com>
Date: Sat, 12 Oct 2019 12:32:26 +0200
Subject: [PATCH] Sync

---
 .../Amidar.jpg                                |  Bin
 .../Amidar_MiST/Amidar.qpf                    |    0
 .../Amidar_MiST/Amidar.qsf                    |    0
 .../Amidar_MiST/Amidar.sdc                    |    0
 .../Amidar_MiST/Amidar.srf                    |    0
 .../Amidar_MiST/README.txt                    |    0
 .../Amidar_MiST/Release/Amidar.rbf            |  Bin
 .../Amidar_MiST/clean.bat                     |    0
 .../Amidar_MiST/rtl/Amidar.sv                 |    0
 .../Amidar_MiST/rtl/MULT18X18.vhd             |    0
 .../Amidar_MiST/rtl/ROM/ROM_LUT.vhd           |    0
 .../Amidar_MiST/rtl/ROM/ROM_OBJ_0.vhd         |    0
 .../Amidar_MiST/rtl/ROM/ROM_OBJ_1.vhd         |    0
 .../Amidar_MiST/rtl/ROM/ROM_PGM.vhd           |    0
 .../Amidar_MiST/rtl/ROM/ROM_SND_0.vhd         |    0
 .../Amidar_MiST/rtl/ROM/ROM_SND_1.vhd         |    0
 .../Amidar_MiST/rtl/ROM/ROM_SND_2.vhd         |    0
 .../Amidar_MiST/rtl/YM2149_linmix_sep.vhd     |    0
 .../Amidar_MiST/rtl/build_id.tcl              |    0
 .../Amidar_MiST/rtl/cpu/T80.vhd               |    0
 .../Amidar_MiST/rtl/cpu/T80_ALU.vhd           |    0
 .../Amidar_MiST/rtl/cpu/T80_MCode.vhd         |    0
 .../Amidar_MiST/rtl/cpu/T80_Pack.vhd          |    0
 .../Amidar_MiST/rtl/cpu/T80_Reg.vhd           |    0
 .../Amidar_MiST/rtl/cpu/T80sed.vhd            |    0
 .../Amidar_MiST/rtl/dac.vhd                   |    0
 .../Amidar_MiST/rtl/dpram.vhd                 |    0
 .../Amidar_MiST/rtl/i82c55.vhd                |    0
 .../Amidar_MiST/rtl/pll.qip                   |    0
 .../Amidar_MiST/rtl/pll.v                     |    0
 .../Amidar_MiST/rtl/scramble.vhd              |    0
 .../Amidar_MiST/rtl/scramble_audio.vhd        |    0
 .../Amidar_MiST/rtl/scramble_top.vhd          |    0
 .../Amidar_MiST/rtl/scramble_video.vhd        |    0
 .../Amored Car.jpg                            |  Bin
 .../AmoredCar_MiST/AmoredCar.qpf              |    0
 .../AmoredCar_MiST/AmoredCar.qsf              |    0
 .../AmoredCar_MiST/AmoredCar.sdc              |    0
 .../AmoredCar_MiST/AmoredCar.srf              |    0
 .../AmoredCar_MiST/README.txt                 |    0
 .../AmoredCar_MiST/Release/AmoredCar.rbf      |  Bin
 .../AmoredCar_MiST/clean.bat                  |    0
 .../AmoredCar_MiST/rtl/AmoredCar_Mist.sv      |    0
 .../AmoredCar_MiST/rtl/MULT18X18.vhd          |    0
 .../AmoredCar_MiST/rtl/T80/T80.vhd            |    0
 .../AmoredCar_MiST/rtl/T80/T80_ALU.vhd        |    0
 .../AmoredCar_MiST/rtl/T80/T80_MCode.vhd      |    0
 .../AmoredCar_MiST/rtl/T80/T80_Pack.vhd       |    0
 .../AmoredCar_MiST/rtl/T80/T80_Reg.vhd        |    0
 .../AmoredCar_MiST/rtl/T80/T80sed.vhd         |    0
 .../AmoredCar_MiST/rtl/YM2149_linmix_sep.vhd  |    0
 .../AmoredCar_MiST/rtl/build_id.tcl           |    0
 .../AmoredCar_MiST/rtl/dpram.vhd              |    0
 .../AmoredCar_MiST/rtl/i82c55.vhd             |    0
 .../AmoredCar_MiST/rtl/pll.qip                |    0
 .../AmoredCar_MiST/rtl/pll.v                  |    0
 .../AmoredCar_MiST/rtl/rom/ROM_LUT.vhd        |    0
 .../AmoredCar_MiST/rtl/rom/ROM_OBJ_0.vhd      |    0
 .../AmoredCar_MiST/rtl/rom/ROM_OBJ_1.vhd      |    0
 .../AmoredCar_MiST/rtl/rom/ROM_PGM.vhd        |    0
 .../AmoredCar_MiST/rtl/rom/ROM_SND_0.vhd      |    0
 .../AmoredCar_MiST/rtl/rom/ROM_SND_1.vhd      |    0
 .../AmoredCar_MiST/rtl/scramble.vhd           |    0
 .../AmoredCar_MiST/rtl/scramble_audio.vhd     |    0
 .../AmoredCar_MiST/rtl/scramble_top.vhd       |    0
 .../AmoredCar_MiST/rtl/scramble_video.vhd     |    0
 .../Konami Scramble Hardware/Calipso.jpg      |  Bin 0 -> 31365 bytes
 .../Calipso_MiST}/Calipso.qpf                 |    0
 .../Calipso_MiST}/Calipso.qsf                 |    0
 .../Calipso_MiST}/README.txt                  |    0
 .../Calipso_MiST}/Release/Calipso.rbf         |  Bin
 .../Calipso_MiST}/clean.bat                   |    0
 .../Calipso_MiST}/rtl/Calipso_Mist.sv         |    0
 .../Calipso_MiST}/rtl/MULT18X18.vhd           |    0
 .../Calipso_MiST}/rtl/T80/T80.vhd             |    0
 .../Calipso_MiST}/rtl/T80/T80_ALU.vhd         |    0
 .../Calipso_MiST}/rtl/T80/T80_MCode.vhd       |    0
 .../Calipso_MiST}/rtl/T80/T80_Pack.vhd        |    0
 .../Calipso_MiST}/rtl/T80/T80_Reg.vhd         |    0
 .../Calipso_MiST}/rtl/T80/T80sed.vhd          |    0
 .../Calipso_MiST}/rtl/YM2149_linmix_sep.vhd   |    0
 .../Calipso_MiST}/rtl/build_id.tcl            |    0
 .../Calipso_MiST}/rtl/dpram.vhd               |    0
 .../Calipso_MiST}/rtl/i82c55.vhd              |    0
 .../Calipso_MiST}/rtl/pll.qip                 |    0
 .../Calipso_MiST}/rtl/pll.v                   |    0
 .../Calipso_MiST}/rtl/rom/ROM_LUT.vhd         |    0
 .../Calipso_MiST}/rtl/rom/ROM_OBJ_0.vhd       |    0
 .../Calipso_MiST}/rtl/rom/ROM_OBJ_1.vhd       |    0
 .../Calipso_MiST}/rtl/rom/ROM_PGM.vhd         |    0
 .../Calipso_MiST}/rtl/rom/ROM_SND_0.vhd       |    0
 .../Calipso_MiST}/rtl/rom/ROM_SND_1.vhd       |    0
 .../Calipso_MiST}/rtl/scramble.vhd            |    0
 .../Calipso_MiST}/rtl/scramble_audio.vhd      |    0
 .../Calipso_MiST}/rtl/scramble_top.vhd        |    0
 .../Calipso_MiST}/rtl/scramble_video.vhd      |    0
 .../Frogger.jpg                               |  Bin
 .../Frogger_MiST/Frogger.qpf                  |    0
 .../Frogger_MiST/Frogger.qsf                  |    0
 .../Frogger_MiST/Frogger.sdc                  |    0
 .../Frogger_MiST/Frogger.srf                  |    0
 .../Frogger_MiST/README.txt                   |    0
 .../Frogger_MiST/Release/Frogger.rbf          |  Bin
 .../Frogger_MiST/clean.bat                    |    0
 .../Frogger_MiST/rtl/FroggerMist.sv           |    0
 .../Frogger_MiST/rtl/MULT18X18.vhd            |    0
 .../Frogger_MiST/rtl/ROM/ROM_LUT.vhd          |    0
 .../Frogger_MiST/rtl/ROM/ROM_OBJ_0.vhd        |    0
 .../Frogger_MiST/rtl/ROM/ROM_OBJ_1.vhd        |    0
 .../Frogger_MiST/rtl/ROM/ROM_PGM.vhd          |    0
 .../Frogger_MiST/rtl/ROM/ROM_SND_0.vhd        |    0
 .../Frogger_MiST/rtl/ROM/ROM_SND_1.vhd        |    0
 .../Frogger_MiST/rtl/ROM/ROM_SND_2.vhd        |    0
 .../Frogger_MiST/rtl/ScrambleMist.sv          |    0
 .../Frogger_MiST/rtl/YM2149_linmix_sep.vhd    |    0
 .../Frogger_MiST/rtl/build_id.tcl             |    0
 .../Frogger_MiST/rtl/cpu/T80.vhd              |    0
 .../Frogger_MiST/rtl/cpu/T80_ALU.vhd          |    0
 .../Frogger_MiST/rtl/cpu/T80_MCode.vhd        |    0
 .../Frogger_MiST/rtl/cpu/T80_Pack.vhd         |    0
 .../Frogger_MiST/rtl/cpu/T80_Reg.vhd          |    0
 .../Frogger_MiST/rtl/cpu/T80sed.vhd           |    0
 .../Frogger_MiST/rtl/dac.vhd                  |    0
 .../Frogger_MiST/rtl/dpram.vhd                |    0
 .../Frogger_MiST/rtl/i82c55.vhd               |    0
 .../Frogger_MiST/rtl/pll.qip                  |    0
 .../Frogger_MiST/rtl/pll.v                    |    0
 .../Frogger_MiST/rtl/scramble.vhd             |    0
 .../Frogger_MiST/rtl/scramble_audio.vhd       |    0
 .../Frogger_MiST/rtl/scramble_top.vhd         |    0
 .../Frogger_MiST/rtl/scramble_video.vhd       |    0
 .../MoonWar_MiST/MoonWar.qpf                  |    0
 .../MoonWar_MiST/MoonWar.qsf                  |    0
 .../MoonWar_MiST/MoonWar.sdc                  |    0
 .../MoonWar_MiST/MoonWar.srf                  |    0
 .../MoonWar_MiST/README.txt                   |    0
 .../MoonWar_MiST/Snapshot/MoonWar.rbf         |  Bin
 .../MoonWar_MiST/clean.bat                    |    0
 .../MoonWar_MiST/rtl/MULT18X18.vhd            |    0
 .../MoonWar_MiST/rtl/MoonWar_Mist.sv          |    0
 .../MoonWar_MiST/rtl/T80/T80.vhd              |    0
 .../MoonWar_MiST/rtl/T80/T80_ALU.vhd          |    0
 .../MoonWar_MiST/rtl/T80/T80_MCode.vhd        |    0
 .../MoonWar_MiST/rtl/T80/T80_Pack.vhd         |    0
 .../MoonWar_MiST/rtl/T80/T80_Reg.vhd          |    0
 .../MoonWar_MiST/rtl/T80/T80sed.vhd           |    0
 .../MoonWar_MiST/rtl/YM2149_linmix_sep.vhd    |    0
 .../MoonWar_MiST/rtl/build_id.tcl             |    0
 .../MoonWar_MiST/rtl/dpram.vhd                |    0
 .../MoonWar_MiST/rtl/i82c55.vhd               |    0
 .../MoonWar_MiST/rtl/moonwar_dail.vhd         |    0
 .../MoonWar_MiST/rtl/pll.qip                  |    0
 .../MoonWar_MiST/rtl/pll.v                    |    0
 .../MoonWar_MiST/rtl/rom/ROM_LUT.vhd          |    0
 .../MoonWar_MiST/rtl/rom/ROM_OBJ_0.vhd        |    0
 .../MoonWar_MiST/rtl/rom/ROM_OBJ_1.vhd        |    0
 .../MoonWar_MiST/rtl/rom/ROM_PGM.vhd          |    0
 .../MoonWar_MiST/rtl/rom/ROM_SND_0.vhd        |    0
 .../MoonWar_MiST/rtl/rom/ROM_SND_1.vhd        |    0
 .../MoonWar_MiST/rtl/scramble.vhd             |    0
 .../MoonWar_MiST/rtl/scramble_audio.vhd       |    0
 .../MoonWar_MiST/rtl/scramble_top.vhd         |    0
 .../MoonWar_MiST/rtl/scramble_video.vhd       |    0
 .../Moonwar.jpg                               |  Bin
 .../ReadMe.txt                                |    0
 .../Scramble.jpg                              |  Bin
 .../Scramble_MiST/README.txt                  |    0
 .../Scramble_MiST/Release/Scramble.rbf        |  Bin
 .../Scramble_MiST/Scramble.qpf                |    0
 .../Scramble_MiST/Scramble.qsf                |    0
 .../Scramble_MiST/Scramble.sdc                |    0
 .../Scramble_MiST/Scramble.srf                |    0
 .../Scramble_MiST/clean.bat                   |    0
 .../Scramble_MiST/rtl/MULT18X18.vhd           |    0
 .../Scramble_MiST/rtl/ROM/ROM_LUT.vhd         |    0
 .../Scramble_MiST/rtl/ROM/ROM_OBJ_0.vhd       |    0
 .../Scramble_MiST/rtl/ROM/ROM_OBJ_1.vhd       |    0
 .../Scramble_MiST/rtl/ROM/ROM_PGM.vhd         |    0
 .../Scramble_MiST/rtl/ROM/ROM_SND_0.vhd       |    0
 .../Scramble_MiST/rtl/ROM/ROM_SND_1.vhd       |    0
 .../Scramble_MiST/rtl/ROM/ROM_SND_2.vhd       |    0
 .../Scramble_MiST/rtl/ScrambleMist.sv         |    0
 .../Scramble_MiST/rtl/YM2149_linmix_sep.vhd   |    0
 .../Scramble_MiST/rtl/build_id.tcl            |    0
 .../Scramble_MiST/rtl/cpu/T80.vhd             |    0
 .../Scramble_MiST/rtl/cpu/T80_ALU.vhd         |    0
 .../Scramble_MiST/rtl/cpu/T80_MCode.vhd       |    0
 .../Scramble_MiST/rtl/cpu/T80_Pack.vhd        |    0
 .../Scramble_MiST/rtl/cpu/T80_Reg.vhd         |    0
 .../Scramble_MiST/rtl/cpu/T80sed.vhd          |    0
 .../Scramble_MiST/rtl/dpram.vhd               |    0
 .../Scramble_MiST/rtl/i82c55.vhd              |    0
 .../Scramble_MiST/rtl/pll.qip                 |    0
 .../Scramble_MiST/rtl/pll.v                   |    0
 .../Scramble_MiST/rtl/scramble.vhd            |    0
 .../Scramble_MiST/rtl/scramble_audio.vhd      |    0
 .../Scramble_MiST/rtl/scramble_top.vhd        |    0
 .../Scramble_MiST/rtl/scramble_video.vhd      |    0
 .../Konami Scramble Hardware/Speed Coin.jpg   |  Bin 0 -> 63624 bytes
 .../SpeedCoin_MiST/README.txt                 |   26 +
 .../SpeedCoin_MiST/Release/SpeedCoin.rbf      |  Bin 0 -> 296649 bytes
 .../SpeedCoin_MiST/SpeedCoin.qpf              |   31 +
 .../SpeedCoin_MiST/SpeedCoin.qsf              |  170 ++
 .../SpeedCoin_MiST/SpeedCoin.sdc}             |    0
 .../SpeedCoin_MiST/SpeedCoin.srf}             |    0
 .../SpeedCoin_MiST}/clean.bat                 |    0
 .../SpeedCoin_MiST}/rtl/MULT18X18.vhd         |    0
 .../SpeedCoin_MiST/rtl/SpeedCoin_Mist.sv      |  204 ++
 .../SpeedCoin_MiST}/rtl/T80/T80.vhd           |    0
 .../SpeedCoin_MiST}/rtl/T80/T80_ALU.vhd       |    0
 .../SpeedCoin_MiST}/rtl/T80/T80_MCode.vhd     |    0
 .../SpeedCoin_MiST}/rtl/T80/T80_Pack.vhd      |    0
 .../SpeedCoin_MiST}/rtl/T80/T80_Reg.vhd       |    0
 .../SpeedCoin_MiST}/rtl/T80/T80sed.vhd        |    0
 .../SpeedCoin_MiST}/rtl/YM2149_linmix_sep.vhd |    0
 .../SpeedCoin_MiST}/rtl/build_id.tcl          |    0
 .../SpeedCoin_MiST}/rtl/dpram.vhd             |    0
 .../SpeedCoin_MiST}/rtl/i82c55.vhd            |    0
 .../SpeedCoin_MiST}/rtl/pll.qip               |    0
 .../SpeedCoin_MiST}/rtl/pll.v                 |    0
 .../SpeedCoin_MiST/rtl/rom/ROM_LUT.vhd        |   24 +
 .../SpeedCoin_MiST/rtl/rom/ROM_OBJ_0.vhd      |  150 ++
 .../SpeedCoin_MiST/rtl/rom/ROM_OBJ_1.vhd      |  150 ++
 .../SpeedCoin_MiST/rtl/rom/ROM_PGM.vhd        |  534 +++++
 .../SpeedCoin_MiST/rtl/rom/ROM_SND_0.vhd      |  150 ++
 .../SpeedCoin_MiST/rtl/rom/ROM_SND_1.vhd      |  150 ++
 .../SpeedCoin_MiST/rtl/scramble.vhd           |  471 ++++
 .../SpeedCoin_MiST/rtl/scramble_audio.vhd     |  788 +++++++
 .../SpeedCoin_MiST}/rtl/scramble_top.vhd      |    0
 .../SpeedCoin_MiST}/rtl/scramble_video.vhd    |    0
 .../Super Cobra.jpg                           |  Bin
 .../SuperCobra_MiST/README.txt                |    0
 .../SuperCobra_MiST/Release/SCobra.rbf        |  Bin
 .../SuperCobra_MiST/SCobra.qpf                |    0
 .../SuperCobra_MiST/SCobra.qsf                |    0
 .../SuperCobra_MiST/SCobra.sdc}               |    0
 .../SuperCobra_MiST/SCobra.srf}               |    0
 .../SuperCobra_MiST}/clean.bat                |    0
 .../SuperCobra_MiST}/rtl/MULT18X18.vhd        |    0
 .../SuperCobra_MiST/rtl/SCobra_Mist.sv        |    0
 .../SuperCobra_MiST}/rtl/T80/T80.vhd          |    0
 .../SuperCobra_MiST}/rtl/T80/T80_ALU.vhd      |    0
 .../SuperCobra_MiST}/rtl/T80/T80_MCode.vhd    |    0
 .../SuperCobra_MiST}/rtl/T80/T80_Pack.vhd     |    0
 .../SuperCobra_MiST}/rtl/T80/T80_Reg.vhd      |    0
 .../SuperCobra_MiST}/rtl/T80/T80sed.vhd       |    0
 .../rtl/YM2149_linmix_sep.vhd                 |    0
 .../SuperCobra_MiST}/rtl/build_id.tcl         |    0
 .../SuperCobra_MiST}/rtl/dpram.vhd            |    0
 .../SuperCobra_MiST}/rtl/i82c55.vhd           |    0
 .../SuperCobra_MiST}/rtl/pll.qip              |    0
 .../SuperCobra_MiST}/rtl/pll.v                |    0
 .../SuperCobra_MiST/rtl/rom/ROM_LUT.vhd       |    0
 .../SuperCobra_MiST/rtl/rom/ROM_OBJ_0.vhd     |    0
 .../SuperCobra_MiST/rtl/rom/ROM_OBJ_1.vhd     |    0
 .../SuperCobra_MiST/rtl/rom/ROM_PGM.vhd       |    0
 .../SuperCobra_MiST/rtl/rom/ROM_SND_0.vhd     |    0
 .../SuperCobra_MiST/rtl/rom/ROM_SND_1.vhd     |    0
 .../SuperCobra_MiST/rtl/rom/ROM_SND_2.vhd     |    0
 .../SuperCobra_MiST/rtl/scramble.vhd          |    0
 .../SuperCobra_MiST/rtl/scramble_audio.vhd    |    0
 .../SuperCobra_MiST}/rtl/scramble_top.vhd     |    0
 .../SuperCobra_MiST}/rtl/scramble_video.vhd   |    0
 .../Tazz Mania.jpeg                           |  Bin
 .../TazzMania_MiST/README.txt                 |    0
 .../TazzMania_MiST/Release/TazzMania.rbf      |  Bin
 .../TazzMania_MiST/TazzMania.qpf              |    0
 .../TazzMania_MiST/TazzMania.qsf              |    0
 .../TazzMania_MiST/TazzMania.sdc}             |    0
 .../TazzMania_MiST/TazzMania.srf}             |    0
 .../TazzMania_MiST}/clean.bat                 |    0
 .../TazzMania_MiST}/rtl/MULT18X18.vhd         |    0
 .../TazzMania_MiST/rtl/T80}/T80.vhd           |    0
 .../TazzMania_MiST/rtl/T80}/T80_ALU.vhd       |    0
 .../TazzMania_MiST/rtl/T80}/T80_MCode.vhd     |    0
 .../TazzMania_MiST/rtl/T80}/T80_Pack.vhd      |    0
 .../TazzMania_MiST/rtl/T80}/T80_Reg.vhd       |    0
 .../TazzMania_MiST/rtl/T80}/T80sed.vhd        |    0
 .../TazzMania_MiST/rtl/TazzMania_Mist.sv      |    0
 .../TazzMania_MiST}/rtl/YM2149_linmix_sep.vhd |    0
 .../TazzMania_MiST}/rtl/build_id.tcl          |    0
 .../TazzMania_MiST}/rtl/dpram.vhd             |    0
 .../TazzMania_MiST}/rtl/i82c55.vhd            |    0
 .../TazzMania_MiST}/rtl/pll.qip               |    0
 .../TazzMania_MiST/rtl/pll.v                  |  320 +++
 .../TazzMania_MiST/rtl/rom/ROM_LUT.vhd        |    0
 .../TazzMania_MiST/rtl/rom/ROM_OBJ_0.vhd      |    0
 .../TazzMania_MiST/rtl/rom/ROM_OBJ_1.vhd      |    0
 .../TazzMania_MiST/rtl/rom/ROM_PGM.vhd        |    0
 .../TazzMania_MiST/rtl/rom/ROM_SND.vhd        |    0
 .../TazzMania_MiST/rtl/scramble.vhd           |    0
 .../TazzMania_MiST/rtl/scramble_audio.vhd     |    0
 .../TazzMania_MiST/rtl/scramble_top.vhd       |  154 ++
 .../TazzMania_MiST/rtl/scramble_video.vhd     |  726 ++++++
 .../The End.jpg                               |  Bin
 .../TheEnd_MiST/README.txt                    |    0
 .../TheEnd_MiST/Release/TheEnd.rbf            |  Bin
 .../TheEnd_MiST/TheEnd.qpf                    |    0
 .../TheEnd_MiST/TheEnd.qsf                    |    0
 .../TheEnd_MiST/TheEnd.sdc                    |  126 ++
 .../TheEnd_MiST/TheEnd.srf                    |   51 +
 .../TheEnd_MiST/clean.bat                     |   37 +
 .../TheEnd_MiST/rtl/MULT18X18.vhd             |   53 +
 .../TheEnd_MiST/rtl/ROM/ROM_LUT.vhd           |    0
 .../TheEnd_MiST/rtl/ROM/ROM_OBJ_0.vhd         |    0
 .../TheEnd_MiST/rtl/ROM/ROM_OBJ_1.vhd         |    0
 .../TheEnd_MiST/rtl/ROM/ROM_PGM.vhd           |    0
 .../TheEnd_MiST/rtl/ROM/ROM_SND_0.vhd         |    0
 .../TheEnd_MiST/rtl/ROM/ROM_SND_1.vhd         |    0
 .../TheEnd_MiST/rtl/TheEnd.sv                 |    0
 .../TheEnd_MiST/rtl/YM2149_linmix_sep.vhd     |  574 +++++
 .../TheEnd_MiST/rtl/build_id.tcl              |   35 +
 .../TheEnd_MiST/rtl/cpu/T80.vhd               | 1080 +++++++++
 .../TheEnd_MiST/rtl/cpu/T80_ALU.vhd           |  371 ++++
 .../TheEnd_MiST/rtl/cpu/T80_MCode.vhd         | 1944 +++++++++++++++++
 .../TheEnd_MiST/rtl/cpu/T80_Pack.vhd          |  217 ++
 .../TheEnd_MiST/rtl/cpu/T80_Reg.vhd           |  105 +
 .../TheEnd_MiST/rtl/cpu/T80sed.vhd            |  179 ++
 .../TheEnd_MiST/rtl/dac.vhd                   |    0
 .../TheEnd_MiST/rtl/dpram.vhd                 |   58 +
 .../TheEnd_MiST/rtl/i82c55.vhd                |  686 ++++++
 .../TheEnd_MiST/rtl/osd.v                     |    0
 .../TheEnd_MiST/rtl/pll.qip                   |    4 +
 .../TheEnd_MiST/rtl/pll.v                     |    0
 .../TheEnd_MiST/rtl/scramble.vhd              |    0
 .../TheEnd_MiST/rtl/scramble_audio.vhd        |    0
 .../TheEnd_MiST/rtl/scramble_top.vhd          |    0
 .../TheEnd_MiST/rtl/scramble_video.vhd        |    0
 328 files changed, 9568 insertions(+)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Amidar.jpg (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Amidar_MiST/Amidar.qpf (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Amidar_MiST/Amidar.qsf (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Amidar_MiST/Amidar.sdc (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Amidar_MiST/Amidar.srf (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Amidar_MiST/README.txt (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Amidar_MiST/Release/Amidar.rbf (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Amidar_MiST/clean.bat (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Amidar_MiST/rtl/Amidar.sv (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Amidar_MiST/rtl/MULT18X18.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Amidar_MiST/rtl/ROM/ROM_LUT.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Amidar_MiST/rtl/ROM/ROM_OBJ_0.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Amidar_MiST/rtl/ROM/ROM_OBJ_1.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Amidar_MiST/rtl/ROM/ROM_PGM.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Amidar_MiST/rtl/ROM/ROM_SND_0.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Amidar_MiST/rtl/ROM/ROM_SND_1.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Amidar_MiST/rtl/ROM/ROM_SND_2.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Amidar_MiST/rtl/YM2149_linmix_sep.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Amidar_MiST/rtl/build_id.tcl (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Amidar_MiST/rtl/cpu/T80.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Amidar_MiST/rtl/cpu/T80_ALU.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Amidar_MiST/rtl/cpu/T80_MCode.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Amidar_MiST/rtl/cpu/T80_Pack.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Amidar_MiST/rtl/cpu/T80_Reg.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Amidar_MiST/rtl/cpu/T80sed.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Amidar_MiST/rtl/dac.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Amidar_MiST/rtl/dpram.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Amidar_MiST/rtl/i82c55.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Amidar_MiST/rtl/pll.qip (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Amidar_MiST/rtl/pll.v (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Amidar_MiST/rtl/scramble.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Amidar_MiST/rtl/scramble_audio.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Amidar_MiST/rtl/scramble_top.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Amidar_MiST/rtl/scramble_video.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Amored Car.jpg (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/AmoredCar_MiST/AmoredCar.qpf (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/AmoredCar_MiST/AmoredCar.qsf (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/AmoredCar_MiST/AmoredCar.sdc (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/AmoredCar_MiST/AmoredCar.srf (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/AmoredCar_MiST/README.txt (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/AmoredCar_MiST/Release/AmoredCar.rbf (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/AmoredCar_MiST/clean.bat (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/AmoredCar_MiST/rtl/AmoredCar_Mist.sv (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/AmoredCar_MiST/rtl/MULT18X18.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/AmoredCar_MiST/rtl/T80/T80.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/AmoredCar_MiST/rtl/T80/T80_ALU.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/AmoredCar_MiST/rtl/T80/T80_MCode.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/AmoredCar_MiST/rtl/T80/T80_Pack.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/AmoredCar_MiST/rtl/T80/T80_Reg.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/AmoredCar_MiST/rtl/T80/T80sed.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/AmoredCar_MiST/rtl/YM2149_linmix_sep.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/AmoredCar_MiST/rtl/build_id.tcl (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/AmoredCar_MiST/rtl/dpram.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/AmoredCar_MiST/rtl/i82c55.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/AmoredCar_MiST/rtl/pll.qip (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/AmoredCar_MiST/rtl/pll.v (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/AmoredCar_MiST/rtl/rom/ROM_LUT.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/AmoredCar_MiST/rtl/rom/ROM_OBJ_0.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/AmoredCar_MiST/rtl/rom/ROM_OBJ_1.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/AmoredCar_MiST/rtl/rom/ROM_PGM.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/AmoredCar_MiST/rtl/rom/ROM_SND_0.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/AmoredCar_MiST/rtl/rom/ROM_SND_1.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/AmoredCar_MiST/rtl/scramble.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/AmoredCar_MiST/rtl/scramble_audio.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/AmoredCar_MiST/rtl/scramble_top.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/AmoredCar_MiST/rtl/scramble_video.vhd (100%)
 create mode 100644 Arcade_MiST/Konami Scramble Hardware/Calipso.jpg
 rename Arcade_MiST/{Scramble Hardware/Calypso_MiST => Konami Scramble Hardware/Calipso_MiST}/Calipso.qpf (100%)
 rename Arcade_MiST/{Scramble Hardware/Calypso_MiST => Konami Scramble Hardware/Calipso_MiST}/Calipso.qsf (100%)
 rename Arcade_MiST/{Scramble Hardware/Calypso_MiST => Konami Scramble Hardware/Calipso_MiST}/README.txt (100%)
 rename Arcade_MiST/{Scramble Hardware/Calypso_MiST => Konami Scramble Hardware/Calipso_MiST}/Release/Calipso.rbf (100%)
 rename Arcade_MiST/{Scramble Hardware/Calypso_MiST => Konami Scramble Hardware/Calipso_MiST}/clean.bat (100%)
 rename Arcade_MiST/{Scramble Hardware/Calypso_MiST => Konami Scramble Hardware/Calipso_MiST}/rtl/Calipso_Mist.sv (100%)
 rename Arcade_MiST/{Scramble Hardware/Calypso_MiST => Konami Scramble Hardware/Calipso_MiST}/rtl/MULT18X18.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/Calypso_MiST => Konami Scramble Hardware/Calipso_MiST}/rtl/T80/T80.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/Calypso_MiST => Konami Scramble Hardware/Calipso_MiST}/rtl/T80/T80_ALU.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/Calypso_MiST => Konami Scramble Hardware/Calipso_MiST}/rtl/T80/T80_MCode.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/Calypso_MiST => Konami Scramble Hardware/Calipso_MiST}/rtl/T80/T80_Pack.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/Calypso_MiST => Konami Scramble Hardware/Calipso_MiST}/rtl/T80/T80_Reg.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/Calypso_MiST => Konami Scramble Hardware/Calipso_MiST}/rtl/T80/T80sed.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/Calypso_MiST => Konami Scramble Hardware/Calipso_MiST}/rtl/YM2149_linmix_sep.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/Calypso_MiST => Konami Scramble Hardware/Calipso_MiST}/rtl/build_id.tcl (100%)
 rename Arcade_MiST/{Scramble Hardware/Calypso_MiST => Konami Scramble Hardware/Calipso_MiST}/rtl/dpram.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/Calypso_MiST => Konami Scramble Hardware/Calipso_MiST}/rtl/i82c55.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/Calypso_MiST => Konami Scramble Hardware/Calipso_MiST}/rtl/pll.qip (100%)
 rename Arcade_MiST/{Scramble Hardware/Calypso_MiST => Konami Scramble Hardware/Calipso_MiST}/rtl/pll.v (100%)
 rename Arcade_MiST/{Scramble Hardware/Calypso_MiST => Konami Scramble Hardware/Calipso_MiST}/rtl/rom/ROM_LUT.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/Calypso_MiST => Konami Scramble Hardware/Calipso_MiST}/rtl/rom/ROM_OBJ_0.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/Calypso_MiST => Konami Scramble Hardware/Calipso_MiST}/rtl/rom/ROM_OBJ_1.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/Calypso_MiST => Konami Scramble Hardware/Calipso_MiST}/rtl/rom/ROM_PGM.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/Calypso_MiST => Konami Scramble Hardware/Calipso_MiST}/rtl/rom/ROM_SND_0.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/Calypso_MiST => Konami Scramble Hardware/Calipso_MiST}/rtl/rom/ROM_SND_1.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/Calypso_MiST => Konami Scramble Hardware/Calipso_MiST}/rtl/scramble.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/Calypso_MiST => Konami Scramble Hardware/Calipso_MiST}/rtl/scramble_audio.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/Calypso_MiST => Konami Scramble Hardware/Calipso_MiST}/rtl/scramble_top.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/Calypso_MiST => Konami Scramble Hardware/Calipso_MiST}/rtl/scramble_video.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Frogger.jpg (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Frogger_MiST/Frogger.qpf (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Frogger_MiST/Frogger.qsf (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Frogger_MiST/Frogger.sdc (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Frogger_MiST/Frogger.srf (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Frogger_MiST/README.txt (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Frogger_MiST/Release/Frogger.rbf (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Frogger_MiST/clean.bat (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Frogger_MiST/rtl/FroggerMist.sv (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Frogger_MiST/rtl/MULT18X18.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Frogger_MiST/rtl/ROM/ROM_LUT.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Frogger_MiST/rtl/ROM/ROM_OBJ_0.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Frogger_MiST/rtl/ROM/ROM_OBJ_1.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Frogger_MiST/rtl/ROM/ROM_PGM.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Frogger_MiST/rtl/ROM/ROM_SND_0.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Frogger_MiST/rtl/ROM/ROM_SND_1.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Frogger_MiST/rtl/ROM/ROM_SND_2.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Frogger_MiST/rtl/ScrambleMist.sv (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Frogger_MiST/rtl/YM2149_linmix_sep.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Frogger_MiST/rtl/build_id.tcl (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Frogger_MiST/rtl/cpu/T80.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Frogger_MiST/rtl/cpu/T80_ALU.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Frogger_MiST/rtl/cpu/T80_MCode.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Frogger_MiST/rtl/cpu/T80_Pack.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Frogger_MiST/rtl/cpu/T80_Reg.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Frogger_MiST/rtl/cpu/T80sed.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Frogger_MiST/rtl/dac.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Frogger_MiST/rtl/dpram.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Frogger_MiST/rtl/i82c55.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Frogger_MiST/rtl/pll.qip (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Frogger_MiST/rtl/pll.v (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Frogger_MiST/rtl/scramble.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Frogger_MiST/rtl/scramble_audio.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Frogger_MiST/rtl/scramble_top.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Frogger_MiST/rtl/scramble_video.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/MoonWar_MiST/MoonWar.qpf (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/MoonWar_MiST/MoonWar.qsf (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/MoonWar_MiST/MoonWar.sdc (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/MoonWar_MiST/MoonWar.srf (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/MoonWar_MiST/README.txt (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/MoonWar_MiST/Snapshot/MoonWar.rbf (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/MoonWar_MiST/clean.bat (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/MoonWar_MiST/rtl/MULT18X18.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/MoonWar_MiST/rtl/MoonWar_Mist.sv (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/MoonWar_MiST/rtl/T80/T80.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/MoonWar_MiST/rtl/T80/T80_ALU.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/MoonWar_MiST/rtl/T80/T80_MCode.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/MoonWar_MiST/rtl/T80/T80_Pack.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/MoonWar_MiST/rtl/T80/T80_Reg.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/MoonWar_MiST/rtl/T80/T80sed.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/MoonWar_MiST/rtl/YM2149_linmix_sep.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/MoonWar_MiST/rtl/build_id.tcl (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/MoonWar_MiST/rtl/dpram.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/MoonWar_MiST/rtl/i82c55.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/MoonWar_MiST/rtl/moonwar_dail.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/MoonWar_MiST/rtl/pll.qip (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/MoonWar_MiST/rtl/pll.v (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/MoonWar_MiST/rtl/rom/ROM_LUT.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/MoonWar_MiST/rtl/rom/ROM_OBJ_0.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/MoonWar_MiST/rtl/rom/ROM_OBJ_1.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/MoonWar_MiST/rtl/rom/ROM_PGM.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/MoonWar_MiST/rtl/rom/ROM_SND_0.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/MoonWar_MiST/rtl/rom/ROM_SND_1.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/MoonWar_MiST/rtl/scramble.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/MoonWar_MiST/rtl/scramble_audio.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/MoonWar_MiST/rtl/scramble_top.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/MoonWar_MiST/rtl/scramble_video.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Moonwar.jpg (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/ReadMe.txt (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Scramble.jpg (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Scramble_MiST/README.txt (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Scramble_MiST/Release/Scramble.rbf (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Scramble_MiST/Scramble.qpf (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Scramble_MiST/Scramble.qsf (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Scramble_MiST/Scramble.sdc (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Scramble_MiST/Scramble.srf (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Scramble_MiST/clean.bat (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Scramble_MiST/rtl/MULT18X18.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Scramble_MiST/rtl/ROM/ROM_LUT.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Scramble_MiST/rtl/ROM/ROM_OBJ_0.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Scramble_MiST/rtl/ROM/ROM_OBJ_1.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Scramble_MiST/rtl/ROM/ROM_PGM.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Scramble_MiST/rtl/ROM/ROM_SND_0.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Scramble_MiST/rtl/ROM/ROM_SND_1.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Scramble_MiST/rtl/ROM/ROM_SND_2.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Scramble_MiST/rtl/ScrambleMist.sv (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Scramble_MiST/rtl/YM2149_linmix_sep.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Scramble_MiST/rtl/build_id.tcl (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Scramble_MiST/rtl/cpu/T80.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Scramble_MiST/rtl/cpu/T80_ALU.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Scramble_MiST/rtl/cpu/T80_MCode.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Scramble_MiST/rtl/cpu/T80_Pack.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Scramble_MiST/rtl/cpu/T80_Reg.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Scramble_MiST/rtl/cpu/T80sed.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Scramble_MiST/rtl/dpram.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Scramble_MiST/rtl/i82c55.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Scramble_MiST/rtl/pll.qip (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Scramble_MiST/rtl/pll.v (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Scramble_MiST/rtl/scramble.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Scramble_MiST/rtl/scramble_audio.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Scramble_MiST/rtl/scramble_top.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Scramble_MiST/rtl/scramble_video.vhd (100%)
 create mode 100644 Arcade_MiST/Konami Scramble Hardware/Speed Coin.jpg
 create mode 100644 Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/README.txt
 create mode 100644 Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/Release/SpeedCoin.rbf
 create mode 100644 Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/SpeedCoin.qpf
 create mode 100644 Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/SpeedCoin.qsf
 rename Arcade_MiST/{Scramble Hardware/SuperCobra_MiST/SCobra.sdc => Konami Scramble Hardware/SpeedCoin_MiST/SpeedCoin.sdc} (100%)
 rename Arcade_MiST/{Scramble Hardware/SuperCobra_MiST/SCobra.srf => Konami Scramble Hardware/SpeedCoin_MiST/SpeedCoin.srf} (100%)
 rename Arcade_MiST/{Scramble Hardware/SuperCobra_MiST => Konami Scramble Hardware/SpeedCoin_MiST}/clean.bat (100%)
 rename Arcade_MiST/{Scramble Hardware/SuperCobra_MiST => Konami Scramble Hardware/SpeedCoin_MiST}/rtl/MULT18X18.vhd (100%)
 create mode 100644 Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/SpeedCoin_Mist.sv
 rename Arcade_MiST/{Scramble Hardware/SuperCobra_MiST => Konami Scramble Hardware/SpeedCoin_MiST}/rtl/T80/T80.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/SuperCobra_MiST => Konami Scramble Hardware/SpeedCoin_MiST}/rtl/T80/T80_ALU.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/SuperCobra_MiST => Konami Scramble Hardware/SpeedCoin_MiST}/rtl/T80/T80_MCode.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/SuperCobra_MiST => Konami Scramble Hardware/SpeedCoin_MiST}/rtl/T80/T80_Pack.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/SuperCobra_MiST => Konami Scramble Hardware/SpeedCoin_MiST}/rtl/T80/T80_Reg.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/SuperCobra_MiST => Konami Scramble Hardware/SpeedCoin_MiST}/rtl/T80/T80sed.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/SuperCobra_MiST => Konami Scramble Hardware/SpeedCoin_MiST}/rtl/YM2149_linmix_sep.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/SuperCobra_MiST => Konami Scramble Hardware/SpeedCoin_MiST}/rtl/build_id.tcl (100%)
 rename Arcade_MiST/{Scramble Hardware/SuperCobra_MiST => Konami Scramble Hardware/SpeedCoin_MiST}/rtl/dpram.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/SuperCobra_MiST => Konami Scramble Hardware/SpeedCoin_MiST}/rtl/i82c55.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/SuperCobra_MiST => Konami Scramble Hardware/SpeedCoin_MiST}/rtl/pll.qip (100%)
 rename Arcade_MiST/{Scramble Hardware/SuperCobra_MiST => Konami Scramble Hardware/SpeedCoin_MiST}/rtl/pll.v (100%)
 create mode 100644 Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/rom/ROM_LUT.vhd
 create mode 100644 Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/rom/ROM_OBJ_0.vhd
 create mode 100644 Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/rom/ROM_OBJ_1.vhd
 create mode 100644 Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/rom/ROM_PGM.vhd
 create mode 100644 Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/rom/ROM_SND_0.vhd
 create mode 100644 Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/rom/ROM_SND_1.vhd
 create mode 100644 Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/scramble.vhd
 create mode 100644 Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/scramble_audio.vhd
 rename Arcade_MiST/{Scramble Hardware/SuperCobra_MiST => Konami Scramble Hardware/SpeedCoin_MiST}/rtl/scramble_top.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/SuperCobra_MiST => Konami Scramble Hardware/SpeedCoin_MiST}/rtl/scramble_video.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Super Cobra.jpg (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/SuperCobra_MiST/README.txt (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/SuperCobra_MiST/Release/SCobra.rbf (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/SuperCobra_MiST/SCobra.qpf (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/SuperCobra_MiST/SCobra.qsf (100%)
 rename Arcade_MiST/{Scramble Hardware/TazzMania_MiST/TazzMania.sdc => Konami Scramble Hardware/SuperCobra_MiST/SCobra.sdc} (100%)
 rename Arcade_MiST/{Scramble Hardware/TazzMania_MiST/TazzMania.srf => Konami Scramble Hardware/SuperCobra_MiST/SCobra.srf} (100%)
 rename Arcade_MiST/{Scramble Hardware/TazzMania_MiST => Konami Scramble Hardware/SuperCobra_MiST}/clean.bat (100%)
 rename Arcade_MiST/{Scramble Hardware/TazzMania_MiST => Konami Scramble Hardware/SuperCobra_MiST}/rtl/MULT18X18.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/SuperCobra_MiST/rtl/SCobra_Mist.sv (100%)
 rename Arcade_MiST/{Scramble Hardware/TazzMania_MiST => Konami Scramble Hardware/SuperCobra_MiST}/rtl/T80/T80.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/TazzMania_MiST => Konami Scramble Hardware/SuperCobra_MiST}/rtl/T80/T80_ALU.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/TazzMania_MiST => Konami Scramble Hardware/SuperCobra_MiST}/rtl/T80/T80_MCode.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/TazzMania_MiST => Konami Scramble Hardware/SuperCobra_MiST}/rtl/T80/T80_Pack.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/TazzMania_MiST => Konami Scramble Hardware/SuperCobra_MiST}/rtl/T80/T80_Reg.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/TazzMania_MiST => Konami Scramble Hardware/SuperCobra_MiST}/rtl/T80/T80sed.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/TazzMania_MiST => Konami Scramble Hardware/SuperCobra_MiST}/rtl/YM2149_linmix_sep.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/TazzMania_MiST => Konami Scramble Hardware/SuperCobra_MiST}/rtl/build_id.tcl (100%)
 rename Arcade_MiST/{Scramble Hardware/TazzMania_MiST => Konami Scramble Hardware/SuperCobra_MiST}/rtl/dpram.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/TazzMania_MiST => Konami Scramble Hardware/SuperCobra_MiST}/rtl/i82c55.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/TazzMania_MiST => Konami Scramble Hardware/SuperCobra_MiST}/rtl/pll.qip (100%)
 rename Arcade_MiST/{Scramble Hardware/TazzMania_MiST => Konami Scramble Hardware/SuperCobra_MiST}/rtl/pll.v (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/SuperCobra_MiST/rtl/rom/ROM_LUT.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/SuperCobra_MiST/rtl/rom/ROM_OBJ_0.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/SuperCobra_MiST/rtl/rom/ROM_OBJ_1.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/SuperCobra_MiST/rtl/rom/ROM_PGM.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/SuperCobra_MiST/rtl/rom/ROM_SND_0.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/SuperCobra_MiST/rtl/rom/ROM_SND_1.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/SuperCobra_MiST/rtl/rom/ROM_SND_2.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/SuperCobra_MiST/rtl/scramble.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/SuperCobra_MiST/rtl/scramble_audio.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/TazzMania_MiST => Konami Scramble Hardware/SuperCobra_MiST}/rtl/scramble_top.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/TazzMania_MiST => Konami Scramble Hardware/SuperCobra_MiST}/rtl/scramble_video.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/Tazz Mania.jpeg (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/TazzMania_MiST/README.txt (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/TazzMania_MiST/Release/TazzMania.rbf (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/TazzMania_MiST/TazzMania.qpf (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/TazzMania_MiST/TazzMania.qsf (100%)
 rename Arcade_MiST/{Scramble Hardware/TheEnd_MiST/TheEnd.sdc => Konami Scramble Hardware/TazzMania_MiST/TazzMania.sdc} (100%)
 rename Arcade_MiST/{Scramble Hardware/TheEnd_MiST/TheEnd.srf => Konami Scramble Hardware/TazzMania_MiST/TazzMania.srf} (100%)
 rename Arcade_MiST/{Scramble Hardware/TheEnd_MiST => Konami Scramble Hardware/TazzMania_MiST}/clean.bat (100%)
 rename Arcade_MiST/{Scramble Hardware/TheEnd_MiST => Konami Scramble Hardware/TazzMania_MiST}/rtl/MULT18X18.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/TheEnd_MiST/rtl/cpu => Konami Scramble Hardware/TazzMania_MiST/rtl/T80}/T80.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/TheEnd_MiST/rtl/cpu => Konami Scramble Hardware/TazzMania_MiST/rtl/T80}/T80_ALU.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/TheEnd_MiST/rtl/cpu => Konami Scramble Hardware/TazzMania_MiST/rtl/T80}/T80_MCode.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/TheEnd_MiST/rtl/cpu => Konami Scramble Hardware/TazzMania_MiST/rtl/T80}/T80_Pack.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/TheEnd_MiST/rtl/cpu => Konami Scramble Hardware/TazzMania_MiST/rtl/T80}/T80_Reg.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/TheEnd_MiST/rtl/cpu => Konami Scramble Hardware/TazzMania_MiST/rtl/T80}/T80sed.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/TazzMania_MiST/rtl/TazzMania_Mist.sv (100%)
 rename Arcade_MiST/{Scramble Hardware/TheEnd_MiST => Konami Scramble Hardware/TazzMania_MiST}/rtl/YM2149_linmix_sep.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/TheEnd_MiST => Konami Scramble Hardware/TazzMania_MiST}/rtl/build_id.tcl (100%)
 rename Arcade_MiST/{Scramble Hardware/TheEnd_MiST => Konami Scramble Hardware/TazzMania_MiST}/rtl/dpram.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/TheEnd_MiST => Konami Scramble Hardware/TazzMania_MiST}/rtl/i82c55.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware/TheEnd_MiST => Konami Scramble Hardware/TazzMania_MiST}/rtl/pll.qip (100%)
 create mode 100644 Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/pll.v
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/TazzMania_MiST/rtl/rom/ROM_LUT.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/TazzMania_MiST/rtl/rom/ROM_OBJ_0.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/TazzMania_MiST/rtl/rom/ROM_OBJ_1.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/TazzMania_MiST/rtl/rom/ROM_PGM.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/TazzMania_MiST/rtl/rom/ROM_SND.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/TazzMania_MiST/rtl/scramble.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/TazzMania_MiST/rtl/scramble_audio.vhd (100%)
 create mode 100644 Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/scramble_top.vhd
 create mode 100644 Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/scramble_video.vhd
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/The End.jpg (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/TheEnd_MiST/README.txt (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/TheEnd_MiST/Release/TheEnd.rbf (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/TheEnd_MiST/TheEnd.qpf (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/TheEnd_MiST/TheEnd.qsf (100%)
 create mode 100644 Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/TheEnd.sdc
 create mode 100644 Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/TheEnd.srf
 create mode 100644 Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/clean.bat
 create mode 100644 Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/MULT18X18.vhd
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/TheEnd_MiST/rtl/ROM/ROM_LUT.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/TheEnd_MiST/rtl/ROM/ROM_OBJ_0.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/TheEnd_MiST/rtl/ROM/ROM_OBJ_1.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/TheEnd_MiST/rtl/ROM/ROM_PGM.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/TheEnd_MiST/rtl/ROM/ROM_SND_0.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/TheEnd_MiST/rtl/ROM/ROM_SND_1.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/TheEnd_MiST/rtl/TheEnd.sv (100%)
 create mode 100644 Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/YM2149_linmix_sep.vhd
 create mode 100644 Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/build_id.tcl
 create mode 100644 Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/cpu/T80.vhd
 create mode 100644 Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/cpu/T80_ALU.vhd
 create mode 100644 Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/cpu/T80_MCode.vhd
 create mode 100644 Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/cpu/T80_Pack.vhd
 create mode 100644 Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/cpu/T80_Reg.vhd
 create mode 100644 Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/cpu/T80sed.vhd
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/TheEnd_MiST/rtl/dac.vhd (100%)
 create mode 100644 Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/dpram.vhd
 create mode 100644 Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/i82c55.vhd
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/TheEnd_MiST/rtl/osd.v (100%)
 create mode 100644 Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/pll.qip
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/TheEnd_MiST/rtl/pll.v (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/TheEnd_MiST/rtl/scramble.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/TheEnd_MiST/rtl/scramble_audio.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/TheEnd_MiST/rtl/scramble_top.vhd (100%)
 rename Arcade_MiST/{Scramble Hardware => Konami Scramble Hardware}/TheEnd_MiST/rtl/scramble_video.vhd (100%)

diff --git a/Arcade_MiST/Scramble Hardware/Amidar.jpg b/Arcade_MiST/Konami Scramble Hardware/Amidar.jpg
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Amidar.jpg
rename to Arcade_MiST/Konami Scramble Hardware/Amidar.jpg
diff --git a/Arcade_MiST/Scramble Hardware/Amidar_MiST/Amidar.qpf b/Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/Amidar.qpf
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Amidar_MiST/Amidar.qpf
rename to Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/Amidar.qpf
diff --git a/Arcade_MiST/Scramble Hardware/Amidar_MiST/Amidar.qsf b/Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/Amidar.qsf
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Amidar_MiST/Amidar.qsf
rename to Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/Amidar.qsf
diff --git a/Arcade_MiST/Scramble Hardware/Amidar_MiST/Amidar.sdc b/Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/Amidar.sdc
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Amidar_MiST/Amidar.sdc
rename to Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/Amidar.sdc
diff --git a/Arcade_MiST/Scramble Hardware/Amidar_MiST/Amidar.srf b/Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/Amidar.srf
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Amidar_MiST/Amidar.srf
rename to Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/Amidar.srf
diff --git a/Arcade_MiST/Scramble Hardware/Amidar_MiST/README.txt b/Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/README.txt
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Amidar_MiST/README.txt
rename to Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/README.txt
diff --git a/Arcade_MiST/Scramble Hardware/Amidar_MiST/Release/Amidar.rbf b/Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/Release/Amidar.rbf
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Amidar_MiST/Release/Amidar.rbf
rename to Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/Release/Amidar.rbf
diff --git a/Arcade_MiST/Scramble Hardware/Amidar_MiST/clean.bat b/Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/clean.bat
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Amidar_MiST/clean.bat
rename to Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/clean.bat
diff --git a/Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/Amidar.sv b/Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/Amidar.sv
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/Amidar.sv
rename to Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/Amidar.sv
diff --git a/Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/MULT18X18.vhd b/Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/MULT18X18.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/MULT18X18.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/MULT18X18.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/ROM/ROM_LUT.vhd b/Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/ROM/ROM_LUT.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/ROM/ROM_LUT.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/ROM/ROM_LUT.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/ROM/ROM_OBJ_0.vhd b/Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/ROM/ROM_OBJ_0.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/ROM/ROM_OBJ_0.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/ROM/ROM_OBJ_0.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/ROM/ROM_OBJ_1.vhd b/Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/ROM/ROM_OBJ_1.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/ROM/ROM_OBJ_1.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/ROM/ROM_OBJ_1.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/ROM/ROM_PGM.vhd b/Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/ROM/ROM_PGM.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/ROM/ROM_PGM.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/ROM/ROM_PGM.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/ROM/ROM_SND_0.vhd b/Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/ROM/ROM_SND_0.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/ROM/ROM_SND_0.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/ROM/ROM_SND_0.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/ROM/ROM_SND_1.vhd b/Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/ROM/ROM_SND_1.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/ROM/ROM_SND_1.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/ROM/ROM_SND_1.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/ROM/ROM_SND_2.vhd b/Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/ROM/ROM_SND_2.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/ROM/ROM_SND_2.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/ROM/ROM_SND_2.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/YM2149_linmix_sep.vhd b/Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/YM2149_linmix_sep.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/YM2149_linmix_sep.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/YM2149_linmix_sep.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/build_id.tcl b/Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/build_id.tcl
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/build_id.tcl
rename to Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/build_id.tcl
diff --git a/Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/cpu/T80.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/cpu/T80.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/cpu/T80.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/cpu/T80_ALU.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/cpu/T80_ALU.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/cpu/T80_ALU.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/cpu/T80_MCode.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/cpu/T80_MCode.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/cpu/T80_MCode.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/cpu/T80_Pack.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/cpu/T80_Pack.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/cpu/T80_Pack.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/cpu/T80_Reg.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/cpu/T80_Reg.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/cpu/T80_Reg.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/cpu/T80sed.vhd b/Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/cpu/T80sed.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/cpu/T80sed.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/cpu/T80sed.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/dac.vhd b/Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/dac.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/dac.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/dac.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/dpram.vhd b/Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/dpram.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/dpram.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/dpram.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/i82c55.vhd b/Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/i82c55.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/i82c55.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/i82c55.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/pll.qip b/Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/pll.qip
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/pll.qip
rename to Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/pll.qip
diff --git a/Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/pll.v b/Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/pll.v
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/pll.v
rename to Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/pll.v
diff --git a/Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/scramble.vhd b/Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/scramble.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/scramble.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/scramble.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/scramble_audio.vhd b/Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/scramble_audio.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/scramble_audio.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/scramble_audio.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/scramble_top.vhd b/Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/scramble_top.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/scramble_top.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/scramble_top.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/scramble_video.vhd b/Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/scramble_video.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Amidar_MiST/rtl/scramble_video.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Amidar_MiST/rtl/scramble_video.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Amored Car.jpg b/Arcade_MiST/Konami Scramble Hardware/Amored Car.jpg
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Amored Car.jpg
rename to Arcade_MiST/Konami Scramble Hardware/Amored Car.jpg
diff --git a/Arcade_MiST/Scramble Hardware/AmoredCar_MiST/AmoredCar.qpf b/Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/AmoredCar.qpf
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/AmoredCar_MiST/AmoredCar.qpf
rename to Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/AmoredCar.qpf
diff --git a/Arcade_MiST/Scramble Hardware/AmoredCar_MiST/AmoredCar.qsf b/Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/AmoredCar.qsf
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/AmoredCar_MiST/AmoredCar.qsf
rename to Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/AmoredCar.qsf
diff --git a/Arcade_MiST/Scramble Hardware/AmoredCar_MiST/AmoredCar.sdc b/Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/AmoredCar.sdc
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/AmoredCar_MiST/AmoredCar.sdc
rename to Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/AmoredCar.sdc
diff --git a/Arcade_MiST/Scramble Hardware/AmoredCar_MiST/AmoredCar.srf b/Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/AmoredCar.srf
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/AmoredCar_MiST/AmoredCar.srf
rename to Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/AmoredCar.srf
diff --git a/Arcade_MiST/Scramble Hardware/AmoredCar_MiST/README.txt b/Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/README.txt
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/AmoredCar_MiST/README.txt
rename to Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/README.txt
diff --git a/Arcade_MiST/Scramble Hardware/AmoredCar_MiST/Release/AmoredCar.rbf b/Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/Release/AmoredCar.rbf
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/AmoredCar_MiST/Release/AmoredCar.rbf
rename to Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/Release/AmoredCar.rbf
diff --git a/Arcade_MiST/Scramble Hardware/AmoredCar_MiST/clean.bat b/Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/clean.bat
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/AmoredCar_MiST/clean.bat
rename to Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/clean.bat
diff --git a/Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/AmoredCar_Mist.sv b/Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/AmoredCar_Mist.sv
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/AmoredCar_Mist.sv
rename to Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/AmoredCar_Mist.sv
diff --git a/Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/MULT18X18.vhd b/Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/MULT18X18.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/MULT18X18.vhd
rename to Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/MULT18X18.vhd
diff --git a/Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/T80/T80.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/T80/T80.vhd
rename to Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/T80/T80.vhd
diff --git a/Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/T80/T80_ALU.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/T80/T80_ALU.vhd
rename to Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/T80/T80_ALU.vhd
diff --git a/Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/T80/T80_MCode.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/T80/T80_MCode.vhd
rename to Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/T80/T80_MCode.vhd
diff --git a/Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/T80/T80_Pack.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/T80/T80_Pack.vhd
rename to Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/T80/T80_Pack.vhd
diff --git a/Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/T80/T80_Reg.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/T80/T80_Reg.vhd
rename to Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/T80/T80_Reg.vhd
diff --git a/Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/T80/T80sed.vhd b/Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/T80/T80sed.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/T80/T80sed.vhd
rename to Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/T80/T80sed.vhd
diff --git a/Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/YM2149_linmix_sep.vhd b/Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/YM2149_linmix_sep.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/YM2149_linmix_sep.vhd
rename to Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/YM2149_linmix_sep.vhd
diff --git a/Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/build_id.tcl b/Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/build_id.tcl
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/build_id.tcl
rename to Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/build_id.tcl
diff --git a/Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/dpram.vhd b/Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/dpram.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/dpram.vhd
rename to Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/dpram.vhd
diff --git a/Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/i82c55.vhd b/Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/i82c55.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/i82c55.vhd
rename to Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/i82c55.vhd
diff --git a/Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/pll.qip b/Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/pll.qip
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/pll.qip
rename to Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/pll.qip
diff --git a/Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/pll.v b/Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/pll.v
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/pll.v
rename to Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/pll.v
diff --git a/Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/rom/ROM_LUT.vhd b/Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/rom/ROM_LUT.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/rom/ROM_LUT.vhd
rename to Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/rom/ROM_LUT.vhd
diff --git a/Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/rom/ROM_OBJ_0.vhd b/Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/rom/ROM_OBJ_0.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/rom/ROM_OBJ_0.vhd
rename to Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/rom/ROM_OBJ_0.vhd
diff --git a/Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/rom/ROM_OBJ_1.vhd b/Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/rom/ROM_OBJ_1.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/rom/ROM_OBJ_1.vhd
rename to Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/rom/ROM_OBJ_1.vhd
diff --git a/Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/rom/ROM_PGM.vhd b/Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/rom/ROM_PGM.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/rom/ROM_PGM.vhd
rename to Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/rom/ROM_PGM.vhd
diff --git a/Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/rom/ROM_SND_0.vhd b/Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/rom/ROM_SND_0.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/rom/ROM_SND_0.vhd
rename to Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/rom/ROM_SND_0.vhd
diff --git a/Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/rom/ROM_SND_1.vhd b/Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/rom/ROM_SND_1.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/rom/ROM_SND_1.vhd
rename to Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/rom/ROM_SND_1.vhd
diff --git a/Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/scramble.vhd b/Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/scramble.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/scramble.vhd
rename to Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/scramble.vhd
diff --git a/Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/scramble_audio.vhd b/Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/scramble_audio.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/scramble_audio.vhd
rename to Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/scramble_audio.vhd
diff --git a/Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/scramble_top.vhd b/Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/scramble_top.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/scramble_top.vhd
rename to Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/scramble_top.vhd
diff --git a/Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/scramble_video.vhd b/Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/scramble_video.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/AmoredCar_MiST/rtl/scramble_video.vhd
rename to Arcade_MiST/Konami Scramble Hardware/AmoredCar_MiST/rtl/scramble_video.vhd
diff --git a/Arcade_MiST/Konami Scramble Hardware/Calipso.jpg b/Arcade_MiST/Konami Scramble Hardware/Calipso.jpg
new file mode 100644
index 0000000000000000000000000000000000000000..6d657aff9a6185a4377fb5596d427dbcacff7201
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literal 0
HcmV?d00001

diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/Calipso.qpf b/Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/Calipso.qpf
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Calypso_MiST/Calipso.qpf
rename to Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/Calipso.qpf
diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/Calipso.qsf b/Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/Calipso.qsf
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Calypso_MiST/Calipso.qsf
rename to Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/Calipso.qsf
diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/README.txt b/Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/README.txt
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Calypso_MiST/README.txt
rename to Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/README.txt
diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/Release/Calipso.rbf b/Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/Release/Calipso.rbf
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Calypso_MiST/Release/Calipso.rbf
rename to Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/Release/Calipso.rbf
diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/clean.bat b/Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/clean.bat
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Calypso_MiST/clean.bat
rename to Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/clean.bat
diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/Calipso_Mist.sv b/Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/Calipso_Mist.sv
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/Calipso_Mist.sv
rename to Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/Calipso_Mist.sv
diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/MULT18X18.vhd b/Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/MULT18X18.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/MULT18X18.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/MULT18X18.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/T80/T80.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/T80/T80.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/T80/T80.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/T80/T80_ALU.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/T80/T80_ALU.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/T80/T80_ALU.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/T80/T80_MCode.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/T80/T80_MCode.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/T80/T80_MCode.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/T80/T80_Pack.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/T80/T80_Pack.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/T80/T80_Pack.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/T80/T80_Reg.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/T80/T80_Reg.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/T80/T80_Reg.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/T80/T80sed.vhd b/Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/T80/T80sed.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/T80/T80sed.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/T80/T80sed.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/YM2149_linmix_sep.vhd b/Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/YM2149_linmix_sep.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/YM2149_linmix_sep.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/YM2149_linmix_sep.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/build_id.tcl b/Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/build_id.tcl
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/build_id.tcl
rename to Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/build_id.tcl
diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/dpram.vhd b/Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/dpram.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/dpram.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/dpram.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/i82c55.vhd b/Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/i82c55.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/i82c55.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/i82c55.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/pll.qip b/Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/pll.qip
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/pll.qip
rename to Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/pll.qip
diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/pll.v b/Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/pll.v
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/pll.v
rename to Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/pll.v
diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/rom/ROM_LUT.vhd b/Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/rom/ROM_LUT.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/rom/ROM_LUT.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/rom/ROM_LUT.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/rom/ROM_OBJ_0.vhd b/Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/rom/ROM_OBJ_0.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/rom/ROM_OBJ_0.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/rom/ROM_OBJ_0.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/rom/ROM_OBJ_1.vhd b/Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/rom/ROM_OBJ_1.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/rom/ROM_OBJ_1.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/rom/ROM_OBJ_1.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/rom/ROM_PGM.vhd b/Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/rom/ROM_PGM.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/rom/ROM_PGM.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/rom/ROM_PGM.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/rom/ROM_SND_0.vhd b/Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/rom/ROM_SND_0.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/rom/ROM_SND_0.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/rom/ROM_SND_0.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/rom/ROM_SND_1.vhd b/Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/rom/ROM_SND_1.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/rom/ROM_SND_1.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/rom/ROM_SND_1.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/scramble.vhd b/Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/scramble.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/scramble.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/scramble.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/scramble_audio.vhd b/Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/scramble_audio.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/scramble_audio.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/scramble_audio.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/scramble_top.vhd b/Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/scramble_top.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/scramble_top.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/scramble_top.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/scramble_video.vhd b/Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/scramble_video.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Calypso_MiST/rtl/scramble_video.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Calipso_MiST/rtl/scramble_video.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Frogger.jpg b/Arcade_MiST/Konami Scramble Hardware/Frogger.jpg
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Frogger.jpg
rename to Arcade_MiST/Konami Scramble Hardware/Frogger.jpg
diff --git a/Arcade_MiST/Scramble Hardware/Frogger_MiST/Frogger.qpf b/Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/Frogger.qpf
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Frogger_MiST/Frogger.qpf
rename to Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/Frogger.qpf
diff --git a/Arcade_MiST/Scramble Hardware/Frogger_MiST/Frogger.qsf b/Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/Frogger.qsf
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Frogger_MiST/Frogger.qsf
rename to Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/Frogger.qsf
diff --git a/Arcade_MiST/Scramble Hardware/Frogger_MiST/Frogger.sdc b/Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/Frogger.sdc
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Frogger_MiST/Frogger.sdc
rename to Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/Frogger.sdc
diff --git a/Arcade_MiST/Scramble Hardware/Frogger_MiST/Frogger.srf b/Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/Frogger.srf
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Frogger_MiST/Frogger.srf
rename to Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/Frogger.srf
diff --git a/Arcade_MiST/Scramble Hardware/Frogger_MiST/README.txt b/Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/README.txt
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Frogger_MiST/README.txt
rename to Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/README.txt
diff --git a/Arcade_MiST/Scramble Hardware/Frogger_MiST/Release/Frogger.rbf b/Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/Release/Frogger.rbf
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Frogger_MiST/Release/Frogger.rbf
rename to Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/Release/Frogger.rbf
diff --git a/Arcade_MiST/Scramble Hardware/Frogger_MiST/clean.bat b/Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/clean.bat
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Frogger_MiST/clean.bat
rename to Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/clean.bat
diff --git a/Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/FroggerMist.sv b/Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/FroggerMist.sv
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/FroggerMist.sv
rename to Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/FroggerMist.sv
diff --git a/Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/MULT18X18.vhd b/Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/MULT18X18.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/MULT18X18.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/MULT18X18.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_LUT.vhd b/Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_LUT.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_LUT.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_LUT.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_OBJ_0.vhd b/Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_OBJ_0.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_OBJ_0.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_OBJ_0.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_OBJ_1.vhd b/Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_OBJ_1.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_OBJ_1.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_OBJ_1.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_PGM.vhd b/Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_PGM.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_PGM.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_PGM.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_SND_0.vhd b/Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_SND_0.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_SND_0.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_SND_0.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_SND_1.vhd b/Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_SND_1.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_SND_1.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_SND_1.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_SND_2.vhd b/Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_SND_2.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_SND_2.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_SND_2.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/ScrambleMist.sv b/Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/ScrambleMist.sv
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/ScrambleMist.sv
rename to Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/ScrambleMist.sv
diff --git a/Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/YM2149_linmix_sep.vhd b/Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/YM2149_linmix_sep.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/YM2149_linmix_sep.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/YM2149_linmix_sep.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/build_id.tcl b/Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/build_id.tcl
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/build_id.tcl
rename to Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/build_id.tcl
diff --git a/Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/cpu/T80.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/cpu/T80.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/cpu/T80.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/cpu/T80_ALU.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/cpu/T80_ALU.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/cpu/T80_ALU.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/cpu/T80_MCode.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/cpu/T80_MCode.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/cpu/T80_MCode.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/cpu/T80_Pack.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/cpu/T80_Pack.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/cpu/T80_Pack.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/cpu/T80_Reg.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/cpu/T80_Reg.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/cpu/T80_Reg.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/cpu/T80sed.vhd b/Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/cpu/T80sed.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/cpu/T80sed.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/cpu/T80sed.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/dac.vhd b/Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/dac.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/dac.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/dac.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/dpram.vhd b/Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/dpram.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/dpram.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/dpram.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/i82c55.vhd b/Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/i82c55.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/i82c55.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/i82c55.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/pll.qip b/Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/pll.qip
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/pll.qip
rename to Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/pll.qip
diff --git a/Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/pll.v b/Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/pll.v
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/pll.v
rename to Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/pll.v
diff --git a/Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/scramble.vhd b/Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/scramble.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/scramble.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/scramble.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/scramble_audio.vhd b/Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/scramble_audio.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/scramble_audio.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/scramble_audio.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/scramble_top.vhd b/Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/scramble_top.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/scramble_top.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/scramble_top.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/scramble_video.vhd b/Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/scramble_video.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Frogger_MiST/rtl/scramble_video.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Frogger_MiST/rtl/scramble_video.vhd
diff --git a/Arcade_MiST/Scramble Hardware/MoonWar_MiST/MoonWar.qpf b/Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/MoonWar.qpf
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/MoonWar_MiST/MoonWar.qpf
rename to Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/MoonWar.qpf
diff --git a/Arcade_MiST/Scramble Hardware/MoonWar_MiST/MoonWar.qsf b/Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/MoonWar.qsf
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/MoonWar_MiST/MoonWar.qsf
rename to Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/MoonWar.qsf
diff --git a/Arcade_MiST/Scramble Hardware/MoonWar_MiST/MoonWar.sdc b/Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/MoonWar.sdc
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/MoonWar_MiST/MoonWar.sdc
rename to Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/MoonWar.sdc
diff --git a/Arcade_MiST/Scramble Hardware/MoonWar_MiST/MoonWar.srf b/Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/MoonWar.srf
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/MoonWar_MiST/MoonWar.srf
rename to Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/MoonWar.srf
diff --git a/Arcade_MiST/Scramble Hardware/MoonWar_MiST/README.txt b/Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/README.txt
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/MoonWar_MiST/README.txt
rename to Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/README.txt
diff --git a/Arcade_MiST/Scramble Hardware/MoonWar_MiST/Snapshot/MoonWar.rbf b/Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/Snapshot/MoonWar.rbf
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/MoonWar_MiST/Snapshot/MoonWar.rbf
rename to Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/Snapshot/MoonWar.rbf
diff --git a/Arcade_MiST/Scramble Hardware/MoonWar_MiST/clean.bat b/Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/clean.bat
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/MoonWar_MiST/clean.bat
rename to Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/clean.bat
diff --git a/Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/MULT18X18.vhd b/Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/MULT18X18.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/MULT18X18.vhd
rename to Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/MULT18X18.vhd
diff --git a/Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/MoonWar_Mist.sv b/Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/MoonWar_Mist.sv
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/MoonWar_Mist.sv
rename to Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/MoonWar_Mist.sv
diff --git a/Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/T80/T80.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/T80/T80.vhd
rename to Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/T80/T80.vhd
diff --git a/Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/T80/T80_ALU.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/T80/T80_ALU.vhd
rename to Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/T80/T80_ALU.vhd
diff --git a/Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/T80/T80_MCode.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/T80/T80_MCode.vhd
rename to Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/T80/T80_MCode.vhd
diff --git a/Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/T80/T80_Pack.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/T80/T80_Pack.vhd
rename to Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/T80/T80_Pack.vhd
diff --git a/Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/T80/T80_Reg.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/T80/T80_Reg.vhd
rename to Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/T80/T80_Reg.vhd
diff --git a/Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/T80/T80sed.vhd b/Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/T80/T80sed.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/T80/T80sed.vhd
rename to Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/T80/T80sed.vhd
diff --git a/Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/YM2149_linmix_sep.vhd b/Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/YM2149_linmix_sep.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/YM2149_linmix_sep.vhd
rename to Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/YM2149_linmix_sep.vhd
diff --git a/Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/build_id.tcl b/Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/build_id.tcl
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/build_id.tcl
rename to Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/build_id.tcl
diff --git a/Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/dpram.vhd b/Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/dpram.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/dpram.vhd
rename to Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/dpram.vhd
diff --git a/Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/i82c55.vhd b/Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/i82c55.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/i82c55.vhd
rename to Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/i82c55.vhd
diff --git a/Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/moonwar_dail.vhd b/Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/moonwar_dail.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/moonwar_dail.vhd
rename to Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/moonwar_dail.vhd
diff --git a/Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/pll.qip b/Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/pll.qip
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/pll.qip
rename to Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/pll.qip
diff --git a/Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/pll.v b/Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/pll.v
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/pll.v
rename to Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/pll.v
diff --git a/Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/rom/ROM_LUT.vhd b/Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/rom/ROM_LUT.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/rom/ROM_LUT.vhd
rename to Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/rom/ROM_LUT.vhd
diff --git a/Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/rom/ROM_OBJ_0.vhd b/Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/rom/ROM_OBJ_0.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/rom/ROM_OBJ_0.vhd
rename to Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/rom/ROM_OBJ_0.vhd
diff --git a/Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/rom/ROM_OBJ_1.vhd b/Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/rom/ROM_OBJ_1.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/rom/ROM_OBJ_1.vhd
rename to Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/rom/ROM_OBJ_1.vhd
diff --git a/Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/rom/ROM_PGM.vhd b/Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/rom/ROM_PGM.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/rom/ROM_PGM.vhd
rename to Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/rom/ROM_PGM.vhd
diff --git a/Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/rom/ROM_SND_0.vhd b/Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/rom/ROM_SND_0.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/rom/ROM_SND_0.vhd
rename to Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/rom/ROM_SND_0.vhd
diff --git a/Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/rom/ROM_SND_1.vhd b/Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/rom/ROM_SND_1.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/rom/ROM_SND_1.vhd
rename to Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/rom/ROM_SND_1.vhd
diff --git a/Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/scramble.vhd b/Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/scramble.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/scramble.vhd
rename to Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/scramble.vhd
diff --git a/Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/scramble_audio.vhd b/Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/scramble_audio.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/scramble_audio.vhd
rename to Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/scramble_audio.vhd
diff --git a/Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/scramble_top.vhd b/Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/scramble_top.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/scramble_top.vhd
rename to Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/scramble_top.vhd
diff --git a/Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/scramble_video.vhd b/Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/scramble_video.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/MoonWar_MiST/rtl/scramble_video.vhd
rename to Arcade_MiST/Konami Scramble Hardware/MoonWar_MiST/rtl/scramble_video.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Moonwar.jpg b/Arcade_MiST/Konami Scramble Hardware/Moonwar.jpg
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Moonwar.jpg
rename to Arcade_MiST/Konami Scramble Hardware/Moonwar.jpg
diff --git a/Arcade_MiST/Scramble Hardware/ReadMe.txt b/Arcade_MiST/Konami Scramble Hardware/ReadMe.txt
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/ReadMe.txt
rename to Arcade_MiST/Konami Scramble Hardware/ReadMe.txt
diff --git a/Arcade_MiST/Scramble Hardware/Scramble.jpg b/Arcade_MiST/Konami Scramble Hardware/Scramble.jpg
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Scramble.jpg
rename to Arcade_MiST/Konami Scramble Hardware/Scramble.jpg
diff --git a/Arcade_MiST/Scramble Hardware/Scramble_MiST/README.txt b/Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/README.txt
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Scramble_MiST/README.txt
rename to Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/README.txt
diff --git a/Arcade_MiST/Scramble Hardware/Scramble_MiST/Release/Scramble.rbf b/Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/Release/Scramble.rbf
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Scramble_MiST/Release/Scramble.rbf
rename to Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/Release/Scramble.rbf
diff --git a/Arcade_MiST/Scramble Hardware/Scramble_MiST/Scramble.qpf b/Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/Scramble.qpf
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Scramble_MiST/Scramble.qpf
rename to Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/Scramble.qpf
diff --git a/Arcade_MiST/Scramble Hardware/Scramble_MiST/Scramble.qsf b/Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/Scramble.qsf
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Scramble_MiST/Scramble.qsf
rename to Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/Scramble.qsf
diff --git a/Arcade_MiST/Scramble Hardware/Scramble_MiST/Scramble.sdc b/Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/Scramble.sdc
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Scramble_MiST/Scramble.sdc
rename to Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/Scramble.sdc
diff --git a/Arcade_MiST/Scramble Hardware/Scramble_MiST/Scramble.srf b/Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/Scramble.srf
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Scramble_MiST/Scramble.srf
rename to Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/Scramble.srf
diff --git a/Arcade_MiST/Scramble Hardware/Scramble_MiST/clean.bat b/Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/clean.bat
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Scramble_MiST/clean.bat
rename to Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/clean.bat
diff --git a/Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/MULT18X18.vhd b/Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/MULT18X18.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/MULT18X18.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/MULT18X18.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_LUT.vhd b/Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_LUT.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_LUT.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_LUT.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_OBJ_0.vhd b/Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_OBJ_0.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_OBJ_0.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_OBJ_0.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_OBJ_1.vhd b/Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_OBJ_1.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_OBJ_1.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_OBJ_1.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_PGM.vhd b/Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_PGM.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_PGM.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_PGM.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_SND_0.vhd b/Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_SND_0.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_SND_0.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_SND_0.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_SND_1.vhd b/Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_SND_1.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_SND_1.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_SND_1.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_SND_2.vhd b/Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_SND_2.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_SND_2.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_SND_2.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/ScrambleMist.sv b/Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/ScrambleMist.sv
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/ScrambleMist.sv
rename to Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/ScrambleMist.sv
diff --git a/Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/YM2149_linmix_sep.vhd b/Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/YM2149_linmix_sep.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/YM2149_linmix_sep.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/YM2149_linmix_sep.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/build_id.tcl b/Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/build_id.tcl
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/build_id.tcl
rename to Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/build_id.tcl
diff --git a/Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/cpu/T80.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/cpu/T80.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/cpu/T80.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/cpu/T80_ALU.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/cpu/T80_ALU.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/cpu/T80_ALU.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/cpu/T80_MCode.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/cpu/T80_MCode.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/cpu/T80_MCode.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/cpu/T80_Pack.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/cpu/T80_Pack.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/cpu/T80_Pack.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/cpu/T80_Reg.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/cpu/T80_Reg.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/cpu/T80_Reg.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/cpu/T80sed.vhd b/Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/cpu/T80sed.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/cpu/T80sed.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/cpu/T80sed.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/dpram.vhd b/Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/dpram.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/dpram.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/dpram.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/i82c55.vhd b/Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/i82c55.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/i82c55.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/i82c55.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/pll.qip b/Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/pll.qip
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/pll.qip
rename to Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/pll.qip
diff --git a/Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/pll.v b/Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/pll.v
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/pll.v
rename to Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/pll.v
diff --git a/Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/scramble.vhd b/Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/scramble.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/scramble.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/scramble.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/scramble_audio.vhd b/Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/scramble_audio.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/scramble_audio.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/scramble_audio.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/scramble_top.vhd b/Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/scramble_top.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/scramble_top.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/scramble_top.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/scramble_video.vhd b/Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/scramble_video.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Scramble_MiST/rtl/scramble_video.vhd
rename to Arcade_MiST/Konami Scramble Hardware/Scramble_MiST/rtl/scramble_video.vhd
diff --git a/Arcade_MiST/Konami Scramble Hardware/Speed Coin.jpg b/Arcade_MiST/Konami Scramble Hardware/Speed Coin.jpg
new file mode 100644
index 0000000000000000000000000000000000000000..9a8da9d0ce5fa8e6e9be7c7d3fc2cb87b9729b11
GIT binary patch
literal 63624
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zu>tN=-ovB3ciRPE1pw|5+`a98Uikmo?%l`3CwM^kkcgP%?t;2Ufcy9G@b2T|5fI?x
z-(Bs0*AKv_BzXKxK>ooKEek?6D3xGPLf%96H&wr>wf|u_gg&|k6A{zU($O<K=j3|9
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diff --git a/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/README.txt b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/README.txt
new file mode 100644
index 00000000..cf3831a9
--- /dev/null
+++ b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/README.txt	
@@ -0,0 +1,26 @@
+---------------------------------------------------------------------------------
+-- 
+-- Arcade: Speed Coin port to MiST by Gehstock
+-- 10 November 2017
+-- 
+---------------------------------------------------------------------------------
+-- A simulation model of Scramble hardware
+-- Copyright (c) MikeJ - Feb 2007
+---------------------------------------------------------------------------------
+-- 
+-- Only controls and OSD are rotated on Video output.
+-- 
+-- 
+-- Keyboard inputs :
+--
+--   ESC         : Coin
+--   F2          : Start 2 players
+--   F1          : Start 1 player
+--   SPACE       : Fire+Bomb
+
+--   UP,DOWN,LEFT,RIGHT arrows : Movements
+--
+-- Joystick support.
+-- 
+---------------------------------------------------------------------------------
+
diff --git a/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/Release/SpeedCoin.rbf b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/Release/SpeedCoin.rbf
new file mode 100644
index 0000000000000000000000000000000000000000..6d563a308ee1af52632cdb1eb5ce83b87ac6ca34
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diff --git a/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/SpeedCoin.qpf b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/SpeedCoin.qpf
new file mode 100644
index 00000000..8c8b8c2c
--- /dev/null
+++ b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/SpeedCoin.qpf	
@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2017  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel MegaCore Function License Agreement, or other 
+# applicable license agreement, including, without limitation, 
+# that your use is for the sole purpose of programming logic 
+# devices manufactured by Intel and sold by Intel or its 
+# authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition
+# Date created = 04:04:47  October 16, 2017
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "17.0"
+DATE = "04:04:47  October 16, 2017"
+
+# Revisions
+
+PROJECT_REVISION = "SpeedCoin"
diff --git a/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/SpeedCoin.qsf b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/SpeedCoin.qsf
new file mode 100644
index 00000000..2f216238
--- /dev/null
+++ b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/SpeedCoin.qsf	
@@ -0,0 +1,170 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 13:34:18  October 06, 2019
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		SpeedCoin_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30  APRIL 20, 2017"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_54 -to CLOCK_27
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_13 -to CONF_DATA0
+set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+set_global_assignment -name TOP_LEVEL_ENTITY SpeedCoin_Mist
+set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
+set_global_assignment -name ENABLE_NCE_PIN OFF
+set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name GENERATE_RBF_FILE ON
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+
+# Power Estimation Assignments
+# ============================
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# Advanced I/O Timing Assignments
+# ===============================
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+# -------------------------
+# start ENTITY(SCobra_Mist)
+
+	# start DESIGN_PARTITION(Top)
+	# ---------------------------
+
+		# Incremental Compilation Assignments
+		# ===================================
+		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+	# end DESIGN_PARTITION(Top)
+	# -------------------------
+
+# end ENTITY(SCobra_Mist)
+# -----------------------
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/SpeedCoin_Mist.sv
+set_global_assignment -name VHDL_FILE rtl/scramble_top.vhd
+set_global_assignment -name VHDL_FILE rtl/scramble.vhd
+set_global_assignment -name VHDL_FILE rtl/scramble_audio.vhd
+set_global_assignment -name VHDL_FILE rtl/scramble_video.vhd
+set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/ROM_PGM.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/ROM_OBJ_1.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/ROM_OBJ_0.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/ROM_SND_2.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/ROM_SND_1.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/ROM_SND_0.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/ROM_LUT.vhd
+set_global_assignment -name VERILOG_FILE rtl/pll.v
+set_global_assignment -name VHDL_FILE rtl/MULT18X18.vhd
+set_global_assignment -name VHDL_FILE rtl/i82c55.vhd
+set_global_assignment -name VHDL_FILE rtl/dpram.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80sed.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
+set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/SCobra.sdc b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/SpeedCoin.sdc
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/SuperCobra_MiST/SCobra.sdc
rename to Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/SpeedCoin.sdc
diff --git a/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/SCobra.srf b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/SpeedCoin.srf
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/SuperCobra_MiST/SCobra.srf
rename to Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/SpeedCoin.srf
diff --git a/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/clean.bat b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/clean.bat
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/SuperCobra_MiST/clean.bat
rename to Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/clean.bat
diff --git a/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/MULT18X18.vhd b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/MULT18X18.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/MULT18X18.vhd
rename to Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/MULT18X18.vhd
diff --git a/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/SpeedCoin_Mist.sv b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/SpeedCoin_Mist.sv
new file mode 100644
index 00000000..aed1958c
--- /dev/null
+++ b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/SpeedCoin_Mist.sv	
@@ -0,0 +1,204 @@
+//============================================================================
+//  Arcade: Speed Coin
+//
+//  Port to MiSTer
+//  Copyright (C) 2017 Sorgelig
+//
+//  This program is free software; you can redistribute it and/or modify it
+//  under the terms of the GNU General Public License as published by the Free
+//  Software Foundation; either version 2 of the License, or (at your option)
+//  any later version.
+//
+//  This program is distributed in the hope that it will be useful, but WITHOUT
+//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+//  more details.
+//
+//  You should have received a copy of the GNU General Public License along
+//  with this program; if not, write to the Free Software Foundation, Inc.,
+//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+//============================================================================
+
+module SpeedCoin_Mist
+(
+	output        LED,						
+	output  [5:0] VGA_R,
+	output  [5:0] VGA_G,
+	output  [5:0] VGA_B,
+	output        VGA_HS,
+	output        VGA_VS,
+	output        AUDIO_L,
+	output        AUDIO_R,	
+	input         SPI_SCK,
+	output        SPI_DO,
+	input         SPI_DI,
+	input         SPI_SS2,
+	input         SPI_SS3,
+	input         CONF_DATA0,
+	input         CLOCK_27	
+);
+
+`include "rtl\build_id.v"
+
+localparam CONF_STR = {
+	"Speed Coin;;",
+	"O2,Rotate Controls,Off,On;",
+	"O34,Scanlines,Off,25%,50%,75%;",
+	"T6,Reset;",
+	"V,v1.00.",`BUILD_DATE
+};
+
+assign LED = 1;
+assign AUDIO_R = AUDIO_L;
+
+wire clk_sys;
+wire pll_locked;
+pll pll(
+	.inclk0(CLOCK_27),
+	.areset(0),
+	.c0(clk_sys),
+	.locked(pll_locked)
+	);
+
+reg ce_6p, ce_6n, ce_12, ce_1p79;
+always @(negedge clk_sys) begin
+reg [1:0] div = 0;
+reg [3:0] div179 = 0;
+	div <= div + 1'd1;
+	ce_12 <= div[0];
+	ce_6p <= div[0] & ~div[1];
+	ce_6n <= div[0] &  div[1];	
+   ce_1p79 <= 0;
+   div179 <= div179 - 1'd1;
+   if(!div179) begin
+		div179 <= 13;
+		ce_1p79 <= 1;
+   end
+end
+
+wire [31:0] status;
+wire  [1:0] buttons;
+wire  [1:0] switches;
+wire  [7:0] joystick_0;
+wire  [7:0] joystick_1;
+wire        scandoublerD;
+wire        ypbpr;
+wire [10:0] ps2_key;
+wire [9:0] audio;
+wire hs, vs;
+wire blankn = ~(hb | vb);
+wire hb, vb;
+wire [3:0] r,b,g;
+
+scramble_top scramble (
+	.O_VIDEO_R(r),
+	.O_VIDEO_G(g),
+	.O_VIDEO_B(b),
+	.O_HSYNC(hs),
+	.O_VSYNC(vs),
+   .O_HBLANK(hb),
+   .O_VBLANK(vb),
+	.O_AUDIO(audio),
+	.ip_dip_switch({1'b1,1'b1,"00",1'b1}),//Lives, Allow_Continue, coin, coin,Cabinet
+	.ip_1p(~{btn_one_player, m_bomb, m_fire, m_left, m_right, m_up, m_down}),
+   .ip_2p(~{btn_two_players, m_bomb, m_fire, m_left,m_right, m_up, m_down}),
+   .ip_service(1'b1),
+   .ip_coin1(~btn_coin),
+   .ip_coin2(1'b1),
+	.RESET(status[0] | status[6] | buttons[1]),
+	.clk(clk_sys),
+	.ena_12(ce_12),
+	.ena_6(ce_6p),
+	.ena_6b(ce_6n),
+	.ena_1_79(ce_1p79)
+	);
+
+mist_video #(.COLOR_DEPTH(4)) mist_video(
+	.clk_sys(clk_sys),
+	.SPI_SCK(SPI_SCK),
+	.SPI_SS3(SPI_SS3),
+	.SPI_DI(SPI_DI),
+	.R(blankn ? r : 0),
+	.G(blankn ? g : 0),
+	.B(blankn ? b : 0),
+	.HSync(~hs),
+	.VSync(~vs),
+	.VGA_R(VGA_R),
+	.VGA_G(VGA_G),
+	.VGA_B(VGA_B),
+	.VGA_VS(VGA_VS),
+	.VGA_HS(VGA_HS),
+	.rotate({1'b1,status[2]}),
+	.scandoubler_disable(scandoublerD),
+	.scanlines(status[4:3]),
+	.ypbpr(ypbpr)
+	);
+
+user_io #(
+	.STRLEN(($size(CONF_STR)>>3)))
+user_io(
+	.clk_sys        (clk_sys        ),
+	.conf_str       (CONF_STR       ),
+	.SPI_CLK        (SPI_SCK        ),
+	.SPI_SS_IO      (CONF_DATA0     ),
+	.SPI_MISO       (SPI_DO         ),
+	.SPI_MOSI       (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches       (switches       ),
+	.scandoubler_disable (scandoublerD	  ),
+	.ypbpr          (ypbpr          ),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
+	.key_code       (key_code       ),
+	.joystick_0     (joystick_0     ),
+	.joystick_1     (joystick_1     ),
+	.status         (status         )
+	);
+
+dac #(10)dac(
+	.clk_i(clk_sys),
+	.res_n_i(1),
+	.dac_i(audio),
+	.dac_o(AUDIO_L)
+	);
+//											Rotated														Normal
+wire m_up     = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3];
+wire m_down   = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2];
+wire m_left   = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1];
+wire m_right  = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0];
+
+wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
+wire m_bomb   = btn_fire2 | joystick_0[5] | joystick_1[5];
+
+reg btn_one_player = 0;
+reg btn_two_players = 0;
+reg btn_left = 0;
+reg btn_right = 0;
+reg btn_down = 0;
+reg btn_up = 0;
+reg btn_fire1 = 0;
+reg btn_fire2 = 0;
+//reg btn_fire3 = 0;
+reg btn_coin  = 0;
+wire       key_pressed;
+wire [7:0] key_code;
+wire       key_strobe;
+
+always @(posedge clk_sys) begin
+	if(key_strobe) begin
+		case(key_code)
+			'h75: btn_up          <= key_pressed; // up
+			'h72: btn_down        <= key_pressed; // down
+			'h6B: btn_left        <= key_pressed; // left
+			'h74: btn_right       <= key_pressed; // right
+			'h76: btn_coin        <= key_pressed; // ESC
+			'h05: btn_one_player  <= key_pressed; // F1
+			'h06: btn_two_players <= key_pressed; // F2
+//			'h14: btn_fire3       <= key_pressed; // ctrl
+			'h11: btn_fire2       <= key_pressed; // alt
+			'h29: btn_fire1       <= key_pressed; // Space
+		endcase
+	end
+end
+
+endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/T80/T80.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/T80/T80.vhd
rename to Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/T80/T80.vhd
diff --git a/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/T80/T80_ALU.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/T80/T80_ALU.vhd
rename to Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/T80/T80_ALU.vhd
diff --git a/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/T80/T80_MCode.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/T80/T80_MCode.vhd
rename to Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/T80/T80_MCode.vhd
diff --git a/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/T80/T80_Pack.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/T80/T80_Pack.vhd
rename to Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/T80/T80_Pack.vhd
diff --git a/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/T80/T80_Reg.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/T80/T80_Reg.vhd
rename to Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/T80/T80_Reg.vhd
diff --git a/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/T80/T80sed.vhd b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/T80/T80sed.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/T80/T80sed.vhd
rename to Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/T80/T80sed.vhd
diff --git a/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/YM2149_linmix_sep.vhd b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/YM2149_linmix_sep.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/YM2149_linmix_sep.vhd
rename to Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/YM2149_linmix_sep.vhd
diff --git a/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/build_id.tcl b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/build_id.tcl
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/build_id.tcl
rename to Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/build_id.tcl
diff --git a/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/dpram.vhd b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/dpram.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/dpram.vhd
rename to Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/dpram.vhd
diff --git a/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/i82c55.vhd b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/i82c55.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/i82c55.vhd
rename to Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/i82c55.vhd
diff --git a/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/pll.qip b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/pll.qip
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/pll.qip
rename to Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/pll.qip
diff --git a/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/pll.v b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/pll.v
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/pll.v
rename to Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/pll.v
diff --git a/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/rom/ROM_LUT.vhd b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/rom/ROM_LUT.vhd
new file mode 100644
index 00000000..d6a5d87f
--- /dev/null
+++ b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/rom/ROM_LUT.vhd	
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity ROM_LUT is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(4 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of ROM_LUT is
+	type rom is array(0 to  31) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"00",X"6D",X"07",X"3F",X"00",X"29",X"07",X"39",X"00",X"92",X"07",X"DB",X"00",X"0E",X"07",X"2F",
+		X"00",X"C9",X"07",X"F0",X"00",X"A4",X"07",X"FF",X"00",X"84",X"07",X"C7",X"00",X"4B",X"07",X"5F");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/rom/ROM_OBJ_0.vhd b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/rom/ROM_OBJ_0.vhd
new file mode 100644
index 00000000..8ff57d85
--- /dev/null
+++ b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/rom/ROM_OBJ_0.vhd	
@@ -0,0 +1,150 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity ROM_OBJ_0 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(10 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of ROM_OBJ_0 is
+	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"38",X"7C",X"C2",X"82",X"86",X"7C",X"38",X"00",X"02",X"02",X"FE",X"FE",X"42",X"02",X"00",X"00",
+		X"62",X"F2",X"BA",X"9A",X"9E",X"CE",X"46",X"00",X"8C",X"DE",X"F2",X"B2",X"92",X"86",X"04",X"00",
+		X"08",X"FE",X"FE",X"C8",X"68",X"38",X"18",X"00",X"1C",X"BE",X"A2",X"A2",X"A2",X"E6",X"E4",X"00",
+		X"0C",X"9E",X"92",X"92",X"D2",X"7E",X"3C",X"00",X"C0",X"E0",X"B0",X"9E",X"8E",X"C0",X"C0",X"00",
+		X"0C",X"6E",X"9A",X"9A",X"B2",X"F2",X"6C",X"00",X"78",X"FC",X"96",X"92",X"92",X"F2",X"60",X"00",
+		X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"00",X"3C",X"42",X"81",X"A5",X"A5",X"99",X"42",X"3C",
+		X"00",X"00",X"00",X"06",X"06",X"00",X"00",X"00",X"00",X"60",X"F0",X"9A",X"8A",X"C0",X"60",X"00",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"01",X"03",X"07",X"0F",X"1F",X"3F",X"7F",X"FF",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"3E",X"7E",X"C8",X"88",X"C8",X"7E",X"3E",X"00",
+		X"6C",X"FE",X"92",X"92",X"92",X"FE",X"FE",X"00",X"44",X"C6",X"82",X"82",X"C6",X"7C",X"38",X"00",
+		X"38",X"7C",X"C6",X"82",X"82",X"FE",X"FE",X"00",X"82",X"92",X"92",X"92",X"FE",X"FE",X"00",X"00",
+		X"80",X"90",X"90",X"90",X"FE",X"FE",X"00",X"00",X"9E",X"9E",X"92",X"82",X"C6",X"7C",X"38",X"00",
+		X"FE",X"FE",X"10",X"10",X"10",X"FE",X"FE",X"00",X"82",X"82",X"FE",X"FE",X"82",X"82",X"00",X"00",
+		X"FC",X"FE",X"06",X"06",X"06",X"0E",X"0C",X"00",X"82",X"C6",X"6C",X"38",X"18",X"FE",X"FE",X"00",
+		X"02",X"02",X"02",X"02",X"FE",X"FE",X"00",X"00",X"FE",X"FE",X"70",X"38",X"70",X"FE",X"FE",X"00",
+		X"FE",X"FE",X"1C",X"38",X"70",X"FE",X"FE",X"00",X"7C",X"FE",X"82",X"82",X"82",X"FE",X"7C",X"00",
+		X"70",X"F8",X"88",X"88",X"88",X"FE",X"FE",X"00",X"7A",X"FC",X"8E",X"8A",X"82",X"FE",X"7C",X"00",
+		X"62",X"F6",X"8E",X"8C",X"88",X"FE",X"FE",X"00",X"0C",X"5E",X"D2",X"92",X"92",X"F6",X"64",X"00",
+		X"80",X"80",X"FE",X"FE",X"80",X"80",X"00",X"00",X"FC",X"FE",X"02",X"02",X"02",X"FE",X"FC",X"00",
+		X"F0",X"F8",X"1C",X"0E",X"1C",X"F8",X"F0",X"00",X"F8",X"FE",X"1C",X"38",X"1C",X"FE",X"F8",X"00",
+		X"C6",X"EE",X"7C",X"38",X"7C",X"EE",X"C6",X"00",X"C0",X"F0",X"1E",X"1E",X"F0",X"C0",X"00",X"00",
+		X"C2",X"E2",X"F2",X"BA",X"9E",X"8E",X"86",X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",
+		X"70",X"70",X"70",X"70",X"E0",X"E0",X"E0",X"E0",X"38",X"38",X"38",X"38",X"70",X"70",X"70",X"70",
+		X"1C",X"1C",X"1C",X"1C",X"38",X"38",X"38",X"38",X"0E",X"0E",X"0E",X"0E",X"1C",X"1C",X"1C",X"1C",
+		X"07",X"07",X"07",X"07",X"0E",X"0E",X"0E",X"0E",X"03",X"03",X"03",X"03",X"07",X"07",X"07",X"07",
+		X"01",X"01",X"01",X"01",X"03",X"03",X"03",X"03",X"00",X"00",X"00",X"00",X"01",X"01",X"01",X"01",
+		X"80",X"80",X"80",X"80",X"00",X"00",X"00",X"00",X"C0",X"C0",X"C0",X"C0",X"80",X"80",X"80",X"80",
+		X"E0",X"E0",X"E0",X"E0",X"C0",X"C0",X"C0",X"C0",X"70",X"70",X"70",X"70",X"70",X"E0",X"E0",X"E0",
+		X"1C",X"38",X"38",X"38",X"38",X"38",X"38",X"70",X"0E",X"0E",X"0E",X"1C",X"1C",X"1C",X"1C",X"1C",
+		X"07",X"07",X"07",X"07",X"07",X"0E",X"0E",X"0E",X"01",X"03",X"03",X"03",X"03",X"03",X"03",X"07",
+		X"00",X"00",X"00",X"01",X"01",X"01",X"01",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
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+		X"03",X"03",X"07",X"07",X"07",X"07",X"0E",X"0E",X"00",X"00",X"01",X"01",X"01",X"01",X"03",X"03",
+		X"80",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"E0",X"E0",X"C0",X"C0",X"C0",X"C0",X"80",X"80",
+		X"18",X"38",X"38",X"30",X"70",X"70",X"60",X"E0",X"07",X"07",X"06",X"0E",X"0E",X"0C",X"1C",X"1C",
+		X"00",X"00",X"01",X"01",X"01",X"03",X"03",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"E0",X"C0",X"C0",X"C0",X"80",X"80",X"80",X"00",X"E0",X"E0",X"E0",X"E0",X"E0",X"E0",X"E0",X"E0",
+		X"70",X"70",X"70",X"70",X"70",X"70",X"70",X"70",X"70",X"70",X"70",X"70",X"70",X"70",X"70",X"70",
+		X"38",X"38",X"38",X"38",X"38",X"38",X"38",X"38",X"38",X"38",X"38",X"38",X"38",X"38",X"38",X"38",
+		X"1C",X"1C",X"1C",X"1C",X"1C",X"1C",X"1C",X"1C",X"1C",X"1C",X"1C",X"1C",X"1C",X"1C",X"1C",X"1C",
+		X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",
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+		X"03",X"03",X"03",X"03",X"03",X"03",X"03",X"03",X"03",X"03",X"03",X"03",X"03",X"03",X"03",X"03",
+		X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
+		X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",
+		X"E0",X"E0",X"E0",X"E0",X"E0",X"E0",X"E0",X"E0",X"0E",X"0E",X"0E",X"0E",X"07",X"07",X"07",X"07",
+		X"1C",X"1C",X"1C",X"1C",X"0E",X"0E",X"0E",X"0E",X"38",X"38",X"38",X"38",X"1C",X"1C",X"1C",X"1C",
+		X"70",X"70",X"70",X"70",X"38",X"38",X"38",X"38",X"E0",X"E0",X"E0",X"E0",X"70",X"70",X"70",X"70",
+		X"C0",X"C0",X"C0",X"C0",X"E0",X"E0",X"E0",X"E0",X"80",X"80",X"80",X"80",X"C0",X"C0",X"C0",X"C0",
+		X"00",X"00",X"00",X"00",X"80",X"80",X"80",X"80",X"01",X"01",X"01",X"01",X"00",X"00",X"00",X"00",
+		X"03",X"03",X"03",X"03",X"01",X"01",X"01",X"01",X"07",X"07",X"07",X"07",X"03",X"03",X"03",X"03",
+		X"0E",X"0E",X"0E",X"0E",X"0E",X"07",X"07",X"07",X"38",X"1C",X"1C",X"1C",X"1C",X"1C",X"1C",X"0E",
+		X"70",X"70",X"70",X"38",X"38",X"38",X"38",X"38",X"E0",X"E0",X"E0",X"E0",X"E0",X"70",X"70",X"70",
+		X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"E0",X"00",X"00",X"00",X"80",X"80",X"80",X"80",X"80",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"01",X"01",X"01",X"01",X"01",X"01",X"00",
+		X"07",X"07",X"07",X"03",X"03",X"03",X"03",X"03",X"1C",X"1C",X"0E",X"0E",X"0E",X"0E",X"07",X"07",
+		X"70",X"70",X"38",X"38",X"38",X"38",X"1C",X"1C",X"C0",X"C0",X"E0",X"E0",X"E0",X"E0",X"70",X"70",
+		X"00",X"00",X"80",X"80",X"80",X"80",X"C0",X"C0",X"01",X"01",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"07",X"07",X"03",X"03",X"03",X"03",X"01",X"01",X"18",X"1C",X"1C",X"0C",X"0E",X"0E",X"06",X"07",
+		X"E0",X"E0",X"60",X"70",X"70",X"30",X"38",X"38",X"00",X"00",X"80",X"80",X"80",X"C0",X"C0",X"C0",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"07",X"03",X"03",X"03",X"01",X"01",X"01",X"00",
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+		X"F8",X"F8",X"FC",X"7F",X"7F",X"3F",X"1F",X"07",X"1F",X"1F",X"3F",X"FE",X"FE",X"FC",X"F8",X"E0",
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+		X"9D",X"09",X"71",X"73",X"77",X"01",X"01",X"FF",X"01",X"01",X"E3",X"C7",X"8F",X"01",X"01",X"FF",
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+		X"3F",X"1F",X"0F",X"07",X"03",X"01",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"7F",X"0F",
+		X"FE",X"FF",X"FF",X"FF",X"FF",X"FF",X"BF",X"DF",X"FF",X"FF",X"BF",X"DF",X"EE",X"FE",X"FE",X"DC",
+		X"FF",X"FF",X"FE",X"FD",X"FF",X"FF",X"FE",X"F0",X"BC",X"78",X"F0",X"E0",X"C0",X"80",X"00",X"00",
+		X"00",X"00",X"01",X"03",X"07",X"0F",X"1F",X"3F",X"0F",X"7F",X"FF",X"FF",X"FD",X"F7",X"EB",X"FD",
+		X"3F",X"7F",X"7F",X"7F",X"FF",X"FF",X"FF",X"FF",X"FD",X"DE",X"FE",X"EF",X"A7",X"EF",X"7F",X"FF",
+		X"F0",X"FE",X"FF",X"FF",X"EF",X"F7",X"FB",X"FD",X"00",X"00",X"80",X"C0",X"E0",X"F0",X"F8",X"FC",
+		X"FF",X"FF",X"FF",X"7F",X"7E",X"7F",X"1F",X"67",X"FC",X"FE",X"FE",X"FE",X"FF",X"FF",X"FF",X"7F",
+		X"FF",X"FF",X"FF",X"FF",X"7F",X"7F",X"7F",X"3F",X"FF",X"FF",X"FF",X"7F",X"F7",X"FF",X"FB",X"FB",
+		X"3F",X"1F",X"0F",X"07",X"03",X"01",X"00",X"00",X"FF",X"FF",X"EF",X"FF",X"FF",X"FF",X"7F",X"0F",
+		X"FB",X"FD",X"FF",X"FD",X"FF",X"FB",X"FB",X"FF",X"FF",X"FF",X"FF",X"FF",X"FE",X"FE",X"FE",X"FC",
+		X"FF",X"FF",X"FD",X"FF",X"FF",X"FF",X"FE",X"F0",X"FC",X"F8",X"F0",X"E0",X"C0",X"80",X"00",X"00",
+		X"00",X"00",X"01",X"03",X"07",X"0F",X"1F",X"3F",X"0F",X"7F",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"3F",X"7F",X"7F",X"7F",X"FF",X"FF",X"FF",X"FF",X"FF",X"EF",X"FE",X"F5",X"7F",X"FF",X"BF",X"DF",
+		X"F0",X"FE",X"FF",X"FF",X"FF",X"FF",X"F5",X"DF",X"00",X"00",X"80",X"C0",X"E0",X"F0",X"F8",X"7C",
+		X"7B",X"7B",X"77",X"F7",X"EF",X"EF",X"DF",X"BF",X"BC",X"DE",X"FE",X"FE",X"FF",X"FF",X"FF",X"DF",
+		X"FF",X"FF",X"FF",X"FF",X"7F",X"7F",X"77",X"3B",X"FF",X"BF",X"7F",X"FF",X"FF",X"FF",X"FF",X"FE",
+		X"3D",X"1E",X"0F",X"07",X"03",X"01",X"00",X"00",X"FF",X"FB",X"77",X"EF",X"BF",X"FF",X"7F",X"0F",
+		X"5F",X"DF",X"DE",X"DF",X"DD",X"DF",X"FB",X"DF",X"BF",X"FF",X"FF",X"FF",X"FE",X"FE",X"FE",X"FC",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FE",X"F0",X"FC",X"F8",X"F0",X"E0",X"C0",X"80",X"00",X"00");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/rom/ROM_OBJ_1.vhd b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/rom/ROM_OBJ_1.vhd
new file mode 100644
index 00000000..bb04f62c
--- /dev/null
+++ b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/rom/ROM_OBJ_1.vhd	
@@ -0,0 +1,150 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity ROM_OBJ_1 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(10 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of ROM_OBJ_1 is
+	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"38",X"7C",X"C2",X"82",X"86",X"7C",X"38",X"00",X"02",X"02",X"FE",X"FE",X"42",X"02",X"00",X"00",
+		X"62",X"F2",X"BA",X"9A",X"9E",X"CE",X"46",X"00",X"8C",X"DE",X"F2",X"B2",X"92",X"86",X"04",X"00",
+		X"08",X"FE",X"FE",X"C8",X"68",X"38",X"18",X"00",X"1C",X"BE",X"A2",X"A2",X"A2",X"E6",X"E4",X"00",
+		X"0C",X"9E",X"92",X"92",X"D2",X"7E",X"3C",X"00",X"C0",X"E0",X"B0",X"9E",X"8E",X"C0",X"C0",X"00",
+		X"0C",X"6E",X"9A",X"9A",X"B2",X"F2",X"6C",X"00",X"78",X"FC",X"96",X"92",X"92",X"F2",X"60",X"00",
+		X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"00",X"00",X"00",X"00",X"24",X"24",X"18",X"00",X"00",
+		X"00",X"00",X"00",X"06",X"06",X"00",X"00",X"00",X"00",X"60",X"F0",X"9A",X"8A",X"C0",X"60",X"00",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"01",X"03",X"07",X"0F",X"1F",X"3F",X"7F",X"FF",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"3E",X"7E",X"C8",X"88",X"C8",X"7E",X"3E",X"00",
+		X"6C",X"FE",X"92",X"92",X"92",X"FE",X"FE",X"00",X"44",X"C6",X"82",X"82",X"C6",X"7C",X"38",X"00",
+		X"38",X"7C",X"C6",X"82",X"82",X"FE",X"FE",X"00",X"82",X"92",X"92",X"92",X"FE",X"FE",X"00",X"00",
+		X"80",X"90",X"90",X"90",X"FE",X"FE",X"00",X"00",X"9E",X"9E",X"92",X"82",X"C6",X"7C",X"38",X"00",
+		X"FE",X"FE",X"10",X"10",X"10",X"FE",X"FE",X"00",X"82",X"82",X"FE",X"FE",X"82",X"82",X"00",X"00",
+		X"FC",X"FE",X"06",X"06",X"06",X"0E",X"0C",X"00",X"82",X"C6",X"6C",X"38",X"18",X"FE",X"FE",X"00",
+		X"02",X"02",X"02",X"02",X"FE",X"FE",X"00",X"00",X"FE",X"FE",X"70",X"38",X"70",X"FE",X"FE",X"00",
+		X"FE",X"FE",X"1C",X"38",X"70",X"FE",X"FE",X"00",X"7C",X"FE",X"82",X"82",X"82",X"FE",X"7C",X"00",
+		X"70",X"F8",X"88",X"88",X"88",X"FE",X"FE",X"00",X"7A",X"FC",X"8E",X"8A",X"82",X"FE",X"7C",X"00",
+		X"62",X"F6",X"8E",X"8C",X"88",X"FE",X"FE",X"00",X"0C",X"5E",X"D2",X"92",X"92",X"F6",X"64",X"00",
+		X"80",X"80",X"FE",X"FE",X"80",X"80",X"00",X"00",X"FC",X"FE",X"02",X"02",X"02",X"FE",X"FC",X"00",
+		X"F0",X"F8",X"1C",X"0E",X"1C",X"F8",X"F0",X"00",X"F8",X"FE",X"1C",X"38",X"1C",X"FE",X"F8",X"00",
+		X"C6",X"EE",X"7C",X"38",X"7C",X"EE",X"C6",X"00",X"C0",X"F0",X"1E",X"1E",X"F0",X"C0",X"00",X"00",
+		X"C2",X"E2",X"F2",X"BA",X"9E",X"8E",X"86",X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",
+		X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"78",X"78",X"78",X"78",X"78",X"78",X"78",X"78",
+		X"3C",X"3C",X"3C",X"3C",X"3C",X"3C",X"3C",X"3C",X"1E",X"1E",X"1E",X"1E",X"1E",X"1E",X"1E",X"1E",
+		X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"07",X"07",X"07",X"07",X"07",X"07",X"07",X"07",
+		X"03",X"03",X"03",X"03",X"03",X"03",X"03",X"03",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
+		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",
+		X"E0",X"E0",X"E0",X"E0",X"E0",X"E0",X"E0",X"E0",X"78",X"78",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",
+		X"3C",X"3C",X"3C",X"3C",X"78",X"78",X"78",X"78",X"1E",X"1E",X"1E",X"1E",X"1E",X"1E",X"3C",X"3C",
+		X"07",X"07",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"03",X"03",X"03",X"03",X"07",X"07",X"07",X"07",
+		X"01",X"01",X"01",X"01",X"01",X"01",X"03",X"03",X"80",X"80",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"C0",X"C0",X"C0",X"C0",X"80",X"80",X"80",X"80",X"E0",X"E0",X"E0",X"E0",X"E0",X"E0",X"C0",X"C0",
+		X"78",X"78",X"78",X"78",X"F0",X"F0",X"F0",X"F0",X"1E",X"1E",X"1E",X"1E",X"3C",X"3C",X"3C",X"3C",
+		X"07",X"07",X"07",X"07",X"0F",X"0F",X"0F",X"0F",X"01",X"01",X"01",X"01",X"03",X"03",X"03",X"03",
+		X"80",X"80",X"80",X"80",X"00",X"00",X"00",X"00",X"E0",X"E0",X"E0",X"E0",X"C0",X"C0",X"C0",X"C0",
+		X"3C",X"3C",X"78",X"78",X"78",X"F0",X"F0",X"F0",X"07",X"0F",X"0F",X"0F",X"1E",X"1E",X"1E",X"3C",
+		X"01",X"01",X"01",X"03",X"03",X"03",X"07",X"07",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"E0",X"E0",X"E0",X"C0",X"C0",X"C0",X"80",X"80",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",
+		X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"78",X"78",X"78",X"78",X"78",X"78",X"78",X"78",
+		X"78",X"78",X"78",X"78",X"78",X"78",X"78",X"78",X"3C",X"3C",X"3C",X"3C",X"3C",X"3C",X"3C",X"3C",
+		X"3C",X"3C",X"3C",X"3C",X"3C",X"3C",X"3C",X"3C",X"1E",X"1E",X"1E",X"1E",X"1E",X"1E",X"1E",X"1E",
+		X"1E",X"1E",X"1E",X"1E",X"1E",X"1E",X"1E",X"1E",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
+		X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"07",X"07",X"07",X"07",X"07",X"07",X"07",X"07",
+		X"07",X"07",X"07",X"07",X"07",X"07",X"07",X"07",X"03",X"03",X"03",X"03",X"03",X"03",X"03",X"03",
+		X"03",X"03",X"03",X"03",X"03",X"03",X"03",X"03",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
+		X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
+		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",
+		X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"E0",X"E0",X"E0",X"E0",X"E0",X"E0",X"E0",X"E0",
+		X"E0",X"E0",X"E0",X"E0",X"E0",X"E0",X"E0",X"E0",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
+		X"1E",X"1E",X"1E",X"1E",X"1E",X"1E",X"1E",X"1E",X"3C",X"3C",X"3C",X"3C",X"3C",X"3C",X"3C",X"3C",
+		X"78",X"78",X"78",X"78",X"78",X"78",X"78",X"78",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",
+		X"E0",X"E0",X"E0",X"E0",X"E0",X"E0",X"E0",X"E0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",
+		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
+		X"03",X"03",X"03",X"03",X"03",X"03",X"03",X"03",X"07",X"07",X"07",X"07",X"07",X"07",X"07",X"07",
+		X"1E",X"1E",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"3C",X"3C",X"3C",X"3C",X"1E",X"1E",X"1E",X"1E",
+		X"78",X"78",X"78",X"78",X"78",X"78",X"3C",X"3C",X"E0",X"E0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",
+		X"C0",X"C0",X"C0",X"C0",X"E0",X"E0",X"E0",X"E0",X"80",X"80",X"80",X"80",X"80",X"80",X"C0",X"C0",
+		X"01",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"03",X"03",X"03",X"01",X"01",X"01",X"01",
+		X"07",X"07",X"07",X"07",X"07",X"07",X"03",X"03",X"1E",X"1E",X"1E",X"1E",X"0F",X"0F",X"0F",X"0F",
+		X"78",X"78",X"78",X"78",X"3C",X"3C",X"3C",X"3C",X"E0",X"E0",X"E0",X"E0",X"F0",X"F0",X"F0",X"F0",
+		X"80",X"80",X"80",X"80",X"C0",X"C0",X"C0",X"C0",X"01",X"01",X"01",X"01",X"00",X"00",X"00",X"00",
+		X"07",X"07",X"07",X"07",X"03",X"03",X"03",X"03",X"3C",X"3C",X"1E",X"1E",X"1E",X"0F",X"0F",X"0F",
+		X"E0",X"F0",X"F0",X"F0",X"78",X"78",X"78",X"3C",X"80",X"80",X"80",X"C0",X"C0",X"C0",X"E0",X"E0",
+		X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"07",X"07",X"07",X"03",X"03",X"03",X"01",X"01",
+		X"07",X"1F",X"3C",X"70",X"60",X"E3",X"C7",X"C7",X"E0",X"F8",X"3C",X"0E",X"06",X"C7",X"E3",X"E3",
+		X"C7",X"C7",X"E3",X"60",X"70",X"3C",X"1F",X"07",X"E3",X"E3",X"C7",X"06",X"0E",X"3C",X"F8",X"E0",
+		X"FF",X"7F",X"3F",X"1F",X"0F",X"07",X"03",X"01",X"F3",X"A1",X"2D",X"6D",X"6D",X"09",X"9B",X"FF",
+		X"7F",X"7F",X"01",X"01",X"7F",X"7F",X"FF",X"FF",X"7D",X"6D",X"6D",X"6D",X"01",X"01",X"FF",X"FF",
+		X"9D",X"09",X"71",X"73",X"77",X"01",X"01",X"FF",X"01",X"01",X"E3",X"C7",X"8F",X"01",X"01",X"FF",
+		X"44",X"44",X"38",X"00",X"44",X"44",X"44",X"38",X"7C",X"18",X"30",X"7C",X"00",X"7C",X"00",X"38",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",
+		X"00",X"01",X"03",X"07",X"0F",X"0F",X"0F",X"0F",X"0F",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"E0",X"F0",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"30",X"F8",X"F8",X"F8",X"F8",X"F8",X"F8",
+		X"0F",X"0F",X"07",X"07",X"03",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"7F",X"0F",X"03",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"FF",X"FF",X"FF",X"F8",X"F0",X"F0",X"70",X"10",X"F8",X"F8",X"F8",X"70",X"30",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"00",X"00",X"00",X"00",X"00",X"7F",X"FF",X"FF",
+		X"01",X"03",X"03",X"03",X"01",X"01",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"E0",X"F8",X"FE",X"FF",X"FF",X"FF",X"FE",X"FE",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"7F",X"7F",X"7F",X"7F",X"4F",X"0F",X"0E",X"08",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"7F",X"3F",X"00",X"00",X"C0",X"E0",X"F8",X"F8",X"F0",X"E0",
+		X"1F",X"1F",X"1F",X"1E",X"00",X"00",X"00",X"00",X"C0",X"80",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"0F",X"1F",X"1F",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"1F",X"3F",X"3F",X"3F",X"7F",X"7F",X"FF",X"FF",
+		X"00",X"00",X"00",X"00",X"F0",X"F8",X"FC",X"FE",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"FE",X"FE",X"FE",X"FE",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"3F",X"7F",X"7F",X"FF",X"0F",X"07",X"07",X"07",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"07",X"0F",X"1F",X"1F",X"07",X"00",X"00",X"00",
+		X"FF",X"FF",X"FF",X"FE",X"FC",X"FC",X"FC",X"FC",X"80",X"80",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"FC",X"FC",X"FE",X"FE",X"FC",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"1F",X"0F",X"0F",X"FF",X"7F",X"7F",X"3F",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"0E",X"3F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"C0",X"E0",X"E0",X"E0",X"E0",X"E0",X"E0",X"E0",
+		X"00",X"00",X"00",X"0F",X"0F",X"0F",X"0F",X"07",X"3F",X"7F",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"03",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"FC",X"FC",X"F8",X"70",X"70",X"00",X"00",X"00",
+		X"FF",X"FF",X"FF",X"FE",X"FE",X"FC",X"FC",X"38",X"C0",X"80",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/rom/ROM_PGM.vhd b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/rom/ROM_PGM.vhd
new file mode 100644
index 00000000..081c70fe
--- /dev/null
+++ b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/rom/ROM_PGM.vhd	
@@ -0,0 +1,534 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity ROM_PGM is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(12 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of ROM_PGM is
+	type rom is array(0 to  8191) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"3A",X"00",X"B0",X"31",X"00",X"88",X"3E",X"9B",X"32",X"03",X"98",X"AF",X"21",X"00",X"A8",X"06",
+		X"08",X"77",X"23",X"10",X"FC",X"21",X"00",X"90",X"06",X"7D",X"77",X"23",X"10",X"FC",X"21",X"00",
+		X"88",X"0E",X"04",X"CD",X"B7",X"00",X"CD",X"6C",X"09",X"21",X"10",X"8B",X"FD",X"21",X"13",X"01",
+		X"06",X"09",X"CD",X"3D",X"0B",X"31",X"20",X"88",X"21",X"00",X"80",X"0E",X"08",X"CD",X"B7",X"00",
+		X"31",X"00",X"88",X"21",X"10",X"8B",X"FD",X"21",X"1C",X"01",X"06",X"09",X"CD",X"3D",X"0B",X"21",
+		X"00",X"00",X"CD",X"A0",X"00",X"21",X"F0",X"8A",X"36",X"15",X"21",X"00",X"10",X"CD",X"A0",X"00",
+		X"3A",X"00",X"98",X"18",X"04",X"00",X"C3",X"4D",X"12",X"E6",X"0A",X"FE",X"0A",X"CA",X"56",X"01",
+		X"11",X"06",X"00",X"FD",X"21",X"25",X"01",X"01",X"07",X"06",X"21",X"10",X"8B",X"3A",X"00",X"98",
+		X"E6",X"0A",X"CA",X"56",X"01",X"3A",X"00",X"98",X"07",X"38",X"08",X"CD",X"3D",X"0B",X"3A",X"00",
+		X"B0",X"18",X"DD",X"FD",X"19",X"0D",X"20",X"F0",X"CD",X"3D",X"0B",X"3A",X"00",X"B0",X"18",X"D0",
+		X"01",X"10",X"00",X"AF",X"86",X"23",X"10",X"FC",X"08",X"3A",X"00",X"B0",X"08",X"0D",X"20",X"F4",
+		X"B7",X"C8",X"3A",X"00",X"B0",X"18",X"FB",X"70",X"7E",X"B8",X"3A",X"00",X"B0",X"20",X"FB",X"10",
+		X"F6",X"51",X"36",X"00",X"23",X"10",X"FB",X"3A",X"00",X"B0",X"0D",X"20",X"F5",X"4A",X"11",X"55",
+		X"00",X"CD",X"FB",X"00",X"11",X"AA",X"55",X"CD",X"E3",X"00",X"11",X"FF",X"AA",X"CD",X"FB",X"00",
+		X"11",X"00",X"FF",X"C5",X"7E",X"BA",X"3A",X"00",X"B0",X"20",X"FB",X"73",X"7E",X"BB",X"3A",X"00",
+		X"B0",X"20",X"FB",X"23",X"10",X"EE",X"0D",X"20",X"EB",X"C1",X"C9",X"C5",X"2B",X"7E",X"BA",X"3A",
+		X"00",X"B0",X"20",X"FB",X"73",X"7E",X"BB",X"3A",X"00",X"B0",X"20",X"FB",X"10",X"EE",X"0D",X"20",
+		X"EB",X"C1",X"C9",X"22",X"11",X"1D",X"10",X"01",X"17",X"18",X"1A",X"1B",X"02",X"13",X"10",X"22",
+		X"1F",X"1D",X"10",X"10",X"10",X"13",X"1F",X"19",X"1E",X"10",X"01",X"13",X"1F",X"19",X"1E",X"10",
+		X"02",X"1C",X"15",X"16",X"24",X"10",X"10",X"22",X"19",X"17",X"18",X"24",X"10",X"20",X"1C",X"11",
+		X"29",X"10",X"02",X"10",X"10",X"10",X"10",X"10",X"10",X"20",X"1C",X"11",X"29",X"10",X"01",X"10",
+		X"10",X"10",X"10",X"10",X"10",X"E6",X"3A",X"00",X"B0",X"3E",X"80",X"32",X"A4",X"80",X"21",X"00",
+		X"88",X"11",X"01",X"88",X"01",X"FF",X"03",X"36",X"10",X"ED",X"B0",X"3E",X"88",X"32",X"03",X"A0",
+		X"3E",X"55",X"32",X"CB",X"80",X"32",X"78",X"80",X"32",X"03",X"A8",X"21",X"01",X"A8",X"71",X"0D",
+		X"71",X"0E",X"3D",X"11",X"40",X"90",X"21",X"C7",X"10",X"ED",X"B0",X"FD",X"21",X"B8",X"0F",X"21",
+		X"A0",X"8B",X"06",X"1B",X"CD",X"3D",X"0B",X"21",X"A1",X"8B",X"06",X"1A",X"CD",X"3D",X"0B",X"21",
+		X"A2",X"8B",X"06",X"17",X"CD",X"3D",X"0B",X"3E",X"04",X"CD",X"2F",X"0D",X"3E",X"0A",X"11",X"CE",
+		X"80",X"21",X"87",X"0F",X"01",X"0A",X"00",X"ED",X"B0",X"3D",X"20",X"F5",X"11",X"55",X"81",X"21",
+		X"87",X"0F",X"0E",X"06",X"ED",X"B0",X"3D",X"20",X"F6",X"21",X"A9",X"80",X"11",X"AA",X"80",X"01",
+		X"0D",X"00",X"36",X"00",X"ED",X"B0",X"18",X"49",X"CD",X"53",X"09",X"3A",X"A4",X"80",X"87",X"20",
+		X"40",X"06",X"00",X"3A",X"A8",X"80",X"21",X"AB",X"80",X"CD",X"CF",X"0A",X"CD",X"84",X"0A",X"3A",
+		X"A8",X"80",X"CB",X"3F",X"C4",X"81",X"0A",X"3E",X"01",X"CD",X"2C",X"0D",X"3A",X"A8",X"80",X"CB",
+		X"3F",X"28",X"06",X"CD",X"FB",X"0B",X"CD",X"08",X"0D",X"CD",X"FB",X"0B",X"3E",X"04",X"CD",X"18",
+		X"09",X"32",X"A8",X"80",X"3E",X"84",X"32",X"A4",X"80",X"3E",X"0C",X"CD",X"18",X"09",X"CD",X"2C",
+		X"0D",X"3E",X"84",X"32",X"A4",X"80",X"3A",X"00",X"98",X"E6",X"2A",X"20",X"38",X"CD",X"6C",X"09",
+		X"21",X"A8",X"8B",X"DD",X"21",X"A9",X"80",X"FD",X"21",X"3F",X"0F",X"CD",X"2A",X"0B",X"21",X"AA",
+		X"8B",X"CD",X"2A",X"0B",X"21",X"AC",X"8B",X"CD",X"2A",X"0B",X"21",X"AE",X"8B",X"CD",X"2A",X"0B",
+		X"21",X"B0",X"8B",X"CD",X"10",X"0B",X"21",X"B2",X"8B",X"CD",X"10",X"0B",X"3A",X"00",X"98",X"E6",
+		X"0A",X"FE",X"0A",X"20",X"F7",X"21",X"75",X"80",X"7E",X"B7",X"20",X"02",X"36",X"10",X"CB",X"16",
+		X"CD",X"6C",X"09",X"21",X"40",X"8A",X"CD",X"61",X"09",X"21",X"41",X"8A",X"3A",X"A8",X"80",X"D6",
+		X"02",X"28",X"02",X"3E",X"10",X"CD",X"62",X"09",X"21",X"91",X"0F",X"11",X"37",X"80",X"01",X"27",
+		X"00",X"ED",X"B0",X"AF",X"32",X"70",X"80",X"3A",X"02",X"98",X"E6",X"08",X"0F",X"0F",X"6F",X"3E",
+		X"05",X"95",X"6F",X"3A",X"A4",X"80",X"87",X"7D",X"CA",X"44",X"03",X"3E",X"01",X"CD",X"2C",X"0D",
+		X"3E",X"FF",X"32",X"CB",X"80",X"CD",X"4A",X"0B",X"21",X"AC",X"8B",X"06",X"1C",X"CD",X"8D",X"0B",
+		X"06",X"1B",X"CD",X"8D",X"0B",X"06",X"15",X"CD",X"8D",X"0B",X"06",X"18",X"CD",X"8D",X"0B",X"06",
+		X"1A",X"CD",X"8D",X"0B",X"06",X"10",X"CD",X"8D",X"0B",X"2C",X"06",X"1B",X"CD",X"8D",X"0B",X"06",
+		X"1B",X"CD",X"8D",X"0B",X"06",X"1A",X"CD",X"8D",X"0B",X"06",X"1A",X"CD",X"8D",X"0B",X"2C",X"06",
+		X"17",X"CD",X"8D",X"0B",X"06",X"19",X"CD",X"8D",X"0B",X"06",X"0D",X"CD",X"8D",X"0B",X"06",X"17",
+		X"CD",X"8D",X"0B",X"06",X"1A",X"CD",X"8D",X"0B",X"06",X"1C",X"CD",X"8D",X"0B",X"3E",X"55",X"32",
+		X"CB",X"80",X"3E",X"08",X"CD",X"18",X"09",X"CD",X"6C",X"09",X"CD",X"4A",X"0B",X"CD",X"91",X"09",
+		X"3E",X"10",X"CD",X"18",X"09",X"AF",X"CD",X"2C",X"0D",X"3E",X"81",X"32",X"A4",X"80",X"21",X"68",
+		X"1D",X"22",X"A6",X"80",X"3E",X"03",X"32",X"58",X"80",X"21",X"80",X"11",X"22",X"5A",X"80",X"3E",
+		X"01",X"32",X"B8",X"80",X"32",X"B7",X"80",X"32",X"41",X"88",X"21",X"37",X"80",X"11",X"79",X"80",
+		X"0E",X"27",X"ED",X"B0",X"C3",X"09",X"05",X"CD",X"26",X"09",X"CD",X"6C",X"09",X"CD",X"53",X"09",
+		X"CD",X"C4",X"09",X"CD",X"FF",X"08",X"E5",X"D1",X"CD",X"48",X"08",X"47",X"BE",X"38",X"2E",X"20",
+		X"10",X"3A",X"80",X"88",X"23",X"BE",X"38",X"25",X"20",X"07",X"3A",X"40",X"88",X"23",X"BE",X"38",
+		X"1C",X"3A",X"B8",X"80",X"1B",X"12",X"13",X"78",X"12",X"3A",X"80",X"88",X"13",X"12",X"3A",X"40",
+		X"88",X"13",X"12",X"3E",X"05",X"CD",X"2C",X"0D",X"3E",X"07",X"CD",X"C6",X"09",X"21",X"40",X"88",
+		X"11",X"F1",X"88",X"01",X"20",X"00",X"3E",X"0C",X"F5",X"7E",X"12",X"09",X"EB",X"F1",X"FE",X"08",
+		X"20",X"03",X"09",X"09",X"09",X"09",X"EB",X"3D",X"20",X"EE",X"21",X"53",X"8B",X"FD",X"21",X"04",
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+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/rom/ROM_SND_0.vhd b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/rom/ROM_SND_0.vhd
new file mode 100644
index 00000000..5e591b11
--- /dev/null
+++ b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/rom/ROM_SND_0.vhd	
@@ -0,0 +1,150 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity ROM_SND_0 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(10 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of ROM_SND_0 is
+	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"00",X"F3",X"31",X"00",X"81",X"C3",X"40",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"C3",X"54",X"05",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"0E",X"10",X"CD",X"6C",X"03",X"0E",X"40",X"CD",X"6C",X"03",X"0E",X"10",X"CD",X"6C",X"03",X"0E",
+		X"40",X"CD",X"6C",X"03",X"CD",X"04",X"01",X"21",X"00",X"80",X"01",X"00",X"04",X"36",X"00",X"23",
+		X"0D",X"20",X"FA",X"10",X"F8",X"3E",X"3F",X"32",X"2A",X"81",X"32",X"38",X"81",X"CD",X"12",X"01",
+		X"01",X"00",X"00",X"ED",X"56",X"FB",X"ED",X"5B",X"01",X"81",X"7A",X"B3",X"28",X"13",X"F3",X"ED",
+		X"4B",X"01",X"81",X"11",X"00",X"00",X"ED",X"53",X"01",X"81",X"31",X"00",X"81",X"CD",X"4D",X"03",
+		X"FB",X"0A",X"03",X"26",X"00",X"87",X"6F",X"11",X"A0",X"00",X"19",X"7E",X"23",X"66",X"6F",X"E9",
+		X"D9",X"01",X"EB",X"01",X"0B",X"02",X"20",X"02",X"2D",X"02",X"37",X"02",X"43",X"02",X"50",X"02",
+		X"62",X"02",X"6C",X"02",X"78",X"02",X"87",X"02",X"A1",X"02",X"B2",X"02",X"C8",X"02",X"DC",X"02",
+		X"E2",X"02",X"EE",X"02",X"01",X"03",X"10",X"03",X"35",X"03",X"41",X"03",X"45",X"03",X"FB",X"01",
+		X"3C",X"01",X"4B",X"01",X"54",X"01",X"88",X"01",X"8D",X"01",X"AB",X"01",X"B0",X"01",X"BF",X"01",
+		X"C4",X"01",X"17",X"02",X"A3",X"03",X"21",X"44",X"81",X"06",X"06",X"11",X"00",X"00",X"CB",X"23",
+		X"CB",X"12",X"CB",X"23",X"CB",X"12",X"7E",X"E6",X"03",X"B3",X"5F",X"2B",X"10",X"F0",X"21",X"00",
+		X"90",X"19",X"77",X"C9",X"3E",X"03",X"21",X"3F",X"81",X"06",X"06",X"77",X"10",X"FD",X"CD",X"E6",
+		X"00",X"C9",X"11",X"23",X"81",X"0E",X"10",X"CD",X"23",X"01",X"11",X"31",X"81",X"0E",X"40",X"CD",
+		X"23",X"01",X"C9",X"2E",X"00",X"06",X"0E",X"7D",X"FE",X"0B",X"1A",X"13",X"38",X"06",X"CD",X"9A",
+		X"03",X"BC",X"28",X"04",X"67",X"CD",X"8B",X"03",X"2C",X"10",X"EC",X"C9",X"21",X"3F",X"81",X"1E",
+		X"06",X"0A",X"77",X"23",X"03",X"1D",X"20",X"F9",X"C3",X"76",X"00",X"DD",X"21",X"2A",X"81",X"21",
+		X"23",X"81",X"18",X"07",X"DD",X"21",X"38",X"81",X"21",X"31",X"81",X"CD",X"79",X"01",X"28",X"04",
+		X"DD",X"CB",X"00",X"86",X"CD",X"79",X"01",X"28",X"04",X"DD",X"CB",X"00",X"8E",X"CD",X"79",X"01",
+		X"28",X"04",X"DD",X"CB",X"00",X"96",X"C3",X"76",X"00",X"EB",X"0A",X"03",X"6F",X"0A",X"03",X"67",
+		X"EB",X"73",X"23",X"72",X"23",X"7A",X"B3",X"C9",X"21",X"29",X"81",X"18",X"03",X"21",X"37",X"81",
+		X"0A",X"03",X"77",X"23",X"0A",X"03",X"CB",X"47",X"28",X"02",X"CB",X"9E",X"CB",X"4F",X"28",X"02",
+		X"CB",X"A6",X"CB",X"57",X"28",X"02",X"CB",X"AE",X"C3",X"76",X"00",X"21",X"2B",X"81",X"18",X"03",
+		X"21",X"39",X"81",X"16",X"03",X"0A",X"77",X"03",X"23",X"15",X"20",X"F9",X"C3",X"76",X"00",X"21",
+		X"2E",X"81",X"18",X"03",X"21",X"3C",X"81",X"EB",X"0A",X"03",X"6F",X"0A",X"03",X"67",X"EB",X"73",
+		X"23",X"72",X"23",X"0A",X"03",X"77",X"C3",X"76",X"00",X"AF",X"32",X"00",X"81",X"01",X"00",X"00",
+		X"ED",X"4B",X"01",X"81",X"78",X"B1",X"C2",X"76",X"00",X"18",X"F5",X"C5",X"CD",X"E6",X"00",X"CD",
+		X"12",X"01",X"3E",X"5C",X"3D",X"20",X"FD",X"C1",X"C3",X"76",X"00",X"C5",X"CD",X"12",X"01",X"CD",
+		X"E6",X"00",X"3E",X"2E",X"3D",X"20",X"FD",X"C1",X"C3",X"76",X"00",X"0A",X"03",X"6F",X"87",X"9F",
+		X"67",X"09",X"44",X"4D",X"C3",X"76",X"00",X"0A",X"03",X"6F",X"0A",X"47",X"4D",X"C3",X"76",X"00",
+		X"0A",X"03",X"6F",X"0A",X"03",X"67",X"35",X"20",X"E2",X"03",X"C3",X"76",X"00",X"0A",X"03",X"6F",
+		X"0A",X"03",X"67",X"5E",X"C3",X"46",X"02",X"0A",X"03",X"6F",X"0A",X"03",X"67",X"5E",X"23",X"56",
+		X"C3",X"56",X"02",X"0A",X"03",X"5F",X"0A",X"03",X"6F",X"0A",X"03",X"67",X"73",X"C3",X"76",X"00",
+		X"0A",X"03",X"5F",X"0A",X"03",X"57",X"0A",X"03",X"6F",X"0A",X"03",X"67",X"73",X"23",X"72",X"C3",
+		X"76",X"00",X"0A",X"03",X"6F",X"0A",X"03",X"67",X"5E",X"C3",X"7B",X"02",X"0A",X"03",X"6F",X"0A",
+		X"03",X"67",X"5E",X"23",X"56",X"C3",X"8D",X"02",X"0A",X"03",X"5F",X"0A",X"03",X"6F",X"0A",X"03",
+		X"67",X"7E",X"83",X"77",X"C3",X"76",X"00",X"0A",X"03",X"5F",X"0A",X"03",X"57",X"0A",X"03",X"6F",
+		X"0A",X"03",X"67",X"E5",X"7E",X"23",X"66",X"6F",X"19",X"EB",X"E1",X"73",X"23",X"72",X"C3",X"76",
+		X"00",X"0A",X"03",X"5F",X"0A",X"03",X"6F",X"0A",X"03",X"67",X"CB",X"2E",X"1D",X"20",X"FB",X"C3",
+		X"76",X"00",X"0A",X"03",X"5F",X"0A",X"03",X"6F",X"0A",X"03",X"67",X"23",X"CB",X"2E",X"2B",X"CB",
+		X"1E",X"23",X"1D",X"20",X"F7",X"C3",X"76",X"00",X"0A",X"03",X"5F",X"0A",X"03",X"6F",X"0A",X"03",
+		X"67",X"0A",X"77",X"23",X"03",X"1D",X"C2",X"D1",X"02",X"C3",X"76",X"00",X"0A",X"03",X"87",X"C3",
+		X"CA",X"02",X"CD",X"6C",X"03",X"CD",X"4D",X"03",X"01",X"00",X"00",X"C3",X"76",X"00",X"0A",X"03",
+		X"57",X"0A",X"03",X"5F",X"0A",X"03",X"6F",X"0A",X"03",X"67",X"7E",X"B2",X"A3",X"77",X"C3",X"76",
+		X"00",X"0A",X"03",X"5F",X"0A",X"03",X"6F",X"0A",X"03",X"67",X"7E",X"B3",X"77",X"C3",X"76",X"00",
+		X"0A",X"03",X"6F",X"0A",X"03",X"67",X"35",X"20",X"09",X"23",X"7E",X"B7",X"20",X"03",X"C3",X"76",
+		X"00",X"35",X"0B",X"0B",X"0B",X"C5",X"CD",X"E6",X"00",X"CD",X"12",X"01",X"3E",X"5C",X"3D",X"20",
+		X"FD",X"C1",X"C3",X"76",X"00",X"0A",X"03",X"6F",X"0A",X"03",X"67",X"C5",X"44",X"4D",X"C3",X"76",
+		X"00",X"C1",X"C3",X"76",X"00",X"3E",X"00",X"32",X"00",X"81",X"C3",X"76",X"00",X"C5",X"21",X"23",
+		X"81",X"06",X"0E",X"AF",X"77",X"23",X"10",X"FC",X"21",X"31",X"81",X"06",X"0E",X"AF",X"77",X"23",
+		X"10",X"FC",X"3E",X"3F",X"32",X"2A",X"81",X"32",X"38",X"81",X"C1",X"C9",X"CD",X"73",X"03",X"0E",
+		X"10",X"18",X"02",X"0E",X"40",X"06",X"0D",X"ED",X"41",X"CB",X"21",X"16",X"00",X"78",X"FE",X"07",
+		X"20",X"02",X"16",X"3F",X"ED",X"51",X"CB",X"39",X"10",X"ED",X"C9",X"ED",X"69",X"CB",X"21",X"ED",
+		X"61",X"CB",X"39",X"C9",X"0E",X"10",X"18",X"02",X"0E",X"40",X"ED",X"69",X"CB",X"21",X"ED",X"60",
+		X"CB",X"39",X"C9",X"0A",X"03",X"6F",X"0A",X"03",X"67",X"C5",X"E5",X"DD",X"E1",X"11",X"05",X"81",
+		X"23",X"23",X"01",X"0C",X"00",X"ED",X"B0",X"DD",X"7E",X"0E",X"32",X"2B",X"81",X"32",X"2C",X"81",
+		X"32",X"2D",X"81",X"32",X"39",X"81",X"32",X"3A",X"81",X"32",X"3B",X"81",X"DD",X"46",X"00",X"48",
+		X"ED",X"43",X"13",X"81",X"ED",X"43",X"15",X"81",X"ED",X"43",X"17",X"81",X"CD",X"EB",X"03",X"2A",
+		X"05",X"81",X"7E",X"B7",X"C2",X"CC",X"03",X"C1",X"C3",X"76",X"00",X"CD",X"15",X"04",X"CD",X"3D",
+		X"04",X"CD",X"65",X"04",X"CD",X"8D",X"04",X"CD",X"B5",X"04",X"CD",X"DD",X"04",X"C5",X"D5",X"E5",
+		X"CD",X"12",X"01",X"ED",X"5B",X"01",X"81",X"7A",X"B3",X"C2",X"76",X"00",X"E1",X"D1",X"C1",X"CD",
+		X"05",X"05",X"10",X"D7",X"C9",X"3A",X"2B",X"81",X"3D",X"32",X"2B",X"81",X"78",X"21",X"13",X"81",
+		X"BE",X"C0",X"DD",X"7E",X"0E",X"32",X"2B",X"81",X"78",X"2A",X"05",X"81",X"96",X"32",X"13",X"81",
+		X"23",X"7E",X"23",X"22",X"05",X"81",X"CD",X"12",X"05",X"22",X"23",X"81",X"C9",X"3A",X"2C",X"81",
+		X"3D",X"32",X"2C",X"81",X"78",X"21",X"14",X"81",X"BE",X"C0",X"DD",X"7E",X"0E",X"32",X"2C",X"81",
+		X"78",X"2A",X"07",X"81",X"96",X"32",X"14",X"81",X"23",X"7E",X"23",X"22",X"07",X"81",X"CD",X"12",
+		X"05",X"22",X"25",X"81",X"C9",X"3A",X"2D",X"81",X"3D",X"32",X"2D",X"81",X"78",X"21",X"15",X"81",
+		X"BE",X"C0",X"DD",X"7E",X"0E",X"32",X"2D",X"81",X"78",X"2A",X"09",X"81",X"96",X"32",X"15",X"81",
+		X"23",X"7E",X"23",X"22",X"09",X"81",X"CD",X"12",X"05",X"22",X"27",X"81",X"C9",X"3A",X"39",X"81",
+		X"3D",X"32",X"39",X"81",X"78",X"21",X"16",X"81",X"BE",X"C0",X"DD",X"7E",X"0E",X"32",X"39",X"81",
+		X"78",X"2A",X"0B",X"81",X"96",X"32",X"16",X"81",X"23",X"7E",X"23",X"22",X"0B",X"81",X"CD",X"12",
+		X"05",X"22",X"31",X"81",X"C9",X"3A",X"3A",X"81",X"3D",X"32",X"3A",X"81",X"78",X"21",X"17",X"81",
+		X"BE",X"C0",X"DD",X"7E",X"0E",X"32",X"3A",X"81",X"78",X"2A",X"0D",X"81",X"96",X"32",X"17",X"81",
+		X"23",X"7E",X"23",X"22",X"0D",X"81",X"CD",X"12",X"05",X"22",X"33",X"81",X"C9",X"3A",X"3B",X"81",
+		X"3D",X"32",X"3B",X"81",X"78",X"21",X"18",X"81",X"BE",X"C0",X"DD",X"7E",X"0E",X"32",X"3B",X"81",
+		X"78",X"2A",X"0F",X"81",X"96",X"32",X"18",X"81",X"23",X"7E",X"23",X"22",X"0F",X"81",X"CD",X"12",
+		X"05",X"22",X"35",X"81",X"C9",X"C5",X"DD",X"46",X"01",X"3E",X"5C",X"3D",X"20",X"FD",X"10",X"F9",
+		X"C1",X"C9",X"C5",X"47",X"E6",X"0F",X"87",X"6F",X"26",X"00",X"11",X"3A",X"05",X"19",X"5E",X"23",
+		X"56",X"78",X"E6",X"7F",X"CB",X"3F",X"CB",X"3F",X"CB",X"3F",X"CB",X"3F",X"47",X"B7",X"CA",X"37",
+		X"05",X"CB",X"3A",X"CB",X"1B",X"10",X"FA",X"EB",X"C1",X"C9",X"00",X"00",X"5D",X"0D",X"9C",X"0C",
+		X"E7",X"0B",X"3C",X"0B",X"9B",X"0A",X"02",X"0A",X"73",X"09",X"EB",X"08",X"6B",X"08",X"F2",X"07",
+		X"80",X"07",X"14",X"07",X"D9",X"08",X"3E",X"0E",X"D3",X"40",X"DB",X"80",X"6F",X"32",X"45",X"81",
+		X"FE",X"0E",X"DA",X"67",X"05",X"2E",X"00",X"26",X"00",X"54",X"5D",X"19",X"19",X"11",X"94",X"05",
+		X"19",X"EB",X"1A",X"21",X"00",X"81",X"BE",X"38",X"17",X"32",X"00",X"81",X"13",X"1A",X"32",X"01",
+		X"81",X"13",X"1A",X"32",X"02",X"81",X"0E",X"10",X"CD",X"6C",X"03",X"0E",X"40",X"CD",X"6C",X"03",
+		X"D9",X"08",X"FB",X"C9",X"40",X"BE",X"05",X"40",X"BF",X"05",X"40",X"BE",X"09",X"40",X"43",X"0A",
+		X"40",X"73",X"0A",X"40",X"8B",X"0A",X"40",X"02",X"0B",X"40",X"BE",X"05",X"40",X"E8",X"05",X"40",
+		X"E6",X"09",X"40",X"43",X"0A",X"40",X"73",X"0A",X"40",X"8B",X"0A",X"40",X"2B",X"0B",X"10",X"18",
+		X"03",X"03",X"03",X"03",X"03",X"03",X"19",X"FF",X"0F",X"FF",X"0F",X"FF",X"0F",X"1A",X"FF",X"0F",
+		X"FF",X"0F",X"FF",X"0F",X"22",X"D9",X"05",X"02",X"FB",X"08",X"B4",X"11",X"06",X"E2",X"06",X"96",
+		X"07",X"62",X"08",X"DE",X"08",X"5A",X"09",X"06",X"18",X"03",X"03",X"03",X"03",X"03",X"03",X"19",
+		X"FF",X"0F",X"FF",X"0F",X"FF",X"0F",X"1A",X"FF",X"0F",X"FF",X"0F",X"FF",X"0F",X"22",X"02",X"06",
+		X"02",X"FB",X"08",X"B4",X"11",X"06",X"E2",X"06",X"96",X"07",X"62",X"08",X"DE",X"08",X"5A",X"09",
+		X"02",X"01",X"80",X"01",X"C9",X"01",X"D4",X"01",X"C9",X"01",X"D1",X"02",X"D4",X"01",X"C8",X"01",
+		X"D4",X"01",X"C8",X"01",X"CB",X"05",X"D4",X"01",X"80",X"01",X"C9",X"01",X"D4",X"01",X"C9",X"01",
+		X"D1",X"02",X"D4",X"01",X"C8",X"01",X"D4",X"01",X"C8",X"01",X"CB",X"03",X"C4",X"01",X"80",X"01",
+		X"C4",X"01",X"80",X"01",X"C9",X"01",X"CC",X"01",X"D5",X"01",X"80",X"01",X"D4",X"01",X"80",X"01",
+		X"D4",X"01",X"80",X"01",X"C9",X"01",X"CC",X"01",X"D5",X"01",X"80",X"01",X"D4",X"02",X"80",X"01",
+		X"80",X"01",X"A9",X"01",X"AC",X"01",X"B9",X"01",X"80",X"01",X"B9",X"01",X"BC",X"01",X"C9",X"01",
+		X"80",X"01",X"C9",X"01",X"CC",X"01",X"D9",X"01",X"80",X"01",X"D9",X"01",X"DC",X"01",X"E9",X"02",
+		X"E9",X"02",X"E9",X"02",X"E9",X"01",X"E9",X"01",X"E9",X"01",X"E9",X"01",X"E4",X"01",X"E6",X"01",
+		X"E1",X"01",X"E4",X"02",X"E6",X"01",X"D9",X"01",X"D9",X"01",X"DB",X"01",X"DC",X"01",X"D9",X"01",
+		X"DB",X"02",X"E1",X"01",X"E9",X"01",X"E1",X"01",X"D9",X"02",X"DB",X"02",X"D9",X"01",X"80",X"01",
+		X"D9",X"02",X"D9",X"02",X"D9",X"02",X"D9",X"01",X"D9",X"01",X"D9",X"01",X"D9",X"01",X"D4",X"01",
+		X"D6",X"01",X"D1",X"01",X"D4",X"02",X"D6",X"01",X"C9",X"01",X"C9",X"01",X"CB",X"01",X"CC",X"01",
+		X"C9",X"01",X"CB",X"02",X"D1",X"01",X"C9",X"01",X"D1",X"01",X"C9",X"02",X"CB",X"02",X"C9",X"02",
+		X"80",X"00",X"02",X"80",X"01",X"C4",X"02",X"80",X"02",X"C4",X"01",X"80",X"01",X"C4",X"01",X"C8",
+		X"01",X"CB",X"05",X"C4",X"02",X"80",X"01",X"C4",X"02",X"80",X"02",X"C4",X"01",X"80",X"01",X"C4",
+		X"01",X"C8",X"01",X"CB",X"03",X"C4",X"01",X"80",X"01",X"C4",X"03",X"80",X"01",X"C5",X"01",X"80",
+		X"01",X"C4",X"01",X"80",X"01",X"C4",X"03",X"80",X"01",X"C5",X"01",X"80",X"01",X"C4",X"02",X"80",
+		X"01",X"80",X"01",X"A9",X"01",X"AC",X"01",X"B9",X"01",X"80",X"01",X"B9",X"01",X"BC",X"01",X"C9",
+		X"01",X"80",X"01",X"C9",X"01",X"CC",X"01",X"D9",X"01",X"80",X"01",X"D9",X"01",X"DC",X"01",X"E9",
+		X"02",X"D9",X"02",X"D9",X"02",X"D9",X"01",X"D9",X"01",X"D9",X"01",X"D9",X"04",X"80",X"02",X"D9",
+		X"01",X"D5",X"01",X"D5",X"01",X"80",X"01",X"D5",X"02",X"80",X"02",X"D4",X"01",X"80",X"01",X"D4",
+		X"01",X"80",X"02",X"D4",X"02",X"D4",X"01",X"80",X"01",X"C9",X"02",X"C9",X"02",X"C9",X"02",X"C9",
+		X"01",X"C9",X"01",X"C9",X"01",X"C9",X"01",X"80",X"01",X"C9",X"02",X"80",X"02",X"C9",X"01",X"C4",
+		X"01",X"C5",X"01",X"80",X"01",X"C5",X"02",X"80",X"02",X"C4",X"01",X"80",X"01",X"C4",X"01",X"80",
+		X"02",X"C4",X"02",X"C4",X"02",X"80",X"01",X"80",X"01",X"C9",X"01",X"D4",X"01",X"C9",X"01",X"D1",
+		X"02",X"D4",X"01",X"C8",X"01",X"D4",X"01",X"C8",X"01",X"CB",X"05",X"D4",X"01",X"80",X"01",X"C9",
+		X"01",X"D4",X"01",X"C9",X"01",X"D1",X"02",X"D4",X"01",X"C8",X"01",X"D4",X"01",X"C8",X"01",X"CB",
+		X"03",X"C4",X"01",X"80",X"01",X"C4",X"01",X"80",X"01",X"C9",X"01",X"CC",X"01",X"D5",X"01",X"80",
+		X"01",X"D4",X"01",X"80",X"01",X"D4",X"01",X"80",X"01",X"C9",X"01",X"CC",X"01",X"D5",X"01",X"80",
+		X"01",X"D4",X"02",X"80",X"01",X"80",X"01",X"A9",X"01",X"AC",X"01",X"B9",X"01",X"80",X"01",X"B9",
+		X"01",X"BC",X"01",X"C9",X"01",X"80",X"01",X"C9",X"01",X"CC",X"01",X"D9",X"01",X"80",X"01",X"D9");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/rom/ROM_SND_1.vhd b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/rom/ROM_SND_1.vhd
new file mode 100644
index 00000000..006afdd6
--- /dev/null
+++ b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/rom/ROM_SND_1.vhd	
@@ -0,0 +1,150 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity ROM_SND_1 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(10 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of ROM_SND_1 is
+	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"01",X"DC",X"01",X"E9",X"02",X"CC",X"02",X"CC",X"02",X"CC",X"02",X"CC",X"01",X"E9",X"01",X"E4",
+		X"01",X"E6",X"01",X"E1",X"01",X"E4",X"02",X"E6",X"01",X"D9",X"01",X"D9",X"01",X"DB",X"01",X"DC",
+		X"01",X"D9",X"01",X"DB",X"02",X"E1",X"01",X"E9",X"01",X"E1",X"01",X"D9",X"02",X"DB",X"02",X"D9",
+		X"01",X"80",X"01",X"D9",X"02",X"BC",X"02",X"BC",X"02",X"BC",X"02",X"BC",X"01",X"D9",X"01",X"D4",
+		X"01",X"D6",X"01",X"D1",X"01",X"D4",X"02",X"D6",X"01",X"C9",X"01",X"C9",X"01",X"CB",X"01",X"CC",
+		X"01",X"C9",X"01",X"CB",X"02",X"D1",X"01",X"C9",X"01",X"D1",X"01",X"C9",X"02",X"CB",X"02",X"C9",
+		X"02",X"80",X"02",X"B9",X"02",X"C1",X"02",X"C1",X"02",X"B9",X"02",X"BB",X"02",X"C2",X"02",X"C2",
+		X"02",X"B4",X"02",X"B9",X"02",X"C1",X"02",X"C1",X"02",X"B9",X"02",X"BB",X"02",X"C2",X"02",X"C2",
+		X"02",X"B4",X"04",X"B5",X"02",X"B4",X"02",X"B4",X"04",X"B5",X"02",X"B4",X"02",X"80",X"02",X"99",
+		X"02",X"80",X"02",X"A9",X"02",X"80",X"02",X"B9",X"02",X"80",X"02",X"C9",X"02",X"80",X"02",X"C9",
+		X"02",X"C9",X"02",X"C9",X"02",X"C9",X"02",X"D1",X"02",X"D1",X"02",X"D1",X"02",X"D1",X"02",X"CC",
+		X"02",X"CC",X"02",X"D1",X"02",X"D1",X"02",X"D1",X"02",X"D2",X"02",X"D1",X"02",X"80",X"02",X"B9",
+		X"02",X"B9",X"02",X"B9",X"02",X"B9",X"02",X"C1",X"02",X"C1",X"02",X"C1",X"02",X"C1",X"02",X"BC",
+		X"02",X"BC",X"02",X"C1",X"02",X"C1",X"02",X"C1",X"02",X"C2",X"02",X"C1",X"02",X"80",X"02",X"A9",
+		X"02",X"B9",X"02",X"B9",X"02",X"A9",X"02",X"AB",X"02",X"B8",X"02",X"B8",X"02",X"A4",X"02",X"A9",
+		X"02",X"B9",X"02",X"B9",X"02",X"A9",X"02",X"AB",X"02",X"B8",X"02",X"B8",X"02",X"A4",X"04",X"A5",
+		X"02",X"A4",X"02",X"A4",X"04",X"A5",X"02",X"A4",X"02",X"80",X"02",X"99",X"02",X"80",X"02",X"A9",
+		X"02",X"80",X"02",X"B9",X"02",X"80",X"02",X"C9",X"02",X"80",X"02",X"C6",X"02",X"C6",X"02",X"C6",
+		X"02",X"C6",X"02",X"C9",X"02",X"C9",X"02",X"C9",X"02",X"C9",X"02",X"C9",X"02",X"C9",X"02",X"C9",
+		X"02",X"C9",X"02",X"C9",X"02",X"C8",X"02",X"C9",X"02",X"80",X"02",X"B6",X"02",X"B6",X"02",X"B6",
+		X"02",X"B6",X"02",X"C9",X"02",X"C9",X"02",X"C9",X"02",X"C9",X"02",X"C9",X"02",X"C9",X"02",X"C9",
+		X"02",X"C9",X"02",X"B9",X"02",X"B8",X"02",X"B9",X"02",X"A0",X"02",X"80",X"02",X"B4",X"02",X"B4",
+		X"02",X"80",X"02",X"80",X"02",X"B4",X"02",X"B4",X"02",X"80",X"02",X"80",X"02",X"B4",X"02",X"B4",
+		X"02",X"80",X"02",X"80",X"02",X"B4",X"02",X"B4",X"02",X"80",X"08",X"80",X"08",X"80",X"08",X"80",
+		X"08",X"80",X"02",X"C3",X"02",X"C3",X"02",X"C3",X"02",X"C3",X"02",X"C4",X"02",X"C4",X"02",X"C4",
+		X"02",X"C4",X"02",X"C5",X"02",X"C5",X"02",X"C4",X"02",X"C4",X"02",X"C4",X"02",X"C4",X"04",X"80",
+		X"02",X"B3",X"02",X"B3",X"02",X"B3",X"02",X"B3",X"02",X"B4",X"02",X"B4",X"02",X"B4",X"02",X"B4",
+		X"02",X"B5",X"02",X"B5",X"02",X"B4",X"02",X"B4",X"02",X"B4",X"02",X"B4",X"04",X"80",X"18",X"03",
+		X"03",X"03",X"03",X"03",X"03",X"19",X"FF",X"0F",X"FF",X"0F",X"FF",X"0F",X"1A",X"FF",X"0F",X"FF",
+		X"0F",X"FF",X"0F",X"22",X"D7",X"09",X"10",X"10",X"6C",X"0E",X"0A",X"1B",X"0A",X"27",X"0A",X"33",
+		X"0A",X"3F",X"0A",X"41",X"0A",X"08",X"18",X"03",X"03",X"03",X"03",X"03",X"03",X"19",X"FF",X"0F",
+		X"FF",X"0F",X"FF",X"0F",X"1A",X"FF",X"0F",X"FF",X"0F",X"FF",X"0F",X"22",X"FF",X"09",X"10",X"10",
+		X"6C",X"0E",X"0A",X"1B",X"0A",X"27",X"0A",X"33",X"0A",X"3F",X"0A",X"41",X"0A",X"03",X"02",X"B1",
+		X"02",X"B5",X"02",X"B8",X"04",X"C1",X"02",X"B8",X"04",X"C1",X"00",X"02",X"B8",X"02",X"C1",X"02",
+		X"C5",X"04",X"C8",X"02",X"C5",X"04",X"C8",X"02",X"B5",X"02",X"B8",X"02",X"C1",X"04",X"C5",X"02",
+		X"C1",X"04",X"C5",X"02",X"C8",X"02",X"D1",X"02",X"D5",X"04",X"D8",X"02",X"D5",X"04",X"D8",X"10",
+		X"80",X"10",X"80",X"19",X"A0",X"00",X"F0",X"00",X"40",X"01",X"1D",X"07",X"09",X"07",X"1E",X"00",
+		X"00",X"00",X"07",X"0F",X"00",X"05",X"81",X"13",X"05",X"81",X"10",X"19",X"A0",X"00",X"F0",X"00",
+		X"40",X"01",X"1D",X"03",X"04",X"03",X"1E",X"00",X"00",X"00",X"07",X"0F",X"00",X"05",X"81",X"13",
+		X"05",X"81",X"10",X"19",X"12",X"00",X"15",X"00",X"20",X"00",X"1D",X"0D",X"0F",X"0D",X"1E",X"00",
+		X"00",X"00",X"07",X"05",X"00",X"05",X"81",X"13",X"05",X"81",X"10",X"18",X"03",X"03",X"03",X"03",
+		X"03",X"03",X"06",X"00",X"00",X"81",X"19",X"FF",X"0F",X"FF",X"0F",X"FF",X"0F",X"1A",X"FF",X"0F",
+		X"FF",X"0F",X"FF",X"0F",X"22",X"A8",X"0A",X"10",X"08",X"55",X"E3",X"0A",X"EE",X"0A",X"F2",X"0A",
+		X"F6",X"0A",X"FA",X"0A",X"FE",X"0A",X"0A",X"18",X"03",X"03",X"03",X"03",X"03",X"03",X"06",X"00",
+		X"00",X"81",X"19",X"FF",X"0F",X"FF",X"0F",X"FF",X"0F",X"1A",X"FF",X"0F",X"FF",X"0F",X"FF",X"0F",
+		X"22",X"D4",X"0A",X"10",X"08",X"55",X"E3",X"0A",X"EE",X"0A",X"F2",X"0A",X"F6",X"0A",X"FA",X"0A",
+		X"FE",X"0A",X"04",X"02",X"C1",X"04",X"C3",X"02",X"BC",X"02",X"C1",X"06",X"C3",X"00",X"08",X"80",
+		X"08",X"80",X"08",X"80",X"08",X"80",X"08",X"80",X"08",X"80",X"08",X"80",X"08",X"80",X"08",X"80",
+		X"08",X"80",X"18",X"03",X"03",X"03",X"03",X"03",X"03",X"19",X"FF",X"0F",X"FF",X"0F",X"FF",X"0F",
+		X"1A",X"FF",X"0F",X"FF",X"0F",X"FF",X"0F",X"22",X"1C",X"0B",X"02",X"FB",X"48",X"1E",X"54",X"0B",
+		X"E1",X"0C",X"1B",X"0E",X"54",X"0B",X"E1",X"0C",X"1B",X"0E",X"07",X"18",X"03",X"03",X"03",X"03",
+		X"03",X"03",X"19",X"FF",X"0F",X"FF",X"0F",X"FF",X"0F",X"1A",X"FF",X"0F",X"FF",X"0F",X"FF",X"0F",
+		X"22",X"45",X"0B",X"02",X"FB",X"48",X"1E",X"54",X"0B",X"E1",X"0C",X"1B",X"0E",X"54",X"0B",X"E1",
+		X"0C",X"1B",X"0E",X"03",X"06",X"D1",X"06",X"C8",X"06",X"D4",X"06",X"D4",X"06",X"D1",X"06",X"D8",
+		X"12",X"D8",X"12",X"C8",X"06",X"D1",X"06",X"D3",X"06",X"D4",X"06",X"D6",X"06",X"D8",X"06",X"D9",
+		X"06",X"CC",X"06",X"D9",X"06",X"D8",X"06",X"D6",X"06",X"D4",X"06",X"D3",X"12",X"D4",X"18",X"D1",
+		X"06",X"CC",X"06",X"D1",X"06",X"D3",X"06",X"D4",X"06",X"D6",X"06",X"D4",X"06",X"D6",X"06",X"D4",
+		X"06",X"D3",X"06",X"D4",X"06",X"D1",X"24",X"D8",X"0C",X"80",X"06",X"D8",X"0C",X"D1",X"06",X"D4",
+		X"0C",X"C6",X"18",X"80",X"0C",X"80",X"06",X"D6",X"0C",X"CB",X"06",X"D3",X"0C",X"C4",X"18",X"80",
+		X"02",X"D4",X"02",X"D6",X"02",X"D4",X"02",X"D6",X"02",X"D4",X"02",X"D6",X"02",X"D4",X"02",X"D6",
+		X"02",X"D4",X"02",X"D6",X"02",X"D4",X"02",X"D6",X"02",X"D4",X"02",X"D6",X"02",X"D4",X"02",X"D6",
+		X"02",X"D4",X"02",X"D6",X"02",X"D4",X"02",X"D6",X"02",X"D4",X"02",X"D6",X"02",X"D4",X"02",X"D6",
+		X"02",X"D4",X"02",X"D6",X"02",X"D4",X"02",X"D6",X"02",X"D4",X"02",X"D6",X"02",X"D4",X"02",X"D6",
+		X"02",X"D4",X"02",X"D6",X"02",X"D4",X"02",X"D6",X"02",X"D4",X"02",X"D6",X"02",X"D4",X"02",X"D6",
+		X"02",X"D4",X"02",X"D6",X"06",X"D6",X"18",X"D3",X"03",X"D8",X"03",X"D6",X"03",X"D4",X"03",X"D3",
+		X"03",X"D1",X"03",X"D3",X"03",X"D1",X"03",X"CB",X"03",X"CA",X"03",X"C8",X"06",X"C7",X"03",X"DA",
+		X"03",X"D8",X"03",X"D7",X"03",X"D5",X"03",X"D3",X"03",X"D4",X"03",X"D3",X"03",X"D1",X"03",X"CB",
+		X"03",X"CA",X"24",X"CB",X"12",X"CA",X"12",X"D7",X"12",X"D8",X"12",X"80",X"24",X"80",X"06",X"C8",
+		X"06",X"C3",X"06",X"CB",X"06",X"CB",X"06",X"C8",X"06",X"D3",X"12",X"D3",X"12",X"C3",X"06",X"C8",
+		X"06",X"CA",X"06",X"CB",X"06",X"D1",X"06",X"D3",X"06",X"D4",X"06",X"C7",X"06",X"D4",X"06",X"D3",
+		X"06",X"D1",X"06",X"CB",X"06",X"CA",X"0C",X"CB",X"18",X"80",X"03",X"80",X"03",X"C8",X"03",X"CA",
+		X"03",X"CB",X"03",X"D1",X"03",X"D3",X"03",X"D4",X"03",X"D6",X"03",X"D4",X"03",X"D3",X"03",X"D1",
+		X"03",X"CB",X"0C",X"CA",X"18",X"80",X"03",X"80",X"03",X"C6",X"03",X"C8",X"03",X"CA",X"03",X"CB",
+		X"03",X"D1",X"03",X"D3",X"03",X"D4",X"03",X"D3",X"03",X"D1",X"03",X"CB",X"03",X"CA",X"0C",X"C8",
+		X"12",X"80",X"06",X"C8",X"0C",X"C6",X"12",X"80",X"06",X"C8",X"0C",X"C4",X"12",X"80",X"06",X"C6",
+		X"0C",X"C3",X"06",X"D3",X"1E",X"CB",X"06",X"D4",X"12",X"D1",X"12",X"80",X"18",X"CB",X"06",X"CA",
+		X"06",X"C8",X"12",X"C7",X"06",X"C8",X"06",X"C3",X"06",X"CB",X"06",X"CB",X"06",X"C8",X"06",X"D2",
+		X"24",X"D2",X"06",X"80",X"06",X"CB",X"06",X"D5",X"06",X"D5",X"06",X"D1",X"06",X"D8",X"24",X"D9",
+		X"00",X"48",X"80",X"48",X"80",X"06",X"C1",X"06",X"B8",X"06",X"C4",X"06",X"C4",X"06",X"C1",X"06",
+		X"C8",X"12",X"C8",X"12",X"B8",X"06",X"C1",X"06",X"C3",X"06",X"C4",X"06",X"C6",X"06",X"C8",X"06",
+		X"C9",X"06",X"BC",X"06",X"C9",X"06",X"C8",X"06",X"C6",X"06",X"C4",X"06",X"C3",X"0C",X"C4",X"1B",
+		X"80",X"03",X"C1",X"03",X"C3",X"03",X"C4",X"03",X"C6",X"03",X"C8",X"03",X"C9",X"03",X"CB",X"03",
+		X"C9",X"03",X"C8",X"03",X"C6",X"03",X"C4",X"0C",X"C3",X"1B",X"80",X"03",X"BB",X"03",X"C1",X"03",
+		X"C3",X"03",X"C4",X"03",X"C6",X"03",X"C8",X"03",X"C9",X"03",X"C8",X"03",X"C6",X"03",X"C4",X"03",
+		X"C3",X"0C",X"C1",X"12",X"80",X"06",X"D1",X"1E",X"CB",X"06",X"D1",X"1E",X"C9",X"06",X"CB",X"0C",
+		X"C8",X"18",X"80",X"48",X"80",X"06",X"C7",X"06",X"C5",X"06",X"C3",X"06",X"D1",X"06",X"CB",X"06",
+		X"CA",X"06",X"CB",X"06",X"D1",X"06",X"CB",X"06",X"CA",X"06",X"CB",X"06",X"C8",X"06",X"D3",X"06",
+		X"D1",X"06",X"CB",X"06",X"CA",X"06",X"C8",X"06",X"C7",X"0C",X"C8",X"06",X"80",X"0C",X"C3",X"06",
+		X"80",X"0C",X"CA",X"06",X"80",X"0C",X"C7",X"06",X"80",X"0C",X"C8",X"18",X"80",X"2A",X"80",X"06",
+		X"C3",X"06",X"CB",X"06",X"CB",X"06",X"C8",X"06",X"D3",X"0C",X"C4",X"18",X"80",X"06",X"C6",X"06",
+		X"C1",X"06",X"CA",X"06",X"CA",X"06",X"C6",X"06",X"D1",X"0C",X"C3",X"18",X"80",X"06",X"C4",X"06",
+		X"BB",X"06",X"C8",X"06",X"C8",X"06",X"C4",X"06",X"CB",X"06",X"C3",X"06",X"BB",X"06",X"C6",X"06",
+		X"C6",X"06",X"C3",X"06",X"CB",X"06",X"C1",X"06",X"C3",X"06",X"C4",X"06",X"C6",X"06",X"C8",X"06",
+		X"CA",X"0C",X"BB",X"12",X"80",X"06",X"C8",X"1E",X"C4",X"06",X"CA",X"06",X"C7",X"03",X"D3",X"03",
+		X"D1",X"03",X"CB",X"03",X"CA",X"03",X"C8",X"03",X"CA",X"03",X"C8",X"03",X"C6",X"03",X"C4",X"03",
+		X"C3",X"18",X"C4",X"06",X"BA",X"06",X"C1",X"0C",X"BB",X"24",X"80",X"06",X"CB",X"0C",X"C8",X"06",
+		X"CB",X"0C",X"C5",X"1B",X"80",X"03",X"D6",X"03",X"D4",X"03",X"D2",X"03",X"D1",X"03",X"CB",X"03",
+		X"C9",X"03",X"CB",X"03",X"C9",X"03",X"C8",X"03",X"C6",X"03",X"C4",X"12",X"B1",X"12",X"C1",X"06",
+		X"BC",X"06",X"BA",X"06",X"B8",X"06",X"C6",X"06",X"C4",X"06",X"C3",X"0C",X"C4",X"06",X"C1",X"0C",
+		X"B9",X"06",X"B6",X"0C",X"B8",X"06",X"BA",X"0C",X"BC",X"06",X"B8",X"0C",X"C1",X"3C",X"80",X"48",
+		X"80",X"06",X"C1",X"06",X"B8",X"06",X"C4",X"06",X"C4",X"06",X"C1",X"06",X"C8",X"0C",X"B9",X"18",
+		X"80",X"06",X"BB",X"06",X"B6",X"06",X"C3",X"06",X"C3",X"06",X"BB",X"06",X"C6",X"0C",X"B8",X"18",
+		X"80",X"06",X"B9",X"06",X"B4",X"06",X"C1",X"06",X"C1",X"06",X"B9",X"06",X"C4",X"06",X"B8",X"06",
+		X"B4",X"06",X"BB",X"06",X"BB",X"06",X"B8",X"06",X"C4",X"06",X"B6",X"06",X"B8",X"06",X"B9",X"06",
+		X"BB",X"06",X"C1",X"06",X"C3",X"12",X"B4",X"12",X"C4",X"12",X"C3",X"12",X"B7",X"06",X"B8",X"06",
+		X"B3",X"06",X"BB",X"06",X"BB",X"06",X"B8",X"06",X"C3",X"12",X"C3",X"12",X"B3",X"06",X"B8",X"06",
+		X"BA",X"06",X"BB",X"06",X"C1",X"06",X"C3",X"06",X"C4",X"06",X"B7",X"06",X"C4",X"06",X"C3",X"06",
+		X"C1",X"06",X"BB",X"06",X"BA",X"12",X"BB",X"12",X"B8",X"06",X"80",X"06",X"B7",X"06",X"B8",X"06",
+		X"BA",X"06",X"BB",X"06",X"C1",X"06",X"BB",X"06",X"C1",X"06",X"BB",X"06",X"BA",X"06",X"BB",X"06",
+		X"B8",X"06",X"C3",X"06",X"C1",X"06",X"BB",X"06",X"BA",X"06",X"B8",X"06",X"B7",X"0C",X"B8",X"06",
+		X"C3",X"0C",X"B8",X"06",X"BB",X"0C",X"B1",X"24",X"80",X"06",X"C1",X"0C",X"B6",X"06",X"BA",X"0C",
+		X"AB",X"18",X"80",X"02",X"AB",X"02",X"B1",X"02",X"AB",X"02",X"B1",X"02",X"AB",X"02",X"B1",X"02",
+		X"AB",X"02",X"B1",X"02",X"AB",X"02",X"B1",X"02",X"AB",X"02",X"B1",X"02",X"AB",X"02",X"B1",X"02",
+		X"AB",X"02",X"B1",X"02",X"AB",X"02",X"B1",X"02",X"AB",X"02",X"B1",X"02",X"AB",X"02",X"B1",X"02",
+		X"AB",X"02",X"B1",X"02",X"AB",X"02",X"B1",X"02",X"AB",X"02",X"B1",X"02",X"AB",X"02",X"B1",X"02",
+		X"AB",X"02",X"B1",X"02",X"AB",X"02",X"B1",X"02",X"AB",X"02",X"B1",X"02",X"AB",X"02",X"B1",X"02",
+		X"AB",X"02",X"B1",X"02",X"AB",X"02",X"B1",X"02",X"AB",X"02",X"B1",X"02",X"AB",X"12",X"AA",X"06",
+		X"80",X"03",X"B3",X"03",X"B1",X"03",X"AB",X"03",X"AA",X"03",X"A8",X"03",X"AA",X"03",X"A8",X"03",
+		X"A6",X"03",X"A4",X"03",X"A3",X"06",X"A1",X"03",X"B4",X"03",X"B3",X"03",X"B1",X"03",X"AB",X"03",
+		X"AA",X"03",X"AB",X"03",X"AA",X"03",X"A8",X"03",X"A7",X"03",X"A5",X"12",X"A3",X"09",X"80",X"03",
+		X"A8",X"03",X"AA",X"03",X"AB",X"03",X"B1",X"03",X"AB",X"03",X"B1",X"03",X"B3",X"03",X"B4",X"03",
+		X"B1",X"03",X"B3",X"03",X"B4",X"03",X"B3",X"03",X"B1",X"03",X"AB",X"03",X"AA",X"0C",X"A8",X"1E",
+		X"80",X"03",X"BB",X"03",X"B9",X"03",X"B8",X"03",X"B6",X"03",X"B5",X"03",X"B6",X"03",X"B5",X"03",
+		X"B3",X"03",X"B1",X"03",X"AB",X"03",X"A9",X"03",X"B6",X"03",X"B5",X"03",X"B3",X"03",X"B1",X"03",
+		X"AB",X"03",X"A9",X"03",X"AB",X"03",X"A9",X"03",X"A8",X"03",X"A6",X"03",X"A5",X"0C",X"A6",X"18",
+		X"80",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/scramble.vhd b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/scramble.vhd
new file mode 100644
index 00000000..a411b0eb
--- /dev/null
+++ b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/scramble.vhd	
@@ -0,0 +1,471 @@
+--
+-- A simulation model of Scramble hardware
+-- Copyright (c) MikeJ - Feb 2007
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- You are responsible for any legal issues arising from your use of this code.
+--
+-- The latest version of this file can be found at: www.fpgaarcade.com
+--
+-- Email support@fpgaarcade.com
+--
+-- Revision list
+--
+-- version 001 initial release
+--
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_arith.all;
+  use ieee.std_logic_unsigned.all;
+
+entity scramble is
+  port (
+    --
+    O_VIDEO_R             : out   std_logic_vector(3 downto 0);
+    O_VIDEO_G             : out   std_logic_vector(3 downto 0);
+    O_VIDEO_B             : out   std_logic_vector(3 downto 0);
+    O_HSYNC               : out   std_logic;
+    O_VSYNC               : out   std_logic;
+    O_HBLANK              : out   std_logic;
+    O_VBLANK              : out   std_logic;
+    --
+    -- to audio board
+    --
+    O_ADDR                : out   std_logic_vector(15 downto 0);
+    O_DATA                : out   std_logic_vector( 7 downto 0);
+    I_DATA                : in    std_logic_vector( 7 downto 0);
+    I_DATA_OE_L           : in    std_logic;
+    O_RD_L                : out   std_logic;
+    O_WR_L                : out   std_logic;
+    O_IOPC7               : out   std_logic;
+    O_RESET_WD_L          : out   std_logic;
+    --
+    ENA                   : in    std_logic;
+    ENAB                  : in    std_logic;
+    ENA_12                : in    std_logic;
+    --
+    RESET                 : in    std_logic; -- active high
+    CLK                   : in    std_logic
+    );
+end;
+
+architecture RTL of scramble is
+
+    type  array_4x8   is array (0 to 3) of std_logic_vector(7 downto 0);
+    -- timing
+    signal hcnt             : std_logic_vector(8 downto 0) := "010000000"; -- 80
+    signal vcnt             : std_logic_vector(8 downto 0) := "011111000"; -- 0F8
+
+    signal reset_wd_l       : std_logic;
+
+    -- timing decode
+    signal do_hsync         : boolean;
+    signal set_vblank       : boolean;
+    signal vsync            : std_logic;
+    signal hsync            : std_logic;
+    signal vblank           : std_logic;
+    signal hblank           : std_logic;
+    --
+    -- cpu
+    signal cpu_ena          : std_logic;
+    signal cpu_mreq_l       : std_logic;
+    signal cpu_rd_l         : std_logic;
+    signal cpu_wr_l         : std_logic;
+    signal cpu_rfsh_l       : std_logic;
+    signal cpu_wait_l       : std_logic;
+    signal cpu_int_l        : std_logic;
+    signal cpu_nmi_l        : std_logic;
+    signal cpu_busrq_l      : std_logic;
+    signal cpu_addr         : std_logic_vector(15 downto 0);
+    signal cpu_data_out     : std_logic_vector(7 downto 0);
+    signal cpu_data_in      : std_logic_vector(7 downto 0);
+
+    signal page_4to7_l      : std_logic;
+
+    signal wren             : std_logic;
+
+    signal objen_l          : std_logic;
+    signal waen_l           : std_logic;
+
+    signal objramrd_l       : std_logic;
+    signal vramrd_l         : std_logic;
+
+    signal select_l         : std_logic;
+    signal objramwr_l       : std_logic;
+    signal vramwr_l         : std_logic;
+
+    -- control reg
+    signal control_reg      : std_logic_vector(7 downto 0);
+    signal intst_l          : std_logic;
+    signal iopc7            : std_logic;
+    signal pout1            : std_logic;
+    signal starson          : std_logic;
+    signal hcma             : std_logic;
+    signal vcma             : std_logic;
+
+    signal pgm_rom_dout     : array_4x8;
+    signal rom_dout         : std_logic_vector(7 downto 0);
+    signal ram_dout         : std_logic_vector(7 downto 0);
+    signal ram_ena          : std_logic;
+
+    signal vram_data        : std_logic_vector(7 downto 0);
+
+begin
+
+  O_HBLANK <= hblank;
+  O_VBLANK <= vblank;
+
+  --
+  -- video timing
+  --
+  p_hvcnt : process
+    variable hcarry,vcarry : boolean;
+  begin
+    wait until rising_edge(CLK);
+    if (ENA = '1') then
+      hcarry := (hcnt = "111111111");
+      if hcarry then
+        hcnt <= "010000000"; -- 080
+      else
+        hcnt <= hcnt +"1";
+      end if;
+      -- hcnt 8 on circuit is 256H_L
+      vcarry := (vcnt = "111111111");
+      if do_hsync then
+        if vcarry then
+          vcnt <= "011111000"; -- 0F8
+        else
+          vcnt <= vcnt +"1";
+        end if;
+      end if;
+    end if;
+  end process;
+
+  p_sync_comb : process(hcnt, vcnt)
+  begin
+    vsync <= not vcnt(8);
+    do_hsync <= (hcnt = "010101111"); -- 0AF
+    set_vblank <= (vcnt = "111101111"); -- 1EF
+  end process;
+
+  p_sync : process
+  begin
+    wait until rising_edge(CLK);
+    -- Timing hardware is coded differently to the real hw
+    -- to avoid the use of multiple clocks. Result is identical.
+    if (ENA = '1') then
+      if (hcnt = "010000001") then -- 081
+        hblank <= '1';
+      elsif (hcnt = "011111111") then -- 0f9
+        hblank <= '0';
+      end if;
+
+      if do_hsync then
+        hsync <= '1';
+      elsif (hcnt = "011001111") then -- 0CF
+        hsync <= '0';
+      end if;
+
+      if do_hsync then
+        if set_vblank then -- 1EF
+          vblank <= '1';
+        elsif (vcnt = "100001111") then -- 10F
+          vblank <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  p_video_timing_reg : process
+  begin
+    wait until rising_edge(CLK);
+    -- match output delay in video module
+    if (ENA = '1') then
+      O_HSYNC     <= HSYNC;
+      O_VSYNC     <= VSYNC;
+    end if;
+  end process;
+
+  p_cpu_ena : process(hcnt, ENA)
+  begin
+    -- cpu clocked on rising edge of 1h, late
+    cpu_ena <= ENA and hcnt(0); -- 1h
+  end process;
+  --
+  -- video
+  --
+  u_video : entity work.scramble_video
+    port map (
+      --
+      I_HCNT          => hcnt,
+      I_VCNT          => vcnt,
+      I_VBLANK        => vblank,
+      I_VSYNC         => vsync,
+
+      I_VCMA          => vcma,
+      I_HCMA          => hcma,
+      --
+      I_CPU_ADDR      => cpu_addr,
+      I_CPU_DATA      => cpu_data_out,
+      O_VRAM_DATA     => vram_data,
+      -- note, looks like the real hardware cannot read from object ram
+      --
+      I_VRAMWR_L      => vramwr_l,
+      I_VRAMRD_L      => vramrd_l,
+      I_OBJRAMWR_L    => objramwr_l,
+      I_OBJRAMRD_L    => objramrd_l,
+      I_OBJEN_L       => objen_l,
+      --
+      I_STARSON       => starson,
+      I_POUT1         => pout1,
+      --
+      O_VIDEO_R       => O_VIDEO_R,
+      O_VIDEO_G       => O_VIDEO_G,
+      O_VIDEO_B       => O_VIDEO_B,
+      --
+      ENA             => ENA,
+      ENAB            => ENAB,
+      ENA_12          => ENA_12,
+      CLK             => CLK
+      );
+
+  -- other cpu signals
+  reset_wd_l <= not RESET; -- FIX
+
+  p_cpu_wait : process(vblank, hblank, waen_l)
+  begin
+    -- this is done a bit differently, the original had a late
+    -- clock to the cpu, and as mreq came out a litle early it could assert
+    -- wait and then gate off the write strobe to vram/objram in time.
+    --
+    -- we are a nice synchronous system therefore we need to do this combinatorially.
+    -- timing is still ok.
+    --
+    if (vblank = '1') then
+      cpu_wait_l <='1';
+    else
+      cpu_wait_l <= '1';
+      if (hblank = '0') and (waen_l = '0') then
+        cpu_wait_l <= '0';
+      end if;
+    end if;
+  end process;
+  wren <= cpu_wait_l;
+
+  p_cpu_int : process
+  begin
+    wait until rising_edge(CLK);
+    if (ENA = '1') then
+      if (intst_l = '0') then
+        cpu_nmi_l <= '1';
+      else
+        if do_hsync and set_vblank then
+          cpu_nmi_l <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  u_cpu : entity work.T80sed
+          port map (
+              RESET_n => reset_wd_l,
+              CLK_n   => clk,
+              CLKEN   => cpu_ena,
+              WAIT_n  => cpu_wait_l,
+              INT_n   => cpu_int_l,
+              NMI_n   => cpu_nmi_l,
+              BUSRQ_n => cpu_busrq_l,
+              M1_n    => open,
+              MREQ_n  => cpu_mreq_l,
+              IORQ_n  => open,
+              RD_n    => cpu_rd_l,
+              WR_n    => cpu_wr_l,
+              RFSH_n  => cpu_rfsh_l,
+              HALT_n  => open,
+              BUSAK_n => open,
+              A       => cpu_addr,
+              DI      => cpu_data_in,
+              DO      => cpu_data_out
+              );
+  --
+  -- primary addr decode
+  --
+  p_mem_decode : process(cpu_rfsh_l, cpu_rd_l, cpu_wr_l, cpu_mreq_l, cpu_addr)
+  begin
+    cpu_int_l   <= '1';
+    cpu_busrq_l <= '1';
+
+    page_4to7_l <= '1';
+    if (cpu_mreq_l = '0') and (cpu_rfsh_l = '1') then
+      if (cpu_addr(15 downto 14) = "10") then page_4to7_l <= '0'; end if;
+    end if;
+
+  end process;
+
+  p_mem_decode2 : process(cpu_addr, page_4to7_l, cpu_rfsh_l, cpu_rd_l, cpu_wr_l, wren)
+  begin
+    waen_l <= '1';
+    objen_l <= '1';
+    if (page_4to7_l = '0') and (cpu_rfsh_l = '1') then
+      if (cpu_addr(13 downto 11) = "001") then waen_l <= '0'; end if;
+      if (cpu_addr(13 downto 11) = "010") then objen_l <= '0'; end if;
+    end if;
+
+    -- read decode
+    vramrd_l <= '1';
+    objramrd_l <= '1';
+
+	 if (page_4to7_l = '0') and (cpu_rd_l = '0') then
+	   if (cpu_addr(13 downto 11) = "001") then vramrd_l <= '0'; end if;
+	   if (cpu_addr(13 downto 11) = "010") then objramrd_l <= '0'; end if;
+	 end if;
+
+    -- write decode
+    vramwr_l <= '1';
+    objramwr_l <= '1';
+    select_l <= '1';
+
+    if (page_4to7_l = '0') and (cpu_wr_l = '0') and (wren = '1') then
+      if (cpu_addr(13 downto 11) = "001") then vramwr_l <= '0'; end if;
+      if (cpu_addr(13 downto 11) = "010") then objramwr_l <= '0'; end if;
+      if (cpu_addr(13 downto 11) = "101") then select_l <= '0'; end if; -- control reg
+    end if;
+  end process;
+
+  p_control_reg : process
+    variable addr : std_logic_vector(2 downto 0);
+    variable dec : std_logic_vector(7 downto 0);
+  begin
+     wait until rising_edge(CLK);
+     if (ENA = '1') then
+      addr := cpu_addr(2 downto 0);
+      dec := "00000000";
+      if (select_l = '0') then
+        case addr(2 downto 0) is
+          when "000" => dec := "00000001";
+          when "001" => dec := "00000010";
+          when "010" => dec := "00000100";
+          when "011" => dec := "00001000";
+          when "100" => dec := "00010000";
+          when "101" => dec := "00100000";
+          when "110" => dec := "01000000";
+          when "111" => dec := "10000000";
+          when others => null;
+        end case;
+      end if;
+      if (reset_wd_l = '0') then
+        control_reg <= (others => '0');
+      else
+        for i in 0 to 7 loop
+          if (dec(i) = '1') then
+            control_reg(i) <= cpu_data_out(0);
+          end if;
+        end loop;
+      end if;
+    end if;
+  end process;
+
+  p_control_reg_assign : process(control_reg)
+  begin
+    intst_l <= control_reg(1);
+    iopc7   <= control_reg(2);
+    pout1   <= control_reg(3);
+    starson <= control_reg(4);
+    hcma    <= control_reg(6);
+    vcma    <= control_reg(7);
+  end process;
+
+  	pgm_rom : entity work.ROM_PGM
+	port map(
+		clk   	=> CLK,
+		addr 		=> cpu_addr(12 downto 0),
+		data     => rom_dout
+	);
+	
+	u_cpu_ram : work.dpram generic map (11,8)
+	port map
+	(
+		clk_a_i  => clk,
+		en_a_i   => ena,
+		we_i     => ram_ena and (not cpu_wr_l),
+
+      addr_a_i => cpu_addr(10 downto 0),
+		data_a_i => cpu_data_out,
+
+		clk_b_i  => clk,
+      addr_b_i => cpu_addr(10 downto 0),
+		data_b_o => ram_dout
+	);
+
+  p_ram_ctrl : process(cpu_addr, page_4to7_l)
+  begin
+    ram_ena <= '0';
+    if (page_4to7_l = '0') and (cpu_addr(13 downto 11) = "000") then
+      ram_ena <= '1';
+    end if;
+  end process;
+
+  p_cpu_data_in_mux : process(cpu_addr, cpu_rd_l, cpu_mreq_l, cpu_rfsh_l, ram_dout, rom_dout, vramrd_l, vram_data, I_DATA_OE_L, I_DATA )
+    variable ram_addr : std_logic_vector(1 downto 0);
+  begin
+		ram_addr := "10";
+    cpu_data_in <= (others => '0');
+    if    (vramrd_l = '0') then
+      cpu_data_in <= vram_data;
+    --
+    elsif (I_DATA_OE_L = '0') then
+      cpu_data_in <= I_DATA;
+    --
+    elsif (cpu_mreq_l = '0') and (cpu_rfsh_l = '1') then
+      if (cpu_addr(15) = '0') and (cpu_rd_l = '0') then
+        cpu_data_in <= rom_dout;
+      --
+      elsif (cpu_addr(15 downto 14) = ram_addr) then
+        if (cpu_addr(13 downto 11) = "000") and (cpu_rd_l = '0') then
+          cpu_data_in <= ram_dout;
+        else
+          cpu_data_in <= x"FF";
+        end if;
+      end if;
+    else
+      cpu_data_in <= x"FF";
+    end if;
+
+  end process;
+
+  -- to audio
+  O_ADDR                <= cpu_addr;
+  O_DATA                <= cpu_data_out;
+  O_RD_L                <= cpu_rd_l;
+  O_WR_L                <= cpu_wr_l;
+  O_IOPC7               <= iopc7;
+  O_RESET_WD_L          <= reset_wd_l;
+
+end RTL;
diff --git a/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/scramble_audio.vhd b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/scramble_audio.vhd
new file mode 100644
index 00000000..52ac6e13
--- /dev/null
+++ b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/scramble_audio.vhd	
@@ -0,0 +1,788 @@
+--
+-- A simulation model of Scramble hardware
+-- Copyright (c) MikeJ - Feb 2007
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- You are responsible for any legal issues arising from your use of this code.
+--
+-- The latest version of this file can be found at: www.fpgaarcade.com
+--
+-- Email support@fpgaarcade.com
+--
+-- Revision list
+--
+-- version 001 initial release
+--
+
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_arith.all;
+  use ieee.std_logic_unsigned.all;
+
+entity scramble_audio is
+  port (
+    --
+    I_ADDR             : in    std_logic_vector(15 downto 0);
+    I_DATA             : in    std_logic_vector( 7 downto 0);
+    O_DATA             : out   std_logic_vector( 7 downto 0);
+    O_DATA_OE_L        : out   std_logic;
+    --
+    I_RD_L             : in    std_logic;
+    I_WR_L             : in    std_logic;
+    I_IOPC7            : in    std_logic;
+    --
+    O_AUDIO            : out   std_logic_vector( 9 downto 0);
+    --
+    I_1P_CTRL          : in    std_logic_vector( 6 downto 0); -- start, shoot1, shoot2, left,right,up,down
+    I_2P_CTRL          : in    std_logic_vector( 6 downto 0); -- start, shoot1, shoot2, left,right,up,down
+    I_SERVICE          : in    std_logic;
+    I_COIN1            : in    std_logic;
+    I_COIN2            : in    std_logic;
+    O_COIN_COUNTER     : out   std_logic;
+    --
+    I_DIP              : in    std_logic_vector( 4 downto 0);
+
+    --
+    I_RESET_L          : in    std_logic;
+    ENA                : in    std_logic; -- 6 MHz
+    ENA_1_79           : in    std_logic; -- 1.78975 MHz
+    CLK                : in    std_logic
+    );
+end;
+
+architecture RTL of scramble_audio is
+
+  signal reset : std_logic;
+  signal cpu_ena            : std_logic;
+  signal cpu_ena_gated      : std_logic;
+  --
+  signal cpu_m1_l           : std_logic;
+  signal cpu_mreq_l         : std_logic;
+  signal cpu_iorq_l         : std_logic;
+  signal cpu_rd_l           : std_logic;
+  signal cpu_wr_l           : std_logic;
+  signal cpu_rfsh_l         : std_logic;
+  signal cpu_wait_l         : std_logic;
+  signal cpu_int_l          : std_logic;
+  signal cpu_nmi_l          : std_logic;
+  signal cpu_busrq_l        : std_logic;
+  signal cpu_addr           : std_logic_vector(15 downto 0);
+  signal cpu_data_out       : std_logic_vector(7 downto 0);
+  signal cpu_data_in        : std_logic_vector(7 downto 0);
+  --
+  signal ram_cs             : std_logic;
+  signal rom_oe             : std_logic;
+  signal filter_load        : std_logic;
+  signal filter_reg         : std_logic_vector(11 downto 0);
+  --
+  signal cpu_rom0_dout      : std_logic_vectoR(7 downto 0);
+  signal cpu_rom1_dout      : std_logic_vectoR(7 downto 0);
+  signal cpu_rom2_dout      : std_logic_vectoR(7 downto 0);
+  signal rom_active         : std_logic;
+
+  signal rom_dout           : std_logic_vector(7 downto 0);
+  signal ram_dout           : std_logic_vector(7 downto 0);
+  --
+  signal i8255_addr         : std_logic_vector(1 downto 0);
+  signal i8255_1D_data      : std_logic_vector(7 downto 0);
+  signal i8255_1D_data_oe_l : std_logic;
+  signal i8255_1D_cs_l      : std_logic;
+  signal i8255_1D_pa_out    : std_logic_vector(7 downto 0);
+  signal i8255_1D_pb_out    : std_logic_vector(7 downto 0);
+  --
+  signal i8255_1E_data      : std_logic_vector(7 downto 0);
+  signal i8255_1E_data_oe_l : std_logic;
+  signal i8255_1E_cs_l      : std_logic;
+  signal i8255_1E_pa        : std_logic_vector(7 downto 0);
+  signal i8255_1E_pb        : std_logic_vector(7 downto 0);
+  signal i8255_1E_pc        : std_logic_vector(7 downto 0);
+
+  -- security
+  signal net_1e10_i         : std_logic;
+  signal net_1e12_i         : std_logic;
+  signal xb                 : std_logic_vector(7 downto 0);
+  signal xbo                : std_logic_vector(7 downto 0);
+
+  signal audio_div_cnt      : std_logic_vector( 8 downto 0) := (others => '0');
+  signal ls90_op            : std_logic_vector(3 downto 0);
+  signal ls90_clk           : std_logic;
+  signal ls90_cnt           : std_logic_vector( 3 downto 0) := (others => '0');
+  -- ym2149 3C
+  signal ym2149_3C_dv       : std_logic_vector(7 downto 0);
+  signal ym2149_3C_oe_l     : std_logic;
+  signal ym2149_3C_bdir     : std_logic;
+  signal ym2149_3C_bc2      : std_logic;
+  signal ym2149_3C_bc1      : std_logic;
+  signal ym2149_3C_audio    : std_logic_vector(7 downto 0);
+  signal ym2149_3C_chan     : std_logic_vector(1 downto 0);
+  signal ym2149_3C_chan_t1  : std_logic_vector(1 downto 0);
+  --
+  -- ym2149 3D
+  signal ym2149_3D_dv       : std_logic_vector(7 downto 0);
+  signal ym2149_3D_oe_l     : std_logic;
+  signal ym2149_3D_bdir     : std_logic;
+  signal ym2149_3D_bc2      : std_logic;
+  signal ym2149_3D_bc1      : std_logic;
+  signal ym2149_3D_audio    : std_logic_vector(7 downto 0);
+  signal ym2149_3D_chan     : std_logic_vector(1 downto 0);
+  signal ym2149_3D_chan_t1  : std_logic_vector(1 downto 0);
+  signal ym2149_3D_ioa_in   : std_logic_vector(7 downto 0);
+  signal ym2149_3D_ioa_out  : std_logic_vector(7 downto 0);
+  signal ym2149_3D_ioa_oe_l : std_logic;
+  signal ym2149_3D_iob_in   : std_logic_vector(7 downto 0);
+  --
+  signal ampm               : std_logic;
+  signal sint               : std_logic;
+  signal sint_t1            : std_logic;
+  --
+  signal audio_3C_mix       : std_logic_vector(9 downto 0);
+  signal audio_3C_final     : std_logic_vector(9 downto 0);
+  signal audio_3D_mix       : std_logic_vector(9 downto 0);
+  signal audio_3D_final     : std_logic_vector(9 downto 0);
+  signal audio_final        : std_logic_vector(10 downto 0);
+
+  signal security_count     : std_logic_vector(2 downto 0);
+  signal rd_l_t1            : std_logic;
+  -- filters
+  signal ym2149_3C_k        : std_logic_vector(16 downto 0);
+  signal ym2149_3D_k        : std_logic_vector(16 downto 0);
+  signal audio_in_m_out_3C  : std_logic_vector(17 downto 0);
+  signal audio_in_m_out_3D  : std_logic_vector(17 downto 0);
+  signal audio_mult_3C      : std_logic_vector(35 downto 0);
+  signal audio_mult_3D      : std_logic_vector(35 downto 0);
+
+  signal rom0_cs, rom1_cs, rom2_cs : std_logic;
+
+
+
+  type array_4of17 is array (3 downto 0) of std_logic_vector(16 downto 0);
+  constant K_Filter : array_4of17 := ('0' & x"00A3",
+                                      '0' & x"00C6",
+                                      '0' & x"039D",
+                                      '1' & x"0000" );
+
+  type filter_pipe is array (3 downto 0) of std_logic_vector(17 downto 0);
+  signal ym2149_3C_audio_pipe : filter_pipe;
+  signal ym2149_3D_audio_pipe : filter_pipe;
+     -- LP filter out = in.k + out_t1.(1-k)
+     --
+     --                 = (in-out_t1).k + out_t1
+     --
+     -- using
+     --        -(Ts.2.PI.Fc)
+     -- k = 1-e
+     --
+     -- sampling freq = 1.79 MHz
+     --
+     -- cut off freqs     bit 0 1
+     --
+     --0.267uf  ~ 713 Hz      1 1   0.00249996 x 00A3
+     --0.220uf  ~ 865 Hz      1 0   0.00303210 x 00C6
+     --0.047uf  ~ 4050 Hz     0 1   0.01411753 x 039D
+     --                       0 0              x10000
+
+begin
+  -- Super Cobra
+  --0000-1fff ROM
+  --8000-83ff RAM
+
+  cpu_ena <= '1'; -- run at audio clock speed
+  -- other cpu signals
+  cpu_busrq_l <= '1';
+  cpu_nmi_l   <= '1';
+  cpu_wait_l  <= '1';
+  --
+  cpu_ena_gated <= ENA_1_79 and cpu_ena;
+  u_cpu : entity work.T80sed
+          port map (
+              RESET_n => I_RESET_L,
+              CLK_n   => CLK,
+              CLKEN   => cpu_ena_gated,
+              WAIT_n  => cpu_wait_l,
+              INT_n   => cpu_int_l,
+              NMI_n   => cpu_nmi_l,
+              BUSRQ_n => cpu_busrq_l,
+              M1_n    => cpu_m1_l,
+              MREQ_n  => cpu_mreq_l,
+              IORQ_n  => cpu_iorq_l,
+              RD_n    => cpu_rd_l,
+              WR_n    => cpu_wr_l,
+              RFSH_n  => cpu_rfsh_l,
+              HALT_n  => open,
+              BUSAK_n => open,
+              A       => cpu_addr,
+              DI      => cpu_data_in,
+              DO      => cpu_data_out
+              );
+
+  p_cpu_int : process(CLK, I_RESET_L)
+  begin
+    if (I_RESET_L = '0') then
+      cpu_int_l <= '1';
+      sint_t1   <= '0';
+    elsif rising_edge(CLK) then
+      if (ENA_1_79 = '1') then
+        sint_t1 <= sint;
+
+        if (cpu_m1_l = '0') and (cpu_iorq_l = '0') then
+          cpu_int_l <= '1';
+        elsif (sint = '0') and (sint_t1 = '1') then
+          cpu_int_l <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  p_mem_decode_comb : process(cpu_rfsh_l, cpu_wr_l, cpu_rd_l, cpu_mreq_l, cpu_addr)
+    variable decode : std_logic;
+  begin
+      decode := '0';
+      if (cpu_rfsh_l = '1') and (cpu_mreq_l = '0') and (cpu_addr(15) = '1') then
+        decode := '1';
+      end if;
+      filter_load <= decode and cpu_addr(12) and (not cpu_wr_l);
+      ram_cs      <= decode and (not cpu_addr(12));
+    rom_oe <= '0';
+      if (cpu_addr(15) = '0') and (cpu_mreq_l = '0') and (cpu_rd_l = '0') then
+        rom_oe <= '1';
+      end if;
+  end process;
+
+  u_rom_5c : entity work.ROM_SND_0
+    port map (
+      CLK         => CLK,
+      ADDR        => cpu_addr(10 downto 0),
+      DATA        => cpu_rom0_dout
+      );
+
+  u_rom_5d : entity work.ROM_SND_1
+    port map (
+      CLK         => CLK,
+      ADDR        => cpu_addr(10 downto 0),
+      DATA        => cpu_rom1_dout
+      );
+		
+  p_rom_mux : process(cpu_rom0_dout, cpu_rom1_dout, cpu_rom2_dout, cpu_addr, rom_oe)
+    variable rom_oe_decode : std_logic;
+    variable cpu_rom0_dout_s : std_logic_vector(7 downto 0);
+  begin
+--    if not I_HWSEL_FROGGER then
+      cpu_rom0_dout_s := cpu_rom0_dout;
+ --   else -- swap bits 0 and 1
+--      cpu_rom0_dout_s := cpu_rom0_dout(7 downto 2) & cpu_rom0_dout(0) & cpu_rom0_dout(1);
+--   end if;
+
+    rom_dout <= (others => '0');
+    rom_oe_decode := '0';
+    case cpu_addr(13 downto 11) is
+      when "000" => rom_dout <= cpu_rom0_dout_s; rom_oe_decode := '1';
+      when "001" => rom_dout <= cpu_rom1_dout;   rom_oe_decode := '1';
+ --     when "010" => rom_dout <= cpu_rom2_dout;   rom_oe_decode := '1';
+      when others => null;
+    end case;
+
+    rom_active <= '0';
+    if (rom_oe = '1') then
+      rom_active <= rom_oe_decode;
+    end if;
+  end process;
+
+	
+	u_ram_6c_6d : work.dpram generic map (10,8)
+	port map
+	(
+        addr_a_i => cpu_addr(9 downto 0),
+        data_a_i => cpu_data_out,
+        clk_b_i  => clk,
+        addr_b_i => cpu_addr(9 downto 0),
+        data_b_o => ram_dout,
+        we_i     => ram_cs and (not cpu_wr_l),
+        en_a_i   => ENA_1_79,
+        clk_a_i  => clk
+	);
+
+  p_cpu_data_mux : process(rom_dout, rom_active, ram_dout, ym2149_3C_oe_l, ym2149_3C_dv, ym2149_3D_oe_l, ym2149_3D_dv, ram_cs, cpu_wr_l)
+  begin
+    if    (rom_active = '1') then
+      cpu_data_in <= rom_dout;
+    elsif (ram_cs = '1') and (cpu_wr_l = '1') then
+      cpu_data_in <= ram_dout;
+    elsif (ym2149_3C_oe_l = '0') then
+      cpu_data_in <= ym2149_3C_dv;
+    elsif (ym2149_3D_oe_l = '0') then
+      cpu_data_in <= ym2149_3D_dv;
+    else
+      cpu_data_in <= (others => '1'); -- float high
+    end if;
+  end process;
+
+  p_filter_reg : process
+  begin
+    wait until rising_edge(CLK);
+    if (ENA_1_79 = '1') then
+      if (filter_load = '1') then
+        filter_reg <= cpu_addr(11 downto 0);
+      end if;
+    end if;
+  end process;
+
+  p_8255_decode : process(I_RESET_L, I_ADDR)
+  begin
+    reset <= not I_RESET_L;
+    i8255_1D_cs_l <= '1';
+    i8255_1E_cs_l <= '1';
+
+    -- the interface one
+    if (I_ADDR(13 downto 11) = "100") and (I_ADDR(15) = '1') then
+      i8255_1D_cs_l <= '0';
+    end if;
+
+    -- the button one
+    if (I_ADDR(13 downto 11) = "011") and (I_ADDR(15) = '1') then
+      i8255_1E_cs_l <= '0';
+    end if;
+    i8255_addr <= I_ADDR(1 downto 0);
+  end process;
+
+  p_ym_decode : process(cpu_rd_l, cpu_wr_l, cpu_iorq_l, cpu_addr)
+    variable rd_3c : std_logic;
+    variable wr_3c : std_logic;
+    variable ad_3c : std_logic;
+    --
+    variable rd_3d : std_logic;
+    variable wr_3d : std_logic;
+    variable ad_3d : std_logic;
+  begin
+
+  --bdir bc2 bc1
+  --  0   0  0    nop
+  --  0   0  1    addr latch   < WR_L AV4 / AV6
+  --  0   1  0    nop
+  --  0   1  1    data read    < RD_L AV5 / AV7
+
+  --  1   0  0    addr latch
+  --  1   0  1    nop
+  --  1   1  0    data write   < WR_L AV5 / AV7
+  --  1   1  1    addr latch
+
+
+    rd_3c := (not cpu_rd_l) and (not cpu_iorq_l) and cpu_addr(5);
+    wr_3c := (not cpu_wr_l) and (not cpu_iorq_l) and cpu_addr(5);
+    ad_3c := (not cpu_wr_l) and (not cpu_iorq_l) and cpu_addr(4);
+
+    ym2149_3C_bdir <= wr_3c;
+    ym2149_3C_bc2  <= rd_3c or wr_3c;
+    ym2149_3C_bc1  <= rd_3c or ad_3c;
+
+
+    rd_3d := (not cpu_rd_l) and (not cpu_iorq_l) and cpu_addr(7);
+    wr_3d := (not cpu_wr_l) and (not cpu_iorq_l) and cpu_addr(7);
+    ad_3d := (not cpu_wr_l) and (not cpu_iorq_l) and cpu_addr(6);
+
+    ym2149_3D_bdir <= wr_3d;
+    ym2149_3D_bc2  <= rd_3d or wr_3d;
+    ym2149_3D_bc1  <= rd_3d or ad_3d;
+
+  end process;
+  
+  i8255_1E_pa(7) <= I_COIN1;--coin1
+  i8255_1E_pa(6) <= I_COIN2;--coin2
+  i8255_1E_pa(5) <= I_1P_CTRL(3); -- left1
+  i8255_1E_pa(4) <= I_1P_CTRL(2); -- right1
+  i8255_1E_pa(3) <= I_1P_CTRL(4); -- shoot1-1
+  i8255_1E_pa(2) <= '1';--unused
+  i8255_1E_pa(1) <= I_1P_CTRL(5); -- shoot1-2
+  i8255_1E_pa(0) <= I_2P_CTRL(1); -- up2
+  
+  i8255_1E_pb(7) <= I_1P_CTRL(6); -- start1
+  i8255_1E_pb(6) <= I_2P_CTRL(6); -- start2
+  i8255_1E_pb(5) <= I_2P_CTRL(3); -- left2
+  i8255_1E_pb(4) <= I_2P_CTRL(2); -- right2
+  i8255_1E_pb(3) <= I_2P_CTRL(4); -- shoot2-1
+  i8255_1E_pb(2) <= I_2P_CTRL(5); -- shoot2-2
+  i8255_1E_pb(1) <= I_DIP(0);--Demo Sounds
+  i8255_1E_pb(0) <= I_DIP(1);--Lives
+  
+  i8255_1E_pc(7) <= '1';--unused
+  i8255_1E_pc(6) <= I_1P_CTRL(0); -- down1
+  i8255_1E_pc(5) <= '1';--unused
+  i8255_1E_pc(4) <= I_1P_CTRL(1); -- up1
+  i8255_1E_pc(3) <= I_DIP(4);--cabinet
+  i8255_1E_pc(2) <= I_DIP(3);--coin
+  i8255_1E_pc(1) <= I_DIP(2);--coin
+  i8255_1E_pc(0) <= I_2P_CTRL(0); -- down2
+  
+  --O_COIN_COUNTER <= not I_IOPC7; -- open drain actually
+
+  --
+  -- PIA CHIPS
+  --
+  u_i8255_1D : entity work.I82C55 -- bus interface
+    port map (
+      I_ADDR            => i8255_addr,
+      I_DATA            => I_DATA,
+      O_DATA            => i8255_1D_data,
+      O_DATA_OE_L       => i8255_1D_data_oe_l,
+
+      I_CS_L            => i8255_1D_cs_l,
+      I_RD_L            => I_RD_L,
+      I_WR_L            => I_WR_L,
+
+      I_PA              => i8255_1D_pa_out,
+      O_PA              => i8255_1D_pa_out,
+      O_PA_OE_L         => open,
+
+      I_PB              => i8255_1D_pb_out,
+      O_PB              => i8255_1D_pb_out,
+      O_PB_OE_L         => open,
+
+      I_PC              => xbo,
+      O_PC              => xb,
+      O_PC_OE_L         => open,
+
+      RESET             => reset,
+      ENA               => ENA,
+      CLK               => CLK
+      );
+
+  u_i8255_1E : entity work.I82C55 -- push button
+    port map (
+      I_ADDR            => i8255_addr,
+      I_DATA            => I_DATA,
+      O_DATA            => i8255_1E_data,
+      O_DATA_OE_L       => i8255_1E_data_oe_l,
+
+      I_CS_L            => i8255_1E_cs_l,
+      I_RD_L            => I_RD_L,
+      I_WR_L            => I_WR_L,
+
+      I_PA              => i8255_1E_pa,
+      O_PA              => open,
+      O_PA_OE_L         => open,
+
+      I_PB              => i8255_1E_pb,
+      O_PB              => open,
+      O_PB_OE_L         => open,
+
+      I_PC              => i8255_1E_pc,
+      O_PC              => open,
+      O_PC_OE_L         => open,
+
+      RESET             => reset,
+      ENA               => ENA,
+      CLK               => CLK
+      );
+
+  p_i8255_1d_bus_control : process(i8255_1D_pa_out, i8255_1D_pb_out, ym2149_3D_ioa_out, ym2149_3D_ioa_oe_l)
+  begin
+    if (ym2149_3D_ioa_oe_l = '0') then
+      ym2149_3D_ioa_in <= ym2149_3D_ioa_out;
+    else
+      ym2149_3D_ioa_in <= i8255_1D_pa_out;
+    end if;
+
+    ampm <= i8255_1D_pb_out(4); -- amp mute
+    sint <= i8255_1D_pb_out(3); -- set int
+  end process;
+
+  p_drive_cpubus : process(i8255_1D_data, i8255_1D_data_oe_l, i8255_1E_data, i8255_1E_data_oe_l)
+  begin
+    O_DATA_OE_L <= '1';
+    O_DATA      <= (others => '0');
+    --
+    if    (i8255_1D_data_oe_l = '0') then
+      --
+      O_DATA_OE_L <= '0';
+      O_DATA      <= i8255_1D_data;
+    elsif (i8255_1E_data_oe_l = '0') then
+      --
+      O_DATA_OE_L <= '0';
+      O_DATA      <= i8255_1E_data;
+    end if;
+  end process;
+  --
+  -- AUDIO CHIPS
+  --
+  p_audio_clockgen : process
+  begin
+    wait until rising_edge(CLK);
+    if (ENA_1_79 = '1') then
+      audio_div_cnt <= audio_div_cnt - "1";
+      ls90_clk <= not audio_div_cnt(8);
+
+      if (audio_div_cnt(8 downto 0) = "000000000") then
+        if (ls90_cnt = x"9") then
+          ls90_cnt <= x"0";
+        else
+          ls90_cnt <= ls90_cnt + "1";
+        end if;
+      end if;
+
+      ls90_op <= "0000";
+      case ls90_cnt is --ls90 outputs DCBA
+        when x"0" => ls90_op <= "0000";
+        when x"1" => ls90_op <= "0010";
+        when x"2" => ls90_op <= "0100";
+        when x"3" => ls90_op <= "0110";
+        when x"4" => ls90_op <= "1000";
+        when x"5" => ls90_op <= "0001";
+        when x"6" => ls90_op <= "0011";
+        when x"7" => ls90_op <= "0101";
+        when x"8" => ls90_op <= "0111";
+        when x"9" => ls90_op <= "1001";
+        when others => ls90_op <= "0000";
+      end case;
+    end if;
+  end process;
+
+  p_ym2149_3d_iob_in : process(ls90_op, ls90_clk)
+  begin
+      ym2149_3D_iob_in <= ls90_op(0) & ls90_op(3) & ls90_op(2) & ls90_clk & "1110";
+  end process;
+
+  u_ym2149_3C : entity work.YM2149
+  port map (
+    -- data bus
+    I_DA                => cpu_data_out,
+    O_DA                => ym2149_3C_dv,
+    O_DA_OE_L           => ym2149_3C_oe_l,
+    -- control
+    I_A9_L              => '0',
+    I_A8                => '1',
+    I_BDIR              => ym2149_3C_bdir,
+    I_BC2               => ym2149_3C_bc2,
+    I_BC1               => ym2149_3C_bc1,
+    I_SEL_L             => '1',
+
+    O_AUDIO             => ym2149_3C_audio,
+    O_CHAN              => ym2149_3C_chan,
+    -- port a
+    I_IOA               => "11111111",
+    O_IOA               => open,
+    O_IOA_OE_L          => open,
+    -- port b
+    I_IOB               => "11111111",
+    O_IOB               => open,
+    O_IOB_OE_L          => open,
+
+    ENA                 => ENA_1_79,
+    RESET_L             => I_RESET_L,
+    CLK                 => CLK
+    );
+
+  u_ym2149_3D : entity work.YM2149
+  port map (
+    -- data bus
+    I_DA                => cpu_data_out,
+    O_DA                => ym2149_3D_dv,
+    O_DA_OE_L           => ym2149_3D_oe_l,
+    -- control
+    I_A9_L              => '0',
+    I_A8                => '1',
+    I_BDIR              => ym2149_3D_bdir,
+    I_BC2               => ym2149_3D_bc2,
+    I_BC1               => ym2149_3D_bc1,
+    I_SEL_L             => '1',
+
+    O_AUDIO             => ym2149_3D_audio,
+    O_CHAN              => ym2149_3D_chan,
+    -- port a
+    I_IOA               => ym2149_3D_ioa_in,
+    O_IOA               => ym2149_3D_ioa_out,
+    O_IOA_OE_L          => ym2149_3D_ioa_oe_l,
+    -- port b
+    I_IOB               => ym2149_3D_iob_in,
+    O_IOB               => open,
+    O_IOB_OE_L          => open,
+
+    ENA                 => ENA_1_79,
+    RESET_L             => I_RESET_L,
+    CLK                 => CLK
+    );
+
+  p_filter_coef : process
+  begin
+    wait until rising_edge(CLK);
+    if (ENA_1_79 = '1') then
+      case ym2149_3C_chan is -- -1 as reg here
+        when "00" => -- chan 3
+          ym2149_3C_k <= (others => '0');
+        when "11" => -- chan 2
+          ym2149_3C_k <= K_FILTER(conv_integer(filter_reg(5 downto 4)));
+        when "10" => -- chan 1
+          ym2149_3C_k <= K_FILTER(conv_integer(filter_reg(3 downto 2)));
+        when "01" => -- chan 0
+          ym2149_3C_k <= K_FILTER(conv_integer(filter_reg(1 downto 0)));
+        when others => null;
+      end case;
+
+      case ym2149_3D_chan is -- -1 as reg here
+        when "00" => -- chan 3
+          ym2149_3D_k <= (others => '0');
+        when "11" => -- chan 2
+          ym2149_3D_k <= K_FILTER(conv_integer(filter_reg(11 downto 10)));
+        when "10" => -- chan 1
+          ym2149_3D_k <= K_FILTER(conv_integer(filter_reg( 9 downto  8)));
+        when "01" => -- chan 0
+          ym2149_3D_k <= K_FILTER(conv_integer(filter_reg( 7 downto  6)));
+        when others => null;
+      end case;
+    end if;
+  end process;
+
+
+  p_ym2149_audio_process : process(ym2149_3C_audio, ym2149_3C_audio_pipe, ym2149_3D_audio, ym2149_3D_audio_pipe)
+  begin
+    audio_in_m_out_3C <= (('0' & ym2149_3C_audio & "000000000"))- ym2149_3C_audio_pipe(3); -- signed
+    audio_in_m_out_3D <= (('0' & ym2149_3D_audio & "000000000"))- ym2149_3D_audio_pipe(3); -- signed
+  end process;
+
+  mult_3C : work.MULT18X18
+      port map
+      (
+        P => audio_mult_3C,-- 35..0 -- audio 8bit on 32..25 33 sign bit,
+        A => audio_in_m_out_3C, --17..0
+        B(17)           => '0',
+        B(16 downto  0) => ym2149_3C_k
+      );
+
+  mult_3D : work.MULT18X18
+      port map
+      (
+        P => audio_mult_3D,-- 35..0 -- audio 8bit on 32..25 33 sign bit,
+        A => audio_in_m_out_3D, --17..0
+        B(17)           => '0',
+        B(16 downto  0) => ym2149_3D_k
+      );
+
+  p_ym2149_audio_pipe : process(I_RESET_L, CLK)
+  begin
+    if (I_RESET_L = '0') then
+      ym2149_3C_audio_pipe <= (others => (others => '0'));
+      ym2149_3D_audio_pipe <= (others => (others => '0'));
+    elsif rising_edge(CLK) then
+--      audio_mult_3C <= audio_in_m_out_3C * ym2149_3C_k;
+--      audio_mult_3D <= audio_in_m_out_3D * ym2149_3D_k;
+      if (ENA_1_79 = '1') then
+        -- we need some holding registers anyway, so lets just make it a shift and save a mux
+        ym2149_3C_audio_pipe(3 downto 1) <= ym2149_3C_audio_pipe(2 downto 0);
+        ym2149_3C_audio_pipe(0)          <= audio_mult_3C(33 downto 16) + ym2149_3C_audio_pipe(3); -- bit 33 sign
+
+        ym2149_3D_audio_pipe(3 downto 1) <= ym2149_3D_audio_pipe(2 downto 0);
+        ym2149_3D_audio_pipe(0)          <= audio_mult_3D(33 downto 16) + ym2149_3D_audio_pipe(3); -- bit 33 sign
+      end if;
+    end if;
+  end process;
+
+  p_ym2149_audio_mix : process
+  begin
+    wait until rising_edge(CLK);
+    if (ENA_1_79 = '1') then
+      ym2149_3C_chan_t1 <= ym2149_3C_chan;
+      ym2149_3D_chan_t1 <= ym2149_3D_chan;
+
+      if (ym2149_3C_chan_t1 = "11") then
+        audio_3C_mix   <= (others => '0');
+        audio_3C_final <= audio_3C_mix;
+      else
+        audio_3C_mix   <= audio_3C_mix + ("00" & ym2149_3C_audio_pipe(0)(16 downto 9));
+      end if;
+
+      if (ym2149_3D_chan_t1(1 downto 0) = "11") then
+        audio_3D_mix   <= (others => '0');
+        audio_3D_final <= audio_3D_mix;
+      else
+        audio_3D_mix   <= audio_3D_mix + ("00" & ym2149_3D_audio_pipe(0)(16 downto 9));
+      end if;
+
+      audio_final <= ('0' & audio_3C_final) + ('0' & audio_3D_final);
+    end if;
+  end process;
+
+  p_audio_out : process(CLK, I_RESET_L)
+  begin
+    if (I_RESET_L = '0') then
+      O_AUDIO <= (others => '0');
+    elsif rising_edge(CLK) then
+      if (ENA_1_79 = '1') then
+        if (ampm = '1') then
+          O_AUDIO <= (others => '0');
+        else
+          if (audio_final(10) = '1') then
+            O_AUDIO <= (others => '1');
+          else
+            O_AUDIO <= audio_final(9 downto 0);
+          end if;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  p_security_6J : process(xb)
+  begin
+    -- chip K10A PAL16L8
+    -- equations from Mark @ http://www.leopardcats.com/
+    xbo(3 downto 0) <= xb(3 downto 0);
+    xbo(4) <= not(xb(0) or xb(1) or xb(2) or xb(3));
+    xbo(5) <= not((not xb(2) and not xb(0)) or (not xb(2) and not xb(1)) or (not xb(3) and not xb(0)) or (not xb(3) and not xb(1)));
+
+    xbo(6) <= not(not xb(0) and not xb(3));
+    xbo(7) <= not((not xb(1)) or xb(2));
+  end process;
+
+  p_security_count : process(CLK, I_RESET_L)
+  begin
+  if (I_RESET_L = '0') then
+    security_count <= "000";
+  elsif rising_edge(CLK) then
+    rd_l_t1 <= i_rd_l;
+    if (I_ADDR = x"8102") and (I_RD_L = '0') and (rd_l_t1 = '1') then
+      security_count <= security_count + "1";
+    end if;
+  end if;
+  end process;
+
+  p_security_2B : process(security_count)
+  begin
+    -- I am not sure what this chip does yet, but this gets us past the initial check for now.
+    case security_count is
+      when "000" => net_1e10_i <= '0'; net_1e12_i <= '1';
+      when "001" => net_1e10_i <= '0'; net_1e12_i <= '1';
+      when "010" => net_1e10_i <= '1'; net_1e12_i <= '0';
+      when "011" => net_1e10_i <= '1'; net_1e12_i <= '1';
+      when "100" => net_1e10_i <= '1'; net_1e12_i <= '1';
+      when "101" => net_1e10_i <= '1'; net_1e12_i <= '1';
+      when "110" => net_1e10_i <= '1'; net_1e12_i <= '1';
+      when "111" => net_1e10_i <= '1'; net_1e12_i <= '1';
+      when others => null;
+    end case;
+  end process;
+
+end RTL;
diff --git a/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/scramble_top.vhd b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/scramble_top.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/scramble_top.vhd
rename to Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/scramble_top.vhd
diff --git a/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/scramble_video.vhd b/Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/scramble_video.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/scramble_video.vhd
rename to Arcade_MiST/Konami Scramble Hardware/SpeedCoin_MiST/rtl/scramble_video.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Super Cobra.jpg b/Arcade_MiST/Konami Scramble Hardware/Super Cobra.jpg
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Super Cobra.jpg
rename to Arcade_MiST/Konami Scramble Hardware/Super Cobra.jpg
diff --git a/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/README.txt b/Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/README.txt
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/SuperCobra_MiST/README.txt
rename to Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/README.txt
diff --git a/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/Release/SCobra.rbf b/Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/Release/SCobra.rbf
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/SuperCobra_MiST/Release/SCobra.rbf
rename to Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/Release/SCobra.rbf
diff --git a/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/SCobra.qpf b/Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/SCobra.qpf
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/SuperCobra_MiST/SCobra.qpf
rename to Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/SCobra.qpf
diff --git a/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/SCobra.qsf b/Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/SCobra.qsf
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/SuperCobra_MiST/SCobra.qsf
rename to Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/SCobra.qsf
diff --git a/Arcade_MiST/Scramble Hardware/TazzMania_MiST/TazzMania.sdc b/Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/SCobra.sdc
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TazzMania_MiST/TazzMania.sdc
rename to Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/SCobra.sdc
diff --git a/Arcade_MiST/Scramble Hardware/TazzMania_MiST/TazzMania.srf b/Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/SCobra.srf
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TazzMania_MiST/TazzMania.srf
rename to Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/SCobra.srf
diff --git a/Arcade_MiST/Scramble Hardware/TazzMania_MiST/clean.bat b/Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/clean.bat
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TazzMania_MiST/clean.bat
rename to Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/clean.bat
diff --git a/Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/MULT18X18.vhd b/Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/MULT18X18.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/MULT18X18.vhd
rename to Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/MULT18X18.vhd
diff --git a/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/SCobra_Mist.sv b/Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/SCobra_Mist.sv
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/SCobra_Mist.sv
rename to Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/SCobra_Mist.sv
diff --git a/Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/T80/T80.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/T80/T80.vhd
rename to Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/T80/T80.vhd
diff --git a/Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/T80/T80_ALU.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/T80/T80_ALU.vhd
rename to Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/T80/T80_ALU.vhd
diff --git a/Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/T80/T80_MCode.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/T80/T80_MCode.vhd
rename to Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/T80/T80_MCode.vhd
diff --git a/Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/T80/T80_Pack.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/T80/T80_Pack.vhd
rename to Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/T80/T80_Pack.vhd
diff --git a/Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/T80/T80_Reg.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/T80/T80_Reg.vhd
rename to Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/T80/T80_Reg.vhd
diff --git a/Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/T80/T80sed.vhd b/Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/T80/T80sed.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/T80/T80sed.vhd
rename to Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/T80/T80sed.vhd
diff --git a/Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/YM2149_linmix_sep.vhd b/Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/YM2149_linmix_sep.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/YM2149_linmix_sep.vhd
rename to Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/YM2149_linmix_sep.vhd
diff --git a/Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/build_id.tcl b/Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/build_id.tcl
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/build_id.tcl
rename to Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/build_id.tcl
diff --git a/Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/dpram.vhd b/Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/dpram.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/dpram.vhd
rename to Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/dpram.vhd
diff --git a/Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/i82c55.vhd b/Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/i82c55.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/i82c55.vhd
rename to Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/i82c55.vhd
diff --git a/Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/pll.qip b/Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/pll.qip
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/pll.qip
rename to Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/pll.qip
diff --git a/Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/pll.v b/Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/pll.v
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/pll.v
rename to Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/pll.v
diff --git a/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/rom/ROM_LUT.vhd b/Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/rom/ROM_LUT.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/rom/ROM_LUT.vhd
rename to Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/rom/ROM_LUT.vhd
diff --git a/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/rom/ROM_OBJ_0.vhd b/Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/rom/ROM_OBJ_0.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/rom/ROM_OBJ_0.vhd
rename to Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/rom/ROM_OBJ_0.vhd
diff --git a/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/rom/ROM_OBJ_1.vhd b/Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/rom/ROM_OBJ_1.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/rom/ROM_OBJ_1.vhd
rename to Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/rom/ROM_OBJ_1.vhd
diff --git a/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/rom/ROM_PGM.vhd b/Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/rom/ROM_PGM.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/rom/ROM_PGM.vhd
rename to Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/rom/ROM_PGM.vhd
diff --git a/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/rom/ROM_SND_0.vhd b/Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/rom/ROM_SND_0.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/rom/ROM_SND_0.vhd
rename to Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/rom/ROM_SND_0.vhd
diff --git a/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/rom/ROM_SND_1.vhd b/Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/rom/ROM_SND_1.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/rom/ROM_SND_1.vhd
rename to Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/rom/ROM_SND_1.vhd
diff --git a/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/rom/ROM_SND_2.vhd b/Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/rom/ROM_SND_2.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/rom/ROM_SND_2.vhd
rename to Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/rom/ROM_SND_2.vhd
diff --git a/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/scramble.vhd b/Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/scramble.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/scramble.vhd
rename to Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/scramble.vhd
diff --git a/Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/scramble_audio.vhd b/Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/scramble_audio.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/SuperCobra_MiST/rtl/scramble_audio.vhd
rename to Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/scramble_audio.vhd
diff --git a/Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/scramble_top.vhd b/Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/scramble_top.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/scramble_top.vhd
rename to Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/scramble_top.vhd
diff --git a/Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/scramble_video.vhd b/Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/scramble_video.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/scramble_video.vhd
rename to Arcade_MiST/Konami Scramble Hardware/SuperCobra_MiST/rtl/scramble_video.vhd
diff --git a/Arcade_MiST/Scramble Hardware/Tazz Mania.jpeg b/Arcade_MiST/Konami Scramble Hardware/Tazz Mania.jpeg
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/Tazz Mania.jpeg
rename to Arcade_MiST/Konami Scramble Hardware/Tazz Mania.jpeg
diff --git a/Arcade_MiST/Scramble Hardware/TazzMania_MiST/README.txt b/Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/README.txt
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TazzMania_MiST/README.txt
rename to Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/README.txt
diff --git a/Arcade_MiST/Scramble Hardware/TazzMania_MiST/Release/TazzMania.rbf b/Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/Release/TazzMania.rbf
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TazzMania_MiST/Release/TazzMania.rbf
rename to Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/Release/TazzMania.rbf
diff --git a/Arcade_MiST/Scramble Hardware/TazzMania_MiST/TazzMania.qpf b/Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/TazzMania.qpf
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TazzMania_MiST/TazzMania.qpf
rename to Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/TazzMania.qpf
diff --git a/Arcade_MiST/Scramble Hardware/TazzMania_MiST/TazzMania.qsf b/Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/TazzMania.qsf
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TazzMania_MiST/TazzMania.qsf
rename to Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/TazzMania.qsf
diff --git a/Arcade_MiST/Scramble Hardware/TheEnd_MiST/TheEnd.sdc b/Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/TazzMania.sdc
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TheEnd_MiST/TheEnd.sdc
rename to Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/TazzMania.sdc
diff --git a/Arcade_MiST/Scramble Hardware/TheEnd_MiST/TheEnd.srf b/Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/TazzMania.srf
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TheEnd_MiST/TheEnd.srf
rename to Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/TazzMania.srf
diff --git a/Arcade_MiST/Scramble Hardware/TheEnd_MiST/clean.bat b/Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/clean.bat
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TheEnd_MiST/clean.bat
rename to Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/clean.bat
diff --git a/Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/MULT18X18.vhd b/Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/MULT18X18.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/MULT18X18.vhd
rename to Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/MULT18X18.vhd
diff --git a/Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/T80/T80.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/cpu/T80.vhd
rename to Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/T80/T80.vhd
diff --git a/Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/T80/T80_ALU.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/cpu/T80_ALU.vhd
rename to Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/T80/T80_ALU.vhd
diff --git a/Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/T80/T80_MCode.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/cpu/T80_MCode.vhd
rename to Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/T80/T80_MCode.vhd
diff --git a/Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/T80/T80_Pack.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/cpu/T80_Pack.vhd
rename to Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/T80/T80_Pack.vhd
diff --git a/Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/T80/T80_Reg.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/cpu/T80_Reg.vhd
rename to Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/T80/T80_Reg.vhd
diff --git a/Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/cpu/T80sed.vhd b/Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/T80/T80sed.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/cpu/T80sed.vhd
rename to Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/T80/T80sed.vhd
diff --git a/Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/TazzMania_Mist.sv b/Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/TazzMania_Mist.sv
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/TazzMania_Mist.sv
rename to Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/TazzMania_Mist.sv
diff --git a/Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/YM2149_linmix_sep.vhd b/Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/YM2149_linmix_sep.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/YM2149_linmix_sep.vhd
rename to Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/YM2149_linmix_sep.vhd
diff --git a/Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/build_id.tcl b/Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/build_id.tcl
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/build_id.tcl
rename to Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/build_id.tcl
diff --git a/Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/dpram.vhd b/Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/dpram.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/dpram.vhd
rename to Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/dpram.vhd
diff --git a/Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/i82c55.vhd b/Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/i82c55.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/i82c55.vhd
rename to Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/i82c55.vhd
diff --git a/Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/pll.qip b/Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/pll.qip
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/pll.qip
rename to Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/pll.qip
diff --git a/Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/pll.v b/Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/pll.v
new file mode 100644
index 00000000..1d3529bd
--- /dev/null
+++ b/Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/pll.v	
@@ -0,0 +1,320 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: pll.v
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.0 Build 162 10/23/2013 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2013 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module pll (
+	areset,
+	inclk0,
+	c0,
+	locked);
+
+	input	  areset;
+	input	  inclk0;
+	output	  c0;
+	output	  locked;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri0	  areset;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire  sub_wire0;
+	wire [4:0] sub_wire1;
+	wire [0:0] sub_wire5 = 1'h0;
+	wire  locked = sub_wire0;
+	wire [0:0] sub_wire2 = sub_wire1[0:0];
+	wire  c0 = sub_wire2;
+	wire  sub_wire3 = inclk0;
+	wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
+
+	altpll	altpll_component (
+				.areset (areset),
+				.inclk (sub_wire4),
+				.locked (sub_wire0),
+				.clk (sub_wire1),
+				.activeclock (),
+				.clkbad (),
+				.clkena ({6{1'b1}}),
+				.clkloss (),
+				.clkswitch (1'b0),
+				.configupdate (1'b0),
+				.enable0 (),
+				.enable1 (),
+				.extclk (),
+				.extclkena ({4{1'b1}}),
+				.fbin (1'b1),
+				.fbmimicbidir (),
+				.fbout (),
+				.fref (),
+				.icdrclk (),
+				.pfdena (1'b1),
+				.phasecounterselect ({4{1'b1}}),
+				.phasedone (),
+				.phasestep (1'b1),
+				.phaseupdown (1'b1),
+				.pllena (1'b1),
+				.scanaclr (1'b0),
+				.scanclk (1'b0),
+				.scanclkena (1'b1),
+				.scandata (1'b0),
+				.scandataout (),
+				.scandone (),
+				.scanread (1'b0),
+				.scanwrite (1'b0),
+				.sclkout0 (),
+				.sclkout1 (),
+				.vcooverrange (),
+				.vcounderrange ());
+	defparam
+		altpll_component.bandwidth_type = "AUTO",
+		altpll_component.clk0_divide_by = 78,
+		altpll_component.clk0_duty_cycle = 50,
+		altpll_component.clk0_multiply_by = 71,
+		altpll_component.clk0_phase_shift = "0",
+		altpll_component.compensate_clock = "CLK0",
+		altpll_component.inclk0_input_frequency = 37037,
+		altpll_component.intended_device_family = "Cyclone III",
+		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
+		altpll_component.lpm_type = "altpll",
+		altpll_component.operation_mode = "NORMAL",
+		altpll_component.pll_type = "AUTO",
+		altpll_component.port_activeclock = "PORT_UNUSED",
+		altpll_component.port_areset = "PORT_USED",
+		altpll_component.port_clkbad0 = "PORT_UNUSED",
+		altpll_component.port_clkbad1 = "PORT_UNUSED",
+		altpll_component.port_clkloss = "PORT_UNUSED",
+		altpll_component.port_clkswitch = "PORT_UNUSED",
+		altpll_component.port_configupdate = "PORT_UNUSED",
+		altpll_component.port_fbin = "PORT_UNUSED",
+		altpll_component.port_inclk0 = "PORT_USED",
+		altpll_component.port_inclk1 = "PORT_UNUSED",
+		altpll_component.port_locked = "PORT_USED",
+		altpll_component.port_pfdena = "PORT_UNUSED",
+		altpll_component.port_phasecounterselect = "PORT_UNUSED",
+		altpll_component.port_phasedone = "PORT_UNUSED",
+		altpll_component.port_phasestep = "PORT_UNUSED",
+		altpll_component.port_phaseupdown = "PORT_UNUSED",
+		altpll_component.port_pllena = "PORT_UNUSED",
+		altpll_component.port_scanaclr = "PORT_UNUSED",
+		altpll_component.port_scanclk = "PORT_UNUSED",
+		altpll_component.port_scanclkena = "PORT_UNUSED",
+		altpll_component.port_scandata = "PORT_UNUSED",
+		altpll_component.port_scandataout = "PORT_UNUSED",
+		altpll_component.port_scandone = "PORT_UNUSED",
+		altpll_component.port_scanread = "PORT_UNUSED",
+		altpll_component.port_scanwrite = "PORT_UNUSED",
+		altpll_component.port_clk0 = "PORT_USED",
+		altpll_component.port_clk1 = "PORT_UNUSED",
+		altpll_component.port_clk2 = "PORT_UNUSED",
+		altpll_component.port_clk3 = "PORT_UNUSED",
+		altpll_component.port_clk4 = "PORT_UNUSED",
+		altpll_component.port_clk5 = "PORT_UNUSED",
+		altpll_component.port_clkena0 = "PORT_UNUSED",
+		altpll_component.port_clkena1 = "PORT_UNUSED",
+		altpll_component.port_clkena2 = "PORT_UNUSED",
+		altpll_component.port_clkena3 = "PORT_UNUSED",
+		altpll_component.port_clkena4 = "PORT_UNUSED",
+		altpll_component.port_clkena5 = "PORT_UNUSED",
+		altpll_component.port_extclk0 = "PORT_UNUSED",
+		altpll_component.port_extclk1 = "PORT_UNUSED",
+		altpll_component.port_extclk2 = "PORT_UNUSED",
+		altpll_component.port_extclk3 = "PORT_UNUSED",
+		altpll_component.self_reset_on_loss_lock = "OFF",
+		altpll_component.width_clock = 5;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "78"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.576923"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "71"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.57627100"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "78"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "71"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/rom/ROM_LUT.vhd b/Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/rom/ROM_LUT.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/rom/ROM_LUT.vhd
rename to Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/rom/ROM_LUT.vhd
diff --git a/Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/rom/ROM_OBJ_0.vhd b/Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/rom/ROM_OBJ_0.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/rom/ROM_OBJ_0.vhd
rename to Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/rom/ROM_OBJ_0.vhd
diff --git a/Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/rom/ROM_OBJ_1.vhd b/Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/rom/ROM_OBJ_1.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/rom/ROM_OBJ_1.vhd
rename to Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/rom/ROM_OBJ_1.vhd
diff --git a/Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/rom/ROM_PGM.vhd b/Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/rom/ROM_PGM.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/rom/ROM_PGM.vhd
rename to Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/rom/ROM_PGM.vhd
diff --git a/Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/rom/ROM_SND.vhd b/Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/rom/ROM_SND.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/rom/ROM_SND.vhd
rename to Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/rom/ROM_SND.vhd
diff --git a/Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/scramble.vhd b/Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/scramble.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/scramble.vhd
rename to Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/scramble.vhd
diff --git a/Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/scramble_audio.vhd b/Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/scramble_audio.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TazzMania_MiST/rtl/scramble_audio.vhd
rename to Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/scramble_audio.vhd
diff --git a/Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/scramble_top.vhd b/Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/scramble_top.vhd
new file mode 100644
index 00000000..201ac3e4
--- /dev/null
+++ b/Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/scramble_top.vhd	
@@ -0,0 +1,154 @@
+--
+-- A simulation model of Scramble hardware
+-- Copyright (c) MikeJ - Feb 2007
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- You are responsible for any legal issues arising from your use of this code.
+--
+-- The latest version of this file can be found at: www.fpgaarcade.com
+--
+-- Email support@fpgaarcade.com
+--
+-- Revision list
+--
+-- version 001 initial release
+--
+
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_arith.all;
+  use ieee.std_logic_unsigned.all;
+
+entity scramble_top is
+port (
+	O_VIDEO_R        : out std_logic_vector(3 downto 0);
+	O_VIDEO_G        : out std_logic_vector(3 downto 0);
+	O_VIDEO_B        : out std_logic_vector(3 downto 0);
+	O_HSYNC          : out std_logic;
+	O_VSYNC          : out std_logic;
+   O_HBLANK         : out std_logic;
+   O_VBLANK         : out std_logic;
+
+	O_AUDIO          : out std_logic_vector(9 downto 0);
+
+	ip_dip_switch    : in  std_logic_vector(4 downto 0);
+	ip_1p            : std_logic_vector(6 downto 0);
+   ip_2p            : std_logic_vector(6 downto 0);
+   ip_service       : std_logic;
+   ip_coin1         : std_logic;
+   ip_coin2         : std_logic;
+
+	RESET            : in  std_logic;
+	clk              : in  std_logic; -- 25
+	ena_12           : in  std_logic; -- 6.25 x 2
+	ena_6            : in  std_logic; -- 6.25 (inverted)
+	ena_6b           : in  std_logic; -- 6.25
+	ena_1_79         : in  std_logic  -- 1.786          
+);
+end;
+
+architecture RTL of scramble_top is
+
+-- ties to audio board
+signal audio_addr       : std_logic_vector(15 downto 0);
+signal audio_data_out   : std_logic_vector(7 downto 0);
+signal audio_data_in    : std_logic_vector(7 downto 0);
+signal audio_data_oe_l  : std_logic;
+signal audio_rd_l       : std_logic;
+signal audio_wr_l       : std_logic;
+signal audio_iopc7      : std_logic;
+signal audio_reset_l    : std_logic;
+
+begin
+
+u_scobra : entity work.scramble
+port map (
+	--
+	O_VIDEO_R             => O_VIDEO_R,
+	O_VIDEO_G             => O_VIDEO_G,
+	O_VIDEO_B             => O_VIDEO_B,
+	O_HSYNC               => O_HSYNC,
+	O_VSYNC               => O_VSYNC,
+   O_HBLANK              => O_HBLANK,
+   O_VBLANK              => O_VBLANK,
+	--
+	-- to audio board
+	--
+	O_ADDR                => audio_addr,
+	O_DATA                => audio_data_out,
+	I_DATA                => audio_data_in,
+	I_DATA_OE_L           => audio_data_oe_l,
+	O_RD_L                => audio_rd_l,
+	O_WR_L                => audio_wr_l,
+	O_IOPC7               => audio_iopc7,
+	O_RESET_WD_L          => audio_reset_l,
+	--
+	ENA                   => ena_6,
+	ENAB                  => ena_6b,
+	ENA_12                => ena_12,
+	--
+	RESET                 => reset,
+	CLK                   => clk
+);
+
+--
+--
+-- audio subsystem
+--
+u_audio : entity work.scramble_audio
+port map (
+	--
+	I_ADDR             => audio_addr,
+	I_DATA             => audio_data_out,
+	O_DATA             => audio_data_in,
+	O_DATA_OE_L        => audio_data_oe_l,
+	--
+	I_RD_L             => audio_rd_l,
+	I_WR_L             => audio_wr_l,
+	I_IOPC7            => audio_iopc7,
+	--
+	O_AUDIO            => O_AUDIO,
+	--
+	I_1P_CTRL          => ip_1p,
+	I_2P_CTRL          => ip_2p,
+	I_SERVICE          => ip_service,
+	I_COIN1            => ip_coin1,
+	I_COIN2            => ip_coin2,
+	O_COIN_COUNTER     => open,
+	--
+	I_DIP              => ip_dip_switch,
+	--
+	I_RESET_L          => audio_reset_l,
+	ENA                => ena_6,
+	ENA_1_79           => ena_1_79,
+	CLK                => clk
+);
+
+end RTL;
diff --git a/Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/scramble_video.vhd b/Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/scramble_video.vhd
new file mode 100644
index 00000000..a29182ab
--- /dev/null
+++ b/Arcade_MiST/Konami Scramble Hardware/TazzMania_MiST/rtl/scramble_video.vhd	
@@ -0,0 +1,726 @@
+--
+-- A simulation model of Scramble hardware
+-- Copyright (c) MikeJ - Feb 2007
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- You are responsible for any legal issues arising from your use of this code.
+--
+-- The latest version of this file can be found at: www.fpgaarcade.com
+--
+-- Email support@fpgaarcade.com
+--
+-- Revision list
+--
+-- version 001 initial release
+--
+
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_arith.all;
+  use ieee.std_logic_unsigned.all;
+
+entity scramble_video is
+  port (
+    --
+    I_HCNT                : in  std_logic_vector(8 downto 0);
+    I_VCNT                : in  std_logic_vector(8 downto 0);
+    I_VBLANK              : in  std_logic;
+    I_VSYNC               : in  std_logic;
+
+    I_VCMA                : in  std_logic;
+    I_HCMA                : in  std_logic;
+    --
+    I_CPU_ADDR            : in  std_logic_vector(15 downto 0);
+    I_CPU_DATA            : in  std_logic_vector(7 downto 0);
+    O_VRAM_DATA           : out std_logic_vector(7 downto 0);
+    -- note, looks like the real hardware cannot read from object ram
+    --
+    I_VRAMWR_L            : in  std_logic;
+    I_VRAMRD_L            : in  std_logic;
+    I_OBJRAMWR_L          : in  std_logic;
+    I_OBJRAMRD_L          : in  std_logic;
+    I_OBJEN_L             : in  std_logic;
+    --
+    I_STARSON             : in  std_logic;
+    I_POUT1               : in  std_logic;
+    --
+    O_VIDEO_R             : out std_logic_vector(3 downto 0);
+    O_VIDEO_G             : out std_logic_vector(3 downto 0);
+    O_VIDEO_B             : out std_logic_vector(3 downto 0);
+    --
+    ENA                   : in  std_logic;
+    ENAB                  : in  std_logic;
+    ENA_12                : in  std_logic;
+    CLK                   : in  std_logic
+    );
+end;
+
+-- chars     stars   vidout?    shell/missile
+--
+-- 220R B    100 B   390R B     100R R
+-- 470R B    150 B              100R G
+-- 220R G    100 G                   blue ?
+-- 470R G    150 G
+--   1K G    100 R
+-- 220R R    150 R
+-- 470R R
+--   1K R
+architecture RTL of scramble_video is
+
+  type array_3x5 is array (2 downto 0) of std_logic_vector(4 downto 0);
+  -- timing
+  signal ld                   : std_logic;
+  signal h256_l               : std_logic;
+  signal h256                 : std_logic;
+  signal cblank_s             : std_logic;
+  signal hcmp1_s              : std_logic;
+  signal hcmp2_s              : std_logic;
+  signal hcmp1                : std_logic;
+  signal hcmp2                : std_logic;
+  signal cblank_l             : std_logic;
+  signal h256_l_s             : std_logic;
+  signal hcnt_f               : std_logic_vector(7 downto 0);
+  signal vcnt_f               : std_logic_vector(7 downto 0);
+
+  -- load strobes
+  signal vpl_load             : std_logic;
+  signal col_load             : std_logic;
+  signal objdata_load         : std_logic;
+  signal missile_load         : std_logic;
+  signal missile_reg_l        : std_logic;
+
+  signal cntr_clr             : std_logic;
+  signal cntr_load            : std_logic;
+  signal sld_l                : std_logic;
+
+  -- video ram
+  signal vram_addr_sum        : std_logic_vector(8 downto 0); -- extra bit for debug
+  signal msld_l               : std_logic;
+  signal vram_addr_reg        : std_logic_vector(7 downto 0);
+  signal vram_addr_xor        : std_logic_vector(3 downto 0);
+  signal vram_addr            : std_logic_vector(9 downto 0);
+  signal vram_dout            : std_logic_vector(7 downto 0);
+  signal ldout                : std_logic;
+
+  -- object ram
+  signal obj_addr             : std_logic_vector(7 downto 0);
+  signal hpla                 : std_logic_vector(7 downto 0);
+  signal objdata              : std_logic_vector(7 downto 0);
+
+  signal obj_rom_addr         : std_logic_vector(10 downto 0);
+  signal obj_rom_0_dout       : std_logic_vector(7 downto 0);
+  signal obj_rom_1_dout       : std_logic_vector(7 downto 0);
+  --
+  signal col_reg              : std_logic_vector(2 downto 0);
+  signal cd                   : std_logic_vector(2 downto 0);
+
+  signal shift_reg_1          : std_logic_vector(7 downto 0);
+  signal shift_reg_0          : std_logic_vector(7 downto 0);
+  signal shift_op             : std_logic_vector(1 downto 0);
+  signal shift_sel            : std_logic_vector(1 downto 0);
+  signal gr                   : std_logic_vector(1 downto 0);
+  signal gc                   : std_logic_vector(2 downto 0);
+
+  signal vid                  : std_logic_vector(1 downto 0);
+  signal col                  : std_logic_vector(2 downto 0);
+
+  signal obj_video_out_reg    : std_logic_vector(4 downto 0);
+  signal vidout_l             : std_logic;
+  signal obj_lut_out          : std_logic_vector(7 downto 0);
+
+  signal cntr_addr            : std_logic_vector(7 downto 0);
+  signal cntr_addr_xor        : std_logic_vector(10 downto 0);
+  signal sprite_sel           : std_logic;
+  signal sprite_ram_ip        : std_logic_vector(7 downto 0);
+  signal sprite_ram_waddr     : std_logic_vector(10 downto 0);
+  signal sprite_ram_op        : std_logic_vector(7 downto 0);
+  -- shell
+  signal shell_cnt            : std_logic_vector(7 downto 0);
+  signal shell_ena            : std_logic;
+  signal shell                : std_logic;
+  signal shell_reg            : std_logic;
+  -- stars
+  signal star_reg_1           : std_logic;
+  signal star_reg_2           : std_logic;
+  signal star_cnt_div         : std_logic_vector(22 downto 0);
+  signal star_cnt             : std_logic_vector(1 downto 0);
+  signal star_shift           : std_logic_vector(16 downto 0);
+  signal star_shift_t1        : std_logic_vector(16 downto 0);
+  signal star_on              : std_logic;
+  signal star_out_reg         : std_logic;
+  -- Blue background
+  signal pout1_reg            : std_logic;
+
+  signal rom0_cs, rom1_cs     : std_logic;
+
+
+begin
+  p_hcnt_decode : process(I_HCNT)
+  begin
+    ld <= '0';
+    if (I_HCNT(2 downto 0) = "111") then
+      ld <= '1';
+    end if;
+    h256_l  <= I_HCNT(8);
+    h256    <= not I_HCNT(8);
+
+  end process;
+
+  p_timing_decode : process(h256, h256_l, I_HCMA, I_VBLANK)
+  begin
+    cblank_s    <= not (I_VBLANK or h256); -- active low
+    hcmp1_s     <= h256_l and I_HCMA;
+  end process;
+
+  p_reg : process
+  begin
+    wait until rising_edge(CLK);
+
+    if (ENA = '1') then
+      if (ld = '1') then
+        hcmp1    <= hcmp1_s;
+        hcmp2    <= hcmp2_s;
+        cblank_l <= cblank_s;
+        h256_l_s <= h256_l;
+        cd     <= col_reg;
+      end if;
+    end if;
+  end process;
+
+  p_load_decode : process(ld, I_HCNT, h256)
+    variable obj_load : std_logic;
+  begin
+    vpl_load         <= '0';
+    obj_load         := '0';
+    col_load         <= '0';
+
+    if (I_HCNT(2 downto 0) = "001") then vpl_load <= '1'; end if; -- 1 clock later
+    if (I_HCNT(2 downto 0) = "011") then obj_load := '1'; end if; -- 1 later
+    if (I_HCNT(2 downto 0) = "101") then col_load <= '1'; end if; -- 1 later
+
+    objdata_load <= obj_load and h256 and (not I_HCNT(3));
+    missile_load <= obj_load and h256 and (    I_HCNT(3));
+
+    cntr_clr  <= ld and (not h256) and (not I_HCNT(3));
+    cntr_load <= ld and (    h256) and (not I_HCNT(3));
+
+  end process;
+
+  p_hv_flip : process(I_HCNT, I_VCNT, I_VCMA, hcmp1_s)
+  begin
+    for i in 0 to 7 loop
+      vcnt_f(i) <= I_VCNT(i) xor I_VCMA;
+      hcnt_f(i) <= I_HCNT(i) xor hcmp1_s;
+    end loop;
+  end process;
+
+  p_video_addr_calc : process(vcnt_f, hpla)
+  begin
+    vram_addr_sum <= ('0' & vcnt_f(7 downto 0)) + ('0' & hpla(7 downto 0));
+  end process;
+
+  p_msld : process(vram_addr_sum)
+  begin
+    msld_l <= '1';
+    if (vram_addr_sum(7 downto 0) = "11111111") then
+      msld_l <= '0';
+    end if;
+  end process;
+
+  p_video_addr_reg : process
+  begin
+    wait until rising_edge(CLK);
+    if (ENA = '1') then
+      if (I_VBLANK = '1') then -- was async
+        vram_addr_reg <= x"00";
+      elsif (vpl_load = '1') then -- vpl_l
+        vram_addr_reg <= vram_addr_sum(7 downto 0);
+      end if;
+    end if;
+  end process;
+
+  p_vram_xor : process(vram_addr_reg, objdata, h256)
+    variable flip : std_logic;
+  begin
+    flip := objdata(7) and h256;
+    for i in 0 to 3 loop
+      vram_addr_xor(i) <= vram_addr_reg(i) xor flip;
+    end loop;
+  end process;
+
+  p_vram_addr : process(vram_addr_reg, cblank_s, ld, I_CPU_ADDR, vram_addr_xor, hcnt_f)
+    variable match : std_logic;
+  begin
+     match := '0';
+     if (vram_addr_reg(7 downto 4) = "1111") then
+       match := '1';
+     end if;
+
+     if (cblank_s = '0') then
+       ldout <= match and ld; -- blanking, sprites
+     else
+       ldout <= ld;
+     end if;
+
+     if (cblank_s = '0') then -- blanking, sprites
+       --vram_cs   <= (not I_VRAMWR_L) or (not I_VRAMRD_L);
+       vram_addr <= I_CPU_ADDR(9 downto 0); -- let the cpu in
+     else
+       --vram_cs   <= '1';
+       vram_addr <= vram_addr_reg(7 downto 4) & vram_addr_xor(3) & hcnt_f(7 downto 3);
+     end if;
+  end process;
+  
+	u_vram : work.dpram generic map (10,8)
+	port map
+	(
+		clk_a_i  => clk,
+		en_a_i   => ena,
+		we_i     => not I_VRAMWR_L,
+
+      addr_a_i => vram_addr,
+		data_a_i => I_CPU_DATA,  -- only cpu can write
+
+		clk_b_i  => clk,
+      addr_b_i => vram_addr,
+		data_b_o => vram_dout
+	);
+
+  O_VRAM_DATA <= vram_dout;
+  
+  p_object_ram_addr : process(h256, I_HCMA, objdata, I_HCNT, hcnt_f, I_CPU_ADDR, I_OBJEN_L)
+  begin
+    -- I believe the object ram can only be written during vblank
+
+    if (h256 = '0') then
+      hcmp2_s <= I_HCMA;
+    else
+      hcmp2_s <= objdata(6);
+    end if;
+
+    if (I_OBJEN_L = '0') then
+      obj_addr <= I_CPU_ADDR(7 downto 0);
+    else
+      obj_addr(7) <= '0';
+      obj_addr(6) <= h256;
+
+      -- A
+      if (h256 = '0') then -- normal
+        obj_addr(5) <= hcnt_f(7); --128h';
+      else                 -- sprite
+        obj_addr(5) <= hcnt_f(3) and I_HCNT(1);-- 8h' and 2h;
+      end if;
+
+      obj_addr(4 downto 2) <= hcnt_f(6 downto 4);
+
+      if (h256 = '0') then -- normal
+        obj_addr(1) <= hcnt_f(3); --8h'
+        obj_addr(0) <= I_HCNT(2); --4h
+      else
+        obj_addr(1) <= I_HCNT(2); --4h
+        obj_addr(0) <= I_HCNT(1); --2h
+      end if;
+
+    end if;
+  end process;
+
+	u_object_ram : work.dpram generic map (8,8)
+	port map
+	(
+		clk_a_i  => clk,
+		en_a_i   => ena,
+		we_i     => not I_OBJRAMWR_L,
+
+      addr_a_i => obj_addr,
+		data_a_i => I_CPU_DATA,  -- only cpu can write
+
+		clk_b_i  => clk,
+      addr_b_i => obj_addr,
+		data_b_o => hpla
+	);
+
+  p_objdata_regs : process
+  begin
+    wait until rising_edge(CLK);
+    if (ENA = '1') then
+      if (col_load = '1') then -- colour load
+        col_reg <= hpla(2 downto 0);
+      end if;
+
+      if (objdata_load = '1') then -- sprite load
+        objdata <= hpla;
+      end if;
+
+      if (I_VBLANK = '1') then -- was async
+        missile_reg_l <= '1';
+      elsif (missile_load = '1') then
+        missile_reg_l <= msld_l;
+      end if;
+    end if;
+  end process;
+
+  p_obj_rom_addr : process(h256, vram_addr_xor, vram_dout, objdata, I_HCNT)
+  begin
+    obj_rom_addr( 2 downto 0) <= vram_addr_xor(2 downto 0);
+    if (h256 = '0') then
+     -- a
+      obj_rom_addr(10 downto 3) <= vram_dout; -- background objects
+    else
+      obj_rom_addr(10 downto 3) <= objdata(5 downto 0) & vram_addr_xor(3) & (objdata(6) xor I_HCNT(3)); -- sprites
+    end if;
+  end process;
+  
+  	obj_rom0 : entity work.ROM_OBJ_0
+	port map(
+		clk   	=> CLK,
+		addr 		=> obj_rom_addr,
+		data     => obj_rom_0_dout
+	);
+	
+	obj_rom1 : entity work.ROM_OBJ_1
+	port map(
+		clk   	=> CLK,
+		addr 		=> obj_rom_addr,
+		data     => obj_rom_1_dout
+	);
+
+  p_obj_rom_shift : process
+    variable obj_rom_0_dout_s : std_logic_vector(7 downto 0);
+  begin
+    wait until rising_edge (CLK);
+    obj_rom_0_dout_s := obj_rom_0_dout;
+
+    if (ENA = '1') then
+      case shift_sel is
+        when "00" => null; -- do nothing
+
+        when "01" => shift_reg_1 <= '0' & shift_reg_1(7 downto 1); -- right
+                     shift_reg_0 <= '0' & shift_reg_0(7 downto 1);
+
+        when "10" => shift_reg_1 <= shift_reg_1(6 downto 0) & '0'; -- left
+                     shift_reg_0 <= shift_reg_0(6 downto 0) & '0';
+
+        when "11" => shift_reg_1 <= obj_rom_1_dout  (7 downto 0); -- load
+                     shift_reg_0 <= obj_rom_0_dout_s(7 downto 0);
+        when others => null;
+      end case;
+    end if;
+  end process;
+
+  p_obj_rom_shift_sel : process(hcmp2, ldout, shift_reg_1, shift_reg_0)
+  begin
+    if (hcmp2 = '0') then
+
+      shift_sel(1) <= '1';
+      shift_sel(0) <= ldout;
+      shift_op(1)  <= shift_reg_1(7);
+      shift_op(0)  <= shift_reg_0(7);
+    else
+
+      shift_sel(1) <= ldout;
+      shift_sel(0) <= '1';
+      shift_op(1)  <= shift_reg_1(0);
+      shift_op(0)  <= shift_reg_0(0);
+    end if;
+  end process;
+
+  p_video_out_logic : process(shift_op, cd, gr, gc)
+    variable vidon : std_logic;
+  begin
+    vidon := shift_op(0) or shift_op(1);
+
+    if (gr(1 downto 0) = "00") then
+      vid(1 downto 0) <= shift_op(1 downto 0);
+    else
+      vid(1 downto 0) <= gr(1 downto 0);
+    end if;
+
+    if (gc(2 downto 0) = "000") and (vidon = '1') then
+      col(2 downto 0) <= cd(2 downto 0);
+    else
+      col(2 downto 0) <= gc(2 downto 0);
+    end if;
+  end process;
+
+  p_shell_ld : process(ld, h256, I_HCNT, missile_reg_l)
+  begin
+    sld_l <= '1';
+    if (ld = '1') and (h256 = '1') and (I_HCNT(3) = '1') then
+      if (missile_reg_l = '0') and (I_HCNT(6 downto 4) /= "111") then
+        sld_l <= '0';
+      end if;
+    end if;
+
+  end process;
+
+  p_shell_reg : process
+  begin
+    wait until rising_edge(CLK);
+    if (ENA = '1') then
+
+      if (sld_l = '0') then
+        shell_cnt <= hpla;
+      elsif (cblank_l = '1') then
+        shell_cnt <= shell_cnt + "1";
+      else
+        shell_cnt <= shell_cnt;
+      end if;
+
+      if (sld_l = '0') then
+        shell_ena <= '1';
+      elsif (shell = '1') then
+        shell_ena <= '0';
+      end if;
+    end if;
+  end process;
+
+  p_shell_op : process(shell_cnt, shell_ena)
+  begin
+    -- note how T input is from QD on the bottom counter
+    -- we get a rc from xF8 to XFF
+    -- so the shell is set at count xFA (rc and bit 1)
+    shell <= '0';
+    if (shell_cnt = x"F8") then -- minus 2 as delay wrong
+      shell <= shell_ena;
+    end if;
+  end process;
+
+  p_cntr_cnt : process
+  begin
+    wait until rising_edge(CLK);
+    if (ENA = '1') then
+      if (cntr_clr = '1') and (h256_l_s = '0') then -- async
+        cntr_addr <= (others => '0');
+      elsif (cntr_load = '1') then
+        cntr_addr <= hpla(7 downto 0);
+      else
+        cntr_addr <= cntr_addr + "1";
+      end if;
+    end if;
+  end process;
+
+  p_cntr_addr : process(cntr_addr, hcmp1)
+  begin
+    cntr_addr_xor(10 downto 8) <= (others => '0');
+    for i in 0 to 7 loop
+      cntr_addr_xor(i) <= cntr_addr(i) xor hcmp1;
+    end loop;
+  end process;
+
+  p_sprite_sel : process(h256_l_s, cntr_addr_xor)
+  begin
+    sprite_sel <= '0';
+    if (h256_l_s = '0') and (cntr_addr_xor(7 downto 4) /= "0000") then
+      sprite_sel <= '1';
+    end if;
+  end process;
+
+  p_sprite_write : process
+  begin
+    wait until rising_edge(CLK);
+    if (ENA = '1') then
+      -- delay 1 clock
+      sprite_ram_ip <= (others => '0');
+      if (sprite_sel = '1') then
+        sprite_ram_ip(4 downto 2) <= col(2 downto 0);
+        sprite_ram_ip(1 downto 0) <= vid(1 downto 0);
+      end if;
+
+      sprite_ram_waddr <= cntr_addr_xor;
+    end if;
+  end process;
+
+	u_sprite_ram : work.dpram generic map (11,8)
+	port map
+	(
+		clk_a_i  => clk,
+		en_a_i   => ena,
+		we_i     => '1',
+
+      addr_a_i => sprite_ram_waddr,
+		data_a_i => sprite_ram_ip,
+
+		clk_b_i  => clk,
+      addr_b_i => cntr_addr_xor,
+		data_b_o => sprite_ram_op
+	);
+
+  gc(2 downto 0) <= sprite_ram_op(4 downto 2);
+  gr(1 downto 0) <= sprite_ram_op(1 downto 0);
+
+  p_video_out_reg : process
+    variable vidout_l_int : std_logic;
+  begin
+    wait until rising_edge(CLK);
+    -- register all objects to match increased video delay
+    if (ENA = '1') then
+      star_shift_t1 <= star_shift;
+
+      if (cblank_l = '0') then
+        -- logic around the clr workes out as a sync reset
+        obj_video_out_reg <= (others => '0');
+        shell_reg <= '0';
+        star_out_reg <= '0';
+        pout1_reg <= '0';
+      else
+
+        obj_video_out_reg(4 downto 2) <= col(2 downto 0);
+        obj_video_out_reg(1 downto 0) <= vid(1 downto 0);
+        vidout_l <= not(vid(1) or vid(0));
+        -- probably wider than the original, we must be a whole 6MHz clock here or the scan-doubler will loose it.
+        shell_reg <= shell;
+
+        star_out_reg <= '0';
+        if (star_shift(7 downto 0) = x"FF") and (star_on = '1') then
+          star_out_reg <= (vcnt_f(0) xor hcnt_f(3)) and (not star_shift(16));
+        end if;
+
+        pout1_reg <= I_POUT1;
+
+      end if;
+    end if;
+  end process;
+
+  col_rom : entity work.ROM_LUT
+    port map(
+		clk 			=> CLK, 
+      addr        => obj_video_out_reg(4 downto 0),
+      data        => obj_lut_out
+      );
+
+  p_col_rom_ce : process
+    variable video : array_3x5;
+  begin
+    wait until rising_edge(CLK);
+    if (ENA = '1') then
+      video(0)(4) := '0';
+      video(1)(4) := '0';
+      video(2)(4) := '0';
+      video(0)(3) := '0'; -- b
+      video(1)(3) := '0'; -- g
+      video(2)(3) := '0'; -- r
+
+      if (vidout_l = '0') then -- cs_l on col rom
+
+        video(0)(2 downto 0) := obj_lut_out(7 downto 6) & '0';
+        video(1)(2 downto 0) := obj_lut_out(5 downto 3);
+        video(2)(2 downto 0) := obj_lut_out(2 downto 0);
+      else
+        video(0)(2 downto 0) := "000";
+        video(1)(2 downto 0) := "000";
+        video(2)(2 downto 0) := "000";
+      end if;
+      --
+      -- end of direct assigns
+      --
+
+      video(1) := video(1) + ("00" & shell_reg & "00");
+      video(2) := video(2) + ("00" & shell_reg & "00");
+
+      -- add stars, background and video
+      if (star_out_reg = '1') and (vidout_l = '1') then
+        video(0) := video(0) + ( '0' & star_shift_t1(13 downto 12) & "00");
+        video(1) := video(1) + ( '0' & star_shift_t1(11 downto 10) & "00");
+        video(2) := video(2) + ( '0' & star_shift_t1( 9 downto  8) & "00");
+      end if;
+
+      if (pout1_reg = '1') and (vidout_l = '1') then
+        video(0) := video(0) + ("00011");
+      end if;
+      -- check for clip
+      for i in 0 to 2 loop
+        if video(i)(4) = '1' or video(i)(3) = '1' then
+          video(i)(2 downto 0) := (others => '1');
+        end if;
+      end loop;
+
+      O_VIDEO_B <= video(0)(2 downto 0) & video(0)(2);
+      O_VIDEO_G <= video(1)(2 downto 0) & video(1)(2);
+      O_VIDEO_R <= video(2)(2 downto 0) & video(2)(2);
+    end if;
+  end process;
+
+  p_stars_timer : process
+  begin
+    wait until rising_edge(CLK);
+    -- 555 period 0.8316 seconds
+    -- ~ 4DF 666
+    if (ENA = '1') then
+      if (star_cnt_div(22 downto 17) = "100111") then
+        star_cnt_div <= (others => '0');
+        star_cnt     <= star_cnt + "1";
+      else
+        star_cnt_div <= star_cnt_div + "1";
+      end if;
+    end if;
+  end process;
+
+  p_stars_demux : process(star_cnt, I_VCNT, star_shift)
+  begin
+    case star_cnt is
+      when "00" => star_on <= star_shift(8);
+      when "01" => star_on <= star_shift(10);
+      when "10" => star_on <= I_VCNT(1);
+      when "11" => star_on <= '1';
+      when others => null;
+    end case;
+  end process;
+
+  p_stars : process
+    variable star_ena : std_logic;
+    variable star_shift_ena : std_logic;
+    variable fb : std_logic;
+    variable star_clear : std_logic;
+  begin
+    wait until rising_edge(CLK);
+    -- stars clocked off 12 MHz clock
+    star_ena := ENA_12 and (not I_VSYNC) and h256_l_s;
+
+    if (ENA = '1') and (I_VSYNC = '1') then
+      star_reg_1 <= '0';
+      star_reg_2 <= '0';
+    elsif (star_ena = '1') then
+      star_reg_1 <= '1';
+      star_reg_2 <= star_reg_1;
+    end if;
+
+    star_shift_ena := (star_reg_2 or I_HCMA) and star_ena;
+
+    star_clear := I_STARSON and (not I_VBLANK);
+
+    fb := (not star_shift(16)) xor star_shift(4);
+    if    (star_clear = '0') then
+      star_shift <= (others => '0');
+    elsif (star_shift_ena = '1') then
+      star_shift(16 downto 0) <= star_shift(15 downto 0) & fb;
+    end if;
+  end process;
+
+end RTL;
diff --git a/Arcade_MiST/Scramble Hardware/The End.jpg b/Arcade_MiST/Konami Scramble Hardware/The End.jpg
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/The End.jpg
rename to Arcade_MiST/Konami Scramble Hardware/The End.jpg
diff --git a/Arcade_MiST/Scramble Hardware/TheEnd_MiST/README.txt b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/README.txt
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TheEnd_MiST/README.txt
rename to Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/README.txt
diff --git a/Arcade_MiST/Scramble Hardware/TheEnd_MiST/Release/TheEnd.rbf b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/Release/TheEnd.rbf
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TheEnd_MiST/Release/TheEnd.rbf
rename to Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/Release/TheEnd.rbf
diff --git a/Arcade_MiST/Scramble Hardware/TheEnd_MiST/TheEnd.qpf b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/TheEnd.qpf
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TheEnd_MiST/TheEnd.qpf
rename to Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/TheEnd.qpf
diff --git a/Arcade_MiST/Scramble Hardware/TheEnd_MiST/TheEnd.qsf b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/TheEnd.qsf
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TheEnd_MiST/TheEnd.qsf
rename to Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/TheEnd.qsf
diff --git a/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/TheEnd.sdc b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/TheEnd.sdc
new file mode 100644
index 00000000..f91c127c
--- /dev/null
+++ b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/TheEnd.sdc	
@@ -0,0 +1,126 @@
+## Generated SDC file "vectrex_MiST.out.sdc"
+
+## Copyright (C) 1991-2013 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Altera Program License 
+## Subscription Agreement, Altera MegaCore Function License 
+## Agreement, or other applicable license agreement, including, 
+## without limitation, that your use is for the sole purpose of 
+## programming logic devices manufactured by Altera and sold by 
+## Altera or its authorized distributors.  Please refer to the 
+## applicable agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+## DATE    "Sun Jun 24 12:53:00 2018"
+
+##
+## DEVICE  "EP3C25E144C8"
+##
+
+# Clock constraints
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {SPI_SCK}  -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {CLOCK_27}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {CONF_DATA0}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DI}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SCK}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS2}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS3}]
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DO}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {LED}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {VGA_*}]
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+set_multicycle_path -to {VGA_*[*]} -setup 2
+set_multicycle_path -to {VGA_*[*]} -hold 1
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
diff --git a/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/TheEnd.srf b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/TheEnd.srf
new file mode 100644
index 00000000..a455f0f5
--- /dev/null
+++ b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/TheEnd.srf	
@@ -0,0 +1,51 @@
+{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Found combinational loop of 47 nodes" {  } {  } 0 332125 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." {  } {  } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" {  } {  } 0 12110 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" {  } {  } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "*" {  } {  } 0 169085 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "*" {  } {  } 0 174073 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "*" {  } {  } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "*" {  } {  } 0 13009 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "*" {  } {  } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "alt_vip_cvo_mode_banks" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "hps_sdram_pll.sv" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "alt_vip_common_frame_counter.v" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "hps_sdram_p0_acv_ldc.v" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "genlock_enable_sync" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "u_calculate_mode" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "genlock_enable" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "reset_value" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "alt_vip_cvo_core.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "alt_vip_packet_transfer.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "hps_sdram_p0.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "RST" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "alt_vip_scaler_alg_core" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "cvo_core" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "vip_HPS_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "alt_vip_dil_scheduler.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
diff --git a/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/clean.bat b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/clean.bat
new file mode 100644
index 00000000..b3b7c3b5
--- /dev/null
+++ b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/clean.bat	
@@ -0,0 +1,37 @@
+@echo off
+del /s *.bak
+del /s *.orig
+del /s *.rej
+del /s *~
+rmdir /s /q db
+rmdir /s /q incremental_db
+rmdir /s /q output_files
+rmdir /s /q simulation
+rmdir /s /q greybox_tmp
+rmdir /s /q hc_output
+rmdir /s /q .qsys_edit
+rmdir /s /q hps_isw_handoff
+rmdir /s /q sys\.qsys_edit
+rmdir /s /q sys\vip
+cd sys
+for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
+cd ..
+for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
+del build_id.v
+del c5_pin_model_dump.txt
+del PLLJ_PLLSPE_INFO.txt
+del /s *.qws
+del /s *.ppf
+del /s *.ddb
+del /s *.csv
+del /s *.cmp
+del /s *.sip
+del /s *.spd
+del /s *.bsf
+del /s *.f
+del /s *.sopcinfo
+del /s *.xml
+del /s new_rtl_netlist
+del /s old_rtl_netlist
+
+pause
diff --git a/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/MULT18X18.vhd b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/MULT18X18.vhd
new file mode 100644
index 00000000..32535505
--- /dev/null
+++ b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/MULT18X18.vhd	
@@ -0,0 +1,53 @@
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY MULT18X18 IS
+	PORT
+	(
+		A		: IN STD_LOGIC_VECTOR (17 DOWNTO 0);
+		B		: IN STD_LOGIC_VECTOR (17 DOWNTO 0);
+		P		: OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
+	);
+END MULT18X18;
+
+
+ARCHITECTURE SYN OF mult18x18 IS
+
+	COMPONENT lpm_mult
+	GENERIC (
+		lpm_hint		: STRING;
+		lpm_representation		: STRING;
+		lpm_type		: STRING;
+		lpm_widtha		: NATURAL;
+		lpm_widthb		: NATURAL;
+		lpm_widthp		: NATURAL
+	);
+	PORT (
+			dataa	: IN STD_LOGIC_VECTOR (17 DOWNTO 0);
+			datab	: IN STD_LOGIC_VECTOR (17 DOWNTO 0);
+			result	: OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	lpm_mult_component : lpm_mult
+	GENERIC MAP (
+		lpm_hint => "MAXIMIZE_SPEED=5",
+		lpm_representation => "SIGNED",
+		lpm_type => "LPM_MULT",
+		lpm_widtha => 18,
+		lpm_widthb => 18,
+		lpm_widthp => 36
+	)
+	PORT MAP (
+		dataa => A,
+		datab => B,
+		result => P
+	);
+
+END SYN;
+
diff --git a/Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_LUT.vhd b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_LUT.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_LUT.vhd
rename to Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_LUT.vhd
diff --git a/Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_OBJ_0.vhd b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_OBJ_0.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_OBJ_0.vhd
rename to Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_OBJ_0.vhd
diff --git a/Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_OBJ_1.vhd b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_OBJ_1.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_OBJ_1.vhd
rename to Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_OBJ_1.vhd
diff --git a/Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_PGM.vhd b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_PGM.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_PGM.vhd
rename to Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_PGM.vhd
diff --git a/Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_SND_0.vhd b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_SND_0.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_SND_0.vhd
rename to Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_SND_0.vhd
diff --git a/Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_SND_1.vhd b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_SND_1.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_SND_1.vhd
rename to Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_SND_1.vhd
diff --git a/Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/TheEnd.sv b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/TheEnd.sv
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/TheEnd.sv
rename to Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/TheEnd.sv
diff --git a/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/YM2149_linmix_sep.vhd b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/YM2149_linmix_sep.vhd
new file mode 100644
index 00000000..6ed2498a
--- /dev/null
+++ b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/YM2149_linmix_sep.vhd	
@@ -0,0 +1,574 @@
+-- changes for seperate audio outputs and enable now enables cpu access as well
+--
+-- A simulation model of YM2149 (AY-3-8910 with bells on)
+
+-- Copyright (c) MikeJ - Jan 2005
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- You are responsible for any legal issues arising from your use of this code.
+--
+-- The latest version of this file can be found at: www.fpgaarcade.com
+--
+-- Email support@fpgaarcade.com
+--
+-- Revision list
+--
+-- version 001 initial release
+--
+-- Clues from MAME sound driver and Kazuhiro TSUJIKAWA
+--
+-- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V)
+-- vol 15 .. 0
+-- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132
+-- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order
+-- to produced all the required values.
+-- (The first part of the curve is a bit steeper and the last bit is more linear than expected)
+--
+-- NOTE, this component uses LINEAR mixing of the three analogue channels, and is only
+-- accurate for designs where the outputs are buffered and not simply wired together.
+-- The ouput level is more complex in that case and requires a larger table.
+
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_arith.all;
+  use ieee.std_logic_unsigned.all;
+
+entity YM2149 is
+  port (
+  -- data bus
+  I_DA                : in  std_logic_vector(7 downto 0);
+  O_DA                : out std_logic_vector(7 downto 0);
+  O_DA_OE_L           : out std_logic;
+  -- control
+  I_A9_L              : in  std_logic;
+  I_A8                : in  std_logic;
+  I_BDIR              : in  std_logic;
+  I_BC2               : in  std_logic;
+  I_BC1               : in  std_logic;
+  I_SEL_L             : in  std_logic;
+
+  O_AUDIO             : out std_logic_vector(7 downto 0);
+  O_CHAN              : out std_logic_vector(1 downto 0);
+  -- port a
+  I_IOA               : in  std_logic_vector(7 downto 0);
+  O_IOA               : out std_logic_vector(7 downto 0);
+  O_IOA_OE_L          : out std_logic;
+  -- port b
+  I_IOB               : in  std_logic_vector(7 downto 0);
+  O_IOB               : out std_logic_vector(7 downto 0);
+  O_IOB_OE_L          : out std_logic;
+
+  ENA                 : in  std_logic; -- clock enable for higher speed operation
+  RESET_L             : in  std_logic;
+  CLK                 : in  std_logic  -- note 6 Mhz
+  );
+end;
+
+architecture RTL of YM2149 is
+  type  array_16x8   is array (0 to 15) of std_logic_vector( 7 downto 0);
+  type  array_3x12   is array (1 to  3) of std_logic_vector(11 downto 0);
+
+  signal cnt_div              : std_logic_vector(3 downto 0) := (others => '0');
+  signal cnt_div_t1           : std_logic_vector(3 downto 0);
+  signal noise_div            : std_logic := '0';
+  signal ena_div              : std_logic;
+  signal ena_div_noise        : std_logic;
+  signal poly17               : std_logic_vector(16 downto 0) := (others => '0');
+
+  -- registers
+  signal addr                 : std_logic_vector(7 downto 0);
+  signal busctrl_addr         : std_logic;
+  signal busctrl_we           : std_logic;
+  signal busctrl_re           : std_logic;
+
+  signal reg                  : array_16x8;
+  signal env_reset            : std_logic;
+  signal ioa_inreg            : std_logic_vector(7 downto 0);
+  signal iob_inreg            : std_logic_vector(7 downto 0);
+
+  signal noise_gen_cnt        : std_logic_vector(4 downto 0);
+  signal noise_gen_op         : std_logic;
+  signal tone_gen_cnt         : array_3x12 := (others => (others => '0'));
+  signal tone_gen_op          : std_logic_vector(3 downto 1) := "000";
+
+  signal env_gen_cnt          : std_logic_vector(15 downto 0);
+  signal env_ena              : std_logic;
+  signal env_hold             : std_logic;
+  signal env_inc              : std_logic;
+  signal env_vol              : std_logic_vector(4 downto 0);
+
+  signal tone_ena_l           : std_logic;
+  signal tone_src             : std_logic;
+  signal noise_ena_l          : std_logic;
+  signal chan_vol             : std_logic_vector(4 downto 0);
+
+  signal dac_amp              : std_logic_vector(7 downto 0);
+begin
+  -- cpu i/f
+  p_busdecode            : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8)
+    variable cs : std_logic;
+    variable sel : std_logic_vector(2 downto 0);
+  begin
+    -- BDIR BC2 BC1 MODE
+    --   0   0   0  inactive
+    --   0   0   1  address
+    --   0   1   0  inactive
+    --   0   1   1  read
+    --   1   0   0  address
+    --   1   0   1  inactive
+    --   1   1   0  write
+    --   1   1   1  read
+    busctrl_addr <= '0';
+    busctrl_we <= '0';
+    busctrl_re <= '0';
+
+    cs := '0';
+    if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then
+      cs := '1';
+    end if;
+
+    sel := (I_BDIR & I_BC2 & I_BC1);
+    case sel is
+      when "000" => null;
+      when "001" => busctrl_addr <= '1';
+      when "010" => null;
+      when "011" => busctrl_re   <= cs;
+      when "100" => busctrl_addr <= '1';
+      when "101" => null;
+      when "110" => busctrl_we   <= cs;
+      when "111" => busctrl_addr <= '1';
+      when others => null;
+    end case;
+  end process;
+
+  p_oe                   : process(busctrl_re)
+  begin
+    -- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns
+    O_DA_OE_L <= not (busctrl_re);
+  end process;
+
+  --
+  -- CLOCKED
+  --
+  p_waddr                : process(RESET_L, CLK)
+  begin
+    -- looks like registers are latches in real chip, but the address is caught at the end of the address state.
+    if (RESET_L = '0') then
+      addr <= (others => '0');
+    elsif rising_edge(CLK) then
+      if (ENA = '1') then
+        if (busctrl_addr = '1') then
+          addr <= I_DA;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  p_wdata                : process(RESET_L, CLK)
+  begin
+    if (RESET_L = '0') then
+      reg <= (others => (others => '0'));
+      env_reset <= '1';
+    elsif rising_edge(CLK) then
+      if (ENA = '1') then
+        env_reset <= '0';
+        if (busctrl_we = '1') then
+          case addr(3 downto 0) is
+            when x"0" => reg(0)  <= I_DA;
+            when x"1" => reg(1)  <= I_DA;
+            when x"2" => reg(2)  <= I_DA;
+            when x"3" => reg(3)  <= I_DA;
+            when x"4" => reg(4)  <= I_DA;
+            when x"5" => reg(5)  <= I_DA;
+            when x"6" => reg(6)  <= I_DA;
+            when x"7" => reg(7)  <= I_DA;
+            when x"8" => reg(8)  <= I_DA;
+            when x"9" => reg(9)  <= I_DA;
+            when x"A" => reg(10) <= I_DA;
+            when x"B" => reg(11) <= I_DA;
+            when x"C" => reg(12) <= I_DA;
+            when x"D" => reg(13) <= I_DA; env_reset <= '1';
+            when x"E" => reg(14) <= I_DA;
+            when x"F" => reg(15) <= I_DA;
+            when others => null;
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  p_rdata                : process(busctrl_re, addr, reg, ioa_inreg, iob_inreg)
+  begin
+    O_DA <= (others => '0'); -- 'X'
+    if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator
+      case addr(3 downto 0) is
+        when x"0" => O_DA <= reg(0) ;
+        when x"1" => O_DA <= "0000" & reg(1)(3 downto 0) ;
+        when x"2" => O_DA <= reg(2) ;
+        when x"3" => O_DA <= "0000" & reg(3)(3 downto 0) ;
+        when x"4" => O_DA <= reg(4) ;
+        when x"5" => O_DA <= "0000" & reg(5)(3 downto 0) ;
+        when x"6" => O_DA <= "000"  & reg(6)(4 downto 0) ;
+        when x"7" => O_DA <= reg(7) ;
+        when x"8" => O_DA <= "000"  & reg(8)(4 downto 0) ;
+        when x"9" => O_DA <= "000"  & reg(9)(4 downto 0) ;
+        when x"A" => O_DA <= "000"  & reg(10)(4 downto 0) ;
+        when x"B" => O_DA <= reg(11);
+        when x"C" => O_DA <= reg(12);
+        when x"D" => O_DA <= "0000" & reg(13)(3 downto 0);
+        when x"E" => if (reg(7)(6) = '0') then -- input
+                       O_DA <= ioa_inreg;
+                     else
+                       O_DA <= reg(14); -- read output reg
+                     end if;
+        when x"F" => if (Reg(7)(7) = '0') then
+                       O_DA <= iob_inreg;
+                     else
+                       O_DA <= reg(15);
+                     end if;
+        when others => null;
+      end case;
+    end if;
+  end process;
+  --
+  p_divider              : process
+  begin
+    wait until rising_edge(CLK);
+    -- / 8 when SEL is high and /16 when SEL is low
+    if (ENA = '1') then
+      ena_div <= '0';
+      ena_div_noise <= '0';
+      if (cnt_div = "0000") then
+        cnt_div <= (not I_SEL_L) & "111";
+        ena_div <= '1';
+
+        noise_div <= not noise_div;
+        if (noise_div = '1') then
+          ena_div_noise <= '1';
+        end if;
+      else
+        cnt_div <= cnt_div - "1";
+      end if;
+    end if;
+  end process;
+
+  p_noise_gen            : process
+    variable noise_gen_comp : std_logic_vector(4 downto 0);
+    variable poly17_zero : std_logic;
+  begin
+    wait until rising_edge(CLK);
+    if (reg(6)(4 downto 0) = "00000") then
+      noise_gen_comp := "00000";
+    else
+      noise_gen_comp := (reg(6)(4 downto 0) - "1");
+    end if;
+
+    poly17_zero := '0';
+    if (poly17 = "00000000000000000") then poly17_zero := '1'; end if;
+
+    if (ENA = '1') then
+      if (ena_div_noise = '1') then -- divider ena
+
+        if (noise_gen_cnt >= noise_gen_comp) then
+          noise_gen_cnt <= "00000";
+          poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1);
+        else
+          noise_gen_cnt <= (noise_gen_cnt + "1");
+        end if;
+      end if;
+    end if;
+  end process;
+  noise_gen_op <= poly17(0);
+
+  p_tone_gens            : process
+    variable tone_gen_freq : array_3x12;
+    variable tone_gen_comp : array_3x12;
+  begin
+    wait until rising_edge(CLK);
+    -- looks like real chips count up - we need to get the Exact behaviour ..
+    tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0);
+    tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2);
+    tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4);
+    -- period 0 = period 1
+    for i in 1 to 3 loop
+      if (tone_gen_freq(i) = x"000") then
+        tone_gen_comp(i) := x"000";
+      else
+        tone_gen_comp(i) := (tone_gen_freq(i) - "1");
+      end if;
+    end loop;
+
+    if (ENA = '1') then
+      for i in 1 to 3 loop
+        if (ena_div = '1') then -- divider ena
+
+          if (tone_gen_cnt(i) >= tone_gen_comp(i)) then
+            tone_gen_cnt(i) <= x"000";
+            tone_gen_op(i) <= not tone_gen_op(i);
+          else
+            tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1");
+          end if;
+        end if;
+      end loop;
+    end if;
+  end process;
+
+  p_envelope_freq        : process
+    variable env_gen_freq : std_logic_vector(15 downto 0);
+    variable env_gen_comp : std_logic_vector(15 downto 0);
+  begin
+    wait until rising_edge(CLK);
+    env_gen_freq := reg(12) & reg(11);
+    -- envelope freqs 1 and 0 are the same.
+    if (env_gen_freq = x"0000") then
+      env_gen_comp := x"0000";
+    else
+      env_gen_comp := (env_gen_freq - "1");
+    end if;
+
+    if (ENA = '1') then
+      env_ena <= '0';
+      if (ena_div = '1') then -- divider ena
+        if (env_gen_cnt >= env_gen_comp) then
+          env_gen_cnt <= x"0000";
+          env_ena <= '1';
+        else
+          env_gen_cnt <= (env_gen_cnt + "1");
+        end if;
+      end if;
+    end if;
+  end process;
+
+  p_envelope_shape       : process(env_reset, reg, CLK)
+    variable is_bot    : boolean;
+    variable is_bot_p1 : boolean;
+    variable is_top_m1 : boolean;
+    variable is_top    : boolean;
+  begin
+        -- envelope shapes
+        -- C AtAlH
+        -- 0 0 x x  \___
+        --
+        -- 0 1 x x  /___
+        --
+        -- 1 0 0 0  \\\\
+        --
+        -- 1 0 0 1  \___
+        --
+        -- 1 0 1 0  \/\/
+        --           ___
+        -- 1 0 1 1  \
+        --
+        -- 1 1 0 0  ////
+        --           ___
+        -- 1 1 0 1  /
+        --
+        -- 1 1 1 0  /\/\
+        --
+        -- 1 1 1 1  /___
+    if (env_reset = '1') then
+      -- load initial state
+      if (reg(13)(2) = '0') then -- attack
+        env_vol <= "11111";
+        env_inc <= '0'; -- -1
+      else
+        env_vol <= "00000";
+        env_inc <= '1'; -- +1
+      end if;
+      env_hold <= '0';
+
+    elsif rising_edge(CLK) then
+      is_bot    := (env_vol = "00000");
+      is_bot_p1 := (env_vol = "00001");
+      is_top_m1 := (env_vol = "11110");
+      is_top    := (env_vol = "11111");
+
+      if (ENA = '1') then
+        if (env_ena = '1') then
+          if (env_hold = '0') then
+            if (env_inc = '1') then
+              env_vol <= (env_vol + "00001");
+            else
+              env_vol <= (env_vol + "11111");
+            end if;
+          end if;
+
+          -- envelope shape control.
+          if (reg(13)(3) = '0') then
+            if (env_inc = '0') then -- down
+              if is_bot_p1 then env_hold <= '1'; end if;
+            else
+              if is_top then env_hold <= '1'; end if;
+            end if;
+          else
+            if (reg(13)(0) = '1') then -- hold = 1
+              if (env_inc = '0') then -- down
+                if (reg(13)(1) = '1') then -- alt
+                  if is_bot    then env_hold <= '1'; end if;
+                else
+                  if is_bot_p1 then env_hold <= '1'; end if;
+                end if;
+              else
+                if (reg(13)(1) = '1') then -- alt
+                  if is_top    then env_hold <= '1'; end if;
+                else
+                  if is_top_m1 then env_hold <= '1'; end if;
+                end if;
+              end if;
+
+            elsif (reg(13)(1) = '1') then -- alternate
+              if (env_inc = '0') then -- down
+                if is_bot_p1 then env_hold <= '1'; end if;
+                if is_bot    then env_hold <= '0'; env_inc <= '1'; end if;
+              else
+                if is_top_m1 then env_hold <= '1'; end if;
+                if is_top    then env_hold <= '0'; env_inc <= '0'; end if;
+              end if;
+            end if;
+
+          end if;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  p_chan_mixer           : process(cnt_div, reg, tone_gen_op)
+  begin
+    tone_ena_l  <= '1'; tone_src <= '1';
+    noise_ena_l <= '1'; chan_vol <= "00000";
+    case cnt_div(1 downto 0) is
+      when "00" =>
+        tone_ena_l  <= reg(7)(0); tone_src <= tone_gen_op(1); chan_vol <= reg(8)(4 downto 0);
+        noise_ena_l <= reg(7)(3);
+      when "01" =>
+        tone_ena_l  <= reg(7)(1); tone_src <= tone_gen_op(2); chan_vol <= reg(9)(4 downto 0);
+        noise_ena_l <= reg(7)(4);
+      when "10" =>
+        tone_ena_l  <= reg(7)(2); tone_src <= tone_gen_op(3); chan_vol <= reg(10)(4 downto 0);
+        noise_ena_l <= reg(7)(5);
+      when "11" => null; -- tone gen outputs become valid on this clock
+      when others => null;
+    end case;
+  end process;
+
+  p_op_mixer             : process
+    variable chan_mixed : std_logic;
+    variable chan_amp : std_logic_vector(4 downto 0);
+  begin
+    wait until rising_edge(CLK);
+    if (ENA = '1') then
+
+      chan_mixed := (tone_ena_l or tone_src) and (noise_ena_l or noise_gen_op);
+
+      chan_amp := (others => '0');
+      if (chan_mixed = '1') then
+        if (chan_vol(4) = '0') then
+          if (chan_vol(3 downto 0) = "0000") then -- nothing is easy ! make sure quiet is quiet
+            chan_amp := "00000";
+          else
+            chan_amp := chan_vol(3 downto 0) & '1'; -- make sure level 31 (env) = level 15 (tone)
+          end if;
+        else
+          chan_amp := env_vol(4 downto 0);
+        end if;
+      end if;
+
+      dac_amp <= x"00";
+      case chan_amp is
+        when "11111" => dac_amp <= x"FF";
+        when "11110" => dac_amp <= x"D9";
+        when "11101" => dac_amp <= x"BA";
+        when "11100" => dac_amp <= x"9F";
+        when "11011" => dac_amp <= x"88";
+        when "11010" => dac_amp <= x"74";
+        when "11001" => dac_amp <= x"63";
+        when "11000" => dac_amp <= x"54";
+        when "10111" => dac_amp <= x"48";
+        when "10110" => dac_amp <= x"3D";
+        when "10101" => dac_amp <= x"34";
+        when "10100" => dac_amp <= x"2C";
+        when "10011" => dac_amp <= x"25";
+        when "10010" => dac_amp <= x"1F";
+        when "10001" => dac_amp <= x"1A";
+        when "10000" => dac_amp <= x"16";
+        when "01111" => dac_amp <= x"13";
+        when "01110" => dac_amp <= x"10";
+        when "01101" => dac_amp <= x"0D";
+        when "01100" => dac_amp <= x"0B";
+        when "01011" => dac_amp <= x"09";
+        when "01010" => dac_amp <= x"08";
+        when "01001" => dac_amp <= x"07";
+        when "01000" => dac_amp <= x"06";
+        when "00111" => dac_amp <= x"05";
+        when "00110" => dac_amp <= x"04";
+        when "00101" => dac_amp <= x"03";
+        when "00100" => dac_amp <= x"03";
+        when "00011" => dac_amp <= x"02";
+        when "00010" => dac_amp <= x"02";
+        when "00001" => dac_amp <= x"01";
+        when "00000" => dac_amp <= x"00";
+        when others => null;
+      end case;
+
+      cnt_div_t1 <= cnt_div;
+    end if;
+  end process;
+
+  p_audio_output         : process(RESET_L, CLK)
+  begin
+    if (RESET_L = '0') then
+      O_AUDIO <= (others => '0');
+      O_CHAN  <= (others => '0');
+    elsif rising_edge(CLK) then
+
+      if (ENA = '1') then
+        O_AUDIO <= dac_amp(7 downto 0);
+        O_CHAN  <= cnt_div_t1(1 downto 0);
+      end if;
+    end if;
+  end process;
+
+  p_io_ports             : process(reg)
+  begin
+    O_IOA      <= reg(14);
+    O_IOA_OE_L <= not reg(7)(6);
+    O_IOB      <= reg(15);
+    O_IOB_OE_L <= not reg(7)(7);
+  end process;
+
+  p_io_ports_inreg       : process
+  begin
+    wait until rising_edge(CLK);
+    if (ENA = '1') then -- resync
+      ioa_inreg <= I_IOA;
+      iob_inreg <= I_IOB;
+    end if;
+  end process;
+end architecture RTL;
diff --git a/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/build_id.tcl b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/build_id.tcl
new file mode 100644
index 00000000..938515d8
--- /dev/null
+++ b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/build_id.tcl	
@@ -0,0 +1,35 @@
+# ================================================================================
+#
+# Build ID Verilog Module Script
+# Jeff Wiencrot - 8/1/2011
+#
+# Generates a Verilog module that contains a timestamp,
+# from the current build. These values are available from the build_date, build_time,
+# physical_address, and host_name output ports of the build_id module in the build_id.v
+# Verilog source file.
+#
+# ================================================================================
+
+proc generateBuildID_Verilog {} {
+
+	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
+	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
+	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
+
+	# Create a Verilog file for output
+	set outputFileName "rtl/build_id.v"
+	set outputFile [open $outputFileName "w"]
+
+	# Output the Verilog source
+	puts $outputFile "`define BUILD_DATE \"$buildDate\""
+	puts $outputFile "`define BUILD_TIME \"$buildTime\""
+	close $outputFile
+
+	# Send confirmation message to the Messages window
+	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
+	post_message "Date:             $buildDate"
+	post_message "Time:             $buildTime"
+}
+
+# Comment out this line to prevent the process from automatically executing when the file is sourced:
+generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/cpu/T80.vhd
new file mode 100644
index 00000000..da01f6b4
--- /dev/null
+++ b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/cpu/T80.vhd	
@@ -0,0 +1,1080 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
+--
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--
+--      0210 : Fixed wait and halt
+--
+--      0211 : Fixed Refresh addition and IM 1
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
+--
+--      0235 : Added clock enable and IM 2 fix by Mike Johnson
+--
+--      0237 : Changed 8080 I/O address output, added IntE output
+--
+--      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
+--
+--      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
+--
+--      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
+--
+--      0247 : Fixed bus req/ack cycle
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80 is
+	generic(
+		Mode   : integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in  std_logic;
+		CLK_n           : in  std_logic;
+		CEN             : in  std_logic;
+		WAIT_n          : in  std_logic;
+		INT_n           : in  std_logic;
+		NMI_n           : in  std_logic;
+		BUSRQ_n         : in  std_logic;
+		M1_n            : out std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DInst           : in  std_logic_vector(7 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0);
+		MC              : out std_logic_vector(2 downto 0);
+		TS              : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out std_logic
+	);
+end T80;
+
+architecture rtl of T80 is
+
+	constant aNone              : std_logic_vector(2 downto 0) := "111";
+	constant aBC                : std_logic_vector(2 downto 0) := "000";
+	constant aDE                : std_logic_vector(2 downto 0) := "001";
+	constant aXY                : std_logic_vector(2 downto 0) := "010";
+	constant aIOA               : std_logic_vector(2 downto 0) := "100";
+	constant aSP                : std_logic_vector(2 downto 0) := "101";
+	constant aZI                : std_logic_vector(2 downto 0) := "110";
+
+	-- Registers
+	signal ACC, F               : std_logic_vector(7 downto 0);
+	signal Ap, Fp               : std_logic_vector(7 downto 0);
+	signal I                    : std_logic_vector(7 downto 0);
+	signal R                    : unsigned(7 downto 0);
+	signal SP, PC               : unsigned(15 downto 0);
+
+	signal RegDIH               : std_logic_vector(7 downto 0);
+	signal RegDIL               : std_logic_vector(7 downto 0);
+	signal RegBusA              : std_logic_vector(15 downto 0);
+	signal RegBusB              : std_logic_vector(15 downto 0);
+	signal RegBusC              : std_logic_vector(15 downto 0);
+	signal RegAddrA_r           : std_logic_vector(2 downto 0);
+	signal RegAddrA             : std_logic_vector(2 downto 0);
+	signal RegAddrB_r           : std_logic_vector(2 downto 0);
+	signal RegAddrB             : std_logic_vector(2 downto 0);
+	signal RegAddrC             : std_logic_vector(2 downto 0);
+	signal RegWEH               : std_logic;
+	signal RegWEL               : std_logic;
+	signal Alternate            : std_logic;
+
+	-- Help Registers
+	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
+	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
+	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
+	signal RegBusA_r            : std_logic_vector(15 downto 0);
+
+	signal ID16                 : signed(15 downto 0);
+	signal Save_Mux             : std_logic_vector(7 downto 0);
+
+	signal TState               : unsigned(2 downto 0);
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal IntE_FF1             : std_logic;
+	signal IntE_FF2             : std_logic;
+	signal Halt_FF              : std_logic;
+	signal BusReq_s             : std_logic;
+	signal BusAck               : std_logic;
+	signal ClkEn                : std_logic;
+	signal NMI_s                : std_logic;
+	signal INT_s                : std_logic;
+	signal IStatus              : std_logic_vector(1 downto 0);
+
+	signal DI_Reg               : std_logic_vector(7 downto 0);
+	signal T_Res                : std_logic;
+	signal XY_State             : std_logic_vector(1 downto 0);
+	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
+	signal NextIs_XY_Fetch      : std_logic;
+	signal XY_Ind               : std_logic;
+	signal No_BTR               : std_logic;
+	signal BTR_r                : std_logic;
+	signal Auto_Wait            : std_logic;
+	signal Auto_Wait_t1         : std_logic;
+	signal Auto_Wait_t2         : std_logic;
+	signal IncDecZ              : std_logic;
+
+	-- ALU signals
+	signal BusB                 : std_logic_vector(7 downto 0);
+	signal BusA                 : std_logic_vector(7 downto 0);
+	signal ALU_Q                : std_logic_vector(7 downto 0);
+	signal F_Out                : std_logic_vector(7 downto 0);
+
+	-- Registered micro code outputs
+	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
+	signal Arith16_r            : std_logic;
+	signal Z16_r                : std_logic;
+	signal ALU_Op_r             : std_logic_vector(3 downto 0);
+	signal Save_ALU_r           : std_logic;
+	signal PreserveC_r          : std_logic;
+	signal MCycles              : std_logic_vector(2 downto 0);
+
+	-- Micro code outputs
+	signal MCycles_d            : std_logic_vector(2 downto 0);
+	signal TStates              : std_logic_vector(2 downto 0);
+	signal IntCycle             : std_logic;
+	signal NMICycle             : std_logic;
+	signal Inc_PC               : std_logic;
+	signal Inc_WZ               : std_logic;
+	signal IncDec_16            : std_logic_vector(3 downto 0);
+	signal Prefix               : std_logic_vector(1 downto 0);
+	signal Read_To_Acc          : std_logic;
+	signal Read_To_Reg          : std_logic;
+	signal Set_BusB_To          : std_logic_vector(3 downto 0);
+	signal Set_BusA_To          : std_logic_vector(3 downto 0);
+	signal ALU_Op               : std_logic_vector(3 downto 0);
+	signal Save_ALU             : std_logic;
+	signal PreserveC            : std_logic;
+	signal Arith16              : std_logic;
+	signal Set_Addr_To          : std_logic_vector(2 downto 0);
+	signal Jump                 : std_logic;
+	signal JumpE                : std_logic;
+	signal JumpXY               : std_logic;
+	signal Call                 : std_logic;
+	signal RstP                 : std_logic;
+	signal LDZ                  : std_logic;
+	signal LDW                  : std_logic;
+	signal LDSPHL               : std_logic;
+	signal IORQ_i               : std_logic;
+	signal Special_LD           : std_logic_vector(2 downto 0);
+	signal ExchangeDH           : std_logic;
+	signal ExchangeRp           : std_logic;
+	signal ExchangeAF           : std_logic;
+	signal ExchangeRS           : std_logic;
+	signal I_DJNZ               : std_logic;
+	signal I_CPL                : std_logic;
+	signal I_CCF                : std_logic;
+	signal I_SCF                : std_logic;
+	signal I_RETN               : std_logic;
+	signal I_BT                 : std_logic;
+	signal I_BC                 : std_logic;
+	signal I_BTR                : std_logic;
+	signal I_RLD                : std_logic;
+	signal I_RRD                : std_logic;
+	signal I_INRC               : std_logic;
+	signal SetDI                : std_logic;
+	signal SetEI                : std_logic;
+	signal IMode                : std_logic_vector(1 downto 0);
+	signal Halt                 : std_logic;
+
+begin
+
+	mcode : T80_MCode
+		generic map(
+			Mode   => Mode,
+			Flag_C => Flag_C,
+			Flag_N => Flag_N,
+			Flag_P => Flag_P,
+			Flag_X => Flag_X,
+			Flag_H => Flag_H,
+			Flag_Y => Flag_Y,
+			Flag_Z => Flag_Z,
+			Flag_S => Flag_S)
+		port map(
+			IR          => IR,
+			ISet        => ISet,
+			MCycle      => MCycle,
+			F           => F,
+			NMICycle    => NMICycle,
+			IntCycle    => IntCycle,
+			MCycles     => MCycles_d,
+			TStates     => TStates,
+			Prefix      => Prefix,
+			Inc_PC      => Inc_PC,
+			Inc_WZ      => Inc_WZ,
+			IncDec_16   => IncDec_16,
+			Read_To_Acc => Read_To_Acc,
+			Read_To_Reg => Read_To_Reg,
+			Set_BusB_To => Set_BusB_To,
+			Set_BusA_To => Set_BusA_To,
+			ALU_Op      => ALU_Op,
+			Save_ALU    => Save_ALU,
+			PreserveC   => PreserveC,
+			Arith16     => Arith16,
+			Set_Addr_To => Set_Addr_To,
+			IORQ        => IORQ_i,
+			Jump        => Jump,
+			JumpE       => JumpE,
+			JumpXY      => JumpXY,
+			Call        => Call,
+			RstP        => RstP,
+			LDZ         => LDZ,
+			LDW         => LDW,
+			LDSPHL      => LDSPHL,
+			Special_LD  => Special_LD,
+			ExchangeDH  => ExchangeDH,
+			ExchangeRp  => ExchangeRp,
+			ExchangeAF  => ExchangeAF,
+			ExchangeRS  => ExchangeRS,
+			I_DJNZ      => I_DJNZ,
+			I_CPL       => I_CPL,
+			I_CCF       => I_CCF,
+			I_SCF       => I_SCF,
+			I_RETN      => I_RETN,
+			I_BT        => I_BT,
+			I_BC        => I_BC,
+			I_BTR       => I_BTR,
+			I_RLD       => I_RLD,
+			I_RRD       => I_RRD,
+			I_INRC      => I_INRC,
+			SetDI       => SetDI,
+			SetEI       => SetEI,
+			IMode       => IMode,
+			Halt        => Halt,
+			NoRead      => NoRead,
+			Write       => Write);
+
+	alu : T80_ALU
+		generic map(
+			Mode   => Mode,
+			Flag_C => Flag_C,
+			Flag_N => Flag_N,
+			Flag_P => Flag_P,
+			Flag_X => Flag_X,
+			Flag_H => Flag_H,
+			Flag_Y => Flag_Y,
+			Flag_Z => Flag_Z,
+			Flag_S => Flag_S)
+		port map(
+			Arith16 => Arith16_r,
+			Z16     => Z16_r,
+			ALU_Op  => ALU_Op_r,
+			IR      => IR(5 downto 0),
+			ISet    => ISet,
+			BusA    => BusA,
+			BusB    => BusB,
+			F_In    => F,
+			Q       => ALU_Q,
+			F_Out   => F_Out);
+
+	ClkEn <= CEN and not BusAck;
+
+	T_Res <= '1' when TState = unsigned(TStates) else '0';
+
+	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
+							((Set_Addr_To = aXY) or
+							(MCycle = "001" and IR = "11001011") or
+							(MCycle = "001" and IR = "00110110")) else '0';
+
+	Save_Mux <= BusB when ExchangeRp = '1' else
+		DI_Reg when Save_ALU_r = '0' else
+		ALU_Q;
+
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			PC <= (others => '0');  -- Program Counter
+			A <= (others => '0');
+			TmpAddr <= (others => '0');
+			IR <= "00000000";
+			ISet <= "00";
+			XY_State <= "00";
+			IStatus <= "00";
+			MCycles <= "000";
+			DO <= "00000000";
+
+			ACC <= (others => '1');
+			F <= (others => '1');
+			Ap <= (others => '1');
+			Fp <= (others => '1');
+			I <= (others => '0');
+			R <= (others => '0');
+			SP <= (others => '1');
+			Alternate <= '0';
+
+			Read_To_Reg_r <= "00000";
+			F <= (others => '1');
+			Arith16_r <= '0';
+			BTR_r <= '0';
+			Z16_r <= '0';
+			ALU_Op_r <= "0000";
+			Save_ALU_r <= '0';
+			PreserveC_r <= '0';
+			XY_Ind <= '0';
+
+		elsif CLK_n'event and CLK_n = '1' then
+
+			if ClkEn = '1' then
+
+			ALU_Op_r <= "0000";
+			Save_ALU_r <= '0';
+			Read_To_Reg_r <= "00000";
+
+			MCycles <= MCycles_d;
+
+			if IMode /= "11" then
+				IStatus <= IMode;
+			end if;
+
+			Arith16_r <= Arith16;
+			PreserveC_r <= PreserveC;
+			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
+				Z16_r <= '1';
+			else
+				Z16_r <= '0';
+			end if;
+
+			if MCycle  = "001" and TState(2) = '0' then
+			-- MCycle = 1 and TState = 1, 2, or 3
+
+				if TState = 2 and Wait_n = '1' then
+					if Mode < 2 then
+						A(7 downto 0) <= std_logic_vector(R);
+						A(15 downto 8) <= I;
+						R(6 downto 0) <= R(6 downto 0) + 1;
+					end if;
+
+					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
+						PC <= PC + 1;
+					end if;
+
+					if IntCycle = '1' and IStatus = "01" then
+						IR <= "11111111";
+					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
+						IR <= "00000000";
+					else
+						IR <= DInst;
+					end if;
+
+					ISet <= "00";
+					if Prefix /= "00" then
+						if Prefix = "11" then
+							if IR(5) = '1' then
+								XY_State <= "10";
+							else
+								XY_State <= "01";
+							end if;
+						else
+							if Prefix = "10" then
+								XY_State <= "00";
+								XY_Ind <= '0';
+							end if;
+							ISet <= Prefix;
+						end if;
+					else
+						XY_State <= "00";
+						XY_Ind <= '0';
+					end if;
+				end if;
+
+			else
+			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
+
+				if MCycle = "110" then
+					XY_Ind <= '1';
+					if Prefix = "01" then
+						ISet <= "01";
+					end if;
+				end if;
+
+				if T_Res = '1' then
+					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
+					if Jump = '1' then
+						A(15 downto 8) <= DI_Reg;
+						A(7 downto 0) <= TmpAddr(7 downto 0);
+						PC(15 downto 8) <= unsigned(DI_Reg);
+						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+					elsif JumpXY = '1' then
+						A <= RegBusC;
+						PC <= unsigned(RegBusC);
+					elsif Call = '1' or RstP = '1' then
+						A <= TmpAddr;
+						PC <= unsigned(TmpAddr);
+					elsif MCycle = MCycles and NMICycle = '1' then
+						A <= "0000000001100110";
+						PC <= "0000000001100110";
+					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
+						A(15 downto 8) <= I;
+						A(7 downto 0) <= TmpAddr(7 downto 0);
+						PC(15 downto 8) <= unsigned(I);
+						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+					else
+						case Set_Addr_To is
+						when aXY =>
+							if XY_State = "00" then
+								A <= RegBusC;
+							else
+								if NextIs_XY_Fetch = '1' then
+									A <= std_logic_vector(PC);
+								else
+									A <= TmpAddr;
+								end if;
+							end if;
+						when aIOA =>
+							if Mode = 3 then
+								-- Memory map I/O on GBZ80
+								A(15 downto 8) <= (others => '1');
+							elsif Mode = 2 then
+								-- Duplicate I/O address on 8080
+								A(15 downto 8) <= DI_Reg;
+							else
+								A(15 downto 8) <= ACC;
+							end if;
+							A(7 downto 0) <= DI_Reg;
+						when aSP =>
+							A <= std_logic_vector(SP);
+						when aBC =>
+							if Mode = 3 and IORQ_i = '1' then
+								-- Memory map I/O on GBZ80
+								A(15 downto 8) <= (others => '1');
+								A(7 downto 0) <= RegBusC(7 downto 0);
+							else
+								A <= RegBusC;
+							end if;
+						when aDE =>
+							A <= RegBusC;
+						when aZI =>
+							if Inc_WZ = '1' then
+								A <= std_logic_vector(unsigned(TmpAddr) + 1);
+							else
+								A(15 downto 8) <= DI_Reg;
+								A(7 downto 0) <= TmpAddr(7 downto 0);
+							end if;
+						when others =>
+							A <= std_logic_vector(PC);
+						end case;
+					end if;
+
+					Save_ALU_r <= Save_ALU;
+					ALU_Op_r <= ALU_Op;
+
+					if I_CPL = '1' then
+						-- CPL
+						ACC <= not ACC;
+						F(Flag_Y) <= not ACC(5);
+						F(Flag_H) <= '1';
+						F(Flag_X) <= not ACC(3);
+						F(Flag_N) <= '1';
+					end if;
+					if I_CCF = '1' then
+						-- CCF
+						F(Flag_C) <= not F(Flag_C);
+						F(Flag_Y) <= ACC(5);
+						F(Flag_H) <= F(Flag_C);
+						F(Flag_X) <= ACC(3);
+						F(Flag_N) <= '0';
+					end if;
+					if I_SCF = '1' then
+						-- SCF
+						F(Flag_C) <= '1';
+						F(Flag_Y) <= ACC(5);
+						F(Flag_H) <= '0';
+						F(Flag_X) <= ACC(3);
+						F(Flag_N) <= '0';
+					end if;
+				end if;
+
+				if TState = 2 and Wait_n = '1' then
+					if ISet = "01" and MCycle = "111" then
+						IR <= DInst;
+					end if;
+					if JumpE = '1' then
+						PC <= unsigned(signed(PC) + signed(DI_Reg));
+					elsif Inc_PC = '1' then
+						PC <= PC + 1;
+					end if;
+					if BTR_r = '1' then
+						PC <= PC - 2;
+					end if;
+					if RstP = '1' then
+						TmpAddr <= (others =>'0');
+						TmpAddr(5 downto 3) <= IR(5 downto 3);
+					end if;
+				end if;
+				if TState = 3 and MCycle = "110" then
+					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
+				end if;
+
+				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
+					if IncDec_16(2 downto 0) = "111" then
+						if IncDec_16(3) = '1' then
+							SP <= SP - 1;
+						else
+							SP <= SP + 1;
+						end if;
+					end if;
+				end if;
+
+				if LDSPHL = '1' then
+					SP <= unsigned(RegBusC);
+				end if;
+				if ExchangeAF = '1' then
+					Ap <= ACC;
+					ACC <= Ap;
+					Fp <= F;
+					F <= Fp;
+				end if;
+				if ExchangeRS = '1' then
+					Alternate <= not Alternate;
+				end if;
+			end if;
+
+			if TState = 3 then
+				if LDZ = '1' then
+					TmpAddr(7 downto 0) <= DI_Reg;
+				end if;
+				if LDW = '1' then
+					TmpAddr(15 downto 8) <= DI_Reg;
+				end if;
+
+				if Special_LD(2) = '1' then
+					case Special_LD(1 downto 0) is
+					when "00" =>
+						ACC <= I;
+						F(Flag_P) <= IntE_FF2;
+					when "01" =>
+						ACC <= std_logic_vector(R);
+						F(Flag_P) <= IntE_FF2;
+					when "10" =>
+						I <= ACC;
+					when others =>
+						R <= unsigned(ACC);
+					end case;
+				end if;
+			end if;
+
+			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
+				if Mode = 3 then
+					F(6) <= F_Out(6);
+					F(5) <= F_Out(5);
+					F(7) <= F_Out(7);
+					if PreserveC_r = '0' then
+						F(4) <= F_Out(4);
+					end if;
+				else
+					F(7 downto 1) <= F_Out(7 downto 1);
+					if PreserveC_r = '0' then
+						F(Flag_C) <= F_Out(0);
+					end if;
+				end if;
+			end if;
+			if T_Res = '1' and I_INRC = '1' then
+				F(Flag_H) <= '0';
+				F(Flag_N) <= '0';
+				if DI_Reg(7 downto 0) = "00000000" then
+					F(Flag_Z) <= '1';
+				else
+					F(Flag_Z) <= '0';
+				end if;
+				F(Flag_S) <= DI_Reg(7);
+				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
+					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
+			end if;
+
+			if TState = 1 then
+				DO <= BusB;
+				if I_RLD = '1' then
+					DO(3 downto 0) <= BusA(3 downto 0);
+					DO(7 downto 4) <= BusB(3 downto 0);
+				end if;
+				if I_RRD = '1' then
+					DO(3 downto 0) <= BusB(7 downto 4);
+					DO(7 downto 4) <= BusA(3 downto 0);
+				end if;
+			end if;
+
+			if T_Res = '1' then
+				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
+				Read_To_Reg_r(4) <= Read_To_Reg;
+				if Read_To_Acc = '1' then
+					Read_To_Reg_r(3 downto 0) <= "0111";
+					Read_To_Reg_r(4) <= '1';
+				end if;
+			end if;
+
+			if TState = 1 and I_BT = '1' then
+				F(Flag_X) <= ALU_Q(3);
+				F(Flag_Y) <= ALU_Q(1);
+				F(Flag_H) <= '0';
+				F(Flag_N) <= '0';
+			end if;
+			if I_BC = '1' or I_BT = '1' then
+				F(Flag_P) <= IncDecZ;
+			end if;
+
+			if (TState = 1 and Save_ALU_r = '0') or
+				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+				case Read_To_Reg_r is
+				when "10111" =>
+					ACC <= Save_Mux;
+				when "10110" =>
+					DO <= Save_Mux;
+				when "11000" =>
+					SP(7 downto 0) <= unsigned(Save_Mux);
+				when "11001" =>
+					SP(15 downto 8) <= unsigned(Save_Mux);
+				when "11011" =>
+					F <= Save_Mux;
+				when others =>
+				end case;
+			end if;
+
+		end if;
+
+		end if;
+
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- BC('), DE('), HL('), IX and IY
+--
+---------------------------------------------------------------------------
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if ClkEn = '1' then
+				-- Bus A / Write
+				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
+				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
+					RegAddrA_r <= XY_State(1) & "11";
+				end if;
+
+				-- Bus B
+				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
+				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
+					RegAddrB_r <= XY_State(1) & "11";
+				end if;
+
+				-- Address from register
+				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
+				-- Jump (HL), LD SP,HL
+				if (JumpXY = '1' or LDSPHL = '1') then
+					RegAddrC <= Alternate & "10";
+				end if;
+				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
+					RegAddrC <= XY_State(1) & "11";
+				end if;
+
+				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
+					IncDecZ <= F_Out(Flag_Z);
+				end if;
+				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
+					if ID16 = 0 then
+						IncDecZ <= '0';
+					else
+						IncDecZ <= '1';
+					end if;
+				end if;
+
+				RegBusA_r <= RegBusA;
+			end if;
+		end if;
+	end process;
+
+	RegAddrA <=
+			-- 16 bit increment/decrement
+			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
+			XY_State(1) & "11" when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
+			-- EX HL,DL
+			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
+			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
+			-- Bus A / Write
+			RegAddrA_r;
+
+	RegAddrB <=
+			-- EX HL,DL
+			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
+			-- Bus B
+			RegAddrB_r;
+
+	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
+			signed(RegBusA) + 1;
+
+	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	begin
+		RegWEH <= '0';
+		RegWEL <= '0';
+		if (TState = 1 and Save_ALU_r = '0') or
+			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+			case Read_To_Reg_r is
+			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
+				RegWEH <= not Read_To_Reg_r(0);
+				RegWEL <= Read_To_Reg_r(0);
+			when others =>
+			end case;
+		end if;
+
+		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
+			RegWEH <= '1';
+			RegWEL <= '1';
+		end if;
+
+		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+			case IncDec_16(1 downto 0) is
+			when "00" | "01" | "10" =>
+				RegWEH <= '1';
+				RegWEL <= '1';
+			when others =>
+			end case;
+		end if;
+	end process;
+
+	process (Save_Mux, RegBusB, RegBusA_r, ID16,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	begin
+		RegDIH <= Save_Mux;
+		RegDIL <= Save_Mux;
+
+		if ExchangeDH = '1' and TState = 3 then
+			RegDIH <= RegBusB(15 downto 8);
+			RegDIL <= RegBusB(7 downto 0);
+		end if;
+		if ExchangeDH = '1' and TState = 4 then
+			RegDIH <= RegBusA_r(15 downto 8);
+			RegDIL <= RegBusA_r(7 downto 0);
+		end if;
+
+		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+			RegDIH <= std_logic_vector(ID16(15 downto 8));
+			RegDIL <= std_logic_vector(ID16(7 downto 0));
+		end if;
+	end process;
+
+	Regs : T80_Reg
+		port map(
+			Clk => CLK_n,
+			CEN => ClkEn,
+			WEH => RegWEH,
+			WEL => RegWEL,
+			AddrA => RegAddrA,
+			AddrB => RegAddrB,
+			AddrC => RegAddrC,
+			DIH => RegDIH,
+			DIL => RegDIL,
+			DOAH => RegBusA(15 downto 8),
+			DOAL => RegBusA(7 downto 0),
+			DOBH => RegBusB(15 downto 8),
+			DOBL => RegBusB(7 downto 0),
+			DOCH => RegBusC(15 downto 8),
+			DOCL => RegBusC(7 downto 0));
+
+---------------------------------------------------------------------------
+--
+-- Buses
+--
+---------------------------------------------------------------------------
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if ClkEn = '1' then
+			case Set_BusB_To is
+			when "0111" =>
+				BusB <= ACC;
+			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+				if Set_BusB_To(0) = '1' then
+					BusB <= RegBusB(7 downto 0);
+				else
+					BusB <= RegBusB(15 downto 8);
+				end if;
+			when "0110" =>
+				BusB <= DI_Reg;
+			when "1000" =>
+				BusB <= std_logic_vector(SP(7 downto 0));
+			when "1001" =>
+				BusB <= std_logic_vector(SP(15 downto 8));
+			when "1010" =>
+				BusB <= "00000001";
+			when "1011" =>
+				BusB <= F;
+			when "1100" =>
+				BusB <= std_logic_vector(PC(7 downto 0));
+			when "1101" =>
+				BusB <= std_logic_vector(PC(15 downto 8));
+			when "1110" =>
+				BusB <= "00000000";
+			when others =>
+				BusB <= "--------";
+			end case;
+
+			case Set_BusA_To is
+			when "0111" =>
+				BusA <= ACC;
+			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+				if Set_BusA_To(0) = '1' then
+					BusA <= RegBusA(7 downto 0);
+				else
+					BusA <= RegBusA(15 downto 8);
+				end if;
+			when "0110" =>
+				BusA <= DI_Reg;
+			when "1000" =>
+				BusA <= std_logic_vector(SP(7 downto 0));
+			when "1001" =>
+				BusA <= std_logic_vector(SP(15 downto 8));
+			when "1010" =>
+				BusA <= "00000000";
+			when others =>
+				BusB <= "--------";
+			end case;
+			end if;
+		end if;
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- Generate external control signals
+--
+---------------------------------------------------------------------------
+	process (RESET_n,CLK_n)
+	begin
+		if RESET_n = '0' then
+			RFSH_n <= '1';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
+				RFSH_n <= '0';
+			else
+				RFSH_n <= '1';
+			end if;
+			end if;
+		end if;
+	end process;
+
+	MC <= std_logic_vector(MCycle);
+	TS <= std_logic_vector(TState);
+	DI_Reg <= DI;
+	HALT_n <= not Halt_FF;
+	BUSAK_n <= not BusAck;
+	IntCycle_n <= not IntCycle;
+	IntE <= IntE_FF1;
+	IORQ <= IORQ_i;
+	Stop <= I_DJNZ;
+
+-------------------------------------------------------------------------
+--
+-- Syncronise inputs
+--
+-------------------------------------------------------------------------
+	process (RESET_n, CLK_n)
+		variable OldNMI_n : std_logic;
+	begin
+		if RESET_n = '0' then
+			BusReq_s <= '0';
+			INT_s <= '0';
+			NMI_s <= '0';
+			OldNMI_n := '0';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			BusReq_s <= not BUSRQ_n;
+			INT_s <= not INT_n;
+			if NMICycle = '1' then
+				NMI_s <= '0';
+			elsif NMI_n = '0' and OldNMI_n = '1' then
+				NMI_s <= '1';
+			end if;
+			OldNMI_n := NMI_n;
+			end if;
+		end if;
+	end process;
+
+-------------------------------------------------------------------------
+--
+-- Main state machine
+--
+-------------------------------------------------------------------------
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			MCycle <= "001";
+			TState <= "000";
+			Pre_XY_F_M <= "000";
+			Halt_FF <= '0';
+			BusAck <= '0';
+			NMICycle <= '0';
+			IntCycle <= '0';
+			IntE_FF1 <= '0';
+			IntE_FF2 <= '0';
+			No_BTR <= '0';
+			Auto_Wait_t1 <= '0';
+			Auto_Wait_t2 <= '0';
+			M1_n <= '1';
+		elsif CLK_n'event and CLK_n = '1' then
+			if CEN = '1' then
+			Auto_Wait_t1 <= Auto_Wait;
+			Auto_Wait_t2 <= Auto_Wait_t1;
+			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
+					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
+					(I_BTR and (not IR(4) or F(Flag_Z)));
+			if TState = 2 then
+				if SetEI = '1' then
+					IntE_FF1 <= '1';
+					IntE_FF2 <= '1';
+				end if;
+				if I_RETN = '1' then
+					IntE_FF1 <= IntE_FF2;
+				end if;
+			end if;
+			if TState = 3 then
+				if SetDI = '1' then
+					IntE_FF1 <= '0';
+					IntE_FF2 <= '0';
+				end if;
+			end if;
+			if IntCycle = '1' or NMICycle = '1' then
+				Halt_FF <= '0';
+			end if;
+			if MCycle = "001" and TState = 2 and Wait_n = '1' then
+				M1_n <= '1';
+			end if;
+			if BusReq_s = '1' and BusAck = '1' then
+			else
+				BusAck <= '0';
+				if TState = 2 and Wait_n = '0' then
+				elsif T_Res = '1' then
+					if Halt = '1' then
+						Halt_FF <= '1';
+					end if;
+					if BusReq_s = '1' then
+						BusAck <= '1';
+					else
+						TState <= "001";
+						if NextIs_XY_Fetch = '1' then
+							MCycle <= "110";
+							Pre_XY_F_M <= MCycle;
+							if IR = "00110110" and Mode = 0 then
+								Pre_XY_F_M <= "010";
+							end if;
+						elsif (MCycle = "111") or
+							(MCycle = "110" and Mode = 1 and ISet /= "01") then
+							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
+						elsif (MCycle = MCycles) or
+							No_BTR = '1' or
+							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
+							M1_n <= '0';
+							MCycle <= "001";
+							IntCycle <= '0';
+							NMICycle <= '0';
+							if NMI_s = '1' and Prefix = "00" then
+								NMICycle <= '1';
+								IntE_FF1 <= '0';
+							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
+								IntCycle <= '1';
+								IntE_FF1 <= '0';
+								IntE_FF2 <= '0';
+							end if;
+						else
+							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
+						end if;
+					end if;
+				else
+					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
+
+						TState <= TState + 1;
+					end if;
+				end if;
+			end if;
+			if TState = 0 then
+				M1_n <= '0';
+			end if;
+			end if;
+		end if;
+	end process;
+
+	process (IntCycle, NMICycle, MCycle)
+	begin
+		Auto_Wait <= '0';
+		if IntCycle = '1' or NMICycle = '1' then
+			if MCycle = "001" then
+				Auto_Wait <= '1';
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/cpu/T80_ALU.vhd
new file mode 100644
index 00000000..95c98dab
--- /dev/null
+++ b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/cpu/T80_ALU.vhd	
@@ -0,0 +1,371 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0238 : Fixed zero flag for 16 bit SBC and ADC
+--
+--      0240 : Added GB operations
+--
+--      0242 : Cleanup
+--
+--      0247 : Cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_ALU is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+end T80_ALU;
+
+architecture rtl of T80_ALU is
+
+	procedure AddSub(A        : std_logic_vector;
+					 B        : std_logic_vector;
+					 Sub      : std_logic;
+					 Carry_In : std_logic;
+			  signal Res      : out std_logic_vector;
+			  signal Carry    : out std_logic) is
+
+		variable B_i          : unsigned(A'length - 1 downto 0);
+		variable Res_i        : unsigned(A'length + 1 downto 0);
+	begin
+		if Sub = '1' then
+			B_i := not unsigned(B);
+		else
+			B_i :=     unsigned(B);
+		end if;
+
+		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
+		Carry <= Res_i(A'length + 1);
+		Res <= std_logic_vector(Res_i(A'length downto 1));
+	end;
+
+	-- AddSub variables (temporary signals)
+	signal UseCarry                : std_logic;
+	signal Carry7_v                : std_logic;
+	signal Overflow_v              : std_logic;
+	signal HalfCarry_v             : std_logic;
+	signal Carry_v                 : std_logic;
+	signal Q_v                     : std_logic_vector(7 downto 0);
+
+	signal BitMask                 : std_logic_vector(7 downto 0);
+
+begin
+
+	with IR(5 downto 3) select BitMask <= "00000001" when "000",
+										  "00000010" when "001",
+										  "00000100" when "010",
+										  "00001000" when "011",
+										  "00010000" when "100",
+										  "00100000" when "101",
+										  "01000000" when "110",
+										  "10000000" when others;
+
+	UseCarry <= not ALU_Op(2) and ALU_Op(0);
+	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
+	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
+	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
+
+	-- bug fix - parity flag is just parity for 8080, also overflow for Z80
+	process (Carry_v, Carry7_v, Q_v)
+	begin
+		if(Mode=2) then
+			OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
+					   Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7));  else
+			OverFlow_v <= Carry_v xor Carry7_v;
+		end if;
+	end process;
+
+	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
+		variable Q_t : std_logic_vector(7 downto 0);
+		variable DAA_Q : unsigned(8 downto 0);
+	begin
+		Q_t := "--------";
+		F_Out <= F_In;
+		DAA_Q := "---------";
+		case ALU_Op is
+		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_C) <= '0';
+			case ALU_OP(2 downto 0) is
+			when "000" | "001" => -- ADD, ADC
+				Q_t := Q_v;
+				F_Out(Flag_C) <= Carry_v;
+				F_Out(Flag_H) <= HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "010" | "011" | "111" => -- SUB, SBC, CP
+				Q_t := Q_v;
+				F_Out(Flag_N) <= '1';
+				F_Out(Flag_C) <= not Carry_v;
+				F_Out(Flag_H) <= not HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "100" => -- AND
+				Q_t(7 downto 0) := BusA and BusB;
+				F_Out(Flag_H) <= '1';
+			when "101" => -- XOR
+				Q_t(7 downto 0) := BusA xor BusB;
+				F_Out(Flag_H) <= '0';
+			when others => -- OR "110"
+				Q_t(7 downto 0) := BusA or BusB;
+				F_Out(Flag_H) <= '0';
+			end case;
+			if ALU_Op(2 downto 0) = "111" then -- CP
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			else
+				F_Out(Flag_X) <= Q_t(3);
+				F_Out(Flag_Y) <= Q_t(5);
+			end if;
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				if Z16 = '1' then
+					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
+				end if;
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			case ALU_Op(2 downto 0) is
+			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
+			when others =>
+				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			end case;
+			if Arith16 = '1' then
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+				F_Out(Flag_P) <= F_In(Flag_P);
+			end if;
+		when "1100" =>
+			-- DAA
+			F_Out(Flag_H) <= F_In(Flag_H);
+			F_Out(Flag_C) <= F_In(Flag_C);
+			DAA_Q(7 downto 0) := unsigned(BusA);
+			DAA_Q(8) := '0';
+			if F_In(Flag_N) = '0' then
+				-- After addition
+				-- Alow > 9 or H = 1
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if (DAA_Q(3 downto 0) > 9) then
+						F_Out(Flag_H) <= '1';
+					else
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q := DAA_Q + 6;
+				end if;
+				-- new Ahigh > 9 or C = 1
+				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q + 96; -- 0x60
+				end if;
+			else
+				-- After subtraction
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if DAA_Q(3 downto 0) > 5 then
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
+				end if;
+				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q - 352; -- 0x160
+				end if;
+			end if;
+			F_Out(Flag_X) <= DAA_Q(3);
+			F_Out(Flag_Y) <= DAA_Q(5);
+			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
+			Q_t := std_logic_vector(DAA_Q(7 downto 0));
+			if DAA_Q(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= DAA_Q(7);
+			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
+				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
+		when "1101" | "1110" =>
+			-- RLD, RRD
+			Q_t(7 downto 4) := BusA(7 downto 4);
+			if ALU_Op(0) = '1' then
+				Q_t(3 downto 0) := BusB(7 downto 4);
+			else
+				Q_t(3 downto 0) := BusB(3 downto 0);
+			end if;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+		when "1001" =>
+			-- BIT
+			Q_t(7 downto 0) := BusB and BitMask;
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				F_Out(Flag_P) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+				F_Out(Flag_P) <= '0';
+			end if;
+			F_Out(Flag_H) <= '1';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= '0';
+			F_Out(Flag_Y) <= '0';
+			if IR(2 downto 0) /= "110" then
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			end if;
+		when "1010" =>
+			-- SET
+			Q_t(7 downto 0) := BusB or BitMask;
+		when "1011" =>
+			-- RES
+			Q_t(7 downto 0) := BusB and not BitMask;
+		when "1000" =>
+			-- ROT
+			case IR(5 downto 3) is
+			when "000" => -- RLC
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := BusA(7);
+				F_Out(Flag_C) <= BusA(7);
+			when "010" => -- RL
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(7);
+			when "001" => -- RRC
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(0);
+				F_Out(Flag_C) <= BusA(0);
+			when "011" => -- RR
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(0);
+			when "100" => -- SLA
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := '0';
+				F_Out(Flag_C) <= BusA(7);
+			when "110" => -- SLL (Undocumented) / SWAP
+				if Mode = 3 then
+					Q_t(7 downto 4) := BusA(3 downto 0);
+					Q_t(3 downto 0) := BusA(7 downto 4);
+					F_Out(Flag_C) <= '0';
+				else
+					Q_t(7 downto 1) := BusA(6 downto 0);
+					Q_t(0) := '1';
+					F_Out(Flag_C) <= BusA(7);
+				end if;
+			when "101" => -- SRA
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(7);
+				F_Out(Flag_C) <= BusA(0);
+			when others => -- SRL
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := '0';
+				F_Out(Flag_C) <= BusA(0);
+			end case;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			if ISet = "00" then
+				F_Out(Flag_P) <= F_In(Flag_P);
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+			end if;
+		when others =>
+			null;
+		end case;
+		Q <= Q_t;
+	end process;
+end;
diff --git a/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/cpu/T80_MCode.vhd
new file mode 100644
index 00000000..43cea1b5
--- /dev/null
+++ b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/cpu/T80_MCode.vhd	
@@ -0,0 +1,1944 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--
+--      0211 : Fixed IM 1
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0235 : Added IM 2 fix by Mike Johnson
+--
+--      0238 : Added NoRead signal
+--
+--      0238b: Fixed instruction timing for POP and DJNZ
+--
+--      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
+
+--      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
+--
+--      0242 : Fixed I/O instruction timing, cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80_MCode is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR                              : in std_logic_vector(7 downto 0);
+		ISet                    : in std_logic_vector(1 downto 0);
+		MCycle                  : in std_logic_vector(2 downto 0);
+		F                               : in std_logic_vector(7 downto 0);
+		NMICycle                : in std_logic;
+		IntCycle                : in std_logic;
+		MCycles                 : out std_logic_vector(2 downto 0);
+		TStates                 : out std_logic_vector(2 downto 0);
+		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC                  : out std_logic;
+		Inc_WZ                  : out std_logic;
+		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg             : out std_logic;
+		Read_To_Acc             : out std_logic;
+		Set_BusA_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU                : out std_logic;
+		PreserveC               : out std_logic;
+		Arith16                 : out std_logic;
+		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ                    : out std_logic;
+		Jump                    : out std_logic;
+		JumpE                   : out std_logic;
+		JumpXY                  : out std_logic;
+		Call                    : out std_logic;
+		RstP                    : out std_logic;
+		LDZ                             : out std_logic;
+		LDW                             : out std_logic;
+		LDSPHL                  : out std_logic;
+		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH              : out std_logic;
+		ExchangeRp              : out std_logic;
+		ExchangeAF              : out std_logic;
+		ExchangeRS              : out std_logic;
+		I_DJNZ                  : out std_logic;
+		I_CPL                   : out std_logic;
+		I_CCF                   : out std_logic;
+		I_SCF                   : out std_logic;
+		I_RETN                  : out std_logic;
+		I_BT                    : out std_logic;
+		I_BC                    : out std_logic;
+		I_BTR                   : out std_logic;
+		I_RLD                   : out std_logic;
+		I_RRD                   : out std_logic;
+		I_INRC                  : out std_logic;
+		SetDI                   : out std_logic;
+		SetEI                   : out std_logic;
+		IMode                   : out std_logic_vector(1 downto 0);
+		Halt                    : out std_logic;
+		NoRead                  : out std_logic;
+		Write                   : out std_logic
+	);
+end T80_MCode;
+
+architecture rtl of T80_MCode is
+
+	constant aNone      : std_logic_vector(2 downto 0) := "111";
+	constant aBC        : std_logic_vector(2 downto 0) := "000";
+	constant aDE        : std_logic_vector(2 downto 0) := "001";
+	constant aXY        : std_logic_vector(2 downto 0) := "010";
+	constant aIOA       : std_logic_vector(2 downto 0) := "100";
+	constant aSP        : std_logic_vector(2 downto 0) := "101";
+	constant aZI        : std_logic_vector(2 downto 0) := "110";
+
+	function is_cc_true(
+		F : std_logic_vector(7 downto 0);
+		cc : bit_vector(2 downto 0)
+		) return boolean is
+	begin
+		if Mode = 3 then
+			case cc is
+			when "000" => return F(7) = '0'; -- NZ
+			when "001" => return F(7) = '1'; -- Z
+			when "010" => return F(4) = '0'; -- NC
+			when "011" => return F(4) = '1'; -- C
+			when "100" => return false;
+			when "101" => return false;
+			when "110" => return false;
+			when "111" => return false;
+			end case;
+		else
+			case cc is
+			when "000" => return F(6) = '0'; -- NZ
+			when "001" => return F(6) = '1'; -- Z
+			when "010" => return F(0) = '0'; -- NC
+			when "011" => return F(0) = '1'; -- C
+			when "100" => return F(2) = '0'; -- PO
+			when "101" => return F(2) = '1'; -- PE
+			when "110" => return F(7) = '0'; -- P
+			when "111" => return F(7) = '1'; -- M
+			end case;
+		end if;
+	end;
+
+begin
+
+	process (IR, ISet, MCycle, F, NMICycle, IntCycle)
+		variable DDD : std_logic_vector(2 downto 0);
+		variable SSS : std_logic_vector(2 downto 0);
+		variable DPair : std_logic_vector(1 downto 0);
+		variable IRB : bit_vector(7 downto 0);
+	begin
+		DDD := IR(5 downto 3);
+		SSS := IR(2 downto 0);
+		DPair := IR(5 downto 4);
+		IRB := to_bitvector(IR);
+
+		MCycles <= "001";
+		if MCycle = "001" then
+			TStates <= "100";
+		else
+			TStates <= "011";
+		end if;
+		Prefix <= "00";
+		Inc_PC <= '0';
+		Inc_WZ <= '0';
+		IncDec_16 <= "0000";
+		Read_To_Acc <= '0';
+		Read_To_Reg <= '0';
+		Set_BusB_To <= "0000";
+		Set_BusA_To <= "0000";
+		ALU_Op <= "0" & IR(5 downto 3);
+		Save_ALU <= '0';
+		PreserveC <= '0';
+		Arith16 <= '0';
+		IORQ <= '0';
+		Set_Addr_To <= aNone;
+		Jump <= '0';
+		JumpE <= '0';
+		JumpXY <= '0';
+		Call <= '0';
+		RstP <= '0';
+		LDZ <= '0';
+		LDW <= '0';
+		LDSPHL <= '0';
+		Special_LD <= "000";
+		ExchangeDH <= '0';
+		ExchangeRp <= '0';
+		ExchangeAF <= '0';
+		ExchangeRS <= '0';
+		I_DJNZ <= '0';
+		I_CPL <= '0';
+		I_CCF <= '0';
+		I_SCF <= '0';
+		I_RETN <= '0';
+		I_BT <= '0';
+		I_BC <= '0';
+		I_BTR <= '0';
+		I_RLD <= '0';
+		I_RRD <= '0';
+		I_INRC <= '0';
+		SetDI <= '0';
+		SetEI <= '0';
+		IMode <= "11";
+		Halt <= '0';
+		NoRead <= '0';
+		Write <= '0';
+
+		case ISet is
+		when "00" =>
+
+------------------------------------------------------------------------------
+--
+--      Unprefixed instructions
+--
+------------------------------------------------------------------------------
+
+		case IRB is
+-- 8 BIT LOAD GROUP
+		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+			-- LD r,r'
+			Set_BusB_To(2 downto 0) <= SSS;
+			ExchangeRp <= '1';
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
+			-- LD r,n
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Set_BusA_To(2 downto 0) <= DDD;
+				Read_To_Reg <= '1';
+			when others => null;
+			end case;
+		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
+			-- LD r,(HL)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				Set_BusA_To(2 downto 0) <= DDD;
+				Read_To_Reg <= '1';
+			when others => null;
+			end case;
+		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
+			-- LD (HL),r
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00110110" =>
+			-- LD (HL),n
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Set_Addr_To <= aXY;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00001010" =>
+			-- LD A,(BC)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aBC;
+			when 2 =>
+				Read_To_Acc <= '1';
+			when others => null;
+			end case;
+		when "00011010" =>
+			-- LD A,(DE)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aDE;
+			when 2 =>
+				Read_To_Acc <= '1';
+			when others => null;
+			end case;
+		when "00111010" =>
+			if Mode = 3 then
+				-- LDD A,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					Read_To_Acc <= '1';
+					IncDec_16 <= "1110";
+				when others => null;
+				end case;
+			else
+				-- LD A,(nn)
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+				when 4 =>
+					Read_To_Acc <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "00000010" =>
+			-- LD (BC),A
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aBC;
+				Set_BusB_To <= "0111";
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00010010" =>
+			-- LD (DE),A
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aDE;
+				Set_BusB_To <= "0111";
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00110010" =>
+			if Mode = 3 then
+				-- LDD (HL),A
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "0111";
+				when 2 =>
+					Write <= '1';
+					IncDec_16 <= "1110";
+				when others => null;
+				end case;
+			else
+				-- LD (nn),A
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					Set_BusB_To <= "0111";
+				when 4 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+
+-- 16 BIT LOAD GROUP
+		when "00000001"|"00010001"|"00100001"|"00110001" =>
+			-- LD dd,nn
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1000";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '1';
+				end if;
+			when 3 =>
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1001";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '0';
+				end if;
+			when others => null;
+			end case;
+		when "00101010" =>
+			if Mode = 3 then
+				-- LDI A,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					Read_To_Acc <= '1';
+					IncDec_16 <= "0110";
+				when others => null;
+				end case;
+			else
+				-- LD HL,(nn)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+				when 4 =>
+					Set_BusA_To(2 downto 0) <= "101"; -- L
+					Read_To_Reg <= '1';
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+				when 5 =>
+					Set_BusA_To(2 downto 0) <= "100"; -- H
+					Read_To_Reg <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "00100010" =>
+			if Mode = 3 then
+				-- LDI (HL),A
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "0111";
+				when 2 =>
+					Write <= '1';
+					IncDec_16 <= "0110";
+				when others => null;
+				end case;
+			else
+				-- LD (nn),HL
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					Set_BusB_To <= "0101"; -- L
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					Set_BusB_To <= "0100"; -- H
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11111001" =>
+			-- LD SP,HL
+			TStates <= "110";
+			LDSPHL <= '1';
+		when "11000101"|"11010101"|"11100101"|"11110101" =>
+			-- PUSH qq
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				IncDec_16 <= "1111";
+				Set_Addr_TO <= aSP;
+				if DPAIR = "11" then
+					Set_BusB_To <= "0111";
+				else
+					Set_BusB_To(2 downto 1) <= DPAIR;
+					Set_BusB_To(0) <= '0';
+					Set_BusB_To(3) <= '0';
+				end if;
+			when 2 =>
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				if DPAIR = "11" then
+					Set_BusB_To <= "1011";
+				else
+					Set_BusB_To(2 downto 1) <= DPAIR;
+					Set_BusB_To(0) <= '1';
+					Set_BusB_To(3) <= '0';
+				end if;
+				Write <= '1';
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "11000001"|"11010001"|"11100001"|"11110001" =>
+			-- POP qq
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aSP;
+			when 2 =>
+				IncDec_16 <= "0111";
+				Set_Addr_To <= aSP;
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1011";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '1';
+				end if;
+			when 3 =>
+				IncDec_16 <= "0111";
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "0111";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '0';
+				end if;
+			when others => null;
+			end case;
+
+-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
+		when "11101011" =>
+			if Mode /= 3 then
+				-- EX DE,HL
+				ExchangeDH <= '1';
+			end if;
+		when "00001000" =>
+			if Mode = 3 then
+				-- LD (nn),SP
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					Set_BusB_To <= "1000";
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					Set_BusB_To <= "1001";
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			elsif Mode < 2 then
+				-- EX AF,AF'
+				ExchangeAF <= '1';
+			end if;
+		when "11011001" =>
+			if Mode = 3 then
+				-- RETI
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_TO <= aSP;
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+					I_RETN <= '1';
+					SetEI <= '1';
+				when others => null;
+				end case;
+			elsif Mode < 2 then
+				-- EXX
+				ExchangeRS <= '1';
+			end if;
+		when "11100011" =>
+			if Mode /= 3 then
+				-- EX (SP),HL
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aSP;
+				when 2 =>
+					Read_To_Reg <= '1';
+					Set_BusA_To <= "0101";
+					Set_BusB_To <= "0101";
+					Set_Addr_To <= aSP;
+				when 3 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					TStates <= "100";
+					Write <= '1';
+				when 4 =>
+					Read_To_Reg <= '1';
+					Set_BusA_To <= "0100";
+					Set_BusB_To <= "0100";
+					Set_Addr_To <= aSP;
+				when 5 =>
+					IncDec_16 <= "1111";
+					TStates <= "101";
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+
+-- 8 BIT ARITHMETIC AND LOGICAL GROUP
+		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+			-- ADD A,r
+			-- ADC A,r
+			-- SUB A,r
+			-- SBC A,r
+			-- AND A,r
+			-- OR A,r
+			-- XOR A,r
+			-- CP A,r
+			Set_BusB_To(2 downto 0) <= SSS;
+			Set_BusA_To(2 downto 0) <= "111";
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+			-- ADD A,(HL)
+			-- ADC A,(HL)
+			-- SUB A,(HL)
+			-- SBC A,(HL)
+			-- AND A,(HL)
+			-- OR A,(HL)
+			-- XOR A,(HL)
+			-- CP A,(HL)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusA_To(2 downto 0) <= "111";
+			when others => null;
+			end case;
+		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+			-- ADD A,n
+			-- ADC A,n
+			-- SUB A,n
+			-- SBC A,n
+			-- AND A,n
+			-- OR A,n
+			-- XOR A,n
+			-- CP A,n
+			MCycles <= "010";
+			if MCycle = "010" then
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusA_To(2 downto 0) <= "111";
+			end if;
+		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
+			-- INC r
+			Set_BusB_To <= "1010";
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+			PreserveC <= '1';
+			ALU_Op <= "0000";
+		when "00110100" =>
+			-- INC (HL)
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				TStates <= "100";
+				Set_Addr_To <= aXY;
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				PreserveC <= '1';
+				ALU_Op <= "0000";
+				Set_BusB_To <= "1010";
+				Set_BusA_To(2 downto 0) <= DDD;
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
+			-- DEC r
+			Set_BusB_To <= "1010";
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+			PreserveC <= '1';
+			ALU_Op <= "0010";
+		when "00110101" =>
+			-- DEC (HL)
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				TStates <= "100";
+				Set_Addr_To <= aXY;
+				ALU_Op <= "0010";
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				PreserveC <= '1';
+				Set_BusB_To <= "1010";
+				Set_BusA_To(2 downto 0) <= DDD;
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+
+-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
+		when "00100111" =>
+			-- DAA
+			Set_BusA_To(2 downto 0) <= "111";
+			Read_To_Reg <= '1';
+			ALU_Op <= "1100";
+			Save_ALU <= '1';
+		when "00101111" =>
+			-- CPL
+			I_CPL <= '1';
+		when "00111111" =>
+			-- CCF
+			I_CCF <= '1';
+		when "00110111" =>
+			-- SCF
+			I_SCF <= '1';
+		when "00000000" =>
+			if NMICycle = '1' then
+				-- NMI
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1101";
+				when 2 =>
+					TStates <= "100";
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 3 =>
+					TStates <= "100";
+					Write <= '1';
+				when others => null;
+				end case;
+			elsif IntCycle = '1' then
+				-- INT (IM 2)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					LDZ <= '1';
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1101";
+				when 2 =>
+					TStates <= "100";
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 3 =>
+					TStates <= "100";
+					Write <= '1';
+				when 4 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 5 =>
+					Jump <= '1';
+				when others => null;
+				end case;
+			else
+				-- NOP
+			end if;
+		when "01110110" =>
+			-- HALT
+			Halt <= '1';
+		when "11110011" =>
+			-- DI
+			SetDI <= '1';
+		when "11111011" =>
+			-- EI
+			SetEI <= '1';
+
+-- 16 BIT ARITHMETIC GROUP
+		when "00001001"|"00011001"|"00101001"|"00111001" =>
+			-- ADD HL,ss
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				NoRead <= '1';
+				ALU_Op <= "0000";
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusA_To(2 downto 0) <= "101";
+				case to_integer(unsigned(IR(5 downto 4))) is
+				when 0|1|2 =>
+					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					Set_BusB_To(0) <= '1';
+				when others =>
+					Set_BusB_To <= "1000";
+				end case;
+				TStates <= "100";
+				Arith16 <= '1';
+			when 3 =>
+				NoRead <= '1';
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				ALU_Op <= "0001";
+				Set_BusA_To(2 downto 0) <= "100";
+				case to_integer(unsigned(IR(5 downto 4))) is
+				when 0|1|2 =>
+					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+				when others =>
+					Set_BusB_To <= "1001";
+				end case;
+				Arith16 <= '1';
+			when others =>
+			end case;
+		when "00000011"|"00010011"|"00100011"|"00110011" =>
+			-- INC ss
+			TStates <= "110";
+			IncDec_16(3 downto 2) <= "01";
+			IncDec_16(1 downto 0) <= DPair;
+		when "00001011"|"00011011"|"00101011"|"00111011" =>
+			-- DEC ss
+			TStates <= "110";
+			IncDec_16(3 downto 2) <= "11";
+			IncDec_16(1 downto 0) <= DPair;
+
+-- ROTATE AND SHIFT GROUP
+		when "00000111"
+			-- RLCA
+			|"00010111"
+			-- RLA
+			|"00001111"
+			-- RRCA
+			|"00011111" =>
+			-- RRA
+			Set_BusA_To(2 downto 0) <= "111";
+			ALU_Op <= "1000";
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+
+-- JUMP GROUP
+		when "11000011" =>
+			-- JP nn
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				LDZ <= '1';
+			when 3 =>
+				Inc_PC <= '1';
+				Jump <= '1';
+			when others => null;
+			end case;
+		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
+			if IR(5) = '1' and Mode = 3 then
+				case IRB(4 downto 3) is
+				when "00" =>
+					-- LD ($FF00+C),A
+					MCycles <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Set_Addr_To <= aBC;
+						Set_BusB_To     <= "0111";
+					when 2 =>
+						Write <= '1';
+						IORQ <= '1';
+					when others =>
+					end case;
+				when "01" =>
+					-- LD (nn),A
+					MCycles <= "100";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+						Set_BusB_To <= "0111";
+					when 4 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				when "10" =>
+					-- LD A,($FF00+C)
+					MCycles <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Set_Addr_To <= aBC;
+					when 2 =>
+						Read_To_Acc <= '1';
+						IORQ <= '1';
+					when others =>
+					end case;
+				when "11" =>
+					-- LD A,(nn)
+					MCycles <= "100";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+					when 4 =>
+						Read_To_Acc <= '1';
+					when others => null;
+					end case;
+				end case;
+			else
+				-- JP cc,nn
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Inc_PC <= '1';
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						Jump <= '1';
+					end if;
+				when others => null;
+				end case;
+			end if;
+		when "00011000" =>
+			if Mode /= 2 then
+				-- JR e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00111000" =>
+			if Mode /= 2 then
+				-- JR C,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_C) = '0' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00110000" =>
+			if Mode /= 2 then
+				-- JR NC,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_C) = '1' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00101000" =>
+			if Mode /= 2 then
+				-- JR Z,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_Z) = '0' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00100000" =>
+			if Mode /= 2 then
+				-- JR NZ,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_Z) = '1' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "11101001" =>
+			-- JP (HL)
+			JumpXY <= '1';
+		when "00010000" =>
+			if Mode = 3 then
+				I_DJNZ <= '1';
+			elsif Mode < 2 then
+				-- DJNZ,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					I_DJNZ <= '1';
+					Set_BusB_To <= "1010";
+					Set_BusA_To(2 downto 0) <= "000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					I_DJNZ <= '1';
+					Inc_PC <= '1';
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+
+-- CALL AND RETURN GROUP
+		when "11001101" =>
+			-- CALL nn
+			MCycles <= "101";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				LDZ <= '1';
+			when 3 =>
+				IncDec_16 <= "1111";
+				Inc_PC <= '1';
+				TStates <= "100";
+				Set_Addr_To <= aSP;
+				LDW <= '1';
+				Set_BusB_To <= "1101";
+			when 4 =>
+				Write <= '1';
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1100";
+			when 5 =>
+				Write <= '1';
+				Call <= '1';
+			when others => null;
+			end case;
+		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
+			if IR(5) = '0' or Mode /= 3 then
+				-- CALL cc,nn
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Inc_PC <= '1';
+					LDW <= '1';
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						IncDec_16 <= "1111";
+						Set_Addr_TO <= aSP;
+						TStates <= "100";
+						Set_BusB_To <= "1101";
+					else
+						MCycles <= "011";
+					end if;
+				when 4 =>
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 5 =>
+					Write <= '1';
+					Call <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11001001" =>
+			-- RET
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				Set_Addr_TO <= aSP;
+			when 2 =>
+				IncDec_16 <= "0111";
+				Set_Addr_To <= aSP;
+				LDZ <= '1';
+			when 3 =>
+				Jump <= '1';
+				IncDec_16 <= "0111";
+			when others => null;
+			end case;
+		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
+			if IR(5) = '1' and Mode = 3 then
+				case IRB(4 downto 3) is
+				when "00" =>
+					-- LD ($FF00+nn),A
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						Set_Addr_To <= aIOA;
+						Set_BusB_To     <= "0111";
+					when 3 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				when "01" =>
+					-- ADD SP,n
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						ALU_Op <= "0000";
+						Inc_PC <= '1';
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						Set_BusA_To <= "1000";
+						Set_BusB_To <= "0110";
+					when 3 =>
+						NoRead <= '1';
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						ALU_Op <= "0001";
+						Set_BusA_To <= "1001";
+						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
+					when others =>
+					end case;
+				when "10" =>
+					-- LD A,($FF00+nn)
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						Set_Addr_To <= aIOA;
+					when 3 =>
+						Read_To_Acc <= '1';
+					when others => null;
+					end case;
+				when "11" =>
+					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
+					MCycles <= "101";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+						LDW <= '1';
+					when 4 =>
+						Set_BusA_To(2 downto 0) <= "101"; -- L
+						Read_To_Reg <= '1';
+						Inc_WZ <= '1';
+						Set_Addr_To <= aZI;
+					when 5 =>
+						Set_BusA_To(2 downto 0) <= "100"; -- H
+						Read_To_Reg <= '1';
+					when others => null;
+					end case;
+				end case;
+			else
+				-- RET cc
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						Set_Addr_TO <= aSP;
+					else
+						MCycles <= "001";
+					end if;
+					TStates <= "101";
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+				when others => null;
+				end case;
+			end if;
+		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
+			-- RST p
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1101";
+			when 2 =>
+				Write <= '1';
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1100";
+			when 3 =>
+				Write <= '1';
+				RstP <= '1';
+			when others => null;
+			end case;
+
+-- INPUT AND OUTPUT GROUP
+		when "11011011" =>
+			if Mode /= 3 then
+				-- IN A,(n)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					Set_Addr_To <= aIOA;
+				when 3 =>
+					Read_To_Acc <= '1';
+					IORQ <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11010011" =>
+			if Mode /= 3 then
+				-- OUT (n),A
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					Set_Addr_To <= aIOA;
+					Set_BusB_To <= "0111";
+				when 3 =>
+					Write <= '1';
+					IORQ <= '1';
+				when others => null;
+				end case;
+			end if;
+
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+-- MULTIBYTE INSTRUCTIONS
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+
+		when "11001011" =>
+			if Mode /= 2 then
+				Prefix <= "01";
+			end if;
+
+		when "11101101" =>
+			if Mode < 2 then
+				Prefix <= "10";
+			end if;
+
+		when "11011101"|"11111101" =>
+			if Mode < 2 then
+				Prefix <= "11";
+			end if;
+
+		end case;
+
+		when "01" =>
+
+------------------------------------------------------------------------------
+--
+--      CB prefixed instructions
+--
+------------------------------------------------------------------------------
+
+			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
+			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+
+			case IRB is
+			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
+				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
+				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
+				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
+				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
+				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
+				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
+				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
+				-- RLC r
+				-- RL r
+				-- RRC r
+				-- RR r
+				-- SLA r
+				-- SRA r
+				-- SRL r
+				-- SLL r (Undocumented) / SWAP r
+				if MCycle = "001" then
+				  ALU_Op <= "1000";
+				  Read_To_Reg <= '1';
+				  Save_ALU <= '1';
+				end if;
+			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
+				-- RLC (HL)
+				-- RL (HL)
+				-- RRC (HL)
+				-- RR (HL)
+				-- SRA (HL)
+				-- SRL (HL)
+				-- SLA (HL)
+				-- SLL (HL) (Undocumented) / SWAP (HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others =>
+				end case;
+			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
+				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+				-- BIT b,r
+				if MCycle = "001" then
+				  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+				  ALU_Op <= "1001";
+				end if;
+			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
+				-- BIT b,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7=>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1001";
+					TStates <= "100";
+				when others => null;
+				end case;
+			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
+				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
+				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
+				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
+				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
+				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
+				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
+				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
+				-- SET b,r
+				if MCycle = "001" then
+				  ALU_Op <= "1010";
+				  Read_To_Reg <= '1';
+				  Save_ALU <= '1';
+				end if;
+			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+				-- SET b,(HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7=>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1010";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+				-- RES b,r
+				if MCycle = "001" then
+					ALU_Op <= "1011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+				end if;
+			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+				-- RES b,(HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end case;
+
+		when others =>
+
+------------------------------------------------------------------------------
+--
+--      ED prefixed instructions
+--
+------------------------------------------------------------------------------
+
+			case IRB is
+			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
+				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
+				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
+				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
+				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
+				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
+				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
+				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
+
+
+				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
+				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
+				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
+				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
+				|                                            "10100100"|"10100101"|"10100110"|"10100111"
+				|                                            "10101100"|"10101101"|"10101110"|"10101111"
+				|                                            "10110100"|"10110101"|"10110110"|"10110111"
+				|                                            "10111100"|"10111101"|"10111110"|"10111111"
+				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
+				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
+				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
+				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
+				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
+				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
+				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
+				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
+				null; -- NOP, undocumented
+			when "01111110"|"01111111" =>
+				-- NOP, undocumented
+				null;
+-- 8 BIT LOAD GROUP
+			when "01010111" =>
+				-- LD A,I
+				Special_LD <= "100";
+				TStates <= "101";
+			when "01011111" =>
+				-- LD A,R
+				Special_LD <= "101";
+				TStates <= "101";
+			when "01000111" =>
+				-- LD I,A
+				Special_LD <= "110";
+				TStates <= "101";
+			when "01001111" =>
+				-- LD R,A
+				Special_LD <= "111";
+				TStates <= "101";
+-- 16 BIT LOAD GROUP
+			when "01001011"|"01011011"|"01101011"|"01111011" =>
+				-- LD dd,(nn)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+				when 4 =>
+					Read_To_Reg <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusA_To <= "1000";
+					else
+						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusA_To(0) <= '1';
+					end if;
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+				when 5 =>
+					Read_To_Reg <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusA_To <= "1001";
+					else
+						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusA_To(0) <= '0';
+					end if;
+				when others => null;
+				end case;
+			when "01000011"|"01010011"|"01100011"|"01110011" =>
+				-- LD (nn),dd
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusB_To <= "1000";
+					else
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '1';
+						Set_BusB_To(3) <= '0';
+					end if;
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusB_To <= "1001";
+					else
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '0';
+						Set_BusB_To(3) <= '0';
+					end if;
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			when "10100000" | "10101000" | "10110000" | "10111000" =>
+				-- LDI, LDD, LDIR, LDDR
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					IncDec_16 <= "1100"; -- BC
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "0000";
+					Set_Addr_To <= aDE;
+					if IR(3) = '0' then
+						IncDec_16 <= "0110"; -- IX
+					else
+						IncDec_16 <= "1110";
+					end if;
+				when 3 =>
+					I_BT <= '1';
+					TStates <= "101";
+					Write <= '1';
+					if IR(3) = '0' then
+						IncDec_16 <= "0101"; -- DE
+					else
+						IncDec_16 <= "1101";
+					end if;
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "10100001" | "10101001" | "10110001" | "10111001" =>
+				-- CPI, CPD, CPIR, CPDR
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					IncDec_16 <= "1100"; -- BC
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "0111";
+					Save_ALU <= '1';
+					PreserveC <= '1';
+					if IR(3) = '0' then
+						IncDec_16 <= "0110";
+					else
+						IncDec_16 <= "1110";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					I_BC <= '1';
+					TStates <= "101";
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
+				-- NEG
+				Alu_OP <= "0010";
+				Set_BusB_To <= "0111";
+				Set_BusA_To <= "1010";
+				Read_To_Acc <= '1';
+				Save_ALU <= '1';
+			when "01000110"|"01001110"|"01100110"|"01101110" =>
+				-- IM 0
+				IMode <= "00";
+			when "01010110"|"01110110" =>
+				-- IM 1
+				IMode <= "01";
+			when "01011110"|"01110111" =>
+				-- IM 2
+				IMode <= "10";
+-- 16 bit arithmetic
+			when "01001010"|"01011010"|"01101010"|"01111010" =>
+				-- ADC HL,ss
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					ALU_Op <= "0001";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "101";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					Set_BusB_To(0) <= '1';
+						when others =>
+						Set_BusB_To <= "1000";
+					end case;
+					TStates <= "100";
+				when 3 =>
+					NoRead <= '1';
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0001";
+					Set_BusA_To(2 downto 0) <= "100";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '0';
+					when others =>
+						Set_BusB_To <= "1001";
+					end case;
+				when others =>
+				end case;
+			when "01000010"|"01010010"|"01100010"|"01110010" =>
+				-- SBC HL,ss
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					ALU_Op <= "0011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "101";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '1';
+					when others =>
+						Set_BusB_To <= "1000";
+					end case;
+					TStates <= "100";
+				when 3 =>
+					NoRead <= '1';
+					ALU_Op <= "0011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "100";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					when others =>
+							Set_BusB_To <= "1001";
+					end case;
+				when others =>
+				end case;
+			when "01101111" =>
+				-- RLD
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					Set_Addr_To <= aXY;
+				when 3 =>
+					Read_To_Reg <= '1';
+					Set_BusB_To(2 downto 0) <= "110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "1101";
+					TStates <= "100";
+					Set_Addr_To <= aXY;
+					Save_ALU <= '1';
+				when 4 =>
+					I_RLD <= '1';
+					Write <= '1';
+				when others =>
+				end case;
+			when "01100111" =>
+				-- RRD
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Set_Addr_To <= aXY;
+				when 3 =>
+					Read_To_Reg <= '1';
+					Set_BusB_To(2 downto 0) <= "110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "1110";
+					TStates <= "100";
+					Set_Addr_To <= aXY;
+					Save_ALU <= '1';
+				when 4 =>
+					I_RRD <= '1';
+					Write <= '1';
+				when others =>
+				end case;
+			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
+				-- RETI, RETN
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_TO <= aSP;
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+					I_RETN <= '1';
+				when others => null;
+				end case;
+			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
+				-- IN r,(C)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+				when 2 =>
+					IORQ <= '1';
+					if IR(5 downto 3) /= "110" then
+						Read_To_Reg <= '1';
+						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
+					end if;
+					I_INRC <= '1';
+				when others =>
+				end case;
+			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
+				-- OUT (C),r
+				-- OUT (C),0
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
+					if IR(5 downto 3) = "110" then
+						Set_BusB_To(3) <= '1';
+					end if;
+				when 2 =>
+					Write <= '1';
+					IORQ <= '1';
+				when others =>
+				end case;
+			when "10100010" | "10101010" | "10110010" | "10111010" =>
+				-- INI, IND, INIR, INDR
+				-- note B is decremented AFTER being put on the bus
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+					Set_BusB_To <= "1010";
+					Set_BusA_To <= "0000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					IORQ <= '1';
+					Set_BusB_To <= "0110";
+					Set_Addr_To <= aXY;
+				when 3 =>
+					if IR(3) = '0' then
+						--IncDec_16 <= "0010";
+						IncDec_16 <= "0110";
+					else
+						--IncDec_16 <= "1010";
+						IncDec_16 <= "1110";
+					end if;
+					TStates <= "100";
+					Write <= '1';
+					I_BTR <= '1';
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "10100011" | "10101011" | "10110011" | "10111011" =>
+				-- OUTI, OUTD, OTIR, OTDR
+				-- note B is decremented BEFORE being put on the bus.
+				-- mikej fix for hl inc
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "1010";
+					Set_BusA_To <= "0000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_Addr_To <= aBC;
+				when 3 =>
+					if IR(3) = '0' then
+						IncDec_16 <= "0110"; -- mikej
+					else
+						IncDec_16 <= "1110"; -- mikej
+					end if;
+					IORQ <= '1';
+					Write <= '1';
+					I_BTR <= '1';
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end case;
+
+		end case;
+
+		if Mode = 1 then
+			if MCycle = "001" then
+--              TStates <= "100";
+			else
+				TStates <= "011";
+			end if;
+		end if;
+
+		if Mode = 3 then
+			if MCycle = "001" then
+--              TStates <= "100";
+			else
+				TStates <= "100";
+			end if;
+		end if;
+
+		if Mode < 2 then
+			if MCycle = "110" then
+				Inc_PC <= '1';
+				if Mode = 1 then
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+					Set_BusB_To(2 downto 0) <= SSS;
+					Set_BusB_To(3) <= '0';
+				end if;
+				if IRB = "00110110" or IRB = "11001011" then
+					Set_Addr_To <= aNone;
+				end if;
+			end if;
+			if MCycle = "111" then
+				if Mode = 0 then
+					TStates <= "101";
+				end if;
+				if ISet /= "01" then
+					Set_Addr_To <= aXY;
+				end if;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+				if IRB = "00110110" or ISet = "01" then
+					-- LD (HL),n
+					Inc_PC <= '1';
+				else
+					NoRead <= '1';
+				end if;
+			end if;
+		end if;
+
+	end process;
+
+end;
diff --git a/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/cpu/T80_Pack.vhd
new file mode 100644
index 00000000..42cf6105
--- /dev/null
+++ b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/cpu/T80_Pack.vhd	
@@ -0,0 +1,217 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package T80_Pack is
+
+	component T80
+	generic(
+		Mode : integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in std_logic;
+		CLK_n           : in std_logic;
+		CEN                     : in std_logic;
+		WAIT_n          : in std_logic;
+		INT_n           : in std_logic;
+		NMI_n           : in std_logic;
+		BUSRQ_n         : in std_logic;
+		M1_n            : out std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A                       : out std_logic_vector(15 downto 0);
+		DInst           : in std_logic_vector(7 downto 0);
+		DI                      : in std_logic_vector(7 downto 0);
+		DO                      : out std_logic_vector(7 downto 0);
+		MC                      : out std_logic_vector(2 downto 0);
+		TS                      : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out std_logic
+	);
+	end component;
+
+	component T80_Reg
+	port(
+		Clk                     : in std_logic;
+		CEN                     : in std_logic;
+		WEH                     : in std_logic;
+		WEL                     : in std_logic;
+		AddrA           : in std_logic_vector(2 downto 0);
+		AddrB           : in std_logic_vector(2 downto 0);
+		AddrC           : in std_logic_vector(2 downto 0);
+		DIH                     : in std_logic_vector(7 downto 0);
+		DIL                     : in std_logic_vector(7 downto 0);
+		DOAH            : out std_logic_vector(7 downto 0);
+		DOAL            : out std_logic_vector(7 downto 0);
+		DOBH            : out std_logic_vector(7 downto 0);
+		DOBL            : out std_logic_vector(7 downto 0);
+		DOCH            : out std_logic_vector(7 downto 0);
+		DOCL            : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+	component T80_MCode
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR                      : in  std_logic_vector(7 downto 0);
+		ISet                    : in  std_logic_vector(1 downto 0);
+		MCycle                  : in  std_logic_vector(2 downto 0);
+		F                       : in  std_logic_vector(7 downto 0);
+		NMICycle                : in  std_logic;
+		IntCycle                : in  std_logic;
+		MCycles                 : out std_logic_vector(2 downto 0);
+		TStates                 : out std_logic_vector(2 downto 0);
+		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC                  : out std_logic;
+		Inc_WZ                  : out std_logic;
+		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg             : out std_logic;
+		Read_To_Acc             : out std_logic;
+		Set_BusA_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU                : out std_logic;
+		PreserveC               : out std_logic;
+		Arith16                 : out std_logic;
+		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ                    : out std_logic;
+		Jump                    : out std_logic;
+		JumpE                   : out std_logic;
+		JumpXY                  : out std_logic;
+		Call                    : out std_logic;
+		RstP                    : out std_logic;
+		LDZ                     : out std_logic;
+		LDW                     : out std_logic;
+		LDSPHL                  : out std_logic;
+		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH              : out std_logic;
+		ExchangeRp              : out std_logic;
+		ExchangeAF              : out std_logic;
+		ExchangeRS              : out std_logic;
+		I_DJNZ                  : out std_logic;
+		I_CPL                   : out std_logic;
+		I_CCF                   : out std_logic;
+		I_SCF                   : out std_logic;
+		I_RETN                  : out std_logic;
+		I_BT                    : out std_logic;
+		I_BC                    : out std_logic;
+		I_BTR                   : out std_logic;
+		I_RLD                   : out std_logic;
+		I_RRD                   : out std_logic;
+		I_INRC                  : out std_logic;
+		SetDI                   : out std_logic;
+		SetEI                   : out std_logic;
+		IMode                   : out std_logic_vector(1 downto 0);
+		Halt                    : out std_logic;
+		NoRead                  : out std_logic;
+		Write                   : out std_logic
+	);
+	end component;
+
+	component T80_ALU
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+end;
diff --git a/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/cpu/T80_Reg.vhd
new file mode 100644
index 00000000..828485fb
--- /dev/null
+++ b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/cpu/T80_Reg.vhd	
@@ -0,0 +1,105 @@
+--
+-- T80 Registers, technology independent
+--
+-- Version : 0244
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--	http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+--	0242 : Initial release
+--
+--	0244 : Changed to single register file
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_Reg is
+	port(
+		Clk			: in std_logic;
+		CEN			: in std_logic;
+		WEH			: in std_logic;
+		WEL			: in std_logic;
+		AddrA		: in std_logic_vector(2 downto 0);
+		AddrB		: in std_logic_vector(2 downto 0);
+		AddrC		: in std_logic_vector(2 downto 0);
+		DIH			: in std_logic_vector(7 downto 0);
+		DIL			: in std_logic_vector(7 downto 0);
+		DOAH		: out std_logic_vector(7 downto 0);
+		DOAL		: out std_logic_vector(7 downto 0);
+		DOBH		: out std_logic_vector(7 downto 0);
+		DOBL		: out std_logic_vector(7 downto 0);
+		DOCH		: out std_logic_vector(7 downto 0);
+		DOCL		: out std_logic_vector(7 downto 0)
+	);
+end T80_Reg;
+
+architecture rtl of T80_Reg is
+
+	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
+	signal	RegsH	: Register_Image(0 to 7);
+	signal	RegsL	: Register_Image(0 to 7);
+
+begin
+
+	process (Clk)
+	begin
+		if Clk'event and Clk = '1' then
+			if CEN = '1' then
+				if WEH = '1' then
+					RegsH(to_integer(unsigned(AddrA))) <= DIH;
+				end if;
+				if WEL = '1' then
+					RegsL(to_integer(unsigned(AddrA))) <= DIL;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	DOAH <= RegsH(to_integer(unsigned(AddrA)));
+	DOAL <= RegsL(to_integer(unsigned(AddrA)));
+	DOBH <= RegsH(to_integer(unsigned(AddrB)));
+	DOBL <= RegsL(to_integer(unsigned(AddrB)));
+	DOCH <= RegsH(to_integer(unsigned(AddrC)));
+	DOCL <= RegsL(to_integer(unsigned(AddrC)));
+
+end;
diff --git a/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/cpu/T80sed.vhd b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/cpu/T80sed.vhd
new file mode 100644
index 00000000..0c28ec21
--- /dev/null
+++ b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/cpu/T80sed.vhd	
@@ -0,0 +1,179 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ **
+--
+-- Z80 compatible microprocessor core, synchronous top level with clock enable
+-- Different timing than the original z80
+-- Inputs needs to be synchronous and outputs may glitch
+--
+-- Version : 0238
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0235 : First release
+--
+--      0236 : Added T2Write generic
+--
+--      0237 : Fixed T2Write with wait state
+--
+--      0238 : Updated for T80 interface change
+--
+--      0242 : Updated for T80 interface change
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80sed is
+	port(
+		RESET_n         : in  std_logic;
+		CLK_n           : in  std_logic;
+		CLKEN           : in  std_logic;
+		WAIT_n          : in  std_logic;
+		INT_n           : in  std_logic;
+		NMI_n           : in  std_logic;
+		BUSRQ_n         : in  std_logic;
+		M1_n            : out std_logic;
+		MREQ_n          : out std_logic;
+		IORQ_n          : out std_logic;
+		RD_n            : out std_logic;
+		WR_n            : out std_logic;
+		RFSH_n          : out std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0)
+	);
+end T80sed;
+
+architecture rtl of T80sed is
+
+	signal IntCycle_n   : std_logic;
+	signal NoRead       : std_logic;
+	signal Write        : std_logic;
+	signal IORQ         : std_logic;
+	signal DI_Reg       : std_logic_vector(7 downto 0);
+	signal MCycle       : std_logic_vector(2 downto 0);
+	signal TState       : std_logic_vector(2 downto 0);
+
+begin
+
+	u0 : T80
+		generic map(
+			Mode      => 0,
+			IOWait    => 1)
+		port map(
+			CEN        => CLKEN,
+			M1_n       => M1_n,
+			IORQ       => IORQ,
+			NoRead     => NoRead,
+			Write      => Write,
+			RFSH_n     => RFSH_n,
+			HALT_n     => HALT_n,
+			WAIT_n     => Wait_n,
+			INT_n      => INT_n,
+			NMI_n      => NMI_n,
+			RESET_n    => RESET_n,
+			BUSRQ_n    => BUSRQ_n,
+			BUSAK_n    => BUSAK_n,
+			CLK_n      => CLK_n,
+			A          => A,
+			DInst      => DI,
+			DI         => DI_Reg,
+			DO         => DO,
+			MC         => MCycle,
+			TS         => TState,
+			IntCycle_n => IntCycle_n);
+
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			RD_n <= '1';
+			WR_n <= '1';
+			IORQ_n <= '1';
+			MREQ_n <= '1';
+			DI_Reg <= "00000000";
+		elsif CLK_n'event and CLK_n = '1' then
+			if CLKEN = '1' then
+				RD_n <= '1';
+				WR_n <= '1';
+				IORQ_n <= '1';
+				MREQ_n <= '1';
+				if MCycle = "001" then
+					if TState = "001" or (TState = "010" and Wait_n = '0') then
+						RD_n <= not IntCycle_n;
+						MREQ_n <= not IntCycle_n;
+						IORQ_n <= IntCycle_n;
+					end if;
+					if TState = "011" then
+						MREQ_n <= '0';
+					end if;
+				else
+					if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then
+						RD_n <= '0';
+						IORQ_n <= not IORQ;
+						MREQ_n <= IORQ;
+					end if;
+						if ((TState = "001") or (TState = "010")) and Write = '1' then
+							WR_n <= '0';
+							IORQ_n <= not IORQ;
+							MREQ_n <= IORQ;
+						end if;
+				end if;
+				if TState = "010" and Wait_n = '1' then
+					DI_Reg <= DI;
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/dac.vhd b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/dac.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/dac.vhd
rename to Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/dac.vhd
diff --git a/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/dpram.vhd b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/dpram.vhd
new file mode 100644
index 00000000..78823ec4
--- /dev/null
+++ b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/dpram.vhd	
@@ -0,0 +1,58 @@
+-------------------------------------------------------------------------------
+-- $Id: dpram.vhd,v 1.1 2006/02/23 21:46:45 arnim Exp $
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dpram is
+
+generic (
+	 addr_width_g : integer := 8;
+	 data_width_g : integer := 8
+);
+port (
+	clk_a_i  : in  std_logic;
+	en_a_i   : in  std_logic;
+	we_i     : in  std_logic;
+	addr_a_i : in  std_logic_vector(addr_width_g-1 downto 0);
+	data_a_i : in  std_logic_vector(data_width_g-1 downto 0);
+	data_a_o : out std_logic_vector(data_width_g-1 downto 0);
+	clk_b_i  : in  std_logic;
+	addr_b_i : in  std_logic_vector(addr_width_g-1 downto 0);
+	data_b_o : out std_logic_vector(data_width_g-1 downto 0)
+);
+
+end dpram;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+architecture rtl of dpram is
+
+  type   ram_t is array (natural range 2**addr_width_g-1 downto 0) of std_logic_vector(data_width_g-1 downto 0);
+  signal ram_q : ram_t;
+
+begin
+
+  mem_a: process (clk_a_i)
+  begin
+    if rising_edge(clk_a_i) then
+      if we_i = '1' and en_a_i = '1' then
+        ram_q(to_integer(unsigned(addr_a_i))) <= data_a_i;
+		  data_a_o <= data_a_i;
+		else
+		  data_a_o <= ram_q(to_integer(unsigned(addr_a_i)));
+      end if;
+    end if;
+  end process mem_a;
+
+  mem_b: process (clk_b_i)
+  begin
+    if rising_edge(clk_b_i) then
+		data_b_o <= ram_q(to_integer(unsigned(addr_b_i)));
+    end if;
+  end process mem_b;
+
+end rtl;
diff --git a/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/i82c55.vhd b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/i82c55.vhd
new file mode 100644
index 00000000..d415d932
--- /dev/null
+++ b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/i82c55.vhd	
@@ -0,0 +1,686 @@
+--
+-- A simulation model of Scramble hardware
+-- Copyright (c) MikeJ - Feb 2007
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- You are responsible for any legal issues arising from your use of this code.
+--
+-- The latest version of this file can be found at: www.fpgaarcade.com
+--
+-- Email support@fpgaarcade.com
+--
+-- Revision list
+--
+-- version 001 initial release
+--
+
+library ieee ;
+  use ieee.std_logic_1164.all ;
+  use ieee.std_logic_unsigned.all;
+  use ieee.numeric_std.all;
+
+entity I82C55 is
+  port (
+
+    I_ADDR            : in    std_logic_vector(1 downto 0); -- A1-A0
+    I_DATA            : in    std_logic_vector(7 downto 0); -- D7-D0
+    O_DATA            : out   std_logic_vector(7 downto 0);
+    O_DATA_OE_L       : out   std_logic;
+
+    I_CS_L            : in    std_logic;
+    I_RD_L            : in    std_logic;
+    I_WR_L            : in    std_logic;
+
+    I_PA              : in    std_logic_vector(7 downto 0);
+    O_PA              : out   std_logic_vector(7 downto 0);
+    O_PA_OE_L         : out   std_logic_vector(7 downto 0);
+
+    I_PB              : in    std_logic_vector(7 downto 0);
+    O_PB              : out   std_logic_vector(7 downto 0);
+    O_PB_OE_L         : out   std_logic_vector(7 downto 0);
+
+    I_PC              : in    std_logic_vector(7 downto 0);
+    O_PC              : out   std_logic_vector(7 downto 0);
+    O_PC_OE_L         : out   std_logic_vector(7 downto 0);
+
+    RESET             : in    std_logic;
+    ENA               : in    std_logic; -- (CPU) clk enable
+    CLK               : in    std_logic
+    );
+end;
+
+architecture RTL of I82C55 is
+
+  -- registers
+  signal bit_mask          : std_logic_vector(7 downto 0);
+  signal r_porta           : std_logic_vector(7 downto 0);
+  signal r_portb           : std_logic_vector(7 downto 0);
+  signal r_portc           : std_logic_vector(7 downto 0);
+  signal r_control         : std_logic_vector(7 downto 0);
+  --
+  signal porta_we          : std_logic;
+  signal portb_we          : std_logic;
+  signal porta_re          : std_logic;
+  signal portb_re          : std_logic;
+  --
+  signal porta_we_t1       : std_logic;
+  signal portb_we_t1       : std_logic;
+  signal porta_re_t1       : std_logic;
+  signal portb_re_t1       : std_logic;
+  --
+  signal porta_we_rising   : boolean;
+  signal portb_we_rising   : boolean;
+  signal porta_re_rising   : boolean;
+  signal portb_re_rising   : boolean;
+  --
+  signal groupa_mode       : std_logic_vector(1 downto 0); -- port a/c upper
+  signal groupb_mode       : std_logic;                    -- port b/c lower
+  --
+  signal porta_read        : std_logic_vector(7 downto 0);
+  signal portb_read        : std_logic_vector(7 downto 0);
+  signal portc_read        : std_logic_vector(7 downto 0);
+  signal control_read      : std_logic_vector(7 downto 0);
+  signal mode_clear        : std_logic;
+  --
+  signal a_inte1           : std_logic;
+  signal a_inte2           : std_logic;
+  signal b_inte            : std_logic;
+  --
+  signal a_intr            : std_logic;
+  signal a_obf_l           : std_logic;
+  signal a_ibf             : std_logic;
+  signal a_ack_l           : std_logic;
+  signal a_stb_l           : std_logic;
+  signal a_ack_l_t1        : std_logic;
+  signal a_stb_l_t1        : std_logic;
+  --
+  signal b_intr            : std_logic;
+  signal b_obf_l           : std_logic;
+  signal b_ibf             : std_logic;
+  signal b_ack_l           : std_logic;
+  signal b_stb_l           : std_logic;
+  signal b_ack_l_t1        : std_logic;
+  signal b_stb_l_t1        : std_logic;
+  --
+  signal a_ack_l_rising    : boolean;
+  signal a_stb_l_rising    : boolean;
+  signal b_ack_l_rising    : boolean;
+  signal b_stb_l_rising    : boolean;
+  --
+  signal porta_ipreg       : std_logic_vector(7 downto 0);
+  signal portb_ipreg       : std_logic_vector(7 downto 0);
+begin
+  --
+  -- mode 0   - basic input/output
+  -- mode 1   - strobed input/output
+  -- mode 2/3 - bi-directional bus
+  --
+  -- control word (write)
+  --
+  -- D7    mode set flag        1 = active
+  -- D6..5 GROUPA mode selection (mode 0,1,2)
+  -- D4    GROUPA porta         1 = input, 0 = output
+  -- D3    GROUPA portc upper   1 = input, 0 = output
+  -- D2    GROUPB mode selection (mode 0 ,1)
+  -- D1    GROUPB portb         1 = input, 0 = output
+  -- D0    GROUPB portc lower   1 = input, 0 = output
+  --
+  -- D7    bit set/reset        0 = active
+  -- D6..4 x
+  -- D3..1 bit select
+  -- d0    1 = set, 0 - reset
+  --
+  -- all output registers including status are reset when mode is changed
+    --1. Port A:
+    --All Modes: Output data is cleared, input data is not cleared.
+
+    --2. Port B:
+    --Mode 0: Output data is cleared, input data is not cleared.
+    --Mode 1 and 2: Both output and input data are cleared.
+
+    --3. Port C:
+    --Mode 0:Output data is cleared, input data is not cleared.
+    --Mode 1 and 2: IBF and INTR are cleared and OBF# is set.
+    --Outputs in Port C which are not used for handshaking or interrupt signals are cleared.
+    --Inputs such as STB#, ACK#, or "spare" inputs are not affected. The interrupts for Ports A and B are disabled.
+
+  p_bit_mask : process(I_DATA)
+  begin
+    bit_mask <= x"01";
+    case I_DATA(3 downto 1) is
+      when "000" => bit_mask <= x"01";
+      when "001" => bit_mask <= x"02";
+      when "010" => bit_mask <= x"04";
+      when "011" => bit_mask <= x"08";
+      when "100" => bit_mask <= x"10";
+      when "101" => bit_mask <= x"20";
+      when "110" => bit_mask <= x"40";
+      when "111" => bit_mask <= x"80";
+      when others => null;
+    end case;
+  end process;
+
+  p_write_reg_reset : process(RESET, CLK)
+    variable r_portc_masked : std_logic_vector(7 downto 0);
+    variable r_portc_setclr : std_logic_vector(7 downto 0);
+  begin
+    if (RESET = '1') then
+      r_porta <= x"00";
+      r_portb <= x"00";
+      r_portc <= x"00";
+      r_control <= x"9B"; -- 10011011
+      mode_clear <= '1';
+    elsif rising_edge(CLK) then
+
+      r_portc_masked := (not bit_mask) and r_portc;
+      for i in 0 to 7 loop
+        r_portc_setclr(i) := bit_mask(i) and I_DATA(0);
+      end loop;
+
+      if (ENA = '1') then
+        mode_clear <= '0';
+        if (I_CS_L = '0') and (I_WR_L = '0') then
+          case I_ADDR is
+            when "00" => r_porta   <= I_DATA;
+            when "01" => r_portb   <= I_DATA;
+            when "10" => r_portc   <= I_DATA;
+
+            when "11" => if (I_DATA(7) = '0') then -- set/clr
+                           r_portc <= r_portc_masked or r_portc_setclr;
+                         else
+                           --mode_clear <= '1';
+                           --r_porta    <= x"00";
+                           --r_portb    <= x"00"; -- clear port b input reg
+                           --r_portc    <= x"00"; -- clear control sigs
+                           r_control  <= I_DATA; -- load new mode
+                         end if;
+            when others => null;
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  p_decode_control : process(r_control)
+  begin
+    groupa_mode <= r_control(6 downto 5);
+    groupb_mode <= r_control(2);
+  end process;
+
+  p_oe : process(I_CS_L, I_RD_L)
+  begin
+    O_DATA_OE_L <= '1';
+    if (I_CS_L = '0') and (I_RD_L = '0') then
+      O_DATA_OE_L <= '0';
+    end if;
+  end process;
+
+  p_read : process(I_ADDR, porta_read, portb_read, portc_read, control_read)
+  begin
+    O_DATA <= x"00"; -- default
+    --if (I_CS_L = '0') and (I_RD_L = '0') then -- not required
+      case I_ADDR is
+        when "00" => O_DATA <= porta_read;
+        when "01" => O_DATA <= portb_read;
+        when "10" => O_DATA <= portc_read;
+        when "11" => O_DATA <= control_read;
+        when others => null;
+      end case;
+    --end if;
+  end process;
+  control_read(7) <= '1'; -- always 1
+  control_read(6 downto 0) <= r_control(6 downto 0);
+
+  p_rw_control : process(I_CS_L, I_RD_L, I_WR_L, I_ADDR)
+  begin
+    porta_we <= '0';
+    portb_we <= '0';
+    porta_re <= '0';
+    portb_re <= '0';
+
+    if (I_CS_L = '0') and (I_ADDR = "00") then
+      porta_we <= not I_WR_L;
+      porta_re <= not I_RD_L;
+    end if;
+
+    if (I_CS_L = '0') and (I_ADDR = "01") then
+      portb_we <= not I_WR_L;
+      portb_re <= not I_RD_L;
+    end if;
+  end process;
+
+  p_rw_control_reg : process
+  begin
+    wait until rising_edge(CLK);
+    if (ENA = '1') then
+      porta_we_t1 <= porta_we;
+      portb_we_t1 <= portb_we;
+      porta_re_t1 <= porta_re;
+      portb_re_t1 <= portb_re;
+
+      a_stb_l_t1 <= a_stb_l;
+      a_ack_l_t1 <= a_ack_l;
+      b_stb_l_t1 <= b_stb_l;
+      b_ack_l_t1 <= b_ack_l;
+    end if;
+  end process;
+
+  porta_we_rising <= (porta_we = '0') and (porta_we_t1 = '1'); -- falling as inverted
+  portb_we_rising <= (portb_we = '0') and (portb_we_t1 = '1'); --  "
+  porta_re_rising <= (porta_re = '0') and (porta_re_t1 = '1'); -- falling as inverted
+  portb_re_rising <= (portb_re = '0') and (portb_re_t1 = '1'); --  "
+  --
+  a_stb_l_rising  <= (a_stb_l = '1') and (a_stb_l_t1 = '0');
+  a_ack_l_rising  <= (a_ack_l = '1') and (a_ack_l_t1 = '0');
+  b_stb_l_rising  <= (b_stb_l = '1') and (b_stb_l_t1 = '0');
+  b_ack_l_rising  <= (b_ack_l = '1') and (b_ack_l_t1 = '0');
+  --
+  -- GROUP A
+  -- in mode 1
+  --
+  -- d4=1 (porta = input)
+  --   pc7,6 io (d3=1 input, d3=0 output)
+  --   pc5 output a_ibf
+  --   pc4 input  a_stb_l
+  --   pc3 output a_intr
+  --
+  -- d4=0 (porta = output)
+  --   pc7 output a_obf_l
+  --   pc6 input  a_ack_l
+  --   pc5,4 io (d3=1 input, d3=0 output)
+  --   pc3 output a_intr
+  --
+  -- GROUP B
+  -- in mode 1
+  -- d1=1 (portb = input)
+  --   pc2 input  b_stb_l
+  --   pc1 output b_ibf
+  --   pc0 output b_intr
+  --
+  -- d1=0 (portb = output)
+  --   pc2 input  b_ack_l
+  --   pc1 output b_obf_l
+  --   pc0 output b_intr
+
+
+  -- WHEN AN INPUT
+  --
+  -- stb_l a low on this input latches input data
+  -- ibf   a high on this output indicates data latched. set by stb_l and reset by rising edge of RD_L
+  -- intr  a high on this output indicates interrupt. set by stb_l high, ibf high and inte high. reset by falling edge of RD_L
+  -- inte A controlled by bit/set PC4
+  -- inte B controlled by bit/set PC2
+
+  -- WHEN AN OUTPUT
+  --
+  -- obf_l output will go low when cpu has written data
+  -- ack_l input - a low on this clears obf_l
+  -- intr  output set when ack_l is high, obf_l is high and inte is one. reset by falling edge of WR_L
+  -- inte A controlled by bit/set PC6
+  -- inte B controlled by bit/set PC2
+
+  -- GROUP A
+  -- in mode 2
+  --
+  -- porta = IO
+  --
+  --  control bits 2..0 still control groupb/c lower 2..0
+  --
+  --
+  --  PC7 output a_obf
+  --  PC6 input  a_ack_l
+  --  PC5 output a_ibf
+  --  PC4 input  a_stb_l
+  --  PC3 is still interrupt out
+  p_control_flags : process(RESET, CLK)
+    variable we   : boolean;
+    variable set1 : boolean;
+    variable set2 : boolean;
+  begin
+    if (RESET = '1') then
+      a_obf_l <= '1';
+      a_inte1 <= '0';
+      a_ibf   <= '0';
+      a_inte2 <= '0';
+      a_intr  <= '0';
+      --
+      b_inte  <= '0';
+      b_obf_l <= '1';
+      b_ibf   <= '0';
+      b_intr  <= '0';
+    elsif rising_edge(CLK) then
+      we := (I_CS_L = '0') and (I_WR_L = '0') and (I_ADDR = "11") and (I_DATA(7) = '0');
+
+      if (ENA = '1') then
+        if (mode_clear = '1') then
+          a_obf_l <= '1';
+          a_inte1 <= '0';
+          a_ibf   <= '0';
+          a_inte2 <= '0';
+          a_intr  <= '0';
+          --
+          b_inte  <= '0';
+          b_obf_l <= '1';
+          b_ibf   <= '0';
+          b_intr  <= '0';
+        else
+          if (bit_mask(7) = '1') and we then
+            a_obf_l <= I_DATA(0);
+          else
+            if porta_we_rising then
+              a_obf_l <= '0';
+            elsif (a_ack_l = '0') then
+              a_obf_l <= '1';
+            end if;
+          end if;
+          --
+          if (bit_mask(6) = '1') and we then a_inte1 <= I_DATA(0); end if; -- bus set when mode1 & input?
+          --
+          if (bit_mask(5) = '1') and we then
+            a_ibf   <= I_DATA(0);
+          else
+            if porta_re_rising then
+              a_ibf <= '0';
+            elsif (a_stb_l = '0') then
+              a_ibf <= '1';
+            end if;
+          end if;
+          --
+          if (bit_mask(4) = '1') and we then a_inte2 <= I_DATA(0); end if; -- bus set when mode1 & output?
+          --
+          set1 := a_ack_l_rising and (a_obf_l = '1') and (a_inte1 = '1');
+          set2 := a_stb_l_rising and (a_ibf   = '1') and (a_inte2 = '1');
+          --
+          if (bit_mask(3) = '1') and we then
+            a_intr  <= I_DATA(0);
+          else
+            if (groupa_mode(1) = '1') then
+              if (porta_we = '1') or (porta_re = '1') then
+                 a_intr <= '0';
+               elsif set1 or set2 then
+                 a_intr <= '1';
+               end if;
+            else
+              if    (r_control(4) = '0') then -- output
+                if (porta_we = '1') then -- falling ?
+                  a_intr <= '0';
+                elsif set1 then
+                  a_intr <= '1';
+                end if;
+              elsif (r_control(4) = '1') then -- input
+                if (porta_re = '1') then -- falling ?
+                  a_intr <= '0';
+                elsif set2 then
+                  a_intr <= '1';
+                end if;
+              end if;
+            end if;
+          end if;
+          --
+          if (bit_mask(2) = '1') and we then b_inte  <= I_DATA(0); end if; -- bus set?
+
+          if (bit_mask(1) = '1') and we then
+            b_obf_l <= I_DATA(0);
+          else
+            if (r_control(1) = '0') then -- output
+              if portb_we_rising then
+                b_obf_l <= '0';
+              elsif (b_ack_l = '0') then
+                b_obf_l <= '1';
+              end if;
+            else
+              if portb_re_rising then
+                b_ibf <= '0';
+              elsif (b_stb_l = '0') then
+                b_ibf <= '1';
+              end if;
+            end if;
+          end if;
+
+          if (bit_mask(0) = '1') and we then
+            b_intr  <= I_DATA(0);
+          else
+            if (r_control(1) = '0') then -- output
+              if (portb_we = '1') then -- falling ?
+                b_intr <= '0';
+              elsif b_ack_l_rising and (b_obf_l = '1') and (b_inte = '1') then
+                b_intr <= '1';
+              end if;
+            else
+              if (portb_re = '1') then -- falling ?
+                b_intr <= '0';
+              elsif b_stb_l_rising and (b_ibf = '1') and (b_inte = '1') then
+                b_intr <= '1';
+              end if;
+            end if;
+          end if;
+
+        end if;
+      end if;
+    end if;
+  end process;
+
+  p_porta : process(r_control, groupa_mode, r_porta, I_PA, porta_ipreg, a_ack_l)
+  begin
+    -- D4    GROUPA porta         1 = input, 0 = output
+    O_PA       <= x"FF"; -- if not driven, float high
+    O_PA_OE_L  <= x"FF";
+    porta_read <= x"00";
+
+    if    (groupa_mode = "00") then -- simple io
+      if (r_control(4) = '0') then -- output
+        O_PA       <= r_porta;
+        O_PA_OE_L  <= x"00";
+      end if;
+      porta_read <= I_PA;
+    elsif (groupa_mode = "01") then -- strobed
+      if (r_control(4) = '0') then -- output
+        O_PA       <= r_porta;
+        O_PA_OE_L  <= x"00";
+      end if;
+      porta_read <= porta_ipreg;
+    else -- if (groupa_mode(1) = '1') then -- bi dir
+      if (a_ack_l = '0') then -- output enable
+        O_PA       <= r_porta;
+        O_PA_OE_L  <= x"00";
+      end if;
+      porta_read <= porta_ipreg; -- latched data
+    end if;
+
+  end process;
+
+  p_portb : process(r_control, groupb_mode, r_portb, I_PB, portb_ipreg)
+  begin
+    O_PB       <= x"FF"; -- if not driven, float high
+    O_PB_OE_L  <= x"FF";
+    portb_read <= x"00";
+
+    if (groupb_mode = '0') then -- simple io
+      if (r_control(1) = '0') then -- output
+        O_PB       <= r_portb;
+        O_PB_OE_L  <= x"00";
+      end if;
+      portb_read <= I_PB;
+    else -- strobed mode
+      if (r_control(1) = '0') then -- output
+        O_PB       <= r_portb;
+        O_PB_OE_L  <= x"00";
+      end if;
+      portb_read <= portb_ipreg;
+    end if;
+  end process;
+
+  p_portc_out : process(r_portc, r_control, groupa_mode, groupb_mode,
+                        a_obf_l, a_ibf, a_intr,b_obf_l, b_ibf, b_intr)
+  begin
+    O_PC       <= x"FF"; -- if not driven, float high
+    O_PC_OE_L  <= x"FF";
+
+    -- bits 7..4
+    if    (groupa_mode = "00") then -- simple io
+      if (r_control(3) = '0') then -- output
+        O_PC     (7 downto 4)  <= r_portc(7 downto 4);
+        O_PC_OE_L(7 downto 4)  <= x"0";
+      end if;
+    elsif (groupa_mode = "01") then -- mode1
+
+      if (r_control(4) = '0') then -- port a output
+        O_PC     (7) <= a_obf_l;
+        O_PC_OE_L(7) <= '0';
+        -- 6 is ack_l input
+        if (r_control(3) = '0') then -- port c output
+          O_PC     (5 downto 4) <= r_portc(5 downto 4);
+          O_PC_OE_L(5 downto 4) <= "00";
+        end if;
+      else -- port a input
+        if (r_control(3) = '0') then -- port c output
+          O_PC     (7 downto 6) <= r_portc(7 downto 6);
+          O_PC_OE_L(7 downto 6) <= "00";
+        end if;
+        O_PC     (5) <= a_ibf;
+        O_PC_OE_L(5) <= '0';
+        -- 4 is stb_l input
+      end if;
+
+    else -- if (groupa_mode(1) = '1') then -- mode2
+      O_PC     (7) <= a_obf_l;
+      O_PC_OE_L(7) <= '0';
+      -- 6 is ack_l input
+      O_PC     (5) <= a_ibf;
+      O_PC_OE_L(5) <= '0';
+      -- 4 is stb_l input
+    end if;
+
+    -- bit 3 (controlled by group a)
+    if    (groupa_mode = "00") then -- group a steals this bit
+      --if (groupb_mode = '0') then -- we will let bit 3 be driven, data sheet is a bit confused about this
+        if (r_control(0) = '0') then -- ouput (note, groupb control bit)
+          O_PC     (3) <= r_portc(3);
+          O_PC_OE_L(3) <= '0';
+        end if;
+      --
+    else -- stolen
+      O_PC     (3) <= a_intr;
+      O_PC_OE_L(3) <= '0';
+    end if;
+
+    -- bits 2..0
+    if    (groupb_mode = '0') then -- simple io
+      if (r_control(0) = '0') then -- output
+        O_PC     (2 downto 0)  <= r_portc(2 downto 0);
+        O_PC_OE_L(2 downto 0)  <= "000";
+      end if;
+    else
+      -- mode 1
+      -- 2 is input
+      if (r_control(1) = '0') then -- output
+        O_PC     (1) <= b_obf_l;
+        O_PC_OE_L(1) <= '0';
+      else -- input
+        O_PC     (1) <= b_ibf;
+        O_PC_OE_L(1) <= '0';
+      end if;
+      O_PC     (0) <= b_intr;
+      O_PC_OE_L(0) <= '0';
+    end if;
+  end process;
+
+  p_portc_in : process(r_portc, I_PC, r_control, groupa_mode, groupb_mode, a_ibf, b_obf_l,
+                       a_obf_l, a_inte1, a_inte2, a_intr, b_inte, b_ibf, b_intr)
+  begin
+    portc_read <= x"00";
+
+    a_stb_l <= '1';
+    a_ack_l <= '1';
+    b_stb_l <= '1';
+    b_ack_l <= '1';
+
+    if    (groupa_mode = "01") then -- mode1 or 2
+      if (r_control(4) = '0') then -- port a output
+        a_ack_l <= I_PC(6);
+      else -- port a input
+        a_stb_l <= I_PC(4);
+      end if;
+    elsif (groupa_mode(1) = '1') then -- mode 2
+      a_ack_l <= I_PC(6);
+      a_stb_l <= I_PC(4);
+    end if;
+
+    if (groupb_mode = '1') then
+      if (r_control(1) = '0') then -- output
+        b_ack_l <= I_PC(2);
+      else -- input
+        b_stb_l <= I_PC(2);
+      end if;
+    end if;
+
+    if    (groupa_mode = "00") then -- simple io
+      portc_read(7 downto 3) <= I_PC(7 downto 3);
+    elsif (groupa_mode = "01") then
+      if (r_control(4) = '0') then -- port a output
+        portc_read(7 downto 3) <= a_obf_l & a_inte1 & I_PC(5 downto 4) & a_intr;
+      else -- input
+        portc_read(7 downto 3) <= I_PC(7 downto 6) & a_ibf & a_inte2 & a_intr;
+      end if;
+    else -- mode 2
+      portc_read(7 downto 3) <= a_obf_l & a_inte1 & a_ibf & a_inte2 & a_intr;
+    end if;
+
+    if    (groupb_mode = '0') then -- simple io
+      portc_read(2 downto 0) <= I_PC(2 downto 0);
+    else
+      if (r_control(1) = '0') then -- output
+        portc_read(2 downto 0) <= b_inte & b_obf_l & b_intr;
+      else -- input
+        portc_read(2 downto 0) <= b_inte & b_ibf   & b_intr;
+      end if;
+    end if;
+  end process;
+
+  p_ipreg : process
+  begin
+    wait until rising_edge(CLK);
+    --   pc4 input  a_stb_l
+    --   pc2 input  b_stb_l
+
+    if (ENA = '1') then
+      if (a_stb_l = '0') then
+        porta_ipreg <= I_PA;
+      end if;
+
+      if (mode_clear = '1') then
+        portb_ipreg <= (others => '0');
+      elsif (b_stb_l = '0') then
+        portb_ipreg <= I_PB;
+      end if;
+    end if;
+  end process;
+
+end architecture RTL;
diff --git a/Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/osd.v b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/osd.v
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/osd.v
rename to Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/osd.v
diff --git a/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/pll.qip b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/pll.qip
new file mode 100644
index 00000000..afd958be
--- /dev/null
+++ b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/pll.qip	
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
diff --git a/Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/pll.v b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/pll.v
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/pll.v
rename to Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/pll.v
diff --git a/Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/scramble.vhd b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/scramble.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/scramble.vhd
rename to Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/scramble.vhd
diff --git a/Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/scramble_audio.vhd b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/scramble_audio.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/scramble_audio.vhd
rename to Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/scramble_audio.vhd
diff --git a/Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/scramble_top.vhd b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/scramble_top.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/scramble_top.vhd
rename to Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/scramble_top.vhd
diff --git a/Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/scramble_video.vhd b/Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/scramble_video.vhd
similarity index 100%
rename from Arcade_MiST/Scramble Hardware/TheEnd_MiST/rtl/scramble_video.vhd
rename to Arcade_MiST/Konami Scramble Hardware/TheEnd_MiST/rtl/scramble_video.vhd