diff --git a/Arcade_MiST/Konami Classic/Pooyan_MiST/pooyan_mist.qsf b/Arcade_MiST/Konami Classic/Pooyan_MiST/pooyan_mist.qsf
index b3d397d4..23214c87 100644
--- a/Arcade_MiST/Konami Classic/Pooyan_MiST/pooyan_mist.qsf
+++ b/Arcade_MiST/Konami Classic/Pooyan_MiST/pooyan_mist.qsf
@@ -41,30 +41,9 @@
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:45:13 JUNE 17,2016"
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/pooyan_mist.sv
-set_global_assignment -name VHDL_FILE rtl/pooyan.vhd
-set_global_assignment -name VHDL_FILE rtl/gen_video.vhd
-set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
-set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd
-set_global_assignment -name VHDL_FILE rtl/pooyan_sound_board.vhd
-set_global_assignment -name VERILOG_FILE rtl/pll.v
-set_global_assignment -name VHDL_FILE rtl/rom/pooyan_sprite_grphx2.vhd
-set_global_assignment -name VHDL_FILE rtl/rom/pooyan_sprite_grphx1.vhd
-set_global_assignment -name VHDL_FILE rtl/rom/pooyan_sprite_color_lut.vhd
-set_global_assignment -name VHDL_FILE rtl/rom/pooyan_sound_prog.vhd
-set_global_assignment -name VHDL_FILE rtl/rom/pooyan_palette.vhd
-set_global_assignment -name VHDL_FILE rtl/rom/pooyan_char_grphx2.vhd
-set_global_assignment -name VHDL_FILE rtl/rom/pooyan_char_grphx1.vhd
-set_global_assignment -name VHDL_FILE rtl/rom/pooyan_char_color_lut.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80se.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
# Pin & Location Assignments
# ==========================
@@ -136,6 +115,40 @@ set_location_assignment PIN_66 -to SDRAM_nWE
set_location_assignment PIN_59 -to SDRAM_nCS
set_location_assignment PIN_33 -to SDRAM_CKE
set_location_assignment PIN_43 -to SDRAM_CLK
+set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
+
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
+
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
# Classic Timing Assignments
# ==========================
@@ -198,9 +211,9 @@ set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
# Incremental Compilation Assignments
# ===================================
- set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
- set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
- set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
# end DESIGN_PARTITION(Top)
# -------------------------
@@ -208,5 +221,22 @@ set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
# end ENTITY(pooyan_mist)
# -----------------------
set_location_assignment PIN_127 -to SPI_SS2
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/pooyan_mist.sv
+set_global_assignment -name VHDL_FILE rtl/pooyan.vhd
+set_global_assignment -name VHDL_FILE rtl/gen_video.vhd
+set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
+set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd
+set_global_assignment -name VERILOG_FILE rtl/pll.v
+set_global_assignment -name VHDL_FILE rtl/rom/pooyan_sprite_grphx2.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/pooyan_sprite_grphx1.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/pooyan_sprite_color_lut.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/pooyan_sound_prog.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/pooyan_palette.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/pooyan_char_grphx2.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/pooyan_char_grphx1.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/pooyan_char_color_lut.vhd
+set_global_assignment -name VHDL_FILE rtl/pooyan_sound_board.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
+set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Konami Classic/Pooyan_MiST/pooyan_mist.sdc b/Arcade_MiST/Konami Classic/Pooyan_MiST/pooyan_mist.sdc
new file mode 100644
index 00000000..ca3faf31
--- /dev/null
+++ b/Arcade_MiST/Konami Classic/Pooyan_MiST/pooyan_mist.sdc
@@ -0,0 +1,138 @@
+## Generated SDC file "vectrex_MiST.out.sdc"
+
+## Copyright (C) 1991-2013 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions
+## and other software and tools, and its AMPP partner logic
+## functions, and any output files from any of the foregoing
+## (including device programming or simulation files), and any
+## associated documentation or information are expressly subject
+## to the terms and conditions of the Altera Program License
+## Subscription Agreement, Altera MegaCore Function License
+## Agreement, or other applicable license agreement, including,
+## without limitation, that your use is for the sole purpose of
+## programming logic devices manufactured by Altera and sold by
+## Altera or its authorized distributors. Please refer to the
+## applicable agreement for further details.
+
+
+## VENDOR "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+## DATE "Sun Jun 24 12:53:00 2018"
+
+##
+## DEVICE "EP3C25E144C8"
+##
+
+# Clock constraints
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
+
+set sys_clk "pll|altpll_component|auto_generated|pll1|clk[1]"
+set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
+set snd_clk "pll|altpll_component|auto_generated|pll1|clk[2]"
+set vid_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}]
+set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}]
+set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}]
+set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}]
+set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}]
+set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}]
+
+set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]]
+set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]]
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
+set_output_delay -add_delay -clock_fall -clock [get_clocks $snd_clk] 1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay -clock_fall -clock [get_clocks $snd_clk] 1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {LED}]
+set_output_delay -add_delay -clock_fall -clock [get_clocks $vid_clk] 1.000 [get_ports {VGA_*}]
+
+set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
+# audio-main cpu clocks are asynchronous
+set_clock_groups -asynchronous -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[3]}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}]
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+set_multicycle_path -to {VGA_*[*]} -setup 2
+set_multicycle_path -to {VGA_*[*]} -hold 1
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
diff --git a/Arcade_MiST/Konami Classic/Pooyan_MiST/pooyan_mist.srf b/Arcade_MiST/Konami Classic/Pooyan_MiST/pooyan_mist.srf
deleted file mode 100644
index e413eda9..00000000
--- a/Arcade_MiST/Konami Classic/Pooyan_MiST/pooyan_mist.srf
+++ /dev/null
@@ -1 +0,0 @@
-{ "" "" "" "*" { } { } 0 10492 "" 0 0 "Quartus II" 0 -1 0 ""}
diff --git a/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/T80/T80.vhd
deleted file mode 100644
index 398fa0df..00000000
--- a/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/T80/T80.vhd
+++ /dev/null
@@ -1,1073 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
--- 0208 : First complete release
---
--- 0210 : Fixed wait and halt
---
--- 0211 : Fixed Refresh addition and IM 1
---
--- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
--- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
--- 0235 : Added clock enable and IM 2 fix by Mike Johnson
---
--- 0237 : Changed 8080 I/O address output, added IntE output
---
--- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
--- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
--- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
--- 0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
- generic(
- Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
- IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
- Flag_C : integer := 0;
- Flag_N : integer := 1;
- Flag_P : integer := 2;
- Flag_X : integer := 3;
- Flag_H : integer := 4;
- Flag_Y : integer := 5;
- Flag_Z : integer := 6;
- Flag_S : integer := 7
- );
- port(
- RESET_n : in std_logic;
- CLK_n : in std_logic;
- CEN : in std_logic;
- WAIT_n : in std_logic;
- INT_n : in std_logic;
- NMI_n : in std_logic;
- BUSRQ_n : in std_logic;
- M1_n : out std_logic;
- IORQ : out std_logic;
- NoRead : out std_logic;
- Write : out std_logic;
- RFSH_n : out std_logic;
- HALT_n : out std_logic;
- BUSAK_n : out std_logic;
- A : out std_logic_vector(15 downto 0);
- DInst : in std_logic_vector(7 downto 0);
- DI : in std_logic_vector(7 downto 0);
- DO : out std_logic_vector(7 downto 0);
- MC : out std_logic_vector(2 downto 0);
- TS : out std_logic_vector(2 downto 0);
- IntCycle_n : out std_logic;
- IntE : out std_logic;
- Stop : out std_logic
- );
-end T80;
-
-architecture rtl of T80 is
-
- constant aNone : std_logic_vector(2 downto 0) := "111";
- constant aBC : std_logic_vector(2 downto 0) := "000";
- constant aDE : std_logic_vector(2 downto 0) := "001";
- constant aXY : std_logic_vector(2 downto 0) := "010";
- constant aIOA : std_logic_vector(2 downto 0) := "100";
- constant aSP : std_logic_vector(2 downto 0) := "101";
- constant aZI : std_logic_vector(2 downto 0) := "110";
-
- -- Registers
- signal ACC, F : std_logic_vector(7 downto 0);
- signal Ap, Fp : std_logic_vector(7 downto 0);
- signal I : std_logic_vector(7 downto 0);
- signal R : unsigned(7 downto 0);
- signal SP, PC : unsigned(15 downto 0);
- signal RegDIH : std_logic_vector(7 downto 0);
- signal RegDIL : std_logic_vector(7 downto 0);
- signal RegBusA : std_logic_vector(15 downto 0);
- signal RegBusB : std_logic_vector(15 downto 0);
- signal RegBusC : std_logic_vector(15 downto 0);
- signal RegAddrA_r : std_logic_vector(2 downto 0);
- signal RegAddrA : std_logic_vector(2 downto 0);
- signal RegAddrB_r : std_logic_vector(2 downto 0);
- signal RegAddrB : std_logic_vector(2 downto 0);
- signal RegAddrC : std_logic_vector(2 downto 0);
- signal RegWEH : std_logic;
- signal RegWEL : std_logic;
- signal Alternate : std_logic;
-
- -- Help Registers
- signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register
- signal IR : std_logic_vector(7 downto 0); -- Instruction register
- signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector
- signal RegBusA_r : std_logic_vector(15 downto 0);
-
- signal ID16 : signed(15 downto 0);
- signal Save_Mux : std_logic_vector(7 downto 0);
-
- signal TState : unsigned(2 downto 0);
- signal MCycle : std_logic_vector(2 downto 0);
- signal IntE_FF1 : std_logic;
- signal IntE_FF2 : std_logic;
- signal Halt_FF : std_logic;
- signal BusReq_s : std_logic;
- signal BusAck : std_logic;
- signal ClkEn : std_logic;
- signal NMI_s : std_logic;
- signal INT_s : std_logic;
- signal IStatus : std_logic_vector(1 downto 0);
-
- signal DI_Reg : std_logic_vector(7 downto 0);
- signal T_Res : std_logic;
- signal XY_State : std_logic_vector(1 downto 0);
- signal Pre_XY_F_M : std_logic_vector(2 downto 0);
- signal NextIs_XY_Fetch : std_logic;
- signal XY_Ind : std_logic;
- signal No_BTR : std_logic;
- signal BTR_r : std_logic;
- signal Auto_Wait : std_logic;
- signal Auto_Wait_t1 : std_logic;
- signal Auto_Wait_t2 : std_logic;
- signal IncDecZ : std_logic;
-
- -- ALU signals
- signal BusB : std_logic_vector(7 downto 0);
- signal BusA : std_logic_vector(7 downto 0);
- signal ALU_Q : std_logic_vector(7 downto 0);
- signal F_Out : std_logic_vector(7 downto 0);
-
- -- Registered micro code outputs
- signal Read_To_Reg_r : std_logic_vector(4 downto 0);
- signal Arith16_r : std_logic;
- signal Z16_r : std_logic;
- signal ALU_Op_r : std_logic_vector(3 downto 0);
- signal Save_ALU_r : std_logic;
- signal PreserveC_r : std_logic;
- signal MCycles : std_logic_vector(2 downto 0);
-
- -- Micro code outputs
- signal MCycles_d : std_logic_vector(2 downto 0);
- signal TStates : std_logic_vector(2 downto 0);
- signal IntCycle : std_logic;
- signal NMICycle : std_logic;
- signal Inc_PC : std_logic;
- signal Inc_WZ : std_logic;
- signal IncDec_16 : std_logic_vector(3 downto 0);
- signal Prefix : std_logic_vector(1 downto 0);
- signal Read_To_Acc : std_logic;
- signal Read_To_Reg : std_logic;
- signal Set_BusB_To : std_logic_vector(3 downto 0);
- signal Set_BusA_To : std_logic_vector(3 downto 0);
- signal ALU_Op : std_logic_vector(3 downto 0);
- signal Save_ALU : std_logic;
- signal PreserveC : std_logic;
- signal Arith16 : std_logic;
- signal Set_Addr_To : std_logic_vector(2 downto 0);
- signal Jump : std_logic;
- signal JumpE : std_logic;
- signal JumpXY : std_logic;
- signal Call : std_logic;
- signal RstP : std_logic;
- signal LDZ : std_logic;
- signal LDW : std_logic;
- signal LDSPHL : std_logic;
- signal IORQ_i : std_logic;
- signal Special_LD : std_logic_vector(2 downto 0);
- signal ExchangeDH : std_logic;
- signal ExchangeRp : std_logic;
- signal ExchangeAF : std_logic;
- signal ExchangeRS : std_logic;
- signal I_DJNZ : std_logic;
- signal I_CPL : std_logic;
- signal I_CCF : std_logic;
- signal I_SCF : std_logic;
- signal I_RETN : std_logic;
- signal I_BT : std_logic;
- signal I_BC : std_logic;
- signal I_BTR : std_logic;
- signal I_RLD : std_logic;
- signal I_RRD : std_logic;
- signal I_INRC : std_logic;
- signal SetDI : std_logic;
- signal SetEI : std_logic;
- signal IMode : std_logic_vector(1 downto 0);
- signal Halt : std_logic;
-
-begin
-
- mcode : T80_MCode
- generic map(
- Mode => Mode,
- Flag_C => Flag_C,
- Flag_N => Flag_N,
- Flag_P => Flag_P,
- Flag_X => Flag_X,
- Flag_H => Flag_H,
- Flag_Y => Flag_Y,
- Flag_Z => Flag_Z,
- Flag_S => Flag_S)
- port map(
- IR => IR,
- ISet => ISet,
- MCycle => MCycle,
- F => F,
- NMICycle => NMICycle,
- IntCycle => IntCycle,
- MCycles => MCycles_d,
- TStates => TStates,
- Prefix => Prefix,
- Inc_PC => Inc_PC,
- Inc_WZ => Inc_WZ,
- IncDec_16 => IncDec_16,
- Read_To_Acc => Read_To_Acc,
- Read_To_Reg => Read_To_Reg,
- Set_BusB_To => Set_BusB_To,
- Set_BusA_To => Set_BusA_To,
- ALU_Op => ALU_Op,
- Save_ALU => Save_ALU,
- PreserveC => PreserveC,
- Arith16 => Arith16,
- Set_Addr_To => Set_Addr_To,
- IORQ => IORQ_i,
- Jump => Jump,
- JumpE => JumpE,
- JumpXY => JumpXY,
- Call => Call,
- RstP => RstP,
- LDZ => LDZ,
- LDW => LDW,
- LDSPHL => LDSPHL,
- Special_LD => Special_LD,
- ExchangeDH => ExchangeDH,
- ExchangeRp => ExchangeRp,
- ExchangeAF => ExchangeAF,
- ExchangeRS => ExchangeRS,
- I_DJNZ => I_DJNZ,
- I_CPL => I_CPL,
- I_CCF => I_CCF,
- I_SCF => I_SCF,
- I_RETN => I_RETN,
- I_BT => I_BT,
- I_BC => I_BC,
- I_BTR => I_BTR,
- I_RLD => I_RLD,
- I_RRD => I_RRD,
- I_INRC => I_INRC,
- SetDI => SetDI,
- SetEI => SetEI,
- IMode => IMode,
- Halt => Halt,
- NoRead => NoRead,
- Write => Write);
-
- alu : T80_ALU
- generic map(
- Mode => Mode,
- Flag_C => Flag_C,
- Flag_N => Flag_N,
- Flag_P => Flag_P,
- Flag_X => Flag_X,
- Flag_H => Flag_H,
- Flag_Y => Flag_Y,
- Flag_Z => Flag_Z,
- Flag_S => Flag_S)
- port map(
- Arith16 => Arith16_r,
- Z16 => Z16_r,
- ALU_Op => ALU_Op_r,
- IR => IR(5 downto 0),
- ISet => ISet,
- BusA => BusA,
- BusB => BusB,
- F_In => F,
- Q => ALU_Q,
- F_Out => F_Out);
-
- ClkEn <= CEN and not BusAck;
-
- T_Res <= '1' when TState = unsigned(TStates) else '0';
-
- NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
- ((Set_Addr_To = aXY) or
- (MCycle = "001" and IR = "11001011") or
- (MCycle = "001" and IR = "00110110")) else '0';
-
- Save_Mux <= BusB when ExchangeRp = '1' else
- DI_Reg when Save_ALU_r = '0' else
- ALU_Q;
-
- process (RESET_n, CLK_n)
- begin
- if RESET_n = '0' then
- PC <= (others => '0'); -- Program Counter
- A <= (others => '0');
- TmpAddr <= (others => '0');
- IR <= "00000000";
- ISet <= "00";
- XY_State <= "00";
- IStatus <= "00";
- MCycles <= "000";
- DO <= "00000000";
-
- ACC <= (others => '1');
- F <= (others => '1');
- Ap <= (others => '1');
- Fp <= (others => '1');
- I <= (others => '0');
- R <= (others => '0');
- SP <= (others => '1');
- Alternate <= '0';
-
- Read_To_Reg_r <= "00000";
- F <= (others => '1');
- Arith16_r <= '0';
- BTR_r <= '0';
- Z16_r <= '0';
- ALU_Op_r <= "0000";
- Save_ALU_r <= '0';
- PreserveC_r <= '0';
- XY_Ind <= '0';
-
- elsif CLK_n'event and CLK_n = '1' then
-
- if ClkEn = '1' then
-
- ALU_Op_r <= "0000";
- Save_ALU_r <= '0';
- Read_To_Reg_r <= "00000";
-
- MCycles <= MCycles_d;
-
- if IMode /= "11" then
- IStatus <= IMode;
- end if;
-
- Arith16_r <= Arith16;
- PreserveC_r <= PreserveC;
- if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
- Z16_r <= '1';
- else
- Z16_r <= '0';
- end if;
-
- if MCycle = "001" and TState(2) = '0' then
- -- MCycle = 1 and TState = 1, 2, or 3
-
- if TState = 2 and Wait_n = '1' then
- if Mode < 2 then
- A(7 downto 0) <= std_logic_vector(R);
- A(15 downto 8) <= I;
- R(6 downto 0) <= R(6 downto 0) + 1;
- end if;
-
- if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
- PC <= PC + 1;
- end if;
-
- if IntCycle = '1' and IStatus = "01" then
- IR <= "11111111";
- elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
- IR <= "00000000";
- else
- IR <= DInst;
- end if;
-
- ISet <= "00";
- if Prefix /= "00" then
- if Prefix = "11" then
- if IR(5) = '1' then
- XY_State <= "10";
- else
- XY_State <= "01";
- end if;
- else
- if Prefix = "10" then
- XY_State <= "00";
- XY_Ind <= '0';
- end if;
- ISet <= Prefix;
- end if;
- else
- XY_State <= "00";
- XY_Ind <= '0';
- end if;
- end if;
-
- else
- -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
- if MCycle = "110" then
- XY_Ind <= '1';
- if Prefix = "01" then
- ISet <= "01";
- end if;
- end if;
-
- if T_Res = '1' then
- BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
- if Jump = '1' then
- A(15 downto 8) <= DI_Reg;
- A(7 downto 0) <= TmpAddr(7 downto 0);
- PC(15 downto 8) <= unsigned(DI_Reg);
- PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
- elsif JumpXY = '1' then
- A <= RegBusC;
- PC <= unsigned(RegBusC);
- elsif Call = '1' or RstP = '1' then
- A <= TmpAddr;
- PC <= unsigned(TmpAddr);
- elsif MCycle = MCycles and NMICycle = '1' then
- A <= "0000000001100110";
- PC <= "0000000001100110";
- elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
- A(15 downto 8) <= I;
- A(7 downto 0) <= TmpAddr(7 downto 0);
- PC(15 downto 8) <= unsigned(I);
- PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
- else
- case Set_Addr_To is
- when aXY =>
- if XY_State = "00" then
- A <= RegBusC;
- else
- if NextIs_XY_Fetch = '1' then
- A <= std_logic_vector(PC);
- else
- A <= TmpAddr;
- end if;
- end if;
- when aIOA =>
- if Mode = 3 then
- -- Memory map I/O on GBZ80
- A(15 downto 8) <= (others => '1');
- elsif Mode = 2 then
- -- Duplicate I/O address on 8080
- A(15 downto 8) <= DI_Reg;
- else
- A(15 downto 8) <= ACC;
- end if;
- A(7 downto 0) <= DI_Reg;
- when aSP =>
- A <= std_logic_vector(SP);
- when aBC =>
- if Mode = 3 and IORQ_i = '1' then
- -- Memory map I/O on GBZ80
- A(15 downto 8) <= (others => '1');
- A(7 downto 0) <= RegBusC(7 downto 0);
- else
- A <= RegBusC;
- end if;
- when aDE =>
- A <= RegBusC;
- when aZI =>
- if Inc_WZ = '1' then
- A <= std_logic_vector(unsigned(TmpAddr) + 1);
- else
- A(15 downto 8) <= DI_Reg;
- A(7 downto 0) <= TmpAddr(7 downto 0);
- end if;
- when others =>
- A <= std_logic_vector(PC);
- end case;
- end if;
-
- Save_ALU_r <= Save_ALU;
- ALU_Op_r <= ALU_Op;
-
- if I_CPL = '1' then
- -- CPL
- ACC <= not ACC;
- F(Flag_Y) <= not ACC(5);
- F(Flag_H) <= '1';
- F(Flag_X) <= not ACC(3);
- F(Flag_N) <= '1';
- end if;
- if I_CCF = '1' then
- -- CCF
- F(Flag_C) <= not F(Flag_C);
- F(Flag_Y) <= ACC(5);
- F(Flag_H) <= F(Flag_C);
- F(Flag_X) <= ACC(3);
- F(Flag_N) <= '0';
- end if;
- if I_SCF = '1' then
- -- SCF
- F(Flag_C) <= '1';
- F(Flag_Y) <= ACC(5);
- F(Flag_H) <= '0';
- F(Flag_X) <= ACC(3);
- F(Flag_N) <= '0';
- end if;
- end if;
-
- if TState = 2 and Wait_n = '1' then
- if ISet = "01" and MCycle = "111" then
- IR <= DInst;
- end if;
- if JumpE = '1' then
- PC <= unsigned(signed(PC) + signed(DI_Reg));
- elsif Inc_PC = '1' then
- PC <= PC + 1;
- end if;
- if BTR_r = '1' then
- PC <= PC - 2;
- end if;
- if RstP = '1' then
- TmpAddr <= (others =>'0');
- TmpAddr(5 downto 3) <= IR(5 downto 3);
- end if;
- end if;
- if TState = 3 and MCycle = "110" then
- TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
- end if;
-
- if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
- if IncDec_16(2 downto 0) = "111" then
- if IncDec_16(3) = '1' then
- SP <= SP - 1;
- else
- SP <= SP + 1;
- end if;
- end if;
- end if;
-
- if LDSPHL = '1' then
- SP <= unsigned(RegBusC);
- end if;
- if ExchangeAF = '1' then
- Ap <= ACC;
- ACC <= Ap;
- Fp <= F;
- F <= Fp;
- end if;
- if ExchangeRS = '1' then
- Alternate <= not Alternate;
- end if;
- end if;
-
- if TState = 3 then
- if LDZ = '1' then
- TmpAddr(7 downto 0) <= DI_Reg;
- end if;
- if LDW = '1' then
- TmpAddr(15 downto 8) <= DI_Reg;
- end if;
-
- if Special_LD(2) = '1' then
- case Special_LD(1 downto 0) is
- when "00" =>
- ACC <= I;
- F(Flag_P) <= IntE_FF2;
- when "01" =>
- ACC <= std_logic_vector(R);
- F(Flag_P) <= IntE_FF2;
- when "10" =>
- I <= ACC;
- when others =>
- R <= unsigned(ACC);
- end case;
- end if;
- end if;
-
- if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
- if Mode = 3 then
- F(6) <= F_Out(6);
- F(5) <= F_Out(5);
- F(7) <= F_Out(7);
- if PreserveC_r = '0' then
- F(4) <= F_Out(4);
- end if;
- else
- F(7 downto 1) <= F_Out(7 downto 1);
- if PreserveC_r = '0' then
- F(Flag_C) <= F_Out(0);
- end if;
- end if;
- end if;
- if T_Res = '1' and I_INRC = '1' then
- F(Flag_H) <= '0';
- F(Flag_N) <= '0';
- if DI_Reg(7 downto 0) = "00000000" then
- F(Flag_Z) <= '1';
- else
- F(Flag_Z) <= '0';
- end if;
- F(Flag_S) <= DI_Reg(7);
- F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
- DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
- end if;
-
- if TState = 1 and Auto_Wait_t1 = '0' then
- DO <= BusB;
- if I_RLD = '1' then
- DO(3 downto 0) <= BusA(3 downto 0);
- DO(7 downto 4) <= BusB(3 downto 0);
- end if;
- if I_RRD = '1' then
- DO(3 downto 0) <= BusB(7 downto 4);
- DO(7 downto 4) <= BusA(3 downto 0);
- end if;
- end if;
-
- if T_Res = '1' then
- Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
- Read_To_Reg_r(4) <= Read_To_Reg;
- if Read_To_Acc = '1' then
- Read_To_Reg_r(3 downto 0) <= "0111";
- Read_To_Reg_r(4) <= '1';
- end if;
- end if;
-
- if TState = 1 and I_BT = '1' then
- F(Flag_X) <= ALU_Q(3);
- F(Flag_Y) <= ALU_Q(1);
- F(Flag_H) <= '0';
- F(Flag_N) <= '0';
- end if;
- if I_BC = '1' or I_BT = '1' then
- F(Flag_P) <= IncDecZ;
- end if;
-
- if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or
- (Save_ALU_r = '1' and ALU_OP_r /= "0111") then
- case Read_To_Reg_r is
- when "10111" =>
- ACC <= Save_Mux;
- when "10110" =>
- DO <= Save_Mux;
- when "11000" =>
- SP(7 downto 0) <= unsigned(Save_Mux);
- when "11001" =>
- SP(15 downto 8) <= unsigned(Save_Mux);
- when "11011" =>
- F <= Save_Mux;
- when others =>
- end case;
- end if;
-
- end if;
-
- end if;
-
- end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
- process (CLK_n)
- begin
- if CLK_n'event and CLK_n = '1' then
- if ClkEn = '1' then
- -- Bus A / Write
- RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
- if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
- RegAddrA_r <= XY_State(1) & "11";
- end if;
-
- -- Bus B
- RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
- if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
- RegAddrB_r <= XY_State(1) & "11";
- end if;
-
- -- Address from register
- RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
- -- Jump (HL), LD SP,HL
- if (JumpXY = '1' or LDSPHL = '1') then
- RegAddrC <= Alternate & "10";
- end if;
- if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
- RegAddrC <= XY_State(1) & "11";
- end if;
-
- if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
- IncDecZ <= F_Out(Flag_Z);
- end if;
- if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
- if ID16 = 0 then
- IncDecZ <= '0';
- else
- IncDecZ <= '1';
- end if;
- end if;
-
- RegBusA_r <= RegBusA;
- end if;
- end if;
- end process;
-
- RegAddrA <=
- -- 16 bit increment/decrement
- Alternate & IncDec_16(1 downto 0) when (TState = 2 or
- (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
- XY_State(1) & "11" when (TState = 2 or
- (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
- -- EX HL,DL
- Alternate & "10" when ExchangeDH = '1' and TState = 3 else
- Alternate & "01" when ExchangeDH = '1' and TState = 4 else
- -- Bus A / Write
- RegAddrA_r;
-
- RegAddrB <=
- -- EX HL,DL
- Alternate & "01" when ExchangeDH = '1' and TState = 3 else
- -- Bus B
- RegAddrB_r;
-
- ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
- signed(RegBusA) + 1;
-
- process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
- ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
- begin
- RegWEH <= '0';
- RegWEL <= '0';
- if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or
- (Save_ALU_r = '1' and ALU_OP_r /= "0111") then
- case Read_To_Reg_r is
- when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
- RegWEH <= not Read_To_Reg_r(0);
- RegWEL <= Read_To_Reg_r(0);
- when others =>
- end case;
- end if;
-
- if ExchangeDH = '1' and (TState = 3 or TState = 4) then
- RegWEH <= '1';
- RegWEL <= '1';
- end if;
-
- if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
- case IncDec_16(1 downto 0) is
- when "00" | "01" | "10" =>
- RegWEH <= '1';
- RegWEL <= '1';
- when others =>
- end case;
- end if;
- end process;
-
- process (Save_Mux, RegBusB, RegBusA_r, ID16,
- ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
- begin
- RegDIH <= Save_Mux;
- RegDIL <= Save_Mux;
-
- if ExchangeDH = '1' and TState = 3 then
- RegDIH <= RegBusB(15 downto 8);
- RegDIL <= RegBusB(7 downto 0);
- end if;
- if ExchangeDH = '1' and TState = 4 then
- RegDIH <= RegBusA_r(15 downto 8);
- RegDIL <= RegBusA_r(7 downto 0);
- end if;
-
- if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
- RegDIH <= std_logic_vector(ID16(15 downto 8));
- RegDIL <= std_logic_vector(ID16(7 downto 0));
- end if;
- end process;
-
- Regs : T80_Reg
- port map(
- Clk => CLK_n,
- CEN => ClkEn,
- WEH => RegWEH,
- WEL => RegWEL,
- AddrA => RegAddrA,
- AddrB => RegAddrB,
- AddrC => RegAddrC,
- DIH => RegDIH,
- DIL => RegDIL,
- DOAH => RegBusA(15 downto 8),
- DOAL => RegBusA(7 downto 0),
- DOBH => RegBusB(15 downto 8),
- DOBL => RegBusB(7 downto 0),
- DOCH => RegBusC(15 downto 8),
- DOCL => RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
- process (CLK_n)
- begin
- if CLK_n'event and CLK_n = '1' then
- if ClkEn = '1' then
- case Set_BusB_To is
- when "0111" =>
- BusB <= ACC;
- when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
- if Set_BusB_To(0) = '1' then
- BusB <= RegBusB(7 downto 0);
- else
- BusB <= RegBusB(15 downto 8);
- end if;
- when "0110" =>
- BusB <= DI_Reg;
- when "1000" =>
- BusB <= std_logic_vector(SP(7 downto 0));
- when "1001" =>
- BusB <= std_logic_vector(SP(15 downto 8));
- when "1010" =>
- BusB <= "00000001";
- when "1011" =>
- BusB <= F;
- when "1100" =>
- BusB <= std_logic_vector(PC(7 downto 0));
- when "1101" =>
- BusB <= std_logic_vector(PC(15 downto 8));
- when "1110" =>
- BusB <= "00000000";
- when others =>
- BusB <= "--------";
- end case;
-
- case Set_BusA_To is
- when "0111" =>
- BusA <= ACC;
- when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
- if Set_BusA_To(0) = '1' then
- BusA <= RegBusA(7 downto 0);
- else
- BusA <= RegBusA(15 downto 8);
- end if;
- when "0110" =>
- BusA <= DI_Reg;
- when "1000" =>
- BusA <= std_logic_vector(SP(7 downto 0));
- when "1001" =>
- BusA <= std_logic_vector(SP(15 downto 8));
- when "1010" =>
- BusA <= "00000000";
- when others =>
- BusB <= "--------";
- end case;
- end if;
- end if;
- end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
- process (RESET_n,CLK_n)
- begin
- if RESET_n = '0' then
- RFSH_n <= '1';
- elsif CLK_n'event and CLK_n = '1' then
- if CEN = '1' then
- if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then
- RFSH_n <= '0';
- else
- RFSH_n <= '1';
- end if;
- end if;
- end if;
- end process;
-
- MC <= std_logic_vector(MCycle);
- TS <= std_logic_vector(TState);
- DI_Reg <= DI;
- HALT_n <= not Halt_FF;
- BUSAK_n <= not BusAck;
- IntCycle_n <= not IntCycle;
- IntE <= IntE_FF1;
- IORQ <= IORQ_i;
- Stop <= I_DJNZ;
-
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
- process (RESET_n, CLK_n)
- variable OldNMI_n : std_logic;
- begin
- if RESET_n = '0' then
- BusReq_s <= '0';
- INT_s <= '0';
- NMI_s <= '0';
- OldNMI_n := '0';
- elsif CLK_n'event and CLK_n = '1' then
- if CEN = '1' then
- BusReq_s <= not BUSRQ_n;
- INT_s <= not INT_n;
- if NMICycle = '1' then
- NMI_s <= '0';
- elsif NMI_n = '0' and OldNMI_n = '1' then
- NMI_s <= '1';
- end if;
- OldNMI_n := NMI_n;
- end if;
- end if;
- end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
- process (RESET_n, CLK_n)
- begin
- if RESET_n = '0' then
- MCycle <= "001";
- TState <= "000";
- Pre_XY_F_M <= "000";
- Halt_FF <= '0';
- BusAck <= '0';
- NMICycle <= '0';
- IntCycle <= '0';
- IntE_FF1 <= '0';
- IntE_FF2 <= '0';
- No_BTR <= '0';
- Auto_Wait_t1 <= '0';
- Auto_Wait_t2 <= '0';
- M1_n <= '1';
- elsif CLK_n'event and CLK_n = '1' then
- if CEN = '1' then
- if T_Res = '1' then
- Auto_Wait_t1 <= '0';
- else
- Auto_Wait_t1 <= Auto_Wait or IORQ_i;
- end if;
- Auto_Wait_t2 <= Auto_Wait_t1;
- No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
- (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
- (I_BTR and (not IR(4) or F(Flag_Z)));
- if TState = 2 then
- if SetEI = '1' then
- IntE_FF1 <= '1';
- IntE_FF2 <= '1';
- end if;
- if I_RETN = '1' then
- IntE_FF1 <= IntE_FF2;
- end if;
- end if;
- if TState = 3 then
- if SetDI = '1' then
- IntE_FF1 <= '0';
- IntE_FF2 <= '0';
- end if;
- end if;
- if IntCycle = '1' or NMICycle = '1' then
- Halt_FF <= '0';
- end if;
- if MCycle = "001" and TState = 2 and Wait_n = '1' then
- M1_n <= '1';
- end if;
- if BusReq_s = '1' and BusAck = '1' then
- else
- BusAck <= '0';
- if TState = 2 and Wait_n = '0' then
- elsif T_Res = '1' then
- if Halt = '1' then
- Halt_FF <= '1';
- end if;
- if BusReq_s = '1' then
- BusAck <= '1';
- else
- TState <= "001";
- if NextIs_XY_Fetch = '1' then
- MCycle <= "110";
- Pre_XY_F_M <= MCycle;
- if IR = "00110110" and Mode = 0 then
- Pre_XY_F_M <= "010";
- end if;
- elsif (MCycle = "111") or
- (MCycle = "110" and Mode = 1 and ISet /= "01") then
- MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
- elsif (MCycle = MCycles) or
- No_BTR = '1' or
- (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
- M1_n <= '0';
- MCycle <= "001";
- IntCycle <= '0';
- NMICycle <= '0';
- if NMI_s = '1' and Prefix = "00" then
- NMICycle <= '1';
- IntE_FF1 <= '0';
- elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
- IntCycle <= '1';
- IntE_FF1 <= '0';
- IntE_FF2 <= '0';
- end if;
- else
- MCycle <= std_logic_vector(unsigned(MCycle) + 1);
- end if;
- end if;
- else
- if (Auto_Wait = '1' and Auto_Wait_t2 = '0') nor
- (IOWait = 1 and IORQ_i = '1' and Auto_Wait_t1 = '0') then
- TState <= TState + 1;
- end if;
- end if;
- end if;
- if TState = 0 then
- M1_n <= '0';
- end if;
- end if;
- end if;
- end process;
-
- process (IntCycle, NMICycle, MCycle)
- begin
- Auto_Wait <= '0';
- if IntCycle = '1' or NMICycle = '1' then
- if MCycle = "001" then
- Auto_Wait <= '1';
- end if;
- end if;
- end process;
-
-end;
diff --git a/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/T80/T80_ALU.vhd
deleted file mode 100644
index 86fddce7..00000000
--- a/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/T80/T80_ALU.vhd
+++ /dev/null
@@ -1,351 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
--- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
--- 0238 : Fixed zero flag for 16 bit SBC and ADC
---
--- 0240 : Added GB operations
---
--- 0242 : Cleanup
---
--- 0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
- generic(
- Mode : integer := 0;
- Flag_C : integer := 0;
- Flag_N : integer := 1;
- Flag_P : integer := 2;
- Flag_X : integer := 3;
- Flag_H : integer := 4;
- Flag_Y : integer := 5;
- Flag_Z : integer := 6;
- Flag_S : integer := 7
- );
- port(
- Arith16 : in std_logic;
- Z16 : in std_logic;
- ALU_Op : in std_logic_vector(3 downto 0);
- IR : in std_logic_vector(5 downto 0);
- ISet : in std_logic_vector(1 downto 0);
- BusA : in std_logic_vector(7 downto 0);
- BusB : in std_logic_vector(7 downto 0);
- F_In : in std_logic_vector(7 downto 0);
- Q : out std_logic_vector(7 downto 0);
- F_Out : out std_logic_vector(7 downto 0)
- );
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
- procedure AddSub(A : std_logic_vector;
- B : std_logic_vector;
- Sub : std_logic;
- Carry_In : std_logic;
- signal Res : out std_logic_vector;
- signal Carry : out std_logic) is
- variable B_i : unsigned(A'length - 1 downto 0);
- variable Res_i : unsigned(A'length + 1 downto 0);
- begin
- if Sub = '1' then
- B_i := not unsigned(B);
- else
- B_i := unsigned(B);
- end if;
- Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
- Carry <= Res_i(A'length + 1);
- Res <= std_logic_vector(Res_i(A'length downto 1));
- end;
-
- -- AddSub variables (temporary signals)
- signal UseCarry : std_logic;
- signal Carry7_v : std_logic;
- signal Overflow_v : std_logic;
- signal HalfCarry_v : std_logic;
- signal Carry_v : std_logic;
- signal Q_v : std_logic_vector(7 downto 0);
-
- signal BitMask : std_logic_vector(7 downto 0);
-
-begin
-
- with IR(5 downto 3) select BitMask <= "00000001" when "000",
- "00000010" when "001",
- "00000100" when "010",
- "00001000" when "011",
- "00010000" when "100",
- "00100000" when "101",
- "01000000" when "110",
- "10000000" when others;
-
- UseCarry <= not ALU_Op(2) and ALU_Op(0);
- AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
- AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
- AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
- OverFlow_v <= Carry_v xor Carry7_v;
-
- process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
- variable Q_t : std_logic_vector(7 downto 0);
- variable DAA_Q : unsigned(8 downto 0);
- begin
- Q_t := "--------";
- F_Out <= F_In;
- DAA_Q := "---------";
- case ALU_Op is
- when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
- F_Out(Flag_N) <= '0';
- F_Out(Flag_C) <= '0';
- case ALU_OP(2 downto 0) is
- when "000" | "001" => -- ADD, ADC
- Q_t := Q_v;
- F_Out(Flag_C) <= Carry_v;
- F_Out(Flag_H) <= HalfCarry_v;
- F_Out(Flag_P) <= OverFlow_v;
- when "010" | "011" | "111" => -- SUB, SBC, CP
- Q_t := Q_v;
- F_Out(Flag_N) <= '1';
- F_Out(Flag_C) <= not Carry_v;
- F_Out(Flag_H) <= not HalfCarry_v;
- F_Out(Flag_P) <= OverFlow_v;
- when "100" => -- AND
- Q_t(7 downto 0) := BusA and BusB;
- F_Out(Flag_H) <= '1';
- when "101" => -- XOR
- Q_t(7 downto 0) := BusA xor BusB;
- F_Out(Flag_H) <= '0';
- when others => -- OR "110"
- Q_t(7 downto 0) := BusA or BusB;
- F_Out(Flag_H) <= '0';
- end case;
- if ALU_Op(2 downto 0) = "111" then -- CP
- F_Out(Flag_X) <= BusB(3);
- F_Out(Flag_Y) <= BusB(5);
- else
- F_Out(Flag_X) <= Q_t(3);
- F_Out(Flag_Y) <= Q_t(5);
- end if;
- if Q_t(7 downto 0) = "00000000" then
- F_Out(Flag_Z) <= '1';
- if Z16 = '1' then
- F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
- end if;
- else
- F_Out(Flag_Z) <= '0';
- end if;
- F_Out(Flag_S) <= Q_t(7);
- case ALU_Op(2 downto 0) is
- when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
- when others =>
- F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
- Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
- end case;
- if Arith16 = '1' then
- F_Out(Flag_S) <= F_In(Flag_S);
- F_Out(Flag_Z) <= F_In(Flag_Z);
- F_Out(Flag_P) <= F_In(Flag_P);
- end if;
- when "1100" =>
- -- DAA
- F_Out(Flag_H) <= F_In(Flag_H);
- F_Out(Flag_C) <= F_In(Flag_C);
- DAA_Q(7 downto 0) := unsigned(BusA);
- DAA_Q(8) := '0';
- if F_In(Flag_N) = '0' then
- -- After addition
- -- Alow > 9 or H = 1
- if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
- if (DAA_Q(3 downto 0) > 9) then
- F_Out(Flag_H) <= '1';
- else
- F_Out(Flag_H) <= '0';
- end if;
- DAA_Q := DAA_Q + 6;
- end if;
- -- new Ahigh > 9 or C = 1
- if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
- DAA_Q := DAA_Q + 96; -- 0x60
- end if;
- else
- -- After subtraction
- if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
- if DAA_Q(3 downto 0) > 5 then
- F_Out(Flag_H) <= '0';
- end if;
- DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
- end if;
- if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
- DAA_Q := DAA_Q - 352; -- 0x160
- end if;
- end if;
- F_Out(Flag_X) <= DAA_Q(3);
- F_Out(Flag_Y) <= DAA_Q(5);
- F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
- Q_t := std_logic_vector(DAA_Q(7 downto 0));
- if DAA_Q(7 downto 0) = "00000000" then
- F_Out(Flag_Z) <= '1';
- else
- F_Out(Flag_Z) <= '0';
- end if;
- F_Out(Flag_S) <= DAA_Q(7);
- F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
- DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
- when "1101" | "1110" =>
- -- RLD, RRD
- Q_t(7 downto 4) := BusA(7 downto 4);
- if ALU_Op(0) = '1' then
- Q_t(3 downto 0) := BusB(7 downto 4);
- else
- Q_t(3 downto 0) := BusB(3 downto 0);
- end if;
- F_Out(Flag_H) <= '0';
- F_Out(Flag_N) <= '0';
- F_Out(Flag_X) <= Q_t(3);
- F_Out(Flag_Y) <= Q_t(5);
- if Q_t(7 downto 0) = "00000000" then
- F_Out(Flag_Z) <= '1';
- else
- F_Out(Flag_Z) <= '0';
- end if;
- F_Out(Flag_S) <= Q_t(7);
- F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
- Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
- when "1001" =>
- -- BIT
- Q_t(7 downto 0) := BusB and BitMask;
- F_Out(Flag_S) <= Q_t(7);
- if Q_t(7 downto 0) = "00000000" then
- F_Out(Flag_Z) <= '1';
- F_Out(Flag_P) <= '1';
- else
- F_Out(Flag_Z) <= '0';
- F_Out(Flag_P) <= '0';
- end if;
- F_Out(Flag_H) <= '1';
- F_Out(Flag_N) <= '0';
- F_Out(Flag_X) <= '0';
- F_Out(Flag_Y) <= '0';
- if IR(2 downto 0) /= "110" then
- F_Out(Flag_X) <= BusB(3);
- F_Out(Flag_Y) <= BusB(5);
- end if;
- when "1010" =>
- -- SET
- Q_t(7 downto 0) := BusB or BitMask;
- when "1011" =>
- -- RES
- Q_t(7 downto 0) := BusB and not BitMask;
- when "1000" =>
- -- ROT
- case IR(5 downto 3) is
- when "000" => -- RLC
- Q_t(7 downto 1) := BusA(6 downto 0);
- Q_t(0) := BusA(7);
- F_Out(Flag_C) <= BusA(7);
- when "010" => -- RL
- Q_t(7 downto 1) := BusA(6 downto 0);
- Q_t(0) := F_In(Flag_C);
- F_Out(Flag_C) <= BusA(7);
- when "001" => -- RRC
- Q_t(6 downto 0) := BusA(7 downto 1);
- Q_t(7) := BusA(0);
- F_Out(Flag_C) <= BusA(0);
- when "011" => -- RR
- Q_t(6 downto 0) := BusA(7 downto 1);
- Q_t(7) := F_In(Flag_C);
- F_Out(Flag_C) <= BusA(0);
- when "100" => -- SLA
- Q_t(7 downto 1) := BusA(6 downto 0);
- Q_t(0) := '0';
- F_Out(Flag_C) <= BusA(7);
- when "110" => -- SLL (Undocumented) / SWAP
- if Mode = 3 then
- Q_t(7 downto 4) := BusA(3 downto 0);
- Q_t(3 downto 0) := BusA(7 downto 4);
- F_Out(Flag_C) <= '0';
- else
- Q_t(7 downto 1) := BusA(6 downto 0);
- Q_t(0) := '1';
- F_Out(Flag_C) <= BusA(7);
- end if;
- when "101" => -- SRA
- Q_t(6 downto 0) := BusA(7 downto 1);
- Q_t(7) := BusA(7);
- F_Out(Flag_C) <= BusA(0);
- when others => -- SRL
- Q_t(6 downto 0) := BusA(7 downto 1);
- Q_t(7) := '0';
- F_Out(Flag_C) <= BusA(0);
- end case;
- F_Out(Flag_H) <= '0';
- F_Out(Flag_N) <= '0';
- F_Out(Flag_X) <= Q_t(3);
- F_Out(Flag_Y) <= Q_t(5);
- F_Out(Flag_S) <= Q_t(7);
- if Q_t(7 downto 0) = "00000000" then
- F_Out(Flag_Z) <= '1';
- else
- F_Out(Flag_Z) <= '0';
- end if;
- F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
- Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
- if ISet = "00" then
- F_Out(Flag_P) <= F_In(Flag_P);
- F_Out(Flag_S) <= F_In(Flag_S);
- F_Out(Flag_Z) <= F_In(Flag_Z);
- end if;
- when others =>
- null;
- end case;
- Q <= Q_t;
- end process;
-
-end;
diff --git a/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/T80/T80_MCode.vhd
deleted file mode 100644
index 4cc30f35..00000000
--- a/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/T80/T80_MCode.vhd
+++ /dev/null
@@ -1,1934 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
--- 0208 : First complete release
---
--- 0211 : Fixed IM 1
---
--- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
--- 0235 : Added IM 2 fix by Mike Johnson
---
--- 0238 : Added NoRead signal
---
--- 0238b: Fixed instruction timing for POP and DJNZ
---
--- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
---
--- 0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_MCode is
- generic(
- Mode : integer := 0;
- Flag_C : integer := 0;
- Flag_N : integer := 1;
- Flag_P : integer := 2;
- Flag_X : integer := 3;
- Flag_H : integer := 4;
- Flag_Y : integer := 5;
- Flag_Z : integer := 6;
- Flag_S : integer := 7
- );
- port(
- IR : in std_logic_vector(7 downto 0);
- ISet : in std_logic_vector(1 downto 0);
- MCycle : in std_logic_vector(2 downto 0);
- F : in std_logic_vector(7 downto 0);
- NMICycle : in std_logic;
- IntCycle : in std_logic;
- MCycles : out std_logic_vector(2 downto 0);
- TStates : out std_logic_vector(2 downto 0);
- Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
- Inc_PC : out std_logic;
- Inc_WZ : out std_logic;
- IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
- Read_To_Reg : out std_logic;
- Read_To_Acc : out std_logic;
- Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
- Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
- ALU_Op : out std_logic_vector(3 downto 0);
- -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
- Save_ALU : out std_logic;
- PreserveC : out std_logic;
- Arith16 : out std_logic;
- Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
- IORQ : out std_logic;
- Jump : out std_logic;
- JumpE : out std_logic;
- JumpXY : out std_logic;
- Call : out std_logic;
- RstP : out std_logic;
- LDZ : out std_logic;
- LDW : out std_logic;
- LDSPHL : out std_logic;
- Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
- ExchangeDH : out std_logic;
- ExchangeRp : out std_logic;
- ExchangeAF : out std_logic;
- ExchangeRS : out std_logic;
- I_DJNZ : out std_logic;
- I_CPL : out std_logic;
- I_CCF : out std_logic;
- I_SCF : out std_logic;
- I_RETN : out std_logic;
- I_BT : out std_logic;
- I_BC : out std_logic;
- I_BTR : out std_logic;
- I_RLD : out std_logic;
- I_RRD : out std_logic;
- I_INRC : out std_logic;
- SetDI : out std_logic;
- SetEI : out std_logic;
- IMode : out std_logic_vector(1 downto 0);
- Halt : out std_logic;
- NoRead : out std_logic;
- Write : out std_logic
- );
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
- constant aNone : std_logic_vector(2 downto 0) := "111";
- constant aBC : std_logic_vector(2 downto 0) := "000";
- constant aDE : std_logic_vector(2 downto 0) := "001";
- constant aXY : std_logic_vector(2 downto 0) := "010";
- constant aIOA : std_logic_vector(2 downto 0) := "100";
- constant aSP : std_logic_vector(2 downto 0) := "101";
- constant aZI : std_logic_vector(2 downto 0) := "110";
--- constant aNone : std_logic_vector(2 downto 0) := "000";
--- constant aXY : std_logic_vector(2 downto 0) := "001";
--- constant aIOA : std_logic_vector(2 downto 0) := "010";
--- constant aSP : std_logic_vector(2 downto 0) := "011";
--- constant aBC : std_logic_vector(2 downto 0) := "100";
--- constant aDE : std_logic_vector(2 downto 0) := "101";
--- constant aZI : std_logic_vector(2 downto 0) := "110";
-
- function is_cc_true(
- F : std_logic_vector(7 downto 0);
- cc : bit_vector(2 downto 0)
- ) return boolean is
- begin
- if Mode = 3 then
- case cc is
- when "000" => return F(7) = '0'; -- NZ
- when "001" => return F(7) = '1'; -- Z
- when "010" => return F(4) = '0'; -- NC
- when "011" => return F(4) = '1'; -- C
- when "100" => return false;
- when "101" => return false;
- when "110" => return false;
- when "111" => return false;
- end case;
- else
- case cc is
- when "000" => return F(6) = '0'; -- NZ
- when "001" => return F(6) = '1'; -- Z
- when "010" => return F(0) = '0'; -- NC
- when "011" => return F(0) = '1'; -- C
- when "100" => return F(2) = '0'; -- PO
- when "101" => return F(2) = '1'; -- PE
- when "110" => return F(7) = '0'; -- P
- when "111" => return F(7) = '1'; -- M
- end case;
- end if;
- end;
-
-begin
-
- process (IR, ISet, MCycle, F, NMICycle, IntCycle)
- variable DDD : std_logic_vector(2 downto 0);
- variable SSS : std_logic_vector(2 downto 0);
- variable DPair : std_logic_vector(1 downto 0);
- variable IRB : bit_vector(7 downto 0);
- begin
- DDD := IR(5 downto 3);
- SSS := IR(2 downto 0);
- DPair := IR(5 downto 4);
- IRB := to_bitvector(IR);
-
- MCycles <= "001";
- if MCycle = "001" then
- TStates <= "100";
- else
- TStates <= "011";
- end if;
- Prefix <= "00";
- Inc_PC <= '0';
- Inc_WZ <= '0';
- IncDec_16 <= "0000";
- Read_To_Acc <= '0';
- Read_To_Reg <= '0';
- Set_BusB_To <= "0000";
- Set_BusA_To <= "0000";
- ALU_Op <= "0" & IR(5 downto 3);
- Save_ALU <= '0';
- PreserveC <= '0';
- Arith16 <= '0';
- IORQ <= '0';
- Set_Addr_To <= aNone;
- Jump <= '0';
- JumpE <= '0';
- JumpXY <= '0';
- Call <= '0';
- RstP <= '0';
- LDZ <= '0';
- LDW <= '0';
- LDSPHL <= '0';
- Special_LD <= "000";
- ExchangeDH <= '0';
- ExchangeRp <= '0';
- ExchangeAF <= '0';
- ExchangeRS <= '0';
- I_DJNZ <= '0';
- I_CPL <= '0';
- I_CCF <= '0';
- I_SCF <= '0';
- I_RETN <= '0';
- I_BT <= '0';
- I_BC <= '0';
- I_BTR <= '0';
- I_RLD <= '0';
- I_RRD <= '0';
- I_INRC <= '0';
- SetDI <= '0';
- SetEI <= '0';
- IMode <= "11";
- Halt <= '0';
- NoRead <= '0';
- Write <= '0';
-
- case ISet is
- when "00" =>
-
-------------------------------------------------------------------------------
---
--- Unprefixed instructions
---
-------------------------------------------------------------------------------
-
- case IRB is
--- 8 BIT LOAD GROUP
- when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
- |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
- |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
- |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
- |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
- |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
- |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
- -- LD r,r'
- Set_BusB_To(2 downto 0) <= SSS;
- ExchangeRp <= '1';
- Set_BusA_To(2 downto 0) <= DDD;
- Read_To_Reg <= '1';
- when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
- -- LD r,n
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- Set_BusA_To(2 downto 0) <= DDD;
- Read_To_Reg <= '1';
- when others => null;
- end case;
- when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
- -- LD r,(HL)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- when 2 =>
- Set_BusA_To(2 downto 0) <= DDD;
- Read_To_Reg <= '1';
- when others => null;
- end case;
- when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
- -- LD (HL),r
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- Set_BusB_To(2 downto 0) <= SSS;
- Set_BusB_To(3) <= '0';
- when 2 =>
- Write <= '1';
- when others => null;
- end case;
- when "00110110" =>
- -- LD (HL),n
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- Set_Addr_To <= aXY;
- Set_BusB_To(2 downto 0) <= SSS;
- Set_BusB_To(3) <= '0';
- when 3 =>
- Write <= '1';
- when others => null;
- end case;
- when "00001010" =>
- -- LD A,(BC)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aBC;
- when 2 =>
- Read_To_Acc <= '1';
- when others => null;
- end case;
- when "00011010" =>
- -- LD A,(DE)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aDE;
- when 2 =>
- Read_To_Acc <= '1';
- when others => null;
- end case;
- when "00111010" =>
- if Mode = 3 then
- -- LDD A,(HL)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- when 2 =>
- Read_To_Acc <= '1';
- IncDec_16 <= "1110";
- when others => null;
- end case;
- else
- -- LD A,(nn)
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- when 4 =>
- Read_To_Acc <= '1';
- when others => null;
- end case;
- end if;
- when "00000010" =>
- -- LD (BC),A
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aBC;
- Set_BusB_To <= "0111";
- when 2 =>
- Write <= '1';
- when others => null;
- end case;
- when "00010010" =>
- -- LD (DE),A
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aDE;
- Set_BusB_To <= "0111";
- when 2 =>
- Write <= '1';
- when others => null;
- end case;
- when "00110010" =>
- if Mode = 3 then
- -- LDD (HL),A
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- Set_BusB_To <= "0111";
- when 2 =>
- Write <= '1';
- IncDec_16 <= "1110";
- when others => null;
- end case;
- else
- -- LD (nn),A
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- Set_BusB_To <= "0111";
- when 4 =>
- Write <= '1';
- when others => null;
- end case;
- end if;
-
--- 16 BIT LOAD GROUP
- when "00000001"|"00010001"|"00100001"|"00110001" =>
- -- LD dd,nn
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- Read_To_Reg <= '1';
- if DPAIR = "11" then
- Set_BusA_To(3 downto 0) <= "1000";
- else
- Set_BusA_To(2 downto 1) <= DPAIR;
- Set_BusA_To(0) <= '1';
- end if;
- when 3 =>
- Inc_PC <= '1';
- Read_To_Reg <= '1';
- if DPAIR = "11" then
- Set_BusA_To(3 downto 0) <= "1001";
- else
- Set_BusA_To(2 downto 1) <= DPAIR;
- Set_BusA_To(0) <= '0';
- end if;
- when others => null;
- end case;
- when "00101010" =>
- if Mode = 3 then
- -- LDI A,(HL)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- when 2 =>
- Read_To_Acc <= '1';
- IncDec_16 <= "0110";
- when others => null;
- end case;
- else
- -- LD HL,(nn)
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- LDW <= '1';
- when 4 =>
- Set_BusA_To(2 downto 0) <= "101"; -- L
- Read_To_Reg <= '1';
- Inc_WZ <= '1';
- Set_Addr_To <= aZI;
- when 5 =>
- Set_BusA_To(2 downto 0) <= "100"; -- H
- Read_To_Reg <= '1';
- when others => null;
- end case;
- end if;
- when "00100010" =>
- if Mode = 3 then
- -- LDI (HL),A
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- Set_BusB_To <= "0111";
- when 2 =>
- Write <= '1';
- IncDec_16 <= "0110";
- when others => null;
- end case;
- else
- -- LD (nn),HL
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- LDW <= '1';
- Set_BusB_To <= "0101"; -- L
- when 4 =>
- Inc_WZ <= '1';
- Set_Addr_To <= aZI;
- Write <= '1';
- Set_BusB_To <= "0100"; -- H
- when 5 =>
- Write <= '1';
- when others => null;
- end case;
- end if;
- when "11111001" =>
- -- LD SP,HL
- TStates <= "110";
- LDSPHL <= '1';
- when "11000101"|"11010101"|"11100101"|"11110101" =>
- -- PUSH qq
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- TStates <= "101";
- IncDec_16 <= "1111";
- Set_Addr_TO <= aSP;
- if DPAIR = "11" then
- Set_BusB_To <= "0111";
- else
- Set_BusB_To(2 downto 1) <= DPAIR;
- Set_BusB_To(0) <= '0';
- Set_BusB_To(3) <= '0';
- end if;
- when 2 =>
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- if DPAIR = "11" then
- Set_BusB_To <= "1011";
- else
- Set_BusB_To(2 downto 1) <= DPAIR;
- Set_BusB_To(0) <= '1';
- Set_BusB_To(3) <= '0';
- end if;
- Write <= '1';
- when 3 =>
- Write <= '1';
- when others => null;
- end case;
- when "11000001"|"11010001"|"11100001"|"11110001" =>
- -- POP qq
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aSP;
- when 2 =>
- IncDec_16 <= "0111";
- Set_Addr_To <= aSP;
- Read_To_Reg <= '1';
- if DPAIR = "11" then
- Set_BusA_To(3 downto 0) <= "1011";
- else
- Set_BusA_To(2 downto 1) <= DPAIR;
- Set_BusA_To(0) <= '1';
- end if;
- when 3 =>
- IncDec_16 <= "0111";
- Read_To_Reg <= '1';
- if DPAIR = "11" then
- Set_BusA_To(3 downto 0) <= "0111";
- else
- Set_BusA_To(2 downto 1) <= DPAIR;
- Set_BusA_To(0) <= '0';
- end if;
- when others => null;
- end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
- when "11101011" =>
- if Mode /= 3 then
- -- EX DE,HL
- ExchangeDH <= '1';
- end if;
- when "00001000" =>
- if Mode = 3 then
- -- LD (nn),SP
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- LDW <= '1';
- Set_BusB_To <= "1000";
- when 4 =>
- Inc_WZ <= '1';
- Set_Addr_To <= aZI;
- Write <= '1';
- Set_BusB_To <= "1001";
- when 5 =>
- Write <= '1';
- when others => null;
- end case;
- elsif Mode < 2 then
- -- EX AF,AF'
- ExchangeAF <= '1';
- end if;
- when "11011001" =>
- if Mode = 3 then
- -- RETI
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_TO <= aSP;
- when 2 =>
- IncDec_16 <= "0111";
- Set_Addr_To <= aSP;
- LDZ <= '1';
- when 3 =>
- Jump <= '1';
- IncDec_16 <= "0111";
- I_RETN <= '1';
- SetEI <= '1';
- when others => null;
- end case;
- elsif Mode < 2 then
- -- EXX
- ExchangeRS <= '1';
- end if;
- when "11100011" =>
- if Mode /= 3 then
- -- EX (SP),HL
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aSP;
- when 2 =>
- Read_To_Reg <= '1';
- Set_BusA_To <= "0101";
- Set_BusB_To <= "0101";
- Set_Addr_To <= aSP;
- when 3 =>
- IncDec_16 <= "0111";
- Set_Addr_To <= aSP;
- TStates <= "100";
- Write <= '1';
- when 4 =>
- Read_To_Reg <= '1';
- Set_BusA_To <= "0100";
- Set_BusB_To <= "0100";
- Set_Addr_To <= aSP;
- when 5 =>
- IncDec_16 <= "1111";
- TStates <= "101";
- Write <= '1';
- when others => null;
- end case;
- end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
- when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
- |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
- |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
- |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
- |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
- |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
- |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
- |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
- -- ADD A,r
- -- ADC A,r
- -- SUB A,r
- -- SBC A,r
- -- AND A,r
- -- OR A,r
- -- XOR A,r
- -- CP A,r
- Set_BusB_To(2 downto 0) <= SSS;
- Set_BusA_To(2 downto 0) <= "111";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
- -- ADD A,(HL)
- -- ADC A,(HL)
- -- SUB A,(HL)
- -- SBC A,(HL)
- -- AND A,(HL)
- -- OR A,(HL)
- -- XOR A,(HL)
- -- CP A,(HL)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- when 2 =>
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_BusB_To(2 downto 0) <= SSS;
- Set_BusA_To(2 downto 0) <= "111";
- when others => null;
- end case;
- when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
- -- ADD A,n
- -- ADC A,n
- -- SUB A,n
- -- SBC A,n
- -- AND A,n
- -- OR A,n
- -- XOR A,n
- -- CP A,n
- MCycles <= "010";
- if MCycle = "010" then
- Inc_PC <= '1';
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_BusB_To(2 downto 0) <= SSS;
- Set_BusA_To(2 downto 0) <= "111";
- end if;
- when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
- -- INC r
- Set_BusB_To <= "1010";
- Set_BusA_To(2 downto 0) <= DDD;
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- PreserveC <= '1';
- ALU_Op <= "0000";
- when "00110100" =>
- -- INC (HL)
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- when 2 =>
- TStates <= "100";
- Set_Addr_To <= aXY;
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- PreserveC <= '1';
- ALU_Op <= "0000";
- Set_BusB_To <= "1010";
- Set_BusA_To(2 downto 0) <= DDD;
- when 3 =>
- Write <= '1';
- when others => null;
- end case;
- when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
- -- DEC r
- Set_BusB_To <= "1010";
- Set_BusA_To(2 downto 0) <= DDD;
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- PreserveC <= '1';
- ALU_Op <= "0010";
- when "00110101" =>
- -- DEC (HL)
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- when 2 =>
- TStates <= "100";
- Set_Addr_To <= aXY;
- ALU_Op <= "0010";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- PreserveC <= '1';
- Set_BusB_To <= "1010";
- Set_BusA_To(2 downto 0) <= DDD;
- when 3 =>
- Write <= '1';
- when others => null;
- end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
- when "00100111" =>
- -- DAA
- Set_BusA_To(2 downto 0) <= "111";
- Read_To_Reg <= '1';
- ALU_Op <= "1100";
- Save_ALU <= '1';
- when "00101111" =>
- -- CPL
- I_CPL <= '1';
- when "00111111" =>
- -- CCF
- I_CCF <= '1';
- when "00110111" =>
- -- SCF
- I_SCF <= '1';
- when "00000000" =>
- if NMICycle = '1' then
- -- NMI
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- TStates <= "101";
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- Set_BusB_To <= "1101";
- when 2 =>
- TStates <= "100";
- Write <= '1';
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- Set_BusB_To <= "1100";
- when 3 =>
- TStates <= "100";
- Write <= '1';
- when others => null;
- end case;
- elsif IntCycle = '1' then
- -- INT (IM 2)
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- LDZ <= '1';
- TStates <= "101";
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- Set_BusB_To <= "1101";
- when 2 =>
- TStates <= "100";
- Write <= '1';
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- Set_BusB_To <= "1100";
- when 3 =>
- TStates <= "100";
- Write <= '1';
- when 4 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 5 =>
- Jump <= '1';
- when others => null;
- end case;
- else
- -- NOP
- end if;
- when "01110110" =>
- -- HALT
- Halt <= '1';
- when "11110011" =>
- -- DI
- SetDI <= '1';
- when "11111011" =>
- -- EI
- SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
- when "00001001"|"00011001"|"00101001"|"00111001" =>
- -- ADD HL,ss
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- NoRead <= '1';
- ALU_Op <= "0000";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_BusA_To(2 downto 0) <= "101";
- case to_integer(unsigned(IR(5 downto 4))) is
- when 0|1|2 =>
- Set_BusB_To(2 downto 1) <= IR(5 downto 4);
- Set_BusB_To(0) <= '1';
- when others =>
- Set_BusB_To <= "1000";
- end case;
- TStates <= "100";
- Arith16 <= '1';
- when 3 =>
- NoRead <= '1';
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- ALU_Op <= "0001";
- Set_BusA_To(2 downto 0) <= "100";
- case to_integer(unsigned(IR(5 downto 4))) is
- when 0|1|2 =>
- Set_BusB_To(2 downto 1) <= IR(5 downto 4);
- when others =>
- Set_BusB_To <= "1001";
- end case;
- Arith16 <= '1';
- when others =>
- end case;
- when "00000011"|"00010011"|"00100011"|"00110011" =>
- -- INC ss
- TStates <= "110";
- IncDec_16(3 downto 2) <= "01";
- IncDec_16(1 downto 0) <= DPair;
- when "00001011"|"00011011"|"00101011"|"00111011" =>
- -- DEC ss
- TStates <= "110";
- IncDec_16(3 downto 2) <= "11";
- IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
- when "00000111"
- -- RLCA
- |"00010111"
- -- RLA
- |"00001111"
- -- RRCA
- |"00011111" =>
- -- RRA
- Set_BusA_To(2 downto 0) <= "111";
- ALU_Op <= "1000";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
-
--- JUMP GROUP
- when "11000011" =>
- -- JP nn
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Inc_PC <= '1';
- Jump <= '1';
- when others => null;
- end case;
- when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
- if IR(5) = '1' and Mode = 3 then
- case IRB(4 downto 3) is
- when "00" =>
- -- LD ($FF00+C),A
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aBC;
- Set_BusB_To <= "0111";
- when 2 =>
- Write <= '1';
- IORQ <= '1';
- when others =>
- end case;
- when "01" =>
- -- LD (nn),A
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- Set_BusB_To <= "0111";
- when 4 =>
- Write <= '1';
- when others => null;
- end case;
- when "10" =>
- -- LD A,($FF00+C)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aBC;
- when 2 =>
- Read_To_Acc <= '1';
- IORQ <= '1';
- when others =>
- end case;
- when "11" =>
- -- LD A,(nn)
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- when 4 =>
- Read_To_Acc <= '1';
- when others => null;
- end case;
- end case;
- else
- -- JP cc,nn
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Inc_PC <= '1';
- if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
- Jump <= '1';
- end if;
- when others => null;
- end case;
- end if;
- when "00011000" =>
- if Mode /= 2 then
- -- JR e
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- when 3 =>
- NoRead <= '1';
- JumpE <= '1';
- TStates <= "101";
- when others => null;
- end case;
- end if;
- when "00111000" =>
- if Mode /= 2 then
- -- JR C,e
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- if F(Flag_C) = '0' then
- MCycles <= "010";
- end if;
- when 3 =>
- NoRead <= '1';
- JumpE <= '1';
- TStates <= "101";
- when others => null;
- end case;
- end if;
- when "00110000" =>
- if Mode /= 2 then
- -- JR NC,e
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- if F(Flag_C) = '1' then
- MCycles <= "010";
- end if;
- when 3 =>
- NoRead <= '1';
- JumpE <= '1';
- TStates <= "101";
- when others => null;
- end case;
- end if;
- when "00101000" =>
- if Mode /= 2 then
- -- JR Z,e
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- if F(Flag_Z) = '0' then
- MCycles <= "010";
- end if;
- when 3 =>
- NoRead <= '1';
- JumpE <= '1';
- TStates <= "101";
- when others => null;
- end case;
- end if;
- when "00100000" =>
- if Mode /= 2 then
- -- JR NZ,e
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- if F(Flag_Z) = '1' then
- MCycles <= "010";
- end if;
- when 3 =>
- NoRead <= '1';
- JumpE <= '1';
- TStates <= "101";
- when others => null;
- end case;
- end if;
- when "11101001" =>
- -- JP (HL)
- JumpXY <= '1';
- when "00010000" =>
- if Mode = 3 then
- I_DJNZ <= '1';
- elsif Mode < 2 then
- -- DJNZ,e
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- TStates <= "101";
- I_DJNZ <= '1';
- Set_BusB_To <= "1010";
- Set_BusA_To(2 downto 0) <= "000";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- ALU_Op <= "0010";
- when 2 =>
- I_DJNZ <= '1';
- Inc_PC <= '1';
- when 3 =>
- NoRead <= '1';
- JumpE <= '1';
- TStates <= "101";
- when others => null;
- end case;
- end if;
-
--- CALL AND RETURN GROUP
- when "11001101" =>
- -- CALL nn
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- IncDec_16 <= "1111";
- Inc_PC <= '1';
- TStates <= "100";
- Set_Addr_To <= aSP;
- LDW <= '1';
- Set_BusB_To <= "1101";
- when 4 =>
- Write <= '1';
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- Set_BusB_To <= "1100";
- when 5 =>
- Write <= '1';
- Call <= '1';
- when others => null;
- end case;
- when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
- if IR(5) = '0' or Mode /= 3 then
- -- CALL cc,nn
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Inc_PC <= '1';
- LDW <= '1';
- if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
- IncDec_16 <= "1111";
- Set_Addr_TO <= aSP;
- TStates <= "100";
- Set_BusB_To <= "1101";
- else
- MCycles <= "011";
- end if;
- when 4 =>
- Write <= '1';
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- Set_BusB_To <= "1100";
- when 5 =>
- Write <= '1';
- Call <= '1';
- when others => null;
- end case;
- end if;
- when "11001001" =>
- -- RET
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- TStates <= "101";
- Set_Addr_TO <= aSP;
- when 2 =>
- IncDec_16 <= "0111";
- Set_Addr_To <= aSP;
- LDZ <= '1';
- when 3 =>
- Jump <= '1';
- IncDec_16 <= "0111";
- when others => null;
- end case;
- when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
- if IR(5) = '1' and Mode = 3 then
- case IRB(4 downto 3) is
- when "00" =>
- -- LD ($FF00+nn),A
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- Set_Addr_To <= aIOA;
- Set_BusB_To <= "0111";
- when 3 =>
- Write <= '1';
- when others => null;
- end case;
- when "01" =>
- -- ADD SP,n
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- ALU_Op <= "0000";
- Inc_PC <= '1';
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_BusA_To <= "1000";
- Set_BusB_To <= "0110";
- when 3 =>
- NoRead <= '1';
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- ALU_Op <= "0001";
- Set_BusA_To <= "1001";
- Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
- when others =>
- end case;
- when "10" =>
- -- LD A,($FF00+nn)
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- Set_Addr_To <= aIOA;
- when 3 =>
- Read_To_Acc <= '1';
- when others => null;
- end case;
- when "11" =>
- -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!!
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- LDW <= '1';
- when 4 =>
- Set_BusA_To(2 downto 0) <= "101"; -- L
- Read_To_Reg <= '1';
- Inc_WZ <= '1';
- Set_Addr_To <= aZI;
- when 5 =>
- Set_BusA_To(2 downto 0) <= "100"; -- H
- Read_To_Reg <= '1';
- when others => null;
- end case;
- end case;
- else
- -- RET cc
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
- Set_Addr_TO <= aSP;
- else
- MCycles <= "001";
- end if;
- TStates <= "101";
- when 2 =>
- IncDec_16 <= "0111";
- Set_Addr_To <= aSP;
- LDZ <= '1';
- when 3 =>
- Jump <= '1';
- IncDec_16 <= "0111";
- when others => null;
- end case;
- end if;
- when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
- -- RST p
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- TStates <= "101";
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- Set_BusB_To <= "1101";
- when 2 =>
- Write <= '1';
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- Set_BusB_To <= "1100";
- when 3 =>
- Write <= '1';
- RstP <= '1';
- when others => null;
- end case;
-
--- INPUT AND OUTPUT GROUP
- when "11011011" =>
- if Mode /= 3 then
- -- IN A,(n)
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- Set_Addr_To <= aIOA;
- when 3 =>
- Read_To_Acc <= '1';
- IORQ <= '1';
- when others => null;
- end case;
- end if;
- when "11010011" =>
- if Mode /= 3 then
- -- OUT (n),A
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- Set_Addr_To <= aIOA;
- Set_BusB_To <= "0111";
- when 3 =>
- Write <= '1';
- IORQ <= '1';
- when others => null;
- end case;
- end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
- when "11001011" =>
- if Mode /= 2 then
- Prefix <= "01";
- end if;
-
- when "11101101" =>
- if Mode < 2 then
- Prefix <= "10";
- end if;
-
- when "11011101"|"11111101" =>
- if Mode < 2 then
- Prefix <= "11";
- end if;
-
- end case;
-
- when "01" =>
-
-------------------------------------------------------------------------------
---
--- CB prefixed instructions
---
-------------------------------------------------------------------------------
-
- Set_BusA_To(2 downto 0) <= IR(2 downto 0);
- Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
- case IRB is
- when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
- |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
- |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
- |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
- |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
- |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
- |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
- |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
- -- RLC r
- -- RL r
- -- RRC r
- -- RR r
- -- SLA r
- -- SRA r
- -- SRL r
- -- SLL r (Undocumented) / SWAP r
- if MCycle = "001" then
- ALU_Op <= "1000";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- end if;
- when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
- -- RLC (HL)
- -- RL (HL)
- -- RRC (HL)
- -- RR (HL)
- -- SRA (HL)
- -- SRL (HL)
- -- SLA (HL)
- -- SLL (HL) (Undocumented) / SWAP (HL)
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 | 7 =>
- Set_Addr_To <= aXY;
- when 2 =>
- ALU_Op <= "1000";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_Addr_To <= aXY;
- TStates <= "100";
- when 3 =>
- Write <= '1';
- when others =>
- end case;
- when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
- |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
- |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
- |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
- |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
- |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
- |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
- |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
- -- BIT b,r
- if MCycle = "001" then
- Set_BusB_To(2 downto 0) <= IR(2 downto 0);
- ALU_Op <= "1001";
- end if;
- when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
- -- BIT b,(HL)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 | 7 =>
- Set_Addr_To <= aXY;
- when 2 =>
- ALU_Op <= "1001";
- TStates <= "100";
- when others =>
- end case;
- when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
- |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
- |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
- |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
- |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
- |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
- |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
- |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
- -- SET b,r
- if MCycle = "001" then
- ALU_Op <= "1010";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- end if;
- when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
- -- SET b,(HL)
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 | 7 =>
- Set_Addr_To <= aXY;
- when 2 =>
- ALU_Op <= "1010";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_Addr_To <= aXY;
- TStates <= "100";
- when 3 =>
- Write <= '1';
- when others =>
- end case;
- when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
- |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
- |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
- |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
- |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
- |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
- |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
- |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
- -- RES b,r
- if MCycle = "001" then
- ALU_Op <= "1011";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- end if;
- when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
- -- RES b,(HL)
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 | 7 =>
- Set_Addr_To <= aXY;
- when 2 =>
- ALU_Op <= "1011";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_Addr_To <= aXY;
- TStates <= "100";
- when 3 =>
- Write <= '1';
- when others =>
- end case;
- end case;
-
- when others =>
-
-------------------------------------------------------------------------------
---
--- ED prefixed instructions
---
-------------------------------------------------------------------------------
-
- case IRB is
- when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
- |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
- |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
- |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
- |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
- |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
- |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
- |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
- |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
- |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
- |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
- |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
- | "10100100"|"10100101"|"10100110"|"10100111"
- | "10101100"|"10101101"|"10101110"|"10101111"
- | "10110100"|"10110101"|"10110110"|"10110111"
- | "10111100"|"10111101"|"10111110"|"10111111"
- |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
- |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
- |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
- |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
- |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
- |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
- |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
- |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
- null; -- NOP, undocumented
- when "01111110"|"01111111" =>
- -- NOP, undocumented
- null;
--- 8 BIT LOAD GROUP
- when "01010111" =>
- -- LD A,I
- Special_LD <= "100";
- TStates <= "101";
- when "01011111" =>
- -- LD A,R
- Special_LD <= "101";
- TStates <= "101";
- when "01000111" =>
- -- LD I,A
- Special_LD <= "110";
- TStates <= "101";
- when "01001111" =>
- -- LD R,A
- Special_LD <= "111";
- TStates <= "101";
--- 16 BIT LOAD GROUP
- when "01001011"|"01011011"|"01101011"|"01111011" =>
- -- LD dd,(nn)
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- LDW <= '1';
- when 4 =>
- Read_To_Reg <= '1';
- if IR(5 downto 4) = "11" then
- Set_BusA_To <= "1000";
- else
- Set_BusA_To(2 downto 1) <= IR(5 downto 4);
- Set_BusA_To(0) <= '1';
- end if;
- Inc_WZ <= '1';
- Set_Addr_To <= aZI;
- when 5 =>
- Read_To_Reg <= '1';
- if IR(5 downto 4) = "11" then
- Set_BusA_To <= "1001";
- else
- Set_BusA_To(2 downto 1) <= IR(5 downto 4);
- Set_BusA_To(0) <= '0';
- end if;
- when others => null;
- end case;
- when "01000011"|"01010011"|"01100011"|"01110011" =>
- -- LD (nn),dd
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- LDW <= '1';
- if IR(5 downto 4) = "11" then
- Set_BusB_To <= "1000";
- else
- Set_BusB_To(2 downto 1) <= IR(5 downto 4);
- Set_BusB_To(0) <= '1';
- Set_BusB_To(3) <= '0';
- end if;
- when 4 =>
- Inc_WZ <= '1';
- Set_Addr_To <= aZI;
- Write <= '1';
- if IR(5 downto 4) = "11" then
- Set_BusB_To <= "1001";
- else
- Set_BusB_To(2 downto 1) <= IR(5 downto 4);
- Set_BusB_To(0) <= '0';
- Set_BusB_To(3) <= '0';
- end if;
- when 5 =>
- Write <= '1';
- when others => null;
- end case;
- when "10100000" | "10101000" | "10110000" | "10111000" =>
- -- LDI, LDD, LDIR, LDDR
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- IncDec_16 <= "1100"; -- BC
- when 2 =>
- Set_BusB_To <= "0110";
- Set_BusA_To(2 downto 0) <= "111";
- ALU_Op <= "0000";
- Set_Addr_To <= aDE;
- if IR(3) = '0' then
- IncDec_16 <= "0110"; -- IX
- else
- IncDec_16 <= "1110";
- end if;
- when 3 =>
- I_BT <= '1';
- TStates <= "101";
- Write <= '1';
- if IR(3) = '0' then
- IncDec_16 <= "0101"; -- DE
- else
- IncDec_16 <= "1101";
- end if;
- when 4 =>
- NoRead <= '1';
- TStates <= "101";
- when others => null;
- end case;
- when "10100001" | "10101001" | "10110001" | "10111001" =>
- -- CPI, CPD, CPIR, CPDR
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- IncDec_16 <= "1100"; -- BC
- when 2 =>
- Set_BusB_To <= "0110";
- Set_BusA_To(2 downto 0) <= "111";
- ALU_Op <= "0111";
- Save_ALU <= '1';
- PreserveC <= '1';
- if IR(3) = '0' then
- IncDec_16 <= "0110";
- else
- IncDec_16 <= "1110";
- end if;
- when 3 =>
- NoRead <= '1';
- I_BC <= '1';
- TStates <= "101";
- when 4 =>
- NoRead <= '1';
- TStates <= "101";
- when others => null;
- end case;
- when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
- -- NEG
- Alu_OP <= "0010";
- Set_BusB_To <= "0111";
- Set_BusA_To <= "1010";
- Read_To_Acc <= '1';
- Save_ALU <= '1';
- when "01000110"|"01001110"|"01100110"|"01101110" =>
- -- IM 0
- IMode <= "00";
- when "01010110"|"01110110" =>
- -- IM 1
- IMode <= "01";
- when "01011110"|"01110111" =>
- -- IM 2
- IMode <= "10";
--- 16 bit arithmetic
- when "01001010"|"01011010"|"01101010"|"01111010" =>
- -- ADC HL,ss
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- NoRead <= '1';
- ALU_Op <= "0001";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_BusA_To(2 downto 0) <= "101";
- case to_integer(unsigned(IR(5 downto 4))) is
- when 0|1|2 =>
- Set_BusB_To(2 downto 1) <= IR(5 downto 4);
- Set_BusB_To(0) <= '1';
- when others =>
- Set_BusB_To <= "1000";
- end case;
- TStates <= "100";
- when 3 =>
- NoRead <= '1';
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- ALU_Op <= "0001";
- Set_BusA_To(2 downto 0) <= "100";
- case to_integer(unsigned(IR(5 downto 4))) is
- when 0|1|2 =>
- Set_BusB_To(2 downto 1) <= IR(5 downto 4);
- Set_BusB_To(0) <= '0';
- when others =>
- Set_BusB_To <= "1001";
- end case;
- when others =>
- end case;
- when "01000010"|"01010010"|"01100010"|"01110010" =>
- -- SBC HL,ss
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- NoRead <= '1';
- ALU_Op <= "0011";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_BusA_To(2 downto 0) <= "101";
- case to_integer(unsigned(IR(5 downto 4))) is
- when 0|1|2 =>
- Set_BusB_To(2 downto 1) <= IR(5 downto 4);
- Set_BusB_To(0) <= '1';
- when others =>
- Set_BusB_To <= "1000";
- end case;
- TStates <= "100";
- when 3 =>
- NoRead <= '1';
- ALU_Op <= "0011";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_BusA_To(2 downto 0) <= "100";
- case to_integer(unsigned(IR(5 downto 4))) is
- when 0|1|2 =>
- Set_BusB_To(2 downto 1) <= IR(5 downto 4);
- when others =>
- Set_BusB_To <= "1001";
- end case;
- when others =>
- end case;
- when "01101111" =>
- -- RLD
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- NoRead <= '1';
- Set_Addr_To <= aXY;
- when 3 =>
- Read_To_Reg <= '1';
- Set_BusB_To(2 downto 0) <= "110";
- Set_BusA_To(2 downto 0) <= "111";
- ALU_Op <= "1101";
- TStates <= "100";
- Set_Addr_To <= aXY;
- Save_ALU <= '1';
- when 4 =>
- I_RLD <= '1';
- Write <= '1';
- when others =>
- end case;
- when "01100111" =>
- -- RRD
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Set_Addr_To <= aXY;
- when 3 =>
- Read_To_Reg <= '1';
- Set_BusB_To(2 downto 0) <= "110";
- Set_BusA_To(2 downto 0) <= "111";
- ALU_Op <= "1110";
- TStates <= "100";
- Set_Addr_To <= aXY;
- Save_ALU <= '1';
- when 4 =>
- I_RRD <= '1';
- Write <= '1';
- when others =>
- end case;
- when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
- -- RETI, RETN
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_TO <= aSP;
- when 2 =>
- IncDec_16 <= "0111";
- Set_Addr_To <= aSP;
- LDZ <= '1';
- when 3 =>
- Jump <= '1';
- IncDec_16 <= "0111";
- I_RETN <= '1';
- when others => null;
- end case;
- when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
- -- IN r,(C)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aBC;
- when 2 =>
- IORQ <= '1';
- if IR(5 downto 3) /= "110" then
- Read_To_Reg <= '1';
- Set_BusA_To(2 downto 0) <= IR(5 downto 3);
- end if;
- I_INRC <= '1';
- when others =>
- end case;
- when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
- -- OUT (C),r
- -- OUT (C),0
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aBC;
- Set_BusB_To(2 downto 0) <= IR(5 downto 3);
- if IR(5 downto 3) = "110" then
- Set_BusB_To(3) <= '1';
- end if;
- when 2 =>
- Write <= '1';
- IORQ <= '1';
- when others =>
- end case;
- when "10100010" | "10101010" | "10110010" | "10111010" =>
- -- INI, IND, INIR, INDR
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aBC;
- Set_BusB_To <= "1010";
- Set_BusA_To <= "0000";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- ALU_Op <= "0010";
- when 2 =>
- IORQ <= '1';
- Set_BusB_To <= "0110";
- Set_Addr_To <= aXY;
- when 3 =>
- if IR(3) = '0' then
- IncDec_16 <= "0010";
- else
- IncDec_16 <= "1010";
- end if;
- TStates <= "100";
- Write <= '1';
- I_BTR <= '1';
- when 4 =>
- NoRead <= '1';
- TStates <= "101";
- when others => null;
- end case;
- when "10100011" | "10101011" | "10110011" | "10111011" =>
- -- OUTI, OUTD, OTIR, OTDR
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- TStates <= "101";
- Set_Addr_To <= aXY;
- Set_BusB_To <= "1010";
- Set_BusA_To <= "0000";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- ALU_Op <= "0010";
- when 2 =>
- Set_BusB_To <= "0110";
- Set_Addr_To <= aBC;
- when 3 =>
- if IR(3) = '0' then
- IncDec_16 <= "0010";
- else
- IncDec_16 <= "1010";
- end if;
- IORQ <= '1';
- Write <= '1';
- I_BTR <= '1';
- when 4 =>
- NoRead <= '1';
- TStates <= "101";
- when others => null;
- end case;
- end case;
-
- end case;
-
- if Mode = 1 then
- if MCycle = "001" then
--- TStates <= "100";
- else
- TStates <= "011";
- end if;
- end if;
-
- if Mode = 3 then
- if MCycle = "001" then
--- TStates <= "100";
- else
- TStates <= "100";
- end if;
- end if;
-
- if Mode < 2 then
- if MCycle = "110" then
- Inc_PC <= '1';
- if Mode = 1 then
- Set_Addr_To <= aXY;
- TStates <= "100";
- Set_BusB_To(2 downto 0) <= SSS;
- Set_BusB_To(3) <= '0';
- end if;
- if IRB = "00110110" or IRB = "11001011" then
- Set_Addr_To <= aNone;
- end if;
- end if;
- if MCycle = "111" then
- if Mode = 0 then
- TStates <= "101";
- end if;
- if ISet /= "01" then
- Set_Addr_To <= aXY;
- end if;
- Set_BusB_To(2 downto 0) <= SSS;
- Set_BusB_To(3) <= '0';
- if IRB = "00110110" or ISet = "01" then
- -- LD (HL),n
- Inc_PC <= '1';
- else
- NoRead <= '1';
- end if;
- end if;
- end if;
-
- end process;
-
-end;
diff --git a/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/T80/T80_Pack.vhd
deleted file mode 100644
index ac7d34da..00000000
--- a/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/T80/T80_Pack.vhd
+++ /dev/null
@@ -1,208 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
- component T80
- generic(
- Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
- IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
- Flag_C : integer := 0;
- Flag_N : integer := 1;
- Flag_P : integer := 2;
- Flag_X : integer := 3;
- Flag_H : integer := 4;
- Flag_Y : integer := 5;
- Flag_Z : integer := 6;
- Flag_S : integer := 7
- );
- port(
- RESET_n : in std_logic;
- CLK_n : in std_logic;
- CEN : in std_logic;
- WAIT_n : in std_logic;
- INT_n : in std_logic;
- NMI_n : in std_logic;
- BUSRQ_n : in std_logic;
- M1_n : out std_logic;
- IORQ : out std_logic;
- NoRead : out std_logic;
- Write : out std_logic;
- RFSH_n : out std_logic;
- HALT_n : out std_logic;
- BUSAK_n : out std_logic;
- A : out std_logic_vector(15 downto 0);
- DInst : in std_logic_vector(7 downto 0);
- DI : in std_logic_vector(7 downto 0);
- DO : out std_logic_vector(7 downto 0);
- MC : out std_logic_vector(2 downto 0);
- TS : out std_logic_vector(2 downto 0);
- IntCycle_n : out std_logic;
- IntE : out std_logic;
- Stop : out std_logic
- );
- end component;
-
- component T80_Reg
- port(
- Clk : in std_logic;
- CEN : in std_logic;
- WEH : in std_logic;
- WEL : in std_logic;
- AddrA : in std_logic_vector(2 downto 0);
- AddrB : in std_logic_vector(2 downto 0);
- AddrC : in std_logic_vector(2 downto 0);
- DIH : in std_logic_vector(7 downto 0);
- DIL : in std_logic_vector(7 downto 0);
- DOAH : out std_logic_vector(7 downto 0);
- DOAL : out std_logic_vector(7 downto 0);
- DOBH : out std_logic_vector(7 downto 0);
- DOBL : out std_logic_vector(7 downto 0);
- DOCH : out std_logic_vector(7 downto 0);
- DOCL : out std_logic_vector(7 downto 0)
- );
- end component;
-
- component T80_MCode
- generic(
- Mode : integer := 0;
- Flag_C : integer := 0;
- Flag_N : integer := 1;
- Flag_P : integer := 2;
- Flag_X : integer := 3;
- Flag_H : integer := 4;
- Flag_Y : integer := 5;
- Flag_Z : integer := 6;
- Flag_S : integer := 7
- );
- port(
- IR : in std_logic_vector(7 downto 0);
- ISet : in std_logic_vector(1 downto 0);
- MCycle : in std_logic_vector(2 downto 0);
- F : in std_logic_vector(7 downto 0);
- NMICycle : in std_logic;
- IntCycle : in std_logic;
- MCycles : out std_logic_vector(2 downto 0);
- TStates : out std_logic_vector(2 downto 0);
- Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
- Inc_PC : out std_logic;
- Inc_WZ : out std_logic;
- IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
- Read_To_Reg : out std_logic;
- Read_To_Acc : out std_logic;
- Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
- Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
- ALU_Op : out std_logic_vector(3 downto 0);
- -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
- Save_ALU : out std_logic;
- PreserveC : out std_logic;
- Arith16 : out std_logic;
- Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
- IORQ : out std_logic;
- Jump : out std_logic;
- JumpE : out std_logic;
- JumpXY : out std_logic;
- Call : out std_logic;
- RstP : out std_logic;
- LDZ : out std_logic;
- LDW : out std_logic;
- LDSPHL : out std_logic;
- Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
- ExchangeDH : out std_logic;
- ExchangeRp : out std_logic;
- ExchangeAF : out std_logic;
- ExchangeRS : out std_logic;
- I_DJNZ : out std_logic;
- I_CPL : out std_logic;
- I_CCF : out std_logic;
- I_SCF : out std_logic;
- I_RETN : out std_logic;
- I_BT : out std_logic;
- I_BC : out std_logic;
- I_BTR : out std_logic;
- I_RLD : out std_logic;
- I_RRD : out std_logic;
- I_INRC : out std_logic;
- SetDI : out std_logic;
- SetEI : out std_logic;
- IMode : out std_logic_vector(1 downto 0);
- Halt : out std_logic;
- NoRead : out std_logic;
- Write : out std_logic
- );
- end component;
-
- component T80_ALU
- generic(
- Mode : integer := 0;
- Flag_C : integer := 0;
- Flag_N : integer := 1;
- Flag_P : integer := 2;
- Flag_X : integer := 3;
- Flag_H : integer := 4;
- Flag_Y : integer := 5;
- Flag_Z : integer := 6;
- Flag_S : integer := 7
- );
- port(
- Arith16 : in std_logic;
- Z16 : in std_logic;
- ALU_Op : in std_logic_vector(3 downto 0);
- IR : in std_logic_vector(5 downto 0);
- ISet : in std_logic_vector(1 downto 0);
- BusA : in std_logic_vector(7 downto 0);
- BusB : in std_logic_vector(7 downto 0);
- F_In : in std_logic_vector(7 downto 0);
- Q : out std_logic_vector(7 downto 0);
- F_Out : out std_logic_vector(7 downto 0)
- );
- end component;
-
-end;
diff --git a/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/T80/T80_Reg.vhd
deleted file mode 100644
index 828485fb..00000000
--- a/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/T80/T80_Reg.vhd
+++ /dev/null
@@ -1,105 +0,0 @@
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
--- 0242 : Initial release
---
--- 0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
- port(
- Clk : in std_logic;
- CEN : in std_logic;
- WEH : in std_logic;
- WEL : in std_logic;
- AddrA : in std_logic_vector(2 downto 0);
- AddrB : in std_logic_vector(2 downto 0);
- AddrC : in std_logic_vector(2 downto 0);
- DIH : in std_logic_vector(7 downto 0);
- DIL : in std_logic_vector(7 downto 0);
- DOAH : out std_logic_vector(7 downto 0);
- DOAL : out std_logic_vector(7 downto 0);
- DOBH : out std_logic_vector(7 downto 0);
- DOBL : out std_logic_vector(7 downto 0);
- DOCH : out std_logic_vector(7 downto 0);
- DOCL : out std_logic_vector(7 downto 0)
- );
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
- type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
- signal RegsH : Register_Image(0 to 7);
- signal RegsL : Register_Image(0 to 7);
-
-begin
-
- process (Clk)
- begin
- if Clk'event and Clk = '1' then
- if CEN = '1' then
- if WEH = '1' then
- RegsH(to_integer(unsigned(AddrA))) <= DIH;
- end if;
- if WEL = '1' then
- RegsL(to_integer(unsigned(AddrA))) <= DIL;
- end if;
- end if;
- end if;
- end process;
-
- DOAH <= RegsH(to_integer(unsigned(AddrA)));
- DOAL <= RegsL(to_integer(unsigned(AddrA)));
- DOBH <= RegsH(to_integer(unsigned(AddrB)));
- DOBL <= RegsL(to_integer(unsigned(AddrB)));
- DOCH <= RegsH(to_integer(unsigned(AddrC)));
- DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
diff --git a/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/T80/T80se.vhd b/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/T80/T80se.vhd
deleted file mode 100644
index ac8886a8..00000000
--- a/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/T80/T80se.vhd
+++ /dev/null
@@ -1,184 +0,0 @@
---
--- Z80 compatible microprocessor core, synchronous top level with clock enable
--- Different timing than the original z80
--- Inputs needs to be synchronous and outputs may glitch
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
--- 0235 : First release
---
--- 0236 : Added T2Write generic
---
--- 0237 : Fixed T2Write with wait state
---
--- 0238 : Updated for T80 interface change
---
--- 0240 : Updated for T80 interface change
---
--- 0242 : Updated for T80 interface change
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80se is
- generic(
- Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
- T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
- IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
- );
- port(
- RESET_n : in std_logic;
- CLK_n : in std_logic;
- CLKEN : in std_logic;
- WAIT_n : in std_logic;
- INT_n : in std_logic;
- NMI_n : in std_logic;
- BUSRQ_n : in std_logic;
- M1_n : out std_logic;
- MREQ_n : out std_logic;
- IORQ_n : out std_logic;
- RD_n : out std_logic;
- WR_n : out std_logic;
- RFSH_n : out std_logic;
- HALT_n : out std_logic;
- BUSAK_n : out std_logic;
- A : out std_logic_vector(15 downto 0);
- DI : in std_logic_vector(7 downto 0);
- DO : out std_logic_vector(7 downto 0)
- );
-end T80se;
-
-architecture rtl of T80se is
-
- signal IntCycle_n : std_logic;
- signal NoRead : std_logic;
- signal Write : std_logic;
- signal IORQ : std_logic;
- signal DI_Reg : std_logic_vector(7 downto 0);
- signal MCycle : std_logic_vector(2 downto 0);
- signal TState : std_logic_vector(2 downto 0);
-
-begin
-
- u0 : T80
- generic map(
- Mode => Mode,
- IOWait => IOWait)
- port map(
- CEN => CLKEN,
- M1_n => M1_n,
- IORQ => IORQ,
- NoRead => NoRead,
- Write => Write,
- RFSH_n => RFSH_n,
- HALT_n => HALT_n,
- WAIT_n => Wait_n,
- INT_n => INT_n,
- NMI_n => NMI_n,
- RESET_n => RESET_n,
- BUSRQ_n => BUSRQ_n,
- BUSAK_n => BUSAK_n,
- CLK_n => CLK_n,
- A => A,
- DInst => DI,
- DI => DI_Reg,
- DO => DO,
- MC => MCycle,
- TS => TState,
- IntCycle_n => IntCycle_n);
-
- process (RESET_n, CLK_n)
- begin
- if RESET_n = '0' then
- RD_n <= '1';
- WR_n <= '1';
- IORQ_n <= '1';
- MREQ_n <= '1';
- DI_Reg <= "00000000";
- elsif CLK_n'event and CLK_n = '1' then
- if CLKEN = '1' then
- RD_n <= '1';
- WR_n <= '1';
- IORQ_n <= '1';
- MREQ_n <= '1';
- if MCycle = "001" then
- if TState = "001" or (TState = "010" and Wait_n = '0') then
- RD_n <= not IntCycle_n;
- MREQ_n <= not IntCycle_n;
- IORQ_n <= IntCycle_n;
- end if;
- if TState = "011" then
- MREQ_n <= '0';
- end if;
- else
- if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
- RD_n <= '0';
- IORQ_n <= not IORQ;
- MREQ_n <= IORQ;
- end if;
- if T2Write = 0 then
- if TState = "010" and Write = '1' then
- WR_n <= '0';
- IORQ_n <= not IORQ;
- MREQ_n <= IORQ;
- end if;
- else
- if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
- WR_n <= '0';
- IORQ_n <= not IORQ;
- MREQ_n <= IORQ;
- end if;
- end if;
- end if;
- if TState = "010" and Wait_n = '1' then
- DI_Reg <= DI;
- end if;
- end if;
- end if;
- end process;
-
-end;
diff --git a/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/pll.v b/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/pll.v
index 3c7dc7fe..f0530bf2 100644
--- a/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/pll.v
+++ b/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/pll.v
@@ -14,7 +14,7 @@
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
-// 13.1.4 Build 182 03/12/2014 SJ Web Edition
+// 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
// ************************************************************
@@ -41,31 +41,35 @@ module pll (
c0,
c1,
c2,
+ c3,
locked);
input inclk0;
output c0;
output c1;
output c2;
+ output c3;
output locked;
wire [4:0] sub_wire0;
- wire sub_wire2;
- wire [0:0] sub_wire7 = 1'h0;
- wire [2:2] sub_wire4 = sub_wire0[2:2];
- wire [0:0] sub_wire3 = sub_wire0[0:0];
+ wire sub_wire3;
+ wire [0:0] sub_wire8 = 1'h0;
+ wire [2:2] sub_wire5 = sub_wire0[2:2];
+ wire [0:0] sub_wire4 = sub_wire0[0:0];
+ wire [3:3] sub_wire2 = sub_wire0[3:3];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
- wire locked = sub_wire2;
- wire c0 = sub_wire3;
- wire c2 = sub_wire4;
- wire sub_wire5 = inclk0;
- wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
+ wire c3 = sub_wire2;
+ wire locked = sub_wire3;
+ wire c0 = sub_wire4;
+ wire c2 = sub_wire5;
+ wire sub_wire6 = inclk0;
+ wire [1:0] sub_wire7 = {sub_wire8, sub_wire6};
altpll altpll_component (
- .inclk (sub_wire6),
+ .inclk (sub_wire7),
.clk (sub_wire0),
- .locked (sub_wire2),
+ .locked (sub_wire3),
.activeclock (),
.areset (1'b0),
.clkbad (),
@@ -102,18 +106,22 @@ module pll (
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
- altpll_component.clk0_divide_by = 26,
+ altpll_component.clk0_divide_by = 115,
altpll_component.clk0_duty_cycle = 50,
- altpll_component.clk0_multiply_by = 47,
+ altpll_component.clk0_multiply_by = 208,
altpll_component.clk0_phase_shift = "0",
- altpll_component.clk1_divide_by = 104,
+ altpll_component.clk1_divide_by = 115,
altpll_component.clk1_duty_cycle = 50,
- altpll_component.clk1_multiply_by = 47,
+ altpll_component.clk1_multiply_by = 52,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 395,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 208,
altpll_component.clk2_phase_shift = "0",
+ altpll_component.clk3_divide_by = 115,
+ altpll_component.clk3_duty_cycle = 50,
+ altpll_component.clk3_multiply_by = 26,
+ altpll_component.clk3_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone III",
@@ -149,7 +157,7 @@ module pll (
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
- altpll_component.port_clk3 = "PORT_UNUSED",
+ altpll_component.port_clk3 = "PORT_USED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
@@ -187,15 +195,18 @@ endmodule
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "26"
-// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "104"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "115"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "115"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "395"
+// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "115"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.807693"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.201923"
+// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.834782"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.208695"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "14.217722"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.104348"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -218,32 +229,40 @@ endmodule
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "47"
-// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "47"
+// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "208"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "52"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "208"
+// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "26"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.78400000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.19600000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "14.22800000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
@@ -268,31 +287,38 @@ endmodule
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "26"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "115"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "47"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "208"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "104"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "115"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "47"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "52"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "395"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "208"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "115"
+// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "26"
+// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
@@ -327,7 +353,7 @@ endmodule
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
@@ -346,6 +372,7 @@ endmodule
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
@@ -353,6 +380,7 @@ endmodule
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
diff --git a/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/pooyan.vhd b/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/pooyan.vhd
index f1cb4573..9b3cd775 100644
--- a/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/pooyan.vhd
+++ b/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/pooyan.vhd
@@ -1,5 +1,5 @@
---------------------------------------------------------------------------------
--- Time pilot by Dar (darfpga@aol.fr) (29/10/2017)
+-- Pooyan by Dar (darfpga@aol.fr) (29/10/2017)
-- http://darfpga.blogspot.fr
---------------------------------------------------------------------------------
-- gen_ram.vhd & io_ps2_keyboard
@@ -72,6 +72,7 @@ use ieee.numeric_std.all;
entity pooyan is
port(
+ clock_6 : in std_logic;
clock_12 : in std_logic;
clock_14 : in std_logic;
reset : in std_logic;
@@ -79,10 +80,10 @@ port(
video_g : out std_logic_vector(2 downto 0);
video_b : out std_logic_vector(1 downto 0);
video_clk : out std_logic;
- video_vblank : out std_logic;
- video_hblank : out std_logic;
+ video_blankn : out std_logic;
video_hs : out std_logic;
video_vs : out std_logic;
+ video_csync : out std_logic;
audio_out : out std_logic_vector(10 downto 0);
roms_addr : out std_logic_vector(14 downto 0);
roms_do : in std_logic_vector(7 downto 0);
@@ -106,7 +107,6 @@ port(
down2 : in std_logic;
up2 : in std_logic;
- sw : in std_logic_vector(9 downto 0);
dbg_cpu_addr : out std_logic_vector(15 downto 0)
);
end pooyan;
@@ -115,7 +115,6 @@ architecture struct of pooyan is
signal reset_n: std_logic;
signal clock_12n : std_logic;
- signal clock_6 : std_logic := '0';
signal clock_6n : std_logic;
signal clock_div : std_logic_vector(1 downto 0) := "00";
@@ -209,7 +208,7 @@ architecture struct of pooyan is
signal input_2 : std_logic_vector(7 downto 0);
begin
-video_clk <= clock_6n;
+
clock_12n <= not clock_12;
clock_6n <= not clock_6;
reset_n <= not reset;
@@ -222,19 +221,6 @@ begin
end if;
end process;
--- make 6MHz clock from 12MHz
-process (clock_12)
-begin
- if reset='1' then
- clock_6 <= '0';
- else
- if rising_edge(clock_12) then
- clock_6 <= not clock_6;
- end if;
- end if;
-end process;
-
-
--------------------------
-- Video/sprite scanner --
--------------------------
@@ -546,35 +532,7 @@ begin
end process;
-- address char color palette 4 colors, 64 sets => 16 colors
-with sw(4 downto 0) select
-ch_palette_addr <=
-ch_color_set & ch_pixels(3) & ch_pixels( 7) & ch_pixels(11) & ch_pixels(15) when '0'&X"0",
-ch_color_set & ch_pixels(3) & ch_pixels( 7) & ch_pixels(15) & ch_pixels(11) when '0'&X"1",
-ch_color_set & ch_pixels(3) & ch_pixels(11) & ch_pixels( 7) & ch_pixels(15) when '0'&X"2",
-ch_color_set & ch_pixels(3) & ch_pixels(11) & ch_pixels(15) & ch_pixels( 7) when '0'&X"3",
-ch_color_set & ch_pixels(3) & ch_pixels(15) & ch_pixels( 7) & ch_pixels(11) when '0'&X"4",
-ch_color_set & ch_pixels(3) & ch_pixels(15) & ch_pixels(11) & ch_pixels( 7) when '0'&X"5",
-
-ch_color_set & ch_pixels(7) & ch_pixels( 3) & ch_pixels(11) & ch_pixels(15) when '0'&X"6",
-ch_color_set & ch_pixels(7) & ch_pixels( 3) & ch_pixels(15) & ch_pixels(11) when '0'&X"7",
-ch_color_set & ch_pixels(7) & ch_pixels(11) & ch_pixels( 3) & ch_pixels(15) when '0'&X"8",
-ch_color_set & ch_pixels(7) & ch_pixels(11) & ch_pixels(15) & ch_pixels( 3) when '0'&X"9",
-ch_color_set & ch_pixels(7) & ch_pixels(15) & ch_pixels( 3) & ch_pixels(11) when '0'&X"A",
-ch_color_set & ch_pixels(7) & ch_pixels(15) & ch_pixels(11) & ch_pixels( 3) when '0'&X"B",
-
-ch_color_set & ch_pixels(11) & ch_pixels( 3) & ch_pixels( 7) & ch_pixels(15) when '0'&X"C",
-ch_color_set & ch_pixels(11) & ch_pixels( 3) & ch_pixels(15) & ch_pixels( 7) when '0'&X"D",
-ch_color_set & ch_pixels(11) & ch_pixels( 7) & ch_pixels( 3) & ch_pixels(15) when '0'&X"E",
-ch_color_set & ch_pixels(11) & ch_pixels( 7) & ch_pixels(15) & ch_pixels( 3) when '0'&X"F",
-ch_color_set & ch_pixels(11) & ch_pixels(15) & ch_pixels( 3) & ch_pixels( 7) when '1'&X"0",
-ch_color_set & ch_pixels(11) & ch_pixels(15) & ch_pixels( 7) & ch_pixels( 3) when '1'&X"1",
-
-ch_color_set & ch_pixels(15) & ch_pixels( 3) & ch_pixels( 7) & ch_pixels(11) when '1'&X"2",
-ch_color_set & ch_pixels(15) & ch_pixels( 3) & ch_pixels(11) & ch_pixels( 7) when '1'&X"3",
-ch_color_set & ch_pixels(15) & ch_pixels( 7) & ch_pixels( 3) & ch_pixels(11) when '1'&X"4",
-ch_color_set & ch_pixels(15) & ch_pixels( 7) & ch_pixels(11) & ch_pixels( 3) when '1'&X"5",
-ch_color_set & ch_pixels(15) & ch_pixels(11) & ch_pixels( 3) & ch_pixels( 7) when '1'&X"6",
-ch_color_set & ch_pixels(15) & ch_pixels(11) & ch_pixels( 7) & ch_pixels( 3) when others;
+ch_palette_addr <= ch_color_set & ch_pixels(3) & ch_pixels( 7) & ch_pixels(11) & ch_pixels(15);
---------------------
-- mux char/sprite --
@@ -604,23 +562,35 @@ begin
end if;
end process;
-video_hblank <= hblank;
-video_vblank <= vblank;
-
----------------------------
-- video syncs and blanks --
----------------------------
+video_csync <= csync;
+
process(clock_6)
- constant hcnt_base : integer := 36;
+ constant hcnt_base : integer := 37;
variable vsync_cnt : std_logic_vector(3 downto 0);
begin
- if rising_edge(clock_6) and pxcnt = "110" then
+
+if rising_edge(clock_6) and pxcnt = "111" then
if hcnt = hcnt_base+0 then hsync0 <= '0';
elsif hcnt = hcnt_base+3 then hsync0 <= '1';
end if;
+ if hcnt = hcnt_base+0 then hsync1 <= '0';
+ elsif hcnt = hcnt_base+1 then hsync1 <= '1';
+ elsif hcnt = hcnt_base+24-48 then hsync1 <= '0';
+ elsif hcnt = hcnt_base+25-48 then hsync1 <= '1';
+ end if;
+
+ if hcnt = hcnt_base+0 then hsync2 <= '0';
+ elsif hcnt = hcnt_base+24-1-48 then hsync2 <= '1';
+ elsif hcnt = hcnt_base+24-48 then hsync2 <= '0';
+ elsif hcnt = hcnt_base+0-1 then hsync2 <= '1';
+ end if;
+
if hcnt = hcnt_base then
if vcnt = 500 then
vsync_cnt := X"0";
@@ -629,17 +599,29 @@ begin
end if;
end if;
- if hcnt = hcnt_base-4 then
- hblank <= '1';
- if vcnt = 496 then
- vblank <= '1'; -- 492 ok
- elsif vcnt = 262 then
- vblank <= '0'; -- 262 ok
+ if vsync_cnt = 0 then csync <= hsync1;
+ elsif vsync_cnt = 1 then csync <= hsync1;
+ elsif vsync_cnt = 2 then csync <= hsync1;
+ elsif vsync_cnt = 3 then csync <= hsync2;
+ elsif vsync_cnt = 4 then csync <= hsync2;
+ elsif vsync_cnt = 5 then csync <= hsync2;
+ elsif vsync_cnt = 6 then csync <= hsync1;
+ elsif vsync_cnt = 7 then csync <= hsync1;
+ elsif vsync_cnt = 8 then csync <= hsync1;
+ else csync <= hsync0;
end if;
- elsif hcnt = 0 then
- hblank <= '0';
+
+ if hcnt = hcnt_base-6 then hblank <= '1';
+ elsif hcnt = hcnt_base+10 then hblank <= '0';
+ end if;
+
+ if vcnt = 496 then vblank <= '1'; -- 492 ok
+ elsif vcnt = 262 then vblank <= '0'; -- 262 ok
end if;
+ -- external sync and blank outputs
+ video_blankn <= not (hblank or vblank);
+
video_hs <= hsync0;
if vsync_cnt = 0 then video_vs <= '0';
diff --git a/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/pooyan_mist.sv b/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/pooyan_mist.sv
index e3b21fd3..da7f3e12 100644
--- a/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/pooyan_mist.sv
+++ b/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/pooyan_mist.sv
@@ -33,23 +33,29 @@ module pooyan_mist(
localparam CONF_STR = {
"POOYAN;;",
"O2,Rotate Controls,Off,On;",
- "O34,Scandoubler Fx,None,CRT 25%,CRT 50%,CRT 75%;",
- "T6,Reset;",
- "V,v1.25.",`BUILD_DATE
+ "O34,Scanlines,Off,25%,50%,75%;",
+ "O5,Blend,Off,On;",
+ "T0,Reset;",
+ "V,v1.15.",`BUILD_DATE
};
-assign LED = 1;
-assign AUDIO_R = AUDIO_L;
-assign SDRAM_CLK = clock_48;
+wire rotate = status[2];
+wire [1:0] scanlines = status[4:3];
+wire blend = status[5];
-wire clock_48, clock_12, clock_14, pll_locked;
+assign LED = 1;
+assign AUDIO_R = AUDIO_L;
+assign SDRAM_CLK = clock_48;
+
+wire clock_48, clock_12, clock_6, clock_14, pll_locked;
pll pll(
- .inclk0(CLOCK_27),
- .c0(clock_48),
- .c1(clock_12),
- .c2(clock_14),
- .locked(pll_locked)
- );
+ .inclk0(CLOCK_27),
+ .c0(clock_48),//24,57600000
+ .c1(clock_12),//12.28800000
+ .c2(clock_14),//14.31800000
+ .c3(clock_6),
+ .locked(pll_locked)
+ );
wire [31:0] status;
wire [1:0] buttons;
@@ -60,9 +66,8 @@ wire [7:0] joystick_1;
wire scandoublerD;
wire ypbpr;
wire [10:0] audio;
-wire hs, vs;
-wire hb, vb;
-wire blankn = ~(hb | vb);
+wire hs, vs;
+wire blankn;
wire [2:0] r,g;
wire [1:0] b;
wire [14:0] rom_addr;
@@ -104,23 +109,23 @@ sdram rom(
reg reset = 1;
reg rom_loaded = 0;
-always @(posedge clock_48) begin
+always @(posedge clock_12) begin
reg ioctl_downlD;
ioctl_downlD <= ioctl_downl;
if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1;
- reset <= status[0] | buttons[1] | status[6] | ~rom_loaded;
+ reset <= status[0] | buttons[1] | ~rom_loaded;
end
pooyan pooyan(
+ .clock_6(clock_6),
.clock_12(clock_12),
.clock_14(clock_14),
.reset(reset),
.video_r(r),
.video_g(g),
.video_b(b),
- .video_hblank(hb),
- .video_vblank(vb),
+ .video_blankn(blankn),
.video_hs(hs),
.video_vs(vs),
.audio_out(audio),
@@ -129,20 +134,19 @@ pooyan pooyan(
.roms_rd ( rom_rd ),
.dip_switch_1("11111111"),// Coinage_B / Coinage_A
.dip_switch_2("11111011"),// Sound(8)/Difficulty(7-5)/Bonus(4)/Cocktail(3)/lives(2-1)
- .start2(btn_two_players),
- .start1(btn_one_player),
- .coin1(btn_coin),
- .fire1(m_fire),
+ .start2(m_two_players),
+ .start1(m_one_player),
+ .coin1(m_coin1),
+ .fire1(m_fireA),
.right1(m_right),
.left1(m_left),
.down1(m_down),
.up1(m_up),
- .fire2(m_fire),
- .right2(m_right),
- .left2(m_left),
- .down2(m_down),
- .up2(m_up),
- .sw("00000000")
+ .fire2(m_fire2A),
+ .right2(m_right2),
+ .left2(m_left2),
+ .down2(m_down2),
+ .up2(m_up2)
);
@@ -151,9 +155,9 @@ mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video(//Wrong Colors have
.SPI_SCK ( SPI_SCK ),
.SPI_SS3 ( SPI_SS3 ),
.SPI_DI ( SPI_DI ),
- .R ( blankn ? {r,r} : 0 ),
- .G ( blankn ? {g,g} : 0 ),
- .B ( blankn ? {b,b,b} : 0 ),
+ .R ( blankn ? r : 0 ),
+ .G ( blankn ? g : 0 ),
+ .B ( blankn ? {b, b[1]} : 0 ),
.HSync ( hs ),
.VSync ( vs ),
.VGA_R ( VGA_R ),
@@ -161,14 +165,15 @@ mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video(//Wrong Colors have
.VGA_B ( VGA_B ),
.VGA_VS ( VGA_VS ),
.VGA_HS ( VGA_HS ),
- .rotate ( {1'b1,status[2]} ),
+ .rotate ( { 1'b1, rotate } ),
.scandoubler_disable( scandoublerD ),
- .scanlines ( status[4:3] ),
+ .blend ( blend ),
+ .scanlines ( scanlines ),
.ypbpr ( ypbpr )
);
user_io #(.STRLEN(($size(CONF_STR)>>3)))user_io(
- .clk_sys (clock_48 ),
+ .clk_sys (clock_12 ),
.conf_str (CONF_STR ),
.SPI_CLK (SPI_SCK ),
.SPI_SS_IO (CONF_DATA0 ),
@@ -187,48 +192,31 @@ user_io #(.STRLEN(($size(CONF_STR)>>3)))user_io(
);
dac #(.C_bits(16))dac(
- .clk_i(clock_48),
+ .clk_i(clock_14),
.res_n_i(1),
.dac_i({audio, 5'b00000}),
.dac_o(AUDIO_L)
);
-// Rotated Normal
-wire m_up = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3];
-wire m_down = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2];
-wire m_left = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1];
-wire m_right = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0];
-wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4];
-//wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5];
-reg btn_one_player = 0;
-reg btn_two_players = 0;
-reg btn_left = 0;
-reg btn_right = 0;
-reg btn_down = 0;
-reg btn_up = 0;
-reg btn_fire1 = 0;
-//reg btn_fire2 = 0;
-//reg btn_fire3 = 0;
-reg btn_coin = 0;
-
-always @(posedge clock_48) begin
- reg old_state;
- old_state <= key_strobe;
- if(old_state != key_strobe) begin
- case(key_code)
- 'h75: btn_up <= key_pressed; // up
- 'h72: btn_down <= key_pressed; // down
- 'h6B: btn_left <= key_pressed; // left
- 'h74: btn_right <= key_pressed; // right
- 'h76: btn_coin <= key_pressed; // ESC
- 'h05: btn_one_player <= key_pressed; // F1
- 'h06: btn_two_players <= key_pressed; // F2
- //'h14: btn_fire3 <= key_pressed; // ctrl
- //'h11: btn_fire2 <= key_pressed; // alt
- 'h29: btn_fire1 <= key_pressed; // Space
- endcase
- end
-end
+// Arcade inputs
+wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
+wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
+wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
+arcade_inputs inputs (
+ .clk ( clock_12 ),
+ .key_strobe ( key_strobe ),
+ .key_pressed ( key_pressed ),
+ .key_code ( key_code ),
+ .joystick_0 ( joystick_0 ),
+ .joystick_1 ( joystick_1 ),
+ .rotate ( rotate ),
+ .orientation ( 2'b11 ),
+ .joyswap ( 1'b0 ),
+ .oneplayer ( 1'b1 ),
+ .controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
+ .player1 ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
+ .player2 ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
+);
endmodule
diff --git a/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/pooyan_sound_board.vhd b/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/pooyan_sound_board.vhd
index a4b38c7d..68495d12 100644
--- a/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/pooyan_sound_board.vhd
+++ b/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/pooyan_sound_board.vhd
@@ -48,8 +48,8 @@ architecture struct of pooyan_sound_board is
signal clock_div1 : std_logic_vector(11 downto 0) := (others => '0');
signal biquinary_div : std_logic_vector(3 downto 0) := (others => '0');
- signal cpu_clock : std_logic;
- signal ayx_clock : std_logic;
+ signal cpu_clock_en : std_logic;
+ signal ayx_clock_en : std_logic;
signal cpu_addr : std_logic_vector(15 downto 0);
signal cpu_di : std_logic_vector( 7 downto 0);
@@ -241,8 +241,8 @@ begin
end process;
-- make clocks for cpu and sound generators
-cpu_clock <= clock_div1(2);
-ayx_clock <= not clock_div1(2);
+cpu_clock_en <= '1' when clock_div1(2 downto 0) = "011" else '0';
+ayx_clock_en <= '1' when clock_div1(2 downto 0) = "111" else '0';
-- mux rom/ram/devices data ouput to cpu data input w.r.t cpu address
cpu_di <= cpu_rom_do when cpu_addr(15 downto 12) = "0000" else -- 0000-0FFF
@@ -277,9 +277,9 @@ ay1_port_b_di <= biquinary_div(0)&biquinary_div(3)&biquinary_div(2)&clock_div1(1
clr_irq_n <= reset_n and (cpu_m1_n or cpu_iorq_n);
-- regsiter filters commands (11 bits data are cpu address)
-process (cpu_clock)
+process (clock_14, cpu_clock_en)
begin
- if rising_edge(cpu_clock) then
+ if rising_edge(clock_14) and cpu_clock_en = '1' then
if filter_cmd_we = '1' then filter_cmd <= cpu_addr(11 downto 0); end if;
end if;
end process;
@@ -303,9 +303,9 @@ begin
end process;
-- demux AY chips output
-process (ayx_clock)
+process (clock_14, ayx_clock_en)
begin
- if rising_edge(ayx_clock) then
+ if rising_edge(clock_14) and ayx_clock_en = '1' then
if ay1_audio_chan = "00" then ay1_chan_a <= ay1_audio_muxed; end if;
if ay1_audio_chan = "01" then ay1_chan_b <= ay1_audio_muxed; end if;
if ay1_audio_chan = "10" then ay1_chan_c <= ay1_audio_muxed; end if;
@@ -320,8 +320,8 @@ cpu : entity work.T80se
generic map(Mode => 0, T2Write => 1, IOWait => 1)
port map(
RESET_n => reset_n,
- CLK_n => cpu_clock,
- CLKEN => '1',
+ CLK_n => clock_14,
+ CLKEN => cpu_clock_en,
WAIT_n => '1',
INT_n => cpu_irq_n,
NMI_n => '1',
@@ -385,9 +385,9 @@ port map(
O_IOB => open, -- out std_logic_vector(7 downto 0);
O_IOB_OE_L => open, -- out std_logic;
- ENA => '1', --cpu_ena, -- in std_logic; -- clock enable for higher speed operation
+ ENA => ayx_clock_en, -- in std_logic; -- clock enable for higher speed operation
RESET_L => reset_n, -- in std_logic;
- CLK => ayx_clock -- in std_logic -- note 6 Mhz
+ CLK => clock_14 -- in std_logic
);
-- AY-3-8910 #2
@@ -417,9 +417,9 @@ port map(
O_IOB => open, -- out std_logic_vector(7 downto 0);
O_IOB_OE_L => open, -- out std_logic;
- ENA => '1', --cpu_ena, -- in std_logic; -- clock enable for higher speed operation
+ ENA => ayx_clock_en, -- in std_logic; -- clock enable for higher speed operation
RESET_L => reset_n, -- in std_logic;
- CLK => ayx_clock -- in std_logic -- note 6 Mhz
+ CLK => clock_14 -- in std_logic
);
diff --git a/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/sdram.sv b/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/sdram.sv
new file mode 100644
index 00000000..53a14e5e
--- /dev/null
+++ b/Arcade_MiST/Konami Classic/Pooyan_MiST/rtl/sdram.sv
@@ -0,0 +1,254 @@
+//
+// sdram.v
+//
+// Static RAM controller implementation using SDRAM MT48LC16M16A2
+//
+// Copyright (c) 2015,2016 Sorgelig
+//
+// Some parts of SDRAM code used from project:
+// http://hamsterworks.co.nz/mediawiki/index.php/Simple_SDRAM_Controller
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see .
+//
+// ------------------------------------------
+//
+// v2.1 - Add universal 8/16 bit mode.
+//
+
+module sdram
+(
+ input init, // reset to initialize RAM
+ input clk, // clock ~100MHz
+ //
+ // SDRAM_* - signals to the MT48LC16M16 chip
+ inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus
+ output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus
+ output reg SDRAM_DQML, // two byte masks
+ output reg SDRAM_DQMH, //
+ output reg [1:0] SDRAM_BA, // two banks
+ output SDRAM_nCS, // a single chip select
+ output SDRAM_nWE, // write enable
+ output SDRAM_nRAS, // row address select
+ output SDRAM_nCAS, // columns address select
+ output SDRAM_CKE, // clock enable
+ //
+ input [1:0] wtbt, // 16bit mode: bit1 - write high byte, bit0 - write low byte,
+ // 8bit mode: 2'b00 - use addr[0] to decide which byte to write
+ // Ignored while reading.
+ //
+ input [24:0] addr, // 25 bit address for 8bit mode. addr[0] = 0 for 16bit mode for correct operations.
+ output [15:0] dout, // data output to cpu
+ input [15:0] din, // data input from cpu
+ input we, // cpu requests write
+ input rd, // cpu requests read
+ output reg ready // dout is valid. Ready to accept new read/write.
+);
+
+assign SDRAM_nCS = command[3];
+assign SDRAM_nRAS = command[2];
+assign SDRAM_nCAS = command[1];
+assign SDRAM_nWE = command[0];
+assign SDRAM_CKE = cke;
+
+// no burst configured
+localparam BURST_LENGTH = 3'b000; // 000=1, 001=2, 010=4, 011=8
+localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
+localparam CAS_LATENCY = 3'd2; // 2 for < 100MHz, 3 for >100MHz
+localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed
+localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write
+localparam MODE = {3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
+
+localparam sdram_startup_cycles= 14'd12100;// 100us, plus a little more, @ 100MHz
+localparam cycles_per_refresh = 14'd186; // (64000*24)/8192-1 Calc'd as (64ms @ 24MHz)/8192 rose
+localparam startup_refresh_max = 14'b11111111111111;
+
+// SDRAM commands
+localparam CMD_INHIBIT = 4'b1111;
+localparam CMD_NOP = 4'b0111;
+localparam CMD_ACTIVE = 4'b0011;
+localparam CMD_READ = 4'b0101;
+localparam CMD_WRITE = 4'b0100;
+localparam CMD_BURST_TERMINATE = 4'b0110;
+localparam CMD_PRECHARGE = 4'b0010;
+localparam CMD_AUTO_REFRESH = 4'b0001;
+localparam CMD_LOAD_MODE = 4'b0000;
+
+reg [13:0] refresh_count = startup_refresh_max - sdram_startup_cycles;
+reg [3:0] command = CMD_INHIBIT;
+reg cke = 0;
+reg [24:0] save_addr;
+reg [15:0] data;
+
+assign dout = save_addr[0] ? {data[7:0], data[15:8]} : {data[15:8], data[7:0]};
+typedef enum
+{
+ STATE_STARTUP,
+ STATE_OPEN_1,
+ STATE_WRITE,
+ STATE_READ,
+ STATE_IDLE, STATE_IDLE_1, STATE_IDLE_2, STATE_IDLE_3,
+ STATE_IDLE_4, STATE_IDLE_5, STATE_IDLE_6, STATE_IDLE_7
+} state_t;
+
+state_t state = STATE_STARTUP;
+
+always @(posedge clk) begin
+ reg old_we, old_rd;
+ reg [CAS_LATENCY:0] data_ready_delay;
+
+ reg [15:0] new_data;
+ reg [1:0] new_wtbt;
+ reg new_we;
+ reg new_rd;
+ reg save_we = 1;
+
+
+ command <= CMD_NOP;
+ refresh_count <= refresh_count+1'b1;
+
+ data_ready_delay <= {1'b0, data_ready_delay[CAS_LATENCY:1]};
+
+ if(data_ready_delay[0]) data <= SDRAM_DQ;
+
+ case(state)
+ STATE_STARTUP: begin
+ //------------------------------------------------------------------------
+ //-- This is the initial startup state, where we wait for at least 100us
+ //-- before starting the start sequence
+ //--
+ //-- The initialisation is sequence is
+ //-- * de-assert SDRAM_CKE
+ //-- * 100us wait,
+ //-- * assert SDRAM_CKE
+ //-- * wait at least one cycle,
+ //-- * PRECHARGE
+ //-- * wait 2 cycles
+ //-- * REFRESH,
+ //-- * tREF wait
+ //-- * REFRESH,
+ //-- * tREF wait
+ //-- * LOAD_MODE_REG
+ //-- * 2 cycles wait
+ //------------------------------------------------------------------------
+ cke <= 1;
+ SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
+ SDRAM_DQML <= 1;
+ SDRAM_DQMH <= 1;
+ SDRAM_A <= 0;
+ SDRAM_BA <= 0;
+
+ // All the commands during the startup are NOPS, except these
+ if(refresh_count == startup_refresh_max-31) begin
+ // ensure all rows are closed
+ command <= CMD_PRECHARGE;
+ SDRAM_A[10] <= 1; // all banks
+ SDRAM_BA <= 2'b00;
+ end else if (refresh_count == startup_refresh_max-23) begin
+ // these refreshes need to be at least tREF (66ns) apart
+ command <= CMD_AUTO_REFRESH;
+ end else if (refresh_count == startup_refresh_max-15)
+ command <= CMD_AUTO_REFRESH;
+ else if (refresh_count == startup_refresh_max-7) begin
+ // Now load the mode register
+ command <= CMD_LOAD_MODE;
+ SDRAM_A <= MODE;
+ end
+
+ //------------------------------------------------------
+ //-- if startup is complete then go into idle mode,
+ //-- get prepared to accept a new command, and schedule
+ //-- the first refresh cycle
+ //------------------------------------------------------
+ if(!refresh_count) begin
+ state <= STATE_IDLE;
+ ready <= 1;
+ refresh_count <= 0;
+ end
+ end
+
+ STATE_IDLE_7: state <= STATE_IDLE_6;
+ STATE_IDLE_6: state <= STATE_IDLE_5;
+ STATE_IDLE_5: state <= STATE_IDLE_4;
+ STATE_IDLE_4: state <= STATE_IDLE_3;
+ STATE_IDLE_3: state <= STATE_IDLE_2;
+ STATE_IDLE_2: state <= STATE_IDLE_1;
+ STATE_IDLE_1: begin
+ SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
+ state <= STATE_IDLE;
+ // mask possible refresh to reduce colliding.
+ if(refresh_count > cycles_per_refresh) begin
+ //------------------------------------------------------------------------
+ //-- Start the refresh cycle.
+ //-- This tasks tRFC (66ns), so 2 idle cycles are needed @ 24MHz
+ //------------------------------------------------------------------------
+ state <= STATE_IDLE_2;
+ command <= CMD_AUTO_REFRESH;
+ refresh_count <= refresh_count - cycles_per_refresh + 1'd1;
+ end
+ end
+
+ STATE_IDLE: begin
+ // Priority is to issue a refresh if one is outstanding
+ if(refresh_count > (cycles_per_refresh<<1)) state <= STATE_IDLE_1;
+ else if(new_rd | new_we) begin
+ new_we <= 0;
+ new_rd <= 0;
+ save_addr<= addr;
+ save_we <= new_we;
+ state <= STATE_OPEN_1;
+ command <= CMD_ACTIVE;
+ SDRAM_A <= addr[13:1];
+ SDRAM_BA <= addr[24:23];
+ end
+ end
+
+ // ACTIVE-to-READ or WRITE delay >20ns (1 cycle @ 24 MHz)(-75)
+ STATE_OPEN_1: begin
+ SDRAM_A <= {4'b0010, save_addr[22:14]};
+ SDRAM_DQML <= save_we & (new_wtbt ? ~new_wtbt[0] : save_addr[0]);
+ SDRAM_DQMH <= save_we & (new_wtbt ? ~new_wtbt[1] : ~save_addr[0]);
+ state <= save_we ? STATE_WRITE : STATE_READ;
+ end
+
+ STATE_READ: begin
+ state <= STATE_IDLE_5;
+ command <= CMD_READ;
+ SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
+
+ // Schedule reading the data values off the bus
+ data_ready_delay[CAS_LATENCY] <= 1;
+ end
+
+ STATE_WRITE: begin
+ state <= STATE_IDLE_5;
+ command <= CMD_WRITE;
+ SDRAM_DQ <= new_wtbt ? new_data : {new_data[7:0], new_data[7:0]};
+ ready <= 1;
+ end
+ endcase
+
+ if(init) begin
+ state <= STATE_STARTUP;
+ refresh_count <= startup_refresh_max - sdram_startup_cycles;
+ end
+
+ old_we <= we;
+ old_rd <= rd;
+ if(we & ~old_we) {ready, new_we, new_data, new_wtbt} <= {1'b0, 1'b1, din, wtbt};
+ else
+ if((rd & ~old_rd) || (rd & old_rd & (save_addr != addr))) {ready, new_rd} <= {1'b0, 1'b1};
+
+end
+
+endmodule
diff --git a/Arcade_MiST/Konami Classic/Power_Surge_MiST/Power_Surge.qsf b/Arcade_MiST/Konami Classic/Power_Surge_MiST/Power_Surge.qsf
index 76223b1b..41934ade 100644
--- a/Arcade_MiST/Konami Classic/Power_Surge_MiST/Power_Surge.qsf
+++ b/Arcade_MiST/Konami Classic/Power_Surge_MiST/Power_Surge.qsf
@@ -41,32 +41,10 @@
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:45:13 JUNE 17,2016"
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/Power_Surge_MiST.sv
-set_global_assignment -name VHDL_FILE rtl/power_surge.vhd
-set_global_assignment -name VHDL_FILE rtl/gen_video.vhd
-set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
-set_global_assignment -name VHDL_FILE rtl/time_pilot_sound_board.vhd
-set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd
-set_global_assignment -name VHDL_FILE rtl/rom/power_surge_sprite_grphx.vhd
-set_global_assignment -name VHDL_FILE rtl/rom/power_surge_sprite_color_lut.vhd
-set_global_assignment -name VHDL_FILE rtl/rom/power_surge_sound_prog.vhd
-set_global_assignment -name VHDL_FILE rtl/rom/power_surge_palette_green_red.vhd
-set_global_assignment -name VHDL_FILE rtl/rom/power_surge_palette_blue_green.vhd
-set_global_assignment -name VHDL_FILE rtl/rom/power_surge_char_grphx.vhd
-set_global_assignment -name VHDL_FILE rtl/rom/power_surge_char_color_lut.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80se.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
-set_global_assignment -name VERILOG_FILE rtl/pll.v
-set_global_assignment -name SYSTEMVERILOG_FILE ../../../common/mist/sdram.sv
-set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
# Pin & Location Assignments
# ==========================
@@ -139,6 +117,40 @@ set_location_assignment PIN_66 -to SDRAM_nWE
set_location_assignment PIN_59 -to SDRAM_nCS
set_location_assignment PIN_33 -to SDRAM_CKE
set_location_assignment PIN_43 -to SDRAM_CLK
+set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
+
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
+
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
# Classic Timing Assignments
# ==========================
@@ -172,7 +184,7 @@ set_global_assignment -name ENABLE_NCE_PIN OFF
# EDA Netlist Writer Assignments
# ==============================
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_SIMULATION_TOOL ""
# Assembler Assignments
# =====================
@@ -204,13 +216,30 @@ set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
# Incremental Compilation Assignments
# ===================================
- set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
- set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
- set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(Power_Surge_MiST)
# ----------------------------
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/Power_Surge_MiST.sv
+set_global_assignment -name VHDL_FILE rtl/power_surge.vhd
+set_global_assignment -name VHDL_FILE rtl/gen_video.vhd
+set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
+set_global_assignment -name VHDL_FILE rtl/time_pilot_sound_board.vhd
+set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/power_surge_sprite_grphx.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/power_surge_sprite_color_lut.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/power_surge_sound_prog.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/power_surge_palette_green_red.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/power_surge_palette_blue_green.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/power_surge_char_grphx.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/power_surge_char_color_lut.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
+set_global_assignment -name VERILOG_FILE rtl/pll.v
+set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
+set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Konami Classic/Power_Surge_MiST/Power_Surge.sdc b/Arcade_MiST/Konami Classic/Power_Surge_MiST/Power_Surge.sdc
new file mode 100644
index 00000000..ca3faf31
--- /dev/null
+++ b/Arcade_MiST/Konami Classic/Power_Surge_MiST/Power_Surge.sdc
@@ -0,0 +1,138 @@
+## Generated SDC file "vectrex_MiST.out.sdc"
+
+## Copyright (C) 1991-2013 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions
+## and other software and tools, and its AMPP partner logic
+## functions, and any output files from any of the foregoing
+## (including device programming or simulation files), and any
+## associated documentation or information are expressly subject
+## to the terms and conditions of the Altera Program License
+## Subscription Agreement, Altera MegaCore Function License
+## Agreement, or other applicable license agreement, including,
+## without limitation, that your use is for the sole purpose of
+## programming logic devices manufactured by Altera and sold by
+## Altera or its authorized distributors. Please refer to the
+## applicable agreement for further details.
+
+
+## VENDOR "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+## DATE "Sun Jun 24 12:53:00 2018"
+
+##
+## DEVICE "EP3C25E144C8"
+##
+
+# Clock constraints
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
+
+set sys_clk "pll|altpll_component|auto_generated|pll1|clk[1]"
+set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
+set snd_clk "pll|altpll_component|auto_generated|pll1|clk[2]"
+set vid_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}]
+set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}]
+set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}]
+set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}]
+set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}]
+set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}]
+
+set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]]
+set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]]
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
+set_output_delay -add_delay -clock_fall -clock [get_clocks $snd_clk] 1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay -clock_fall -clock [get_clocks $snd_clk] 1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {LED}]
+set_output_delay -add_delay -clock_fall -clock [get_clocks $vid_clk] 1.000 [get_ports {VGA_*}]
+
+set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
+# audio-main cpu clocks are asynchronous
+set_clock_groups -asynchronous -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[3]}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}]
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+set_multicycle_path -to {VGA_*[*]} -setup 2
+set_multicycle_path -to {VGA_*[*]} -hold 1
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
diff --git a/Arcade_MiST/Konami Classic/Power_Surge_MiST/Power_Surge.srf b/Arcade_MiST/Konami Classic/Power_Surge_MiST/Power_Surge.srf
deleted file mode 100644
index e413eda9..00000000
--- a/Arcade_MiST/Konami Classic/Power_Surge_MiST/Power_Surge.srf
+++ /dev/null
@@ -1 +0,0 @@
-{ "" "" "" "*" { } { } 0 10492 "" 0 0 "Quartus II" 0 -1 0 ""}
diff --git a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/Power_Surge_MiST.sv b/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/Power_Surge_MiST.sv
index 5ce11996..cff34b2d 100644
--- a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/Power_Surge_MiST.sv
+++ b/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/Power_Surge_MiST.sv
@@ -58,23 +58,28 @@ localparam CONF_STR = {
"PSURGE;;",
"O2,Rotate Controls,Off,On;",
"O34,Scanlines,Off,25%,50%,75%;",
- "T6,Reset;",
- "V,v1.10.",`BUILD_DATE
+ "O5,Blend,Off,On;",
+ "T0,Reset;",
+ "V,v1.15.",`BUILD_DATE
};
-assign LED = 1;
-assign AUDIO_R = AUDIO_L;
-assign SDRAM_CLK = clock_48;
+wire rotate = status[2];
+wire [1:0] scanlines = status[4:3];
+wire blend = status[5];
-wire clock_48, clock_12, clock_14, pll_locked;
+assign LED = 1;
+assign AUDIO_R = AUDIO_L;
+assign SDRAM_CLK = clock_48;
+
+wire clock_48, clock_12, clock_6, clock_14, pll_locked;
pll pll(
.inclk0(CLOCK_27),
.c0(clock_48),//24,57600000
.c1(clock_12),//12.28800000
.c2(clock_14),//14.31800000
+ .c3(clock_6),
.locked(pll_locked)
- );
-
+);
wire [31:0] status;
wire [1:0] buttons;
@@ -128,14 +133,15 @@ sdram rom(
reg reset = 1;
reg rom_loaded = 0;
-always @(posedge clock_48) begin
+always @(posedge clock_12) begin
reg ioctl_downlD;
ioctl_downlD <= ioctl_downl;
if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1;
- reset <= status[0] | buttons[1] | status[6] | ~rom_loaded;
+ reset <= status[0] | buttons[1] | ~rom_loaded;
end
power_surge power_surge(
+ .clock_6(clock_6),
.clock_12(clock_12),
.clock_14(clock_14),
.reset(reset),
@@ -150,22 +156,22 @@ power_surge power_surge(
.roms_addr(rom_addr),
.roms_do(rom_do[7:0]),
.roms_rd(rom_rd),
- .dip_switch_1("01111000"), // Cabinet Unknown Lives Lives Initial_Energy Unknown Unknown Unknown
- .dip_switch_2("11100000"), // Stop_at_Junctions, Unknown, Unknown, Cheat, Coin_B Coin_B Coin_A Coin_A
- .start2(btn_two_players),
- .start1(btn_one_player),
- .coin1(btn_coin),
+ .dip_switch_1(8'b0111_1000), // Cabinet Unknown Lives Lives Initial_Energy Unknown Unknown Unknown
+ .dip_switch_2(8'b1110_0000), // Stop_at_Junctions, Unknown, Unknown, Cheat, Coin_B Coin_B Coin_A Coin_A
+ .start2(m_two_players),
+ .start1(m_one_player),
+ .coin1(m_coin1),
- .fire1(m_fire),
+ .fire1(m_fireA),
.right1(m_right),
.left1(m_left),
.down1(m_down),
.up1(m_up),
- .fire2(m_fire),
- .right2(m_right),
- .left2(m_left),
- .down2(m_down),
- .up2(m_up)
+ .fire2(m_fire2A),
+ .right2(m_right2),
+ .left2(m_left2),
+ .down2(m_down2),
+ .up2(m_up2)
);
mist_video #(.COLOR_DEPTH(5), .SD_HCNT_WIDTH(10)) mist_video(//Wrong Colors have no Idea
@@ -173,9 +179,9 @@ mist_video #(.COLOR_DEPTH(5), .SD_HCNT_WIDTH(10)) mist_video(//Wrong Colors have
.SPI_SCK ( SPI_SCK ),
.SPI_SS3 ( SPI_SS3 ),
.SPI_DI ( SPI_DI ),
- .R ( blankn ? r : 0 ),
- .G ( blankn ? g : 0 ),
- .B ( blankn ? b : 0 ),
+ .R ( r ),
+ .G ( g ),
+ .B ( b ),
.HSync ( hs ),
.VSync ( vs ),
.VGA_R ( VGA_R ),
@@ -183,15 +189,15 @@ mist_video #(.COLOR_DEPTH(5), .SD_HCNT_WIDTH(10)) mist_video(//Wrong Colors have
.VGA_B ( VGA_B ),
.VGA_VS ( VGA_VS ),
.VGA_HS ( VGA_HS ),
-// .ce_divider(0),
- .rotate ( {1'b0,status[2]} ),
+ .rotate ( { 1'b0, rotate } ),
.scandoubler_disable( scandoublerD ),
- .scanlines ( status[4:3] ),
+ .scanlines ( scanlines ),
+ .blend ( blend ),
.ypbpr ( ypbpr )
);
user_io #(.STRLEN(($size(CONF_STR)>>3)))user_io(
- .clk_sys (clock_48 ),
+ .clk_sys (clock_12 ),
.conf_str (CONF_STR ),
.SPI_CLK (SPI_SCK ),
.SPI_SS_IO (CONF_DATA0 ),
@@ -210,47 +216,31 @@ user_io #(.STRLEN(($size(CONF_STR)>>3)))user_io(
);
dac #(.C_bits(16))dac(
- .clk_i(clock_48),
+ .clk_i(clock_14),
.res_n_i(1),
.dac_i({audio, 5'b00000}),
.dac_o(AUDIO_L)
);
-wire m_up = ~status[2] ? btn_right | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3];
-wire m_down = ~status[2] ? btn_left | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2];
-wire m_left = ~status[2] ? btn_up | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1];
-wire m_right = ~status[2] ? btn_down | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0];
-wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4];
-//wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5];
-
-reg btn_one_player = 0;
-reg btn_two_players = 0;
-reg btn_left = 0;
-reg btn_right = 0;
-reg btn_down = 0;
-reg btn_up = 0;
-reg btn_fire1 = 0;
-//reg btn_fire2 = 0;
-//reg btn_fire3 = 0;
-reg btn_coin = 0;
-
-always @(posedge clock_48) begin
- reg old_state;
- old_state <= key_strobe;
- if(old_state != key_strobe) begin
- case(key_code)
- 'h75: btn_up <= key_pressed; // up
- 'h72: btn_down <= key_pressed; // down
- 'h6B: btn_left <= key_pressed; // left
- 'h74: btn_right <= key_pressed; // right
- 'h76: btn_coin <= key_pressed; // ESC
- 'h05: btn_one_player <= key_pressed; // F1
- 'h06: btn_two_players <= key_pressed; // F2
-// 'h14: btn_fire3 <= key_pressed; // ctrl
-// 'h11: btn_fire2 <= key_pressed; // alt
- 'h29: btn_fire1 <= key_pressed; // Space
- endcase
- end
-end
+// Arcade inputs
+wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
+wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
+wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
+
+arcade_inputs inputs (
+ .clk ( clock_12 ),
+ .key_strobe ( key_strobe ),
+ .key_pressed ( key_pressed ),
+ .key_code ( key_code ),
+ .joystick_0 ( joystick_0 ),
+ .joystick_1 ( joystick_1 ),
+ .rotate ( rotate ),
+ .orientation ( 2'b01 ),
+ .joyswap ( 1'b0 ),
+ .oneplayer ( 1'b1 ),
+ .controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
+ .player1 ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
+ .player2 ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
+);
endmodule
\ No newline at end of file
diff --git a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/T80/T80.vhd
deleted file mode 100644
index 398fa0df..00000000
--- a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/T80/T80.vhd
+++ /dev/null
@@ -1,1073 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
--- 0208 : First complete release
---
--- 0210 : Fixed wait and halt
---
--- 0211 : Fixed Refresh addition and IM 1
---
--- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
--- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
--- 0235 : Added clock enable and IM 2 fix by Mike Johnson
---
--- 0237 : Changed 8080 I/O address output, added IntE output
---
--- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
--- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
--- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
--- 0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
- generic(
- Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
- IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
- Flag_C : integer := 0;
- Flag_N : integer := 1;
- Flag_P : integer := 2;
- Flag_X : integer := 3;
- Flag_H : integer := 4;
- Flag_Y : integer := 5;
- Flag_Z : integer := 6;
- Flag_S : integer := 7
- );
- port(
- RESET_n : in std_logic;
- CLK_n : in std_logic;
- CEN : in std_logic;
- WAIT_n : in std_logic;
- INT_n : in std_logic;
- NMI_n : in std_logic;
- BUSRQ_n : in std_logic;
- M1_n : out std_logic;
- IORQ : out std_logic;
- NoRead : out std_logic;
- Write : out std_logic;
- RFSH_n : out std_logic;
- HALT_n : out std_logic;
- BUSAK_n : out std_logic;
- A : out std_logic_vector(15 downto 0);
- DInst : in std_logic_vector(7 downto 0);
- DI : in std_logic_vector(7 downto 0);
- DO : out std_logic_vector(7 downto 0);
- MC : out std_logic_vector(2 downto 0);
- TS : out std_logic_vector(2 downto 0);
- IntCycle_n : out std_logic;
- IntE : out std_logic;
- Stop : out std_logic
- );
-end T80;
-
-architecture rtl of T80 is
-
- constant aNone : std_logic_vector(2 downto 0) := "111";
- constant aBC : std_logic_vector(2 downto 0) := "000";
- constant aDE : std_logic_vector(2 downto 0) := "001";
- constant aXY : std_logic_vector(2 downto 0) := "010";
- constant aIOA : std_logic_vector(2 downto 0) := "100";
- constant aSP : std_logic_vector(2 downto 0) := "101";
- constant aZI : std_logic_vector(2 downto 0) := "110";
-
- -- Registers
- signal ACC, F : std_logic_vector(7 downto 0);
- signal Ap, Fp : std_logic_vector(7 downto 0);
- signal I : std_logic_vector(7 downto 0);
- signal R : unsigned(7 downto 0);
- signal SP, PC : unsigned(15 downto 0);
- signal RegDIH : std_logic_vector(7 downto 0);
- signal RegDIL : std_logic_vector(7 downto 0);
- signal RegBusA : std_logic_vector(15 downto 0);
- signal RegBusB : std_logic_vector(15 downto 0);
- signal RegBusC : std_logic_vector(15 downto 0);
- signal RegAddrA_r : std_logic_vector(2 downto 0);
- signal RegAddrA : std_logic_vector(2 downto 0);
- signal RegAddrB_r : std_logic_vector(2 downto 0);
- signal RegAddrB : std_logic_vector(2 downto 0);
- signal RegAddrC : std_logic_vector(2 downto 0);
- signal RegWEH : std_logic;
- signal RegWEL : std_logic;
- signal Alternate : std_logic;
-
- -- Help Registers
- signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register
- signal IR : std_logic_vector(7 downto 0); -- Instruction register
- signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector
- signal RegBusA_r : std_logic_vector(15 downto 0);
-
- signal ID16 : signed(15 downto 0);
- signal Save_Mux : std_logic_vector(7 downto 0);
-
- signal TState : unsigned(2 downto 0);
- signal MCycle : std_logic_vector(2 downto 0);
- signal IntE_FF1 : std_logic;
- signal IntE_FF2 : std_logic;
- signal Halt_FF : std_logic;
- signal BusReq_s : std_logic;
- signal BusAck : std_logic;
- signal ClkEn : std_logic;
- signal NMI_s : std_logic;
- signal INT_s : std_logic;
- signal IStatus : std_logic_vector(1 downto 0);
-
- signal DI_Reg : std_logic_vector(7 downto 0);
- signal T_Res : std_logic;
- signal XY_State : std_logic_vector(1 downto 0);
- signal Pre_XY_F_M : std_logic_vector(2 downto 0);
- signal NextIs_XY_Fetch : std_logic;
- signal XY_Ind : std_logic;
- signal No_BTR : std_logic;
- signal BTR_r : std_logic;
- signal Auto_Wait : std_logic;
- signal Auto_Wait_t1 : std_logic;
- signal Auto_Wait_t2 : std_logic;
- signal IncDecZ : std_logic;
-
- -- ALU signals
- signal BusB : std_logic_vector(7 downto 0);
- signal BusA : std_logic_vector(7 downto 0);
- signal ALU_Q : std_logic_vector(7 downto 0);
- signal F_Out : std_logic_vector(7 downto 0);
-
- -- Registered micro code outputs
- signal Read_To_Reg_r : std_logic_vector(4 downto 0);
- signal Arith16_r : std_logic;
- signal Z16_r : std_logic;
- signal ALU_Op_r : std_logic_vector(3 downto 0);
- signal Save_ALU_r : std_logic;
- signal PreserveC_r : std_logic;
- signal MCycles : std_logic_vector(2 downto 0);
-
- -- Micro code outputs
- signal MCycles_d : std_logic_vector(2 downto 0);
- signal TStates : std_logic_vector(2 downto 0);
- signal IntCycle : std_logic;
- signal NMICycle : std_logic;
- signal Inc_PC : std_logic;
- signal Inc_WZ : std_logic;
- signal IncDec_16 : std_logic_vector(3 downto 0);
- signal Prefix : std_logic_vector(1 downto 0);
- signal Read_To_Acc : std_logic;
- signal Read_To_Reg : std_logic;
- signal Set_BusB_To : std_logic_vector(3 downto 0);
- signal Set_BusA_To : std_logic_vector(3 downto 0);
- signal ALU_Op : std_logic_vector(3 downto 0);
- signal Save_ALU : std_logic;
- signal PreserveC : std_logic;
- signal Arith16 : std_logic;
- signal Set_Addr_To : std_logic_vector(2 downto 0);
- signal Jump : std_logic;
- signal JumpE : std_logic;
- signal JumpXY : std_logic;
- signal Call : std_logic;
- signal RstP : std_logic;
- signal LDZ : std_logic;
- signal LDW : std_logic;
- signal LDSPHL : std_logic;
- signal IORQ_i : std_logic;
- signal Special_LD : std_logic_vector(2 downto 0);
- signal ExchangeDH : std_logic;
- signal ExchangeRp : std_logic;
- signal ExchangeAF : std_logic;
- signal ExchangeRS : std_logic;
- signal I_DJNZ : std_logic;
- signal I_CPL : std_logic;
- signal I_CCF : std_logic;
- signal I_SCF : std_logic;
- signal I_RETN : std_logic;
- signal I_BT : std_logic;
- signal I_BC : std_logic;
- signal I_BTR : std_logic;
- signal I_RLD : std_logic;
- signal I_RRD : std_logic;
- signal I_INRC : std_logic;
- signal SetDI : std_logic;
- signal SetEI : std_logic;
- signal IMode : std_logic_vector(1 downto 0);
- signal Halt : std_logic;
-
-begin
-
- mcode : T80_MCode
- generic map(
- Mode => Mode,
- Flag_C => Flag_C,
- Flag_N => Flag_N,
- Flag_P => Flag_P,
- Flag_X => Flag_X,
- Flag_H => Flag_H,
- Flag_Y => Flag_Y,
- Flag_Z => Flag_Z,
- Flag_S => Flag_S)
- port map(
- IR => IR,
- ISet => ISet,
- MCycle => MCycle,
- F => F,
- NMICycle => NMICycle,
- IntCycle => IntCycle,
- MCycles => MCycles_d,
- TStates => TStates,
- Prefix => Prefix,
- Inc_PC => Inc_PC,
- Inc_WZ => Inc_WZ,
- IncDec_16 => IncDec_16,
- Read_To_Acc => Read_To_Acc,
- Read_To_Reg => Read_To_Reg,
- Set_BusB_To => Set_BusB_To,
- Set_BusA_To => Set_BusA_To,
- ALU_Op => ALU_Op,
- Save_ALU => Save_ALU,
- PreserveC => PreserveC,
- Arith16 => Arith16,
- Set_Addr_To => Set_Addr_To,
- IORQ => IORQ_i,
- Jump => Jump,
- JumpE => JumpE,
- JumpXY => JumpXY,
- Call => Call,
- RstP => RstP,
- LDZ => LDZ,
- LDW => LDW,
- LDSPHL => LDSPHL,
- Special_LD => Special_LD,
- ExchangeDH => ExchangeDH,
- ExchangeRp => ExchangeRp,
- ExchangeAF => ExchangeAF,
- ExchangeRS => ExchangeRS,
- I_DJNZ => I_DJNZ,
- I_CPL => I_CPL,
- I_CCF => I_CCF,
- I_SCF => I_SCF,
- I_RETN => I_RETN,
- I_BT => I_BT,
- I_BC => I_BC,
- I_BTR => I_BTR,
- I_RLD => I_RLD,
- I_RRD => I_RRD,
- I_INRC => I_INRC,
- SetDI => SetDI,
- SetEI => SetEI,
- IMode => IMode,
- Halt => Halt,
- NoRead => NoRead,
- Write => Write);
-
- alu : T80_ALU
- generic map(
- Mode => Mode,
- Flag_C => Flag_C,
- Flag_N => Flag_N,
- Flag_P => Flag_P,
- Flag_X => Flag_X,
- Flag_H => Flag_H,
- Flag_Y => Flag_Y,
- Flag_Z => Flag_Z,
- Flag_S => Flag_S)
- port map(
- Arith16 => Arith16_r,
- Z16 => Z16_r,
- ALU_Op => ALU_Op_r,
- IR => IR(5 downto 0),
- ISet => ISet,
- BusA => BusA,
- BusB => BusB,
- F_In => F,
- Q => ALU_Q,
- F_Out => F_Out);
-
- ClkEn <= CEN and not BusAck;
-
- T_Res <= '1' when TState = unsigned(TStates) else '0';
-
- NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
- ((Set_Addr_To = aXY) or
- (MCycle = "001" and IR = "11001011") or
- (MCycle = "001" and IR = "00110110")) else '0';
-
- Save_Mux <= BusB when ExchangeRp = '1' else
- DI_Reg when Save_ALU_r = '0' else
- ALU_Q;
-
- process (RESET_n, CLK_n)
- begin
- if RESET_n = '0' then
- PC <= (others => '0'); -- Program Counter
- A <= (others => '0');
- TmpAddr <= (others => '0');
- IR <= "00000000";
- ISet <= "00";
- XY_State <= "00";
- IStatus <= "00";
- MCycles <= "000";
- DO <= "00000000";
-
- ACC <= (others => '1');
- F <= (others => '1');
- Ap <= (others => '1');
- Fp <= (others => '1');
- I <= (others => '0');
- R <= (others => '0');
- SP <= (others => '1');
- Alternate <= '0';
-
- Read_To_Reg_r <= "00000";
- F <= (others => '1');
- Arith16_r <= '0';
- BTR_r <= '0';
- Z16_r <= '0';
- ALU_Op_r <= "0000";
- Save_ALU_r <= '0';
- PreserveC_r <= '0';
- XY_Ind <= '0';
-
- elsif CLK_n'event and CLK_n = '1' then
-
- if ClkEn = '1' then
-
- ALU_Op_r <= "0000";
- Save_ALU_r <= '0';
- Read_To_Reg_r <= "00000";
-
- MCycles <= MCycles_d;
-
- if IMode /= "11" then
- IStatus <= IMode;
- end if;
-
- Arith16_r <= Arith16;
- PreserveC_r <= PreserveC;
- if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
- Z16_r <= '1';
- else
- Z16_r <= '0';
- end if;
-
- if MCycle = "001" and TState(2) = '0' then
- -- MCycle = 1 and TState = 1, 2, or 3
-
- if TState = 2 and Wait_n = '1' then
- if Mode < 2 then
- A(7 downto 0) <= std_logic_vector(R);
- A(15 downto 8) <= I;
- R(6 downto 0) <= R(6 downto 0) + 1;
- end if;
-
- if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
- PC <= PC + 1;
- end if;
-
- if IntCycle = '1' and IStatus = "01" then
- IR <= "11111111";
- elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
- IR <= "00000000";
- else
- IR <= DInst;
- end if;
-
- ISet <= "00";
- if Prefix /= "00" then
- if Prefix = "11" then
- if IR(5) = '1' then
- XY_State <= "10";
- else
- XY_State <= "01";
- end if;
- else
- if Prefix = "10" then
- XY_State <= "00";
- XY_Ind <= '0';
- end if;
- ISet <= Prefix;
- end if;
- else
- XY_State <= "00";
- XY_Ind <= '0';
- end if;
- end if;
-
- else
- -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
- if MCycle = "110" then
- XY_Ind <= '1';
- if Prefix = "01" then
- ISet <= "01";
- end if;
- end if;
-
- if T_Res = '1' then
- BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
- if Jump = '1' then
- A(15 downto 8) <= DI_Reg;
- A(7 downto 0) <= TmpAddr(7 downto 0);
- PC(15 downto 8) <= unsigned(DI_Reg);
- PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
- elsif JumpXY = '1' then
- A <= RegBusC;
- PC <= unsigned(RegBusC);
- elsif Call = '1' or RstP = '1' then
- A <= TmpAddr;
- PC <= unsigned(TmpAddr);
- elsif MCycle = MCycles and NMICycle = '1' then
- A <= "0000000001100110";
- PC <= "0000000001100110";
- elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
- A(15 downto 8) <= I;
- A(7 downto 0) <= TmpAddr(7 downto 0);
- PC(15 downto 8) <= unsigned(I);
- PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
- else
- case Set_Addr_To is
- when aXY =>
- if XY_State = "00" then
- A <= RegBusC;
- else
- if NextIs_XY_Fetch = '1' then
- A <= std_logic_vector(PC);
- else
- A <= TmpAddr;
- end if;
- end if;
- when aIOA =>
- if Mode = 3 then
- -- Memory map I/O on GBZ80
- A(15 downto 8) <= (others => '1');
- elsif Mode = 2 then
- -- Duplicate I/O address on 8080
- A(15 downto 8) <= DI_Reg;
- else
- A(15 downto 8) <= ACC;
- end if;
- A(7 downto 0) <= DI_Reg;
- when aSP =>
- A <= std_logic_vector(SP);
- when aBC =>
- if Mode = 3 and IORQ_i = '1' then
- -- Memory map I/O on GBZ80
- A(15 downto 8) <= (others => '1');
- A(7 downto 0) <= RegBusC(7 downto 0);
- else
- A <= RegBusC;
- end if;
- when aDE =>
- A <= RegBusC;
- when aZI =>
- if Inc_WZ = '1' then
- A <= std_logic_vector(unsigned(TmpAddr) + 1);
- else
- A(15 downto 8) <= DI_Reg;
- A(7 downto 0) <= TmpAddr(7 downto 0);
- end if;
- when others =>
- A <= std_logic_vector(PC);
- end case;
- end if;
-
- Save_ALU_r <= Save_ALU;
- ALU_Op_r <= ALU_Op;
-
- if I_CPL = '1' then
- -- CPL
- ACC <= not ACC;
- F(Flag_Y) <= not ACC(5);
- F(Flag_H) <= '1';
- F(Flag_X) <= not ACC(3);
- F(Flag_N) <= '1';
- end if;
- if I_CCF = '1' then
- -- CCF
- F(Flag_C) <= not F(Flag_C);
- F(Flag_Y) <= ACC(5);
- F(Flag_H) <= F(Flag_C);
- F(Flag_X) <= ACC(3);
- F(Flag_N) <= '0';
- end if;
- if I_SCF = '1' then
- -- SCF
- F(Flag_C) <= '1';
- F(Flag_Y) <= ACC(5);
- F(Flag_H) <= '0';
- F(Flag_X) <= ACC(3);
- F(Flag_N) <= '0';
- end if;
- end if;
-
- if TState = 2 and Wait_n = '1' then
- if ISet = "01" and MCycle = "111" then
- IR <= DInst;
- end if;
- if JumpE = '1' then
- PC <= unsigned(signed(PC) + signed(DI_Reg));
- elsif Inc_PC = '1' then
- PC <= PC + 1;
- end if;
- if BTR_r = '1' then
- PC <= PC - 2;
- end if;
- if RstP = '1' then
- TmpAddr <= (others =>'0');
- TmpAddr(5 downto 3) <= IR(5 downto 3);
- end if;
- end if;
- if TState = 3 and MCycle = "110" then
- TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
- end if;
-
- if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
- if IncDec_16(2 downto 0) = "111" then
- if IncDec_16(3) = '1' then
- SP <= SP - 1;
- else
- SP <= SP + 1;
- end if;
- end if;
- end if;
-
- if LDSPHL = '1' then
- SP <= unsigned(RegBusC);
- end if;
- if ExchangeAF = '1' then
- Ap <= ACC;
- ACC <= Ap;
- Fp <= F;
- F <= Fp;
- end if;
- if ExchangeRS = '1' then
- Alternate <= not Alternate;
- end if;
- end if;
-
- if TState = 3 then
- if LDZ = '1' then
- TmpAddr(7 downto 0) <= DI_Reg;
- end if;
- if LDW = '1' then
- TmpAddr(15 downto 8) <= DI_Reg;
- end if;
-
- if Special_LD(2) = '1' then
- case Special_LD(1 downto 0) is
- when "00" =>
- ACC <= I;
- F(Flag_P) <= IntE_FF2;
- when "01" =>
- ACC <= std_logic_vector(R);
- F(Flag_P) <= IntE_FF2;
- when "10" =>
- I <= ACC;
- when others =>
- R <= unsigned(ACC);
- end case;
- end if;
- end if;
-
- if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
- if Mode = 3 then
- F(6) <= F_Out(6);
- F(5) <= F_Out(5);
- F(7) <= F_Out(7);
- if PreserveC_r = '0' then
- F(4) <= F_Out(4);
- end if;
- else
- F(7 downto 1) <= F_Out(7 downto 1);
- if PreserveC_r = '0' then
- F(Flag_C) <= F_Out(0);
- end if;
- end if;
- end if;
- if T_Res = '1' and I_INRC = '1' then
- F(Flag_H) <= '0';
- F(Flag_N) <= '0';
- if DI_Reg(7 downto 0) = "00000000" then
- F(Flag_Z) <= '1';
- else
- F(Flag_Z) <= '0';
- end if;
- F(Flag_S) <= DI_Reg(7);
- F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
- DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
- end if;
-
- if TState = 1 and Auto_Wait_t1 = '0' then
- DO <= BusB;
- if I_RLD = '1' then
- DO(3 downto 0) <= BusA(3 downto 0);
- DO(7 downto 4) <= BusB(3 downto 0);
- end if;
- if I_RRD = '1' then
- DO(3 downto 0) <= BusB(7 downto 4);
- DO(7 downto 4) <= BusA(3 downto 0);
- end if;
- end if;
-
- if T_Res = '1' then
- Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
- Read_To_Reg_r(4) <= Read_To_Reg;
- if Read_To_Acc = '1' then
- Read_To_Reg_r(3 downto 0) <= "0111";
- Read_To_Reg_r(4) <= '1';
- end if;
- end if;
-
- if TState = 1 and I_BT = '1' then
- F(Flag_X) <= ALU_Q(3);
- F(Flag_Y) <= ALU_Q(1);
- F(Flag_H) <= '0';
- F(Flag_N) <= '0';
- end if;
- if I_BC = '1' or I_BT = '1' then
- F(Flag_P) <= IncDecZ;
- end if;
-
- if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or
- (Save_ALU_r = '1' and ALU_OP_r /= "0111") then
- case Read_To_Reg_r is
- when "10111" =>
- ACC <= Save_Mux;
- when "10110" =>
- DO <= Save_Mux;
- when "11000" =>
- SP(7 downto 0) <= unsigned(Save_Mux);
- when "11001" =>
- SP(15 downto 8) <= unsigned(Save_Mux);
- when "11011" =>
- F <= Save_Mux;
- when others =>
- end case;
- end if;
-
- end if;
-
- end if;
-
- end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
- process (CLK_n)
- begin
- if CLK_n'event and CLK_n = '1' then
- if ClkEn = '1' then
- -- Bus A / Write
- RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
- if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
- RegAddrA_r <= XY_State(1) & "11";
- end if;
-
- -- Bus B
- RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
- if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
- RegAddrB_r <= XY_State(1) & "11";
- end if;
-
- -- Address from register
- RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
- -- Jump (HL), LD SP,HL
- if (JumpXY = '1' or LDSPHL = '1') then
- RegAddrC <= Alternate & "10";
- end if;
- if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
- RegAddrC <= XY_State(1) & "11";
- end if;
-
- if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
- IncDecZ <= F_Out(Flag_Z);
- end if;
- if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
- if ID16 = 0 then
- IncDecZ <= '0';
- else
- IncDecZ <= '1';
- end if;
- end if;
-
- RegBusA_r <= RegBusA;
- end if;
- end if;
- end process;
-
- RegAddrA <=
- -- 16 bit increment/decrement
- Alternate & IncDec_16(1 downto 0) when (TState = 2 or
- (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
- XY_State(1) & "11" when (TState = 2 or
- (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
- -- EX HL,DL
- Alternate & "10" when ExchangeDH = '1' and TState = 3 else
- Alternate & "01" when ExchangeDH = '1' and TState = 4 else
- -- Bus A / Write
- RegAddrA_r;
-
- RegAddrB <=
- -- EX HL,DL
- Alternate & "01" when ExchangeDH = '1' and TState = 3 else
- -- Bus B
- RegAddrB_r;
-
- ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
- signed(RegBusA) + 1;
-
- process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
- ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
- begin
- RegWEH <= '0';
- RegWEL <= '0';
- if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or
- (Save_ALU_r = '1' and ALU_OP_r /= "0111") then
- case Read_To_Reg_r is
- when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
- RegWEH <= not Read_To_Reg_r(0);
- RegWEL <= Read_To_Reg_r(0);
- when others =>
- end case;
- end if;
-
- if ExchangeDH = '1' and (TState = 3 or TState = 4) then
- RegWEH <= '1';
- RegWEL <= '1';
- end if;
-
- if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
- case IncDec_16(1 downto 0) is
- when "00" | "01" | "10" =>
- RegWEH <= '1';
- RegWEL <= '1';
- when others =>
- end case;
- end if;
- end process;
-
- process (Save_Mux, RegBusB, RegBusA_r, ID16,
- ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
- begin
- RegDIH <= Save_Mux;
- RegDIL <= Save_Mux;
-
- if ExchangeDH = '1' and TState = 3 then
- RegDIH <= RegBusB(15 downto 8);
- RegDIL <= RegBusB(7 downto 0);
- end if;
- if ExchangeDH = '1' and TState = 4 then
- RegDIH <= RegBusA_r(15 downto 8);
- RegDIL <= RegBusA_r(7 downto 0);
- end if;
-
- if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
- RegDIH <= std_logic_vector(ID16(15 downto 8));
- RegDIL <= std_logic_vector(ID16(7 downto 0));
- end if;
- end process;
-
- Regs : T80_Reg
- port map(
- Clk => CLK_n,
- CEN => ClkEn,
- WEH => RegWEH,
- WEL => RegWEL,
- AddrA => RegAddrA,
- AddrB => RegAddrB,
- AddrC => RegAddrC,
- DIH => RegDIH,
- DIL => RegDIL,
- DOAH => RegBusA(15 downto 8),
- DOAL => RegBusA(7 downto 0),
- DOBH => RegBusB(15 downto 8),
- DOBL => RegBusB(7 downto 0),
- DOCH => RegBusC(15 downto 8),
- DOCL => RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
- process (CLK_n)
- begin
- if CLK_n'event and CLK_n = '1' then
- if ClkEn = '1' then
- case Set_BusB_To is
- when "0111" =>
- BusB <= ACC;
- when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
- if Set_BusB_To(0) = '1' then
- BusB <= RegBusB(7 downto 0);
- else
- BusB <= RegBusB(15 downto 8);
- end if;
- when "0110" =>
- BusB <= DI_Reg;
- when "1000" =>
- BusB <= std_logic_vector(SP(7 downto 0));
- when "1001" =>
- BusB <= std_logic_vector(SP(15 downto 8));
- when "1010" =>
- BusB <= "00000001";
- when "1011" =>
- BusB <= F;
- when "1100" =>
- BusB <= std_logic_vector(PC(7 downto 0));
- when "1101" =>
- BusB <= std_logic_vector(PC(15 downto 8));
- when "1110" =>
- BusB <= "00000000";
- when others =>
- BusB <= "--------";
- end case;
-
- case Set_BusA_To is
- when "0111" =>
- BusA <= ACC;
- when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
- if Set_BusA_To(0) = '1' then
- BusA <= RegBusA(7 downto 0);
- else
- BusA <= RegBusA(15 downto 8);
- end if;
- when "0110" =>
- BusA <= DI_Reg;
- when "1000" =>
- BusA <= std_logic_vector(SP(7 downto 0));
- when "1001" =>
- BusA <= std_logic_vector(SP(15 downto 8));
- when "1010" =>
- BusA <= "00000000";
- when others =>
- BusB <= "--------";
- end case;
- end if;
- end if;
- end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
- process (RESET_n,CLK_n)
- begin
- if RESET_n = '0' then
- RFSH_n <= '1';
- elsif CLK_n'event and CLK_n = '1' then
- if CEN = '1' then
- if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then
- RFSH_n <= '0';
- else
- RFSH_n <= '1';
- end if;
- end if;
- end if;
- end process;
-
- MC <= std_logic_vector(MCycle);
- TS <= std_logic_vector(TState);
- DI_Reg <= DI;
- HALT_n <= not Halt_FF;
- BUSAK_n <= not BusAck;
- IntCycle_n <= not IntCycle;
- IntE <= IntE_FF1;
- IORQ <= IORQ_i;
- Stop <= I_DJNZ;
-
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
- process (RESET_n, CLK_n)
- variable OldNMI_n : std_logic;
- begin
- if RESET_n = '0' then
- BusReq_s <= '0';
- INT_s <= '0';
- NMI_s <= '0';
- OldNMI_n := '0';
- elsif CLK_n'event and CLK_n = '1' then
- if CEN = '1' then
- BusReq_s <= not BUSRQ_n;
- INT_s <= not INT_n;
- if NMICycle = '1' then
- NMI_s <= '0';
- elsif NMI_n = '0' and OldNMI_n = '1' then
- NMI_s <= '1';
- end if;
- OldNMI_n := NMI_n;
- end if;
- end if;
- end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
- process (RESET_n, CLK_n)
- begin
- if RESET_n = '0' then
- MCycle <= "001";
- TState <= "000";
- Pre_XY_F_M <= "000";
- Halt_FF <= '0';
- BusAck <= '0';
- NMICycle <= '0';
- IntCycle <= '0';
- IntE_FF1 <= '0';
- IntE_FF2 <= '0';
- No_BTR <= '0';
- Auto_Wait_t1 <= '0';
- Auto_Wait_t2 <= '0';
- M1_n <= '1';
- elsif CLK_n'event and CLK_n = '1' then
- if CEN = '1' then
- if T_Res = '1' then
- Auto_Wait_t1 <= '0';
- else
- Auto_Wait_t1 <= Auto_Wait or IORQ_i;
- end if;
- Auto_Wait_t2 <= Auto_Wait_t1;
- No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
- (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
- (I_BTR and (not IR(4) or F(Flag_Z)));
- if TState = 2 then
- if SetEI = '1' then
- IntE_FF1 <= '1';
- IntE_FF2 <= '1';
- end if;
- if I_RETN = '1' then
- IntE_FF1 <= IntE_FF2;
- end if;
- end if;
- if TState = 3 then
- if SetDI = '1' then
- IntE_FF1 <= '0';
- IntE_FF2 <= '0';
- end if;
- end if;
- if IntCycle = '1' or NMICycle = '1' then
- Halt_FF <= '0';
- end if;
- if MCycle = "001" and TState = 2 and Wait_n = '1' then
- M1_n <= '1';
- end if;
- if BusReq_s = '1' and BusAck = '1' then
- else
- BusAck <= '0';
- if TState = 2 and Wait_n = '0' then
- elsif T_Res = '1' then
- if Halt = '1' then
- Halt_FF <= '1';
- end if;
- if BusReq_s = '1' then
- BusAck <= '1';
- else
- TState <= "001";
- if NextIs_XY_Fetch = '1' then
- MCycle <= "110";
- Pre_XY_F_M <= MCycle;
- if IR = "00110110" and Mode = 0 then
- Pre_XY_F_M <= "010";
- end if;
- elsif (MCycle = "111") or
- (MCycle = "110" and Mode = 1 and ISet /= "01") then
- MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
- elsif (MCycle = MCycles) or
- No_BTR = '1' or
- (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
- M1_n <= '0';
- MCycle <= "001";
- IntCycle <= '0';
- NMICycle <= '0';
- if NMI_s = '1' and Prefix = "00" then
- NMICycle <= '1';
- IntE_FF1 <= '0';
- elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
- IntCycle <= '1';
- IntE_FF1 <= '0';
- IntE_FF2 <= '0';
- end if;
- else
- MCycle <= std_logic_vector(unsigned(MCycle) + 1);
- end if;
- end if;
- else
- if (Auto_Wait = '1' and Auto_Wait_t2 = '0') nor
- (IOWait = 1 and IORQ_i = '1' and Auto_Wait_t1 = '0') then
- TState <= TState + 1;
- end if;
- end if;
- end if;
- if TState = 0 then
- M1_n <= '0';
- end if;
- end if;
- end if;
- end process;
-
- process (IntCycle, NMICycle, MCycle)
- begin
- Auto_Wait <= '0';
- if IntCycle = '1' or NMICycle = '1' then
- if MCycle = "001" then
- Auto_Wait <= '1';
- end if;
- end if;
- end process;
-
-end;
diff --git a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/T80/T8080se.vhd b/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/T80/T8080se.vhd
deleted file mode 100644
index 2b6d28f8..00000000
--- a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/T80/T8080se.vhd
+++ /dev/null
@@ -1,185 +0,0 @@
---
--- 8080 compatible microprocessor core, synchronous top level with clock enable
--- Different timing than the original 8080
--- Inputs needs to be synchronous and outputs may glitch
---
--- Version : 0242
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
--- STACK status output not supported
---
--- File history :
---
--- 0237 : First version
---
--- 0238 : Updated for T80 interface change
---
--- 0240 : Updated for T80 interface change
---
--- 0242 : Updated for T80 interface change
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T8080se is
- generic(
- Mode : integer := 2; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
- T2Write : integer := 0 -- 0 => WR_n active in T3, /=0 => WR_n active in T2
- );
- port(
- RESET_n : in std_logic;
- CLK : in std_logic;
- CLKEN : in std_logic;
- READY : in std_logic;
- HOLD : in std_logic;
- INT : in std_logic;
- INTE : out std_logic;
- DBIN : out std_logic;
- SYNC : out std_logic;
- VAIT : out std_logic;
- HLDA : out std_logic;
- WR_n : out std_logic;
- A : out std_logic_vector(15 downto 0);
- DI : in std_logic_vector(7 downto 0);
- DO : out std_logic_vector(7 downto 0)
- );
-end T8080se;
-
-architecture rtl of T8080se is
-
- signal IntCycle_n : std_logic;
- signal NoRead : std_logic;
- signal Write : std_logic;
- signal IORQ : std_logic;
- signal INT_n : std_logic;
- signal HALT_n : std_logic;
- signal BUSRQ_n : std_logic;
- signal BUSAK_n : std_logic;
- signal DO_i : std_logic_vector(7 downto 0);
- signal DI_Reg : std_logic_vector(7 downto 0);
- signal MCycle : std_logic_vector(2 downto 0);
- signal TState : std_logic_vector(2 downto 0);
- signal One : std_logic;
-
-begin
-
- INT_n <= not INT;
- BUSRQ_n <= HOLD;
- HLDA <= not BUSAK_n;
- SYNC <= '1' when TState = "001" else '0';
- VAIT <= '1' when TState = "010" else '0';
- One <= '1';
-
- DO(0) <= not IntCycle_n when TState = "001" else DO_i(0); -- INTA
- DO(1) <= Write when TState = "001" else DO_i(1); -- WO_n
- DO(2) <= DO_i(2); -- STACK not supported !!!!!!!!!!
- DO(3) <= not HALT_n when TState = "001" else DO_i(3); -- HLTA
- DO(4) <= IORQ and Write when TState = "001" else DO_i(4); -- OUT
- DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0'; -- M1
- DO(6) <= IORQ and not Write when TState = "001" else DO_i(6); -- INP
- DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7); -- MEMR
-
- u0 : T80
- generic map(
- Mode => Mode,
- IOWait => 0)
- port map(
- CEN => CLKEN,
- M1_n => open,
- IORQ => IORQ,
- NoRead => NoRead,
- Write => Write,
- RFSH_n => open,
- HALT_n => HALT_n,
- WAIT_n => READY,
- INT_n => INT_n,
- NMI_n => One,
- RESET_n => RESET_n,
- BUSRQ_n => One,
- BUSAK_n => BUSAK_n,
- CLK_n => CLK,
- A => A,
- DInst => DI,
- DI => DI_Reg,
- DO => DO_i,
- MC => MCycle,
- TS => TState,
- IntCycle_n => IntCycle_n,
- IntE => INTE);
-
- process (RESET_n, CLK)
- begin
- if RESET_n = '0' then
- DBIN <= '0';
- WR_n <= '1';
- DI_Reg <= "00000000";
- elsif CLK'event and CLK = '1' then
- if CLKEN = '1' then
- DBIN <= '0';
- WR_n <= '1';
- if MCycle = "001" then
- if TState = "001" or (TState = "010" and READY = '0') then
- DBIN <= IntCycle_n;
- end if;
- else
- if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
- DBIN <= '1';
- end if;
- if T2Write = 0 then
- if TState = "010" and Write = '1' then
- WR_n <= '0';
- end if;
- else
- if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
- WR_n <= '0';
- end if;
- end if;
- end if;
- if TState = "010" and READY = '1' then
- DI_Reg <= DI;
- end if;
- end if;
- end if;
- end process;
-
-end;
diff --git a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/T80/T80_ALU.vhd
deleted file mode 100644
index 86fddce7..00000000
--- a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/T80/T80_ALU.vhd
+++ /dev/null
@@ -1,351 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
--- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
--- 0238 : Fixed zero flag for 16 bit SBC and ADC
---
--- 0240 : Added GB operations
---
--- 0242 : Cleanup
---
--- 0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
- generic(
- Mode : integer := 0;
- Flag_C : integer := 0;
- Flag_N : integer := 1;
- Flag_P : integer := 2;
- Flag_X : integer := 3;
- Flag_H : integer := 4;
- Flag_Y : integer := 5;
- Flag_Z : integer := 6;
- Flag_S : integer := 7
- );
- port(
- Arith16 : in std_logic;
- Z16 : in std_logic;
- ALU_Op : in std_logic_vector(3 downto 0);
- IR : in std_logic_vector(5 downto 0);
- ISet : in std_logic_vector(1 downto 0);
- BusA : in std_logic_vector(7 downto 0);
- BusB : in std_logic_vector(7 downto 0);
- F_In : in std_logic_vector(7 downto 0);
- Q : out std_logic_vector(7 downto 0);
- F_Out : out std_logic_vector(7 downto 0)
- );
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
- procedure AddSub(A : std_logic_vector;
- B : std_logic_vector;
- Sub : std_logic;
- Carry_In : std_logic;
- signal Res : out std_logic_vector;
- signal Carry : out std_logic) is
- variable B_i : unsigned(A'length - 1 downto 0);
- variable Res_i : unsigned(A'length + 1 downto 0);
- begin
- if Sub = '1' then
- B_i := not unsigned(B);
- else
- B_i := unsigned(B);
- end if;
- Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
- Carry <= Res_i(A'length + 1);
- Res <= std_logic_vector(Res_i(A'length downto 1));
- end;
-
- -- AddSub variables (temporary signals)
- signal UseCarry : std_logic;
- signal Carry7_v : std_logic;
- signal Overflow_v : std_logic;
- signal HalfCarry_v : std_logic;
- signal Carry_v : std_logic;
- signal Q_v : std_logic_vector(7 downto 0);
-
- signal BitMask : std_logic_vector(7 downto 0);
-
-begin
-
- with IR(5 downto 3) select BitMask <= "00000001" when "000",
- "00000010" when "001",
- "00000100" when "010",
- "00001000" when "011",
- "00010000" when "100",
- "00100000" when "101",
- "01000000" when "110",
- "10000000" when others;
-
- UseCarry <= not ALU_Op(2) and ALU_Op(0);
- AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
- AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
- AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
- OverFlow_v <= Carry_v xor Carry7_v;
-
- process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
- variable Q_t : std_logic_vector(7 downto 0);
- variable DAA_Q : unsigned(8 downto 0);
- begin
- Q_t := "--------";
- F_Out <= F_In;
- DAA_Q := "---------";
- case ALU_Op is
- when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
- F_Out(Flag_N) <= '0';
- F_Out(Flag_C) <= '0';
- case ALU_OP(2 downto 0) is
- when "000" | "001" => -- ADD, ADC
- Q_t := Q_v;
- F_Out(Flag_C) <= Carry_v;
- F_Out(Flag_H) <= HalfCarry_v;
- F_Out(Flag_P) <= OverFlow_v;
- when "010" | "011" | "111" => -- SUB, SBC, CP
- Q_t := Q_v;
- F_Out(Flag_N) <= '1';
- F_Out(Flag_C) <= not Carry_v;
- F_Out(Flag_H) <= not HalfCarry_v;
- F_Out(Flag_P) <= OverFlow_v;
- when "100" => -- AND
- Q_t(7 downto 0) := BusA and BusB;
- F_Out(Flag_H) <= '1';
- when "101" => -- XOR
- Q_t(7 downto 0) := BusA xor BusB;
- F_Out(Flag_H) <= '0';
- when others => -- OR "110"
- Q_t(7 downto 0) := BusA or BusB;
- F_Out(Flag_H) <= '0';
- end case;
- if ALU_Op(2 downto 0) = "111" then -- CP
- F_Out(Flag_X) <= BusB(3);
- F_Out(Flag_Y) <= BusB(5);
- else
- F_Out(Flag_X) <= Q_t(3);
- F_Out(Flag_Y) <= Q_t(5);
- end if;
- if Q_t(7 downto 0) = "00000000" then
- F_Out(Flag_Z) <= '1';
- if Z16 = '1' then
- F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
- end if;
- else
- F_Out(Flag_Z) <= '0';
- end if;
- F_Out(Flag_S) <= Q_t(7);
- case ALU_Op(2 downto 0) is
- when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
- when others =>
- F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
- Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
- end case;
- if Arith16 = '1' then
- F_Out(Flag_S) <= F_In(Flag_S);
- F_Out(Flag_Z) <= F_In(Flag_Z);
- F_Out(Flag_P) <= F_In(Flag_P);
- end if;
- when "1100" =>
- -- DAA
- F_Out(Flag_H) <= F_In(Flag_H);
- F_Out(Flag_C) <= F_In(Flag_C);
- DAA_Q(7 downto 0) := unsigned(BusA);
- DAA_Q(8) := '0';
- if F_In(Flag_N) = '0' then
- -- After addition
- -- Alow > 9 or H = 1
- if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
- if (DAA_Q(3 downto 0) > 9) then
- F_Out(Flag_H) <= '1';
- else
- F_Out(Flag_H) <= '0';
- end if;
- DAA_Q := DAA_Q + 6;
- end if;
- -- new Ahigh > 9 or C = 1
- if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
- DAA_Q := DAA_Q + 96; -- 0x60
- end if;
- else
- -- After subtraction
- if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
- if DAA_Q(3 downto 0) > 5 then
- F_Out(Flag_H) <= '0';
- end if;
- DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
- end if;
- if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
- DAA_Q := DAA_Q - 352; -- 0x160
- end if;
- end if;
- F_Out(Flag_X) <= DAA_Q(3);
- F_Out(Flag_Y) <= DAA_Q(5);
- F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
- Q_t := std_logic_vector(DAA_Q(7 downto 0));
- if DAA_Q(7 downto 0) = "00000000" then
- F_Out(Flag_Z) <= '1';
- else
- F_Out(Flag_Z) <= '0';
- end if;
- F_Out(Flag_S) <= DAA_Q(7);
- F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
- DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
- when "1101" | "1110" =>
- -- RLD, RRD
- Q_t(7 downto 4) := BusA(7 downto 4);
- if ALU_Op(0) = '1' then
- Q_t(3 downto 0) := BusB(7 downto 4);
- else
- Q_t(3 downto 0) := BusB(3 downto 0);
- end if;
- F_Out(Flag_H) <= '0';
- F_Out(Flag_N) <= '0';
- F_Out(Flag_X) <= Q_t(3);
- F_Out(Flag_Y) <= Q_t(5);
- if Q_t(7 downto 0) = "00000000" then
- F_Out(Flag_Z) <= '1';
- else
- F_Out(Flag_Z) <= '0';
- end if;
- F_Out(Flag_S) <= Q_t(7);
- F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
- Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
- when "1001" =>
- -- BIT
- Q_t(7 downto 0) := BusB and BitMask;
- F_Out(Flag_S) <= Q_t(7);
- if Q_t(7 downto 0) = "00000000" then
- F_Out(Flag_Z) <= '1';
- F_Out(Flag_P) <= '1';
- else
- F_Out(Flag_Z) <= '0';
- F_Out(Flag_P) <= '0';
- end if;
- F_Out(Flag_H) <= '1';
- F_Out(Flag_N) <= '0';
- F_Out(Flag_X) <= '0';
- F_Out(Flag_Y) <= '0';
- if IR(2 downto 0) /= "110" then
- F_Out(Flag_X) <= BusB(3);
- F_Out(Flag_Y) <= BusB(5);
- end if;
- when "1010" =>
- -- SET
- Q_t(7 downto 0) := BusB or BitMask;
- when "1011" =>
- -- RES
- Q_t(7 downto 0) := BusB and not BitMask;
- when "1000" =>
- -- ROT
- case IR(5 downto 3) is
- when "000" => -- RLC
- Q_t(7 downto 1) := BusA(6 downto 0);
- Q_t(0) := BusA(7);
- F_Out(Flag_C) <= BusA(7);
- when "010" => -- RL
- Q_t(7 downto 1) := BusA(6 downto 0);
- Q_t(0) := F_In(Flag_C);
- F_Out(Flag_C) <= BusA(7);
- when "001" => -- RRC
- Q_t(6 downto 0) := BusA(7 downto 1);
- Q_t(7) := BusA(0);
- F_Out(Flag_C) <= BusA(0);
- when "011" => -- RR
- Q_t(6 downto 0) := BusA(7 downto 1);
- Q_t(7) := F_In(Flag_C);
- F_Out(Flag_C) <= BusA(0);
- when "100" => -- SLA
- Q_t(7 downto 1) := BusA(6 downto 0);
- Q_t(0) := '0';
- F_Out(Flag_C) <= BusA(7);
- when "110" => -- SLL (Undocumented) / SWAP
- if Mode = 3 then
- Q_t(7 downto 4) := BusA(3 downto 0);
- Q_t(3 downto 0) := BusA(7 downto 4);
- F_Out(Flag_C) <= '0';
- else
- Q_t(7 downto 1) := BusA(6 downto 0);
- Q_t(0) := '1';
- F_Out(Flag_C) <= BusA(7);
- end if;
- when "101" => -- SRA
- Q_t(6 downto 0) := BusA(7 downto 1);
- Q_t(7) := BusA(7);
- F_Out(Flag_C) <= BusA(0);
- when others => -- SRL
- Q_t(6 downto 0) := BusA(7 downto 1);
- Q_t(7) := '0';
- F_Out(Flag_C) <= BusA(0);
- end case;
- F_Out(Flag_H) <= '0';
- F_Out(Flag_N) <= '0';
- F_Out(Flag_X) <= Q_t(3);
- F_Out(Flag_Y) <= Q_t(5);
- F_Out(Flag_S) <= Q_t(7);
- if Q_t(7 downto 0) = "00000000" then
- F_Out(Flag_Z) <= '1';
- else
- F_Out(Flag_Z) <= '0';
- end if;
- F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
- Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
- if ISet = "00" then
- F_Out(Flag_P) <= F_In(Flag_P);
- F_Out(Flag_S) <= F_In(Flag_S);
- F_Out(Flag_Z) <= F_In(Flag_Z);
- end if;
- when others =>
- null;
- end case;
- Q <= Q_t;
- end process;
-
-end;
diff --git a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/T80/T80_MCode.vhd
deleted file mode 100644
index 4cc30f35..00000000
--- a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/T80/T80_MCode.vhd
+++ /dev/null
@@ -1,1934 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
--- 0208 : First complete release
---
--- 0211 : Fixed IM 1
---
--- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
--- 0235 : Added IM 2 fix by Mike Johnson
---
--- 0238 : Added NoRead signal
---
--- 0238b: Fixed instruction timing for POP and DJNZ
---
--- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
---
--- 0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_MCode is
- generic(
- Mode : integer := 0;
- Flag_C : integer := 0;
- Flag_N : integer := 1;
- Flag_P : integer := 2;
- Flag_X : integer := 3;
- Flag_H : integer := 4;
- Flag_Y : integer := 5;
- Flag_Z : integer := 6;
- Flag_S : integer := 7
- );
- port(
- IR : in std_logic_vector(7 downto 0);
- ISet : in std_logic_vector(1 downto 0);
- MCycle : in std_logic_vector(2 downto 0);
- F : in std_logic_vector(7 downto 0);
- NMICycle : in std_logic;
- IntCycle : in std_logic;
- MCycles : out std_logic_vector(2 downto 0);
- TStates : out std_logic_vector(2 downto 0);
- Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
- Inc_PC : out std_logic;
- Inc_WZ : out std_logic;
- IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
- Read_To_Reg : out std_logic;
- Read_To_Acc : out std_logic;
- Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
- Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
- ALU_Op : out std_logic_vector(3 downto 0);
- -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
- Save_ALU : out std_logic;
- PreserveC : out std_logic;
- Arith16 : out std_logic;
- Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
- IORQ : out std_logic;
- Jump : out std_logic;
- JumpE : out std_logic;
- JumpXY : out std_logic;
- Call : out std_logic;
- RstP : out std_logic;
- LDZ : out std_logic;
- LDW : out std_logic;
- LDSPHL : out std_logic;
- Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
- ExchangeDH : out std_logic;
- ExchangeRp : out std_logic;
- ExchangeAF : out std_logic;
- ExchangeRS : out std_logic;
- I_DJNZ : out std_logic;
- I_CPL : out std_logic;
- I_CCF : out std_logic;
- I_SCF : out std_logic;
- I_RETN : out std_logic;
- I_BT : out std_logic;
- I_BC : out std_logic;
- I_BTR : out std_logic;
- I_RLD : out std_logic;
- I_RRD : out std_logic;
- I_INRC : out std_logic;
- SetDI : out std_logic;
- SetEI : out std_logic;
- IMode : out std_logic_vector(1 downto 0);
- Halt : out std_logic;
- NoRead : out std_logic;
- Write : out std_logic
- );
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
- constant aNone : std_logic_vector(2 downto 0) := "111";
- constant aBC : std_logic_vector(2 downto 0) := "000";
- constant aDE : std_logic_vector(2 downto 0) := "001";
- constant aXY : std_logic_vector(2 downto 0) := "010";
- constant aIOA : std_logic_vector(2 downto 0) := "100";
- constant aSP : std_logic_vector(2 downto 0) := "101";
- constant aZI : std_logic_vector(2 downto 0) := "110";
--- constant aNone : std_logic_vector(2 downto 0) := "000";
--- constant aXY : std_logic_vector(2 downto 0) := "001";
--- constant aIOA : std_logic_vector(2 downto 0) := "010";
--- constant aSP : std_logic_vector(2 downto 0) := "011";
--- constant aBC : std_logic_vector(2 downto 0) := "100";
--- constant aDE : std_logic_vector(2 downto 0) := "101";
--- constant aZI : std_logic_vector(2 downto 0) := "110";
-
- function is_cc_true(
- F : std_logic_vector(7 downto 0);
- cc : bit_vector(2 downto 0)
- ) return boolean is
- begin
- if Mode = 3 then
- case cc is
- when "000" => return F(7) = '0'; -- NZ
- when "001" => return F(7) = '1'; -- Z
- when "010" => return F(4) = '0'; -- NC
- when "011" => return F(4) = '1'; -- C
- when "100" => return false;
- when "101" => return false;
- when "110" => return false;
- when "111" => return false;
- end case;
- else
- case cc is
- when "000" => return F(6) = '0'; -- NZ
- when "001" => return F(6) = '1'; -- Z
- when "010" => return F(0) = '0'; -- NC
- when "011" => return F(0) = '1'; -- C
- when "100" => return F(2) = '0'; -- PO
- when "101" => return F(2) = '1'; -- PE
- when "110" => return F(7) = '0'; -- P
- when "111" => return F(7) = '1'; -- M
- end case;
- end if;
- end;
-
-begin
-
- process (IR, ISet, MCycle, F, NMICycle, IntCycle)
- variable DDD : std_logic_vector(2 downto 0);
- variable SSS : std_logic_vector(2 downto 0);
- variable DPair : std_logic_vector(1 downto 0);
- variable IRB : bit_vector(7 downto 0);
- begin
- DDD := IR(5 downto 3);
- SSS := IR(2 downto 0);
- DPair := IR(5 downto 4);
- IRB := to_bitvector(IR);
-
- MCycles <= "001";
- if MCycle = "001" then
- TStates <= "100";
- else
- TStates <= "011";
- end if;
- Prefix <= "00";
- Inc_PC <= '0';
- Inc_WZ <= '0';
- IncDec_16 <= "0000";
- Read_To_Acc <= '0';
- Read_To_Reg <= '0';
- Set_BusB_To <= "0000";
- Set_BusA_To <= "0000";
- ALU_Op <= "0" & IR(5 downto 3);
- Save_ALU <= '0';
- PreserveC <= '0';
- Arith16 <= '0';
- IORQ <= '0';
- Set_Addr_To <= aNone;
- Jump <= '0';
- JumpE <= '0';
- JumpXY <= '0';
- Call <= '0';
- RstP <= '0';
- LDZ <= '0';
- LDW <= '0';
- LDSPHL <= '0';
- Special_LD <= "000";
- ExchangeDH <= '0';
- ExchangeRp <= '0';
- ExchangeAF <= '0';
- ExchangeRS <= '0';
- I_DJNZ <= '0';
- I_CPL <= '0';
- I_CCF <= '0';
- I_SCF <= '0';
- I_RETN <= '0';
- I_BT <= '0';
- I_BC <= '0';
- I_BTR <= '0';
- I_RLD <= '0';
- I_RRD <= '0';
- I_INRC <= '0';
- SetDI <= '0';
- SetEI <= '0';
- IMode <= "11";
- Halt <= '0';
- NoRead <= '0';
- Write <= '0';
-
- case ISet is
- when "00" =>
-
-------------------------------------------------------------------------------
---
--- Unprefixed instructions
---
-------------------------------------------------------------------------------
-
- case IRB is
--- 8 BIT LOAD GROUP
- when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
- |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
- |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
- |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
- |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
- |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
- |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
- -- LD r,r'
- Set_BusB_To(2 downto 0) <= SSS;
- ExchangeRp <= '1';
- Set_BusA_To(2 downto 0) <= DDD;
- Read_To_Reg <= '1';
- when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
- -- LD r,n
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- Set_BusA_To(2 downto 0) <= DDD;
- Read_To_Reg <= '1';
- when others => null;
- end case;
- when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
- -- LD r,(HL)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- when 2 =>
- Set_BusA_To(2 downto 0) <= DDD;
- Read_To_Reg <= '1';
- when others => null;
- end case;
- when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
- -- LD (HL),r
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- Set_BusB_To(2 downto 0) <= SSS;
- Set_BusB_To(3) <= '0';
- when 2 =>
- Write <= '1';
- when others => null;
- end case;
- when "00110110" =>
- -- LD (HL),n
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- Set_Addr_To <= aXY;
- Set_BusB_To(2 downto 0) <= SSS;
- Set_BusB_To(3) <= '0';
- when 3 =>
- Write <= '1';
- when others => null;
- end case;
- when "00001010" =>
- -- LD A,(BC)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aBC;
- when 2 =>
- Read_To_Acc <= '1';
- when others => null;
- end case;
- when "00011010" =>
- -- LD A,(DE)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aDE;
- when 2 =>
- Read_To_Acc <= '1';
- when others => null;
- end case;
- when "00111010" =>
- if Mode = 3 then
- -- LDD A,(HL)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- when 2 =>
- Read_To_Acc <= '1';
- IncDec_16 <= "1110";
- when others => null;
- end case;
- else
- -- LD A,(nn)
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- when 4 =>
- Read_To_Acc <= '1';
- when others => null;
- end case;
- end if;
- when "00000010" =>
- -- LD (BC),A
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aBC;
- Set_BusB_To <= "0111";
- when 2 =>
- Write <= '1';
- when others => null;
- end case;
- when "00010010" =>
- -- LD (DE),A
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aDE;
- Set_BusB_To <= "0111";
- when 2 =>
- Write <= '1';
- when others => null;
- end case;
- when "00110010" =>
- if Mode = 3 then
- -- LDD (HL),A
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- Set_BusB_To <= "0111";
- when 2 =>
- Write <= '1';
- IncDec_16 <= "1110";
- when others => null;
- end case;
- else
- -- LD (nn),A
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- Set_BusB_To <= "0111";
- when 4 =>
- Write <= '1';
- when others => null;
- end case;
- end if;
-
--- 16 BIT LOAD GROUP
- when "00000001"|"00010001"|"00100001"|"00110001" =>
- -- LD dd,nn
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- Read_To_Reg <= '1';
- if DPAIR = "11" then
- Set_BusA_To(3 downto 0) <= "1000";
- else
- Set_BusA_To(2 downto 1) <= DPAIR;
- Set_BusA_To(0) <= '1';
- end if;
- when 3 =>
- Inc_PC <= '1';
- Read_To_Reg <= '1';
- if DPAIR = "11" then
- Set_BusA_To(3 downto 0) <= "1001";
- else
- Set_BusA_To(2 downto 1) <= DPAIR;
- Set_BusA_To(0) <= '0';
- end if;
- when others => null;
- end case;
- when "00101010" =>
- if Mode = 3 then
- -- LDI A,(HL)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- when 2 =>
- Read_To_Acc <= '1';
- IncDec_16 <= "0110";
- when others => null;
- end case;
- else
- -- LD HL,(nn)
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- LDW <= '1';
- when 4 =>
- Set_BusA_To(2 downto 0) <= "101"; -- L
- Read_To_Reg <= '1';
- Inc_WZ <= '1';
- Set_Addr_To <= aZI;
- when 5 =>
- Set_BusA_To(2 downto 0) <= "100"; -- H
- Read_To_Reg <= '1';
- when others => null;
- end case;
- end if;
- when "00100010" =>
- if Mode = 3 then
- -- LDI (HL),A
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- Set_BusB_To <= "0111";
- when 2 =>
- Write <= '1';
- IncDec_16 <= "0110";
- when others => null;
- end case;
- else
- -- LD (nn),HL
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- LDW <= '1';
- Set_BusB_To <= "0101"; -- L
- when 4 =>
- Inc_WZ <= '1';
- Set_Addr_To <= aZI;
- Write <= '1';
- Set_BusB_To <= "0100"; -- H
- when 5 =>
- Write <= '1';
- when others => null;
- end case;
- end if;
- when "11111001" =>
- -- LD SP,HL
- TStates <= "110";
- LDSPHL <= '1';
- when "11000101"|"11010101"|"11100101"|"11110101" =>
- -- PUSH qq
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- TStates <= "101";
- IncDec_16 <= "1111";
- Set_Addr_TO <= aSP;
- if DPAIR = "11" then
- Set_BusB_To <= "0111";
- else
- Set_BusB_To(2 downto 1) <= DPAIR;
- Set_BusB_To(0) <= '0';
- Set_BusB_To(3) <= '0';
- end if;
- when 2 =>
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- if DPAIR = "11" then
- Set_BusB_To <= "1011";
- else
- Set_BusB_To(2 downto 1) <= DPAIR;
- Set_BusB_To(0) <= '1';
- Set_BusB_To(3) <= '0';
- end if;
- Write <= '1';
- when 3 =>
- Write <= '1';
- when others => null;
- end case;
- when "11000001"|"11010001"|"11100001"|"11110001" =>
- -- POP qq
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aSP;
- when 2 =>
- IncDec_16 <= "0111";
- Set_Addr_To <= aSP;
- Read_To_Reg <= '1';
- if DPAIR = "11" then
- Set_BusA_To(3 downto 0) <= "1011";
- else
- Set_BusA_To(2 downto 1) <= DPAIR;
- Set_BusA_To(0) <= '1';
- end if;
- when 3 =>
- IncDec_16 <= "0111";
- Read_To_Reg <= '1';
- if DPAIR = "11" then
- Set_BusA_To(3 downto 0) <= "0111";
- else
- Set_BusA_To(2 downto 1) <= DPAIR;
- Set_BusA_To(0) <= '0';
- end if;
- when others => null;
- end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
- when "11101011" =>
- if Mode /= 3 then
- -- EX DE,HL
- ExchangeDH <= '1';
- end if;
- when "00001000" =>
- if Mode = 3 then
- -- LD (nn),SP
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- LDW <= '1';
- Set_BusB_To <= "1000";
- when 4 =>
- Inc_WZ <= '1';
- Set_Addr_To <= aZI;
- Write <= '1';
- Set_BusB_To <= "1001";
- when 5 =>
- Write <= '1';
- when others => null;
- end case;
- elsif Mode < 2 then
- -- EX AF,AF'
- ExchangeAF <= '1';
- end if;
- when "11011001" =>
- if Mode = 3 then
- -- RETI
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_TO <= aSP;
- when 2 =>
- IncDec_16 <= "0111";
- Set_Addr_To <= aSP;
- LDZ <= '1';
- when 3 =>
- Jump <= '1';
- IncDec_16 <= "0111";
- I_RETN <= '1';
- SetEI <= '1';
- when others => null;
- end case;
- elsif Mode < 2 then
- -- EXX
- ExchangeRS <= '1';
- end if;
- when "11100011" =>
- if Mode /= 3 then
- -- EX (SP),HL
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aSP;
- when 2 =>
- Read_To_Reg <= '1';
- Set_BusA_To <= "0101";
- Set_BusB_To <= "0101";
- Set_Addr_To <= aSP;
- when 3 =>
- IncDec_16 <= "0111";
- Set_Addr_To <= aSP;
- TStates <= "100";
- Write <= '1';
- when 4 =>
- Read_To_Reg <= '1';
- Set_BusA_To <= "0100";
- Set_BusB_To <= "0100";
- Set_Addr_To <= aSP;
- when 5 =>
- IncDec_16 <= "1111";
- TStates <= "101";
- Write <= '1';
- when others => null;
- end case;
- end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
- when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
- |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
- |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
- |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
- |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
- |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
- |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
- |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
- -- ADD A,r
- -- ADC A,r
- -- SUB A,r
- -- SBC A,r
- -- AND A,r
- -- OR A,r
- -- XOR A,r
- -- CP A,r
- Set_BusB_To(2 downto 0) <= SSS;
- Set_BusA_To(2 downto 0) <= "111";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
- -- ADD A,(HL)
- -- ADC A,(HL)
- -- SUB A,(HL)
- -- SBC A,(HL)
- -- AND A,(HL)
- -- OR A,(HL)
- -- XOR A,(HL)
- -- CP A,(HL)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- when 2 =>
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_BusB_To(2 downto 0) <= SSS;
- Set_BusA_To(2 downto 0) <= "111";
- when others => null;
- end case;
- when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
- -- ADD A,n
- -- ADC A,n
- -- SUB A,n
- -- SBC A,n
- -- AND A,n
- -- OR A,n
- -- XOR A,n
- -- CP A,n
- MCycles <= "010";
- if MCycle = "010" then
- Inc_PC <= '1';
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_BusB_To(2 downto 0) <= SSS;
- Set_BusA_To(2 downto 0) <= "111";
- end if;
- when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
- -- INC r
- Set_BusB_To <= "1010";
- Set_BusA_To(2 downto 0) <= DDD;
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- PreserveC <= '1';
- ALU_Op <= "0000";
- when "00110100" =>
- -- INC (HL)
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- when 2 =>
- TStates <= "100";
- Set_Addr_To <= aXY;
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- PreserveC <= '1';
- ALU_Op <= "0000";
- Set_BusB_To <= "1010";
- Set_BusA_To(2 downto 0) <= DDD;
- when 3 =>
- Write <= '1';
- when others => null;
- end case;
- when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
- -- DEC r
- Set_BusB_To <= "1010";
- Set_BusA_To(2 downto 0) <= DDD;
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- PreserveC <= '1';
- ALU_Op <= "0010";
- when "00110101" =>
- -- DEC (HL)
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- when 2 =>
- TStates <= "100";
- Set_Addr_To <= aXY;
- ALU_Op <= "0010";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- PreserveC <= '1';
- Set_BusB_To <= "1010";
- Set_BusA_To(2 downto 0) <= DDD;
- when 3 =>
- Write <= '1';
- when others => null;
- end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
- when "00100111" =>
- -- DAA
- Set_BusA_To(2 downto 0) <= "111";
- Read_To_Reg <= '1';
- ALU_Op <= "1100";
- Save_ALU <= '1';
- when "00101111" =>
- -- CPL
- I_CPL <= '1';
- when "00111111" =>
- -- CCF
- I_CCF <= '1';
- when "00110111" =>
- -- SCF
- I_SCF <= '1';
- when "00000000" =>
- if NMICycle = '1' then
- -- NMI
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- TStates <= "101";
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- Set_BusB_To <= "1101";
- when 2 =>
- TStates <= "100";
- Write <= '1';
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- Set_BusB_To <= "1100";
- when 3 =>
- TStates <= "100";
- Write <= '1';
- when others => null;
- end case;
- elsif IntCycle = '1' then
- -- INT (IM 2)
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- LDZ <= '1';
- TStates <= "101";
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- Set_BusB_To <= "1101";
- when 2 =>
- TStates <= "100";
- Write <= '1';
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- Set_BusB_To <= "1100";
- when 3 =>
- TStates <= "100";
- Write <= '1';
- when 4 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 5 =>
- Jump <= '1';
- when others => null;
- end case;
- else
- -- NOP
- end if;
- when "01110110" =>
- -- HALT
- Halt <= '1';
- when "11110011" =>
- -- DI
- SetDI <= '1';
- when "11111011" =>
- -- EI
- SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
- when "00001001"|"00011001"|"00101001"|"00111001" =>
- -- ADD HL,ss
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- NoRead <= '1';
- ALU_Op <= "0000";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_BusA_To(2 downto 0) <= "101";
- case to_integer(unsigned(IR(5 downto 4))) is
- when 0|1|2 =>
- Set_BusB_To(2 downto 1) <= IR(5 downto 4);
- Set_BusB_To(0) <= '1';
- when others =>
- Set_BusB_To <= "1000";
- end case;
- TStates <= "100";
- Arith16 <= '1';
- when 3 =>
- NoRead <= '1';
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- ALU_Op <= "0001";
- Set_BusA_To(2 downto 0) <= "100";
- case to_integer(unsigned(IR(5 downto 4))) is
- when 0|1|2 =>
- Set_BusB_To(2 downto 1) <= IR(5 downto 4);
- when others =>
- Set_BusB_To <= "1001";
- end case;
- Arith16 <= '1';
- when others =>
- end case;
- when "00000011"|"00010011"|"00100011"|"00110011" =>
- -- INC ss
- TStates <= "110";
- IncDec_16(3 downto 2) <= "01";
- IncDec_16(1 downto 0) <= DPair;
- when "00001011"|"00011011"|"00101011"|"00111011" =>
- -- DEC ss
- TStates <= "110";
- IncDec_16(3 downto 2) <= "11";
- IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
- when "00000111"
- -- RLCA
- |"00010111"
- -- RLA
- |"00001111"
- -- RRCA
- |"00011111" =>
- -- RRA
- Set_BusA_To(2 downto 0) <= "111";
- ALU_Op <= "1000";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
-
--- JUMP GROUP
- when "11000011" =>
- -- JP nn
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Inc_PC <= '1';
- Jump <= '1';
- when others => null;
- end case;
- when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
- if IR(5) = '1' and Mode = 3 then
- case IRB(4 downto 3) is
- when "00" =>
- -- LD ($FF00+C),A
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aBC;
- Set_BusB_To <= "0111";
- when 2 =>
- Write <= '1';
- IORQ <= '1';
- when others =>
- end case;
- when "01" =>
- -- LD (nn),A
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- Set_BusB_To <= "0111";
- when 4 =>
- Write <= '1';
- when others => null;
- end case;
- when "10" =>
- -- LD A,($FF00+C)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aBC;
- when 2 =>
- Read_To_Acc <= '1';
- IORQ <= '1';
- when others =>
- end case;
- when "11" =>
- -- LD A,(nn)
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- when 4 =>
- Read_To_Acc <= '1';
- when others => null;
- end case;
- end case;
- else
- -- JP cc,nn
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Inc_PC <= '1';
- if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
- Jump <= '1';
- end if;
- when others => null;
- end case;
- end if;
- when "00011000" =>
- if Mode /= 2 then
- -- JR e
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- when 3 =>
- NoRead <= '1';
- JumpE <= '1';
- TStates <= "101";
- when others => null;
- end case;
- end if;
- when "00111000" =>
- if Mode /= 2 then
- -- JR C,e
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- if F(Flag_C) = '0' then
- MCycles <= "010";
- end if;
- when 3 =>
- NoRead <= '1';
- JumpE <= '1';
- TStates <= "101";
- when others => null;
- end case;
- end if;
- when "00110000" =>
- if Mode /= 2 then
- -- JR NC,e
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- if F(Flag_C) = '1' then
- MCycles <= "010";
- end if;
- when 3 =>
- NoRead <= '1';
- JumpE <= '1';
- TStates <= "101";
- when others => null;
- end case;
- end if;
- when "00101000" =>
- if Mode /= 2 then
- -- JR Z,e
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- if F(Flag_Z) = '0' then
- MCycles <= "010";
- end if;
- when 3 =>
- NoRead <= '1';
- JumpE <= '1';
- TStates <= "101";
- when others => null;
- end case;
- end if;
- when "00100000" =>
- if Mode /= 2 then
- -- JR NZ,e
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- if F(Flag_Z) = '1' then
- MCycles <= "010";
- end if;
- when 3 =>
- NoRead <= '1';
- JumpE <= '1';
- TStates <= "101";
- when others => null;
- end case;
- end if;
- when "11101001" =>
- -- JP (HL)
- JumpXY <= '1';
- when "00010000" =>
- if Mode = 3 then
- I_DJNZ <= '1';
- elsif Mode < 2 then
- -- DJNZ,e
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- TStates <= "101";
- I_DJNZ <= '1';
- Set_BusB_To <= "1010";
- Set_BusA_To(2 downto 0) <= "000";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- ALU_Op <= "0010";
- when 2 =>
- I_DJNZ <= '1';
- Inc_PC <= '1';
- when 3 =>
- NoRead <= '1';
- JumpE <= '1';
- TStates <= "101";
- when others => null;
- end case;
- end if;
-
--- CALL AND RETURN GROUP
- when "11001101" =>
- -- CALL nn
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- IncDec_16 <= "1111";
- Inc_PC <= '1';
- TStates <= "100";
- Set_Addr_To <= aSP;
- LDW <= '1';
- Set_BusB_To <= "1101";
- when 4 =>
- Write <= '1';
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- Set_BusB_To <= "1100";
- when 5 =>
- Write <= '1';
- Call <= '1';
- when others => null;
- end case;
- when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
- if IR(5) = '0' or Mode /= 3 then
- -- CALL cc,nn
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Inc_PC <= '1';
- LDW <= '1';
- if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
- IncDec_16 <= "1111";
- Set_Addr_TO <= aSP;
- TStates <= "100";
- Set_BusB_To <= "1101";
- else
- MCycles <= "011";
- end if;
- when 4 =>
- Write <= '1';
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- Set_BusB_To <= "1100";
- when 5 =>
- Write <= '1';
- Call <= '1';
- when others => null;
- end case;
- end if;
- when "11001001" =>
- -- RET
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- TStates <= "101";
- Set_Addr_TO <= aSP;
- when 2 =>
- IncDec_16 <= "0111";
- Set_Addr_To <= aSP;
- LDZ <= '1';
- when 3 =>
- Jump <= '1';
- IncDec_16 <= "0111";
- when others => null;
- end case;
- when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
- if IR(5) = '1' and Mode = 3 then
- case IRB(4 downto 3) is
- when "00" =>
- -- LD ($FF00+nn),A
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- Set_Addr_To <= aIOA;
- Set_BusB_To <= "0111";
- when 3 =>
- Write <= '1';
- when others => null;
- end case;
- when "01" =>
- -- ADD SP,n
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- ALU_Op <= "0000";
- Inc_PC <= '1';
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_BusA_To <= "1000";
- Set_BusB_To <= "0110";
- when 3 =>
- NoRead <= '1';
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- ALU_Op <= "0001";
- Set_BusA_To <= "1001";
- Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
- when others =>
- end case;
- when "10" =>
- -- LD A,($FF00+nn)
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- Set_Addr_To <= aIOA;
- when 3 =>
- Read_To_Acc <= '1';
- when others => null;
- end case;
- when "11" =>
- -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!!
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- LDW <= '1';
- when 4 =>
- Set_BusA_To(2 downto 0) <= "101"; -- L
- Read_To_Reg <= '1';
- Inc_WZ <= '1';
- Set_Addr_To <= aZI;
- when 5 =>
- Set_BusA_To(2 downto 0) <= "100"; -- H
- Read_To_Reg <= '1';
- when others => null;
- end case;
- end case;
- else
- -- RET cc
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
- Set_Addr_TO <= aSP;
- else
- MCycles <= "001";
- end if;
- TStates <= "101";
- when 2 =>
- IncDec_16 <= "0111";
- Set_Addr_To <= aSP;
- LDZ <= '1';
- when 3 =>
- Jump <= '1';
- IncDec_16 <= "0111";
- when others => null;
- end case;
- end if;
- when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
- -- RST p
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- TStates <= "101";
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- Set_BusB_To <= "1101";
- when 2 =>
- Write <= '1';
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- Set_BusB_To <= "1100";
- when 3 =>
- Write <= '1';
- RstP <= '1';
- when others => null;
- end case;
-
--- INPUT AND OUTPUT GROUP
- when "11011011" =>
- if Mode /= 3 then
- -- IN A,(n)
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- Set_Addr_To <= aIOA;
- when 3 =>
- Read_To_Acc <= '1';
- IORQ <= '1';
- when others => null;
- end case;
- end if;
- when "11010011" =>
- if Mode /= 3 then
- -- OUT (n),A
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- Set_Addr_To <= aIOA;
- Set_BusB_To <= "0111";
- when 3 =>
- Write <= '1';
- IORQ <= '1';
- when others => null;
- end case;
- end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
- when "11001011" =>
- if Mode /= 2 then
- Prefix <= "01";
- end if;
-
- when "11101101" =>
- if Mode < 2 then
- Prefix <= "10";
- end if;
-
- when "11011101"|"11111101" =>
- if Mode < 2 then
- Prefix <= "11";
- end if;
-
- end case;
-
- when "01" =>
-
-------------------------------------------------------------------------------
---
--- CB prefixed instructions
---
-------------------------------------------------------------------------------
-
- Set_BusA_To(2 downto 0) <= IR(2 downto 0);
- Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
- case IRB is
- when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
- |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
- |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
- |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
- |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
- |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
- |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
- |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
- -- RLC r
- -- RL r
- -- RRC r
- -- RR r
- -- SLA r
- -- SRA r
- -- SRL r
- -- SLL r (Undocumented) / SWAP r
- if MCycle = "001" then
- ALU_Op <= "1000";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- end if;
- when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
- -- RLC (HL)
- -- RL (HL)
- -- RRC (HL)
- -- RR (HL)
- -- SRA (HL)
- -- SRL (HL)
- -- SLA (HL)
- -- SLL (HL) (Undocumented) / SWAP (HL)
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 | 7 =>
- Set_Addr_To <= aXY;
- when 2 =>
- ALU_Op <= "1000";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_Addr_To <= aXY;
- TStates <= "100";
- when 3 =>
- Write <= '1';
- when others =>
- end case;
- when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
- |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
- |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
- |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
- |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
- |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
- |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
- |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
- -- BIT b,r
- if MCycle = "001" then
- Set_BusB_To(2 downto 0) <= IR(2 downto 0);
- ALU_Op <= "1001";
- end if;
- when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
- -- BIT b,(HL)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 | 7 =>
- Set_Addr_To <= aXY;
- when 2 =>
- ALU_Op <= "1001";
- TStates <= "100";
- when others =>
- end case;
- when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
- |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
- |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
- |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
- |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
- |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
- |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
- |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
- -- SET b,r
- if MCycle = "001" then
- ALU_Op <= "1010";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- end if;
- when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
- -- SET b,(HL)
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 | 7 =>
- Set_Addr_To <= aXY;
- when 2 =>
- ALU_Op <= "1010";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_Addr_To <= aXY;
- TStates <= "100";
- when 3 =>
- Write <= '1';
- when others =>
- end case;
- when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
- |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
- |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
- |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
- |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
- |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
- |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
- |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
- -- RES b,r
- if MCycle = "001" then
- ALU_Op <= "1011";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- end if;
- when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
- -- RES b,(HL)
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 | 7 =>
- Set_Addr_To <= aXY;
- when 2 =>
- ALU_Op <= "1011";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_Addr_To <= aXY;
- TStates <= "100";
- when 3 =>
- Write <= '1';
- when others =>
- end case;
- end case;
-
- when others =>
-
-------------------------------------------------------------------------------
---
--- ED prefixed instructions
---
-------------------------------------------------------------------------------
-
- case IRB is
- when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
- |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
- |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
- |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
- |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
- |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
- |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
- |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
- |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
- |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
- |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
- |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
- | "10100100"|"10100101"|"10100110"|"10100111"
- | "10101100"|"10101101"|"10101110"|"10101111"
- | "10110100"|"10110101"|"10110110"|"10110111"
- | "10111100"|"10111101"|"10111110"|"10111111"
- |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
- |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
- |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
- |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
- |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
- |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
- |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
- |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
- null; -- NOP, undocumented
- when "01111110"|"01111111" =>
- -- NOP, undocumented
- null;
--- 8 BIT LOAD GROUP
- when "01010111" =>
- -- LD A,I
- Special_LD <= "100";
- TStates <= "101";
- when "01011111" =>
- -- LD A,R
- Special_LD <= "101";
- TStates <= "101";
- when "01000111" =>
- -- LD I,A
- Special_LD <= "110";
- TStates <= "101";
- when "01001111" =>
- -- LD R,A
- Special_LD <= "111";
- TStates <= "101";
--- 16 BIT LOAD GROUP
- when "01001011"|"01011011"|"01101011"|"01111011" =>
- -- LD dd,(nn)
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- LDW <= '1';
- when 4 =>
- Read_To_Reg <= '1';
- if IR(5 downto 4) = "11" then
- Set_BusA_To <= "1000";
- else
- Set_BusA_To(2 downto 1) <= IR(5 downto 4);
- Set_BusA_To(0) <= '1';
- end if;
- Inc_WZ <= '1';
- Set_Addr_To <= aZI;
- when 5 =>
- Read_To_Reg <= '1';
- if IR(5 downto 4) = "11" then
- Set_BusA_To <= "1001";
- else
- Set_BusA_To(2 downto 1) <= IR(5 downto 4);
- Set_BusA_To(0) <= '0';
- end if;
- when others => null;
- end case;
- when "01000011"|"01010011"|"01100011"|"01110011" =>
- -- LD (nn),dd
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- LDW <= '1';
- if IR(5 downto 4) = "11" then
- Set_BusB_To <= "1000";
- else
- Set_BusB_To(2 downto 1) <= IR(5 downto 4);
- Set_BusB_To(0) <= '1';
- Set_BusB_To(3) <= '0';
- end if;
- when 4 =>
- Inc_WZ <= '1';
- Set_Addr_To <= aZI;
- Write <= '1';
- if IR(5 downto 4) = "11" then
- Set_BusB_To <= "1001";
- else
- Set_BusB_To(2 downto 1) <= IR(5 downto 4);
- Set_BusB_To(0) <= '0';
- Set_BusB_To(3) <= '0';
- end if;
- when 5 =>
- Write <= '1';
- when others => null;
- end case;
- when "10100000" | "10101000" | "10110000" | "10111000" =>
- -- LDI, LDD, LDIR, LDDR
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- IncDec_16 <= "1100"; -- BC
- when 2 =>
- Set_BusB_To <= "0110";
- Set_BusA_To(2 downto 0) <= "111";
- ALU_Op <= "0000";
- Set_Addr_To <= aDE;
- if IR(3) = '0' then
- IncDec_16 <= "0110"; -- IX
- else
- IncDec_16 <= "1110";
- end if;
- when 3 =>
- I_BT <= '1';
- TStates <= "101";
- Write <= '1';
- if IR(3) = '0' then
- IncDec_16 <= "0101"; -- DE
- else
- IncDec_16 <= "1101";
- end if;
- when 4 =>
- NoRead <= '1';
- TStates <= "101";
- when others => null;
- end case;
- when "10100001" | "10101001" | "10110001" | "10111001" =>
- -- CPI, CPD, CPIR, CPDR
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- IncDec_16 <= "1100"; -- BC
- when 2 =>
- Set_BusB_To <= "0110";
- Set_BusA_To(2 downto 0) <= "111";
- ALU_Op <= "0111";
- Save_ALU <= '1';
- PreserveC <= '1';
- if IR(3) = '0' then
- IncDec_16 <= "0110";
- else
- IncDec_16 <= "1110";
- end if;
- when 3 =>
- NoRead <= '1';
- I_BC <= '1';
- TStates <= "101";
- when 4 =>
- NoRead <= '1';
- TStates <= "101";
- when others => null;
- end case;
- when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
- -- NEG
- Alu_OP <= "0010";
- Set_BusB_To <= "0111";
- Set_BusA_To <= "1010";
- Read_To_Acc <= '1';
- Save_ALU <= '1';
- when "01000110"|"01001110"|"01100110"|"01101110" =>
- -- IM 0
- IMode <= "00";
- when "01010110"|"01110110" =>
- -- IM 1
- IMode <= "01";
- when "01011110"|"01110111" =>
- -- IM 2
- IMode <= "10";
--- 16 bit arithmetic
- when "01001010"|"01011010"|"01101010"|"01111010" =>
- -- ADC HL,ss
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- NoRead <= '1';
- ALU_Op <= "0001";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_BusA_To(2 downto 0) <= "101";
- case to_integer(unsigned(IR(5 downto 4))) is
- when 0|1|2 =>
- Set_BusB_To(2 downto 1) <= IR(5 downto 4);
- Set_BusB_To(0) <= '1';
- when others =>
- Set_BusB_To <= "1000";
- end case;
- TStates <= "100";
- when 3 =>
- NoRead <= '1';
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- ALU_Op <= "0001";
- Set_BusA_To(2 downto 0) <= "100";
- case to_integer(unsigned(IR(5 downto 4))) is
- when 0|1|2 =>
- Set_BusB_To(2 downto 1) <= IR(5 downto 4);
- Set_BusB_To(0) <= '0';
- when others =>
- Set_BusB_To <= "1001";
- end case;
- when others =>
- end case;
- when "01000010"|"01010010"|"01100010"|"01110010" =>
- -- SBC HL,ss
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- NoRead <= '1';
- ALU_Op <= "0011";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_BusA_To(2 downto 0) <= "101";
- case to_integer(unsigned(IR(5 downto 4))) is
- when 0|1|2 =>
- Set_BusB_To(2 downto 1) <= IR(5 downto 4);
- Set_BusB_To(0) <= '1';
- when others =>
- Set_BusB_To <= "1000";
- end case;
- TStates <= "100";
- when 3 =>
- NoRead <= '1';
- ALU_Op <= "0011";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_BusA_To(2 downto 0) <= "100";
- case to_integer(unsigned(IR(5 downto 4))) is
- when 0|1|2 =>
- Set_BusB_To(2 downto 1) <= IR(5 downto 4);
- when others =>
- Set_BusB_To <= "1001";
- end case;
- when others =>
- end case;
- when "01101111" =>
- -- RLD
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- NoRead <= '1';
- Set_Addr_To <= aXY;
- when 3 =>
- Read_To_Reg <= '1';
- Set_BusB_To(2 downto 0) <= "110";
- Set_BusA_To(2 downto 0) <= "111";
- ALU_Op <= "1101";
- TStates <= "100";
- Set_Addr_To <= aXY;
- Save_ALU <= '1';
- when 4 =>
- I_RLD <= '1';
- Write <= '1';
- when others =>
- end case;
- when "01100111" =>
- -- RRD
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Set_Addr_To <= aXY;
- when 3 =>
- Read_To_Reg <= '1';
- Set_BusB_To(2 downto 0) <= "110";
- Set_BusA_To(2 downto 0) <= "111";
- ALU_Op <= "1110";
- TStates <= "100";
- Set_Addr_To <= aXY;
- Save_ALU <= '1';
- when 4 =>
- I_RRD <= '1';
- Write <= '1';
- when others =>
- end case;
- when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
- -- RETI, RETN
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_TO <= aSP;
- when 2 =>
- IncDec_16 <= "0111";
- Set_Addr_To <= aSP;
- LDZ <= '1';
- when 3 =>
- Jump <= '1';
- IncDec_16 <= "0111";
- I_RETN <= '1';
- when others => null;
- end case;
- when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
- -- IN r,(C)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aBC;
- when 2 =>
- IORQ <= '1';
- if IR(5 downto 3) /= "110" then
- Read_To_Reg <= '1';
- Set_BusA_To(2 downto 0) <= IR(5 downto 3);
- end if;
- I_INRC <= '1';
- when others =>
- end case;
- when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
- -- OUT (C),r
- -- OUT (C),0
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aBC;
- Set_BusB_To(2 downto 0) <= IR(5 downto 3);
- if IR(5 downto 3) = "110" then
- Set_BusB_To(3) <= '1';
- end if;
- when 2 =>
- Write <= '1';
- IORQ <= '1';
- when others =>
- end case;
- when "10100010" | "10101010" | "10110010" | "10111010" =>
- -- INI, IND, INIR, INDR
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aBC;
- Set_BusB_To <= "1010";
- Set_BusA_To <= "0000";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- ALU_Op <= "0010";
- when 2 =>
- IORQ <= '1';
- Set_BusB_To <= "0110";
- Set_Addr_To <= aXY;
- when 3 =>
- if IR(3) = '0' then
- IncDec_16 <= "0010";
- else
- IncDec_16 <= "1010";
- end if;
- TStates <= "100";
- Write <= '1';
- I_BTR <= '1';
- when 4 =>
- NoRead <= '1';
- TStates <= "101";
- when others => null;
- end case;
- when "10100011" | "10101011" | "10110011" | "10111011" =>
- -- OUTI, OUTD, OTIR, OTDR
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- TStates <= "101";
- Set_Addr_To <= aXY;
- Set_BusB_To <= "1010";
- Set_BusA_To <= "0000";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- ALU_Op <= "0010";
- when 2 =>
- Set_BusB_To <= "0110";
- Set_Addr_To <= aBC;
- when 3 =>
- if IR(3) = '0' then
- IncDec_16 <= "0010";
- else
- IncDec_16 <= "1010";
- end if;
- IORQ <= '1';
- Write <= '1';
- I_BTR <= '1';
- when 4 =>
- NoRead <= '1';
- TStates <= "101";
- when others => null;
- end case;
- end case;
-
- end case;
-
- if Mode = 1 then
- if MCycle = "001" then
--- TStates <= "100";
- else
- TStates <= "011";
- end if;
- end if;
-
- if Mode = 3 then
- if MCycle = "001" then
--- TStates <= "100";
- else
- TStates <= "100";
- end if;
- end if;
-
- if Mode < 2 then
- if MCycle = "110" then
- Inc_PC <= '1';
- if Mode = 1 then
- Set_Addr_To <= aXY;
- TStates <= "100";
- Set_BusB_To(2 downto 0) <= SSS;
- Set_BusB_To(3) <= '0';
- end if;
- if IRB = "00110110" or IRB = "11001011" then
- Set_Addr_To <= aNone;
- end if;
- end if;
- if MCycle = "111" then
- if Mode = 0 then
- TStates <= "101";
- end if;
- if ISet /= "01" then
- Set_Addr_To <= aXY;
- end if;
- Set_BusB_To(2 downto 0) <= SSS;
- Set_BusB_To(3) <= '0';
- if IRB = "00110110" or ISet = "01" then
- -- LD (HL),n
- Inc_PC <= '1';
- else
- NoRead <= '1';
- end if;
- end if;
- end if;
-
- end process;
-
-end;
diff --git a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/T80/T80_Pack.vhd
deleted file mode 100644
index ac7d34da..00000000
--- a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/T80/T80_Pack.vhd
+++ /dev/null
@@ -1,208 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
- component T80
- generic(
- Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
- IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
- Flag_C : integer := 0;
- Flag_N : integer := 1;
- Flag_P : integer := 2;
- Flag_X : integer := 3;
- Flag_H : integer := 4;
- Flag_Y : integer := 5;
- Flag_Z : integer := 6;
- Flag_S : integer := 7
- );
- port(
- RESET_n : in std_logic;
- CLK_n : in std_logic;
- CEN : in std_logic;
- WAIT_n : in std_logic;
- INT_n : in std_logic;
- NMI_n : in std_logic;
- BUSRQ_n : in std_logic;
- M1_n : out std_logic;
- IORQ : out std_logic;
- NoRead : out std_logic;
- Write : out std_logic;
- RFSH_n : out std_logic;
- HALT_n : out std_logic;
- BUSAK_n : out std_logic;
- A : out std_logic_vector(15 downto 0);
- DInst : in std_logic_vector(7 downto 0);
- DI : in std_logic_vector(7 downto 0);
- DO : out std_logic_vector(7 downto 0);
- MC : out std_logic_vector(2 downto 0);
- TS : out std_logic_vector(2 downto 0);
- IntCycle_n : out std_logic;
- IntE : out std_logic;
- Stop : out std_logic
- );
- end component;
-
- component T80_Reg
- port(
- Clk : in std_logic;
- CEN : in std_logic;
- WEH : in std_logic;
- WEL : in std_logic;
- AddrA : in std_logic_vector(2 downto 0);
- AddrB : in std_logic_vector(2 downto 0);
- AddrC : in std_logic_vector(2 downto 0);
- DIH : in std_logic_vector(7 downto 0);
- DIL : in std_logic_vector(7 downto 0);
- DOAH : out std_logic_vector(7 downto 0);
- DOAL : out std_logic_vector(7 downto 0);
- DOBH : out std_logic_vector(7 downto 0);
- DOBL : out std_logic_vector(7 downto 0);
- DOCH : out std_logic_vector(7 downto 0);
- DOCL : out std_logic_vector(7 downto 0)
- );
- end component;
-
- component T80_MCode
- generic(
- Mode : integer := 0;
- Flag_C : integer := 0;
- Flag_N : integer := 1;
- Flag_P : integer := 2;
- Flag_X : integer := 3;
- Flag_H : integer := 4;
- Flag_Y : integer := 5;
- Flag_Z : integer := 6;
- Flag_S : integer := 7
- );
- port(
- IR : in std_logic_vector(7 downto 0);
- ISet : in std_logic_vector(1 downto 0);
- MCycle : in std_logic_vector(2 downto 0);
- F : in std_logic_vector(7 downto 0);
- NMICycle : in std_logic;
- IntCycle : in std_logic;
- MCycles : out std_logic_vector(2 downto 0);
- TStates : out std_logic_vector(2 downto 0);
- Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
- Inc_PC : out std_logic;
- Inc_WZ : out std_logic;
- IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
- Read_To_Reg : out std_logic;
- Read_To_Acc : out std_logic;
- Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
- Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
- ALU_Op : out std_logic_vector(3 downto 0);
- -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
- Save_ALU : out std_logic;
- PreserveC : out std_logic;
- Arith16 : out std_logic;
- Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
- IORQ : out std_logic;
- Jump : out std_logic;
- JumpE : out std_logic;
- JumpXY : out std_logic;
- Call : out std_logic;
- RstP : out std_logic;
- LDZ : out std_logic;
- LDW : out std_logic;
- LDSPHL : out std_logic;
- Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
- ExchangeDH : out std_logic;
- ExchangeRp : out std_logic;
- ExchangeAF : out std_logic;
- ExchangeRS : out std_logic;
- I_DJNZ : out std_logic;
- I_CPL : out std_logic;
- I_CCF : out std_logic;
- I_SCF : out std_logic;
- I_RETN : out std_logic;
- I_BT : out std_logic;
- I_BC : out std_logic;
- I_BTR : out std_logic;
- I_RLD : out std_logic;
- I_RRD : out std_logic;
- I_INRC : out std_logic;
- SetDI : out std_logic;
- SetEI : out std_logic;
- IMode : out std_logic_vector(1 downto 0);
- Halt : out std_logic;
- NoRead : out std_logic;
- Write : out std_logic
- );
- end component;
-
- component T80_ALU
- generic(
- Mode : integer := 0;
- Flag_C : integer := 0;
- Flag_N : integer := 1;
- Flag_P : integer := 2;
- Flag_X : integer := 3;
- Flag_H : integer := 4;
- Flag_Y : integer := 5;
- Flag_Z : integer := 6;
- Flag_S : integer := 7
- );
- port(
- Arith16 : in std_logic;
- Z16 : in std_logic;
- ALU_Op : in std_logic_vector(3 downto 0);
- IR : in std_logic_vector(5 downto 0);
- ISet : in std_logic_vector(1 downto 0);
- BusA : in std_logic_vector(7 downto 0);
- BusB : in std_logic_vector(7 downto 0);
- F_In : in std_logic_vector(7 downto 0);
- Q : out std_logic_vector(7 downto 0);
- F_Out : out std_logic_vector(7 downto 0)
- );
- end component;
-
-end;
diff --git a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/T80/T80_Reg.vhd
deleted file mode 100644
index 828485fb..00000000
--- a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/T80/T80_Reg.vhd
+++ /dev/null
@@ -1,105 +0,0 @@
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
--- 0242 : Initial release
---
--- 0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
- port(
- Clk : in std_logic;
- CEN : in std_logic;
- WEH : in std_logic;
- WEL : in std_logic;
- AddrA : in std_logic_vector(2 downto 0);
- AddrB : in std_logic_vector(2 downto 0);
- AddrC : in std_logic_vector(2 downto 0);
- DIH : in std_logic_vector(7 downto 0);
- DIL : in std_logic_vector(7 downto 0);
- DOAH : out std_logic_vector(7 downto 0);
- DOAL : out std_logic_vector(7 downto 0);
- DOBH : out std_logic_vector(7 downto 0);
- DOBL : out std_logic_vector(7 downto 0);
- DOCH : out std_logic_vector(7 downto 0);
- DOCL : out std_logic_vector(7 downto 0)
- );
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
- type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
- signal RegsH : Register_Image(0 to 7);
- signal RegsL : Register_Image(0 to 7);
-
-begin
-
- process (Clk)
- begin
- if Clk'event and Clk = '1' then
- if CEN = '1' then
- if WEH = '1' then
- RegsH(to_integer(unsigned(AddrA))) <= DIH;
- end if;
- if WEL = '1' then
- RegsL(to_integer(unsigned(AddrA))) <= DIL;
- end if;
- end if;
- end if;
- end process;
-
- DOAH <= RegsH(to_integer(unsigned(AddrA)));
- DOAL <= RegsL(to_integer(unsigned(AddrA)));
- DOBH <= RegsH(to_integer(unsigned(AddrB)));
- DOBL <= RegsL(to_integer(unsigned(AddrB)));
- DOCH <= RegsH(to_integer(unsigned(AddrC)));
- DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
diff --git a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/T80/T80se.vhd b/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/T80/T80se.vhd
deleted file mode 100644
index ac8886a8..00000000
--- a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/T80/T80se.vhd
+++ /dev/null
@@ -1,184 +0,0 @@
---
--- Z80 compatible microprocessor core, synchronous top level with clock enable
--- Different timing than the original z80
--- Inputs needs to be synchronous and outputs may glitch
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
--- 0235 : First release
---
--- 0236 : Added T2Write generic
---
--- 0237 : Fixed T2Write with wait state
---
--- 0238 : Updated for T80 interface change
---
--- 0240 : Updated for T80 interface change
---
--- 0242 : Updated for T80 interface change
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80se is
- generic(
- Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
- T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
- IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
- );
- port(
- RESET_n : in std_logic;
- CLK_n : in std_logic;
- CLKEN : in std_logic;
- WAIT_n : in std_logic;
- INT_n : in std_logic;
- NMI_n : in std_logic;
- BUSRQ_n : in std_logic;
- M1_n : out std_logic;
- MREQ_n : out std_logic;
- IORQ_n : out std_logic;
- RD_n : out std_logic;
- WR_n : out std_logic;
- RFSH_n : out std_logic;
- HALT_n : out std_logic;
- BUSAK_n : out std_logic;
- A : out std_logic_vector(15 downto 0);
- DI : in std_logic_vector(7 downto 0);
- DO : out std_logic_vector(7 downto 0)
- );
-end T80se;
-
-architecture rtl of T80se is
-
- signal IntCycle_n : std_logic;
- signal NoRead : std_logic;
- signal Write : std_logic;
- signal IORQ : std_logic;
- signal DI_Reg : std_logic_vector(7 downto 0);
- signal MCycle : std_logic_vector(2 downto 0);
- signal TState : std_logic_vector(2 downto 0);
-
-begin
-
- u0 : T80
- generic map(
- Mode => Mode,
- IOWait => IOWait)
- port map(
- CEN => CLKEN,
- M1_n => M1_n,
- IORQ => IORQ,
- NoRead => NoRead,
- Write => Write,
- RFSH_n => RFSH_n,
- HALT_n => HALT_n,
- WAIT_n => Wait_n,
- INT_n => INT_n,
- NMI_n => NMI_n,
- RESET_n => RESET_n,
- BUSRQ_n => BUSRQ_n,
- BUSAK_n => BUSAK_n,
- CLK_n => CLK_n,
- A => A,
- DInst => DI,
- DI => DI_Reg,
- DO => DO,
- MC => MCycle,
- TS => TState,
- IntCycle_n => IntCycle_n);
-
- process (RESET_n, CLK_n)
- begin
- if RESET_n = '0' then
- RD_n <= '1';
- WR_n <= '1';
- IORQ_n <= '1';
- MREQ_n <= '1';
- DI_Reg <= "00000000";
- elsif CLK_n'event and CLK_n = '1' then
- if CLKEN = '1' then
- RD_n <= '1';
- WR_n <= '1';
- IORQ_n <= '1';
- MREQ_n <= '1';
- if MCycle = "001" then
- if TState = "001" or (TState = "010" and Wait_n = '0') then
- RD_n <= not IntCycle_n;
- MREQ_n <= not IntCycle_n;
- IORQ_n <= IntCycle_n;
- end if;
- if TState = "011" then
- MREQ_n <= '0';
- end if;
- else
- if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
- RD_n <= '0';
- IORQ_n <= not IORQ;
- MREQ_n <= IORQ;
- end if;
- if T2Write = 0 then
- if TState = "010" and Write = '1' then
- WR_n <= '0';
- IORQ_n <= not IORQ;
- MREQ_n <= IORQ;
- end if;
- else
- if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
- WR_n <= '0';
- IORQ_n <= not IORQ;
- MREQ_n <= IORQ;
- end if;
- end if;
- end if;
- if TState = "010" and Wait_n = '1' then
- DI_Reg <= DI;
- end if;
- end if;
- end if;
- end process;
-
-end;
diff --git a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/pll.v b/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/pll.v
index 3c7dc7fe..f0530bf2 100644
--- a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/pll.v
+++ b/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/pll.v
@@ -14,7 +14,7 @@
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
-// 13.1.4 Build 182 03/12/2014 SJ Web Edition
+// 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
// ************************************************************
@@ -41,31 +41,35 @@ module pll (
c0,
c1,
c2,
+ c3,
locked);
input inclk0;
output c0;
output c1;
output c2;
+ output c3;
output locked;
wire [4:0] sub_wire0;
- wire sub_wire2;
- wire [0:0] sub_wire7 = 1'h0;
- wire [2:2] sub_wire4 = sub_wire0[2:2];
- wire [0:0] sub_wire3 = sub_wire0[0:0];
+ wire sub_wire3;
+ wire [0:0] sub_wire8 = 1'h0;
+ wire [2:2] sub_wire5 = sub_wire0[2:2];
+ wire [0:0] sub_wire4 = sub_wire0[0:0];
+ wire [3:3] sub_wire2 = sub_wire0[3:3];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
- wire locked = sub_wire2;
- wire c0 = sub_wire3;
- wire c2 = sub_wire4;
- wire sub_wire5 = inclk0;
- wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
+ wire c3 = sub_wire2;
+ wire locked = sub_wire3;
+ wire c0 = sub_wire4;
+ wire c2 = sub_wire5;
+ wire sub_wire6 = inclk0;
+ wire [1:0] sub_wire7 = {sub_wire8, sub_wire6};
altpll altpll_component (
- .inclk (sub_wire6),
+ .inclk (sub_wire7),
.clk (sub_wire0),
- .locked (sub_wire2),
+ .locked (sub_wire3),
.activeclock (),
.areset (1'b0),
.clkbad (),
@@ -102,18 +106,22 @@ module pll (
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
- altpll_component.clk0_divide_by = 26,
+ altpll_component.clk0_divide_by = 115,
altpll_component.clk0_duty_cycle = 50,
- altpll_component.clk0_multiply_by = 47,
+ altpll_component.clk0_multiply_by = 208,
altpll_component.clk0_phase_shift = "0",
- altpll_component.clk1_divide_by = 104,
+ altpll_component.clk1_divide_by = 115,
altpll_component.clk1_duty_cycle = 50,
- altpll_component.clk1_multiply_by = 47,
+ altpll_component.clk1_multiply_by = 52,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 395,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 208,
altpll_component.clk2_phase_shift = "0",
+ altpll_component.clk3_divide_by = 115,
+ altpll_component.clk3_duty_cycle = 50,
+ altpll_component.clk3_multiply_by = 26,
+ altpll_component.clk3_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone III",
@@ -149,7 +157,7 @@ module pll (
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
- altpll_component.port_clk3 = "PORT_UNUSED",
+ altpll_component.port_clk3 = "PORT_USED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
@@ -187,15 +195,18 @@ endmodule
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "26"
-// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "104"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "115"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "115"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "395"
+// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "115"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.807693"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.201923"
+// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.834782"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.208695"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "14.217722"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.104348"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -218,32 +229,40 @@ endmodule
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "47"
-// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "47"
+// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "208"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "52"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "208"
+// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "26"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.78400000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.19600000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "14.22800000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
@@ -268,31 +287,38 @@ endmodule
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "26"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "115"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "47"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "208"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "104"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "115"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "47"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "52"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "395"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "208"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "115"
+// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "26"
+// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
@@ -327,7 +353,7 @@ endmodule
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
@@ -346,6 +372,7 @@ endmodule
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
@@ -353,6 +380,7 @@ endmodule
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
diff --git a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/power_surge.vhd b/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/power_surge.vhd
index 2cad8bca..8426d71b 100644
--- a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/power_surge.vhd
+++ b/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/power_surge.vhd
@@ -81,6 +81,7 @@ use ieee.numeric_std.all;
entity power_surge is
port(
+ clock_6 : in std_logic;
clock_12 : in std_logic;
clock_14 : in std_logic;
reset : in std_logic;
@@ -121,7 +122,6 @@ architecture struct of power_surge is
signal reset_n: std_logic;
signal clock_12n : std_logic;
- signal clock_6 : std_logic := '0';
signal clock_6n : std_logic;
signal clock_div : std_logic_vector(1 downto 0) := "00";
@@ -220,19 +220,6 @@ clock_12n <= not clock_12;
clock_6n <= not clock_6;
reset_n <= not reset;
--- make 6MHz clock from 12MHz
-process (clock_12)
-begin
- if reset='1' then
- clock_6 <= '0';
- else
- if rising_edge(clock_12) then
- clock_6 <= not clock_6;
- end if;
- end if;
-end process;
-
-
--------------------------
-- Video/sprite scanner --
--------------------------
@@ -614,7 +601,7 @@ begin
if hcnt = hcnt_base-4 then
hblank <= '1';
- if vcnt = 496 then
+ if vcnt = 495 then
vblank <= '1'; -- 492 ok
elsif vcnt = 262 then
vblank <= '0'; -- 262 ok
diff --git a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/sdram.sv b/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/sdram.sv
new file mode 100644
index 00000000..53a14e5e
--- /dev/null
+++ b/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/sdram.sv
@@ -0,0 +1,254 @@
+//
+// sdram.v
+//
+// Static RAM controller implementation using SDRAM MT48LC16M16A2
+//
+// Copyright (c) 2015,2016 Sorgelig
+//
+// Some parts of SDRAM code used from project:
+// http://hamsterworks.co.nz/mediawiki/index.php/Simple_SDRAM_Controller
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see .
+//
+// ------------------------------------------
+//
+// v2.1 - Add universal 8/16 bit mode.
+//
+
+module sdram
+(
+ input init, // reset to initialize RAM
+ input clk, // clock ~100MHz
+ //
+ // SDRAM_* - signals to the MT48LC16M16 chip
+ inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus
+ output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus
+ output reg SDRAM_DQML, // two byte masks
+ output reg SDRAM_DQMH, //
+ output reg [1:0] SDRAM_BA, // two banks
+ output SDRAM_nCS, // a single chip select
+ output SDRAM_nWE, // write enable
+ output SDRAM_nRAS, // row address select
+ output SDRAM_nCAS, // columns address select
+ output SDRAM_CKE, // clock enable
+ //
+ input [1:0] wtbt, // 16bit mode: bit1 - write high byte, bit0 - write low byte,
+ // 8bit mode: 2'b00 - use addr[0] to decide which byte to write
+ // Ignored while reading.
+ //
+ input [24:0] addr, // 25 bit address for 8bit mode. addr[0] = 0 for 16bit mode for correct operations.
+ output [15:0] dout, // data output to cpu
+ input [15:0] din, // data input from cpu
+ input we, // cpu requests write
+ input rd, // cpu requests read
+ output reg ready // dout is valid. Ready to accept new read/write.
+);
+
+assign SDRAM_nCS = command[3];
+assign SDRAM_nRAS = command[2];
+assign SDRAM_nCAS = command[1];
+assign SDRAM_nWE = command[0];
+assign SDRAM_CKE = cke;
+
+// no burst configured
+localparam BURST_LENGTH = 3'b000; // 000=1, 001=2, 010=4, 011=8
+localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
+localparam CAS_LATENCY = 3'd2; // 2 for < 100MHz, 3 for >100MHz
+localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed
+localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write
+localparam MODE = {3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
+
+localparam sdram_startup_cycles= 14'd12100;// 100us, plus a little more, @ 100MHz
+localparam cycles_per_refresh = 14'd186; // (64000*24)/8192-1 Calc'd as (64ms @ 24MHz)/8192 rose
+localparam startup_refresh_max = 14'b11111111111111;
+
+// SDRAM commands
+localparam CMD_INHIBIT = 4'b1111;
+localparam CMD_NOP = 4'b0111;
+localparam CMD_ACTIVE = 4'b0011;
+localparam CMD_READ = 4'b0101;
+localparam CMD_WRITE = 4'b0100;
+localparam CMD_BURST_TERMINATE = 4'b0110;
+localparam CMD_PRECHARGE = 4'b0010;
+localparam CMD_AUTO_REFRESH = 4'b0001;
+localparam CMD_LOAD_MODE = 4'b0000;
+
+reg [13:0] refresh_count = startup_refresh_max - sdram_startup_cycles;
+reg [3:0] command = CMD_INHIBIT;
+reg cke = 0;
+reg [24:0] save_addr;
+reg [15:0] data;
+
+assign dout = save_addr[0] ? {data[7:0], data[15:8]} : {data[15:8], data[7:0]};
+typedef enum
+{
+ STATE_STARTUP,
+ STATE_OPEN_1,
+ STATE_WRITE,
+ STATE_READ,
+ STATE_IDLE, STATE_IDLE_1, STATE_IDLE_2, STATE_IDLE_3,
+ STATE_IDLE_4, STATE_IDLE_5, STATE_IDLE_6, STATE_IDLE_7
+} state_t;
+
+state_t state = STATE_STARTUP;
+
+always @(posedge clk) begin
+ reg old_we, old_rd;
+ reg [CAS_LATENCY:0] data_ready_delay;
+
+ reg [15:0] new_data;
+ reg [1:0] new_wtbt;
+ reg new_we;
+ reg new_rd;
+ reg save_we = 1;
+
+
+ command <= CMD_NOP;
+ refresh_count <= refresh_count+1'b1;
+
+ data_ready_delay <= {1'b0, data_ready_delay[CAS_LATENCY:1]};
+
+ if(data_ready_delay[0]) data <= SDRAM_DQ;
+
+ case(state)
+ STATE_STARTUP: begin
+ //------------------------------------------------------------------------
+ //-- This is the initial startup state, where we wait for at least 100us
+ //-- before starting the start sequence
+ //--
+ //-- The initialisation is sequence is
+ //-- * de-assert SDRAM_CKE
+ //-- * 100us wait,
+ //-- * assert SDRAM_CKE
+ //-- * wait at least one cycle,
+ //-- * PRECHARGE
+ //-- * wait 2 cycles
+ //-- * REFRESH,
+ //-- * tREF wait
+ //-- * REFRESH,
+ //-- * tREF wait
+ //-- * LOAD_MODE_REG
+ //-- * 2 cycles wait
+ //------------------------------------------------------------------------
+ cke <= 1;
+ SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
+ SDRAM_DQML <= 1;
+ SDRAM_DQMH <= 1;
+ SDRAM_A <= 0;
+ SDRAM_BA <= 0;
+
+ // All the commands during the startup are NOPS, except these
+ if(refresh_count == startup_refresh_max-31) begin
+ // ensure all rows are closed
+ command <= CMD_PRECHARGE;
+ SDRAM_A[10] <= 1; // all banks
+ SDRAM_BA <= 2'b00;
+ end else if (refresh_count == startup_refresh_max-23) begin
+ // these refreshes need to be at least tREF (66ns) apart
+ command <= CMD_AUTO_REFRESH;
+ end else if (refresh_count == startup_refresh_max-15)
+ command <= CMD_AUTO_REFRESH;
+ else if (refresh_count == startup_refresh_max-7) begin
+ // Now load the mode register
+ command <= CMD_LOAD_MODE;
+ SDRAM_A <= MODE;
+ end
+
+ //------------------------------------------------------
+ //-- if startup is complete then go into idle mode,
+ //-- get prepared to accept a new command, and schedule
+ //-- the first refresh cycle
+ //------------------------------------------------------
+ if(!refresh_count) begin
+ state <= STATE_IDLE;
+ ready <= 1;
+ refresh_count <= 0;
+ end
+ end
+
+ STATE_IDLE_7: state <= STATE_IDLE_6;
+ STATE_IDLE_6: state <= STATE_IDLE_5;
+ STATE_IDLE_5: state <= STATE_IDLE_4;
+ STATE_IDLE_4: state <= STATE_IDLE_3;
+ STATE_IDLE_3: state <= STATE_IDLE_2;
+ STATE_IDLE_2: state <= STATE_IDLE_1;
+ STATE_IDLE_1: begin
+ SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
+ state <= STATE_IDLE;
+ // mask possible refresh to reduce colliding.
+ if(refresh_count > cycles_per_refresh) begin
+ //------------------------------------------------------------------------
+ //-- Start the refresh cycle.
+ //-- This tasks tRFC (66ns), so 2 idle cycles are needed @ 24MHz
+ //------------------------------------------------------------------------
+ state <= STATE_IDLE_2;
+ command <= CMD_AUTO_REFRESH;
+ refresh_count <= refresh_count - cycles_per_refresh + 1'd1;
+ end
+ end
+
+ STATE_IDLE: begin
+ // Priority is to issue a refresh if one is outstanding
+ if(refresh_count > (cycles_per_refresh<<1)) state <= STATE_IDLE_1;
+ else if(new_rd | new_we) begin
+ new_we <= 0;
+ new_rd <= 0;
+ save_addr<= addr;
+ save_we <= new_we;
+ state <= STATE_OPEN_1;
+ command <= CMD_ACTIVE;
+ SDRAM_A <= addr[13:1];
+ SDRAM_BA <= addr[24:23];
+ end
+ end
+
+ // ACTIVE-to-READ or WRITE delay >20ns (1 cycle @ 24 MHz)(-75)
+ STATE_OPEN_1: begin
+ SDRAM_A <= {4'b0010, save_addr[22:14]};
+ SDRAM_DQML <= save_we & (new_wtbt ? ~new_wtbt[0] : save_addr[0]);
+ SDRAM_DQMH <= save_we & (new_wtbt ? ~new_wtbt[1] : ~save_addr[0]);
+ state <= save_we ? STATE_WRITE : STATE_READ;
+ end
+
+ STATE_READ: begin
+ state <= STATE_IDLE_5;
+ command <= CMD_READ;
+ SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
+
+ // Schedule reading the data values off the bus
+ data_ready_delay[CAS_LATENCY] <= 1;
+ end
+
+ STATE_WRITE: begin
+ state <= STATE_IDLE_5;
+ command <= CMD_WRITE;
+ SDRAM_DQ <= new_wtbt ? new_data : {new_data[7:0], new_data[7:0]};
+ ready <= 1;
+ end
+ endcase
+
+ if(init) begin
+ state <= STATE_STARTUP;
+ refresh_count <= startup_refresh_max - sdram_startup_cycles;
+ end
+
+ old_we <= we;
+ old_rd <= rd;
+ if(we & ~old_we) {ready, new_we, new_data, new_wtbt} <= {1'b0, 1'b1, din, wtbt};
+ else
+ if((rd & ~old_rd) || (rd & old_rd & (save_addr != addr))) {ready, new_rd} <= {1'b0, 1'b1};
+
+end
+
+endmodule
diff --git a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/time_pilot_sound_board.vhd b/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/time_pilot_sound_board.vhd
index 0965ad14..c92f6e64 100644
--- a/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/time_pilot_sound_board.vhd
+++ b/Arcade_MiST/Konami Classic/Power_Surge_MiST/rtl/time_pilot_sound_board.vhd
@@ -34,7 +34,9 @@ port(
sound_cmd : in std_logic_vector(7 downto 0);
sound_trig : in std_logic;
- audio_out : out std_logic_vector(10 downto 0)
+ audio_out : out std_logic_vector(10 downto 0);
+
+ dbg_cpu_addr : out std_logic_vector(15 downto 0)
);
end time_pilot_sound_board;
@@ -46,8 +48,8 @@ architecture struct of time_pilot_sound_board is
signal clock_div1 : std_logic_vector(11 downto 0) := (others => '0');
signal biquinary_div : std_logic_vector(3 downto 0) := (others => '0');
- signal cpu_clock : std_logic;
- signal ayx_clock : std_logic;
+ signal cpu_clock_en : std_logic;
+ signal ayx_clock_en : std_logic;
signal cpu_addr : std_logic_vector(15 downto 0);
signal cpu_di : std_logic_vector( 7 downto 0);
@@ -115,6 +117,14 @@ begin
clock_14n <= not clock_14;
reset_n <= not reset;
+-- debug
+process (reset, clock_14)
+begin
+ if rising_edge(clock_14) and cpu_mreq_n ='0' then
+ dbg_cpu_addr <= cpu_addr;
+ end if;
+end process;
+
--------------------------------------------------------
-- RC filters equation
--
@@ -231,11 +241,11 @@ begin
end process;
-- make clocks for cpu and sound generators
-cpu_clock <= clock_div1(2);
-ayx_clock <= not clock_div1(2);
+cpu_clock_en <= '1' when clock_div1(2 downto 0) = "011" else '0';
+ayx_clock_en <= '1' when clock_div1(2 downto 0) = "111" else '0';
-- mux rom/ram/devices data ouput to cpu data input w.r.t cpu address
-cpu_di <= cpu_rom_do when cpu_addr(15 downto 12) = "0000" else -- 0000-0FFF
+cpu_di <= cpu_rom_do when cpu_addr(15 downto 13) = "000" else -- 0000-1FFF
wram_do when cpu_addr(15 downto 12) = "0011" else -- 3000-3FFF
ay1_do when cpu_addr(15 downto 13) = "010" else -- 4000-5FFF
ay2_do when cpu_addr(15 downto 13) = "011" else -- 6000-7FFF
@@ -267,9 +277,9 @@ ay1_port_b_di <= biquinary_div(0)&biquinary_div(3)&biquinary_div(2)&clock_div1(1
clr_irq_n <= reset_n and (cpu_m1_n or cpu_iorq_n);
-- regsiter filters commands (11 bits data are cpu address)
-process (cpu_clock)
+process (clock_14, cpu_clock_en)
begin
- if rising_edge(cpu_clock) then
+ if rising_edge(clock_14) and cpu_clock_en = '1' then
if filter_cmd_we = '1' then filter_cmd <= cpu_addr(11 downto 0); end if;
end if;
end process;
@@ -293,9 +303,9 @@ begin
end process;
-- demux AY chips output
-process (ayx_clock)
+process (clock_14, ayx_clock_en)
begin
- if rising_edge(ayx_clock) then
+ if rising_edge(clock_14) and ayx_clock_en = '1' then
if ay1_audio_chan = "00" then ay1_chan_a <= ay1_audio_muxed; end if;
if ay1_audio_chan = "01" then ay1_chan_b <= ay1_audio_muxed; end if;
if ay1_audio_chan = "10" then ay1_chan_c <= ay1_audio_muxed; end if;
@@ -310,8 +320,8 @@ cpu : entity work.T80se
generic map(Mode => 0, T2Write => 1, IOWait => 1)
port map(
RESET_n => reset_n,
- CLK_n => cpu_clock,
- CLKEN => '1',
+ CLK_n => clock_14,
+ CLKEN => cpu_clock_en,
WAIT_n => '1',
INT_n => cpu_irq_n,
NMI_n => '1',
@@ -375,9 +385,9 @@ port map(
O_IOB => open, -- out std_logic_vector(7 downto 0);
O_IOB_OE_L => open, -- out std_logic;
- ENA => '1', --cpu_ena, -- in std_logic; -- clock enable for higher speed operation
+ ENA => ayx_clock_en, -- in std_logic; -- clock enable for higher speed operation
RESET_L => reset_n, -- in std_logic;
- CLK => ayx_clock -- in std_logic -- note 6 Mhz
+ CLK => clock_14 -- in std_logic
);
-- AY-3-8910 #2
@@ -407,9 +417,9 @@ port map(
O_IOB => open, -- out std_logic_vector(7 downto 0);
O_IOB_OE_L => open, -- out std_logic;
- ENA => '1', --cpu_ena, -- in std_logic; -- clock enable for higher speed operation
+ ENA => ayx_clock_en, -- in std_logic; -- clock enable for higher speed operation
RESET_L => reset_n, -- in std_logic;
- CLK => ayx_clock -- in std_logic -- note 6 Mhz
+ CLK => clock_14 -- in std_logic
);
diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80/T80.vhd
deleted file mode 100644
index 398fa0df..00000000
--- a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80/T80.vhd
+++ /dev/null
@@ -1,1073 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
--- 0208 : First complete release
---
--- 0210 : Fixed wait and halt
---
--- 0211 : Fixed Refresh addition and IM 1
---
--- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
--- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
--- 0235 : Added clock enable and IM 2 fix by Mike Johnson
---
--- 0237 : Changed 8080 I/O address output, added IntE output
---
--- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
--- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
--- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
--- 0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
- generic(
- Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
- IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
- Flag_C : integer := 0;
- Flag_N : integer := 1;
- Flag_P : integer := 2;
- Flag_X : integer := 3;
- Flag_H : integer := 4;
- Flag_Y : integer := 5;
- Flag_Z : integer := 6;
- Flag_S : integer := 7
- );
- port(
- RESET_n : in std_logic;
- CLK_n : in std_logic;
- CEN : in std_logic;
- WAIT_n : in std_logic;
- INT_n : in std_logic;
- NMI_n : in std_logic;
- BUSRQ_n : in std_logic;
- M1_n : out std_logic;
- IORQ : out std_logic;
- NoRead : out std_logic;
- Write : out std_logic;
- RFSH_n : out std_logic;
- HALT_n : out std_logic;
- BUSAK_n : out std_logic;
- A : out std_logic_vector(15 downto 0);
- DInst : in std_logic_vector(7 downto 0);
- DI : in std_logic_vector(7 downto 0);
- DO : out std_logic_vector(7 downto 0);
- MC : out std_logic_vector(2 downto 0);
- TS : out std_logic_vector(2 downto 0);
- IntCycle_n : out std_logic;
- IntE : out std_logic;
- Stop : out std_logic
- );
-end T80;
-
-architecture rtl of T80 is
-
- constant aNone : std_logic_vector(2 downto 0) := "111";
- constant aBC : std_logic_vector(2 downto 0) := "000";
- constant aDE : std_logic_vector(2 downto 0) := "001";
- constant aXY : std_logic_vector(2 downto 0) := "010";
- constant aIOA : std_logic_vector(2 downto 0) := "100";
- constant aSP : std_logic_vector(2 downto 0) := "101";
- constant aZI : std_logic_vector(2 downto 0) := "110";
-
- -- Registers
- signal ACC, F : std_logic_vector(7 downto 0);
- signal Ap, Fp : std_logic_vector(7 downto 0);
- signal I : std_logic_vector(7 downto 0);
- signal R : unsigned(7 downto 0);
- signal SP, PC : unsigned(15 downto 0);
- signal RegDIH : std_logic_vector(7 downto 0);
- signal RegDIL : std_logic_vector(7 downto 0);
- signal RegBusA : std_logic_vector(15 downto 0);
- signal RegBusB : std_logic_vector(15 downto 0);
- signal RegBusC : std_logic_vector(15 downto 0);
- signal RegAddrA_r : std_logic_vector(2 downto 0);
- signal RegAddrA : std_logic_vector(2 downto 0);
- signal RegAddrB_r : std_logic_vector(2 downto 0);
- signal RegAddrB : std_logic_vector(2 downto 0);
- signal RegAddrC : std_logic_vector(2 downto 0);
- signal RegWEH : std_logic;
- signal RegWEL : std_logic;
- signal Alternate : std_logic;
-
- -- Help Registers
- signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register
- signal IR : std_logic_vector(7 downto 0); -- Instruction register
- signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector
- signal RegBusA_r : std_logic_vector(15 downto 0);
-
- signal ID16 : signed(15 downto 0);
- signal Save_Mux : std_logic_vector(7 downto 0);
-
- signal TState : unsigned(2 downto 0);
- signal MCycle : std_logic_vector(2 downto 0);
- signal IntE_FF1 : std_logic;
- signal IntE_FF2 : std_logic;
- signal Halt_FF : std_logic;
- signal BusReq_s : std_logic;
- signal BusAck : std_logic;
- signal ClkEn : std_logic;
- signal NMI_s : std_logic;
- signal INT_s : std_logic;
- signal IStatus : std_logic_vector(1 downto 0);
-
- signal DI_Reg : std_logic_vector(7 downto 0);
- signal T_Res : std_logic;
- signal XY_State : std_logic_vector(1 downto 0);
- signal Pre_XY_F_M : std_logic_vector(2 downto 0);
- signal NextIs_XY_Fetch : std_logic;
- signal XY_Ind : std_logic;
- signal No_BTR : std_logic;
- signal BTR_r : std_logic;
- signal Auto_Wait : std_logic;
- signal Auto_Wait_t1 : std_logic;
- signal Auto_Wait_t2 : std_logic;
- signal IncDecZ : std_logic;
-
- -- ALU signals
- signal BusB : std_logic_vector(7 downto 0);
- signal BusA : std_logic_vector(7 downto 0);
- signal ALU_Q : std_logic_vector(7 downto 0);
- signal F_Out : std_logic_vector(7 downto 0);
-
- -- Registered micro code outputs
- signal Read_To_Reg_r : std_logic_vector(4 downto 0);
- signal Arith16_r : std_logic;
- signal Z16_r : std_logic;
- signal ALU_Op_r : std_logic_vector(3 downto 0);
- signal Save_ALU_r : std_logic;
- signal PreserveC_r : std_logic;
- signal MCycles : std_logic_vector(2 downto 0);
-
- -- Micro code outputs
- signal MCycles_d : std_logic_vector(2 downto 0);
- signal TStates : std_logic_vector(2 downto 0);
- signal IntCycle : std_logic;
- signal NMICycle : std_logic;
- signal Inc_PC : std_logic;
- signal Inc_WZ : std_logic;
- signal IncDec_16 : std_logic_vector(3 downto 0);
- signal Prefix : std_logic_vector(1 downto 0);
- signal Read_To_Acc : std_logic;
- signal Read_To_Reg : std_logic;
- signal Set_BusB_To : std_logic_vector(3 downto 0);
- signal Set_BusA_To : std_logic_vector(3 downto 0);
- signal ALU_Op : std_logic_vector(3 downto 0);
- signal Save_ALU : std_logic;
- signal PreserveC : std_logic;
- signal Arith16 : std_logic;
- signal Set_Addr_To : std_logic_vector(2 downto 0);
- signal Jump : std_logic;
- signal JumpE : std_logic;
- signal JumpXY : std_logic;
- signal Call : std_logic;
- signal RstP : std_logic;
- signal LDZ : std_logic;
- signal LDW : std_logic;
- signal LDSPHL : std_logic;
- signal IORQ_i : std_logic;
- signal Special_LD : std_logic_vector(2 downto 0);
- signal ExchangeDH : std_logic;
- signal ExchangeRp : std_logic;
- signal ExchangeAF : std_logic;
- signal ExchangeRS : std_logic;
- signal I_DJNZ : std_logic;
- signal I_CPL : std_logic;
- signal I_CCF : std_logic;
- signal I_SCF : std_logic;
- signal I_RETN : std_logic;
- signal I_BT : std_logic;
- signal I_BC : std_logic;
- signal I_BTR : std_logic;
- signal I_RLD : std_logic;
- signal I_RRD : std_logic;
- signal I_INRC : std_logic;
- signal SetDI : std_logic;
- signal SetEI : std_logic;
- signal IMode : std_logic_vector(1 downto 0);
- signal Halt : std_logic;
-
-begin
-
- mcode : T80_MCode
- generic map(
- Mode => Mode,
- Flag_C => Flag_C,
- Flag_N => Flag_N,
- Flag_P => Flag_P,
- Flag_X => Flag_X,
- Flag_H => Flag_H,
- Flag_Y => Flag_Y,
- Flag_Z => Flag_Z,
- Flag_S => Flag_S)
- port map(
- IR => IR,
- ISet => ISet,
- MCycle => MCycle,
- F => F,
- NMICycle => NMICycle,
- IntCycle => IntCycle,
- MCycles => MCycles_d,
- TStates => TStates,
- Prefix => Prefix,
- Inc_PC => Inc_PC,
- Inc_WZ => Inc_WZ,
- IncDec_16 => IncDec_16,
- Read_To_Acc => Read_To_Acc,
- Read_To_Reg => Read_To_Reg,
- Set_BusB_To => Set_BusB_To,
- Set_BusA_To => Set_BusA_To,
- ALU_Op => ALU_Op,
- Save_ALU => Save_ALU,
- PreserveC => PreserveC,
- Arith16 => Arith16,
- Set_Addr_To => Set_Addr_To,
- IORQ => IORQ_i,
- Jump => Jump,
- JumpE => JumpE,
- JumpXY => JumpXY,
- Call => Call,
- RstP => RstP,
- LDZ => LDZ,
- LDW => LDW,
- LDSPHL => LDSPHL,
- Special_LD => Special_LD,
- ExchangeDH => ExchangeDH,
- ExchangeRp => ExchangeRp,
- ExchangeAF => ExchangeAF,
- ExchangeRS => ExchangeRS,
- I_DJNZ => I_DJNZ,
- I_CPL => I_CPL,
- I_CCF => I_CCF,
- I_SCF => I_SCF,
- I_RETN => I_RETN,
- I_BT => I_BT,
- I_BC => I_BC,
- I_BTR => I_BTR,
- I_RLD => I_RLD,
- I_RRD => I_RRD,
- I_INRC => I_INRC,
- SetDI => SetDI,
- SetEI => SetEI,
- IMode => IMode,
- Halt => Halt,
- NoRead => NoRead,
- Write => Write);
-
- alu : T80_ALU
- generic map(
- Mode => Mode,
- Flag_C => Flag_C,
- Flag_N => Flag_N,
- Flag_P => Flag_P,
- Flag_X => Flag_X,
- Flag_H => Flag_H,
- Flag_Y => Flag_Y,
- Flag_Z => Flag_Z,
- Flag_S => Flag_S)
- port map(
- Arith16 => Arith16_r,
- Z16 => Z16_r,
- ALU_Op => ALU_Op_r,
- IR => IR(5 downto 0),
- ISet => ISet,
- BusA => BusA,
- BusB => BusB,
- F_In => F,
- Q => ALU_Q,
- F_Out => F_Out);
-
- ClkEn <= CEN and not BusAck;
-
- T_Res <= '1' when TState = unsigned(TStates) else '0';
-
- NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
- ((Set_Addr_To = aXY) or
- (MCycle = "001" and IR = "11001011") or
- (MCycle = "001" and IR = "00110110")) else '0';
-
- Save_Mux <= BusB when ExchangeRp = '1' else
- DI_Reg when Save_ALU_r = '0' else
- ALU_Q;
-
- process (RESET_n, CLK_n)
- begin
- if RESET_n = '0' then
- PC <= (others => '0'); -- Program Counter
- A <= (others => '0');
- TmpAddr <= (others => '0');
- IR <= "00000000";
- ISet <= "00";
- XY_State <= "00";
- IStatus <= "00";
- MCycles <= "000";
- DO <= "00000000";
-
- ACC <= (others => '1');
- F <= (others => '1');
- Ap <= (others => '1');
- Fp <= (others => '1');
- I <= (others => '0');
- R <= (others => '0');
- SP <= (others => '1');
- Alternate <= '0';
-
- Read_To_Reg_r <= "00000";
- F <= (others => '1');
- Arith16_r <= '0';
- BTR_r <= '0';
- Z16_r <= '0';
- ALU_Op_r <= "0000";
- Save_ALU_r <= '0';
- PreserveC_r <= '0';
- XY_Ind <= '0';
-
- elsif CLK_n'event and CLK_n = '1' then
-
- if ClkEn = '1' then
-
- ALU_Op_r <= "0000";
- Save_ALU_r <= '0';
- Read_To_Reg_r <= "00000";
-
- MCycles <= MCycles_d;
-
- if IMode /= "11" then
- IStatus <= IMode;
- end if;
-
- Arith16_r <= Arith16;
- PreserveC_r <= PreserveC;
- if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
- Z16_r <= '1';
- else
- Z16_r <= '0';
- end if;
-
- if MCycle = "001" and TState(2) = '0' then
- -- MCycle = 1 and TState = 1, 2, or 3
-
- if TState = 2 and Wait_n = '1' then
- if Mode < 2 then
- A(7 downto 0) <= std_logic_vector(R);
- A(15 downto 8) <= I;
- R(6 downto 0) <= R(6 downto 0) + 1;
- end if;
-
- if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
- PC <= PC + 1;
- end if;
-
- if IntCycle = '1' and IStatus = "01" then
- IR <= "11111111";
- elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
- IR <= "00000000";
- else
- IR <= DInst;
- end if;
-
- ISet <= "00";
- if Prefix /= "00" then
- if Prefix = "11" then
- if IR(5) = '1' then
- XY_State <= "10";
- else
- XY_State <= "01";
- end if;
- else
- if Prefix = "10" then
- XY_State <= "00";
- XY_Ind <= '0';
- end if;
- ISet <= Prefix;
- end if;
- else
- XY_State <= "00";
- XY_Ind <= '0';
- end if;
- end if;
-
- else
- -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
- if MCycle = "110" then
- XY_Ind <= '1';
- if Prefix = "01" then
- ISet <= "01";
- end if;
- end if;
-
- if T_Res = '1' then
- BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
- if Jump = '1' then
- A(15 downto 8) <= DI_Reg;
- A(7 downto 0) <= TmpAddr(7 downto 0);
- PC(15 downto 8) <= unsigned(DI_Reg);
- PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
- elsif JumpXY = '1' then
- A <= RegBusC;
- PC <= unsigned(RegBusC);
- elsif Call = '1' or RstP = '1' then
- A <= TmpAddr;
- PC <= unsigned(TmpAddr);
- elsif MCycle = MCycles and NMICycle = '1' then
- A <= "0000000001100110";
- PC <= "0000000001100110";
- elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
- A(15 downto 8) <= I;
- A(7 downto 0) <= TmpAddr(7 downto 0);
- PC(15 downto 8) <= unsigned(I);
- PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
- else
- case Set_Addr_To is
- when aXY =>
- if XY_State = "00" then
- A <= RegBusC;
- else
- if NextIs_XY_Fetch = '1' then
- A <= std_logic_vector(PC);
- else
- A <= TmpAddr;
- end if;
- end if;
- when aIOA =>
- if Mode = 3 then
- -- Memory map I/O on GBZ80
- A(15 downto 8) <= (others => '1');
- elsif Mode = 2 then
- -- Duplicate I/O address on 8080
- A(15 downto 8) <= DI_Reg;
- else
- A(15 downto 8) <= ACC;
- end if;
- A(7 downto 0) <= DI_Reg;
- when aSP =>
- A <= std_logic_vector(SP);
- when aBC =>
- if Mode = 3 and IORQ_i = '1' then
- -- Memory map I/O on GBZ80
- A(15 downto 8) <= (others => '1');
- A(7 downto 0) <= RegBusC(7 downto 0);
- else
- A <= RegBusC;
- end if;
- when aDE =>
- A <= RegBusC;
- when aZI =>
- if Inc_WZ = '1' then
- A <= std_logic_vector(unsigned(TmpAddr) + 1);
- else
- A(15 downto 8) <= DI_Reg;
- A(7 downto 0) <= TmpAddr(7 downto 0);
- end if;
- when others =>
- A <= std_logic_vector(PC);
- end case;
- end if;
-
- Save_ALU_r <= Save_ALU;
- ALU_Op_r <= ALU_Op;
-
- if I_CPL = '1' then
- -- CPL
- ACC <= not ACC;
- F(Flag_Y) <= not ACC(5);
- F(Flag_H) <= '1';
- F(Flag_X) <= not ACC(3);
- F(Flag_N) <= '1';
- end if;
- if I_CCF = '1' then
- -- CCF
- F(Flag_C) <= not F(Flag_C);
- F(Flag_Y) <= ACC(5);
- F(Flag_H) <= F(Flag_C);
- F(Flag_X) <= ACC(3);
- F(Flag_N) <= '0';
- end if;
- if I_SCF = '1' then
- -- SCF
- F(Flag_C) <= '1';
- F(Flag_Y) <= ACC(5);
- F(Flag_H) <= '0';
- F(Flag_X) <= ACC(3);
- F(Flag_N) <= '0';
- end if;
- end if;
-
- if TState = 2 and Wait_n = '1' then
- if ISet = "01" and MCycle = "111" then
- IR <= DInst;
- end if;
- if JumpE = '1' then
- PC <= unsigned(signed(PC) + signed(DI_Reg));
- elsif Inc_PC = '1' then
- PC <= PC + 1;
- end if;
- if BTR_r = '1' then
- PC <= PC - 2;
- end if;
- if RstP = '1' then
- TmpAddr <= (others =>'0');
- TmpAddr(5 downto 3) <= IR(5 downto 3);
- end if;
- end if;
- if TState = 3 and MCycle = "110" then
- TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
- end if;
-
- if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
- if IncDec_16(2 downto 0) = "111" then
- if IncDec_16(3) = '1' then
- SP <= SP - 1;
- else
- SP <= SP + 1;
- end if;
- end if;
- end if;
-
- if LDSPHL = '1' then
- SP <= unsigned(RegBusC);
- end if;
- if ExchangeAF = '1' then
- Ap <= ACC;
- ACC <= Ap;
- Fp <= F;
- F <= Fp;
- end if;
- if ExchangeRS = '1' then
- Alternate <= not Alternate;
- end if;
- end if;
-
- if TState = 3 then
- if LDZ = '1' then
- TmpAddr(7 downto 0) <= DI_Reg;
- end if;
- if LDW = '1' then
- TmpAddr(15 downto 8) <= DI_Reg;
- end if;
-
- if Special_LD(2) = '1' then
- case Special_LD(1 downto 0) is
- when "00" =>
- ACC <= I;
- F(Flag_P) <= IntE_FF2;
- when "01" =>
- ACC <= std_logic_vector(R);
- F(Flag_P) <= IntE_FF2;
- when "10" =>
- I <= ACC;
- when others =>
- R <= unsigned(ACC);
- end case;
- end if;
- end if;
-
- if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
- if Mode = 3 then
- F(6) <= F_Out(6);
- F(5) <= F_Out(5);
- F(7) <= F_Out(7);
- if PreserveC_r = '0' then
- F(4) <= F_Out(4);
- end if;
- else
- F(7 downto 1) <= F_Out(7 downto 1);
- if PreserveC_r = '0' then
- F(Flag_C) <= F_Out(0);
- end if;
- end if;
- end if;
- if T_Res = '1' and I_INRC = '1' then
- F(Flag_H) <= '0';
- F(Flag_N) <= '0';
- if DI_Reg(7 downto 0) = "00000000" then
- F(Flag_Z) <= '1';
- else
- F(Flag_Z) <= '0';
- end if;
- F(Flag_S) <= DI_Reg(7);
- F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
- DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
- end if;
-
- if TState = 1 and Auto_Wait_t1 = '0' then
- DO <= BusB;
- if I_RLD = '1' then
- DO(3 downto 0) <= BusA(3 downto 0);
- DO(7 downto 4) <= BusB(3 downto 0);
- end if;
- if I_RRD = '1' then
- DO(3 downto 0) <= BusB(7 downto 4);
- DO(7 downto 4) <= BusA(3 downto 0);
- end if;
- end if;
-
- if T_Res = '1' then
- Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
- Read_To_Reg_r(4) <= Read_To_Reg;
- if Read_To_Acc = '1' then
- Read_To_Reg_r(3 downto 0) <= "0111";
- Read_To_Reg_r(4) <= '1';
- end if;
- end if;
-
- if TState = 1 and I_BT = '1' then
- F(Flag_X) <= ALU_Q(3);
- F(Flag_Y) <= ALU_Q(1);
- F(Flag_H) <= '0';
- F(Flag_N) <= '0';
- end if;
- if I_BC = '1' or I_BT = '1' then
- F(Flag_P) <= IncDecZ;
- end if;
-
- if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or
- (Save_ALU_r = '1' and ALU_OP_r /= "0111") then
- case Read_To_Reg_r is
- when "10111" =>
- ACC <= Save_Mux;
- when "10110" =>
- DO <= Save_Mux;
- when "11000" =>
- SP(7 downto 0) <= unsigned(Save_Mux);
- when "11001" =>
- SP(15 downto 8) <= unsigned(Save_Mux);
- when "11011" =>
- F <= Save_Mux;
- when others =>
- end case;
- end if;
-
- end if;
-
- end if;
-
- end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
- process (CLK_n)
- begin
- if CLK_n'event and CLK_n = '1' then
- if ClkEn = '1' then
- -- Bus A / Write
- RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
- if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
- RegAddrA_r <= XY_State(1) & "11";
- end if;
-
- -- Bus B
- RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
- if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
- RegAddrB_r <= XY_State(1) & "11";
- end if;
-
- -- Address from register
- RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
- -- Jump (HL), LD SP,HL
- if (JumpXY = '1' or LDSPHL = '1') then
- RegAddrC <= Alternate & "10";
- end if;
- if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
- RegAddrC <= XY_State(1) & "11";
- end if;
-
- if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
- IncDecZ <= F_Out(Flag_Z);
- end if;
- if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
- if ID16 = 0 then
- IncDecZ <= '0';
- else
- IncDecZ <= '1';
- end if;
- end if;
-
- RegBusA_r <= RegBusA;
- end if;
- end if;
- end process;
-
- RegAddrA <=
- -- 16 bit increment/decrement
- Alternate & IncDec_16(1 downto 0) when (TState = 2 or
- (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
- XY_State(1) & "11" when (TState = 2 or
- (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
- -- EX HL,DL
- Alternate & "10" when ExchangeDH = '1' and TState = 3 else
- Alternate & "01" when ExchangeDH = '1' and TState = 4 else
- -- Bus A / Write
- RegAddrA_r;
-
- RegAddrB <=
- -- EX HL,DL
- Alternate & "01" when ExchangeDH = '1' and TState = 3 else
- -- Bus B
- RegAddrB_r;
-
- ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
- signed(RegBusA) + 1;
-
- process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
- ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
- begin
- RegWEH <= '0';
- RegWEL <= '0';
- if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or
- (Save_ALU_r = '1' and ALU_OP_r /= "0111") then
- case Read_To_Reg_r is
- when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
- RegWEH <= not Read_To_Reg_r(0);
- RegWEL <= Read_To_Reg_r(0);
- when others =>
- end case;
- end if;
-
- if ExchangeDH = '1' and (TState = 3 or TState = 4) then
- RegWEH <= '1';
- RegWEL <= '1';
- end if;
-
- if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
- case IncDec_16(1 downto 0) is
- when "00" | "01" | "10" =>
- RegWEH <= '1';
- RegWEL <= '1';
- when others =>
- end case;
- end if;
- end process;
-
- process (Save_Mux, RegBusB, RegBusA_r, ID16,
- ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
- begin
- RegDIH <= Save_Mux;
- RegDIL <= Save_Mux;
-
- if ExchangeDH = '1' and TState = 3 then
- RegDIH <= RegBusB(15 downto 8);
- RegDIL <= RegBusB(7 downto 0);
- end if;
- if ExchangeDH = '1' and TState = 4 then
- RegDIH <= RegBusA_r(15 downto 8);
- RegDIL <= RegBusA_r(7 downto 0);
- end if;
-
- if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
- RegDIH <= std_logic_vector(ID16(15 downto 8));
- RegDIL <= std_logic_vector(ID16(7 downto 0));
- end if;
- end process;
-
- Regs : T80_Reg
- port map(
- Clk => CLK_n,
- CEN => ClkEn,
- WEH => RegWEH,
- WEL => RegWEL,
- AddrA => RegAddrA,
- AddrB => RegAddrB,
- AddrC => RegAddrC,
- DIH => RegDIH,
- DIL => RegDIL,
- DOAH => RegBusA(15 downto 8),
- DOAL => RegBusA(7 downto 0),
- DOBH => RegBusB(15 downto 8),
- DOBL => RegBusB(7 downto 0),
- DOCH => RegBusC(15 downto 8),
- DOCL => RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
- process (CLK_n)
- begin
- if CLK_n'event and CLK_n = '1' then
- if ClkEn = '1' then
- case Set_BusB_To is
- when "0111" =>
- BusB <= ACC;
- when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
- if Set_BusB_To(0) = '1' then
- BusB <= RegBusB(7 downto 0);
- else
- BusB <= RegBusB(15 downto 8);
- end if;
- when "0110" =>
- BusB <= DI_Reg;
- when "1000" =>
- BusB <= std_logic_vector(SP(7 downto 0));
- when "1001" =>
- BusB <= std_logic_vector(SP(15 downto 8));
- when "1010" =>
- BusB <= "00000001";
- when "1011" =>
- BusB <= F;
- when "1100" =>
- BusB <= std_logic_vector(PC(7 downto 0));
- when "1101" =>
- BusB <= std_logic_vector(PC(15 downto 8));
- when "1110" =>
- BusB <= "00000000";
- when others =>
- BusB <= "--------";
- end case;
-
- case Set_BusA_To is
- when "0111" =>
- BusA <= ACC;
- when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
- if Set_BusA_To(0) = '1' then
- BusA <= RegBusA(7 downto 0);
- else
- BusA <= RegBusA(15 downto 8);
- end if;
- when "0110" =>
- BusA <= DI_Reg;
- when "1000" =>
- BusA <= std_logic_vector(SP(7 downto 0));
- when "1001" =>
- BusA <= std_logic_vector(SP(15 downto 8));
- when "1010" =>
- BusA <= "00000000";
- when others =>
- BusB <= "--------";
- end case;
- end if;
- end if;
- end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
- process (RESET_n,CLK_n)
- begin
- if RESET_n = '0' then
- RFSH_n <= '1';
- elsif CLK_n'event and CLK_n = '1' then
- if CEN = '1' then
- if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then
- RFSH_n <= '0';
- else
- RFSH_n <= '1';
- end if;
- end if;
- end if;
- end process;
-
- MC <= std_logic_vector(MCycle);
- TS <= std_logic_vector(TState);
- DI_Reg <= DI;
- HALT_n <= not Halt_FF;
- BUSAK_n <= not BusAck;
- IntCycle_n <= not IntCycle;
- IntE <= IntE_FF1;
- IORQ <= IORQ_i;
- Stop <= I_DJNZ;
-
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
- process (RESET_n, CLK_n)
- variable OldNMI_n : std_logic;
- begin
- if RESET_n = '0' then
- BusReq_s <= '0';
- INT_s <= '0';
- NMI_s <= '0';
- OldNMI_n := '0';
- elsif CLK_n'event and CLK_n = '1' then
- if CEN = '1' then
- BusReq_s <= not BUSRQ_n;
- INT_s <= not INT_n;
- if NMICycle = '1' then
- NMI_s <= '0';
- elsif NMI_n = '0' and OldNMI_n = '1' then
- NMI_s <= '1';
- end if;
- OldNMI_n := NMI_n;
- end if;
- end if;
- end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
- process (RESET_n, CLK_n)
- begin
- if RESET_n = '0' then
- MCycle <= "001";
- TState <= "000";
- Pre_XY_F_M <= "000";
- Halt_FF <= '0';
- BusAck <= '0';
- NMICycle <= '0';
- IntCycle <= '0';
- IntE_FF1 <= '0';
- IntE_FF2 <= '0';
- No_BTR <= '0';
- Auto_Wait_t1 <= '0';
- Auto_Wait_t2 <= '0';
- M1_n <= '1';
- elsif CLK_n'event and CLK_n = '1' then
- if CEN = '1' then
- if T_Res = '1' then
- Auto_Wait_t1 <= '0';
- else
- Auto_Wait_t1 <= Auto_Wait or IORQ_i;
- end if;
- Auto_Wait_t2 <= Auto_Wait_t1;
- No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
- (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
- (I_BTR and (not IR(4) or F(Flag_Z)));
- if TState = 2 then
- if SetEI = '1' then
- IntE_FF1 <= '1';
- IntE_FF2 <= '1';
- end if;
- if I_RETN = '1' then
- IntE_FF1 <= IntE_FF2;
- end if;
- end if;
- if TState = 3 then
- if SetDI = '1' then
- IntE_FF1 <= '0';
- IntE_FF2 <= '0';
- end if;
- end if;
- if IntCycle = '1' or NMICycle = '1' then
- Halt_FF <= '0';
- end if;
- if MCycle = "001" and TState = 2 and Wait_n = '1' then
- M1_n <= '1';
- end if;
- if BusReq_s = '1' and BusAck = '1' then
- else
- BusAck <= '0';
- if TState = 2 and Wait_n = '0' then
- elsif T_Res = '1' then
- if Halt = '1' then
- Halt_FF <= '1';
- end if;
- if BusReq_s = '1' then
- BusAck <= '1';
- else
- TState <= "001";
- if NextIs_XY_Fetch = '1' then
- MCycle <= "110";
- Pre_XY_F_M <= MCycle;
- if IR = "00110110" and Mode = 0 then
- Pre_XY_F_M <= "010";
- end if;
- elsif (MCycle = "111") or
- (MCycle = "110" and Mode = 1 and ISet /= "01") then
- MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
- elsif (MCycle = MCycles) or
- No_BTR = '1' or
- (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
- M1_n <= '0';
- MCycle <= "001";
- IntCycle <= '0';
- NMICycle <= '0';
- if NMI_s = '1' and Prefix = "00" then
- NMICycle <= '1';
- IntE_FF1 <= '0';
- elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
- IntCycle <= '1';
- IntE_FF1 <= '0';
- IntE_FF2 <= '0';
- end if;
- else
- MCycle <= std_logic_vector(unsigned(MCycle) + 1);
- end if;
- end if;
- else
- if (Auto_Wait = '1' and Auto_Wait_t2 = '0') nor
- (IOWait = 1 and IORQ_i = '1' and Auto_Wait_t1 = '0') then
- TState <= TState + 1;
- end if;
- end if;
- end if;
- if TState = 0 then
- M1_n <= '0';
- end if;
- end if;
- end if;
- end process;
-
- process (IntCycle, NMICycle, MCycle)
- begin
- Auto_Wait <= '0';
- if IntCycle = '1' or NMICycle = '1' then
- if MCycle = "001" then
- Auto_Wait <= '1';
- end if;
- end if;
- end process;
-
-end;
diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80/T80_ALU.vhd
deleted file mode 100644
index 86fddce7..00000000
--- a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80/T80_ALU.vhd
+++ /dev/null
@@ -1,351 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
--- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
--- 0238 : Fixed zero flag for 16 bit SBC and ADC
---
--- 0240 : Added GB operations
---
--- 0242 : Cleanup
---
--- 0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
- generic(
- Mode : integer := 0;
- Flag_C : integer := 0;
- Flag_N : integer := 1;
- Flag_P : integer := 2;
- Flag_X : integer := 3;
- Flag_H : integer := 4;
- Flag_Y : integer := 5;
- Flag_Z : integer := 6;
- Flag_S : integer := 7
- );
- port(
- Arith16 : in std_logic;
- Z16 : in std_logic;
- ALU_Op : in std_logic_vector(3 downto 0);
- IR : in std_logic_vector(5 downto 0);
- ISet : in std_logic_vector(1 downto 0);
- BusA : in std_logic_vector(7 downto 0);
- BusB : in std_logic_vector(7 downto 0);
- F_In : in std_logic_vector(7 downto 0);
- Q : out std_logic_vector(7 downto 0);
- F_Out : out std_logic_vector(7 downto 0)
- );
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
- procedure AddSub(A : std_logic_vector;
- B : std_logic_vector;
- Sub : std_logic;
- Carry_In : std_logic;
- signal Res : out std_logic_vector;
- signal Carry : out std_logic) is
- variable B_i : unsigned(A'length - 1 downto 0);
- variable Res_i : unsigned(A'length + 1 downto 0);
- begin
- if Sub = '1' then
- B_i := not unsigned(B);
- else
- B_i := unsigned(B);
- end if;
- Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
- Carry <= Res_i(A'length + 1);
- Res <= std_logic_vector(Res_i(A'length downto 1));
- end;
-
- -- AddSub variables (temporary signals)
- signal UseCarry : std_logic;
- signal Carry7_v : std_logic;
- signal Overflow_v : std_logic;
- signal HalfCarry_v : std_logic;
- signal Carry_v : std_logic;
- signal Q_v : std_logic_vector(7 downto 0);
-
- signal BitMask : std_logic_vector(7 downto 0);
-
-begin
-
- with IR(5 downto 3) select BitMask <= "00000001" when "000",
- "00000010" when "001",
- "00000100" when "010",
- "00001000" when "011",
- "00010000" when "100",
- "00100000" when "101",
- "01000000" when "110",
- "10000000" when others;
-
- UseCarry <= not ALU_Op(2) and ALU_Op(0);
- AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
- AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
- AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
- OverFlow_v <= Carry_v xor Carry7_v;
-
- process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
- variable Q_t : std_logic_vector(7 downto 0);
- variable DAA_Q : unsigned(8 downto 0);
- begin
- Q_t := "--------";
- F_Out <= F_In;
- DAA_Q := "---------";
- case ALU_Op is
- when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
- F_Out(Flag_N) <= '0';
- F_Out(Flag_C) <= '0';
- case ALU_OP(2 downto 0) is
- when "000" | "001" => -- ADD, ADC
- Q_t := Q_v;
- F_Out(Flag_C) <= Carry_v;
- F_Out(Flag_H) <= HalfCarry_v;
- F_Out(Flag_P) <= OverFlow_v;
- when "010" | "011" | "111" => -- SUB, SBC, CP
- Q_t := Q_v;
- F_Out(Flag_N) <= '1';
- F_Out(Flag_C) <= not Carry_v;
- F_Out(Flag_H) <= not HalfCarry_v;
- F_Out(Flag_P) <= OverFlow_v;
- when "100" => -- AND
- Q_t(7 downto 0) := BusA and BusB;
- F_Out(Flag_H) <= '1';
- when "101" => -- XOR
- Q_t(7 downto 0) := BusA xor BusB;
- F_Out(Flag_H) <= '0';
- when others => -- OR "110"
- Q_t(7 downto 0) := BusA or BusB;
- F_Out(Flag_H) <= '0';
- end case;
- if ALU_Op(2 downto 0) = "111" then -- CP
- F_Out(Flag_X) <= BusB(3);
- F_Out(Flag_Y) <= BusB(5);
- else
- F_Out(Flag_X) <= Q_t(3);
- F_Out(Flag_Y) <= Q_t(5);
- end if;
- if Q_t(7 downto 0) = "00000000" then
- F_Out(Flag_Z) <= '1';
- if Z16 = '1' then
- F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
- end if;
- else
- F_Out(Flag_Z) <= '0';
- end if;
- F_Out(Flag_S) <= Q_t(7);
- case ALU_Op(2 downto 0) is
- when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
- when others =>
- F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
- Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
- end case;
- if Arith16 = '1' then
- F_Out(Flag_S) <= F_In(Flag_S);
- F_Out(Flag_Z) <= F_In(Flag_Z);
- F_Out(Flag_P) <= F_In(Flag_P);
- end if;
- when "1100" =>
- -- DAA
- F_Out(Flag_H) <= F_In(Flag_H);
- F_Out(Flag_C) <= F_In(Flag_C);
- DAA_Q(7 downto 0) := unsigned(BusA);
- DAA_Q(8) := '0';
- if F_In(Flag_N) = '0' then
- -- After addition
- -- Alow > 9 or H = 1
- if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
- if (DAA_Q(3 downto 0) > 9) then
- F_Out(Flag_H) <= '1';
- else
- F_Out(Flag_H) <= '0';
- end if;
- DAA_Q := DAA_Q + 6;
- end if;
- -- new Ahigh > 9 or C = 1
- if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
- DAA_Q := DAA_Q + 96; -- 0x60
- end if;
- else
- -- After subtraction
- if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
- if DAA_Q(3 downto 0) > 5 then
- F_Out(Flag_H) <= '0';
- end if;
- DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
- end if;
- if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
- DAA_Q := DAA_Q - 352; -- 0x160
- end if;
- end if;
- F_Out(Flag_X) <= DAA_Q(3);
- F_Out(Flag_Y) <= DAA_Q(5);
- F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
- Q_t := std_logic_vector(DAA_Q(7 downto 0));
- if DAA_Q(7 downto 0) = "00000000" then
- F_Out(Flag_Z) <= '1';
- else
- F_Out(Flag_Z) <= '0';
- end if;
- F_Out(Flag_S) <= DAA_Q(7);
- F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
- DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
- when "1101" | "1110" =>
- -- RLD, RRD
- Q_t(7 downto 4) := BusA(7 downto 4);
- if ALU_Op(0) = '1' then
- Q_t(3 downto 0) := BusB(7 downto 4);
- else
- Q_t(3 downto 0) := BusB(3 downto 0);
- end if;
- F_Out(Flag_H) <= '0';
- F_Out(Flag_N) <= '0';
- F_Out(Flag_X) <= Q_t(3);
- F_Out(Flag_Y) <= Q_t(5);
- if Q_t(7 downto 0) = "00000000" then
- F_Out(Flag_Z) <= '1';
- else
- F_Out(Flag_Z) <= '0';
- end if;
- F_Out(Flag_S) <= Q_t(7);
- F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
- Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
- when "1001" =>
- -- BIT
- Q_t(7 downto 0) := BusB and BitMask;
- F_Out(Flag_S) <= Q_t(7);
- if Q_t(7 downto 0) = "00000000" then
- F_Out(Flag_Z) <= '1';
- F_Out(Flag_P) <= '1';
- else
- F_Out(Flag_Z) <= '0';
- F_Out(Flag_P) <= '0';
- end if;
- F_Out(Flag_H) <= '1';
- F_Out(Flag_N) <= '0';
- F_Out(Flag_X) <= '0';
- F_Out(Flag_Y) <= '0';
- if IR(2 downto 0) /= "110" then
- F_Out(Flag_X) <= BusB(3);
- F_Out(Flag_Y) <= BusB(5);
- end if;
- when "1010" =>
- -- SET
- Q_t(7 downto 0) := BusB or BitMask;
- when "1011" =>
- -- RES
- Q_t(7 downto 0) := BusB and not BitMask;
- when "1000" =>
- -- ROT
- case IR(5 downto 3) is
- when "000" => -- RLC
- Q_t(7 downto 1) := BusA(6 downto 0);
- Q_t(0) := BusA(7);
- F_Out(Flag_C) <= BusA(7);
- when "010" => -- RL
- Q_t(7 downto 1) := BusA(6 downto 0);
- Q_t(0) := F_In(Flag_C);
- F_Out(Flag_C) <= BusA(7);
- when "001" => -- RRC
- Q_t(6 downto 0) := BusA(7 downto 1);
- Q_t(7) := BusA(0);
- F_Out(Flag_C) <= BusA(0);
- when "011" => -- RR
- Q_t(6 downto 0) := BusA(7 downto 1);
- Q_t(7) := F_In(Flag_C);
- F_Out(Flag_C) <= BusA(0);
- when "100" => -- SLA
- Q_t(7 downto 1) := BusA(6 downto 0);
- Q_t(0) := '0';
- F_Out(Flag_C) <= BusA(7);
- when "110" => -- SLL (Undocumented) / SWAP
- if Mode = 3 then
- Q_t(7 downto 4) := BusA(3 downto 0);
- Q_t(3 downto 0) := BusA(7 downto 4);
- F_Out(Flag_C) <= '0';
- else
- Q_t(7 downto 1) := BusA(6 downto 0);
- Q_t(0) := '1';
- F_Out(Flag_C) <= BusA(7);
- end if;
- when "101" => -- SRA
- Q_t(6 downto 0) := BusA(7 downto 1);
- Q_t(7) := BusA(7);
- F_Out(Flag_C) <= BusA(0);
- when others => -- SRL
- Q_t(6 downto 0) := BusA(7 downto 1);
- Q_t(7) := '0';
- F_Out(Flag_C) <= BusA(0);
- end case;
- F_Out(Flag_H) <= '0';
- F_Out(Flag_N) <= '0';
- F_Out(Flag_X) <= Q_t(3);
- F_Out(Flag_Y) <= Q_t(5);
- F_Out(Flag_S) <= Q_t(7);
- if Q_t(7 downto 0) = "00000000" then
- F_Out(Flag_Z) <= '1';
- else
- F_Out(Flag_Z) <= '0';
- end if;
- F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
- Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
- if ISet = "00" then
- F_Out(Flag_P) <= F_In(Flag_P);
- F_Out(Flag_S) <= F_In(Flag_S);
- F_Out(Flag_Z) <= F_In(Flag_Z);
- end if;
- when others =>
- null;
- end case;
- Q <= Q_t;
- end process;
-
-end;
diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80/T80_MCode.vhd
deleted file mode 100644
index 4cc30f35..00000000
--- a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80/T80_MCode.vhd
+++ /dev/null
@@ -1,1934 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
--- 0208 : First complete release
---
--- 0211 : Fixed IM 1
---
--- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
--- 0235 : Added IM 2 fix by Mike Johnson
---
--- 0238 : Added NoRead signal
---
--- 0238b: Fixed instruction timing for POP and DJNZ
---
--- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
---
--- 0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_MCode is
- generic(
- Mode : integer := 0;
- Flag_C : integer := 0;
- Flag_N : integer := 1;
- Flag_P : integer := 2;
- Flag_X : integer := 3;
- Flag_H : integer := 4;
- Flag_Y : integer := 5;
- Flag_Z : integer := 6;
- Flag_S : integer := 7
- );
- port(
- IR : in std_logic_vector(7 downto 0);
- ISet : in std_logic_vector(1 downto 0);
- MCycle : in std_logic_vector(2 downto 0);
- F : in std_logic_vector(7 downto 0);
- NMICycle : in std_logic;
- IntCycle : in std_logic;
- MCycles : out std_logic_vector(2 downto 0);
- TStates : out std_logic_vector(2 downto 0);
- Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
- Inc_PC : out std_logic;
- Inc_WZ : out std_logic;
- IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
- Read_To_Reg : out std_logic;
- Read_To_Acc : out std_logic;
- Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
- Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
- ALU_Op : out std_logic_vector(3 downto 0);
- -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
- Save_ALU : out std_logic;
- PreserveC : out std_logic;
- Arith16 : out std_logic;
- Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
- IORQ : out std_logic;
- Jump : out std_logic;
- JumpE : out std_logic;
- JumpXY : out std_logic;
- Call : out std_logic;
- RstP : out std_logic;
- LDZ : out std_logic;
- LDW : out std_logic;
- LDSPHL : out std_logic;
- Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
- ExchangeDH : out std_logic;
- ExchangeRp : out std_logic;
- ExchangeAF : out std_logic;
- ExchangeRS : out std_logic;
- I_DJNZ : out std_logic;
- I_CPL : out std_logic;
- I_CCF : out std_logic;
- I_SCF : out std_logic;
- I_RETN : out std_logic;
- I_BT : out std_logic;
- I_BC : out std_logic;
- I_BTR : out std_logic;
- I_RLD : out std_logic;
- I_RRD : out std_logic;
- I_INRC : out std_logic;
- SetDI : out std_logic;
- SetEI : out std_logic;
- IMode : out std_logic_vector(1 downto 0);
- Halt : out std_logic;
- NoRead : out std_logic;
- Write : out std_logic
- );
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
- constant aNone : std_logic_vector(2 downto 0) := "111";
- constant aBC : std_logic_vector(2 downto 0) := "000";
- constant aDE : std_logic_vector(2 downto 0) := "001";
- constant aXY : std_logic_vector(2 downto 0) := "010";
- constant aIOA : std_logic_vector(2 downto 0) := "100";
- constant aSP : std_logic_vector(2 downto 0) := "101";
- constant aZI : std_logic_vector(2 downto 0) := "110";
--- constant aNone : std_logic_vector(2 downto 0) := "000";
--- constant aXY : std_logic_vector(2 downto 0) := "001";
--- constant aIOA : std_logic_vector(2 downto 0) := "010";
--- constant aSP : std_logic_vector(2 downto 0) := "011";
--- constant aBC : std_logic_vector(2 downto 0) := "100";
--- constant aDE : std_logic_vector(2 downto 0) := "101";
--- constant aZI : std_logic_vector(2 downto 0) := "110";
-
- function is_cc_true(
- F : std_logic_vector(7 downto 0);
- cc : bit_vector(2 downto 0)
- ) return boolean is
- begin
- if Mode = 3 then
- case cc is
- when "000" => return F(7) = '0'; -- NZ
- when "001" => return F(7) = '1'; -- Z
- when "010" => return F(4) = '0'; -- NC
- when "011" => return F(4) = '1'; -- C
- when "100" => return false;
- when "101" => return false;
- when "110" => return false;
- when "111" => return false;
- end case;
- else
- case cc is
- when "000" => return F(6) = '0'; -- NZ
- when "001" => return F(6) = '1'; -- Z
- when "010" => return F(0) = '0'; -- NC
- when "011" => return F(0) = '1'; -- C
- when "100" => return F(2) = '0'; -- PO
- when "101" => return F(2) = '1'; -- PE
- when "110" => return F(7) = '0'; -- P
- when "111" => return F(7) = '1'; -- M
- end case;
- end if;
- end;
-
-begin
-
- process (IR, ISet, MCycle, F, NMICycle, IntCycle)
- variable DDD : std_logic_vector(2 downto 0);
- variable SSS : std_logic_vector(2 downto 0);
- variable DPair : std_logic_vector(1 downto 0);
- variable IRB : bit_vector(7 downto 0);
- begin
- DDD := IR(5 downto 3);
- SSS := IR(2 downto 0);
- DPair := IR(5 downto 4);
- IRB := to_bitvector(IR);
-
- MCycles <= "001";
- if MCycle = "001" then
- TStates <= "100";
- else
- TStates <= "011";
- end if;
- Prefix <= "00";
- Inc_PC <= '0';
- Inc_WZ <= '0';
- IncDec_16 <= "0000";
- Read_To_Acc <= '0';
- Read_To_Reg <= '0';
- Set_BusB_To <= "0000";
- Set_BusA_To <= "0000";
- ALU_Op <= "0" & IR(5 downto 3);
- Save_ALU <= '0';
- PreserveC <= '0';
- Arith16 <= '0';
- IORQ <= '0';
- Set_Addr_To <= aNone;
- Jump <= '0';
- JumpE <= '0';
- JumpXY <= '0';
- Call <= '0';
- RstP <= '0';
- LDZ <= '0';
- LDW <= '0';
- LDSPHL <= '0';
- Special_LD <= "000";
- ExchangeDH <= '0';
- ExchangeRp <= '0';
- ExchangeAF <= '0';
- ExchangeRS <= '0';
- I_DJNZ <= '0';
- I_CPL <= '0';
- I_CCF <= '0';
- I_SCF <= '0';
- I_RETN <= '0';
- I_BT <= '0';
- I_BC <= '0';
- I_BTR <= '0';
- I_RLD <= '0';
- I_RRD <= '0';
- I_INRC <= '0';
- SetDI <= '0';
- SetEI <= '0';
- IMode <= "11";
- Halt <= '0';
- NoRead <= '0';
- Write <= '0';
-
- case ISet is
- when "00" =>
-
-------------------------------------------------------------------------------
---
--- Unprefixed instructions
---
-------------------------------------------------------------------------------
-
- case IRB is
--- 8 BIT LOAD GROUP
- when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
- |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
- |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
- |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
- |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
- |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
- |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
- -- LD r,r'
- Set_BusB_To(2 downto 0) <= SSS;
- ExchangeRp <= '1';
- Set_BusA_To(2 downto 0) <= DDD;
- Read_To_Reg <= '1';
- when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
- -- LD r,n
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- Set_BusA_To(2 downto 0) <= DDD;
- Read_To_Reg <= '1';
- when others => null;
- end case;
- when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
- -- LD r,(HL)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- when 2 =>
- Set_BusA_To(2 downto 0) <= DDD;
- Read_To_Reg <= '1';
- when others => null;
- end case;
- when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
- -- LD (HL),r
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- Set_BusB_To(2 downto 0) <= SSS;
- Set_BusB_To(3) <= '0';
- when 2 =>
- Write <= '1';
- when others => null;
- end case;
- when "00110110" =>
- -- LD (HL),n
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- Set_Addr_To <= aXY;
- Set_BusB_To(2 downto 0) <= SSS;
- Set_BusB_To(3) <= '0';
- when 3 =>
- Write <= '1';
- when others => null;
- end case;
- when "00001010" =>
- -- LD A,(BC)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aBC;
- when 2 =>
- Read_To_Acc <= '1';
- when others => null;
- end case;
- when "00011010" =>
- -- LD A,(DE)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aDE;
- when 2 =>
- Read_To_Acc <= '1';
- when others => null;
- end case;
- when "00111010" =>
- if Mode = 3 then
- -- LDD A,(HL)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- when 2 =>
- Read_To_Acc <= '1';
- IncDec_16 <= "1110";
- when others => null;
- end case;
- else
- -- LD A,(nn)
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- when 4 =>
- Read_To_Acc <= '1';
- when others => null;
- end case;
- end if;
- when "00000010" =>
- -- LD (BC),A
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aBC;
- Set_BusB_To <= "0111";
- when 2 =>
- Write <= '1';
- when others => null;
- end case;
- when "00010010" =>
- -- LD (DE),A
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aDE;
- Set_BusB_To <= "0111";
- when 2 =>
- Write <= '1';
- when others => null;
- end case;
- when "00110010" =>
- if Mode = 3 then
- -- LDD (HL),A
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- Set_BusB_To <= "0111";
- when 2 =>
- Write <= '1';
- IncDec_16 <= "1110";
- when others => null;
- end case;
- else
- -- LD (nn),A
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- Set_BusB_To <= "0111";
- when 4 =>
- Write <= '1';
- when others => null;
- end case;
- end if;
-
--- 16 BIT LOAD GROUP
- when "00000001"|"00010001"|"00100001"|"00110001" =>
- -- LD dd,nn
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- Read_To_Reg <= '1';
- if DPAIR = "11" then
- Set_BusA_To(3 downto 0) <= "1000";
- else
- Set_BusA_To(2 downto 1) <= DPAIR;
- Set_BusA_To(0) <= '1';
- end if;
- when 3 =>
- Inc_PC <= '1';
- Read_To_Reg <= '1';
- if DPAIR = "11" then
- Set_BusA_To(3 downto 0) <= "1001";
- else
- Set_BusA_To(2 downto 1) <= DPAIR;
- Set_BusA_To(0) <= '0';
- end if;
- when others => null;
- end case;
- when "00101010" =>
- if Mode = 3 then
- -- LDI A,(HL)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- when 2 =>
- Read_To_Acc <= '1';
- IncDec_16 <= "0110";
- when others => null;
- end case;
- else
- -- LD HL,(nn)
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- LDW <= '1';
- when 4 =>
- Set_BusA_To(2 downto 0) <= "101"; -- L
- Read_To_Reg <= '1';
- Inc_WZ <= '1';
- Set_Addr_To <= aZI;
- when 5 =>
- Set_BusA_To(2 downto 0) <= "100"; -- H
- Read_To_Reg <= '1';
- when others => null;
- end case;
- end if;
- when "00100010" =>
- if Mode = 3 then
- -- LDI (HL),A
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- Set_BusB_To <= "0111";
- when 2 =>
- Write <= '1';
- IncDec_16 <= "0110";
- when others => null;
- end case;
- else
- -- LD (nn),HL
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- LDW <= '1';
- Set_BusB_To <= "0101"; -- L
- when 4 =>
- Inc_WZ <= '1';
- Set_Addr_To <= aZI;
- Write <= '1';
- Set_BusB_To <= "0100"; -- H
- when 5 =>
- Write <= '1';
- when others => null;
- end case;
- end if;
- when "11111001" =>
- -- LD SP,HL
- TStates <= "110";
- LDSPHL <= '1';
- when "11000101"|"11010101"|"11100101"|"11110101" =>
- -- PUSH qq
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- TStates <= "101";
- IncDec_16 <= "1111";
- Set_Addr_TO <= aSP;
- if DPAIR = "11" then
- Set_BusB_To <= "0111";
- else
- Set_BusB_To(2 downto 1) <= DPAIR;
- Set_BusB_To(0) <= '0';
- Set_BusB_To(3) <= '0';
- end if;
- when 2 =>
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- if DPAIR = "11" then
- Set_BusB_To <= "1011";
- else
- Set_BusB_To(2 downto 1) <= DPAIR;
- Set_BusB_To(0) <= '1';
- Set_BusB_To(3) <= '0';
- end if;
- Write <= '1';
- when 3 =>
- Write <= '1';
- when others => null;
- end case;
- when "11000001"|"11010001"|"11100001"|"11110001" =>
- -- POP qq
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aSP;
- when 2 =>
- IncDec_16 <= "0111";
- Set_Addr_To <= aSP;
- Read_To_Reg <= '1';
- if DPAIR = "11" then
- Set_BusA_To(3 downto 0) <= "1011";
- else
- Set_BusA_To(2 downto 1) <= DPAIR;
- Set_BusA_To(0) <= '1';
- end if;
- when 3 =>
- IncDec_16 <= "0111";
- Read_To_Reg <= '1';
- if DPAIR = "11" then
- Set_BusA_To(3 downto 0) <= "0111";
- else
- Set_BusA_To(2 downto 1) <= DPAIR;
- Set_BusA_To(0) <= '0';
- end if;
- when others => null;
- end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
- when "11101011" =>
- if Mode /= 3 then
- -- EX DE,HL
- ExchangeDH <= '1';
- end if;
- when "00001000" =>
- if Mode = 3 then
- -- LD (nn),SP
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- LDW <= '1';
- Set_BusB_To <= "1000";
- when 4 =>
- Inc_WZ <= '1';
- Set_Addr_To <= aZI;
- Write <= '1';
- Set_BusB_To <= "1001";
- when 5 =>
- Write <= '1';
- when others => null;
- end case;
- elsif Mode < 2 then
- -- EX AF,AF'
- ExchangeAF <= '1';
- end if;
- when "11011001" =>
- if Mode = 3 then
- -- RETI
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_TO <= aSP;
- when 2 =>
- IncDec_16 <= "0111";
- Set_Addr_To <= aSP;
- LDZ <= '1';
- when 3 =>
- Jump <= '1';
- IncDec_16 <= "0111";
- I_RETN <= '1';
- SetEI <= '1';
- when others => null;
- end case;
- elsif Mode < 2 then
- -- EXX
- ExchangeRS <= '1';
- end if;
- when "11100011" =>
- if Mode /= 3 then
- -- EX (SP),HL
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aSP;
- when 2 =>
- Read_To_Reg <= '1';
- Set_BusA_To <= "0101";
- Set_BusB_To <= "0101";
- Set_Addr_To <= aSP;
- when 3 =>
- IncDec_16 <= "0111";
- Set_Addr_To <= aSP;
- TStates <= "100";
- Write <= '1';
- when 4 =>
- Read_To_Reg <= '1';
- Set_BusA_To <= "0100";
- Set_BusB_To <= "0100";
- Set_Addr_To <= aSP;
- when 5 =>
- IncDec_16 <= "1111";
- TStates <= "101";
- Write <= '1';
- when others => null;
- end case;
- end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
- when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
- |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
- |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
- |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
- |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
- |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
- |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
- |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
- -- ADD A,r
- -- ADC A,r
- -- SUB A,r
- -- SBC A,r
- -- AND A,r
- -- OR A,r
- -- XOR A,r
- -- CP A,r
- Set_BusB_To(2 downto 0) <= SSS;
- Set_BusA_To(2 downto 0) <= "111";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
- -- ADD A,(HL)
- -- ADC A,(HL)
- -- SUB A,(HL)
- -- SBC A,(HL)
- -- AND A,(HL)
- -- OR A,(HL)
- -- XOR A,(HL)
- -- CP A,(HL)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- when 2 =>
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_BusB_To(2 downto 0) <= SSS;
- Set_BusA_To(2 downto 0) <= "111";
- when others => null;
- end case;
- when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
- -- ADD A,n
- -- ADC A,n
- -- SUB A,n
- -- SBC A,n
- -- AND A,n
- -- OR A,n
- -- XOR A,n
- -- CP A,n
- MCycles <= "010";
- if MCycle = "010" then
- Inc_PC <= '1';
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_BusB_To(2 downto 0) <= SSS;
- Set_BusA_To(2 downto 0) <= "111";
- end if;
- when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
- -- INC r
- Set_BusB_To <= "1010";
- Set_BusA_To(2 downto 0) <= DDD;
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- PreserveC <= '1';
- ALU_Op <= "0000";
- when "00110100" =>
- -- INC (HL)
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- when 2 =>
- TStates <= "100";
- Set_Addr_To <= aXY;
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- PreserveC <= '1';
- ALU_Op <= "0000";
- Set_BusB_To <= "1010";
- Set_BusA_To(2 downto 0) <= DDD;
- when 3 =>
- Write <= '1';
- when others => null;
- end case;
- when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
- -- DEC r
- Set_BusB_To <= "1010";
- Set_BusA_To(2 downto 0) <= DDD;
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- PreserveC <= '1';
- ALU_Op <= "0010";
- when "00110101" =>
- -- DEC (HL)
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- when 2 =>
- TStates <= "100";
- Set_Addr_To <= aXY;
- ALU_Op <= "0010";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- PreserveC <= '1';
- Set_BusB_To <= "1010";
- Set_BusA_To(2 downto 0) <= DDD;
- when 3 =>
- Write <= '1';
- when others => null;
- end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
- when "00100111" =>
- -- DAA
- Set_BusA_To(2 downto 0) <= "111";
- Read_To_Reg <= '1';
- ALU_Op <= "1100";
- Save_ALU <= '1';
- when "00101111" =>
- -- CPL
- I_CPL <= '1';
- when "00111111" =>
- -- CCF
- I_CCF <= '1';
- when "00110111" =>
- -- SCF
- I_SCF <= '1';
- when "00000000" =>
- if NMICycle = '1' then
- -- NMI
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- TStates <= "101";
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- Set_BusB_To <= "1101";
- when 2 =>
- TStates <= "100";
- Write <= '1';
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- Set_BusB_To <= "1100";
- when 3 =>
- TStates <= "100";
- Write <= '1';
- when others => null;
- end case;
- elsif IntCycle = '1' then
- -- INT (IM 2)
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- LDZ <= '1';
- TStates <= "101";
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- Set_BusB_To <= "1101";
- when 2 =>
- TStates <= "100";
- Write <= '1';
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- Set_BusB_To <= "1100";
- when 3 =>
- TStates <= "100";
- Write <= '1';
- when 4 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 5 =>
- Jump <= '1';
- when others => null;
- end case;
- else
- -- NOP
- end if;
- when "01110110" =>
- -- HALT
- Halt <= '1';
- when "11110011" =>
- -- DI
- SetDI <= '1';
- when "11111011" =>
- -- EI
- SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
- when "00001001"|"00011001"|"00101001"|"00111001" =>
- -- ADD HL,ss
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- NoRead <= '1';
- ALU_Op <= "0000";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_BusA_To(2 downto 0) <= "101";
- case to_integer(unsigned(IR(5 downto 4))) is
- when 0|1|2 =>
- Set_BusB_To(2 downto 1) <= IR(5 downto 4);
- Set_BusB_To(0) <= '1';
- when others =>
- Set_BusB_To <= "1000";
- end case;
- TStates <= "100";
- Arith16 <= '1';
- when 3 =>
- NoRead <= '1';
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- ALU_Op <= "0001";
- Set_BusA_To(2 downto 0) <= "100";
- case to_integer(unsigned(IR(5 downto 4))) is
- when 0|1|2 =>
- Set_BusB_To(2 downto 1) <= IR(5 downto 4);
- when others =>
- Set_BusB_To <= "1001";
- end case;
- Arith16 <= '1';
- when others =>
- end case;
- when "00000011"|"00010011"|"00100011"|"00110011" =>
- -- INC ss
- TStates <= "110";
- IncDec_16(3 downto 2) <= "01";
- IncDec_16(1 downto 0) <= DPair;
- when "00001011"|"00011011"|"00101011"|"00111011" =>
- -- DEC ss
- TStates <= "110";
- IncDec_16(3 downto 2) <= "11";
- IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
- when "00000111"
- -- RLCA
- |"00010111"
- -- RLA
- |"00001111"
- -- RRCA
- |"00011111" =>
- -- RRA
- Set_BusA_To(2 downto 0) <= "111";
- ALU_Op <= "1000";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
-
--- JUMP GROUP
- when "11000011" =>
- -- JP nn
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Inc_PC <= '1';
- Jump <= '1';
- when others => null;
- end case;
- when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
- if IR(5) = '1' and Mode = 3 then
- case IRB(4 downto 3) is
- when "00" =>
- -- LD ($FF00+C),A
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aBC;
- Set_BusB_To <= "0111";
- when 2 =>
- Write <= '1';
- IORQ <= '1';
- when others =>
- end case;
- when "01" =>
- -- LD (nn),A
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- Set_BusB_To <= "0111";
- when 4 =>
- Write <= '1';
- when others => null;
- end case;
- when "10" =>
- -- LD A,($FF00+C)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aBC;
- when 2 =>
- Read_To_Acc <= '1';
- IORQ <= '1';
- when others =>
- end case;
- when "11" =>
- -- LD A,(nn)
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- when 4 =>
- Read_To_Acc <= '1';
- when others => null;
- end case;
- end case;
- else
- -- JP cc,nn
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Inc_PC <= '1';
- if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
- Jump <= '1';
- end if;
- when others => null;
- end case;
- end if;
- when "00011000" =>
- if Mode /= 2 then
- -- JR e
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- when 3 =>
- NoRead <= '1';
- JumpE <= '1';
- TStates <= "101";
- when others => null;
- end case;
- end if;
- when "00111000" =>
- if Mode /= 2 then
- -- JR C,e
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- if F(Flag_C) = '0' then
- MCycles <= "010";
- end if;
- when 3 =>
- NoRead <= '1';
- JumpE <= '1';
- TStates <= "101";
- when others => null;
- end case;
- end if;
- when "00110000" =>
- if Mode /= 2 then
- -- JR NC,e
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- if F(Flag_C) = '1' then
- MCycles <= "010";
- end if;
- when 3 =>
- NoRead <= '1';
- JumpE <= '1';
- TStates <= "101";
- when others => null;
- end case;
- end if;
- when "00101000" =>
- if Mode /= 2 then
- -- JR Z,e
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- if F(Flag_Z) = '0' then
- MCycles <= "010";
- end if;
- when 3 =>
- NoRead <= '1';
- JumpE <= '1';
- TStates <= "101";
- when others => null;
- end case;
- end if;
- when "00100000" =>
- if Mode /= 2 then
- -- JR NZ,e
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- if F(Flag_Z) = '1' then
- MCycles <= "010";
- end if;
- when 3 =>
- NoRead <= '1';
- JumpE <= '1';
- TStates <= "101";
- when others => null;
- end case;
- end if;
- when "11101001" =>
- -- JP (HL)
- JumpXY <= '1';
- when "00010000" =>
- if Mode = 3 then
- I_DJNZ <= '1';
- elsif Mode < 2 then
- -- DJNZ,e
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- TStates <= "101";
- I_DJNZ <= '1';
- Set_BusB_To <= "1010";
- Set_BusA_To(2 downto 0) <= "000";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- ALU_Op <= "0010";
- when 2 =>
- I_DJNZ <= '1';
- Inc_PC <= '1';
- when 3 =>
- NoRead <= '1';
- JumpE <= '1';
- TStates <= "101";
- when others => null;
- end case;
- end if;
-
--- CALL AND RETURN GROUP
- when "11001101" =>
- -- CALL nn
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- IncDec_16 <= "1111";
- Inc_PC <= '1';
- TStates <= "100";
- Set_Addr_To <= aSP;
- LDW <= '1';
- Set_BusB_To <= "1101";
- when 4 =>
- Write <= '1';
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- Set_BusB_To <= "1100";
- when 5 =>
- Write <= '1';
- Call <= '1';
- when others => null;
- end case;
- when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
- if IR(5) = '0' or Mode /= 3 then
- -- CALL cc,nn
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Inc_PC <= '1';
- LDW <= '1';
- if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
- IncDec_16 <= "1111";
- Set_Addr_TO <= aSP;
- TStates <= "100";
- Set_BusB_To <= "1101";
- else
- MCycles <= "011";
- end if;
- when 4 =>
- Write <= '1';
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- Set_BusB_To <= "1100";
- when 5 =>
- Write <= '1';
- Call <= '1';
- when others => null;
- end case;
- end if;
- when "11001001" =>
- -- RET
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- TStates <= "101";
- Set_Addr_TO <= aSP;
- when 2 =>
- IncDec_16 <= "0111";
- Set_Addr_To <= aSP;
- LDZ <= '1';
- when 3 =>
- Jump <= '1';
- IncDec_16 <= "0111";
- when others => null;
- end case;
- when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
- if IR(5) = '1' and Mode = 3 then
- case IRB(4 downto 3) is
- when "00" =>
- -- LD ($FF00+nn),A
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- Set_Addr_To <= aIOA;
- Set_BusB_To <= "0111";
- when 3 =>
- Write <= '1';
- when others => null;
- end case;
- when "01" =>
- -- ADD SP,n
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- ALU_Op <= "0000";
- Inc_PC <= '1';
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_BusA_To <= "1000";
- Set_BusB_To <= "0110";
- when 3 =>
- NoRead <= '1';
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- ALU_Op <= "0001";
- Set_BusA_To <= "1001";
- Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
- when others =>
- end case;
- when "10" =>
- -- LD A,($FF00+nn)
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- Set_Addr_To <= aIOA;
- when 3 =>
- Read_To_Acc <= '1';
- when others => null;
- end case;
- when "11" =>
- -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!!
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- LDW <= '1';
- when 4 =>
- Set_BusA_To(2 downto 0) <= "101"; -- L
- Read_To_Reg <= '1';
- Inc_WZ <= '1';
- Set_Addr_To <= aZI;
- when 5 =>
- Set_BusA_To(2 downto 0) <= "100"; -- H
- Read_To_Reg <= '1';
- when others => null;
- end case;
- end case;
- else
- -- RET cc
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
- Set_Addr_TO <= aSP;
- else
- MCycles <= "001";
- end if;
- TStates <= "101";
- when 2 =>
- IncDec_16 <= "0111";
- Set_Addr_To <= aSP;
- LDZ <= '1';
- when 3 =>
- Jump <= '1';
- IncDec_16 <= "0111";
- when others => null;
- end case;
- end if;
- when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
- -- RST p
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- TStates <= "101";
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- Set_BusB_To <= "1101";
- when 2 =>
- Write <= '1';
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- Set_BusB_To <= "1100";
- when 3 =>
- Write <= '1';
- RstP <= '1';
- when others => null;
- end case;
-
--- INPUT AND OUTPUT GROUP
- when "11011011" =>
- if Mode /= 3 then
- -- IN A,(n)
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- Set_Addr_To <= aIOA;
- when 3 =>
- Read_To_Acc <= '1';
- IORQ <= '1';
- when others => null;
- end case;
- end if;
- when "11010011" =>
- if Mode /= 3 then
- -- OUT (n),A
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- Set_Addr_To <= aIOA;
- Set_BusB_To <= "0111";
- when 3 =>
- Write <= '1';
- IORQ <= '1';
- when others => null;
- end case;
- end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
- when "11001011" =>
- if Mode /= 2 then
- Prefix <= "01";
- end if;
-
- when "11101101" =>
- if Mode < 2 then
- Prefix <= "10";
- end if;
-
- when "11011101"|"11111101" =>
- if Mode < 2 then
- Prefix <= "11";
- end if;
-
- end case;
-
- when "01" =>
-
-------------------------------------------------------------------------------
---
--- CB prefixed instructions
---
-------------------------------------------------------------------------------
-
- Set_BusA_To(2 downto 0) <= IR(2 downto 0);
- Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
- case IRB is
- when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
- |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
- |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
- |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
- |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
- |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
- |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
- |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
- -- RLC r
- -- RL r
- -- RRC r
- -- RR r
- -- SLA r
- -- SRA r
- -- SRL r
- -- SLL r (Undocumented) / SWAP r
- if MCycle = "001" then
- ALU_Op <= "1000";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- end if;
- when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
- -- RLC (HL)
- -- RL (HL)
- -- RRC (HL)
- -- RR (HL)
- -- SRA (HL)
- -- SRL (HL)
- -- SLA (HL)
- -- SLL (HL) (Undocumented) / SWAP (HL)
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 | 7 =>
- Set_Addr_To <= aXY;
- when 2 =>
- ALU_Op <= "1000";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_Addr_To <= aXY;
- TStates <= "100";
- when 3 =>
- Write <= '1';
- when others =>
- end case;
- when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
- |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
- |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
- |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
- |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
- |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
- |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
- |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
- -- BIT b,r
- if MCycle = "001" then
- Set_BusB_To(2 downto 0) <= IR(2 downto 0);
- ALU_Op <= "1001";
- end if;
- when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
- -- BIT b,(HL)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 | 7 =>
- Set_Addr_To <= aXY;
- when 2 =>
- ALU_Op <= "1001";
- TStates <= "100";
- when others =>
- end case;
- when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
- |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
- |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
- |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
- |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
- |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
- |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
- |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
- -- SET b,r
- if MCycle = "001" then
- ALU_Op <= "1010";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- end if;
- when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
- -- SET b,(HL)
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 | 7 =>
- Set_Addr_To <= aXY;
- when 2 =>
- ALU_Op <= "1010";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_Addr_To <= aXY;
- TStates <= "100";
- when 3 =>
- Write <= '1';
- when others =>
- end case;
- when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
- |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
- |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
- |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
- |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
- |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
- |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
- |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
- -- RES b,r
- if MCycle = "001" then
- ALU_Op <= "1011";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- end if;
- when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
- -- RES b,(HL)
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 | 7 =>
- Set_Addr_To <= aXY;
- when 2 =>
- ALU_Op <= "1011";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_Addr_To <= aXY;
- TStates <= "100";
- when 3 =>
- Write <= '1';
- when others =>
- end case;
- end case;
-
- when others =>
-
-------------------------------------------------------------------------------
---
--- ED prefixed instructions
---
-------------------------------------------------------------------------------
-
- case IRB is
- when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
- |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
- |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
- |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
- |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
- |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
- |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
- |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
- |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
- |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
- |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
- |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
- | "10100100"|"10100101"|"10100110"|"10100111"
- | "10101100"|"10101101"|"10101110"|"10101111"
- | "10110100"|"10110101"|"10110110"|"10110111"
- | "10111100"|"10111101"|"10111110"|"10111111"
- |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
- |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
- |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
- |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
- |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
- |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
- |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
- |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
- null; -- NOP, undocumented
- when "01111110"|"01111111" =>
- -- NOP, undocumented
- null;
--- 8 BIT LOAD GROUP
- when "01010111" =>
- -- LD A,I
- Special_LD <= "100";
- TStates <= "101";
- when "01011111" =>
- -- LD A,R
- Special_LD <= "101";
- TStates <= "101";
- when "01000111" =>
- -- LD I,A
- Special_LD <= "110";
- TStates <= "101";
- when "01001111" =>
- -- LD R,A
- Special_LD <= "111";
- TStates <= "101";
--- 16 BIT LOAD GROUP
- when "01001011"|"01011011"|"01101011"|"01111011" =>
- -- LD dd,(nn)
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- LDW <= '1';
- when 4 =>
- Read_To_Reg <= '1';
- if IR(5 downto 4) = "11" then
- Set_BusA_To <= "1000";
- else
- Set_BusA_To(2 downto 1) <= IR(5 downto 4);
- Set_BusA_To(0) <= '1';
- end if;
- Inc_WZ <= '1';
- Set_Addr_To <= aZI;
- when 5 =>
- Read_To_Reg <= '1';
- if IR(5 downto 4) = "11" then
- Set_BusA_To <= "1001";
- else
- Set_BusA_To(2 downto 1) <= IR(5 downto 4);
- Set_BusA_To(0) <= '0';
- end if;
- when others => null;
- end case;
- when "01000011"|"01010011"|"01100011"|"01110011" =>
- -- LD (nn),dd
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- LDW <= '1';
- if IR(5 downto 4) = "11" then
- Set_BusB_To <= "1000";
- else
- Set_BusB_To(2 downto 1) <= IR(5 downto 4);
- Set_BusB_To(0) <= '1';
- Set_BusB_To(3) <= '0';
- end if;
- when 4 =>
- Inc_WZ <= '1';
- Set_Addr_To <= aZI;
- Write <= '1';
- if IR(5 downto 4) = "11" then
- Set_BusB_To <= "1001";
- else
- Set_BusB_To(2 downto 1) <= IR(5 downto 4);
- Set_BusB_To(0) <= '0';
- Set_BusB_To(3) <= '0';
- end if;
- when 5 =>
- Write <= '1';
- when others => null;
- end case;
- when "10100000" | "10101000" | "10110000" | "10111000" =>
- -- LDI, LDD, LDIR, LDDR
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- IncDec_16 <= "1100"; -- BC
- when 2 =>
- Set_BusB_To <= "0110";
- Set_BusA_To(2 downto 0) <= "111";
- ALU_Op <= "0000";
- Set_Addr_To <= aDE;
- if IR(3) = '0' then
- IncDec_16 <= "0110"; -- IX
- else
- IncDec_16 <= "1110";
- end if;
- when 3 =>
- I_BT <= '1';
- TStates <= "101";
- Write <= '1';
- if IR(3) = '0' then
- IncDec_16 <= "0101"; -- DE
- else
- IncDec_16 <= "1101";
- end if;
- when 4 =>
- NoRead <= '1';
- TStates <= "101";
- when others => null;
- end case;
- when "10100001" | "10101001" | "10110001" | "10111001" =>
- -- CPI, CPD, CPIR, CPDR
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- IncDec_16 <= "1100"; -- BC
- when 2 =>
- Set_BusB_To <= "0110";
- Set_BusA_To(2 downto 0) <= "111";
- ALU_Op <= "0111";
- Save_ALU <= '1';
- PreserveC <= '1';
- if IR(3) = '0' then
- IncDec_16 <= "0110";
- else
- IncDec_16 <= "1110";
- end if;
- when 3 =>
- NoRead <= '1';
- I_BC <= '1';
- TStates <= "101";
- when 4 =>
- NoRead <= '1';
- TStates <= "101";
- when others => null;
- end case;
- when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
- -- NEG
- Alu_OP <= "0010";
- Set_BusB_To <= "0111";
- Set_BusA_To <= "1010";
- Read_To_Acc <= '1';
- Save_ALU <= '1';
- when "01000110"|"01001110"|"01100110"|"01101110" =>
- -- IM 0
- IMode <= "00";
- when "01010110"|"01110110" =>
- -- IM 1
- IMode <= "01";
- when "01011110"|"01110111" =>
- -- IM 2
- IMode <= "10";
--- 16 bit arithmetic
- when "01001010"|"01011010"|"01101010"|"01111010" =>
- -- ADC HL,ss
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- NoRead <= '1';
- ALU_Op <= "0001";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_BusA_To(2 downto 0) <= "101";
- case to_integer(unsigned(IR(5 downto 4))) is
- when 0|1|2 =>
- Set_BusB_To(2 downto 1) <= IR(5 downto 4);
- Set_BusB_To(0) <= '1';
- when others =>
- Set_BusB_To <= "1000";
- end case;
- TStates <= "100";
- when 3 =>
- NoRead <= '1';
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- ALU_Op <= "0001";
- Set_BusA_To(2 downto 0) <= "100";
- case to_integer(unsigned(IR(5 downto 4))) is
- when 0|1|2 =>
- Set_BusB_To(2 downto 1) <= IR(5 downto 4);
- Set_BusB_To(0) <= '0';
- when others =>
- Set_BusB_To <= "1001";
- end case;
- when others =>
- end case;
- when "01000010"|"01010010"|"01100010"|"01110010" =>
- -- SBC HL,ss
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- NoRead <= '1';
- ALU_Op <= "0011";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_BusA_To(2 downto 0) <= "101";
- case to_integer(unsigned(IR(5 downto 4))) is
- when 0|1|2 =>
- Set_BusB_To(2 downto 1) <= IR(5 downto 4);
- Set_BusB_To(0) <= '1';
- when others =>
- Set_BusB_To <= "1000";
- end case;
- TStates <= "100";
- when 3 =>
- NoRead <= '1';
- ALU_Op <= "0011";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_BusA_To(2 downto 0) <= "100";
- case to_integer(unsigned(IR(5 downto 4))) is
- when 0|1|2 =>
- Set_BusB_To(2 downto 1) <= IR(5 downto 4);
- when others =>
- Set_BusB_To <= "1001";
- end case;
- when others =>
- end case;
- when "01101111" =>
- -- RLD
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- NoRead <= '1';
- Set_Addr_To <= aXY;
- when 3 =>
- Read_To_Reg <= '1';
- Set_BusB_To(2 downto 0) <= "110";
- Set_BusA_To(2 downto 0) <= "111";
- ALU_Op <= "1101";
- TStates <= "100";
- Set_Addr_To <= aXY;
- Save_ALU <= '1';
- when 4 =>
- I_RLD <= '1';
- Write <= '1';
- when others =>
- end case;
- when "01100111" =>
- -- RRD
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Set_Addr_To <= aXY;
- when 3 =>
- Read_To_Reg <= '1';
- Set_BusB_To(2 downto 0) <= "110";
- Set_BusA_To(2 downto 0) <= "111";
- ALU_Op <= "1110";
- TStates <= "100";
- Set_Addr_To <= aXY;
- Save_ALU <= '1';
- when 4 =>
- I_RRD <= '1';
- Write <= '1';
- when others =>
- end case;
- when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
- -- RETI, RETN
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_TO <= aSP;
- when 2 =>
- IncDec_16 <= "0111";
- Set_Addr_To <= aSP;
- LDZ <= '1';
- when 3 =>
- Jump <= '1';
- IncDec_16 <= "0111";
- I_RETN <= '1';
- when others => null;
- end case;
- when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
- -- IN r,(C)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aBC;
- when 2 =>
- IORQ <= '1';
- if IR(5 downto 3) /= "110" then
- Read_To_Reg <= '1';
- Set_BusA_To(2 downto 0) <= IR(5 downto 3);
- end if;
- I_INRC <= '1';
- when others =>
- end case;
- when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
- -- OUT (C),r
- -- OUT (C),0
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aBC;
- Set_BusB_To(2 downto 0) <= IR(5 downto 3);
- if IR(5 downto 3) = "110" then
- Set_BusB_To(3) <= '1';
- end if;
- when 2 =>
- Write <= '1';
- IORQ <= '1';
- when others =>
- end case;
- when "10100010" | "10101010" | "10110010" | "10111010" =>
- -- INI, IND, INIR, INDR
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aBC;
- Set_BusB_To <= "1010";
- Set_BusA_To <= "0000";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- ALU_Op <= "0010";
- when 2 =>
- IORQ <= '1';
- Set_BusB_To <= "0110";
- Set_Addr_To <= aXY;
- when 3 =>
- if IR(3) = '0' then
- IncDec_16 <= "0010";
- else
- IncDec_16 <= "1010";
- end if;
- TStates <= "100";
- Write <= '1';
- I_BTR <= '1';
- when 4 =>
- NoRead <= '1';
- TStates <= "101";
- when others => null;
- end case;
- when "10100011" | "10101011" | "10110011" | "10111011" =>
- -- OUTI, OUTD, OTIR, OTDR
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- TStates <= "101";
- Set_Addr_To <= aXY;
- Set_BusB_To <= "1010";
- Set_BusA_To <= "0000";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- ALU_Op <= "0010";
- when 2 =>
- Set_BusB_To <= "0110";
- Set_Addr_To <= aBC;
- when 3 =>
- if IR(3) = '0' then
- IncDec_16 <= "0010";
- else
- IncDec_16 <= "1010";
- end if;
- IORQ <= '1';
- Write <= '1';
- I_BTR <= '1';
- when 4 =>
- NoRead <= '1';
- TStates <= "101";
- when others => null;
- end case;
- end case;
-
- end case;
-
- if Mode = 1 then
- if MCycle = "001" then
--- TStates <= "100";
- else
- TStates <= "011";
- end if;
- end if;
-
- if Mode = 3 then
- if MCycle = "001" then
--- TStates <= "100";
- else
- TStates <= "100";
- end if;
- end if;
-
- if Mode < 2 then
- if MCycle = "110" then
- Inc_PC <= '1';
- if Mode = 1 then
- Set_Addr_To <= aXY;
- TStates <= "100";
- Set_BusB_To(2 downto 0) <= SSS;
- Set_BusB_To(3) <= '0';
- end if;
- if IRB = "00110110" or IRB = "11001011" then
- Set_Addr_To <= aNone;
- end if;
- end if;
- if MCycle = "111" then
- if Mode = 0 then
- TStates <= "101";
- end if;
- if ISet /= "01" then
- Set_Addr_To <= aXY;
- end if;
- Set_BusB_To(2 downto 0) <= SSS;
- Set_BusB_To(3) <= '0';
- if IRB = "00110110" or ISet = "01" then
- -- LD (HL),n
- Inc_PC <= '1';
- else
- NoRead <= '1';
- end if;
- end if;
- end if;
-
- end process;
-
-end;
diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80/T80_Pack.vhd
deleted file mode 100644
index ac7d34da..00000000
--- a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80/T80_Pack.vhd
+++ /dev/null
@@ -1,208 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
- component T80
- generic(
- Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
- IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
- Flag_C : integer := 0;
- Flag_N : integer := 1;
- Flag_P : integer := 2;
- Flag_X : integer := 3;
- Flag_H : integer := 4;
- Flag_Y : integer := 5;
- Flag_Z : integer := 6;
- Flag_S : integer := 7
- );
- port(
- RESET_n : in std_logic;
- CLK_n : in std_logic;
- CEN : in std_logic;
- WAIT_n : in std_logic;
- INT_n : in std_logic;
- NMI_n : in std_logic;
- BUSRQ_n : in std_logic;
- M1_n : out std_logic;
- IORQ : out std_logic;
- NoRead : out std_logic;
- Write : out std_logic;
- RFSH_n : out std_logic;
- HALT_n : out std_logic;
- BUSAK_n : out std_logic;
- A : out std_logic_vector(15 downto 0);
- DInst : in std_logic_vector(7 downto 0);
- DI : in std_logic_vector(7 downto 0);
- DO : out std_logic_vector(7 downto 0);
- MC : out std_logic_vector(2 downto 0);
- TS : out std_logic_vector(2 downto 0);
- IntCycle_n : out std_logic;
- IntE : out std_logic;
- Stop : out std_logic
- );
- end component;
-
- component T80_Reg
- port(
- Clk : in std_logic;
- CEN : in std_logic;
- WEH : in std_logic;
- WEL : in std_logic;
- AddrA : in std_logic_vector(2 downto 0);
- AddrB : in std_logic_vector(2 downto 0);
- AddrC : in std_logic_vector(2 downto 0);
- DIH : in std_logic_vector(7 downto 0);
- DIL : in std_logic_vector(7 downto 0);
- DOAH : out std_logic_vector(7 downto 0);
- DOAL : out std_logic_vector(7 downto 0);
- DOBH : out std_logic_vector(7 downto 0);
- DOBL : out std_logic_vector(7 downto 0);
- DOCH : out std_logic_vector(7 downto 0);
- DOCL : out std_logic_vector(7 downto 0)
- );
- end component;
-
- component T80_MCode
- generic(
- Mode : integer := 0;
- Flag_C : integer := 0;
- Flag_N : integer := 1;
- Flag_P : integer := 2;
- Flag_X : integer := 3;
- Flag_H : integer := 4;
- Flag_Y : integer := 5;
- Flag_Z : integer := 6;
- Flag_S : integer := 7
- );
- port(
- IR : in std_logic_vector(7 downto 0);
- ISet : in std_logic_vector(1 downto 0);
- MCycle : in std_logic_vector(2 downto 0);
- F : in std_logic_vector(7 downto 0);
- NMICycle : in std_logic;
- IntCycle : in std_logic;
- MCycles : out std_logic_vector(2 downto 0);
- TStates : out std_logic_vector(2 downto 0);
- Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
- Inc_PC : out std_logic;
- Inc_WZ : out std_logic;
- IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
- Read_To_Reg : out std_logic;
- Read_To_Acc : out std_logic;
- Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
- Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
- ALU_Op : out std_logic_vector(3 downto 0);
- -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
- Save_ALU : out std_logic;
- PreserveC : out std_logic;
- Arith16 : out std_logic;
- Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
- IORQ : out std_logic;
- Jump : out std_logic;
- JumpE : out std_logic;
- JumpXY : out std_logic;
- Call : out std_logic;
- RstP : out std_logic;
- LDZ : out std_logic;
- LDW : out std_logic;
- LDSPHL : out std_logic;
- Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
- ExchangeDH : out std_logic;
- ExchangeRp : out std_logic;
- ExchangeAF : out std_logic;
- ExchangeRS : out std_logic;
- I_DJNZ : out std_logic;
- I_CPL : out std_logic;
- I_CCF : out std_logic;
- I_SCF : out std_logic;
- I_RETN : out std_logic;
- I_BT : out std_logic;
- I_BC : out std_logic;
- I_BTR : out std_logic;
- I_RLD : out std_logic;
- I_RRD : out std_logic;
- I_INRC : out std_logic;
- SetDI : out std_logic;
- SetEI : out std_logic;
- IMode : out std_logic_vector(1 downto 0);
- Halt : out std_logic;
- NoRead : out std_logic;
- Write : out std_logic
- );
- end component;
-
- component T80_ALU
- generic(
- Mode : integer := 0;
- Flag_C : integer := 0;
- Flag_N : integer := 1;
- Flag_P : integer := 2;
- Flag_X : integer := 3;
- Flag_H : integer := 4;
- Flag_Y : integer := 5;
- Flag_Z : integer := 6;
- Flag_S : integer := 7
- );
- port(
- Arith16 : in std_logic;
- Z16 : in std_logic;
- ALU_Op : in std_logic_vector(3 downto 0);
- IR : in std_logic_vector(5 downto 0);
- ISet : in std_logic_vector(1 downto 0);
- BusA : in std_logic_vector(7 downto 0);
- BusB : in std_logic_vector(7 downto 0);
- F_In : in std_logic_vector(7 downto 0);
- Q : out std_logic_vector(7 downto 0);
- F_Out : out std_logic_vector(7 downto 0)
- );
- end component;
-
-end;
diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80/T80_Reg.vhd
deleted file mode 100644
index 828485fb..00000000
--- a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80/T80_Reg.vhd
+++ /dev/null
@@ -1,105 +0,0 @@
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
--- 0242 : Initial release
---
--- 0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
- port(
- Clk : in std_logic;
- CEN : in std_logic;
- WEH : in std_logic;
- WEL : in std_logic;
- AddrA : in std_logic_vector(2 downto 0);
- AddrB : in std_logic_vector(2 downto 0);
- AddrC : in std_logic_vector(2 downto 0);
- DIH : in std_logic_vector(7 downto 0);
- DIL : in std_logic_vector(7 downto 0);
- DOAH : out std_logic_vector(7 downto 0);
- DOAL : out std_logic_vector(7 downto 0);
- DOBH : out std_logic_vector(7 downto 0);
- DOBL : out std_logic_vector(7 downto 0);
- DOCH : out std_logic_vector(7 downto 0);
- DOCL : out std_logic_vector(7 downto 0)
- );
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
- type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
- signal RegsH : Register_Image(0 to 7);
- signal RegsL : Register_Image(0 to 7);
-
-begin
-
- process (Clk)
- begin
- if Clk'event and Clk = '1' then
- if CEN = '1' then
- if WEH = '1' then
- RegsH(to_integer(unsigned(AddrA))) <= DIH;
- end if;
- if WEL = '1' then
- RegsL(to_integer(unsigned(AddrA))) <= DIL;
- end if;
- end if;
- end if;
- end process;
-
- DOAH <= RegsH(to_integer(unsigned(AddrA)));
- DOAL <= RegsL(to_integer(unsigned(AddrA)));
- DOBH <= RegsH(to_integer(unsigned(AddrB)));
- DOBL <= RegsL(to_integer(unsigned(AddrB)));
- DOCH <= RegsH(to_integer(unsigned(AddrC)));
- DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80/T80se.vhd b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80/T80se.vhd
deleted file mode 100644
index ac8886a8..00000000
--- a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/T80/T80se.vhd
+++ /dev/null
@@ -1,184 +0,0 @@
---
--- Z80 compatible microprocessor core, synchronous top level with clock enable
--- Different timing than the original z80
--- Inputs needs to be synchronous and outputs may glitch
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
--- 0235 : First release
---
--- 0236 : Added T2Write generic
---
--- 0237 : Fixed T2Write with wait state
---
--- 0238 : Updated for T80 interface change
---
--- 0240 : Updated for T80 interface change
---
--- 0242 : Updated for T80 interface change
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80se is
- generic(
- Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
- T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
- IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
- );
- port(
- RESET_n : in std_logic;
- CLK_n : in std_logic;
- CLKEN : in std_logic;
- WAIT_n : in std_logic;
- INT_n : in std_logic;
- NMI_n : in std_logic;
- BUSRQ_n : in std_logic;
- M1_n : out std_logic;
- MREQ_n : out std_logic;
- IORQ_n : out std_logic;
- RD_n : out std_logic;
- WR_n : out std_logic;
- RFSH_n : out std_logic;
- HALT_n : out std_logic;
- BUSAK_n : out std_logic;
- A : out std_logic_vector(15 downto 0);
- DI : in std_logic_vector(7 downto 0);
- DO : out std_logic_vector(7 downto 0)
- );
-end T80se;
-
-architecture rtl of T80se is
-
- signal IntCycle_n : std_logic;
- signal NoRead : std_logic;
- signal Write : std_logic;
- signal IORQ : std_logic;
- signal DI_Reg : std_logic_vector(7 downto 0);
- signal MCycle : std_logic_vector(2 downto 0);
- signal TState : std_logic_vector(2 downto 0);
-
-begin
-
- u0 : T80
- generic map(
- Mode => Mode,
- IOWait => IOWait)
- port map(
- CEN => CLKEN,
- M1_n => M1_n,
- IORQ => IORQ,
- NoRead => NoRead,
- Write => Write,
- RFSH_n => RFSH_n,
- HALT_n => HALT_n,
- WAIT_n => Wait_n,
- INT_n => INT_n,
- NMI_n => NMI_n,
- RESET_n => RESET_n,
- BUSRQ_n => BUSRQ_n,
- BUSAK_n => BUSAK_n,
- CLK_n => CLK_n,
- A => A,
- DInst => DI,
- DI => DI_Reg,
- DO => DO,
- MC => MCycle,
- TS => TState,
- IntCycle_n => IntCycle_n);
-
- process (RESET_n, CLK_n)
- begin
- if RESET_n = '0' then
- RD_n <= '1';
- WR_n <= '1';
- IORQ_n <= '1';
- MREQ_n <= '1';
- DI_Reg <= "00000000";
- elsif CLK_n'event and CLK_n = '1' then
- if CLKEN = '1' then
- RD_n <= '1';
- WR_n <= '1';
- IORQ_n <= '1';
- MREQ_n <= '1';
- if MCycle = "001" then
- if TState = "001" or (TState = "010" and Wait_n = '0') then
- RD_n <= not IntCycle_n;
- MREQ_n <= not IntCycle_n;
- IORQ_n <= IntCycle_n;
- end if;
- if TState = "011" then
- MREQ_n <= '0';
- end if;
- else
- if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
- RD_n <= '0';
- IORQ_n <= not IORQ;
- MREQ_n <= IORQ;
- end if;
- if T2Write = 0 then
- if TState = "010" and Write = '1' then
- WR_n <= '0';
- IORQ_n <= not IORQ;
- MREQ_n <= IORQ;
- end if;
- else
- if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
- WR_n <= '0';
- IORQ_n <= not IORQ;
- MREQ_n <= IORQ;
- end if;
- end if;
- end if;
- if TState = "010" and Wait_n = '1' then
- DI_Reg <= DI;
- end if;
- end if;
- end if;
- end process;
-
-end;
diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/TimePilot_MiST.sv b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/TimePilot_MiST.sv
index 0a258feb..fdb79b6a 100644
--- a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/TimePilot_MiST.sv
+++ b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/TimePilot_MiST.sv
@@ -55,24 +55,29 @@ module TimePilot_MiST(
`include "rtl\build_id.v"
localparam CONF_STR = {
-// "SPACEPLT;;",
"TIMEPLT;;",
"O2,Rotate Controls,Off,On;",
"O34,Scanlines,Off,25%,50%,75%;",
- "T6,Reset;",
+ "O5,Blend,Off,On;",
+ "T0,Reset;",
"V,v1.15.",`BUILD_DATE
};
+wire rotate = status[2];
+wire [1:0] scanlines = status[4:3];
+wire blend = status[5];
+
assign LED = 1;
assign AUDIO_R = AUDIO_L;
-assign SDRAM_CLK = clock_48;
+assign SDRAM_CLK = clock_48;
-wire clock_48, clock_12, clock_14, pll_locked;
+wire clock_48, clock_12, clock_6, clock_14, pll_locked;
pll pll(
.inclk0(CLOCK_27),
.c0(clock_48),//24,57600000
.c1(clock_12),//12.28800000
.c2(clock_14),//14.31800000
+ .c3(clock_6),
.locked(pll_locked)
);
@@ -83,10 +88,8 @@ wire [7:0] joystick_0;
wire [7:0] joystick_1;
wire scandoublerD;
wire ypbpr;
-reg [10:0] audio;
-wire hb, vb;
-wire blankn = ~(hb | vb);
-wire hs, vs;
+reg [10:0] audio;
+wire hs, vs;
wire [4:0] r,g,b;
wire [14:0] rom_addr;
wire [15:0] rom_do;
@@ -111,7 +114,7 @@ data_io data_io(
.ioctl_addr ( ioctl_addr ),
.ioctl_dout ( ioctl_dout )
);
-
+
sdram rom(
.*,
.init ( ~pll_locked ),
@@ -127,54 +130,53 @@ sdram rom(
reg reset = 1;
reg rom_loaded = 0;
-always @(posedge clock_48) begin
+always @(posedge clock_12) begin
reg ioctl_downlD;
ioctl_downlD <= ioctl_downl;
if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1;
- reset <= status[0] | buttons[1] | status[6] | ~rom_loaded;
+ reset <= status[0] | buttons[1] | ~rom_loaded;
end
-
time_pilot time_pilot(
+ .clock_6(clock_6),
.clock_12(clock_12),
.clock_14(clock_14),
.reset(reset),
.video_r(r),
.video_g(g),
.video_b(b),
- .video_hblank(hb),
- .video_vblank(vb),
.video_hs(hs),
.video_vs(vs),
.audio_out(audio),
.roms_addr(rom_addr),
.roms_do(rom_do[7:0]),
.roms_rd(rom_rd),
- .dip_switch_1("FF"), // Coinage_B / Coinage_A
- .dip_switch_2("4B"), // Sound(8)/Difficulty(7-5)/Bonus(4)/Cocktail(3)/lives(2-1)
- .start2(btn_two_players),
- .start1(btn_one_player),
- .coin1(btn_coin),
- .fire1(m_fire),
+ .dip_switch_1(8'hFF), // Coinage_B / Coinage_A
+ .dip_switch_2(8'h4B), // Sound(8)/Difficulty(7-5)/Bonus(4)/Cocktail(3)/lives(2-1)
+ .start2(m_two_players),
+ .start1(m_one_player),
+ .coin1(m_coin1),
+ .fire1(m_fireA),
.right1(m_right),
.left1(m_left),
.down1(m_down),
.up1(m_up),
- .fire2(m_fire),
- .right2(m_right),
- .left2(m_left),
- .down2(m_down),
- .up2(m_up) );
-
-mist_video #(.COLOR_DEPTH(5), .SD_HCNT_WIDTH(10)) mist_video(//Wrong Colors have no Idea
+ .fire2(m_fire2A),
+ .right2(m_right2),
+ .left2(m_left2),
+ .down2(m_down2),
+ .up2(m_up2)
+);
+
+mist_video #(.COLOR_DEPTH(5), .SD_HCNT_WIDTH(10)) mist_video(
.clk_sys ( clock_48 ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS3 ( SPI_SS3 ),
.SPI_DI ( SPI_DI ),
- .R ( blankn ? r : 0 ),
- .G ( blankn ? g : 0 ),
- .B ( blankn ? b : 0 ),
+ .R ( r ),
+ .G ( g ),
+ .B ( b ),
.HSync ( hs ),
.VSync ( vs ),
.VGA_R ( VGA_R ),
@@ -182,15 +184,16 @@ mist_video #(.COLOR_DEPTH(5), .SD_HCNT_WIDTH(10)) mist_video(//Wrong Colors have
.VGA_B ( VGA_B ),
.VGA_VS ( VGA_VS ),
.VGA_HS ( VGA_HS ),
-// .ce_divider(0),
- .rotate ( {1'b1,status[2]} ),
+ .ce_divider ( 1'b0 ),
+ .rotate ( { 1'b1, rotate } ),
.scandoubler_disable( scandoublerD ),
- .scanlines ( status[4:3] ),
+ .scanlines ( scanlines ),
+ .blend ( blend ),
.ypbpr ( ypbpr )
);
user_io #(.STRLEN(($size(CONF_STR)>>3)))user_io(
- .clk_sys (clock_48 ),
+ .clk_sys (clock_12 ),
.conf_str (CONF_STR ),
.SPI_CLK (SPI_SCK ),
.SPI_SS_IO (CONF_DATA0 ),
@@ -209,48 +212,31 @@ user_io #(.STRLEN(($size(CONF_STR)>>3)))user_io(
);
dac #(.C_bits(16))dac(
- .clk_i(clock_48),
+ .clk_i(clock_14),
.res_n_i(1),
.dac_i({audio, 5'b00000}),
.dac_o(AUDIO_L)
);
-// Rotated Normal
-wire m_up = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3];
-wire m_down = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2];
-wire m_left = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1];
-wire m_right = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0];
-wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4];
-//wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5];
-
-reg btn_one_player = 0;
-reg btn_two_players = 0;
-reg btn_left = 0;
-reg btn_right = 0;
-reg btn_down = 0;
-reg btn_up = 0;
-reg btn_fire1 = 0;
-//reg btn_fire2 = 0;
-//reg btn_fire3 = 0;
-reg btn_coin = 0;
-
-always @(posedge clock_48) begin
- reg old_state;
- old_state <= key_strobe;
- if(old_state != key_strobe) begin
- case(key_code)
- 'h75: btn_up <= key_pressed; // up
- 'h72: btn_down <= key_pressed; // down
- 'h6B: btn_left <= key_pressed; // left
- 'h74: btn_right <= key_pressed; // right
- 'h76: btn_coin <= key_pressed; // ESC
- 'h05: btn_one_player <= key_pressed; // F1
- 'h06: btn_two_players <= key_pressed; // F2
- //'h14: btn_fire3 <= key_pressed; // ctrl
- //'h11: btn_fire2 <= key_pressed; // alt
- 'h29: btn_fire1 <= key_pressed; // Space
- endcase
- end
-end
+// Arcade inputs
+wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
+wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
+wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
+
+arcade_inputs inputs (
+ .clk ( clock_12 ),
+ .key_strobe ( key_strobe ),
+ .key_pressed ( key_pressed ),
+ .key_code ( key_code ),
+ .joystick_0 ( joystick_0 ),
+ .joystick_1 ( joystick_1 ),
+ .rotate ( rotate ),
+ .orientation ( 2'b11 ),
+ .joyswap ( 1'b0 ),
+ .oneplayer ( 1'b1 ),
+ .controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
+ .player1 ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
+ .player2 ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
+);
endmodule
\ No newline at end of file
diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/pll.v b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/pll.v
index 3c7dc7fe..f0530bf2 100644
--- a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/pll.v
+++ b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/pll.v
@@ -14,7 +14,7 @@
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
-// 13.1.4 Build 182 03/12/2014 SJ Web Edition
+// 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
// ************************************************************
@@ -41,31 +41,35 @@ module pll (
c0,
c1,
c2,
+ c3,
locked);
input inclk0;
output c0;
output c1;
output c2;
+ output c3;
output locked;
wire [4:0] sub_wire0;
- wire sub_wire2;
- wire [0:0] sub_wire7 = 1'h0;
- wire [2:2] sub_wire4 = sub_wire0[2:2];
- wire [0:0] sub_wire3 = sub_wire0[0:0];
+ wire sub_wire3;
+ wire [0:0] sub_wire8 = 1'h0;
+ wire [2:2] sub_wire5 = sub_wire0[2:2];
+ wire [0:0] sub_wire4 = sub_wire0[0:0];
+ wire [3:3] sub_wire2 = sub_wire0[3:3];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
- wire locked = sub_wire2;
- wire c0 = sub_wire3;
- wire c2 = sub_wire4;
- wire sub_wire5 = inclk0;
- wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
+ wire c3 = sub_wire2;
+ wire locked = sub_wire3;
+ wire c0 = sub_wire4;
+ wire c2 = sub_wire5;
+ wire sub_wire6 = inclk0;
+ wire [1:0] sub_wire7 = {sub_wire8, sub_wire6};
altpll altpll_component (
- .inclk (sub_wire6),
+ .inclk (sub_wire7),
.clk (sub_wire0),
- .locked (sub_wire2),
+ .locked (sub_wire3),
.activeclock (),
.areset (1'b0),
.clkbad (),
@@ -102,18 +106,22 @@ module pll (
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
- altpll_component.clk0_divide_by = 26,
+ altpll_component.clk0_divide_by = 115,
altpll_component.clk0_duty_cycle = 50,
- altpll_component.clk0_multiply_by = 47,
+ altpll_component.clk0_multiply_by = 208,
altpll_component.clk0_phase_shift = "0",
- altpll_component.clk1_divide_by = 104,
+ altpll_component.clk1_divide_by = 115,
altpll_component.clk1_duty_cycle = 50,
- altpll_component.clk1_multiply_by = 47,
+ altpll_component.clk1_multiply_by = 52,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 395,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 208,
altpll_component.clk2_phase_shift = "0",
+ altpll_component.clk3_divide_by = 115,
+ altpll_component.clk3_duty_cycle = 50,
+ altpll_component.clk3_multiply_by = 26,
+ altpll_component.clk3_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone III",
@@ -149,7 +157,7 @@ module pll (
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
- altpll_component.port_clk3 = "PORT_UNUSED",
+ altpll_component.port_clk3 = "PORT_USED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
@@ -187,15 +195,18 @@ endmodule
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "26"
-// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "104"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "115"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "115"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "395"
+// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "115"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.807693"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.201923"
+// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.834782"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.208695"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "14.217722"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.104348"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -218,32 +229,40 @@ endmodule
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "47"
-// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "47"
+// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "208"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "52"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "208"
+// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "26"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.78400000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.19600000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "14.22800000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
@@ -268,31 +287,38 @@ endmodule
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "26"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "115"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "47"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "208"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "104"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "115"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "47"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "52"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "395"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "208"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "115"
+// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "26"
+// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
@@ -327,7 +353,7 @@ endmodule
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
@@ -346,6 +372,7 @@ endmodule
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
@@ -353,6 +380,7 @@ endmodule
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/sdram.sv b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/sdram.sv
new file mode 100644
index 00000000..53a14e5e
--- /dev/null
+++ b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/sdram.sv
@@ -0,0 +1,254 @@
+//
+// sdram.v
+//
+// Static RAM controller implementation using SDRAM MT48LC16M16A2
+//
+// Copyright (c) 2015,2016 Sorgelig
+//
+// Some parts of SDRAM code used from project:
+// http://hamsterworks.co.nz/mediawiki/index.php/Simple_SDRAM_Controller
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see .
+//
+// ------------------------------------------
+//
+// v2.1 - Add universal 8/16 bit mode.
+//
+
+module sdram
+(
+ input init, // reset to initialize RAM
+ input clk, // clock ~100MHz
+ //
+ // SDRAM_* - signals to the MT48LC16M16 chip
+ inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus
+ output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus
+ output reg SDRAM_DQML, // two byte masks
+ output reg SDRAM_DQMH, //
+ output reg [1:0] SDRAM_BA, // two banks
+ output SDRAM_nCS, // a single chip select
+ output SDRAM_nWE, // write enable
+ output SDRAM_nRAS, // row address select
+ output SDRAM_nCAS, // columns address select
+ output SDRAM_CKE, // clock enable
+ //
+ input [1:0] wtbt, // 16bit mode: bit1 - write high byte, bit0 - write low byte,
+ // 8bit mode: 2'b00 - use addr[0] to decide which byte to write
+ // Ignored while reading.
+ //
+ input [24:0] addr, // 25 bit address for 8bit mode. addr[0] = 0 for 16bit mode for correct operations.
+ output [15:0] dout, // data output to cpu
+ input [15:0] din, // data input from cpu
+ input we, // cpu requests write
+ input rd, // cpu requests read
+ output reg ready // dout is valid. Ready to accept new read/write.
+);
+
+assign SDRAM_nCS = command[3];
+assign SDRAM_nRAS = command[2];
+assign SDRAM_nCAS = command[1];
+assign SDRAM_nWE = command[0];
+assign SDRAM_CKE = cke;
+
+// no burst configured
+localparam BURST_LENGTH = 3'b000; // 000=1, 001=2, 010=4, 011=8
+localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
+localparam CAS_LATENCY = 3'd2; // 2 for < 100MHz, 3 for >100MHz
+localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed
+localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write
+localparam MODE = {3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
+
+localparam sdram_startup_cycles= 14'd12100;// 100us, plus a little more, @ 100MHz
+localparam cycles_per_refresh = 14'd186; // (64000*24)/8192-1 Calc'd as (64ms @ 24MHz)/8192 rose
+localparam startup_refresh_max = 14'b11111111111111;
+
+// SDRAM commands
+localparam CMD_INHIBIT = 4'b1111;
+localparam CMD_NOP = 4'b0111;
+localparam CMD_ACTIVE = 4'b0011;
+localparam CMD_READ = 4'b0101;
+localparam CMD_WRITE = 4'b0100;
+localparam CMD_BURST_TERMINATE = 4'b0110;
+localparam CMD_PRECHARGE = 4'b0010;
+localparam CMD_AUTO_REFRESH = 4'b0001;
+localparam CMD_LOAD_MODE = 4'b0000;
+
+reg [13:0] refresh_count = startup_refresh_max - sdram_startup_cycles;
+reg [3:0] command = CMD_INHIBIT;
+reg cke = 0;
+reg [24:0] save_addr;
+reg [15:0] data;
+
+assign dout = save_addr[0] ? {data[7:0], data[15:8]} : {data[15:8], data[7:0]};
+typedef enum
+{
+ STATE_STARTUP,
+ STATE_OPEN_1,
+ STATE_WRITE,
+ STATE_READ,
+ STATE_IDLE, STATE_IDLE_1, STATE_IDLE_2, STATE_IDLE_3,
+ STATE_IDLE_4, STATE_IDLE_5, STATE_IDLE_6, STATE_IDLE_7
+} state_t;
+
+state_t state = STATE_STARTUP;
+
+always @(posedge clk) begin
+ reg old_we, old_rd;
+ reg [CAS_LATENCY:0] data_ready_delay;
+
+ reg [15:0] new_data;
+ reg [1:0] new_wtbt;
+ reg new_we;
+ reg new_rd;
+ reg save_we = 1;
+
+
+ command <= CMD_NOP;
+ refresh_count <= refresh_count+1'b1;
+
+ data_ready_delay <= {1'b0, data_ready_delay[CAS_LATENCY:1]};
+
+ if(data_ready_delay[0]) data <= SDRAM_DQ;
+
+ case(state)
+ STATE_STARTUP: begin
+ //------------------------------------------------------------------------
+ //-- This is the initial startup state, where we wait for at least 100us
+ //-- before starting the start sequence
+ //--
+ //-- The initialisation is sequence is
+ //-- * de-assert SDRAM_CKE
+ //-- * 100us wait,
+ //-- * assert SDRAM_CKE
+ //-- * wait at least one cycle,
+ //-- * PRECHARGE
+ //-- * wait 2 cycles
+ //-- * REFRESH,
+ //-- * tREF wait
+ //-- * REFRESH,
+ //-- * tREF wait
+ //-- * LOAD_MODE_REG
+ //-- * 2 cycles wait
+ //------------------------------------------------------------------------
+ cke <= 1;
+ SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
+ SDRAM_DQML <= 1;
+ SDRAM_DQMH <= 1;
+ SDRAM_A <= 0;
+ SDRAM_BA <= 0;
+
+ // All the commands during the startup are NOPS, except these
+ if(refresh_count == startup_refresh_max-31) begin
+ // ensure all rows are closed
+ command <= CMD_PRECHARGE;
+ SDRAM_A[10] <= 1; // all banks
+ SDRAM_BA <= 2'b00;
+ end else if (refresh_count == startup_refresh_max-23) begin
+ // these refreshes need to be at least tREF (66ns) apart
+ command <= CMD_AUTO_REFRESH;
+ end else if (refresh_count == startup_refresh_max-15)
+ command <= CMD_AUTO_REFRESH;
+ else if (refresh_count == startup_refresh_max-7) begin
+ // Now load the mode register
+ command <= CMD_LOAD_MODE;
+ SDRAM_A <= MODE;
+ end
+
+ //------------------------------------------------------
+ //-- if startup is complete then go into idle mode,
+ //-- get prepared to accept a new command, and schedule
+ //-- the first refresh cycle
+ //------------------------------------------------------
+ if(!refresh_count) begin
+ state <= STATE_IDLE;
+ ready <= 1;
+ refresh_count <= 0;
+ end
+ end
+
+ STATE_IDLE_7: state <= STATE_IDLE_6;
+ STATE_IDLE_6: state <= STATE_IDLE_5;
+ STATE_IDLE_5: state <= STATE_IDLE_4;
+ STATE_IDLE_4: state <= STATE_IDLE_3;
+ STATE_IDLE_3: state <= STATE_IDLE_2;
+ STATE_IDLE_2: state <= STATE_IDLE_1;
+ STATE_IDLE_1: begin
+ SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
+ state <= STATE_IDLE;
+ // mask possible refresh to reduce colliding.
+ if(refresh_count > cycles_per_refresh) begin
+ //------------------------------------------------------------------------
+ //-- Start the refresh cycle.
+ //-- This tasks tRFC (66ns), so 2 idle cycles are needed @ 24MHz
+ //------------------------------------------------------------------------
+ state <= STATE_IDLE_2;
+ command <= CMD_AUTO_REFRESH;
+ refresh_count <= refresh_count - cycles_per_refresh + 1'd1;
+ end
+ end
+
+ STATE_IDLE: begin
+ // Priority is to issue a refresh if one is outstanding
+ if(refresh_count > (cycles_per_refresh<<1)) state <= STATE_IDLE_1;
+ else if(new_rd | new_we) begin
+ new_we <= 0;
+ new_rd <= 0;
+ save_addr<= addr;
+ save_we <= new_we;
+ state <= STATE_OPEN_1;
+ command <= CMD_ACTIVE;
+ SDRAM_A <= addr[13:1];
+ SDRAM_BA <= addr[24:23];
+ end
+ end
+
+ // ACTIVE-to-READ or WRITE delay >20ns (1 cycle @ 24 MHz)(-75)
+ STATE_OPEN_1: begin
+ SDRAM_A <= {4'b0010, save_addr[22:14]};
+ SDRAM_DQML <= save_we & (new_wtbt ? ~new_wtbt[0] : save_addr[0]);
+ SDRAM_DQMH <= save_we & (new_wtbt ? ~new_wtbt[1] : ~save_addr[0]);
+ state <= save_we ? STATE_WRITE : STATE_READ;
+ end
+
+ STATE_READ: begin
+ state <= STATE_IDLE_5;
+ command <= CMD_READ;
+ SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
+
+ // Schedule reading the data values off the bus
+ data_ready_delay[CAS_LATENCY] <= 1;
+ end
+
+ STATE_WRITE: begin
+ state <= STATE_IDLE_5;
+ command <= CMD_WRITE;
+ SDRAM_DQ <= new_wtbt ? new_data : {new_data[7:0], new_data[7:0]};
+ ready <= 1;
+ end
+ endcase
+
+ if(init) begin
+ state <= STATE_STARTUP;
+ refresh_count <= startup_refresh_max - sdram_startup_cycles;
+ end
+
+ old_we <= we;
+ old_rd <= rd;
+ if(we & ~old_we) {ready, new_we, new_data, new_wtbt} <= {1'b0, 1'b1, din, wtbt};
+ else
+ if((rd & ~old_rd) || (rd & old_rd & (save_addr != addr))) {ready, new_rd} <= {1'b0, 1'b1};
+
+end
+
+endmodule
diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/time_pilot.vhd b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/time_pilot.vhd
index b8da3949..3574d728 100644
--- a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/time_pilot.vhd
+++ b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/time_pilot.vhd
@@ -81,6 +81,7 @@ use ieee.numeric_std.all;
entity time_pilot is
port(
+ clock_6 : in std_logic;
clock_12 : in std_logic;
clock_14 : in std_logic;
reset : in std_logic;
@@ -123,7 +124,6 @@ architecture struct of time_pilot is
signal reset_n: std_logic;
signal clock_12n : std_logic;
- signal clock_6 : std_logic := '0';
signal clock_6n : std_logic;
signal clock_div : std_logic_vector(1 downto 0) := "00";
@@ -229,19 +229,6 @@ begin
end if;
end process;
--- make 6MHz clock from 12MHz
-process (clock_12)
-begin
- if reset='1' then
- clock_6 <= '0';
- else
- if rising_edge(clock_12) then
- clock_6 <= not clock_6;
- end if;
- end if;
-end process;
-
-
--------------------------
-- Video/sprite scanner --
--------------------------
diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/time_pilot_sound_board.vhd b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/time_pilot_sound_board.vhd
index 44bbb38f..626d06d9 100644
--- a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/time_pilot_sound_board.vhd
+++ b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/rtl/time_pilot_sound_board.vhd
@@ -48,8 +48,8 @@ architecture struct of time_pilot_sound_board is
signal clock_div1 : std_logic_vector(11 downto 0) := (others => '0');
signal biquinary_div : std_logic_vector(3 downto 0) := (others => '0');
- signal cpu_clock : std_logic;
- signal ayx_clock : std_logic;
+ signal cpu_clock_en : std_logic;
+ signal ayx_clock_en : std_logic;
signal cpu_addr : std_logic_vector(15 downto 0);
signal cpu_di : std_logic_vector( 7 downto 0);
@@ -241,8 +241,8 @@ begin
end process;
-- make clocks for cpu and sound generators
-cpu_clock <= clock_div1(2);
-ayx_clock <= not clock_div1(2);
+cpu_clock_en <= '1' when clock_div1(2 downto 0) = "011" else '0';
+ayx_clock_en <= '1' when clock_div1(2 downto 0) = "111" else '0';
-- mux rom/ram/devices data ouput to cpu data input w.r.t cpu address
cpu_di <= cpu_rom_do when cpu_addr(15 downto 12) = "0000" else -- 0000-0FFF
@@ -277,9 +277,9 @@ ay1_port_b_di <= biquinary_div(0)&biquinary_div(3)&biquinary_div(2)&clock_div1(1
clr_irq_n <= reset_n and (cpu_m1_n or cpu_iorq_n);
-- regsiter filters commands (11 bits data are cpu address)
-process (cpu_clock)
+process (clock_14, cpu_clock_en)
begin
- if rising_edge(cpu_clock) then
+ if rising_edge(clock_14) and cpu_clock_en = '1' then
if filter_cmd_we = '1' then filter_cmd <= cpu_addr(11 downto 0); end if;
end if;
end process;
@@ -303,9 +303,9 @@ begin
end process;
-- demux AY chips output
-process (ayx_clock)
+process (clock_14, ayx_clock_en)
begin
- if rising_edge(ayx_clock) then
+ if rising_edge(clock_14) and ayx_clock_en = '1' then
if ay1_audio_chan = "00" then ay1_chan_a <= ay1_audio_muxed; end if;
if ay1_audio_chan = "01" then ay1_chan_b <= ay1_audio_muxed; end if;
if ay1_audio_chan = "10" then ay1_chan_c <= ay1_audio_muxed; end if;
@@ -320,8 +320,8 @@ cpu : entity work.T80se
generic map(Mode => 0, T2Write => 1, IOWait => 1)
port map(
RESET_n => reset_n,
- CLK_n => cpu_clock,
- CLKEN => '1',
+ CLK_n => clock_14,
+ CLKEN => cpu_clock_en,
WAIT_n => '1',
INT_n => cpu_irq_n,
NMI_n => '1',
@@ -385,9 +385,9 @@ port map(
O_IOB => open, -- out std_logic_vector(7 downto 0);
O_IOB_OE_L => open, -- out std_logic;
- ENA => '1', --cpu_ena, -- in std_logic; -- clock enable for higher speed operation
+ ENA => ayx_clock_en, -- in std_logic; -- clock enable for higher speed operation
RESET_L => reset_n, -- in std_logic;
- CLK => ayx_clock -- in std_logic -- note 6 Mhz
+ CLK => clock_14 -- in std_logic
);
-- AY-3-8910 #2
@@ -417,9 +417,9 @@ port map(
O_IOB => open, -- out std_logic_vector(7 downto 0);
O_IOB_OE_L => open, -- out std_logic;
- ENA => '1', --cpu_ena, -- in std_logic; -- clock enable for higher speed operation
+ ENA => ayx_clock_en, -- in std_logic; -- clock enable for higher speed operation
RESET_L => reset_n, -- in std_logic;
- CLK => ayx_clock -- in std_logic -- note 6 Mhz
+ CLK => clock_14 -- in std_logic
);
diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/time_pilot_mist.qsf b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/time_pilot_mist.qsf
index 652c73ba..fe7b2113 100644
--- a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/time_pilot_mist.qsf
+++ b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/time_pilot_mist.qsf
@@ -41,31 +41,10 @@
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:45:13 JUNE 17,2016"
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/TimePilot_MiST.sv
-set_global_assignment -name VHDL_FILE rtl/time_pilot.vhd
-set_global_assignment -name VHDL_FILE rtl/gen_video.vhd
-set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
-set_global_assignment -name VHDL_FILE rtl/time_pilot_sound_board.vhd
-set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd
-set_global_assignment -name VHDL_FILE rtl/rom/time_pilot_sprite_grphx.vhd
-set_global_assignment -name VHDL_FILE rtl/rom/time_pilot_sprite_color_lut.vhd
-set_global_assignment -name VHDL_FILE rtl/rom/time_pilot_sound_prog.vhd
-set_global_assignment -name VHDL_FILE rtl/rom/time_pilot_palette_green_red.vhd
-set_global_assignment -name VHDL_FILE rtl/rom/time_pilot_palette_blue_green.vhd
-set_global_assignment -name VHDL_FILE rtl/rom/time_pilot_char_grphx.vhd
-set_global_assignment -name VHDL_FILE rtl/rom/time_pilot_char_color_lut.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80se.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
-set_global_assignment -name VERILOG_FILE rtl/pll.v
-set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
# Pin & Location Assignments
# ==========================
@@ -138,6 +117,40 @@ set_location_assignment PIN_66 -to SDRAM_nWE
set_location_assignment PIN_59 -to SDRAM_nCS
set_location_assignment PIN_33 -to SDRAM_CKE
set_location_assignment PIN_43 -to SDRAM_CLK
+set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
+
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
+
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
# Classic Timing Assignments
# ==========================
@@ -171,7 +184,7 @@ set_global_assignment -name ENABLE_NCE_PIN OFF
# EDA Netlist Writer Assignments
# ==============================
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_SIMULATION_TOOL ""
# Assembler Assignments
# =====================
@@ -203,13 +216,30 @@ set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
# Incremental Compilation Assignments
# ===================================
- set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
- set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
- set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(TimePilot_MiST)
# --------------------------
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/TimePilot_MiST.sv
+set_global_assignment -name VHDL_FILE rtl/time_pilot.vhd
+set_global_assignment -name VHDL_FILE rtl/gen_video.vhd
+set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
+set_global_assignment -name VHDL_FILE rtl/time_pilot_sound_board.vhd
+set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/time_pilot_sprite_grphx.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/time_pilot_sprite_color_lut.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/time_pilot_sound_prog.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/time_pilot_palette_green_red.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/time_pilot_palette_blue_green.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/time_pilot_char_grphx.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/time_pilot_char_color_lut.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
+set_global_assignment -name VERILOG_FILE rtl/pll.v
+set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
+set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/time_pilot_mist.sdc b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/time_pilot_mist.sdc
new file mode 100644
index 00000000..ca3faf31
--- /dev/null
+++ b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/time_pilot_mist.sdc
@@ -0,0 +1,138 @@
+## Generated SDC file "vectrex_MiST.out.sdc"
+
+## Copyright (C) 1991-2013 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions
+## and other software and tools, and its AMPP partner logic
+## functions, and any output files from any of the foregoing
+## (including device programming or simulation files), and any
+## associated documentation or information are expressly subject
+## to the terms and conditions of the Altera Program License
+## Subscription Agreement, Altera MegaCore Function License
+## Agreement, or other applicable license agreement, including,
+## without limitation, that your use is for the sole purpose of
+## programming logic devices manufactured by Altera and sold by
+## Altera or its authorized distributors. Please refer to the
+## applicable agreement for further details.
+
+
+## VENDOR "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+## DATE "Sun Jun 24 12:53:00 2018"
+
+##
+## DEVICE "EP3C25E144C8"
+##
+
+# Clock constraints
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
+
+set sys_clk "pll|altpll_component|auto_generated|pll1|clk[1]"
+set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
+set snd_clk "pll|altpll_component|auto_generated|pll1|clk[2]"
+set vid_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}]
+set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}]
+set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}]
+set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}]
+set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}]
+set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}]
+
+set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]]
+set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]]
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
+set_output_delay -add_delay -clock_fall -clock [get_clocks $snd_clk] 1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay -clock_fall -clock [get_clocks $snd_clk] 1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {LED}]
+set_output_delay -add_delay -clock_fall -clock [get_clocks $vid_clk] 1.000 [get_ports {VGA_*}]
+
+set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
+# audio-main cpu clocks are asynchronous
+set_clock_groups -asynchronous -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[3]}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}]
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+set_multicycle_path -to {VGA_*[*]} -setup 2
+set_multicycle_path -to {VGA_*[*]} -hold 1
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
diff --git a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/time_pilot_mist.srf b/Arcade_MiST/Konami Classic/Time_Pilot_MiST/time_pilot_mist.srf
deleted file mode 100644
index e413eda9..00000000
--- a/Arcade_MiST/Konami Classic/Time_Pilot_MiST/time_pilot_mist.srf
+++ /dev/null
@@ -1 +0,0 @@
-{ "" "" "" "*" { } { } 0 10492 "" 0 0 "Quartus II" 0 -1 0 ""}